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JimLewis/OSVVM | demo/AlertLog_Demo_Hierarchy.vhd | 2 | 8,410 | --
-- File Name: AlertLog_Demo_Hierarchy.vhd
-- Design Unit Name: AlertLog_Demo_Hierarchy
-- Revision: STANDARD VERSION, 2015.01
--
-- Copyright (c) 2015 by SynthWorks Design Inc. All rights reserved.
--
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
-- Description:
-- Demo showing use of hierarchy in AlertLogPkg
-- Both TB and CPU use sublevels of hierarchy
-- UART does not use sublevels of hierarchy
-- Usage of block statements emulates a separate entity/architecture
--
-- Developed for:
-- SynthWorks Design Inc.
-- Training Courses
-- 11898 SW 128th Ave.
-- Tigard, Or 97223
-- http://www.SynthWorks.com
--
--
-- Revision History:
-- Date Version Description
-- 01/2015 2015.01 Refining tests
-- 01/2020 2020.01 Updated Licenses to Apache
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2015 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library IEEE ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use std.textio.all ;
use ieee.std_logic_textio.all ;
library osvvm ;
use osvvm.OsvvmGlobalPkg.all ;
use osvvm.TranscriptPkg.all ;
use osvvm.AlertLogPkg.all ;
entity AlertLog_Demo_Hierarchy is
end AlertLog_Demo_Hierarchy ;
architecture hierarchy of AlertLog_Demo_Hierarchy is
signal Clk : std_logic := '0';
begin
Clk <= not Clk after 10 ns ;
-- /////////////////////////////////////////////////////////////
-- \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
Testbench_1 : block
constant TB_AlertLogID : AlertLogIDType := GetAlertLogID("Testbench_1") ;
begin
TbP0 : process
variable ClkNum : integer := 0 ;
begin
wait until Clk = '1' ;
ClkNum := ClkNum + 1 ;
print(LF & "Clock Number " & to_string(ClkNum)) ;
end process TbP0 ;
------------------------------------------------------------
TbP1 : process
constant TB_P1_ID : AlertLogIDType := GetAlertLogID("TB P1", TB_AlertLogID) ;
variable TempID : AlertLogIDType ;
begin
-- Uncomment this line to use a log file rather than OUTPUT
-- TranscriptOpen("./Demo_Hierarchy.txt") ;
-- Uncomment this line and the simulation will stop after 15 errors
-- SetAlertStopCount(ERROR, 15) ;
SetAlertLogName("AlertLog_Demo_Hierarchy") ;
wait for 0 ns ; -- make sure all processes have elaborated
SetLogEnable(DEBUG, TRUE) ; -- Enable DEBUG Messages for all levels of the hierarchy
TempID := GetAlertLogID("CPU_1") ; -- Get The CPU AlertLogID
SetLogEnable(TempID, DEBUG, FALSE) ; -- turn off DEBUG messages in CPU
SetLogEnable(TempID, INFO, TRUE) ; -- turn on INFO messages in CPU
-- Uncomment this line to justify alert and log reports
-- SetAlertLogJustify ;
for i in 1 to 5 loop
wait until Clk = '1' ;
if i = 4 then SetLogEnable(DEBUG, FALSE) ; end if ; -- DEBUG Mode OFF
wait for 1 ns ;
Alert(TB_P1_ID, "Tb.P1.E alert " & to_string(i) & " of 5") ; -- ERROR by default
Log (TB_P1_ID, "Tb.P1.D log " & to_string(i) & " of 5", DEBUG) ;
end loop ;
wait until Clk = '1' ;
wait until Clk = '1' ;
wait for 1 ns ;
-- Report Alerts without expected errors
ReportAlerts ;
print("") ;
-- Report Alerts with expected errors expressed as a negative ExternalErrors value
ReportAlerts(Name => "AlertLog_Demo_Hierarchy with expected errors", ExternalErrors => -(FAILURE => 0, ERROR => 20, WARNING => 15)) ;
TranscriptClose ;
print(LF & "The following is brought to you by std.env.stop:") ;
std.env.stop ;
wait ;
end process TbP1 ;
------------------------------------------------------------
TbP2 : process
constant TB_P2_ID : AlertLogIDType := GetAlertLogID("TB P2", TB_AlertLogID) ;
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 2 ns ;
Alert(TB_P2_ID, "Tb.P2.E alert " & to_string(i) & " of 5", ERROR) ;
-- example of a log that is not enabled, so it does not print
Log (TB_P2_ID, "Tb.P2.I log " & to_string(i) & " of 5", INFO) ;
end loop ;
wait until Clk = '1' ;
wait for 2 ns ;
-- Uncomment this line to and the simulation will stop here
-- Alert(TB_P2_ID, "Tb.P2.F Message 1 of 1", FAILURE) ;
wait ;
end process TbP2 ;
------------------------------------------------------------
TbP3 : process
constant TB_P3_ID : AlertLogIDType := GetAlertLogID("TB P3", TB_AlertLogID) ;
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 3 ns ;
Alert(TB_P3_ID, "Tb.P3.W alert " & to_string(i) & " of 5", WARNING) ;
end loop ;
wait ;
end process TbP3 ;
end block Testbench_1 ;
-- /////////////////////////////////////////////////////////////
-- \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
Cpu_1 : block
constant CPU_AlertLogID : AlertLogIDType := GetAlertLogID("CPU_1") ;
begin
------------------------------------------------------------
CpuP1 : process
constant CPU_P1_ID : AlertLogIDType := GetAlertLogID("CPU P1", CPU_AlertLogID) ;
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 5 ns ;
Alert(CPU_P1_ID, "Cpu.P1.E Message " & to_string(i) & " of 5", ERROR) ;
Log (CPU_P1_ID, "Cpu.P1.D log " & to_string(i) & " of 5", DEBUG) ;
Log (CPU_P1_ID, "Cpu.P1.F log " & to_string(i) & " of 5", FINAL) ; -- disabled
end loop ;
wait ;
end process CpuP1 ;
------------------------------------------------------------
CpuP2 : process
constant CPU_P2_ID : AlertLogIDType := GetAlertLogID("CPU P2", CPU_AlertLogID) ;
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 6 ns ;
Alert(CPU_P2_ID, "Cpu.P2.W Message " & to_string(i) & " of 5", WARNING) ;
Log (CPU_P2_ID, "Cpu.P2.I log " & to_string(i) & " of 5", INFO) ;
end loop ;
wait ;
end process CpuP2 ;
end block Cpu_1 ;
-- /////////////////////////////////////////////////////////////
-- \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
Uart_1 : block
constant UART_AlertLogID : AlertLogIDType := GetAlertLogID("UART_1") ;
begin
-- Enable FINAL logs for every level
-- Note it is expected that most control of alerts will occur only in the testbench block
-- Note that this does not turn on FINAL messages for CPU - see global for settings that impact CPU
SetLogEnable(UART_AlertLogID, FINAL, TRUE) ; -- Runs once at initialization time
------------------------------------------------------------
UartP1 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 10 ns ;
Alert(UART_AlertLogID, "Uart.P1.E alert " & to_string(i) & " of 5") ; -- ERROR by default
Log (UART_AlertLogID, "UART.P1.D log " & to_string(i) & " of 5", DEBUG) ;
end loop ;
wait ;
end process UartP1 ;
------------------------------------------------------------
UartP2 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 11 ns ;
Alert(UART_AlertLogID, "Uart.P2.W alert " & to_string(i) & " of 5", WARNING) ;
-- Info not enabled
Log (UART_AlertLogID, "UART.P2.I log " & to_string(i) & " of 5", INFO) ;
Log (UART_AlertLogID, "UART.P2.F log " & to_string(i) & " of 5", FINAL) ;
end loop ;
wait ;
end process UartP2 ;
end block Uart_1 ;
end hierarchy ; | artistic-2.0 | af993c914bc21f33497113680389f481 | 0.540547 | 3.721239 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/Stack/src/MROM.vhd | 1 | 1,718 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library stack;
use stack.OneHotStack.all;
entity MROM is
port (
RE: in std_logic;
ADDR: in mem_addr;
DOUT: out command
);
end MROM;
architecture Beh_Stack of MROM is
type tROM is array (0 to 31) of command;
constant STUB: mem_addr := "00000";
constant LENGTH: mem_addr := "10000";
constant COUNTER: mem_addr := "10001";
constant CURRENT_VALUE: mem_addr := "10010";
constant DATA_START: mem_addr := "00000";
constant INIT_VALUE: mem_addr := "10011";
constant ZERO: mem_addr := "10100";
constant ONE: mem_addr := "10101";
constant EMPTY_SPACE: mem_addr := "10110";
constant LOADDR: mem_addr := "01010";
constant ROM: tROM :=(
-- OP CODE | RAM ADDR
-- Init
PUSH & ZERO,
POP & COUNTER,
PUSH & ZERO,
POP & CURRENT_VALUE,
PUSH & ZERO,
POP & DATA_START,
PUSH & ONE,
PUSH & LENGTH,
SUBT & STUB,
POP & LENGTH,
-- Loop
PUSH & COUNTER,
PUSH & ONE,
ADD & STUB,
POP & COUNTER,
PUSH & COUNTER,
SHIFT & STUB,
POP & CURRENT_VALUE,
PUSH & CURRENT_VALUE,
POPIN & COUNTER,
PUSH & LENGTH,
PUSH & COUNTER,
SUBT & STUB,
JNZ & LOADDR,
others => HALT & STUB
);
signal data: command;
begin
data <= ROM(conv_integer(ADDR));
zbufs: process (RE, data)
begin
if (RE = '1') then
DOUT <= data;
else
DOUT <= (others => 'Z');
end if;
end process;
end Beh_Stack; | mit | 9d2fa5c7732c6a0c231d3ebdba6cc202 | 0.51688 | 3.123636 | false | false | false | false |
JimLewis/OSVVM | ResolutionPkg.vhd | 1 | 21,683 | --
-- File Name: ResolutionPkg.vhd
-- Design Unit Name: ResolutionPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
-- Package Defines
-- resolved resolution functions for integer, real, and time
-- types resolved_integer, resolved_real, resolved_time
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 09/2006 0.1 Initial revision
-- Numerous revisions for VHDL Testbenches and Verification
-- 02/2009 1.0 VHDL-2008 STANDARD VERSION
-- 05/2015 2015.05 Added Alerts
-- -- Replaced Alerts with asserts as alerts are illegal in pure functions
-- 11/2016 2016.11 Removed Asserts as they are not working as intended.
-- See ResolutionPkg_debug as it uses Alerts to correctly detect errors
-- 01/2020 2020.01 Updated Licenses to Apache
-- 12/2020 2020.12 Updated ToTransaction and FromTransaction with length parameter.
-- Downsizing now permitted when it does not change the value.
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2005 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
library osvvm ;
use osvvm.AlertLogPkg.all ;
package ResolutionPkg is
constant MULTIPLE_DRIVER_SEVERITY : severity_level := ERROR ;
--
-- Note that not all simulators support resolution functions of the form:
-- subtype std_logic_vector_max is (resolved_max) std_ulogic_vector ;
--
-- Hence, types of the form are offered as a temporary workaround until they do:
-- std_logic_vector_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
--
-- resolved_max
-- return maximum value.
-- No initializations required on ports, default of type'left is ok
function resolved_max ( s : std_ulogic_vector) return std_ulogic ;
subtype std_logic_max is resolved_max std_ulogic ;
subtype std_logic_vector_max is (resolved_max) std_ulogic_vector ;
type std_logic_vector_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
subtype unsigned_max is (resolved_max) unresolved_unsigned ;
type unsigned_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
subtype signed_max is (resolved_max) unresolved_signed ;
type signed_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
function resolved_max ( s : bit_vector) return bit ;
subtype bit_max is resolved_max bit ;
subtype bit_vector_max is (resolved_max) bit_vector ;
type bit_vector_max_c is array (natural range <>) of bit_max ; -- for non VHDL-2008
function resolved_max ( s : integer_vector ) return integer ;
subtype integer_max is resolved_max integer ;
subtype integer_vector_max is (resolved_max) integer_vector ;
type integer_vector_max_c is array (natural range <>) of integer_max ; -- for non VHDL-2008
function resolved_max ( s : time_vector ) return time ;
subtype time_max is resolved_max time ;
subtype time_vector_max is (resolved_max) time_vector ;
type time_vector_max_c is array (natural range <>) of time_max ; -- for non VHDL-2008
function resolved_max ( s : real_vector ) return real ;
subtype real_max is resolved_max real ;
subtype real_vector_max is (resolved_max) real_vector ;
type real_vector_max_c is array (natural range <>) of real_max ; -- for non VHDL-2008
function resolved_max ( s : string) return character ;
subtype character_max is resolved_max character ;
subtype string_max is (resolved_max) string ;
type string_max_c is array (positive range <>) of character_max ; -- for non VHDL-2008
function resolved_max ( s : boolean_vector) return boolean ;
subtype boolean_max is resolved_max boolean ;
subtype boolean_vector_max is (resolved_max) boolean_vector ;
type boolean_vector_max_c is array (natural range <>) of boolean_max ; -- for non VHDL-2008
--
-- ToTransaction and FromTransaction
-- Convert from Common types to their corresponding _max_c type
--
function Extend(A: std_logic_vector; Size : natural) return std_logic_vector ;
function Reduce(A: std_logic_vector; Size : natural) return std_logic_vector ;
function ToTransaction(A : std_logic_vector) return std_logic_vector_max_c ;
impure function ToTransaction(A : std_logic_vector ; Size : natural) return std_logic_vector_max_c ;
function ToTransaction(A : integer; Size : natural) return std_logic_vector_max_c ;
function FromTransaction (A: std_logic_vector_max_c) return std_logic_vector ;
impure function FromTransaction (A: std_logic_vector_max_c ; Size : natural) return std_logic_vector ;
function FromTransaction (A: std_logic_vector_max_c) return integer ;
--
-- ToTransaction and FromTransaction for _max provided to support a
-- common methodology, conversions are not needed
function ToTransaction(A : std_logic_vector) return std_logic_vector_max ;
impure function ToTransaction(A : std_logic_vector ; Size : natural) return std_logic_vector_max ;
function ToTransaction(A : integer; Size : natural) return std_logic_vector_max ;
function FromTransaction (A: std_logic_vector_max) return std_logic_vector ;
impure function FromTransaction (A: std_logic_vector_max ; Size : natural) return std_logic_vector ;
function FromTransaction (A: std_logic_vector_max) return integer ;
-- return sum of values that /= type'left
-- No initializations required on ports, default of type'left is ok
function resolved_sum ( s : integer_vector ) return integer ;
subtype integer_sum is resolved_sum integer ;
subtype integer_vector_sum is (resolved_sum) integer_vector ;
type integer_vector_sum_c is array (natural range <>) of integer_sum ; -- for non VHDL-2008
function resolved_sum ( s : time_vector ) return time ;
subtype time_sum is resolved_sum time ;
subtype time_vector_sum is (resolved_sum) time_vector ;
type time_vector_sum_c is array (natural range <>) of time_sum ; -- for non VHDL-2008
function resolved_sum ( s : real_vector ) return real ;
subtype real_sum is resolved_sum real ;
subtype real_vector_sum is (resolved_sum) real_vector ;
type real_vector_sum_c is array (natural range <>) of real_sum ; -- for non VHDL-2008
-- resolved_weak
-- Special just for std_ulogic
-- No initializations required on ports, default of type'left is ok
function resolved_weak (s : std_ulogic_vector) return std_ulogic ; -- no init, type'left
subtype std_logic_weak is resolved_weak std_ulogic ;
subtype std_logic_vector_weak is (resolved_weak) std_ulogic_vector ;
-- legacy stuff
-- requires ports to be initialized to 0 in the appropriate type.
function resolved ( s : integer_vector ) return integer ;
subtype resolved_integer is resolved integer ;
function resolved ( s : time_vector ) return time ;
subtype resolved_time is resolved time ;
function resolved ( s : real_vector ) return real ;
subtype resolved_real is resolved real ;
function resolved (s : string) return character ; -- same as resolved_max
subtype resolved_character is resolved character ;
-- subtype resolved_string is (resolved) string ; -- subtype will replace type later
type resolved_string is array (positive range <>) of resolved_character; -- will change to subtype -- assert but no init
function resolved ( s : boolean_vector) return boolean ; --same as resolved_max
subtype resolved_boolean is resolved boolean ;
end package ResolutionPkg ;
package body ResolutionPkg is
--
-- ToTransaction and FromTransaction
-- Convert from Common types to their corresponding _max_c type
--
function Extend(A: std_logic_vector; Size : natural) return std_logic_vector is
variable extA : std_logic_vector(Size downto 1) := (others => '0') ;
begin
extA(A'length downto 1) := A ;
return extA ;
end function Extend ;
function Reduce(A: std_logic_vector; Size : natural) return std_logic_vector is
alias aA : std_logic_vector(A'length-1 downto 0) is A ;
begin
return aA(Size-1 downto 0) ;
end function Reduce ;
-- SafeResize - handles std_logic_vector as unsigned
impure function SafeResize(A: std_logic_vector; Size : natural) return std_logic_vector is
variable Result : std_logic_vector(Size-1 downto 0) := (others => '0') ;
alias aA : std_logic_vector(A'length-1 downto 0) is A ;
begin
if A'length <= Size then
-- Extend A
Result(A'length-1 downto 0) := aA ;
else
-- Reduce A and Error if any extra bits of A are a '1'
AlertIf((OR aA(A'length-1 downto Size) = '1'), "ToTransaction/FromTransaction, threw away a 1") ;
Result := aA(Size-1 downto 0) ;
end if ;
return Result ;
end function SafeResize ;
function ToTransaction(A : std_logic_vector) return std_logic_vector_max_c is
begin
return std_logic_vector_max_c(A) ;
end function ToTransaction ;
impure function ToTransaction(A : std_logic_vector ; Size : natural) return std_logic_vector_max_c is
begin
return std_logic_vector_max_c(SafeResize(A, Size)) ;
end function ToTransaction ;
function ToTransaction(A : integer; Size : natural) return std_logic_vector_max_c is
begin
return std_logic_vector_max_c(to_signed(A, Size)) ;
end function ToTransaction ;
function FromTransaction (A: std_logic_vector_max_c) return std_logic_vector is
begin
return std_logic_vector(A) ;
end function FromTransaction ;
impure function FromTransaction (A: std_logic_vector_max_c ; Size : natural) return std_logic_vector is
begin
return SafeResize(std_logic_vector(A), Size) ;
end function FromTransaction ;
function FromTransaction (A: std_logic_vector_max_c) return integer is
begin
return to_integer(signed(A)) ;
end function FromTransaction ;
----------------------
-- Support for _max provided to support a common methodology,
-- conversions are not needed
function ToTransaction(A : std_logic_vector) return std_logic_vector_max is
begin
return A ;
end function ToTransaction ;
impure function ToTransaction(A : std_logic_vector ; Size : natural) return std_logic_vector_max is
begin
return SafeResize(A, Size) ;
end function ToTransaction ;
function ToTransaction(A : integer; Size : natural) return std_logic_vector_max is
begin
return std_logic_vector_max(to_signed(A, Size)) ;
end function ToTransaction ;
function FromTransaction (A: std_logic_vector_max) return std_logic_vector is
begin
return A ;
end function FromTransaction ;
impure function FromTransaction (A: std_logic_vector_max ; Size : natural) return std_logic_vector is
begin
return SafeResize(A, Size) ;
end function FromTransaction ;
function FromTransaction (A: std_logic_vector_max) return integer is
begin
return to_integer(signed(A)) ;
end function FromTransaction ;
-- resolved_max
-- return maximum value. Assert FAILURE if more than 1 /= type'left
-- No initializations required on ports, default of type'left is ok
-- Optimized version is just the following:
-- ------------------------------------------------------------
-- function resolved_max ( s : <array_type> ) return <element_type> is
-- ------------------------------------------------------------
-- begin
-- return maximum(s) ;
-- end function resolved_max ;
------------------------------------------------------------
function resolved_max (s : std_ulogic_vector) return std_ulogic is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : bit_vector ) return bit is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : integer_vector ) return integer is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : time_vector ) return time is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : real_vector ) return real is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : string ) return character is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : boolean_vector) return boolean is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
-- resolved_sum - appropriate for numeric types
-- return sum of values that /= type'left
-- No initializations required on ports, default of type'left is ok
------------------------------------------------------------
function resolved_sum ( s : integer_vector ) return integer is
------------------------------------------------------------
variable result : integer := 0 ;
begin
for i in s'RANGE loop
if s(i) /= integer'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
------------------------------------------------------------
function resolved_sum ( s : time_vector ) return time is
------------------------------------------------------------
variable result : time := 0 sec ;
begin
for i in s'RANGE loop
if s(i) /= time'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
------------------------------------------------------------
function resolved_sum ( s : real_vector ) return real is
------------------------------------------------------------
variable result : real := 0.0 ;
begin
for i in s'RANGE loop
if s(i) /= real'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
-- resolved_weak
-- Special just for std_ulogic
-- No initializations required on ports, default of type'left is ok
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant weak_resolution_table : stdlogic_table := (
-- Resolution order: Z < U < W < X < - < L < H < 0 < 1
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
('U', 'X', '0', '1', 'U', 'W', 'L', 'H', '-'), -- | U |
('X', 'X', '0', '1', 'X', 'X', 'L', 'H', '-'), -- | X |
('0', '0', '0', '1', '0', '0', '0', '0', '0'), -- | 0 |
('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | 1 |
('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'), -- | Z |
('W', 'X', '0', '1', 'W', 'W', 'L', 'H', '-'), -- | W |
('L', 'L', '0', '1', 'L', 'L', 'L', 'H', 'L'), -- | L |
('H', 'H', '0', '1', 'H', 'H', 'W', 'H', 'H'), -- | H |
('-', '-', '0', '1', '-', '-', 'L', 'H', '-') -- | - |
);
------------------------------------------------------------
function resolved_weak (s : std_ulogic_vector) return std_ulogic is
------------------------------------------------------------
variable result : std_ulogic := 'Z' ;
begin
for i in s'RANGE loop
result := weak_resolution_table(result, s(i)) ;
end loop ;
return result ;
end function resolved_weak ;
-- legacy stuff.
-- requires ports to be initialized to 0 in the appropriate type.
------------------------------------------------------------
function resolved ( s : integer_vector ) return integer is
-- requires interface to be initialized to 0
------------------------------------------------------------
variable result : integer := 0 ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= 0 then
failed := failed or (result /= 0) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on integer" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on integer") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : time_vector ) return time is
-- requires interface to be initialized to 0 ns
------------------------------------------------------------
variable result : time := 0 ns ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) > 0 ns then
failed := failed or (result /= 0 ns) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on time" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on time") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : real_vector ) return real is
-- requires interface to be initialized to 0.0
------------------------------------------------------------
variable result : real := 0.0 ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= 0.0 then
failed := failed or (result /= 0.0) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on real" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on real") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved (s : string) return character is
-- same as resolved_max
------------------------------------------------------------
variable result : character := NUL ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= NUL then
failed := failed or (result /= NUL) ;
result := maximum(result, s(i)) ;
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on character" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on character") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : boolean_vector) return boolean is
-- same as resolved_max
------------------------------------------------------------
variable result : boolean := FALSE ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) then
failed := failed or result ;
result := TRUE ;
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on boolean" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on boolean") ;
return result ;
end function resolved ;
end package body ResolutionPkg ;
| artistic-2.0 | 3514765c2b1863dfbe69c31984d0fe46 | 0.567357 | 4.291114 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/Zynq_Book/hls/tut3A/matrix_mult_prj/solution3/syn/vhdl/matrix_mult.vhd | 1 | 52,959 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity matrix_mult is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
a_address0 : OUT STD_LOGIC_VECTOR (4 downto 0);
a_ce0 : OUT STD_LOGIC;
a_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
a_address1 : OUT STD_LOGIC_VECTOR (4 downto 0);
a_ce1 : OUT STD_LOGIC;
a_q1 : IN STD_LOGIC_VECTOR (7 downto 0);
b_address0 : OUT STD_LOGIC_VECTOR (4 downto 0);
b_ce0 : OUT STD_LOGIC;
b_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
b_address1 : OUT STD_LOGIC_VECTOR (4 downto 0);
b_ce1 : OUT STD_LOGIC;
b_q1 : IN STD_LOGIC_VECTOR (7 downto 0);
prod_address0 : OUT STD_LOGIC_VECTOR (4 downto 0);
prod_ce0 : OUT STD_LOGIC;
prod_we0 : OUT STD_LOGIC;
prod_d0 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of matrix_mult is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"matrix_mult,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=5.415000,HLS_SYN_LAT=88,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=3,HLS_SYN_FF=1012,HLS_SYN_LUT=635}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv5_19 : STD_LOGIC_VECTOR (4 downto 0) := "11001";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_const_lv3_5 : STD_LOGIC_VECTOR (2 downto 0) := "101";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv4_5 : STD_LOGIC_VECTOR (3 downto 0) := "0101";
constant ap_const_lv5_14 : STD_LOGIC_VECTOR (4 downto 0) := "10100";
constant ap_const_lv6_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_const_lv6_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100";
constant ap_const_lv5_F : STD_LOGIC_VECTOR (4 downto 0) := "01111";
constant ap_const_lv6_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
constant ap_const_lv6_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011";
constant ap_const_lv5_A : STD_LOGIC_VECTOR (4 downto 0) := "01010";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal indvar_flatten_reg_172 : STD_LOGIC_VECTOR (4 downto 0);
signal i_reg_183 : STD_LOGIC_VECTOR (2 downto 0);
signal j_reg_194 : STD_LOGIC_VECTOR (2 downto 0);
signal reg_205 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_block_state2_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state5_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state8_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state11_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state14_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal exitcond_flatten_reg_453 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage2 : signal is "none";
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal ap_block_state4_pp0_stage2_iter0 : BOOLEAN;
signal ap_block_state7_pp0_stage2_iter1 : BOOLEAN;
signal ap_block_state10_pp0_stage2_iter2 : BOOLEAN;
signal ap_block_state13_pp0_stage2_iter3 : BOOLEAN;
signal ap_block_state16_pp0_stage2_iter4 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011001 : BOOLEAN;
signal ap_reg_pp0_iter2_exitcond_flatten_reg_453 : STD_LOGIC_VECTOR (0 downto 0);
signal reg_209 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_pp0_stage1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage1 : signal is "none";
signal ap_block_state3_pp0_stage1_iter0 : BOOLEAN;
signal ap_block_state6_pp0_stage1_iter1 : BOOLEAN;
signal ap_block_state9_pp0_stage1_iter2 : BOOLEAN;
signal ap_block_state12_pp0_stage1_iter3 : BOOLEAN;
signal ap_block_state15_pp0_stage1_iter4 : BOOLEAN;
signal ap_block_pp0_stage1_flag00011001 : BOOLEAN;
signal ap_reg_pp0_iter1_exitcond_flatten_reg_453 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten_fu_214_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_exitcond_flatten_reg_453 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter4_exitcond_flatten_reg_453 : STD_LOGIC_VECTOR (0 downto 0);
signal indvar_flatten_next_fu_220_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal indvar_flatten_next_reg_457 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal j_mid2_fu_238_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal j_mid2_reg_462 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter1_j_mid2_reg_462 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter2_j_mid2_reg_462 : STD_LOGIC_VECTOR (2 downto 0);
signal i_cast6_mid2_v_fu_246_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal i_cast6_mid2_v_reg_471 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_7_fu_268_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_7_reg_478 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_pp0_iter1_tmp_7_reg_478 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_pp0_iter2_tmp_7_reg_478 : STD_LOGIC_VECTOR (5 downto 0);
signal j_cast5_cast3_fu_274_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal j_cast5_cast3_reg_488 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_pp0_iter1_j_cast5_cast3_reg_488 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_pp0_iter2_j_cast5_cast3_reg_488 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_12_fu_280_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_reg_494 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_15_fu_286_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_15_reg_499 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_8_fu_292_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_8_reg_504 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_11_fu_297_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_11_reg_509 : STD_LOGIC_VECTOR (5 downto 0);
signal j_1_fu_310_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal j_1_reg_524 : STD_LOGIC_VECTOR (2 downto 0);
signal b_load_1_reg_539 : STD_LOGIC_VECTOR (7 downto 0);
signal a_load_1_reg_544 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_14_fu_323_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_14_reg_549 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_9_fu_342_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_9_reg_564 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_10_fu_347_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_10_reg_569 : STD_LOGIC_VECTOR (5 downto 0);
signal b_load_3_reg_604 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_13_fu_387_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_13_reg_614 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_16_fu_392_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_16_reg_619 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_pp0_iter3_tmp_16_reg_619 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_fu_336_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_reg_649 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_362_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_reg_654 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_432_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp4_reg_669 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
signal grp_fu_439_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp1_reg_674 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_446_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp3_reg_679 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
signal tmp_3_4_fu_424_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 : string;
attribute use_dsp48 of tmp_3_4_fu_424_p2 : signal is "no";
signal tmp_3_4_reg_684 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state2 : STD_LOGIC;
signal ap_block_pp0_stage2_flag00011011 : BOOLEAN;
signal indvar_flatten_phi_fu_176_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal i_phi_fu_187_p4 : STD_LOGIC_VECTOR (2 downto 0);
signal j_phi_fu_198_p4 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_cast_fu_302_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_block_pp0_stage2_flag00000000 : BOOLEAN;
signal tmp_15_cast_fu_306_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_cast_fu_315_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_cast_fu_319_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_14_cast_fu_352_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_9_cast_fu_368_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_block_pp0_stage1_flag00000000 : BOOLEAN;
signal tmp_10_cast_fu_372_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal j_cast5_fu_376_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_7_cast_fu_380_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_13_cast_fu_404_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_16_cast_fu_428_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal exitcond_fu_232_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_1_fu_226_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_fu_257_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal i_cast6_mid2_cast_fu_254_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl_cast_fu_264_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal j_cast5_cast_fu_277_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal j_cast5_cast4_fu_384_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state17 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state17 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
signal ap_block_pp0_stage1_flag00011011 : BOOLEAN;
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component matrix_mult_mul_8bkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component matrix_mult_mac_mcud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
din2 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component matrix_mult_mac_mdEe IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
din2 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
begin
matrix_mult_mul_8bkb_U0 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => reg_209,
din1 => reg_205,
ce => ap_const_logic_1,
dout => grp_fu_336_p2);
matrix_mult_mul_8bkb_U1 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => a_load_1_reg_544,
din1 => b_load_1_reg_539,
ce => ap_const_logic_1,
dout => grp_fu_362_p2);
matrix_mult_mac_mcud_U2 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => a_q1,
din1 => b_load_3_reg_604,
din2 => tmp_2_4_reg_649,
ce => ap_const_logic_1,
dout => grp_fu_432_p3);
matrix_mult_mac_mcud_U3 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => a_q0,
din1 => reg_205,
din2 => tmp_2_1_reg_654,
ce => ap_const_logic_1,
dout => grp_fu_439_p3);
matrix_mult_mac_mdEe_U4 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => reg_209,
din1 => b_q1,
din2 => tmp4_reg_669,
ce => ap_const_logic_1,
dout => grp_fu_446_p3);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2)) then
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state2 xor ap_const_logic_1);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
i_reg_183_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten_reg_453 = ap_const_lv1_0))) then
i_reg_183 <= i_cast6_mid2_v_reg_471;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_183 <= ap_const_lv3_0;
end if;
end if;
end process;
indvar_flatten_reg_172_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten_reg_453 = ap_const_lv1_0))) then
indvar_flatten_reg_172 <= indvar_flatten_next_reg_457;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
indvar_flatten_reg_172 <= ap_const_lv5_0;
end if;
end if;
end process;
j_reg_194_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten_reg_453 = ap_const_lv1_0))) then
j_reg_194 <= j_1_reg_524;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
j_reg_194 <= ap_const_lv3_0;
end if;
end if;
end process;
reg_209_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter2_exitcond_flatten_reg_453))) then
reg_209 <= a_q0;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten_reg_453))) then
reg_209 <= a_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten_reg_453))) then
a_load_1_reg_544 <= a_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter1_exitcond_flatten_reg_453 <= exitcond_flatten_reg_453;
ap_reg_pp0_iter1_j_mid2_reg_462 <= j_mid2_reg_462;
ap_reg_pp0_iter2_exitcond_flatten_reg_453 <= ap_reg_pp0_iter1_exitcond_flatten_reg_453;
ap_reg_pp0_iter2_j_mid2_reg_462 <= ap_reg_pp0_iter1_j_mid2_reg_462;
ap_reg_pp0_iter3_exitcond_flatten_reg_453 <= ap_reg_pp0_iter2_exitcond_flatten_reg_453;
ap_reg_pp0_iter4_exitcond_flatten_reg_453 <= ap_reg_pp0_iter3_exitcond_flatten_reg_453;
exitcond_flatten_reg_453 <= exitcond_flatten_fu_214_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter1_j_cast5_cast3_reg_488(2 downto 0) <= j_cast5_cast3_reg_488(2 downto 0);
ap_reg_pp0_iter1_tmp_7_reg_478 <= tmp_7_reg_478;
ap_reg_pp0_iter2_j_cast5_cast3_reg_488(2 downto 0) <= ap_reg_pp0_iter1_j_cast5_cast3_reg_488(2 downto 0);
ap_reg_pp0_iter2_tmp_7_reg_478 <= ap_reg_pp0_iter1_tmp_7_reg_478;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter3_tmp_16_reg_619 <= tmp_16_reg_619;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten_reg_453 = ap_const_lv1_0))) then
b_load_1_reg_539 <= b_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_const_lv1_0 = ap_reg_pp0_iter2_exitcond_flatten_reg_453) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
b_load_3_reg_604 <= b_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_lv1_0 = exitcond_flatten_fu_214_p2))) then
i_cast6_mid2_v_reg_471 <= i_cast6_mid2_v_fu_246_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
indvar_flatten_next_reg_457 <= indvar_flatten_next_fu_220_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten_reg_453 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
j_1_reg_524 <= j_1_fu_310_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten_reg_453 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
j_cast5_cast3_reg_488(2 downto 0) <= j_cast5_cast3_fu_274_p1(2 downto 0);
tmp_12_reg_494 <= tmp_12_fu_280_p2;
tmp_15_reg_499 <= tmp_15_fu_286_p2;
tmp_7_reg_478 <= tmp_7_fu_268_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond_flatten_fu_214_p2))) then
j_mid2_reg_462 <= j_mid2_fu_238_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten_reg_453 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter2_exitcond_flatten_reg_453)))) then
reg_205 <= b_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter3_exitcond_flatten_reg_453) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
tmp1_reg_674 <= grp_fu_439_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter3_exitcond_flatten_reg_453) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
tmp3_reg_679 <= grp_fu_446_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter3_exitcond_flatten_reg_453) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
tmp4_reg_669 <= grp_fu_432_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten_reg_453))) then
tmp_10_reg_569 <= tmp_10_fu_347_p2;
tmp_9_reg_564 <= tmp_9_fu_342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten_reg_453 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
tmp_11_reg_509 <= tmp_11_fu_297_p2;
tmp_8_reg_504 <= tmp_8_fu_292_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter2_exitcond_flatten_reg_453))) then
tmp_13_reg_614 <= tmp_13_fu_387_p2;
tmp_16_reg_619 <= tmp_16_fu_392_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond_flatten_reg_453))) then
tmp_14_reg_549 <= tmp_14_fu_323_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter3_exitcond_flatten_reg_453))) then
tmp_2_1_reg_654 <= grp_fu_362_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter2_exitcond_flatten_reg_453))) then
tmp_2_4_reg_649 <= grp_fu_336_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter4_exitcond_flatten_reg_453))) then
tmp_3_4_reg_684 <= tmp_3_4_fu_424_p2;
end if;
end if;
end process;
j_cast5_cast3_reg_488(4 downto 3) <= "00";
ap_reg_pp0_iter1_j_cast5_cast3_reg_488(4 downto 3) <= "00";
ap_reg_pp0_iter2_j_cast5_cast3_reg_488(4 downto 3) <= "00";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage2, exitcond_flatten_fu_214_p2, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011011, ap_block_pp0_stage2_flag00011011, ap_block_pp0_stage1_flag00011011)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_pp0_stage0 =>
if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_flatten_fu_214_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_flatten_fu_214_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state17;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage1 =>
if ((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
end if;
when ap_ST_fsm_pp0_stage2 =>
if (((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state17;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
end if;
when ap_ST_fsm_state17 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
a_address0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage2_flag00000000, tmp_8_cast_fu_315_p1, tmp_9_cast_fu_368_p1, ap_block_pp0_stage1_flag00000000, tmp_7_cast_fu_380_p1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
a_address0 <= tmp_7_cast_fu_380_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
a_address0 <= tmp_9_cast_fu_368_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
a_address0 <= tmp_8_cast_fu_315_p1(5 - 1 downto 0);
else
a_address0 <= "XXXXX";
end if;
end process;
a_address1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage0_flag00000000, tmp_11_cast_fu_319_p1, ap_block_pp0_stage1_flag00000000, tmp_10_cast_fu_372_p1)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
a_address1 <= tmp_10_cast_fu_372_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
a_address1 <= tmp_11_cast_fu_319_p1(5 - 1 downto 0);
else
a_address1 <= "XXXXX";
end if;
end process;
a_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)))) then
a_ce0 <= ap_const_logic_1;
else
a_ce0 <= ap_const_logic_0;
end if;
end process;
a_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)))) then
a_ce1 <= ap_const_logic_1;
else
a_ce1 <= ap_const_logic_0;
end if;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(1);
ap_CS_fsm_pp0_stage1 <= ap_CS_fsm(2);
ap_CS_fsm_pp0_stage2 <= ap_CS_fsm(3);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state17 <= ap_CS_fsm(4);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state10_pp0_stage2_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage1_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage2_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state14_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state15_pp0_stage1_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state16_pp0_stage2_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state2_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage1_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage2_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage1_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_pp0_exit_iter0_state2_assign_proc : process(exitcond_flatten_fu_214_p2)
begin
if ((exitcond_flatten_fu_214_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_CS_fsm_state17)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state17)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2) and (ap_const_logic_0 = ap_enable_reg_pp0_iter3) and (ap_const_logic_0 = ap_enable_reg_pp0_iter4))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state17)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state17)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
b_address0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage2_flag00000000, tmp_15_cast_fu_306_p1, tmp_14_cast_fu_352_p1, ap_block_pp0_stage1_flag00000000, j_cast5_fu_376_p1)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
b_address0 <= j_cast5_fu_376_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
b_address0 <= tmp_14_cast_fu_352_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
b_address0 <= tmp_15_cast_fu_306_p1(5 - 1 downto 0);
else
b_address0 <= "XXXXX";
end if;
end process;
b_address1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_flag00000000, tmp_12_cast_fu_302_p1, ap_block_pp0_stage2_flag00000000, tmp_13_cast_fu_404_p1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
b_address1 <= tmp_13_cast_fu_404_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
b_address1 <= tmp_12_cast_fu_302_p1(5 - 1 downto 0);
else
b_address1 <= "XXXXX";
end if;
end process;
b_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_enable_reg_pp0_iter0)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2)))) then
b_ce0 <= ap_const_logic_1;
else
b_ce0 <= ap_const_logic_0;
end if;
end process;
b_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3)))) then
b_ce1 <= ap_const_logic_1;
else
b_ce1 <= ap_const_logic_0;
end if;
end process;
exitcond_flatten_fu_214_p2 <= "1" when (indvar_flatten_phi_fu_176_p4 = ap_const_lv5_19) else "0";
exitcond_fu_232_p2 <= "1" when (j_phi_fu_198_p4 = ap_const_lv3_5) else "0";
i_1_fu_226_p2 <= std_logic_vector(unsigned(i_phi_fu_187_p4) + unsigned(ap_const_lv3_1));
i_cast6_mid2_cast_fu_254_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_cast6_mid2_v_reg_471),6));
i_cast6_mid2_v_fu_246_p3 <=
i_1_fu_226_p2 when (exitcond_fu_232_p2(0) = '1') else
i_phi_fu_187_p4;
i_phi_fu_187_p4_assign_proc : process(i_reg_183, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_453, i_cast6_mid2_v_reg_471, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (exitcond_flatten_reg_453 = ap_const_lv1_0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
i_phi_fu_187_p4 <= i_cast6_mid2_v_reg_471;
else
i_phi_fu_187_p4 <= i_reg_183;
end if;
end process;
indvar_flatten_next_fu_220_p2 <= std_logic_vector(unsigned(indvar_flatten_phi_fu_176_p4) + unsigned(ap_const_lv5_1));
indvar_flatten_phi_fu_176_p4_assign_proc : process(indvar_flatten_reg_172, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_453, indvar_flatten_next_reg_457, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (exitcond_flatten_reg_453 = ap_const_lv1_0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
indvar_flatten_phi_fu_176_p4 <= indvar_flatten_next_reg_457;
else
indvar_flatten_phi_fu_176_p4 <= indvar_flatten_reg_172;
end if;
end process;
j_1_fu_310_p2 <= std_logic_vector(unsigned(j_mid2_reg_462) + unsigned(ap_const_lv3_1));
j_cast5_cast3_fu_274_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_mid2_reg_462),5));
j_cast5_cast4_fu_384_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter2_j_mid2_reg_462),6));
j_cast5_cast_fu_277_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_mid2_reg_462),4));
j_cast5_fu_376_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter2_j_mid2_reg_462),32));
j_mid2_fu_238_p3 <=
ap_const_lv3_0 when (exitcond_fu_232_p2(0) = '1') else
j_phi_fu_198_p4;
j_phi_fu_198_p4_assign_proc : process(j_reg_194, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_453, j_1_reg_524, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (exitcond_flatten_reg_453 = ap_const_lv1_0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
j_phi_fu_198_p4 <= j_1_reg_524;
else
j_phi_fu_198_p4 <= j_reg_194;
end if;
end process;
p_shl_cast_fu_264_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_fu_257_p3),6));
prod_address0 <= tmp_16_cast_fu_428_p1(5 - 1 downto 0);
prod_ce0_assign_proc : process(ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter4)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
prod_ce0 <= ap_const_logic_1;
else
prod_ce0 <= ap_const_logic_0;
end if;
end process;
prod_d0 <= tmp_3_4_reg_684;
prod_we0_assign_proc : process(ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_reg_pp0_iter4_exitcond_flatten_reg_453, ap_enable_reg_pp0_iter4)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4) and (ap_const_lv1_0 = ap_reg_pp0_iter4_exitcond_flatten_reg_453))) then
prod_we0 <= ap_const_logic_1;
else
prod_we0 <= ap_const_logic_0;
end if;
end process;
tmp_10_cast_fu_372_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_10_reg_569),32));
tmp_10_fu_347_p2 <= std_logic_vector(unsigned(ap_reg_pp0_iter1_tmp_7_reg_478) + unsigned(ap_const_lv6_3));
tmp_11_cast_fu_319_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_11_reg_509),32));
tmp_11_fu_297_p2 <= std_logic_vector(unsigned(tmp_7_reg_478) + unsigned(ap_const_lv6_4));
tmp_12_cast_fu_302_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_12_reg_494),32));
tmp_12_fu_280_p2 <= std_logic_vector(unsigned(j_cast5_cast_fu_277_p1) + unsigned(ap_const_lv4_5));
tmp_13_cast_fu_404_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_reg_614),32));
tmp_13_fu_387_p2 <= std_logic_vector(unsigned(ap_reg_pp0_iter2_j_cast5_cast3_reg_488) + unsigned(ap_const_lv5_A));
tmp_14_cast_fu_352_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_14_reg_549),32));
tmp_14_fu_323_p2 <= std_logic_vector(unsigned(ap_reg_pp0_iter1_j_cast5_cast3_reg_488) + unsigned(ap_const_lv5_F));
tmp_15_cast_fu_306_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_15_reg_499),32));
tmp_15_fu_286_p2 <= std_logic_vector(unsigned(j_cast5_cast3_fu_274_p1) + unsigned(ap_const_lv5_14));
tmp_16_cast_fu_428_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter3_tmp_16_reg_619),32));
tmp_16_fu_392_p2 <= std_logic_vector(unsigned(ap_reg_pp0_iter2_tmp_7_reg_478) + unsigned(j_cast5_cast4_fu_384_p1));
tmp_3_4_fu_424_p2 <= std_logic_vector(signed(tmp1_reg_674) + signed(tmp3_reg_679));
tmp_7_cast_fu_380_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter2_tmp_7_reg_478),32));
tmp_7_fu_268_p2 <= std_logic_vector(unsigned(i_cast6_mid2_cast_fu_254_p1) + unsigned(p_shl_cast_fu_264_p1));
tmp_8_cast_fu_315_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_8_reg_504),32));
tmp_8_fu_292_p2 <= std_logic_vector(unsigned(tmp_7_reg_478) + unsigned(ap_const_lv6_1));
tmp_9_cast_fu_368_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_9_reg_564),32));
tmp_9_fu_342_p2 <= std_logic_vector(unsigned(ap_reg_pp0_iter1_tmp_7_reg_478) + unsigned(ap_const_lv6_2));
tmp_fu_257_p3 <= (i_cast6_mid2_v_reg_471 & ap_const_lv2_0);
end behav;
| mit | 400d8b86455956fa7de9828198565b99 | 0.600011 | 2.807113 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/memctrl/sdctrl.vhd | 1 | 29,625 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdctrl
-- File: sdctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 32-bit SDRAM memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
entity sdctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of sdctrl is
constant WPROTEN : boolean := wprot = 1;
constant SDINVCLK : boolean := invclk = 1;
constant BUS64 : boolean := (sdbits = 64);
constant REVISION : integer := 1;
constant PM_PD : std_logic_vector(2 downto 0) := "001";
constant PM_SR : std_logic_vector(2 downto 0) := "010";
constant PM_DPD : std_logic_vector(2 downto 0) := "101";
constant std_rammask: Std_Logic_Vector(31 downto 20) :=
Conv_Std_Logic_Vector(hmask, 12);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SDCTRL, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, leadout);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4, wr5, sidle,
sref, pd, dpd);
type icycletype is (iidle, pre, ref, lmode, emode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(14 downto 0);
renable : std_ulogic;
pageburst : std_ulogic;
mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
cke : std_ulogic; -- Clock enable
end record;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
bdrive : std_ulogic;
nbdrive : std_ulogic;
burst : std_ulogic;
wprothit : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
icnt : std_logic_vector(2 downto 0);
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(sdbits-1 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
size : std_logic_vector(1 downto 0);
cfg : sdram_cfg_type;
trfc : std_logic_vector(3 downto 0);
refresh : std_logic_vector(14 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
address : std_logic_vector(16 downto 2); -- memory address
bsel : std_ulogic;
idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref
pwron : std_ulogic;
end record;
signal r, ri : reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
ctrl : process(rst, ahbsi, r, sdi, rbdrive)
variable v : reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(12 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable dout : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable lline : std_logic_vector(2 downto 0);
variable lineburst : boolean;
variable haddr_tmp : std_logic_vector(31 downto 0);
variable arefresh : std_logic;
variable hwdata : std_logic_vector(31 downto 0);
begin
-- Variable default settings to avoid latches
v := r; startsd := '0'; v.hresp := HRESP_OKAY; vbdrive := rbdrive; arefresh := '0';
v.hrdata(sdbits-1 downto sdbits-32) := sdi.data(sdbits-1 downto sdbits-32);
v.hrdata(31 downto 0) := sdi.data(31 downto 0);
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2)); v.hwdata := hwdata;
lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then
lineburst := true;
else lineburst := false; end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := v.hio;
end if;
v.haddr := ahbsi.haddr;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
v.haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size;
htrans := r.htrans; hwrite := r.hwrite;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if fast = 1 then haddr := r.haddr; end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
-- main state
case r.size is
when "00" =>
case r.haddr(1 downto 0) is
when "00" => dqm := "11110111";
when "01" => dqm := "11111011";
when "10" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
if r.haddr(1) = '0' then dqm := "11110011"; else dqm := "11111100"; end if;
when others => dqm := "11110000";
end case;
if BUS64 and (r.bsel = '1') then dqm := dqm(3 downto 0) & "1111"; end if;
-- main FSM
case r.mstate is
when midle =>
if ((v.hsel and htrans(1) and not v.hio) = '1') then
if (r.sdstate = sidle) and (r.cfg.command = "000")
and (r.cmstate = midle) and (v.hio = '0')
then
if fast = 0 then startsd := '1'; else v.startsd := '1'; end if;
v.mstate := active;
elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
and (r.cfg.command = "000") and (r.cmstate = midle) and (v.hio = '0')
then
v.startsd := '1';
if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
v.hresp := HRESP_ERROR;
else
v.mstate := active;
end if;
end if;
end if;
when others => null;
end case;
startsd := startsd or r.startsd;
-- generate row and column address size
case r.cfg.csize is
when "00" => raddr := haddr(22 downto 10);
when "01" => raddr := haddr(23 downto 11);
when "10" => raddr := haddr(24 downto 12);
when others =>
if r.cfg.bsize = "111" then raddr := haddr(26 downto 14);
else raddr := haddr(25 downto 13); end if;
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
genmux(r.cfg.bsize, haddr(27 downto 20));
-- generate chip select
if BUS64 then
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
v.bsel := genmux(r.cfg.bsize, r.haddr(29 downto 22));
else
adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
end if;
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
v.address(16 downto 2) := ba & raddr;
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
v.startsd := '0';
elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
case r.cfg.pmode is
when PM_SR =>
v.cfg.cke := '0'; v.sdstate := sref;
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
when PM_DPD =>
v.cfg.cke := '0'; v.sdstate := dpd;
v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
when others =>
end case;
end if;
when act1 =>
v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
if r.cfg.casdel = '1' then v.sdstate := act2; else
v.sdstate := act3;
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
end if;
if WPROTEN then
v.wprothit := sdi.wprot;
if sdi.wprot = '1' then v.hresp := HRESP_ERROR; end if;
end if;
when act2 =>
v.sdstate := act3;
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '0';
end if;
when act3 =>
v.casn := '0';
v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
v.dqm := dqm; v.burst := r.hready;
if r.hwrite = '1' then
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0';
if ahbsi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '1';
v.sdstate := wr1; v.sdwen := '1'; v.bdrive := '1'; v.casn := '1';
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
if (((r.burst and r.hready) = '1') and (r.htrans = "11"))
and not (WPROTEN and (r.wprothit = '1'))
then
v.hready := ahbsi.htrans(0) and ahbsi.htrans(1) and r.hready;
if ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
v.hready := '0';
end if;
else
v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
end if;
when wr2 =>
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
v.sdstate := wr3;
when wr3 =>
if (r.cfg.trp = '1') then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
else
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if (r.cfg.trp = '1') then v.sdstate := wr5;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
when wr5 =>
v.sdstate := sidle; v.idlecnt := (others => '1');
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
if lineburst and (ahbsi.htrans = "11") then
if r.haddr(4 downto 2) = "111" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd7 =>
v.casn := '1';
if r.cfg.casdel = '1' then
v.sdstate := rd2;
if lineburst and (ahbsi.htrans = "11") then
if r.haddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else
v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if r.haddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if ahbsi.htrans /= "11" then v.rasn := '0'; v.sdwen := '0';
elsif lineburst then
if r.haddr(4 downto 2) = "101" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
elsif lineburst and (ahbsi.htrans = "11") and (r.casn = '1') then
if r.haddr(4 downto 2) = ("10" & not r.cfg.casdel) then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (ahbsi.htrans /= "11") or (r.sdcsn = "11") or
((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) -- exit on refresh
then
v.hready := '0'; v.dqm := (others => '1');
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
end if;
elsif lineburst then
if (r.haddr(4 downto 2) = lline) and (r.casn = '1') then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
v.casn := '1';
when rd6 =>
v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when sref =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
if r.trfc = "0000" then -- Minimum duration (= tRAS)
v.cfg.cke := '1';
v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
end if;
if r.cfg.cke = '1' then
if (r.idlecnt = "0000") then -- tXSR ns with NOP
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.sref_tmpcom := r.cfg.command;
v.cfg.command := "100";
end if;
else
v.idlecnt := r.cfg.txsr;
end if;
end if;
when pd =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
v.cfg.cke := '1';
v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when dpd =>
v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
v.cfg.renable := '0';
if (startsd = '1' and r.hio = '0') then
v.hready := '1'; -- ack all accesses with Error response
v.startsd := '0';
v.hresp := HRESP_ERROR;
elsif r.cfg.pmode /= PM_DPD then
v.cfg.cke := '1';
if r.cfg.cke = '1' then
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.cfg.renable := '1';
end if;
end if;
when others =>
v.sdstate := sidle; v.idlecnt := (others => '1');
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when "010" => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when "100" => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when "110" => -- Lodad Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
if lineburst then
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0011";
else
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0111";
end if;
when "111" => -- Load Ext-Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
& r.cfg.pasr(2 downto 0);
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; --v.cfg.command := "000";
v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
when leadout =>
if r.trfc = "0000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
v.cfg.cke := '1';
if (r.cfg.renable = '1' or (pwron /= 0 and r.pwron = '1')) and r.cfg.cke = '1' then
v.cfg.command := "010"; v.istate := pre;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
end if;
when ref =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.icnt := r.icnt - 1;
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.mobileen = "11" then
v.cfg.command := "111"; v.istate := emode;
else
v.istate := finish;
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := finish;
end if;
when others =>
if pwron /= 0 then v.pwron := '0'; end if;
if r.cfg.renable = '0' and r.sdstate /= dpd then
v.istate := iidle;
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
if (r.hsel and r.hio and not r.hready) = '1' then v.hready := '1'; end if;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
-- pragma translate_off
if not is_x(r.cfg.refresh) then
-- pragma translate_on
if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
v.refresh := r.refresh - 1;
if (v.refresh(14) and not r.refresh(14)) = '1' then
v.refresh := r.cfg.refresh;
v.cfg.command := "100";
arefresh := '1';
end if;
end if;
-- pragma translate_off
end if;
-- pragma translate_on
-- AHB register access
if (r.hsel and r.hio and r.hwrite and r.htrans(1)) = '1' then
if r.haddr(3 downto 2) = "00" then
if pageburst = 2 then v.cfg.pageburst := hwdata(17); end if;
v.cfg.command := hwdata(20 downto 18);
v.cfg.csize := hwdata(22 downto 21);
v.cfg.bsize := hwdata(25 downto 23);
v.cfg.casdel := hwdata(26);
v.cfg.trfc := hwdata(29 downto 27);
v.cfg.trp := hwdata(30);
v.cfg.renable := hwdata(31);
v.cfg.refresh := hwdata(14 downto 0);
v.refresh := (others => '0');
elsif r.haddr(3 downto 2) = "01" then
if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := hwdata(31); end if;
if r.cfg.pmode = "000" then
v.cfg.cke := hwdata(30);
end if;
if r.cfg.mobileen(1) = '1' then
v.cfg.txsr := hwdata(23 downto 20);
v.cfg.pmode := hwdata(18 downto 16);
v.cfg.ds(3 downto 2) := hwdata( 6 downto 5);
v.cfg.tcsr(3 downto 2) := hwdata( 4 downto 3);
v.cfg.pasr(5 downto 3) := hwdata( 2 downto 0);
end if;
end if;
end if;
-- Disable CS and DPD when Mobile SDR is Disabled
if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
-- Update EMR when ds, tcsr or pasr change
if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
end if;
if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
end if;
if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
end if;
end if;
regsd := (others => '0');
if r.haddr(3 downto 2) = "00" then
regsd(31 downto 18) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command;
if not lineburst then regsd(17) := '1'; end if;
regsd(16) := r.cfg.mobileen(1);
if BUS64 then regsd(15) := '1'; end if;
regsd(14 downto 0) := r.cfg.refresh;
elsif r.haddr(3 downto 2) = "01" then
regsd(31) := r.cfg.mobileen(0);
regsd(30) := r.cfg.cke;
regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
end if;
if (r.hsel and r.hio) = '1' then dout := regsd;
else
if BUS64 and r.bsel = '1' then dout := r.hrdata(63 downto 32);
else dout := r.hrdata(31 downto 0); end if;
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := iidle;
v.cmstate := midle;
v.hsel := '0';
v.cfg.command := "000";
v.cfg.csize := "10";
v.cfg.bsize := "000";
v.cfg.casdel := '1';
v.cfg.trfc := "111";
v.cfg.renable := '0';
v.cfg.trp := '1';
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '1';
v.bsel := '0';
v.startsd := '0';
if pwron /= 0 then v.pwron := '1'; end if;
if (pageburst = 2) then
v.cfg.pageburst := '0';
end if;
if mobile >= 2 then v.cfg.mobileen := "11";
elsif mobile = 1 then v.cfg.mobileen := "10";
else v.cfg.mobileen := "00"; end if;
v.cfg.txsr := (others => '1');
v.cfg.pmode := (others => '0');
v.cfg.ds := (others => '0');
v.cfg.tcsr := (others => '0');
v.cfg.pasr := (others => '0');
if mobile >= 2 then v.cfg.cke := '0';
else v.cfg.cke := '1'; end if;
v.sref_tmpcom := "000";
v.idlecnt := (others => '1');
v.hio := '0';
end if;
if pwron = 0 then v.pwron := '0'; end if;
if not WPROTEN then v.wprothit := '0'; end if;
ri <= v;
ribdrive <= vbdrive;
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= ahbdrivedata(dout);
end process;
--sdo.sdcke <= (others => '1');
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
driveundriven : block
begin
sdo.qdrive <= '0';
sdo.nbdrive <= '0';
sdo.ce <= '0';
sdo.moben <= '0';
sdo.cal_rst <= '0';
sdo.oct <= '0';
sdo.dqs_gate <= '0';
sdo.xsdcsn <= (others => '1');
sdo.data(127 downto sdbits) <= (others => '0');
sdo.cb <= (others => '0');
sdo.ba <= (others => '0');
sdo.sdck <= (others => '0');
sdo.cal_en <= (others => '0');
sdo.cal_inc <= (others => '0');
sdo.cal_pll <= (others => '0');
sdo.odt <= (others => '0');
sdo.conf <= (others => '0');
sdo.vcbdrive <= (others => '0');
sdo.cbdqm <= (others => '0');
sdo.cbcal_en <= (others => '0');
sdo.cbcal_inc <= (others => '0');
sdo.read_pend <= (others => '0');
sdo.regwdata <= (others => '0');
sdo.regwrite <= (others => '0');
end block driveundriven;
regs : process(clk, rst) begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive;
if rst = '0' then r.icnt <= (others => '0'); end if;
end if;
if (rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
end if;
end process;
rgen : if not SDINVCLK generate
sdo.address <= r.address;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.vbdrive <= zero32 & rbdrive;
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
drivebus: for i in 0 to sdbits/64 generate
sdo.data(31+32*i downto 32*i) <= r.hwdata;
end generate;
end generate;
ngen : if SDINVCLK generate
nregs : process(clk, rst) begin
if falling_edge(clk) then
sdo.address <= r.address;
if oepol = 1 then sdo.bdrive <= r.nbdrive;
else sdo.bdrive <= r.bdrive; end if;
sdo.vbdrive <= zero32 & rbdrive;
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
for i in 0 to sdbits/64 loop
sdo.data(31+32*i downto 32*i) <= r.hwdata;
end loop;
end if;
if rst = '0' then sdo.sdcsn <= (others => '1'); end if;
end process;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("sdctrl" & tost(hindex) &
": PC133 SDRAM controller rev " & tost(REVISION));
-- pragma translate_on
end;
| gpl-2.0 | e713a72474d2c8cb05e74708a980d4b0 | 0.524489 | 3.254064 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-xc3sd-1800/config.vhd | 1 | 7,528 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (25);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4;
constant CFG_ATBSZ : integer := 4;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#001234#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (125);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (32);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (128);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- SVGA controller
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 2422645965169ccf66faf136d657a40c | 0.65263 | 3.583056 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/eth/core/eth_ahb_mst.vhd | 1 | 5,989 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: eth_ahb_mst
-- File: eth_ahb_mst.vhd
-- Author: Marko Isomaki - Gaisler Research
-- Description: Ethernet MAC AHB master interface
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity eth_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
attribute sync_set_reset of rst : signal is "true";
end entity;
architecture rtl of eth_ahb_mst is
type reg_type is record
bg : std_ulogic; --bus granted
bo : std_ulogic; --bus owner, 0=rx, 1=tx
ba : std_ulogic; --bus active
bb : std_ulogic; --1kB burst boundary detected
retry : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process(rst, r, tmsti, rmsti, ahbmi) is
variable v : reg_type;
variable htrans : std_logic_vector(1 downto 0);
variable hbusreq : std_ulogic;
variable hwrite : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable nbo : std_ulogic;
variable tretry : std_ulogic;
variable rretry : std_ulogic;
variable rready : std_ulogic;
variable tready : std_ulogic;
variable rerror : std_ulogic;
variable terror : std_ulogic;
variable tgrant : std_ulogic;
variable rgrant : std_ulogic;
begin
v := r; htrans := HTRANS_IDLE; rready := '0'; tready := '0'; tretry := '0';
rretry := '0'; rerror := '0'; terror := '0'; tgrant := '0'; rgrant := '0';
if r.bo = '0' then hwdata := rmsti.data;
else hwdata := tmsti.data; end if;
hbusreq := tmsti.req or rmsti.req;
if hbusreq = '1' then htrans := HTRANS_NONSEQ; end if;
if r.retry = '0' then
nbo := tmsti.req and not (rmsti.req and not r.bo);
else
nbo := r.bo;
end if;
if nbo = '0' then
haddr := rmsti.addr; hwrite := rmsti.write;
if (rmsti.req and r.ba and not r.bo and not r.retry) = '1' then
htrans := HTRANS_SEQ;
end if;
if (rmsti.req and r.bg and ahbmi.hready and not r.retry) = '1'
then rgrant := '1'; end if;
else
haddr := tmsti.addr; hwrite := tmsti.write;
if (tmsti.req and r.ba and r.bo and not r.retry) = '1' then
htrans := HTRANS_SEQ;
end if;
if (tmsti.req and r.bg and ahbmi.hready and not r.retry) = '1'
then tgrant := '1'; end if;
end if;
--1 kB burst boundary
if ahbmi.hready = '1' then
if haddr(9 downto 2) = "11111111" then
v.bb := '1';
else
v.bb := '0';
end if;
end if;
if (r.bb = '1') and (htrans /= HTRANS_IDLE) then
htrans := HTRANS_NONSEQ;
end if;
if r.bo = '0' then
if r.ba = '1' then
if ahbmi.hready = '1' then
case ahbmi.hresp is
when HRESP_OKAY => rready := '1';
when HRESP_SPLIT | HRESP_RETRY => rretry := '1';
when HRESP_ERROR => rerror := '1';
when others => null;
end case;
end if;
end if;
else
if r.ba = '1' then
if ahbmi.hready = '1' then
case ahbmi.hresp is
when HRESP_OKAY => tready := '1';
when HRESP_SPLIT | HRESP_RETRY => tretry := '1';
when HRESP_ERROR => terror := '1';
when others => null;
end case;
end if;
end if;
end if;
if (r.ba = '1') and
((ahbmi.hresp = HRESP_RETRY) or (ahbmi.hresp = HRESP_SPLIT))
then v.retry := not ahbmi.hready; else v.retry := '0'; end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
if ahbmi.hready = '1' then
v.bo := nbo; v.bg := ahbmi.hgrant;
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else
v.ba := '0';
end if;
end if;
if rst = '0' then
v.bg := '0'; v.ba := '0'; v.bo := '0'; v.bb := '0';
end if;
rin <= v;
tmsto.data <= ahbmi.hrdata;
rmsto.data <= ahbmi.hrdata;
tmsto.error <= terror;
tmsto.retry <= tretry;
tmsto.ready <= tready;
rmsto.error <= rerror;
rmsto.retry <= rretry;
rmsto.ready <= rready;
tmsto.grant <= tgrant;
rmsto.grant <= rgrant;
ahbmo.htrans <= htrans;
ahbmo.hbusreq <= hbusreq;
ahbmo.haddr <= haddr;
ahbmo.hwrite <= hwrite;
ahbmo.hwdata <= hwdata;
end process;
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
ahbmo.hlock <= '0';
ahbmo.hsize <= HSIZE_WORD;
ahbmo.hburst <= HBURST_INCR;
ahbmo.hprot <= "0011";
end architecture;
| gpl-2.0 | 4ddde1d635e9d4235c9d855e328ed418 | 0.55819 | 3.53125 | false | false | false | false |
eamadio/fpgaMSP430 | fmsp430/core/fmsp_mem_backbone.vhd | 1 | 20,747 |
------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_mem_backbone.vhd
--!
--! @brief fpgaMSP430 Memory interface backbone (decoder + arbiter)
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; --! for the signed, unsigned types and arithmetic ops
use work.fmsp_core_package.all;
use work.fmsp_functions.all;
entity fmsp_mem_backbone is
generic (
PMEM_SIZE : integer := 32768; --! Program Memory Size
DMEM_SIZE : integer := 16384; --! Data Memory Size
PER_SIZE : integer := 16384; --! Peripheral Memory Size
DMA_IF_EN : boolean := false --! Wakeup condition from DMA interface
);
port (
mclk : in std_logic; --! Main system clock
mrst : in std_logic; --! Main system reset
--! INPUTs
cpu_halt_st : in std_logic; --! Halt/Run status from CPU
dbg_halt_cmd : in std_logic; --! Debug interface Halt CPU command
dbg_mem_addr : in std_logic_vector(15 downto 0); --! Debug address for rd/wr access
dbg_mem_dout : in std_logic_vector(15 downto 0); --! Debug unit data output
dbg_mem_en : in std_logic; --! Debug unit memory enable
dbg_mem_wr : in std_logic_vector(1 downto 0); --! Debug unit memory write
dmem_dout : in std_logic_vector(15 downto 0); --! Data Memory data output
eu_mab : in std_logic_vector(14 downto 0); --! Execution Unit Memory address bus
eu_mb_en : in std_logic; --! Execution Unit Memory bus enable
eu_mb_wr : in std_logic_vector(1 downto 0); --! Execution Unit Memory bus write transfer
eu_mdb_out : in std_logic_vector(15 downto 0); --! Execution Unit Memory data bus output
fe_mab : in std_logic_vector(14 downto 0); --! Frontend Memory address bus
fe_mb_en : in std_logic; --! Frontend Memory bus enable
dma_addr : in std_logic_vector(15 downto 0); --! Direct Memory Access address
dma_din : in std_logic_vector(15 downto 0); --! Direct Memory Access data input
dma_en : in std_logic; --! Direct Memory Access enable (high active)
dma_priority : in std_logic; --! Direct Memory Access priority (0:low / 1:high)
dma_we : in std_logic_vector(1 downto 0); --! Direct Memory Access write byte enable (high active)
per_dout : in std_logic_vector(15 downto 0); --! Peripheral data output
pmem_dout : in std_logic_vector(15 downto 0); --! Program Memory data output
--! OUTPUTs
cpu_halt_cmd : out std_logic; --! Halt CPU command
dbg_mem_din : out std_logic_vector(15 downto 0); --! Debug unit Memory data input
dmem_addr : out std_logic_vector(f_log2(DMEM_SIZE)-2 downto 0); --! Data Memory address
dmem_cen : out std_logic; --! Data Memory chip enable (low active)
dmem_din : out std_logic_vector(15 downto 0); --! Data Memory data input
dmem_wen : out std_logic_vector(1 downto 0); --! Data Memory write enable (low active)
eu_mdb_in : out std_logic_vector(15 downto 0); --! Execution Unit Memory data bus input
fe_mdb_in : out std_logic_vector(15 downto 0); --! Frontend Memory data bus input
fe_pmem_wait : out std_logic; --! Frontend wait for Instruction fetch
dma_dout : out std_logic_vector(15 downto 0); --! Direct Memory Access data output
dma_ready : out std_logic; --! Direct Memory Access is complete
dma_resp : out std_logic; --! Direct Memory Access response (0:Okay / 1:Error)
per_addr : out std_logic_vector(13 downto 0); --! Peripheral address
per_din : out std_logic_vector(15 downto 0); --! Peripheral data input
per_we : out std_logic_vector(1 downto 0); --! Peripheral write enable (high active)
per_en : out std_logic; --! Peripheral enable (high active)
pmem_addr : out std_logic_vector(f_log2(PMEM_SIZE)-2 downto 0); --! Program Memory address
pmem_cen : out std_logic; --! Program Memory chip enable (low active)
pmem_din : out std_logic_vector(15 downto 0); --! Program Memory data input (optional)
pmem_wen : out std_logic_vector(1 downto 0) --! Program Memory write enable (low active) (optional)
);
end entity fmsp_mem_backbone;
architecture RTL of fmsp_mem_backbone is
--! Data Memory Base Adresses
constant DMEM_BASE :integer := PER_SIZE;
--! Program & Data Memory most significant address bit (for 16 bit words)
constant PMEM_MSB :integer := (f_log2(PMEM_SIZE)-2);
constant DMEM_MSB :integer := (f_log2(DMEM_SIZE)-2);
constant PER_MSB :integer := (f_log2(PER_SIZE)-2);
constant DMEM_END :integer := (DMEM_BASE + DMEM_SIZE);
constant PMEM_OFFSET :integer := (65535 - PMEM_SIZE + 1);
signal w_eu_dmem_cen : std_logic;
signal w_cpu_halt_cmd : std_logic;
signal w_dma_resp : std_logic;
signal w_dma_ready : std_logic;
signal r_dma_ready_dly : std_logic;
signal w_ext_mem_en : std_logic;
signal w_ext_mem_wr : std_logic_vector(1 downto 0);
signal w_ext_mem_addr : std_logic_vector(15 downto 0);
signal w_ext_mem_dout : std_logic_vector(15 downto 0);
signal w_dbg_mem_din : std_logic_vector(15 downto 0);
signal w_dma_dout : std_logic_vector(15 downto 0);
signal w_eu_dmem_sel : std_logic;
signal w_eu_dmem_en : std_logic;
signal w_eu_dmem_addr : std_logic_vector(15 downto 0);
signal w_ext_dmem_sel : std_logic;
signal w_ext_dmem_en : std_logic;
signal w_ext_dmem_addr : std_logic_vector(15 downto 0);
signal w_dmem_cen : std_logic;
signal w_dmem_wen : std_logic_vector(1 downto 0);
signal w_dmem_addr : std_logic_vector(DMEM_MSB downto 0);
signal w_dmem_din : std_logic_vector(15 downto 0);
signal w_eu_pmem_sel : std_logic;
signal w_eu_pmem_en : std_logic;
signal w_eu_pmem_addr : std_logic_vector(15 downto 0);
signal w_fe_pmem_sel : std_logic;
signal w_fe_pmem_en : std_logic;
signal w_fe_pmem_addr : std_logic_vector(15 downto 0);
signal w_ext_pmem_sel : std_logic;
signal w_ext_pmem_en : std_logic;
signal w_ext_pmem_addr : std_logic_vector(15 downto 0);
signal w_pmem_cen : std_logic;
signal w_pmem_wen : std_logic_vector(1 downto 0);
signal w_pmem_addr : std_logic_vector(PMEM_MSB downto 0);
signal w_pmem_din : std_logic_vector(15 downto 0);
signal w_fe_pmem_wait : std_logic;
signal w_eu_per_sel : std_logic;
signal w_eu_per_en : std_logic;
signal w_ext_per_sel : std_logic;
signal w_ext_per_en : std_logic;
signal w_per_en : std_logic;
signal w_per_we : std_logic_vector(1 downto 0);
signal w_per_addr_mux : std_logic_vector(PER_MSB downto 0);
signal w_per_addr_ful : std_logic_vector(14 downto 0);
signal w_per_addr : std_logic_vector(13 downto 0);
signal w_per_din : std_logic_vector(15 downto 0);
signal r_per_dout_val : std_logic_vector(15 downto 0);
signal w_fe_pmem_en_dly : std_logic;
signal w_fe_pmem_save : std_logic;
signal w_fe_pmem_restore : std_logic;
signal w_pmem_dout_bckup : std_logic_vector(15 downto 0);
signal w_pmem_dout_bckup_sel: std_logic;
signal w_fe_mdb_in : std_logic_vector(15 downto 0);
signal w_eu_mdb_in_sel : std_logic_vector(1 downto 0);
signal w_eu_mdb_in : std_logic_vector(15 downto 0);
signal w_ext_mem_din_sel : std_logic_vector(1 downto 0);
signal w_ext_mem_din : std_logic_vector(15 downto 0);
--! Register peripheral data read path
signal r_fe_pmem_en_dly : std_logic;
signal r_pmem_dout_bckup : std_logic_vector(15 downto 0);
signal r_pmem_dout_bckup_sel : std_logic;
signal r_eu_mdb_in_sel : std_logic_vector(1 downto 0);
signal r_ext_mem_din_sel : std_logic_vector(1 downto 0);
begin
--=============================================================================
--! 1) DECODER
--=============================================================================
COMB : process(all)
begin
--------------------------------------------
--! Arbiter between DMA and Debug interface
--------------------------------------------
if (DMA_IF_EN = true) then
--! Debug-interface always stops the CPU
--! Master interface stops the CPU in priority mode
w_cpu_halt_cmd <= dbg_halt_cmd or (dma_en and dma_priority);
--! Return ERROR response if address lays outside the memory spaces (Peripheral, Data and Program memories)
w_dma_resp <= not(dbg_mem_en) and not(w_ext_dmem_sel or w_ext_pmem_sel or w_ext_per_sel) and dma_en;
--! Master interface access is ready when the memory access occures
w_dma_ready <= not(dbg_mem_en) and (w_ext_dmem_en or w_ext_pmem_en or w_ext_per_en or dma_resp);
--! Use delayed version of 'dma_ready' to mask the 'dma_dout' data output
--! when not accessed and reduce toggle rate (thus power consumption)
--! Mux between debug and master interface
w_ext_mem_en <= dbg_mem_en or dma_en;
if (dbg_mem_en = '1') then
w_ext_mem_wr <= dbg_mem_wr;
w_ext_mem_addr <= dbg_mem_addr;
w_ext_mem_dout <= dbg_mem_dout;
else
w_ext_mem_wr <= dma_we;
w_ext_mem_addr <= dma_addr;
w_ext_mem_dout <= dma_din;
end if;
--! External interface read data
w_dbg_mem_din <= w_ext_mem_din;
if (r_dma_ready_dly = '1') then
w_dma_dout <= w_ext_mem_din;
else
w_dma_dout <= x"0000";
end if;
else
--! Debug-interface always stops the CPU
w_cpu_halt_cmd <= dbg_halt_cmd;
--! Master interface access is always ready with error response when excluded
w_dma_resp <= '1';
w_dma_ready <= '1';
--! Debug interface only
w_ext_mem_en <= dbg_mem_en;
w_ext_mem_wr <= dbg_mem_wr;
w_ext_mem_addr <= dbg_mem_addr;
w_ext_mem_dout <= dbg_mem_dout;
--! External interface read data
w_dbg_mem_din <= w_ext_mem_din;
w_dma_dout <= x"0000";
end if;
--------------------------------------------
--! DATA-MEMORY Interface
--------------------------------------------
--! Execution unit access
--w_eu_dmem_sel <= (eu_mab>=(`DMEM_BASE>>1)) and (eu_mab< ( DMEM_END >>1));
if ( ( UNSIGNED(eu_mab) >= TO_UNSIGNED((DMEM_BASE/2),15) ) and
( UNSIGNED(eu_mab) < TO_UNSIGNED((DMEM_END/2),15) ) ) then
w_eu_dmem_sel <= '1';
else
w_eu_dmem_sel <= '0';
end if;
w_eu_dmem_en <= eu_mb_en and w_eu_dmem_sel;
w_eu_dmem_addr <= STD_LOGIC_VECTOR( (UNSIGNED(eu_mab)/2) - TO_UNSIGNED((DMEM_BASE/2),16) );
--! Front-end access
--! --! not allowed to execute from data memory --
--! External Master/Debug interface access
--w_ext_dmem_sel <= (ext_mem_addr[15:1]>=(`DMEM_BASE>>1)) an (ext_mem_addr[15:1]< ( DMEM_END >>1));
if ( ( UNSIGNED(w_ext_mem_addr(15 downto 1)) >= TO_UNSIGNED((DMEM_BASE/2),15) ) and
( UNSIGNED(w_ext_mem_addr(15 downto 1)) < TO_UNSIGNED((DMEM_END/2),15) ) ) then
w_ext_dmem_sel <= '1';
else
w_ext_dmem_sel <= '0';
end if;
w_ext_dmem_en <= w_ext_mem_en and w_ext_dmem_sel and not(w_eu_dmem_en);
--w_ext_dmem_addr<= {1'b0, ext_mem_addr[15:1]}-(`DMEM_BASE>>1);
w_ext_dmem_addr <= STD_LOGIC_VECTOR( (UNSIGNED(w_ext_mem_addr)/2) - TO_UNSIGNED((DMEM_BASE/2),16) );
--! Data-Memory Interface
w_dmem_cen <= not(w_ext_dmem_en or w_eu_dmem_en);
if (w_ext_dmem_en = '1') then
w_dmem_wen <= not(w_ext_mem_wr);
w_dmem_addr <= w_ext_dmem_addr(DMEM_MSB downto 0);
w_dmem_din <= w_ext_mem_dout;
else
w_dmem_wen <= not(eu_mb_wr);
w_dmem_addr <= w_eu_dmem_addr(DMEM_MSB downto 0);
w_dmem_din <= eu_mdb_out;
end if;
--------------------------------------------
--! PROGRAM-MEMORY Interface
--------------------------------------------
--! Execution unit access (only read access are accepted)
--w_eu_pmem_sel <= (eu_mab>=(PMEM_OFFSET>>1));
if ( UNSIGNED(eu_mab) >= TO_UNSIGNED((PMEM_OFFSET/2),15) ) then
w_eu_pmem_sel <= '1';
else
w_eu_pmem_sel <= '0';
end if;
w_eu_pmem_en <= eu_mb_en and not(eu_mb_wr(1) or eu_mb_wr(0)) and w_eu_pmem_sel;
--w_eu_pmem_addr <= eu_mab-(PMEM_OFFSET>>1);
w_eu_pmem_addr <= STD_LOGIC_VECTOR( UNSIGNED(eu_mab) - TO_UNSIGNED((PMEM_OFFSET/2),16) );
--! Front-end access
--w_fe_pmem_sel <= (fe_mab>=(PMEM_OFFSET>>1));
if ( UNSIGNED(fe_mab) >= TO_UNSIGNED((PMEM_OFFSET/2),15) ) then
w_fe_pmem_sel <= '1';
else
w_fe_pmem_sel <= '0';
end if;
w_fe_pmem_en <= fe_mb_en and w_fe_pmem_sel;
--w_fe_pmem_addr <= fe_mab-(PMEM_OFFSET>>1);
w_fe_pmem_addr <= STD_LOGIC_VECTOR( UNSIGNED(fe_mab) - TO_UNSIGNED((PMEM_OFFSET/2),16) );
--! External Master/Debug interface access
--w_ext_pmem_sel <= (ext_mem_addr[15:1]>=(PMEM_OFFSET>>1));
if ( UNSIGNED(w_ext_mem_addr(15 downto 1)) >= TO_UNSIGNED((PMEM_OFFSET/2),15) ) then
w_ext_pmem_sel <= '1';
else
w_ext_pmem_sel <= '0';
end if;
w_ext_pmem_en <= w_ext_mem_en and w_ext_pmem_sel and not(w_eu_pmem_en) and not(w_fe_pmem_en);
--w_ext_pmem_addr <= {1'b0, ext_mem_addr[15:1]}-(PMEM_OFFSET>>1);
w_ext_pmem_addr <= STD_LOGIC_VECTOR( UNSIGNED(w_ext_mem_addr(15 downto 1)) - TO_UNSIGNED((PMEM_OFFSET/2),16) );
--! Program-Memory Interface (Execution unit has priority over the Front-end)
w_pmem_cen <= not(w_fe_pmem_en or w_eu_pmem_en or w_ext_pmem_en);
if (w_ext_pmem_en = '1') then
w_pmem_wen <= not(w_ext_mem_wr);
else
w_pmem_wen <= "11";
end if;
if (w_ext_pmem_en = '1') then
w_pmem_addr <= w_ext_pmem_addr(PMEM_MSB downto 0);
elsif (w_eu_pmem_en = '1') then
w_pmem_addr <= w_eu_pmem_addr(PMEM_MSB downto 0);
else
w_pmem_addr <= w_fe_pmem_addr(PMEM_MSB downto 0);
end if;
w_pmem_din <= w_ext_mem_dout;
w_fe_pmem_wait <= w_fe_pmem_en and w_eu_pmem_en;
--------------------------------------------
--! PERIPHERALS Interface
--------------------------------------------
--! Execution unit access
--w_eu_per_sel <= (eu_mab<(`PER_SIZE>>1));
if ( UNSIGNED(eu_mab) < TO_UNSIGNED((PER_SIZE/2),15) ) then
w_eu_per_sel <= '1';
else
w_eu_per_sel <= '0';
end if;
w_eu_per_en <= eu_mb_en and w_eu_per_sel;
--! Front-end access
--! --! not allowed to execute from peripherals memory space --
--! External Master/Debug interface access
--w_ext_per_sel <= (ext_mem_addr[15:1]<(`PER_SIZE>>1));
if ( UNSIGNED(w_ext_mem_addr(15 downto 1)) < TO_UNSIGNED((PER_SIZE/2),15) ) then
w_ext_per_sel <= '1';
else
w_ext_per_sel <= '0';
end if;
w_ext_per_en <= w_ext_mem_en and w_ext_per_sel and not(w_eu_per_en);
--! Peripheral Interface
w_per_en <= w_ext_per_en or w_eu_per_en;
if (w_ext_per_en = '1') then
w_per_we <= w_ext_mem_wr;
w_per_addr_mux <= w_ext_mem_addr(PER_MSB+1 downto 1);
w_per_din <= w_ext_mem_dout;
else
w_per_we <= eu_mb_wr;
w_per_addr_mux <= eu_mab(PER_MSB downto 0);
w_per_din <= eu_mdb_out;
end if;
--w_per_addr_ful <= {{15-`PER_AWIDTH{1'b0}}, per_addr_mux};
w_per_addr_ful <= STD_LOGIC_VECTOR( resize( UNSIGNED(w_per_addr_mux), 15) );
w_per_addr <= w_per_addr_ful(13 downto 0);
--------------------------------------------
--! Frontend data Mux
--------------------------------------------
--! Whenever the frontend doesn't access the program memory, backup the data
--! Detect whenever the data should be backuped and restored
w_fe_pmem_save <= (not(w_fe_pmem_en) and r_fe_pmem_en_dly) and not(cpu_halt_st);
w_fe_pmem_restore<= ( w_fe_pmem_en and not(r_fe_pmem_en_dly)) or cpu_halt_st;
--! Mux between the Program memory data and the backup
if (r_pmem_dout_bckup_sel = '1') then
w_fe_mdb_in <= r_pmem_dout_bckup;
else
w_fe_mdb_in <= pmem_dout;
end if;
--------------------------------------------
--! Execution-Unit data Mux
--------------------------------------------
--! Select between Peripherals, Program and Data memories
--! Mux
if (r_eu_mdb_in_sel(1) = '1') then
w_eu_mdb_in <= pmem_dout;
elsif (r_eu_mdb_in_sel(0) = '1') then
w_eu_mdb_in <= r_per_dout_val;
else
w_eu_mdb_in <= dmem_dout;
end if;
--------------------------------------------
--! External Master/Debug interface data Mux
--------------------------------------------
--! Select between Peripherals, Program and Data memories
--! Mux
if (r_ext_mem_din_sel(1) = '1') then
w_ext_mem_din <= pmem_dout;
elsif (r_ext_mem_din_sel(0) = '1') then
w_ext_mem_din <= r_per_dout_val;
else
w_ext_mem_din <= dmem_dout;
end if;
end process COMB;
REGS : process (mclk, mrst)
begin
if (mrst = '1') then
r_dma_ready_dly <= '0';
r_per_dout_val <= x"0000";
r_fe_pmem_en_dly <= '0';
r_pmem_dout_bckup_sel <= '0';
r_pmem_dout_bckup <= x"0000";
r_eu_mdb_in_sel <= "00";
r_ext_mem_din_sel <= "00";
elsif rising_edge(mclk) then
--! Use delayed version of 'dma_ready' to mask the 'dma_dout' data output
--! when not accessed and reduce toggle rate (thus power consumption)
r_dma_ready_dly <= dma_ready;
--! Register peripheral data read path
r_per_dout_val <= per_dout;
--! Detect whenever the data should be backuped and restored
r_fe_pmem_en_dly <= w_fe_pmem_en;
--! Mux between the Program memory data and the backup
if (w_fe_pmem_save = '1') then
r_pmem_dout_bckup_sel <= '1';
elsif (w_fe_pmem_restore = '1') then
r_pmem_dout_bckup_sel <= '0';
end if;
if (w_fe_pmem_save = '1') then
r_pmem_dout_bckup <= pmem_dout;
end if;
--! Select between Peripherals, Program and Data memories
r_eu_mdb_in_sel <= w_eu_pmem_en & w_eu_per_en;
r_ext_mem_din_sel <= w_ext_pmem_en & w_ext_per_en;
end if;
end process REGS;
cpu_halt_cmd <= w_cpu_halt_cmd; --! Halt CPU command
dbg_mem_din <= w_dbg_mem_din; --! Debug unit Memory data input
dmem_addr <= w_dmem_addr; --! Data Memory address
dmem_cen <= w_dmem_cen; --! Data Memory chip enable (low active)
dmem_din <= w_dmem_din; --! Data Memory data input
dmem_wen <= w_dmem_wen; --! Data Memory write enable (low active)
eu_mdb_in <= w_eu_mdb_in; --! Execution Unit Memory data bus input
fe_mdb_in <= w_fe_mdb_in; --! Frontend Memory data bus input
fe_pmem_wait <= w_fe_pmem_wait; --! Frontend wait for Instruction fetch
dma_dout <= w_dma_dout; --! Direct Memory Access data output
dma_ready <= w_dma_ready; --! Direct Memory Access is complete
dma_resp <= w_dma_resp; --! Direct Memory Access response (0:Okay / 1:Error)
per_addr <= w_per_addr; --! Peripheral address
per_din <= w_per_din; --! Peripheral data input
per_we <= w_per_we; --! Peripheral write enable (high active)
per_en <= w_per_en; --! Peripheral enable (high active)
pmem_addr <= w_pmem_addr; --! Program Memory address
pmem_cen <= w_pmem_cen; --! Program Memory chip enable (low active)
pmem_din <= w_pmem_din; --! Program Memory data input (optional)
pmem_wen <= w_pmem_wen; --! Program Memory write enable (low active) (optional)
end RTL; --! fmsp_mem_backbone | bsd-3-clause | 6e4be5ab48427364172e53471a0d79a4 | 0.608859 | 2.787451 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-4/src/JC.vhd | 1 | 721 | library ieee;
use ieee.std_logic_1164.all;
entity JC is
generic (n:integer := 2);
port(
CLK: in std_logic;
RST: in std_logic;
LS: in std_logic;
Pin: in std_logic_vector(0 to 2**n-1);
Pout: out std_logic_vector(0 to 2**n-1)
);
end JC;
architecture behavior of JC is
signal sreg: std_logic_vector(0 to 2**n-1);
signal sdat: std_logic_vector(0 to 2**n-1);
Begin
Main: process (CLK, RST, sdat)
begin
if RST = '1' then
sreg <= (others => '0');
elsif rising_edge(CLK) then
sreg <= sdat;
end if;
end process;
Data: process (LS, Pin, sreg)
begin
if LS = '0' then
sdat <= Pin;
else
sdat <= not(sreg(2**n-1)) & sreg(0 to 2**n-2);
end if;
end process;
Pout <= sreg;
End behavior; | mit | 6e4b8519817401e1bd82fd452b2cafed | 0.615811 | 2.477663 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/grlib/amba/dma2ahb_pkg.vhd | 1 | 6,000 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : DMA2AHB_Package (package declaration)
--
-- File name : dma2ahb_pkg.vhd
--
-- Purpose : Interface package for AMBA AHB master interface with DMA input
--
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
-- The document can be retrieved from http://www.arm.com
-- AMBA is a trademark of ARM Limited.
-- ARM is a registered trademark of ARM Limited.
--
-- Note : Naming convention according to AMBA(TM) Specification:
-- Signal names are in upper case, except for the following:
-- A lower case 'n' in the name indicates that the signal
-- is active low.
-- Constant names are in upper case.
-- The least significant bit of an array is located to the right,
-- carrying the index number zero.
--
-- Limitations : See DMA2AHB VHDL core
--
-- Library : gaisler
--
-- Authors : Aeroflex Gaisler AB
--
-- Contact : mailto:[email protected]
-- http://www.gaisler.com
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 1.4 SH 1 Jul 2005 Support for fixed length incrementing bursts
-- Support for record types
-- 1.5 SH 1 Sep 2005 New library gaisler
-- 1.6 SH 20 Sep 2005 Added transparent HSIZE support
-- 1.7 SH 6 Dec 2007 Added syncrst generic
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package DMA2AHB_Package is
-----------------------------------------------------------------------------
-- Direct Memory Access to AMBA AHB Master Interface Types
-----------------------------------------------------------------------------
type DMA_In_Type is record
Reset: Std_Logic;
Address: Std_Logic_Vector(32-1 downto 0);
Data: Std_Logic_Vector(32-1 downto 0);
Request: Std_Logic; -- access requested
Burst: Std_Logic; -- burst requested
Beat: Std_Logic_Vector(1 downto 0); -- incrementing beat
Size: Std_Logic_Vector(1 downto 0); -- size
Store: Std_Logic; -- data write requested
Lock: Std_Logic; -- locked Transfer
end record;
type DMA_Out_Type is record
Grant: Std_Logic; -- access accepted
OKAY: Std_Logic; -- write access ready
Ready: Std_Logic; -- read data ready
Retry: Std_Logic; -- retry
Fault: Std_Logic; -- error occured
Data: Std_Logic_Vector(32-1 downto 0);
end record;
-- constants for HBURST definition (used with dma_in_type.Beat)
constant HINCR: Std_Logic_Vector(1 downto 0) := "00";
constant HINCR4: Std_Logic_Vector(1 downto 0) := "01";
constant HINCR8: Std_Logic_Vector(1 downto 0) := "10";
constant HINCR16: Std_Logic_Vector(1 downto 0) := "11";
-- constants for HSIZE definition (used with dma_in_type.Size)
constant HSIZE8: Std_Logic_Vector(1 downto 0) := "00";
constant HSIZE16: Std_Logic_Vector(1 downto 0) := "01";
constant HSIZE32: Std_Logic_Vector(1 downto 0) := "10";
-----------------------------------------------------------------------------
-- Direct Memory Access to AMBA AHB Master Interface
-----------------------------------------------------------------------------
component DMA2AHB is
generic(
hindex: in Integer := 0;
vendorid: in Integer := 0;
deviceid: in Integer := 0;
version: in Integer := 0;
syncrst: in Integer := 1;
boundary: in Integer := 1);
port(
-- AMBA AHB system signals
HCLK: in Std_ULogic;
HRESETn: in Std_ULogic;
-- Direct Memory Access Interface
DMAIn: in DMA_In_Type;
DMAOut: out DMA_OUt_Type;
-- AMBA AHB Master Interface
AHBIn: in AHB_Mst_In_Type;
AHBOut: out AHB_Mst_Out_Type);
end component DMA2AHB;
end package DMA2AHB_Package; --===============================================--
| gpl-2.0 | 503ded4cfad89787c29bdf871bceaa2d | 0.501833 | 4.716981 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-jopdesign-ep1c12/leon3mp.vhd | 1 | 31,579 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(7 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
emddis : out std_logic;
epwrdwn : out std_logic;
ereset : out std_logic;
esleep : out std_logic;
epause : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic;
can_rxd : in std_logic;
can_stb : out std_logic;
spw_clk : in std_logic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2)
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbmsp : integer := NCPU+CFG_AHB_UART+
CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI);
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_logic;
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal tck, tms, tdi, tdo : std_logic;
signal spwi : grspw_in_type_vector(0 to 2);
signal spwo : grspw_out_type_vector(0 to 2);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
constant BOARD_FREQ : integer := 20000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;
constant IOAEN : integer := CFG_SDCTRL + CFG_CAN;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant CFG_INVCLK : integer := CFG_SDCTRL_INVCLK + CFG_MCTRL_INVCLK;
constant sysfreq : integer := (CFG_CLKMUL/CFG_CLKDIV)*20000;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= '0';
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_CLK_NOFB, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo3);
apbo(0) <= apb_none;
end generate;
sdc : if CFG_SDCTRL = 1 generate
sdc : sdctrl generic map (hindex => 3, haddr => 16#600#, hmask => 16#F00#,
ioaddr => 1, fast => 0, pwron => 0, invclk => CFG_SDCTRL_INVCLK,
sdbits => 32 + 32*CFG_SDCTRL_SD64)
port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo2);
sa_pad : outpadv generic map (width => 15, tech => padtech)
port map (sa, sdo2.address);
sd_pad : iopadv generic map (width => 32, tech => padtech)
port map (sd(31 downto 0), sdo2.data, sdo2.bdrive, sdi.data(31 downto 0));
sd2 : if CFG_SDCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (width => 32)
port map (sd(63 downto 32), sdo2.data, sdo2.bdrive, sdi.data(63 downto 32));
end generate;
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo2.sdcke);
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo2.sdwen);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo2.sdcsn);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo2.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo2.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo2.dqm);
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) and (CFG_SDCTRL = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 8, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(8));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(8) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 8)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
pio_pads : for i in 0 to 7 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
apbi, apbo(4), ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(8));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 10, paddr => 10,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(10)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech) -- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
nop1 : if CFG_PCI <= 1 generate apbo(4) <= apb_none; end generate;
nop2 : if CFG_PCI <= 2 generate apbo(5) <= apb_none; end generate;
nop3 : if CFG_PCI <= 1 generate ahbso(4) <= ahbs_none; end generate;
notrc : if CFG_PCITBUFEN = 0 generate apbo(8) <= apb_none; end generate;
noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
emdis_pad : outpad generic map (tech => padtech)
port map (emddis, vcc(0));
eepwrdwn_pad : outpad generic map (tech => padtech)
port map (epwrdwn, gnd(0));
esleep_pad : outpad generic map (tech => padtech)
port map (esleep, gnd(0));
epause_pad : outpad generic map (tech => padtech)
port map (epause, gnd(0));
ereset_pad : outpad generic map (tech => padtech)
port map (ereset, gnd(0));
end generate;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FFF#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
can_stb <= '0'; -- no standby
can_loopback : if CFG_CANLOOP = 1 generate
can_lrx <= can_ltx;
end generate;
can_pads : if CFG_CANLOOP = 0 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd, can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd, can_lrx);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_lclk);
spw_rxtxclk <= spw_lclk;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i,
sysfreq => sysfreq, nsync => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC, rmapbufs => CFG_SPW_RMAPBUF,
fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO,
rxclkbuftype => 1, ports => 1, dmachan => CFG_SPW_DMACHAN,
spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME)
port map(resetn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi, ahbmo(maxahbmsp+i),
apbi, apbo(12+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(sysfreq/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxd(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxs(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in maxahbm to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_PCI-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 12+(CFG_SPW_NUM*CFG_SPW_EN) to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-- nah0 : for i in 9 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 MP Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | fe3c8d4d6010e036889328a4e2ad5665 | 0.559802 | 3.460333 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/tech/stratixiii/simprims/stratixiii_components.vhd | 2 | 106,590 | -- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 9.0 Build 235 03/01/2009
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiii_atom_pack.all;
package STRATIXIII_COMPONENTS is
--
-- stratixiii_ff
--
component stratixiii_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "stratixiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--
-- STRATIXIII_CLKSELECT Model
--
component stratixiii_clkselect
generic (
lpm_type : STRING := "stratixiii_clkselect";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
outclk : out std_logic
);
end component;
--
-- STRATIXIII_CLKENA
--
component stratixiii_clkena
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixiii_clkena";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
enaout : out std_logic;
outclk : out std_logic
);
end component;
--
-- STRATIXIII_MLAB_CELL
--
component stratixiii_mlab_cell
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
logical_ram_name : STRING := "lutram";
init_file : STRING := "UNUSED";
data_interleave_offset_in_bits : INTEGER := 1;
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
data_width : INTEGER := 1;
address_width : INTEGER := 1;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
lpm_type : string := "stratixiii_mlab_cell";
lpm_hint : string := "true";
mixed_port_feed_through_mode : string := "dont_care";
mem_init0 : BIT_VECTOR := X"0";
-- --------- VITAL PARAMETERS --------
tipd_clk0 : VitalDelayType01 := DefPropDelay01;
tipd_ena0 : VitalDelayType01 := DefPropDelay01;
tipd_portaaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portbaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portabyteenamasks : VitalDelayArrayType01(20 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
clk0 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
end component;
--
-- STRATIXIII_IO_IBUF
--
COMPONENT stratixiii_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "stratixiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- STRATIXIII_IO_OBUF
--
COMPONENT stratixiii_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
sim_dynamic_termination_control_is_connected : string := "false";
bus_hold : string := "false";
lpm_type : string := "stratixiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
dynamicterminationcontrol : IN std_logic := '0';
seriesterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
parallelterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- STRATIXIII_DDIO_IN
--
COMPONENT stratixiii_ddio_in
generic(
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkn : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_clkn : string := "false";
lpm_type : string := "stratixiii_ddio_in"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
clkn : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
regoutlo : OUT std_logic;
regouthi : OUT std_logic;
dfflo : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- STRATIXIII_DDIO_OE
--
COMPONENT stratixiii_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "stratixiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- STRATIXIII_DDIO_OUT
--
COMPONENT stratixiii_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic_vector(1 downto 0) ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiii_termination Model
--
COMPONENT stratixiii_termination
GENERIC (
runtime_control : STRING := "false";
allow_serial_data_from_core : STRING := "false";
power_down : STRING := "true";
enable_parallel_termination : STRING := "false";
test_mode : STRING := "false";
enable_calclk_divider : STRING := "false"; -- replaced by below
clock_divider_enable : STRING := "false";
enable_pwrupmode_enser_for_usrmode : STRING := "false";
bypass_enser_logic : STRING := "false";
bypass_rt_calclk : STRING := "false";
enable_rt_scan_mode : STRING := "false";
enable_loopback : STRING := "false";
force_rtcalen_for_pllbiasen : STRING := "false";
enable_rt_sm_loopback : STRING := "false";
select_vrefl_values : integer := 0;
select_vrefh_values : integer := 0;
divide_intosc_by : integer := 2;
use_usrmode_clear_for_configmode : STRING := "false";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_serializerenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationcontrolin : VitalDelayType01 := DefpropDelay01;
tipd_otherserializerenable : VitalDelayArrayType01(8 downto 0) := (OTHERS => DefPropDelay01);
lpm_type : STRING := "stratixiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
serializerenable : IN std_logic := '0';
terminationcontrolin : IN std_logic := '0';
scanin : IN std_logic := '0';
scanen : IN std_logic := '0';
otherserializerenable : IN std_logic_vector(8 DOWNTO 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
incrup : OUT std_logic;
incrdn : OUT std_logic;
serializerenableout : OUT std_logic;
terminationcontrol : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
scanout : OUT std_logic;
shiftregisterprobe : OUT std_logic);
END COMPONENT;
--
-- stratixiii_termination_logic Model
--
COMPONENT stratixiii_termination_logic
GENERIC (
tipd_serialloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_parallelloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationdata : VitalDelayType01 := DefpropDelay01;
test_mode : string := "false";
lpm_type : string := "stratixiii_termination_logic");
PORT (
serialloadenable : IN std_logic := '0';
terminationclock : IN std_logic := '0';
parallelloadenable : IN std_logic := '0';
terminationdata : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
seriesterminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
parallelterminationcontrol : OUT std_logic_vector(13 DOWNTO 0));
END COMPONENT;
--
-- stratixiii_dll Model
--
COMPONENT stratixiii_dll
GENERIC (
input_frequency : string := "0 ps";
delay_buffer_mode : string := "low";
delay_chain_length : integer := 12;
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "stratixiii_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetdelayctrlclkout : OUT std_logic;
upndnout : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_dll_offset_ctrl Model
--
COMPONENT stratixiii_dll_offset_ctrl
GENERIC (
use_offset : string := "false";
static_offset : string := "0";
delay_buffer_mode : string := "low";
lpm_type : string := "stratixiii_dll_offset_ctrl";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000";
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
addnsub : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
offsettestout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0)
);
END COMPONENT;
--
-- stratixiii_dqs_delay_chain Model
--
COMPONENT stratixiii_dqs_delay_chain
GENERIC (
dqs_input_frequency : string := "unused" ;
use_phasectrlin : string := "false";
phase_setting : integer := 0;
delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
-- DFT added in WYS 1.33
test_enable : string := "false";
test_select : integer := 0;
-- SIM only
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_dqs_delay_chain";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01;
tipd_phasectrlin : VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01);
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
offsetctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
dqsupdateen : IN std_logic := '1';
phasectrlin : IN std_logic_vector(2 downto 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic;
dffin : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_dqs_enable Model
--
COMPONENT stratixiii_dqs_enable
GENERIC (
lpm_type : string := "stratixiii_dqs_enable";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_dqsenable : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
dqsenable : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_dqs_enable_ctrl Model
--
COMPONENT stratixiii_dqs_enable_ctrl
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
level_dqs_enable : string := "false";
delay_dqs_enable_by_half_cycle : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_dqs_enable_ctrl";
tipd_dqsenablein : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsenablein : IN std_logic := '1';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsenableout : OUT std_logic;
dffin : OUT std_logic;
dffextenddqsenable : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_delay_chain Model
--
COMPONENT stratixiii_delay_chain
GENERIC (
sim_delayctrlin_rising_delay_0 : integer := 0;
sim_delayctrlin_rising_delay_1 : integer := 50;
sim_delayctrlin_rising_delay_2 : integer := 100;
sim_delayctrlin_rising_delay_3 : integer := 150;
sim_delayctrlin_rising_delay_4 : integer := 200;
sim_delayctrlin_rising_delay_5 : integer := 250;
sim_delayctrlin_rising_delay_6 : integer := 300;
sim_delayctrlin_rising_delay_7 : integer := 350;
sim_delayctrlin_rising_delay_8 : integer := 400;
sim_delayctrlin_rising_delay_9 : integer := 450;
sim_delayctrlin_rising_delay_10 : integer := 500;
sim_delayctrlin_rising_delay_11 : integer := 550;
sim_delayctrlin_rising_delay_12 : integer := 600;
sim_delayctrlin_rising_delay_13 : integer := 650;
sim_delayctrlin_rising_delay_14 : integer := 700;
sim_delayctrlin_rising_delay_15 : integer := 750;
sim_delayctrlin_falling_delay_0 : integer := 0;
sim_delayctrlin_falling_delay_1 : integer := 50;
sim_delayctrlin_falling_delay_2 : integer := 100;
sim_delayctrlin_falling_delay_3 : integer := 150;
sim_delayctrlin_falling_delay_4 : integer := 200;
sim_delayctrlin_falling_delay_5 : integer := 250;
sim_delayctrlin_falling_delay_6 : integer := 300;
sim_delayctrlin_falling_delay_7 : integer := 350;
sim_delayctrlin_falling_delay_8 : integer := 400;
sim_delayctrlin_falling_delay_9 : integer := 450;
sim_delayctrlin_falling_delay_10 : integer := 500;
sim_delayctrlin_falling_delay_11 : integer := 550;
sim_delayctrlin_falling_delay_12 : integer := 600;
sim_delayctrlin_falling_delay_13 : integer := 650;
sim_delayctrlin_falling_delay_14 : integer := 700;
sim_delayctrlin_falling_delay_15 : integer := 750;
use_delayctrlin : string := "true";
delay_setting : integer := 0;
-- new in STRATIXIV ww30.2008
sim_finedelayctrlin_falling_delay_0 : integer := 0;
sim_finedelayctrlin_falling_delay_1 : integer := 25;
sim_finedelayctrlin_rising_delay_0 : integer := 0;
sim_finedelayctrlin_rising_delay_1 : integer := 25;
use_finedelayctrlin : string := "false";
lpm_type : string := "stratixiii_delay_chain";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
delayctrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
finedelayctrlin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_io_clock_divider Model
--
COMPONENT stratixiii_io_clock_divider
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
use_masterin : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_io_clock_divider";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_phaseselect : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
tipd_masterin : VitalDelayType01 := DefpropDelay01;
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
clk : IN std_logic := '0';
phaseselect : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
phaseinvertctrl : IN std_logic := '0';
masterin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
clkout : OUT std_logic;
slaveout : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_output_phase_alignment Model
--
COMPONENT stratixiii_output_phase_alignment
GENERIC (
operation_mode : string := "ddio_out";
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
add_output_cycle_delay : string := "false";
use_delayed_clock : string := "false";
add_phase_transfer_reg : string := "false";
use_phasectrl_clock : string := "true";
use_primary_clock : string := "true";
invert_phase : string := "false";
bypass_input_register : string := "false";
phase_setting_for_delayed_clock : integer := 2;
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
-- new in STRATIXIV: ww30.2008
duty_cycle_delay_mode : string := "none";
sim_dutycycledelayctrlin_falling_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_falling_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_falling_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_falling_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_falling_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_falling_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_falling_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_falling_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_falling_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_falling_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_falling_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_falling_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_falling_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_falling_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_falling_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_falling_delay_9 : integer := 225 ;
sim_dutycycledelayctrlin_rising_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_rising_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_rising_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_rising_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_rising_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_rising_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_rising_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_rising_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_rising_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_rising_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_rising_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_rising_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_rising_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_rising_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_rising_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_rising_delay_9 : integer := 225 ;
lpm_type : string := "stratixiii_output_phase_alignment";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_sreset : VitalDelayType01 := DefpropDelay01;
tipd_clkena : VitalDelayType01 := DefpropDelay01;
tipd_enaoutputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
clkena : IN std_logic := '1';
enaoutputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
delaymode : IN std_logic := '0'; -- new in STRATIXIV: ww30.2008
dutycycledelayctrlin: IN std_logic_vector(3 downto 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic;
dffin : OUT std_logic_vector(1 downto 0);
dff1t : OUT std_logic_vector(1 downto 0);
dffddiodataout : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_input_phase_alignment Model
--
COMPONENT stratixiii_input_phase_alignment
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
add_input_cycle_delay : string := "false";
bypass_output_register : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_input_phase_alignment";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_enainputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
enainputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic;
dffin : OUT std_logic;
dff1t : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_half_rate_input Model
--
COMPONENT stratixiii_half_rate_input
GENERIC (
power_up : string := "low";
async_mode : string := "none";
use_dataoutbypass : string := "false";
lpm_type : string := "stratixiii_half_rate_input";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_directin : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_dataoutbypass : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
directin : IN std_logic := '0';
clk : IN std_logic := '0';
areset : IN std_logic := '0';
dataoutbypass: IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic_vector(3 downto 0);
dffin : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_io_config Model
--
COMPONENT stratixiii_io_config
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "stratixiii_io_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
-- new STRATIXIV: ww30.2008
dutycycledelaymode : OUT std_logic;
dutycycledelaysettings : OUT std_logic_vector(3 downto 0);
outputfinedelaysetting1 : OUT std_logic;
outputfinedelaysetting2 : OUT std_logic;
outputonlydelaysetting2 : OUT std_logic_vector(2 downto 0);
outputonlyfinedelaysetting2 : OUT std_logic;
padtoinputregisterfinedelaysetting : OUT std_logic;
padtoinputregisterdelaysetting : OUT std_logic_vector(3 downto 0);
outputdelaysetting1 : OUT std_logic_vector(3 downto 0);
outputdelaysetting2 : OUT std_logic_vector(2 downto 0);
dataout : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_dqs_config Model
--
COMPONENT stratixiii_dqs_config
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "stratixiii_dqs_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '0';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusoutfinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsenablefinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsbusoutdelaysetting : OUT std_logic_vector(3 downto 0);
dqsinputphasesetting : OUT std_logic_vector(2 downto 0);
dqsenablectrlphasesetting : OUT std_logic_vector(3 downto 0);
dqsoutputphasesetting : OUT std_logic_vector(3 downto 0);
dqoutputphasesetting : OUT std_logic_vector(3 downto 0);
resyncinputphasesetting : OUT std_logic_vector(3 downto 0);
dividerphasesetting : OUT std_logic;
enaoctcycledelaysetting : OUT std_logic;
enainputcycledelaysetting : OUT std_logic;
enaoutputcycledelaysetting: OUT std_logic;
dqsenabledelaysetting : OUT std_logic_vector(2 downto 0);
octdelaysetting1 : OUT std_logic_vector(3 downto 0);
octdelaysetting2 : OUT std_logic_vector(2 downto 0);
enadataoutbypass : OUT std_logic;
enadqsenablephasetransferreg : OUT std_logic;
enaoctphasetransferreg : OUT std_logic;
enaoutputphasetransferreg : OUT std_logic;
enainputphasetransferreg : OUT std_logic;
resyncinputphaseinvert : OUT std_logic;
dqsenablectrlphaseinvert : OUT std_logic;
dqoutputphaseinvert : OUT std_logic;
dqsoutputphaseinvert : OUT std_logic;
dataout : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_MAC_MULT
--
component stratixiii_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
scanouta_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
scanouta_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_type : string := "stratixiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0);
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END component;
--
-- stratixiii_MAC_OUT
--
component stratixiii_mac_out
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
chainin_width : integer := 1;
round_width : integer := 15;
round_chain_out_width : integer := 15;
saturate_width : integer := 15;
saturate_chain_out_width : integer := 15;
first_adder0_clock : string := "none";
first_adder0_clear : string := "none";
first_adder1_clock : string := "none";
first_adder1_clear : string := "none";
second_adder_clock : string := "none";
second_adder_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
signa_clock : string := "none";
signa_clear : string := "none";
signb_clock : string := "none";
signb_clear : string := "none";
round_clock : string := "none";
round_clear : string := "none";
roundchainout_clock : string := "none";
roundchainout_clear : string := "none";
saturate_clock : string := "none";
saturate_clear : string := "none";
saturatechainout_clock : string := "none";
saturatechainout_clear : string := "none";
zeroacc_clock : string := "none";
zeroacc_clear : string := "none";
zeroloopback_clock : string := "none";
zeroloopback_clear : string := "none";
rotate_clock : string := "none";
rotate_clear : string := "none";
shiftright_clock : string := "none";
shiftright_clear : string := "none";
signa_pipeline_clock : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clock : string := "none";
signb_pipeline_clear : string := "none";
round_pipeline_clock : string := "none";
round_pipeline_clear : string := "none";
roundchainout_pipeline_clock : string := "none";
roundchainout_pipeline_clear : string := "none";
saturate_pipeline_clock : string := "none";
saturate_pipeline_clear : string := "none";
saturatechainout_pipeline_clock: string := "none";
saturatechainout_pipeline_clear: string := "none";
zeroacc_pipeline_clock : string := "none";
zeroacc_pipeline_clear : string := "none";
zeroloopback_pipeline_clock : string := "none";
zeroloopback_pipeline_clear : string := "none";
rotate_pipeline_clock : string := "none";
rotate_pipeline_clear : string := "none";
shiftright_pipeline_clock : string := "none";
shiftright_pipeline_clear : string := "none";
roundchainout_output_clock : string := "none";
roundchainout_output_clear : string := "none";
saturatechainout_output_clock : string := "none";
saturatechainout_output_clear : string := "none";
zerochainout_output_clock : string := "none";
zerochainout_output_clear : string := "none";
zeroloopback_output_clock : string := "none";
zeroloopback_output_clear : string := "none";
rotate_output_clock : string := "none";
rotate_output_clear : string := "none";
shiftright_output_clock : string := "none";
shiftright_output_clear : string := "none";
first_adder0_mode : string := "add";
first_adder1_mode : string := "add";
acc_adder_operation : string := "add";
round_mode : string := "nearest_integer";
round_chain_out_mode : string := "nearest_integer";
saturate_mode : string := "asymmetric";
saturate_chain_out_mode : string := "asymmetric";
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
lpm_type : string := "stratixiii_mac_out";
dataout_width : integer:= 72
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
zeroacc : IN std_logic := '0';
roundchainout : IN std_logic := '0';
saturatechainout : IN std_logic := '0';
zerochainout : IN std_logic := '0';
zeroloopback : IN std_logic := '0';
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0';
saturatechainoutoverflow: OUT std_logic := '0';
dftout : OUT std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1'
);
end component;
--
-- STRATIXIII_IO_PAD
--
component stratixiii_io_pad
generic (
lpm_type : STRING := "stratixiii_io_pad"
);
PORT (
padin : in std_logic := '1';
padout: out std_logic
);
end component;
--
-- STRATIXIII_PLL
--
COMPONENT stratixiii_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 0;
clk5_divide_by : integer := 0;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
clk6_output_frequency : integer := 0;
clk6_multiply_by : integer := 0;
clk6_divide_by : integer := 0;
clk6_phase_shift : string := "0";
clk6_duty_cycle : integer := 50;
clk7_output_frequency : integer := 0;
clk7_multiply_by : integer := 0;
clk7_divide_by : integer := 0;
clk7_phase_shift : string := "0";
clk7_duty_cycle : integer := 50;
clk8_output_frequency : integer := 0;
clk8_multiply_by : integer := 0;
clk8_divide_by : integer := 0;
clk8_phase_shift : string := "0";
clk8_duty_cycle : integer := 50;
clk9_output_frequency : integer := 0;
clk9_multiply_by : integer := 0;
clk9_divide_by : integer := 0;
clk9_phase_shift : string := "0";
clk9_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
c6_high : integer := 1;
c6_low : integer := 1;
c6_initial : integer := 1;
c6_mode : string := "bypass";
c6_ph : integer := 0;
c7_high : integer := 1;
c7_low : integer := 1;
c7_initial : integer := 1;
c7_mode : string := "bypass";
c7_ph : integer := 0;
c8_high : integer := 1;
c8_low : integer := 1;
c8_initial : integer := 1;
c8_mode : string := "bypass";
c8_ph : integer := 0;
c9_high : integer := 1;
c9_low : integer := 1;
c9_initial : integer := 1;
c9_mode : string := "bypass";
c9_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
clk5_counter : string := "unused";
clk6_counter : string := "unused";
clk7_counter : string := "unused";
clk8_counter : string := "unused";
clk9_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
c5_test_source : integer := -1;
c6_test_source : integer := -1;
c7_test_source : integer := -1;
c8_test_source : integer := -1;
c9_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
lpm_type : string := "stratixiii_pll";
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk6_use_even_counter_mode : string := "off";
clk7_use_even_counter_mode : string := "off";
clk8_use_even_counter_mode : string := "off";
clk9_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
clk6_use_even_counter_value : string := "off";
clk7_use_even_counter_value : string := "off";
clk8_use_even_counter_value : string := "off";
clk9_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_c6_delay_chain_bits : integer := 0;
test_counter_c7_delay_chain_bits : integer := 0;
test_counter_c8_delay_chain_bits : integer := 0;
test_counter_c9_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
dpa_output_clock_phase_shift : integer := 0;
test_counter_c3_sclk_delay_chain_bits : integer := -1;
test_counter_c4_sclk_delay_chain_bits : integer := -1;
test_counter_c5_lden_delay_chain_bits : integer := -1;
test_counter_c6_lden_delay_chain_bits : integer := -1;
auto_settings : string := "true";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT (
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(9 downto 0);
phasecounterselect : in std_logic_vector(3 downto 0) := "0000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END COMPONENT;
--
-- STRATIXIII_ASMIBLOCK
--
component stratixiii_asmiblock
generic (
lpm_type : string := "stratixiii_asmiblock"
);
port (
dclkin : in std_logic := '0';
scein : in std_logic := '0';
sdoin : in std_logic := '0';
data0in : in std_logic := '0';
oe : in std_logic := '0';
dclkout : out std_logic;
sceout : out std_logic;
sdoout : out std_logic;
data0out: out std_logic
);
end component;
--
-- stratixiii_LVDS_RECEIVER
--
COMPONENT stratixiii_lvds_receiver
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
enable_soft_cdr : string := "off";
dpa_output_clock_phase_shift : INTEGER := 0;
enable_dpa_initial_phase_selection : string := "off";
dpa_initial_phase_value : INTEGER := 0;
enable_dpa_align_to_rising_edge_only : string := "off";
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : string := "off";
rx_input_path_delay_engineering_bits : INTEGER := -1;
x_on_bitslip : string := "on";
lpm_type : string := "stratixiii_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic;
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
divfwdclk : OUT std_logic;
dpaclkout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiii_pseudo_diff_out
--
COMPONENT stratixiii_pseudo_diff_out
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "stratixiii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_bias_block
--
component stratixiii_bias_block
generic (
lpm_type : string := "stratixiii_bias_block";
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
tipd_din : VitalDelayType01 := DefPropDelay01;
tsetup_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dout_posedge : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
din : in std_logic := '0';
dout : out std_logic := '0'
);
end component;
--
-- STRATIXIII_ASMIBLOCK
--
component stratixiii_tsdblock
generic (
poi_cal_temperature : integer := 85;
clock_divider_enable : string := "on";
clock_divider_value : integer := 40;
sim_tsdcalo : integer := 0;
user_offset_enable : string := "off";
lpm_type : string := "stratixiii_tsdblock"
);
port (
offset : in std_logic_vector(5 downto 0) := (OTHERS => '0');
clk : in std_logic := '0';
ce : in std_logic := '0';
clr : in std_logic := '0';
testin : in std_logic_vector(7 downto 0) := (OTHERS => '0');
tsdcalo : out std_logic_vector(7 downto 0);
tsdcaldone : out std_logic;
fdbkctrlfromcore : in std_logic := '0';
compouttest : in std_logic := '0';
tsdcompout : out std_logic;
offsetout : out std_logic_vector(5 downto 0)
);
end component;
--
-- STRATIXIII_LCELL_COMB
--
component stratixiii_lcell_comb
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
dont_touch : string := "off";
lpm_type : string := "stratixiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
end component;
--
-- STRATIXIII_JTAG
--
component stratixiii_jtag
generic (
lpm_type : string := "stratixiii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end component;
--
--
-- STRATIXIII_CRCBLOCK
--
--
component stratixiii_crcblock
generic (
oscillator_divider : integer := 1;
crc_deld_disable : string := "off";
error_delay : integer := 0 ;
error_dra_dl_bypass : string := "off";
lpm_type : string := "stratixiii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end component;
--
-- STRATIXIII_ROUTING_WIRE
--
component stratixiii_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
end component;
--
-- STRATIXIII_LVDS_TRANSMITTER
--
COMPONENT stratixiii_lvds_transmitter
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
is_used_as_outclk : String := "false";
tx_output_path_delay_engineering_bits : Integer := -1;
enable_dpaclk_to_lvdsout : string := "off";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : String := "stratixiii_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
dpaclkin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
END COMPONENT;
--
--
-- STRATIXIII_RUBLOCK
--
--
component stratixiii_rublock
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type: string := "stratixiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end component;
--
-- stratixiii_ram_block
--
component stratixiii_ram_block
generic
(
operation_mode : string := "single_port";
mixed_port_feed_through_mode : string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name : string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout : string := "none";
enable_ecc : STRING := "false";
data_interleave_width_in_bits : integer := 1;
data_interleave_offset_in_bits : integer := 1;
port_a_logical_ram_depth : integer := 0;
port_a_logical_ram_width : integer := 0;
port_a_address_clear : string := "none";
port_a_data_out_clock : string := "none";
port_a_data_out_clear : string := "none";
port_a_first_address : integer := 0;
port_a_last_address : integer := 0;
port_a_first_bit_number : integer := 0;
port_a_data_width : integer := 1;
port_a_data_in_clock : string := "clock0";
port_a_address_clock : string := "clock0";
port_a_write_enable_clock : string := "clock0";
port_a_read_enable_clock : string := "clock0";
port_a_byte_enable_clock : string := "clock0";
port_b_logical_ram_depth : integer := 0;
port_b_logical_ram_width : integer := 0;
port_b_data_in_clock : string := "clock1";
port_b_address_clock : string := "clock1";
port_b_address_clear : string := "none";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_data_out_clock : string := "none";
port_b_data_out_clear : string := "none";
port_b_first_address : integer := 0;
port_b_last_address : integer := 0;
port_b_first_bit_number : integer := 0;
port_b_data_width : integer := 1;
port_b_byte_enable_clock : string := "clock1";
port_a_address_width : integer := 1;
port_b_address_width : integer := 1;
port_a_byte_enable_mask_width : integer := 1;
port_b_byte_enable_mask_width : integer := 1;
power_up_uninitialized : string := "false";
port_a_byte_size : integer := 0;
port_b_byte_size : integer := 0;
lpm_type : string := "stratixiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
clock_duty_cycle_dependence : STRING := "Auto";
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
mem_init5 : BIT_VECTOR := X"0";
mem_init6 : BIT_VECTOR := X"0";
mem_init7 : BIT_VECTOR := X"0";
mem_init8 : BIT_VECTOR := X"0";
mem_init9 : BIT_VECTOR := X"0";
mem_init10 : BIT_VECTOR := X"0";
mem_init11 : BIT_VECTOR := X"0";
mem_init12 : BIT_VECTOR := X"0";
mem_init13 : BIT_VECTOR := X"0";
mem_init14 : BIT_VECTOR := X"0";
mem_init15 : BIT_VECTOR := X"0";
mem_init16 : BIT_VECTOR := X"0";
mem_init17 : BIT_VECTOR := X"0";
mem_init18 : BIT_VECTOR := X"0";
mem_init19 : BIT_VECTOR := X"0";
mem_init20 : BIT_VECTOR := X"0";
mem_init21 : BIT_VECTOR := X"0";
mem_init22 : BIT_VECTOR := X"0";
mem_init23 : BIT_VECTOR := X"0";
mem_init24 : BIT_VECTOR := X"0";
mem_init25 : BIT_VECTOR := X"0";
mem_init26 : BIT_VECTOR := X"0";
mem_init27 : BIT_VECTOR := X"0";
mem_init28 : BIT_VECTOR := X"0";
mem_init29 : BIT_VECTOR := X"0";
mem_init30 : BIT_VECTOR := X"0";
mem_init31 : BIT_VECTOR := X"0";
mem_init32 : BIT_VECTOR := X"0";
mem_init33 : BIT_VECTOR := X"0";
mem_init34 : BIT_VECTOR := X"0";
mem_init35 : BIT_VECTOR := X"0";
mem_init36 : BIT_VECTOR := X"0";
mem_init37 : BIT_VECTOR := X"0";
mem_init38 : BIT_VECTOR := X"0";
mem_init39 : BIT_VECTOR := X"0";
mem_init40 : BIT_VECTOR := X"0";
mem_init41 : BIT_VECTOR := X"0";
mem_init42 : BIT_VECTOR := X"0";
mem_init43 : BIT_VECTOR := X"0";
mem_init44 : BIT_VECTOR := X"0";
mem_init45 : BIT_VECTOR := X"0";
mem_init46 : BIT_VECTOR := X"0";
mem_init47 : BIT_VECTOR := X"0";
mem_init48 : BIT_VECTOR := X"0";
mem_init49 : BIT_VECTOR := X"0";
mem_init50 : BIT_VECTOR := X"0";
mem_init51 : BIT_VECTOR := X"0";
mem_init52 : BIT_VECTOR := X"0";
mem_init53 : BIT_VECTOR := X"0";
mem_init54 : BIT_VECTOR := X"0";
mem_init55 : BIT_VECTOR := X"0";
mem_init56 : BIT_VECTOR := X"0";
mem_init57 : BIT_VECTOR := X"0";
mem_init58 : BIT_VECTOR := X"0";
mem_init59 : BIT_VECTOR := X"0";
mem_init60 : BIT_VECTOR := X"0";
mem_init61 : BIT_VECTOR := X"0";
mem_init62 : BIT_VECTOR := X"0";
mem_init63 : BIT_VECTOR := X"0";
mem_init64 : BIT_VECTOR := X"0";
mem_init65 : BIT_VECTOR := X"0";
mem_init66 : BIT_VECTOR := X"0";
mem_init67 : BIT_VECTOR := X"0";
mem_init68 : BIT_VECTOR := X"0";
mem_init69 : BIT_VECTOR := X"0";
mem_init70 : BIT_VECTOR := X"0";
mem_init71 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
port
(
portawe : in std_logic := '0';
portare : in std_logic := '1';
portabyteenamasks : in std_logic_vector (port_a_byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbbyteenamasks : in std_logic_vector (port_b_byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbre : in std_logic := '1';
portbwe : in std_logic := '0';
clr0 : in std_logic := '0';
clr1 : in std_logic := '0';
clk0 : in std_logic := '0';
clk1 : in std_logic := '0';
ena0 : in std_logic := '1';
ena1 : in std_logic := '1';
ena2 : in std_logic := '1';
ena3 : in std_logic := '1';
portadatain : in std_logic_vector (port_a_data_width - 1 DOWNTO 0) := (others => '0');
portbdatain : in std_logic_vector (port_b_data_width - 1 DOWNTO 0) := (others => '0');
portaaddr : in std_logic_vector (port_a_address_width - 1 DOWNTO 0) := (others => '0');
portbaddr : in std_logic_vector (port_b_address_width - 1 DOWNTO 0) := (others => '0');
portaaddrstall : in std_logic := '0';
portbaddrstall : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
eccstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : out std_logic_vector (port_a_data_width - 1 DOWNTO 0);
portbdataout : out std_logic_vector (port_b_data_width - 1 DOWNTO 0)
);
end component;
end stratixiii_components;
| gpl-2.0 | 500daa6365d72ea2c35fa1e4f9e8dd2a | 0.46828 | 4.461326 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_rst_ps7_0_100M_1/sim/zqynq_lab_1_design_rst_ps7_0_100M_1.vhd | 1 | 5,911 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_11;
USE proc_sys_reset_v5_0_11.proc_sys_reset;
ENTITY zqynq_lab_1_design_rst_ps7_0_100M_1 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END zqynq_lab_1_design_rst_ps7_0_100M_1;
ARCHITECTURE zqynq_lab_1_design_rst_ps7_0_100M_1_arch OF zqynq_lab_1_design_rst_ps7_0_100M_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zqynq_lab_1_design_rst_ps7_0_100M_1_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END zqynq_lab_1_design_rst_ps7_0_100M_1_arch;
| mit | 07e8890a5ab7c18ac9504b8d8098981a | 0.706649 | 3.514269 | false | false | false | false |
Piasy/THCO-MIPS-CPU | src/Common_Register.vhd | 2 | 3,017 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:27:36 11/22/2013
-- Design Name:
-- Module Name: Register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Common_Register is
port(
clk : in STD_LOGIC;
rs : in STD_LOGIC_VECTOR(2 downto 0);
rt : in STD_LOGIC_VECTOR(2 downto 0);
write_flag : in STD_LOGIC;
write_reg : in STD_LOGIC_VECTOR(2 downto 0);
write_data : in STD_LOGIC_VECTOR(15 downto 0);
a : out STD_LOGIC_VECTOR(15 downto 0);
b : out STD_LOGIC_VECTOR(15 downto 0)
);
end Common_Register;
architecture Behavioral of Common_Register is
signal R0 : STD_LOGIC_VECTOR(15 downto 0) := ZERO;
signal R1 : STD_LOGIC_VECTOR(15 downto 0) := ZERO;
signal R2 : STD_LOGIC_VECTOR(15 downto 0) := ZERO;
signal R3 : STD_LOGIC_VECTOR(15 downto 0) := ZERO;
signal R4 : STD_LOGIC_VECTOR(15 downto 0) := ZERO;
signal R5 : STD_LOGIC_VECTOR(15 downto 0) := ZERO;
signal R6 : STD_LOGIC_VECTOR(15 downto 0) := ZERO;
signal R7 : STD_LOGIC_VECTOR(15 downto 0) := ZERO;
begin
process(clk)
begin
if (clk'event and clk = '0') then
if (write_flag = WRITE_REGS_YES) then
case write_reg is
when REG0 =>
R0 <= write_data;
when REG1 =>
R1 <= write_data;
when REG2 =>
R2 <= write_data;
when REG3 =>
R3 <= write_data;
when REG4 =>
R4 <= write_data;
when REG5 =>
R5 <= write_data;
when REG6 =>
R6 <= write_data;
when REG7 =>
R7 <= write_data;
when others =>
NULL;
end case;
end if;
end if;
end process;
process(rs, R0, R1, R2, R3, R4, R5, R6, R7)
begin
case rs is
when REG0 =>
a <= R0;
when REG1 =>
a <= R1;
when REG2 =>
a <= R2;
when REG3 =>
a <= R3;
when REG4 =>
a <= R4;
when REG5 =>
a <= R5;
when REG6 =>
a <= R6;
when REG7 =>
a <= R7;
when others =>
a <= ZERO;
end case;
end process;
process(rt, R0, R1, R2, R3, R4, R5, R6, R7)
begin
case rt is
when REG0 =>
b <= R0;
when REG1 =>
b <= R1;
when REG2 =>
b <= R2;
when REG3 =>
b <= R3;
when REG4 =>
b <= R4;
when REG5 =>
b <= R5;
when REG6 =>
b <= R6;
when REG7 =>
b <= R7;
when others =>
b <= ZERO;
end case;
end process;
end Behavioral;
| apache-2.0 | e4ff11c56e819e6db9ac7dbe806c8640 | 0.561485 | 2.898175 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/ddr/ahb2mig_series7.vhd | 1 | 28,712 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig
-- File: ahb2mig.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Virtex-7 MIG.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.all;
use gaisler.ahb2mig_series7_pkg.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.config_types.all;
use grlib.config.all;
library std;
use std.textio.all;
entity ahb2mig_series7 is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
maxwriteburst : integer := 8;
maxreadburst : integer := 8;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end ;
architecture rtl of ahb2mig_series7 is
type bstate_type is (idle, start, read_cmd, read_data, read_wait, read_output, write_cmd, write_burst);
constant AHBDW : integer := CFG_AHBDW;
constant maxburst : integer := 8;
constant maxmigcmds : integer := nbrmaxmigcmds(AHBDW);
constant wrsteps : integer := log2(32);
constant wrmask : integer := log2(32/8);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIG_SERIES7, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIG_SERIES7, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd : std_logic_vector(2 downto 0);
cmd_en : std_logic;
wr_en : std_logic;
wr_end : std_logic;
cmd_count : unsigned(31 downto 0);
wr_count : unsigned(31 downto 0);
rd_count : unsigned(31 downto 0);
hready : std_logic;
hwrite : std_logic;
hwdata_burst : std_logic_vector(512*maxmigcmds-1 downto 0);
mask_burst : std_logic_vector(64*maxmigcmds-1 downto 0);
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(31 downto 0);
haddr_start : std_logic_vector(31 downto 0);
haddr_offset : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
int_buffer : unsigned(512*maxmigcmds-1 downto 0);
rd_buffer : unsigned(512*maxmigcmds-1 downto 0);
wdf_data_buffer : std_logic_vector(511 downto 0);
wdf_mask_buffer : std_logic_vector(63 downto 0);
migcommands : integer;
nxt : std_logic;
end record;
type mig_in_type is record
app_addr : std_logic_vector(27 downto 0);
app_cmd : std_logic_vector(2 downto 0);
app_en : std_logic;
app_wdf_data : std_logic_vector(511 downto 0);
app_wdf_end : std_logic;
app_wdf_mask : std_logic_vector(63 downto 0);
app_wdf_wren : std_logic;
end record;
type mig_out_type is record
app_rd_data : std_logic_vector(511 downto 0);
app_rd_data_end : std_logic;
app_rd_data_valid : std_logic;
app_rdy : std_logic;
app_wdf_rdy : std_logic;
end record;
signal rin, r, rnxt, rnxtin : reg_type;
signal migin : mig_in_type;
signal migout,migoutraw : mig_out_type;
signal debug : std_logic := '0';
signal size_to_watch : std_logic_vector(2 downto 0) := HSIZE_4WORD;
component mig is
generic(
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE"
);
port (
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk_ref_i : in std_logic;
app_addr : in std_logic_vector(27 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(511 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(63 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(511 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
sys_rst : in std_logic
);
end component mig;
component mig_interface_model is
port (
app_addr : in std_logic_vector(27 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(511 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(63 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(511 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
sys_rst : in std_logic
);
end component mig_interface_model;
begin
comb: process( rst_n_syn, r, rin, ahbsi, migout )
-- Design temp variables
variable v,vnxt : reg_type;
variable writedata : std_logic_vector(255 downto 0);
variable wmask : std_logic_vector(AHBDW/4-1 downto 0);
variable shift_steps : natural;
variable hrdata_shift_steps : natural;
variable steps_write : unsigned(31 downto 0);
variable shift_steps_write : natural;
variable shift_steps_write_mask : natural;
variable startaddress : unsigned(v.haddr'length-1 downto 0);
variable start_address : std_logic_vector(v.haddr'length-1 downto 0);
variable step_offset : unsigned(steps_write'length-1 downto 0);
variable haddr_offset : unsigned(steps_write'length-1 downto 0);
begin
-- Make all register visible for the statemachine
v := r; vnxt := rnxt;
-- workout the start address in AHB2MIG buffer based upon
startaddress := resize(unsigned(unsigned(ahbsi.haddr(ahbsi.haddr'left-3 downto 8)) & "00000"),startaddress'length);
-- Adjust offset in memory buffer
startaddress := resize(startaddress + unsigned(unsigned(ahbsi.haddr(7 downto 6))&"000"),startaddress'length);
start_address := std_logic_vector(startaddress);
-- Workout local offset to be able to adust for warp-around
haddr_offset := unsigned(r.haddr_start) - unsigned(unsigned(r.haddr_offset(r.haddr_offset'length-1 downto 6))&"000000");
step_offset := resize(unsigned(haddr_offset(7 downto 6)&"0000"),step_offset'length);
-- Fetch AMBA Commands
if (( ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready and not ahbsi.htrans(0)) = '1'
and (ahbsi.hwrite = '0' or ahbsi.hwrite = '1' )) then
vnxt.cmd_count:= (others => '0');
vnxt.wr_count := (others => '0');
vnxt.rd_count := (others => '0');
vnxt.hrdata := (others => '0');
-- Clear old pointers and MIG command signals
vnxt.cmd := (others => '0');
vnxt.cmd_en := '0';
vnxt.wr_en := '0';
vnxt.wr_end := '0';
vnxt.hwrite := '0';
vnxt.hwdata_burst := (others => '0');
vnxt.mask_burst := (others => '0');
-- Hold info regarding transaction and execute
vnxt.hburst := ahbsi.hburst;
vnxt.hwrite := ahbsi.hwrite;
vnxt.hsize := ahbsi.hsize;
vnxt.hmaster := ahbsi.hmaster;
vnxt.hready := '0';
vnxt.htrans := ahbsi.htrans;
vnxt.bstate := start;
vnxt.haddr := start_address;
vnxt.haddr_start := ahbsi.haddr;
vnxt.haddr_offset := ahbsi.haddr;
vnxt.cmd(2 downto 0) := (others => '0');
vnxt.cmd(0) := not ahbsi.hwrite;
if (r.bstate = idle) then vnxt.nxt := '0'; else vnxt.nxt := '1'; end if;
-- Clear some old stuff
vnxt.int_buffer := (others => '0');
vnxt.rd_buffer := (others => '0');
vnxt.wdf_data_buffer := (others => '0');
vnxt.wdf_mask_buffer := (others => '0');
end if;
case r.bstate is
when idle =>
-- Clear old pointers and MIG command signals
v.cmd := (others => '0');
v.cmd_en := '0';
v.wr_en := '0';
v.wr_end := '0';
v.hready := '1';
v.hwrite := '0';
v.hwdata_burst := (others => '0');
v.mask_burst := (others => '0');
v.rd_count := (others => '0');
vnxt.cmd := (others => '0');
vnxt.cmd_en := '0';
vnxt.wr_en := '0';
vnxt.wr_end := '0';
vnxt.hready := '1';
vnxt.hwrite := '0';
vnxt.hwdata_burst := (others => '0');
vnxt.mask_burst := (others => '0');
vnxt.rd_count := (others => '0');
vnxt.wr_count := (others => '0');
vnxt.cmd_count := (others => '0');
-- Check if this is a single or burst transfer (and not a BUSY transfer)
if (( ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready) = '1'
and (ahbsi.hwrite = '0' or ahbsi.hwrite = '1' )) then
-- Hold info regarding transaction and execute
v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite;
v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
v.htrans := ahbsi.htrans;
v.bstate := start;
v.haddr := start_address;
v.haddr_start := ahbsi.haddr;
v.haddr_offset := ahbsi.haddr;
v.cmd := (others => '0');
v.cmd(0) := not ahbsi.hwrite;
end if;
when start =>
v.migcommands := nbrmigcmds(r.hwrite,r.hsize,ahbsi.htrans,step_offset,AHBDW);
-- Check if a write command shall be issued to the DDR3 memory
if r.hwrite = '1' then
wmask := (others => '0');
writedata := (others => '0');
if ((ahbsi.htrans /= HTRANS_SEQ) or ((ahbsi.htrans = HTRANS_SEQ) and (r.rd_count > 0) and (r.rd_count <= maxburst))) then
-- work out how many steps we need to shift the input
steps_write := ahbselectdatanoreplicastep(r.haddr_start(7 downto 2),r.hsize(2 downto 0)) + step_offset;
shift_steps_write := to_integer(shift_left(steps_write,wrsteps));
shift_steps_write_mask := to_integer(shift_left(steps_write,wrmask));
-- generate mask for complete burst (only need to use addr[3:0])
wmask := ahbselectdatanoreplicamask(r.haddr_start(6 downto 0),r.hsize(2 downto 0));
v.mask_burst := r.mask_burst or std_logic_vector(shift_left(resize(unsigned(wmask), r.mask_burst'length),shift_steps_write_mask));
-- fetch all wdata before write to memory can begin (only supports upto 128bits i.e. addr[4:0]
writedata(AHBDW-1 downto 0) := ahbselectdatanoreplica(ahbsi.hwdata(AHBDW-1 downto 0),r.haddr_start(4 downto 0),r.hsize(2 downto 0));
v.hwdata_burst := r.hwdata_burst or std_logic_vector(shift_left(resize(unsigned(writedata),v.hwdata_burst'length),shift_steps_write));
v.haddr_start := ahbsi.haddr;
end if;
-- Check if this is a cont burst longer than internal buffer
if (ahbsi.htrans = HTRANS_SEQ) then
if (r.rd_count < maxburst-1) then
v.hready := '1';
else
v.hready := '0';
end if;
if (r.rd_count >= maxburst) then
if (r.htrans = HTRANS_SEQ) then
v.bstate := write_cmd;
end if;
v.htrans := ahbsi.htrans;
end if;
else
v.bstate := write_cmd;
v.htrans := ahbsi.htrans;
end if;
-- Else issue a read command when ready
else
if migout.app_rdy = '1' and migout.app_wdf_rdy = '1' then
v.cmd := "001";
v.bstate := read_cmd;
v.htrans := ahbsi.htrans;
v.cmd_count := to_unsigned(0,v.cmd_count'length);
end if;
end if;
when write_cmd =>
-- Check if burst has ended due to max size burst
if (ahbsi.htrans /= HTRANS_SEQ) then
v.htrans := (others => '0');
end if;
-- Stop when addr and write command is accepted by mig
if (r.wr_count >= r.migcommands) and (r.cmd_count >= r.migcommands) then
if (r.htrans /= HTRANS_SEQ) then
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
else
v.bstate := idle;
end if;
else -- Cont burst and work out new offset for next write command
v.bstate := write_burst;
v.hready := '1';
end if;
end if;
when write_burst =>
v.bstate := start;
v.hready := '0';
v.hwdata_burst := (others => '0');
v.mask_burst := (others => '0');
v.haddr := start_address;
v.haddr_offset := ahbsi.haddr;
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
end if;
when read_cmd =>
v.hready := '0';
v.rd_count := (others => '0');
-- stop when read command is accepted ny mig.
if (r.cmd_count >= r.migcommands) then
v.bstate := read_data;
--v.int_buffer := (others => '0');
end if;
when read_data =>
-- We are not ready yet so issue a read command to the memory controller
v.hready := '0';
-- If read data is valid store data in buffers
if (migout.app_rd_data_valid = '1') then
v.rd_count := r.rd_count + 1;
-- Viviado seems to misinterpet the following shift construct and
-- therefore changed to a if-else statement
--v.int_buffer := r.int_buffer or shift_left( resize(unsigned(migout.app_rd_data),r.int_buffer'length),
-- to_integer(shift_left(r.rd_count,9)));
if (r.rd_count = 0) then
v.int_buffer(511 downto 0) := unsigned(migout.app_rd_data);
elsif (r.rd_count = 1) then
v.int_buffer(1023 downto 512) := unsigned(migout.app_rd_data);
elsif (AHBDW > 64) then
if (r.rd_count = 2) then
v.int_buffer(1535 downto 1024) := unsigned(migout.app_rd_data);
else
v.int_buffer(2047 downto 1536) := unsigned(migout.app_rd_data);
end if;
end if;
end if;
if (r.rd_count >= r.migcommands) then
v.rd_buffer := r.int_buffer;
v.bstate := read_output;
v.rd_count := to_unsigned(0,v.rd_count'length);
end if;
when read_output =>
-- Data is fetched from memory and ready to be transfered
v.hready := '1';
-- uses the "wr_count" signal to keep track of number of bytes output'd to AHB
-- Select correct 32bit/64bit/128bit to output
v.hrdata := ahbselectdatanoreplicaoutput(r.haddr_start(7 downto 0),r.wr_count,r.hsize,r.rd_buffer,r.wr_count,true);
-- Count number of bytes send
v.wr_count := r.wr_count + 1;
-- Check if this was the last transaction
if (r.wr_count >= maxburst-1) then
v.bstate := read_wait;
end if;
-- Check if transfer was interrupted or no burst
if (ahbsi.htrans = HTRANS_IDLE) or ((ahbsi.htrans = HTRANS_NONSEQ) and (r.wr_count < maxburst)) then
v.bstate := read_wait;
v.wr_count := (others => '0');
v.rd_count := (others => '0');
v.cmd_count := (others => '0');
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
v.bstate := start;
end if;
end if;
when read_wait =>
if ((r.wr_count >= maxburst) and (ahbsi.htrans = HTRANS_SEQ)) then
v.hready := '0';
v.bstate := start;
v.haddr_start := ahbsi.haddr;
v.haddr := start_address;
v.haddr_offset := ahbsi.haddr;
else
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
v.bstate := start;
else
v.bstate := idle;
v.hready := '1';
end if;
end if;
when others =>
v.bstate := idle;
end case;
if ((ahbsi.htrans /= HTRANS_SEQ) and (r.bstate = start)) then
v.hready := '0';
end if;
if rst_n_syn = '0' then
v.bstate := idle; v.hready := '1'; v.cmd_en := '0'; v.wr_en := '0'; v.wr_end := '0';
--v.wdf_mask_buffer := (others => '0'); v.wdf_data_buffer := (others => '0'); v.haddr := (others => '0');
end if;
rin <= v;
rnxtin <= vnxt;
end process;
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= ahbdrivedata(r.hrdata);
migin.app_addr <= r.haddr(27 downto 2) & "00";
migin.app_cmd <= r.cmd;
migin.app_en <= r.cmd_en;
migin.app_wdf_data <= r.wdf_data_buffer;
migin.app_wdf_end <= r.wr_end;
migin.app_wdf_mask <= r.wdf_mask_buffer;
migin.app_wdf_wren <= r.wr_en;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.prdata <= (others => '0');
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
-- Copy variables into registers (Default values)
r <= rin;
rnxt <= rnxtin;
-- add extra pipe-stage for read data
migout <= migoutraw;
-- IDLE Clear
if ((r.bstate = idle) or (r.bstate = read_wait)) then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= (others => '0');
end if;
if (r.bstate = write_burst) then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= to_unsigned(1,r.rd_count'length);
end if;
-- Read AHB write data
if (r.bstate = start) and (r.hwrite = '1') then
r.rd_count <= r.rd_count + 1;
end if;
-- Write command repsonse
if r.bstate = write_cmd then
if (r.cmd_count < 1) then
r.cmd_en <= '1';
end if;
if (migoutraw.app_rdy = '1') and (r.cmd_en = '1' ) then
r.cmd_count <= r.cmd_count + 1;
if (r.cmd_count < r.migcommands-1 ) then
r.haddr <= r.haddr + 8;
end if;
if (r.cmd_count >= r.migcommands-1) then
r.cmd_en <= '0';
end if;
end if;
if (r.wr_count < 1 ) then
r.wr_en <= '1';
r.wr_end <= '1';
r.wdf_mask_buffer <= not r.mask_burst(63 downto 0);
r.wdf_data_buffer <= r.hwdata_burst(511 downto 0);
end if;
if (migoutraw.app_wdf_rdy = '1') and (r.wr_en = '1' ) then
if (r.wr_count = 0) then
r.wdf_mask_buffer <= not r.mask_burst(127 downto 64);
r.wdf_data_buffer <= r.hwdata_burst(1023 downto 512);
elsif (AHBDW > 64) then
if (r.wr_count = 1) then
r.wdf_mask_buffer <= not r.mask_burst(191 downto 128);
r.wdf_data_buffer <= r.hwdata_burst(1535 downto 1024);
else
r.wdf_mask_buffer <= not r.mask_burst(255 downto 192);
r.wdf_data_buffer <= r.hwdata_burst(2047 downto 1536);
end if;
else
r.wdf_mask_buffer <= not r.mask_burst(127 downto 64);
r.wdf_data_buffer <= r.hwdata_burst(1023 downto 512);
end if;
r.wr_count <= r.wr_count + 1;
if (r.wr_count >= r.migcommands - 1) then
r.wr_en <= '0';
r.wr_end <= '0';
end if;
end if;
end if;
-- Burst Write Wait
if r.bstate = write_burst then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= (others => '0');
end if;
-- Read command repsonse
if r.bstate = read_cmd then
if (r.cmd_count < 1) then
r.cmd_en <= '1';
end if;
if (migoutraw.app_rdy = '1') and (r.cmd_en = '1' ) then
r.cmd_count <= r.cmd_count + 1;
if (r.cmd_count < r.migcommands-1 ) then
r.haddr <= r.haddr + 8;
end if;
if (r.cmd_count >= r.migcommands-1) then
r.cmd_en <= '0';
end if;
end if;
end if;
end if;
end process;
gen_mig : if (USE_MIG_INTERFACE_MODEL /= true) generate
MCB_inst : mig
generic map(
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION)
port map (
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
clk_ref_i => clk_ref_i,
app_addr => migin.app_addr,
app_cmd => migin.app_cmd,
app_en => migin.app_en,
app_rdy => migoutraw.app_rdy,
app_wdf_data => migin.app_wdf_data,
app_wdf_end => migin.app_wdf_end,
app_wdf_mask => migin.app_wdf_mask,
app_wdf_wren => migin.app_wdf_wren,
app_wdf_rdy => migoutraw.app_wdf_rdy,
app_rd_data => migoutraw.app_rd_data,
app_rd_data_end => migoutraw.app_rd_data_end,
app_rd_data_valid => migoutraw.app_rd_data_valid,
app_sr_req => '0',
app_ref_req => '0',
app_zq_req => '0',
app_sr_active => open,
app_ref_ack => open,
app_zq_ack => open,
ui_clk => ui_clk,
ui_clk_sync_rst => ui_clk_sync_rst,
init_calib_complete => calib_done,
sys_rst => rst_n_async
);
end generate gen_mig;
gen_mig_model : if (USE_MIG_INTERFACE_MODEL = true) generate
MCB_model_inst : mig_interface_model
port map (
-- user interface signals
app_addr => migin.app_addr,
app_cmd => migin.app_cmd,
app_en => migin.app_en,
app_rdy => migoutraw.app_rdy,
app_wdf_data => migin.app_wdf_data,
app_wdf_end => migin.app_wdf_end,
app_wdf_mask => migin.app_wdf_mask,
app_wdf_wren => migin.app_wdf_wren,
app_wdf_rdy => migoutraw.app_wdf_rdy,
app_rd_data => migoutraw.app_rd_data,
app_rd_data_end => migoutraw.app_rd_data_end,
app_rd_data_valid => migoutraw.app_rd_data_valid,
ui_clk => ui_clk,
ui_clk_sync_rst => ui_clk_sync_rst,
init_calib_complete => calib_done,
sys_rst => rst_n_async
);
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
ddr3_addr <= (others => '0');
ddr3_ba <= (others => '0');
ddr3_ras_n <= '0';
ddr3_cas_n <= '0';
ddr3_we_n <= '0';
ddr3_reset_n <= '1';
ddr3_ck_p <= (others => '0');
ddr3_ck_n <= (others => '0');
ddr3_cke <= (others => '0');
ddr3_cs_n <= (others => '0');
ddr3_dm <= (others => '0');
ddr3_odt <= (others => '0');
end generate gen_mig_model;
end;
| gpl-2.0 | e1ed708aa3cf6c6d79f34d4f675e65f2 | 0.517136 | 3.431576 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-digilent-nexys4/leon3mp.vhd | 1 | 24,478 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.BUFG;
use unisim.PLLE2_ADV;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
clk : in std_ulogic;
-- onBoard Cellular RAM, Numonyx StrataFlash and Numonyx Quad Flash
RamOE : out std_ulogic;
RamWE : out std_ulogic;
RamAdv : out std_ulogic;
RamCE : out std_ulogic;
RamClk : out std_ulogic;
RamCRE : out std_ulogic;
RamLB : out std_ulogic;
RamUB : out std_ulogic;
--RamWait : in std_ulogic;
--QspiCSn : out std_ulogic;
--QspiSCK : out std_ulogic;
--QspiDB : inout std_logic_vector(3 downto 0);
address : out std_logic_vector(22 downto 0);
data : inout std_logic_vector(15 downto 0);
-- 7 segment display
--seg : out std_logic_vector(6 downto 0);
--an : out std_logic_vector(7 downto 0);
-- LEDs
Led : out std_logic_vector(15 downto 0);
-- Switches
sw : in std_logic_vector(15 downto 0);
-- Buttons
btnCpuResetn : in std_ulogic;
btn : in std_logic_vector(4 downto 0);
-- VGA Connector
--vgaRed : out std_logic_vector(2 downto 0);
--vgaGreen : out std_logic_vector(2 downto 0);
--vgaBlue : out std_logic_vector(2 downto 1);
--Hsync : out std_ulogic;
--Vsync : out std_ulogic;
-- 12 pin connectors
--ja : inout std_logic_vector(7 downto 0);
--jb : inout std_logic_vector(7 downto 0);
--jc : inout std_logic_vector(7 downto 0);
--jd : inout std_logic_vector(7 downto 0);
-- SMSC ethernet PHY
PhyRstn : out std_ulogic;
PhyCrs : in std_ulogic;
PhyClk50Mhz : out std_ulogic;
PhyTxd : out std_logic_vector(1 downto 0);
PhyTxEn : out std_ulogic;
PhyRxd : in std_logic_vector(1 downto 0);
PhyRxEr : in std_ulogic;
PhyMdc : out std_ulogic;
PhyMdio : inout std_logic;
-- Pic USB-HID interface
--~ PS2KeyboardData : inout std_logic;
--~ PS2KeyboardClk : inout std_logic;
--~ PS2MouseData : inout std_logic;
--~ PS2MouseClk : inout std_logic;
--~ PicGpio : out std_logic_vector(1 downto 0);
-- USB-RS232 interface
RsRx : in std_logic;
RsTx : out std_logic
);
end;
architecture rtl of leon3mp is
component PLLE2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT : integer := 5;
CLKFBOUT_PHASE : real := 0.0;
CLKIN1_PERIOD : real := 0.0;
CLKIN2_PERIOD : real := 0.0;
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 0.0;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 0.0;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 0.0;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 0.0;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 0.0;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 0.0;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
STARTUP_WAIT : string := "FALSE"
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
signal CLKFBOUT : std_logic;
signal CLKFBIN : std_logic;
signal eth_pll_rst : std_logic;
signal eth_clk_nobuf : std_logic;
signal eth_clk90_nobuf : std_logic;
signal eth_clk : std_logic;
signal eth_clk90 : std_logic;
signal vcc : std_logic;
signal gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ndsuact : std_ulogic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal btnCpuReset : std_logic;
signal lock : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 100000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
led(15 downto 4) <= (others =>'0'); -- unused leds off
btnCpuReset<= not btnCpuResetn;
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 1)
port map (btnCpuReset, clkm, lock, rstn, rstraw);
lock <= cgo.clklock;
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (clk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
led(3) <= not dbgo(0).error;
led(2) <= not dsuo.active;
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
--dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (RsRx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (RsTx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0, rommask => 0,
iomask => 0, ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,srbanks=>1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (tech => padtech, width => 23)
port map (address, memo.address(23 downto 1));
oen_pad : outpad generic map (tech => padtech)
port map (RamOE, memo.oen);
cs_pad : outpad generic map (tech => padtech)
port map (RamCE, memo.ramsn(0));
lb_pad : outpad generic map (tech => padtech)
port map (RamLB, memo.mben(0));
ub_pad : outpad generic map (tech => padtech)
port map (RamUB, memo.mben(1));
wri_pad : outpad generic map (tech => padtech)
port map (RamWE, memo.writen);
end generate;
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(23 downto 16),
memo.bdrive(1), memi.data(23 downto 16));
bdr2 : iopadv generic map (tech => padtech, width => 8)
port map (data(15 downto 8), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
RamCRE <= '0';
RamClk <= '0';
RamAdv <= '0';
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
noddr : if (CFG_DDR2SP+CFG_MIG_DDR2) = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
-- serrx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd1);
-- sertx_pad : outpad generic map (tech => padtech) port map (dsutx, txd1);
-- led(0) <= not rxd1;
-- led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
nospi: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0 generate
apbo(7) <= apb_none;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G, rmii => 1)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
PhyRstn<=rstn;
end generate;
etxc_pad : outpad generic map (tech => padtech)
port map (PhyClk50Mhz, eth_clk);
ethpads : if (CFG_GRETH = 1) generate
emdio_pad : iopad generic map (tech => padtech)
port map (PhyMdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
ethi.rmii_clk<=eth_clk90;
erxd_pad : inpadv generic map (tech => padtech, width => 2) --8
port map (PhyRxd, ethi.rxd(1 downto 0));
erxer_pad : inpad generic map (tech => padtech)
port map (PhyRxEr, ethi.rx_er);
erxcr_pad : inpad generic map (tech => padtech)
port map (PhyCrs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 2)
port map (PhyTxd, etho.txd(1 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (PhyTxEn, etho.tx_en);
emdc_pad : outpad generic map (tech => padtech)
port map (PhyMdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Digilent NEXYS 3 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
-----------------------------------------------------------------------
--- Ethernet Clock Generation ---------------------------------------
-----------------------------------------------------------------------
-- 50 MHz clock for output
bufgclk0 : BUFG port map (I => eth_clk_nobuf, O => eth_clk);
-- 50 MHz with +90 deg phase for Rx GRETH
bufgclk45 : BUFG port map (I => eth_clk90_nobuf, O => eth_clk90);
CLKFBIN <= CLKFBOUT;
eth_pll_rst <= not cgi.pllrst;
PLLE2_ADV_inst : PLLE2_ADV generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 8, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => 1000000.0/real(100000.0),
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => 16,
CLKOUT1_DIVIDE => 16,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 90.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => "TRUE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => eth_clk_nobuf,
CLKOUT1 => eth_clk90_nobuf,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
-- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
DO => open,
DRDY => open,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => CLKFBOUT,
-- Status Ports: 1-bit (each) output: PLL status ports
LOCKED => open,
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => clk,
CLKIN2 => '0',
-- Con trol Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => eth_pll_rst,
-- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => CLKFBIN
);
end rtl;
| gpl-2.0 | 20ad0c128898ce0d9ef9a16b7075e69f | 0.521938 | 3.843907 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/6223c44b21ae4a4d/zqynq_lab_1_design_axi_gpio_1_1_sim_netlist.vhdl | 1 | 111,233 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Fri Sep 22 23:00:32 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_gpio_1_1_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_gpio_1_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
port (
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[4]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
Read_Reg_Rst : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]_0\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
start2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
is_read : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
\bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 4 downto 0 );
\Not_Dual.gpio_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
bus2ip_reset : in STD_LOGIC;
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\ : STD_LOGIC;
signal \^not_dual.gpio_data_out_reg[4]\ : STD_LOGIC;
signal \^ip2bus_data_i_d1_reg[0]\ : STD_LOGIC;
signal \^ip_irpt_enable_reg_reg[0]\ : STD_LOGIC;
signal p_10_in : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_11_out : STD_LOGIC;
signal p_12_in : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_15_out : STD_LOGIC;
signal p_16_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in_0 : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_in : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pselect_hit_i_1 : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of intr2bus_rdack_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of intr2bus_wrack_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of irpt_rdack_d1_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of irpt_wrack_d1_i_1 : label is "soft_lutpair1";
begin
\Not_Dual.gpio_Data_Out_reg[4]\ <= \^not_dual.gpio_data_out_reg[4]\;
\ip2bus_data_i_D1_reg[0]\ <= \^ip2bus_data_i_d1_reg[0]\;
\ip_irpt_enable_reg_reg[0]\ <= \^ip_irpt_enable_reg_reg[0]\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => start2,
I2 => \^ip_irpt_enable_reg_reg[0]\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^ip_irpt_enable_reg_reg[0]\,
R => '0'
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_9_out
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_9_out,
Q => p_10_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_8_out
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_8_out,
Q => p_9_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_7_out
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_7_out,
Q => \^ip2bus_data_i_d1_reg[0]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_6_out
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_6_out,
Q => p_7_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_5_out
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_5_out,
Q => p_6_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_4_out
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_4_out,
Q => p_5_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\,
Q => p_4_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\,
Q => p_3_in_0,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\,
Q => p_2_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => s_axi_aresetn,
I1 => \^s_axi_arready\,
I2 => \^s_axi_wready\,
O => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_15_out
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_15_out,
Q => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\,
Q => p_16_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_14_out
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_14_out,
Q => p_15_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_13_out
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_13_out,
Q => p_14_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0200000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_12_out
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_12_out,
Q => p_13_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_11_out
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_11_out,
Q => p_12_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_10_out
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_10_out,
Q => p_11_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => intr_rd_ce_or_reduce
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FE0000"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => ip2Bus_RdAck_intr_reg_hole_d1,
I4 => \^ip_irpt_enable_reg_reg[0]\,
O => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FE"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => intr_wr_ce_or_reduce
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => p_16_in,
I1 => p_2_in,
I2 => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\,
I3 => p_14_in,
I4 => p_15_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_12_in,
I1 => p_13_in,
I2 => p_10_in,
I3 => p_11_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_5_in,
I1 => p_7_in,
I2 => p_3_in_0,
I3 => p_4_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000FE"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ip_irpt_enable_reg_reg[0]\,
I4 => ip2Bus_WrAck_intr_reg_hole_d1,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\
);
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => start2,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(4),
I3 => \bus2ip_addr_i_reg[8]\(5),
I4 => \bus2ip_addr_i_reg[8]\(3),
I5 => \bus2ip_addr_i_reg[8]\(2),
O => pselect_hit_i_1
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => pselect_hit_i_1,
Q => \^not_dual.gpio_data_out_reg[4]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(4),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(4),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[4]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => GPIO_DBus_i(0)
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(3),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(3),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[4]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(2),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(2),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[4]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(1),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(1),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[4]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^not_dual.gpio_data_out_reg[4]\,
I1 => GPIO_xferAck_i,
I2 => bus2ip_rnw_i_reg,
I3 => gpio_xferAck_Reg,
O => Read_Reg_Rst
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(0),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(0),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[4]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\
);
\Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000100"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^not_dual.gpio_data_out_reg[4]\,
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => bus2ip_reset,
O => \Not_Dual.gpio_Data_Out_reg[0]\(0)
);
\Not_Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(9),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[4]\,
I3 => s_axi_wdata(4),
O => D(4)
);
\Not_Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(8),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[4]\,
I3 => s_axi_wdata(3),
O => D(3)
);
\Not_Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(7),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[4]\,
I3 => s_axi_wdata(2),
O => D(2)
);
\Not_Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(6),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[4]\,
I3 => s_axi_wdata(1),
O => D(1)
);
\Not_Dual.gpio_Data_Out[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(5),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[4]\,
I3 => s_axi_wdata(0),
O => D(0)
);
\Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF01000000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^not_dual.gpio_data_out_reg[4]\,
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => bus2ip_reset,
O => E(0)
);
intr2bus_rdack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"44444440"
)
port map (
I0 => irpt_rdack_d1,
I1 => \^ip_irpt_enable_reg_reg[0]\,
I2 => p_9_in,
I3 => \^ip2bus_data_i_d1_reg[0]\,
I4 => p_6_in,
O => intr2bus_rdack0
);
intr2bus_wrack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000FE"
)
port map (
I0 => p_9_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => p_6_in,
I3 => \^ip_irpt_enable_reg_reg[0]\,
I4 => irpt_wrack_d1,
O => interrupt_wrce_strb
);
\ip2bus_data_i_D1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => p_0_in(0),
I1 => p_9_in,
I2 => \^ip_irpt_enable_reg_reg[0]\,
I3 => p_6_in,
I4 => \^ip2bus_data_i_d1_reg[0]\,
O => \ip2bus_data_i_D1_reg[0]_0\(1)
);
\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEAAAAFAAAAAAA"
)
port map (
I0 => ip2bus_data(0),
I1 => p_3_in(0),
I2 => p_1_in(0),
I3 => p_6_in,
I4 => \^ip_irpt_enable_reg_reg[0]\,
I5 => \^ip2bus_data_i_d1_reg[0]\,
O => \ip2bus_data_i_D1_reg[0]_0\(0)
);
\ip_irpt_enable_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => p_6_in,
I2 => \^ip_irpt_enable_reg_reg[0]\,
I3 => p_1_in(0),
O => \ip_irpt_enable_reg_reg[0]_0\
);
ipif_glbl_irpt_enable_reg_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(9),
I1 => p_9_in,
I2 => \^ip_irpt_enable_reg_reg[0]\,
I3 => p_0_in(0),
O => ipif_glbl_irpt_enable_reg_reg
);
irpt_rdack_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => p_9_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => p_6_in,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => irpt_rdack
);
irpt_wrack_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00FE"
)
port map (
I0 => p_9_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => p_6_in,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => irpt_wrack
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_read,
I5 => ip2bus_rdack_i_D1,
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_write_reg,
I5 => ip2bus_wrack_i_D1,
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
scndry_vect_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_4 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d2_4 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
signal s_level_out_bus_d3_4 : STD_LOGIC;
signal \^scndry_vect_out\ : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
scndry_vect_out(4 downto 0) <= \^scndry_vect_out\(4 downto 0);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_4,
Q => s_level_out_bus_d2_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_4,
Q => s_level_out_bus_d3_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => \^scndry_vect_out\(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => \^scndry_vect_out\(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => \^scndry_vect_out\(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => \^scndry_vect_out\(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_4,
Q => \^scndry_vect_out\(4),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(4),
Q => s_level_out_bus_d1_cdc_to_4,
R => '0'
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => \^scndry_vect_out\(4),
O => D(4)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => \^scndry_vect_out\(3),
O => D(3)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => \^scndry_vect_out\(2),
O => D(2)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => \^scndry_vect_out\(1),
O => D(1)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => \^scndry_vect_out\(0),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_interrupt_control is
port (
irpt_wrack_d1 : out STD_LOGIC;
p_3_in : out STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
p_0_in : out STD_LOGIC_VECTOR ( 0 to 0 );
IP2INTC_Irpt_i : out STD_LOGIC;
ip2bus_wrack_i : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
bus2ip_reset : in STD_LOGIC;
irpt_wrack : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
GPIO_intr : in STD_LOGIC;
interrupt_wrce_strb : in STD_LOGIC;
irpt_rdack : in STD_LOGIC;
intr2bus_rdack0 : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ : in STD_LOGIC;
p_8_in : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole : in STD_LOGIC;
bus2ip_rnw : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_interrupt_control;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_interrupt_control is
signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\ : STD_LOGIC;
signal intr2bus_rdack : STD_LOGIC;
signal intr2bus_wrack : STD_LOGIC;
signal irpt_dly1 : STD_LOGIC;
signal irpt_dly2 : STD_LOGIC;
signal \^irpt_wrack_d1\ : STD_LOGIC;
signal \^p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^p_1_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^p_3_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
irpt_wrack_d1 <= \^irpt_wrack_d1\;
p_0_in(0) <= \^p_0_in\(0);
p_1_in(0) <= \^p_1_in\(0);
p_3_in(0) <= \^p_3_in\(0);
\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_intr,
Q => irpt_dly1,
S => bus2ip_reset
);
\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_dly1,
Q => irpt_dly2,
S => bus2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4F4F4F44FF4F4F4"
)
port map (
I0 => irpt_dly2,
I1 => irpt_dly1,
I2 => \^p_3_in\(0),
I3 => p_8_in,
I4 => s_axi_wdata(0),
I5 => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\,
O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^irpt_wrack_d1\,
I1 => Bus_RNW_reg,
O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\,
Q => \^p_3_in\(0),
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2intc_irpt_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^p_3_in\(0),
I1 => \^p_1_in\(0),
I2 => \^p_0_in\(0),
O => IP2INTC_Irpt_i
);
intr2bus_rdack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr2bus_rdack0,
Q => intr2bus_rdack,
R => bus2ip_reset
);
intr2bus_wrack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => interrupt_wrce_strb,
Q => intr2bus_wrack,
R => bus2ip_reset
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FEEE"
)
port map (
I0 => ip2Bus_RdAck_intr_reg_hole,
I1 => intr2bus_rdack,
I2 => bus2ip_rnw,
I3 => GPIO_xferAck_i,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"EFEE"
)
port map (
I0 => ip2Bus_WrAck_intr_reg_hole,
I1 => intr2bus_wrack,
I2 => bus2ip_rnw,
I3 => GPIO_xferAck_i,
O => ip2bus_wrack_i
);
\ip_irpt_enable_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\,
Q => \^p_1_in\(0),
R => bus2ip_reset
);
ipif_glbl_irpt_enable_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\,
Q => \^p_0_in\(0),
R => bus2ip_reset
);
irpt_rdack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_rdack,
Q => irpt_rdack_d1,
R => bus2ip_reset
);
irpt_wrack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_wrack,
Q => \^irpt_wrack_d1\,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is
port (
ip2bus_data : out STD_LOGIC_VECTOR ( 4 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
GPIO_intr : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 4 downto 0 );
Read_Reg_Rst : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[4]_0\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[3]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[2]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[1]_0\ : in STD_LOGIC;
GPIO_DBus_i : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_reset : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC_VECTOR ( 0 to 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 4 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[4]\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal gpio_data_in_xor : STD_LOGIC_VECTOR ( 0 to 4 );
signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 4 );
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
signal or_ints : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
Q(4 downto 0) <= \^q\(4 downto 0);
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus_i(0),
Q => ip2bus_data(4),
R => Read_Reg_Rst
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[1]_0\,
Q => ip2bus_data(3),
R => Read_Reg_Rst
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[2]_0\,
Q => ip2bus_data(2),
R => Read_Reg_Rst
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[3]_0\,
Q => ip2bus_data(1),
R => Read_Reg_Rst
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[4]_0\,
Q => ip2bus_data(0),
R => Read_Reg_Rst
);
\Not_Dual.GEN_INTERRUPT.GPIO_intr_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => or_ints,
Q => GPIO_intr,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(0),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(1),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(2),
Q => p_1_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(3),
Q => p_2_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(4),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[4]\,
R => bus2ip_reset
);
\Not_Dual.INPUT_DOUBLE_REGS3\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
D(4) => gpio_data_in_xor(0),
D(3) => gpio_data_in_xor(1),
D(2) => gpio_data_in_xor(2),
D(1) => gpio_data_in_xor(3),
D(0) => gpio_data_in_xor(4),
Q(4 downto 0) => \^q\(4 downto 0),
gpio_io_i(4 downto 0) => gpio_io_i(4 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(4) => gpio_io_i_d2(0),
scndry_vect_out(3) => gpio_io_i_d2(1),
scndry_vect_out(2) => gpio_io_i_d2(2),
scndry_vect_out(1) => gpio_io_i_d2(3),
scndry_vect_out(0) => gpio_io_i_d2(4)
);
\Not_Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(0),
Q => \^q\(4),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(1),
Q => \^q\(3),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(2),
Q => \^q\(2),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(3),
Q => \^q\(1),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(4),
Q => \^q\(0),
R => '0'
);
\Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(4),
Q => gpio_io_o(4),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(3),
Q => gpio_io_o(3),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(2),
Q => gpio_io_o(2),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(1),
Q => gpio_io_o(1),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(0),
Q => gpio_io_o(0),
R => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(4),
Q => gpio_io_t(4),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(3),
Q => gpio_io_t(3),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(2),
Q => gpio_io_t(2),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(1),
Q => gpio_io_t(1),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(0),
Q => gpio_io_t(0),
S => bus2ip_reset
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => bus2ip_reset
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => \^gpio_xferack_reg\,
I1 => \^gpio_xferack_i\,
I2 => bus2ip_cs(0),
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => bus2ip_reset
);
or_reduce: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => p_1_in,
I1 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[4]\,
I2 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\,
I3 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\,
I4 => p_2_in,
O => or_ints
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
port (
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[4]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
Read_Reg_Rst : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]_0\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 5 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
\ip2bus_data_i_D1_reg[0]_1\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^not_dual.gpio_oe_reg[0]\ : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 );
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal \p_0_out__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 8 downto 2 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \bus2ip_addr_i[4]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair4";
begin
\Not_Dual.gpio_OE_reg[0]\ <= \^not_dual.gpio_oe_reg[0]\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(1),
I1 => state(0),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
port map (
D(4 downto 0) => D(4 downto 0),
E(0) => E(0),
GPIO_DBus_i(0) => GPIO_DBus_i(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\,
\Not_Dual.gpio_Data_In_reg[0]\(4 downto 0) => Q(4 downto 0),
\Not_Dual.gpio_Data_Out_reg[0]\(0) => \Not_Dual.gpio_Data_Out_reg[0]\(0),
\Not_Dual.gpio_Data_Out_reg[4]\ => \Not_Dual.gpio_Data_Out_reg[4]\,
Q(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
Read_Reg_Rst => Read_Reg_Rst,
\bus2ip_addr_i_reg[8]\(6) => bus2ip_addr(0),
\bus2ip_addr_i_reg[8]\(5) => bus2ip_addr(1),
\bus2ip_addr_i_reg[8]\(4) => bus2ip_addr(2),
\bus2ip_addr_i_reg[8]\(3) => bus2ip_addr(3),
\bus2ip_addr_i_reg[8]\(2) => bus2ip_addr(4),
\bus2ip_addr_i_reg[8]\(1) => bus2ip_addr(5),
\bus2ip_addr_i_reg[8]\(0) => bus2ip_addr(6),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw_i_reg => \^not_dual.gpio_oe_reg[0]\,
gpio_io_t(4 downto 0) => gpio_io_t(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_data(0) => ip2bus_data(0),
\ip2bus_data_i_D1_reg[0]\ => \ip2bus_data_i_D1_reg[0]\,
\ip2bus_data_i_D1_reg[0]_0\(1 downto 0) => \ip2bus_data_i_D1_reg[0]_0\(1 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => \ip_irpt_enable_reg_reg[0]\,
\ip_irpt_enable_reg_reg[0]_0\ => \ip_irpt_enable_reg_reg[0]_0\,
ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
p_0_in(0) => p_0_in(0),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0),
s_axi_wready => \^s_axi_wready\,
start2 => start2
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(0),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(0),
O => \p_1_in__0\(2)
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(1),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(1),
O => \p_1_in__0\(3)
);
\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(2),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(2),
O => \p_1_in__0\(4)
);
\bus2ip_addr_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(3),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(3),
O => \p_1_in__0\(5)
);
\bus2ip_addr_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(4),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(4),
O => \p_1_in__0\(6)
);
\bus2ip_addr_i[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(5),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(5),
O => \p_1_in__0\(7)
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(6),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(6),
O => \p_1_in__0\(8)
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(2),
Q => bus2ip_addr(6),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(3),
Q => bus2ip_addr(5),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(4),
Q => bus2ip_addr(4),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(5),
Q => bus2ip_addr(3),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(6),
Q => bus2ip_addr(2),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(7),
Q => bus2ip_addr(1),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(8),
Q => bus2ip_addr(0),
R => bus2ip_reset
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => s_axi_arvalid,
I1 => state(0),
I2 => state(1),
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => bus2ip_rnw_i06_out,
Q => \^not_dual.gpio_oe_reg[0]\,
R => bus2ip_reset
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state[1]_i_2_n_0\,
I2 => state(1),
I3 => state(0),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => bus2ip_reset
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1000FFFF10000000"
)
port map (
I0 => state(1),
I1 => s_axi_arvalid,
I2 => s_axi_wvalid,
I3 => s_axi_awvalid,
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
I4 => state(1),
I5 => state(0),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => bus2ip_reset
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => bus2ip_reset
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(0),
Q => s_axi_rdata(0),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(1),
Q => s_axi_rdata(1),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(2),
Q => s_axi_rdata(2),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(5),
Q => s_axi_rdata(5),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(3),
Q => s_axi_rdata(3),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(4),
Q => s_axi_rdata(4),
R => bus2ip_reset
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => bus2ip_reset
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(0),
I4 => state(1),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => bus2ip_reset
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FFFAACC"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_arvalid,
I2 => \state[1]_i_2_n_0\,
I3 => state(1),
I4 => state(0),
O => \p_0_out__0\(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2E2E2E2ECCCCFFCC"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(1),
I2 => \state[1]_i_2_n_0\,
I3 => \state[1]_i_3_n_0\,
I4 => s_axi_arvalid,
I5 => state(0),
O => \p_0_out__0\(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \p_0_out__0\(0),
Q => state(0),
R => bus2ip_reset
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \p_0_out__0\(1),
Q => state(1),
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
port (
p_8_in : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
Read_Reg_Rst : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 5 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
\ip2bus_data_i_D1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
port map (
D(4 downto 0) => D(4 downto 0),
E(0) => E(0),
GPIO_DBus_i(0) => GPIO_DBus_i(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\,
\Not_Dual.gpio_Data_Out_reg[0]\(0) => \Not_Dual.gpio_Data_Out_reg[0]\(0),
\Not_Dual.gpio_Data_Out_reg[4]\ => bus2ip_cs(0),
\Not_Dual.gpio_OE_reg[0]\ => bus2ip_rnw,
Q(4 downto 0) => Q(4 downto 0),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_reset => bus2ip_reset,
gpio_io_t(4 downto 0) => gpio_io_t(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_data(0) => ip2bus_data(0),
\ip2bus_data_i_D1_reg[0]\ => p_8_in,
\ip2bus_data_i_D1_reg[0]_0\(1 downto 0) => \ip2bus_data_i_D1_reg[0]\(1 downto 0),
\ip2bus_data_i_D1_reg[0]_1\(5 downto 0) => \ip2bus_data_i_D1_reg[0]_0\(5 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => Bus_RNW_reg,
\ip_irpt_enable_reg_reg[0]_0\ => \ip_irpt_enable_reg_reg[0]\,
ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(0),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(6 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(6 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(5 downto 0) => s_axi_rdata(5 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 1;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 5;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 1;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "LOGICORE";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_14 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_15 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_16 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_18 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_19 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_27 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_29 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_31 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_32 : STD_LOGIC;
signal DBus_Reg : STD_LOGIC_VECTOR ( 0 to 4 );
signal GPIO_DBus_i : STD_LOGIC_VECTOR ( 27 to 27 );
signal GPIO_intr : STD_LOGIC;
signal GPIO_xferAck_i : STD_LOGIC;
signal IP2INTC_Irpt_i : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\ : STD_LOGIC;
signal Read_Reg_Rst : STD_LOGIC;
signal bus2ip_cs : STD_LOGIC_VECTOR ( 1 to 1 );
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_reset_i_1_n_0 : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 4 );
signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal gpio_xferAck_Reg : STD_LOGIC;
signal interrupt_wrce_strb : STD_LOGIC;
signal intr2bus_rdack0 : STD_LOGIC;
signal intr_rd_ce_or_reduce : STD_LOGIC;
signal intr_wr_ce_or_reduce : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole_d1 : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole_d1 : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 27 to 31 );
signal ip2bus_data_i : STD_LOGIC_VECTOR ( 31 to 31 );
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 0 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal irpt_rdack : STD_LOGIC;
signal irpt_rdack_d1 : STD_LOGIC;
signal irpt_wrack : STD_LOGIC;
signal irpt_wrack_d1 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 31 to 31 );
signal p_0_out : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_3_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
attribute sigis : string;
attribute sigis of \INTR_CTRLR_GEN.ip2intc_irpt_reg\ : label is "INTR_LEVEL_HIGH";
begin
gpio2_io_o(31) <= \<const0>\;
gpio2_io_o(30) <= \<const0>\;
gpio2_io_o(29) <= \<const0>\;
gpio2_io_o(28) <= \<const0>\;
gpio2_io_o(27) <= \<const0>\;
gpio2_io_o(26) <= \<const0>\;
gpio2_io_o(25) <= \<const0>\;
gpio2_io_o(24) <= \<const0>\;
gpio2_io_o(23) <= \<const0>\;
gpio2_io_o(22) <= \<const0>\;
gpio2_io_o(21) <= \<const0>\;
gpio2_io_o(20) <= \<const0>\;
gpio2_io_o(19) <= \<const0>\;
gpio2_io_o(18) <= \<const0>\;
gpio2_io_o(17) <= \<const0>\;
gpio2_io_o(16) <= \<const0>\;
gpio2_io_o(15) <= \<const0>\;
gpio2_io_o(14) <= \<const0>\;
gpio2_io_o(13) <= \<const0>\;
gpio2_io_o(12) <= \<const0>\;
gpio2_io_o(11) <= \<const0>\;
gpio2_io_o(10) <= \<const0>\;
gpio2_io_o(9) <= \<const0>\;
gpio2_io_o(8) <= \<const0>\;
gpio2_io_o(7) <= \<const0>\;
gpio2_io_o(6) <= \<const0>\;
gpio2_io_o(5) <= \<const0>\;
gpio2_io_o(4) <= \<const0>\;
gpio2_io_o(3) <= \<const0>\;
gpio2_io_o(2) <= \<const0>\;
gpio2_io_o(1) <= \<const0>\;
gpio2_io_o(0) <= \<const0>\;
gpio2_io_t(31) <= \<const1>\;
gpio2_io_t(30) <= \<const1>\;
gpio2_io_t(29) <= \<const1>\;
gpio2_io_t(28) <= \<const1>\;
gpio2_io_t(27) <= \<const1>\;
gpio2_io_t(26) <= \<const1>\;
gpio2_io_t(25) <= \<const1>\;
gpio2_io_t(24) <= \<const1>\;
gpio2_io_t(23) <= \<const1>\;
gpio2_io_t(22) <= \<const1>\;
gpio2_io_t(21) <= \<const1>\;
gpio2_io_t(20) <= \<const1>\;
gpio2_io_t(19) <= \<const1>\;
gpio2_io_t(18) <= \<const1>\;
gpio2_io_t(17) <= \<const1>\;
gpio2_io_t(16) <= \<const1>\;
gpio2_io_t(15) <= \<const1>\;
gpio2_io_t(14) <= \<const1>\;
gpio2_io_t(13) <= \<const1>\;
gpio2_io_t(12) <= \<const1>\;
gpio2_io_t(11) <= \<const1>\;
gpio2_io_t(10) <= \<const1>\;
gpio2_io_t(9) <= \<const1>\;
gpio2_io_t(8) <= \<const1>\;
gpio2_io_t(7) <= \<const1>\;
gpio2_io_t(6) <= \<const1>\;
gpio2_io_t(5) <= \<const1>\;
gpio2_io_t(4) <= \<const1>\;
gpio2_io_t(3) <= \<const1>\;
gpio2_io_t(2) <= \<const1>\;
gpio2_io_t(1) <= \<const1>\;
gpio2_io_t(0) <= \<const1>\;
gpio_io_t(4 downto 0) <= \^gpio_io_t\(4 downto 0);
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \^s_axi_rdata\(31);
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4 downto 0) <= \^s_axi_rdata\(4 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
D(4) => DBus_Reg(0),
D(3) => DBus_Reg(1),
D(2) => DBus_Reg(2),
D(1) => DBus_Reg(3),
D(0) => DBus_Reg(4),
E(0) => AXI_LITE_IPIF_I_n_18,
GPIO_DBus_i(0) => GPIO_DBus_i(27),
GPIO_xferAck_i => GPIO_xferAck_i,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => AXI_LITE_IPIF_I_n_27,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => AXI_LITE_IPIF_I_n_29,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ => AXI_LITE_IPIF_I_n_16,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ => AXI_LITE_IPIF_I_n_15,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ => AXI_LITE_IPIF_I_n_14,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ => AXI_LITE_IPIF_I_n_13,
\Not_Dual.gpio_Data_Out_reg[0]\(0) => AXI_LITE_IPIF_I_n_19,
Q(4) => gpio_Data_In(0),
Q(3) => gpio_Data_In(1),
Q(2) => gpio_Data_In(2),
Q(1) => gpio_Data_In(3),
Q(0) => gpio_Data_In(4),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_cs(0) => bus2ip_cs(1),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio_io_t(4 downto 0) => \^gpio_io_t\(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_data(0) => ip2bus_data(31),
\ip2bus_data_i_D1_reg[0]\(1) => p_0_out(0),
\ip2bus_data_i_D1_reg[0]\(0) => ip2bus_data_i(31),
\ip2bus_data_i_D1_reg[0]_0\(5) => ip2bus_data_i_D1(0),
\ip2bus_data_i_D1_reg[0]_0\(4) => ip2bus_data_i_D1(27),
\ip2bus_data_i_D1_reg[0]_0\(3) => ip2bus_data_i_D1(28),
\ip2bus_data_i_D1_reg[0]_0\(2) => ip2bus_data_i_D1(29),
\ip2bus_data_i_D1_reg[0]_0\(1) => ip2bus_data_i_D1(30),
\ip2bus_data_i_D1_reg[0]_0\(0) => ip2bus_data_i_D1(31),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => AXI_LITE_IPIF_I_n_31,
ipif_glbl_irpt_enable_reg_reg => AXI_LITE_IPIF_I_n_32,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(31),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
p_8_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(8 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(8 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(5) => \^s_axi_rdata\(31),
s_axi_rdata(4 downto 0) => \^s_axi_rdata\(4 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(9 downto 5) => s_axi_wdata(31 downto 27),
s_axi_wdata(4 downto 0) => s_axi_wdata(4 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_interrupt_control
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ => AXI_LITE_IPIF_I_n_32,
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\ => AXI_LITE_IPIF_I_n_31,
GPIO_intr => GPIO_intr,
GPIO_xferAck_i => GPIO_xferAck_i,
IP2INTC_Irpt_i => IP2INTC_Irpt_i,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
ip2Bus_RdAck_intr_reg_hole => ip2Bus_RdAck_intr_reg_hole,
ip2Bus_WrAck_intr_reg_hole => ip2Bus_WrAck_intr_reg_hole,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i => ip2bus_wrack_i,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(31),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
p_8_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(0) => s_axi_wdata(0)
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_rd_ce_or_reduce,
Q => ip2Bus_RdAck_intr_reg_hole_d1,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_LITE_IPIF_I_n_27,
Q => ip2Bus_RdAck_intr_reg_hole,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_wr_ce_or_reduce,
Q => ip2Bus_WrAck_intr_reg_hole_d1,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_LITE_IPIF_I_n_29,
Q => ip2Bus_WrAck_intr_reg_hole,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2intc_irpt_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => IP2INTC_Irpt_i,
Q => ip2intc_irpt,
R => bus2ip_reset
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
bus2ip_reset_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => bus2ip_reset_i_1_n_0
);
bus2ip_reset_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_reset_i_1_n_0,
Q => bus2ip_reset,
R => '0'
);
gpio_core_1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
port map (
D(4) => DBus_Reg(0),
D(3) => DBus_Reg(1),
D(2) => DBus_Reg(2),
D(1) => DBus_Reg(3),
D(0) => DBus_Reg(4),
E(0) => AXI_LITE_IPIF_I_n_19,
GPIO_DBus_i(0) => GPIO_DBus_i(27),
GPIO_intr => GPIO_intr,
GPIO_xferAck_i => GPIO_xferAck_i,
\Not_Dual.gpio_OE_reg[1]_0\ => AXI_LITE_IPIF_I_n_16,
\Not_Dual.gpio_OE_reg[2]_0\ => AXI_LITE_IPIF_I_n_15,
\Not_Dual.gpio_OE_reg[3]_0\ => AXI_LITE_IPIF_I_n_14,
\Not_Dual.gpio_OE_reg[4]_0\ => AXI_LITE_IPIF_I_n_13,
Q(4) => gpio_Data_In(0),
Q(3) => gpio_Data_In(1),
Q(2) => gpio_Data_In(2),
Q(1) => gpio_Data_In(3),
Q(0) => gpio_Data_In(4),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_cs(0) => bus2ip_cs(1),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw_i_reg(0) => AXI_LITE_IPIF_I_n_18,
gpio_io_i(4 downto 0) => gpio_io_i(4 downto 0),
gpio_io_o(4 downto 0) => gpio_io_o(4 downto 0),
gpio_io_t(4 downto 0) => \^gpio_io_t\(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_data(4) => ip2bus_data(27),
ip2bus_data(3) => ip2bus_data(28),
ip2bus_data(2) => ip2bus_data(29),
ip2bus_data(1) => ip2bus_data(30),
ip2bus_data(0) => ip2bus_data(31),
s_axi_aclk => s_axi_aclk
);
\ip2bus_data_i_D1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(0),
Q => ip2bus_data_i_D1(0),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(27),
Q => ip2bus_data_i_D1(27),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(28),
Q => ip2bus_data_i_D1(28),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(29),
Q => ip2bus_data_i_D1(29),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_i(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_wrack_i,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_axi_gpio_1_1,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_gpio,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_gpio_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 1;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 5;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 1;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
port map (
gpio2_io_i(31 downto 0) => B"00000000000000000000000000000000",
gpio2_io_o(31 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(31 downto 0),
gpio2_io_t(31 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(31 downto 0),
gpio_io_i(4 downto 0) => gpio_io_i(4 downto 0),
gpio_io_o(4 downto 0) => NLW_U0_gpio_io_o_UNCONNECTED(4 downto 0),
gpio_io_t(4 downto 0) => NLW_U0_gpio_io_t_UNCONNECTED(4 downto 0),
ip2intc_irpt => ip2intc_irpt,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | e7d2e33da3385170757f18ebc8eece9a | 0.578704 | 2.570732 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/can/can_mc.vhd | 1 | 6,345 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_oc
-- File: can_oc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB interface for the OpenCores CAN MAC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.can.all;
entity can_mc is
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
ncores : integer range 1 to 8 := 1;
sepirq : integer range 0 to 1 := 0;
syncrst : integer range 0 to 2 := 0;
ft : integer range 0 to 1 := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(0 to 7);
can_txo : out std_logic_vector(0 to 7)
);
attribute sync_set_reset of resetn : signal is "true";
end;
architecture rtl of can_mc is
constant REVISION : amba_version_type := ncores-1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_CANAHB, 0, REVISION, irq),
4 => ahb_iobar(ioaddr, iomask), others => zero32);
type ahbregs is record
hsel : std_ulogic;
hwrite : std_ulogic;
hwrite2 : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(10 downto 0);
hwdata : std_logic_vector(7 downto 0);
herr : std_ulogic;
hready : std_ulogic;
ws : std_logic_vector(1 downto 0);
irqi : std_logic_vector(ncores-1 downto 0);
irqo : std_logic_vector(ncores-1 downto 0);
end record;
subtype cdata is std_logic_vector(7 downto 0);
type cdataarr is array (0 to 7) of cdata;
signal data_out : cdataarr;
signal reset : std_logic;
signal irqo : std_logic_vector(ncores-1 downto 0);
signal cs : std_logic_vector(7 downto 0);
signal vcc, gnd : std_ulogic;
signal r, rin : ahbregs;
--attribute sync_set_reset : string;
attribute sync_set_reset of reset : signal is "true";
begin
gnd <= '0'; vcc <= '1'; reset <= not resetn;
comb : process(ahbsi, r, resetn, data_out, irqo)
variable v : ahbregs;
variable hresp : std_logic_vector(1 downto 0);
variable lcs, dataout : std_logic_vector(7 downto 0);
variable irqvec : std_logic_vector(NAHBIRQ-1 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
begin
v := r;
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
if (r.hsel = '1' ) and (r.ws /= "11") then v.ws := r.ws + 1; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(slvndx);
v.haddr := ahbsi.haddr(10 downto 0);
v.htrans := ahbsi.htrans;
v.hwrite := ahbsi.hwrite;
v.herr := orv(ahbsi.hsize) and ahbsi.hwrite;
v.ws := "00";
end if;
v.hready := (r.hsel and r.ws(1) and not r.ws(0)) or not resetn
or (ahbsi.hready and not ahbsi.htrans(1)) or not v.hsel;
v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and not r.herr;
if (r.herr and r.ws(1)) = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
case r.haddr(1 downto 0) is
when "00" => v.hwdata := hwdata(31 downto 24);
when "01" => v.hwdata := hwdata(23 downto 16);
when "10" => v.hwdata := hwdata(15 downto 8);
when others => v.hwdata := hwdata(7 downto 0);
end case;
if ncores > 1 then
if r.hsel = '1' then lcs := decode(r.haddr(10 downto 8));
else lcs := (others => '0'); end if;
dataout := data_out(conv_integer(r.haddr(10 downto 8)));
else dataout := data_out(0); lcs := "0000000" & r.hsel; end if;
-- Interrupt goes to low when appeard and is normal high
-- but the irq controller from leon is active high and the interrupt should appear only
-- for 1 Clk cycle,
v.irqi := irqo; v.irqo:= (r.irqi and not irqo);
irqvec := (others => '0');
if sepirq = 1 then irqvec(ncores-1+irq downto irq) := r.irqo;
else irqvec(irq) := orv(r.irqo); end if;
ahbso.hirq <= irqvec;
ahbso.hrdata <= ahbdrivedata(dataout);
cs <= lcs;
ahbso.hresp <= hresp; rin <= v;
end process;
reg : process(clk)
begin if clk'event and clk = '1' then r <= rin; end if; end process;
cgen : for i in 0 to 7 generate
c0 : if i < ncores generate
cmod : can_mod generic map (memtech, syncrst, ft)
port map (reset, clk, cs(i), r.hwrite2, r.haddr(7 downto 0), r.hwdata,
data_out(i), irqo(i), can_rxi(i), can_txo(i), ahbsi.testen);
end generate;
c1 : if i >= ncores generate
can_txo(i) <= '0'; data_out(i) <= (others => '0');
end generate;
end generate;
ahbso.hconfig <= hconfig;
ahbso.hindex <= slvndx;
ahbso.hsplit <= (others => '0');
ahbso.hready <= r.hready;
-- pragma translate_off
bootmsg : report_version
generic map (
"can_oc" & tost(slvndx) &
": SJA1000 Compatible CAN MAC, #cores " & tost(REVISION+1) & ", irq " & tost(irq));
-- pragma translate_on
end;
| gpl-2.0 | 879fd3bfb2afa3854563d361327dd623 | 0.591174 | 3.480527 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/outpad.vhd | 1 | 5,685 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: outpad
-- File: outpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity outpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of outpad is
signal padx, gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
gen0 : if has_pads(tech) = 0 generate
pad <= i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when slew = 0 else i;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
pa3 : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
um : if (tech = umc) generate
x0 : umc_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
saed : if (tech = saed32) generate
x0 : saed32_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
dar : if (tech = dare) generate
x0 : dare_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
ihprh : if (tech = ihp25rh) generate
x0 : ihp25rh_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength) port map (padx, i, gnd, open);
pad <= padx;
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, vcc);
end generate;
nex : if (tech = easic90) generate
x0 : nextreme_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, vcc);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_outpad generic map (level, slew, voltage, strength)
port map(pad, i, cfgi(0), cfgi(1),
cfgi(19 downto 15), cfgi(14 downto 10), cfgi(9 downto 6), cfgi(5 downto 2));
end generate;
ut90nhbd : if (tech = ut90) generate
x0 : ut90nhbd_outpad generic map (level, slew, voltage, strength)
port map(pad, i, cfgi(0));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity outpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12; width : integer := 1);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of outpadv is
begin
v : for j in width-1 downto 0 generate
x0 : outpad generic map (tech, level, slew, voltage, strength)
port map (pad(j), i(j), cfgi);
end generate;
end;
| gpl-2.0 | c2a8ed408e11a2913e14e00f0fff5cf0 | 0.643096 | 3.548689 | false | false | false | false |
khaledhassan/vhdl-examples | adder_tree/adder_tree_tb.vhd | 1 | 2,505 | -- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Testbench for the generic adder tree.
library ieee;
use ieee.std_logic_1164.all;
entity adder_tree_tb is
end adder_tree_tb;
architecture TB of adder_tree_tb is
signal rst, clk : std_logic;
signal input : std_logic_vector(19 downto 0);
signal output : std_logic_vector(3 downto 0);
constant clk_period : time := 20 ns; -- for a 50MHz clock
signal valid, valid_out : std_logic;
begin
-- Instantiate the Unit Under Test (UUT)
UUT : entity work.adder_tree
generic map (
WIDTH => 4,
TOPWIDTH => 5
)
port map (
rst => rst,
clk => clk,
input => input,
output => output,
valid_in => valid,
valid_out => valid_out
);
-- Clock process
process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
process
begin
--input <= "00111011";
--input <= "000100100100";
input <= "10010001001001001000";
valid <= '1';
rst <= '1';
wait for clk_period;
rst <= '0';
wait for clk_period;
valid <= '0';
wait;
end process;
end TB;
| mit | 75632fda98eb941b6f91329896755b4b | 0.635529 | 4.224283 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/pci/grpci1/pci_mtf.vhd | 1 | 99,259 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci_mtf
-- File: pci_mtf.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Alf Vaerneus - Gaisler Research
-- Description: PCI master and target interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
use gaisler.pcilib.all;
entity pci_mtf is
generic (
memtech : integer := DEFMEMTECH;
hmstndx : integer := 0;
dmamst : integer := NAHBMST;
readpref : integer := 0;
abits : integer := 21;
dmaabits : integer := 26;
fifodepth : integer := 3; -- FIFO depth
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
master : integer := 1; -- Enable PCI Master
hslvndx : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
irq : integer := 0;
irqmask : integer := 0;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
oepol : integer := 0;
endian : integer := 0; -- 0 little, 1 big
class_code: integer := 16#0B4000#;
rev : integer := 0;
scanen : integer := 0;
syncrst : integer := 0;
hostrst : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
attribute sync_set_reset of rst : signal is "true";
end;
architecture rtl of pci_mtf is
function byte_twist(di : in std_logic_vector(31 downto 0); enable : in std_logic) return std_logic_vector is
variable do : std_logic_vector(31 downto 0);
begin
if enable = '1' then
for i in 0 to 3 loop
do(31-i*8 downto 24-i*8) := di(31-(3-i)*8 downto 24-(3-i)*8);
end loop;
else
do := di;
end if;
return do;
end function;
function nr_of_1(di : in integer) return integer is
variable vec : unsigned(31 downto 0);
variable ones : integer;
begin
ones := 0;
vec := to_unsigned(di,32);
for i in 0 to 31 loop
if vec(i) = '1' then
ones := ones + 1;
end if;
end loop;
return ones;
end function;
constant REVISION : amba_version_type := rev;
constant CSYNC : integer := nsync-1;
constant HADDR_WIDTH : integer := 28;
constant MADDR_WIDTH : integer := abits;
constant DMAMADDR_WIDTH : integer := dmaabits;
constant FIFO_DEPTH : integer := fifodepth;
constant FIFO_FULL : std_logic_vector(FIFO_DEPTH - 2 downto 0) := (others => '1');
constant FIFO_DATA_BITS : integer := 32; -- One valid bit
constant NO_CPU_REGS : integer := 6; -- Number of CPU sync registers (pci->ahb)
constant NO_PCI_REGS : integer := 6; -- Number of PCI sync registers (ahb->pci)
constant HMASK_WIDTH : integer := nr_of_1(hmask);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCIFBRG, 0, REVISION, irq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCIFBRG, 0, REVISION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
5 => ahb_iobar (ioaddr, 16#E00#),
others => zero32);
type pci_input_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_logic;
devsel : std_logic;
idsel : std_logic;
trdy : std_logic;
irdy : std_logic;
par : std_logic;
stop : std_logic;
gnt : std_logic;
host : std_logic;
end record;
type pci_fifo_in_type is record
ren : std_logic;
raddr : std_logic_vector(FIFO_DEPTH - 1 downto 0);
wen : std_logic;
waddr : std_logic_vector(FIFO_DEPTH - 1 downto 0);
wdata : std_logic_vector(FIFO_DATA_BITS - 1 downto 0);
end record;
type pci_fifo_out_type is record
rdata : std_logic_vector(FIFO_DATA_BITS - 1 downto 0);
end record;
type fifo_type is record
side : std_logic; -- Owner access side. Receiver accesses the other side
raddr : std_logic_vector(FIFO_DEPTH - 2 downto 0);
waddr : std_logic_vector(FIFO_DEPTH - 2 downto 0);
end record;
type pci_target_state_type is (idle, b_busy, s_data, backoff, turn_ar);
type pci_master_state_type is (idle, addr, m_data, turn_ar, s_tar, dr_bus);
type pci_master_fifo_state_type is (idle, addr, incr, last1, sync, t_retry, ttermwd, ttermnd, abort, done, wdone);
type pci_target_type is record
state : pci_target_state_type;
cnt : std_logic_vector(2 downto 0);
csel : std_logic; -- Configuration chip select
msel : std_logic; -- Memory hit
barsel : std_logic; -- Memory hit
psel : std_logic; -- Page hit
addr : std_logic_vector(31 downto 0);
laddr : std_logic_vector(31 downto 0);
lsize : std_logic_vector(1 downto 0);
lcbe : std_logic_vector(3 downto 0);
lwrite : std_logic;
lburst : std_logic;
lmult : std_logic;
mult : std_logic;
read : std_logic; -- PCI target read
burst : std_logic;
pending : std_logic;
wdel : std_logic;
last : std_logic;
fifo : fifo_type;
trdy_del : std_logic; -- (delay trdy to send last word in fifo) bug fix ***
thold : std_logic; -- hold target while last word is transfered
thold2 : std_logic; -- hold target while last word is transfered
ready_del: std_logic; -- delayed ready
detectperr : std_logic_vector(1 downto 0);
end record;
type pci_master_type is record
state : pci_master_state_type;
fstate : pci_master_fifo_state_type;
cnt : std_logic_vector(2 downto 0);
ltim : std_logic_vector(7 downto 0); -- Latency timer
request : std_logic;
hwrite : std_logic;
stop_req : std_logic;
last : std_logic;
valid : std_logic;
split : std_logic;
first : std_logic;
firstw : std_logic;
fifo : fifo_type;
rmdone : std_logic; -- bug fix ***
stopframe: std_logic;
lto : std_logic; -- bug fix latency timer timeout
detectperr : std_logic_vector(1 downto 0);
end record;
type pci_sync_regs is array (0 to NO_PCI_REGS - 1) of std_logic_vector(csync downto 0);
type pci_reg_type is record
pci : pci_sigs_type;
noe_par : std_logic;
noe_ad : std_logic;
noe_ctrl : std_logic;
noe_cbe : std_logic;
noe_frame : std_logic;
noe_irdy : std_logic;
noe_req : std_logic;
noe_perr : std_logic;
noe_serr : std_logic;
m : pci_master_type;
t : pci_target_type;
comm : pci_config_command_type; -- Command register
stat : pci_config_status_type; -- Status register
bar0 : std_logic_vector(31 downto MADDR_WIDTH); -- Base Address register 0
bar1 : std_logic_vector(31 downto DMAMADDR_WIDTH); -- Base Address register 1
bar0_conf : std_logic;
bar1_conf : std_logic;
page : std_logic_vector(31 downto MADDR_WIDTH-1); -- AHB page
bt_enable : std_logic; -- Byte twist enable, page0 bit 0
ltim : std_logic_vector(7 downto 0); -- Latency timer
cline : std_logic_vector(7 downto 0); -- Cache Line Size
intline : std_logic_vector(7 downto 0); -- Interrupt Line
syncs : pci_sync_regs;
trans : std_logic_vector(NO_CPU_REGS - 1 downto 0);
end record;
type cpu_master_state_type is (idle, cbe_prepare, write, read_w, read, stop);
type cpu_slave_state_type is (idle, w_wait, t_data, r_hold, r_wait, w_done, t_done);
type cpu_master_type is record
state : cpu_master_state_type; -- AMBA master state machine
dmaddr : std_logic_vector(31 downto 0);
fifo : fifo_type;
cbe_fifo : fifo_type;
cur_cbe : std_logic_vector(3 downto 0);
cbe_prep_cnt : std_ulogic;
read_half : std_logic;
last_side_wr : std_ulogic;
end record;
type cpu_slave_type is record
state : cpu_slave_state_type; -- AMBA slave state machine
maddr : std_logic_vector(31 downto 0);
mdata : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0);
perror : std_logic;
hresp : std_logic_vector(1 downto 0);
hready : std_logic;
htrans : std_logic_vector(1 downto 0);
hmaster : std_logic_vector(3 downto 0);
pcicomm : std_logic_vector(3 downto 0);
hold : std_logic;
fifos_write : std_logic;
fifo : fifo_type;
last_side : std_logic;
hold_retry : std_logic_vector(1 downto 0); -- Used to detect non-burst accesses in r_hold state -- ***
end record;
type cpu_sync_regs is array (0 to NO_CPU_REGS - 1) of std_logic_vector(csync downto 0);
type cpu_reg_type is record
m : cpu_master_type;
s : cpu_slave_type;
syncs : cpu_sync_regs;
trans : std_logic_vector(NO_PCI_REGS - 1 downto 0);
pciba : std_logic_vector(HMASK_WIDTH-1 downto 0);
cfto : std_logic;
wcomm : std_logic;
rcomm : std_logic;
werr : std_logic;
clscnt : std_logic_vector(8 downto 0);
dmapage : std_logic_vector(31 downto DMAMADDR_WIDTH); -- DMA page
ioba : std_logic_vector(15 downto 0);
bus_nr : std_logic_vector(3 downto 0);
irq : std_logic_vector(9 downto 0);
irq_en : std_logic_vector(9 downto 0);
pirq : std_logic_vector(0 to 1);
end record;
signal clk_int : std_logic;
signal pr : pci_input_type;
signal r, rin : pci_reg_type;
signal r2, r2in : cpu_reg_type;
signal dmai : pci_ahb_dma_in_type;
signal dmao : pci_ahb_dma_out_type;
signal fifo1i, fifo2i, fifo3i, fifo4i, cbe_fifoi : pci_fifo_in_type;
signal fifo1o, fifo2o, fifo3o, fifo4o, cbe_fifoo : pci_fifo_out_type;
signal roe_ad, rioe_ad, ad, adin : std_logic_vector(31 downto 0);
signal pcirst : std_logic;
signal prrst : std_logic;
signal pcirstin : std_logic;
--attribute sync_set_reset : string;
attribute sync_set_reset of prrst : signal is "true";
attribute async_set_reset : string;
attribute async_set_reset of pcirst : signal is "true";
attribute sync_set_reset of pcirst : signal is "true";
attribute syn_preserve : boolean;
attribute syn_preserve of roe_ad : signal is true;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ad : signal is "registers";
attribute syn_preserve of ad : signal is true;
begin
-----------------------------------------------
-- Back-end state machine (AHB clock domain) --
-----------------------------------------------
comb : process (rst, r2, r, dmao, ahbsi, fifo2o, fifo4o, apbi, pr,
cbe_fifoo, dmai, pcii)
variable vdmai : pci_ahb_dma_in_type;
variable v : cpu_reg_type;
variable hready : std_logic;
variable hresp, hsize : std_logic_vector(1 downto 0);
variable p_done, wsdone, wmdone, rtdone, rmdone : std_logic;
variable pstart, habort, hstart_ack : std_logic;
variable hstart, pabort, pstart_ack, pcidc : std_logic;
variable i : integer range 0 to NO_CPU_REGS;
variable fifom_write, fifos_write : std_logic;
variable prdata : std_logic_vector(31 downto 0);
variable wmvalid, wsvalid, rmvalid, rsvalid, burst_read, hold : std_logic;
variable fifors_limit, fifows_limit,fiform_limit, fifowm_limit, fifows_stop : std_logic;
variable comp, request, s_read_side, m_read_side : std_logic;
variable ahb_access : std_logic; -- *** access control fix
variable start, single_access : std_logic;
variable next_cbe : std_logic_vector(3 downto 0);
variable byteaddr : std_logic_vector(1 downto 0);
begin
v := r2;
vdmai.start := '0';
vdmai.irq := '0'; vdmai.busy := '0'; vdmai.burst := '1';
vdmai.wdata := fifo2o.rdata(31 downto 0); vdmai.write := r.t.lwrite;
rmvalid := '1'; wmvalid := '1'; request := '0'; hold := '0';
rsvalid := '1'; wsvalid := '1'; burst_read := '0';
hready := '1'; hresp := HRESP_OKAY; hsize := "10";
fifom_write := '0'; v.s.fifos_write := '0';
comp := '0'; prdata := (others => '0'); v.s.hold := '0';
s_read_side := not r.m.fifo.side; m_read_side := not r.t.fifo.side;
ahb_access := '0'; -- *** access control fix
-- Synch registers
pstart := r2.trans(0);
habort := r2.trans(1);
hstart_ack := r2.trans(2);
-- fifows_limit := r2.trans(3);
wsdone := r2.trans(4);
wmdone := r2.trans(5);
for i in 0 to NO_CPU_REGS - 1 loop
v.syncs(i)(csync) := r.trans(i);
if csync /= 0 then v.syncs(i)(0) := r2.syncs(i)(csync); end if;
end loop;
hstart := r2.syncs(0)(0);
pabort := r2.syncs(1)(0);
pstart_ack := r2.syncs(2)(0);
pcidc := r2.syncs(3)(0);
rtdone := r2.syncs(4)(0);
rmdone := r2.syncs(5)(0);
p_done := pstart_ack or pabort;
-- Interrupts
if irq /= 0 then
if to_x01(pcii.host) = '0' then
v.irq(3 downto 0) := (not pcii.int);
end if;
end if;
v.irq(9 downto 4) := r.stat.dpe & r.stat.sse & r.stat.rma & r.stat.rta & r.stat.sta & r.stat.dped;
apbo.pirq <= (others => '0');
apbo.pirq(irq) <= orv(r2.irq and r2.irq_en);
if r2.m.fifo.raddr = FIFO_FULL then fiform_limit := '1'; else fiform_limit := '0'; end if;
if r2.m.fifo.waddr = FIFO_FULL then fifowm_limit := '1'; else fifowm_limit := '0'; end if;
if r2.s.fifo.raddr = FIFO_FULL then fifors_limit := '1'; else fifors_limit := '0'; end if;
if r2.s.fifo.waddr = FIFO_FULL then fifows_limit := '1'; else fifows_limit := '0'; end if;
if r2.s.fifo.waddr(FIFO_DEPTH - 2 downto 1) = FIFO_FULL(FIFO_DEPTH - 2 downto 1) then fifows_stop := '1'; else fifows_stop := '0'; end if;
-----------------------------------
---- APB Control & Status regs ----
-----------------------------------
if (apbi.psel(pindex) and apbi.penable) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
if apbi.pwrite = '1' then
v.pciba := apbi.pwdata(31 downto 31-HMASK_WIDTH+1);
v.bus_nr := apbi.pwdata(26 downto 23);
v.werr := r2.werr and not apbi.pwdata(14);
v.wcomm := apbi.pwdata(10) and r.comm.mwie;
v.rcomm := apbi.pwdata(9);
end if;
prdata(31 downto 31-HMASK_WIDTH+1) := r2.pciba;
prdata(26 downto 23) := r2.bus_nr;
prdata(22 downto 0) := r.ltim & r2.werr & not pr.host & r.comm.msen & r.comm.men & r2.wcomm & r2.rcomm & r2.cfto & r.cline;
when "001" =>
prdata := r.bar0(31 downto MADDR_WIDTH) & addzero(MADDR_WIDTH-1 downto 0);
when "010" =>
prdata := r.page(31 downto MADDR_WIDTH-1) & addzero(MADDR_WIDTH-2 downto 1) & r.bt_enable;
when "011" =>
prdata := r.bar1(31 downto DMAMADDR_WIDTH) & addzero(DMAMADDR_WIDTH-1 downto 0);
when "100" =>
if apbi.pwrite = '1' then
v.dmapage(31 downto DMAMADDR_WIDTH) := apbi.pwdata(31 downto DMAMADDR_WIDTH);
end if;
prdata := r2.dmapage(31 downto DMAMADDR_WIDTH) & addzero(DMAMADDR_WIDTH-1 downto 0);
when "101" =>
if apbi.pwrite = '1' then
v.ioba := apbi.pwdata(31 downto 16);
end if;
prdata := r2.ioba & addzero(15 downto 4) & hstart & hstart_ack & pstart & pstart_ack;
when "110" =>
prdata(1) := r.comm.men;
prdata(2) := r.comm.msen;
prdata(4) := r.comm.mwie;
prdata(6) := r.comm.per;
prdata(8) := r.comm.ser;
prdata(24) := r.stat.dped;
prdata(26) := '1';
prdata(27) := r.stat.sta;
prdata(28) := r.stat.rta;
prdata(29) := r.stat.rma;
prdata(30) := r.stat.sse;
prdata(31) := r.stat.dpe;
when "111" =>
if apbi.pwrite = '1' then
v.irq_en := apbi.pwdata(25 downto 16);
end if;
prdata(31 downto 26) := (others => '0');
prdata(25 downto 16) := r2.irq_en;
prdata(15 downto 10) := (others => '0');
prdata(9 downto 0) := r2.irq;
when others =>
end case;
end if;
---------------------
---- AHB MASTER ----
---------------------
-- Burst control
if (r2.m.state = read or r2.m.state = read_w) then
if r.t.lmult = '1' then
comp := fifowm_limit and r2.m.fifo.side;
elsif r.t.lburst = '1' then
if r2.clscnt(8) = '1' then comp := '1';
else v.clscnt := r2.clscnt - (dmao.active and dmao.ready); end if;
else comp := '1'; end if;
else
v.clscnt := '0' & (r.cline - '1'); -- set burst counter to cache line size
end if;
if (rtdone = '1' and (r2.m.fifo.raddr + '1') = r.t.fifo.waddr) then rmvalid := '0'; end if;
-- step DMA address
if dmao.ready = '1' then
v.m.dmaddr(31 downto 2) := r2.m.dmaddr(31 downto 2) + '1';
end if;
-- Translate current CBE to hsize and address
byteaddr := "00";
if endian = 0 then -- pci is little endian
case r2.m.cur_cbe is
when "0000" => -- 32 bit access
vdmai.size := "10"; byteaddr := "00";
when "1100" => -- 16 bit
vdmai.size := "01"; byteaddr := "00";
when "0011" =>
vdmai.size := "01"; byteaddr := "10";
when "1110" => -- 8 bit
vdmai.size := "00"; byteaddr := "00";
when "1101" =>
vdmai.size := "00"; byteaddr := "01";
when "1011" =>
vdmai.size := "00"; byteaddr := "10";
when "0111" =>
vdmai.size := "00"; byteaddr := "11";
when others => vdmai.size := "10";
end case;
else -- big endian
case r2.m.cur_cbe is
when "0000" => -- 32 bit access
vdmai.size := "10"; byteaddr := "00";
when "0011" => -- 16 bit
vdmai.size := "01"; byteaddr := "00";
when "1100" =>
vdmai.size := "01"; byteaddr := "10";
when "0111" => -- 8 bit
vdmai.size := "00"; byteaddr := "00";
when "1011" =>
vdmai.size := "00"; byteaddr := "01";
when "1101" =>
vdmai.size := "00"; byteaddr := "10";
when "1110" =>
vdmai.size := "00"; byteaddr := "11";
when others => vdmai.size := "10";
end case;
end if;
vdmai.address := r2.m.dmaddr(31 downto 2) & byteaddr;
next_cbe := cbe_fifoo.rdata(3 downto 0);
-- AHB master state machine
case r2.m.state is
when idle =>
v.m.read_half := '0';
v.m.last_side_wr := '0';
v.m.cur_cbe := (others => '0');
v.m.fifo.waddr := (others => '0');
if hstart = '1' then
wmdone := '0';
fifowm_limit := '0';
-- v.m.fifo.waddr := (others => '0');
if r.t.lwrite = '1' then
v.m.dmaddr := r.t.laddr;
v.m.state := write;
v.m.cur_cbe := cbe_fifoo.rdata(3 downto 0);
-- burst access
if rtdone = '0' or conv_integer(r.t.fifo.waddr) /= 1 then
v.m.cbe_fifo.raddr := r2.m.cbe_fifo.raddr + 1;
v.m.state := cbe_prepare;
v.m.cbe_prep_cnt := '1';
end if;
-- vdmai.busy := '1';
-- if rmvalid = '1' then v.m.state := write;
-- else vdmai.start := '0'; v.m.state := stop; end if;
else
--vdmai.start := '1';
v.m.state := read_w;
v.m.dmaddr := r.t.laddr;
end if;
-- Latching dmaddr is now only done when hstart = 1 [nisse]
else --v.m.dmaddr := r.t.laddr;
end if;
when cbe_prepare =>
v.m.cur_cbe := next_cbe;
-- Need to wait for correct cycle to sample next
-- cbe if we have switched FIFO side.
if r2.m.cbe_prep_cnt = '1' then
v.m.state := write;
else
v.m.cbe_prep_cnt := '1';
end if;
when write =>
start := '0';
--if fiform_limit = '1' then
--if fiform_limit = '1' and dmao.start = '1' then -- 1k bug fix (store last word in first
-- v.m.read_half := '1'; -- fifo half if addr = 0x400 ...)
--end if;
--if fiform_limit = '1' and dmao.start = '1' and dmao.ready = '1' then -- 1k bug fix (store last word in first
-- Need to check dmao active and ready to handle retry/split on last word (check dmao start instead of active result in lockup if waitstates on AHB)
if fiform_limit = '1' and dmao.active = '1' and dmao.ready = '1' then -- 1k bug fix (store last word in first
v.m.read_half := '1'; -- fifo half if addr = 0x400 ...)
end if;
-- Don't start again until PCI side is done filling second half of fifo (bug fix kc)
if r2.m.read_half = '1' then
if rtdone = '1' then
start := ((rmvalid and not fiform_limit) or (not dmao.active and not rmvalid));
end if;
else
-- vdmai.start := ((rmvalid and not fiform_limit) or (not dmao.active and not rmvalid));
-- 1k bug fix (store last word in first fifo half if addr = 0x400 ...)
start := ((rmvalid and not v.m.read_half) or (not dmao.active and not rmvalid));
end if;
if (fiform_limit and dmao.active) = '1' then start := '0'; end if; -- [nisse]
-- Burst CBE handling
if rtdone = '0' or conv_integer(r.t.fifo.waddr) /= 1 then
-- Current or access is subword. Must be forced to single access
if r2.m.cur_cbe /= "0000" then
vdmai.burst := '0';
if dmao.active = '1' then
start := '0';
end if;
end if;
-- Next access is subword. Make current access last in burst
if rmvalid = '1' and next_cbe /= "0000" then
if dmao.active = '1' then
start := '0';
end if;
end if;
end if;
vdmai.start := start;
-- End of data phase for access with cur_cbe
if (dmao.active and dmao.ready) = '1' then
v.m.fifo.raddr := r2.m.fifo.raddr + (rmvalid and not fiform_limit and not dmao.mexc);
v.m.cbe_fifo.raddr := r2.m.cbe_fifo.raddr + (rmvalid and not fiform_limit and not dmao.mexc);
v.m.last_side_wr := m_read_side;
-- First half of FIFO
if v.m.read_half = '0' then
v.m.cur_cbe := next_cbe;
-- FIFO side switch
elsif r2.m.read_half = '0' then
v.m.cbe_prep_cnt := '0';
v.m.state := cbe_prepare;
elsif v.m.last_side_wr = '0' then
v.m.cbe_prep_cnt := '0';
v.m.state := cbe_prepare;
-- Second side of FIFO
else
v.m.cur_cbe := next_cbe;
end if;
if (dmao.mexc = '1' or rmvalid = '0') then
habort := dmao.mexc and not r.t.lwrite;
v.werr := r2.werr or (dmao.mexc and r.t.lwrite);
v.m.state := stop;
end if;
end if;
when read_w =>
vdmai.start := not (comp and dmao.active);
if dmao.mexc = '1' then
habort := not r.t.lwrite;
v.werr := '1';
v.m.state := stop;
elsif dmao.ready = '1' then
fifom_write := '1';
wmvalid := not (comp or dmao.mexc);
if comp = '1' then
v.m.state := stop;
v.m.fifo.waddr := r2.m.fifo.waddr + '1';
else
v.m.fifo.waddr := r2.m.fifo.waddr + (not fifowm_limit);
v.m.state := read; end if;
end if;
when read =>
vdmai.start := not (comp and dmao.active);
fifom_write := dmao.ready; wmvalid := not (comp or dmao.mexc);
-- if ((comp and dmao.ready) or dmao.retry) = '1' then
if (comp and dmao.ready) = '1' then
v.m.state := stop; v.m.fifo.waddr := r2.m.fifo.waddr + '1';
elsif (dmao.active and dmao.ready) = '1' then
v.m.fifo.waddr := r2.m.fifo.waddr + (not dmao.mexc and not fifowm_limit);
if dmao.mexc = '1' then habort := not r.t.lwrite; v.werr := r2.werr or r.t.lwrite; v.m.state := stop; end if;
end if;
when stop =>
if hstart = '0' and ((r.t.lwrite and not fiform_limit) = '1' or wmdone = '1') then
v.m.state := idle; hstart_ack := '0';
v.m.fifo.side := '0'; habort := '0';
v.m.fifo.raddr := (others => '0');
v.m.cbe_fifo.raddr := (others => '0');
else
comp := '1';
fiform_limit := r.t.lwrite;
fifowm_limit := not r.t.lwrite;
end if;
end case;
-- FIFO control
if fifowm_limit = '1' then
-- if (((r2.m.fifo.side or hstart_ack or (not hstart)) = '0' and not (dmao.active and not dmao.ready) = '1')
if (((r2.m.fifo.side or hstart_ack or (not hstart)) = '0' and (dmao.ready or comp) = '1')
or ((hstart_ack and not hstart) = '1' and v.m.state = stop)) then
if v.m.state = stop then wmdone := '1';
else v.m.fifo.waddr := (others => '0'); end if;
hstart_ack := '1';
v.m.fifo.side := not r2.m.fifo.side;
end if;
elsif fiform_limit = '1' then
-- if dmao.active = '0' then
if dmao.active = '0' and dmai.start = '0' then -- 1k bug fix ***
m_read_side := '1';
hstart_ack := '1';
-- v.m.fifo.raddr := (others => hstart);
v.m.fifo.raddr := (others => '0'); -- 1k bug fix ***
v.m.cbe_fifo.raddr := conv_std_logic_vector(1, FIFO_DEPTH-1);
end if;
end if;
-----------------------
--- AHB MASTER END ----
-----------------------
-------------------
---- AHB SLAVE ----
-------------------
-- if MASTER = 1 then
-- Access decode
if (ahbsi.hready and ahbsi.hsel(hslvndx)) = '1' then
if (ahbsi.hmbsel(0) or ahbsi.hmbsel(1)) = '1' then
hsize := ahbsi.hsize(1 downto 0); v.s.htrans := ahbsi.htrans;
--if (v.s.htrans(1) and r.comm.msen) = '1' then request := '1'; end if;
if (v.s.htrans(1) and r.comm.msen) = '1' then -- fix access control ***
ahb_access := '1';
--if (r2.s.state /= r_wait and r2.s.state /= r_hold) or r2.s.hmaster = ahbsi.hmaster then
--if (r2.s.state = idle or r2.s.state = t_done) or r2.s.hmaster = ahbsi.hmaster then
if (r2.s.state = idle) or r2.s.hmaster = ahbsi.hmaster then
request := '1';
end if;
end if;
end if;
end if;
-- Access latches
if (request = '1' and r2.s.state = idle) then
if ahbsi.hmbsel(1) = '1' then
if ahbsi.haddr(16) = '1' then -- Configuration cycles
v.s.maddr := (others => '0');
if r2.bus_nr = "0000" then -- Type 0
v.s.maddr(conv_integer(ahbsi.haddr(15 downto 11)) + 10) := '1';
v.s.maddr(10 downto 0) := ahbsi.haddr(10 downto 2) & "00";
else -- Type 1
v.s.maddr(19 downto 0) := r2.bus_nr & ahbsi.haddr(15 downto 2) & "01";
end if;
v.s.pcicomm := "101" & ahbsi.hwrite;
else -- I/O space access
v.s.maddr(31 downto 16) := r2.ioba;
v.s.maddr(15 downto 0) := ahbsi.haddr(15 downto 0);
v.s.pcicomm := "001" & ahbsi.hwrite;
end if;
else -- Memory space access
if conv_integer(ahbsi.hmaster) = dmamst then
v.s.maddr := ahbsi.haddr;
else
v.s.maddr := r2.pciba & ahbsi.haddr(31-HMASK_WIDTH downto 2) & "00";
end if;
if ahbsi.hwrite = '1' then
v.s.pcicomm := r2.wcomm & "111";
else
v.s.pcicomm := ahbsi.hburst(0) & '1' & (r2.rcomm or not ahbsi.hburst(0)) & '0';
end if;
end if;
-- Decode HSIZE and HADDR
if endian = 0 then -- pci is little endian
case hsize is
when "00" => -- Decode byte enable
case ahbsi.haddr(1 downto 0) is
when "00" => v.s.be := "1110";
when "01" => v.s.be := "1101";
when "10" => v.s.be := "1011";
when "11" => v.s.be := "0111";
when others => v.s.be := "1111";
end case;
when "01" =>
case ahbsi.haddr(1 downto 0) is
when "00" => v.s.be := "1100";
when "10" => v.s.be := "0011";
when others => v.s.be := "1111";
end case;
when "10" => v.s.be := "0000";
when others => v.s.be := "1111";
end case;
else -- pci is big endian
case hsize is
when "00" => -- Decode byte enable
case ahbsi.haddr(1 downto 0) is
when "00" => v.s.be := "0111";
when "01" => v.s.be := "1011";
when "10" => v.s.be := "1101";
when "11" => v.s.be := "1110";
when others => v.s.be := "1111";
end case;
when "01" =>
case ahbsi.haddr(1 downto 0) is
when "00" => v.s.be := "0011";
when "10" => v.s.be := "1100";
when others => v.s.be := "1111";
end case;
when "10" => v.s.be := "0000";
when others => v.s.be := "1111";
end case;
end if;
end if;
if ((rmdone and not r2.s.pcicomm(0)) = '1' and (r2.s.fifo.raddr + '1' + pcidc) = r.m.fifo.waddr) then rsvalid := '0'; end if;
-- FIFO address counters
-- if (r2.s.state = t_data or r2.s.state = w_wait) then
if (r2.s.state = t_data or r2.s.state = w_wait or -- bug fix ***
--(r2.s.state = r_hold and fifors_limit = '0' and ((pstart_ack or pstart) = '0') and request = '1')) then -- (r_hold -> t_data) bug fix ***
(r2.s.state = r_hold and fifors_limit = '0' and ((pstart_ack or pstart) = '0') and request = '1' and rmdone = '1')) then -- (r_hold -> t_data) bug fix ***
v.s.fifos_write := r2.s.pcicomm(0) and r2.s.htrans(1);
v.s.fifo.waddr := r2.s.fifo.waddr + r2.s.fifos_write;
v.s.fifo.raddr := r2.s.fifo.raddr + ((ahbsi.htrans(1) and not r2.s.pcicomm(0) and not fifors_limit and rsvalid) or not ahbsi.hready);
end if;
if pstart_ack = '1' then
if pabort = '1' then
if (r2.s.pcicomm = CONF_WRITE or r2.s.pcicomm = CONF_READ) then v.cfto := '1';
else v.s.perror := '1'; end if;
else v.s.perror := '0'; v.cfto := '0'; end if;
end if;
--
-- AHB slave state machine
case r2.s.state is
when idle =>
v.s.hold_retry := "00";
if request = '1' and p_done = '0' then
if ahbsi.hwrite = '1' then
v.s.state := w_wait;
v.s.fifo.side := '0';
else
pstart := '1'; v.s.state := r_wait;
end if;
v.s.hmaster := ahbsi.hmaster;
end if;
when w_wait =>
if ((ahbsi.hready and not ahbsi.htrans(0)) = '1') then
v.s.state := w_done; fifows_limit := not wsvalid;
else
v.s.state := t_data;
end if;
when t_data =>
if ahbsi.htrans(1) = '1' then v.s.hold_retry := "00"; end if;
burst_read := ahbsi.htrans(1) and not fifors_limit;
if (fifows_stop and r2.s.fifos_write) = '1' then
if r2.s.fifo.side = '1' then
v.s.state := w_done;
end if;
elsif ((fifors_limit or not rsvalid) = '1' and v.s.htrans(1) = '1') then
if (r.m.fifo.side = '0') or (rsvalid = '0') then
v.s.state := t_done;
--else v.s.state := r_hold; end if;
else v.s.state := r_hold; v.s.hold_retry := "00"; end if; -- reset hold_retry ***
end if;
if ((ahbsi.hready and not ahbsi.htrans(0)) = '1') then
if r2.s.pcicomm(0) = '1' then
--v.s.state := w_done; wsvalid := '0';
v.s.state := w_done;
if ahbsi.htrans /= "00" then wsvalid := '0'; end if; -- fix dont set wsvalid if amba idle
else -- (if wsvalid = 0 side is changed before last write
v.s.state := t_done; -- to fifo if hrans = 00)
wsvalid := '0'; -- Bug fix, must give RETRY here! /KC
end if;
end if;
when r_hold =>
s_read_side := '1';
if r2.s.hold_retry(1) = '0' then -- only check this once (first access)
if ahbsi.htrans = "11" then
v.s.hold_retry := "11"; -- Seq Burst access
elsif ahbsi.htrans /= "01" then -- if busy, wait to decide
v.s.hold_retry := "10"; -- New nonseq or idle
end if;
end if;
if v.s.hold_retry = "10" then
v.s.state := t_done;
--elsif fifors_limit = '0' and ((pstart_ack or pstart) = '0') and request = '1' and v.s.hold_retry = "11" then
elsif rmdone = '1' and fifors_limit = '0' and ((pstart_ack or pstart) = '0') and request = '1' and v.s.hold_retry = "11" then
v.s.state := t_data;
burst_read := ahbsi.htrans(1) and not fifors_limit; -- bug fix ***
else
v.s.hold := '1';
end if;
--if fifors_limit = '0' and ((pstart_ack or pstart) = '0') and request = '1' then
-- --if rmdone = '0' then -- bug fix ***
-- v.s.state := t_data;
-- burst_read := ahbsi.htrans(1) and not fifors_limit; -- bug fix ***
-- --else
-- -- v.s.state := t_done;
-- --end if;
--elsif (ahbsi.hready = '1' and ahbsi.htrans = "00" and r2.s.hresp = HRESP_OKAY) then -- (idle -> t_done) bug fix ***
-- v.s.state := t_done;
--else v.s.hold := '1'; end if;
when r_wait =>
s_read_side := '0';
if (pstart_ack and request) = '1' then
v.s.state := t_data; hready := '0';
end if;
if r2.s.hmaster /= ahbsi.hmaster and conv_integer(ahbsi.hmaster) = dmamst and pstart_ack = '1' then -- if pcidma cancel read
v.s.state := t_done;
end if;
when w_done =>
v.s.state := t_done; wsvalid := '0';
-- if (r2.s.htrans(1) or not fifows_limit) = '1' then
-- if (r2.s.htrans(1) and fifows_limit) = '1' then
v.s.fifo.waddr := r2.s.fifo.waddr + r2.s.fifos_write;
-- end if;
fifows_limit := '1';
when t_done =>
wsvalid := '0';
fifors_limit := not r2.s.pcicomm(0);
if (pstart or pstart_ack) = '0' then
v.s.state := idle; v.s.perror := '0';
v.s.fifo.waddr := (others => '0'); wsdone := '0'; fifows_limit := '0';
v.s.pcicomm := (0 => '1', others => '0'); -- default write
else fifows_limit := r2.s.pcicomm(0); end if;
end case;
-- Respond encoder
if v.s.state = t_data
or (v.s.state = r_hold and v.s.hold = '0') -- bug fix ***
or (v.s.state = t_done and r2.s.state = t_data) -- (end of trans) bug fix ***
or (v.s.state = w_wait and ahbsi.hwrite = '1') then
if r2.s.perror = '1' then hresp := HRESP_ERROR;
elsif wsvalid = '1' then hresp := HRESP_OKAY;
else hresp := HRESP_RETRY; end if;
v.s.perror := '0';
else hresp := HRESP_RETRY; end if;
-- added to provent read from unvalid fifo address
if r2.s.state = t_data and rsvalid = '0' and r2.s.hold_retry /= "00" then hresp := HRESP_RETRY; end if;
if r.comm.msen = '0' then hresp := HRESP_ERROR; end if; -- Master disabled
--if (v.s.htrans(1) and request) = '0' then hresp := HRESP_OKAY; end if; -- Response OK for BUSY and IDLE
if (v.s.htrans(1) and ahb_access) = '0' then hresp := HRESP_OKAY; end if; -- Response OK for BUSY and IDLE -- *** access control fix
if (hresp /= HRESP_OKAY or hready = '0') then v.s.hready := '0'; else v.s.hready := '1'; end if;
-- Dont change hresp during wait states
if ahbsi.hready = '0' then hresp := r2.s.hresp; end if;
v.s.hresp := hresp;
-- FIFO controller
if fifows_limit = '1' then
if (r2.s.fifos_write or not wsvalid) = '1' and (r2.s.fifo.side = '0' or pstart_ack = '1') then
--if wsvalid = '0' then wsdone := '1';
if wsvalid = '0' or v.s.state = w_done then wsdone := '1'; -- fix set wsdone and pstart at the same time
else v.s.fifo.waddr := (others => '0'); end if;
pstart := not pstart_ack;
v.s.fifo.side := pstart;
end if;
elsif ((r2.s.state = t_done or r2.s.state = r_hold) and fifors_limit = '1') then
if pstart_ack = '1' then pstart := '0'; v.s.fifo.raddr := (others => '0');
else v.s.fifo.raddr := (others => '0'); end if;
end if;
-- Set last fifo side written so that PCI master knows when to stop
if (r2.s.fifos_write = '1') then
v.s.last_side := r2.s.fifo.side;
end if;
-- end if;
-----------------------
---- AHB SLAVE END ----
-----------------------
-- Sync registers
v.trans(0) := pstart;
v.trans(1) := habort;
v.trans(2) := hstart_ack;
v.trans(3) := fifows_limit;
v.trans(4) := wsdone;
v.trans(5) := wmdone;
-- input data for write accesses
if r2.s.pcicomm(0) = '1' then v.s.mdata := ahbreadword(ahbsi.hwdata); end if;
-- output data for read accesses
-- if (ahbsi.htrans(1) and not r2.s.hold and not r2.s.pcicomm(0)) = '1' then v.s.mdata := fifo4o.rdata(31 downto 0); end if;
if (ahbsi.htrans(1) and not r2.s.pcicomm(0)) = '1' then v.s.mdata := fifo4o.rdata(31 downto 0); end if; -- bug fix ***
if rst = '0' then
v.s.state := idle;
v.m.state := idle;
v.s.perror := '0';
v.pciba := (others => '0');
v.trans := (others => '0');
v.m.cbe_fifo.waddr := (others => '0');
v.m.cbe_fifo.raddr := (others => '0');
v.m.fifo.waddr := (others => '0');
v.m.fifo.raddr := (others => '0');
v.s.fifo.waddr := (others => '0');
v.s.fifo.raddr := (others => '0');
v.m.fifo.side := '0';
v.s.fifo.side := '0';
v.wcomm := '0';
v.rcomm := '0';
v.werr := '0';
v.cfto := '0';
v.dmapage := (others => '0');
v.ioba := (others => '0');
v.bus_nr := (others => '0');
v.irq := (others => '0');
v.irq_en := (others => '0');
v.m.cbe_prep_cnt := '0';
end if;
apbo.prdata <= prdata;
ahbso.hready <= r2.s.hready;
ahbso.hresp <= r2.s.hresp;
ahbso.hrdata <= ahbdrivedata(byte_twist(r2.s.mdata, r.bt_enable));
ahbso.hindex <= hslvndx;
fifo1i.wen <= fifom_write;
fifo1i.waddr <= r2.m.fifo.side & r2.m.fifo.waddr;
fifo1i.wdata <= dmao.rdata;
fifo2i.ren <= '1';
fifo2i.raddr <= m_read_side & (r2.m.fifo.raddr + dmao.ready);
fifo3i.wen <= r2.s.fifos_write;
fifo3i.waddr <= r2.s.fifo.side & r2.s.fifo.waddr;
fifo3i.wdata <= byte_twist(r2.s.mdata, r.bt_enable);
fifo4i.ren <= '1';
fifo4i.raddr <= s_read_side & (r2.s.fifo.raddr + burst_read);
cbe_fifoi.ren <= '1';
cbe_fifoi.raddr <= m_read_side & (r2.m.cbe_fifo.raddr + dmao.ready); -- read one cycle before data fifo
r2in <= v; dmai <= vdmai;
end process;
ahbso.hconfig <= hconfig when MASTER = 1 else (others => zero32);
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
---------------------------------
-- PCI core (PCI clock domain) --
---------------------------------
pcicomb : process(pr, pcii, r, r2, fifo1o, fifo3o, roe_ad, prrst, ahbmi,
pcirstin, ad)
variable v : pci_reg_type;
variable chit, mhit0, mhit1, phit, hit, hosthit, ready, cwrite, retry : std_logic;
variable cdata, cwdata : std_logic_vector(31 downto 0);
variable comp : std_logic; -- Last transaction cycle on PCI bus
variable mto, tto, term, ben_err, lto : std_logic;
variable i : integer range 0 to NO_PCI_REGS;
variable tad, mad : std_logic_vector(31 downto 0);
variable pstart, habort, hstart_ack, wsdone, wmdone : std_logic;
variable hstart, pabort, pstart_ack, pcidc, rtdone, rmdone : std_logic;
variable fifort_limit, fifowt_limit, fiform_limit, fifowm_limit, fifowm_stop, t_valid : std_logic;
variable d_ready, tabort, backendnr : std_logic;
variable m_fifo_write, t_fifo_write, grant : std_logic;
variable write_access, memwrite, memread, read_match, m_read_side, t_read_side : std_logic;
variable readt_dly : std_logic; -- 1 turnaround cycle
variable bus_idle, data_transfer, data_transfer_r, data_phase, targ_d_w_data, targ_abort, m_request : std_logic;
variable voe_ad : std_logic_vector(31 downto 0);
variable oe_par : std_logic;
variable oe_ad : std_logic;
variable oe_ctrl : std_logic;
variable oe_cbe : std_logic;
variable oe_frame : std_logic;
variable oe_irdy : std_logic;
variable oe_req : std_logic;
variable oe_perr : std_logic;
variable oe_serr : std_logic;
begin
-- Process defaults
v := r; v.pci.trdy := '1'; v.pci.stop := '1'; v.pci.frame := '1';
v.pci.oe_ad := '1'; v.pci.devsel := '1'; v.pci.oe_frame := '1';
v.pci.irdy := '1'; v.pci.req := '1'; hosthit := '0'; m_request := '0';
v.pci.oe_req := '0'; v.pci.oe_cbe := '1'; v.pci.oe_irdy := '1';
mto := '0'; tto := '0'; v.m.stop_req := '0'; lto := '0';
cdata := (others => '0'); retry := '0'; t_fifo_write := '0';
chit := '0'; phit := '0'; mhit0 := '0'; mhit1 := '0'; tabort := '0';
readt_dly := '0'; m_fifo_write := '0'; voe_ad := roe_ad;
tad := r.pci.ad; mad := r.pci.ad; grant := pcii.gnt; d_ready := '0';
m_read_side := not r2.s.fifo.side; t_read_side := not r2.m.fifo.side;
v.m.rmdone := '0';
write_access := not r.t.read and not pr.irdy and not pr.trdy;
memwrite := r.t.msel and r.t.lwrite and not r.t.read;
memread := r.t.msel and not r.t.lwrite and r.t.read;
-- Synch registers
hstart := r.trans(0);
pabort := r.trans(1);
pstart_ack := r.trans(2);
pcidc := r.trans(3);
rtdone := r.trans(4);
rmdone := r.trans(5);
for i in 0 to NO_PCI_REGS - 1 loop
v.syncs(i)(csync) := r2.trans(i);
if csync /= 0 then v.syncs(i)(0) := r.syncs(i)(csync); end if;
end loop;
pstart := r.syncs(0)(0);
habort := r.syncs(1)(0);
hstart_ack := r.syncs(2)(0);
backendnr := r.syncs(3)(0);
wsdone := r.syncs(4)(0);
wmdone := r.syncs(5)(0);
-- FIFO limit detector
if r.t.fifo.raddr = FIFO_FULL then fifort_limit := '1'; else fifort_limit := '0'; end if;
if r.t.fifo.waddr = FIFO_FULL then fifowt_limit := '1'; else fifowt_limit := '0'; end if;
if r.m.fifo.raddr = FIFO_FULL then fiform_limit := '1'; else fiform_limit := '0'; end if;
if r.m.fifo.waddr = FIFO_FULL then fifowm_limit := '1'; else fifowm_limit := '0'; end if;
if r.m.fifo.waddr(FIFO_DEPTH - 2 downto 1) = FIFO_FULL(FIFO_DEPTH - 2 downto 1) then fifowm_stop := '1'; else fifowm_stop := '0'; end if;
-- useful control variables
--if (r.t.laddr = r.page & r.t.addr(MADDR_WIDTH-2 downto 0) or r.t.laddr = r2.dmapage & r.t.addr(DMAMADDR_WIDTH-1 downto 0))
if (r.t.laddr(31 downto 2) = r.page & r.t.addr(MADDR_WIDTH-2 downto 2) -- bug fix match if byte access
or r.t.laddr(31 downto 2) = r2.dmapage & r.t.addr(DMAMADDR_WIDTH-1 downto 2))
and (r.t.lcbe = pr.cbe) -- bug fix match byte access
and (r.t.lburst = r.t.burst) then read_match := r.t.pending; else read_match := r.t.csel or r.t.psel; end if;
-- if (pr.cbe = "0000" and r.t.lsize = "10") or (pr.cbe = "1100" and r.t.lsize = "01") or (pr.cbe = "1110" and r.t.lsize = "00")
-- pragma translate_off
-- or (pr.cbe = "XXXX") -- For simulation purposes
-- pragma translate_on
-- then ben_err := '0'; else ben_err := '1'; end if;
ben_err := '0';
--if r.stat.dpe = '0' then v.stat.dpe := not (r.pci.perr and r.pci.serr); end if;
if r.stat.dpe = '0' and (r.m.detectperr(1) = '1' or r.t.detectperr(1) = '1' or r.pci.serr = '0') then v.stat.dpe := not (r.pci.perr and r.pci.serr); end if;
-------------------------
----- PCI TARGET --------
-------------------------
-- Data valid?
if ((wmdone and not r.t.lwrite) = '1' and (r.t.fifo.raddr + '1') = r2.m.fifo.waddr) then t_valid := '0';
else t_valid := not fifowt_limit or not r.t.fifo.side; end if;
-- Step addresses
if (r.t.state = s_data or r.t.state = turn_ar or r.t.state = backoff) then
--if (pcii.irdy or r.pci.trdy) = '0' then
if (pcii.irdy or r.t.trdy_del) = '0' then
v.t.addr := r.t.addr + ((r.t.csel and r.t.read) & "00");
readt_dly := '1';
if r.t.msel = '1' then
-- **** ???? **** Is r2.m.fifo.side really synced here ??? *** may need to be changed *** [nisse]
v.t.wdel := (fifort_limit and r2.m.fifo.side) or r.t.lwrite;
v.t.fifo.raddr := r.t.fifo.raddr + (r.t.read and not fifort_limit and t_valid);
end if;
end if;
if write_access = '1' then
v.t.fifo.waddr := r.t.fifo.waddr + (r.t.msel and not r.t.read and not ben_err);
t_fifo_write := r.t.msel;
v.t.addr := r.t.addr + ((r.t.csel and not r.t.read) & "00");
end if;
tabort := habort;
else v.t.wdel := '0'; end if;
-- signal to hold target while last word is transfered
if (fifort_limit and not (pcii.irdy or r.t.trdy_del) and not r.t.thold) = '1' then -- should be r.pci.trdy
v.t.thold := '1';
elsif (r.t.thold and not (pcii.irdy or r.t.trdy_del)) = '1' then -- should be r.pci.trdy
v.t.thold := '0';
end if;
-- Config space read access
case r.t.addr(7 downto 2) is
when "000000" => -- 0x00, device & vendor id
cdata := conv_std_logic_vector(DEVICE_ID, 16) &
conv_std_logic_vector(VENDOR_ID, 16);
when "000001" => -- 0x04, status & command
cdata(1) := r.comm.men;
cdata(2) := r.comm.msen;
cdata(4) := r.comm.mwie;
cdata(6) := r.comm.per;
cdata(8) := r.comm.ser;
cdata(24) := r.stat.dped;
cdata(26) := '1';
cdata(27) := r.stat.sta;
cdata(28) := r.stat.rta;
cdata(29) := r.stat.rma;
cdata(30) := r.stat.sse;
cdata(31) := r.stat.dpe;
when "000010" => -- 0x08, class code & revision
cdata(31 downto 0) := conv_std_logic_vector(CLASS_CODE,24) & conv_std_logic_vector(REV,8) ;
when "000011" => -- 0x0C, latency & cacheline size
cdata(7 downto 0) := r.cline;
cdata(15 downto 8) := r.ltim;
when "000100" => -- 0x10, BAR0
cdata(31 downto MADDR_WIDTH) := r.bar0;
when "000101" => -- 0x14, BAR1
cdata(31 downto DMAMADDR_WIDTH) := r.bar1;
when "001111" => -- 0x3C, Interrupts & Latency timer settings
cdata(7 downto 0) := r.intline; -- Interrupt line
cdata(8) := '1'; -- Use interrupt pin INTA#
if fifodepth < 11 then cdata(fifodepth+13) := '1'; end if; --Define wanted burst period
when others =>
end case;
-- Config space write access
cwdata := pr.ad;
if pr.cbe(3) = '1' then cwdata(31 downto 24) := cdata(31 downto 24); end if;
if pr.cbe(2) = '1' then cwdata(23 downto 16) := cdata(23 downto 16); end if;
if pr.cbe(1) = '1' then cwdata(15 downto 8) := cdata(15 downto 8); end if;
if pr.cbe(0) = '1' then cwdata( 7 downto 0) := cdata( 7 downto 0); end if;
if (r.t.csel and write_access) = '1' then
case r.t.addr(7 downto 2) is
when "000001" => -- 0x04, status & command
-- Command register
v.comm.men := cwdata(1);
if MASTER = 1 then v.comm.msen := cwdata(2); end if;
v.comm.mwie := cwdata(4);
v.comm.per := cwdata(6);
v.comm.ser := cwdata(8);
-- Status register, sticky bits
v.stat.dped := r.stat.dped and not cwdata(24);
v.stat.sta := r.stat.sta and not cwdata(27);
v.stat.rta := r.stat.rta and not cwdata(28);
v.stat.rma := r.stat.rma and not cwdata(29);
v.stat.sse := r.stat.sse and not cwdata(30);
v.stat.dpe := r.stat.dpe and not cwdata(31);
when "000011" => -- 0x0c, latency & cacheline size
if FIFO_DEPTH <= 7 then v.cline(FIFO_DEPTH - 1 downto 0) := cwdata(FIFO_DEPTH - 1 downto 0);
else v.cline := cwdata(7 downto 0); end if;
v.ltim := cwdata(15 downto 8);
when "000100" => -- 0x10, BAR0
v.bar0 := cwdata(31 downto MADDR_WIDTH);
if v.bar0 = zero(31 downto MADDR_WIDTH) then v.bar0_conf := '0'; else v.bar0_conf := '1'; end if;
when "000101" => -- 0x14, BAR1
v.bar1 := cwdata(31 downto DMAMADDR_WIDTH);
if v.bar1 = zero(31 downto DMAMADDR_WIDTH) then v.bar1_conf := '0'; else v.bar1_conf := '1'; end if;
when "001111" => -- 0x3C, Interrupts & Latency timer settings
v.intline := cwdata(7 downto 0); -- Interrupt line
when others =>
end case;
end if;
-- Page bar write
if (r.t.psel and write_access) = '1' then
v.page := pr.ad(31 downto MADDR_WIDTH - 1);
v.bt_enable := pr.ad(0);
end if;
-- Command and address decode
case pr.cbe is
when CONF_READ | CONF_WRITE =>
if pr.ad(1 downto 0) = "00" then chit := '1'; end if;
if pr.host = '0' then --Active low
if pr.ad(31 downto 11) = "000000000000000000000" then hosthit := '1'; end if;
end if;
when MEM_READ | MEM_WRITE =>
if pr.ad(31 downto MADDR_WIDTH) = r.bar0 then
phit := r.bar0_conf and pr.ad(MADDR_WIDTH - 1);
mhit0 := r.bar0_conf and not pr.ad(MADDR_WIDTH - 1);
elsif pr.ad(31 downto DMAMADDR_WIDTH) = r.bar1 then
mhit1 := r.bar1_conf;
end if;
when MEM_R_MULT | MEM_R_LINE | MEM_W_INV =>
if pr.ad(31 downto MADDR_WIDTH - 1) = r.bar0 & '0' then mhit0 := r.bar0_conf;
elsif pr.ad(31 downto DMAMADDR_WIDTH) = r.bar1 then mhit1 := r.bar1_conf; end if;
when others => phit := '0'; mhit0 := '0'; chit := '0'; mhit1 := '0';
end case;
-- SERR, address phase parity error. Treat as non hit.
v.pci.serr := '1';
v.pci.oe_serr := '1';
--if pr.frame = '0' then
if pr.frame = '0' and (r.t.state = idle or r.t.state = turn_ar) then -- Only signal address parity error on SERR#
if ( (pcii.par xor xorv(pr.ad & pr.cbe)) = '1') then
v.pci.serr := '0';
chit := '0'; phit := '0'; mhit0 := '0'; mhit1 := '0';
--if r.comm.ser = '1' then
if r.comm.ser = '1' and r.comm.per = '1' then -- Address parity error only if "Parity Error Response" and "SERR# enable" is enabled.
v.pci.oe_serr := '0';
v.stat.sse := '1';
end if;
end if;
end if;
-- Hit detect
hit := r.t.csel or r.t.msel or r.t.psel;
if (hstart and r.pci.devsel) = '1' then
if (r.t.pending or r.t.lwrite) = '0' then
hstart := not hstart_ack;
v.t.fifo.raddr := (others => '0');
end if;
end if;
-- Ready to transfer data
if ((r.t.csel and not readt_dly) or r.t.psel) = '1'
or ((((memwrite and not r.pci.devsel) = '1')
-- Changed to transfer last word (instead of delaying trdy) [nisse]
--or (memread = '1' and not (hstart_ack and v.t.wdel) = '1')) and ben_err = '0')
or (memread = '1' and not (hstart_ack and r.t.wdel) = '1')) and ben_err = '0')
then ready := '1'; else ready := '0'; t_read_side := r.t.read and not hstart; end if;
v.t.ready_del := ready;
-- Target timeout counter
--if (hit and pr.trdy and not (pr.frame and pr.irdy)) = '1' then
--if (hit and pr.trdy and not (pr.frame and pr.irdy) and v.t.wdel) = '1' then
if (hit and pr.trdy and not (pr.frame and pr.irdy) and not ready) = '1' then
if r.t.cnt /= "000" then v.t.cnt := r.t.cnt - 1;
else tto := '1'; end if;
else v.t.cnt := (0 => '0', others => '1'); end if;
-- -- Ready to transfer data
-- if ((r.t.csel and not readt_dly) or r.t.psel) = '1'
-- or ((((memwrite and not r.pci.devsel) = '1')
-- or (memread = '1' and not (hstart_ack and v.t.wdel) = '1')) and ben_err = '0')
-- then ready := '1'; else ready := '0'; t_read_side := r.t.read and not hstart; end if;
-- Terminate current transaction
if (((r.t.fifo.waddr >= (FIFO_FULL - "10") and r.t.fifo.side = '1')
or (t_valid = '0') or r.pci.stop = '0') and pcii.frame = '0')
or ((r.t.read xor r.t.lwrite) = '0' and r.pci.devsel = '0')
or (tto = '1') or (ben_err = '1')
then
term := '1';
else term := '0'; end if;
-- Retry transfer
if r.t.state = b_busy then
if not ((r.t.read and not r.t.lwrite and hstart_ack and read_match) = '1'
or (r.t.read or hstart or hstart_ack) = '0'
or ((r.t.csel or r.t.psel) and not hstart and not hstart_ack) = '1')
then
retry := '1';
end if;
end if;
-- Target state machine
case r.t.state is
when idle =>
v.t.detectperr(0) := '0';
v.t.thold := '0';
v.t.thold2 := '0';
if pr.frame = '0' then v.t.state := b_busy; end if; -- !HIT ?
v.t.addr := pr.ad;
if readpref = 1 then v.t.burst := '1';
else v.t.burst := pr.cbe(3); end if;
v.t.read := not pr.cbe(0); v.t.mult := not pr.cbe(1);
v.t.csel := (pr.idsel or hosthit) and chit; v.t.psel := phit;
v.t.msel := r.comm.men and (mhit0 or mhit1); v.t.barsel := mhit1;
when turn_ar =>
v.t.detectperr(0) := '0';
if pr.frame = '1' then
v.t.state := idle;
v.t.fifo.raddr := (others => '0'); -- fix reset fifo read address
else v.t.state := b_busy; end if; -- !HIT ?
v.t.addr := pr.ad; v.t.wdel := '1';
if readpref = 1 then v.t.burst := '1';
else v.t.burst := pr.cbe(3); end if;
v.t.read := not pr.cbe(0); v.t.mult := not pr.cbe(1);
v.t.csel := (pr.idsel or hosthit) and chit; v.t.psel := phit;
v.t.msel := r.comm.men and (mhit0 or mhit1); v.t.barsel := mhit1;
when b_busy =>
v.t.thold := '0';
v.t.thold2 := '0';
if (pr.frame and pr.irdy) = '1' then
v.t.state := idle;
elsif hit = '1' then
v.t.detectperr(0) := '1';
v.t.state := s_data;
v.t.fifo.raddr := r.t.fifo.raddr + (r.t.read and r.t.msel);
readt_dly := '1';
if r.t.pending = '0' then
v.t.pending := retry and not hstart_ack;
end if;
end if;
-- else v.t.state := backoff; end if;
-- We should not go to back off if the access wasn't to us
when s_data =>
if r.t.pending = '1' then v.t.pending := not ((habort or not r.pci.trdy) and read_match); end if;
if (pcii.frame = '0' and r.pci.stop ='0' and (r.pci.trdy or not pcii.irdy) = '1') then
v.t.state := backoff;
if r.t.last = '0' then v.t.last := r.t.msel and r.t.lwrite and v.t.wdel; end if;
v.t.fifo.raddr := r.t.fifo.raddr - (r.t.read and r.t.msel and not fifort_limit);
-- elsif (pcii.frame = '1' and (r.pci.trdy = '0' or r.pci.stop = '0')) then
elsif (pcii.frame = '1' and (r.t.trdy_del = '0' or r.pci.stop = '0')) then -- (send last word in fifo) bug fix ***
v.t.state := turn_ar;
if r.t.last = '0' then v.t.last := r.t.msel and r.t.lwrite and v.t.wdel; end if;
v.t.fifo.raddr := r.t.fifo.raddr - (r.t.read and r.t.msel and not fifort_limit);
end if;
when backoff =>
v.t.detectperr(0) := '0';
if pcii.frame = '1' then v.t.state := turn_ar; end if;
end case;
-- #TRDY assert
--if (v.t.state = s_data and habort = '0' and ready = '1' and retry = '0') then v.pci.trdy := '0'; end if;
-- Changed to only deassert trdy when irdy is asserted [nisse]
if (v.t.state = s_data and habort = '0' and (ready or (pcii.irdy and not r.pci.trdy)) = '1' and retry = '0') then v.pci.trdy := '0'; end if;
-- #STOP assert
--if (v.t.state = backoff or (v.t.state = s_data and ((tabort or ((term or retry) and not habort)) = '1'))) then
-- Changed to only deassert stop when irdy is asserted [nisse]
if (v.t.state = backoff or (v.t.state = s_data and ((tabort or (((term and (not pcii.irdy or not r.pci.stop)) or retry) and not habort)) = '1'))) then
v.pci.stop := '0'; end if;
-- #DEVSEL assert
if (((v.t.state = backoff and r.pci.devsel = '0') or v.t.state = s_data) and (read_match and tabort) = '0') then v.pci.devsel := '0'; end if;
-- Enable #TRDY, #STOP and #DEVSEL
if (v.t.state = s_data) or (v.t.state = backoff) or (v.t.state = turn_ar) then
v.pci.oe_ctrl := not hit;
else v.pci.oe_ctrl := '1'; end if;
-- Signaled target abort
if (r.pci.devsel and not (r.pci.stop or r.pci.oe_ctrl)) = '1' then v.stat.sta := '1'; end if;
if (fifort_limit and v.t.thold) = '1' then --v.pci.trdy := '0';
elsif (r.t.thold and not v.t.thold) = '1' then --v.pci.trdy := '1';
end if;
-- Removed, (ready is delayed instead) [nisse]
--if r.t.state = s_data and v.t.state = s_data and r.pci.trdy = '0'
-- and v.pci.trdy = '1' and v.t.wdel = '1' and pcii.frame = '0' then -- (send last word in fifo) bug fix ***
-- v.t.trdy_del := '0';
--v.pci.trdy := '0';
--v.t.trdy_del := v.pci.trdy;
--else
v.t.trdy_del := v.pci.trdy;
--end if;
if r.t.state = s_data and r.pci.trdy = '1' and v.pci.trdy = '0' and pcii.frame = '0' then -- bug fix ***
readt_dly := '1';
v.t.fifo.raddr := r.t.fifo.raddr + (r.t.read and not fifort_limit and t_valid);
end if;
-- Latched signals to AHB backend
if (r.t.state = b_busy) then
if (hstart or hstart_ack) = '0' then -- must be idle
v.t.lwrite := not r.t.read;
if r.t.msel = '1' then
v.t.lburst := r.t.burst;
v.t.lcbe := pr.cbe;
if r.t.barsel = '0' then v.t.laddr := r.page & r.t.addr(MADDR_WIDTH-2 downto 2) & "00";
else v.t.laddr := r2.dmapage & r.t.addr(DMAMADDR_WIDTH-1 downto 2) & "00"; end if;
v.t.lmult := r.t.mult;
rtdone := '0'; v.t.fifo.waddr := (others => '0');
hstart := r.t.read and r.t.msel;
end if;
end if;
end if;
-- Read data mux
if r.t.csel = '1' then tad := cdata;
elsif r.t.psel = '1' then
tad(31 downto MADDR_WIDTH-1) := r.page;
tad(MADDR_WIDTH-2 downto 0) := zero32(MADDR_WIDTH-2 downto 1) & r.bt_enable;
-- elsif (r.t.state = b_busy or (r.pci.trdy or pcii.irdy) = '0') then tad := fifo1o.rdata(31 downto 0);
elsif (r.t.state = b_busy or (r.pci.trdy or pcii.irdy) = '0' or r.t.wdel = '1') then tad := byte_twist(fifo1o.rdata(31 downto 0), r.bt_enable); -- bug fix ***
end if;
-- FIFO controller
if ((fifowt_limit and write_access) = '1' or (r.t.last or rtdone) = '1') then
if hstart = hstart_ack then
if rtdone = '0' then hstart := not hstart_ack; v.t.fifo.side := hstart; end if;
if r.t.last = '1' then rtdone := '1'; v.t.last := '0';
else v.t.fifo.waddr := (others => '0');
if rtdone = '1' then
rtdone := '0'; hstart := '0'; v.t.fifo.side := '0';
end if;
end if;
end if;
end if;
-- Changed to only reset address counter when last word is transfered [nisse]
--if (fifort_limit and v.t.wdel) = '1' then
-- if hstart_ack = '1' then hstart := '0'; v.t.fifo.raddr := (others => '0');
-- else v.t.fifo.raddr := (others => '0'); end if;
--end if;
if hstart_ack = '1' and (fifort_limit and r.t.thold and not v.t.thold) = '1' then
hstart := '0'; v.t.fifo.raddr := (others => '0');
end if;
-- Hold AD if irdy waitstates after fifo switch [nisse]
if r.t.state = s_data and pcii.irdy = '1' and r.pci.trdy = '1' and v.pci.trdy = '0' and r.t.thold2 = '0' then v.t.thold2 := '1';
elsif r.t.thold2 = '1' and pcii.irdy = '0' then v.t.thold2 := '0'; end if;
----------------------
--- PCI TARGET END ---
----------------------
------------------
--- PCI MASTER ---
------------------
if MASTER = 1 then
bus_idle := pcii.frame and pcii.irdy;
data_transfer := not (pcii.trdy or r.pci.irdy);
data_transfer_r := not (pr.trdy or pr.irdy);
data_phase := not ((pcii.trdy and pcii.stop) or r.pci.irdy);
targ_d_w_data := not (pr.stop or pr.trdy);
targ_abort := pr.devsel and not pr.stop;
-- Request from AHB backend to start PCI transaction
if (pstart and not pstart_ack) = '1' then
if (r.m.fstate = idle and r.m.request = '0') then
v.m.request := '1';
rmdone := '0'; v.m.valid := '1';
v.m.fifo.waddr := (others => '0');
v.m.hwrite := r2.s.pcicomm(0);
end if;
end if;
-- Master timeout and DEVSEL timeout
if ((pr.irdy and not pr.frame) or (pr.devsel and not r.pci.oe_frame)) = '1' then
if r.m.cnt /= "000" then v.m.cnt := r.m.cnt - 1;
else mto := '1'; end if;
else v.m.cnt := (others => '1'); end if;
-- Latency counter
if r.pci.frame = '0' then
if r.m.ltim > "00000000" then v.m.ltim := r.m.ltim - '1';
else lto := '1'; end if;
else
v.m.ltim := r.ltim;
end if;
-- Last data
case r2.s.pcicomm is
when MEM_R_MULT | MEM_R_LINE =>
if (r.m.fifo.waddr >= (FIFO_FULL - "10") and r.m.fifo.side = '1') then
comp := '1';
else comp := '0'; end if;
when MEM_WRITE | MEM_W_INV => comp := not r.m.valid;
when others => comp := '1';
end case;
-- Minimun latency
--if lto = '0' then grant := '0'; end if;
if lto = '0' then grant := '0'; -- latency timer bug fix
elsif pcii.gnt = '1' then v.m.lto := '1'; end if;
-- Data parity error detected
if (r.m.fstate /= idle and r.stat.dped = '0') then v.stat.dped := r.comm.per and not pcii.perr; end if;
-- FIFO control state machine
case r.m.fstate is
when idle =>
v.m.lto := '0';
if (r.m.request and bus_idle and not pcii.gnt) = '1' and (r.m.state = idle or r.m.state = dr_bus) then
v.m.fstate := addr; v.m.fifo.waddr := (others => '0'); v.m.fifo.side := '0'; m_request := '1';
end if;
when addr =>
-- if (wsdone = '1' and (r.m.fifo.raddr + '1') = r2.s.fifo.waddr) then v.m.valid := '0'; end if;
if (wsdone = '1' and ((r.m.fifo.raddr + '1') = r2.s.fifo.waddr) and (m_read_side = r2.s.last_side)) then v.m.valid := '0'; end if; --bug fix kc
if fiform_limit = '1' then v.m.fstate := last1;
else v.m.fstate := incr; end if;
v.m.fifo.raddr := r.m.fifo.raddr + r.m.hwrite;
v.m.first := '1'; v.m.firstw := '1';
when incr =>
d_ready := '1';
if r.m.valid = '0' then v.m.lto := '0'; end if; -- dont look at latency timer if done
if data_transfer = '1' then
--if fiform_limit = '1' then v.m.fstate := last1; v.m.split := not backendnr; end if;
if fiform_limit = '1' and r.m.lto = '0' then v.m.fstate := last1; v.m.split := not backendnr; end if; -- bug fix latency timer
-- if (wsdone = '1' and (r.m.fifo.raddr + pcii.stop) = r2.s.fifo.waddr) then v.m.valid := '0'; end if;
if (wsdone = '1' and ((r.m.fifo.raddr + pcii.stop) = r2.s.fifo.waddr) and (m_read_side = r2.s.last_side)) then v.m.valid := '0'; end if; --bug fix kc
v.m.fifo.raddr := r.m.fifo.raddr + r.m.hwrite;
v.m.first := '0';
end if;
if data_transfer_r = '1' then
if fifowm_stop = '1' then
if r.m.firstw = '1' then
if (fifowm_limit and pr.stop) = '1' then v.m.fifo.side := not r.m.fifo.side; v.m.firstw := '0'; pstart_ack := pstart; end if;
end if;
end if;
v.m.fifo.waddr := r.m.fifo.waddr + (not r.m.hwrite);
end if;
if pr.stop = '0' then
if targ_abort = '1' then v.m.fstate := abort;
elsif targ_d_w_data = '1' then v.m.fstate := ttermwd;
elsif r.m.first = '1' then v.m.fstate := t_retry;
-- else v.m.fstate := ttermnd; end if;
else -- bug fix ***
-- if r.m.fifo.waddr = "0000000" then v.m.rmdone := '1'; end if;
if r.m.fifo.waddr = zero32(FIFO_DEPTH - 2 downto 0) then v.m.rmdone := '1'; end if;
v.m.fstate := ttermnd;
end if;
elsif mto = '1' then v.m.fstate := abort;
--elsif grant = '1' then -- pci_gnt bug fix
-- if r.m.hwrite = '0' then rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; v.m.fstate := done; pstart_ack := pstart;
-- else v.m.fstate := idle; end if;
--elsif (pr.frame and not r.m.first) = '1' then
elsif (pr.frame and not pr.trdy and not r.m.first) = '1' then -- not done if target not ready *** bug fix
if r.m.hwrite = '0' then rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; v.m.fstate := done; pstart_ack := pstart;
--else v.m.fstate := done; pstart_ack := pstart; end if;
else
if r.m.lto = '1' then -- latency timer bug fix
v.m.fifo.raddr := r.m.fifo.raddr - r.m.hwrite;
v.m.fstate := idle;
else
v.m.fstate := done; pstart_ack := pstart;
end if;
end if;
elsif (pr.devsel and not r.m.first) = '1' then
if r.m.hwrite = '0' then rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; v.m.fstate := done; pstart_ack := pstart;
else v.m.fstate := idle; end if;
end if;
when last1 =>
if (pr.trdy and not pr.stop) = '1' then
if targ_abort = '1' then v.m.fstate := abort;
elsif targ_d_w_data = '1' then v.m.fstate := ttermwd;
else v.m.fstate := ttermnd; v.m.valid := '1'; end if;
--elsif (pr.frame and not r.m.first and not r.m.split) = '1' then v.m.fstate := done; rmdone := not r.m.fifo.side; pstart_ack := pstart;
-- not done if target not ready *** bug fix
elsif (pr.frame and not pr.trdy and not r.m.first and not r.m.split) = '1' then v.m.fstate := done; rmdone := not r.m.fifo.side; pstart_ack := pstart;
elsif data_transfer = '1' then
if r.m.valid = '1' then v.m.fstate := sync; pstart_ack := pstart;
else v.m.fstate := done; rmdone := not r.m.fifo.side; pstart_ack := pstart; end if;
else d_ready := '1';
end if;
when sync =>
if pstart = not pstart_ack then
v.m.split := '0';
if ((r.m.split or (pr.trdy and not pr.stop and not r.m.split)) = '1' or r.m.state /= m_data) then v.m.fstate := idle; d_ready := '1';
else
--if (wsdone = '1' and (r.m.fifo.raddr + '1') = r2.s.fifo.waddr) then v.m.valid := '0'; end if;
if (r2.trans(4) = '1' and (r.m.fifo.raddr + '1') = r2.s.fifo.waddr) then v.m.valid := '0'; end if; -- not synced wsdone
v.m.fstate := incr; data_transfer := '1'; v.m.fifo.raddr := r.m.fifo.raddr + r.m.hwrite; d_ready := '1';
end if;
else m_read_side := '1';
end if;
when t_retry =>
v.m.fifo.raddr := r.m.fifo.raddr - r.m.hwrite; v.m.fstate := idle;
when ttermwd =>
if data_transfer = '1' then v.m.fifo.raddr := r.m.fifo.raddr + r.m.hwrite;
elsif pr.trdy = '1' then v.m.fifo.raddr := r.m.fifo.raddr - r.m.hwrite;
if (r.m.hwrite and r.m.valid) = '1' then v.m.fstate := idle;
else v.m.fstate := done; rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; pstart_ack := pstart; end if;
end if;
when ttermnd =>
if r.m.hwrite = '1' then
v.m.fifo.raddr := r.m.fifo.raddr - '1';
-- if (r.m.fifo.raddr /= (r2.s.fifo.waddr + '1') or wsdone = '0') then v.m.valid := '1'; v.m.fstate := idle; -- bug fix ***
if (r.m.fifo.raddr /= (r2.s.fifo.waddr + '1') or wsdone = '0' or r.m.valid = '1') then v.m.valid := '1'; v.m.fstate := idle;
else v.m.fstate := done; rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; pstart_ack := pstart; end if;
-- else v.m.fstate := done; rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; pstart_ack := pstart; end if;
else v.m.fstate := done; rmdone := (not r.m.fifo.side or r.m.rmdone); v.m.fifo.side := '1'; pstart_ack := pstart; end if; -- bug fix ***
when abort =>
v.m.fifo.raddr := (others => '0'); v.m.fifo.waddr := (others => '0');
v.m.fstate := done; pstart_ack := pstart; pabort := '1';
when done =>
d_ready := '1'; comp := '1'; v.m.request := '0';
if (pstart or pstart_ack) = '0' then
v.m.fstate := wdone; v.m.fifo.raddr := (others => '0'); v.m.fifo.side := '0'; rmdone := '1';
else pstart_ack := pstart; end if;
when wdone =>
d_ready := '1'; comp := '1';
if (r.m.state = idle or r.m.state = dr_bus) then v.m.fstate := idle; pabort := '0'; end if;
end case;
-- PCI master state machine
case r.m.state is
when idle => -- Master idle
v.m.stopframe := '0';
if (pcii.gnt = '0' and bus_idle = '1') then
if m_request = '1' then v.m.state := addr;
else v.m.state := dr_bus; end if;
end if;
when addr => -- Always one address cycle at the beginning of an transaction
v.m.stopframe := '0';
v.m.state := m_data;
when m_data => -- Master transfers data
if r.m.hwrite = '0' then v.m.detectperr(0) := '1'; end if; -- Only detect perr on read
if r.pci.frame = '1' then v.m.stopframe := '1'; end if; -- ***
if (r.pci.frame = '0') or ((r.pci.frame and pcii.trdy and pcii.stop and not mto) = '1') then
v.m.state := m_data;
if (r.pci.frame and not d_ready) = '1' then d_ready := '1'; end if;
elsif ((r.pci.frame and (mto or not pcii.stop)) = '1') then
v.m.state := s_tar;
v.m.stop_req := '1';
else v.m.state := turn_ar; end if;
when turn_ar => -- Transaction complete
v.m.detectperr(0) := '0';
if pcii.gnt = '0' then
if m_request = '1' then v.m.state := addr;
else v.m.state := dr_bus; end if;
else v.m.state := idle; end if;
when s_tar => -- Stop was asserted
v.m.detectperr(0) := '0';
if pcii.gnt = '0' then v.m.state := dr_bus;
else v.m.state := idle; end if;
when dr_bus => -- Drive bus when parked on this agent
if pcii.gnt = '1' then v.m.state := idle;
elsif m_request = '1' then v.m.state := addr; end if;
end case;
-- FIFO write strobe
m_fifo_write := not r.m.hwrite and not pr.irdy and not (pr.trdy and (pr.stop or not r.trans(3))) and not r.pci.oe_irdy;
-- PCI data mux
if v.m.state = addr then
if r.m.hwrite = '1' then mad := (r2.s.maddr + ((((not r2.s.fifo.side) & r.m.fifo.raddr)) & "00"));
else mad := r2.s.maddr; end if;
elsif (r.m.state = addr or data_transfer = '1') then mad := fifo3o.rdata(31 downto 0);
end if;
-- Target abort
if ((pr.devsel and pr.trdy and not pr.gnt and not pr.stop) = '1') then v.stat.rta := '1'; end if;
-- Master abort
if mto = '1' then v.stat.rma := '1'; end if;
-- Drive FRAME# and IRDY#
if (v.m.state = addr or v.m.state = m_data) then v.pci.oe_frame := '0'; end if;
-- Drive CBE#
if (v.m.state = addr or v.m.state = m_data or v.m.state = dr_bus) then v.pci.oe_cbe := '0'; end if;
-- Drive IRDY# (FRAME# delayed one pciclk)
v.pci.oe_irdy := r.pci.oe_frame;
-- FRAME# assert
if (v.m.state = addr or (v.m.state = m_data and mto = '0' and v.m.stopframe = '0' -- stopframe fix frame when pci_gnt is deasserted
--and ((((pcii.stop or not d_ready) and not (comp or v.m.split or not v.m.valid)) and not grant)) = '1')) -- dont change frame when gnt = 1 if not irdy and trdy or stop
and ((((pcii.stop or not d_ready) and not (comp or v.m.split or not v.m.valid)) and not (grant and not pr.irdy and (not pcii.trdy or not pcii.stop) ) )) = '1'))
then
v.pci.frame := '0';
end if;
-- IRDY# assert
if (v.m.state = m_data and ((d_ready or mto or (not r.m.valid) or (v.pci.frame and not r.pci.frame)) = '1')) then v.pci.irdy := '0'; end if;
-- REQ# assert
if ((v.m.request = '1' and (r.m.fstate = idle or comp = '0')) and (v.m.stop_req or r.m.stop_req) = '0') then v.pci.req := '0'; end if;
-- C/BE# assert
if v.m.state = addr then v.pci.cbe := r2.s.pcicomm; else v.pci.cbe := r2.s.be; end if;
end if;
---------------------
---PCI MASTER END ---
---------------------
----------------------
--- SHARED SIGNALS ---
----------------------
v.m.detectperr(1) := r.m.detectperr(0);
v.t.detectperr(1) := r.t.detectperr(0);
-- Drive PAR one clock after AD
v.pci.oe_par := r.pci.oe_ad;
v.pci.par := xorv(r.pci.ad & r.pci.cbe); -- Default asserted by master
-- PERR error
if (r.m.detectperr(0) = '1' or (r.m.detectperr(1) and not r.pci.perr) = '1') -- Drive perr for master:read
or (r.t.detectperr(0) = '1' or (r.t.detectperr(1) and not r.pci.perr) = '1') then -- Drive perr for target:write
v.pci.oe_perr := not(r.comm.per and r.pci.oe_par and not (pr.irdy and pr.trdy)) and (r.pci.oe_perr or r.pci.perr);
else
v.pci.oe_perr := (r.pci.oe_perr or r.pci.perr);
end if;
v.pci.perr := not (pcii.par xor xorv(pr.ad & pr.cbe)) or pr.irdy or pr.trdy; -- Detect parity error
v.pci.ad := mad; -- Default asserted by master
-- Master drives AD
if (v.m.state = addr or (v.m.state = m_data and r.m.hwrite = '1') or v.m.state = dr_bus) then
v.pci.oe_ad := '0';
end if;
-- Target drives AD
if r.t.read = '1' then
if v.t.state = s_data then
v.pci.oe_ad := '0';
--v.pci.ad := tad; end if;
-- Hold AD when master adds waitstates [nisse]
if (v.t.thold = '0' or (v.t.trdy_del = '0' and r.t.trdy_del = '0')) and v.t.thold2 = '0' and (pcii.irdy and not r.pci.trdy) = '0' then v.pci.ad := tad; end if;
end if;
if r.t.state = s_data then
v.pci.par := xorv(r.pci.ad & pcii.cbe);
end if;
end if;
adin <= v.pci.ad;
v.noe_ad := not v.pci.oe_ad;
v.noe_ctrl := not v.pci.oe_ctrl;
v.noe_par := not v.pci.oe_par;
v.noe_req := not v.pci.oe_req;
v.noe_frame := not v.pci.oe_frame;
v.noe_cbe := not v.pci.oe_cbe;
v.noe_irdy := not v.pci.oe_irdy;
v.noe_perr := not v.pci.oe_perr;
v.noe_serr := not v.pci.oe_serr;
if (scanen = 1) and (syncrst = 1) and (ahbmi.testen = '1') then
voe_ad := (others => ahbmi.testoen);
oe_ad := '1';
oe_ctrl := '1';
oe_par := '1';
oe_req := '1';
oe_frame := '1';
oe_cbe := '1';
oe_irdy := '1';
oe_perr := '1';
oe_serr := '1';
elsif oepol = 0 then
if (syncrst = 1) and (pcirstin = '0') then
voe_ad := (others => '1');
oe_ad := '1';
oe_ctrl := '1';
oe_par := '1';
oe_req := '1';
oe_frame := '1';
oe_cbe := '1';
oe_irdy := '1';
oe_perr := '1';
else
voe_ad := (others => v.pci.oe_ad);
oe_ad := r.pci.oe_ad;
oe_ctrl := r.pci.oe_ctrl;
oe_par := r.pci.oe_par;
oe_req := r.pci.oe_req;
oe_frame := r.pci.oe_frame;
oe_cbe := r.pci.oe_cbe;
oe_irdy := r.pci.oe_irdy;
oe_perr := r.pci.oe_perr;
oe_serr := r.pci.oe_serr;
end if;
else -- oepol = 1
if (syncrst = 1) and (pcirstin = '0') then
voe_ad := (others => '0');
oe_ad := '0';
oe_ctrl := '0';
oe_par := '0';
oe_req := '0';
oe_frame := '0';
oe_cbe := '0';
oe_irdy := '0';
oe_perr := '0';
else
voe_ad := (others => v.noe_ad);
oe_ad := r.noe_ad;
oe_ctrl := r.noe_ctrl;
oe_par := r.noe_par;
oe_req := r.noe_req;
oe_frame := r.noe_frame;
oe_cbe := r.noe_cbe;
oe_irdy := r.noe_irdy;
oe_perr := r.noe_perr;
oe_serr := r.noe_serr;
end if;
end if;
--------------------------
--- SHARED SIGNALS END ---
--------------------------
v.trans(0) := hstart;
v.trans(1) := pabort;
v.trans(2) := pstart_ack;
v.trans(3) := pcidc;
v.trans(4) := rtdone;
v.trans(5) := rmdone;
if prrst = '0' then
v.t.state := idle; v.m.state := idle; v.m.fstate := idle;
v.bar0 := (others => '0'); v.bar0_conf := '0';
v.bar1 := (others => '0'); v.bar1_conf := '0';
v.t.msel := '0'; v.t.csel := '0';
v.t.pending := '0'; v.t.lwrite := '0';
v.bt_enable := '1'; -- twisting enabled by default, changed through page0
v.page(31 downto 30) := "01";
v.page(29 downto MADDR_WIDTH-1) := zero32(29 downto MADDR_WIDTH-1);
v.pci.par := '0';
v.comm.msen := not pr.host;
v.comm.men := '0';
v.comm.mwie := '0';
v.comm.per := '0';
v.comm.ser := '0';
v.stat.rta := '0';
v.stat.rma := '0';
v.stat.sta := '0';
v.stat.dped := '0';
v.stat.dpe := '0';
v.stat.sse := '0';
v.cline := (others => '0');
v.ltim := (others => '0');
v.intline := (others => '0');
v.trans := (others => '0');
v.t.fifo.waddr := (others => '0');
v.t.fifo.raddr := (others => '0');
v.m.fifo.waddr := (others => '0');
v.m.fifo.raddr := (others => '0');
v.t.fifo.side := '0';
v.m.fifo.side := '0';
v.m.request := '0';
v.m.hwrite := '0';
v.m.valid := '1';
v.m.split := '0';
v.m.last := '0'; v.t.last := '0';
v.t.laddr := (others => '0'); -- to remove x problem in gate-simulation
v.m.detectperr(0) := '0'; v.t.detectperr(0) := '0';
end if;
cbe_fifoi.wen <= t_fifo_write;
cbe_fifoi.waddr <= r.t.fifo.side & r.t.fifo.waddr;
cbe_fifoi.wdata(3 downto 0) <= pr.cbe;
fifo2i.wen <= t_fifo_write;
fifo2i.waddr <= r.t.fifo.side & r.t.fifo.waddr;
fifo2i.wdata <= byte_twist(pr.ad, r.bt_enable);
fifo1i.ren <= '1';
fifo1i.raddr <= t_read_side & (r.t.fifo.raddr + readt_dly);
fifo4i.wen <= m_fifo_write;
fifo4i.waddr <= r.m.fifo.side & r.m.fifo.waddr;
fifo4i.wdata <= pr.ad;
fifo3i.ren <= '1';
fifo3i.raddr <= m_read_side & (r.m.fifo.raddr + data_transfer);
rin <= v;
rioe_ad <= voe_ad;
pcio.cbeen <= (others => oe_cbe);
pcio.cbe <= r.pci.cbe;
pcio.vaden <= roe_ad;
pcio.aden <= oe_ad;
pcio.ad <= ad;
-- pcio.trdy <= r.pci.trdy;
pcio.trdy <= r.t.trdy_del; -- (send last word in fifo) bug fix ***
pcio.ctrlen <= oe_ctrl;
pcio.trdyen <= oe_ctrl;
pcio.devselen <= oe_ctrl;
pcio.stopen <= oe_ctrl;
pcio.stop <= r.pci.stop;
pcio.devsel <= r.pci.devsel;
pcio.par <= r.pci.par;
pcio.paren <= oe_par;
pcio.perren <= oe_perr;
pcio.perr <= r.pci.perr;
pcio.serr <= r.pci.serr;
pcio.serren <= oe_serr;
pcio.reqen <= oe_req;
pcio.req <= r.pci.req;
pcio.frameen <= oe_frame;
pcio.frame <= r.pci.frame;
pcio.irdyen <= oe_irdy;
pcio.irdy <= r.pci.irdy;
end process;
rstinputgen : if hostrst = 0 generate
pcirstin <= pcii.rst;
pcio.rst <= '1';
end generate;
hostrstgen : if hostrst = 1 generate
--pcirstin <= rst when pcii.host = '0' else pcii.rst;
pcirstin <= pcii.rst;
pcio.rst <= rst when pcii.host = '0' else '1';
end generate;
pcirst <= ahbmi.testrst when (scanen = 1) and (ahbmi.testen = '1')
else pcirstin;
pr_regs : process (pciclk)
begin
if rising_edge (pciclk) then
pr.ad <= to_x01(pcii.ad);
pr.cbe <= to_x01(pcii.cbe);
pr.devsel <= to_x01(pcii.devsel);
pr.frame <= to_x01(pcii.frame);
pr.idsel <= to_x01(pcii.idsel);
pr.irdy <= to_x01(pcii.irdy);
pr.trdy <= to_x01(pcii.trdy);
pr.par <= to_x01(pcii.par);
pr.stop <= to_x01(pcii.stop);
prrst <= to_x01(pcirstin);
pr.gnt <= to_x01(pcii.gnt);
pr.host <= to_x01(pcii.host);
end if;
end process;
regs : process (pciclk, pcirst)
begin
if rising_edge (pciclk) then
r <= rin; ad <= adin;
end if;
if (syncrst = 0) and (pcirst = '0') then -- asynch reset required
r.pci.oe_ad <= '1'; r.pci.oe_ctrl <= '1'; r.pci.oe_par <= '1';
r.pci.oe_req <= '1'; r.pci.oe_frame <= '1'; r.pci.oe_cbe <= '1';
r.pci.oe_irdy <= '1'; r.pci.oe_perr <= '1';
r.noe_ad <= '0'; r.noe_ctrl <= '0'; r.noe_par <= '0';
r.noe_req <= '0'; r.noe_frame <= '0'; r.noe_cbe <= '0';
r.noe_irdy <= '0'; r.noe_perr <= '0';
end if;
end process;
oeregs_pol0 : if oepol = 0 generate
oeregs : process (pciclk, pcirst)
begin
if rising_edge (pciclk) then
roe_ad <= rioe_ad;
end if;
if (syncrst = 0) and (pcirst = '0') then -- asynch reset required
roe_ad <= (others => '1');
end if;
end process;
end generate;
oeregs_pol1 : if oepol = 1 generate
oeregs : process (pciclk, pcirst)
begin
if rising_edge (pciclk) then
roe_ad <= rioe_ad;
end if;
if (syncrst = 0) and (pcirst = '0') then -- asynch reset required
roe_ad <= (others => '0');
end if;
end process;
end generate;
cpur : process (clk)
begin
if rising_edge (clk) then
r2 <= r2in;
end if;
end process;
oe0 : if oepol = 0 generate
pcio.inten <= '1';
pcio.vinten <= (others => '1');
pcio.locken <= '1';
end generate;
oe1 : if oepol = 1 generate
pcio.inten <= '0';
pcio.vinten <= (others => '0');
pcio.locken <= '0';
end generate;
pcio.int <= '1';
pcio.lock <= '1';
pcio.power_state <= (others => '0');
pcio.pme_enable <= '0';
pcio.pme_clear <= '0';
msttgt : if MASTER = 1 generate
ahbmst0 : pciahbmst generic map (hindex => hmstndx, devid => GAISLER_PCIFBRG, incaddr => 1)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
fifo1 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (pciclk, fifo1i.ren, fifo1i.raddr, fifo1o.rdata, clk, fifo1i.wen, fifo1i.waddr, fifo1i.wdata);
fifo2 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (clk, fifo2i.ren, fifo2i.raddr, fifo2o.rdata, pciclk, fifo2i.wen, fifo2i.waddr, fifo2i.wdata);
fifo3 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (pciclk, fifo3i.ren, fifo3i.raddr, fifo3o.rdata, clk, fifo3i.wen, fifo3i.waddr, fifo3i.wdata);
fifo4 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (clk, fifo4i.ren, fifo4i.raddr, fifo4o.rdata, pciclk, fifo4i.wen, fifo4i.waddr, fifo4i.wdata);
cbe_fifo : syncram_2p generic map (tech => 0, abits => FIFO_DEPTH, dbits => 4, sepclk => 1)
port map (clk, cbe_fifoi.ren, cbe_fifoi.raddr, cbe_fifoo.rdata(3 downto 0), pciclk, cbe_fifoi.wen, cbe_fifoi.waddr, cbe_fifoi.wdata(3 downto 0));
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mtf" & tost(hslvndx) &
": 32-bit PCI/AHB bridge rev " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR, " &
tost(2**FIFO_DEPTH) & "-word FIFOs" );
-- pragma translate_on
end generate;
tgtonly : if MASTER = 0 generate
ahbmst0 : pciahbmst generic map (hindex => hmstndx, devid => GAISLER_PCIFBRG, incaddr => 1)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
fifo1 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (pciclk, fifo1i.ren, fifo1i.raddr, fifo1o.rdata, clk, fifo1i.wen, fifo1i.waddr, fifo1i.wdata);
fifo2 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (clk, fifo2i.ren, fifo2i.raddr, fifo2o.rdata, pciclk, fifo2i.wen, fifo2i.waddr, fifo2i.wdata);
cbe_fifo : syncram_2p generic map (tech => 0, abits => FIFO_DEPTH, dbits => 4, sepclk => 1)
port map (clk, cbe_fifoi.ren, cbe_fifoi.raddr, cbe_fifoo.rdata(3 downto 0), pciclk, cbe_fifoi.wen, cbe_fifoi.waddr, cbe_fifoi.wdata(3 downto 0));
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mtf" & tost(hmstndx) &
": 32-bit PCI/AHB bridge rev, target-only, " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR, " &
tost(2**FIFO_DEPTH) & "-word FIFOs" );
-- pragma translate_on
end generate;
end;
| gpl-2.0 | 456dd72b2ed41a24a369bec0a3aaec27 | 0.463978 | 3.399514 | false | false | false | false |
dsaves/dsaves-hdl | dft/bscan_cell.vhd | 1 | 2,379 | --MIT License
--
--Copyright (c) 2017 Danny Savory
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
library ieee, dsaves;
use ieee.std_logic_1164.all;
entity bscan_cell is
port(
data_in : in std_logic;
scan_in : in std_logic;
shift_DR : in std_logic;
capture_DR : in std_logic;
update_DR : in std_logic;
mode : in std_logic;
trst : in std_logic;
data_out : out std_logic
);
end entity;
architecture POS_EDGE of BSCAN_CELL is
signal capture_reg_in : std_logic;
signal capture_reg_out : std_logic;
signal update_latch_out : std_logic;
begin
capture_reg_in <= data_in when shift_DR = '0' else
scan_in;
capture_reg_INST : entity dsaves.FF(POS_EDGE_HI_EN)
port map(
clk => capture_DR,
d => capture_reg_in,
en => '1',
rst => trst,
q => capture_reg_out
);
update_latch_INST : entity dsaves.LATCH(HI_EN)
port map(
clk => update_DR,
i => capture_reg_out,
o => update_latch_out
);
data_out <= data_in when mode = '0' else
update_latch_out;
end architecture;
| mit | f11f40d609dec5d6140ab34acad33921 | 0.610761 | 3.998319 | false | false | false | false |
JimLewis/OSVVM | NamePkg.vhd | 1 | 4,132 | --
-- File Name: NamePkg.vhd
-- Design Unit Name: NamePkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Package Defines
-- Data structure for name.
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 06/2010: 0.1 Initial revision
-- 07/2014: 2014.07 Moved specialization required by CoveragePkg to CoveragePkg
-- Separated name handling from message handling to simplify naming
-- 12/2014: 2014.07a Removed initialized pointers which can lead to memory leaks.
-- 05/2015 2015.06 Added input to Get to return when not initialized
-- 01/2020 2020.01 Updated Licenses to Apache
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2010 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
package NamePkg is
type NamePType is protected
procedure Set (NameIn : String) ;
impure function Get (DefaultName : string := "") return string ;
impure function GetOpt return string ;
impure function IsSet return boolean ;
procedure Clear ; -- clear name
procedure Deallocate ; -- effectively alias to clear name
end protected NamePType ;
end package NamePkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body NamePkg is
type NamePType is protected body
variable NamePtr : line ;
------------------------------------------------------------
procedure Set (NameIn : String) is
------------------------------------------------------------
begin
deallocate(NamePtr) ;
NamePtr := new string'(NameIn) ;
end procedure Set ;
------------------------------------------------------------
impure function Get (DefaultName : string := "") return string is
------------------------------------------------------------
begin
if NamePtr = NULL then
return DefaultName ;
else
return NamePtr.all ;
end if ;
end function Get ;
------------------------------------------------------------
impure function GetOpt return string is
------------------------------------------------------------
begin
if NamePtr = NULL then
return NUL & "" ;
else
return NamePtr.all ;
end if ;
end function GetOpt ;
------------------------------------------------------------
impure function IsSet return boolean is
------------------------------------------------------------
begin
return NamePtr /= NULL ;
end function IsSet ;
------------------------------------------------------------
procedure Clear is -- clear name
------------------------------------------------------------
begin
deallocate(NamePtr) ;
end procedure Clear ;
------------------------------------------------------------
procedure Deallocate is -- clear name
------------------------------------------------------------
begin
Clear ;
end procedure Deallocate ;
end protected body NamePType ;
end package body NamePkg ; | artistic-2.0 | 149865c196695d52f89ad5654468b863 | 0.483543 | 5.345408 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/iopad_ddr.vhd | 1 | 4,909 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad_ddr, iopad_ddrv, iopad_ddrvv
-- File: iopad_ddr.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: Wrapper that instantiates an iopad connected to DDR register.
-- Special case for easic90 tech since this tech requires that
-- oe is directly connected between DDR register and pad.
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allddr.all;
use techmap.allpads.all;
entity iopad_ddr is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
oepol : integer := 0);
port (
pad : inout std_ulogic;
i1, i2 : in std_ulogic; -- Input H and L
en : in std_ulogic; -- Output enable
o1, o2 : out std_ulogic; -- Output H and L
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic);
end;
architecture rtl of iopad_ddr is
signal oe, oen, d, q : std_ulogic;
begin
def: if (tech /= easic90) generate
p : iopad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad, q, en, d);
ddrregi : ddr_ireg generic map (tech)
port map (o1, o2, c1, c2, ce, d, r, s);
ddrrego : ddr_oreg generic map (tech)
port map (q, c1, c2, ce, i1, i2, r, s);
oe <= '0'; oen <= '0'; -- Not used in this configuration
end generate def;
nex : if (tech = easic90) generate
oen <= not en when oepol /= padoen_polarity(tech) else en;
p : nextreme_iopad generic map (level, slew, voltage, strength)
port map (pad, q, oe, d);
ddrregi : nextreme_iddr_reg
port map (ck => c1, d => d, qh => o1, ql => o2, rstb => r);
ddrrego : nextreme_oddr_reg
port map (ck => c1, dh => i1, dl => i2, doe => oen, q => q,
oe => oe, rstb => r);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_ddrv is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o1, o2 : out std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic);
end;
architecture rtl of iopad_ddrv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ddr generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i1(j), i2(j), en, o1(j), o2(j), c1, c2, ce, r, s);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_ddrvv is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o1, o2 : out std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic);
end;
architecture rtl of iopad_ddrvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ddr generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i1(j), i2(j), en(j), o1(j), o2(j), c1, c2, ce, r, s);
end generate;
end;
| gpl-2.0 | f4adbb14b0c4d00ebd1650260278a5b1 | 0.580159 | 3.380854 | false | false | false | false |
a4a881d4/ringbus4xilinx | src/example/rcbus2.vhd | 2 | 3,424 | ---------------------------------------------------------------------------------------------------
--
-- Title : Two End Point Example for Ring Control Bus
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : rcbus2.vhd
-- Generated : 2013/9/13
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : Ring Control bus example
-- two end point
--
-- Rev: 3.1
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.rb_config.all;
use work.contr_config.all;
entity RCBUS2 is
port(
-- system
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-- CPU bus
wr : in std_logic;
rd : in std_logic;
addr : in std_logic_vector( 7 downto 0 );
Din : in std_logic_vector( 7 downto 0 );
Dout : out std_logic_vector( 7 downto 0 );
cpuClk : in std_logic
);
end RCBUS2;
architecture behave of RCBUS2 is
component blockdram
generic(
depth: integer := 256;
Dwidth: integer := 8;
Awidth: integer := 8
);
port(
addra: IN std_logic_VECTOR(Awidth-1 downto 0);
clka: IN std_logic;
addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
clkb: IN std_logic;
dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
wea: IN std_logic;
reb: IN std_logic;
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0) := (others => '0')
);
end component;
signal mtx, mrx : std_logic_vector( 31 downto 0 );
signal mreq, mtx_sop, mrx_sop : std_logic_vector( 1 downto 0 );
signal laddr,ldin,ldout : std_logic_vector( 15 downto 0 );
signal lwr, lrd : std_logic;
signal cs0 : std_logic;
begin
busm:RBUS
generic map(
Bwidth => 16,
Num => 2
)
port map(
-- system
sync=>'0',
clk=>clk,
rst=>rst,
-- tx
tx => mtx,
Req => mreq,
tx_sop => mtx_sop,
-- rx
rx_sop => mrx_sop,
rx => mrx
);
mem:blockdram
generic map(
depth=>65536,
Dwidth=>16,
Awidth=>16
)
port map(
addra=>laddr,
clka=>clk,
addrb=>laddr,
clkb=>clk,
dia=>ldout,
wea=>wr,
reb=>rd,
dob=>ldin
);
slave:CSlave
generic map(
Bwidth => 16
)
port map(
-- system
clk => clk,
rst => rst,
-- send to bus
tx => mtx(31 downto 16 ),
Req => mreq(1),
tx_sop => mtx_sop(1),
en => '1',
-- read from bus
rx_sop => mrx_sop(1),
rx => mrx( 31 downto 16 ),
-- Local Bus
addr => laddr,
Din => ldin,
Dout => ldout,
wr => lwr,
rd => lrd
--
);
master:CMaster
generic map(
Bwidth => 16,
POS => 0,
myBusID => 0
)
port map(
-- system
-- system
clk => clk,
rst => rst,
-- send to bus
tx => mtx(15 downto 0 ),
Req => mreq(0),
tx_sop => mtx_sop(0),
en => '1',
-- read from bus
rx_sop => mrx_sop(0),
rx => mrx( 15 downto 0 ),
-- Local Bus
CS => cs0,
addr => addr( 3 downto 0 ),
wr => wr,
rd => rd,
Din => Din,
Dout => Dout,
cpuClk => cpuClk
--
);
cs0<='1' when addr(7 downto 4) = "0000" else '0';
end behave;
| gpl-2.0 | fcc7301514ae99096242dac076f9a39e | 0.469042 | 3.0194 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.cache/ip/2017.2/d5e322d2745b1271/zynq_design_1_axi_bram_ctrl_0_1_sim_netlist.vhdl | 1 | 330,319 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:30:00 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_axi_bram_ctrl_0_1_sim_netlist.vhdl
-- Design : zynq_design_1_axi_bram_ctrl_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
bid_gets_fifo_load : out STD_LOGIC;
bvalid_cnt_inc : out STD_LOGIC;
bid_gets_fifo_load_d1_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
axi_wdata_full_cmb114_out : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
\bvalid_cnt_reg[2]\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
\bvalid_cnt_reg[2]_0\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
bram_addr_ld_en : in STD_LOGIC;
bid_gets_fifo_load_d1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
axi_bvalid_int_reg : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
\bvalid_cnt_reg[1]\ : in STD_LOGIC;
aw_active : in STD_LOGIC;
s_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
axi_wr_burst : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO is
signal \Addr_Counters[0].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[1].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[2].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].XORCY_I_i_1_n_0\ : STD_LOGIC;
signal CI : STD_LOGIC;
signal D_0 : STD_LOGIC;
signal Data_Exists_DFF_i_2_n_0 : STD_LOGIC;
signal Data_Exists_DFF_i_3_n_0 : STD_LOGIC;
signal S : STD_LOGIC;
signal S0_out : STD_LOGIC;
signal S1_out : STD_LOGIC;
signal addr_cy_1 : STD_LOGIC;
signal addr_cy_2 : STD_LOGIC;
signal addr_cy_3 : STD_LOGIC;
signal \axi_bid_int[11]_i_3_n_0\ : STD_LOGIC;
signal axi_bvalid_int_i_4_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_5_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_6_n_0 : STD_LOGIC;
signal \^axi_wdata_full_cmb114_out\ : STD_LOGIC;
signal bid_fifo_ld : STD_LOGIC_VECTOR ( 11 downto 0 );
signal bid_fifo_not_empty : STD_LOGIC;
signal bid_fifo_rd : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^bid_gets_fifo_load\ : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_3_n_0 : STD_LOGIC;
signal \^bid_gets_fifo_load_d1_reg\ : STD_LOGIC;
signal \^bvalid_cnt_inc\ : STD_LOGIC;
signal sum_A_0 : STD_LOGIC;
signal sum_A_1 : STD_LOGIC;
signal sum_A_2 : STD_LOGIC;
signal sum_A_3 : STD_LOGIC;
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \Addr_Counters[0].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "LO:O";
attribute BOX_TYPE of \Addr_Counters[1].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[2].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[3].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of Data_Exists_DFF : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of Data_Exists_DFF : label is "FDR";
attribute BOX_TYPE of \FIFO_RAM[0].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name : string;
attribute srl_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I ";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FIFO_RAM[0].SRL16E_I_i_1\ : label is "soft_lutpair44";
attribute BOX_TYPE of \FIFO_RAM[10].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[10].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[10].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[10].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[10].SRL16E_I_i_1\ : label is "soft_lutpair54";
attribute BOX_TYPE of \FIFO_RAM[11].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[11].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[11].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[11].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[11].SRL16E_I_i_1\ : label is "soft_lutpair55";
attribute BOX_TYPE of \FIFO_RAM[1].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[1].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[1].SRL16E_I_i_1\ : label is "soft_lutpair45";
attribute BOX_TYPE of \FIFO_RAM[2].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[2].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[2].SRL16E_I_i_1\ : label is "soft_lutpair46";
attribute BOX_TYPE of \FIFO_RAM[3].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[3].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[3].SRL16E_I_i_1\ : label is "soft_lutpair47";
attribute BOX_TYPE of \FIFO_RAM[4].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[4].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[4].SRL16E_I_i_1\ : label is "soft_lutpair48";
attribute BOX_TYPE of \FIFO_RAM[5].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[5].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[5].SRL16E_I_i_1\ : label is "soft_lutpair49";
attribute BOX_TYPE of \FIFO_RAM[6].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[6].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[6].SRL16E_I_i_1\ : label is "soft_lutpair50";
attribute BOX_TYPE of \FIFO_RAM[7].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[7].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[7].SRL16E_I_i_1\ : label is "soft_lutpair51";
attribute BOX_TYPE of \FIFO_RAM[8].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[8].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[8].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[8].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[8].SRL16E_I_i_1\ : label is "soft_lutpair52";
attribute BOX_TYPE of \FIFO_RAM[9].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[9].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[9].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[9].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[9].SRL16E_I_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \axi_bid_int[0]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \axi_bid_int[10]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \axi_bid_int[11]_i_2\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \axi_bid_int[1]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \axi_bid_int[2]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \axi_bid_int[3]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \axi_bid_int[4]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \axi_bid_int[5]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \axi_bid_int[6]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \axi_bid_int[7]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axi_bid_int[8]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \axi_bid_int[9]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of axi_bvalid_int_i_3 : label is "soft_lutpair56";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_3 : label is "soft_lutpair56";
begin
axi_wdata_full_cmb114_out <= \^axi_wdata_full_cmb114_out\;
bid_gets_fifo_load <= \^bid_gets_fifo_load\;
bid_gets_fifo_load_d1_reg <= \^bid_gets_fifo_load_d1_reg\;
bvalid_cnt_inc <= \^bvalid_cnt_inc\;
\Addr_Counters[0].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_3,
Q => \Addr_Counters[0].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[0].MUXCY_L_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\(3),
CO(2) => addr_cy_1,
CO(1) => addr_cy_2,
CO(0) => addr_cy_3,
CYINIT => CI,
DI(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\(3),
DI(2) => \Addr_Counters[2].FDRE_I_n_0\,
DI(1) => \Addr_Counters[1].FDRE_I_n_0\,
DI(0) => \Addr_Counters[0].FDRE_I_n_0\,
O(3) => sum_A_0,
O(2) => sum_A_1,
O(1) => sum_A_2,
O(0) => sum_A_3,
S(3) => \Addr_Counters[3].XORCY_I_i_1_n_0\,
S(2) => S0_out,
S(1) => S1_out,
S(0) => S
);
\Addr_Counters[0].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[1].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[0].FDRE_I_n_0\,
O => S
);
\Addr_Counters[0].MUXCY_L_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAAAAAAAAAAAAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => \axi_bid_int[11]_i_3_n_0\,
I2 => \Addr_Counters[0].FDRE_I_n_0\,
I3 => \Addr_Counters[1].FDRE_I_n_0\,
I4 => \Addr_Counters[3].FDRE_I_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => CI
);
\Addr_Counters[1].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_2,
Q => \Addr_Counters[1].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[1].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[1].FDRE_I_n_0\,
O => S1_out
);
\Addr_Counters[2].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_1,
Q => \Addr_Counters[2].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[2].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => S0_out
);
\Addr_Counters[3].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_0,
Q => \Addr_Counters[3].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[3].XORCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[3].FDRE_I_n_0\,
O => \Addr_Counters[3].XORCY_I_i_1_n_0\
);
Data_Exists_DFF: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D_0,
Q => bid_fifo_not_empty,
R => SR(0)
);
Data_Exists_DFF_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE0A"
)
port map (
I0 => bram_addr_ld_en,
I1 => Data_Exists_DFF_i_2_n_0,
I2 => Data_Exists_DFF_i_3_n_0,
I3 => bid_fifo_not_empty,
O => D_0
);
Data_Exists_DFF_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFFD"
)
port map (
I0 => \^bvalid_cnt_inc\,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
I3 => bvalid_cnt(1),
I4 => \^bid_gets_fifo_load_d1_reg\,
I5 => bid_gets_fifo_load_d1,
O => Data_Exists_DFF_i_2_n_0
);
Data_Exists_DFF_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => \Addr_Counters[2].FDRE_I_n_0\,
O => Data_Exists_DFF_i_3_n_0
);
\FIFO_RAM[0].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(11),
Q => bid_fifo_rd(11)
);
\FIFO_RAM[0].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(11),
I1 => axi_awaddr_full,
I2 => s_axi_awid(11),
O => bid_fifo_ld(11)
);
\FIFO_RAM[10].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(1),
Q => bid_fifo_rd(1)
);
\FIFO_RAM[10].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awid(1),
O => bid_fifo_ld(1)
);
\FIFO_RAM[11].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(0),
Q => bid_fifo_rd(0)
);
\FIFO_RAM[11].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awid(0),
O => bid_fifo_ld(0)
);
\FIFO_RAM[1].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(10),
Q => bid_fifo_rd(10)
);
\FIFO_RAM[1].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(10),
I1 => axi_awaddr_full,
I2 => s_axi_awid(10),
O => bid_fifo_ld(10)
);
\FIFO_RAM[2].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(9),
Q => bid_fifo_rd(9)
);
\FIFO_RAM[2].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(9),
I1 => axi_awaddr_full,
I2 => s_axi_awid(9),
O => bid_fifo_ld(9)
);
\FIFO_RAM[3].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(8),
Q => bid_fifo_rd(8)
);
\FIFO_RAM[3].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(8),
I1 => axi_awaddr_full,
I2 => s_axi_awid(8),
O => bid_fifo_ld(8)
);
\FIFO_RAM[4].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(7),
Q => bid_fifo_rd(7)
);
\FIFO_RAM[4].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(7),
I1 => axi_awaddr_full,
I2 => s_axi_awid(7),
O => bid_fifo_ld(7)
);
\FIFO_RAM[5].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(6),
Q => bid_fifo_rd(6)
);
\FIFO_RAM[5].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(6),
I1 => axi_awaddr_full,
I2 => s_axi_awid(6),
O => bid_fifo_ld(6)
);
\FIFO_RAM[6].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(5),
Q => bid_fifo_rd(5)
);
\FIFO_RAM[6].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(5),
I1 => axi_awaddr_full,
I2 => s_axi_awid(5),
O => bid_fifo_ld(5)
);
\FIFO_RAM[7].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(4),
Q => bid_fifo_rd(4)
);
\FIFO_RAM[7].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(4),
I1 => axi_awaddr_full,
I2 => s_axi_awid(4),
O => bid_fifo_ld(4)
);
\FIFO_RAM[8].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(3),
Q => bid_fifo_rd(3)
);
\FIFO_RAM[8].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awid(3),
O => bid_fifo_ld(3)
);
\FIFO_RAM[9].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(2),
Q => bid_fifo_rd(2)
);
\FIFO_RAM[9].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => s_axi_awid(2),
O => bid_fifo_ld(2)
);
\axi_bid_int[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awid(0),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(0),
O => D(0)
);
\axi_bid_int[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(10),
I1 => axi_awaddr_full,
I2 => s_axi_awid(10),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(10),
O => D(10)
);
\axi_bid_int[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^bid_gets_fifo_load\,
I1 => \axi_bid_int[11]_i_3_n_0\,
O => E(0)
);
\axi_bid_int[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(11),
I1 => axi_awaddr_full,
I2 => s_axi_awid(11),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(11),
O => D(11)
);
\axi_bid_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A888AAAAA8888888"
)
port map (
I0 => bid_fifo_not_empty,
I1 => bid_gets_fifo_load_d1,
I2 => s_axi_bready,
I3 => axi_bvalid_int_reg,
I4 => bid_gets_fifo_load_d1_i_3_n_0,
I5 => \^bvalid_cnt_inc\,
O => \axi_bid_int[11]_i_3_n_0\
);
\axi_bid_int[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awid(1),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(1),
O => D(1)
);
\axi_bid_int[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => s_axi_awid(2),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(2),
O => D(2)
);
\axi_bid_int[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awid(3),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(3),
O => D(3)
);
\axi_bid_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(4),
I1 => axi_awaddr_full,
I2 => s_axi_awid(4),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(4),
O => D(4)
);
\axi_bid_int[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(5),
I1 => axi_awaddr_full,
I2 => s_axi_awid(5),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(5),
O => D(5)
);
\axi_bid_int[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(6),
I1 => axi_awaddr_full,
I2 => s_axi_awid(6),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(6),
O => D(6)
);
\axi_bid_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(7),
I1 => axi_awaddr_full,
I2 => s_axi_awid(7),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(7),
O => D(7)
);
\axi_bid_int[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(8),
I1 => axi_awaddr_full,
I2 => s_axi_awid(8),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(8),
O => D(8)
);
\axi_bid_int[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(9),
I1 => axi_awaddr_full,
I2 => s_axi_awid(9),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(9),
O => D(9)
);
axi_bvalid_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000055FD00000000"
)
port map (
I0 => \out\(2),
I1 => \^axi_wdata_full_cmb114_out\,
I2 => axi_bvalid_int_i_4_n_0,
I3 => axi_wr_burst,
I4 => \out\(1),
I5 => axi_bvalid_int_i_5_n_0,
O => \^bvalid_cnt_inc\
);
axi_bvalid_int_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FE000000"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => axi_bvalid_int_reg,
I4 => s_axi_bready,
O => \^bid_gets_fifo_load_d1_reg\
);
axi_bvalid_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"1F11000000000000"
)
port map (
I0 => axi_bvalid_int_i_6_n_0,
I1 => \bvalid_cnt_reg[2]\,
I2 => wr_addr_sm_cs,
I3 => \bvalid_cnt_reg[2]_0\,
I4 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I5 => axi_awaddr_full,
O => axi_bvalid_int_i_4_n_0
);
axi_bvalid_int_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"74446444"
)
port map (
I0 => \out\(0),
I1 => \out\(2),
I2 => s_axi_wvalid,
I3 => s_axi_wlast,
I4 => \^axi_wdata_full_cmb114_out\,
O => axi_bvalid_int_i_5_n_0
);
axi_bvalid_int_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFFFFFF"
)
port map (
I0 => curr_awlen_reg_1_or_2,
I1 => axi_awlen_pipe_1_or_2,
I2 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I3 => axi_awaddr_full,
I4 => last_data_ack_mod,
O => axi_bvalid_int_i_6_n_0
);
axi_wready_int_mod_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"7F7F7F007F007F00"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => aw_active,
I4 => s_axi_awready,
I5 => s_axi_awvalid,
O => \^axi_wdata_full_cmb114_out\
);
bid_gets_fifo_load_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000800AA00AA00"
)
port map (
I0 => bram_addr_ld_en,
I1 => \^bid_gets_fifo_load_d1_reg\,
I2 => bid_fifo_not_empty,
I3 => \^bvalid_cnt_inc\,
I4 => \bvalid_cnt_reg[1]\,
I5 => bid_gets_fifo_load_d1_i_3_n_0,
O => \^bid_gets_fifo_load\
);
bid_gets_fifo_load_d1_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => bid_gets_fifo_load_d1_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_addr_ld_en_mod : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : out STD_LOGIC;
bram_addr_ld_en : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_1\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_2\ : out STD_LOGIC;
curr_fixed_burst_reg_reg : out STD_LOGIC;
curr_wrap_burst_reg_reg : out STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
bram_addr_inc : in STD_LOGIC;
bram_addr_rst_cmb : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC;
bram_addr_a : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
aw_active : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_awsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
curr_fixed_burst : in STD_LOGIC;
curr_wrap_burst : in STD_LOGIC;
s_axi_aresetn_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst is
signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[8]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal bram_addr_ld : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^bram_addr_ld_en_mod\ : STD_LOGIC;
signal save_init_bram_addr_ld : STD_LOGIC_VECTOR ( 15 downto 3 );
signal \save_init_bram_addr_ld[3]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_1\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_2\ : STD_LOGIC;
signal wrap_burst_total : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \wrap_burst_total[0]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_2_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_3_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_3__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \curr_wrap_burst_reg_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[15]_i_4\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[3]_i_2__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_2\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_3\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3__0\ : label is "soft_lutpair57";
begin
D(13 downto 0) <= \^d\(13 downto 0);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[8]\;
SR(0) <= \^sr\(0);
bram_addr_ld_en <= \^bram_addr_ld_en\;
bram_addr_ld_en_mod <= \^bram_addr_ld_en_mod\;
\save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\;
\save_init_bram_addr_ld_reg[15]_1\ <= \^save_init_bram_addr_ld_reg[15]_1\;
\save_init_bram_addr_ld_reg[15]_2\ <= \^save_init_bram_addr_ld_reg[15]_2\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB8BBBBB88B88888"
)
port map (
I0 => bram_addr_ld(8),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(7),
I5 => bram_addr_a(8),
O => \^d\(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(9),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(9),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\,
I4 => bram_addr_a(8),
O => \^d\(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(12),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(10),
O => \^d\(10)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(13),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(11),
O => \^d\(11)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(14),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(12),
O => \^d\(12)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"4500FFFF"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => bram_addr_inc,
I3 => bram_addr_rst_cmb,
I4 => s_axi_aresetn,
O => \^sr\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => \^bram_addr_ld_en_mod\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(15),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(13),
O => \^d\(13)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555555FFFFFFDF"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => wrap_burst_total(1),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(0),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00C000"
)
port map (
I0 => bram_addr_a(2),
I1 => bram_addr_a(1),
I2 => wrap_burst_total(1),
I3 => bram_addr_a(0),
I4 => wrap_burst_total(0),
I5 => wrap_burst_total(2),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B800B800FFFF"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
I1 => axi_awaddr_full,
I2 => s_axi_awaddr(0),
I3 => \^bram_addr_ld_en\,
I4 => \^bram_addr_ld_en_mod\,
I5 => bram_addr_a(0),
O => \^d\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BB8"
)
port map (
I0 => bram_addr_ld(1),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(1),
I3 => bram_addr_a(0),
O => \^d\(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BB8B8B8"
)
port map (
I0 => bram_addr_ld(2),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(2),
I3 => bram_addr_a(0),
I4 => bram_addr_a(1),
O => \^d\(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8BB8B8B8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(3),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(3),
I3 => bram_addr_a(2),
I4 => bram_addr_a(0),
I5 => bram_addr_a(1),
O => \^d\(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B88B"
)
port map (
I0 => bram_addr_ld(4),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(4),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
O => \^d\(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(5),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(5),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I4 => bram_addr_a(4),
O => \^d\(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B88BB8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(6),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => bram_addr_a(4),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => bram_addr_a(5),
O => \^d\(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => bram_addr_a(1),
I1 => bram_addr_a(0),
I2 => bram_addr_a(2),
I3 => bram_addr_a(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(7),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(6),
O => \^d\(7)
);
\curr_fixed_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_fixed_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_fixed_burst,
I3 => \^sr\(0),
O => curr_fixed_burst_reg_reg
);
\curr_wrap_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_wrap_burst,
I3 => \^sr\(0),
O => curr_wrap_burst_reg_reg
);
\save_init_bram_addr_ld[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(10),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(8),
O => bram_addr_ld(8)
);
\save_init_bram_addr_ld[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(11),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(9),
O => bram_addr_ld(9)
);
\save_init_bram_addr_ld[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808080808AA0808"
)
port map (
I0 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I1 => \^save_init_bram_addr_ld_reg[15]_0\,
I2 => wr_addr_sm_cs,
I3 => \^save_init_bram_addr_ld_reg[15]_1\,
I4 => last_data_ack_mod,
I5 => \^save_init_bram_addr_ld_reg[15]_2\,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"007F007F007F0000"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
I3 => aw_active,
I4 => axi_awaddr_full,
I5 => s_axi_awvalid,
O => \^save_init_bram_addr_ld_reg[15]_0\
);
\save_init_bram_addr_ld[15]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => \^save_init_bram_addr_ld_reg[15]_1\
);
\save_init_bram_addr_ld[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I2 => axi_awlen_pipe_1_or_2,
I3 => curr_awlen_reg_1_or_2,
O => \^save_init_bram_addr_ld_reg[15]_2\
);
\save_init_bram_addr_ld[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2__0_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(1),
O => bram_addr_ld(1)
);
\save_init_bram_addr_ld[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"C80C"
)
port map (
I0 => wrap_burst_total(0),
I1 => save_init_bram_addr_ld(3),
I2 => wrap_burst_total(1),
I3 => wrap_burst_total(2),
O => \save_init_bram_addr_ld[3]_i_2__0_n_0\
);
\save_init_bram_addr_ld[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2__0_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(2),
O => bram_addr_ld(2)
);
\save_init_bram_addr_ld[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => save_init_bram_addr_ld(4),
I1 => wrap_burst_total(0),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[4]_i_2__0_n_0\
);
\save_init_bram_addr_ld[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F808F8F8F808080"
)
port map (
I0 => save_init_bram_addr_ld(5),
I1 => \save_init_bram_addr_ld[5]_i_2__0_n_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I3 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
I4 => axi_awaddr_full,
I5 => s_axi_awaddr(3),
O => bram_addr_ld(3)
);
\save_init_bram_addr_ld[5]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => wrap_burst_total(0),
I1 => wrap_burst_total(2),
I2 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[5]_i_2__0_n_0\
);
\save_init_bram_addr_ld[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(4),
O => bram_addr_ld(4)
);
\save_init_bram_addr_ld[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(7),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(5),
O => bram_addr_ld(5)
);
\save_init_bram_addr_ld[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(8),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(6),
O => bram_addr_ld(6)
);
\save_init_bram_addr_ld[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(9),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(7),
O => bram_addr_ld(7)
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(8),
Q => save_init_bram_addr_ld(10),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(9),
Q => save_init_bram_addr_ld(11),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(10),
Q => save_init_bram_addr_ld(12),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(11),
Q => save_init_bram_addr_ld(13),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(12),
Q => save_init_bram_addr_ld(14),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(13),
Q => save_init_bram_addr_ld(15),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(1),
Q => save_init_bram_addr_ld(3),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(2),
Q => save_init_bram_addr_ld(4),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(3),
Q => save_init_bram_addr_ld(5),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(4),
Q => save_init_bram_addr_ld(6),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(5),
Q => save_init_bram_addr_ld(7),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(6),
Q => save_init_bram_addr_ld(8),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(7),
Q => save_init_bram_addr_ld(9),
R => s_axi_aresetn_0(0)
);
\wrap_burst_total[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000A22200000000"
)
port map (
I0 => \wrap_burst_total[0]_i_2__0_n_0\,
I1 => \wrap_burst_total[0]_i_3_n_0\,
I2 => Q(1),
I3 => Q(2),
I4 => \wrap_burst_total[2]_i_2__0_n_0\,
I5 => \wrap_burst_total[1]_i_2_n_0\,
O => \wrap_burst_total[0]_i_1__0_n_0\
);
\wrap_burst_total[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCA533A5FFA5FFA5"
)
port map (
I0 => s_axi_awlen(2),
I1 => Q(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => Q(1),
I5 => axi_awsize_pipe(0),
O => \wrap_burst_total[0]_i_2__0_n_0\
);
\wrap_burst_total[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_awaddr_full,
I1 => axi_awsize_pipe(0),
O => \wrap_burst_total[0]_i_3_n_0\
);
\wrap_burst_total[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"08000800F3000000"
)
port map (
I0 => \wrap_burst_total[2]_i_3__0_n_0\,
I1 => axi_awaddr_full,
I2 => axi_awsize_pipe(0),
I3 => \wrap_burst_total[1]_i_2_n_0\,
I4 => \wrap_burst_total[1]_i_3_n_0\,
I5 => \wrap_burst_total[2]_i_2__0_n_0\,
O => \wrap_burst_total[1]_i_1__0_n_0\
);
\wrap_burst_total[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(0),
O => \wrap_burst_total[1]_i_2_n_0\
);
\wrap_burst_total[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(1),
O => \wrap_burst_total[1]_i_3_n_0\
);
\wrap_burst_total[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A000000088008800"
)
port map (
I0 => \wrap_burst_total[2]_i_2__0_n_0\,
I1 => s_axi_awlen(0),
I2 => Q(0),
I3 => \wrap_burst_total[2]_i_3__0_n_0\,
I4 => axi_awsize_pipe(0),
I5 => axi_awaddr_full,
O => \wrap_burst_total[2]_i_1__0_n_0\
);
\wrap_burst_total[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(3),
O => \wrap_burst_total[2]_i_2__0_n_0\
);
\wrap_burst_total[2]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA000A0"
)
port map (
I0 => s_axi_awlen(2),
I1 => Q(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => Q(1),
O => \wrap_burst_total[2]_i_3__0_n_0\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1__0_n_0\,
Q => wrap_burst_total(0),
R => s_axi_aresetn_0(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1__0_n_0\,
Q => wrap_burst_total(1),
R => s_axi_aresetn_0(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1__0_n_0\,
Q => wrap_burst_total(2),
R => s_axi_aresetn_0(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_burst_total_reg[0]_0\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_1\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_2\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_3\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 1 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
bram_addr_ld_en : out STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : out STD_LOGIC;
\rd_data_sm_cs_reg[1]\ : out STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC;
axi_b2b_brst_reg : out STD_LOGIC;
\rd_data_sm_cs_reg[3]\ : out STD_LOGIC;
rd_adv_buf67_out : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_arsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_araddr_full : in STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
\rd_data_sm_cs_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_rd_burst_two_reg : in STD_LOGIC;
axi_rd_burst : in STD_LOGIC;
axi_aresetn_d2 : in STD_LOGIC;
rd_addr_sm_cs : in STD_LOGIC;
last_bram_addr : in STD_LOGIC;
ar_active : in STD_LOGIC;
pend_rd_op : in STD_LOGIC;
no_ar_ack : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
brst_zero : in STD_LOGIC;
axi_rvalid_int_reg : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
end_brst_rd : in STD_LOGIC;
axi_b2b_brst : in STD_LOGIC;
axi_arsize_pipe_max : in STD_LOGIC;
disable_b2b_brst : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_arlen_pipe_1_or_2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 : entity is "wrap_brst";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 is
signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[6]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axi_b2b_brst_reg\ : STD_LOGIC;
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^rd_adv_buf67_out\ : STD_LOGIC;
signal \^rd_data_sm_cs_reg[1]\ : STD_LOGIC;
signal \^rd_data_sm_cs_reg[3]\ : STD_LOGIC;
signal \save_init_bram_addr_ld[10]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[15]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[6]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[7]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[8]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[10]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[11]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[12]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[13]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[14]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[15]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[3]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[4]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[5]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[6]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[7]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[8]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_1\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_2\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_3\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[2]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[5]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_5\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3\ : label is "soft_lutpair3";
begin
D(13 downto 0) <= \^d\(13 downto 0);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[6]\;
SR(0) <= \^sr\(0);
axi_b2b_brst_reg <= \^axi_b2b_brst_reg\;
bram_addr_ld_en <= \^bram_addr_ld_en\;
rd_adv_buf67_out <= \^rd_adv_buf67_out\;
\rd_data_sm_cs_reg[1]\ <= \^rd_data_sm_cs_reg[1]\;
\rd_data_sm_cs_reg[3]\ <= \^rd_data_sm_cs_reg[3]\;
\save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\;
\wrap_burst_total_reg[0]_0\ <= \^wrap_burst_total_reg[0]_0\;
\wrap_burst_total_reg[0]_1\ <= \^wrap_burst_total_reg[0]_1\;
\wrap_burst_total_reg[0]_2\ <= \^wrap_burst_total_reg[0]_2\;
\wrap_burst_total_reg[0]_3\ <= \^wrap_burst_total_reg[0]_3\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"DF20FFFFDF200000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
O => \^d\(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"5D"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
I2 => curr_fixed_burst_reg,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
O => \^d\(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0E0F0F0E0E0FFF0"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\,
I2 => \^rd_data_sm_cs_reg[1]\,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I4 => \rd_data_sm_cs_reg[3]_0\(1),
I5 => \rd_data_sm_cs_reg[3]_0\(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg,
I1 => \rd_data_sm_cs_reg[3]_0\(0),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080800080"
)
port map (
I0 => \rd_data_sm_cs_reg[3]_0\(0),
I1 => axi_rvalid_int_reg,
I2 => s_axi_rready,
I3 => end_brst_rd,
I4 => axi_b2b_brst,
I5 => brst_zero,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[12]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(10),
O => \^d\(10)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[13]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(11),
O => \^d\(11)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[14]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(12),
O => \^d\(12)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
O => E(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[15]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(13),
O => \^d\(13)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A80000"
)
port map (
I0 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\,
I2 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I4 => curr_wrap_burst_reg,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00A000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I2 => \wrap_burst_total_reg_n_0_[1]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I4 => \wrap_burst_total_reg_n_0_[0]\,
I5 => \wrap_burst_total_reg_n_0_[2]\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000A808FD5D"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => s_axi_araddr(0),
I2 => axi_araddr_full,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
O => \^d\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6F60"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I3 => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
O => \^d\(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AFF6A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
O => \^d\(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAFFFF6AAA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
O => \^d\(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I3 => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
O => \^d\(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
O => \^d\(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A6AAFFFFA6AA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I2 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
O => \^d\(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
O => \^d\(7)
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_rvalid_int_reg,
I1 => s_axi_rready,
O => \^rd_adv_buf67_out\
);
axi_b2b_brst_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFDFFFF"
)
port map (
I0 => axi_arsize_pipe_max,
I1 => disable_b2b_brst,
I2 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\,
I3 => axi_arlen_pipe_1_or_2,
I4 => axi_araddr_full,
O => \^axi_b2b_brst_reg\
);
bram_en_int_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \rd_data_sm_cs_reg[3]_0\(3),
I1 => \rd_data_sm_cs_reg[3]_0\(2),
O => \^rd_data_sm_cs_reg[3]\
);
bram_en_int_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => end_brst_rd,
I1 => brst_zero,
I2 => \rd_data_sm_cs_reg[3]_0\(2),
I3 => \rd_data_sm_cs_reg[3]_0\(0),
I4 => axi_rvalid_int_reg,
I5 => s_axi_rready,
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\
);
bram_rst_b_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\rd_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F000E000F0000"
)
port map (
I0 => axi_rd_burst_two_reg,
I1 => axi_rd_burst,
I2 => \rd_data_sm_cs_reg[3]_0\(3),
I3 => \rd_data_sm_cs_reg[3]_0\(2),
I4 => \rd_data_sm_cs_reg[3]_0\(1),
I5 => \rd_data_sm_cs_reg[3]_0\(0),
O => \^rd_data_sm_cs_reg[1]\
);
\save_init_bram_addr_ld[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[10]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(8),
O => \save_init_bram_addr_ld[10]_i_1__0_n_0\
);
\save_init_bram_addr_ld[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[11]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(9),
O => \save_init_bram_addr_ld[11]_i_1__0_n_0\
);
\save_init_bram_addr_ld[15]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"02AA0202"
)
port map (
I0 => axi_aresetn_d2,
I1 => rd_addr_sm_cs,
I2 => \save_init_bram_addr_ld[15]_i_2__0_n_0\,
I3 => \^save_init_bram_addr_ld_reg[15]_0\,
I4 => last_bram_addr,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[15]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFEFEFF"
)
port map (
I0 => ar_active,
I1 => pend_rd_op,
I2 => no_ar_ack,
I3 => s_axi_arvalid,
I4 => axi_araddr_full,
O => \save_init_bram_addr_ld[15]_i_2__0_n_0\
);
\save_init_bram_addr_ld[15]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABAAABAFFFFAABA"
)
port map (
I0 => \^axi_b2b_brst_reg\,
I1 => \rd_data_sm_cs_reg[3]_0\(0),
I2 => \rd_data_sm_cs_reg[3]_0\(1),
I3 => \^rd_data_sm_cs_reg[3]\,
I4 => brst_zero,
I5 => \^rd_adv_buf67_out\,
O => \^save_init_bram_addr_ld_reg[15]_0\
);
\save_init_bram_addr_ld[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(1),
O => \save_init_bram_addr_ld[3]_i_1__0_n_0\
);
\save_init_bram_addr_ld[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A282"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[3]\,
I1 => \wrap_burst_total_reg_n_0_[1]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[0]\,
O => \save_init_bram_addr_ld[3]_i_2_n_0\
);
\save_init_bram_addr_ld[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(2),
O => \save_init_bram_addr_ld[4]_i_1__0_n_0\
);
\save_init_bram_addr_ld[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[4]\,
I1 => \wrap_burst_total_reg_n_0_[0]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[4]_i_2_n_0\
);
\save_init_bram_addr_ld[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F202F2F2F202020"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[5]\,
I1 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
I4 => axi_araddr_full,
I5 => s_axi_araddr(3),
O => \save_init_bram_addr_ld[5]_i_1__0_n_0\
);
\save_init_bram_addr_ld[5]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \wrap_burst_total_reg_n_0_[0]\,
I1 => \wrap_burst_total_reg_n_0_[2]\,
I2 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[5]_i_2_n_0\
);
\save_init_bram_addr_ld[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[6]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(4),
O => \save_init_bram_addr_ld[6]_i_1__0_n_0\
);
\save_init_bram_addr_ld[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[7]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(5),
O => \save_init_bram_addr_ld[7]_i_1__0_n_0\
);
\save_init_bram_addr_ld[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[8]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(6),
O => \save_init_bram_addr_ld[8]_i_1__0_n_0\
);
\save_init_bram_addr_ld[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[9]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(7),
O => \save_init_bram_addr_ld[9]_i_1__0_n_0\
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[10]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[11]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(10),
Q => \save_init_bram_addr_ld_reg_n_0_[12]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(11),
Q => \save_init_bram_addr_ld_reg_n_0_[13]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(12),
Q => \save_init_bram_addr_ld_reg_n_0_[14]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(13),
Q => \save_init_bram_addr_ld_reg_n_0_[15]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[3]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[4]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[5]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[6]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[7]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[8]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[9]\,
R => \^sr\(0)
);
\wrap_burst_total[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3202010100000000"
)
port map (
I0 => \^wrap_burst_total_reg[0]_0\,
I1 => \^wrap_burst_total_reg[0]_1\,
I2 => \wrap_burst_total[0]_i_3__0_n_0\,
I3 => Q(2),
I4 => \^wrap_burst_total_reg[0]_2\,
I5 => \^wrap_burst_total_reg[0]_3\,
O => \wrap_burst_total[0]_i_1_n_0\
);
\wrap_burst_total[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => axi_araddr_full,
I2 => s_axi_arlen(2),
O => \^wrap_burst_total_reg[0]_0\
);
\wrap_burst_total[0]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_araddr_full,
I1 => axi_arsize_pipe(0),
O => \wrap_burst_total[0]_i_3__0_n_0\
);
\wrap_burst_total[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
O => \^wrap_burst_total_reg[0]_2\
);
\wrap_burst_total[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_araddr_full,
I2 => s_axi_arlen(0),
O => \^wrap_burst_total_reg[0]_3\
);
\wrap_burst_total[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"220A880A000A880A"
)
port map (
I0 => \wrap_burst_total[2]_i_2_n_0\,
I1 => axi_arsize_pipe(0),
I2 => s_axi_arlen(3),
I3 => axi_araddr_full,
I4 => Q(3),
I5 => Q(2),
O => \wrap_burst_total[1]_i_1_n_0\
);
\wrap_burst_total[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8088008880000000"
)
port map (
I0 => \wrap_burst_total[2]_i_2_n_0\,
I1 => \^wrap_burst_total_reg[0]_1\,
I2 => axi_arsize_pipe(0),
I3 => axi_araddr_full,
I4 => Q(2),
I5 => s_axi_arlen(2),
O => \wrap_burst_total[2]_i_1_n_0\
);
\wrap_burst_total[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA000A0"
)
port map (
I0 => s_axi_arlen(1),
I1 => Q(1),
I2 => s_axi_arlen(0),
I3 => axi_araddr_full,
I4 => Q(0),
O => \wrap_burst_total[2]_i_2_n_0\
);
\wrap_burst_total[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_araddr_full,
I2 => s_axi_arlen(3),
O => \^wrap_burst_total_reg[0]_1\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[0]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[1]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[2]\,
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl is
port (
bram_rst_a : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_aclk : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
axi_aresetn_d2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
axi_aresetn_re_reg : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl is
signal \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \/i__n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_arready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_4_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp2_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[11]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp_full_i_1_n_0\ : STD_LOGIC;
signal I_WRAP_BRST_n_1 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_13 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_15 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_18 : STD_LOGIC;
signal I_WRAP_BRST_n_19 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_21 : STD_LOGIC;
signal I_WRAP_BRST_n_23 : STD_LOGIC;
signal I_WRAP_BRST_n_24 : STD_LOGIC;
signal I_WRAP_BRST_n_25 : STD_LOGIC;
signal I_WRAP_BRST_n_26 : STD_LOGIC;
signal I_WRAP_BRST_n_27 : STD_LOGIC;
signal I_WRAP_BRST_n_28 : STD_LOGIC;
signal I_WRAP_BRST_n_3 : STD_LOGIC;
signal I_WRAP_BRST_n_4 : STD_LOGIC;
signal I_WRAP_BRST_n_6 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal act_rd_burst : STD_LOGIC;
signal act_rd_burst_i_1_n_0 : STD_LOGIC;
signal act_rd_burst_i_3_n_0 : STD_LOGIC;
signal act_rd_burst_i_4_n_0 : STD_LOGIC;
signal act_rd_burst_set : STD_LOGIC;
signal act_rd_burst_two : STD_LOGIC;
signal act_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal ar_active : STD_LOGIC;
signal araddr_pipe_ld43_out : STD_LOGIC;
signal axi_araddr_full : STD_LOGIC;
signal axi_arburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_arid_pipe : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_arlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_arlen_pipe_1_or_2 : STD_LOGIC;
signal axi_arready_int : STD_LOGIC;
signal axi_arsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_arsize_pipe_max : STD_LOGIC;
signal axi_arsize_pipe_max_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst : STD_LOGIC;
signal axi_b2b_brst_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst_i_3_n_0 : STD_LOGIC;
signal axi_early_arready_int : STD_LOGIC;
signal axi_rd_burst : STD_LOGIC;
signal axi_rd_burst_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_i_2_n_0 : STD_LOGIC;
signal axi_rd_burst_i_3_n_0 : STD_LOGIC;
signal axi_rd_burst_two : STD_LOGIC;
signal axi_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_two_reg_n_0 : STD_LOGIC;
signal axi_rid_temp : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp2 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp20_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp2_full : STD_LOGIC;
signal axi_rid_temp_full : STD_LOGIC;
signal axi_rid_temp_full_d1 : STD_LOGIC;
signal axi_rlast_int_i_1_n_0 : STD_LOGIC;
signal axi_rlast_set : STD_LOGIC;
signal axi_rvalid_clr_ok : STD_LOGIC;
signal axi_rvalid_clr_ok_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_2_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_3_n_0 : STD_LOGIC;
signal axi_rvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_set : STD_LOGIC;
signal axi_rvalid_set_cmb : STD_LOGIC;
signal bram_addr_ld_en : STD_LOGIC;
signal bram_addr_ld_en_mod : STD_LOGIC;
signal \^bram_en_b\ : STD_LOGIC;
signal bram_en_int_i_10_n_0 : STD_LOGIC;
signal bram_en_int_i_11_n_0 : STD_LOGIC;
signal bram_en_int_i_1_n_0 : STD_LOGIC;
signal bram_en_int_i_2_n_0 : STD_LOGIC;
signal bram_en_int_i_3_n_0 : STD_LOGIC;
signal bram_en_int_i_4_n_0 : STD_LOGIC;
signal bram_en_int_i_6_n_0 : STD_LOGIC;
signal bram_en_int_i_7_n_0 : STD_LOGIC;
signal bram_en_int_i_9_n_0 : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
signal brst_cnt : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \brst_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal brst_cnt_max : STD_LOGIC;
signal brst_cnt_max_d1 : STD_LOGIC;
signal brst_one : STD_LOGIC;
signal brst_one0 : STD_LOGIC;
signal brst_one_i_1_n_0 : STD_LOGIC;
signal brst_zero : STD_LOGIC;
signal brst_zero_i_1_n_0 : STD_LOGIC;
signal brst_zero_i_2_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal disable_b2b_brst : STD_LOGIC;
signal disable_b2b_brst_cmb : STD_LOGIC;
signal disable_b2b_brst_i_2_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_3_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_4_n_0 : STD_LOGIC;
signal end_brst_rd : STD_LOGIC;
signal end_brst_rd_clr : STD_LOGIC;
signal end_brst_rd_clr_i_1_n_0 : STD_LOGIC;
signal end_brst_rd_i_1_n_0 : STD_LOGIC;
signal last_bram_addr : STD_LOGIC;
signal last_bram_addr0 : STD_LOGIC;
signal last_bram_addr_i_2_n_0 : STD_LOGIC;
signal last_bram_addr_i_3_n_0 : STD_LOGIC;
signal last_bram_addr_i_4_n_0 : STD_LOGIC;
signal last_bram_addr_i_5_n_0 : STD_LOGIC;
signal last_bram_addr_i_6_n_0 : STD_LOGIC;
signal last_bram_addr_i_7_n_0 : STD_LOGIC;
signal last_bram_addr_i_8_n_0 : STD_LOGIC;
signal last_bram_addr_i_9_n_0 : STD_LOGIC;
signal no_ar_ack : STD_LOGIC;
signal no_ar_ack_i_1_n_0 : STD_LOGIC;
signal p_0_in13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_26_out : STD_LOGIC;
signal p_48_out : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pend_rd_op : STD_LOGIC;
signal pend_rd_op_i_1_n_0 : STD_LOGIC;
signal pend_rd_op_i_2_n_0 : STD_LOGIC;
signal pend_rd_op_i_3_n_0 : STD_LOGIC;
signal pend_rd_op_i_4_n_0 : STD_LOGIC;
signal pend_rd_op_i_5_n_0 : STD_LOGIC;
signal pend_rd_op_i_6_n_0 : STD_LOGIC;
signal pend_rd_op_i_7_n_0 : STD_LOGIC;
signal pend_rd_op_i_8_n_0 : STD_LOGIC;
signal pend_rd_op_i_9_n_0 : STD_LOGIC;
signal rd_addr_sm_cs : STD_LOGIC;
signal rd_adv_buf67_out : STD_LOGIC;
signal rd_data_sm_cs : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \rd_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_6_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_7_n_0\ : STD_LOGIC;
signal rd_data_sm_ns : STD_LOGIC;
signal rd_skid_buf : STD_LOGIC_VECTOR ( 31 downto 0 );
signal rd_skid_buf_ld : STD_LOGIC;
signal rd_skid_buf_ld_cmb : STD_LOGIC;
signal rd_skid_buf_ld_reg : STD_LOGIC;
signal rddata_mux_sel : STD_LOGIC;
signal rddata_mux_sel_cmb : STD_LOGIC;
signal rddata_mux_sel_i_1_n_0 : STD_LOGIC;
signal rddata_mux_sel_i_3_n_0 : STD_LOGIC;
signal rlast_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of rlast_sm_cs : signal is "yes";
signal \^s_axi_rlast\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_arready_int_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_early_arready_int_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[0]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[10]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[11]_i_2\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[2]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[4]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[5]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[7]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[8]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[9]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of act_rd_burst_i_4 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_2 : label is "soft_lutpair11";
attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_3 : label is "soft_lutpair19";
attribute SOFT_HLUTNM of axi_rvalid_set_i_1 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \brst_cnt[4]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_2\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_3\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_4\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of brst_zero_i_1 : label is "soft_lutpair15";
attribute SOFT_HLUTNM of brst_zero_i_2 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_1 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_1 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of disable_b2b_brst_i_2 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of last_bram_addr_i_4 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of last_bram_addr_i_5 : label is "soft_lutpair23";
attribute SOFT_HLUTNM of last_bram_addr_i_7 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of last_bram_addr_i_9 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of pend_rd_op_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of pend_rd_op_i_6 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of pend_rd_op_i_7 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of pend_rd_op_i_8 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of pend_rd_op_i_9 : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \rd_data_sm_cs[0]_i_3\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_4\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_5\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_3\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_4\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_6\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of rddata_mux_sel_i_1 : label is "soft_lutpair13";
begin
Q(13 downto 0) <= \^q\(13 downto 0);
bram_en_b <= \^bram_en_b\;
bram_rst_a <= \^bram_rst_a\;
s_axi_rlast <= \^s_axi_rlast\;
s_axi_rvalid <= \^s_axi_rvalid\;
\/FSM_sequential_rlast_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0011001300130013"
)
port map (
I0 => axi_rd_burst,
I1 => rlast_sm_cs(1),
I2 => act_rd_burst_two,
I3 => axi_rd_burst_two_reg_n_0,
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\
);
\/FSM_sequential_rlast_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"003F007F003F0055"
)
port map (
I0 => axi_rd_burst,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => rlast_sm_cs(1),
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_two,
O => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\
);
\/i_\: unisim.vcomponents.LUT6
generic map(
INIT => X"F000F111F000E000"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(1),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => rlast_sm_cs(0),
I5 => last_bram_addr,
O => \/i__n_0\
);
\/i___0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00008080000F8080"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(1),
I4 => rlast_sm_cs(2),
I5 => \^s_axi_rlast\,
O => axi_rlast_set
);
\FSM_sequential_rlast_sm_cs[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(0),
O => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(1),
O => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A4FFFF00A40000"
)
port map (
I0 => rlast_sm_cs(1),
I1 => p_0_in13_in,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(2),
I4 => \/i__n_0\,
I5 => rlast_sm_cs(2),
O => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst,
O => p_0_in13_in
);
\FSM_sequential_rlast_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\,
Q => rlast_sm_cs(0),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\,
Q => rlast_sm_cs(1),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\,
Q => rlast_sm_cs(2),
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_arready_int_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAEEE"
)
port map (
I0 => p_9_out,
I1 => axi_arready_int,
I2 => s_axi_arvalid,
I3 => axi_araddr_full,
I4 => araddr_pipe_ld43_out,
O => \GEN_ARREADY.axi_arready_int_i_1_n_0\
);
\GEN_ARREADY.axi_arready_int_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BAAA"
)
port map (
I0 => axi_aresetn_re_reg,
I1 => axi_early_arready_int,
I2 => axi_araddr_full,
I3 => bram_addr_ld_en,
O => p_9_out
);
\GEN_ARREADY.axi_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_ARREADY.axi_arready_int_i_1_n_0\,
Q => axi_arready_int,
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_early_arready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000200"
)
port map (
I0 => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\,
I1 => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\,
I2 => rd_data_sm_cs(3),
I3 => brst_one,
I4 => axi_arready_int,
I5 => I_WRAP_BRST_n_26,
O => p_48_out
);
\GEN_ARREADY.axi_early_arready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CC304400000044"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\
);
\GEN_ARREADY.axi_early_arready_int_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => axi_araddr_full,
I1 => s_axi_arvalid,
O => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\
);
\GEN_ARREADY.axi_early_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_48_out,
Q => axi_early_arready_int,
R => \^bram_rst_a\
);
\GEN_AR_DUAL.ar_active_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CDCDCDDDCCCCCCCC"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_2_n_0\,
I1 => bram_addr_ld_en,
I2 => \GEN_AR_DUAL.ar_active_i_3_n_0\,
I3 => end_brst_rd,
I4 => brst_zero,
I5 => ar_active,
O => \GEN_AR_DUAL.ar_active_i_1_n_0\
);
\GEN_AR_DUAL.ar_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"808880808088A280"
)
port map (
I0 => pend_rd_op_i_6_n_0,
I1 => rd_data_sm_cs(1),
I2 => \GEN_AR_DUAL.ar_active_i_4_n_0\,
I3 => rd_data_sm_cs(0),
I4 => axi_rd_burst_two_reg_n_0,
I5 => axi_rd_burst,
O => \GEN_AR_DUAL.ar_active_i_2_n_0\
);
\GEN_AR_DUAL.ar_active_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \GEN_AR_DUAL.ar_active_i_3_n_0\
);
\GEN_AR_DUAL.ar_active_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A88000000000000"
)
port map (
I0 => I_WRAP_BRST_n_27,
I1 => brst_zero,
I2 => axi_b2b_brst,
I3 => end_brst_rd,
I4 => rd_adv_buf67_out,
I5 => rd_data_sm_cs(0),
O => \GEN_AR_DUAL.ar_active_i_4_n_0\
);
\GEN_AR_DUAL.ar_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.ar_active_i_1_n_0\,
Q => ar_active,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_DUAL.rd_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"10001000F0F01000"
)
port map (
I0 => rd_addr_sm_cs,
I1 => axi_araddr_full,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I4 => last_bram_addr,
I5 => I_WRAP_BRST_n_26,
O => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\
);
\GEN_AR_DUAL.rd_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\,
Q => rd_addr_sm_cs,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(8),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(9),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(10),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(11),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(12),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(13),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(0),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(1),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(2),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(3),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(4),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(5),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(6),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(7),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C08888CCCC8888"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => s_axi_aresetn,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I4 => axi_araddr_full,
I5 => bram_addr_ld_en,
O => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\,
Q => axi_araddr_full,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"03AA"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
I1 => s_axi_arburst(0),
I2 => s_axi_arburst(1),
I3 => araddr_pipe_ld43_out,
O => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(0),
Q => axi_arburst_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(1),
Q => axi_arburst_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(0),
Q => axi_arid_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(10),
Q => axi_arid_pipe(10),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(11),
Q => axi_arid_pipe(11),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(1),
Q => axi_arid_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(2),
Q => axi_arid_pipe(2),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(3),
Q => axi_arid_pipe(3),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(4),
Q => axi_arid_pipe(4),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(5),
Q => axi_arid_pipe(5),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(6),
Q => axi_arid_pipe(6),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(7),
Q => axi_arid_pipe(7),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(8),
Q => axi_arid_pipe(8),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(9),
Q => axi_arid_pipe(9),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"220022002A002200"
)
port map (
I0 => axi_aresetn_d2,
I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I2 => rd_addr_sm_cs,
I3 => s_axi_arvalid,
I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I5 => axi_araddr_full,
O => araddr_pipe_ld43_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => I_WRAP_BRST_n_26,
I1 => last_bram_addr,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => no_ar_ack,
I1 => pend_rd_op,
I2 => ar_active,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_arlen(7),
I1 => s_axi_arlen(1),
I2 => s_axi_arlen(3),
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\,
O => p_13_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_axi_arlen(5),
I1 => s_axi_arlen(4),
I2 => s_axi_arlen(2),
I3 => s_axi_arlen(6),
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => p_13_out,
Q => axi_arlen_pipe_1_or_2,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(0),
Q => axi_arlen_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(1),
Q => axi_arlen_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(2),
Q => axi_arlen_pipe(2),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(3),
Q => axi_arlen_pipe(3),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(4),
Q => axi_arlen_pipe(4),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(5),
Q => axi_arlen_pipe(5),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(6),
Q => axi_arlen_pipe(6),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(7),
Q => axi_arlen_pipe(7),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => '1',
Q => axi_arsize_pipe(1),
R => '0'
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BAAA0000"
)
port map (
I0 => brst_cnt_max,
I1 => pend_rd_op,
I2 => ar_active,
I3 => brst_zero,
I4 => s_axi_aresetn,
I5 => bram_addr_ld_en,
O => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\,
Q => brst_cnt_max,
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(4),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(3),
I5 => \^q\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => I_WRAP_BRST_n_23,
I3 => \^q\(5),
I4 => \^q\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_13,
Q => \^q\(8),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_12,
Q => \^q\(9),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_11,
Q => \^q\(10),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_10,
Q => \^q\(11),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_9,
Q => \^q\(12),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_8,
Q => \^q\(13),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_21,
Q => \^q\(0),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_20,
Q => \^q\(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_19,
Q => \^q\(2),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_18,
Q => \^q\(3),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_17,
Q => \^q\(4),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_16,
Q => \^q\(5),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_15,
Q => \^q\(6),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_14,
Q => \^q\(7),
R => '0'
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(0),
I1 => bram_rddata_b(0),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\,
Q => s_axi_rdata(0),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(10),
I1 => bram_rddata_b(10),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\,
Q => s_axi_rdata(10),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(11),
I1 => bram_rddata_b(11),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\,
Q => s_axi_rdata(11),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(12),
I1 => bram_rddata_b(12),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\,
Q => s_axi_rdata(12),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(13),
I1 => bram_rddata_b(13),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\,
Q => s_axi_rdata(13),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(14),
I1 => bram_rddata_b(14),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\,
Q => s_axi_rdata(14),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(15),
I1 => bram_rddata_b(15),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\,
Q => s_axi_rdata(15),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(16),
I1 => bram_rddata_b(16),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\,
Q => s_axi_rdata(16),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(17),
I1 => bram_rddata_b(17),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\,
Q => s_axi_rdata(17),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(18),
I1 => bram_rddata_b(18),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\,
Q => s_axi_rdata(18),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(19),
I1 => bram_rddata_b(19),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\,
Q => s_axi_rdata(19),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(1),
I1 => bram_rddata_b(1),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\,
Q => s_axi_rdata(1),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(20),
I1 => bram_rddata_b(20),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\,
Q => s_axi_rdata(20),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(21),
I1 => bram_rddata_b(21),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\,
Q => s_axi_rdata(21),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(22),
I1 => bram_rddata_b(22),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\,
Q => s_axi_rdata(22),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(23),
I1 => bram_rddata_b(23),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\,
Q => s_axi_rdata(23),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(24),
I1 => bram_rddata_b(24),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\,
Q => s_axi_rdata(24),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(25),
I1 => bram_rddata_b(25),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\,
Q => s_axi_rdata(25),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(26),
I1 => bram_rddata_b(26),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\,
Q => s_axi_rdata(26),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(27),
I1 => bram_rddata_b(27),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\,
Q => s_axi_rdata(27),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(28),
I1 => bram_rddata_b(28),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\,
Q => s_axi_rdata(28),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(29),
I1 => bram_rddata_b(29),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\,
Q => s_axi_rdata(29),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(2),
I1 => bram_rddata_b(2),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\,
Q => s_axi_rdata(2),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(30),
I1 => bram_rddata_b(30),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\,
Q => s_axi_rdata(30),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1414545410000404"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\,
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(31),
I1 => bram_rddata_b(31),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
Q => s_axi_rdata(31),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(3),
I1 => bram_rddata_b(3),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\,
Q => s_axi_rdata(3),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(4),
I1 => bram_rddata_b(4),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\,
Q => s_axi_rdata(4),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(5),
I1 => bram_rddata_b(5),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\,
Q => s_axi_rdata(5),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(6),
I1 => bram_rddata_b(6),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\,
Q => s_axi_rdata(6),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(7),
I1 => bram_rddata_b(7),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\,
Q => s_axi_rdata(7),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(8),
I1 => bram_rddata_b(8),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\,
Q => s_axi_rdata(8),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(9),
I1 => bram_rddata_b(9),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\,
Q => s_axi_rdata(9),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAEAA"
)
port map (
I0 => rd_skid_buf_ld_reg,
I1 => rd_adv_buf67_out,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(3),
O => rd_skid_buf_ld
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(0),
Q => rd_skid_buf(0),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(10),
Q => rd_skid_buf(10),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(11),
Q => rd_skid_buf(11),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(12),
Q => rd_skid_buf(12),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(13),
Q => rd_skid_buf(13),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(14),
Q => rd_skid_buf(14),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(15),
Q => rd_skid_buf(15),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(16),
Q => rd_skid_buf(16),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(17),
Q => rd_skid_buf(17),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(18),
Q => rd_skid_buf(18),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(19),
Q => rd_skid_buf(19),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(1),
Q => rd_skid_buf(1),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(20),
Q => rd_skid_buf(20),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(21),
Q => rd_skid_buf(21),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(22),
Q => rd_skid_buf(22),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(23),
Q => rd_skid_buf(23),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(24),
Q => rd_skid_buf(24),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(25),
Q => rd_skid_buf(25),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(26),
Q => rd_skid_buf(26),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(27),
Q => rd_skid_buf(27),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(28),
Q => rd_skid_buf(28),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(29),
Q => rd_skid_buf(29),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(2),
Q => rd_skid_buf(2),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(30),
Q => rd_skid_buf(30),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(31),
Q => rd_skid_buf(31),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(3),
Q => rd_skid_buf(3),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(4),
Q => rd_skid_buf(4),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(5),
Q => rd_skid_buf(5),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(6),
Q => rd_skid_buf(6),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(7),
Q => rd_skid_buf(7),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(8),
Q => rd_skid_buf(8),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(9),
Q => rd_skid_buf(9),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_int[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"08FF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rlast\,
I2 => axi_b2b_brst,
I3 => s_axi_aresetn,
O => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_rvalid_set,
I1 => s_axi_rready,
I2 => \^s_axi_rlast\,
I3 => axi_b2b_brst,
O => p_4_out
);
\GEN_RID.axi_rid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(0),
Q => s_axi_rid(0),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(10),
Q => s_axi_rid(10),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(11),
Q => s_axi_rid(11),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(1),
Q => s_axi_rid(1),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(2),
Q => s_axi_rid(2),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(3),
Q => s_axi_rid(3),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(4),
Q => s_axi_rid(4),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(5),
Q => s_axi_rid(5),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(6),
Q => s_axi_rid(6),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(7),
Q => s_axi_rid(7),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(8),
Q => s_axi_rid(8),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(9),
Q => s_axi_rid(9),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_temp2[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(0),
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
O => axi_rid_temp20_in(0)
);
\GEN_RID.axi_rid_temp2[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(10),
I1 => axi_araddr_full,
I2 => s_axi_arid(10),
O => axi_rid_temp20_in(10)
);
\GEN_RID.axi_rid_temp2[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_rid_temp_full,
I1 => bram_addr_ld_en,
O => p_26_out
);
\GEN_RID.axi_rid_temp2[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(11),
I1 => axi_araddr_full,
I2 => s_axi_arid(11),
O => axi_rid_temp20_in(11)
);
\GEN_RID.axi_rid_temp2[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arid(1),
O => axi_rid_temp20_in(1)
);
\GEN_RID.axi_rid_temp2[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(2),
I1 => axi_araddr_full,
I2 => s_axi_arid(2),
O => axi_rid_temp20_in(2)
);
\GEN_RID.axi_rid_temp2[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(3),
I1 => axi_araddr_full,
I2 => s_axi_arid(3),
O => axi_rid_temp20_in(3)
);
\GEN_RID.axi_rid_temp2[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arid(4),
O => axi_rid_temp20_in(4)
);
\GEN_RID.axi_rid_temp2[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arid(5),
O => axi_rid_temp20_in(5)
);
\GEN_RID.axi_rid_temp2[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arid(6),
O => axi_rid_temp20_in(6)
);
\GEN_RID.axi_rid_temp2[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arid(7),
O => axi_rid_temp20_in(7)
);
\GEN_RID.axi_rid_temp2[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(8),
I1 => axi_araddr_full,
I2 => s_axi_arid(8),
O => axi_rid_temp20_in(8)
);
\GEN_RID.axi_rid_temp2[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(9),
I1 => axi_araddr_full,
I2 => s_axi_arid(9),
O => axi_rid_temp20_in(9)
);
\GEN_RID.axi_rid_temp2_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080000C8C800C0"
)
port map (
I0 => bram_addr_ld_en,
I1 => s_axi_aresetn,
I2 => axi_rid_temp2_full,
I3 => axi_rid_temp_full_d1,
I4 => axi_rid_temp_full,
I5 => p_4_out,
O => \GEN_RID.axi_rid_temp2_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp2_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp2_full_i_1_n_0\,
Q => axi_rid_temp2_full,
R => '0'
);
\GEN_RID.axi_rid_temp2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(0),
Q => axi_rid_temp2(0),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(10),
Q => axi_rid_temp2(10),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(11),
Q => axi_rid_temp2(11),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(1),
Q => axi_rid_temp2(1),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(2),
Q => axi_rid_temp2(2),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(3),
Q => axi_rid_temp2(3),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(4),
Q => axi_rid_temp2(4),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(5),
Q => axi_rid_temp2(5),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(6),
Q => axi_rid_temp2(6),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(7),
Q => axi_rid_temp2(7),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(8),
Q => axi_rid_temp2(8),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(9),
Q => axi_rid_temp2(9),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(0),
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(0),
O => \GEN_RID.axi_rid_temp[0]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(10),
I1 => axi_araddr_full,
I2 => s_axi_arid(10),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(10),
O => \GEN_RID.axi_rid_temp[10]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A0FFA0E0"
)
port map (
I0 => p_4_out,
I1 => axi_rid_temp_full_d1,
I2 => axi_rid_temp2_full,
I3 => axi_rid_temp_full,
I4 => bram_addr_ld_en,
O => \GEN_RID.axi_rid_temp[11]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(11),
I1 => axi_araddr_full,
I2 => s_axi_arid(11),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(11),
O => \GEN_RID.axi_rid_temp[11]_i_2_n_0\
);
\GEN_RID.axi_rid_temp[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arid(1),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(1),
O => \GEN_RID.axi_rid_temp[1]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(2),
I1 => axi_araddr_full,
I2 => s_axi_arid(2),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(2),
O => \GEN_RID.axi_rid_temp[2]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(3),
I1 => axi_araddr_full,
I2 => s_axi_arid(3),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(3),
O => \GEN_RID.axi_rid_temp[3]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arid(4),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(4),
O => \GEN_RID.axi_rid_temp[4]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arid(5),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(5),
O => \GEN_RID.axi_rid_temp[5]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arid(6),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(6),
O => \GEN_RID.axi_rid_temp[6]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arid(7),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(7),
O => \GEN_RID.axi_rid_temp[7]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(8),
I1 => axi_araddr_full,
I2 => s_axi_arid(8),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(8),
O => \GEN_RID.axi_rid_temp[8]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(9),
I1 => axi_araddr_full,
I2 => s_axi_arid(9),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(9),
O => \GEN_RID.axi_rid_temp[9]_i_1_n_0\
);
\GEN_RID.axi_rid_temp_full_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rid_temp_full,
Q => axi_rid_temp_full_d1,
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0E000F0A0A0"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_rid_temp_full_d1,
I2 => s_axi_aresetn,
I3 => p_4_out,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2_full,
O => \GEN_RID.axi_rid_temp_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp_full_i_1_n_0\,
Q => axi_rid_temp_full,
R => '0'
);
\GEN_RID.axi_rid_temp_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[0]_i_1_n_0\,
Q => axi_rid_temp(0),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[10]_i_1_n_0\,
Q => axi_rid_temp(10),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[11]_i_2_n_0\,
Q => axi_rid_temp(11),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[1]_i_1_n_0\,
Q => axi_rid_temp(1),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[2]_i_1_n_0\,
Q => axi_rid_temp(2),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[3]_i_1_n_0\,
Q => axi_rid_temp(3),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[4]_i_1_n_0\,
Q => axi_rid_temp(4),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[5]_i_1_n_0\,
Q => axi_rid_temp(5),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[6]_i_1_n_0\,
Q => axi_rid_temp(6),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[7]_i_1_n_0\,
Q => axi_rid_temp(7),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[8]_i_1_n_0\,
Q => axi_rid_temp(8),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[9]_i_1_n_0\,
Q => axi_rid_temp(9),
R => \^bram_rst_a\
);
I_WRAP_BRST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0
port map (
D(13) => I_WRAP_BRST_n_8,
D(12) => I_WRAP_BRST_n_9,
D(11) => I_WRAP_BRST_n_10,
D(10) => I_WRAP_BRST_n_11,
D(9) => I_WRAP_BRST_n_12,
D(8) => I_WRAP_BRST_n_13,
D(7) => I_WRAP_BRST_n_14,
D(6) => I_WRAP_BRST_n_15,
D(5) => I_WRAP_BRST_n_16,
D(4) => I_WRAP_BRST_n_17,
D(3) => I_WRAP_BRST_n_18,
D(2) => I_WRAP_BRST_n_19,
D(1) => I_WRAP_BRST_n_20,
D(0) => I_WRAP_BRST_n_21,
E(1) => bram_addr_ld_en_mod,
E(0) => I_WRAP_BRST_n_6,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ => I_WRAP_BRST_n_7,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ => I_WRAP_BRST_n_25,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9 downto 0) => \^q\(9 downto 0),
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => I_WRAP_BRST_n_23,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\,
Q(3 downto 0) => axi_arlen_pipe(3 downto 0),
SR(0) => \^bram_rst_a\,
ar_active => ar_active,
axi_araddr_full => axi_araddr_full,
axi_aresetn_d2 => axi_aresetn_d2,
axi_arlen_pipe_1_or_2 => axi_arlen_pipe_1_or_2,
axi_arsize_pipe(0) => axi_arsize_pipe(1),
axi_arsize_pipe_max => axi_arsize_pipe_max,
axi_b2b_brst => axi_b2b_brst,
axi_b2b_brst_reg => I_WRAP_BRST_n_27,
axi_rd_burst => axi_rd_burst,
axi_rd_burst_two_reg => axi_rd_burst_two_reg_n_0,
axi_rvalid_int_reg => \^s_axi_rvalid\,
bram_addr_ld_en => bram_addr_ld_en,
brst_zero => brst_zero,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_wrap_burst_reg => curr_wrap_burst_reg,
disable_b2b_brst => disable_b2b_brst,
end_brst_rd => end_brst_rd,
last_bram_addr => last_bram_addr,
no_ar_ack => no_ar_ack,
pend_rd_op => pend_rd_op,
rd_addr_sm_cs => rd_addr_sm_cs,
rd_adv_buf67_out => rd_adv_buf67_out,
\rd_data_sm_cs_reg[1]\ => I_WRAP_BRST_n_24,
\rd_data_sm_cs_reg[3]\ => I_WRAP_BRST_n_28,
\rd_data_sm_cs_reg[3]_0\(3 downto 0) => rd_data_sm_cs(3 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_rready => s_axi_rready,
\save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_26,
\wrap_burst_total_reg[0]_0\ => I_WRAP_BRST_n_1,
\wrap_burst_total_reg[0]_1\ => I_WRAP_BRST_n_2,
\wrap_burst_total_reg[0]_2\ => I_WRAP_BRST_n_3,
\wrap_burst_total_reg[0]_3\ => I_WRAP_BRST_n_4
);
act_rd_burst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002EEE22E2"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_set,
I2 => bram_addr_ld_en,
I3 => axi_rd_burst_two,
I4 => axi_rd_burst,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_i_1_n_0
);
act_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8AAA8A8A8A8A8"
)
port map (
I0 => pend_rd_op_i_6_n_0,
I1 => act_rd_burst_i_4_n_0,
I2 => axi_b2b_brst_i_3_n_0,
I3 => \rd_data_sm_cs[2]_i_4_n_0\,
I4 => last_bram_addr_i_7_n_0,
I5 => bram_addr_ld_en,
O => act_rd_burst_set
);
act_rd_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"04000010FFFFFFFF"
)
port map (
I0 => \rd_data_sm_cs[3]_i_6_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => s_axi_aresetn,
O => act_rd_burst_i_3_n_0
);
act_rd_burst_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"4440"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
I2 => axi_rd_burst,
I3 => axi_rd_burst_two_reg_n_0,
O => act_rd_burst_i_4_n_0
);
act_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_i_1_n_0,
Q => act_rd_burst,
R => '0'
);
act_rd_burst_two_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2EEE222"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst_set,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_two_i_1_n_0
);
act_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_two_i_1_n_0,
Q => act_rd_burst_two,
R => '0'
);
axi_arsize_pipe_max_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => axi_arsize_pipe_max,
O => axi_arsize_pipe_max_i_1_n_0
);
axi_arsize_pipe_max_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_arsize_pipe_max_i_1_n_0,
Q => axi_arsize_pipe_max,
R => \^bram_rst_a\
);
axi_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CC0CCC55CC0CCCCC"
)
port map (
I0 => I_WRAP_BRST_n_27,
I1 => axi_b2b_brst,
I2 => disable_b2b_brst_i_2_n_0,
I3 => rd_data_sm_cs(3),
I4 => rd_data_sm_cs(2),
I5 => axi_b2b_brst_i_3_n_0,
O => axi_b2b_brst_i_1_n_0
);
axi_b2b_brst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000088880080"
)
port map (
I0 => \rd_data_sm_cs[0]_i_3_n_0\,
I1 => rd_adv_buf67_out,
I2 => end_brst_rd,
I3 => axi_b2b_brst,
I4 => brst_zero,
I5 => I_WRAP_BRST_n_27,
O => axi_b2b_brst_i_3_n_0
);
axi_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_b2b_brst_i_1_n_0,
Q => axi_b2b_brst,
R => \^bram_rst_a\
);
axi_rd_burst_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"303000A0"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_i_2_n_0,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_i_1_n_0
);
axi_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \brst_cnt[6]_i_2_n_0\,
I1 => axi_rd_burst_i_3_n_0,
I2 => I_WRAP_BRST_n_3,
I3 => \brst_cnt[7]_i_3_n_0\,
I4 => I_WRAP_BRST_n_2,
I5 => I_WRAP_BRST_n_1,
O => axi_rd_burst_i_2_n_0
);
axi_rd_burst_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arlen(5),
I1 => axi_arlen_pipe(5),
I2 => s_axi_arlen(4),
I3 => axi_araddr_full,
I4 => axi_arlen_pipe(4),
O => axi_rd_burst_i_3_n_0
);
axi_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_i_1_n_0,
Q => axi_rd_burst,
R => '0'
);
axi_rd_burst_two_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"C0C000A0"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst_two,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_two_i_1_n_0
);
axi_rd_burst_two_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"A808"
)
port map (
I0 => axi_rd_burst_i_2_n_0,
I1 => s_axi_arlen(0),
I2 => axi_araddr_full,
I3 => axi_arlen_pipe(0),
O => axi_rd_burst_two
);
axi_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_two_i_1_n_0,
Q => axi_rd_burst_two_reg_n_0,
R => '0'
);
axi_rlast_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"88A8"
)
port map (
I0 => s_axi_aresetn,
I1 => axi_rlast_set,
I2 => \^s_axi_rlast\,
I3 => s_axi_rready,
O => axi_rlast_int_i_1_n_0
);
axi_rlast_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rlast_int_i_1_n_0,
Q => \^s_axi_rlast\,
R => '0'
);
axi_rvalid_clr_ok_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFEEEA"
)
port map (
I0 => axi_rvalid_clr_ok,
I1 => last_bram_addr,
I2 => disable_b2b_brst,
I3 => disable_b2b_brst_cmb,
I4 => axi_rvalid_clr_ok_i_2_n_0,
I5 => axi_rvalid_clr_ok_i_3_n_0,
O => axi_rvalid_clr_ok_i_1_n_0
);
axi_rvalid_clr_ok_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAABAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
O => axi_rvalid_clr_ok_i_2_n_0
);
axi_rvalid_clr_ok_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => I_WRAP_BRST_n_26,
I1 => bram_addr_ld_en,
I2 => s_axi_aresetn,
O => axi_rvalid_clr_ok_i_3_n_0
);
axi_rvalid_clr_ok_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_clr_ok_i_1_n_0,
Q => axi_rvalid_clr_ok,
R => '0'
);
axi_rvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00E0E0E0E0E0E0E0"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => axi_rvalid_set,
I2 => s_axi_aresetn,
I3 => axi_rvalid_clr_ok,
I4 => \^s_axi_rlast\,
I5 => s_axi_rready,
O => axi_rvalid_int_i_1_n_0
);
axi_rvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_int_i_1_n_0,
Q => \^s_axi_rvalid\,
R => '0'
);
axi_rvalid_set_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
O => axi_rvalid_set_cmb
);
axi_rvalid_set_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_set_cmb,
Q => axi_rvalid_set,
R => \^bram_rst_a\
);
bram_en_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEFFFEEEEE000E"
)
port map (
I0 => bram_en_int_i_2_n_0,
I1 => bram_en_int_i_3_n_0,
I2 => bram_en_int_i_4_n_0,
I3 => I_WRAP_BRST_n_28,
I4 => bram_en_int_i_6_n_0,
I5 => \^bram_en_b\,
O => bram_en_int_i_1_n_0
);
bram_en_int_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF777FFFFFFFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => act_rd_burst,
I3 => act_rd_burst_two,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_10_n_0
);
bram_en_int_i_11: unisim.vcomponents.LUT6
generic map(
INIT => X"D0D000F0D0D0F0F0"
)
port map (
I0 => \rd_data_sm_cs[3]_i_7_n_0\,
I1 => I_WRAP_BRST_n_27,
I2 => rd_data_sm_cs(1),
I3 => brst_one,
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[2]_i_5_n_0\,
O => bram_en_int_i_11_n_0
);
bram_en_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FDF50000"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => pend_rd_op,
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(1),
I5 => bram_en_int_i_7_n_0,
O => bram_en_int_i_2_n_0
);
bram_en_int_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAEEAFAAAAAAEE"
)
port map (
I0 => I_WRAP_BRST_n_25,
I1 => bram_addr_ld_en,
I2 => p_0_in13_in,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_3_n_0
);
bram_en_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"000F007F0000007F"
)
port map (
I0 => pend_rd_op,
I1 => rd_adv_buf67_out,
I2 => \rd_data_sm_cs[0]_i_3_n_0\,
I3 => bram_en_int_i_9_n_0,
I4 => bram_addr_ld_en,
I5 => bram_en_int_i_10_n_0,
O => bram_en_int_i_4_n_0
);
bram_en_int_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"1010111111111110"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => bram_en_int_i_11_n_0,
I3 => bram_addr_ld_en,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_6_n_0
);
bram_en_int_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"5500050544444444"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => axi_rd_burst_two_reg_n_0,
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => \rd_data_sm_cs[3]_i_7_n_0\,
I4 => rd_adv_buf67_out,
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_7_n_0
);
bram_en_int_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111111111000"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => brst_zero,
I5 => end_brst_rd,
O => bram_en_int_i_9_n_0
);
bram_en_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_int_i_1_n_0,
Q => \^bram_en_b\,
R => \^bram_rst_a\
);
\brst_cnt[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D1DDD111"
)
port map (
I0 => brst_cnt(0),
I1 => bram_addr_ld_en,
I2 => axi_arlen_pipe(0),
I3 => axi_araddr_full,
I4 => s_axi_arlen(0),
O => \brst_cnt[0]_i_1_n_0\
);
\brst_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB800B800B8FF"
)
port map (
I0 => axi_arlen_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
I3 => bram_addr_ld_en,
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[1]_i_1_n_0\
);
\brst_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_1,
I1 => bram_addr_ld_en,
I2 => brst_cnt(2),
I3 => brst_cnt(1),
I4 => brst_cnt(0),
O => \brst_cnt[2]_i_1_n_0\
);
\brst_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_2,
I1 => bram_addr_ld_en,
I2 => brst_cnt(3),
I3 => brst_cnt(2),
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[3]_i_1_n_0\
);
\brst_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => axi_arlen_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arlen(4),
I3 => bram_addr_ld_en,
I4 => brst_cnt(4),
I5 => \brst_cnt[4]_i_2_n_0\,
O => \brst_cnt[4]_i_1_n_0\
);
\brst_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => brst_cnt(2),
I1 => brst_cnt(0),
I2 => brst_cnt(1),
I3 => brst_cnt(3),
O => \brst_cnt[4]_i_2_n_0\
);
\brst_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => axi_arlen_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arlen(5),
I3 => bram_addr_ld_en,
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[5]_i_1_n_0\
);
\brst_cnt[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => \brst_cnt[6]_i_2_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(6),
I3 => brst_cnt(5),
I4 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[6]_i_1_n_0\
);
\brst_cnt[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arlen(6),
O => \brst_cnt[6]_i_2_n_0\
);
\brst_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => bram_addr_ld_en,
I1 => I_WRAP_BRST_n_7,
O => \brst_cnt[7]_i_1_n_0\
);
\brst_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B88BB8B8B8B8"
)
port map (
I0 => \brst_cnt[7]_i_3_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(7),
I3 => brst_cnt(6),
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[7]_i_2_n_0\
);
\brst_cnt[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arlen(7),
O => \brst_cnt[7]_i_3_n_0\
);
\brst_cnt[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => brst_cnt(3),
I1 => brst_cnt(1),
I2 => brst_cnt(0),
I3 => brst_cnt(2),
I4 => brst_cnt(4),
O => \brst_cnt[7]_i_4_n_0\
);
brst_cnt_max_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_cnt_max,
Q => brst_cnt_max_d1,
R => \^bram_rst_a\
);
\brst_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[0]_i_1_n_0\,
Q => brst_cnt(0),
R => \^bram_rst_a\
);
\brst_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[1]_i_1_n_0\,
Q => brst_cnt(1),
R => \^bram_rst_a\
);
\brst_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[2]_i_1_n_0\,
Q => brst_cnt(2),
R => \^bram_rst_a\
);
\brst_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[3]_i_1_n_0\,
Q => brst_cnt(3),
R => \^bram_rst_a\
);
\brst_cnt_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[4]_i_1_n_0\,
Q => brst_cnt(4),
R => \^bram_rst_a\
);
\brst_cnt_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[5]_i_1_n_0\,
Q => brst_cnt(5),
R => \^bram_rst_a\
);
\brst_cnt_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[6]_i_1_n_0\,
Q => brst_cnt(6),
R => \^bram_rst_a\
);
\brst_cnt_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[7]_i_2_n_0\,
Q => brst_cnt(7),
R => \^bram_rst_a\
);
brst_one_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E0EE0000"
)
port map (
I0 => brst_one,
I1 => brst_one0,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => s_axi_aresetn,
I5 => last_bram_addr_i_6_n_0,
O => brst_one_i_1_n_0
);
brst_one_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => bram_addr_ld_en,
I1 => I_WRAP_BRST_n_4,
I2 => axi_rd_burst_i_2_n_0,
I3 => brst_cnt(0),
I4 => brst_cnt(1),
I5 => last_bram_addr_i_8_n_0,
O => brst_one0
);
brst_one_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_one_i_1_n_0,
Q => brst_one,
R => '0'
);
brst_zero_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => brst_zero,
I1 => last_bram_addr_i_6_n_0,
I2 => s_axi_aresetn,
I3 => brst_zero_i_2_n_0,
O => brst_zero_i_1_n_0
);
brst_zero_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8A80AAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_arlen_pipe(0),
I2 => axi_araddr_full,
I3 => s_axi_arlen(0),
I4 => axi_rd_burst_i_2_n_0,
O => brst_zero_i_2_n_0
);
brst_zero_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_zero_i_1_n_0,
Q => brst_zero,
R => '0'
);
curr_fixed_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arburst(0),
I1 => axi_arburst_pipe(0),
I2 => s_axi_arburst(1),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(1),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_fixed_burst,
Q => curr_fixed_burst_reg,
R => \^bram_rst_a\
);
curr_wrap_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_arburst(1),
I1 => axi_arburst_pipe(1),
I2 => s_axi_arburst(0),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_wrap_burst,
Q => curr_wrap_burst_reg,
R => \^bram_rst_a\
);
disable_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000D0000"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_two_reg_n_0,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(3),
I4 => disable_b2b_brst_i_2_n_0,
I5 => disable_b2b_brst_i_3_n_0,
O => disable_b2b_brst_cmb
);
disable_b2b_brst_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
O => disable_b2b_brst_i_2_n_0
);
disable_b2b_brst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"F6EF0000F6EFF6EF"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(0),
I4 => disable_b2b_brst,
I5 => disable_b2b_brst_i_4_n_0,
O => disable_b2b_brst_i_3_n_0
);
disable_b2b_brst_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"DFDFDFDFDFDFDFFF"
)
port map (
I0 => pend_rd_op_i_6_n_0,
I1 => rd_adv_buf67_out,
I2 => rd_data_sm_cs(0),
I3 => brst_zero,
I4 => end_brst_rd,
I5 => brst_one,
O => disable_b2b_brst_i_4_n_0
);
disable_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => disable_b2b_brst_cmb,
Q => disable_b2b_brst,
R => \^bram_rst_a\
);
end_brst_rd_clr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFF10100000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => bram_addr_ld_en,
I4 => rd_data_sm_cs(0),
I5 => end_brst_rd_clr,
O => end_brst_rd_clr_i_1_n_0
);
end_brst_rd_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_clr_i_1_n_0,
Q => end_brst_rd_clr,
R => \^bram_rst_a\
);
end_brst_rd_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0020F020"
)
port map (
I0 => brst_cnt_max,
I1 => brst_cnt_max_d1,
I2 => s_axi_aresetn,
I3 => end_brst_rd,
I4 => end_brst_rd_clr,
O => end_brst_rd_i_1_n_0
);
end_brst_rd_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_i_1_n_0,
Q => end_brst_rd,
R => '0'
);
last_bram_addr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF1F110000"
)
port map (
I0 => last_bram_addr_i_2_n_0,
I1 => rd_data_sm_cs(2),
I2 => last_bram_addr_i_3_n_0,
I3 => last_bram_addr_i_4_n_0,
I4 => last_bram_addr_i_5_n_0,
I5 => last_bram_addr_i_6_n_0,
O => last_bram_addr0
);
last_bram_addr_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"EF00EFFFEFFFEFFF"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_two_reg_n_0,
I2 => rd_adv_buf67_out,
I3 => rd_data_sm_cs(3),
I4 => bram_addr_ld_en,
I5 => last_bram_addr_i_7_n_0,
O => last_bram_addr_i_2_n_0
);
last_bram_addr_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDDFFFCFFFF"
)
port map (
I0 => last_bram_addr_i_7_n_0,
I1 => I_WRAP_BRST_n_28,
I2 => axi_rd_burst,
I3 => axi_rd_burst_two_reg_n_0,
I4 => pend_rd_op,
I5 => bram_addr_ld_en,
O => last_bram_addr_i_3_n_0
);
last_bram_addr_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => bram_addr_ld_en,
I3 => pend_rd_op,
O => last_bram_addr_i_4_n_0
);
last_bram_addr_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"81"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
O => last_bram_addr_i_5_n_0
);
last_bram_addr_i_6: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => last_bram_addr_i_8_n_0,
I1 => brst_cnt(0),
I2 => brst_cnt(1),
O => last_bram_addr_i_6_n_0
);
last_bram_addr_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"02A2"
)
port map (
I0 => axi_rd_burst_i_2_n_0,
I1 => s_axi_arlen(0),
I2 => axi_araddr_full,
I3 => axi_arlen_pipe(0),
O => last_bram_addr_i_7_n_0
);
last_bram_addr_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => I_WRAP_BRST_n_7,
I1 => last_bram_addr_i_9_n_0,
I2 => brst_cnt(3),
I3 => brst_cnt(2),
I4 => brst_cnt(4),
I5 => brst_cnt(7),
O => last_bram_addr_i_8_n_0
);
last_bram_addr_i_9: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => brst_cnt(6),
I1 => brst_cnt(5),
O => last_bram_addr_i_9_n_0
);
last_bram_addr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => last_bram_addr0,
Q => last_bram_addr,
R => \^bram_rst_a\
);
no_ar_ack_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA88C8AAAA"
)
port map (
I0 => no_ar_ack,
I1 => rd_data_sm_cs(1),
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(0),
I5 => I_WRAP_BRST_n_28,
O => no_ar_ack_i_1_n_0
);
no_ar_ack_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => no_ar_ack_i_1_n_0,
Q => no_ar_ack,
R => \^bram_rst_a\
);
pend_rd_op_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EFAAEFEF20AA2020"
)
port map (
I0 => pend_rd_op_i_2_n_0,
I1 => pend_rd_op_i_3_n_0,
I2 => pend_rd_op_i_4_n_0,
I3 => pend_rd_op_i_5_n_0,
I4 => pend_rd_op_i_6_n_0,
I5 => pend_rd_op,
O => pend_rd_op_i_1_n_0
);
pend_rd_op_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFCC8C80CCCC8C8"
)
port map (
I0 => p_0_in13_in,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => pend_rd_op_i_7_n_0,
O => pend_rd_op_i_2_n_0
);
pend_rd_op_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00030005"
)
port map (
I0 => pend_rd_op_i_8_n_0,
I1 => pend_rd_op_i_7_n_0,
I2 => bram_addr_ld_en,
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => I_WRAP_BRST_n_28,
O => pend_rd_op_i_3_n_0
);
pend_rd_op_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF00EA"
)
port map (
I0 => bram_addr_ld_en,
I1 => end_brst_rd,
I2 => ar_active,
I3 => rd_data_sm_cs(0),
I4 => pend_rd_op_i_9_n_0,
O => pend_rd_op_i_4_n_0
);
pend_rd_op_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0303070733F3FFFF"
)
port map (
I0 => p_0_in13_in,
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(1),
I3 => \^s_axi_rlast\,
I4 => pend_rd_op,
I5 => bram_addr_ld_en,
O => pend_rd_op_i_5_n_0
);
pend_rd_op_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
O => pend_rd_op_i_6_n_0
);
pend_rd_op_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => ar_active,
I1 => end_brst_rd,
O => pend_rd_op_i_7_n_0
);
pend_rd_op_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => pend_rd_op,
I1 => \^s_axi_rlast\,
O => pend_rd_op_i_8_n_0
);
pend_rd_op_i_9: unisim.vcomponents.LUT5
generic map(
INIT => X"8000FFFF"
)
port map (
I0 => pend_rd_op,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
O => pend_rd_op_i_9_n_0
);
pend_rd_op_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => pend_rd_op_i_1_n_0,
Q => pend_rd_op,
R => \^bram_rst_a\
);
\rd_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF54005555"
)
port map (
I0 => \rd_data_sm_cs[0]_i_2_n_0\,
I1 => pend_rd_op,
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => \rd_data_sm_cs[0]_i_3_n_0\,
I5 => \rd_data_sm_cs[0]_i_4_n_0\,
O => \rd_data_sm_cs[0]_i_1_n_0\
);
\rd_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEAAAAAAFEAAFEAA"
)
port map (
I0 => I_WRAP_BRST_n_28,
I1 => act_rd_burst_two,
I2 => act_rd_burst,
I3 => disable_b2b_brst_i_2_n_0,
I4 => bram_addr_ld_en,
I5 => rd_adv_buf67_out,
O => \rd_data_sm_cs[0]_i_2_n_0\
);
\rd_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[0]_i_3_n_0\
);
\rd_data_sm_cs[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"000300BF0003008F"
)
port map (
I0 => rd_adv_buf67_out,
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(3),
I5 => p_0_in13_in,
O => \rd_data_sm_cs[0]_i_4_n_0\
);
\rd_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABAAABAFFFFAABA"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => I_WRAP_BRST_n_28,
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => rd_data_sm_cs(0),
I4 => I_WRAP_BRST_n_24,
I5 => \rd_data_sm_cs[1]_i_3_n_0\,
O => \rd_data_sm_cs[1]_i_1_n_0\
);
\rd_data_sm_cs[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0CCCCCC88888888"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => I_WRAP_BRST_n_27,
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
I5 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[1]_i_3_n_0\
);
\rd_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAABAEAFAAAB"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(3),
I3 => \rd_data_sm_cs[2]_i_3_n_0\,
I4 => \rd_data_sm_cs[2]_i_4_n_0\,
I5 => \rd_data_sm_cs[2]_i_5_n_0\,
O => \rd_data_sm_cs[2]_i_1_n_0\
);
\rd_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000DF00000"
)
port map (
I0 => bram_addr_ld_en,
I1 => \rd_data_sm_cs[3]_i_6_n_0\,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => rd_data_sm_cs(3),
O => \rd_data_sm_cs[2]_i_2_n_0\
);
\rd_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C0FFFF33F3BBBB"
)
port map (
I0 => axi_rd_burst,
I1 => rd_data_sm_cs(0),
I2 => rd_adv_buf67_out,
I3 => I_WRAP_BRST_n_27,
I4 => rd_data_sm_cs(1),
I5 => axi_rd_burst_two_reg_n_0,
O => \rd_data_sm_cs[2]_i_3_n_0\
);
\rd_data_sm_cs[2]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[2]_i_4_n_0\
);
\rd_data_sm_cs[2]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => brst_zero,
I1 => end_brst_rd,
O => \rd_data_sm_cs[2]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F80FF8F8F80F080"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \rd_data_sm_cs[3]_i_3_n_0\,
I3 => bram_addr_ld_en,
I4 => \rd_data_sm_cs[3]_i_4_n_0\,
I5 => \rd_data_sm_cs[3]_i_5_n_0\,
O => rd_data_sm_ns
);
\rd_data_sm_cs[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000004050005040"
)
port map (
I0 => I_WRAP_BRST_n_28,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => \rd_data_sm_cs[3]_i_6_n_0\,
I5 => rd_adv_buf67_out,
O => \rd_data_sm_cs[3]_i_2_n_0\
);
\rd_data_sm_cs[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4052"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_3_n_0\
);
\rd_data_sm_cs[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0035"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_4_n_0\
);
\rd_data_sm_cs[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF5EFFFF"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(3),
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[3]_i_7_n_0\,
O => \rd_data_sm_cs[3]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"1FFF"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \rd_data_sm_cs[3]_i_6_n_0\
);
\rd_data_sm_cs[3]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => brst_zero,
I1 => axi_b2b_brst,
I2 => end_brst_rd,
O => \rd_data_sm_cs[3]_i_7_n_0\
);
\rd_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[0]_i_1_n_0\,
Q => rd_data_sm_cs(0),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[1]_i_1_n_0\,
Q => rd_data_sm_cs(1),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[2]_i_1_n_0\,
Q => rd_data_sm_cs(2),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[3]_i_2_n_0\,
Q => rd_data_sm_cs(3),
R => \^bram_rst_a\
);
rd_skid_buf_ld_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1110011001100110"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => s_axi_rready,
I5 => \^s_axi_rvalid\,
O => rd_skid_buf_ld_cmb
);
rd_skid_buf_ld_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rd_skid_buf_ld_cmb,
Q => rd_skid_buf_ld_reg,
R => \^bram_rst_a\
);
rddata_mux_sel_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE02"
)
port map (
I0 => rddata_mux_sel_cmb,
I1 => rd_data_sm_cs(3),
I2 => rddata_mux_sel_i_3_n_0,
I3 => rddata_mux_sel,
O => rddata_mux_sel_i_1_n_0
);
rddata_mux_sel_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F010F00F00F000"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
I5 => rd_adv_buf67_out,
O => rddata_mux_sel_cmb
);
rddata_mux_sel_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"F700070FF70F070F"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => axi_rd_burst_two_reg_n_0,
O => rddata_mux_sel_i_3_n_0
);
rddata_mux_sel_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rddata_mux_sel_i_1_n_0,
Q => rddata_mux_sel,
R => \^bram_rst_a\
);
s_axi_arready_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_arready_int,
I1 => \^s_axi_rvalid\,
I2 => s_axi_rready,
I3 => axi_early_arready_int,
O => s_axi_arready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl is
port (
axi_aresetn_d2 : out STD_LOGIC;
axi_aresetn_re_reg : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\GEN_AW_DUAL.aw_active_reg_0\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl is
signal BID_FIFO_n_0 : STD_LOGIC;
signal BID_FIFO_n_10 : STD_LOGIC;
signal BID_FIFO_n_11 : STD_LOGIC;
signal BID_FIFO_n_12 : STD_LOGIC;
signal BID_FIFO_n_13 : STD_LOGIC;
signal BID_FIFO_n_14 : STD_LOGIC;
signal BID_FIFO_n_15 : STD_LOGIC;
signal BID_FIFO_n_3 : STD_LOGIC;
signal BID_FIFO_n_4 : STD_LOGIC;
signal BID_FIFO_n_5 : STD_LOGIC;
signal BID_FIFO_n_6 : STD_LOGIC;
signal BID_FIFO_n_7 : STD_LOGIC;
signal BID_FIFO_n_8 : STD_LOGIC;
signal BID_FIFO_n_9 : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.aw_active_i_2_n_0\ : STD_LOGIC;
signal \^gen_aw_dual.aw_active_reg_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\ : STD_LOGIC;
signal \I_RD_CHNL/axi_aresetn_d1\ : STD_LOGIC;
signal I_WRAP_BRST_n_0 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_13 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_15 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_19 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_21 : STD_LOGIC;
signal I_WRAP_BRST_n_22 : STD_LOGIC;
signal I_WRAP_BRST_n_23 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal aw_active : STD_LOGIC;
signal \^axi_aresetn_d2\ : STD_LOGIC;
signal axi_aresetn_re : STD_LOGIC;
signal \^axi_aresetn_re_reg\ : STD_LOGIC;
signal axi_awaddr_full : STD_LOGIC;
signal axi_awburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_awid_pipe : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_awlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_awlen_pipe_1_or_2 : STD_LOGIC;
signal axi_awsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_bvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_wdata_full_cmb : STD_LOGIC;
signal axi_wdata_full_cmb114_out : STD_LOGIC;
signal axi_wdata_full_reg : STD_LOGIC;
signal axi_wr_burst : STD_LOGIC;
signal axi_wr_burst_cmb : STD_LOGIC;
signal axi_wr_burst_cmb0 : STD_LOGIC;
signal axi_wr_burst_i_1_n_0 : STD_LOGIC;
signal axi_wr_burst_i_3_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_1_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_3_n_0 : STD_LOGIC;
signal bid_gets_fifo_load : STD_LOGIC;
signal bid_gets_fifo_load_d1 : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_2_n_0 : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal bram_addr_inc : STD_LOGIC;
signal bram_addr_ld : STD_LOGIC_VECTOR ( 13 downto 10 );
signal bram_addr_ld_en : STD_LOGIC;
signal bram_addr_ld_en_mod : STD_LOGIC;
signal bram_addr_rst_cmb : STD_LOGIC;
signal bram_en_cmb : STD_LOGIC;
signal bvalid_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \bvalid_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal bvalid_cnt_inc : STD_LOGIC;
signal bvalid_cnt_inc11_out : STD_LOGIC;
signal clr_bram_we : STD_LOGIC;
signal clr_bram_we_cmb : STD_LOGIC;
signal curr_awlen_reg_1_or_2 : STD_LOGIC;
signal curr_awlen_reg_1_or_20 : STD_LOGIC;
signal curr_awlen_reg_1_or_2_i_2_n_0 : STD_LOGIC;
signal curr_awlen_reg_1_or_2_i_3_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal delay_aw_active_clr : STD_LOGIC;
signal last_data_ack_mod : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal wr_addr_sm_cs : STD_LOGIC;
signal wr_data_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of wr_data_sm_cs : signal is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\ : label is "soft_lutpair65";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \GEN_AW_DUAL.last_data_ack_mod_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_2 : label is "soft_lutpair63";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_2 : label is "soft_lutpair62";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_2 : label is "soft_lutpair62";
begin
\GEN_AW_DUAL.aw_active_reg_0\ <= \^gen_aw_dual.aw_active_reg_0\;
axi_aresetn_d2 <= \^axi_aresetn_d2\;
axi_aresetn_re_reg <= \^axi_aresetn_re_reg\;
bram_addr_a(13 downto 0) <= \^bram_addr_a\(13 downto 0);
s_axi_awready <= \^s_axi_awready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_wready <= \^s_axi_wready\;
BID_FIFO: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO
port map (
D(11) => BID_FIFO_n_4,
D(10) => BID_FIFO_n_5,
D(9) => BID_FIFO_n_6,
D(8) => BID_FIFO_n_7,
D(7) => BID_FIFO_n_8,
D(6) => BID_FIFO_n_9,
D(5) => BID_FIFO_n_10,
D(4) => BID_FIFO_n_11,
D(3) => BID_FIFO_n_12,
D(2) => BID_FIFO_n_13,
D(1) => BID_FIFO_n_14,
D(0) => BID_FIFO_n_15,
E(0) => BID_FIFO_n_0,
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
Q(11 downto 0) => axi_awid_pipe(11 downto 0),
SR(0) => SR(0),
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
axi_bvalid_int_reg => \^s_axi_bvalid\,
axi_wdata_full_cmb114_out => axi_wdata_full_cmb114_out,
axi_wr_burst => axi_wr_burst,
bid_gets_fifo_load => bid_gets_fifo_load,
bid_gets_fifo_load_d1 => bid_gets_fifo_load_d1,
bid_gets_fifo_load_d1_reg => BID_FIFO_n_3,
bram_addr_ld_en => bram_addr_ld_en,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
bvalid_cnt_inc => bvalid_cnt_inc,
\bvalid_cnt_reg[1]\ => bid_gets_fifo_load_d1_i_2_n_0,
\bvalid_cnt_reg[2]\ => I_WRAP_BRST_n_20,
\bvalid_cnt_reg[2]_0\ => I_WRAP_BRST_n_19,
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awready => \^s_axi_awready\,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
wr_addr_sm_cs => wr_addr_sm_cs
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(0),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"05051F1A"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => axi_wr_burst_cmb0,
I2 => wr_data_sm_cs(0),
I3 => axi_wdata_full_cmb114_out,
I4 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"5515"
)
port map (
I0 => I_WRAP_BRST_n_21,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
O => axi_wr_burst_cmb0
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(1),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000554000555540"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => s_axi_wlast,
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(2),
I5 => axi_wr_burst,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"44010001"
)
port map (
I0 => wr_data_sm_cs(2),
I1 => wr_data_sm_cs(1),
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7774777774744444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(0),
I5 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\,
Q => wr_data_sm_cs(0),
R => SR(0)
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\,
Q => wr_data_sm_cs(1),
R => SR(0)
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\,
Q => wr_data_sm_cs(2),
R => SR(0)
);
\GEN_AWREADY.axi_aresetn_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_aresetn,
Q => \I_RD_CHNL/axi_aresetn_d1\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \I_RD_CHNL/axi_aresetn_d1\,
Q => \^axi_aresetn_d2\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_re_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_aresetn,
I1 => \I_RD_CHNL/axi_aresetn_d1\,
O => axi_aresetn_re
);
\GEN_AWREADY.axi_aresetn_re_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_aresetn_re,
Q => \^axi_aresetn_re_reg\,
R => '0'
);
\GEN_AWREADY.axi_awready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFBFFFFFAA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => bram_addr_ld_en,
I4 => \^axi_aresetn_re_reg\,
I5 => \^s_axi_awready\,
O => \GEN_AWREADY.axi_awready_int_i_1_n_0\
);
\GEN_AWREADY.axi_awready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"5444444400000000"
)
port map (
I0 => \GEN_AWREADY.axi_awready_int_i_3_n_0\,
I1 => aw_active,
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => s_axi_awvalid,
O => \GEN_AWREADY.axi_awready_int_i_2_n_0\
);
\GEN_AWREADY.axi_awready_int_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABABABABABABABA"
)
port map (
I0 => wr_addr_sm_cs,
I1 => I_WRAP_BRST_n_21,
I2 => last_data_ack_mod,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \GEN_AWREADY.axi_awready_int_i_3_n_0\
);
\GEN_AWREADY.axi_awready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AWREADY.axi_awready_int_i_1_n_0\,
Q => \^s_axi_awready\,
R => SR(0)
);
\GEN_AW_DUAL.aw_active_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axi_aresetn_d2\,
O => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.aw_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF7FFFFFF0000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => wr_data_sm_cs(2),
I3 => delay_aw_active_clr,
I4 => bram_addr_ld_en,
I5 => aw_active,
O => \GEN_AW_DUAL.aw_active_i_2_n_0\
);
\GEN_AW_DUAL.aw_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.aw_active_i_2_n_0\,
Q => aw_active,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.last_data_ack_mod_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => p_18_out
);
\GEN_AW_DUAL.last_data_ack_mod_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_18_out,
Q => last_data_ack_mod,
R => SR(0)
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000100000"
)
port map (
I0 => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\,
I1 => wr_addr_sm_cs,
I2 => s_axi_awvalid,
I3 => axi_awaddr_full,
I4 => I_WRAP_BRST_n_20,
I5 => aw_active,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => I_WRAP_BRST_n_20,
I1 => last_data_ack_mod,
I2 => axi_awaddr_full,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => axi_awlen_pipe_1_or_2,
I5 => curr_awlen_reg_1_or_2,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\,
Q => wr_addr_sm_cs,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(8),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(9),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(10),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(11),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(12),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(13),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(0),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(1),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(2),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(3),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(4),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(5),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(6),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(7),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4000EA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => s_axi_aresetn,
I4 => bram_addr_ld_en,
O => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\,
Q => axi_awaddr_full,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BF00BF00BF00FF40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => s_axi_awburst(0),
I5 => s_axi_awburst(1),
O => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(0),
Q => axi_awburst_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(1),
Q => axi_awburst_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(0),
Q => axi_awid_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(10),
Q => axi_awid_pipe(10),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(11),
Q => axi_awid_pipe(11),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(1),
Q => axi_awid_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(2),
Q => axi_awid_pipe(2),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(3),
Q => axi_awid_pipe(3),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(4),
Q => axi_awid_pipe(4),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(5),
Q => axi_awid_pipe(5),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(6),
Q => axi_awid_pipe(6),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(7),
Q => axi_awid_pipe(7),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(8),
Q => axi_awid_pipe(8),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(9),
Q => axi_awid_pipe(9),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
I1 => s_axi_awlen(3),
I2 => s_axi_awlen(2),
I3 => s_axi_awlen(1),
O => p_9_out
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_awlen(4),
I1 => s_axi_awlen(6),
I2 => s_axi_awlen(7),
I3 => s_axi_awlen(5),
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => p_9_out,
Q => axi_awlen_pipe_1_or_2,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(0),
Q => axi_awlen_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(1),
Q => axi_awlen_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(2),
Q => axi_awlen_pipe(2),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(3),
Q => axi_awlen_pipe(3),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(4),
Q => axi_awlen_pipe(4),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(5),
Q => axi_awlen_pipe(5),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(6),
Q => axi_awlen_pipe(6),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(7),
Q => axi_awlen_pipe(7),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => '1',
Q => axi_awsize_pipe(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^bram_addr_a\(4),
I1 => \^bram_addr_a\(1),
I2 => \^bram_addr_a\(0),
I3 => \^bram_addr_a\(2),
I4 => \^bram_addr_a\(3),
I5 => \^bram_addr_a\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^bram_addr_a\(6),
I1 => \^bram_addr_a\(4),
I2 => I_WRAP_BRST_n_17,
I3 => \^bram_addr_a\(5),
I4 => \^bram_addr_a\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => s_axi_wvalid,
O => bram_addr_inc
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => wr_data_sm_cs(1),
O => bram_addr_rst_cmb
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_8,
Q => \^bram_addr_a\(8),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_7,
Q => \^bram_addr_a\(9),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(10),
Q => \^bram_addr_a\(10),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(11),
Q => \^bram_addr_a\(11),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(12),
Q => \^bram_addr_a\(12),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(13),
Q => \^bram_addr_a\(13),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_16,
Q => \^bram_addr_a\(0),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_15,
Q => \^bram_addr_a\(1),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_14,
Q => \^bram_addr_a\(2),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_13,
Q => \^bram_addr_a\(3),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_12,
Q => \^bram_addr_a\(4),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_11,
Q => \^bram_addr_a\(5),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_10,
Q => \^bram_addr_a\(6),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_9,
Q => \^bram_addr_a\(7),
R => I_WRAP_BRST_n_0
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"15FF1500"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
O => axi_wdata_full_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wdata_full_cmb,
Q => axi_wdata_full_reg,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4777477444444444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => s_axi_wvalid,
O => bram_en_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_cmb,
Q => bram_en_a,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000101110"
)
port map (
I0 => wr_data_sm_cs(0),
I1 => wr_data_sm_cs(1),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I5 => axi_wr_burst,
O => clr_bram_we_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => clr_bram_we_cmb,
Q => clr_bram_we,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEAAFEFF02AA0200"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\,
I1 => axi_wr_burst,
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\,
I5 => delay_aw_active_clr,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000222E"
)
port map (
I0 => s_axi_wlast,
I1 => wr_data_sm_cs(2),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(1),
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8B338B0088008800"
)
port map (
I0 => delay_aw_active_clr,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => bvalid_cnt_inc11_out,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_wlast,
O => bvalid_cnt_inc11_out
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\,
Q => delay_aw_active_clr,
R => SR(0)
);
\GEN_WRDATA[0].bram_wrdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(0),
Q => bram_wrdata_a(0),
R => '0'
);
\GEN_WRDATA[10].bram_wrdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(10),
Q => bram_wrdata_a(10),
R => '0'
);
\GEN_WRDATA[11].bram_wrdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(11),
Q => bram_wrdata_a(11),
R => '0'
);
\GEN_WRDATA[12].bram_wrdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(12),
Q => bram_wrdata_a(12),
R => '0'
);
\GEN_WRDATA[13].bram_wrdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(13),
Q => bram_wrdata_a(13),
R => '0'
);
\GEN_WRDATA[14].bram_wrdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(14),
Q => bram_wrdata_a(14),
R => '0'
);
\GEN_WRDATA[15].bram_wrdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(15),
Q => bram_wrdata_a(15),
R => '0'
);
\GEN_WRDATA[16].bram_wrdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(16),
Q => bram_wrdata_a(16),
R => '0'
);
\GEN_WRDATA[17].bram_wrdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(17),
Q => bram_wrdata_a(17),
R => '0'
);
\GEN_WRDATA[18].bram_wrdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(18),
Q => bram_wrdata_a(18),
R => '0'
);
\GEN_WRDATA[19].bram_wrdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(19),
Q => bram_wrdata_a(19),
R => '0'
);
\GEN_WRDATA[1].bram_wrdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(1),
Q => bram_wrdata_a(1),
R => '0'
);
\GEN_WRDATA[20].bram_wrdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(20),
Q => bram_wrdata_a(20),
R => '0'
);
\GEN_WRDATA[21].bram_wrdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(21),
Q => bram_wrdata_a(21),
R => '0'
);
\GEN_WRDATA[22].bram_wrdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(22),
Q => bram_wrdata_a(22),
R => '0'
);
\GEN_WRDATA[23].bram_wrdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(23),
Q => bram_wrdata_a(23),
R => '0'
);
\GEN_WRDATA[24].bram_wrdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(24),
Q => bram_wrdata_a(24),
R => '0'
);
\GEN_WRDATA[25].bram_wrdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(25),
Q => bram_wrdata_a(25),
R => '0'
);
\GEN_WRDATA[26].bram_wrdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(26),
Q => bram_wrdata_a(26),
R => '0'
);
\GEN_WRDATA[27].bram_wrdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(27),
Q => bram_wrdata_a(27),
R => '0'
);
\GEN_WRDATA[28].bram_wrdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(28),
Q => bram_wrdata_a(28),
R => '0'
);
\GEN_WRDATA[29].bram_wrdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(29),
Q => bram_wrdata_a(29),
R => '0'
);
\GEN_WRDATA[2].bram_wrdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(2),
Q => bram_wrdata_a(2),
R => '0'
);
\GEN_WRDATA[30].bram_wrdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(30),
Q => bram_wrdata_a(30),
R => '0'
);
\GEN_WRDATA[31].bram_wrdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(31),
Q => bram_wrdata_a(31),
R => '0'
);
\GEN_WRDATA[3].bram_wrdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(3),
Q => bram_wrdata_a(3),
R => '0'
);
\GEN_WRDATA[4].bram_wrdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(4),
Q => bram_wrdata_a(4),
R => '0'
);
\GEN_WRDATA[5].bram_wrdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(5),
Q => bram_wrdata_a(5),
R => '0'
);
\GEN_WRDATA[6].bram_wrdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(6),
Q => bram_wrdata_a(6),
R => '0'
);
\GEN_WRDATA[7].bram_wrdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(7),
Q => bram_wrdata_a(7),
R => '0'
);
\GEN_WRDATA[8].bram_wrdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(8),
Q => bram_wrdata_a(8),
R => '0'
);
\GEN_WRDATA[9].bram_wrdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(9),
Q => bram_wrdata_a(9),
R => '0'
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"D0FF"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => clr_bram_we,
I3 => s_axi_aresetn,
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(0),
Q => bram_we_a(0),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(1),
Q => bram_we_a(1),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(2),
Q => bram_we_a(2),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(3),
Q => bram_we_a(3),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
I_WRAP_BRST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst
port map (
D(13 downto 10) => bram_addr_ld(13 downto 10),
D(9) => I_WRAP_BRST_n_7,
D(8) => I_WRAP_BRST_n_8,
D(7) => I_WRAP_BRST_n_9,
D(6) => I_WRAP_BRST_n_10,
D(5) => I_WRAP_BRST_n_11,
D(4) => I_WRAP_BRST_n_12,
D(3) => I_WRAP_BRST_n_13,
D(2) => I_WRAP_BRST_n_14,
D(1) => I_WRAP_BRST_n_15,
D(0) => I_WRAP_BRST_n_16,
E(0) => I_WRAP_BRST_n_2,
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => I_WRAP_BRST_n_17,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\,
Q(3 downto 0) => axi_awlen_pipe(3 downto 0),
SR(0) => I_WRAP_BRST_n_0,
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
axi_awsize_pipe(0) => axi_awsize_pipe(1),
bram_addr_a(9 downto 0) => \^bram_addr_a\(9 downto 0),
bram_addr_inc => bram_addr_inc,
bram_addr_ld_en => bram_addr_ld_en,
bram_addr_ld_en_mod => bram_addr_ld_en_mod,
bram_addr_rst_cmb => bram_addr_rst_cmb,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
curr_fixed_burst => curr_fixed_burst,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_fixed_burst_reg_reg => I_WRAP_BRST_n_22,
curr_wrap_burst => curr_wrap_burst,
curr_wrap_burst_reg => curr_wrap_burst_reg,
curr_wrap_burst_reg_reg => I_WRAP_BRST_n_23,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0(0) => SR(0),
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_wvalid => s_axi_wvalid,
\save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_19,
\save_init_bram_addr_ld_reg[15]_1\ => I_WRAP_BRST_n_20,
\save_init_bram_addr_ld_reg[15]_2\ => I_WRAP_BRST_n_21,
wr_addr_sm_cs => wr_addr_sm_cs
);
\axi_bid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_15,
Q => s_axi_bid(0),
R => SR(0)
);
\axi_bid_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_5,
Q => s_axi_bid(10),
R => SR(0)
);
\axi_bid_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_4,
Q => s_axi_bid(11),
R => SR(0)
);
\axi_bid_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_14,
Q => s_axi_bid(1),
R => SR(0)
);
\axi_bid_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_13,
Q => s_axi_bid(2),
R => SR(0)
);
\axi_bid_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_12,
Q => s_axi_bid(3),
R => SR(0)
);
\axi_bid_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_11,
Q => s_axi_bid(4),
R => SR(0)
);
\axi_bid_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_10,
Q => s_axi_bid(5),
R => SR(0)
);
\axi_bid_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_9,
Q => s_axi_bid(6),
R => SR(0)
);
\axi_bid_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_8,
Q => s_axi_bid(7),
R => SR(0)
);
\axi_bid_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_7,
Q => s_axi_bid(8),
R => SR(0)
);
\axi_bid_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_6,
Q => s_axi_bid(9),
R => SR(0)
);
axi_bvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAA8A88"
)
port map (
I0 => s_axi_aresetn,
I1 => bvalid_cnt_inc,
I2 => BID_FIFO_n_3,
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => bvalid_cnt(1),
O => axi_bvalid_int_i_1_n_0
);
axi_bvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_bvalid_int_i_1_n_0,
Q => \^s_axi_bvalid\,
R => '0'
);
axi_wr_burst_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_wr_burst_cmb,
I1 => axi_wr_burst_i_3_n_0,
I2 => axi_wr_burst,
O => axi_wr_burst_i_1_n_0
);
axi_wr_burst_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"3088FCBB"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wlast,
O => axi_wr_burst_cmb
);
axi_wr_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAA222"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(0),
I2 => axi_wr_burst_cmb0,
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(1),
I5 => wr_data_sm_cs(2),
O => axi_wr_burst_i_3_n_0
);
axi_wr_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wr_burst_i_1_n_0,
Q => axi_wr_burst,
R => SR(0)
);
axi_wready_int_mod_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EA00EAFF00000000"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
I5 => s_axi_aresetn,
O => axi_wready_int_mod_i_1_n_0
);
axi_wready_int_mod_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"F8F9F0F0"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => axi_wdata_full_reg,
I3 => axi_wdata_full_cmb114_out,
I4 => s_axi_wvalid,
O => axi_wready_int_mod_i_3_n_0
);
axi_wready_int_mod_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wready_int_mod_i_1_n_0,
Q => \^s_axi_wready\,
R => '0'
);
bid_gets_fifo_load_d1_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
O => bid_gets_fifo_load_d1_i_2_n_0
);
bid_gets_fifo_load_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bid_gets_fifo_load,
Q => bid_gets_fifo_load_d1,
R => SR(0)
);
\bvalid_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"95956A6A95956AAA"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[0]_i_1_n_0\
);
\bvalid_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D5D5BFBF2A2A4000"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[1]_i_1_n_0\
);
\bvalid_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D52AFF00FF00BF00"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[2]_i_1_n_0\
);
\bvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[0]_i_1_n_0\,
Q => bvalid_cnt(0),
R => SR(0)
);
\bvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[1]_i_1_n_0\,
Q => bvalid_cnt(1),
R => SR(0)
);
\bvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[2]_i_1_n_0\,
Q => bvalid_cnt(2),
R => SR(0)
);
curr_awlen_reg_1_or_2_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00A0000000A0E0E0"
)
port map (
I0 => curr_awlen_reg_1_or_2_i_2_n_0,
I1 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
I2 => curr_awlen_reg_1_or_2_i_3_n_0,
I3 => axi_awlen_pipe(3),
I4 => axi_awaddr_full,
I5 => s_axi_awlen(3),
O => curr_awlen_reg_1_or_20
);
curr_awlen_reg_1_or_2_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => axi_awlen_pipe(7),
I1 => axi_awaddr_full,
I2 => axi_awlen_pipe(5),
I3 => axi_awlen_pipe(4),
I4 => axi_awlen_pipe(6),
O => curr_awlen_reg_1_or_2_i_2_n_0
);
curr_awlen_reg_1_or_2_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awlen(2),
I1 => axi_awlen_pipe(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => axi_awlen_pipe(1),
O => curr_awlen_reg_1_or_2_i_3_n_0
);
curr_awlen_reg_1_or_2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_awlen_reg_1_or_20,
Q => curr_awlen_reg_1_or_2,
R => SR(0)
);
curr_fixed_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_22,
Q => curr_fixed_burst_reg,
R => '0'
);
curr_wrap_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_23,
Q => curr_wrap_burst_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi is
signal I_WR_CHNL_n_36 : STD_LOGIC;
signal axi_aresetn_d2 : STD_LOGIC;
signal axi_aresetn_re_reg : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
begin
bram_rst_a <= \^bram_rst_a\;
I_RD_CHNL: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl
port map (
\GEN_AWREADY.axi_aresetn_d2_reg\ => I_WR_CHNL_n_36,
Q(13 downto 0) => bram_addr_b(13 downto 0),
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
I_WR_CHNL: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl
port map (
\GEN_AW_DUAL.aw_active_reg_0\ => I_WR_CHNL_n_36,
SR(0) => \^bram_rst_a\,
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0),
bram_en_a => bram_en_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top is
begin
\GEN_AXI4.I_FULL_AXI\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi
port map (
bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0),
bram_addr_b(13 downto 0) => bram_addr_b(13 downto 0),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ecc_interrupt : out STD_LOGIC;
ecc_ue : out STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_ctrl_awvalid : in STD_LOGIC;
s_axi_ctrl_awready : out STD_LOGIC;
s_axi_ctrl_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wvalid : in STD_LOGIC;
s_axi_ctrl_wready : out STD_LOGIC;
s_axi_ctrl_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_bvalid : out STD_LOGIC;
s_axi_ctrl_bready : in STD_LOGIC;
s_axi_ctrl_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_arvalid : in STD_LOGIC;
s_axi_ctrl_arready : out STD_LOGIC;
s_axi_ctrl_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_rvalid : out STD_LOGIC;
s_axi_ctrl_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 14;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 16384;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 16;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 12;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl is
signal \<const0>\ : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 15 downto 2 );
signal \^bram_addr_b\ : STD_LOGIC_VECTOR ( 15 downto 2 );
signal \^bram_rst_a\ : STD_LOGIC;
signal \^s_axi_aclk\ : STD_LOGIC;
begin
\^s_axi_aclk\ <= s_axi_aclk;
bram_addr_a(15 downto 2) <= \^bram_addr_a\(15 downto 2);
bram_addr_a(1) <= \<const0>\;
bram_addr_a(0) <= \<const0>\;
bram_addr_b(15 downto 2) <= \^bram_addr_b\(15 downto 2);
bram_addr_b(1) <= \<const0>\;
bram_addr_b(0) <= \<const0>\;
bram_clk_a <= \^s_axi_aclk\;
bram_clk_b <= \^s_axi_aclk\;
bram_rst_a <= \^bram_rst_a\;
bram_rst_b <= \^bram_rst_a\;
bram_we_b(3) <= \<const0>\;
bram_we_b(2) <= \<const0>\;
bram_we_b(1) <= \<const0>\;
bram_we_b(0) <= \<const0>\;
bram_wrdata_b(31) <= \<const0>\;
bram_wrdata_b(30) <= \<const0>\;
bram_wrdata_b(29) <= \<const0>\;
bram_wrdata_b(28) <= \<const0>\;
bram_wrdata_b(27) <= \<const0>\;
bram_wrdata_b(26) <= \<const0>\;
bram_wrdata_b(25) <= \<const0>\;
bram_wrdata_b(24) <= \<const0>\;
bram_wrdata_b(23) <= \<const0>\;
bram_wrdata_b(22) <= \<const0>\;
bram_wrdata_b(21) <= \<const0>\;
bram_wrdata_b(20) <= \<const0>\;
bram_wrdata_b(19) <= \<const0>\;
bram_wrdata_b(18) <= \<const0>\;
bram_wrdata_b(17) <= \<const0>\;
bram_wrdata_b(16) <= \<const0>\;
bram_wrdata_b(15) <= \<const0>\;
bram_wrdata_b(14) <= \<const0>\;
bram_wrdata_b(13) <= \<const0>\;
bram_wrdata_b(12) <= \<const0>\;
bram_wrdata_b(11) <= \<const0>\;
bram_wrdata_b(10) <= \<const0>\;
bram_wrdata_b(9) <= \<const0>\;
bram_wrdata_b(8) <= \<const0>\;
bram_wrdata_b(7) <= \<const0>\;
bram_wrdata_b(6) <= \<const0>\;
bram_wrdata_b(5) <= \<const0>\;
bram_wrdata_b(4) <= \<const0>\;
bram_wrdata_b(3) <= \<const0>\;
bram_wrdata_b(2) <= \<const0>\;
bram_wrdata_b(1) <= \<const0>\;
bram_wrdata_b(0) <= \<const0>\;
ecc_interrupt <= \<const0>\;
ecc_ue <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_ctrl_arready <= \<const0>\;
s_axi_ctrl_awready <= \<const0>\;
s_axi_ctrl_bresp(1) <= \<const0>\;
s_axi_ctrl_bresp(0) <= \<const0>\;
s_axi_ctrl_bvalid <= \<const0>\;
s_axi_ctrl_rdata(31) <= \<const0>\;
s_axi_ctrl_rdata(30) <= \<const0>\;
s_axi_ctrl_rdata(29) <= \<const0>\;
s_axi_ctrl_rdata(28) <= \<const0>\;
s_axi_ctrl_rdata(27) <= \<const0>\;
s_axi_ctrl_rdata(26) <= \<const0>\;
s_axi_ctrl_rdata(25) <= \<const0>\;
s_axi_ctrl_rdata(24) <= \<const0>\;
s_axi_ctrl_rdata(23) <= \<const0>\;
s_axi_ctrl_rdata(22) <= \<const0>\;
s_axi_ctrl_rdata(21) <= \<const0>\;
s_axi_ctrl_rdata(20) <= \<const0>\;
s_axi_ctrl_rdata(19) <= \<const0>\;
s_axi_ctrl_rdata(18) <= \<const0>\;
s_axi_ctrl_rdata(17) <= \<const0>\;
s_axi_ctrl_rdata(16) <= \<const0>\;
s_axi_ctrl_rdata(15) <= \<const0>\;
s_axi_ctrl_rdata(14) <= \<const0>\;
s_axi_ctrl_rdata(13) <= \<const0>\;
s_axi_ctrl_rdata(12) <= \<const0>\;
s_axi_ctrl_rdata(11) <= \<const0>\;
s_axi_ctrl_rdata(10) <= \<const0>\;
s_axi_ctrl_rdata(9) <= \<const0>\;
s_axi_ctrl_rdata(8) <= \<const0>\;
s_axi_ctrl_rdata(7) <= \<const0>\;
s_axi_ctrl_rdata(6) <= \<const0>\;
s_axi_ctrl_rdata(5) <= \<const0>\;
s_axi_ctrl_rdata(4) <= \<const0>\;
s_axi_ctrl_rdata(3) <= \<const0>\;
s_axi_ctrl_rdata(2) <= \<const0>\;
s_axi_ctrl_rdata(1) <= \<const0>\;
s_axi_ctrl_rdata(0) <= \<const0>\;
s_axi_ctrl_rresp(1) <= \<const0>\;
s_axi_ctrl_rresp(0) <= \<const0>\;
s_axi_ctrl_rvalid <= \<const0>\;
s_axi_ctrl_wready <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gext_inst.abcv4_0_ext_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top
port map (
bram_addr_a(13 downto 0) => \^bram_addr_a\(15 downto 2),
bram_addr_b(13 downto 0) => \^bram_addr_b\(15 downto 2),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => \^s_axi_aclk\,
s_axi_araddr(13 downto 0) => s_axi_araddr(15 downto 2),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(15 downto 2),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zynq_design_1_axi_bram_ctrl_0_1,axi_bram_ctrl,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_bram_ctrl,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_ecc_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_ecc_ue_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ctrl_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_ctrl_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of U0 : label is 14;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of U0 : label is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of U0 : label is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of U0 : label is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of U0 : label is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of U0 : label is 16384;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 16;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of U0 : label is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of U0 : label is 12;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of U0 : label is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of U0 : label is 0;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl
port map (
bram_addr_a(15 downto 0) => bram_addr_a(15 downto 0),
bram_addr_b(15 downto 0) => bram_addr_b(15 downto 0),
bram_clk_a => bram_clk_a,
bram_clk_b => bram_clk_b,
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_a(31 downto 0) => bram_rddata_a(31 downto 0),
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_rst_b => bram_rst_b,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_we_b(3 downto 0) => bram_we_b(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
bram_wrdata_b(31 downto 0) => bram_wrdata_b(31 downto 0),
ecc_interrupt => NLW_U0_ecc_interrupt_UNCONNECTED,
ecc_ue => NLW_U0_ecc_ue_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(15 downto 0) => s_axi_araddr(15 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock => s_axi_arlock,
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(15 downto 0) => s_axi_awaddr(15 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock => s_axi_awlock,
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_ctrl_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_arready => NLW_U0_s_axi_ctrl_arready_UNCONNECTED,
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_awready => NLW_U0_s_axi_ctrl_awready_UNCONNECTED,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_bresp(1 downto 0) => NLW_U0_s_axi_ctrl_bresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_bvalid => NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED,
s_axi_ctrl_rdata(31 downto 0) => NLW_U0_s_axi_ctrl_rdata_UNCONNECTED(31 downto 0),
s_axi_ctrl_rready => '0',
s_axi_ctrl_rresp(1 downto 0) => NLW_U0_s_axi_ctrl_rresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_rvalid => NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED,
s_axi_ctrl_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_wready => NLW_U0_s_axi_ctrl_wready_UNCONNECTED,
s_axi_ctrl_wvalid => '0',
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 009a0aeef4ad721df105ef2b0411f05f | 0.545279 | 2.566402 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_bram_ctrl_0_0/sim/zynq_design_1_axi_bram_ctrl_0_0.vhd | 2 | 16,920 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0_11;
USE axi_bram_ctrl_v4_0_11.axi_bram_ctrl;
ENTITY zynq_design_1_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END zynq_design_1_axi_bram_ctrl_0_0;
ARCHITECTURE zynq_design_1_axi_bram_ctrl_0_0_arch OF zynq_design_1_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 16384,
C_BRAM_ADDR_WIDTH => 14,
C_S_AXI_ADDR_WIDTH => 16,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 12,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 0,
C_FAMILY => "zynq",
C_SELECT_XPM => 0,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rst_b => bram_rst_b,
bram_clk_b => bram_clk_b,
bram_en_b => bram_en_b,
bram_we_b => bram_we_b,
bram_addr_b => bram_addr_b,
bram_wrdata_b => bram_wrdata_b,
bram_rddata_b => bram_rddata_b
);
END zynq_design_1_axi_bram_ctrl_0_0_arch;
| mit | 0a706d55a655505d14d9f25b87f89e9a | 0.67169 | 3.085902 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/can/can_rd.vhd | 1 | 6,705 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_oc
-- File: can_oc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB interface for the OpenCores CAN MAC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.can.all;
entity can_rd is
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
dmap : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(1 downto 0);
can_txo : out std_logic_vector(1 downto 0)
);
end;
architecture rtl of can_rd is
constant ncores : integer := 1;
constant sepirq : integer := 0;
constant REVISION : amba_version_type := ncores-1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_CANAHB, 0, REVISION, irq),
4 => ahb_iobar(ioaddr, iomask), others => zero32);
type ahbregs is record
hsel : std_ulogic;
hwrite : std_ulogic;
hwrite2 : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(10 downto 0);
hwdata : std_logic_vector(7 downto 0);
herr : std_ulogic;
hready : std_ulogic;
ws : std_logic_vector(1 downto 0);
irqi : std_logic_vector(ncores-1 downto 0);
irqo : std_logic_vector(ncores-1 downto 0);
muxsel : std_logic;
writemux : std_logic;
end record;
subtype cdata is std_logic_vector(7 downto 0);
type cdataarr is array (0 to 7) of cdata;
signal data_out : cdataarr;
signal reset : std_logic;
signal irqo : std_logic_vector(ncores-1 downto 0);
signal addr : std_logic_vector(7 downto 0);
signal vcc, gnd : std_ulogic;
signal r, rin : ahbregs;
signal can_lrxi, can_ltxo : std_logic;
begin
gnd <= '0'; vcc <= '1'; reset <= not resetn;
comb : process(ahbsi, r, resetn, data_out, irqo)
variable v : ahbregs;
variable hresp : std_logic_vector(1 downto 0);
variable dataout : std_logic_vector(7 downto 0);
variable irqvec : std_logic_vector(NAHBIRQ-1 downto 0);
variable vmuxreg : std_logic;
variable hwdata : std_logic_vector(31 downto 0);
begin
v := r;
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
if (r.hsel = '1' ) and (r.ws /= "11") then v.ws := r.ws + 1; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(slvndx);
v.haddr := ahbsi.haddr(10 downto 0);
v.htrans := ahbsi.htrans;
v.hwrite := ahbsi.hwrite;
v.herr := orv(ahbsi.hsize) and ahbsi.hwrite;
v.ws := "00";
end if;
v.hready := (r.hsel and r.ws(1) and not r.ws(0)) or not resetn
or (ahbsi.hready and not ahbsi.htrans(1));
vmuxreg := not r.haddr(7) and r.haddr(6);
--v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
-- and not r.ws(0) and not r.herr;
v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and not r.herr and not vmuxreg;
v.writemux := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and vmuxreg;
if (r.herr and r.ws(1)) = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
case r.haddr(1 downto 0) is
when "00" => v.hwdata := hwdata(31 downto 24);
when "01" => v.hwdata := hwdata(23 downto 16);
when "10" => v.hwdata := hwdata(15 downto 8);
when others => v.hwdata := hwdata(7 downto 0);
end case;
--dataout := data_out(0);
if r.haddr(7 downto 6) = "01" then
dataout := (others => r.muxsel);
if r.writemux = '1' then
v.muxsel := r.hwdata(0);
end if;
else
dataout := data_out(0);
end if;
-- Interrupt goes to low when appeard and is normal high
-- but the irq controller from leon is active high and the interrupt should appear only
-- for 1 Clk cycle,
v.irqi := irqo; v.irqo:= (r.irqi and not irqo);
irqvec := (others => '0');
if sepirq = 1 then irqvec(ncores-1+irq downto irq) := r.irqo;
else irqvec(irq) := orv(r.irqo); end if;
ahbso.hirq <= irqvec;
ahbso.hrdata <= ahbdrivedata(dataout);
ahbso.hresp <= hresp; rin <= v;
end process;
-- Double mapping of registers [byte (offset 0), word (offset 0x80)]
dmap0 : if dmap = 0 generate
addr <= r.haddr(7 downto 0);
end generate;
dmap1 : if dmap = 1 generate
addr <= "000"&r.haddr(6 downto 2) when r.haddr(7) = '1' else
r.haddr(7 downto 0);
end generate;
reg : process(clk)
begin if clk'event and clk = '1' then r <= rin; end if; end process;
cmod : can_mod generic map (memtech, syncrst)
--port map (reset, clk, r.hsel, r.hwrite2, r.haddr(7 downto 0), r.hwdata,
port map (reset, clk, r.hsel, r.hwrite2, addr, r.hwdata,
data_out(0), irqo(0), can_lrxi, can_ltxo, ahbsi.testen);
cmux : canmux port map (r.muxsel, can_lrxi, can_ltxo, can_rxi, can_txo);
ahbso.hconfig <= hconfig;
ahbso.hindex <= slvndx;
ahbso.hsplit <= (others => '0');
ahbso.hready <= r.hready;
-- pragma translate_off
bootmsg : report_version
generic map (
"can_oc" & tost(slvndx) &
": SJA1000 Compatible CAN MAC, revision " & tost(REVISION) &
", irq " & tost(irq));
-- pragma translate_on
end;
| gpl-2.0 | d1dbf74c35569c910d1b273fda069963 | 0.594631 | 3.412214 | false | false | false | false |
dsaves/dsaves-hdl | primitives/lut.vhd | 1 | 2,492 | --MIT License
--
--Copyright (c) 2017 Danny Savory
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
library ieee, dsaves;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity LUT is
generic(
N : natural
);
port(
clk : in std_logic;
rst : in std_logic;
d : in std_logic_vector((2**N)-1 downto 0);
wen : in std_logic;
s : in std_logic_vector(N-1 downto 0);
o : out std_logic
);
end entity;
architecture POS_EDGE of LUT is
signal mem_bank : std_logic_vector((2**N)-1 downto 0);
begin
MEM_GENERATE:
for i in 0 to ((2**N)-1) generate
FF : entity dsaves.FF(POS_EDGE_HI_EN)
port map(
clk => clk,
d => d(i),
en => wen,
rst => rst,
q => mem_bank(i)
);
end generate;
o <= mem_bank(to_integer(unsigned(s)));
end architecture;
architecture NEG_EDGE of LUT is
signal mem_bank : std_logic_vector((2**N)-1 downto 0);
begin
MEM_GENERATE:
for i in 0 to ((2**N)-1) generate
FF : entity dsaves.FF(NEG_EDGE_HI_EN)
port map(
clk => clk,
d => d(i),
en => wen,
rst => rst,
q => mem_bank(i)
);
end generate;
o <= mem_bank(to_integer(unsigned(s)));
end architecture;
| mit | b889983b2ec5203d0d85ca402d4858ee | 0.598315 | 3.845679 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/misc/gptimer.vhd | 1 | 17,976 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gptimer
-- File: gptimer.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implemets a set of general-purpose timers with a
-- common prescaler. Then number of timers and the width of
-- the timers is propgrammable through generics
--
-- Revision 1 of this core merges functionality of the GRTIMET unit:
--
-- This unit also implements the use of an external clock source for the
-- timers.
--
-- This unit also implements a latching register for each timer, latching the
-- timer value on the occurence of an interrupt on the apbi.priq input. The
-- interrupt selection in possible via a mask register.
--
-- This unit also implements loading of all timers on the event of a selected
-- incoming interrupt.
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity gptimer is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
sepirq : integer := 0; -- use separate interrupts for each timer
sbits : integer := 16; -- scaler bits
ntimers : integer range 1 to 7 := 1; -- number of timers
nbits : integer := 32; -- timer bits
wdog : integer := 0;
ewdogen : integer := 0;
glatch : integer := 0;
gextclk : integer := 0;
gset : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpti : in gptimer_in_type;
gpto : out gptimer_out_type
);
end;
architecture rtl of gptimer is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_GPTIMER, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type timer_reg is record
enable : std_ulogic; -- enable counter
load : std_ulogic; -- load counter
restart : std_ulogic; -- restart counter
irqpen : std_ulogic; -- interrupt pending
irqen : std_ulogic; -- interrupt enable
irq : std_ulogic; -- interrupt pulse
chain : std_ulogic; -- chain with previous timer
value : std_logic_vector(nbits-1 downto 0);
reload : std_logic_vector(nbits-1 downto 0);
latch : std_logic_vector(glatch*(nbits-1) downto 0);
end record;
type timer_reg_vector is array (Natural range <> ) of timer_reg;
constant TBITS : integer := log2x(ntimers+1);
type registers is record
scaler : std_logic_vector(sbits-1 downto 0);
reload : std_logic_vector(sbits-1 downto 0);
tick : std_ulogic;
tsel : integer range 0 to ntimers;
timers : timer_reg_vector(1 to ntimers);
dishlt : std_ulogic;
wdogn : std_ulogic;
wdog : std_ulogic;
wdogdis : std_ulogic;
wdognmi : std_ulogic;
end record;
type registers2 is record
latchsel : std_logic_vector(NAHBIRQ-1 downto 0);
latchen : std_ulogic;
latchdel : std_ulogic;
extclken : std_ulogic;
extclk : std_logic_vector(2 downto 0);
seten : std_ulogic;
setdel : std_ulogic;
end record;
constant NMI : integer := 15;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
function RESVAL_FUNC return registers is
variable vres : registers;
begin
vres.scaler := (others => '1');
vres.reload := (others => '1');
vres.tick := '0';
vres.tsel := 0;
for i in 1 to ntimers loop
vres.timers(i).enable := '0';
vres.timers(i).load := '0';
vres.timers(i).restart := '0';
vres.timers(i).irqpen := '0';
vres.timers(i).irqen := '0';
vres.timers(i).irq := '0';
vres.timers(i).chain := '0';
vres.timers(i).value := (others => '0');
vres.timers(i).reload := (others => '0');
vres.timers(i).latch := (others => '0');
end loop;
if wdog /= 0 then
vres.timers(ntimers).enable := '1'; -- May be overriden by ewdogen
vres.timers(ntimers).load := '1';
vres.timers(ntimers).reload := conv_std_logic_vector(wdog, nbits);
vres.timers(ntimers).irqen := '1';
end if;
vres.dishlt := '0';
vres.wdogn := '1';
vres.wdog := '0';
vres.wdogdis := '0';
vres.wdognmi := '0';
return vres;
end function RESVAL_FUNC;
constant RESVAL : registers := RESVAL_FUNC;
constant RESVAL2 : registers2 := (
latchsel => (others => '0'),
latchen => '0',
latchdel => '0',
extclken => '0',
extclk => (others => '0'),
seten => '0',
setdel => '0');
signal r, rin : registers;
signal r2, rin2 : registers2;
begin
comb : process(rst, r, r2, apbi, gpti)
variable scaler : std_logic_vector(sbits downto 0);
variable readdata, timer1 : std_logic_vector(31 downto 0);
variable res, addin : std_logic_vector(nbits-1 downto 0);
variable v : registers;
variable z : std_ulogic;
variable vtimers : timer_reg_vector(0 to ntimers);
variable xirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable nirq : std_logic_vector(0 to ntimers-1);
variable tick : std_logic_vector(1 to 7);
variable latch : std_ulogic;
variable v2 : registers2;
begin
v := r; v2 := r2; v.tick := '0'; tick := (others => '0'); latch := '0';
vtimers(0) := ('0', '0', '0', '0', '0', '0', '0',
zero32(nbits-1 downto 0), zero32(nbits-1 downto 0),
zero32(glatch*(nbits-1) downto 0));
vtimers(1 to ntimers) := r.timers; xirq := (others => '0');
for i in 1 to ntimers loop
v.timers(i).irq := '0'; v.timers(i).load := '0';
tick(i) := r.timers(i).irq;
end loop;
v.wdog := r.timers(ntimers).irqpen and not r.wdogdis;
v.wdogn := not v.wdog;
-- scaler operation
scaler := ('0' & r.scaler) - 1; -- decrement scaler
if gextclk = 1 then -- optional external timer clock
v2.extclk := r2.extclk(1 downto 0) & gpti.extclk;
end if;
if ((gextclk=0) or (gextclk=1 and r2.extclken='0') or
(gextclk=1 and r2.extclken='1' and r2.extclk(2 downto 1) = "01")) then
if (not gpti.dhalt or r.dishlt) = '1' then -- halt timers in debug mode
if (scaler(sbits) = '1') then
v.scaler := r.reload; v.tick := '1'; -- reload scaler
else v.scaler := scaler(sbits-1 downto 0); end if;
end if;
end if;
-- timer operation
if (r.tick = '1') or (r.tsel /= 0) then
if r.tsel = ntimers then v.tsel := 0;
else v.tsel := r.tsel + 1; end if;
end if;
res := vtimers(r.tsel).value - 1; -- decrement selected timer
if (res(nbits-1) = '1') and ((vtimers(r.tsel).value(nbits-1) = '0'))
then z := '1'; else z := '0'; end if; -- undeflow detect
-- update corresponding register and generate irq
for i in 1 to ntimers-1 loop nirq(i) := r.timers(i).irq; end loop;
nirq(0) := r.timers(ntimers).irq;
for i in 1 to ntimers loop
if i = r.tsel then
if (r.timers(i).enable = '1') and
(((r.timers(i).chain and nirq(i-1)) or not (r.timers(i).chain)) = '1')
then
v.timers(i).irq := z and not r.timers(i).load;
if (v.timers(i).irq and r.timers(i).irqen) = '1' then
v.timers(i).irqpen := '1';
end if;
v.timers(i).value := res;
if (z and not r.timers(i).load) = '1' then
v.timers(i).enable := r.timers(i).restart;
if r.timers(i).restart = '1' then
v.timers(i).value := r.timers(i).reload;
end if;
end if;
end if;
end if;
if r.timers(i).load = '1' then
v.timers(i).value := r.timers(i).reload;
end if;
end loop;
-- timer external set
if gset = 1 then
if NAHBIRQ <= 32 then
for i in NAHBIRQ-1 downto 0 loop
latch := latch or (v2.latchsel(i) and apbi.pirq(i));
end loop;
else
for i in 31 downto 0 loop
latch := latch or (v2.latchsel(i) and apbi.pirq(i));
end loop;
end if;
if (latch='1' and r2.seten='1' and r.tsel = 0) or
(r2.setdel = '1' and r2.seten='1' and r.tsel = 0) then
for i in 1 to ntimers loop
v.timers(i).value := r.timers(i).reload;
end loop;
v2.seten := '0';
v2.setdel := '0';
elsif latch='1' and r2.seten='1' and r.tsel /= 0 then
v2.setdel := '1';
end if;
end if;
if sepirq /= 0 then
for i in 1 to ntimers loop
xirq(i-1+pirq) := r.timers(i).irq and r.timers(i).irqen;
end loop;
else
for i in 1 to ntimers loop
xirq(pirq) := xirq(pirq) or (r.timers(i).irq and r.timers(i).irqen);
end loop;
end if;
if wdog /= 0 then
if (r.wdognmi and r.timers(ntimers).irq and r.timers(ntimers).irqen) = '1' then
xirq(NMI) := '1';
end if;
end if;
-- read registers
readdata := (others => '0');
case apbi.paddr(6 downto 2) is
when "00000" => readdata(sbits-1 downto 0) := r.scaler;
when "00001" => readdata(sbits-1 downto 0) := r.reload;
when "00010" =>
readdata(2 downto 0) := conv_std_logic_vector(ntimers, 3) ;
readdata(7 downto 3) := conv_std_logic_vector(pirq, 5) ;
if (sepirq /= 0) then readdata(8) := '1'; end if;
readdata(9) := r.dishlt;
if gextclk = 1 then readdata(10) := r2.extclken; end if;
if glatch = 1 then readdata(11) := r2.latchen; end if;
if gset = 1 then readdata(12) := r2.seten; end if;
when "00011" =>
if glatch = 1 then
if NAHBIRQ <= 32 then
for i in NAHBIRQ-1 downto 0 loop
readdata(i) := r2.latchsel(i);
end loop;
else
for i in 31 downto 0 loop
readdata(i) := r2.latchsel(i);
end loop;
end if;
end if;
when others =>
for i in 1 to ntimers loop
if conv_integer(apbi.paddr(6 downto 4)) = i then
case apbi.paddr(3 downto 2) is
when "00" => readdata(nbits-1 downto 0) := r.timers(i).value;
when "01" => readdata(nbits-1 downto 0) := r.timers(i).reload;
when "10" =>
if wdog /= 0 and i = ntimers then
readdata(8 downto 7) := r.wdogdis & r.wdognmi;
end if;
readdata(6 downto 0) :=
gpti.dhalt & r.timers(i).chain &
r.timers(i).irqpen & r.timers(i).irqen & r.timers(i).load &
r.timers(i).restart & r.timers(i).enable;
when "11" =>
if glatch = 1 then
readdata(glatch*(nbits-1) downto 0) := r.timers(i).latch;
end if;
when others =>
end case;
end if;
end loop;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(6 downto 2) is
when "00000" => v.scaler := apbi.pwdata(sbits-1 downto 0);
when "00001" => v.reload := apbi.pwdata(sbits-1 downto 0);
v.scaler := apbi.pwdata(sbits-1 downto 0);
when "00010" => v.dishlt := apbi.pwdata(9);
if gextclk = 1 then v2.extclken := apbi.pwdata(10); end if;
if glatch = 1 then v2.latchen := apbi.pwdata(11); end if;
if gset = 1 then v2.seten := apbi.pwdata(12); end if;
when "00011" =>
if glatch=1 then
if NAHBIRQ <= 32 then
for i in NAHBIRQ-1 downto 0 loop
v2.latchsel(i) := apbi.pwdata(i);
end loop;
else
for i in 31 downto 0 loop
v2.latchsel(i) := apbi.pwdata(i);
end loop;
end if;
end if;
when others =>
for i in 1 to ntimers loop
if conv_integer(apbi.paddr(6 downto 4)) = i then
case apbi.paddr(3 downto 2) is
when "00" => v.timers(i).value := apbi.pwdata(nbits-1 downto 0);
when "01" => v.timers(i).reload := apbi.pwdata(nbits-1 downto 0);
when "10" => if wdog /= 0 and i = ntimers then
v.wdogdis := apbi.pwdata(8);
v.wdognmi := apbi.pwdata(7);
end if;
v.timers(i).chain := apbi.pwdata(5);
v.timers(i).irqpen := v.timers(i).irqpen and not apbi.pwdata(4);
v.timers(i).irqen := apbi.pwdata(3);
v.timers(i).load := apbi.pwdata(2);
v.timers(i).restart := apbi.pwdata(1);
v.timers(i).enable := apbi.pwdata(0);
when others =>
end case;
end if;
end loop;
end case;
end if;
-- timer latches
if glatch=1 then
latch := '0';
if NAHBIRQ <= 32 then
for i in NAHBIRQ-1 downto 0 loop
latch := latch or (v2.latchsel(i) and apbi.pirq(i));
end loop;
else
for i in 31 downto 0 loop
latch := latch or (v2.latchsel(i) and apbi.pirq(i));
end loop;
end if;
if ((latch='1' and r2.latchen='1' and r.tsel = 0) or
(r2.latchdel = '1' and r2.latchen='1' and r.tsel = 0)) then
for i in 1 to ntimers loop
v.timers(i).latch := r.timers(i).value(glatch*(nbits-1) downto 0);
end loop;
v2.latchen := '0';
v2.latchdel := '0';
elsif latch='1' and r2.latchen='1' and r.tsel /= 0 then
v2.latchdel := '1';
end if;
end if;
-- reset operation
if (not RESET_ALL) and (rst = '0') then
for i in 1 to ntimers loop
v.timers(i).enable := RESVAL.timers(i).enable;
v.timers(i).irqen := RESVAL.timers(i).irqen;
v.timers(i).irqpen := RESVAL.timers(i).irqpen;
v.timers(i).irq := RESVAL.timers(i).irq;
end loop;
v.scaler := RESVAL.scaler; v.reload := RESVAL.reload;
v.tsel := RESVAL.tsel; v.dishlt := RESVAL.dishlt;
v.timers(ntimers).irq := RESVAL.timers(ntimers).irq;
if (wdog /= 0) then
if ewdogen /= 0 then v.timers(ntimers).enable := gpti.wdogen;
else v.timers(ntimers).enable := RESVAL.timers(ntimers).enable; end if;
v.timers(ntimers).load := RESVAL.timers(ntimers).load;
v.timers(ntimers).reload := RESVAL.timers(ntimers).reload;
v.timers(ntimers).chain := RESVAL.timers(ntimers).chain;
v.timers(ntimers).irqen := RESVAL.timers(ntimers).irqen;
v.timers(ntimers).irqpen := RESVAL.timers(ntimers).irqpen;
v.timers(ntimers).restart := RESVAL.timers(ntimers).restart;
end if;
v.wdogdis := RESVAL.wdogdis; v.wdognmi := RESVAL.wdognmi;
if glatch = 1 then
for i in 1 to ntimers loop v.timers(i).latch := RESVAL.timers(i).latch; end loop;
v2.latchen := RESVAL2.latchen; v2.latchdel := RESVAL2.latchdel;
v2.latchsel := RESVAL2.latchsel;
end if;
if gextclk = 1 then
v2.extclken := RESVAL2.extclken;
v2.extclk := RESVAL2.extclk;
end if;
if gset = 1 then v2.seten := RESVAL2.seten; v2.setdel := RESVAL2.setdel; end if;
end if;
if wdog = 0 then v.wdogdis := '0'; v.wdognmi := '0'; end if;
if glatch = 0 then
for i in 1 to ntimers loop v.timers(i).latch := (others => '0'); end loop;
v2.latchen := '0'; v2.latchdel := '0'; v2.latchsel := (others => '0');
end if;
if gextclk = 0 then v2.extclken := '0'; v2.extclk := (others => '0'); end if;
if gset = 0 then v2.seten := '0'; v2.setdel := '0'; end if;
timer1 := (others => '0'); timer1(nbits-1 downto 0) := r.timers(1).value;
rin <= v; rin2 <= v2;
apbo.prdata <= readdata; -- drive apb read bus
apbo.pirq <= xirq;
apbo.pindex <= pindex;
gpto.tick <= r.tick & tick;
gpto.timer1 <= timer1; -- output timer1 value for debugging
gpto.wdogn <= r.wdogn;
gpto.wdog <= r.wdog;
end process;
apbo.pconfig <= pconfig;
-- registers
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin; r2 <= rin2;
if RESET_ALL and rst = '0' then
r <= RESVAL; r2 <= RESVAL2;
if wdog /= 0 and ewdogen /= 0 then
r.timers(ntimers).enable <= gpti.wdogen;
end if;
end if;
end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("gptimer" & tost(pindex) &
": Timer Unit rev " & tost(REVISION) &
", " & tost(sbits) & "-bit scaler, " & tost(ntimers) &
" " & tost(nbits) & "-bit timers" & ", irq " & tost(pirq));
-- pragma translate_on
end;
| gpl-2.0 | 1d6097afac60996ea9d32b1184616ed9 | 0.556297 | 3.441041 | false | false | false | false |
JimLewis/OSVVM | AlertLogPkg.vhd | 1 | 258,368 | --
-- File Name: AlertLogPkg.vhd
-- Design Unit Name: AlertLogPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis [email protected]
-- Rob Gaddi Highland Technology. Inspired SetAlertLogPrefix / Suffix
--
--
-- Description:
-- Alert handling and log filtering (verbosity control)
-- Alert handling provides a method to count failures, errors, and warnings
-- To accumlate counts, a data structure is created in a shared variable
-- It is of type AlertLogStructPType which is defined in AlertLogBasePkg
-- Log filtering provides verbosity control for logs (display or do not display)
-- AlertLogPkg provides a simplified interface to the shared variable
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 01/2015 2015.01 Initial revision
-- 03/2015 2015.03 Added: AlertIfEqual, AlertIfNotEqual, AlertIfDiff, PathTail,
-- ReportNonZeroAlerts, ReadLogEnables
-- 05/2015 2015.06 Added IncAlertCount, AffirmIf
-- 07/2015 2016.01 Fixed AlertLogID issue with > 32 IDs
-- 02/2016 2016.02 Fixed IsLogEnableType (for PASSED), AffirmIf (to pass AlertLevel)
-- Created LocalInitialize
-- 05/2017 2017.05 AffirmIfEqual, AffirmIfDiff,
-- GetAffirmCount (deprecates GetAffirmCheckCount), IncAffirmCount (deprecates IncAffirmCheckCount),
-- IsAlertEnabled (alias), IsLogEnabled (alias)
-- 04/2018 2018.04 Fix to PathTail. Prep to change AlertLogIDType to a type.
-- 10/2018 2018.10 Added pragmas to allow alerts, logs, and affirmations in RTL code
-- Added local variable to mirror top level ErrorCount and display in simulator
-- Added prefix and suffix
-- Debug printing with number of errors as prefix
-- 01/2020 2020.01 Updated Licenses to Apache
-- 05/2020 2020.05 Added internal variables AlertCount (W, E, F) and ErrorCount (integer)
-- that hold the error state. These can be displayed in wave windows
-- in simulation to track number of errors.
-- Calls to std.env.stop now return ErrorCount
-- Updated calls to check for valid AlertLogIDs
-- Added affirmation count for each level.
-- Turn off reporting with SetAlertLogOptions (PrintAffirmations => TRUE) ;
-- Disabled Alerts now handled in separate bins and reported separately.
-- Turn off reporting with SetAlertLogOptions (PrintDisabledAlerts => TRUE) ;
-- 08/2020 2020.08 Alpha Test Release of Specification Tracking - Changes are provisional and subject to change
-- Added Passed Goals - reported with ReportAlerts and ReportRequirements.
-- Added WriteAlerts - CSV format of the information in ReportAlerts
-- Tests fail when requirements are not met and FailOnRequirementErrors is true (default TRUE).
-- Set using: SetAlertLogOptions(FailOnRequirementErrors => TRUE)
-- Turn on requirements printing in summary and details with PrintRequirements (default FALSE,
-- Turn on requirements printing in summary with PrintIfHaveRequirements (Default TRUE)
-- Added Requirements Bin, ReadSpecification, GetReqID, SetPassedGoal
-- Added AffirmIf("Req ID 1", ...) -- will work even if ID not set by GetReqID or ReadSpecification
-- Added ReportRequirements, WriteRequirements, and ReadRequirements (to merge results of multiple tests)
-- Added WriteTestSummary, ReadTestSummaries, ReportTestSummaries, and WriteTestSummaries.
-- 10/2020 2020.10 Added MetaMatch.
-- Updated AlertIfEqual and AlertIfNotEqual for std_logic family to use MetaMatch
-- 12/2020 2020.12 Added MetaMatch to AffirmIfEqual and AffirmIfNotEqual for std_logic family to use MetaMatch
-- Added AffirmIfEqual for boolean
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2015 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
use work.OsvvmGlobalPkg.all ;
use work.TranscriptPkg.all ;
use work.TextUtilPkg.all ;
library IEEE ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
package AlertLogPkg is
-- type AlertLogIDType is range integer'low to integer'high ; -- next revision
subtype AlertLogIDType is integer ;
type AlertLogIDVectorType is array (integer range <>) of AlertLogIDType ;
type AlertType is (FAILURE, ERROR, WARNING) ; -- NEVER
subtype AlertIndexType is AlertType range FAILURE to WARNING ;
type AlertCountType is array (AlertIndexType) of integer ;
type AlertEnableType is array(AlertIndexType) of boolean ;
type LogType is (ALWAYS, DEBUG, FINAL, INFO, PASSED) ; -- NEVER -- See function IsLogEnableType
subtype LogIndexType is LogType range DEBUG to PASSED ;
type LogEnableType is array (LogIndexType) of boolean ;
constant ALERTLOG_BASE_ID : AlertLogIDType := 0 ; -- Careful as some code may assume this is 0.
constant ALERTLOG_DEFAULT_ID : AlertLogIDType := ALERTLOG_BASE_ID + 1 ;
constant OSVVM_ALERTLOG_ID : AlertLogIDType := ALERTLOG_BASE_ID + 2 ; -- reporting for packages
constant REQUIREMENT_ALERTLOG_ID : AlertLogIDType := ALERTLOG_BASE_ID + 3 ;
-- May have its own ID or OSVVM_ALERTLOG_ID as default - most scoreboards allocate their own ID
constant OSVVM_SCOREBOARD_ALERTLOG_ID : AlertLogIDType := OSVVM_ALERTLOG_ID ;
-- Same as ALERTLOG_DEFAULT_ID
constant ALERT_DEFAULT_ID : AlertLogIDType := ALERTLOG_DEFAULT_ID ;
constant LOG_DEFAULT_ID : AlertLogIDType := ALERTLOG_DEFAULT_ID ;
constant ALERTLOG_ID_NOT_FOUND : AlertLogIDType := -1 ; -- alternately integer'right
constant ALERTLOG_ID_NOT_ASSIGNED : AlertLogIDType := -1 ;
constant MIN_NUM_AL_IDS : AlertLogIDType := 32 ; -- Number IDs initially allocated
alias AlertLogOptionsType is work.OsvvmGlobalPkg.OsvvmOptionsType ;
------------------------------------------------------------
-- Alert always goes to the transcript file
procedure Alert(
AlertLogID : AlertLogIDType ;
Message : string ;
Level : AlertType := ERROR
) ;
procedure Alert( Message : string ; Level : AlertType := ERROR ) ;
------------------------------------------------------------
procedure IncAlertCount( -- A silent form of alert
AlertLogID : AlertLogIDType ;
Level : AlertType := ERROR
) ;
procedure IncAlertCount( Level : AlertType := ERROR ) ;
------------------------------------------------------------
-- Similar to assert, except condition is positive
procedure AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) ;
impure function AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ;
impure function AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ;
------------------------------------------------------------
-- Direct replacement for assert
procedure AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) ;
impure function AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ;
impure function AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ;
------------------------------------------------------------
-- overloading for common functionality
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : time ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : time ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : time ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : time ; Message : string ; Level : AlertType := ERROR ) ;
------------------------------------------------------------
-- Simple Diff for file comparisons
procedure AlertIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) ;
procedure AlertIfDiff (Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) ;
procedure AlertIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) ;
procedure AlertIfDiff (file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) ;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
procedure AffirmIf(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
condition : boolean ;
ReceivedMessage : string ;
ExpectedMessage : string ;
Enable : boolean := FALSE -- override internal enable
) ;
procedure AffirmIf( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) ;
impure function AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean ;
impure function AffirmIf( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean ;
procedure AffirmIf(
AlertLogID : AlertLogIDType ;
condition : boolean ;
Message : string ;
Enable : boolean := FALSE -- override internal enable
) ;
procedure AffirmIf(condition : boolean ; Message : string ; Enable : boolean := FALSE ) ;
impure function AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean ;
impure function AffirmIf( condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean ;
------------------------------------------------------------
procedure AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) ;
procedure AffirmIfNot( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) ;
impure function AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean ;
impure function AffirmIfNot( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean ;
------------------------------------------------------------
procedure AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) ;
procedure AffirmIfNot( condition : boolean ; Message : string ; Enable : boolean := FALSE ) ;
impure function AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean ;
impure function AffirmIfNot( condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean ;
------------------------------------------------------------
procedure AffirmPassed( AlertLogID : AlertLogIDType ; Message : string ; Enable : boolean := FALSE ) ;
procedure AffirmPassed( Message : string ; Enable : boolean := FALSE ) ;
procedure AffirmError( AlertLogID : AlertLogIDType ; Message : string ) ;
procedure AffirmError( Message : string ) ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : boolean ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : std_logic ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : std_logic_vector ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : unsigned ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : signed ; Message : string := "" ; Enable : boolean := FALSE );
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : integer ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : real ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : character ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : string ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : time ; Message : string := "" ; Enable : boolean := FALSE ) ;
-- Without AlertLogID
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : boolean ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : std_logic ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : std_logic_vector ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : unsigned ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : signed ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : integer ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : real ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : character ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : string ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : time ; Message : string := "" ; Enable : boolean := FALSE ) ;
------------------------------------------------------------
procedure AffirmIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfDiff (Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfDiff (file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) ;
------------------------------------------------------------
-- Support for Specification / Requirements Tracking
procedure AffirmIf( RequirementsIDName : string ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) ;
procedure AffirmIf( RequirementsIDName : string ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) ;
------------------------------------------------------------
procedure SetAlertLogJustify (Enable : boolean := TRUE) ;
procedure ReportAlerts ( Name : String ; AlertCount : AlertCountType ) ;
procedure ReportRequirements ;
procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) ;
procedure ReportNonZeroAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) ;
procedure WriteTestSummary ( FileName : string ; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteTestSummaries ( FileName : string ; OpenKind : File_Open_Kind := WRITE_MODE ) ;
procedure ReportTestSummaries ;
procedure WriteAlerts (
FileName : string ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
OpenKind : File_Open_Kind := WRITE_MODE
) ;
procedure WriteRequirements (
FileName : string ;
AlertLogID : AlertLogIDType := REQUIREMENT_ALERTLOG_ID ;
OpenKind : File_Open_Kind := WRITE_MODE
) ;
procedure ReadSpecification (FileName : string ; PassedGoal : integer := -1) ;
procedure ReadRequirements (
FileName : string ;
ThresholdPassed : boolean := FALSE
) ;
procedure ReadTestSummaries (FileName : string) ;
procedure ClearAlerts ;
procedure ClearAlertStopCounts ;
procedure ClearAlertCounts ;
function "ABS" (L : AlertCountType) return AlertCountType ;
function "+" (L, R : AlertCountType) return AlertCountType ;
function "-" (L, R : AlertCountType) return AlertCountType ;
function "-" (R : AlertCountType) return AlertCountType ;
impure function SumAlertCount(AlertCount: AlertCountType) return integer ;
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ;
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer ;
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ;
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer ;
impure function GetDisabledAlertCount return AlertCountType ;
impure function GetDisabledAlertCount return integer ;
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType ;
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return integer ;
------------------------------------------------------------
-- log filtering for verbosity control, optionally has a separate file parameter
procedure Log(
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType := ALWAYS ;
Enable : boolean := FALSE -- override internal enable
) ;
procedure Log( Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE) ;
------------------------------------------------------------
-- Alert Enables
procedure SetAlertEnable(Level : AlertType ; Enable : boolean) ;
procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ;
impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean ;
impure function GetAlertEnable(Level : AlertType) return boolean ;
alias IsAlertEnabled is GetAlertEnable[AlertLogIDType, AlertType return boolean] ;
alias IsAlertEnabled is GetAlertEnable[AlertType return boolean] ;
-- Log Enables
procedure SetLogEnable(Level : LogType ; Enable : boolean) ;
procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ;
impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean ;
impure function GetLogEnable(Level : LogType) return boolean ;
alias IsLogEnabled is GetLogEnable [AlertLogIDType, LogType return boolean] ; -- same as GetLogEnable
alias IsLogEnabled is GetLogEnable [LogType return boolean] ; -- same as GetLogEnable
procedure ReportLogEnables ;
procedure SetAlertLogName(Name : string ) ;
-- synthesis translate_off
impure function GetAlertLogName(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return string ;
-- synthesis translate_on
procedure DeallocateAlertLogStruct ;
procedure InitializeAlertLogStruct ;
impure function FindAlertLogID(Name : string ) return AlertLogIDType ;
impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType ;
impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_ID_NOT_ASSIGNED ; CreateHierarchy : Boolean := TRUE) return AlertLogIDType ;
impure function GetReqID(Name : string ; PassedGoal : integer := -1 ; ParentID : AlertLogIDType := ALERTLOG_ID_NOT_ASSIGNED ; CreateHierarchy : Boolean := TRUE) return AlertLogIDType ;
procedure SetPassedGoal(AlertLogID : AlertLogIDType ; PassedGoal : integer ) ;
impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType ;
procedure SetAlertLogPrefix(AlertLogID : AlertLogIDType; Name : string ) ;
procedure UnSetAlertLogPrefix(AlertLogID : AlertLogIDType) ;
-- synthesis translate_off
impure function GetAlertLogPrefix(AlertLogID : AlertLogIDType) return string ;
-- synthesis translate_on
procedure SetAlertLogSuffix(AlertLogID : AlertLogIDType; Name : string ) ;
procedure UnSetAlertLogSuffix(AlertLogID : AlertLogIDType) ;
-- synthesis translate_off
impure function GetAlertLogSuffix(AlertLogID : AlertLogIDType) return string ;
-- synthesis translate_on
------------------------------------------------------------
-- Accessor Methods
procedure SetGlobalAlertEnable (A : boolean := TRUE) ;
impure function SetGlobalAlertEnable (A : boolean := TRUE) return boolean ;
impure function GetGlobalAlertEnable return boolean ;
procedure IncAffirmCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) ;
impure function GetAffirmCount return natural ;
procedure IncAffirmPassedCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) ;
impure function GetAffirmPassedCount return natural ;
procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) ;
procedure SetAlertStopCount(Level : AlertType ; Count : integer) ;
impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer ;
impure function GetAlertStopCount(Level : AlertType) return integer ;
------------------------------------------------------------
procedure SetAlertLogOptions (
FailOnWarning : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
FailOnDisabledErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
FailOnRequirementErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
ReportHierarchy : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertErrorCount : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogErrorCount : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
PrintPassed : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
PrintAffirmations : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
PrintDisabledAlerts : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
PrintRequirements : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
PrintIfHaveRequirements : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
DefaultPassedGoal : integer := integer'left ;
AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
procedure ReportAlertLogOptions ;
-- synthesis translate_off
impure function GetAlertLogFailOnWarning return AlertLogOptionsType ;
impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType ;
impure function GetAlertLogFailOnRequirementErrors return AlertLogOptionsType ;
impure function GetAlertLogReportHierarchy return AlertLogOptionsType ;
impure function GetAlertLogFoundReportHier return boolean ;
impure function GetAlertLogFoundAlertHier return boolean ;
impure function GetAlertLogWriteAlertErrorCount return AlertLogOptionsType ;
impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType ;
impure function GetAlertLogWriteAlertName return AlertLogOptionsType ;
impure function GetAlertLogWriteAlertTime return AlertLogOptionsType ;
impure function GetAlertLogWriteLogErrorCount return AlertLogOptionsType ;
impure function GetAlertLogWriteLogLevel return AlertLogOptionsType ;
impure function GetAlertLogWriteLogName return AlertLogOptionsType ;
impure function GetAlertLogWriteLogTime return AlertLogOptionsType ;
impure function GetAlertLogPrintPassed return AlertLogOptionsType ;
impure function GetAlertLogPrintAffirmations return AlertLogOptionsType ;
impure function GetAlertLogPrintDisabledAlerts return AlertLogOptionsType ;
impure function GetAlertLogPrintRequirements return AlertLogOptionsType ;
impure function GetAlertLogPrintIfHaveRequirements return AlertLogOptionsType ;
impure function GetAlertLogDefaultPassedGoal return integer ;
impure function GetAlertLogAlertPrefix return string ;
impure function GetAlertLogLogPrefix return string ;
impure function GetAlertLogReportPrefix return string ;
impure function GetAlertLogDoneName return string ;
impure function GetAlertLogPassName return string ;
impure function GetAlertLogFailName return string ;
-- File Reading Utilities
function IsLogEnableType (Name : String) return boolean ;
procedure ReadLogEnables (file AlertLogInitFile : text) ;
procedure ReadLogEnables (FileName : string) ;
-- String Helper Functions -- This should be in a more general string package
function PathTail (A : string) return string ;
------------------------------------------------------------
-- MetaMatch
-- Similar to STD_MATCH, except
-- it returns TRUE for U=U, X=X, Z=Z, and W=W
-- All other values are consistent with STD_MATCH
-- MetaMatch, BooleanTableType, and MetaMatchTable are derivatives
-- of STD_MATCH from IEEE.Numeric_Std copyright by IEEE.
-- Numeric_Std is also released under the Apache License, Version 2.0.
-- Coding Styles were updated to match OSVVM
------------------------------------------------------------
function MetaMatch (l, r : std_ulogic) return boolean ;
function MetaMatch (L, R : std_ulogic_vector) return boolean ;
function MetaMatch (L, R : unresolved_unsigned) return boolean ;
function MetaMatch (L, R : unresolved_signed) return boolean ;
-- synthesis translate_on
-- ------------------------------------------------------------
-- Deprecated
--
-- deprecated
procedure AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) ;
impure function AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean ;
-- deprecated
procedure AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) ;
impure function AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean ;
-- deprecated
procedure AffirmIf(
AlertLogID : AlertLogIDType ;
condition : boolean ;
Message : string ;
LogLevel : LogType ; -- := PASSED
AlertLevel : AlertType := ERROR
) ;
procedure AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; AlertLevel : AlertType ) ;
procedure AffirmIf(condition : boolean ; Message : string ; LogLevel : LogType ; AlertLevel : AlertType := ERROR) ;
procedure AffirmIf(condition : boolean ; Message : string ; AlertLevel : AlertType ) ;
alias IncAffirmCheckCount is IncAffirmCount [AlertLogIDType] ;
alias GetAffirmCheckCount is GetAffirmCount [return natural] ;
alias IsLoggingEnabled is GetLogEnable [AlertLogIDType, LogType return boolean] ; -- same as IsLogEnabled
alias IsLoggingEnabled is GetLogEnable [LogType return boolean] ; -- same as IsLogEnabled
end AlertLogPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
use work.NamePkg.all ;
package body AlertLogPkg is
-- synthesis translate_off
-- instead of justify(to_upper(to_string())), just look up the upper case, left justified values
type AlertNameType is array(AlertType) of string(1 to 7) ;
constant ALERT_NAME : AlertNameType := (WARNING => "WARNING", ERROR => "ERROR ", FAILURE => "FAILURE") ; -- , NEVER => "NEVER "
type LogNameType is array(LogType) of string(1 to 7) ;
constant LOG_NAME : LogNameType := (DEBUG => "DEBUG ", FINAL => "FINAL ", INFO => "INFO ", ALWAYS => "ALWAYS ", PASSED => "PASSED ") ; -- , NEVER => "NEVER "
------------------------------------------------------------
-- Package Local
function LeftJustify(A : String; Amount : integer) return string is
------------------------------------------------------------
constant Spaces : string(1 to maximum(1, Amount)) := (others => ' ') ;
begin
if A'length >= Amount then
return A ;
else
return A & Spaces(1 to Amount - A'length) ;
end if ;
end function LeftJustify ;
type AlertLogStructPType is protected
------------------------------------------------------------
procedure alert (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
message : string ;
level : AlertType := ERROR
) ;
------------------------------------------------------------
procedure IncAlertCount ( AlertLogID : AlertLogIDType ; level : AlertType := ERROR ) ;
procedure SetJustify (
Enable : boolean := TRUE ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID
) ;
procedure ReportAlerts ( Name : string ; AlertCount : AlertCountType ) ;
procedure ReportRequirements ;
procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (0,0,0) ; ReportAll : boolean := TRUE ) ;
procedure WriteTestSummary ( FileName : string ; OpenKind : File_Open_Kind ) ;
procedure WriteTestSummaries ( FileName : string ; OpenKind : File_Open_Kind ) ;
procedure ReportTestSummaries ;
procedure WriteAlerts (
FileName : string ;
AlertLogID : AlertLogIDType ;
OpenKind : File_Open_Kind
) ;
procedure WriteRequirements (
FileName : string ;
AlertLogID : AlertLogIDType ;
OpenKind : File_Open_Kind
) ;
procedure ReadSpecification (FileName : string ; PassedGoal : integer ) ;
procedure ReadRequirements (
FileName : string ;
ThresholdPassed : boolean ;
TestSummary : boolean
) ;
procedure ClearAlerts ;
procedure ClearAlertStopCounts ;
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ;
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ;
impure function GetDisabledAlertCount return AlertCountType ;
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType ;
------------------------------------------------------------
procedure log (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType := ALWAYS ;
Enable : boolean := FALSE -- override internal enable
) ;
------------------------------------------------------------
-- FILE IO Controls
-- procedure SetTranscriptEnable (A : boolean := TRUE) ;
-- impure function IsTranscriptEnabled return boolean ;
-- procedure MirrorTranscript (A : boolean := TRUE) ;
-- impure function IsTranscriptMirrored return boolean ;
------------------------------------------------------------
------------------------------------------------------------
-- AlertLog Structure Creation and Interaction Methods
------------------------------------------------------------
procedure SetAlertLogName(Name : string ) ;
procedure SetNumAlertLogIDs (NewNumAlertLogIDs : AlertLogIDType) ;
impure function FindAlertLogID(Name : string ) return AlertLogIDType ;
impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType ;
impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType ; CreateHierarchy : Boolean) return AlertLogIDType ;
impure function GetReqID(Name : string ; PassedGoal : integer ; ParentID : AlertLogIDType ; CreateHierarchy : Boolean) return AlertLogIDType ;
procedure SetPassedGoal(AlertLogID : AlertLogIDType ; PassedGoal : integer ) ;
impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType ;
procedure Initialize(NewNumAlertLogIDs : AlertLogIDType := MIN_NUM_AL_IDS) ;
procedure Deallocate ;
procedure SetAlertLogPrefix(AlertLogID : AlertLogIDType; Name : string ) ;
procedure UnSetAlertLogPrefix(AlertLogID : AlertLogIDType) ;
impure function GetAlertLogPrefix(AlertLogID : AlertLogIDType) return string ;
procedure SetAlertLogSuffix(AlertLogID : AlertLogIDType; Name : string ) ;
procedure UnSetAlertLogSuffix(AlertLogID : AlertLogIDType) ;
impure function GetAlertLogSuffix(AlertLogID : AlertLogIDType) return string ;
------------------------------------------------------------
------------------------------------------------------------
-- Accessor Methods
------------------------------------------------------------
procedure SetGlobalAlertEnable (A : boolean := TRUE) ;
impure function GetAlertLogName(AlertLogID : AlertLogIDType) return string ;
impure function GetGlobalAlertEnable return boolean ;
procedure IncAffirmCount(AlertLogID : AlertLogIDType) ;
impure function GetAffirmCount return natural ;
procedure IncAffirmPassedCount(AlertLogID : AlertLogIDType) ;
impure function GetAffirmPassedCount return natural ;
procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) ;
impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer ;
procedure SetAlertEnable(Level : AlertType ; Enable : boolean) ;
procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ;
impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean ;
procedure SetLogEnable(Level : LogType ; Enable : boolean) ;
procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ;
impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean ;
procedure ReportLogEnables ;
------------------------------------------------------------
-- Reporting Accessor
procedure SetAlertLogOptions (
FailOnWarning : AlertLogOptionsType ;
FailOnDisabledErrors : AlertLogOptionsType ;
FailOnRequirementErrors : AlertLogOptionsType ;
ReportHierarchy : AlertLogOptionsType ;
WriteAlertErrorCount : AlertLogOptionsType ;
WriteAlertLevel : AlertLogOptionsType ;
WriteAlertName : AlertLogOptionsType ;
WriteAlertTime : AlertLogOptionsType ;
WriteLogErrorCount : AlertLogOptionsType ;
WriteLogLevel : AlertLogOptionsType ;
WriteLogName : AlertLogOptionsType ;
WriteLogTime : AlertLogOptionsType ;
PrintPassed : AlertLogOptionsType ;
PrintAffirmations : AlertLogOptionsType ;
PrintDisabledAlerts : AlertLogOptionsType ;
PrintRequirements : AlertLogOptionsType ;
PrintIfHaveRequirements : AlertLogOptionsType ;
DefaultPassedGoal : integer ;
AlertPrefix : string ;
LogPrefix : string ;
ReportPrefix : string ;
DoneName : string ;
PassName : string ;
FailName : string
) ;
procedure ReportAlertLogOptions ;
impure function GetAlertLogFailOnWarning return AlertLogOptionsType ;
impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType ;
impure function GetAlertLogFailOnRequirementErrors return AlertLogOptionsType ;
impure function GetAlertLogReportHierarchy return AlertLogOptionsType ;
impure function GetAlertLogFoundReportHier return boolean ;
impure function GetAlertLogFoundAlertHier return boolean ;
impure function GetAlertLogWriteAlertErrorCount return AlertLogOptionsType ;
impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType ;
impure function GetAlertLogWriteAlertName return AlertLogOptionsType ;
impure function GetAlertLogWriteAlertTime return AlertLogOptionsType ;
impure function GetAlertLogWriteLogErrorCount return AlertLogOptionsType ;
impure function GetAlertLogWriteLogLevel return AlertLogOptionsType ;
impure function GetAlertLogWriteLogName return AlertLogOptionsType ;
impure function GetAlertLogWriteLogTime return AlertLogOptionsType ;
impure function GetAlertLogPrintPassed return AlertLogOptionsType ;
impure function GetAlertLogPrintAffirmations return AlertLogOptionsType ;
impure function GetAlertLogPrintDisabledAlerts return AlertLogOptionsType ;
impure function GetAlertLogPrintRequirements return AlertLogOptionsType ;
impure function GetAlertLogPrintIfHaveRequirements return AlertLogOptionsType ;
impure function GetAlertLogDefaultPassedGoal return integer ;
impure function GetAlertLogAlertPrefix return string ;
impure function GetAlertLogLogPrefix return string ;
impure function GetAlertLogReportPrefix return string ;
impure function GetAlertLogDoneName return string ;
impure function GetAlertLogPassName return string ;
impure function GetAlertLogFailName return string ;
end protected AlertLogStructPType ;
--- ///////////////////////////////////////////////////////////////////////////
type AlertLogStructPType is protected body
variable GlobalAlertEnabledVar : boolean := TRUE ; -- Allows turn off and on
variable AffirmCheckCountVar : natural := 0 ;
variable PassedCountVar : natural := 0 ;
variable ErrorCount : integer := 0 ;
variable AlertCount : AlertCountType := (0, 0, 0) ;
------------------------------------------------------------
type AlertLogRecType is record
------------------------------------------------------------
Name : Line ;
NameLower : Line ;
Prefix : Line ;
Suffix : Line ;
ParentID : AlertLogIDType ;
ParentIDSet : Boolean ;
SiblingID : AlertLogIDType ;
ChildID : AlertLogIDType ;
ChildIDLast : AlertLogIDType ;
AlertCount : AlertCountType ;
DisabledAlertCount : AlertCountType ;
AffirmCount : Integer ;
PassedCount : Integer ;
PassedGoal : Integer ;
PassedGoalSet : Boolean ;
AlertStopCount : AlertCountType ;
AlertEnabled : AlertEnableType ;
LogEnabled : LogEnableType ;
-- Used only by ReadTestSummaries
TotalErrors : integer ;
AffirmPassedCount : integer ;
-- IsRequirment : boolean ;
end record AlertLogRecType ;
------------------------------------------------------------
-- Basis for AlertLog Data Structure
variable NumAlertLogIDsVar : AlertLogIDType := 0 ; -- defined by initialize
variable NumAllocatedAlertLogIDsVar : AlertLogIDType := 0 ;
type AlertLogRecPtrType is access AlertLogRecType ;
type AlertLogArrayType is array (AlertLogIDType range <>) of AlertLogRecPtrType ;
type AlertLogArrayPtrType is access AlertLogArrayType ;
variable AlertLogPtr : AlertLogArrayPtrType ;
------------------------------------------------------------
-- Report formatting settings, with defaults
variable PrintPassedVar : boolean := TRUE ;
variable PrintAffirmationsVar : boolean := FALSE ;
variable PrintDisabledAlertsVar : boolean := FALSE ;
variable PrintRequirementsVar : boolean := FALSE ;
variable HasRequirementsVar : boolean := FALSE ;
variable PrintIfHaveRequirementsVar : boolean := TRUE ;
variable DefaultPassedGoalVar : integer := 1 ;
variable FailOnWarningVar : boolean := TRUE ;
variable FailOnDisabledErrorsVar : boolean := TRUE ;
variable FailOnRequirementErrorsVar : boolean := TRUE ;
variable ReportHierarchyVar : boolean := TRUE ;
variable FoundReportHierVar : boolean := FALSE ;
variable FoundAlertHierVar : boolean := FALSE ;
variable WriteAlertErrorCountVar : boolean := FALSE ;
variable WriteAlertLevelVar : boolean := TRUE ;
variable WriteAlertNameVar : boolean := TRUE ;
variable WriteAlertTimeVar : boolean := TRUE ;
variable WriteLogErrorCountVar : boolean := FALSE ;
variable WriteLogLevelVar : boolean := TRUE ;
variable WriteLogNameVar : boolean := TRUE ;
variable WriteLogTimeVar : boolean := TRUE ;
variable AlertPrefixVar : NamePType ;
variable LogPrefixVar : NamePType ;
variable ReportPrefixVar : NamePType ;
variable DoneNameVar : NamePType ;
variable PassNameVar : NamePType ;
variable FailNameVar : NamePType ;
variable AlertLogJustifyAmountVar : integer := 0 ;
variable ReportJustifyAmountVar : integer := 0 ;
------------------------------------------------------------
-- PT Local
impure function VerifyID(
AlertLogID : AlertLogIDType ;
LOWEST_ID : AlertLogIDType := ALERTLOG_BASE_ID
) return AlertLogIDType is
------------------------------------------------------------
begin
if AlertLogID < LOWEST_ID or AlertLogID > NumAlertLogIDsVar then
Alert("Invalid AlertLogID") ;
return LOWEST_ID ;
else
return AlertLogID ;
end if ;
end function VerifyID ;
------------------------------------------------------------
procedure IncAffirmCount(AlertLogID : AlertLogIDType) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
if GlobalAlertEnabledVar then
localAlertLogID := VerifyID(AlertLogID) ;
AlertLogPtr(localAlertLogID).AffirmCount := AlertLogPtr(localAlertLogID).AffirmCount + 1 ;
AffirmCheckCountVar := AffirmCheckCountVar + 1 ;
end if ;
end procedure IncAffirmCount ;
------------------------------------------------------------
impure function GetAffirmCount return natural is
------------------------------------------------------------
begin
return AffirmCheckCountVar ;
end function GetAffirmCount ;
------------------------------------------------------------
procedure IncAffirmPassedCount(AlertLogID : AlertLogIDType) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
if GlobalAlertEnabledVar then
localAlertLogID := VerifyID(AlertLogID) ;
AlertLogPtr(localAlertLogID).PassedCount := AlertLogPtr(localAlertLogID).PassedCount + 1 ;
PassedCountVar := PassedCountVar + 1 ;
AlertLogPtr(localAlertLogID).AffirmCount := AlertLogPtr(localAlertLogID).AffirmCount + 1 ;
AffirmCheckCountVar := AffirmCheckCountVar + 1 ;
end if ;
end procedure IncAffirmPassedCount ;
------------------------------------------------------------
impure function GetAffirmPassedCount return natural is
------------------------------------------------------------
begin
return PassedCountVar ;
end function GetAffirmPassedCount ;
------------------------------------------------------------
-- PT Local
procedure IncrementAlertCount(
------------------------------------------------------------
constant AlertLogID : in AlertLogIDType ;
constant Level : in AlertType ;
variable StopDueToCount : inout boolean ;
variable IncrementByAmount : in integer := 1
) is
begin
if AlertLogPtr(AlertLogID).AlertEnabled(Level) then
AlertLogPtr(AlertLogID).AlertCount(Level) := AlertLogPtr(AlertLogID).AlertCount(Level) + IncrementByAmount ;
-- Exceeded Stop Count at this level?
if AlertLogPtr(AlertLogID).AlertCount(Level) >= AlertLogPtr(AlertLogID).AlertStopCount(Level) then
StopDueToCount := TRUE ;
end if ;
-- Propagate counts to parent(s) -- Ascend Hierarchy
if AlertLogID /= ALERTLOG_BASE_ID then
IncrementAlertCount(AlertLogPtr(AlertLogID).ParentID, Level, StopDueToCount, IncrementByAmount) ;
end if ;
else
-- Disabled, increment disabled count
AlertLogPtr(AlertLogID).DisabledAlertCount(Level) := AlertLogPtr(AlertLogID).DisabledAlertCount(Level) + IncrementByAmount ;
end if ;
end procedure IncrementAlertCount ;
------------------------------------------------------------
procedure alert (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
message : string ;
level : AlertType := ERROR
) is
variable buf : Line ;
constant AlertPrefix : string := AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ;
variable StopDueToCount : boolean := FALSE ;
variable localAlertLogID : AlertLogIDType ;
begin
-- Only write and count when GlobalAlertEnabledVar is enabled
if GlobalAlertEnabledVar then
localAlertLogID := VerifyID(AlertLogID) ;
-- Write when Alert is Enabled
if AlertLogPtr(localAlertLogID).AlertEnabled(Level) then
-- Print %% Alert (nominally)
write(buf, AlertPrefix) ;
-- Debug Mode
if WriteAlertErrorCountVar then
write(buf, ' ' & justify(to_string(ErrorCount + 1), RIGHT, 2));
end if ;
-- Level Name, when enabled (default)
if WriteAlertLevelVar then
write(buf, " " & ALERT_NAME(Level)) ; -- uses constant lookup
end if ;
-- AlertLog Name
if FoundAlertHierVar and WriteAlertNameVar then
write(buf, " in " & LeftJustify(AlertLogPtr(localAlertLogID).Name.all & ',', AlertLogJustifyAmountVar) ) ;
end if ;
-- Prefix
if AlertLogPtr(localAlertLogID).Prefix /= NULL then
write(buf, ' ' & AlertLogPtr(localAlertLogID).Prefix.all) ;
end if ;
-- Message
write(buf, " " & Message) ;
-- Suffix
if AlertLogPtr(localAlertLogID).Suffix /= NULL then
write(buf, ' ' & AlertLogPtr(localAlertLogID).Suffix.all) ;
end if ;
-- Time
if WriteAlertTimeVar then
write(buf, " at " & to_string(NOW, 1 ns)) ;
end if ;
writeline(buf) ;
end if ;
-- Always Count
IncrementAlertCount(localAlertLogID, Level, StopDueToCount) ;
AlertCount := AlertLogPtr(ALERTLOG_BASE_ID).AlertCount;
ErrorCount := SumAlertCount(AlertCount);
if StopDueToCount then
write(buf, LF & AlertPrefix & " Stop Count on " & ALERT_NAME(Level) & " reached") ;
if FoundAlertHierVar then
write(buf, " in " & AlertLogPtr(localAlertLogID).Name.all) ;
end if ;
write(buf, " at " & to_string(NOW, 1 ns) & " ") ;
writeline(buf) ;
ReportAlerts(ReportAll => TRUE) ;
std.env.stop(ErrorCount) ;
end if ;
end if ;
end procedure alert ;
------------------------------------------------------------
procedure IncAlertCount (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
level : AlertType := ERROR
) is
variable buf : Line ;
constant AlertPrefix : string := AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ;
variable StopDueToCount : boolean := FALSE ;
variable localAlertLogID : AlertLogIDType ;
begin
if GlobalAlertEnabledVar then
localAlertLogID := VerifyID(AlertLogID) ;
IncrementAlertCount(localAlertLogID, Level, StopDueToCount) ;
AlertCount := AlertLogPtr(ALERTLOG_BASE_ID).AlertCount;
ErrorCount := SumAlertCount(AlertCount);
if StopDueToCount then
write(buf, LF & AlertPrefix & " Stop Count on " & ALERT_NAME(Level) & " reached") ;
if FoundAlertHierVar then
write(buf, " in " & AlertLogPtr(localAlertLogID).Name.all) ;
end if ;
write(buf, " at " & to_string(NOW, 1 ns) & " ") ;
writeline(buf) ;
ReportAlerts(ReportAll => TRUE) ;
std.env.stop(ErrorCount) ;
end if ;
end if ;
end procedure IncAlertCount ;
------------------------------------------------------------
-- PT Local
impure function CalcJustify (AlertLogID : AlertLogIDType ; CurrentLength : integer ; IndentAmount : integer) return integer_vector is
------------------------------------------------------------
variable ResultValues, LowerLevelValues : integer_vector(1 to 2) ; -- 1 = Max, 2 = Indented
variable CurID : AlertLogIDType ;
begin
ResultValues(1) := CurrentLength + 1 ; -- AlertLogJustifyAmountVar
ResultValues(2) := CurrentLength + IndentAmount ; -- ReportJustifyAmountVar
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
if CurID = REQUIREMENT_ALERTLOG_ID and HasRequirementsVar = FALSE then
CurID := AlertLogPtr(CurID).SiblingID ;
next ;
end if ;
LowerLevelValues := CalcJustify(CurID, AlertLogPtr(CurID).Name'length, IndentAmount + 2) ;
ResultValues(1) := maximum(ResultValues(1), LowerLevelValues(1)) ;
ResultValues(2) := maximum(ResultValues(2), LowerLevelValues(2)) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
return ResultValues ;
end function CalcJustify ;
------------------------------------------------------------
procedure SetJustify (
------------------------------------------------------------
Enable : boolean := TRUE ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID
) is
begin
if Enable then
(AlertLogJustifyAmountVar, ReportJustifyAmountVar) := CalcJustify(AlertLogID, 0, 0) ;
else
AlertLogJustifyAmountVar := 0 ;
ReportJustifyAmountVar := 0 ;
end if;
end procedure SetJustify ;
------------------------------------------------------------
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).AlertCount ;
end function GetAlertCount ;
------------------------------------------------------------
-- Local
impure function RemoveNonFailingWarnings(A : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Count : AlertCountType ;
begin
Count := A ;
if not FailOnWarningVar then
Count(WARNING) := 0 ;
end if ;
return Count ;
end function RemoveNonFailingWarnings ;
------------------------------------------------------------
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
variable Count : AlertCountType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return RemoveNonFailingWarnings( AlertLogPtr(localAlertLogID).AlertCount ) ;
end function GetEnabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount return AlertCountType is
------------------------------------------------------------
variable Count : AlertCountType := (others => 0) ;
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
Count := Count + AlertLogPtr(i).DisabledAlertCount ;
--? Should excluded warnings get counted as disabled errors?
--? if not FailOnWarningVar then
--? Count(WARNING) := Count(WARNING) + AlertLogPtr(i).AlertCount(WARNING) ;
--? end if ;
end loop ;
return Count ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
impure function LocalGetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType is
------------------------------------------------------------
variable Count : AlertCountType ;
variable CurID : AlertLogIDType ;
begin
Count := AlertLogPtr(AlertLogID).DisabledAlertCount ;
-- Find Children of this ID
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
Count := Count + LocalGetDisabledAlertCount(CurID) ; -- Recursively descend into children
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
return Count ;
end function LocalGetDisabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return LocalGetDisabledAlertCount(localAlertLogID) ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
-- Local
procedure GetRequirementsCount(
AlertLogID : AlertLogIDType;
RequirementsPassed : out integer ;
RequirementsGoal : out integer
) is
------------------------------------------------------------
variable ChildRequirementsPassed, ChildRequirementsGoal : integer ;
variable CurID : AlertLogIDType ;
begin
RequirementsPassed := 0 ;
RequirementsGoal := 0 ;
if AlertLogPtr(AlertLogID).PassedGoal > 0 then
RequirementsGoal := 1 ;
if AlertLogPtr(AlertLogID).PassedCount >= AlertLogPtr(AlertLogID).PassedGoal then
RequirementsPassed := 1 ;
end if ;
end if ;
-- Find Children of this ID
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
GetRequirementsCount(CurID, ChildRequirementsPassed, ChildRequirementsGoal) ;
RequirementsPassed := RequirementsPassed + ChildRequirementsPassed ;
RequirementsGoal := RequirementsGoal + ChildRequirementsGoal ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure GetRequirementsCount ;
------------------------------------------------------------
-- Local
procedure GetPassedAffirmCount(
AlertLogID : AlertLogIDType;
PassedCount : out integer ;
AffirmCount : out integer
) is
------------------------------------------------------------
variable ChildPassedCount, ChildAffirmCount : integer ;
variable CurID : AlertLogIDType ;
begin
PassedCount := AlertLogPtr(AlertLogID).PassedCount ;
AffirmCount := AlertLogPtr(AlertLogID).AffirmCount ;
-- Find Children of this ID
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
GetPassedAffirmCount(CurID, ChildPassedCount, ChildAffirmCount) ;
PassedCount := PassedCount + ChildPassedCount ;
AffirmCount := AffirmCount + ChildAffirmCount ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure GetPassedAffirmCount ;
------------------------------------------------------------
-- PT Local
procedure PrintTopAlerts (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Name : string ;
ExternalErrors : AlertCountType ;
variable HasDisabledAlerts : inout Boolean ;
variable TestFailed : inout Boolean
) is
constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt ) ;
constant DoneName : string := ResolveOsvvmDoneName(DoneNameVar.GetOpt ) ;
constant PassName : string := ResolveOsvvmPassName(PassNameVar.GetOpt ) ;
constant FailName : string := ResolveOsvvmFailName(FailNameVar.GetOpt ) ;
variable buf : line ;
variable TotalErrors : integer ;
variable TotalAlertErrors, TotalDisabledAlertErrors : integer ;
variable TotalRequirementsPassed, TotalRequirementsGoal, TotalRequirementErrors : integer ;
variable AlertCountVar, DisabledAlertCount : AlertCountType ;
variable PassedCount, AffirmCheckCount : integer ;
begin
AlertCountVar := AlertLogPtr(AlertLogID).AlertCount + ExternalErrors ;
TotalAlertErrors := SumAlertCount( RemoveNonFailingWarnings(AlertCountVar)) ;
DisabledAlertCount := GetDisabledAlertCount(AlertLogID) ;
TotalDisabledAlertErrors := SumAlertCount( RemoveNonFailingWarnings(DisabledAlertCount) ) ;
HasDisabledAlerts := TotalDisabledAlertErrors /= 0 ;
GetRequirementsCount(AlertLogID, TotalRequirementsPassed, TotalRequirementsGoal) ;
TotalRequirementErrors := TotalRequirementsGoal - TotalRequirementsPassed ;
TotalErrors := TotalAlertErrors ;
if FailOnDisabledErrorsVar then
TotalErrors := TotalErrors + TotalDisabledAlertErrors ;
end if ;
if FailOnRequirementErrorsVar then
TotalErrors := TotalErrors + TotalRequirementErrors ;
end if ;
TestFailed := TotalErrors /= 0 ;
GetPassedAffirmCount(AlertLogID, PassedCount, AffirmCheckCount) ;
if not TestFailed then
write(buf, ReportPrefix & DoneName & " " & PassName & " " & Name) ; -- PASSED
else
write(buf, ReportPrefix & DoneName & " " & FailName & " " & Name) ; -- FAILED
end if ;
--? Also print when warnings exist and are hidden by FailOnWarningVar=FALSE
if TestFailed then
write(buf, " Total Error(s) = " & to_string(TotalErrors) ) ;
write(buf, " Failures: " & to_string(AlertCountVar(FAILURE)) ) ;
write(buf, " Errors: " & to_string(AlertCountVar(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertCountVar(WARNING) ) ) ;
end if ;
if HasDisabledAlerts or PrintDisabledAlertsVar then -- print if exist or enabled
write(buf, " Total Disabled Error(s) = " & to_string(TotalDisabledAlertErrors)) ;
end if ;
if (HasDisabledAlerts and FailOnDisabledErrorsVar) or PrintDisabledAlertsVar then -- print if enabled
write(buf, " Failures: " & to_string(DisabledAlertCount(FAILURE)) ) ;
write(buf, " Errors: " & to_string(DisabledAlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(DisabledAlertCount(WARNING) ) ) ;
end if ;
if PrintPassedVar or (AffirmCheckCount /= 0) or PrintAffirmationsVar then -- Print if passed or printing affirmations
write(buf, " Passed: " & to_string(PassedCount)) ;
end if;
if (AffirmCheckCount /= 0) or PrintAffirmationsVar then
write(buf, " Affirmations Checked: " & to_string(AffirmCheckCount)) ;
end if ;
if PrintRequirementsVar or
(PrintIfHaveRequirementsVar and HasRequirementsVar) or
(FailOnRequirementErrorsVar and TotalRequirementErrors /= 0)
then
write(buf, " Requirements Passed: " & to_string(TotalRequirementsPassed) &
" of " & to_string(TotalRequirementsGoal) ) ;
end if ;
write(buf, " at " & to_string(NOW, 1 ns)) ;
WriteLine(buf) ;
end procedure PrintTopAlerts ;
------------------------------------------------------------
-- PT Local
procedure PrintOneChild(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Prefix : string ;
IndentAmount : integer ;
ReportAll : boolean ;
HasDisabledErrors : boolean
) is
variable buf : line ;
alias CurID : AlertLogIDType is AlertLogID ;
begin
if
ReportAll or -- ReportAlerts
-- ReportNonZeroAlerts and (AlertCount or (FailOn and DisabledAlertCount))
(SumAlertCount(AlertLogPtr(CurID).AlertCount) > 0) or
(FailOnDisabledErrorsVar and (SumAlertCount(AlertLogPtr(CurID).DisabledAlertCount) > 0)) or
(FailOnRequirementErrorsVar and (AlertLogPtr(CurID).PassedCount < AlertLogPtr(CurID).PassedGoal))
then
write(buf, Prefix & " " & LeftJustify(AlertLogPtr(CurID).Name.all, ReportJustifyAmountVar - IndentAmount)) ;
write(buf, " Failures: " & to_string(AlertLogPtr(CurID).AlertCount(FAILURE) ) ) ;
write(buf, " Errors: " & to_string(AlertLogPtr(CurID).AlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertLogPtr(CurID).AlertCount(WARNING) ) ) ;
if (HasDisabledErrors and FailOnDisabledErrorsVar) or PrintDisabledAlertsVar then
write(buf, " Disabled Failures: " & to_string(AlertLogPtr(CurID).DisabledAlertCount(FAILURE) ) ) ;
write(buf, " Errors: " & to_string(AlertLogPtr(CurID).DisabledAlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertLogPtr(CurID).DisabledAlertCount(WARNING) ) ) ;
end if ;
if PrintPassedVar or PrintRequirementsVar then
write(buf, " Passed: " & to_string(AlertLogPtr(CurID).PassedCount)) ;
end if;
if PrintRequirementsVar then
write(buf, " of " & to_string(AlertLogPtr(CurID).PassedGoal) ) ;
end if ;
if PrintAffirmationsVar then
write(buf, " Affirmations: " & to_string(AlertLogPtr(CurID).AffirmCount ) ) ;
end if ;
WriteLine(buf) ;
end if ;
end procedure PrintOneChild ;
------------------------------------------------------------
-- PT Local
procedure IterateAndPrintChildren(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Prefix : string ;
IndentAmount : integer ;
ReportAll : boolean ;
HasDisabledErrors : boolean
) is
variable buf : line ;
variable CurID : AlertLogIDType ;
begin
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
-- Don't print requirements if there no requirements
if CurID = REQUIREMENT_ALERTLOG_ID and HasRequirementsVar = FALSE then
CurID := AlertLogPtr(CurID).SiblingID ;
next ;
end if ;
PrintOneChild(
AlertLogID => CurID,
Prefix => Prefix,
IndentAmount => IndentAmount,
ReportAll => ReportAll,
HasDisabledErrors => HasDisabledErrors
) ;
IterateAndPrintChildren(
AlertLogID => CurID,
Prefix => Prefix & " ",
IndentAmount => IndentAmount + 2,
ReportAll => ReportAll,
HasDisabledErrors => HasDisabledErrors
) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure IterateAndPrintChildren ;
------------------------------------------------------------
procedure ReportAlerts (
Name : string := OSVVM_STRING_INIT_PARM_DETECT ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
ExternalErrors : AlertCountType := (0,0,0) ;
ReportAll : boolean := TRUE
) is
------------------------------------------------------------
variable TestFailed, HasDisabledErrors : boolean ;
constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) ;
variable TurnedOnJustify : boolean := FALSE ;
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
if ReportJustifyAmountVar <= 0 then
TurnedOnJustify := TRUE ;
SetJustify ;
end if ;
if IsOsvvmStringSet(Name) then
PrintTopAlerts (
AlertLogID => localAlertLogID,
Name => Name,
ExternalErrors => ExternalErrors,
HasDisabledAlerts => HasDisabledErrors,
TestFailed => TestFailed
) ;
else
PrintTopAlerts (
AlertLogID => localAlertLogID,
Name => AlertLogPtr(localAlertLogID).Name.all,
ExternalErrors => ExternalErrors,
HasDisabledAlerts => HasDisabledErrors,
TestFailed => TestFailed
) ;
end if ;
--Print Hierarchy when enabled and test failed
if (FoundReportHierVar and ReportHierarchyVar) and TestFailed then
-- (NumErrors /= 0 or (NumDisabledErrors /=0 and FailOnDisabledErrorsVar)) then
IterateAndPrintChildren(
AlertLogID => localAlertLogID,
Prefix => ReportPrefix & " ",
IndentAmount => 2,
ReportAll => ReportAll,
HasDisabledErrors => HasDisabledErrors -- NumDisabledErrors /= 0
) ;
end if ;
if TurnedOnJustify then
-- Turn it back off
SetJustify(FALSE) ;
end if ;
end procedure ReportAlerts ;
------------------------------------------------------------
procedure ReportRequirements is
------------------------------------------------------------
variable TestFailed, HasDisabledErrors : boolean ;
constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) ;
variable TurnedOnJustify : boolean := FALSE ;
variable SavedPrintRequirementsVar : boolean ;
begin
SavedPrintRequirementsVar := PrintRequirementsVar ;
PrintRequirementsVar := TRUE ;
if ReportJustifyAmountVar <= 0 then
TurnedOnJustify := TRUE ;
SetJustify ;
end if ;
PrintTopAlerts (
AlertLogID => ALERTLOG_BASE_ID,
Name => AlertLogPtr(ALERTLOG_BASE_ID).Name.all,
ExternalErrors => (0,0,0),
HasDisabledAlerts => HasDisabledErrors,
TestFailed => TestFailed
) ;
IterateAndPrintChildren(
AlertLogID => REQUIREMENT_ALERTLOG_ID,
Prefix => ReportPrefix & " ",
IndentAmount => 2,
ReportAll => TRUE,
HasDisabledErrors => HasDisabledErrors -- NumDisabledErrors /= 0
) ;
if TurnedOnJustify then
-- Turn it back off
SetJustify(FALSE) ;
end if ;
PrintRequirementsVar := SavedPrintRequirementsVar ;
end procedure ReportRequirements ;
------------------------------------------------------------
procedure ReportAlerts ( Name : string ; AlertCount : AlertCountType ) is
------------------------------------------------------------
constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt ) ;
constant DoneName : string := ResolveOsvvmDoneName(DoneNameVar.GetOpt ) ;
constant PassName : string := ResolveOsvvmPassName(PassNameVar.GetOpt ) ;
constant FailName : string := ResolveOsvvmFailName(FailNameVar.GetOpt ) ;
variable buf : line ;
variable NumErrors : integer ;
begin
NumErrors := SumAlertCount(AlertCount) ;
if NumErrors = 0 then
-- Passed
write(buf, ReportPrefix & DoneName & " " & PassName & " " & Name) ;
write(buf, " at " & to_string(NOW, 1 ns)) ;
WriteLine(buf) ;
else
-- Failed
write(buf, ReportPrefix & DoneName & " " & FailName & " "& Name) ;
write(buf, " Total Error(s) = " & to_string(NumErrors) ) ;
write(buf, " Failures: " & to_string(AlertCount(FAILURE)) ) ;
write(buf, " Errors: " & to_string(AlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertCount(WARNING) ) ) ;
write(buf, " at " & to_string(NOW, 1 ns)) ;
writeLine(buf) ;
end if ;
end procedure ReportAlerts ;
------------------------------------------------------------
-- PT Local
impure function IsRequirement(AlertLogID : AlertLogIDType) return boolean is
------------------------------------------------------------
begin
if AlertLogID = REQUIREMENT_ALERTLOG_ID then
return TRUE ;
elsif AlertLogID <= ALERTLOG_BASE_ID then
return FALSE ;
else
return IsRequirement(AlertLogPtr(AlertLogID).ParentID) ;
end if ;
end function IsRequirement ;
------------------------------------------------------------
-- pt local
procedure WriteOneTestSummary (
------------------------------------------------------------
file TestFile : text ;
AlertLogID : AlertLogIDType ;
RequirementsGoal : integer ;
RequirementsPassed : integer ;
TotalErrors : integer ;
AlertCount : AlertCountType ;
AffirmCount : integer ;
PassedCount : integer ;
Delimiter : string
) is
variable buf : line ;
begin
-- Should disabled errors be included here?
-- In the previous step, we counted DisabledErrors as a regular error if FailOnDisabledErrorsVar (default TRUE)
write(buf, AlertLogPtr(AlertLogID).Name.all & Delimiter) ;
write(buf, to_string( RequirementsGoal ) & Delimiter) ;
write(buf, to_string( RequirementsPassed ) & Delimiter) ;
write(buf, to_string( TotalErrors ) & Delimiter) ;
write(buf, to_string( AlertCount(FAILURE) ) & Delimiter) ;
write(buf, to_string( AlertCount(ERROR) ) & Delimiter) ;
write(buf, to_string( AlertCount(WARNING) ) & Delimiter) ;
write(buf, to_string( AffirmCount ) & Delimiter) ;
write(buf, to_string( PassedCount )) ;
WriteLine(TestFile, buf) ;
end procedure WriteOneTestSummary ;
------------------------------------------------------------
procedure WriteTestSummary (file TestFile : text) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
variable TotalErrors : integer ;
variable TotalAlertErrors, TotalDisabledAlertErrors : integer ;
variable TotalRequirementsPassed, TotalRequirementsGoal : integer ;
variable TotalRequirementErrors : integer ;
variable TotalAlertCount, DisabledAlertCount : AlertCountType ;
constant AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
variable PassedCount, AffirmCount : integer ;
constant DELIMITER : string := "," ;
begin
TotalAlertCount := AlertLogPtr(AlertLogID).AlertCount ;
TotalAlertErrors := SumAlertCount( RemoveNonFailingWarnings(TotalAlertCount)) ;
DisabledAlertCount := GetDisabledAlertCount(AlertLogID) ;
TotalDisabledAlertErrors := SumAlertCount( RemoveNonFailingWarnings(DisabledAlertCount) ) ;
GetRequirementsCount(AlertLogID, TotalRequirementsPassed, TotalRequirementsGoal) ;
TotalRequirementErrors := TotalRequirementsGoal - TotalRequirementsPassed ;
TotalErrors := TotalAlertErrors ;
if FailOnDisabledErrorsVar then
TotalErrors := TotalErrors + TotalDisabledAlertErrors ;
TotalAlertCount := TotalAlertCount + DisabledAlertCount ;
end if ;
if FailOnRequirementErrorsVar then
TotalErrors := TotalErrors + TotalRequirementErrors ;
end if ;
GetPassedAffirmCount(AlertLogID, PassedCount, AffirmCount) ;
WriteOneTestSummary(
TestFile => TestFile,
AlertLogID => AlertLogID,
RequirementsGoal => TotalRequirementsGoal,
RequirementsPassed => TotalRequirementsPassed,
TotalErrors => TotalErrors,
AlertCount => TotalAlertCount,
AffirmCount => AffirmCount,
PassedCount => PassedCount,
Delimiter => DELIMITER
) ;
end procedure WriteTestSummary ;
------------------------------------------------------------
procedure WriteTestSummary (
------------------------------------------------------------
FileName : string ;
OpenKind : File_Open_Kind
) is
-- Format: Action Count min1 max1 min2 max2
file TestFile : text open OpenKind is FileName ;
begin
WriteTestSummary(TestFile => TestFile) ;
end procedure WriteTestSummary ;
------------------------------------------------------------
procedure WriteTestSummaries ( -- PT Local
------------------------------------------------------------
file TestFile : text ;
AlertLogID : AlertLogIDType
) is
variable CurID : AlertLogIDType ;
variable TotalErrors, RequirementsGoal, RequirementsPassed : integer ;
begin
-- Descend from WriteRequirements
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
TotalErrors := AlertLogPtr(CurID).TotalErrors ;
RequirementsGoal := AlertLogPtr(CurID).PassedGoal ;
RequirementsPassed := AlertLogPtr(CurID).PassedCount ;
if AlertLogPtr(CurID).AffirmCount <= 0 and FailOnRequirementErrorsVar and
(RequirementsGoal > RequirementsPassed) then
-- Add errors for tests that did not run.
TotalErrors := RequirementsGoal - RequirementsPassed ;
end if ;
WriteOneTestSummary(
TestFile => TestFile,
AlertLogID => CurID,
RequirementsGoal => RequirementsGoal,
RequirementsPassed => RequirementsPassed,
TotalErrors => TotalErrors,
AlertCount => AlertLogPtr(CurID).AlertCount,
AffirmCount => AlertLogPtr(CurID).AffirmCount,
PassedCount => AlertLogPtr(CurID).AffirmPassedCount,
Delimiter => ","
) ;
WriteTestSummaries(TestFile, CurID) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure WriteTestSummaries ;
------------------------------------------------------------
procedure WriteTestSummaries (
------------------------------------------------------------
FileName : string ;
OpenKind : File_Open_Kind
) is
-- Format: Action Count min1 max1 min2 max2
file TestFile : text open OpenKind is FileName ;
begin
WriteTestSummaries(
TestFile => TestFile,
AlertLogID => REQUIREMENT_ALERTLOG_ID
) ;
end procedure WriteTestSummaries ;
------------------------------------------------------------
procedure ReportOneTestSummary ( -- PT Local
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
RequirementsGoal : integer ;
RequirementsPassed : integer ;
TotalErrors : integer ;
AlertCount : AlertCountType ;
AffirmCount : integer ;
PassedCount : integer ;
Delimiter : string
) is
variable buf : line ;
constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt ) ;
constant PassName : string := ResolveOsvvmPassName(PassNameVar.GetOpt ) ;
constant FailName : string := ResolveOsvvmFailName(FailNameVar.GetOpt ) ;
begin
write(buf, ReportPrefix & " ") ;
if (AffirmCount > 0) and (TotalErrors = 0) then
write(buf, PassName) ;
elsif TotalErrors > 0 then
write(buf, FailName) ;
else
write(buf, string'("??????")) ;
end if ;
write(buf, " " & LeftJustify(AlertLogPtr(AlertLogID).Name.all, ReportJustifyAmountVar)) ;
write(buf, " Total Error(s) = " & to_string(TotalErrors) ) ;
write(buf, " Failures: " & to_string(AlertCount(FAILURE) ) ) ;
write(buf, " Errors: " & to_string(AlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertCount(WARNING) ) ) ;
write(buf, " Affirmations Passed: " & to_string(PassedCount) &
" of " & to_string(AffirmCount)) ;
write(buf, " Requirements Passed: " & to_string(RequirementsPassed) &
" of " & to_string(RequirementsGoal) ) ;
WriteLine(buf) ;
end procedure ReportOneTestSummary ;
------------------------------------------------------------
procedure ReportTestSummaries ( -- PT Local
------------------------------------------------------------
AlertLogID : AlertLogIDType
) is
variable CurID : AlertLogIDType ;
variable TotalErrors, RequirementsGoal, RequirementsPassed : integer ;
begin
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
TotalErrors := AlertLogPtr(CurID).TotalErrors ;
RequirementsGoal := AlertLogPtr(CurID).PassedGoal ;
RequirementsPassed := AlertLogPtr(CurID).PassedCount ;
if AlertLogPtr(CurID).AffirmCount <= 0 and FailOnRequirementErrorsVar and
(RequirementsGoal > RequirementsPassed) then
-- Add errors for tests that did not run.
TotalErrors := RequirementsGoal - RequirementsPassed ;
end if ;
ReportOneTestSummary(
AlertLogID => CurID,
RequirementsGoal => RequirementsGoal,
RequirementsPassed => RequirementsPassed,
TotalErrors => TotalErrors,
AlertCount => AlertLogPtr(CurID).AlertCount,
AffirmCount => AlertLogPtr(CurID).AffirmCount,
PassedCount => AlertLogPtr(CurID).AffirmPassedCount,
Delimiter => ","
) ;
ReportTestSummaries(
AlertLogID => CurID
) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure ReportTestSummaries ;
------------------------------------------------------------
procedure ReportTestSummaries is
------------------------------------------------------------
variable IgnoredValue, OldReportJustifyAmount : integer ;
begin
OldReportJustifyAmount := ReportJustifyAmountVar ;
(IgnoredValue, ReportJustifyAmountVar) := CalcJustify(REQUIREMENT_ALERTLOG_ID, 0, 0) ;
ReportTestSummaries(AlertLogID => REQUIREMENT_ALERTLOG_ID) ;
ReportJustifyAmountVar := OldReportJustifyAmount ;
end procedure ReportTestSummaries ;
------------------------------------------------------------
-- pt local
procedure WriteAlerts ( -- pt local
file AlertsFile : text ;
AlertLogID : AlertLogIDType
) is
------------------------------------------------------------
-- Format: Name, PassedGoal, #Passed, #TotalErrors, FAILURE, ERROR, WARNING, Affirmations
variable buf : line ;
variable AlertCountVar : AlertCountType ;
constant DELIMITER : character := ',' ;
variable CurID : AlertLogIDType ;
begin
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
write(buf, AlertLogPtr(CurID).Name.all) ;
write(buf, DELIMITER & to_string(AlertLogPtr(CurID).PassedGoal)) ;
-- Handling for PassedCount > PassedGoal done in ReadRequirements
write(buf, DELIMITER & to_string(AlertLogPtr(CurID).PassedCount)) ;
AlertCountVar := AlertLogPtr(CurID).AlertCount ;
if FailOnDisabledErrorsVar then
AlertCountVar := AlertCountVar + AlertLogPtr(CurID).DisabledAlertCount ;
end if;
-- TotalErrors
write(buf, DELIMITER & to_string( SumAlertCount(RemoveNonFailingWarnings(AlertCountVar)))) ;
write(buf, DELIMITER & to_string( AlertCountVar(FAILURE) )) ;
write(buf, DELIMITER & to_string( AlertCountVar(ERROR) )) ;
write(buf, DELIMITER & to_string( AlertCountVar(WARNING) )) ;
write(buf, DELIMITER & to_string( AlertLogPtr(CurID).AffirmCount )) ;
-- write(buf, DELIMITER & to_string(AlertLogPtr(CurID).PassedCount)) ; -- redundancy intentional, for reading WriteTestSummary
WriteLine(AlertsFile, buf) ;
WriteAlerts(AlertsFile, CurID) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure WriteAlerts ;
------------------------------------------------------------
procedure WriteRequirements (
------------------------------------------------------------
FileName : string ;
AlertLogID : AlertLogIDType ;
OpenKind : File_Open_Kind
) is
-- Format: Action Count min1 max1 min2 max2
file RequirementsFile : text open OpenKind is FileName ;
variable LocalAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
WriteTestSummary(RequirementsFile) ;
if IsRequirement(localAlertLogID) then
WriteAlerts(RequirementsFile, localAlertLogID) ;
else
Alert("WriteRequirements: Called without a Requirement") ;
WriteAlerts(RequirementsFile, REQUIREMENT_ALERTLOG_ID) ;
end if ;
end procedure WriteRequirements ;
------------------------------------------------------------
procedure WriteAlerts (
------------------------------------------------------------
FileName : string ;
AlertLogID : AlertLogIDType ;
OpenKind : File_Open_Kind
) is
-- Format: Action Count min1 max1 min2 max2
file AlertsFile : text open OpenKind is FileName ;
variable LocalAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
WriteTestSummary(AlertsFile) ;
WriteAlerts(AlertsFile, localAlertLogID) ;
end procedure WriteAlerts ;
------------------------------------------------------------
procedure ReadSpecification (file SpecificationFile : text ; PassedGoalIn : integer ) is -- PT Local
------------------------------------------------------------
variable buf,Name,Description : line ;
variable ReadValid : boolean ;
variable Empty : boolean ;
variable MultiLineComment : boolean := FALSE ;
variable PassedGoal : integer ;
variable PassedGoalSet : boolean ;
variable Char : character ;
constant DELIMITER : character := ',' ;
variable AlertLogID : AlertLogIDType ;
begin
HasRequirementsVar := TRUE ;
-- Format: Spec Name, [Spec Description = "",] [Requirement Goal = 0]
ReadFileLoop : while not EndFile(SpecificationFile) loop
ReadLoop : loop
ReadLine(SpecificationFile, buf) ;
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next ReadFileLoop when Empty ;
-- defaults
PassedGoal := DefaultPassedGoalVar ;
PassedGoalSet := FALSE ;
-- Read Name and Remove delimiter
ReadUntilDelimiterOrEOL(buf, Name, DELIMITER, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadSpecification: Failed while reading Name", FAILURE) ;
-- If rest of line is blank or comment, then skip it.
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
exit ReadLoop when Empty ;
-- Optional: Read Description
ReadUntilDelimiterOrEOL(buf, Description, DELIMITER, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadSpecification: Failed while reading Description", FAILURE) ;
if IsNumber(Description.all) then
read(Description, PassedGoal, ReadValid) ;
deallocate(Description) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadSpecification: Failed while reading PassedGoal (while skipping Description)", FAILURE) ;
PassedGoalSet := TRUE ;
else
-- If rest of line is blank or comment, then skip it.
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
exit ReadLoop when Empty ;
-- Read PassedGoal
read(buf, PassedGoal, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadSpecification: Failed while reading PassedGoal", FAILURE) ;
PassedGoalSet := TRUE ;
end if ;
exit ReadLoop ;
end loop ReadLoop ;
-- AlertLogID := GetReqID(Name.all) ; -- For new items, sets DefaultPassedGoalVar and PassedGoalSet = FALSE.
AlertLogID := GetReqID(Name => Name.all, PassedGoal => -1, ParentID=> ALERTLOG_ID_NOT_ASSIGNED, CreateHierarchy => TRUE) ;
deallocate(Name) ;
deallocate(Description) ; -- not used
-- Implementation 1: Just put the values in
-- If Override values specified, then use them.
if PassedGoalIn >= 0 then
PassedGoal := PassedGoalIn ;
PassedGoalSet := TRUE ;
end if ;
if PassedGoalSet then
-- Is there a goal to update?
if AlertLogPtr(AlertLogID).PassedGoalSet then
-- Merge Old and New
AlertLogPtr(AlertLogID).PassedGoal := maximum(PassedGoal, AlertLogPtr(AlertLogID).PassedGoal) ;
else
-- No Old, Just use New
AlertLogPtr(AlertLogID).PassedGoal := PassedGoal ;
end if ;
AlertLogPtr(AlertLogID).PassedGoalSet := TRUE ;
end if ;
end loop ReadFileLoop ;
end procedure ReadSpecification ;
------------------------------------------------------------
procedure ReadSpecification (FileName : string ; PassedGoal : integer ) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
file SpecificationFile : text open READ_MODE is FileName ;
begin
ReadSpecification(SpecificationFile, PassedGoal) ;
end procedure ReadSpecification ;
------------------------------------------------------------
-- PT Local
procedure ReadRequirements ( -- PT Local
file RequirementsFile : text ;
ThresholdPassed : boolean ;
TestSummary : boolean
) is
------------------------------------------------------------
constant DELIMITER : character := ',' ;
variable buf,Name : line ;
variable ReadValid : boolean ;
variable Empty : boolean ;
variable MultiLineComment : boolean := FALSE ;
variable StopDueToCount : boolean := FALSE ;
-- variable ReadFailed : boolean := TRUE ;
variable Found : boolean ;
variable ReqPassedGoal : integer ;
variable ReqPassedCount : integer ;
variable TotalErrorCount : integer ;
variable AlertCount : AlertCountType ;
variable AffirmCount : integer ;
variable AffirmPassedCount : integer ;
variable AlertLogID : AlertLogIDType ;
begin
if not TestSummary then
-- For requirements, skip the first line that has the test summary
ReadLine(RequirementsFile, buf) ;
end if ;
ReadFileLoop : while not EndFile(RequirementsFile) loop
ReadLoop : loop
ReadLine(RequirementsFile, buf) ;
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next ReadFileLoop when Empty ;
-- defaults
-- ReadFailed := TRUE ;
ReqPassedGoal := 0 ;
ReqPassedCount := 0 ;
TotalErrorCount := 0 ;
AlertCount := (0, 0, 0) ;
AffirmCount := 0 ;
AffirmPassedCount := 0 ;
-- Read Name. Remove delimiter
ReadUntilDelimiterOrEOL(buf, Name, DELIMITER, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading Name", FAILURE) ;
-- Read ReqPassedGoal
read(buf, ReqPassedGoal, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading PassedGoal", FAILURE) ;
FindDelimiter(buf, DELIMITER, Found) ;
exit ReadFileLoop when AlertIf(OSVVM_ALERTLOG_ID, not Found,
"AlertLogPkg.ReadRequirements: Failed after reading PassedGoal", FAILURE) ;
-- Read ReqPassedCount
read(buf, ReqPassedCount, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading PassedCount", FAILURE) ;
AffirmPassedCount := ReqPassedGoal ;
FindDelimiter(buf, DELIMITER, Found) ;
exit ReadFileLoop when AlertIf(OSVVM_ALERTLOG_ID, not Found,
"AlertLogPkg.ReadRequirements: Failed after reading PassedCount", FAILURE) ;
-- Read TotalErrorCount
read(buf, TotalErrorCount, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading TotalErrorCount", FAILURE) ;
AlertCount := (0, TotalErrorCount, 0) ; -- Default
FindDelimiter(buf, DELIMITER, Found) ;
exit ReadFileLoop when AlertIf(OSVVM_ALERTLOG_ID, not Found,
"AlertLogPkg.ReadRequirements: Failed after reading PassedCount", FAILURE) ;
-- Read AlertCount
for i in AlertType'left to AlertType'right loop
read(buf, AlertCount(i), ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading " &
"AlertCount(" & to_string(i) & ")", FAILURE) ;
FindDelimiter(buf, DELIMITER, Found) ;
exit ReadFileLoop when AlertIf(OSVVM_ALERTLOG_ID, not Found,
"AlertLogPkg.ReadRequirements: Failed after reading " &
"AlertCount(" & to_string(i) & ")", FAILURE) ;
end loop ;
-- Read AffirmCount
read(buf, AffirmCount, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading AffirmCount", FAILURE) ;
if TestSummary then
FindDelimiter(buf, DELIMITER, Found) ;
exit ReadFileLoop when AlertIf(OSVVM_ALERTLOG_ID, not Found,
"AlertLogPkg.ReadRequirements: Failed after reading AffirmCount", FAILURE) ;
-- Read AffirmPassedCount
read(buf, AffirmPassedCount, ReadValid) ;
if not ReadValid then
AffirmPassedCount := ReqPassedGoal ;
Alert(OSVVM_ALERTLOG_ID, "AlertLogPkg.ReadRequirements: Failed while reading AffirmPassedCount", FAILURE) ;
exit ReadFileLoop ;
end if ;
end if ;
exit ReadLoop ;
end loop ReadLoop ;
-- AlertLogID := GetReqID(Name.all) ;
AlertLogID := GetReqID(Name => Name.all, PassedGoal => -1, ParentID=> ALERTLOG_ID_NOT_ASSIGNED, CreateHierarchy => TRUE) ; --! GHDL
deallocate(Name) ;
-- if Merge then
-- Passed Goal
if AlertLogPtr(AlertLogID).PassedGoalSet then
AlertLogPtr(AlertLogID).PassedGoal := maximum(AlertLogPtr(AlertLogID).PassedGoal, ReqPassedGoal) ;
else
AlertLogPtr(AlertLogID).PassedGoal := ReqPassedGoal ;
end if ;
-- Requirements Passed Count
if ThresholdPassed then
ReqPassedCount := minimum(ReqPassedCount, ReqPassedGoal) ;
end if ;
AlertLogPtr(AlertLogID).PassedCount := AlertLogPtr(AlertLogID).PassedCount + ReqPassedCount ;
AlertLogPtr(AlertLogID).TotalErrors := AlertLogPtr(AlertLogID).TotalErrors + TotalErrorCount ;
-- AlertCount
IncrementAlertCount(AlertLogID, FAILURE, StopDueToCount, AlertCount(FAILURE)) ;
IncrementAlertCount(AlertLogID, ERROR, StopDueToCount, AlertCount(ERROR)) ;
IncrementAlertCount(AlertLogID, WARNING, StopDueToCount, AlertCount(WARNING)) ;
-- AffirmCount
AlertLogPtr(AlertLogID).AffirmCount := AlertLogPtr(AlertLogID).AffirmCount + AffirmCount ;
AlertLogPtr(AlertLogID).AffirmPassedCount := AlertLogPtr(AlertLogID).AffirmPassedCount + AffirmPassedCount ;
-- else
-- AlertLogPtr(AlertLogID).PassedGoal := ReqPassedGoal ;
-- AlertLogPtr(AlertLogID).PassedCount := ReqPassedCount ;
--
-- IncrementAlertCount(AlertLogID, FAILURE, StopDueToCount, AlertCount(FAILURE)) ;
-- IncrementAlertCount(AlertLogID, ERROR, StopDueToCount, AlertCount(ERROR)) ;
-- IncrementAlertCount(AlertLogID, WARNING, StopDueToCount, AlertCount(WARNING)) ;
--
-- AlertLogPtr(AlertLogID).AffirmCount := ReqPassedCount + TotalErrorCount ;
-- end if;
AlertLogPtr(AlertLogID).PassedGoalSet := TRUE ;
end loop ReadFileLoop ;
end procedure ReadRequirements ;
------------------------------------------------------------
procedure ReadRequirements (
FileName : string ;
ThresholdPassed : boolean ;
TestSummary : boolean
) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
file RequirementsFile : text open READ_MODE is FileName ;
begin
ReadRequirements(RequirementsFile, ThresholdPassed, TestSummary) ;
end procedure ReadRequirements ;
------------------------------------------------------------
procedure ClearAlerts is
------------------------------------------------------------
begin
AffirmCheckCountVar := 0 ;
PassedCountVar := 0 ;
AlertCount := (0, 0, 0) ;
ErrorCount := 0 ;
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
AlertLogPtr(i).AlertCount := (0, 0, 0) ;
AlertLogPtr(i).DisabledAlertCount := (0, 0, 0) ;
AlertLogPtr(i).AffirmCount := 0 ;
AlertLogPtr(i).PassedCount := 0 ;
AlertLogPtr(i).PassedGoal := 0 ;
end loop ;
end procedure ClearAlerts ;
------------------------------------------------------------
procedure ClearAlertStopCounts is
------------------------------------------------------------
begin
AlertLogPtr(ALERTLOG_BASE_ID).AlertStopCount := (FAILURE => 0, ERROR => integer'right, WARNING => integer'right) ;
for i in ALERTLOG_BASE_ID + 1 to NumAlertLogIDsVar loop
AlertLogPtr(i).AlertStopCount := (FAILURE => integer'right, ERROR => integer'right, WARNING => integer'right) ;
end loop ;
end procedure ClearAlertStopCounts ;
------------------------------------------------------------
-- PT Local
procedure LocalLog (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType
) is
variable buf : line ;
constant LogPrefix : string := LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX) ;
begin
-- Print %% log (nominally)
write(buf, LogPrefix) ;
-- Debug Mode
if WriteLogErrorCountVar then
if WriteAlertErrorCountVar then
if ErrorCount > 0 then
write(buf, ' ' & justify(to_string(ErrorCount), RIGHT, 2)) ;
else
swrite(buf, " ") ;
end if ;
end if ;
end if ;
-- Level Name, when enabled (default)
if WriteLogLevelVar then
write(buf, " " & LOG_NAME(Level) ) ;
end if ;
-- AlertLog Name
if FoundAlertHierVar and WriteLogNameVar then
write(buf, " in " & LeftJustify(AlertLogPtr(AlertLogID).Name.all & ',', AlertLogJustifyAmountVar) ) ;
end if ;
-- Prefix
if AlertLogPtr(AlertLogID).Prefix /= NULL then
write(buf, ' ' & AlertLogPtr(AlertLogID).Prefix.all) ;
end if ;
-- Message
write(buf, " " & Message) ;
-- Suffix
if AlertLogPtr(AlertLogID).Suffix /= NULL then
write(buf, ' ' & AlertLogPtr(AlertLogID).Suffix.all) ;
end if ;
-- Time
if WriteLogTimeVar then
write(buf, " at " & to_string(NOW, 1 ns)) ;
end if ;
writeline(buf) ;
end procedure LocalLog ;
------------------------------------------------------------
procedure log (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType := ALWAYS ;
Enable : boolean := FALSE -- override internal enable
) is
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
if Level = ALWAYS or Enable then
LocalLog(localAlertLogID, Message, Level) ;
elsif AlertLogPtr(localAlertLogID).LogEnabled(Level) then
LocalLog(localAlertLogID, Message, Level) ;
end if ;
if Level = PASSED then
IncAffirmPassedCount(AlertLogID) ; -- count the passed and affirmation
end if ;
end procedure log ;
------------------------------------------------------------
------------------------------------------------------------
-- AlertLog Structure Creation and Interaction Methods
------------------------------------------------------------
procedure SetAlertLogName(Name : string ) is
------------------------------------------------------------
begin
Deallocate(AlertLogPtr(ALERTLOG_BASE_ID).Name) ;
AlertLogPtr(ALERTLOG_BASE_ID).Name := new string'(Name) ;
AlertLogPtr(ALERTLOG_BASE_ID).NameLower := new string'(to_lower(NAME)) ;
end procedure SetAlertLogName ;
------------------------------------------------------------
impure function GetAlertLogName(AlertLogID : AlertLogIDType) return string is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).Name.all ;
end function GetAlertLogName ;
------------------------------------------------------------
-- PT Local
procedure DeQueueID(AlertLogID : AlertLogIDType) is
------------------------------------------------------------
variable ParentID, CurID : AlertLogIDType ;
begin
ParentID := AlertLogPtr(AlertLogID).ParentID ;
CurID := AlertLogPtr(ParentID).ChildID ;
-- Found at top of list
if AlertLogPtr(ParentID).ChildID = AlertLogID then
AlertLogPtr(ParentID).ChildID := AlertLogPtr(AlertLogID).SiblingID ;
else
-- Find among Siblings
loop
if AlertLogPtr(CurID).SiblingID = AlertLogID then
AlertLogPtr(CurID).SiblingID := AlertLogPtr(AlertLogID).SiblingID ;
exit ;
end if ;
if AlertLogPtr(CurID).SiblingID <= ALERTLOG_BASE_ID then
Alert("DeQueueID: AlertLogID not found") ;
exit ;
end if ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end if ;
end procedure DeQueueID ;
------------------------------------------------------------
-- PT Local
procedure EnQueueID(AlertLogID, ParentID : AlertLogIDType ; ParentIDSet : boolean := TRUE) is
------------------------------------------------------------
variable CurID : AlertLogIDType ;
begin
AlertLogPtr(AlertLogID).ParentIDSet := ParentIDSet ;
AlertLogPtr(AlertLogID).ParentID := ParentID ;
AlertLogPtr(AlertLogID).SiblingID := ALERTLOG_ID_NOT_ASSIGNED ;
if AlertLogPtr(ParentID).ChildID < ALERTLOG_BASE_ID then
AlertLogPtr(ParentID).ChildID := AlertLogID ;
else
CurID := AlertLogPtr(ParentID).ChildIDLast ;
AlertLogPtr(CurID).SiblingID := AlertLogID ;
end if ;
AlertLogPtr(ParentID).ChildIDLast := AlertLogID ;
end procedure EnQueueID ;
------------------------------------------------------------
-- PT Local
procedure NewAlertLogRec(AlertLogID : AlertLogIDType ; Name : string ; ParentID : AlertLogIDType) is
------------------------------------------------------------
variable AlertEnabled : AlertEnableType ;
variable AlertStopCount : AlertCountType ;
variable LogEnabled : LogEnableType ;
begin
AlertLogPtr(AlertLogID) := new AlertLogRecType ;
if AlertLogID = ALERTLOG_BASE_ID then
AlertEnabled := (TRUE, TRUE, TRUE) ;
LogEnabled := (others => FALSE) ;
AlertStopCount := (FAILURE => 0, ERROR => integer'right, WARNING => integer'right) ;
EnQueueID(AlertLogID, ALERTLOG_BASE_ID, TRUE) ;
else
if ParentID < ALERTLOG_BASE_ID then
AlertEnabled := AlertLogPtr(ALERTLOG_BASE_ID).AlertEnabled ;
LogEnabled := AlertLogPtr(ALERTLOG_BASE_ID).LogEnabled ;
EnQueueID(AlertLogID, ALERTLOG_BASE_ID, FALSE) ;
else
AlertEnabled := AlertLogPtr(ParentID).AlertEnabled ;
LogEnabled := AlertLogPtr(ParentID).LogEnabled ;
EnQueueID(AlertLogID, ParentID, TRUE) ;
end if ;
AlertStopCount := (FAILURE => integer'right, ERROR => integer'right, WARNING => integer'right) ;
end if ;
AlertLogPtr(AlertLogID).Name := new string'(NAME) ;
AlertLogPtr(AlertLogID).NameLower := new string'(to_lower(NAME)) ;
AlertLogPtr(AlertLogID).AlertCount := (0, 0, 0) ;
AlertLogPtr(AlertLogID).DisabledAlertCount := (0, 0, 0) ;
AlertLogPtr(AlertLogID).AffirmCount := 0 ;
AlertLogPtr(AlertLogID).PassedCount := 0 ;
AlertLogPtr(AlertLogID).PassedGoal := 0 ;
AlertLogPtr(AlertLogID).AlertEnabled := AlertEnabled ;
AlertLogPtr(AlertLogID).AlertStopCount := AlertStopCount ;
AlertLogPtr(AlertLogID).LogEnabled := LogEnabled ;
-- Set ChildID, ChildIDLast, SiblingID to ALERTLOG_ID_NOT_ASSIGNED
AlertLogPtr(AlertLogID).SiblingID := ALERTLOG_ID_NOT_ASSIGNED ;
AlertLogPtr(AlertLogID).ChildID := ALERTLOG_ID_NOT_ASSIGNED ;
AlertLogPtr(AlertLogID).ChildIDLast := ALERTLOG_ID_NOT_ASSIGNED ;
AlertLogPtr(AlertLogID).TotalErrors := 0 ;
AlertLogPtr(AlertLogID).AffirmPassedCount := 0 ;
end procedure NewAlertLogRec ;
------------------------------------------------------------
-- PT Local
-- Construct initial data structure
procedure LocalInitialize(NewNumAlertLogIDs : AlertLogIDType := MIN_NUM_AL_IDS) is
------------------------------------------------------------
begin
if NumAllocatedAlertLogIDsVar /= 0 then
Alert(ALERT_DEFAULT_ID, "AlertLogPkg: Initialize, data structure already initialized", FAILURE) ;
return ;
end if ;
-- Initialize Pointer
AlertLogPtr := new AlertLogArrayType(ALERTLOG_BASE_ID to ALERTLOG_BASE_ID + NewNumAlertLogIDs) ;
NumAllocatedAlertLogIDsVar := NewNumAlertLogIDs ;
-- Create BASE AlertLogID (if it differs from DEFAULT
NewAlertLogRec(ALERTLOG_BASE_ID, "AlertLogTop", ALERTLOG_BASE_ID) ;
-- Create DEFAULT AlertLogID
NewAlertLogRec(ALERT_DEFAULT_ID, "Default", ALERTLOG_BASE_ID) ;
NumAlertLogIDsVar := ALERT_DEFAULT_ID ;
-- Create OSVVM AlertLogID (if it differs from DEFAULT
if OSVVM_ALERTLOG_ID /= ALERT_DEFAULT_ID then
NewAlertLogRec(OSVVM_ALERTLOG_ID, "OSVVM", ALERTLOG_BASE_ID) ;
NumAlertLogIDsVar := NumAlertLogIDsVar + 1 ;
end if ;
if REQUIREMENT_ALERTLOG_ID /= ALERT_DEFAULT_ID then
NewAlertLogRec(REQUIREMENT_ALERTLOG_ID, "Requirements", ALERTLOG_BASE_ID) ;
NumAlertLogIDsVar := NumAlertLogIDsVar + 1 ;
end if ;
if OSVVM_SCOREBOARD_ALERTLOG_ID /= OSVVM_ALERTLOG_ID then
NewAlertLogRec(OSVVM_SCOREBOARD_ALERTLOG_ID, "OSVVM Scoreboard", ALERTLOG_BASE_ID) ;
NumAlertLogIDsVar := NumAlertLogIDsVar + 1 ;
end if ;
end procedure LocalInitialize ;
------------------------------------------------------------
-- Construct initial data structure
procedure Initialize(NewNumAlertLogIDs : AlertLogIDType := MIN_NUM_AL_IDS) is
------------------------------------------------------------
begin
LocalInitialize(NewNumAlertLogIDs) ;
end procedure Initialize ;
------------------------------------------------------------
-- PT Local
-- Constructs initial data structure using constant below
impure function LocalInitialize return boolean is
------------------------------------------------------------
begin
LocalInitialize(MIN_NUM_AL_IDS) ;
return TRUE ;
end function LocalInitialize ;
constant CONSTRUCT_ALERT_DATA_STRUCTURE : boolean := LocalInitialize ;
------------------------------------------------------------
procedure Deallocate is
------------------------------------------------------------
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
Deallocate(AlertLogPtr(i).Name) ;
Deallocate(AlertLogPtr(i)) ;
end loop ;
deallocate(AlertLogPtr) ;
-- Free up space used by protected types within AlertLogPkg
AlertPrefixVar.Deallocate ;
LogPrefixVar.Deallocate ;
ReportPrefixVar.Deallocate ;
DoneNameVar.Deallocate ;
PassNameVar.Deallocate ;
FailNameVar.Deallocate ;
-- Restore variables to their initial state
PrintPassedVar := TRUE ;
PrintAffirmationsVar := FALSE ;
PrintDisabledAlertsVar := FALSE ;
PrintRequirementsVar := FALSE ;
PrintIfHaveRequirementsVar := TRUE ;
DefaultPassedGoalVar := 1 ;
NumAlertLogIDsVar := 0 ;
NumAllocatedAlertLogIDsVar := 0 ;
GlobalAlertEnabledVar := TRUE ; -- Allows turn off and on
AffirmCheckCountVar := 0 ;
PassedCountVar := 0 ;
FailOnWarningVar := TRUE ;
FailOnDisabledErrorsVar := TRUE ;
FailOnRequirementErrorsVar := TRUE ;
ReportHierarchyVar := TRUE ;
FoundReportHierVar := FALSE ;
FoundAlertHierVar := FALSE ;
WriteAlertErrorCountVar := FALSE ;
WriteAlertLevelVar := TRUE ;
WriteAlertNameVar := TRUE ;
WriteAlertTimeVar := TRUE ;
WriteLogErrorCountVar := FALSE ;
WriteLogLevelVar := TRUE ;
WriteLogNameVar := TRUE ;
WriteLogTimeVar := TRUE ;
end procedure Deallocate ;
------------------------------------------------------------
-- PT Local.
procedure GrowAlertStructure (NewNumAlertLogIDs : AlertLogIDType) is
------------------------------------------------------------
variable oldAlertLogPtr : AlertLogArrayPtrType ;
begin
if NumAllocatedAlertLogIDsVar = 0 then
Initialize (NewNumAlertLogIDs) ; -- Construct initial structure
else
oldAlertLogPtr := AlertLogPtr ;
AlertLogPtr := new AlertLogArrayType(ALERTLOG_BASE_ID to NewNumAlertLogIDs) ;
AlertLogPtr(ALERTLOG_BASE_ID to NumAlertLogIDsVar) := oldAlertLogPtr(ALERTLOG_BASE_ID to NumAlertLogIDsVar) ;
deallocate(oldAlertLogPtr) ;
end if ;
NumAllocatedAlertLogIDsVar := NewNumAlertLogIDs ;
end procedure GrowAlertStructure ;
------------------------------------------------------------
-- Sets a AlertLogPtr to a particular size
-- Use for small bins to save space or large bins to
-- suppress the resize and copy as a CovBin autosizes.
procedure SetNumAlertLogIDs (NewNumAlertLogIDs : AlertLogIDType) is
------------------------------------------------------------
variable oldAlertLogPtr : AlertLogArrayPtrType ;
begin
if NewNumAlertLogIDs > NumAllocatedAlertLogIDsVar then
GrowAlertStructure(NewNumAlertLogIDs) ;
end if;
end procedure SetNumAlertLogIDs ;
------------------------------------------------------------
-- PT Local
impure function GetNextAlertLogID return AlertLogIDType is
------------------------------------------------------------
variable NewNumAlertLogIDs : AlertLogIDType ;
begin
NewNumAlertLogIDs := NumAlertLogIDsVar + 1 ;
if NewNumAlertLogIDs > NumAllocatedAlertLogIDsVar then
GrowAlertStructure(NumAllocatedAlertLogIDsVar + MIN_NUM_AL_IDS) ;
end if ;
NumAlertLogIDsVar := NewNumAlertLogIDs ;
return NumAlertLogIDsVar ;
end function GetNextAlertLogID ;
------------------------------------------------------------
impure function FindAlertLogID(Name : string ) return AlertLogIDType is
------------------------------------------------------------
constant NameLower : string := to_lower(Name) ;
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
if NameLower = AlertLogPtr(i).NameLower.all then
return i ;
end if ;
end loop ;
return ALERTLOG_ID_NOT_FOUND ; -- not found
end function FindAlertLogID ;
------------------------------------------------------------
-- PT Local
impure function LocalFindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
constant NameLower : string := to_lower(Name) ;
begin
if ParentID = ALERTLOG_ID_NOT_ASSIGNED then
return FindAlertLogID(Name) ;
else
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
if NameLower = AlertLogPtr(i).NameLower.all and
(AlertLogPtr(i).ParentID = ParentID or AlertLogPtr(i).ParentIDSet = FALSE)
then
return i ;
end if ;
end loop ;
return ALERTLOG_ID_NOT_FOUND ; -- not found
end if ;
end function LocalFindAlertLogID ;
------------------------------------------------------------
impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
variable localParentID : AlertLogIDType ;
begin
localParentID := VerifyID(ParentID, ALERTLOG_ID_NOT_ASSIGNED) ;
return LocalFindAlertLogID(Name, localParentID) ;
end function FindAlertLogID ;
------------------------------------------------------------
-- PT Local
procedure AdjustID(AlertLogID, ParentID : AlertLogIDType ; ParentIDSet : boolean := TRUE) is
------------------------------------------------------------
begin
if IsRequirement(AlertLogID) and not IsRequirement(ParentID) then
Alert(AlertLogID, "GetAlertLogID/GetReqID: Parent of a Requirement must be a Requirement") ;
else
if ParentID /= AlertLogPtr(AlertLogID).ParentID then
DeQueueID(AlertLogID) ;
EnQueueID(AlertLogID, ParentID, ParentIDSet) ;
else
AlertLogPtr(AlertLogID).ParentIDSet := ParentIDSet ;
end if ;
end if ;
end procedure AdjustID ;
------------------------------------------------------------
impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType ; CreateHierarchy : Boolean) return AlertLogIDType is
------------------------------------------------------------
variable ResultID : AlertLogIDType ;
variable localParentID : AlertLogIDType ;
begin
localParentID := VerifyID(ParentID, ALERTLOG_ID_NOT_ASSIGNED) ;
ResultID := LocalFindAlertLogID(Name, localParentID) ;
if ResultID /= ALERTLOG_ID_NOT_FOUND then -- found it, set localParentID
if AlertLogPtr(ResultID).ParentIDSet = FALSE and localParentID /= ALERTLOG_ID_NOT_ASSIGNED then
AdjustID(ResultID, localParentID, TRUE) ;
-- else -- do not update as ParentIDs are either same or input localParentID = ALERTLOG_ID_NOT_ASSIGNED
end if ;
else
-- Create a new ID
ResultID := GetNextAlertLogID ;
NewAlertLogRec(ResultID, Name, localParentID) ;
FoundAlertHierVar := TRUE ;
if CreateHierarchy then
FoundReportHierVar := TRUE ;
end if ;
AlertLogPtr(ResultID).PassedGoal := 0 ;
AlertLogPtr(ResultID).PassedGoalSet := FALSE ;
end if ;
return ResultID ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function GetReqID(Name : string ; PassedGoal : integer ; ParentID : AlertLogIDType ; CreateHierarchy : Boolean) return AlertLogIDType is
------------------------------------------------------------
variable ResultID : AlertLogIDType ;
variable localParentID : AlertLogIDType ;
begin
HasRequirementsVar := TRUE ;
localParentID := VerifyID(ParentID, ALERTLOG_ID_NOT_ASSIGNED) ;
ResultID := LocalFindAlertLogID(Name, localParentID) ;
if ResultID /= ALERTLOG_ID_NOT_FOUND then -- found it, set localParentID
if AlertLogPtr(ResultID).ParentIDSet = FALSE then
if localParentID /= ALERTLOG_ID_NOT_ASSIGNED then
AdjustID(ResultID, localParentID, TRUE) ;
else
AdjustID(ResultID, REQUIREMENT_ALERTLOG_ID, FALSE) ;
end if ;
end if ;
if AlertLogPtr(ResultID).PassedGoalSet = FALSE then
if PassedGoal >= 0 then
AlertLogPtr(ResultID).PassedGoal := PassedGoal ;
AlertLogPtr(ResultID).PassedGoalSet := TRUE ;
else
AlertLogPtr(ResultID).PassedGoal := DefaultPassedGoalVar ;
AlertLogPtr(ResultID).PassedGoalSet := FALSE ;
end if ;
end if ;
else
-- Create a new ID
ResultID := GetNextAlertLogID ;
if localParentID = ALERTLOG_ID_NOT_ASSIGNED then
NewAlertLogRec(ResultID, Name, REQUIREMENT_ALERTLOG_ID) ;
AlertLogPtr(ResultID).ParentIDSet := FALSE ;
else
NewAlertLogRec(ResultID, Name, localParentID) ;
end if ;
FoundAlertHierVar := TRUE ;
if CreateHierarchy then
FoundReportHierVar := TRUE ;
end if ;
if PassedGoal >= 0 then
AlertLogPtr(ResultID).PassedGoal := PassedGoal ;
AlertLogPtr(ResultID).PassedGoalSet := TRUE ;
else
AlertLogPtr(ResultID).PassedGoal := DefaultPassedGoalVar ;
AlertLogPtr(ResultID).PassedGoalSet := FALSE ;
end if ;
end if ;
return ResultID ;
end function GetReqID ;
------------------------------------------------------------
procedure SetPassedGoal(AlertLogID : AlertLogIDType ; PassedGoal : integer ) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
HasRequirementsVar := TRUE ;
localAlertLogID := VerifyID(AlertLogID) ;
if PassedGoal >= 0 then
AlertLogPtr(localAlertLogID).PassedGoal := PassedGoal ;
else
AlertLogPtr(localAlertLogID).PassedGoal := DefaultPassedGoalVar ;
end if ;
end procedure SetPassedGoal ;
------------------------------------------------------------
impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).ParentID ;
end function GetAlertLogParentID ;
------------------------------------------------------------
procedure SetAlertLogPrefix(AlertLogID : AlertLogIDType; Name : string ) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
Deallocate(AlertLogPtr(localAlertLogID).Prefix) ;
if Name'length > 0 then
AlertLogPtr(localAlertLogID).Prefix := new string'(Name) ;
end if ;
end procedure SetAlertLogPrefix ;
------------------------------------------------------------
procedure UnSetAlertLogPrefix(AlertLogID : AlertLogIDType) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
Deallocate(AlertLogPtr(localAlertLogID).Prefix) ;
end procedure UnSetAlertLogPrefix ;
------------------------------------------------------------
impure function GetAlertLogPrefix(AlertLogID : AlertLogIDType) return string is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).Prefix.all ;
end function GetAlertLogPrefix ;
------------------------------------------------------------
procedure SetAlertLogSuffix(AlertLogID : AlertLogIDType; Name : string ) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
Deallocate(AlertLogPtr(localAlertLogID).Suffix) ;
if Name'length > 0 then
AlertLogPtr(localAlertLogID).Suffix := new string'(Name) ;
end if ;
end procedure SetAlertLogSuffix ;
------------------------------------------------------------
procedure UnSetAlertLogSuffix(AlertLogID : AlertLogIDType) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
Deallocate(AlertLogPtr(localAlertLogID).Suffix) ;
end procedure UnSetAlertLogSuffix ;
------------------------------------------------------------
impure function GetAlertLogSuffix(AlertLogID : AlertLogIDType) return string is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).Suffix.all ;
end function GetAlertLogSuffix ;
------------------------------------------------------------
------------------------------------------------------------
-- Accessor Methods
------------------------------------------------------------
------------------------------------------------------------
procedure SetGlobalAlertEnable (A : boolean := TRUE) is
------------------------------------------------------------
begin
GlobalAlertEnabledVar := A ;
end procedure SetGlobalAlertEnable ;
------------------------------------------------------------
impure function GetGlobalAlertEnable return boolean is
------------------------------------------------------------
begin
return GlobalAlertEnabledVar ;
end function GetGlobalAlertEnable ;
------------------------------------------------------------
-- PT LOCAL
procedure SetOneStopCount(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Level : AlertType ;
Count : integer
) is
begin
if AlertLogPtr(AlertLogID).AlertStopCount(Level) = integer'right then
AlertLogPtr(AlertLogID).AlertStopCount(Level) := Count ;
else
AlertLogPtr(AlertLogID).AlertStopCount(Level) :=
AlertLogPtr(AlertLogID).AlertStopCount(Level) + Count ;
end if ;
end procedure SetOneStopCount ;
------------------------------------------------------------
-- PT Local
procedure LocalSetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is
------------------------------------------------------------
begin
SetOneStopCount(AlertLogID, Level, Count) ;
if AlertLogID /= ALERTLOG_BASE_ID then
LocalSetAlertStopCount(AlertLogPtr(AlertLogID).ParentID, Level, Count) ;
end if ;
end procedure LocalSetAlertStopCount ;
------------------------------------------------------------
procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
LocalSetAlertStopCount(AlertLogID, Level, Count) ;
end procedure SetAlertStopCount ;
------------------------------------------------------------
impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).AlertStopCount(Level) ;
end function GetAlertStopCount ;
------------------------------------------------------------
procedure SetAlertEnable(Level : AlertType ; Enable : boolean) is
------------------------------------------------------------
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
AlertLogPtr(i).AlertEnabled(Level) := Enable ;
end loop ;
end procedure SetAlertEnable ;
------------------------------------------------------------
-- PT Local
procedure LocalSetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
variable CurID : AlertLogIDType ;
begin
AlertLogPtr(AlertLogID).AlertEnabled(Level) := Enable ;
if DescendHierarchy then
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
LocalSetAlertEnable(CurID, Level, Enable, DescendHierarchy) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end if ;
end procedure LocalSetAlertEnable ;
------------------------------------------------------------
procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
LocalSetAlertEnable(localAlertLogID, Level, Enable, DescendHierarchy) ;
end procedure SetAlertEnable ;
------------------------------------------------------------
impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).AlertEnabled(Level) ;
end function GetAlertEnable ;
------------------------------------------------------------
procedure SetLogEnable(Level : LogType ; Enable : boolean) is
------------------------------------------------------------
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
AlertLogPtr(i).LogEnabled(Level) := Enable ;
end loop ;
end procedure SetLogEnable ;
------------------------------------------------------------
-- PT Local
procedure LocalSetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
variable CurID : AlertLogIDType ;
begin
AlertLogPtr(AlertLogID).LogEnabled(Level) := Enable ;
if DescendHierarchy then
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
LocalSetLogEnable(CurID, Level, Enable, DescendHierarchy) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end if ;
end procedure LocalSetLogEnable ;
------------------------------------------------------------
procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
LocalSetLogEnable(localAlertLogID, Level, Enable, DescendHierarchy) ;
end procedure SetLogEnable ;
------------------------------------------------------------
impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
if Level = ALWAYS then
return TRUE ;
else
return AlertLogPtr(localAlertLogID).LogEnabled(Level) ;
end if ;
end function GetLogEnable ;
------------------------------------------------------------
-- PT Local
procedure PrintLogLevels(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Prefix : string ;
IndentAmount : integer
) is
variable buf : line ;
variable CurID : AlertLogIDType ;
begin
write(buf, Prefix & " " & LeftJustify(AlertLogPtr(AlertLogID).Name.all, ReportJustifyAmountVar - IndentAmount)) ;
for i in LogIndexType loop
if AlertLogPtr(AlertLogID).LogEnabled(i) then
-- write(buf, " " & to_string(AlertLogPtr(AlertLogID).LogEnabled(i)) ) ;
write(buf, " " & to_string(i)) ;
end if ;
end loop ;
WriteLine(buf) ;
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
-- Always print requirements
-- if CurID = REQUIREMENT_ALERTLOG_ID and HasRequirementsVar = FALSE then
-- CurID := AlertLogPtr(CurID).SiblingID ;
-- next ;
-- end if ;
PrintLogLevels(
AlertLogID => CurID,
Prefix => Prefix & " ",
IndentAmount => IndentAmount + 2
) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure PrintLogLevels ;
------------------------------------------------------------
procedure ReportLogEnables is
------------------------------------------------------------
variable TurnedOnJustify : boolean := FALSE ;
begin
if ReportJustifyAmountVar <= 0 then
TurnedOnJustify := TRUE ;
SetJustify ;
end if ;
PrintLogLevels(ALERTLOG_BASE_ID, "", 0) ;
if TurnedOnJustify then
-- Turn it back off
SetJustify(FALSE) ;
end if ;
end procedure ReportLogEnables ;
------------------------------------------------------------
procedure SetAlertLogOptions (
------------------------------------------------------------
FailOnWarning : AlertLogOptionsType ;
FailOnDisabledErrors : AlertLogOptionsType ;
FailOnRequirementErrors : AlertLogOptionsType ;
ReportHierarchy : AlertLogOptionsType ;
WriteAlertErrorCount : AlertLogOptionsType ;
WriteAlertLevel : AlertLogOptionsType ;
WriteAlertName : AlertLogOptionsType ;
WriteAlertTime : AlertLogOptionsType ;
WriteLogErrorCount : AlertLogOptionsType ;
WriteLogLevel : AlertLogOptionsType ;
WriteLogName : AlertLogOptionsType ;
WriteLogTime : AlertLogOptionsType ;
PrintPassed : AlertLogOptionsType ;
PrintAffirmations : AlertLogOptionsType ;
PrintDisabledAlerts : AlertLogOptionsType ;
PrintRequirements : AlertLogOptionsType ;
PrintIfHaveRequirements : AlertLogOptionsType ;
DefaultPassedGoal : integer ;
AlertPrefix : string ;
LogPrefix : string ;
ReportPrefix : string ;
DoneName : string ;
PassName : string ;
FailName : string
) is
begin
if FailOnWarning /= OPT_INIT_PARM_DETECT then
FailOnWarningVar := IsEnabled(FailOnWarning) ;
end if ;
if FailOnDisabledErrors /= OPT_INIT_PARM_DETECT then
FailOnDisabledErrorsVar := IsEnabled(FailOnDisabledErrors) ;
end if ;
if FailOnRequirementErrors /= OPT_INIT_PARM_DETECT then
FailOnRequirementErrorsVar := IsEnabled(FailOnRequirementErrors) ;
end if ;
if ReportHierarchy /= OPT_INIT_PARM_DETECT then
ReportHierarchyVar := IsEnabled(ReportHierarchy) ;
end if ;
if WriteAlertErrorCount /= OPT_INIT_PARM_DETECT then
WriteAlertErrorCountVar := IsEnabled(WriteAlertErrorCount) ;
end if ;
if WriteAlertLevel /= OPT_INIT_PARM_DETECT then
WriteAlertLevelVar := IsEnabled(WriteAlertLevel) ;
end if ;
if WriteAlertName /= OPT_INIT_PARM_DETECT then
WriteAlertNameVar := IsEnabled(WriteAlertName) ;
end if ;
if WriteAlertTime /= OPT_INIT_PARM_DETECT then
WriteAlertTimeVar := IsEnabled(WriteAlertTime) ;
end if ;
if WriteLogErrorCount /= OPT_INIT_PARM_DETECT then
WriteLogErrorCountVar := IsEnabled(WriteLogErrorCount) ;
end if ;
if WriteLogLevel /= OPT_INIT_PARM_DETECT then
WriteLogLevelVar := IsEnabled(WriteLogLevel) ;
end if ;
if WriteLogName /= OPT_INIT_PARM_DETECT then
WriteLogNameVar := IsEnabled(WriteLogName) ;
end if ;
if WriteLogTime /= OPT_INIT_PARM_DETECT then
WriteLogTimeVar := IsEnabled(WriteLogTime) ;
end if ;
if PrintPassed /= OPT_INIT_PARM_DETECT then
PrintPassedVar := IsEnabled(PrintPassed) ;
end if ;
if PrintAffirmations /= OPT_INIT_PARM_DETECT then
PrintAffirmationsVar := IsEnabled(PrintAffirmations) ;
end if ;
if PrintDisabledAlerts /= OPT_INIT_PARM_DETECT then
PrintDisabledAlertsVar := IsEnabled(PrintDisabledAlerts) ;
end if ;
if PrintRequirements /= OPT_INIT_PARM_DETECT then
PrintRequirementsVar := IsEnabled(PrintRequirements) ;
end if ;
if PrintIfHaveRequirements /= OPT_INIT_PARM_DETECT then
PrintIfHaveRequirementsVar := IsEnabled(PrintIfHaveRequirements) ;
end if ;
if DefaultPassedGoal > 0 then
DefaultPassedGoalVar := DefaultPassedGoal ;
end if ;
if AlertPrefix /= OSVVM_STRING_INIT_PARM_DETECT then
AlertPrefixVar.Set(AlertPrefix) ;
end if ;
if LogPrefix /= OSVVM_STRING_INIT_PARM_DETECT then
LogPrefixVar.Set(LogPrefix) ;
end if ;
if ReportPrefix /= OSVVM_STRING_INIT_PARM_DETECT then
ReportPrefixVar.Set(ReportPrefix) ;
end if ;
if DoneName /= OSVVM_STRING_INIT_PARM_DETECT then
DoneNameVar.Set(DoneName) ;
end if ;
if PassName /= OSVVM_STRING_INIT_PARM_DETECT then
PassNameVar.Set(PassName) ;
end if ;
if FailName /= OSVVM_STRING_INIT_PARM_DETECT then
FailNameVar.Set(FailName) ;
end if ;
end procedure SetAlertLogOptions ;
------------------------------------------------------------
procedure ReportAlertLogOptions is
------------------------------------------------------------
variable buf : line ;
begin
-- Boolean Values
swrite(buf, "ReportAlertLogOptions" & LF ) ;
swrite(buf, "---------------------" & LF ) ;
swrite(buf, "FailOnWarningVar: " & to_string(FailOnWarningVar ) & LF ) ;
swrite(buf, "FailOnDisabledErrorsVar: " & to_string(FailOnDisabledErrorsVar ) & LF ) ;
swrite(buf, "FailOnRequirementErrorsVar: " & to_string(FailOnRequirementErrorsVar ) & LF ) ;
swrite(buf, "ReportHierarchyVar: " & to_string(ReportHierarchyVar ) & LF ) ;
swrite(buf, "FoundReportHierVar: " & to_string(FoundReportHierVar ) & LF ) ; -- Not set by user
swrite(buf, "FoundAlertHierVar: " & to_string(FoundAlertHierVar ) & LF ) ; -- Not set by user
swrite(buf, "WriteAlertErrorCountVar: " & to_string(WriteAlertErrorCountVar ) & LF ) ;
swrite(buf, "WriteAlertLevelVar: " & to_string(WriteAlertLevelVar ) & LF ) ;
swrite(buf, "WriteAlertNameVar: " & to_string(WriteAlertNameVar ) & LF ) ;
swrite(buf, "WriteAlertTimeVar: " & to_string(WriteAlertTimeVar ) & LF ) ;
swrite(buf, "WriteLogErrorCountVar: " & to_string(WriteLogErrorCountVar ) & LF ) ;
swrite(buf, "WriteLogLevelVar: " & to_string(WriteLogLevelVar ) & LF ) ;
swrite(buf, "WriteLogNameVar: " & to_string(WriteLogNameVar ) & LF ) ;
swrite(buf, "WriteLogTimeVar: " & to_string(WriteLogTimeVar ) & LF ) ;
swrite(buf, "PrintPassedVar: " & to_string(PrintPassedVar ) & LF ) ;
swrite(buf, "PrintAffirmationsVar: " & to_string(PrintAffirmationsVar ) & LF ) ;
swrite(buf, "PrintDisabledAlertsVar: " & to_string(PrintDisabledAlertsVar ) & LF ) ;
swrite(buf, "PrintRequirementsVar: " & to_string(PrintRequirementsVar ) & LF ) ;
swrite(buf, "PrintIfHaveRequirementsVar: " & to_string(PrintIfHaveRequirementsVar ) & LF ) ;
-- String
swrite(buf, "AlertPrefixVar: " & string'(AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX)) & LF ) ;
swrite(buf, "LogPrefixVar: " & string'(LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX)) & LF ) ;
swrite(buf, "ReportPrefixVar: " & ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) & LF ) ;
swrite(buf, "DoneNameVar: " & ResolveOsvvmDoneName(DoneNameVar.GetOpt) & LF ) ;
swrite(buf, "PassNameVar: " & ResolveOsvvmPassName(PassNameVar.GetOpt) & LF ) ;
swrite(buf, "FailNameVar: " & ResolveOsvvmFailName(FailNameVar.GetOpt) & LF ) ;
writeline(buf) ;
end procedure ReportAlertLogOptions ;
------------------------------------------------------------
impure function GetAlertLogFailOnWarning return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(FailOnWarningVar) ;
end function GetAlertLogFailOnWarning ;
------------------------------------------------------------
impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(FailOnDisabledErrorsVar) ;
end function GetAlertLogFailOnDisabledErrors ;
------------------------------------------------------------
impure function GetAlertLogFailOnRequirementErrors return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(FailOnRequirementErrorsVar) ;
end function GetAlertLogFailOnRequirementErrors ;
------------------------------------------------------------
impure function GetAlertLogReportHierarchy return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(ReportHierarchyVar) ;
end function GetAlertLogReportHierarchy ;
------------------------------------------------------------
impure function GetAlertLogFoundReportHier return boolean is
------------------------------------------------------------
begin
return FoundReportHierVar ;
end function GetAlertLogFoundReportHier ;
------------------------------------------------------------
impure function GetAlertLogFoundAlertHier return boolean is
------------------------------------------------------------
begin
return FoundAlertHierVar ;
end function GetAlertLogFoundAlertHier ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertErrorCount return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteAlertErrorCountVar) ;
end function GetAlertLogWriteAlertErrorCount ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteAlertLevelVar) ;
end function GetAlertLogWriteAlertLevel ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertName return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteAlertNameVar) ;
end function GetAlertLogWriteAlertName ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertTime return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteAlertTimeVar) ;
end function GetAlertLogWriteAlertTime ;
------------------------------------------------------------
impure function GetAlertLogWriteLogErrorCount return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteLogErrorCountVar) ;
end function GetAlertLogWriteLogErrorCount ;
------------------------------------------------------------
impure function GetAlertLogWriteLogLevel return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteLogLevelVar) ;
end function GetAlertLogWriteLogLevel ;
------------------------------------------------------------
impure function GetAlertLogWriteLogName return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteLogNameVar) ;
end function GetAlertLogWriteLogName ;
------------------------------------------------------------
impure function GetAlertLogWriteLogTime return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteLogTimeVar) ;
end function GetAlertLogWriteLogTime ;
------------------------------------------------------------
impure function GetAlertLogPrintPassed return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(PrintPassedVar) ;
end function GetAlertLogPrintPassed ;
------------------------------------------------------------
impure function GetAlertLogPrintAffirmations return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(PrintAffirmationsVar) ;
end function GetAlertLogPrintAffirmations ;
------------------------------------------------------------
impure function GetAlertLogPrintDisabledAlerts return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(PrintDisabledAlertsVar) ;
end function GetAlertLogPrintDisabledAlerts ;
------------------------------------------------------------
impure function GetAlertLogPrintRequirements return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(PrintRequirementsVar) ;
end function GetAlertLogPrintRequirements ;
------------------------------------------------------------
impure function GetAlertLogPrintIfHaveRequirements return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(PrintIfHaveRequirementsVar) ;
end function GetAlertLogPrintIfHaveRequirements ;
------------------------------------------------------------
impure function GetAlertLogDefaultPassedGoal return integer is
------------------------------------------------------------
begin
return DefaultPassedGoalVar ;
end function GetAlertLogDefaultPassedGoal ;
------------------------------------------------------------
impure function GetAlertLogAlertPrefix return string is
------------------------------------------------------------
begin
return AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ;
end function GetAlertLogAlertPrefix ;
------------------------------------------------------------
impure function GetAlertLogLogPrefix return string is
------------------------------------------------------------
begin
return LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX) ;
end function GetAlertLogLogPrefix ;
------------------------------------------------------------
impure function GetAlertLogReportPrefix return string is
------------------------------------------------------------
begin
return ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) ;
end function GetAlertLogReportPrefix ;
------------------------------------------------------------
impure function GetAlertLogDoneName return string is
------------------------------------------------------------
begin
return ResolveOsvvmDoneName(DoneNameVar.GetOpt) ;
end function GetAlertLogDoneName ;
------------------------------------------------------------
impure function GetAlertLogPassName return string is
------------------------------------------------------------
begin
return ResolveOsvvmPassName(PassNameVar.GetOpt) ;
end function GetAlertLogPassName ;
------------------------------------------------------------
impure function GetAlertLogFailName return string is
------------------------------------------------------------
begin
return ResolveOsvvmFailName(FailNameVar.GetOpt) ;
end function GetAlertLogFailName ;
end protected body AlertLogStructPType ;
shared variable AlertLogStruct : AlertLogStructPType ;
-- synthesis translate_on
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
procedure Alert(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : AlertType := ERROR
) is
begin
-- synthesis translate_off
AlertLogStruct.Alert(AlertLogID, Message, Level) ;
-- synthesis translate_on
end procedure alert ;
------------------------------------------------------------
procedure Alert( Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ;
-- synthesis translate_on
end procedure alert ;
------------------------------------------------------------
procedure IncAlertCount(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Level : AlertType := ERROR
) is
begin
-- synthesis translate_off
AlertLogStruct.IncAlertCount(AlertLogID, Level) ;
-- synthesis translate_on
end procedure IncAlertCount ;
------------------------------------------------------------
procedure IncAlertCount( Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.IncAlertCount(ALERT_DEFAULT_ID, Level) ;
-- synthesis translate_on
end procedure IncAlertCount ;
------------------------------------------------------------
procedure AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if condition then
AlertLogStruct.Alert(AlertLogID , Message, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIf ;
------------------------------------------------------------
procedure AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if condition then
AlertLogStruct.Alert(ALERT_DEFAULT_ID , Message, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIf ;
------------------------------------------------------------
-- useful in a loop: exit when AlertIf( not ReadValid, failure, "Read Failed") ;
impure function AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
if condition then
AlertLogStruct.Alert(AlertLogID , Message, Level) ;
end if ;
-- synthesis translate_on
return condition ;
end function AlertIf ;
------------------------------------------------------------
impure function AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
if condition then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ;
end if ;
-- synthesis translate_on
return condition ;
end function AlertIf ;
------------------------------------------------------------
procedure AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not condition then
AlertLogStruct.Alert(AlertLogID, Message, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNot ;
------------------------------------------------------------
procedure AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not condition then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNot ;
------------------------------------------------------------
-- useful in a loop: exit when AlertIfNot( not ReadValid, failure, "Read Failed") ;
impure function AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
if not condition then
AlertLogStruct.Alert(AlertLogID, Message, Level) ;
end if ;
-- synthesis translate_on
return not condition ;
end function AlertIfNot ;
------------------------------------------------------------
impure function AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
if not condition then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ;
end if ;
-- synthesis translate_on
return not condition ;
end function AlertIfNot ;
------------------------------------------------------------
-- AlertIfEqual with AlertLogID
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : time ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
-- AlertIfEqual without AlertLogID
------------------------------------------------------------
procedure AlertIfEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : time ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
-- AlertIfNotEqual with AlertLogID
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : time ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
-- AlertIfNotEqual without AlertLogID
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : time ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
-- Local
procedure LocalAlertIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string ; Level : AlertType ; Valid : out boolean ) is
-- Simple diff.
------------------------------------------------------------
variable Buf1, Buf2 : line ;
variable File1Done, File2Done : boolean ;
variable LineCount : integer := 0 ;
begin
-- synthesis translate_off
ReadLoop : loop
File1Done := EndFile(File1) ;
File2Done := EndFile(File2) ;
exit ReadLoop when File1Done or File2Done ;
ReadLine(File1, Buf1) ;
ReadLine(File2, Buf2) ;
LineCount := LineCount + 1 ;
if Buf1.all /= Buf2.all then
AlertLogStruct.Alert(AlertLogID , Message & " File miscompare on line " & to_string(LineCount), Level) ;
exit ReadLoop ;
end if ;
end loop ReadLoop ;
if File1Done /= File2Done then
if not File1Done then
AlertLogStruct.Alert(AlertLogID , Message & " File1 longer than File2 " & to_string(LineCount), Level) ;
end if ;
if not File2Done then
AlertLogStruct.Alert(AlertLogID , Message & " File2 longer than File1 " & to_string(LineCount), Level) ;
end if ;
end if;
if File1Done and File2Done then
Valid := TRUE ;
else
Valid := FALSE ;
end if ;
-- synthesis translate_on
end procedure LocalAlertIfDiff ;
------------------------------------------------------------
-- Local
procedure LocalAlertIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string ; Level : AlertType ; Valid : out boolean ) is
-- Open files and call AlertIfDiff[text, ...]
------------------------------------------------------------
file FileID1, FileID2 : text ;
variable status1, status2 : file_open_status ;
begin
-- synthesis translate_off
Valid := FALSE ;
file_open(status1, FileID1, Name1, READ_MODE) ;
file_open(status2, FileID2, Name2, READ_MODE) ;
if status1 = OPEN_OK and status2 = OPEN_OK then
LocalAlertIfDiff (AlertLogID, FileID1, FileID2, Message & " " & Name1 & " /= " & Name2 & ", ", Level, Valid) ;
else
if status1 /= OPEN_OK then
AlertLogStruct.Alert(AlertLogID , Message & " File, " & Name1 & ", did not open", Level) ;
end if ;
if status2 /= OPEN_OK then
AlertLogStruct.Alert(AlertLogID , Message & " File, " & Name2 & ", did not open", Level) ;
end if ;
end if;
-- synthesis translate_on
end procedure LocalAlertIfDiff ;
------------------------------------------------------------
procedure AlertIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) is
-- Open files and call AlertIfDiff[text, ...]
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (AlertLogID, Name1, Name2, Message, Level, Valid) ;
-- synthesis translate_on
end procedure AlertIfDiff ;
------------------------------------------------------------
procedure AlertIfDiff (Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) is
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (ALERT_DEFAULT_ID, Name1, Name2, Message, Level, Valid) ;
-- synthesis translate_on
end procedure AlertIfDiff ;
------------------------------------------------------------
procedure AlertIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) is
-- Simple diff.
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (AlertLogID, File1, File2, Message, Level, Valid ) ;
-- synthesis translate_on
end procedure AlertIfDiff ;
------------------------------------------------------------
procedure AlertIfDiff (file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) is
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (ALERT_DEFAULT_ID, File1, File2, Message, Level, Valid ) ;
-- synthesis translate_on
end procedure AlertIfDiff ;
------------------------------------------------------------
procedure AffirmIf(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
condition : boolean ;
ReceivedMessage : string ;
ExpectedMessage : string ;
Enable : boolean := FALSE -- override internal enable
) is
begin
-- synthesis translate_off
if condition then
-- PASSED. Count affirmations and PASSED internal to LOG to catch all of them
AlertLogStruct.Log(AlertLogID, ReceivedMessage, PASSED, Enable) ;
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
AlertLogStruct.Alert(AlertLogID, ReceivedMessage & ' ' & ExpectedMessage, ERROR) ;
end if ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
procedure AffirmIf( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
impure function AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
return condition ;
end function AffirmIf ;
------------------------------------------------------------
impure function AffirmIf( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
return condition ;
end function AffirmIf ;
------------------------------------------------------------
procedure AffirmIf(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
condition : boolean ;
Message : string ;
Enable : boolean := FALSE -- override internal enable
) is
begin
-- synthesis translate_off
if condition then
-- PASSED. Count affirmations and PASSED internal to LOG to catch all of them
AlertLogStruct.Log(AlertLogID, Message, PASSED, Enable) ;
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
AlertLogStruct.Alert(AlertLogID, Message, ERROR) ;
end if ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
procedure AffirmIf(condition : boolean ; Message : string ; Enable : boolean := FALSE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIf;
------------------------------------------------------------
-- useful in a loop: exit when AffirmIf( ID, not ReadValid, "Read Failed") ;
impure function AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, condition, Message, Enable) ;
-- synthesis translate_on
return condition ;
end function AffirmIf ;
------------------------------------------------------------
impure function AffirmIf( condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, Message, Enable) ;
-- synthesis translate_on
return condition ;
end function AffirmIf ;
------------------------------------------------------------
------------------------------------------------------------
procedure AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, not condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
end procedure AffirmIfNot ;
------------------------------------------------------------
procedure AffirmIfNot( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, not condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
end procedure AffirmIfNot ;
------------------------------------------------------------
-- useful in a loop: exit when AffirmIfNot( not ReadValid, failure, "Read Failed") ;
impure function AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, not condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
return not condition ;
end function AffirmIfNot ;
------------------------------------------------------------
impure function AffirmIfNot( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, not condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
return not condition ;
end function AffirmIfNot ;
------------------------------------------------------------
procedure AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, not condition, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIfNot ;
------------------------------------------------------------
procedure AffirmIfNot( condition : boolean ; Message : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, not condition, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIfNot ;
------------------------------------------------------------
-- useful in a loop: exit when AffirmIfNot( not ReadValid, failure, "Read Failed") ;
impure function AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, not condition, Message, Enable) ;
-- synthesis translate_on
return not condition ;
end function AffirmIfNot ;
------------------------------------------------------------
impure function AffirmIfNot( condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, not condition, Message, Enable) ;
-- synthesis translate_on
return not condition ;
end function AffirmIfNot ;
------------------------------------------------------------
------------------------------------------------------------
procedure AffirmPassed( AlertLogID : AlertLogIDType ; Message : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, TRUE, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmPassed ;
------------------------------------------------------------
procedure AffirmPassed( Message : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, TRUE, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmPassed ;
------------------------------------------------------------
procedure AffirmError( AlertLogID : AlertLogIDType ; Message : string ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, FALSE, Message, FALSE) ;
-- synthesis translate_on
end procedure AffirmError ;
------------------------------------------------------------
procedure AffirmError( Message : string ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, FALSE, Message, FALSE) ;
-- synthesis translate_on
end procedure AffirmError ;
-- With AlertLogID
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : boolean ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & to_string(Received),
"?= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : std_logic ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, MetaMatch(Received, Expected),
Message & " Received : " & to_string(Received),
"?= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : std_logic_vector ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, MetaMatch(Received, Expected),
Message & " Received : " & to_hstring(Received),
"?= Expected : " & to_hstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : unsigned ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, MetaMatch(Received, Expected),
Message & " Received : " & to_hstring(Received),
"?= Expected : " & to_hstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : signed ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, MetaMatch(Received, Expected),
Message & " Received : " & to_hstring(Received),
"?= Expected : " & to_hstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : integer ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & to_string(Received),
"= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : real ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & to_string(Received, 4),
"= Expected : " & to_string(Expected, 4),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : character ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & to_string(Received),
"= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : string ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & Received,
"= Expected : " & Expected,
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : time ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & to_string(Received),
"= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
-- Without AlertLogID
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : boolean ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & to_string(Received),
"?= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : std_logic ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, MetaMatch(Received, Expected),
Message & " Received : " & to_string(Received),
"?= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : std_logic_vector ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, MetaMatch(Received, Expected),
Message & " Received : " & to_hstring(Received),
"?= Expected : " & to_hstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : unsigned ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, MetaMatch(Received, Expected),
Message & " Received : " & to_hstring(Received),
"?= Expected : " & to_hstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : signed ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, MetaMatch(Received, Expected),
Message & " Received : " & to_hstring(Received),
"?= Expected : " & to_hstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : integer ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & to_string(Received),
"= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : real ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & to_string(Received, 4),
"= Expected : " & to_string(Expected, 4),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : character ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & to_string(Received),
"= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : string ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & Received,
"= Expected : " & Expected,
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : time ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & to_string(Received),
"= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) is
-- Open files and call AffirmIfDiff[text, ...]
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (AlertLogID, Name1, Name2, Message, ERROR, Valid) ;
if Valid then
AlertLogStruct.Log(AlertLogID, Message & " " & Name1 & " = " & Name2, PASSED, Enable) ;
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
-- Alert already signaled by LocalAlertIfDiff
end if ;
-- synthesis translate_on
end procedure AffirmIfDiff ;
------------------------------------------------------------
procedure AffirmIfDiff (Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIfDiff(ALERT_DEFAULT_ID, Name1, Name2, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIfDiff ;
------------------------------------------------------------
procedure AffirmIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) is
-- Simple diff.
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (AlertLogID, File1, File2, Message, ERROR, Valid ) ;
if Valid then
AlertLogStruct.Log(AlertLogID, Message, PASSED, Enable) ;
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
-- Alert already signaled by LocalAlertIfDiff
end if ;
-- synthesis translate_on
end procedure AffirmIfDiff ;
------------------------------------------------------------
procedure AffirmIfDiff (file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIfDiff(ALERT_DEFAULT_ID, File1, File2, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIfDiff ;
-- Support for Specification / Requirements Tracking
------------------------------------------------------------
procedure AffirmIf( RequirementsIDName : string ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
--?? Set Goal to 1? Should the ID already exist?
AffirmIf(GetReqID(RequirementsIDName), condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
procedure AffirmIf( RequirementsIDName : string ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
--?? Set Goal to 1? Should the ID already exist?
AffirmIf(GetReqID(RequirementsIDName), condition, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
procedure SetAlertLogJustify (Enable : boolean := TRUE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetJustify(Enable) ;
-- synthesis translate_on
end procedure SetAlertLogJustify ;
------------------------------------------------------------
procedure ReportAlerts ( Name : String ; AlertCount : AlertCountType ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportAlerts(Name, AlertCount) ;
-- synthesis translate_on
end procedure ReportAlerts ;
------------------------------------------------------------
procedure ReportRequirements is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportRequirements ;
-- synthesis translate_on
end procedure ReportRequirements ;
------------------------------------------------------------
procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportAlerts(Name, AlertLogID, ExternalErrors, TRUE) ;
-- synthesis translate_on
end procedure ReportAlerts ;
------------------------------------------------------------
procedure ReportNonZeroAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportAlerts(Name, AlertLogID, ExternalErrors, FALSE) ;
-- synthesis translate_on
end procedure ReportNonZeroAlerts ;
------------------------------------------------------------
procedure WriteTestSummary (
------------------------------------------------------------
FileName : string ;
OpenKind : File_Open_Kind := APPEND_MODE
) is
begin
-- synthesis translate_off
AlertLogStruct.WriteTestSummary(FileName, OpenKind) ;
-- synthesis translate_on
end procedure WriteTestSummary ;
------------------------------------------------------------
procedure WriteTestSummaries (
------------------------------------------------------------
FileName : string ;
OpenKind : File_Open_Kind := WRITE_MODE
) is
begin
-- synthesis translate_off
AlertLogStruct.WriteTestSummaries(FileName, OpenKind) ;
-- synthesis translate_on
end procedure WriteTestSummaries ;
------------------------------------------------------------
procedure ReportTestSummaries is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportTestSummaries ;
-- synthesis translate_on
end procedure ReportTestSummaries ;
------------------------------------------------------------
procedure WriteAlerts (
------------------------------------------------------------
FileName : string ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
OpenKind : File_Open_Kind := WRITE_MODE
) is
begin
-- synthesis translate_off
AlertLogStruct.WriteAlerts(FileName, AlertLogID, OpenKind) ;
-- synthesis translate_on
end procedure WriteAlerts ;
------------------------------------------------------------
procedure WriteRequirements (
------------------------------------------------------------
FileName : string ;
AlertLogID : AlertLogIDType := REQUIREMENT_ALERTLOG_ID ;
OpenKind : File_Open_Kind := WRITE_MODE
) is
begin
-- synthesis translate_off
AlertLogStruct.WriteRequirements(FileName, AlertLogID, OpenKind) ;
-- synthesis translate_on
end procedure WriteRequirements ;
------------------------------------------------------------
procedure ReadSpecification (FileName : string ; PassedGoal : integer := -1 ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReadSpecification(FileName, PassedGoal) ;
-- synthesis translate_on
end procedure ReadSpecification ;
------------------------------------------------------------
procedure ReadRequirements (
------------------------------------------------------------
FileName : string ;
ThresholdPassed : boolean := FALSE
) is
begin
-- synthesis translate_off
AlertLogStruct.ReadRequirements(FileName, ThresholdPassed, TestSummary => FALSE) ;
-- synthesis translate_on
end procedure ReadRequirements ;
------------------------------------------------------------
procedure ReadTestSummaries (FileName : string) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReadRequirements(FileName, ThresholdPassed => FALSE, TestSummary => TRUE) ;
-- synthesis translate_on
end procedure ReadTestSummaries ;
-- ------------------------------------------------------------
-- procedure ReportTestSummaries (FileName : string) is
-- ------------------------------------------------------------
-- begin
-- -- synthesis translate_off
-- AlertLogStruct.ReadRequirements(FileName, ThresholdPassed => FALSE, TestSummary => TRUE) ;
-- -- synthesis translate_on
-- end procedure ReportTestSummaries ;
------------------------------------------------------------
procedure ClearAlerts is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ClearAlerts ;
-- synthesis translate_on
end procedure ClearAlerts ;
------------------------------------------------------------
procedure ClearAlertStopCounts is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ClearAlertStopCounts ;
-- synthesis translate_on
end procedure ClearAlertStopCounts ;
------------------------------------------------------------
procedure ClearAlertCounts is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ClearAlerts ;
AlertLogStruct.ClearAlertStopCounts ;
-- synthesis translate_on
end procedure ClearAlertCounts ;
------------------------------------------------------------
function "ABS" (L : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Result : AlertCountType ;
begin
-- synthesis translate_off
Result(FAILURE) := ABS( L(FAILURE) ) ;
Result(ERROR) := ABS( L(ERROR) ) ;
Result(WARNING) := ABS( L(WARNING) );
-- synthesis translate_on
return Result ;
end function "ABS" ;
------------------------------------------------------------
function "+" (L, R : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Result : AlertCountType ;
begin
-- synthesis translate_off
Result(FAILURE) := L(FAILURE) + R(FAILURE) ;
Result(ERROR) := L(ERROR) + R(ERROR) ;
Result(WARNING) := L(WARNING) + R(WARNING) ;
-- synthesis translate_on
return Result ;
end function "+" ;
------------------------------------------------------------
function "-" (L, R : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Result : AlertCountType ;
begin
-- synthesis translate_off
Result(FAILURE) := L(FAILURE) - R(FAILURE) ;
Result(ERROR) := L(ERROR) - R(ERROR) ;
Result(WARNING) := L(WARNING) - R(WARNING) ;
-- synthesis translate_on
return Result ;
end function "-" ;
------------------------------------------------------------
function "-" (R : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Result : AlertCountType ;
begin
-- synthesis translate_off
Result(FAILURE) := - R(FAILURE) ;
Result(ERROR) := - R(ERROR) ;
Result(WARNING) := - R(WARNING) ;
-- synthesis translate_on
return Result ;
end function "-" ;
------------------------------------------------------------
impure function SumAlertCount(AlertCount: AlertCountType) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
-- Using ABS ensures correct expected error handling.
result := abs(AlertCount(FAILURE)) + abs(AlertCount(ERROR)) + abs(AlertCount(WARNING)) ;
-- synthesis translate_on
return result ;
end function SumAlertCount ;
------------------------------------------------------------
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is
------------------------------------------------------------
variable result : AlertCountType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertCount(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetAlertCount ;
------------------------------------------------------------
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := SumAlertCount(AlertLogStruct.GetAlertCount(AlertLogID)) ;
-- synthesis translate_on
return result ;
end function GetAlertCount ;
------------------------------------------------------------
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is
------------------------------------------------------------
variable result : AlertCountType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetEnabledAlertCount(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetEnabledAlertCount ;
------------------------------------------------------------
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := SumAlertCount(AlertLogStruct.GetEnabledAlertCount(AlertLogID)) ;
-- synthesis translate_on
return result ;
end function GetEnabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount return AlertCountType is
------------------------------------------------------------
variable result : AlertCountType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetDisabledAlertCount ;
-- synthesis translate_on
return result ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := SumAlertCount(AlertLogStruct.GetDisabledAlertCount) ;
-- synthesis translate_on
return result ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType is
------------------------------------------------------------
variable result : AlertCountType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetDisabledAlertCount(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := SumAlertCount(AlertLogStruct.GetDisabledAlertCount(AlertLogID)) ;
-- synthesis translate_on
return result ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
procedure Log(
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType := ALWAYS ;
Enable : boolean := FALSE -- override internal enable
) is
begin
-- synthesis translate_off
AlertLogStruct.Log(AlertLogID, Message, Level, Enable) ;
-- synthesis translate_on
end procedure log ;
------------------------------------------------------------
procedure Log( Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.Log(LOG_DEFAULT_ID, Message, Level, Enable) ;
-- synthesis translate_on
end procedure log ;
------------------------------------------------------------
procedure SetAlertEnable(Level : AlertType ; Enable : boolean) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertEnable(Level, Enable) ;
-- synthesis translate_on
end procedure SetAlertEnable ;
------------------------------------------------------------
procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertEnable(AlertLogID, Level, Enable, DescendHierarchy) ;
-- synthesis translate_on
end procedure SetAlertEnable ;
------------------------------------------------------------
impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean is
------------------------------------------------------------
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertEnable(AlertLogID, Level) ;
-- synthesis translate_on
return result ;
end function GetAlertEnable ;
------------------------------------------------------------
impure function GetAlertEnable(Level : AlertType) return boolean is
------------------------------------------------------------
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertEnable(ALERT_DEFAULT_ID, Level) ;
-- synthesis translate_on
return result ;
end function GetAlertEnable ;
------------------------------------------------------------
procedure SetLogEnable(Level : LogType ; Enable : boolean) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetLogEnable(Level, Enable) ;
-- synthesis translate_on
end procedure SetLogEnable ;
------------------------------------------------------------
procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetLogEnable(AlertLogID, Level, Enable, DescendHierarchy) ;
-- synthesis translate_on
end procedure SetLogEnable ;
------------------------------------------------------------
impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean is
------------------------------------------------------------
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetLogEnable(AlertLogID, Level) ;
-- synthesis translate_on
return result ;
end function GetLogEnable ;
------------------------------------------------------------
impure function GetLogEnable(Level : LogType) return boolean is
------------------------------------------------------------
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetLogEnable(LOG_DEFAULT_ID, Level) ;
-- synthesis translate_on
return result ;
end function GetLogEnable ;
------------------------------------------------------------
procedure ReportLogEnables is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportLogEnables ;
-- synthesis translate_on
end ReportLogEnables ;
------------------------------------------------------------
procedure SetAlertLogName(Name : string ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogName(Name) ;
-- synthesis translate_on
end procedure SetAlertLogName ;
-- synthesis translate_off
------------------------------------------------------------
impure function GetAlertLogName(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogName(AlertLogID) ;
end GetAlertLogName ;
-- synthesis translate_on
------------------------------------------------------------
procedure DeallocateAlertLogStruct is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.Deallocate ;
-- synthesis translate_on
end procedure DeallocateAlertLogStruct ;
------------------------------------------------------------
procedure InitializeAlertLogStruct is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.Initialize ;
-- synthesis translate_on
end procedure InitializeAlertLogStruct ;
------------------------------------------------------------
impure function FindAlertLogID(Name : string ) return AlertLogIDType is
------------------------------------------------------------
variable result : AlertLogIDType ;
begin
-- synthesis translate_off
result := AlertLogStruct.FindAlertLogID(Name) ;
-- synthesis translate_on
return result ;
end function FindAlertLogID ;
------------------------------------------------------------
impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
variable result : AlertLogIDType ;
begin
-- synthesis translate_off
result := AlertLogStruct.FindAlertLogID(Name, ParentID) ;
-- synthesis translate_on
return result ;
end function FindAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_ID_NOT_ASSIGNED ; CreateHierarchy : Boolean := TRUE) return AlertLogIDType is
------------------------------------------------------------
variable result : AlertLogIDType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertLogID(Name, ParentID, CreateHierarchy ) ;
-- synthesis translate_on
return result ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function GetReqID(Name : string ; PassedGoal : integer := -1 ; ParentID : AlertLogIDType := ALERTLOG_ID_NOT_ASSIGNED ; CreateHierarchy : Boolean := TRUE) return AlertLogIDType is
------------------------------------------------------------
variable result : AlertLogIDType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetReqID(Name, PassedGoal, ParentID, CreateHierarchy) ;
-- synthesis translate_on
return result ;
end function GetReqID ;
------------------------------------------------------------
procedure SetPassedGoal(AlertLogID : AlertLogIDType ; PassedGoal : integer ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetPassedGoal(AlertLogID, PassedGoal) ;
-- synthesis translate_on
end procedure SetPassedGoal ;
------------------------------------------------------------
impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
variable result : AlertLogIDType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertLogParentID(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetAlertLogParentID ;
------------------------------------------------------------
procedure SetAlertLogPrefix(AlertLogID : AlertLogIDType; Name : string ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogPrefix(AlertLogID, Name) ;
-- synthesis translate_on
end procedure SetAlertLogPrefix ;
------------------------------------------------------------
procedure UnSetAlertLogPrefix(AlertLogID : AlertLogIDType ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.UnSetAlertLogPrefix(AlertLogID) ;
-- synthesis translate_on
end procedure UnSetAlertLogPrefix ;
-- synthesis translate_off
------------------------------------------------------------
impure function GetAlertLogPrefix(AlertLogID : AlertLogIDType) return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrefix(AlertLogID) ;
end function GetAlertLogPrefix ;
-- synthesis translate_on
------------------------------------------------------------
procedure SetAlertLogSuffix(AlertLogID : AlertLogIDType; Name : string ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogSuffix(AlertLogID, Name) ;
-- synthesis translate_on
end procedure SetAlertLogSuffix ;
------------------------------------------------------------
procedure UnSetAlertLogSuffix(AlertLogID : AlertLogIDType ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.UnSetAlertLogSuffix(AlertLogID) ;
-- synthesis translate_on
end procedure UnSetAlertLogSuffix ;
-- synthesis translate_off
------------------------------------------------------------
impure function GetAlertLogSuffix(AlertLogID : AlertLogIDType) return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogSuffix(AlertLogID) ;
end function GetAlertLogSuffix ;
-- synthesis translate_on
------------------------------------------------------------
procedure SetGlobalAlertEnable (A : boolean := TRUE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetGlobalAlertEnable(A) ;
-- synthesis translate_on
end procedure SetGlobalAlertEnable ;
------------------------------------------------------------
-- Set using constant. Set before code runs.
impure function SetGlobalAlertEnable (A : boolean := TRUE) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetGlobalAlertEnable(A) ;
-- synthesis translate_on
return A ;
end function SetGlobalAlertEnable ;
------------------------------------------------------------
impure function GetGlobalAlertEnable return boolean is
------------------------------------------------------------
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetGlobalAlertEnable ;
-- synthesis translate_on
return result ;
end function GetGlobalAlertEnable ;
------------------------------------------------------------
procedure IncAffirmCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.IncAffirmCount(AlertLogID) ;
-- synthesis translate_on
end procedure IncAffirmCount ;
------------------------------------------------------------
impure function GetAffirmCount return natural is
------------------------------------------------------------
variable result : natural ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAffirmCount ;
-- synthesis translate_on
return result ;
end function GetAffirmCount ;
------------------------------------------------------------
procedure IncAffirmPassedCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.IncAffirmPassedCount(AlertLogID) ;
-- synthesis translate_on
end procedure IncAffirmPassedCount ;
------------------------------------------------------------
impure function GetAffirmPassedCount return natural is
------------------------------------------------------------
variable result : natural ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAffirmPassedCount ;
-- synthesis translate_on
return result ;
end function GetAffirmPassedCount ;
------------------------------------------------------------
procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertStopCount(AlertLogID, Level, Count) ;
-- synthesis translate_on
end procedure SetAlertStopCount ;
------------------------------------------------------------
procedure SetAlertStopCount(Level : AlertType ; Count : integer) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertStopCount(ALERTLOG_BASE_ID, Level, Count) ;
-- synthesis translate_on
end procedure SetAlertStopCount ;
------------------------------------------------------------
impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertStopCount(AlertLogID, Level) ;
-- synthesis translate_on
return result ;
end function GetAlertStopCount ;
------------------------------------------------------------
impure function GetAlertStopCount(Level : AlertType) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertStopCount(ALERTLOG_BASE_ID, Level) ;
-- synthesis translate_on
return result ;
end function GetAlertStopCount ;
------------------------------------------------------------
procedure SetAlertLogOptions (
------------------------------------------------------------
FailOnWarning : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
FailOnDisabledErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
FailOnRequirementErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
ReportHierarchy : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertErrorCount : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogErrorCount : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
PrintPassed : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
PrintAffirmations : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
PrintDisabledAlerts : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
PrintRequirements : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
PrintIfHaveRequirements : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
DefaultPassedGoal : integer := integer'left ;
AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) is
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogOptions (
FailOnWarning => FailOnWarning,
FailOnDisabledErrors => FailOnDisabledErrors,
FailOnRequirementErrors => FailOnRequirementErrors,
ReportHierarchy => ReportHierarchy,
WriteAlertErrorCount => WriteAlertErrorCount,
WriteAlertLevel => WriteAlertLevel,
WriteAlertName => WriteAlertName,
WriteAlertTime => WriteAlertTime,
WriteLogErrorCount => WriteLogErrorCount,
WriteLogLevel => WriteLogLevel,
WriteLogName => WriteLogName,
WriteLogTime => WriteLogTime,
PrintPassed => PrintPassed,
PrintAffirmations => PrintAffirmations,
PrintDisabledAlerts => PrintDisabledAlerts,
PrintRequirements => PrintRequirements,
PrintIfHaveRequirements => PrintIfHaveRequirements,
DefaultPassedGoal => DefaultPassedGoal,
AlertPrefix => AlertPrefix,
LogPrefix => LogPrefix,
ReportPrefix => ReportPrefix,
DoneName => DoneName,
PassName => PassName,
FailName => FailName
);
-- synthesis translate_on
end procedure SetAlertLogOptions ;
------------------------------------------------------------
procedure ReportAlertLogOptions is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportAlertLogOptions ;
-- synthesis translate_on
end procedure ReportAlertLogOptions ;
-- synthesis translate_off
------------------------------------------------------------
impure function GetAlertLogFailOnWarning return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFailOnWarning ;
end function GetAlertLogFailOnWarning ;
------------------------------------------------------------
impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFailOnDisabledErrors ;
end function GetAlertLogFailOnDisabledErrors ;
------------------------------------------------------------
impure function GetAlertLogFailOnRequirementErrors return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFailOnRequirementErrors ;
end function GetAlertLogFailOnRequirementErrors ;
------------------------------------------------------------
impure function GetAlertLogReportHierarchy return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogReportHierarchy ;
end function GetAlertLogReportHierarchy ;
------------------------------------------------------------
impure function GetAlertLogFoundReportHier return boolean is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFoundReportHier ;
end function GetAlertLogFoundReportHier ;
------------------------------------------------------------
impure function GetAlertLogFoundAlertHier return boolean is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFoundAlertHier ;
end function GetAlertLogFoundAlertHier ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertErrorCount return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteAlertErrorCount ;
end function GetAlertLogWriteAlertErrorCount ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteAlertLevel ;
end function GetAlertLogWriteAlertLevel ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertName return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteAlertName ;
end function GetAlertLogWriteAlertName ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertTime return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteAlertTime ;
end function GetAlertLogWriteAlertTime ;
------------------------------------------------------------
impure function GetAlertLogWriteLogErrorCount return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteLogErrorCount ;
end function GetAlertLogWriteLogErrorCount ;
------------------------------------------------------------
impure function GetAlertLogWriteLogLevel return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteLogLevel ;
end function GetAlertLogWriteLogLevel ;
------------------------------------------------------------
impure function GetAlertLogWriteLogName return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteLogName ;
end function GetAlertLogWriteLogName ;
------------------------------------------------------------
impure function GetAlertLogWriteLogTime return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteLogTime ;
end function GetAlertLogWriteLogTime ;
------------------------------------------------------------
impure function GetAlertLogPrintPassed return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrintPassed ;
end function GetAlertLogPrintPassed ;
------------------------------------------------------------
impure function GetAlertLogPrintAffirmations return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrintAffirmations ;
end function GetAlertLogPrintAffirmations ;
------------------------------------------------------------
impure function GetAlertLogPrintDisabledAlerts return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrintDisabledAlerts ;
end function GetAlertLogPrintDisabledAlerts ;
------------------------------------------------------------
impure function GetAlertLogPrintRequirements return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrintRequirements ;
end function GetAlertLogPrintRequirements ;
------------------------------------------------------------
impure function GetAlertLogPrintIfHaveRequirements return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrintIfHaveRequirements ;
end function GetAlertLogPrintIfHaveRequirements ;
------------------------------------------------------------
impure function GetAlertLogDefaultPassedGoal return integer is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogDefaultPassedGoal ;
end function GetAlertLogDefaultPassedGoal ;
------------------------------------------------------------
impure function GetAlertLogAlertPrefix return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogAlertPrefix ;
end function GetAlertLogAlertPrefix ;
------------------------------------------------------------
impure function GetAlertLogLogPrefix return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogLogPrefix ;
end function GetAlertLogLogPrefix ;
------------------------------------------------------------
impure function GetAlertLogReportPrefix return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogReportPrefix ;
end function GetAlertLogReportPrefix ;
------------------------------------------------------------
impure function GetAlertLogDoneName return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogDoneName ;
end function GetAlertLogDoneName ;
------------------------------------------------------------
impure function GetAlertLogPassName return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPassName ;
end function GetAlertLogPassName ;
------------------------------------------------------------
impure function GetAlertLogFailName return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFailName ;
end function GetAlertLogFailName ;
------------------------------------------------------------
function IsLogEnableType (Name : String) return boolean is
------------------------------------------------------------
-- type LogType is (ALWAYS, DEBUG, FINAL, INFO, PASSED) ; -- NEVER
begin
if Name = "PASSED" then return TRUE ;
elsif Name = "DEBUG" then return TRUE ;
elsif Name = "FINAL" then return TRUE ;
elsif Name = "INFO" then return TRUE ;
end if ;
return FALSE ;
end function IsLogEnableType ;
------------------------------------------------------------
procedure ReadLogEnables (file AlertLogInitFile : text) is
-- Preferred Read format
-- Line 1: instance1_name log_enable log_enable log_enable
-- Line 2: instance2_name log_enable log_enable log_enable
-- when reading multiple log_enables on a line, they must be separated by a space
--
--- Also supports alternate format from Lyle/....
-- Line 1: instance1_name
-- Line 2: log enable
-- Line 3: instance2_name
-- Line 4: log enable
--
------------------------------------------------------------
type ReadStateType is (GET_ID, GET_ENABLE) ;
variable ReadState : ReadStateType := GET_ID ;
variable buf : line ;
variable Empty : boolean ;
variable MultiLineComment : boolean := FALSE ;
variable Name : string(1 to 80) ;
variable NameLen : integer ;
variable AlertLogID : AlertLogIDType ;
variable ReadAnEnable : boolean ;
variable LogLevel : LogType ;
begin
ReadState := GET_ID ;
ReadLineLoop : while not EndFile(AlertLogInitFile) loop
ReadLine(AlertLogInitFile, buf) ;
if ReadAnEnable then
-- Read one or more enable values, next line read AlertLog name
-- Note that any newline with ReadAnEnable TRUE will result in
-- searching for another AlertLogID name - this includes multi-line comments.
ReadState := GET_ID ;
end if ;
ReadNameLoop : loop
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next ReadLineLoop when Empty ;
case ReadState is
when GET_ID =>
sread(buf, Name, NameLen) ;
exit ReadNameLoop when NameLen = 0 ;
AlertLogID := GetAlertLogID(Name(1 to NameLen), ALERTLOG_ID_NOT_ASSIGNED) ;
ReadState := GET_ENABLE ;
ReadAnEnable := FALSE ;
when GET_ENABLE =>
sread(buf, Name, NameLen) ;
exit ReadNameLoop when NameLen = 0 ;
ReadAnEnable := TRUE ;
if not IsLogEnableType(Name(1 to NameLen)) then
Alert(OSVVM_ALERTLOG_ID, "AlertLogPkg.ReadLogEnables: Found Invalid LogEnable: " & Name(1 to NameLen)) ;
exit ReadNameLoop ;
end if ;
-- Log(OSVVM_ALERTLOG_ID, "SetLogEnable(OSVVM_ALERTLOG_ID, " & Name(1 to NameLen) & ", TRUE) ;", DEBUG) ;
LogLevel := LogType'value("" & Name(1 to NameLen)) ; -- "" & added for RivieraPro 2020.10
SetLogEnable(AlertLogID, LogLevel, TRUE) ;
end case ;
end loop ReadNameLoop ;
end loop ReadLineLoop ;
end procedure ReadLogEnables ;
------------------------------------------------------------
procedure ReadLogEnables (FileName : string) is
------------------------------------------------------------
file AlertLogInitFile : text open READ_MODE is FileName ;
begin
ReadLogEnables(AlertLogInitFile) ;
end procedure ReadLogEnables ;
------------------------------------------------------------
function PathTail (A : string) return string is
------------------------------------------------------------
alias aA : string(1 to A'length) is A ;
variable LenA : integer := A'length ;
begin
if aA(LenA) = ':' then
LenA := LenA - 1 ;
end if ;
for i in LenA downto 1 loop
if aA(i) = ':' then
return aA(i+1 to LenA) ;
end if ;
end loop ;
return aA(1 to LenA) ;
end function PathTail ;
------------------------------------------------------------
-- MetaMatch
-- Similar to STD_MATCH, except
-- it returns TRUE for U=U, X=X, Z=Z, and W=W
-- All other values are consistent with STD_MATCH
-- MetaMatch, BooleanTableType, and MetaMatchTable are derivatives
-- of STD_MATCH from IEEE.Numeric_Std copyright by IEEE.
-- Numeric_Std is also released under the Apache License, Version 2.0.
-- Coding Styles were updated to match OSVVM
------------------------------------------------------------
type BooleanTableType is array(std_ulogic, std_ulogic) of boolean;
constant MetaMatchTable : BooleanTableType := (
--------------------------------------------------------------------------
-- U X 0 1 Z W L H -
--------------------------------------------------------------------------
(TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | U |
(FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | X |
(FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, TRUE), -- | 0 |
(FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, TRUE), -- | 1 |
(FALSE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE), -- | Z |
(FALSE, FALSE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, TRUE), -- | W |
(FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, TRUE), -- | L |
(FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, TRUE), -- | H |
(TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE) -- | - |
);
function MetaMatch (l, r : std_ulogic) return boolean is
begin
return MetaMatchTable(l, r);
end function MetaMatch;
function MetaMatch (L, R : std_ulogic_vector) return boolean is
alias aL : std_ulogic_vector(1 to L'length) is L;
alias aR : std_ulogic_vector(1 to R'length) is R;
begin
if aL'length /= aR'length then
--! log(OSVVM_ALERTLOG_ID, "AlertLogPkg.MetaMatch: Length Mismatch", DEBUG) ;
return FALSE;
else
for i in aL'range loop
if not (MetaMatchTable(aL(i), aR(i))) then
return FALSE;
end if;
end loop;
return TRUE;
end if;
end function MetaMatch;
function MetaMatch (L, R : unresolved_unsigned) return boolean is
begin
return MetaMatch( std_ulogic_vector(L), std_ulogic_vector(R)) ;
end function MetaMatch;
function MetaMatch (L, R : unresolved_signed) return boolean is
begin
return MetaMatch( std_ulogic_vector(L), std_ulogic_vector(R)) ;
end function MetaMatch;
-- synthesis translate_on
-- ------------------------------------------------------------
-- Deprecated
--
------------------------------------------------------------
-- deprecated
procedure AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) is
begin
-- synthesis translate_off
AlertIf( AlertLogID, condition, Message, Level) ;
-- synthesis translate_on
end procedure AlertIf ;
------------------------------------------------------------
-- deprecated
impure function AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean is
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertIf( AlertLogID, condition, Message, Level) ;
-- synthesis translate_on
return result ;
end function AlertIf ;
------------------------------------------------------------
-- deprecated
procedure AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) is
begin
-- synthesis translate_off
AlertIfNot( AlertLogID, condition, Message, Level) ;
-- synthesis translate_on
end procedure AlertIfNot ;
------------------------------------------------------------
-- deprecated
impure function AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean is
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertIfNot( AlertLogID, condition, Message, Level) ;
-- synthesis translate_on
return result ;
end function AlertIfNot ;
------------------------------------------------------------
-- deprecated
procedure AffirmIf(
AlertLogID : AlertLogIDType ;
condition : boolean ;
Message : string ;
LogLevel : LogType ; -- := PASSED
AlertLevel : AlertType := ERROR
) is
begin
-- synthesis translate_off
if condition then
-- PASSED. Count affirmations and PASSED internal to LOG to catch all of them
AlertLogStruct.Log(AlertLogID, Message, LogLevel) ; -- call log
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
AlertLogStruct.Alert(AlertLogID, Message, AlertLevel) ; -- signal failure
end if ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
-- deprecated
procedure AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; AlertLevel : AlertType ) is
begin
-- synthesis translate_off
AffirmIf(AlertLogID, condition, Message, PASSED, AlertLevel) ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
-- deprecated
procedure AffirmIf(condition : boolean ; Message : string ; LogLevel : LogType ; AlertLevel : AlertType := ERROR) is
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, Message, LogLevel, AlertLevel) ;
-- synthesis translate_on
end procedure AffirmIf;
------------------------------------------------------------
-- deprecated
procedure AffirmIf(condition : boolean ; Message : string ; AlertLevel : AlertType ) is
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, Message, PASSED, AlertLevel) ;
-- synthesis translate_on
end procedure AffirmIf;
end package body AlertLogPkg ; | artistic-2.0 | 95ddee203277ab94949d6a188079d3c1 | 0.536607 | 5.692179 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/582af9791eb33514/ip_design_lms_pcore_0_0_sim_netlist.vhdl | 1 | 877,760 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 18:54:20 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_lms_pcore_0_0_sim_netlist.vhdl
-- Design : ip_design_lms_pcore_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_LMS is
port (
mul_temp_16 : out STD_LOGIC_VECTOR ( 15 downto 0 );
filter_sum : out STD_LOGIC_VECTOR ( 15 downto 0 );
\write_reg_x_k_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
cop_dut_enable : in STD_LOGIC;
IPCORE_CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\write_reg_d_k_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
DI : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 14 downto 0 );
\write_reg_d_k_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\write_reg_d_k_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\write_reg_d_k_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_LMS;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_LMS is
signal \ARG__0_i_1_n_0\ : STD_LOGIC;
signal \ARG__0_n_100\ : STD_LOGIC;
signal \ARG__0_n_101\ : STD_LOGIC;
signal \ARG__0_n_102\ : STD_LOGIC;
signal \ARG__0_n_103\ : STD_LOGIC;
signal \ARG__0_n_104\ : STD_LOGIC;
signal \ARG__0_n_105\ : STD_LOGIC;
signal \ARG__0_n_92\ : STD_LOGIC;
signal \ARG__0_n_93\ : STD_LOGIC;
signal \ARG__0_n_94\ : STD_LOGIC;
signal \ARG__0_n_95\ : STD_LOGIC;
signal \ARG__0_n_96\ : STD_LOGIC;
signal \ARG__0_n_97\ : STD_LOGIC;
signal \ARG__0_n_98\ : STD_LOGIC;
signal \ARG__0_n_99\ : STD_LOGIC;
signal \ARG__10_i_1_n_0\ : STD_LOGIC;
signal \ARG__10_n_100\ : STD_LOGIC;
signal \ARG__10_n_101\ : STD_LOGIC;
signal \ARG__10_n_102\ : STD_LOGIC;
signal \ARG__10_n_103\ : STD_LOGIC;
signal \ARG__10_n_104\ : STD_LOGIC;
signal \ARG__10_n_105\ : STD_LOGIC;
signal \ARG__10_n_92\ : STD_LOGIC;
signal \ARG__10_n_93\ : STD_LOGIC;
signal \ARG__10_n_94\ : STD_LOGIC;
signal \ARG__10_n_95\ : STD_LOGIC;
signal \ARG__10_n_96\ : STD_LOGIC;
signal \ARG__10_n_97\ : STD_LOGIC;
signal \ARG__10_n_98\ : STD_LOGIC;
signal \ARG__10_n_99\ : STD_LOGIC;
signal \ARG__11_i_1_n_0\ : STD_LOGIC;
signal \ARG__11_n_100\ : STD_LOGIC;
signal \ARG__11_n_101\ : STD_LOGIC;
signal \ARG__11_n_102\ : STD_LOGIC;
signal \ARG__11_n_103\ : STD_LOGIC;
signal \ARG__11_n_104\ : STD_LOGIC;
signal \ARG__11_n_105\ : STD_LOGIC;
signal \ARG__11_n_76\ : STD_LOGIC;
signal \ARG__11_n_77\ : STD_LOGIC;
signal \ARG__11_n_78\ : STD_LOGIC;
signal \ARG__11_n_79\ : STD_LOGIC;
signal \ARG__11_n_80\ : STD_LOGIC;
signal \ARG__11_n_81\ : STD_LOGIC;
signal \ARG__11_n_82\ : STD_LOGIC;
signal \ARG__11_n_83\ : STD_LOGIC;
signal \ARG__11_n_84\ : STD_LOGIC;
signal \ARG__11_n_85\ : STD_LOGIC;
signal \ARG__11_n_86\ : STD_LOGIC;
signal \ARG__11_n_87\ : STD_LOGIC;
signal \ARG__11_n_88\ : STD_LOGIC;
signal \ARG__11_n_89\ : STD_LOGIC;
signal \ARG__11_n_90\ : STD_LOGIC;
signal \ARG__11_n_91\ : STD_LOGIC;
signal \ARG__11_n_92\ : STD_LOGIC;
signal \ARG__11_n_93\ : STD_LOGIC;
signal \ARG__11_n_94\ : STD_LOGIC;
signal \ARG__11_n_95\ : STD_LOGIC;
signal \ARG__11_n_96\ : STD_LOGIC;
signal \ARG__11_n_97\ : STD_LOGIC;
signal \ARG__11_n_98\ : STD_LOGIC;
signal \ARG__11_n_99\ : STD_LOGIC;
signal \ARG__12_i_1_n_0\ : STD_LOGIC;
signal \ARG__12_n_100\ : STD_LOGIC;
signal \ARG__12_n_101\ : STD_LOGIC;
signal \ARG__12_n_102\ : STD_LOGIC;
signal \ARG__12_n_103\ : STD_LOGIC;
signal \ARG__12_n_104\ : STD_LOGIC;
signal \ARG__12_n_105\ : STD_LOGIC;
signal \ARG__12_n_92\ : STD_LOGIC;
signal \ARG__12_n_93\ : STD_LOGIC;
signal \ARG__12_n_94\ : STD_LOGIC;
signal \ARG__12_n_95\ : STD_LOGIC;
signal \ARG__12_n_96\ : STD_LOGIC;
signal \ARG__12_n_97\ : STD_LOGIC;
signal \ARG__12_n_98\ : STD_LOGIC;
signal \ARG__12_n_99\ : STD_LOGIC;
signal \ARG__13_i_1_n_0\ : STD_LOGIC;
signal \ARG__13_n_100\ : STD_LOGIC;
signal \ARG__13_n_101\ : STD_LOGIC;
signal \ARG__13_n_102\ : STD_LOGIC;
signal \ARG__13_n_103\ : STD_LOGIC;
signal \ARG__13_n_104\ : STD_LOGIC;
signal \ARG__13_n_105\ : STD_LOGIC;
signal \ARG__13_n_76\ : STD_LOGIC;
signal \ARG__13_n_77\ : STD_LOGIC;
signal \ARG__13_n_78\ : STD_LOGIC;
signal \ARG__13_n_79\ : STD_LOGIC;
signal \ARG__13_n_80\ : STD_LOGIC;
signal \ARG__13_n_81\ : STD_LOGIC;
signal \ARG__13_n_82\ : STD_LOGIC;
signal \ARG__13_n_83\ : STD_LOGIC;
signal \ARG__13_n_84\ : STD_LOGIC;
signal \ARG__13_n_85\ : STD_LOGIC;
signal \ARG__13_n_86\ : STD_LOGIC;
signal \ARG__13_n_87\ : STD_LOGIC;
signal \ARG__13_n_88\ : STD_LOGIC;
signal \ARG__13_n_89\ : STD_LOGIC;
signal \ARG__13_n_90\ : STD_LOGIC;
signal \ARG__13_n_91\ : STD_LOGIC;
signal \ARG__13_n_92\ : STD_LOGIC;
signal \ARG__13_n_93\ : STD_LOGIC;
signal \ARG__13_n_94\ : STD_LOGIC;
signal \ARG__13_n_95\ : STD_LOGIC;
signal \ARG__13_n_96\ : STD_LOGIC;
signal \ARG__13_n_97\ : STD_LOGIC;
signal \ARG__13_n_98\ : STD_LOGIC;
signal \ARG__13_n_99\ : STD_LOGIC;
signal \ARG__14_i_1_n_0\ : STD_LOGIC;
signal \ARG__14_n_100\ : STD_LOGIC;
signal \ARG__14_n_101\ : STD_LOGIC;
signal \ARG__14_n_102\ : STD_LOGIC;
signal \ARG__14_n_103\ : STD_LOGIC;
signal \ARG__14_n_104\ : STD_LOGIC;
signal \ARG__14_n_105\ : STD_LOGIC;
signal \ARG__14_n_92\ : STD_LOGIC;
signal \ARG__14_n_93\ : STD_LOGIC;
signal \ARG__14_n_94\ : STD_LOGIC;
signal \ARG__14_n_95\ : STD_LOGIC;
signal \ARG__14_n_96\ : STD_LOGIC;
signal \ARG__14_n_97\ : STD_LOGIC;
signal \ARG__14_n_98\ : STD_LOGIC;
signal \ARG__14_n_99\ : STD_LOGIC;
signal \ARG__15_i_1_n_0\ : STD_LOGIC;
signal \ARG__15_n_100\ : STD_LOGIC;
signal \ARG__15_n_101\ : STD_LOGIC;
signal \ARG__15_n_102\ : STD_LOGIC;
signal \ARG__15_n_103\ : STD_LOGIC;
signal \ARG__15_n_104\ : STD_LOGIC;
signal \ARG__15_n_105\ : STD_LOGIC;
signal \ARG__15_n_76\ : STD_LOGIC;
signal \ARG__15_n_77\ : STD_LOGIC;
signal \ARG__15_n_78\ : STD_LOGIC;
signal \ARG__15_n_79\ : STD_LOGIC;
signal \ARG__15_n_80\ : STD_LOGIC;
signal \ARG__15_n_81\ : STD_LOGIC;
signal \ARG__15_n_82\ : STD_LOGIC;
signal \ARG__15_n_83\ : STD_LOGIC;
signal \ARG__15_n_84\ : STD_LOGIC;
signal \ARG__15_n_85\ : STD_LOGIC;
signal \ARG__15_n_86\ : STD_LOGIC;
signal \ARG__15_n_87\ : STD_LOGIC;
signal \ARG__15_n_88\ : STD_LOGIC;
signal \ARG__15_n_89\ : STD_LOGIC;
signal \ARG__15_n_90\ : STD_LOGIC;
signal \ARG__15_n_91\ : STD_LOGIC;
signal \ARG__15_n_92\ : STD_LOGIC;
signal \ARG__15_n_93\ : STD_LOGIC;
signal \ARG__15_n_94\ : STD_LOGIC;
signal \ARG__15_n_95\ : STD_LOGIC;
signal \ARG__15_n_96\ : STD_LOGIC;
signal \ARG__15_n_97\ : STD_LOGIC;
signal \ARG__15_n_98\ : STD_LOGIC;
signal \ARG__15_n_99\ : STD_LOGIC;
signal \ARG__16_i_1_n_0\ : STD_LOGIC;
signal \ARG__16_n_100\ : STD_LOGIC;
signal \ARG__16_n_101\ : STD_LOGIC;
signal \ARG__16_n_102\ : STD_LOGIC;
signal \ARG__16_n_103\ : STD_LOGIC;
signal \ARG__16_n_104\ : STD_LOGIC;
signal \ARG__16_n_105\ : STD_LOGIC;
signal \ARG__16_n_92\ : STD_LOGIC;
signal \ARG__16_n_93\ : STD_LOGIC;
signal \ARG__16_n_94\ : STD_LOGIC;
signal \ARG__16_n_95\ : STD_LOGIC;
signal \ARG__16_n_96\ : STD_LOGIC;
signal \ARG__16_n_97\ : STD_LOGIC;
signal \ARG__16_n_98\ : STD_LOGIC;
signal \ARG__16_n_99\ : STD_LOGIC;
signal \ARG__17_i_1_n_0\ : STD_LOGIC;
signal \ARG__17_n_100\ : STD_LOGIC;
signal \ARG__17_n_101\ : STD_LOGIC;
signal \ARG__17_n_102\ : STD_LOGIC;
signal \ARG__17_n_103\ : STD_LOGIC;
signal \ARG__17_n_104\ : STD_LOGIC;
signal \ARG__17_n_105\ : STD_LOGIC;
signal \ARG__17_n_76\ : STD_LOGIC;
signal \ARG__17_n_77\ : STD_LOGIC;
signal \ARG__17_n_78\ : STD_LOGIC;
signal \ARG__17_n_79\ : STD_LOGIC;
signal \ARG__17_n_80\ : STD_LOGIC;
signal \ARG__17_n_81\ : STD_LOGIC;
signal \ARG__17_n_82\ : STD_LOGIC;
signal \ARG__17_n_83\ : STD_LOGIC;
signal \ARG__17_n_84\ : STD_LOGIC;
signal \ARG__17_n_85\ : STD_LOGIC;
signal \ARG__17_n_86\ : STD_LOGIC;
signal \ARG__17_n_87\ : STD_LOGIC;
signal \ARG__17_n_88\ : STD_LOGIC;
signal \ARG__17_n_89\ : STD_LOGIC;
signal \ARG__17_n_90\ : STD_LOGIC;
signal \ARG__17_n_91\ : STD_LOGIC;
signal \ARG__17_n_92\ : STD_LOGIC;
signal \ARG__17_n_93\ : STD_LOGIC;
signal \ARG__17_n_94\ : STD_LOGIC;
signal \ARG__17_n_95\ : STD_LOGIC;
signal \ARG__17_n_96\ : STD_LOGIC;
signal \ARG__17_n_97\ : STD_LOGIC;
signal \ARG__17_n_98\ : STD_LOGIC;
signal \ARG__17_n_99\ : STD_LOGIC;
signal \ARG__18_i_1_n_0\ : STD_LOGIC;
signal \ARG__18_n_100\ : STD_LOGIC;
signal \ARG__18_n_101\ : STD_LOGIC;
signal \ARG__18_n_102\ : STD_LOGIC;
signal \ARG__18_n_103\ : STD_LOGIC;
signal \ARG__18_n_104\ : STD_LOGIC;
signal \ARG__18_n_105\ : STD_LOGIC;
signal \ARG__18_n_92\ : STD_LOGIC;
signal \ARG__18_n_93\ : STD_LOGIC;
signal \ARG__18_n_94\ : STD_LOGIC;
signal \ARG__18_n_95\ : STD_LOGIC;
signal \ARG__18_n_96\ : STD_LOGIC;
signal \ARG__18_n_97\ : STD_LOGIC;
signal \ARG__18_n_98\ : STD_LOGIC;
signal \ARG__18_n_99\ : STD_LOGIC;
signal \ARG__19_i_1_n_0\ : STD_LOGIC;
signal \ARG__19_n_100\ : STD_LOGIC;
signal \ARG__19_n_101\ : STD_LOGIC;
signal \ARG__19_n_102\ : STD_LOGIC;
signal \ARG__19_n_103\ : STD_LOGIC;
signal \ARG__19_n_104\ : STD_LOGIC;
signal \ARG__19_n_105\ : STD_LOGIC;
signal \ARG__19_n_76\ : STD_LOGIC;
signal \ARG__19_n_77\ : STD_LOGIC;
signal \ARG__19_n_78\ : STD_LOGIC;
signal \ARG__19_n_79\ : STD_LOGIC;
signal \ARG__19_n_80\ : STD_LOGIC;
signal \ARG__19_n_81\ : STD_LOGIC;
signal \ARG__19_n_82\ : STD_LOGIC;
signal \ARG__19_n_83\ : STD_LOGIC;
signal \ARG__19_n_84\ : STD_LOGIC;
signal \ARG__19_n_85\ : STD_LOGIC;
signal \ARG__19_n_86\ : STD_LOGIC;
signal \ARG__19_n_87\ : STD_LOGIC;
signal \ARG__19_n_88\ : STD_LOGIC;
signal \ARG__19_n_89\ : STD_LOGIC;
signal \ARG__19_n_90\ : STD_LOGIC;
signal \ARG__19_n_91\ : STD_LOGIC;
signal \ARG__19_n_92\ : STD_LOGIC;
signal \ARG__19_n_93\ : STD_LOGIC;
signal \ARG__19_n_94\ : STD_LOGIC;
signal \ARG__19_n_95\ : STD_LOGIC;
signal \ARG__19_n_96\ : STD_LOGIC;
signal \ARG__19_n_97\ : STD_LOGIC;
signal \ARG__19_n_98\ : STD_LOGIC;
signal \ARG__19_n_99\ : STD_LOGIC;
signal \ARG__1_i_1_n_0\ : STD_LOGIC;
signal \ARG__1_n_100\ : STD_LOGIC;
signal \ARG__1_n_101\ : STD_LOGIC;
signal \ARG__1_n_102\ : STD_LOGIC;
signal \ARG__1_n_103\ : STD_LOGIC;
signal \ARG__1_n_104\ : STD_LOGIC;
signal \ARG__1_n_105\ : STD_LOGIC;
signal \ARG__1_n_76\ : STD_LOGIC;
signal \ARG__1_n_77\ : STD_LOGIC;
signal \ARG__1_n_78\ : STD_LOGIC;
signal \ARG__1_n_79\ : STD_LOGIC;
signal \ARG__1_n_80\ : STD_LOGIC;
signal \ARG__1_n_81\ : STD_LOGIC;
signal \ARG__1_n_82\ : STD_LOGIC;
signal \ARG__1_n_83\ : STD_LOGIC;
signal \ARG__1_n_84\ : STD_LOGIC;
signal \ARG__1_n_85\ : STD_LOGIC;
signal \ARG__1_n_86\ : STD_LOGIC;
signal \ARG__1_n_87\ : STD_LOGIC;
signal \ARG__1_n_88\ : STD_LOGIC;
signal \ARG__1_n_89\ : STD_LOGIC;
signal \ARG__1_n_90\ : STD_LOGIC;
signal \ARG__1_n_91\ : STD_LOGIC;
signal \ARG__1_n_92\ : STD_LOGIC;
signal \ARG__1_n_93\ : STD_LOGIC;
signal \ARG__1_n_94\ : STD_LOGIC;
signal \ARG__1_n_95\ : STD_LOGIC;
signal \ARG__1_n_96\ : STD_LOGIC;
signal \ARG__1_n_97\ : STD_LOGIC;
signal \ARG__1_n_98\ : STD_LOGIC;
signal \ARG__1_n_99\ : STD_LOGIC;
signal \ARG__20_i_1_n_0\ : STD_LOGIC;
signal \ARG__20_n_100\ : STD_LOGIC;
signal \ARG__20_n_101\ : STD_LOGIC;
signal \ARG__20_n_102\ : STD_LOGIC;
signal \ARG__20_n_103\ : STD_LOGIC;
signal \ARG__20_n_104\ : STD_LOGIC;
signal \ARG__20_n_105\ : STD_LOGIC;
signal \ARG__20_n_92\ : STD_LOGIC;
signal \ARG__20_n_93\ : STD_LOGIC;
signal \ARG__20_n_94\ : STD_LOGIC;
signal \ARG__20_n_95\ : STD_LOGIC;
signal \ARG__20_n_96\ : STD_LOGIC;
signal \ARG__20_n_97\ : STD_LOGIC;
signal \ARG__20_n_98\ : STD_LOGIC;
signal \ARG__20_n_99\ : STD_LOGIC;
signal \ARG__21_i_1_n_0\ : STD_LOGIC;
signal \ARG__21_n_100\ : STD_LOGIC;
signal \ARG__21_n_101\ : STD_LOGIC;
signal \ARG__21_n_102\ : STD_LOGIC;
signal \ARG__21_n_103\ : STD_LOGIC;
signal \ARG__21_n_104\ : STD_LOGIC;
signal \ARG__21_n_105\ : STD_LOGIC;
signal \ARG__21_n_76\ : STD_LOGIC;
signal \ARG__21_n_77\ : STD_LOGIC;
signal \ARG__21_n_78\ : STD_LOGIC;
signal \ARG__21_n_79\ : STD_LOGIC;
signal \ARG__21_n_80\ : STD_LOGIC;
signal \ARG__21_n_81\ : STD_LOGIC;
signal \ARG__21_n_82\ : STD_LOGIC;
signal \ARG__21_n_83\ : STD_LOGIC;
signal \ARG__21_n_84\ : STD_LOGIC;
signal \ARG__21_n_85\ : STD_LOGIC;
signal \ARG__21_n_86\ : STD_LOGIC;
signal \ARG__21_n_87\ : STD_LOGIC;
signal \ARG__21_n_88\ : STD_LOGIC;
signal \ARG__21_n_89\ : STD_LOGIC;
signal \ARG__21_n_90\ : STD_LOGIC;
signal \ARG__21_n_91\ : STD_LOGIC;
signal \ARG__21_n_92\ : STD_LOGIC;
signal \ARG__21_n_93\ : STD_LOGIC;
signal \ARG__21_n_94\ : STD_LOGIC;
signal \ARG__21_n_95\ : STD_LOGIC;
signal \ARG__21_n_96\ : STD_LOGIC;
signal \ARG__21_n_97\ : STD_LOGIC;
signal \ARG__21_n_98\ : STD_LOGIC;
signal \ARG__21_n_99\ : STD_LOGIC;
signal \ARG__22_i_1_n_0\ : STD_LOGIC;
signal \ARG__22_n_100\ : STD_LOGIC;
signal \ARG__22_n_101\ : STD_LOGIC;
signal \ARG__22_n_102\ : STD_LOGIC;
signal \ARG__22_n_103\ : STD_LOGIC;
signal \ARG__22_n_104\ : STD_LOGIC;
signal \ARG__22_n_105\ : STD_LOGIC;
signal \ARG__22_n_92\ : STD_LOGIC;
signal \ARG__22_n_93\ : STD_LOGIC;
signal \ARG__22_n_94\ : STD_LOGIC;
signal \ARG__22_n_95\ : STD_LOGIC;
signal \ARG__22_n_96\ : STD_LOGIC;
signal \ARG__22_n_97\ : STD_LOGIC;
signal \ARG__22_n_98\ : STD_LOGIC;
signal \ARG__22_n_99\ : STD_LOGIC;
signal \ARG__23_i_1_n_0\ : STD_LOGIC;
signal \ARG__23_n_100\ : STD_LOGIC;
signal \ARG__23_n_101\ : STD_LOGIC;
signal \ARG__23_n_102\ : STD_LOGIC;
signal \ARG__23_n_103\ : STD_LOGIC;
signal \ARG__23_n_104\ : STD_LOGIC;
signal \ARG__23_n_105\ : STD_LOGIC;
signal \ARG__23_n_76\ : STD_LOGIC;
signal \ARG__23_n_77\ : STD_LOGIC;
signal \ARG__23_n_78\ : STD_LOGIC;
signal \ARG__23_n_79\ : STD_LOGIC;
signal \ARG__23_n_80\ : STD_LOGIC;
signal \ARG__23_n_81\ : STD_LOGIC;
signal \ARG__23_n_82\ : STD_LOGIC;
signal \ARG__23_n_83\ : STD_LOGIC;
signal \ARG__23_n_84\ : STD_LOGIC;
signal \ARG__23_n_85\ : STD_LOGIC;
signal \ARG__23_n_86\ : STD_LOGIC;
signal \ARG__23_n_87\ : STD_LOGIC;
signal \ARG__23_n_88\ : STD_LOGIC;
signal \ARG__23_n_89\ : STD_LOGIC;
signal \ARG__23_n_90\ : STD_LOGIC;
signal \ARG__23_n_91\ : STD_LOGIC;
signal \ARG__23_n_92\ : STD_LOGIC;
signal \ARG__23_n_93\ : STD_LOGIC;
signal \ARG__23_n_94\ : STD_LOGIC;
signal \ARG__23_n_95\ : STD_LOGIC;
signal \ARG__23_n_96\ : STD_LOGIC;
signal \ARG__23_n_97\ : STD_LOGIC;
signal \ARG__23_n_98\ : STD_LOGIC;
signal \ARG__23_n_99\ : STD_LOGIC;
signal \ARG__24_i_1_n_0\ : STD_LOGIC;
signal \ARG__24_n_100\ : STD_LOGIC;
signal \ARG__24_n_101\ : STD_LOGIC;
signal \ARG__24_n_102\ : STD_LOGIC;
signal \ARG__24_n_103\ : STD_LOGIC;
signal \ARG__24_n_104\ : STD_LOGIC;
signal \ARG__24_n_105\ : STD_LOGIC;
signal \ARG__24_n_92\ : STD_LOGIC;
signal \ARG__24_n_93\ : STD_LOGIC;
signal \ARG__24_n_94\ : STD_LOGIC;
signal \ARG__24_n_95\ : STD_LOGIC;
signal \ARG__24_n_96\ : STD_LOGIC;
signal \ARG__24_n_97\ : STD_LOGIC;
signal \ARG__24_n_98\ : STD_LOGIC;
signal \ARG__24_n_99\ : STD_LOGIC;
signal \ARG__25_i_1_n_0\ : STD_LOGIC;
signal \ARG__25_n_100\ : STD_LOGIC;
signal \ARG__25_n_101\ : STD_LOGIC;
signal \ARG__25_n_102\ : STD_LOGIC;
signal \ARG__25_n_103\ : STD_LOGIC;
signal \ARG__25_n_104\ : STD_LOGIC;
signal \ARG__25_n_105\ : STD_LOGIC;
signal \ARG__25_n_76\ : STD_LOGIC;
signal \ARG__25_n_77\ : STD_LOGIC;
signal \ARG__25_n_78\ : STD_LOGIC;
signal \ARG__25_n_79\ : STD_LOGIC;
signal \ARG__25_n_80\ : STD_LOGIC;
signal \ARG__25_n_81\ : STD_LOGIC;
signal \ARG__25_n_82\ : STD_LOGIC;
signal \ARG__25_n_83\ : STD_LOGIC;
signal \ARG__25_n_84\ : STD_LOGIC;
signal \ARG__25_n_85\ : STD_LOGIC;
signal \ARG__25_n_86\ : STD_LOGIC;
signal \ARG__25_n_87\ : STD_LOGIC;
signal \ARG__25_n_88\ : STD_LOGIC;
signal \ARG__25_n_89\ : STD_LOGIC;
signal \ARG__25_n_90\ : STD_LOGIC;
signal \ARG__25_n_91\ : STD_LOGIC;
signal \ARG__25_n_92\ : STD_LOGIC;
signal \ARG__25_n_93\ : STD_LOGIC;
signal \ARG__25_n_94\ : STD_LOGIC;
signal \ARG__25_n_95\ : STD_LOGIC;
signal \ARG__25_n_96\ : STD_LOGIC;
signal \ARG__25_n_97\ : STD_LOGIC;
signal \ARG__25_n_98\ : STD_LOGIC;
signal \ARG__25_n_99\ : STD_LOGIC;
signal \ARG__26_i_1_n_0\ : STD_LOGIC;
signal \ARG__26_n_100\ : STD_LOGIC;
signal \ARG__26_n_101\ : STD_LOGIC;
signal \ARG__26_n_102\ : STD_LOGIC;
signal \ARG__26_n_103\ : STD_LOGIC;
signal \ARG__26_n_104\ : STD_LOGIC;
signal \ARG__26_n_105\ : STD_LOGIC;
signal \ARG__26_n_92\ : STD_LOGIC;
signal \ARG__26_n_93\ : STD_LOGIC;
signal \ARG__26_n_94\ : STD_LOGIC;
signal \ARG__26_n_95\ : STD_LOGIC;
signal \ARG__26_n_96\ : STD_LOGIC;
signal \ARG__26_n_97\ : STD_LOGIC;
signal \ARG__26_n_98\ : STD_LOGIC;
signal \ARG__26_n_99\ : STD_LOGIC;
signal \ARG__27_i_1_n_0\ : STD_LOGIC;
signal \ARG__27_n_100\ : STD_LOGIC;
signal \ARG__27_n_101\ : STD_LOGIC;
signal \ARG__27_n_102\ : STD_LOGIC;
signal \ARG__27_n_103\ : STD_LOGIC;
signal \ARG__27_n_104\ : STD_LOGIC;
signal \ARG__27_n_105\ : STD_LOGIC;
signal \ARG__27_n_76\ : STD_LOGIC;
signal \ARG__27_n_77\ : STD_LOGIC;
signal \ARG__27_n_78\ : STD_LOGIC;
signal \ARG__27_n_79\ : STD_LOGIC;
signal \ARG__27_n_80\ : STD_LOGIC;
signal \ARG__27_n_81\ : STD_LOGIC;
signal \ARG__27_n_82\ : STD_LOGIC;
signal \ARG__27_n_83\ : STD_LOGIC;
signal \ARG__27_n_84\ : STD_LOGIC;
signal \ARG__27_n_85\ : STD_LOGIC;
signal \ARG__27_n_86\ : STD_LOGIC;
signal \ARG__27_n_87\ : STD_LOGIC;
signal \ARG__27_n_88\ : STD_LOGIC;
signal \ARG__27_n_89\ : STD_LOGIC;
signal \ARG__27_n_90\ : STD_LOGIC;
signal \ARG__27_n_91\ : STD_LOGIC;
signal \ARG__27_n_92\ : STD_LOGIC;
signal \ARG__27_n_93\ : STD_LOGIC;
signal \ARG__27_n_94\ : STD_LOGIC;
signal \ARG__27_n_95\ : STD_LOGIC;
signal \ARG__27_n_96\ : STD_LOGIC;
signal \ARG__27_n_97\ : STD_LOGIC;
signal \ARG__27_n_98\ : STD_LOGIC;
signal \ARG__27_n_99\ : STD_LOGIC;
signal \ARG__28_i_1_n_0\ : STD_LOGIC;
signal \ARG__28_n_100\ : STD_LOGIC;
signal \ARG__28_n_101\ : STD_LOGIC;
signal \ARG__28_n_102\ : STD_LOGIC;
signal \ARG__28_n_103\ : STD_LOGIC;
signal \ARG__28_n_104\ : STD_LOGIC;
signal \ARG__28_n_105\ : STD_LOGIC;
signal \ARG__28_n_92\ : STD_LOGIC;
signal \ARG__28_n_93\ : STD_LOGIC;
signal \ARG__28_n_94\ : STD_LOGIC;
signal \ARG__28_n_95\ : STD_LOGIC;
signal \ARG__28_n_96\ : STD_LOGIC;
signal \ARG__28_n_97\ : STD_LOGIC;
signal \ARG__28_n_98\ : STD_LOGIC;
signal \ARG__28_n_99\ : STD_LOGIC;
signal \ARG__29_i_1_n_0\ : STD_LOGIC;
signal \ARG__29_n_100\ : STD_LOGIC;
signal \ARG__29_n_101\ : STD_LOGIC;
signal \ARG__29_n_102\ : STD_LOGIC;
signal \ARG__29_n_103\ : STD_LOGIC;
signal \ARG__29_n_104\ : STD_LOGIC;
signal \ARG__29_n_105\ : STD_LOGIC;
signal \ARG__29_n_76\ : STD_LOGIC;
signal \ARG__29_n_77\ : STD_LOGIC;
signal \ARG__29_n_78\ : STD_LOGIC;
signal \ARG__29_n_79\ : STD_LOGIC;
signal \ARG__29_n_80\ : STD_LOGIC;
signal \ARG__29_n_81\ : STD_LOGIC;
signal \ARG__29_n_82\ : STD_LOGIC;
signal \ARG__29_n_83\ : STD_LOGIC;
signal \ARG__29_n_84\ : STD_LOGIC;
signal \ARG__29_n_85\ : STD_LOGIC;
signal \ARG__29_n_86\ : STD_LOGIC;
signal \ARG__29_n_87\ : STD_LOGIC;
signal \ARG__29_n_88\ : STD_LOGIC;
signal \ARG__29_n_89\ : STD_LOGIC;
signal \ARG__29_n_90\ : STD_LOGIC;
signal \ARG__29_n_91\ : STD_LOGIC;
signal \ARG__29_n_92\ : STD_LOGIC;
signal \ARG__29_n_93\ : STD_LOGIC;
signal \ARG__29_n_94\ : STD_LOGIC;
signal \ARG__29_n_95\ : STD_LOGIC;
signal \ARG__29_n_96\ : STD_LOGIC;
signal \ARG__29_n_97\ : STD_LOGIC;
signal \ARG__29_n_98\ : STD_LOGIC;
signal \ARG__29_n_99\ : STD_LOGIC;
signal \ARG__2_i_1_n_0\ : STD_LOGIC;
signal \ARG__2_n_100\ : STD_LOGIC;
signal \ARG__2_n_101\ : STD_LOGIC;
signal \ARG__2_n_102\ : STD_LOGIC;
signal \ARG__2_n_103\ : STD_LOGIC;
signal \ARG__2_n_104\ : STD_LOGIC;
signal \ARG__2_n_105\ : STD_LOGIC;
signal \ARG__2_n_92\ : STD_LOGIC;
signal \ARG__2_n_93\ : STD_LOGIC;
signal \ARG__2_n_94\ : STD_LOGIC;
signal \ARG__2_n_95\ : STD_LOGIC;
signal \ARG__2_n_96\ : STD_LOGIC;
signal \ARG__2_n_97\ : STD_LOGIC;
signal \ARG__2_n_98\ : STD_LOGIC;
signal \ARG__2_n_99\ : STD_LOGIC;
signal \ARG__30_i_1_n_0\ : STD_LOGIC;
signal \ARG__30_n_100\ : STD_LOGIC;
signal \ARG__30_n_101\ : STD_LOGIC;
signal \ARG__30_n_102\ : STD_LOGIC;
signal \ARG__30_n_103\ : STD_LOGIC;
signal \ARG__30_n_104\ : STD_LOGIC;
signal \ARG__30_n_105\ : STD_LOGIC;
signal \ARG__30_n_92\ : STD_LOGIC;
signal \ARG__30_n_93\ : STD_LOGIC;
signal \ARG__30_n_94\ : STD_LOGIC;
signal \ARG__30_n_95\ : STD_LOGIC;
signal \ARG__30_n_96\ : STD_LOGIC;
signal \ARG__30_n_97\ : STD_LOGIC;
signal \ARG__30_n_98\ : STD_LOGIC;
signal \ARG__30_n_99\ : STD_LOGIC;
signal \ARG__31\ : STD_LOGIC_VECTOR ( 32 downto 17 );
signal \ARG__3_i_1_n_0\ : STD_LOGIC;
signal \ARG__3_n_100\ : STD_LOGIC;
signal \ARG__3_n_101\ : STD_LOGIC;
signal \ARG__3_n_102\ : STD_LOGIC;
signal \ARG__3_n_103\ : STD_LOGIC;
signal \ARG__3_n_104\ : STD_LOGIC;
signal \ARG__3_n_105\ : STD_LOGIC;
signal \ARG__3_n_76\ : STD_LOGIC;
signal \ARG__3_n_77\ : STD_LOGIC;
signal \ARG__3_n_78\ : STD_LOGIC;
signal \ARG__3_n_79\ : STD_LOGIC;
signal \ARG__3_n_80\ : STD_LOGIC;
signal \ARG__3_n_81\ : STD_LOGIC;
signal \ARG__3_n_82\ : STD_LOGIC;
signal \ARG__3_n_83\ : STD_LOGIC;
signal \ARG__3_n_84\ : STD_LOGIC;
signal \ARG__3_n_85\ : STD_LOGIC;
signal \ARG__3_n_86\ : STD_LOGIC;
signal \ARG__3_n_87\ : STD_LOGIC;
signal \ARG__3_n_88\ : STD_LOGIC;
signal \ARG__3_n_89\ : STD_LOGIC;
signal \ARG__3_n_90\ : STD_LOGIC;
signal \ARG__3_n_91\ : STD_LOGIC;
signal \ARG__3_n_92\ : STD_LOGIC;
signal \ARG__3_n_93\ : STD_LOGIC;
signal \ARG__3_n_94\ : STD_LOGIC;
signal \ARG__3_n_95\ : STD_LOGIC;
signal \ARG__3_n_96\ : STD_LOGIC;
signal \ARG__3_n_97\ : STD_LOGIC;
signal \ARG__3_n_98\ : STD_LOGIC;
signal \ARG__3_n_99\ : STD_LOGIC;
signal \ARG__4_i_1_n_0\ : STD_LOGIC;
signal \ARG__4_n_100\ : STD_LOGIC;
signal \ARG__4_n_101\ : STD_LOGIC;
signal \ARG__4_n_102\ : STD_LOGIC;
signal \ARG__4_n_103\ : STD_LOGIC;
signal \ARG__4_n_104\ : STD_LOGIC;
signal \ARG__4_n_105\ : STD_LOGIC;
signal \ARG__4_n_92\ : STD_LOGIC;
signal \ARG__4_n_93\ : STD_LOGIC;
signal \ARG__4_n_94\ : STD_LOGIC;
signal \ARG__4_n_95\ : STD_LOGIC;
signal \ARG__4_n_96\ : STD_LOGIC;
signal \ARG__4_n_97\ : STD_LOGIC;
signal \ARG__4_n_98\ : STD_LOGIC;
signal \ARG__4_n_99\ : STD_LOGIC;
signal \ARG__5_i_1_n_0\ : STD_LOGIC;
signal \ARG__5_n_100\ : STD_LOGIC;
signal \ARG__5_n_101\ : STD_LOGIC;
signal \ARG__5_n_102\ : STD_LOGIC;
signal \ARG__5_n_103\ : STD_LOGIC;
signal \ARG__5_n_104\ : STD_LOGIC;
signal \ARG__5_n_105\ : STD_LOGIC;
signal \ARG__5_n_76\ : STD_LOGIC;
signal \ARG__5_n_77\ : STD_LOGIC;
signal \ARG__5_n_78\ : STD_LOGIC;
signal \ARG__5_n_79\ : STD_LOGIC;
signal \ARG__5_n_80\ : STD_LOGIC;
signal \ARG__5_n_81\ : STD_LOGIC;
signal \ARG__5_n_82\ : STD_LOGIC;
signal \ARG__5_n_83\ : STD_LOGIC;
signal \ARG__5_n_84\ : STD_LOGIC;
signal \ARG__5_n_85\ : STD_LOGIC;
signal \ARG__5_n_86\ : STD_LOGIC;
signal \ARG__5_n_87\ : STD_LOGIC;
signal \ARG__5_n_88\ : STD_LOGIC;
signal \ARG__5_n_89\ : STD_LOGIC;
signal \ARG__5_n_90\ : STD_LOGIC;
signal \ARG__5_n_91\ : STD_LOGIC;
signal \ARG__5_n_92\ : STD_LOGIC;
signal \ARG__5_n_93\ : STD_LOGIC;
signal \ARG__5_n_94\ : STD_LOGIC;
signal \ARG__5_n_95\ : STD_LOGIC;
signal \ARG__5_n_96\ : STD_LOGIC;
signal \ARG__5_n_97\ : STD_LOGIC;
signal \ARG__5_n_98\ : STD_LOGIC;
signal \ARG__5_n_99\ : STD_LOGIC;
signal \ARG__6_i_1_n_0\ : STD_LOGIC;
signal \ARG__6_n_100\ : STD_LOGIC;
signal \ARG__6_n_101\ : STD_LOGIC;
signal \ARG__6_n_102\ : STD_LOGIC;
signal \ARG__6_n_103\ : STD_LOGIC;
signal \ARG__6_n_104\ : STD_LOGIC;
signal \ARG__6_n_105\ : STD_LOGIC;
signal \ARG__6_n_92\ : STD_LOGIC;
signal \ARG__6_n_93\ : STD_LOGIC;
signal \ARG__6_n_94\ : STD_LOGIC;
signal \ARG__6_n_95\ : STD_LOGIC;
signal \ARG__6_n_96\ : STD_LOGIC;
signal \ARG__6_n_97\ : STD_LOGIC;
signal \ARG__6_n_98\ : STD_LOGIC;
signal \ARG__6_n_99\ : STD_LOGIC;
signal \ARG__7_i_1_n_0\ : STD_LOGIC;
signal \ARG__7_n_100\ : STD_LOGIC;
signal \ARG__7_n_101\ : STD_LOGIC;
signal \ARG__7_n_102\ : STD_LOGIC;
signal \ARG__7_n_103\ : STD_LOGIC;
signal \ARG__7_n_104\ : STD_LOGIC;
signal \ARG__7_n_105\ : STD_LOGIC;
signal \ARG__7_n_76\ : STD_LOGIC;
signal \ARG__7_n_77\ : STD_LOGIC;
signal \ARG__7_n_78\ : STD_LOGIC;
signal \ARG__7_n_79\ : STD_LOGIC;
signal \ARG__7_n_80\ : STD_LOGIC;
signal \ARG__7_n_81\ : STD_LOGIC;
signal \ARG__7_n_82\ : STD_LOGIC;
signal \ARG__7_n_83\ : STD_LOGIC;
signal \ARG__7_n_84\ : STD_LOGIC;
signal \ARG__7_n_85\ : STD_LOGIC;
signal \ARG__7_n_86\ : STD_LOGIC;
signal \ARG__7_n_87\ : STD_LOGIC;
signal \ARG__7_n_88\ : STD_LOGIC;
signal \ARG__7_n_89\ : STD_LOGIC;
signal \ARG__7_n_90\ : STD_LOGIC;
signal \ARG__7_n_91\ : STD_LOGIC;
signal \ARG__7_n_92\ : STD_LOGIC;
signal \ARG__7_n_93\ : STD_LOGIC;
signal \ARG__7_n_94\ : STD_LOGIC;
signal \ARG__7_n_95\ : STD_LOGIC;
signal \ARG__7_n_96\ : STD_LOGIC;
signal \ARG__7_n_97\ : STD_LOGIC;
signal \ARG__7_n_98\ : STD_LOGIC;
signal \ARG__7_n_99\ : STD_LOGIC;
signal \ARG__8_i_1_n_0\ : STD_LOGIC;
signal \ARG__8_n_100\ : STD_LOGIC;
signal \ARG__8_n_101\ : STD_LOGIC;
signal \ARG__8_n_102\ : STD_LOGIC;
signal \ARG__8_n_103\ : STD_LOGIC;
signal \ARG__8_n_104\ : STD_LOGIC;
signal \ARG__8_n_105\ : STD_LOGIC;
signal \ARG__8_n_92\ : STD_LOGIC;
signal \ARG__8_n_93\ : STD_LOGIC;
signal \ARG__8_n_94\ : STD_LOGIC;
signal \ARG__8_n_95\ : STD_LOGIC;
signal \ARG__8_n_96\ : STD_LOGIC;
signal \ARG__8_n_97\ : STD_LOGIC;
signal \ARG__8_n_98\ : STD_LOGIC;
signal \ARG__8_n_99\ : STD_LOGIC;
signal \ARG__9_i_1_n_0\ : STD_LOGIC;
signal \ARG__9_n_100\ : STD_LOGIC;
signal \ARG__9_n_101\ : STD_LOGIC;
signal \ARG__9_n_102\ : STD_LOGIC;
signal \ARG__9_n_103\ : STD_LOGIC;
signal \ARG__9_n_104\ : STD_LOGIC;
signal \ARG__9_n_105\ : STD_LOGIC;
signal \ARG__9_n_76\ : STD_LOGIC;
signal \ARG__9_n_77\ : STD_LOGIC;
signal \ARG__9_n_78\ : STD_LOGIC;
signal \ARG__9_n_79\ : STD_LOGIC;
signal \ARG__9_n_80\ : STD_LOGIC;
signal \ARG__9_n_81\ : STD_LOGIC;
signal \ARG__9_n_82\ : STD_LOGIC;
signal \ARG__9_n_83\ : STD_LOGIC;
signal \ARG__9_n_84\ : STD_LOGIC;
signal \ARG__9_n_85\ : STD_LOGIC;
signal \ARG__9_n_86\ : STD_LOGIC;
signal \ARG__9_n_87\ : STD_LOGIC;
signal \ARG__9_n_88\ : STD_LOGIC;
signal \ARG__9_n_89\ : STD_LOGIC;
signal \ARG__9_n_90\ : STD_LOGIC;
signal \ARG__9_n_91\ : STD_LOGIC;
signal \ARG__9_n_92\ : STD_LOGIC;
signal \ARG__9_n_93\ : STD_LOGIC;
signal \ARG__9_n_94\ : STD_LOGIC;
signal \ARG__9_n_95\ : STD_LOGIC;
signal \ARG__9_n_96\ : STD_LOGIC;
signal \ARG__9_n_97\ : STD_LOGIC;
signal \ARG__9_n_98\ : STD_LOGIC;
signal \ARG__9_n_99\ : STD_LOGIC;
signal \ARG_carry__0_i_2_n_0\ : STD_LOGIC;
signal \ARG_carry__0_i_3_n_0\ : STD_LOGIC;
signal \ARG_carry__0_i_4_n_0\ : STD_LOGIC;
signal \ARG_carry__0_n_0\ : STD_LOGIC;
signal \ARG_carry__0_n_1\ : STD_LOGIC;
signal \ARG_carry__0_n_2\ : STD_LOGIC;
signal \ARG_carry__0_n_3\ : STD_LOGIC;
signal \ARG_carry__1_i_1_n_0\ : STD_LOGIC;
signal \ARG_carry__1_i_2_n_0\ : STD_LOGIC;
signal \ARG_carry__1_i_3_n_0\ : STD_LOGIC;
signal \ARG_carry__1_i_4_n_0\ : STD_LOGIC;
signal \ARG_carry__1_n_0\ : STD_LOGIC;
signal \ARG_carry__1_n_1\ : STD_LOGIC;
signal \ARG_carry__1_n_2\ : STD_LOGIC;
signal \ARG_carry__1_n_3\ : STD_LOGIC;
signal \ARG_carry__2_i_1_n_0\ : STD_LOGIC;
signal \ARG_carry__2_i_2_n_0\ : STD_LOGIC;
signal \ARG_carry__2_i_3_n_0\ : STD_LOGIC;
signal \ARG_carry__2_i_4_n_0\ : STD_LOGIC;
signal \ARG_carry__2_n_0\ : STD_LOGIC;
signal \ARG_carry__2_n_1\ : STD_LOGIC;
signal \ARG_carry__2_n_2\ : STD_LOGIC;
signal \ARG_carry__2_n_3\ : STD_LOGIC;
signal \ARG_carry__3_i_1_n_0\ : STD_LOGIC;
signal \ARG_carry__3_n_3\ : STD_LOGIC;
signal ARG_carry_n_0 : STD_LOGIC;
signal ARG_carry_n_1 : STD_LOGIC;
signal ARG_carry_n_2 : STD_LOGIC;
signal ARG_carry_n_3 : STD_LOGIC;
signal ARG_i_1_n_0 : STD_LOGIC;
signal ARG_n_100 : STD_LOGIC;
signal ARG_n_101 : STD_LOGIC;
signal ARG_n_102 : STD_LOGIC;
signal ARG_n_103 : STD_LOGIC;
signal ARG_n_104 : STD_LOGIC;
signal ARG_n_105 : STD_LOGIC;
signal ARG_n_92 : STD_LOGIC;
signal ARG_n_93 : STD_LOGIC;
signal ARG_n_94 : STD_LOGIC;
signal ARG_n_95 : STD_LOGIC;
signal ARG_n_96 : STD_LOGIC;
signal ARG_n_97 : STD_LOGIC;
signal ARG_n_98 : STD_LOGIC;
signal ARG_n_99 : STD_LOGIC;
signal RESIZE15 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE16 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE18 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE20 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE22 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE24 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE26 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE28 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE30 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE32 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE34 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE36 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE38 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE40 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE42 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE44 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \add_temp_14__0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_10_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_11_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_12_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_9_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_10_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_11_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_12_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_9_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_10_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_11_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_9_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_10_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_9_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__278_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__278_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_7\ : STD_LOGIC;
signal \data_pipeline_tmp_reg[0]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[10]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[11]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[12]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[13]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[14]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[1]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[2]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[3]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[4]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[5]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[6]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[7]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[8]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[9]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \in\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^mul_temp\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mul_temp_1\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mul_temp_10\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_10_n_100 : STD_LOGIC;
signal mul_temp_10_n_101 : STD_LOGIC;
signal mul_temp_10_n_102 : STD_LOGIC;
signal mul_temp_10_n_103 : STD_LOGIC;
signal mul_temp_10_n_104 : STD_LOGIC;
signal mul_temp_10_n_105 : STD_LOGIC;
signal mul_temp_10_n_74 : STD_LOGIC;
signal mul_temp_10_n_75 : STD_LOGIC;
signal mul_temp_10_n_76 : STD_LOGIC;
signal mul_temp_10_n_77 : STD_LOGIC;
signal mul_temp_10_n_78 : STD_LOGIC;
signal mul_temp_10_n_79 : STD_LOGIC;
signal mul_temp_10_n_80 : STD_LOGIC;
signal mul_temp_10_n_81 : STD_LOGIC;
signal mul_temp_10_n_82 : STD_LOGIC;
signal mul_temp_10_n_83 : STD_LOGIC;
signal mul_temp_10_n_84 : STD_LOGIC;
signal mul_temp_10_n_85 : STD_LOGIC;
signal mul_temp_10_n_86 : STD_LOGIC;
signal mul_temp_10_n_87 : STD_LOGIC;
signal mul_temp_10_n_88 : STD_LOGIC;
signal mul_temp_10_n_89 : STD_LOGIC;
signal mul_temp_10_n_90 : STD_LOGIC;
signal mul_temp_10_n_92 : STD_LOGIC;
signal mul_temp_10_n_93 : STD_LOGIC;
signal mul_temp_10_n_94 : STD_LOGIC;
signal mul_temp_10_n_95 : STD_LOGIC;
signal mul_temp_10_n_96 : STD_LOGIC;
signal mul_temp_10_n_97 : STD_LOGIC;
signal mul_temp_10_n_98 : STD_LOGIC;
signal mul_temp_10_n_99 : STD_LOGIC;
signal \^mul_temp_11\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_11_n_100 : STD_LOGIC;
signal mul_temp_11_n_101 : STD_LOGIC;
signal mul_temp_11_n_102 : STD_LOGIC;
signal mul_temp_11_n_103 : STD_LOGIC;
signal mul_temp_11_n_104 : STD_LOGIC;
signal mul_temp_11_n_105 : STD_LOGIC;
signal mul_temp_11_n_74 : STD_LOGIC;
signal mul_temp_11_n_75 : STD_LOGIC;
signal mul_temp_11_n_76 : STD_LOGIC;
signal mul_temp_11_n_77 : STD_LOGIC;
signal mul_temp_11_n_78 : STD_LOGIC;
signal mul_temp_11_n_79 : STD_LOGIC;
signal mul_temp_11_n_80 : STD_LOGIC;
signal mul_temp_11_n_81 : STD_LOGIC;
signal mul_temp_11_n_82 : STD_LOGIC;
signal mul_temp_11_n_83 : STD_LOGIC;
signal mul_temp_11_n_84 : STD_LOGIC;
signal mul_temp_11_n_85 : STD_LOGIC;
signal mul_temp_11_n_86 : STD_LOGIC;
signal mul_temp_11_n_87 : STD_LOGIC;
signal mul_temp_11_n_88 : STD_LOGIC;
signal mul_temp_11_n_89 : STD_LOGIC;
signal mul_temp_11_n_90 : STD_LOGIC;
signal mul_temp_11_n_92 : STD_LOGIC;
signal mul_temp_11_n_93 : STD_LOGIC;
signal mul_temp_11_n_94 : STD_LOGIC;
signal mul_temp_11_n_95 : STD_LOGIC;
signal mul_temp_11_n_96 : STD_LOGIC;
signal mul_temp_11_n_97 : STD_LOGIC;
signal mul_temp_11_n_98 : STD_LOGIC;
signal mul_temp_11_n_99 : STD_LOGIC;
signal \^mul_temp_12\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_12_n_100 : STD_LOGIC;
signal mul_temp_12_n_101 : STD_LOGIC;
signal mul_temp_12_n_102 : STD_LOGIC;
signal mul_temp_12_n_103 : STD_LOGIC;
signal mul_temp_12_n_104 : STD_LOGIC;
signal mul_temp_12_n_105 : STD_LOGIC;
signal mul_temp_12_n_74 : STD_LOGIC;
signal mul_temp_12_n_75 : STD_LOGIC;
signal mul_temp_12_n_76 : STD_LOGIC;
signal mul_temp_12_n_77 : STD_LOGIC;
signal mul_temp_12_n_78 : STD_LOGIC;
signal mul_temp_12_n_79 : STD_LOGIC;
signal mul_temp_12_n_80 : STD_LOGIC;
signal mul_temp_12_n_81 : STD_LOGIC;
signal mul_temp_12_n_82 : STD_LOGIC;
signal mul_temp_12_n_83 : STD_LOGIC;
signal mul_temp_12_n_84 : STD_LOGIC;
signal mul_temp_12_n_85 : STD_LOGIC;
signal mul_temp_12_n_86 : STD_LOGIC;
signal mul_temp_12_n_87 : STD_LOGIC;
signal mul_temp_12_n_88 : STD_LOGIC;
signal mul_temp_12_n_89 : STD_LOGIC;
signal mul_temp_12_n_90 : STD_LOGIC;
signal mul_temp_12_n_92 : STD_LOGIC;
signal mul_temp_12_n_93 : STD_LOGIC;
signal mul_temp_12_n_94 : STD_LOGIC;
signal mul_temp_12_n_95 : STD_LOGIC;
signal mul_temp_12_n_96 : STD_LOGIC;
signal mul_temp_12_n_97 : STD_LOGIC;
signal mul_temp_12_n_98 : STD_LOGIC;
signal mul_temp_12_n_99 : STD_LOGIC;
signal \^mul_temp_13\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_13_n_100 : STD_LOGIC;
signal mul_temp_13_n_101 : STD_LOGIC;
signal mul_temp_13_n_102 : STD_LOGIC;
signal mul_temp_13_n_103 : STD_LOGIC;
signal mul_temp_13_n_104 : STD_LOGIC;
signal mul_temp_13_n_105 : STD_LOGIC;
signal mul_temp_13_n_74 : STD_LOGIC;
signal mul_temp_13_n_75 : STD_LOGIC;
signal mul_temp_13_n_76 : STD_LOGIC;
signal mul_temp_13_n_77 : STD_LOGIC;
signal mul_temp_13_n_78 : STD_LOGIC;
signal mul_temp_13_n_79 : STD_LOGIC;
signal mul_temp_13_n_80 : STD_LOGIC;
signal mul_temp_13_n_81 : STD_LOGIC;
signal mul_temp_13_n_82 : STD_LOGIC;
signal mul_temp_13_n_83 : STD_LOGIC;
signal mul_temp_13_n_84 : STD_LOGIC;
signal mul_temp_13_n_85 : STD_LOGIC;
signal mul_temp_13_n_86 : STD_LOGIC;
signal mul_temp_13_n_87 : STD_LOGIC;
signal mul_temp_13_n_88 : STD_LOGIC;
signal mul_temp_13_n_89 : STD_LOGIC;
signal mul_temp_13_n_90 : STD_LOGIC;
signal mul_temp_13_n_92 : STD_LOGIC;
signal mul_temp_13_n_93 : STD_LOGIC;
signal mul_temp_13_n_94 : STD_LOGIC;
signal mul_temp_13_n_95 : STD_LOGIC;
signal mul_temp_13_n_96 : STD_LOGIC;
signal mul_temp_13_n_97 : STD_LOGIC;
signal mul_temp_13_n_98 : STD_LOGIC;
signal mul_temp_13_n_99 : STD_LOGIC;
signal \^mul_temp_14\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_14_n_100 : STD_LOGIC;
signal mul_temp_14_n_101 : STD_LOGIC;
signal mul_temp_14_n_102 : STD_LOGIC;
signal mul_temp_14_n_103 : STD_LOGIC;
signal mul_temp_14_n_104 : STD_LOGIC;
signal mul_temp_14_n_105 : STD_LOGIC;
signal mul_temp_14_n_74 : STD_LOGIC;
signal mul_temp_14_n_75 : STD_LOGIC;
signal mul_temp_14_n_76 : STD_LOGIC;
signal mul_temp_14_n_77 : STD_LOGIC;
signal mul_temp_14_n_78 : STD_LOGIC;
signal mul_temp_14_n_79 : STD_LOGIC;
signal mul_temp_14_n_80 : STD_LOGIC;
signal mul_temp_14_n_81 : STD_LOGIC;
signal mul_temp_14_n_82 : STD_LOGIC;
signal mul_temp_14_n_83 : STD_LOGIC;
signal mul_temp_14_n_84 : STD_LOGIC;
signal mul_temp_14_n_85 : STD_LOGIC;
signal mul_temp_14_n_86 : STD_LOGIC;
signal mul_temp_14_n_87 : STD_LOGIC;
signal mul_temp_14_n_88 : STD_LOGIC;
signal mul_temp_14_n_89 : STD_LOGIC;
signal mul_temp_14_n_90 : STD_LOGIC;
signal mul_temp_14_n_92 : STD_LOGIC;
signal mul_temp_14_n_93 : STD_LOGIC;
signal mul_temp_14_n_94 : STD_LOGIC;
signal mul_temp_14_n_95 : STD_LOGIC;
signal mul_temp_14_n_96 : STD_LOGIC;
signal mul_temp_14_n_97 : STD_LOGIC;
signal mul_temp_14_n_98 : STD_LOGIC;
signal mul_temp_14_n_99 : STD_LOGIC;
signal \^mul_temp_15\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_15_n_100 : STD_LOGIC;
signal mul_temp_15_n_101 : STD_LOGIC;
signal mul_temp_15_n_102 : STD_LOGIC;
signal mul_temp_15_n_103 : STD_LOGIC;
signal mul_temp_15_n_104 : STD_LOGIC;
signal mul_temp_15_n_105 : STD_LOGIC;
signal mul_temp_15_n_74 : STD_LOGIC;
signal mul_temp_15_n_75 : STD_LOGIC;
signal mul_temp_15_n_76 : STD_LOGIC;
signal mul_temp_15_n_77 : STD_LOGIC;
signal mul_temp_15_n_78 : STD_LOGIC;
signal mul_temp_15_n_79 : STD_LOGIC;
signal mul_temp_15_n_80 : STD_LOGIC;
signal mul_temp_15_n_81 : STD_LOGIC;
signal mul_temp_15_n_82 : STD_LOGIC;
signal mul_temp_15_n_83 : STD_LOGIC;
signal mul_temp_15_n_84 : STD_LOGIC;
signal mul_temp_15_n_85 : STD_LOGIC;
signal mul_temp_15_n_86 : STD_LOGIC;
signal mul_temp_15_n_87 : STD_LOGIC;
signal mul_temp_15_n_88 : STD_LOGIC;
signal mul_temp_15_n_89 : STD_LOGIC;
signal mul_temp_15_n_90 : STD_LOGIC;
signal mul_temp_15_n_92 : STD_LOGIC;
signal mul_temp_15_n_93 : STD_LOGIC;
signal mul_temp_15_n_94 : STD_LOGIC;
signal mul_temp_15_n_95 : STD_LOGIC;
signal mul_temp_15_n_96 : STD_LOGIC;
signal mul_temp_15_n_97 : STD_LOGIC;
signal mul_temp_15_n_98 : STD_LOGIC;
signal mul_temp_15_n_99 : STD_LOGIC;
signal \^mul_temp_16\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^mul_temp_17\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_17_n_100 : STD_LOGIC;
signal mul_temp_17_n_101 : STD_LOGIC;
signal mul_temp_17_n_102 : STD_LOGIC;
signal mul_temp_17_n_103 : STD_LOGIC;
signal mul_temp_17_n_104 : STD_LOGIC;
signal mul_temp_17_n_105 : STD_LOGIC;
signal mul_temp_17_n_74 : STD_LOGIC;
signal mul_temp_17_n_75 : STD_LOGIC;
signal mul_temp_17_n_76 : STD_LOGIC;
signal mul_temp_17_n_77 : STD_LOGIC;
signal mul_temp_17_n_78 : STD_LOGIC;
signal mul_temp_17_n_79 : STD_LOGIC;
signal mul_temp_17_n_80 : STD_LOGIC;
signal mul_temp_17_n_81 : STD_LOGIC;
signal mul_temp_17_n_82 : STD_LOGIC;
signal mul_temp_17_n_83 : STD_LOGIC;
signal mul_temp_17_n_84 : STD_LOGIC;
signal mul_temp_17_n_85 : STD_LOGIC;
signal mul_temp_17_n_86 : STD_LOGIC;
signal mul_temp_17_n_87 : STD_LOGIC;
signal mul_temp_17_n_88 : STD_LOGIC;
signal mul_temp_17_n_89 : STD_LOGIC;
signal mul_temp_17_n_90 : STD_LOGIC;
signal mul_temp_17_n_92 : STD_LOGIC;
signal mul_temp_17_n_93 : STD_LOGIC;
signal mul_temp_17_n_94 : STD_LOGIC;
signal mul_temp_17_n_95 : STD_LOGIC;
signal mul_temp_17_n_96 : STD_LOGIC;
signal mul_temp_17_n_97 : STD_LOGIC;
signal mul_temp_17_n_98 : STD_LOGIC;
signal mul_temp_17_n_99 : STD_LOGIC;
signal \^mul_temp_18\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_18_n_100 : STD_LOGIC;
signal mul_temp_18_n_101 : STD_LOGIC;
signal mul_temp_18_n_102 : STD_LOGIC;
signal mul_temp_18_n_103 : STD_LOGIC;
signal mul_temp_18_n_104 : STD_LOGIC;
signal mul_temp_18_n_105 : STD_LOGIC;
signal mul_temp_18_n_74 : STD_LOGIC;
signal mul_temp_18_n_75 : STD_LOGIC;
signal mul_temp_18_n_76 : STD_LOGIC;
signal mul_temp_18_n_77 : STD_LOGIC;
signal mul_temp_18_n_78 : STD_LOGIC;
signal mul_temp_18_n_79 : STD_LOGIC;
signal mul_temp_18_n_80 : STD_LOGIC;
signal mul_temp_18_n_81 : STD_LOGIC;
signal mul_temp_18_n_82 : STD_LOGIC;
signal mul_temp_18_n_83 : STD_LOGIC;
signal mul_temp_18_n_84 : STD_LOGIC;
signal mul_temp_18_n_85 : STD_LOGIC;
signal mul_temp_18_n_86 : STD_LOGIC;
signal mul_temp_18_n_87 : STD_LOGIC;
signal mul_temp_18_n_88 : STD_LOGIC;
signal mul_temp_18_n_89 : STD_LOGIC;
signal mul_temp_18_n_90 : STD_LOGIC;
signal mul_temp_18_n_92 : STD_LOGIC;
signal mul_temp_18_n_93 : STD_LOGIC;
signal mul_temp_18_n_94 : STD_LOGIC;
signal mul_temp_18_n_95 : STD_LOGIC;
signal mul_temp_18_n_96 : STD_LOGIC;
signal mul_temp_18_n_97 : STD_LOGIC;
signal mul_temp_18_n_98 : STD_LOGIC;
signal mul_temp_18_n_99 : STD_LOGIC;
signal \^mul_temp_19\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_19_n_100 : STD_LOGIC;
signal mul_temp_19_n_101 : STD_LOGIC;
signal mul_temp_19_n_102 : STD_LOGIC;
signal mul_temp_19_n_103 : STD_LOGIC;
signal mul_temp_19_n_104 : STD_LOGIC;
signal mul_temp_19_n_105 : STD_LOGIC;
signal mul_temp_19_n_74 : STD_LOGIC;
signal mul_temp_19_n_75 : STD_LOGIC;
signal mul_temp_19_n_76 : STD_LOGIC;
signal mul_temp_19_n_77 : STD_LOGIC;
signal mul_temp_19_n_78 : STD_LOGIC;
signal mul_temp_19_n_79 : STD_LOGIC;
signal mul_temp_19_n_80 : STD_LOGIC;
signal mul_temp_19_n_81 : STD_LOGIC;
signal mul_temp_19_n_82 : STD_LOGIC;
signal mul_temp_19_n_83 : STD_LOGIC;
signal mul_temp_19_n_84 : STD_LOGIC;
signal mul_temp_19_n_85 : STD_LOGIC;
signal mul_temp_19_n_86 : STD_LOGIC;
signal mul_temp_19_n_87 : STD_LOGIC;
signal mul_temp_19_n_88 : STD_LOGIC;
signal mul_temp_19_n_89 : STD_LOGIC;
signal mul_temp_19_n_90 : STD_LOGIC;
signal mul_temp_19_n_92 : STD_LOGIC;
signal mul_temp_19_n_93 : STD_LOGIC;
signal mul_temp_19_n_94 : STD_LOGIC;
signal mul_temp_19_n_95 : STD_LOGIC;
signal mul_temp_19_n_96 : STD_LOGIC;
signal mul_temp_19_n_97 : STD_LOGIC;
signal mul_temp_19_n_98 : STD_LOGIC;
signal mul_temp_19_n_99 : STD_LOGIC;
signal mul_temp_1_n_100 : STD_LOGIC;
signal mul_temp_1_n_101 : STD_LOGIC;
signal mul_temp_1_n_102 : STD_LOGIC;
signal mul_temp_1_n_103 : STD_LOGIC;
signal mul_temp_1_n_104 : STD_LOGIC;
signal mul_temp_1_n_105 : STD_LOGIC;
signal mul_temp_1_n_74 : STD_LOGIC;
signal mul_temp_1_n_75 : STD_LOGIC;
signal mul_temp_1_n_76 : STD_LOGIC;
signal mul_temp_1_n_77 : STD_LOGIC;
signal mul_temp_1_n_78 : STD_LOGIC;
signal mul_temp_1_n_79 : STD_LOGIC;
signal mul_temp_1_n_80 : STD_LOGIC;
signal mul_temp_1_n_81 : STD_LOGIC;
signal mul_temp_1_n_82 : STD_LOGIC;
signal mul_temp_1_n_83 : STD_LOGIC;
signal mul_temp_1_n_84 : STD_LOGIC;
signal mul_temp_1_n_85 : STD_LOGIC;
signal mul_temp_1_n_86 : STD_LOGIC;
signal mul_temp_1_n_87 : STD_LOGIC;
signal mul_temp_1_n_88 : STD_LOGIC;
signal mul_temp_1_n_89 : STD_LOGIC;
signal mul_temp_1_n_90 : STD_LOGIC;
signal mul_temp_1_n_92 : STD_LOGIC;
signal mul_temp_1_n_93 : STD_LOGIC;
signal mul_temp_1_n_94 : STD_LOGIC;
signal mul_temp_1_n_95 : STD_LOGIC;
signal mul_temp_1_n_96 : STD_LOGIC;
signal mul_temp_1_n_97 : STD_LOGIC;
signal mul_temp_1_n_98 : STD_LOGIC;
signal mul_temp_1_n_99 : STD_LOGIC;
signal \^mul_temp_2\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mul_temp_20\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_20_n_100 : STD_LOGIC;
signal mul_temp_20_n_101 : STD_LOGIC;
signal mul_temp_20_n_102 : STD_LOGIC;
signal mul_temp_20_n_103 : STD_LOGIC;
signal mul_temp_20_n_104 : STD_LOGIC;
signal mul_temp_20_n_105 : STD_LOGIC;
signal mul_temp_20_n_74 : STD_LOGIC;
signal mul_temp_20_n_75 : STD_LOGIC;
signal mul_temp_20_n_76 : STD_LOGIC;
signal mul_temp_20_n_77 : STD_LOGIC;
signal mul_temp_20_n_78 : STD_LOGIC;
signal mul_temp_20_n_79 : STD_LOGIC;
signal mul_temp_20_n_80 : STD_LOGIC;
signal mul_temp_20_n_81 : STD_LOGIC;
signal mul_temp_20_n_82 : STD_LOGIC;
signal mul_temp_20_n_83 : STD_LOGIC;
signal mul_temp_20_n_84 : STD_LOGIC;
signal mul_temp_20_n_85 : STD_LOGIC;
signal mul_temp_20_n_86 : STD_LOGIC;
signal mul_temp_20_n_87 : STD_LOGIC;
signal mul_temp_20_n_88 : STD_LOGIC;
signal mul_temp_20_n_89 : STD_LOGIC;
signal mul_temp_20_n_90 : STD_LOGIC;
signal mul_temp_20_n_92 : STD_LOGIC;
signal mul_temp_20_n_93 : STD_LOGIC;
signal mul_temp_20_n_94 : STD_LOGIC;
signal mul_temp_20_n_95 : STD_LOGIC;
signal mul_temp_20_n_96 : STD_LOGIC;
signal mul_temp_20_n_97 : STD_LOGIC;
signal mul_temp_20_n_98 : STD_LOGIC;
signal mul_temp_20_n_99 : STD_LOGIC;
signal \^mul_temp_21\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_21_n_100 : STD_LOGIC;
signal mul_temp_21_n_101 : STD_LOGIC;
signal mul_temp_21_n_102 : STD_LOGIC;
signal mul_temp_21_n_103 : STD_LOGIC;
signal mul_temp_21_n_104 : STD_LOGIC;
signal mul_temp_21_n_105 : STD_LOGIC;
signal mul_temp_21_n_74 : STD_LOGIC;
signal mul_temp_21_n_75 : STD_LOGIC;
signal mul_temp_21_n_76 : STD_LOGIC;
signal mul_temp_21_n_77 : STD_LOGIC;
signal mul_temp_21_n_78 : STD_LOGIC;
signal mul_temp_21_n_79 : STD_LOGIC;
signal mul_temp_21_n_80 : STD_LOGIC;
signal mul_temp_21_n_81 : STD_LOGIC;
signal mul_temp_21_n_82 : STD_LOGIC;
signal mul_temp_21_n_83 : STD_LOGIC;
signal mul_temp_21_n_84 : STD_LOGIC;
signal mul_temp_21_n_85 : STD_LOGIC;
signal mul_temp_21_n_86 : STD_LOGIC;
signal mul_temp_21_n_87 : STD_LOGIC;
signal mul_temp_21_n_88 : STD_LOGIC;
signal mul_temp_21_n_89 : STD_LOGIC;
signal mul_temp_21_n_90 : STD_LOGIC;
signal mul_temp_21_n_92 : STD_LOGIC;
signal mul_temp_21_n_93 : STD_LOGIC;
signal mul_temp_21_n_94 : STD_LOGIC;
signal mul_temp_21_n_95 : STD_LOGIC;
signal mul_temp_21_n_96 : STD_LOGIC;
signal mul_temp_21_n_97 : STD_LOGIC;
signal mul_temp_21_n_98 : STD_LOGIC;
signal mul_temp_21_n_99 : STD_LOGIC;
signal \^mul_temp_22\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_22_n_100 : STD_LOGIC;
signal mul_temp_22_n_101 : STD_LOGIC;
signal mul_temp_22_n_102 : STD_LOGIC;
signal mul_temp_22_n_103 : STD_LOGIC;
signal mul_temp_22_n_104 : STD_LOGIC;
signal mul_temp_22_n_105 : STD_LOGIC;
signal mul_temp_22_n_74 : STD_LOGIC;
signal mul_temp_22_n_75 : STD_LOGIC;
signal mul_temp_22_n_76 : STD_LOGIC;
signal mul_temp_22_n_77 : STD_LOGIC;
signal mul_temp_22_n_78 : STD_LOGIC;
signal mul_temp_22_n_79 : STD_LOGIC;
signal mul_temp_22_n_80 : STD_LOGIC;
signal mul_temp_22_n_81 : STD_LOGIC;
signal mul_temp_22_n_82 : STD_LOGIC;
signal mul_temp_22_n_83 : STD_LOGIC;
signal mul_temp_22_n_84 : STD_LOGIC;
signal mul_temp_22_n_85 : STD_LOGIC;
signal mul_temp_22_n_86 : STD_LOGIC;
signal mul_temp_22_n_87 : STD_LOGIC;
signal mul_temp_22_n_88 : STD_LOGIC;
signal mul_temp_22_n_89 : STD_LOGIC;
signal mul_temp_22_n_90 : STD_LOGIC;
signal mul_temp_22_n_92 : STD_LOGIC;
signal mul_temp_22_n_93 : STD_LOGIC;
signal mul_temp_22_n_94 : STD_LOGIC;
signal mul_temp_22_n_95 : STD_LOGIC;
signal mul_temp_22_n_96 : STD_LOGIC;
signal mul_temp_22_n_97 : STD_LOGIC;
signal mul_temp_22_n_98 : STD_LOGIC;
signal mul_temp_22_n_99 : STD_LOGIC;
signal \^mul_temp_23\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_23_n_100 : STD_LOGIC;
signal mul_temp_23_n_101 : STD_LOGIC;
signal mul_temp_23_n_102 : STD_LOGIC;
signal mul_temp_23_n_103 : STD_LOGIC;
signal mul_temp_23_n_104 : STD_LOGIC;
signal mul_temp_23_n_105 : STD_LOGIC;
signal mul_temp_23_n_74 : STD_LOGIC;
signal mul_temp_23_n_75 : STD_LOGIC;
signal mul_temp_23_n_76 : STD_LOGIC;
signal mul_temp_23_n_77 : STD_LOGIC;
signal mul_temp_23_n_78 : STD_LOGIC;
signal mul_temp_23_n_79 : STD_LOGIC;
signal mul_temp_23_n_80 : STD_LOGIC;
signal mul_temp_23_n_81 : STD_LOGIC;
signal mul_temp_23_n_82 : STD_LOGIC;
signal mul_temp_23_n_83 : STD_LOGIC;
signal mul_temp_23_n_84 : STD_LOGIC;
signal mul_temp_23_n_85 : STD_LOGIC;
signal mul_temp_23_n_86 : STD_LOGIC;
signal mul_temp_23_n_87 : STD_LOGIC;
signal mul_temp_23_n_88 : STD_LOGIC;
signal mul_temp_23_n_89 : STD_LOGIC;
signal mul_temp_23_n_90 : STD_LOGIC;
signal mul_temp_23_n_92 : STD_LOGIC;
signal mul_temp_23_n_93 : STD_LOGIC;
signal mul_temp_23_n_94 : STD_LOGIC;
signal mul_temp_23_n_95 : STD_LOGIC;
signal mul_temp_23_n_96 : STD_LOGIC;
signal mul_temp_23_n_97 : STD_LOGIC;
signal mul_temp_23_n_98 : STD_LOGIC;
signal mul_temp_23_n_99 : STD_LOGIC;
signal \^mul_temp_24\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_24_n_100 : STD_LOGIC;
signal mul_temp_24_n_101 : STD_LOGIC;
signal mul_temp_24_n_102 : STD_LOGIC;
signal mul_temp_24_n_103 : STD_LOGIC;
signal mul_temp_24_n_104 : STD_LOGIC;
signal mul_temp_24_n_105 : STD_LOGIC;
signal mul_temp_24_n_74 : STD_LOGIC;
signal mul_temp_24_n_75 : STD_LOGIC;
signal mul_temp_24_n_76 : STD_LOGIC;
signal mul_temp_24_n_77 : STD_LOGIC;
signal mul_temp_24_n_78 : STD_LOGIC;
signal mul_temp_24_n_79 : STD_LOGIC;
signal mul_temp_24_n_80 : STD_LOGIC;
signal mul_temp_24_n_81 : STD_LOGIC;
signal mul_temp_24_n_82 : STD_LOGIC;
signal mul_temp_24_n_83 : STD_LOGIC;
signal mul_temp_24_n_84 : STD_LOGIC;
signal mul_temp_24_n_85 : STD_LOGIC;
signal mul_temp_24_n_86 : STD_LOGIC;
signal mul_temp_24_n_87 : STD_LOGIC;
signal mul_temp_24_n_88 : STD_LOGIC;
signal mul_temp_24_n_89 : STD_LOGIC;
signal mul_temp_24_n_90 : STD_LOGIC;
signal mul_temp_24_n_92 : STD_LOGIC;
signal mul_temp_24_n_93 : STD_LOGIC;
signal mul_temp_24_n_94 : STD_LOGIC;
signal mul_temp_24_n_95 : STD_LOGIC;
signal mul_temp_24_n_96 : STD_LOGIC;
signal mul_temp_24_n_97 : STD_LOGIC;
signal mul_temp_24_n_98 : STD_LOGIC;
signal mul_temp_24_n_99 : STD_LOGIC;
signal \^mul_temp_25\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_25_n_100 : STD_LOGIC;
signal mul_temp_25_n_101 : STD_LOGIC;
signal mul_temp_25_n_102 : STD_LOGIC;
signal mul_temp_25_n_103 : STD_LOGIC;
signal mul_temp_25_n_104 : STD_LOGIC;
signal mul_temp_25_n_105 : STD_LOGIC;
signal mul_temp_25_n_74 : STD_LOGIC;
signal mul_temp_25_n_75 : STD_LOGIC;
signal mul_temp_25_n_76 : STD_LOGIC;
signal mul_temp_25_n_77 : STD_LOGIC;
signal mul_temp_25_n_78 : STD_LOGIC;
signal mul_temp_25_n_79 : STD_LOGIC;
signal mul_temp_25_n_80 : STD_LOGIC;
signal mul_temp_25_n_81 : STD_LOGIC;
signal mul_temp_25_n_82 : STD_LOGIC;
signal mul_temp_25_n_83 : STD_LOGIC;
signal mul_temp_25_n_84 : STD_LOGIC;
signal mul_temp_25_n_85 : STD_LOGIC;
signal mul_temp_25_n_86 : STD_LOGIC;
signal mul_temp_25_n_87 : STD_LOGIC;
signal mul_temp_25_n_88 : STD_LOGIC;
signal mul_temp_25_n_89 : STD_LOGIC;
signal mul_temp_25_n_90 : STD_LOGIC;
signal mul_temp_25_n_92 : STD_LOGIC;
signal mul_temp_25_n_93 : STD_LOGIC;
signal mul_temp_25_n_94 : STD_LOGIC;
signal mul_temp_25_n_95 : STD_LOGIC;
signal mul_temp_25_n_96 : STD_LOGIC;
signal mul_temp_25_n_97 : STD_LOGIC;
signal mul_temp_25_n_98 : STD_LOGIC;
signal mul_temp_25_n_99 : STD_LOGIC;
signal \^mul_temp_26\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_26_n_100 : STD_LOGIC;
signal mul_temp_26_n_101 : STD_LOGIC;
signal mul_temp_26_n_102 : STD_LOGIC;
signal mul_temp_26_n_103 : STD_LOGIC;
signal mul_temp_26_n_104 : STD_LOGIC;
signal mul_temp_26_n_105 : STD_LOGIC;
signal mul_temp_26_n_74 : STD_LOGIC;
signal mul_temp_26_n_75 : STD_LOGIC;
signal mul_temp_26_n_76 : STD_LOGIC;
signal mul_temp_26_n_77 : STD_LOGIC;
signal mul_temp_26_n_78 : STD_LOGIC;
signal mul_temp_26_n_79 : STD_LOGIC;
signal mul_temp_26_n_80 : STD_LOGIC;
signal mul_temp_26_n_81 : STD_LOGIC;
signal mul_temp_26_n_82 : STD_LOGIC;
signal mul_temp_26_n_83 : STD_LOGIC;
signal mul_temp_26_n_84 : STD_LOGIC;
signal mul_temp_26_n_85 : STD_LOGIC;
signal mul_temp_26_n_86 : STD_LOGIC;
signal mul_temp_26_n_87 : STD_LOGIC;
signal mul_temp_26_n_88 : STD_LOGIC;
signal mul_temp_26_n_89 : STD_LOGIC;
signal mul_temp_26_n_90 : STD_LOGIC;
signal mul_temp_26_n_92 : STD_LOGIC;
signal mul_temp_26_n_93 : STD_LOGIC;
signal mul_temp_26_n_94 : STD_LOGIC;
signal mul_temp_26_n_95 : STD_LOGIC;
signal mul_temp_26_n_96 : STD_LOGIC;
signal mul_temp_26_n_97 : STD_LOGIC;
signal mul_temp_26_n_98 : STD_LOGIC;
signal mul_temp_26_n_99 : STD_LOGIC;
signal \^mul_temp_27\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_27_n_100 : STD_LOGIC;
signal mul_temp_27_n_101 : STD_LOGIC;
signal mul_temp_27_n_102 : STD_LOGIC;
signal mul_temp_27_n_103 : STD_LOGIC;
signal mul_temp_27_n_104 : STD_LOGIC;
signal mul_temp_27_n_105 : STD_LOGIC;
signal mul_temp_27_n_74 : STD_LOGIC;
signal mul_temp_27_n_75 : STD_LOGIC;
signal mul_temp_27_n_76 : STD_LOGIC;
signal mul_temp_27_n_77 : STD_LOGIC;
signal mul_temp_27_n_78 : STD_LOGIC;
signal mul_temp_27_n_79 : STD_LOGIC;
signal mul_temp_27_n_80 : STD_LOGIC;
signal mul_temp_27_n_81 : STD_LOGIC;
signal mul_temp_27_n_82 : STD_LOGIC;
signal mul_temp_27_n_83 : STD_LOGIC;
signal mul_temp_27_n_84 : STD_LOGIC;
signal mul_temp_27_n_85 : STD_LOGIC;
signal mul_temp_27_n_86 : STD_LOGIC;
signal mul_temp_27_n_87 : STD_LOGIC;
signal mul_temp_27_n_88 : STD_LOGIC;
signal mul_temp_27_n_89 : STD_LOGIC;
signal mul_temp_27_n_90 : STD_LOGIC;
signal mul_temp_27_n_92 : STD_LOGIC;
signal mul_temp_27_n_93 : STD_LOGIC;
signal mul_temp_27_n_94 : STD_LOGIC;
signal mul_temp_27_n_95 : STD_LOGIC;
signal mul_temp_27_n_96 : STD_LOGIC;
signal mul_temp_27_n_97 : STD_LOGIC;
signal mul_temp_27_n_98 : STD_LOGIC;
signal mul_temp_27_n_99 : STD_LOGIC;
signal \^mul_temp_28\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_28_n_100 : STD_LOGIC;
signal mul_temp_28_n_101 : STD_LOGIC;
signal mul_temp_28_n_102 : STD_LOGIC;
signal mul_temp_28_n_103 : STD_LOGIC;
signal mul_temp_28_n_104 : STD_LOGIC;
signal mul_temp_28_n_105 : STD_LOGIC;
signal mul_temp_28_n_74 : STD_LOGIC;
signal mul_temp_28_n_75 : STD_LOGIC;
signal mul_temp_28_n_76 : STD_LOGIC;
signal mul_temp_28_n_77 : STD_LOGIC;
signal mul_temp_28_n_78 : STD_LOGIC;
signal mul_temp_28_n_79 : STD_LOGIC;
signal mul_temp_28_n_80 : STD_LOGIC;
signal mul_temp_28_n_81 : STD_LOGIC;
signal mul_temp_28_n_82 : STD_LOGIC;
signal mul_temp_28_n_83 : STD_LOGIC;
signal mul_temp_28_n_84 : STD_LOGIC;
signal mul_temp_28_n_85 : STD_LOGIC;
signal mul_temp_28_n_86 : STD_LOGIC;
signal mul_temp_28_n_87 : STD_LOGIC;
signal mul_temp_28_n_88 : STD_LOGIC;
signal mul_temp_28_n_89 : STD_LOGIC;
signal mul_temp_28_n_90 : STD_LOGIC;
signal mul_temp_28_n_92 : STD_LOGIC;
signal mul_temp_28_n_93 : STD_LOGIC;
signal mul_temp_28_n_94 : STD_LOGIC;
signal mul_temp_28_n_95 : STD_LOGIC;
signal mul_temp_28_n_96 : STD_LOGIC;
signal mul_temp_28_n_97 : STD_LOGIC;
signal mul_temp_28_n_98 : STD_LOGIC;
signal mul_temp_28_n_99 : STD_LOGIC;
signal \^mul_temp_29\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_29_n_100 : STD_LOGIC;
signal mul_temp_29_n_101 : STD_LOGIC;
signal mul_temp_29_n_102 : STD_LOGIC;
signal mul_temp_29_n_103 : STD_LOGIC;
signal mul_temp_29_n_104 : STD_LOGIC;
signal mul_temp_29_n_105 : STD_LOGIC;
signal mul_temp_29_n_74 : STD_LOGIC;
signal mul_temp_29_n_75 : STD_LOGIC;
signal mul_temp_29_n_76 : STD_LOGIC;
signal mul_temp_29_n_77 : STD_LOGIC;
signal mul_temp_29_n_78 : STD_LOGIC;
signal mul_temp_29_n_79 : STD_LOGIC;
signal mul_temp_29_n_80 : STD_LOGIC;
signal mul_temp_29_n_81 : STD_LOGIC;
signal mul_temp_29_n_82 : STD_LOGIC;
signal mul_temp_29_n_83 : STD_LOGIC;
signal mul_temp_29_n_84 : STD_LOGIC;
signal mul_temp_29_n_85 : STD_LOGIC;
signal mul_temp_29_n_86 : STD_LOGIC;
signal mul_temp_29_n_87 : STD_LOGIC;
signal mul_temp_29_n_88 : STD_LOGIC;
signal mul_temp_29_n_89 : STD_LOGIC;
signal mul_temp_29_n_90 : STD_LOGIC;
signal mul_temp_29_n_92 : STD_LOGIC;
signal mul_temp_29_n_93 : STD_LOGIC;
signal mul_temp_29_n_94 : STD_LOGIC;
signal mul_temp_29_n_95 : STD_LOGIC;
signal mul_temp_29_n_96 : STD_LOGIC;
signal mul_temp_29_n_97 : STD_LOGIC;
signal mul_temp_29_n_98 : STD_LOGIC;
signal mul_temp_29_n_99 : STD_LOGIC;
signal mul_temp_2_n_100 : STD_LOGIC;
signal mul_temp_2_n_101 : STD_LOGIC;
signal mul_temp_2_n_102 : STD_LOGIC;
signal mul_temp_2_n_103 : STD_LOGIC;
signal mul_temp_2_n_104 : STD_LOGIC;
signal mul_temp_2_n_105 : STD_LOGIC;
signal mul_temp_2_n_74 : STD_LOGIC;
signal mul_temp_2_n_75 : STD_LOGIC;
signal mul_temp_2_n_76 : STD_LOGIC;
signal mul_temp_2_n_77 : STD_LOGIC;
signal mul_temp_2_n_78 : STD_LOGIC;
signal mul_temp_2_n_79 : STD_LOGIC;
signal mul_temp_2_n_80 : STD_LOGIC;
signal mul_temp_2_n_81 : STD_LOGIC;
signal mul_temp_2_n_82 : STD_LOGIC;
signal mul_temp_2_n_83 : STD_LOGIC;
signal mul_temp_2_n_84 : STD_LOGIC;
signal mul_temp_2_n_85 : STD_LOGIC;
signal mul_temp_2_n_86 : STD_LOGIC;
signal mul_temp_2_n_87 : STD_LOGIC;
signal mul_temp_2_n_88 : STD_LOGIC;
signal mul_temp_2_n_89 : STD_LOGIC;
signal mul_temp_2_n_90 : STD_LOGIC;
signal mul_temp_2_n_92 : STD_LOGIC;
signal mul_temp_2_n_93 : STD_LOGIC;
signal mul_temp_2_n_94 : STD_LOGIC;
signal mul_temp_2_n_95 : STD_LOGIC;
signal mul_temp_2_n_96 : STD_LOGIC;
signal mul_temp_2_n_97 : STD_LOGIC;
signal mul_temp_2_n_98 : STD_LOGIC;
signal mul_temp_2_n_99 : STD_LOGIC;
signal \^mul_temp_3\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mul_temp_30\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_30_n_100 : STD_LOGIC;
signal mul_temp_30_n_101 : STD_LOGIC;
signal mul_temp_30_n_102 : STD_LOGIC;
signal mul_temp_30_n_103 : STD_LOGIC;
signal mul_temp_30_n_104 : STD_LOGIC;
signal mul_temp_30_n_105 : STD_LOGIC;
signal mul_temp_30_n_74 : STD_LOGIC;
signal mul_temp_30_n_75 : STD_LOGIC;
signal mul_temp_30_n_76 : STD_LOGIC;
signal mul_temp_30_n_77 : STD_LOGIC;
signal mul_temp_30_n_78 : STD_LOGIC;
signal mul_temp_30_n_79 : STD_LOGIC;
signal mul_temp_30_n_80 : STD_LOGIC;
signal mul_temp_30_n_81 : STD_LOGIC;
signal mul_temp_30_n_82 : STD_LOGIC;
signal mul_temp_30_n_83 : STD_LOGIC;
signal mul_temp_30_n_84 : STD_LOGIC;
signal mul_temp_30_n_85 : STD_LOGIC;
signal mul_temp_30_n_86 : STD_LOGIC;
signal mul_temp_30_n_87 : STD_LOGIC;
signal mul_temp_30_n_88 : STD_LOGIC;
signal mul_temp_30_n_89 : STD_LOGIC;
signal mul_temp_30_n_90 : STD_LOGIC;
signal mul_temp_30_n_92 : STD_LOGIC;
signal mul_temp_30_n_93 : STD_LOGIC;
signal mul_temp_30_n_94 : STD_LOGIC;
signal mul_temp_30_n_95 : STD_LOGIC;
signal mul_temp_30_n_96 : STD_LOGIC;
signal mul_temp_30_n_97 : STD_LOGIC;
signal mul_temp_30_n_98 : STD_LOGIC;
signal mul_temp_30_n_99 : STD_LOGIC;
signal \^mul_temp_31\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_31_n_100 : STD_LOGIC;
signal mul_temp_31_n_101 : STD_LOGIC;
signal mul_temp_31_n_102 : STD_LOGIC;
signal mul_temp_31_n_103 : STD_LOGIC;
signal mul_temp_31_n_104 : STD_LOGIC;
signal mul_temp_31_n_105 : STD_LOGIC;
signal mul_temp_31_n_74 : STD_LOGIC;
signal mul_temp_31_n_75 : STD_LOGIC;
signal mul_temp_31_n_76 : STD_LOGIC;
signal mul_temp_31_n_77 : STD_LOGIC;
signal mul_temp_31_n_78 : STD_LOGIC;
signal mul_temp_31_n_79 : STD_LOGIC;
signal mul_temp_31_n_80 : STD_LOGIC;
signal mul_temp_31_n_81 : STD_LOGIC;
signal mul_temp_31_n_82 : STD_LOGIC;
signal mul_temp_31_n_83 : STD_LOGIC;
signal mul_temp_31_n_84 : STD_LOGIC;
signal mul_temp_31_n_85 : STD_LOGIC;
signal mul_temp_31_n_86 : STD_LOGIC;
signal mul_temp_31_n_87 : STD_LOGIC;
signal mul_temp_31_n_88 : STD_LOGIC;
signal mul_temp_31_n_89 : STD_LOGIC;
signal mul_temp_31_n_90 : STD_LOGIC;
signal mul_temp_31_n_92 : STD_LOGIC;
signal mul_temp_31_n_93 : STD_LOGIC;
signal mul_temp_31_n_94 : STD_LOGIC;
signal mul_temp_31_n_95 : STD_LOGIC;
signal mul_temp_31_n_96 : STD_LOGIC;
signal mul_temp_31_n_97 : STD_LOGIC;
signal mul_temp_31_n_98 : STD_LOGIC;
signal mul_temp_31_n_99 : STD_LOGIC;
signal \^mul_temp_32\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_32_n_100 : STD_LOGIC;
signal mul_temp_32_n_101 : STD_LOGIC;
signal mul_temp_32_n_102 : STD_LOGIC;
signal mul_temp_32_n_103 : STD_LOGIC;
signal mul_temp_32_n_104 : STD_LOGIC;
signal mul_temp_32_n_105 : STD_LOGIC;
signal mul_temp_32_n_74 : STD_LOGIC;
signal mul_temp_32_n_75 : STD_LOGIC;
signal mul_temp_32_n_76 : STD_LOGIC;
signal mul_temp_32_n_77 : STD_LOGIC;
signal mul_temp_32_n_78 : STD_LOGIC;
signal mul_temp_32_n_79 : STD_LOGIC;
signal mul_temp_32_n_80 : STD_LOGIC;
signal mul_temp_32_n_81 : STD_LOGIC;
signal mul_temp_32_n_82 : STD_LOGIC;
signal mul_temp_32_n_83 : STD_LOGIC;
signal mul_temp_32_n_84 : STD_LOGIC;
signal mul_temp_32_n_85 : STD_LOGIC;
signal mul_temp_32_n_86 : STD_LOGIC;
signal mul_temp_32_n_87 : STD_LOGIC;
signal mul_temp_32_n_88 : STD_LOGIC;
signal mul_temp_32_n_89 : STD_LOGIC;
signal mul_temp_32_n_90 : STD_LOGIC;
signal mul_temp_32_n_92 : STD_LOGIC;
signal mul_temp_32_n_93 : STD_LOGIC;
signal mul_temp_32_n_94 : STD_LOGIC;
signal mul_temp_32_n_95 : STD_LOGIC;
signal mul_temp_32_n_96 : STD_LOGIC;
signal mul_temp_32_n_97 : STD_LOGIC;
signal mul_temp_32_n_98 : STD_LOGIC;
signal mul_temp_32_n_99 : STD_LOGIC;
signal mul_temp_3_n_100 : STD_LOGIC;
signal mul_temp_3_n_101 : STD_LOGIC;
signal mul_temp_3_n_102 : STD_LOGIC;
signal mul_temp_3_n_103 : STD_LOGIC;
signal mul_temp_3_n_104 : STD_LOGIC;
signal mul_temp_3_n_105 : STD_LOGIC;
signal mul_temp_3_n_74 : STD_LOGIC;
signal mul_temp_3_n_75 : STD_LOGIC;
signal mul_temp_3_n_76 : STD_LOGIC;
signal mul_temp_3_n_77 : STD_LOGIC;
signal mul_temp_3_n_78 : STD_LOGIC;
signal mul_temp_3_n_79 : STD_LOGIC;
signal mul_temp_3_n_80 : STD_LOGIC;
signal mul_temp_3_n_81 : STD_LOGIC;
signal mul_temp_3_n_82 : STD_LOGIC;
signal mul_temp_3_n_83 : STD_LOGIC;
signal mul_temp_3_n_84 : STD_LOGIC;
signal mul_temp_3_n_85 : STD_LOGIC;
signal mul_temp_3_n_86 : STD_LOGIC;
signal mul_temp_3_n_87 : STD_LOGIC;
signal mul_temp_3_n_88 : STD_LOGIC;
signal mul_temp_3_n_89 : STD_LOGIC;
signal mul_temp_3_n_90 : STD_LOGIC;
signal mul_temp_3_n_92 : STD_LOGIC;
signal mul_temp_3_n_93 : STD_LOGIC;
signal mul_temp_3_n_94 : STD_LOGIC;
signal mul_temp_3_n_95 : STD_LOGIC;
signal mul_temp_3_n_96 : STD_LOGIC;
signal mul_temp_3_n_97 : STD_LOGIC;
signal mul_temp_3_n_98 : STD_LOGIC;
signal mul_temp_3_n_99 : STD_LOGIC;
signal \^mul_temp_4\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_4_n_100 : STD_LOGIC;
signal mul_temp_4_n_101 : STD_LOGIC;
signal mul_temp_4_n_102 : STD_LOGIC;
signal mul_temp_4_n_103 : STD_LOGIC;
signal mul_temp_4_n_104 : STD_LOGIC;
signal mul_temp_4_n_105 : STD_LOGIC;
signal mul_temp_4_n_74 : STD_LOGIC;
signal mul_temp_4_n_75 : STD_LOGIC;
signal mul_temp_4_n_76 : STD_LOGIC;
signal mul_temp_4_n_77 : STD_LOGIC;
signal mul_temp_4_n_78 : STD_LOGIC;
signal mul_temp_4_n_79 : STD_LOGIC;
signal mul_temp_4_n_80 : STD_LOGIC;
signal mul_temp_4_n_81 : STD_LOGIC;
signal mul_temp_4_n_82 : STD_LOGIC;
signal mul_temp_4_n_83 : STD_LOGIC;
signal mul_temp_4_n_84 : STD_LOGIC;
signal mul_temp_4_n_85 : STD_LOGIC;
signal mul_temp_4_n_86 : STD_LOGIC;
signal mul_temp_4_n_87 : STD_LOGIC;
signal mul_temp_4_n_88 : STD_LOGIC;
signal mul_temp_4_n_89 : STD_LOGIC;
signal mul_temp_4_n_90 : STD_LOGIC;
signal mul_temp_4_n_92 : STD_LOGIC;
signal mul_temp_4_n_93 : STD_LOGIC;
signal mul_temp_4_n_94 : STD_LOGIC;
signal mul_temp_4_n_95 : STD_LOGIC;
signal mul_temp_4_n_96 : STD_LOGIC;
signal mul_temp_4_n_97 : STD_LOGIC;
signal mul_temp_4_n_98 : STD_LOGIC;
signal mul_temp_4_n_99 : STD_LOGIC;
signal \^mul_temp_5\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_5_n_100 : STD_LOGIC;
signal mul_temp_5_n_101 : STD_LOGIC;
signal mul_temp_5_n_102 : STD_LOGIC;
signal mul_temp_5_n_103 : STD_LOGIC;
signal mul_temp_5_n_104 : STD_LOGIC;
signal mul_temp_5_n_105 : STD_LOGIC;
signal mul_temp_5_n_74 : STD_LOGIC;
signal mul_temp_5_n_75 : STD_LOGIC;
signal mul_temp_5_n_76 : STD_LOGIC;
signal mul_temp_5_n_77 : STD_LOGIC;
signal mul_temp_5_n_78 : STD_LOGIC;
signal mul_temp_5_n_79 : STD_LOGIC;
signal mul_temp_5_n_80 : STD_LOGIC;
signal mul_temp_5_n_81 : STD_LOGIC;
signal mul_temp_5_n_82 : STD_LOGIC;
signal mul_temp_5_n_83 : STD_LOGIC;
signal mul_temp_5_n_84 : STD_LOGIC;
signal mul_temp_5_n_85 : STD_LOGIC;
signal mul_temp_5_n_86 : STD_LOGIC;
signal mul_temp_5_n_87 : STD_LOGIC;
signal mul_temp_5_n_88 : STD_LOGIC;
signal mul_temp_5_n_89 : STD_LOGIC;
signal mul_temp_5_n_90 : STD_LOGIC;
signal mul_temp_5_n_92 : STD_LOGIC;
signal mul_temp_5_n_93 : STD_LOGIC;
signal mul_temp_5_n_94 : STD_LOGIC;
signal mul_temp_5_n_95 : STD_LOGIC;
signal mul_temp_5_n_96 : STD_LOGIC;
signal mul_temp_5_n_97 : STD_LOGIC;
signal mul_temp_5_n_98 : STD_LOGIC;
signal mul_temp_5_n_99 : STD_LOGIC;
signal \^mul_temp_6\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_6_n_100 : STD_LOGIC;
signal mul_temp_6_n_101 : STD_LOGIC;
signal mul_temp_6_n_102 : STD_LOGIC;
signal mul_temp_6_n_103 : STD_LOGIC;
signal mul_temp_6_n_104 : STD_LOGIC;
signal mul_temp_6_n_105 : STD_LOGIC;
signal mul_temp_6_n_74 : STD_LOGIC;
signal mul_temp_6_n_75 : STD_LOGIC;
signal mul_temp_6_n_76 : STD_LOGIC;
signal mul_temp_6_n_77 : STD_LOGIC;
signal mul_temp_6_n_78 : STD_LOGIC;
signal mul_temp_6_n_79 : STD_LOGIC;
signal mul_temp_6_n_80 : STD_LOGIC;
signal mul_temp_6_n_81 : STD_LOGIC;
signal mul_temp_6_n_82 : STD_LOGIC;
signal mul_temp_6_n_83 : STD_LOGIC;
signal mul_temp_6_n_84 : STD_LOGIC;
signal mul_temp_6_n_85 : STD_LOGIC;
signal mul_temp_6_n_86 : STD_LOGIC;
signal mul_temp_6_n_87 : STD_LOGIC;
signal mul_temp_6_n_88 : STD_LOGIC;
signal mul_temp_6_n_89 : STD_LOGIC;
signal mul_temp_6_n_90 : STD_LOGIC;
signal mul_temp_6_n_92 : STD_LOGIC;
signal mul_temp_6_n_93 : STD_LOGIC;
signal mul_temp_6_n_94 : STD_LOGIC;
signal mul_temp_6_n_95 : STD_LOGIC;
signal mul_temp_6_n_96 : STD_LOGIC;
signal mul_temp_6_n_97 : STD_LOGIC;
signal mul_temp_6_n_98 : STD_LOGIC;
signal mul_temp_6_n_99 : STD_LOGIC;
signal \^mul_temp_7\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_7_n_100 : STD_LOGIC;
signal mul_temp_7_n_101 : STD_LOGIC;
signal mul_temp_7_n_102 : STD_LOGIC;
signal mul_temp_7_n_103 : STD_LOGIC;
signal mul_temp_7_n_104 : STD_LOGIC;
signal mul_temp_7_n_105 : STD_LOGIC;
signal mul_temp_7_n_74 : STD_LOGIC;
signal mul_temp_7_n_75 : STD_LOGIC;
signal mul_temp_7_n_76 : STD_LOGIC;
signal mul_temp_7_n_77 : STD_LOGIC;
signal mul_temp_7_n_78 : STD_LOGIC;
signal mul_temp_7_n_79 : STD_LOGIC;
signal mul_temp_7_n_80 : STD_LOGIC;
signal mul_temp_7_n_81 : STD_LOGIC;
signal mul_temp_7_n_82 : STD_LOGIC;
signal mul_temp_7_n_83 : STD_LOGIC;
signal mul_temp_7_n_84 : STD_LOGIC;
signal mul_temp_7_n_85 : STD_LOGIC;
signal mul_temp_7_n_86 : STD_LOGIC;
signal mul_temp_7_n_87 : STD_LOGIC;
signal mul_temp_7_n_88 : STD_LOGIC;
signal mul_temp_7_n_89 : STD_LOGIC;
signal mul_temp_7_n_90 : STD_LOGIC;
signal mul_temp_7_n_92 : STD_LOGIC;
signal mul_temp_7_n_93 : STD_LOGIC;
signal mul_temp_7_n_94 : STD_LOGIC;
signal mul_temp_7_n_95 : STD_LOGIC;
signal mul_temp_7_n_96 : STD_LOGIC;
signal mul_temp_7_n_97 : STD_LOGIC;
signal mul_temp_7_n_98 : STD_LOGIC;
signal mul_temp_7_n_99 : STD_LOGIC;
signal \^mul_temp_8\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_8_n_100 : STD_LOGIC;
signal mul_temp_8_n_101 : STD_LOGIC;
signal mul_temp_8_n_102 : STD_LOGIC;
signal mul_temp_8_n_103 : STD_LOGIC;
signal mul_temp_8_n_104 : STD_LOGIC;
signal mul_temp_8_n_105 : STD_LOGIC;
signal mul_temp_8_n_74 : STD_LOGIC;
signal mul_temp_8_n_75 : STD_LOGIC;
signal mul_temp_8_n_76 : STD_LOGIC;
signal mul_temp_8_n_77 : STD_LOGIC;
signal mul_temp_8_n_78 : STD_LOGIC;
signal mul_temp_8_n_79 : STD_LOGIC;
signal mul_temp_8_n_80 : STD_LOGIC;
signal mul_temp_8_n_81 : STD_LOGIC;
signal mul_temp_8_n_82 : STD_LOGIC;
signal mul_temp_8_n_83 : STD_LOGIC;
signal mul_temp_8_n_84 : STD_LOGIC;
signal mul_temp_8_n_85 : STD_LOGIC;
signal mul_temp_8_n_86 : STD_LOGIC;
signal mul_temp_8_n_87 : STD_LOGIC;
signal mul_temp_8_n_88 : STD_LOGIC;
signal mul_temp_8_n_89 : STD_LOGIC;
signal mul_temp_8_n_90 : STD_LOGIC;
signal mul_temp_8_n_92 : STD_LOGIC;
signal mul_temp_8_n_93 : STD_LOGIC;
signal mul_temp_8_n_94 : STD_LOGIC;
signal mul_temp_8_n_95 : STD_LOGIC;
signal mul_temp_8_n_96 : STD_LOGIC;
signal mul_temp_8_n_97 : STD_LOGIC;
signal mul_temp_8_n_98 : STD_LOGIC;
signal mul_temp_8_n_99 : STD_LOGIC;
signal \^mul_temp_9\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_9_n_100 : STD_LOGIC;
signal mul_temp_9_n_101 : STD_LOGIC;
signal mul_temp_9_n_102 : STD_LOGIC;
signal mul_temp_9_n_103 : STD_LOGIC;
signal mul_temp_9_n_104 : STD_LOGIC;
signal mul_temp_9_n_105 : STD_LOGIC;
signal mul_temp_9_n_74 : STD_LOGIC;
signal mul_temp_9_n_75 : STD_LOGIC;
signal mul_temp_9_n_76 : STD_LOGIC;
signal mul_temp_9_n_77 : STD_LOGIC;
signal mul_temp_9_n_78 : STD_LOGIC;
signal mul_temp_9_n_79 : STD_LOGIC;
signal mul_temp_9_n_80 : STD_LOGIC;
signal mul_temp_9_n_81 : STD_LOGIC;
signal mul_temp_9_n_82 : STD_LOGIC;
signal mul_temp_9_n_83 : STD_LOGIC;
signal mul_temp_9_n_84 : STD_LOGIC;
signal mul_temp_9_n_85 : STD_LOGIC;
signal mul_temp_9_n_86 : STD_LOGIC;
signal mul_temp_9_n_87 : STD_LOGIC;
signal mul_temp_9_n_88 : STD_LOGIC;
signal mul_temp_9_n_89 : STD_LOGIC;
signal mul_temp_9_n_90 : STD_LOGIC;
signal mul_temp_9_n_92 : STD_LOGIC;
signal mul_temp_9_n_93 : STD_LOGIC;
signal mul_temp_9_n_94 : STD_LOGIC;
signal mul_temp_9_n_95 : STD_LOGIC;
signal mul_temp_9_n_96 : STD_LOGIC;
signal mul_temp_9_n_97 : STD_LOGIC;
signal mul_temp_9_n_98 : STD_LOGIC;
signal mul_temp_9_n_99 : STD_LOGIC;
signal mul_temp_n_100 : STD_LOGIC;
signal mul_temp_n_101 : STD_LOGIC;
signal mul_temp_n_102 : STD_LOGIC;
signal mul_temp_n_103 : STD_LOGIC;
signal mul_temp_n_104 : STD_LOGIC;
signal mul_temp_n_105 : STD_LOGIC;
signal mul_temp_n_74 : STD_LOGIC;
signal mul_temp_n_75 : STD_LOGIC;
signal mul_temp_n_76 : STD_LOGIC;
signal mul_temp_n_77 : STD_LOGIC;
signal mul_temp_n_78 : STD_LOGIC;
signal mul_temp_n_79 : STD_LOGIC;
signal mul_temp_n_80 : STD_LOGIC;
signal mul_temp_n_81 : STD_LOGIC;
signal mul_temp_n_82 : STD_LOGIC;
signal mul_temp_n_83 : STD_LOGIC;
signal mul_temp_n_84 : STD_LOGIC;
signal mul_temp_n_85 : STD_LOGIC;
signal mul_temp_n_86 : STD_LOGIC;
signal mul_temp_n_87 : STD_LOGIC;
signal mul_temp_n_88 : STD_LOGIC;
signal mul_temp_n_89 : STD_LOGIC;
signal mul_temp_n_90 : STD_LOGIC;
signal mul_temp_n_92 : STD_LOGIC;
signal mul_temp_n_93 : STD_LOGIC;
signal mul_temp_n_94 : STD_LOGIC;
signal mul_temp_n_95 : STD_LOGIC;
signal mul_temp_n_96 : STD_LOGIC;
signal mul_temp_n_97 : STD_LOGIC;
signal mul_temp_n_98 : STD_LOGIC;
signal mul_temp_n_99 : STD_LOGIC;
signal \sub_temp_carry__0_n_0\ : STD_LOGIC;
signal \sub_temp_carry__0_n_1\ : STD_LOGIC;
signal \sub_temp_carry__0_n_2\ : STD_LOGIC;
signal \sub_temp_carry__0_n_3\ : STD_LOGIC;
signal \sub_temp_carry__1_n_0\ : STD_LOGIC;
signal \sub_temp_carry__1_n_1\ : STD_LOGIC;
signal \sub_temp_carry__1_n_2\ : STD_LOGIC;
signal \sub_temp_carry__1_n_3\ : STD_LOGIC;
signal \sub_temp_carry__2_n_1\ : STD_LOGIC;
signal \sub_temp_carry__2_n_2\ : STD_LOGIC;
signal \sub_temp_carry__2_n_3\ : STD_LOGIC;
signal sub_temp_carry_n_0 : STD_LOGIC;
signal sub_temp_carry_n_1 : STD_LOGIC;
signal sub_temp_carry_n_2 : STD_LOGIC;
signal sub_temp_carry_n_3 : STD_LOGIC;
signal \weight[0][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[0][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[0][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[0][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[0][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[0][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[0][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[0][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[0][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[0][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[0][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[0][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[0][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[0][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[0][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[0][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[10][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[10][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[10][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[10][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[10][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[10][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[10][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[10][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[10][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[10][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[10][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[10][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[10][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[10][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[10][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[10][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[11][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[11][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[11][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[11][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[11][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[11][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[11][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[11][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[11][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[11][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[11][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[11][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[11][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[11][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[11][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[11][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[12][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[12][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[12][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[12][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[12][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[12][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[12][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[12][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[12][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[12][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[12][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[12][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[12][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[12][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[12][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[12][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[13][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[13][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[13][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[13][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[13][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[13][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[13][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[13][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[13][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[13][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[13][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[13][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[13][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[13][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[13][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[13][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[14][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[14][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[14][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[14][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[14][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[14][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[14][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[14][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[14][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[14][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[14][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[14][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[14][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[14][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[14][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[14][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[15][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[15][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[15][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[15][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[15][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[15][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[15][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[15][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[15][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[15][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[15][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[15][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[15][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[15][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[15][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[15][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[1][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[1][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[1][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[1][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[1][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[1][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[1][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[1][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[1][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[1][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[1][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[1][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[1][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[1][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[1][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[1][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[2][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[2][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[2][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[2][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[2][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[2][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[2][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[2][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[2][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[2][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[2][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[2][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[2][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[2][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[2][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[2][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[3][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[3][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[3][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[3][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[3][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[3][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[3][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[3][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[3][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[3][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[3][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[3][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[3][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[3][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[3][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[3][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[4][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[4][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[4][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[4][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[4][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[4][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[4][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[4][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[4][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[4][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[4][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[4][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[4][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[4][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[4][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[4][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[5][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[5][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[5][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[5][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[5][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[5][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[5][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[5][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[5][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[5][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[5][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[5][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[5][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[5][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[5][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[5][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[6][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[6][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[6][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[6][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[6][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[6][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[6][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[6][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[6][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[6][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[6][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[6][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[6][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[6][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[6][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[6][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[7][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[7][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[7][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[7][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[7][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[7][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[7][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[7][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[7][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[7][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[7][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[7][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[7][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[7][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[7][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[7][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[8][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[8][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[8][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[8][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[8][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[8][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[8][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[8][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[8][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[8][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[8][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[8][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[8][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[8][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[8][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[8][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[9][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[9][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[9][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[9][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[9][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[9][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[9][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[9][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[9][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[9][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[9][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[9][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[9][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[9][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[9][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[9][8]_i_5_n_0\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[0]_15\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[10][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[10]_9\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[11][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[11]_10\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[12][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[12]_11\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[13][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[13]_12\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[14][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[14]_13\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[15][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[15]_14\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[1][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[1]_0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[2][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[2]_1\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[3][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[3]_2\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[4][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[4]_3\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[5][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[5]_4\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[6][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[6]_5\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[7][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[7]_6\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[8][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[8]_7\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[9][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[9]_8\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_ARG_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_ARG_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_ARG_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_ARG_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 30 );
signal NLW_ARG_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__0_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__1_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__1_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__1_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__1_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__1_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__10_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__10_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__10_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__10_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__10_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__11_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__11_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__11_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__11_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__11_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__12_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__12_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__12_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__12_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__12_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__13_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__13_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__13_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__13_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__13_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__14_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__14_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__14_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__14_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__14_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__15_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__15_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__15_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__15_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__15_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__16_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__16_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__16_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__16_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__16_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__17_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__17_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__17_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__17_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__17_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__18_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__18_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__18_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__18_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__18_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__19_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__19_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__19_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__19_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__19_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__2_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__2_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__2_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__2_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__2_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__20_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__20_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__20_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__20_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__20_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__21_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__21_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__21_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__21_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__21_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__22_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__22_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__22_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__22_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__22_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__23_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__23_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__23_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__23_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__23_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__24_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__24_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__24_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__24_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__24_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__25_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__25_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__25_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__25_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__25_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__26_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__26_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__26_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__26_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__26_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__27_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__27_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__27_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__27_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__27_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__28_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__28_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__28_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__28_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__28_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__29_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__29_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__29_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__29_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__29_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__3_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__3_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__3_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__3_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__3_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__30_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__30_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__30_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__30_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__30_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__4_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__4_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__4_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__4_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__4_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__5_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__5_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__5_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__5_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__5_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__6_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__6_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__6_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__6_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__6_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__7_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__7_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__7_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__7_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__7_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__8_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__8_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__8_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__8_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__8_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__9_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__9_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__9_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__9_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__9_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_ARG_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG_carry__3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_ARG_carry__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_add_temp_14__0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__138_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__184_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__230_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__278_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__46_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__92_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_mul_temp_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_1_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_1_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_1_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_1_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_1_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_10_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_10_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_10_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_10_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_10_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_11_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_11_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_11_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_11_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_11_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_12_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_12_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_12_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_12_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_12_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_13_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_13_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_13_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_13_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_13_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_14_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_14_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_14_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_14_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_14_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_15_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_15_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_15_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_15_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_15_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_17_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_17_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_17_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_17_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_17_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_18_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_18_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_18_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_18_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_18_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_19_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_19_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_19_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_19_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_19_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_2_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_2_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_2_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_2_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_2_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_20_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_20_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_20_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_20_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_20_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_21_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_21_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_21_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_21_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_21_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_22_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_22_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_22_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_22_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_22_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_23_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_23_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_23_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_23_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_23_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_24_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_24_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_24_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_24_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_24_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_25_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_25_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_25_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_25_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_25_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_26_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_26_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_26_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_26_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_26_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_27_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_27_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_27_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_27_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_27_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_28_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_28_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_28_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_28_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_28_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_29_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_29_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_29_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_29_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_29_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_3_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_3_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_3_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_3_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_3_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_30_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_30_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_30_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_30_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_30_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_31_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_31_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_31_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_31_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_31_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_32_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_32_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_32_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_32_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_32_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_4_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_4_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_4_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_4_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_4_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_5_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_5_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_5_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_5_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_5_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_6_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_6_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_6_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_6_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_6_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_7_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_7_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_7_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_7_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_7_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_8_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_8_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_8_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_8_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_8_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_9_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_9_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_9_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_9_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_9_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_sub_temp_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[0][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[10][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[11][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[12][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[13][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[14][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[15][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[1][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[2][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[3][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[4][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[5][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[6][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[7][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[8][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[9][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of ARG : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__0\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__1\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__10\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__11\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__12\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__13\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__14\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__15\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__16\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__17\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__18\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__19\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__2\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__20\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__21\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__22\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__23\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__24\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__25\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__26\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__27\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__28\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__29\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__3\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__30\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__4\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__5\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__6\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__7\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__8\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__9\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute HLUTNM : string;
attribute HLUTNM of \add_temp_14__0_carry__0_i_1\ : label is "lutpair6";
attribute HLUTNM of \add_temp_14__0_carry__0_i_2\ : label is "lutpair5";
attribute HLUTNM of \add_temp_14__0_carry__0_i_3\ : label is "lutpair4";
attribute HLUTNM of \add_temp_14__0_carry__0_i_4\ : label is "lutpair3";
attribute HLUTNM of \add_temp_14__0_carry__0_i_5\ : label is "lutpair7";
attribute HLUTNM of \add_temp_14__0_carry__0_i_6\ : label is "lutpair6";
attribute HLUTNM of \add_temp_14__0_carry__0_i_7\ : label is "lutpair5";
attribute HLUTNM of \add_temp_14__0_carry__0_i_8\ : label is "lutpair4";
attribute HLUTNM of \add_temp_14__0_carry__1_i_1\ : label is "lutpair10";
attribute HLUTNM of \add_temp_14__0_carry__1_i_2\ : label is "lutpair9";
attribute HLUTNM of \add_temp_14__0_carry__1_i_3\ : label is "lutpair8";
attribute HLUTNM of \add_temp_14__0_carry__1_i_4\ : label is "lutpair7";
attribute HLUTNM of \add_temp_14__0_carry__1_i_5\ : label is "lutpair11";
attribute HLUTNM of \add_temp_14__0_carry__1_i_6\ : label is "lutpair10";
attribute HLUTNM of \add_temp_14__0_carry__1_i_7\ : label is "lutpair9";
attribute HLUTNM of \add_temp_14__0_carry__1_i_8\ : label is "lutpair8";
attribute HLUTNM of \add_temp_14__0_carry__2_i_1\ : label is "lutpair13";
attribute HLUTNM of \add_temp_14__0_carry__2_i_2\ : label is "lutpair12";
attribute HLUTNM of \add_temp_14__0_carry__2_i_3\ : label is "lutpair11";
attribute HLUTNM of \add_temp_14__0_carry__2_i_6\ : label is "lutpair13";
attribute HLUTNM of \add_temp_14__0_carry__2_i_7\ : label is "lutpair12";
attribute HLUTNM of \add_temp_14__0_carry_i_1\ : label is "lutpair2";
attribute HLUTNM of \add_temp_14__0_carry_i_2\ : label is "lutpair1";
attribute HLUTNM of \add_temp_14__0_carry_i_3\ : label is "lutpair0";
attribute HLUTNM of \add_temp_14__0_carry_i_4\ : label is "lutpair3";
attribute HLUTNM of \add_temp_14__0_carry_i_5\ : label is "lutpair2";
attribute HLUTNM of \add_temp_14__0_carry_i_6\ : label is "lutpair1";
attribute HLUTNM of \add_temp_14__0_carry_i_7\ : label is "lutpair0";
attribute HLUTNM of \add_temp_14__138_carry__0_i_1\ : label is "lutpair48";
attribute HLUTNM of \add_temp_14__138_carry__0_i_2\ : label is "lutpair47";
attribute HLUTNM of \add_temp_14__138_carry__0_i_3\ : label is "lutpair46";
attribute HLUTNM of \add_temp_14__138_carry__0_i_4\ : label is "lutpair45";
attribute HLUTNM of \add_temp_14__138_carry__0_i_5\ : label is "lutpair49";
attribute HLUTNM of \add_temp_14__138_carry__0_i_6\ : label is "lutpair48";
attribute HLUTNM of \add_temp_14__138_carry__0_i_7\ : label is "lutpair47";
attribute HLUTNM of \add_temp_14__138_carry__0_i_8\ : label is "lutpair46";
attribute HLUTNM of \add_temp_14__138_carry__1_i_1\ : label is "lutpair52";
attribute HLUTNM of \add_temp_14__138_carry__1_i_2\ : label is "lutpair51";
attribute HLUTNM of \add_temp_14__138_carry__1_i_3\ : label is "lutpair50";
attribute HLUTNM of \add_temp_14__138_carry__1_i_4\ : label is "lutpair49";
attribute HLUTNM of \add_temp_14__138_carry__1_i_5\ : label is "lutpair53";
attribute HLUTNM of \add_temp_14__138_carry__1_i_6\ : label is "lutpair52";
attribute HLUTNM of \add_temp_14__138_carry__1_i_7\ : label is "lutpair51";
attribute HLUTNM of \add_temp_14__138_carry__1_i_8\ : label is "lutpair50";
attribute HLUTNM of \add_temp_14__138_carry__2_i_1\ : label is "lutpair55";
attribute HLUTNM of \add_temp_14__138_carry__2_i_2\ : label is "lutpair54";
attribute HLUTNM of \add_temp_14__138_carry__2_i_3\ : label is "lutpair53";
attribute HLUTNM of \add_temp_14__138_carry__2_i_6\ : label is "lutpair55";
attribute HLUTNM of \add_temp_14__138_carry__2_i_7\ : label is "lutpair54";
attribute HLUTNM of \add_temp_14__138_carry_i_1\ : label is "lutpair44";
attribute HLUTNM of \add_temp_14__138_carry_i_2\ : label is "lutpair43";
attribute HLUTNM of \add_temp_14__138_carry_i_3\ : label is "lutpair42";
attribute HLUTNM of \add_temp_14__138_carry_i_4\ : label is "lutpair45";
attribute HLUTNM of \add_temp_14__138_carry_i_5\ : label is "lutpair44";
attribute HLUTNM of \add_temp_14__138_carry_i_6\ : label is "lutpair43";
attribute HLUTNM of \add_temp_14__138_carry_i_7\ : label is "lutpair42";
attribute HLUTNM of \add_temp_14__184_carry__0_i_1\ : label is "lutpair62";
attribute HLUTNM of \add_temp_14__184_carry__0_i_2\ : label is "lutpair61";
attribute HLUTNM of \add_temp_14__184_carry__0_i_3\ : label is "lutpair60";
attribute HLUTNM of \add_temp_14__184_carry__0_i_4\ : label is "lutpair59";
attribute HLUTNM of \add_temp_14__184_carry__0_i_5\ : label is "lutpair63";
attribute HLUTNM of \add_temp_14__184_carry__0_i_6\ : label is "lutpair62";
attribute HLUTNM of \add_temp_14__184_carry__0_i_7\ : label is "lutpair61";
attribute HLUTNM of \add_temp_14__184_carry__0_i_8\ : label is "lutpair60";
attribute HLUTNM of \add_temp_14__184_carry__1_i_1\ : label is "lutpair66";
attribute HLUTNM of \add_temp_14__184_carry__1_i_2\ : label is "lutpair65";
attribute HLUTNM of \add_temp_14__184_carry__1_i_3\ : label is "lutpair64";
attribute HLUTNM of \add_temp_14__184_carry__1_i_4\ : label is "lutpair63";
attribute HLUTNM of \add_temp_14__184_carry__1_i_5\ : label is "lutpair67";
attribute HLUTNM of \add_temp_14__184_carry__1_i_6\ : label is "lutpair66";
attribute HLUTNM of \add_temp_14__184_carry__1_i_7\ : label is "lutpair65";
attribute HLUTNM of \add_temp_14__184_carry__1_i_8\ : label is "lutpair64";
attribute HLUTNM of \add_temp_14__184_carry__2_i_1\ : label is "lutpair69";
attribute HLUTNM of \add_temp_14__184_carry__2_i_2\ : label is "lutpair68";
attribute HLUTNM of \add_temp_14__184_carry__2_i_3\ : label is "lutpair67";
attribute HLUTNM of \add_temp_14__184_carry__2_i_6\ : label is "lutpair69";
attribute HLUTNM of \add_temp_14__184_carry__2_i_7\ : label is "lutpair68";
attribute HLUTNM of \add_temp_14__184_carry_i_1\ : label is "lutpair58";
attribute HLUTNM of \add_temp_14__184_carry_i_2\ : label is "lutpair57";
attribute HLUTNM of \add_temp_14__184_carry_i_3\ : label is "lutpair56";
attribute HLUTNM of \add_temp_14__184_carry_i_4\ : label is "lutpair59";
attribute HLUTNM of \add_temp_14__184_carry_i_5\ : label is "lutpair58";
attribute HLUTNM of \add_temp_14__184_carry_i_6\ : label is "lutpair57";
attribute HLUTNM of \add_temp_14__184_carry_i_7\ : label is "lutpair56";
attribute HLUTNM of \add_temp_14__230_carry__0_i_1\ : label is "lutpair76";
attribute HLUTNM of \add_temp_14__230_carry__0_i_2\ : label is "lutpair75";
attribute HLUTNM of \add_temp_14__230_carry__0_i_3\ : label is "lutpair74";
attribute HLUTNM of \add_temp_14__230_carry__0_i_4\ : label is "lutpair73";
attribute HLUTNM of \add_temp_14__230_carry__0_i_5\ : label is "lutpair77";
attribute HLUTNM of \add_temp_14__230_carry__0_i_6\ : label is "lutpair76";
attribute HLUTNM of \add_temp_14__230_carry__0_i_7\ : label is "lutpair75";
attribute HLUTNM of \add_temp_14__230_carry__0_i_8\ : label is "lutpair74";
attribute HLUTNM of \add_temp_14__230_carry__1_i_1\ : label is "lutpair80";
attribute HLUTNM of \add_temp_14__230_carry__1_i_2\ : label is "lutpair79";
attribute HLUTNM of \add_temp_14__230_carry__1_i_3\ : label is "lutpair78";
attribute HLUTNM of \add_temp_14__230_carry__1_i_4\ : label is "lutpair77";
attribute HLUTNM of \add_temp_14__230_carry__1_i_5\ : label is "lutpair81";
attribute HLUTNM of \add_temp_14__230_carry__1_i_6\ : label is "lutpair80";
attribute HLUTNM of \add_temp_14__230_carry__1_i_7\ : label is "lutpair79";
attribute HLUTNM of \add_temp_14__230_carry__1_i_8\ : label is "lutpair78";
attribute HLUTNM of \add_temp_14__230_carry__2_i_1\ : label is "lutpair83";
attribute HLUTNM of \add_temp_14__230_carry__2_i_2\ : label is "lutpair82";
attribute HLUTNM of \add_temp_14__230_carry__2_i_3\ : label is "lutpair81";
attribute HLUTNM of \add_temp_14__230_carry__2_i_6\ : label is "lutpair83";
attribute HLUTNM of \add_temp_14__230_carry__2_i_7\ : label is "lutpair82";
attribute HLUTNM of \add_temp_14__230_carry_i_1\ : label is "lutpair72";
attribute HLUTNM of \add_temp_14__230_carry_i_2\ : label is "lutpair71";
attribute HLUTNM of \add_temp_14__230_carry_i_3\ : label is "lutpair70";
attribute HLUTNM of \add_temp_14__230_carry_i_4\ : label is "lutpair73";
attribute HLUTNM of \add_temp_14__230_carry_i_5\ : label is "lutpair72";
attribute HLUTNM of \add_temp_14__230_carry_i_6\ : label is "lutpair71";
attribute HLUTNM of \add_temp_14__230_carry_i_7\ : label is "lutpair70";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \add_temp_14__278_carry__1_i_10\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \add_temp_14__278_carry__1_i_11\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \add_temp_14__278_carry__2_i_8\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \add_temp_14__278_carry__2_i_9\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \add_temp_14__278_carry_i_10\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \add_temp_14__278_carry_i_9\ : label is "soft_lutpair6";
attribute HLUTNM of \add_temp_14__46_carry__0_i_1\ : label is "lutpair20";
attribute HLUTNM of \add_temp_14__46_carry__0_i_2\ : label is "lutpair19";
attribute HLUTNM of \add_temp_14__46_carry__0_i_3\ : label is "lutpair18";
attribute HLUTNM of \add_temp_14__46_carry__0_i_4\ : label is "lutpair17";
attribute HLUTNM of \add_temp_14__46_carry__0_i_5\ : label is "lutpair21";
attribute HLUTNM of \add_temp_14__46_carry__0_i_6\ : label is "lutpair20";
attribute HLUTNM of \add_temp_14__46_carry__0_i_7\ : label is "lutpair19";
attribute HLUTNM of \add_temp_14__46_carry__0_i_8\ : label is "lutpair18";
attribute HLUTNM of \add_temp_14__46_carry__1_i_1\ : label is "lutpair24";
attribute HLUTNM of \add_temp_14__46_carry__1_i_2\ : label is "lutpair23";
attribute HLUTNM of \add_temp_14__46_carry__1_i_3\ : label is "lutpair22";
attribute HLUTNM of \add_temp_14__46_carry__1_i_4\ : label is "lutpair21";
attribute HLUTNM of \add_temp_14__46_carry__1_i_5\ : label is "lutpair25";
attribute HLUTNM of \add_temp_14__46_carry__1_i_6\ : label is "lutpair24";
attribute HLUTNM of \add_temp_14__46_carry__1_i_7\ : label is "lutpair23";
attribute HLUTNM of \add_temp_14__46_carry__1_i_8\ : label is "lutpair22";
attribute HLUTNM of \add_temp_14__46_carry__2_i_1\ : label is "lutpair27";
attribute HLUTNM of \add_temp_14__46_carry__2_i_2\ : label is "lutpair26";
attribute HLUTNM of \add_temp_14__46_carry__2_i_3\ : label is "lutpair25";
attribute HLUTNM of \add_temp_14__46_carry__2_i_6\ : label is "lutpair27";
attribute HLUTNM of \add_temp_14__46_carry__2_i_7\ : label is "lutpair26";
attribute HLUTNM of \add_temp_14__46_carry_i_1\ : label is "lutpair16";
attribute HLUTNM of \add_temp_14__46_carry_i_2\ : label is "lutpair15";
attribute HLUTNM of \add_temp_14__46_carry_i_3\ : label is "lutpair14";
attribute HLUTNM of \add_temp_14__46_carry_i_4\ : label is "lutpair17";
attribute HLUTNM of \add_temp_14__46_carry_i_5\ : label is "lutpair16";
attribute HLUTNM of \add_temp_14__46_carry_i_6\ : label is "lutpair15";
attribute HLUTNM of \add_temp_14__46_carry_i_7\ : label is "lutpair14";
attribute HLUTNM of \add_temp_14__92_carry__0_i_1\ : label is "lutpair34";
attribute HLUTNM of \add_temp_14__92_carry__0_i_2\ : label is "lutpair33";
attribute HLUTNM of \add_temp_14__92_carry__0_i_3\ : label is "lutpair32";
attribute HLUTNM of \add_temp_14__92_carry__0_i_4\ : label is "lutpair31";
attribute HLUTNM of \add_temp_14__92_carry__0_i_5\ : label is "lutpair35";
attribute HLUTNM of \add_temp_14__92_carry__0_i_6\ : label is "lutpair34";
attribute HLUTNM of \add_temp_14__92_carry__0_i_7\ : label is "lutpair33";
attribute HLUTNM of \add_temp_14__92_carry__0_i_8\ : label is "lutpair32";
attribute HLUTNM of \add_temp_14__92_carry__1_i_1\ : label is "lutpair38";
attribute HLUTNM of \add_temp_14__92_carry__1_i_2\ : label is "lutpair37";
attribute HLUTNM of \add_temp_14__92_carry__1_i_3\ : label is "lutpair36";
attribute HLUTNM of \add_temp_14__92_carry__1_i_4\ : label is "lutpair35";
attribute HLUTNM of \add_temp_14__92_carry__1_i_5\ : label is "lutpair39";
attribute HLUTNM of \add_temp_14__92_carry__1_i_6\ : label is "lutpair38";
attribute HLUTNM of \add_temp_14__92_carry__1_i_7\ : label is "lutpair37";
attribute HLUTNM of \add_temp_14__92_carry__1_i_8\ : label is "lutpair36";
attribute HLUTNM of \add_temp_14__92_carry__2_i_1\ : label is "lutpair41";
attribute HLUTNM of \add_temp_14__92_carry__2_i_2\ : label is "lutpair40";
attribute HLUTNM of \add_temp_14__92_carry__2_i_3\ : label is "lutpair39";
attribute HLUTNM of \add_temp_14__92_carry__2_i_6\ : label is "lutpair41";
attribute HLUTNM of \add_temp_14__92_carry__2_i_7\ : label is "lutpair40";
attribute HLUTNM of \add_temp_14__92_carry_i_1\ : label is "lutpair30";
attribute HLUTNM of \add_temp_14__92_carry_i_2\ : label is "lutpair29";
attribute HLUTNM of \add_temp_14__92_carry_i_3\ : label is "lutpair28";
attribute HLUTNM of \add_temp_14__92_carry_i_4\ : label is "lutpair31";
attribute HLUTNM of \add_temp_14__92_carry_i_5\ : label is "lutpair30";
attribute HLUTNM of \add_temp_14__92_carry_i_6\ : label is "lutpair29";
attribute HLUTNM of \add_temp_14__92_carry_i_7\ : label is "lutpair28";
attribute METHODOLOGY_DRC_VIOS of mul_temp : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_1 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_10 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_11 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_12 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_13 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_14 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_15 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_17 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_18 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_19 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_2 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_20 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_21 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_22 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_23 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_24 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_25 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_26 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_27 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_28 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_29 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_3 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_30 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_31 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_32 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_4 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_5 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_6 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_7 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_8 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_9 : label is "{SYNTH-13 {cell *THIS*}}";
begin
mul_temp_16(15 downto 0) <= \^mul_temp_16\(15 downto 0);
ARG: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[1]\(15),
A(28) => \data_pipeline_tmp_reg[1]\(15),
A(27) => \data_pipeline_tmp_reg[1]\(15),
A(26) => \data_pipeline_tmp_reg[1]\(15),
A(25) => \data_pipeline_tmp_reg[1]\(15),
A(24) => \data_pipeline_tmp_reg[1]\(15),
A(23) => \data_pipeline_tmp_reg[1]\(15),
A(22) => \data_pipeline_tmp_reg[1]\(15),
A(21) => \data_pipeline_tmp_reg[1]\(15),
A(20) => \data_pipeline_tmp_reg[1]\(15),
A(19) => \data_pipeline_tmp_reg[1]\(15),
A(18) => \data_pipeline_tmp_reg[1]\(15),
A(17) => \data_pipeline_tmp_reg[1]\(15),
A(16) => \data_pipeline_tmp_reg[1]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[1]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_ARG_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_ARG_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_18\(14),
C(12) => ARG_i_1_n_0,
C(11) => ARG_i_1_n_0,
C(10) => ARG_i_1_n_0,
C(9) => ARG_i_1_n_0,
C(8) => ARG_i_1_n_0,
C(7) => ARG_i_1_n_0,
C(6) => ARG_i_1_n_0,
C(5) => ARG_i_1_n_0,
C(4) => ARG_i_1_n_0,
C(3) => ARG_i_1_n_0,
C(2) => ARG_i_1_n_0,
C(1) => ARG_i_1_n_0,
C(0) => ARG_i_1_n_0,
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_ARG_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_ARG_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_ARG_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => NLW_ARG_OVERFLOW_UNCONNECTED,
P(47 downto 30) => NLW_ARG_P_UNCONNECTED(47 downto 30),
P(29 downto 14) => \in\(15 downto 0),
P(13) => ARG_n_92,
P(12) => ARG_n_93,
P(11) => ARG_n_94,
P(10) => ARG_n_95,
P(9) => ARG_n_96,
P(8) => ARG_n_97,
P(7) => ARG_n_98,
P(6) => ARG_n_99,
P(5) => ARG_n_100,
P(4) => ARG_n_101,
P(3) => ARG_n_102,
P(2) => ARG_n_103,
P(1) => ARG_n_104,
P(0) => ARG_n_105,
PATTERNBDETECT => NLW_ARG_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_ARG_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_ARG_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_ARG_UNDERFLOW_UNCONNECTED
);
\ARG__0\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[1]\(15),
A(28) => \data_pipeline_tmp_reg[1]\(15),
A(27) => \data_pipeline_tmp_reg[1]\(15),
A(26) => \data_pipeline_tmp_reg[1]\(15),
A(25) => \data_pipeline_tmp_reg[1]\(15),
A(24) => \data_pipeline_tmp_reg[1]\(15),
A(23) => \data_pipeline_tmp_reg[1]\(15),
A(22) => \data_pipeline_tmp_reg[1]\(15),
A(21) => \data_pipeline_tmp_reg[1]\(15),
A(20) => \data_pipeline_tmp_reg[1]\(15),
A(19) => \data_pipeline_tmp_reg[1]\(15),
A(18) => \data_pipeline_tmp_reg[1]\(15),
A(17) => \data_pipeline_tmp_reg[1]\(15),
A(16) => \data_pipeline_tmp_reg[1]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[1]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__0_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[1]_0\(15),
B(16) => \weight_reg[1]_0\(15),
B(15 downto 0) => \weight_reg[1]_0\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__0_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_1\(14),
C(12) => \ARG__0_i_1_n_0\,
C(11) => \ARG__0_i_1_n_0\,
C(10) => \ARG__0_i_1_n_0\,
C(9) => \ARG__0_i_1_n_0\,
C(8) => \ARG__0_i_1_n_0\,
C(7) => \ARG__0_i_1_n_0\,
C(6) => \ARG__0_i_1_n_0\,
C(5) => \ARG__0_i_1_n_0\,
C(4) => \ARG__0_i_1_n_0\,
C(3) => \ARG__0_i_1_n_0\,
C(2) => \ARG__0_i_1_n_0\,
C(1) => \ARG__0_i_1_n_0\,
C(0) => \ARG__0_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__0_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__0_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__0_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__0_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__0_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE16(15 downto 0),
P(13) => \ARG__0_n_92\,
P(12) => \ARG__0_n_93\,
P(11) => \ARG__0_n_94\,
P(10) => \ARG__0_n_95\,
P(9) => \ARG__0_n_96\,
P(8) => \ARG__0_n_97\,
P(7) => \ARG__0_n_98\,
P(6) => \ARG__0_n_99\,
P(5) => \ARG__0_n_100\,
P(4) => \ARG__0_n_101\,
P(3) => \ARG__0_n_102\,
P(2) => \ARG__0_n_103\,
P(1) => \ARG__0_n_104\,
P(0) => \ARG__0_n_105\,
PATTERNBDETECT => \NLW_ARG__0_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__0_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__0_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__0_UNDERFLOW_UNCONNECTED\
);
\ARG__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_1\(14),
O => \ARG__0_i_1_n_0\
);
\ARG__1\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[2]\(15),
A(28) => \data_pipeline_tmp_reg[2]\(15),
A(27) => \data_pipeline_tmp_reg[2]\(15),
A(26) => \data_pipeline_tmp_reg[2]\(15),
A(25) => \data_pipeline_tmp_reg[2]\(15),
A(24) => \data_pipeline_tmp_reg[2]\(15),
A(23) => \data_pipeline_tmp_reg[2]\(15),
A(22) => \data_pipeline_tmp_reg[2]\(15),
A(21) => \data_pipeline_tmp_reg[2]\(15),
A(20) => \data_pipeline_tmp_reg[2]\(15),
A(19) => \data_pipeline_tmp_reg[2]\(15),
A(18) => \data_pipeline_tmp_reg[2]\(15),
A(17) => \data_pipeline_tmp_reg[2]\(15),
A(16) => \data_pipeline_tmp_reg[2]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[2]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__1_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__1_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_19\(14),
C(12) => \ARG__1_i_1_n_0\,
C(11) => \ARG__1_i_1_n_0\,
C(10) => \ARG__1_i_1_n_0\,
C(9) => \ARG__1_i_1_n_0\,
C(8) => \ARG__1_i_1_n_0\,
C(7) => \ARG__1_i_1_n_0\,
C(6) => \ARG__1_i_1_n_0\,
C(5) => \ARG__1_i_1_n_0\,
C(4) => \ARG__1_i_1_n_0\,
C(3) => \ARG__1_i_1_n_0\,
C(2) => \ARG__1_i_1_n_0\,
C(1) => \ARG__1_i_1_n_0\,
C(0) => \ARG__1_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__1_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__1_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__1_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__1_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__1_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__1_n_76\,
P(28) => \ARG__1_n_77\,
P(27) => \ARG__1_n_78\,
P(26) => \ARG__1_n_79\,
P(25) => \ARG__1_n_80\,
P(24) => \ARG__1_n_81\,
P(23) => \ARG__1_n_82\,
P(22) => \ARG__1_n_83\,
P(21) => \ARG__1_n_84\,
P(20) => \ARG__1_n_85\,
P(19) => \ARG__1_n_86\,
P(18) => \ARG__1_n_87\,
P(17) => \ARG__1_n_88\,
P(16) => \ARG__1_n_89\,
P(15) => \ARG__1_n_90\,
P(14) => \ARG__1_n_91\,
P(13) => \ARG__1_n_92\,
P(12) => \ARG__1_n_93\,
P(11) => \ARG__1_n_94\,
P(10) => \ARG__1_n_95\,
P(9) => \ARG__1_n_96\,
P(8) => \ARG__1_n_97\,
P(7) => \ARG__1_n_98\,
P(6) => \ARG__1_n_99\,
P(5) => \ARG__1_n_100\,
P(4) => \ARG__1_n_101\,
P(3) => \ARG__1_n_102\,
P(2) => \ARG__1_n_103\,
P(1) => \ARG__1_n_104\,
P(0) => \ARG__1_n_105\,
PATTERNBDETECT => \NLW_ARG__1_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__1_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__1_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__1_UNDERFLOW_UNCONNECTED\
);
\ARG__10\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[6]\(15),
A(28) => \data_pipeline_tmp_reg[6]\(15),
A(27) => \data_pipeline_tmp_reg[6]\(15),
A(26) => \data_pipeline_tmp_reg[6]\(15),
A(25) => \data_pipeline_tmp_reg[6]\(15),
A(24) => \data_pipeline_tmp_reg[6]\(15),
A(23) => \data_pipeline_tmp_reg[6]\(15),
A(22) => \data_pipeline_tmp_reg[6]\(15),
A(21) => \data_pipeline_tmp_reg[6]\(15),
A(20) => \data_pipeline_tmp_reg[6]\(15),
A(19) => \data_pipeline_tmp_reg[6]\(15),
A(18) => \data_pipeline_tmp_reg[6]\(15),
A(17) => \data_pipeline_tmp_reg[6]\(15),
A(16) => \data_pipeline_tmp_reg[6]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[6]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__10_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[6]_5\(15),
B(16) => \weight_reg[6]_5\(15),
B(15 downto 0) => \weight_reg[6]_5\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__10_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_6\(14),
C(12) => \ARG__10_i_1_n_0\,
C(11) => \ARG__10_i_1_n_0\,
C(10) => \ARG__10_i_1_n_0\,
C(9) => \ARG__10_i_1_n_0\,
C(8) => \ARG__10_i_1_n_0\,
C(7) => \ARG__10_i_1_n_0\,
C(6) => \ARG__10_i_1_n_0\,
C(5) => \ARG__10_i_1_n_0\,
C(4) => \ARG__10_i_1_n_0\,
C(3) => \ARG__10_i_1_n_0\,
C(2) => \ARG__10_i_1_n_0\,
C(1) => \ARG__10_i_1_n_0\,
C(0) => \ARG__10_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__10_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__10_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__10_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__10_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__10_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE26(15 downto 0),
P(13) => \ARG__10_n_92\,
P(12) => \ARG__10_n_93\,
P(11) => \ARG__10_n_94\,
P(10) => \ARG__10_n_95\,
P(9) => \ARG__10_n_96\,
P(8) => \ARG__10_n_97\,
P(7) => \ARG__10_n_98\,
P(6) => \ARG__10_n_99\,
P(5) => \ARG__10_n_100\,
P(4) => \ARG__10_n_101\,
P(3) => \ARG__10_n_102\,
P(2) => \ARG__10_n_103\,
P(1) => \ARG__10_n_104\,
P(0) => \ARG__10_n_105\,
PATTERNBDETECT => \NLW_ARG__10_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__10_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__10_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__10_UNDERFLOW_UNCONNECTED\
);
\ARG__10_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_6\(14),
O => \ARG__10_i_1_n_0\
);
\ARG__11\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[7]\(15),
A(28) => \data_pipeline_tmp_reg[7]\(15),
A(27) => \data_pipeline_tmp_reg[7]\(15),
A(26) => \data_pipeline_tmp_reg[7]\(15),
A(25) => \data_pipeline_tmp_reg[7]\(15),
A(24) => \data_pipeline_tmp_reg[7]\(15),
A(23) => \data_pipeline_tmp_reg[7]\(15),
A(22) => \data_pipeline_tmp_reg[7]\(15),
A(21) => \data_pipeline_tmp_reg[7]\(15),
A(20) => \data_pipeline_tmp_reg[7]\(15),
A(19) => \data_pipeline_tmp_reg[7]\(15),
A(18) => \data_pipeline_tmp_reg[7]\(15),
A(17) => \data_pipeline_tmp_reg[7]\(15),
A(16) => \data_pipeline_tmp_reg[7]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[7]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__11_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__11_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_24\(14),
C(12) => \ARG__11_i_1_n_0\,
C(11) => \ARG__11_i_1_n_0\,
C(10) => \ARG__11_i_1_n_0\,
C(9) => \ARG__11_i_1_n_0\,
C(8) => \ARG__11_i_1_n_0\,
C(7) => \ARG__11_i_1_n_0\,
C(6) => \ARG__11_i_1_n_0\,
C(5) => \ARG__11_i_1_n_0\,
C(4) => \ARG__11_i_1_n_0\,
C(3) => \ARG__11_i_1_n_0\,
C(2) => \ARG__11_i_1_n_0\,
C(1) => \ARG__11_i_1_n_0\,
C(0) => \ARG__11_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__11_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__11_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__11_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__11_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__11_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__11_n_76\,
P(28) => \ARG__11_n_77\,
P(27) => \ARG__11_n_78\,
P(26) => \ARG__11_n_79\,
P(25) => \ARG__11_n_80\,
P(24) => \ARG__11_n_81\,
P(23) => \ARG__11_n_82\,
P(22) => \ARG__11_n_83\,
P(21) => \ARG__11_n_84\,
P(20) => \ARG__11_n_85\,
P(19) => \ARG__11_n_86\,
P(18) => \ARG__11_n_87\,
P(17) => \ARG__11_n_88\,
P(16) => \ARG__11_n_89\,
P(15) => \ARG__11_n_90\,
P(14) => \ARG__11_n_91\,
P(13) => \ARG__11_n_92\,
P(12) => \ARG__11_n_93\,
P(11) => \ARG__11_n_94\,
P(10) => \ARG__11_n_95\,
P(9) => \ARG__11_n_96\,
P(8) => \ARG__11_n_97\,
P(7) => \ARG__11_n_98\,
P(6) => \ARG__11_n_99\,
P(5) => \ARG__11_n_100\,
P(4) => \ARG__11_n_101\,
P(3) => \ARG__11_n_102\,
P(2) => \ARG__11_n_103\,
P(1) => \ARG__11_n_104\,
P(0) => \ARG__11_n_105\,
PATTERNBDETECT => \NLW_ARG__11_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__11_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__11_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__11_UNDERFLOW_UNCONNECTED\
);
\ARG__11_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_24\(14),
O => \ARG__11_i_1_n_0\
);
\ARG__12\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[7]\(15),
A(28) => \data_pipeline_tmp_reg[7]\(15),
A(27) => \data_pipeline_tmp_reg[7]\(15),
A(26) => \data_pipeline_tmp_reg[7]\(15),
A(25) => \data_pipeline_tmp_reg[7]\(15),
A(24) => \data_pipeline_tmp_reg[7]\(15),
A(23) => \data_pipeline_tmp_reg[7]\(15),
A(22) => \data_pipeline_tmp_reg[7]\(15),
A(21) => \data_pipeline_tmp_reg[7]\(15),
A(20) => \data_pipeline_tmp_reg[7]\(15),
A(19) => \data_pipeline_tmp_reg[7]\(15),
A(18) => \data_pipeline_tmp_reg[7]\(15),
A(17) => \data_pipeline_tmp_reg[7]\(15),
A(16) => \data_pipeline_tmp_reg[7]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[7]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__12_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[7]_6\(15),
B(16) => \weight_reg[7]_6\(15),
B(15 downto 0) => \weight_reg[7]_6\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__12_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_7\(14),
C(12) => \ARG__12_i_1_n_0\,
C(11) => \ARG__12_i_1_n_0\,
C(10) => \ARG__12_i_1_n_0\,
C(9) => \ARG__12_i_1_n_0\,
C(8) => \ARG__12_i_1_n_0\,
C(7) => \ARG__12_i_1_n_0\,
C(6) => \ARG__12_i_1_n_0\,
C(5) => \ARG__12_i_1_n_0\,
C(4) => \ARG__12_i_1_n_0\,
C(3) => \ARG__12_i_1_n_0\,
C(2) => \ARG__12_i_1_n_0\,
C(1) => \ARG__12_i_1_n_0\,
C(0) => \ARG__12_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__12_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__12_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__12_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__12_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__12_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE28(15 downto 0),
P(13) => \ARG__12_n_92\,
P(12) => \ARG__12_n_93\,
P(11) => \ARG__12_n_94\,
P(10) => \ARG__12_n_95\,
P(9) => \ARG__12_n_96\,
P(8) => \ARG__12_n_97\,
P(7) => \ARG__12_n_98\,
P(6) => \ARG__12_n_99\,
P(5) => \ARG__12_n_100\,
P(4) => \ARG__12_n_101\,
P(3) => \ARG__12_n_102\,
P(2) => \ARG__12_n_103\,
P(1) => \ARG__12_n_104\,
P(0) => \ARG__12_n_105\,
PATTERNBDETECT => \NLW_ARG__12_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__12_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__12_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__12_UNDERFLOW_UNCONNECTED\
);
\ARG__12_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_7\(14),
O => \ARG__12_i_1_n_0\
);
\ARG__13\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[8]\(15),
A(28) => \data_pipeline_tmp_reg[8]\(15),
A(27) => \data_pipeline_tmp_reg[8]\(15),
A(26) => \data_pipeline_tmp_reg[8]\(15),
A(25) => \data_pipeline_tmp_reg[8]\(15),
A(24) => \data_pipeline_tmp_reg[8]\(15),
A(23) => \data_pipeline_tmp_reg[8]\(15),
A(22) => \data_pipeline_tmp_reg[8]\(15),
A(21) => \data_pipeline_tmp_reg[8]\(15),
A(20) => \data_pipeline_tmp_reg[8]\(15),
A(19) => \data_pipeline_tmp_reg[8]\(15),
A(18) => \data_pipeline_tmp_reg[8]\(15),
A(17) => \data_pipeline_tmp_reg[8]\(15),
A(16) => \data_pipeline_tmp_reg[8]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[8]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__13_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__13_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_25\(14),
C(12) => \ARG__13_i_1_n_0\,
C(11) => \ARG__13_i_1_n_0\,
C(10) => \ARG__13_i_1_n_0\,
C(9) => \ARG__13_i_1_n_0\,
C(8) => \ARG__13_i_1_n_0\,
C(7) => \ARG__13_i_1_n_0\,
C(6) => \ARG__13_i_1_n_0\,
C(5) => \ARG__13_i_1_n_0\,
C(4) => \ARG__13_i_1_n_0\,
C(3) => \ARG__13_i_1_n_0\,
C(2) => \ARG__13_i_1_n_0\,
C(1) => \ARG__13_i_1_n_0\,
C(0) => \ARG__13_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__13_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__13_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__13_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__13_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__13_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__13_n_76\,
P(28) => \ARG__13_n_77\,
P(27) => \ARG__13_n_78\,
P(26) => \ARG__13_n_79\,
P(25) => \ARG__13_n_80\,
P(24) => \ARG__13_n_81\,
P(23) => \ARG__13_n_82\,
P(22) => \ARG__13_n_83\,
P(21) => \ARG__13_n_84\,
P(20) => \ARG__13_n_85\,
P(19) => \ARG__13_n_86\,
P(18) => \ARG__13_n_87\,
P(17) => \ARG__13_n_88\,
P(16) => \ARG__13_n_89\,
P(15) => \ARG__13_n_90\,
P(14) => \ARG__13_n_91\,
P(13) => \ARG__13_n_92\,
P(12) => \ARG__13_n_93\,
P(11) => \ARG__13_n_94\,
P(10) => \ARG__13_n_95\,
P(9) => \ARG__13_n_96\,
P(8) => \ARG__13_n_97\,
P(7) => \ARG__13_n_98\,
P(6) => \ARG__13_n_99\,
P(5) => \ARG__13_n_100\,
P(4) => \ARG__13_n_101\,
P(3) => \ARG__13_n_102\,
P(2) => \ARG__13_n_103\,
P(1) => \ARG__13_n_104\,
P(0) => \ARG__13_n_105\,
PATTERNBDETECT => \NLW_ARG__13_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__13_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__13_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__13_UNDERFLOW_UNCONNECTED\
);
\ARG__13_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_25\(14),
O => \ARG__13_i_1_n_0\
);
\ARG__14\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[8]\(15),
A(28) => \data_pipeline_tmp_reg[8]\(15),
A(27) => \data_pipeline_tmp_reg[8]\(15),
A(26) => \data_pipeline_tmp_reg[8]\(15),
A(25) => \data_pipeline_tmp_reg[8]\(15),
A(24) => \data_pipeline_tmp_reg[8]\(15),
A(23) => \data_pipeline_tmp_reg[8]\(15),
A(22) => \data_pipeline_tmp_reg[8]\(15),
A(21) => \data_pipeline_tmp_reg[8]\(15),
A(20) => \data_pipeline_tmp_reg[8]\(15),
A(19) => \data_pipeline_tmp_reg[8]\(15),
A(18) => \data_pipeline_tmp_reg[8]\(15),
A(17) => \data_pipeline_tmp_reg[8]\(15),
A(16) => \data_pipeline_tmp_reg[8]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[8]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__14_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[8]_7\(15),
B(16) => \weight_reg[8]_7\(15),
B(15 downto 0) => \weight_reg[8]_7\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__14_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_8\(14),
C(12) => \ARG__14_i_1_n_0\,
C(11) => \ARG__14_i_1_n_0\,
C(10) => \ARG__14_i_1_n_0\,
C(9) => \ARG__14_i_1_n_0\,
C(8) => \ARG__14_i_1_n_0\,
C(7) => \ARG__14_i_1_n_0\,
C(6) => \ARG__14_i_1_n_0\,
C(5) => \ARG__14_i_1_n_0\,
C(4) => \ARG__14_i_1_n_0\,
C(3) => \ARG__14_i_1_n_0\,
C(2) => \ARG__14_i_1_n_0\,
C(1) => \ARG__14_i_1_n_0\,
C(0) => \ARG__14_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__14_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__14_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__14_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__14_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__14_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE30(15 downto 0),
P(13) => \ARG__14_n_92\,
P(12) => \ARG__14_n_93\,
P(11) => \ARG__14_n_94\,
P(10) => \ARG__14_n_95\,
P(9) => \ARG__14_n_96\,
P(8) => \ARG__14_n_97\,
P(7) => \ARG__14_n_98\,
P(6) => \ARG__14_n_99\,
P(5) => \ARG__14_n_100\,
P(4) => \ARG__14_n_101\,
P(3) => \ARG__14_n_102\,
P(2) => \ARG__14_n_103\,
P(1) => \ARG__14_n_104\,
P(0) => \ARG__14_n_105\,
PATTERNBDETECT => \NLW_ARG__14_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__14_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__14_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__14_UNDERFLOW_UNCONNECTED\
);
\ARG__14_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_8\(14),
O => \ARG__14_i_1_n_0\
);
\ARG__15\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[9]\(15),
A(28) => \data_pipeline_tmp_reg[9]\(15),
A(27) => \data_pipeline_tmp_reg[9]\(15),
A(26) => \data_pipeline_tmp_reg[9]\(15),
A(25) => \data_pipeline_tmp_reg[9]\(15),
A(24) => \data_pipeline_tmp_reg[9]\(15),
A(23) => \data_pipeline_tmp_reg[9]\(15),
A(22) => \data_pipeline_tmp_reg[9]\(15),
A(21) => \data_pipeline_tmp_reg[9]\(15),
A(20) => \data_pipeline_tmp_reg[9]\(15),
A(19) => \data_pipeline_tmp_reg[9]\(15),
A(18) => \data_pipeline_tmp_reg[9]\(15),
A(17) => \data_pipeline_tmp_reg[9]\(15),
A(16) => \data_pipeline_tmp_reg[9]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[9]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__15_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__15_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_26\(14),
C(12) => \ARG__15_i_1_n_0\,
C(11) => \ARG__15_i_1_n_0\,
C(10) => \ARG__15_i_1_n_0\,
C(9) => \ARG__15_i_1_n_0\,
C(8) => \ARG__15_i_1_n_0\,
C(7) => \ARG__15_i_1_n_0\,
C(6) => \ARG__15_i_1_n_0\,
C(5) => \ARG__15_i_1_n_0\,
C(4) => \ARG__15_i_1_n_0\,
C(3) => \ARG__15_i_1_n_0\,
C(2) => \ARG__15_i_1_n_0\,
C(1) => \ARG__15_i_1_n_0\,
C(0) => \ARG__15_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__15_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__15_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__15_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__15_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__15_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__15_n_76\,
P(28) => \ARG__15_n_77\,
P(27) => \ARG__15_n_78\,
P(26) => \ARG__15_n_79\,
P(25) => \ARG__15_n_80\,
P(24) => \ARG__15_n_81\,
P(23) => \ARG__15_n_82\,
P(22) => \ARG__15_n_83\,
P(21) => \ARG__15_n_84\,
P(20) => \ARG__15_n_85\,
P(19) => \ARG__15_n_86\,
P(18) => \ARG__15_n_87\,
P(17) => \ARG__15_n_88\,
P(16) => \ARG__15_n_89\,
P(15) => \ARG__15_n_90\,
P(14) => \ARG__15_n_91\,
P(13) => \ARG__15_n_92\,
P(12) => \ARG__15_n_93\,
P(11) => \ARG__15_n_94\,
P(10) => \ARG__15_n_95\,
P(9) => \ARG__15_n_96\,
P(8) => \ARG__15_n_97\,
P(7) => \ARG__15_n_98\,
P(6) => \ARG__15_n_99\,
P(5) => \ARG__15_n_100\,
P(4) => \ARG__15_n_101\,
P(3) => \ARG__15_n_102\,
P(2) => \ARG__15_n_103\,
P(1) => \ARG__15_n_104\,
P(0) => \ARG__15_n_105\,
PATTERNBDETECT => \NLW_ARG__15_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__15_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__15_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__15_UNDERFLOW_UNCONNECTED\
);
\ARG__15_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_26\(14),
O => \ARG__15_i_1_n_0\
);
\ARG__16\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[9]\(15),
A(28) => \data_pipeline_tmp_reg[9]\(15),
A(27) => \data_pipeline_tmp_reg[9]\(15),
A(26) => \data_pipeline_tmp_reg[9]\(15),
A(25) => \data_pipeline_tmp_reg[9]\(15),
A(24) => \data_pipeline_tmp_reg[9]\(15),
A(23) => \data_pipeline_tmp_reg[9]\(15),
A(22) => \data_pipeline_tmp_reg[9]\(15),
A(21) => \data_pipeline_tmp_reg[9]\(15),
A(20) => \data_pipeline_tmp_reg[9]\(15),
A(19) => \data_pipeline_tmp_reg[9]\(15),
A(18) => \data_pipeline_tmp_reg[9]\(15),
A(17) => \data_pipeline_tmp_reg[9]\(15),
A(16) => \data_pipeline_tmp_reg[9]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[9]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__16_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[9]_8\(15),
B(16) => \weight_reg[9]_8\(15),
B(15 downto 0) => \weight_reg[9]_8\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__16_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_9\(14),
C(12) => \ARG__16_i_1_n_0\,
C(11) => \ARG__16_i_1_n_0\,
C(10) => \ARG__16_i_1_n_0\,
C(9) => \ARG__16_i_1_n_0\,
C(8) => \ARG__16_i_1_n_0\,
C(7) => \ARG__16_i_1_n_0\,
C(6) => \ARG__16_i_1_n_0\,
C(5) => \ARG__16_i_1_n_0\,
C(4) => \ARG__16_i_1_n_0\,
C(3) => \ARG__16_i_1_n_0\,
C(2) => \ARG__16_i_1_n_0\,
C(1) => \ARG__16_i_1_n_0\,
C(0) => \ARG__16_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__16_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__16_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__16_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__16_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__16_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE32(15 downto 0),
P(13) => \ARG__16_n_92\,
P(12) => \ARG__16_n_93\,
P(11) => \ARG__16_n_94\,
P(10) => \ARG__16_n_95\,
P(9) => \ARG__16_n_96\,
P(8) => \ARG__16_n_97\,
P(7) => \ARG__16_n_98\,
P(6) => \ARG__16_n_99\,
P(5) => \ARG__16_n_100\,
P(4) => \ARG__16_n_101\,
P(3) => \ARG__16_n_102\,
P(2) => \ARG__16_n_103\,
P(1) => \ARG__16_n_104\,
P(0) => \ARG__16_n_105\,
PATTERNBDETECT => \NLW_ARG__16_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__16_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__16_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__16_UNDERFLOW_UNCONNECTED\
);
\ARG__16_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_9\(14),
O => \ARG__16_i_1_n_0\
);
\ARG__17\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[10]\(15),
A(28) => \data_pipeline_tmp_reg[10]\(15),
A(27) => \data_pipeline_tmp_reg[10]\(15),
A(26) => \data_pipeline_tmp_reg[10]\(15),
A(25) => \data_pipeline_tmp_reg[10]\(15),
A(24) => \data_pipeline_tmp_reg[10]\(15),
A(23) => \data_pipeline_tmp_reg[10]\(15),
A(22) => \data_pipeline_tmp_reg[10]\(15),
A(21) => \data_pipeline_tmp_reg[10]\(15),
A(20) => \data_pipeline_tmp_reg[10]\(15),
A(19) => \data_pipeline_tmp_reg[10]\(15),
A(18) => \data_pipeline_tmp_reg[10]\(15),
A(17) => \data_pipeline_tmp_reg[10]\(15),
A(16) => \data_pipeline_tmp_reg[10]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[10]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__17_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__17_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_27\(14),
C(12) => \ARG__17_i_1_n_0\,
C(11) => \ARG__17_i_1_n_0\,
C(10) => \ARG__17_i_1_n_0\,
C(9) => \ARG__17_i_1_n_0\,
C(8) => \ARG__17_i_1_n_0\,
C(7) => \ARG__17_i_1_n_0\,
C(6) => \ARG__17_i_1_n_0\,
C(5) => \ARG__17_i_1_n_0\,
C(4) => \ARG__17_i_1_n_0\,
C(3) => \ARG__17_i_1_n_0\,
C(2) => \ARG__17_i_1_n_0\,
C(1) => \ARG__17_i_1_n_0\,
C(0) => \ARG__17_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__17_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__17_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__17_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__17_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__17_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__17_n_76\,
P(28) => \ARG__17_n_77\,
P(27) => \ARG__17_n_78\,
P(26) => \ARG__17_n_79\,
P(25) => \ARG__17_n_80\,
P(24) => \ARG__17_n_81\,
P(23) => \ARG__17_n_82\,
P(22) => \ARG__17_n_83\,
P(21) => \ARG__17_n_84\,
P(20) => \ARG__17_n_85\,
P(19) => \ARG__17_n_86\,
P(18) => \ARG__17_n_87\,
P(17) => \ARG__17_n_88\,
P(16) => \ARG__17_n_89\,
P(15) => \ARG__17_n_90\,
P(14) => \ARG__17_n_91\,
P(13) => \ARG__17_n_92\,
P(12) => \ARG__17_n_93\,
P(11) => \ARG__17_n_94\,
P(10) => \ARG__17_n_95\,
P(9) => \ARG__17_n_96\,
P(8) => \ARG__17_n_97\,
P(7) => \ARG__17_n_98\,
P(6) => \ARG__17_n_99\,
P(5) => \ARG__17_n_100\,
P(4) => \ARG__17_n_101\,
P(3) => \ARG__17_n_102\,
P(2) => \ARG__17_n_103\,
P(1) => \ARG__17_n_104\,
P(0) => \ARG__17_n_105\,
PATTERNBDETECT => \NLW_ARG__17_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__17_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__17_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__17_UNDERFLOW_UNCONNECTED\
);
\ARG__17_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_27\(14),
O => \ARG__17_i_1_n_0\
);
\ARG__18\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[10]\(15),
A(28) => \data_pipeline_tmp_reg[10]\(15),
A(27) => \data_pipeline_tmp_reg[10]\(15),
A(26) => \data_pipeline_tmp_reg[10]\(15),
A(25) => \data_pipeline_tmp_reg[10]\(15),
A(24) => \data_pipeline_tmp_reg[10]\(15),
A(23) => \data_pipeline_tmp_reg[10]\(15),
A(22) => \data_pipeline_tmp_reg[10]\(15),
A(21) => \data_pipeline_tmp_reg[10]\(15),
A(20) => \data_pipeline_tmp_reg[10]\(15),
A(19) => \data_pipeline_tmp_reg[10]\(15),
A(18) => \data_pipeline_tmp_reg[10]\(15),
A(17) => \data_pipeline_tmp_reg[10]\(15),
A(16) => \data_pipeline_tmp_reg[10]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[10]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__18_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[10]_9\(15),
B(16) => \weight_reg[10]_9\(15),
B(15 downto 0) => \weight_reg[10]_9\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__18_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_10\(14),
C(12) => \ARG__18_i_1_n_0\,
C(11) => \ARG__18_i_1_n_0\,
C(10) => \ARG__18_i_1_n_0\,
C(9) => \ARG__18_i_1_n_0\,
C(8) => \ARG__18_i_1_n_0\,
C(7) => \ARG__18_i_1_n_0\,
C(6) => \ARG__18_i_1_n_0\,
C(5) => \ARG__18_i_1_n_0\,
C(4) => \ARG__18_i_1_n_0\,
C(3) => \ARG__18_i_1_n_0\,
C(2) => \ARG__18_i_1_n_0\,
C(1) => \ARG__18_i_1_n_0\,
C(0) => \ARG__18_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__18_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__18_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__18_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__18_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__18_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE34(15 downto 0),
P(13) => \ARG__18_n_92\,
P(12) => \ARG__18_n_93\,
P(11) => \ARG__18_n_94\,
P(10) => \ARG__18_n_95\,
P(9) => \ARG__18_n_96\,
P(8) => \ARG__18_n_97\,
P(7) => \ARG__18_n_98\,
P(6) => \ARG__18_n_99\,
P(5) => \ARG__18_n_100\,
P(4) => \ARG__18_n_101\,
P(3) => \ARG__18_n_102\,
P(2) => \ARG__18_n_103\,
P(1) => \ARG__18_n_104\,
P(0) => \ARG__18_n_105\,
PATTERNBDETECT => \NLW_ARG__18_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__18_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__18_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__18_UNDERFLOW_UNCONNECTED\
);
\ARG__18_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_10\(14),
O => \ARG__18_i_1_n_0\
);
\ARG__19\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[11]\(15),
A(28) => \data_pipeline_tmp_reg[11]\(15),
A(27) => \data_pipeline_tmp_reg[11]\(15),
A(26) => \data_pipeline_tmp_reg[11]\(15),
A(25) => \data_pipeline_tmp_reg[11]\(15),
A(24) => \data_pipeline_tmp_reg[11]\(15),
A(23) => \data_pipeline_tmp_reg[11]\(15),
A(22) => \data_pipeline_tmp_reg[11]\(15),
A(21) => \data_pipeline_tmp_reg[11]\(15),
A(20) => \data_pipeline_tmp_reg[11]\(15),
A(19) => \data_pipeline_tmp_reg[11]\(15),
A(18) => \data_pipeline_tmp_reg[11]\(15),
A(17) => \data_pipeline_tmp_reg[11]\(15),
A(16) => \data_pipeline_tmp_reg[11]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[11]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__19_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__19_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_28\(14),
C(12) => \ARG__19_i_1_n_0\,
C(11) => \ARG__19_i_1_n_0\,
C(10) => \ARG__19_i_1_n_0\,
C(9) => \ARG__19_i_1_n_0\,
C(8) => \ARG__19_i_1_n_0\,
C(7) => \ARG__19_i_1_n_0\,
C(6) => \ARG__19_i_1_n_0\,
C(5) => \ARG__19_i_1_n_0\,
C(4) => \ARG__19_i_1_n_0\,
C(3) => \ARG__19_i_1_n_0\,
C(2) => \ARG__19_i_1_n_0\,
C(1) => \ARG__19_i_1_n_0\,
C(0) => \ARG__19_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__19_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__19_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__19_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__19_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__19_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__19_n_76\,
P(28) => \ARG__19_n_77\,
P(27) => \ARG__19_n_78\,
P(26) => \ARG__19_n_79\,
P(25) => \ARG__19_n_80\,
P(24) => \ARG__19_n_81\,
P(23) => \ARG__19_n_82\,
P(22) => \ARG__19_n_83\,
P(21) => \ARG__19_n_84\,
P(20) => \ARG__19_n_85\,
P(19) => \ARG__19_n_86\,
P(18) => \ARG__19_n_87\,
P(17) => \ARG__19_n_88\,
P(16) => \ARG__19_n_89\,
P(15) => \ARG__19_n_90\,
P(14) => \ARG__19_n_91\,
P(13) => \ARG__19_n_92\,
P(12) => \ARG__19_n_93\,
P(11) => \ARG__19_n_94\,
P(10) => \ARG__19_n_95\,
P(9) => \ARG__19_n_96\,
P(8) => \ARG__19_n_97\,
P(7) => \ARG__19_n_98\,
P(6) => \ARG__19_n_99\,
P(5) => \ARG__19_n_100\,
P(4) => \ARG__19_n_101\,
P(3) => \ARG__19_n_102\,
P(2) => \ARG__19_n_103\,
P(1) => \ARG__19_n_104\,
P(0) => \ARG__19_n_105\,
PATTERNBDETECT => \NLW_ARG__19_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__19_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__19_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__19_UNDERFLOW_UNCONNECTED\
);
\ARG__19_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_28\(14),
O => \ARG__19_i_1_n_0\
);
\ARG__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_19\(14),
O => \ARG__1_i_1_n_0\
);
\ARG__2\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[2]\(15),
A(28) => \data_pipeline_tmp_reg[2]\(15),
A(27) => \data_pipeline_tmp_reg[2]\(15),
A(26) => \data_pipeline_tmp_reg[2]\(15),
A(25) => \data_pipeline_tmp_reg[2]\(15),
A(24) => \data_pipeline_tmp_reg[2]\(15),
A(23) => \data_pipeline_tmp_reg[2]\(15),
A(22) => \data_pipeline_tmp_reg[2]\(15),
A(21) => \data_pipeline_tmp_reg[2]\(15),
A(20) => \data_pipeline_tmp_reg[2]\(15),
A(19) => \data_pipeline_tmp_reg[2]\(15),
A(18) => \data_pipeline_tmp_reg[2]\(15),
A(17) => \data_pipeline_tmp_reg[2]\(15),
A(16) => \data_pipeline_tmp_reg[2]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[2]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__2_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[2]_1\(15),
B(16) => \weight_reg[2]_1\(15),
B(15 downto 0) => \weight_reg[2]_1\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__2_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_2\(14),
C(12) => \ARG__2_i_1_n_0\,
C(11) => \ARG__2_i_1_n_0\,
C(10) => \ARG__2_i_1_n_0\,
C(9) => \ARG__2_i_1_n_0\,
C(8) => \ARG__2_i_1_n_0\,
C(7) => \ARG__2_i_1_n_0\,
C(6) => \ARG__2_i_1_n_0\,
C(5) => \ARG__2_i_1_n_0\,
C(4) => \ARG__2_i_1_n_0\,
C(3) => \ARG__2_i_1_n_0\,
C(2) => \ARG__2_i_1_n_0\,
C(1) => \ARG__2_i_1_n_0\,
C(0) => \ARG__2_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__2_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__2_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__2_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__2_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__2_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE18(15 downto 0),
P(13) => \ARG__2_n_92\,
P(12) => \ARG__2_n_93\,
P(11) => \ARG__2_n_94\,
P(10) => \ARG__2_n_95\,
P(9) => \ARG__2_n_96\,
P(8) => \ARG__2_n_97\,
P(7) => \ARG__2_n_98\,
P(6) => \ARG__2_n_99\,
P(5) => \ARG__2_n_100\,
P(4) => \ARG__2_n_101\,
P(3) => \ARG__2_n_102\,
P(2) => \ARG__2_n_103\,
P(1) => \ARG__2_n_104\,
P(0) => \ARG__2_n_105\,
PATTERNBDETECT => \NLW_ARG__2_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__2_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__2_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__2_UNDERFLOW_UNCONNECTED\
);
\ARG__20\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[11]\(15),
A(28) => \data_pipeline_tmp_reg[11]\(15),
A(27) => \data_pipeline_tmp_reg[11]\(15),
A(26) => \data_pipeline_tmp_reg[11]\(15),
A(25) => \data_pipeline_tmp_reg[11]\(15),
A(24) => \data_pipeline_tmp_reg[11]\(15),
A(23) => \data_pipeline_tmp_reg[11]\(15),
A(22) => \data_pipeline_tmp_reg[11]\(15),
A(21) => \data_pipeline_tmp_reg[11]\(15),
A(20) => \data_pipeline_tmp_reg[11]\(15),
A(19) => \data_pipeline_tmp_reg[11]\(15),
A(18) => \data_pipeline_tmp_reg[11]\(15),
A(17) => \data_pipeline_tmp_reg[11]\(15),
A(16) => \data_pipeline_tmp_reg[11]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[11]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__20_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[11]_10\(15),
B(16) => \weight_reg[11]_10\(15),
B(15 downto 0) => \weight_reg[11]_10\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__20_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_11\(14),
C(12) => \ARG__20_i_1_n_0\,
C(11) => \ARG__20_i_1_n_0\,
C(10) => \ARG__20_i_1_n_0\,
C(9) => \ARG__20_i_1_n_0\,
C(8) => \ARG__20_i_1_n_0\,
C(7) => \ARG__20_i_1_n_0\,
C(6) => \ARG__20_i_1_n_0\,
C(5) => \ARG__20_i_1_n_0\,
C(4) => \ARG__20_i_1_n_0\,
C(3) => \ARG__20_i_1_n_0\,
C(2) => \ARG__20_i_1_n_0\,
C(1) => \ARG__20_i_1_n_0\,
C(0) => \ARG__20_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__20_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__20_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__20_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__20_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__20_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE36(15 downto 0),
P(13) => \ARG__20_n_92\,
P(12) => \ARG__20_n_93\,
P(11) => \ARG__20_n_94\,
P(10) => \ARG__20_n_95\,
P(9) => \ARG__20_n_96\,
P(8) => \ARG__20_n_97\,
P(7) => \ARG__20_n_98\,
P(6) => \ARG__20_n_99\,
P(5) => \ARG__20_n_100\,
P(4) => \ARG__20_n_101\,
P(3) => \ARG__20_n_102\,
P(2) => \ARG__20_n_103\,
P(1) => \ARG__20_n_104\,
P(0) => \ARG__20_n_105\,
PATTERNBDETECT => \NLW_ARG__20_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__20_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__20_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__20_UNDERFLOW_UNCONNECTED\
);
\ARG__20_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_11\(14),
O => \ARG__20_i_1_n_0\
);
\ARG__21\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[12]\(15),
A(28) => \data_pipeline_tmp_reg[12]\(15),
A(27) => \data_pipeline_tmp_reg[12]\(15),
A(26) => \data_pipeline_tmp_reg[12]\(15),
A(25) => \data_pipeline_tmp_reg[12]\(15),
A(24) => \data_pipeline_tmp_reg[12]\(15),
A(23) => \data_pipeline_tmp_reg[12]\(15),
A(22) => \data_pipeline_tmp_reg[12]\(15),
A(21) => \data_pipeline_tmp_reg[12]\(15),
A(20) => \data_pipeline_tmp_reg[12]\(15),
A(19) => \data_pipeline_tmp_reg[12]\(15),
A(18) => \data_pipeline_tmp_reg[12]\(15),
A(17) => \data_pipeline_tmp_reg[12]\(15),
A(16) => \data_pipeline_tmp_reg[12]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[12]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__21_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__21_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_29\(14),
C(12) => \ARG__21_i_1_n_0\,
C(11) => \ARG__21_i_1_n_0\,
C(10) => \ARG__21_i_1_n_0\,
C(9) => \ARG__21_i_1_n_0\,
C(8) => \ARG__21_i_1_n_0\,
C(7) => \ARG__21_i_1_n_0\,
C(6) => \ARG__21_i_1_n_0\,
C(5) => \ARG__21_i_1_n_0\,
C(4) => \ARG__21_i_1_n_0\,
C(3) => \ARG__21_i_1_n_0\,
C(2) => \ARG__21_i_1_n_0\,
C(1) => \ARG__21_i_1_n_0\,
C(0) => \ARG__21_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__21_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__21_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__21_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__21_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__21_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__21_n_76\,
P(28) => \ARG__21_n_77\,
P(27) => \ARG__21_n_78\,
P(26) => \ARG__21_n_79\,
P(25) => \ARG__21_n_80\,
P(24) => \ARG__21_n_81\,
P(23) => \ARG__21_n_82\,
P(22) => \ARG__21_n_83\,
P(21) => \ARG__21_n_84\,
P(20) => \ARG__21_n_85\,
P(19) => \ARG__21_n_86\,
P(18) => \ARG__21_n_87\,
P(17) => \ARG__21_n_88\,
P(16) => \ARG__21_n_89\,
P(15) => \ARG__21_n_90\,
P(14) => \ARG__21_n_91\,
P(13) => \ARG__21_n_92\,
P(12) => \ARG__21_n_93\,
P(11) => \ARG__21_n_94\,
P(10) => \ARG__21_n_95\,
P(9) => \ARG__21_n_96\,
P(8) => \ARG__21_n_97\,
P(7) => \ARG__21_n_98\,
P(6) => \ARG__21_n_99\,
P(5) => \ARG__21_n_100\,
P(4) => \ARG__21_n_101\,
P(3) => \ARG__21_n_102\,
P(2) => \ARG__21_n_103\,
P(1) => \ARG__21_n_104\,
P(0) => \ARG__21_n_105\,
PATTERNBDETECT => \NLW_ARG__21_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__21_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__21_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__21_UNDERFLOW_UNCONNECTED\
);
\ARG__21_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_29\(14),
O => \ARG__21_i_1_n_0\
);
\ARG__22\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[12]\(15),
A(28) => \data_pipeline_tmp_reg[12]\(15),
A(27) => \data_pipeline_tmp_reg[12]\(15),
A(26) => \data_pipeline_tmp_reg[12]\(15),
A(25) => \data_pipeline_tmp_reg[12]\(15),
A(24) => \data_pipeline_tmp_reg[12]\(15),
A(23) => \data_pipeline_tmp_reg[12]\(15),
A(22) => \data_pipeline_tmp_reg[12]\(15),
A(21) => \data_pipeline_tmp_reg[12]\(15),
A(20) => \data_pipeline_tmp_reg[12]\(15),
A(19) => \data_pipeline_tmp_reg[12]\(15),
A(18) => \data_pipeline_tmp_reg[12]\(15),
A(17) => \data_pipeline_tmp_reg[12]\(15),
A(16) => \data_pipeline_tmp_reg[12]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[12]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__22_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[12]_11\(15),
B(16) => \weight_reg[12]_11\(15),
B(15 downto 0) => \weight_reg[12]_11\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__22_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_12\(14),
C(12) => \ARG__22_i_1_n_0\,
C(11) => \ARG__22_i_1_n_0\,
C(10) => \ARG__22_i_1_n_0\,
C(9) => \ARG__22_i_1_n_0\,
C(8) => \ARG__22_i_1_n_0\,
C(7) => \ARG__22_i_1_n_0\,
C(6) => \ARG__22_i_1_n_0\,
C(5) => \ARG__22_i_1_n_0\,
C(4) => \ARG__22_i_1_n_0\,
C(3) => \ARG__22_i_1_n_0\,
C(2) => \ARG__22_i_1_n_0\,
C(1) => \ARG__22_i_1_n_0\,
C(0) => \ARG__22_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__22_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__22_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__22_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__22_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__22_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE38(15 downto 0),
P(13) => \ARG__22_n_92\,
P(12) => \ARG__22_n_93\,
P(11) => \ARG__22_n_94\,
P(10) => \ARG__22_n_95\,
P(9) => \ARG__22_n_96\,
P(8) => \ARG__22_n_97\,
P(7) => \ARG__22_n_98\,
P(6) => \ARG__22_n_99\,
P(5) => \ARG__22_n_100\,
P(4) => \ARG__22_n_101\,
P(3) => \ARG__22_n_102\,
P(2) => \ARG__22_n_103\,
P(1) => \ARG__22_n_104\,
P(0) => \ARG__22_n_105\,
PATTERNBDETECT => \NLW_ARG__22_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__22_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__22_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__22_UNDERFLOW_UNCONNECTED\
);
\ARG__22_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_12\(14),
O => \ARG__22_i_1_n_0\
);
\ARG__23\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[13]\(15),
A(28) => \data_pipeline_tmp_reg[13]\(15),
A(27) => \data_pipeline_tmp_reg[13]\(15),
A(26) => \data_pipeline_tmp_reg[13]\(15),
A(25) => \data_pipeline_tmp_reg[13]\(15),
A(24) => \data_pipeline_tmp_reg[13]\(15),
A(23) => \data_pipeline_tmp_reg[13]\(15),
A(22) => \data_pipeline_tmp_reg[13]\(15),
A(21) => \data_pipeline_tmp_reg[13]\(15),
A(20) => \data_pipeline_tmp_reg[13]\(15),
A(19) => \data_pipeline_tmp_reg[13]\(15),
A(18) => \data_pipeline_tmp_reg[13]\(15),
A(17) => \data_pipeline_tmp_reg[13]\(15),
A(16) => \data_pipeline_tmp_reg[13]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[13]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__23_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__23_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_30\(14),
C(12) => \ARG__23_i_1_n_0\,
C(11) => \ARG__23_i_1_n_0\,
C(10) => \ARG__23_i_1_n_0\,
C(9) => \ARG__23_i_1_n_0\,
C(8) => \ARG__23_i_1_n_0\,
C(7) => \ARG__23_i_1_n_0\,
C(6) => \ARG__23_i_1_n_0\,
C(5) => \ARG__23_i_1_n_0\,
C(4) => \ARG__23_i_1_n_0\,
C(3) => \ARG__23_i_1_n_0\,
C(2) => \ARG__23_i_1_n_0\,
C(1) => \ARG__23_i_1_n_0\,
C(0) => \ARG__23_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__23_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__23_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__23_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__23_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__23_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__23_n_76\,
P(28) => \ARG__23_n_77\,
P(27) => \ARG__23_n_78\,
P(26) => \ARG__23_n_79\,
P(25) => \ARG__23_n_80\,
P(24) => \ARG__23_n_81\,
P(23) => \ARG__23_n_82\,
P(22) => \ARG__23_n_83\,
P(21) => \ARG__23_n_84\,
P(20) => \ARG__23_n_85\,
P(19) => \ARG__23_n_86\,
P(18) => \ARG__23_n_87\,
P(17) => \ARG__23_n_88\,
P(16) => \ARG__23_n_89\,
P(15) => \ARG__23_n_90\,
P(14) => \ARG__23_n_91\,
P(13) => \ARG__23_n_92\,
P(12) => \ARG__23_n_93\,
P(11) => \ARG__23_n_94\,
P(10) => \ARG__23_n_95\,
P(9) => \ARG__23_n_96\,
P(8) => \ARG__23_n_97\,
P(7) => \ARG__23_n_98\,
P(6) => \ARG__23_n_99\,
P(5) => \ARG__23_n_100\,
P(4) => \ARG__23_n_101\,
P(3) => \ARG__23_n_102\,
P(2) => \ARG__23_n_103\,
P(1) => \ARG__23_n_104\,
P(0) => \ARG__23_n_105\,
PATTERNBDETECT => \NLW_ARG__23_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__23_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__23_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__23_UNDERFLOW_UNCONNECTED\
);
\ARG__23_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_30\(14),
O => \ARG__23_i_1_n_0\
);
\ARG__24\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[13]\(15),
A(28) => \data_pipeline_tmp_reg[13]\(15),
A(27) => \data_pipeline_tmp_reg[13]\(15),
A(26) => \data_pipeline_tmp_reg[13]\(15),
A(25) => \data_pipeline_tmp_reg[13]\(15),
A(24) => \data_pipeline_tmp_reg[13]\(15),
A(23) => \data_pipeline_tmp_reg[13]\(15),
A(22) => \data_pipeline_tmp_reg[13]\(15),
A(21) => \data_pipeline_tmp_reg[13]\(15),
A(20) => \data_pipeline_tmp_reg[13]\(15),
A(19) => \data_pipeline_tmp_reg[13]\(15),
A(18) => \data_pipeline_tmp_reg[13]\(15),
A(17) => \data_pipeline_tmp_reg[13]\(15),
A(16) => \data_pipeline_tmp_reg[13]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[13]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__24_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[13]_12\(15),
B(16) => \weight_reg[13]_12\(15),
B(15 downto 0) => \weight_reg[13]_12\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__24_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_13\(14),
C(12) => \ARG__24_i_1_n_0\,
C(11) => \ARG__24_i_1_n_0\,
C(10) => \ARG__24_i_1_n_0\,
C(9) => \ARG__24_i_1_n_0\,
C(8) => \ARG__24_i_1_n_0\,
C(7) => \ARG__24_i_1_n_0\,
C(6) => \ARG__24_i_1_n_0\,
C(5) => \ARG__24_i_1_n_0\,
C(4) => \ARG__24_i_1_n_0\,
C(3) => \ARG__24_i_1_n_0\,
C(2) => \ARG__24_i_1_n_0\,
C(1) => \ARG__24_i_1_n_0\,
C(0) => \ARG__24_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__24_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__24_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__24_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__24_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__24_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE40(15 downto 0),
P(13) => \ARG__24_n_92\,
P(12) => \ARG__24_n_93\,
P(11) => \ARG__24_n_94\,
P(10) => \ARG__24_n_95\,
P(9) => \ARG__24_n_96\,
P(8) => \ARG__24_n_97\,
P(7) => \ARG__24_n_98\,
P(6) => \ARG__24_n_99\,
P(5) => \ARG__24_n_100\,
P(4) => \ARG__24_n_101\,
P(3) => \ARG__24_n_102\,
P(2) => \ARG__24_n_103\,
P(1) => \ARG__24_n_104\,
P(0) => \ARG__24_n_105\,
PATTERNBDETECT => \NLW_ARG__24_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__24_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__24_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__24_UNDERFLOW_UNCONNECTED\
);
\ARG__24_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_13\(14),
O => \ARG__24_i_1_n_0\
);
\ARG__25\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[14]\(15),
A(28) => \data_pipeline_tmp_reg[14]\(15),
A(27) => \data_pipeline_tmp_reg[14]\(15),
A(26) => \data_pipeline_tmp_reg[14]\(15),
A(25) => \data_pipeline_tmp_reg[14]\(15),
A(24) => \data_pipeline_tmp_reg[14]\(15),
A(23) => \data_pipeline_tmp_reg[14]\(15),
A(22) => \data_pipeline_tmp_reg[14]\(15),
A(21) => \data_pipeline_tmp_reg[14]\(15),
A(20) => \data_pipeline_tmp_reg[14]\(15),
A(19) => \data_pipeline_tmp_reg[14]\(15),
A(18) => \data_pipeline_tmp_reg[14]\(15),
A(17) => \data_pipeline_tmp_reg[14]\(15),
A(16) => \data_pipeline_tmp_reg[14]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[14]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__25_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__25_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_31\(14),
C(12) => \ARG__25_i_1_n_0\,
C(11) => \ARG__25_i_1_n_0\,
C(10) => \ARG__25_i_1_n_0\,
C(9) => \ARG__25_i_1_n_0\,
C(8) => \ARG__25_i_1_n_0\,
C(7) => \ARG__25_i_1_n_0\,
C(6) => \ARG__25_i_1_n_0\,
C(5) => \ARG__25_i_1_n_0\,
C(4) => \ARG__25_i_1_n_0\,
C(3) => \ARG__25_i_1_n_0\,
C(2) => \ARG__25_i_1_n_0\,
C(1) => \ARG__25_i_1_n_0\,
C(0) => \ARG__25_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__25_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__25_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__25_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__25_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__25_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__25_n_76\,
P(28) => \ARG__25_n_77\,
P(27) => \ARG__25_n_78\,
P(26) => \ARG__25_n_79\,
P(25) => \ARG__25_n_80\,
P(24) => \ARG__25_n_81\,
P(23) => \ARG__25_n_82\,
P(22) => \ARG__25_n_83\,
P(21) => \ARG__25_n_84\,
P(20) => \ARG__25_n_85\,
P(19) => \ARG__25_n_86\,
P(18) => \ARG__25_n_87\,
P(17) => \ARG__25_n_88\,
P(16) => \ARG__25_n_89\,
P(15) => \ARG__25_n_90\,
P(14) => \ARG__25_n_91\,
P(13) => \ARG__25_n_92\,
P(12) => \ARG__25_n_93\,
P(11) => \ARG__25_n_94\,
P(10) => \ARG__25_n_95\,
P(9) => \ARG__25_n_96\,
P(8) => \ARG__25_n_97\,
P(7) => \ARG__25_n_98\,
P(6) => \ARG__25_n_99\,
P(5) => \ARG__25_n_100\,
P(4) => \ARG__25_n_101\,
P(3) => \ARG__25_n_102\,
P(2) => \ARG__25_n_103\,
P(1) => \ARG__25_n_104\,
P(0) => \ARG__25_n_105\,
PATTERNBDETECT => \NLW_ARG__25_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__25_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__25_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__25_UNDERFLOW_UNCONNECTED\
);
\ARG__25_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_31\(14),
O => \ARG__25_i_1_n_0\
);
\ARG__26\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[14]\(15),
A(28) => \data_pipeline_tmp_reg[14]\(15),
A(27) => \data_pipeline_tmp_reg[14]\(15),
A(26) => \data_pipeline_tmp_reg[14]\(15),
A(25) => \data_pipeline_tmp_reg[14]\(15),
A(24) => \data_pipeline_tmp_reg[14]\(15),
A(23) => \data_pipeline_tmp_reg[14]\(15),
A(22) => \data_pipeline_tmp_reg[14]\(15),
A(21) => \data_pipeline_tmp_reg[14]\(15),
A(20) => \data_pipeline_tmp_reg[14]\(15),
A(19) => \data_pipeline_tmp_reg[14]\(15),
A(18) => \data_pipeline_tmp_reg[14]\(15),
A(17) => \data_pipeline_tmp_reg[14]\(15),
A(16) => \data_pipeline_tmp_reg[14]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[14]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__26_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[14]_13\(15),
B(16) => \weight_reg[14]_13\(15),
B(15 downto 0) => \weight_reg[14]_13\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__26_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_14\(14),
C(12) => \ARG__26_i_1_n_0\,
C(11) => \ARG__26_i_1_n_0\,
C(10) => \ARG__26_i_1_n_0\,
C(9) => \ARG__26_i_1_n_0\,
C(8) => \ARG__26_i_1_n_0\,
C(7) => \ARG__26_i_1_n_0\,
C(6) => \ARG__26_i_1_n_0\,
C(5) => \ARG__26_i_1_n_0\,
C(4) => \ARG__26_i_1_n_0\,
C(3) => \ARG__26_i_1_n_0\,
C(2) => \ARG__26_i_1_n_0\,
C(1) => \ARG__26_i_1_n_0\,
C(0) => \ARG__26_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__26_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__26_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__26_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__26_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__26_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE42(15 downto 0),
P(13) => \ARG__26_n_92\,
P(12) => \ARG__26_n_93\,
P(11) => \ARG__26_n_94\,
P(10) => \ARG__26_n_95\,
P(9) => \ARG__26_n_96\,
P(8) => \ARG__26_n_97\,
P(7) => \ARG__26_n_98\,
P(6) => \ARG__26_n_99\,
P(5) => \ARG__26_n_100\,
P(4) => \ARG__26_n_101\,
P(3) => \ARG__26_n_102\,
P(2) => \ARG__26_n_103\,
P(1) => \ARG__26_n_104\,
P(0) => \ARG__26_n_105\,
PATTERNBDETECT => \NLW_ARG__26_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__26_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__26_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__26_UNDERFLOW_UNCONNECTED\
);
\ARG__26_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_14\(14),
O => \ARG__26_i_1_n_0\
);
\ARG__27\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \write_reg_x_k_reg[15]\(15),
A(28) => \write_reg_x_k_reg[15]\(15),
A(27) => \write_reg_x_k_reg[15]\(15),
A(26) => \write_reg_x_k_reg[15]\(15),
A(25) => \write_reg_x_k_reg[15]\(15),
A(24) => \write_reg_x_k_reg[15]\(15),
A(23) => \write_reg_x_k_reg[15]\(15),
A(22) => \write_reg_x_k_reg[15]\(15),
A(21) => \write_reg_x_k_reg[15]\(15),
A(20) => \write_reg_x_k_reg[15]\(15),
A(19) => \write_reg_x_k_reg[15]\(15),
A(18) => \write_reg_x_k_reg[15]\(15),
A(17) => \write_reg_x_k_reg[15]\(15),
A(16) => \write_reg_x_k_reg[15]\(15),
A(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__27_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__27_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_32\(14),
C(12) => \ARG__27_i_1_n_0\,
C(11) => \ARG__27_i_1_n_0\,
C(10) => \ARG__27_i_1_n_0\,
C(9) => \ARG__27_i_1_n_0\,
C(8) => \ARG__27_i_1_n_0\,
C(7) => \ARG__27_i_1_n_0\,
C(6) => \ARG__27_i_1_n_0\,
C(5) => \ARG__27_i_1_n_0\,
C(4) => \ARG__27_i_1_n_0\,
C(3) => \ARG__27_i_1_n_0\,
C(2) => \ARG__27_i_1_n_0\,
C(1) => \ARG__27_i_1_n_0\,
C(0) => \ARG__27_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__27_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__27_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__27_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__27_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__27_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__27_n_76\,
P(28) => \ARG__27_n_77\,
P(27) => \ARG__27_n_78\,
P(26) => \ARG__27_n_79\,
P(25) => \ARG__27_n_80\,
P(24) => \ARG__27_n_81\,
P(23) => \ARG__27_n_82\,
P(22) => \ARG__27_n_83\,
P(21) => \ARG__27_n_84\,
P(20) => \ARG__27_n_85\,
P(19) => \ARG__27_n_86\,
P(18) => \ARG__27_n_87\,
P(17) => \ARG__27_n_88\,
P(16) => \ARG__27_n_89\,
P(15) => \ARG__27_n_90\,
P(14) => \ARG__27_n_91\,
P(13) => \ARG__27_n_92\,
P(12) => \ARG__27_n_93\,
P(11) => \ARG__27_n_94\,
P(10) => \ARG__27_n_95\,
P(9) => \ARG__27_n_96\,
P(8) => \ARG__27_n_97\,
P(7) => \ARG__27_n_98\,
P(6) => \ARG__27_n_99\,
P(5) => \ARG__27_n_100\,
P(4) => \ARG__27_n_101\,
P(3) => \ARG__27_n_102\,
P(2) => \ARG__27_n_103\,
P(1) => \ARG__27_n_104\,
P(0) => \ARG__27_n_105\,
PATTERNBDETECT => \NLW_ARG__27_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__27_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__27_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__27_UNDERFLOW_UNCONNECTED\
);
\ARG__27_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_32\(14),
O => \ARG__27_i_1_n_0\
);
\ARG__28\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \write_reg_x_k_reg[15]\(15),
A(28) => \write_reg_x_k_reg[15]\(15),
A(27) => \write_reg_x_k_reg[15]\(15),
A(26) => \write_reg_x_k_reg[15]\(15),
A(25) => \write_reg_x_k_reg[15]\(15),
A(24) => \write_reg_x_k_reg[15]\(15),
A(23) => \write_reg_x_k_reg[15]\(15),
A(22) => \write_reg_x_k_reg[15]\(15),
A(21) => \write_reg_x_k_reg[15]\(15),
A(20) => \write_reg_x_k_reg[15]\(15),
A(19) => \write_reg_x_k_reg[15]\(15),
A(18) => \write_reg_x_k_reg[15]\(15),
A(17) => \write_reg_x_k_reg[15]\(15),
A(16) => \write_reg_x_k_reg[15]\(15),
A(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__28_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[15]_14\(15),
B(16) => \weight_reg[15]_14\(15),
B(15 downto 0) => \weight_reg[15]_14\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__28_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_15\(14),
C(12) => \ARG__28_i_1_n_0\,
C(11) => \ARG__28_i_1_n_0\,
C(10) => \ARG__28_i_1_n_0\,
C(9) => \ARG__28_i_1_n_0\,
C(8) => \ARG__28_i_1_n_0\,
C(7) => \ARG__28_i_1_n_0\,
C(6) => \ARG__28_i_1_n_0\,
C(5) => \ARG__28_i_1_n_0\,
C(4) => \ARG__28_i_1_n_0\,
C(3) => \ARG__28_i_1_n_0\,
C(2) => \ARG__28_i_1_n_0\,
C(1) => \ARG__28_i_1_n_0\,
C(0) => \ARG__28_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__28_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__28_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__28_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__28_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__28_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE44(15 downto 0),
P(13) => \ARG__28_n_92\,
P(12) => \ARG__28_n_93\,
P(11) => \ARG__28_n_94\,
P(10) => \ARG__28_n_95\,
P(9) => \ARG__28_n_96\,
P(8) => \ARG__28_n_97\,
P(7) => \ARG__28_n_98\,
P(6) => \ARG__28_n_99\,
P(5) => \ARG__28_n_100\,
P(4) => \ARG__28_n_101\,
P(3) => \ARG__28_n_102\,
P(2) => \ARG__28_n_103\,
P(1) => \ARG__28_n_104\,
P(0) => \ARG__28_n_105\,
PATTERNBDETECT => \NLW_ARG__28_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__28_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__28_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__28_UNDERFLOW_UNCONNECTED\
);
\ARG__28_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_15\(14),
O => \ARG__28_i_1_n_0\
);
\ARG__29\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[0]\(15),
A(28) => \data_pipeline_tmp_reg[0]\(15),
A(27) => \data_pipeline_tmp_reg[0]\(15),
A(26) => \data_pipeline_tmp_reg[0]\(15),
A(25) => \data_pipeline_tmp_reg[0]\(15),
A(24) => \data_pipeline_tmp_reg[0]\(15),
A(23) => \data_pipeline_tmp_reg[0]\(15),
A(22) => \data_pipeline_tmp_reg[0]\(15),
A(21) => \data_pipeline_tmp_reg[0]\(15),
A(20) => \data_pipeline_tmp_reg[0]\(15),
A(19) => \data_pipeline_tmp_reg[0]\(15),
A(18) => \data_pipeline_tmp_reg[0]\(15),
A(17) => \data_pipeline_tmp_reg[0]\(15),
A(16) => \data_pipeline_tmp_reg[0]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[0]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__29_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__29_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_17\(14),
C(12) => \ARG__29_i_1_n_0\,
C(11) => \ARG__29_i_1_n_0\,
C(10) => \ARG__29_i_1_n_0\,
C(9) => \ARG__29_i_1_n_0\,
C(8) => \ARG__29_i_1_n_0\,
C(7) => \ARG__29_i_1_n_0\,
C(6) => \ARG__29_i_1_n_0\,
C(5) => \ARG__29_i_1_n_0\,
C(4) => \ARG__29_i_1_n_0\,
C(3) => \ARG__29_i_1_n_0\,
C(2) => \ARG__29_i_1_n_0\,
C(1) => \ARG__29_i_1_n_0\,
C(0) => \ARG__29_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__29_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__29_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__29_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__29_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__29_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__29_n_76\,
P(28) => \ARG__29_n_77\,
P(27) => \ARG__29_n_78\,
P(26) => \ARG__29_n_79\,
P(25) => \ARG__29_n_80\,
P(24) => \ARG__29_n_81\,
P(23) => \ARG__29_n_82\,
P(22) => \ARG__29_n_83\,
P(21) => \ARG__29_n_84\,
P(20) => \ARG__29_n_85\,
P(19) => \ARG__29_n_86\,
P(18) => \ARG__29_n_87\,
P(17) => \ARG__29_n_88\,
P(16) => \ARG__29_n_89\,
P(15) => \ARG__29_n_90\,
P(14) => \ARG__29_n_91\,
P(13) => \ARG__29_n_92\,
P(12) => \ARG__29_n_93\,
P(11) => \ARG__29_n_94\,
P(10) => \ARG__29_n_95\,
P(9) => \ARG__29_n_96\,
P(8) => \ARG__29_n_97\,
P(7) => \ARG__29_n_98\,
P(6) => \ARG__29_n_99\,
P(5) => \ARG__29_n_100\,
P(4) => \ARG__29_n_101\,
P(3) => \ARG__29_n_102\,
P(2) => \ARG__29_n_103\,
P(1) => \ARG__29_n_104\,
P(0) => \ARG__29_n_105\,
PATTERNBDETECT => \NLW_ARG__29_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__29_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__29_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__29_UNDERFLOW_UNCONNECTED\
);
\ARG__29_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_17\(14),
O => \ARG__29_i_1_n_0\
);
\ARG__2_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_2\(14),
O => \ARG__2_i_1_n_0\
);
\ARG__3\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[3]\(15),
A(28) => \data_pipeline_tmp_reg[3]\(15),
A(27) => \data_pipeline_tmp_reg[3]\(15),
A(26) => \data_pipeline_tmp_reg[3]\(15),
A(25) => \data_pipeline_tmp_reg[3]\(15),
A(24) => \data_pipeline_tmp_reg[3]\(15),
A(23) => \data_pipeline_tmp_reg[3]\(15),
A(22) => \data_pipeline_tmp_reg[3]\(15),
A(21) => \data_pipeline_tmp_reg[3]\(15),
A(20) => \data_pipeline_tmp_reg[3]\(15),
A(19) => \data_pipeline_tmp_reg[3]\(15),
A(18) => \data_pipeline_tmp_reg[3]\(15),
A(17) => \data_pipeline_tmp_reg[3]\(15),
A(16) => \data_pipeline_tmp_reg[3]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[3]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__3_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__3_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_20\(14),
C(12) => \ARG__3_i_1_n_0\,
C(11) => \ARG__3_i_1_n_0\,
C(10) => \ARG__3_i_1_n_0\,
C(9) => \ARG__3_i_1_n_0\,
C(8) => \ARG__3_i_1_n_0\,
C(7) => \ARG__3_i_1_n_0\,
C(6) => \ARG__3_i_1_n_0\,
C(5) => \ARG__3_i_1_n_0\,
C(4) => \ARG__3_i_1_n_0\,
C(3) => \ARG__3_i_1_n_0\,
C(2) => \ARG__3_i_1_n_0\,
C(1) => \ARG__3_i_1_n_0\,
C(0) => \ARG__3_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__3_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__3_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__3_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__3_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__3_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__3_n_76\,
P(28) => \ARG__3_n_77\,
P(27) => \ARG__3_n_78\,
P(26) => \ARG__3_n_79\,
P(25) => \ARG__3_n_80\,
P(24) => \ARG__3_n_81\,
P(23) => \ARG__3_n_82\,
P(22) => \ARG__3_n_83\,
P(21) => \ARG__3_n_84\,
P(20) => \ARG__3_n_85\,
P(19) => \ARG__3_n_86\,
P(18) => \ARG__3_n_87\,
P(17) => \ARG__3_n_88\,
P(16) => \ARG__3_n_89\,
P(15) => \ARG__3_n_90\,
P(14) => \ARG__3_n_91\,
P(13) => \ARG__3_n_92\,
P(12) => \ARG__3_n_93\,
P(11) => \ARG__3_n_94\,
P(10) => \ARG__3_n_95\,
P(9) => \ARG__3_n_96\,
P(8) => \ARG__3_n_97\,
P(7) => \ARG__3_n_98\,
P(6) => \ARG__3_n_99\,
P(5) => \ARG__3_n_100\,
P(4) => \ARG__3_n_101\,
P(3) => \ARG__3_n_102\,
P(2) => \ARG__3_n_103\,
P(1) => \ARG__3_n_104\,
P(0) => \ARG__3_n_105\,
PATTERNBDETECT => \NLW_ARG__3_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__3_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__3_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__3_UNDERFLOW_UNCONNECTED\
);
\ARG__30\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[0]\(15),
A(28) => \data_pipeline_tmp_reg[0]\(15),
A(27) => \data_pipeline_tmp_reg[0]\(15),
A(26) => \data_pipeline_tmp_reg[0]\(15),
A(25) => \data_pipeline_tmp_reg[0]\(15),
A(24) => \data_pipeline_tmp_reg[0]\(15),
A(23) => \data_pipeline_tmp_reg[0]\(15),
A(22) => \data_pipeline_tmp_reg[0]\(15),
A(21) => \data_pipeline_tmp_reg[0]\(15),
A(20) => \data_pipeline_tmp_reg[0]\(15),
A(19) => \data_pipeline_tmp_reg[0]\(15),
A(18) => \data_pipeline_tmp_reg[0]\(15),
A(17) => \data_pipeline_tmp_reg[0]\(15),
A(16) => \data_pipeline_tmp_reg[0]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[0]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__30_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[0]_15\(15),
B(16) => \weight_reg[0]_15\(15),
B(15 downto 0) => \weight_reg[0]_15\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__30_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp\(14),
C(12) => \ARG__30_i_1_n_0\,
C(11) => \ARG__30_i_1_n_0\,
C(10) => \ARG__30_i_1_n_0\,
C(9) => \ARG__30_i_1_n_0\,
C(8) => \ARG__30_i_1_n_0\,
C(7) => \ARG__30_i_1_n_0\,
C(6) => \ARG__30_i_1_n_0\,
C(5) => \ARG__30_i_1_n_0\,
C(4) => \ARG__30_i_1_n_0\,
C(3) => \ARG__30_i_1_n_0\,
C(2) => \ARG__30_i_1_n_0\,
C(1) => \ARG__30_i_1_n_0\,
C(0) => \ARG__30_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__30_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__30_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__30_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__30_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__30_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE15(15 downto 0),
P(13) => \ARG__30_n_92\,
P(12) => \ARG__30_n_93\,
P(11) => \ARG__30_n_94\,
P(10) => \ARG__30_n_95\,
P(9) => \ARG__30_n_96\,
P(8) => \ARG__30_n_97\,
P(7) => \ARG__30_n_98\,
P(6) => \ARG__30_n_99\,
P(5) => \ARG__30_n_100\,
P(4) => \ARG__30_n_101\,
P(3) => \ARG__30_n_102\,
P(2) => \ARG__30_n_103\,
P(1) => \ARG__30_n_104\,
P(0) => \ARG__30_n_105\,
PATTERNBDETECT => \NLW_ARG__30_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__30_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__30_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__30_UNDERFLOW_UNCONNECTED\
);
\ARG__30_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp\(14),
O => \ARG__30_i_1_n_0\
);
\ARG__3_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_20\(14),
O => \ARG__3_i_1_n_0\
);
\ARG__4\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[3]\(15),
A(28) => \data_pipeline_tmp_reg[3]\(15),
A(27) => \data_pipeline_tmp_reg[3]\(15),
A(26) => \data_pipeline_tmp_reg[3]\(15),
A(25) => \data_pipeline_tmp_reg[3]\(15),
A(24) => \data_pipeline_tmp_reg[3]\(15),
A(23) => \data_pipeline_tmp_reg[3]\(15),
A(22) => \data_pipeline_tmp_reg[3]\(15),
A(21) => \data_pipeline_tmp_reg[3]\(15),
A(20) => \data_pipeline_tmp_reg[3]\(15),
A(19) => \data_pipeline_tmp_reg[3]\(15),
A(18) => \data_pipeline_tmp_reg[3]\(15),
A(17) => \data_pipeline_tmp_reg[3]\(15),
A(16) => \data_pipeline_tmp_reg[3]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[3]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__4_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[3]_2\(15),
B(16) => \weight_reg[3]_2\(15),
B(15 downto 0) => \weight_reg[3]_2\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__4_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_3\(14),
C(12) => \ARG__4_i_1_n_0\,
C(11) => \ARG__4_i_1_n_0\,
C(10) => \ARG__4_i_1_n_0\,
C(9) => \ARG__4_i_1_n_0\,
C(8) => \ARG__4_i_1_n_0\,
C(7) => \ARG__4_i_1_n_0\,
C(6) => \ARG__4_i_1_n_0\,
C(5) => \ARG__4_i_1_n_0\,
C(4) => \ARG__4_i_1_n_0\,
C(3) => \ARG__4_i_1_n_0\,
C(2) => \ARG__4_i_1_n_0\,
C(1) => \ARG__4_i_1_n_0\,
C(0) => \ARG__4_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__4_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__4_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__4_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__4_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__4_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE20(15 downto 0),
P(13) => \ARG__4_n_92\,
P(12) => \ARG__4_n_93\,
P(11) => \ARG__4_n_94\,
P(10) => \ARG__4_n_95\,
P(9) => \ARG__4_n_96\,
P(8) => \ARG__4_n_97\,
P(7) => \ARG__4_n_98\,
P(6) => \ARG__4_n_99\,
P(5) => \ARG__4_n_100\,
P(4) => \ARG__4_n_101\,
P(3) => \ARG__4_n_102\,
P(2) => \ARG__4_n_103\,
P(1) => \ARG__4_n_104\,
P(0) => \ARG__4_n_105\,
PATTERNBDETECT => \NLW_ARG__4_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__4_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__4_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__4_UNDERFLOW_UNCONNECTED\
);
\ARG__4_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_3\(14),
O => \ARG__4_i_1_n_0\
);
\ARG__5\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[4]\(15),
A(28) => \data_pipeline_tmp_reg[4]\(15),
A(27) => \data_pipeline_tmp_reg[4]\(15),
A(26) => \data_pipeline_tmp_reg[4]\(15),
A(25) => \data_pipeline_tmp_reg[4]\(15),
A(24) => \data_pipeline_tmp_reg[4]\(15),
A(23) => \data_pipeline_tmp_reg[4]\(15),
A(22) => \data_pipeline_tmp_reg[4]\(15),
A(21) => \data_pipeline_tmp_reg[4]\(15),
A(20) => \data_pipeline_tmp_reg[4]\(15),
A(19) => \data_pipeline_tmp_reg[4]\(15),
A(18) => \data_pipeline_tmp_reg[4]\(15),
A(17) => \data_pipeline_tmp_reg[4]\(15),
A(16) => \data_pipeline_tmp_reg[4]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[4]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__5_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__5_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_21\(14),
C(12) => \ARG__5_i_1_n_0\,
C(11) => \ARG__5_i_1_n_0\,
C(10) => \ARG__5_i_1_n_0\,
C(9) => \ARG__5_i_1_n_0\,
C(8) => \ARG__5_i_1_n_0\,
C(7) => \ARG__5_i_1_n_0\,
C(6) => \ARG__5_i_1_n_0\,
C(5) => \ARG__5_i_1_n_0\,
C(4) => \ARG__5_i_1_n_0\,
C(3) => \ARG__5_i_1_n_0\,
C(2) => \ARG__5_i_1_n_0\,
C(1) => \ARG__5_i_1_n_0\,
C(0) => \ARG__5_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__5_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__5_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__5_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__5_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__5_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__5_n_76\,
P(28) => \ARG__5_n_77\,
P(27) => \ARG__5_n_78\,
P(26) => \ARG__5_n_79\,
P(25) => \ARG__5_n_80\,
P(24) => \ARG__5_n_81\,
P(23) => \ARG__5_n_82\,
P(22) => \ARG__5_n_83\,
P(21) => \ARG__5_n_84\,
P(20) => \ARG__5_n_85\,
P(19) => \ARG__5_n_86\,
P(18) => \ARG__5_n_87\,
P(17) => \ARG__5_n_88\,
P(16) => \ARG__5_n_89\,
P(15) => \ARG__5_n_90\,
P(14) => \ARG__5_n_91\,
P(13) => \ARG__5_n_92\,
P(12) => \ARG__5_n_93\,
P(11) => \ARG__5_n_94\,
P(10) => \ARG__5_n_95\,
P(9) => \ARG__5_n_96\,
P(8) => \ARG__5_n_97\,
P(7) => \ARG__5_n_98\,
P(6) => \ARG__5_n_99\,
P(5) => \ARG__5_n_100\,
P(4) => \ARG__5_n_101\,
P(3) => \ARG__5_n_102\,
P(2) => \ARG__5_n_103\,
P(1) => \ARG__5_n_104\,
P(0) => \ARG__5_n_105\,
PATTERNBDETECT => \NLW_ARG__5_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__5_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__5_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__5_UNDERFLOW_UNCONNECTED\
);
\ARG__5_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_21\(14),
O => \ARG__5_i_1_n_0\
);
\ARG__6\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[4]\(15),
A(28) => \data_pipeline_tmp_reg[4]\(15),
A(27) => \data_pipeline_tmp_reg[4]\(15),
A(26) => \data_pipeline_tmp_reg[4]\(15),
A(25) => \data_pipeline_tmp_reg[4]\(15),
A(24) => \data_pipeline_tmp_reg[4]\(15),
A(23) => \data_pipeline_tmp_reg[4]\(15),
A(22) => \data_pipeline_tmp_reg[4]\(15),
A(21) => \data_pipeline_tmp_reg[4]\(15),
A(20) => \data_pipeline_tmp_reg[4]\(15),
A(19) => \data_pipeline_tmp_reg[4]\(15),
A(18) => \data_pipeline_tmp_reg[4]\(15),
A(17) => \data_pipeline_tmp_reg[4]\(15),
A(16) => \data_pipeline_tmp_reg[4]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[4]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__6_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[4]_3\(15),
B(16) => \weight_reg[4]_3\(15),
B(15 downto 0) => \weight_reg[4]_3\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__6_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_4\(14),
C(12) => \ARG__6_i_1_n_0\,
C(11) => \ARG__6_i_1_n_0\,
C(10) => \ARG__6_i_1_n_0\,
C(9) => \ARG__6_i_1_n_0\,
C(8) => \ARG__6_i_1_n_0\,
C(7) => \ARG__6_i_1_n_0\,
C(6) => \ARG__6_i_1_n_0\,
C(5) => \ARG__6_i_1_n_0\,
C(4) => \ARG__6_i_1_n_0\,
C(3) => \ARG__6_i_1_n_0\,
C(2) => \ARG__6_i_1_n_0\,
C(1) => \ARG__6_i_1_n_0\,
C(0) => \ARG__6_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__6_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__6_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__6_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__6_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__6_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE22(15 downto 0),
P(13) => \ARG__6_n_92\,
P(12) => \ARG__6_n_93\,
P(11) => \ARG__6_n_94\,
P(10) => \ARG__6_n_95\,
P(9) => \ARG__6_n_96\,
P(8) => \ARG__6_n_97\,
P(7) => \ARG__6_n_98\,
P(6) => \ARG__6_n_99\,
P(5) => \ARG__6_n_100\,
P(4) => \ARG__6_n_101\,
P(3) => \ARG__6_n_102\,
P(2) => \ARG__6_n_103\,
P(1) => \ARG__6_n_104\,
P(0) => \ARG__6_n_105\,
PATTERNBDETECT => \NLW_ARG__6_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__6_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__6_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__6_UNDERFLOW_UNCONNECTED\
);
\ARG__6_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_4\(14),
O => \ARG__6_i_1_n_0\
);
\ARG__7\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[5]\(15),
A(28) => \data_pipeline_tmp_reg[5]\(15),
A(27) => \data_pipeline_tmp_reg[5]\(15),
A(26) => \data_pipeline_tmp_reg[5]\(15),
A(25) => \data_pipeline_tmp_reg[5]\(15),
A(24) => \data_pipeline_tmp_reg[5]\(15),
A(23) => \data_pipeline_tmp_reg[5]\(15),
A(22) => \data_pipeline_tmp_reg[5]\(15),
A(21) => \data_pipeline_tmp_reg[5]\(15),
A(20) => \data_pipeline_tmp_reg[5]\(15),
A(19) => \data_pipeline_tmp_reg[5]\(15),
A(18) => \data_pipeline_tmp_reg[5]\(15),
A(17) => \data_pipeline_tmp_reg[5]\(15),
A(16) => \data_pipeline_tmp_reg[5]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[5]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__7_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__7_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_22\(14),
C(12) => \ARG__7_i_1_n_0\,
C(11) => \ARG__7_i_1_n_0\,
C(10) => \ARG__7_i_1_n_0\,
C(9) => \ARG__7_i_1_n_0\,
C(8) => \ARG__7_i_1_n_0\,
C(7) => \ARG__7_i_1_n_0\,
C(6) => \ARG__7_i_1_n_0\,
C(5) => \ARG__7_i_1_n_0\,
C(4) => \ARG__7_i_1_n_0\,
C(3) => \ARG__7_i_1_n_0\,
C(2) => \ARG__7_i_1_n_0\,
C(1) => \ARG__7_i_1_n_0\,
C(0) => \ARG__7_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__7_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__7_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__7_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__7_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__7_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__7_n_76\,
P(28) => \ARG__7_n_77\,
P(27) => \ARG__7_n_78\,
P(26) => \ARG__7_n_79\,
P(25) => \ARG__7_n_80\,
P(24) => \ARG__7_n_81\,
P(23) => \ARG__7_n_82\,
P(22) => \ARG__7_n_83\,
P(21) => \ARG__7_n_84\,
P(20) => \ARG__7_n_85\,
P(19) => \ARG__7_n_86\,
P(18) => \ARG__7_n_87\,
P(17) => \ARG__7_n_88\,
P(16) => \ARG__7_n_89\,
P(15) => \ARG__7_n_90\,
P(14) => \ARG__7_n_91\,
P(13) => \ARG__7_n_92\,
P(12) => \ARG__7_n_93\,
P(11) => \ARG__7_n_94\,
P(10) => \ARG__7_n_95\,
P(9) => \ARG__7_n_96\,
P(8) => \ARG__7_n_97\,
P(7) => \ARG__7_n_98\,
P(6) => \ARG__7_n_99\,
P(5) => \ARG__7_n_100\,
P(4) => \ARG__7_n_101\,
P(3) => \ARG__7_n_102\,
P(2) => \ARG__7_n_103\,
P(1) => \ARG__7_n_104\,
P(0) => \ARG__7_n_105\,
PATTERNBDETECT => \NLW_ARG__7_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__7_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__7_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__7_UNDERFLOW_UNCONNECTED\
);
\ARG__7_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_22\(14),
O => \ARG__7_i_1_n_0\
);
\ARG__8\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[5]\(15),
A(28) => \data_pipeline_tmp_reg[5]\(15),
A(27) => \data_pipeline_tmp_reg[5]\(15),
A(26) => \data_pipeline_tmp_reg[5]\(15),
A(25) => \data_pipeline_tmp_reg[5]\(15),
A(24) => \data_pipeline_tmp_reg[5]\(15),
A(23) => \data_pipeline_tmp_reg[5]\(15),
A(22) => \data_pipeline_tmp_reg[5]\(15),
A(21) => \data_pipeline_tmp_reg[5]\(15),
A(20) => \data_pipeline_tmp_reg[5]\(15),
A(19) => \data_pipeline_tmp_reg[5]\(15),
A(18) => \data_pipeline_tmp_reg[5]\(15),
A(17) => \data_pipeline_tmp_reg[5]\(15),
A(16) => \data_pipeline_tmp_reg[5]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[5]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__8_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[5]_4\(15),
B(16) => \weight_reg[5]_4\(15),
B(15 downto 0) => \weight_reg[5]_4\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__8_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_5\(14),
C(12) => \ARG__8_i_1_n_0\,
C(11) => \ARG__8_i_1_n_0\,
C(10) => \ARG__8_i_1_n_0\,
C(9) => \ARG__8_i_1_n_0\,
C(8) => \ARG__8_i_1_n_0\,
C(7) => \ARG__8_i_1_n_0\,
C(6) => \ARG__8_i_1_n_0\,
C(5) => \ARG__8_i_1_n_0\,
C(4) => \ARG__8_i_1_n_0\,
C(3) => \ARG__8_i_1_n_0\,
C(2) => \ARG__8_i_1_n_0\,
C(1) => \ARG__8_i_1_n_0\,
C(0) => \ARG__8_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__8_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__8_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__8_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__8_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__8_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE24(15 downto 0),
P(13) => \ARG__8_n_92\,
P(12) => \ARG__8_n_93\,
P(11) => \ARG__8_n_94\,
P(10) => \ARG__8_n_95\,
P(9) => \ARG__8_n_96\,
P(8) => \ARG__8_n_97\,
P(7) => \ARG__8_n_98\,
P(6) => \ARG__8_n_99\,
P(5) => \ARG__8_n_100\,
P(4) => \ARG__8_n_101\,
P(3) => \ARG__8_n_102\,
P(2) => \ARG__8_n_103\,
P(1) => \ARG__8_n_104\,
P(0) => \ARG__8_n_105\,
PATTERNBDETECT => \NLW_ARG__8_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__8_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__8_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__8_UNDERFLOW_UNCONNECTED\
);
\ARG__8_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_5\(14),
O => \ARG__8_i_1_n_0\
);
\ARG__9\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[6]\(15),
A(28) => \data_pipeline_tmp_reg[6]\(15),
A(27) => \data_pipeline_tmp_reg[6]\(15),
A(26) => \data_pipeline_tmp_reg[6]\(15),
A(25) => \data_pipeline_tmp_reg[6]\(15),
A(24) => \data_pipeline_tmp_reg[6]\(15),
A(23) => \data_pipeline_tmp_reg[6]\(15),
A(22) => \data_pipeline_tmp_reg[6]\(15),
A(21) => \data_pipeline_tmp_reg[6]\(15),
A(20) => \data_pipeline_tmp_reg[6]\(15),
A(19) => \data_pipeline_tmp_reg[6]\(15),
A(18) => \data_pipeline_tmp_reg[6]\(15),
A(17) => \data_pipeline_tmp_reg[6]\(15),
A(16) => \data_pipeline_tmp_reg[6]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[6]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__9_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__9_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_23\(14),
C(12) => \ARG__9_i_1_n_0\,
C(11) => \ARG__9_i_1_n_0\,
C(10) => \ARG__9_i_1_n_0\,
C(9) => \ARG__9_i_1_n_0\,
C(8) => \ARG__9_i_1_n_0\,
C(7) => \ARG__9_i_1_n_0\,
C(6) => \ARG__9_i_1_n_0\,
C(5) => \ARG__9_i_1_n_0\,
C(4) => \ARG__9_i_1_n_0\,
C(3) => \ARG__9_i_1_n_0\,
C(2) => \ARG__9_i_1_n_0\,
C(1) => \ARG__9_i_1_n_0\,
C(0) => \ARG__9_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__9_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__9_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__9_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__9_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__9_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__9_n_76\,
P(28) => \ARG__9_n_77\,
P(27) => \ARG__9_n_78\,
P(26) => \ARG__9_n_79\,
P(25) => \ARG__9_n_80\,
P(24) => \ARG__9_n_81\,
P(23) => \ARG__9_n_82\,
P(22) => \ARG__9_n_83\,
P(21) => \ARG__9_n_84\,
P(20) => \ARG__9_n_85\,
P(19) => \ARG__9_n_86\,
P(18) => \ARG__9_n_87\,
P(17) => \ARG__9_n_88\,
P(16) => \ARG__9_n_89\,
P(15) => \ARG__9_n_90\,
P(14) => \ARG__9_n_91\,
P(13) => \ARG__9_n_92\,
P(12) => \ARG__9_n_93\,
P(11) => \ARG__9_n_94\,
P(10) => \ARG__9_n_95\,
P(9) => \ARG__9_n_96\,
P(8) => \ARG__9_n_97\,
P(7) => \ARG__9_n_98\,
P(6) => \ARG__9_n_99\,
P(5) => \ARG__9_n_100\,
P(4) => \ARG__9_n_101\,
P(3) => \ARG__9_n_102\,
P(2) => \ARG__9_n_103\,
P(1) => \ARG__9_n_104\,
P(0) => \ARG__9_n_105\,
PATTERNBDETECT => \NLW_ARG__9_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__9_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__9_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__9_UNDERFLOW_UNCONNECTED\
);
\ARG__9_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_23\(14),
O => \ARG__9_i_1_n_0\
);
ARG_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => ARG_carry_n_0,
CO(2) => ARG_carry_n_1,
CO(1) => ARG_carry_n_2,
CO(0) => ARG_carry_n_3,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 1) => \^mul_temp_16\(1 downto 0),
DI(0) => '1',
O(3 downto 0) => NLW_ARG_carry_O_UNCONNECTED(3 downto 0),
S(3) => \^mul_temp_16\(2),
S(2 downto 0) => \write_reg_d_k_reg[3]\(2 downto 0)
);
\ARG_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => ARG_carry_n_0,
CO(3) => \ARG_carry__0_n_0\,
CO(2) => \ARG_carry__0_n_1\,
CO(1) => \ARG_carry__0_n_2\,
CO(0) => \ARG_carry__0_n_3\,
CYINIT => '0',
DI(3) => \^mul_temp_16\(5),
DI(2) => \^mul_temp_16\(3),
DI(1) => \^mul_temp_16\(4),
DI(0) => DI(0),
O(3 downto 0) => \ARG__31\(20 downto 17),
S(3) => \ARG_carry__0_i_2_n_0\,
S(2) => \ARG_carry__0_i_3_n_0\,
S(1) => \ARG_carry__0_i_4_n_0\,
S(0) => \^mul_temp_16\(3)
);
\ARG_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(5),
I1 => \^mul_temp_16\(6),
O => \ARG_carry__0_i_2_n_0\
);
\ARG_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(3),
I1 => \^mul_temp_16\(5),
O => \ARG_carry__0_i_3_n_0\
);
\ARG_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(3),
I1 => \^mul_temp_16\(4),
O => \ARG_carry__0_i_4_n_0\
);
\ARG_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \ARG_carry__0_n_0\,
CO(3) => \ARG_carry__1_n_0\,
CO(2) => \ARG_carry__1_n_1\,
CO(1) => \ARG_carry__1_n_2\,
CO(0) => \ARG_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^mul_temp_16\(9 downto 6),
O(3 downto 0) => \ARG__31\(24 downto 21),
S(3) => \ARG_carry__1_i_1_n_0\,
S(2) => \ARG_carry__1_i_2_n_0\,
S(1) => \ARG_carry__1_i_3_n_0\,
S(0) => \ARG_carry__1_i_4_n_0\
);
\ARG_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(9),
I1 => \^mul_temp_16\(10),
O => \ARG_carry__1_i_1_n_0\
);
\ARG_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(8),
I1 => \^mul_temp_16\(9),
O => \ARG_carry__1_i_2_n_0\
);
\ARG_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(7),
I1 => \^mul_temp_16\(8),
O => \ARG_carry__1_i_3_n_0\
);
\ARG_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(6),
I1 => \^mul_temp_16\(7),
O => \ARG_carry__1_i_4_n_0\
);
\ARG_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \ARG_carry__1_n_0\,
CO(3) => \ARG_carry__2_n_0\,
CO(2) => \ARG_carry__2_n_1\,
CO(1) => \ARG_carry__2_n_2\,
CO(0) => \ARG_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^mul_temp_16\(13 downto 10),
O(3 downto 0) => \ARG__31\(28 downto 25),
S(3) => \ARG_carry__2_i_1_n_0\,
S(2) => \ARG_carry__2_i_2_n_0\,
S(1) => \ARG_carry__2_i_3_n_0\,
S(0) => \ARG_carry__2_i_4_n_0\
);
\ARG_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(13),
I1 => \^mul_temp_16\(14),
O => \ARG_carry__2_i_1_n_0\
);
\ARG_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(12),
I1 => \^mul_temp_16\(13),
O => \ARG_carry__2_i_2_n_0\
);
\ARG_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(11),
I1 => \^mul_temp_16\(12),
O => \ARG_carry__2_i_3_n_0\
);
\ARG_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(10),
I1 => \^mul_temp_16\(11),
O => \ARG_carry__2_i_4_n_0\
);
\ARG_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \ARG_carry__2_n_0\,
CO(3 downto 1) => \NLW_ARG_carry__3_CO_UNCONNECTED\(3 downto 1),
CO(0) => \ARG_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \^mul_temp_16\(14),
O(3 downto 2) => \NLW_ARG_carry__3_O_UNCONNECTED\(3 downto 2),
O(1) => \ARG__31\(32),
O(0) => \ARG__31\(29),
S(3 downto 1) => B"001",
S(0) => \ARG_carry__3_i_1_n_0\
);
\ARG_carry__3_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(14),
I1 => \^mul_temp_16\(15),
O => \ARG_carry__3_i_1_n_0\
);
ARG_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_18\(14),
O => ARG_i_1_n_0
);
\add_temp_14__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__0_carry_n_0\,
CO(2) => \add_temp_14__0_carry_n_1\,
CO(1) => \add_temp_14__0_carry_n_2\,
CO(0) => \add_temp_14__0_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__0_carry_i_1_n_0\,
DI(2) => \add_temp_14__0_carry_i_2_n_0\,
DI(1) => \add_temp_14__0_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__0_carry_n_4\,
O(2) => \add_temp_14__0_carry_n_5\,
O(1) => \add_temp_14__0_carry_n_6\,
O(0) => \add_temp_14__0_carry_n_7\,
S(3) => \add_temp_14__0_carry_i_4_n_0\,
S(2) => \add_temp_14__0_carry_i_5_n_0\,
S(1) => \add_temp_14__0_carry_i_6_n_0\,
S(0) => \add_temp_14__0_carry_i_7_n_0\
);
\add_temp_14__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__0_carry_n_0\,
CO(3) => \add_temp_14__0_carry__0_n_0\,
CO(2) => \add_temp_14__0_carry__0_n_1\,
CO(1) => \add_temp_14__0_carry__0_n_2\,
CO(0) => \add_temp_14__0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__0_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__0_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__0_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__0_carry__0_i_4_n_0\,
O(3) => \add_temp_14__0_carry__0_n_4\,
O(2) => \add_temp_14__0_carry__0_n_5\,
O(1) => \add_temp_14__0_carry__0_n_6\,
O(0) => \add_temp_14__0_carry__0_n_7\,
S(3) => \add_temp_14__0_carry__0_i_5_n_0\,
S(2) => \add_temp_14__0_carry__0_i_6_n_0\,
S(1) => \add_temp_14__0_carry__0_i_7_n_0\,
S(0) => \add_temp_14__0_carry__0_i_8_n_0\
);
\add_temp_14__0_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(6),
I1 => RESIZE15(6),
I2 => RESIZE42(6),
O => \add_temp_14__0_carry__0_i_1_n_0\
);
\add_temp_14__0_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(5),
I1 => RESIZE15(5),
I2 => RESIZE42(5),
O => \add_temp_14__0_carry__0_i_2_n_0\
);
\add_temp_14__0_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(4),
I1 => RESIZE15(4),
I2 => RESIZE42(4),
O => \add_temp_14__0_carry__0_i_3_n_0\
);
\add_temp_14__0_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(3),
I1 => RESIZE15(3),
I2 => RESIZE42(3),
O => \add_temp_14__0_carry__0_i_4_n_0\
);
\add_temp_14__0_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(7),
I1 => RESIZE15(7),
I2 => RESIZE42(7),
I3 => \add_temp_14__0_carry__0_i_1_n_0\,
O => \add_temp_14__0_carry__0_i_5_n_0\
);
\add_temp_14__0_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(6),
I1 => RESIZE15(6),
I2 => RESIZE42(6),
I3 => \add_temp_14__0_carry__0_i_2_n_0\,
O => \add_temp_14__0_carry__0_i_6_n_0\
);
\add_temp_14__0_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(5),
I1 => RESIZE15(5),
I2 => RESIZE42(5),
I3 => \add_temp_14__0_carry__0_i_3_n_0\,
O => \add_temp_14__0_carry__0_i_7_n_0\
);
\add_temp_14__0_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(4),
I1 => RESIZE15(4),
I2 => RESIZE42(4),
I3 => \add_temp_14__0_carry__0_i_4_n_0\,
O => \add_temp_14__0_carry__0_i_8_n_0\
);
\add_temp_14__0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__0_carry__0_n_0\,
CO(3) => \add_temp_14__0_carry__1_n_0\,
CO(2) => \add_temp_14__0_carry__1_n_1\,
CO(1) => \add_temp_14__0_carry__1_n_2\,
CO(0) => \add_temp_14__0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__0_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__0_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__0_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__0_carry__1_i_4_n_0\,
O(3) => \add_temp_14__0_carry__1_n_4\,
O(2) => \add_temp_14__0_carry__1_n_5\,
O(1) => \add_temp_14__0_carry__1_n_6\,
O(0) => \add_temp_14__0_carry__1_n_7\,
S(3) => \add_temp_14__0_carry__1_i_5_n_0\,
S(2) => \add_temp_14__0_carry__1_i_6_n_0\,
S(1) => \add_temp_14__0_carry__1_i_7_n_0\,
S(0) => \add_temp_14__0_carry__1_i_8_n_0\
);
\add_temp_14__0_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(10),
I1 => RESIZE42(10),
I2 => RESIZE15(10),
O => \add_temp_14__0_carry__1_i_1_n_0\
);
\add_temp_14__0_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(9),
I1 => RESIZE42(9),
I2 => RESIZE15(9),
O => \add_temp_14__0_carry__1_i_2_n_0\
);
\add_temp_14__0_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(8),
I1 => RESIZE15(8),
I2 => RESIZE42(8),
O => \add_temp_14__0_carry__1_i_3_n_0\
);
\add_temp_14__0_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(7),
I1 => RESIZE15(7),
I2 => RESIZE42(7),
O => \add_temp_14__0_carry__1_i_4_n_0\
);
\add_temp_14__0_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(11),
I1 => RESIZE15(11),
I2 => RESIZE42(11),
I3 => \add_temp_14__0_carry__1_i_1_n_0\,
O => \add_temp_14__0_carry__1_i_5_n_0\
);
\add_temp_14__0_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(10),
I1 => RESIZE42(10),
I2 => RESIZE15(10),
I3 => \add_temp_14__0_carry__1_i_2_n_0\,
O => \add_temp_14__0_carry__1_i_6_n_0\
);
\add_temp_14__0_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(9),
I1 => RESIZE42(9),
I2 => RESIZE15(9),
I3 => \add_temp_14__0_carry__1_i_3_n_0\,
O => \add_temp_14__0_carry__1_i_7_n_0\
);
\add_temp_14__0_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(8),
I1 => RESIZE15(8),
I2 => RESIZE42(8),
I3 => \add_temp_14__0_carry__1_i_4_n_0\,
O => \add_temp_14__0_carry__1_i_8_n_0\
);
\add_temp_14__0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__0_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__0_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__0_carry__2_n_1\,
CO(1) => \add_temp_14__0_carry__2_n_2\,
CO(0) => \add_temp_14__0_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__0_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__0_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__0_carry__2_i_3_n_0\,
O(3) => \add_temp_14__0_carry__2_n_4\,
O(2) => \add_temp_14__0_carry__2_n_5\,
O(1) => \add_temp_14__0_carry__2_n_6\,
O(0) => \add_temp_14__0_carry__2_n_7\,
S(3) => \add_temp_14__0_carry__2_i_4_n_0\,
S(2) => \add_temp_14__0_carry__2_i_5_n_0\,
S(1) => \add_temp_14__0_carry__2_i_6_n_0\,
S(0) => \add_temp_14__0_carry__2_i_7_n_0\
);
\add_temp_14__0_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE15(13),
I1 => RESIZE42(13),
I2 => RESIZE44(13),
O => \add_temp_14__0_carry__2_i_1_n_0\
);
\add_temp_14__0_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(12),
I1 => RESIZE15(12),
I2 => RESIZE42(12),
O => \add_temp_14__0_carry__2_i_2_n_0\
);
\add_temp_14__0_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(11),
I1 => RESIZE15(11),
I2 => RESIZE42(11),
O => \add_temp_14__0_carry__2_i_3_n_0\
);
\add_temp_14__0_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE15(14),
I1 => RESIZE44(14),
I2 => RESIZE42(14),
I3 => RESIZE44(15),
I4 => RESIZE42(15),
I5 => RESIZE15(15),
O => \add_temp_14__0_carry__2_i_4_n_0\
);
\add_temp_14__0_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__2_i_1_n_0\,
I1 => RESIZE44(14),
I2 => RESIZE42(14),
I3 => RESIZE15(14),
O => \add_temp_14__0_carry__2_i_5_n_0\
);
\add_temp_14__0_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE15(13),
I1 => RESIZE42(13),
I2 => RESIZE44(13),
I3 => \add_temp_14__0_carry__2_i_2_n_0\,
O => \add_temp_14__0_carry__2_i_6_n_0\
);
\add_temp_14__0_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(12),
I1 => RESIZE15(12),
I2 => RESIZE42(12),
I3 => \add_temp_14__0_carry__2_i_3_n_0\,
O => \add_temp_14__0_carry__2_i_7_n_0\
);
\add_temp_14__0_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(2),
I1 => RESIZE15(2),
I2 => RESIZE42(2),
O => \add_temp_14__0_carry_i_1_n_0\
);
\add_temp_14__0_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(1),
I1 => RESIZE15(1),
I2 => RESIZE42(1),
O => \add_temp_14__0_carry_i_2_n_0\
);
\add_temp_14__0_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(0),
I1 => RESIZE15(0),
I2 => RESIZE42(0),
O => \add_temp_14__0_carry_i_3_n_0\
);
\add_temp_14__0_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(3),
I1 => RESIZE15(3),
I2 => RESIZE42(3),
I3 => \add_temp_14__0_carry_i_1_n_0\,
O => \add_temp_14__0_carry_i_4_n_0\
);
\add_temp_14__0_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(2),
I1 => RESIZE15(2),
I2 => RESIZE42(2),
I3 => \add_temp_14__0_carry_i_2_n_0\,
O => \add_temp_14__0_carry_i_5_n_0\
);
\add_temp_14__0_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(1),
I1 => RESIZE15(1),
I2 => RESIZE42(1),
I3 => \add_temp_14__0_carry_i_3_n_0\,
O => \add_temp_14__0_carry_i_6_n_0\
);
\add_temp_14__0_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE44(0),
I1 => RESIZE15(0),
I2 => RESIZE42(0),
O => \add_temp_14__0_carry_i_7_n_0\
);
\add_temp_14__138_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__138_carry_n_0\,
CO(2) => \add_temp_14__138_carry_n_1\,
CO(1) => \add_temp_14__138_carry_n_2\,
CO(0) => \add_temp_14__138_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__138_carry_i_1_n_0\,
DI(2) => \add_temp_14__138_carry_i_2_n_0\,
DI(1) => \add_temp_14__138_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__138_carry_n_4\,
O(2) => \add_temp_14__138_carry_n_5\,
O(1) => \add_temp_14__138_carry_n_6\,
O(0) => \add_temp_14__138_carry_n_7\,
S(3) => \add_temp_14__138_carry_i_4_n_0\,
S(2) => \add_temp_14__138_carry_i_5_n_0\,
S(1) => \add_temp_14__138_carry_i_6_n_0\,
S(0) => \add_temp_14__138_carry_i_7_n_0\
);
\add_temp_14__138_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__138_carry_n_0\,
CO(3) => \add_temp_14__138_carry__0_n_0\,
CO(2) => \add_temp_14__138_carry__0_n_1\,
CO(1) => \add_temp_14__138_carry__0_n_2\,
CO(0) => \add_temp_14__138_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__138_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__138_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__138_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__138_carry__0_i_4_n_0\,
O(3) => \add_temp_14__138_carry__0_n_4\,
O(2) => \add_temp_14__138_carry__0_n_5\,
O(1) => \add_temp_14__138_carry__0_n_6\,
O(0) => \add_temp_14__138_carry__0_n_7\,
S(3) => \add_temp_14__138_carry__0_i_5_n_0\,
S(2) => \add_temp_14__138_carry__0_i_6_n_0\,
S(1) => \add_temp_14__138_carry__0_i_7_n_0\,
S(0) => \add_temp_14__138_carry__0_i_8_n_0\
);
\add_temp_14__138_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(6),
I1 => RESIZE26(6),
I2 => RESIZE28(6),
O => \add_temp_14__138_carry__0_i_1_n_0\
);
\add_temp_14__138_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE28(5),
I1 => RESIZE24(5),
I2 => RESIZE26(5),
O => \add_temp_14__138_carry__0_i_2_n_0\
);
\add_temp_14__138_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(4),
I1 => RESIZE24(4),
I2 => RESIZE28(4),
O => \add_temp_14__138_carry__0_i_3_n_0\
);
\add_temp_14__138_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(3),
I1 => RESIZE28(3),
I2 => RESIZE24(3),
O => \add_temp_14__138_carry__0_i_4_n_0\
);
\add_temp_14__138_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(7),
I1 => RESIZE26(7),
I2 => RESIZE28(7),
I3 => \add_temp_14__138_carry__0_i_1_n_0\,
O => \add_temp_14__138_carry__0_i_5_n_0\
);
\add_temp_14__138_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(6),
I1 => RESIZE26(6),
I2 => RESIZE28(6),
I3 => \add_temp_14__138_carry__0_i_2_n_0\,
O => \add_temp_14__138_carry__0_i_6_n_0\
);
\add_temp_14__138_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE28(5),
I1 => RESIZE24(5),
I2 => RESIZE26(5),
I3 => \add_temp_14__138_carry__0_i_3_n_0\,
O => \add_temp_14__138_carry__0_i_7_n_0\
);
\add_temp_14__138_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE26(4),
I1 => RESIZE24(4),
I2 => RESIZE28(4),
I3 => \add_temp_14__138_carry__0_i_4_n_0\,
O => \add_temp_14__138_carry__0_i_8_n_0\
);
\add_temp_14__138_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__138_carry__0_n_0\,
CO(3) => \add_temp_14__138_carry__1_n_0\,
CO(2) => \add_temp_14__138_carry__1_n_1\,
CO(1) => \add_temp_14__138_carry__1_n_2\,
CO(0) => \add_temp_14__138_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__138_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__138_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__138_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__138_carry__1_i_4_n_0\,
O(3) => \add_temp_14__138_carry__1_n_4\,
O(2) => \add_temp_14__138_carry__1_n_5\,
O(1) => \add_temp_14__138_carry__1_n_6\,
O(0) => \add_temp_14__138_carry__1_n_7\,
S(3) => \add_temp_14__138_carry__1_i_5_n_0\,
S(2) => \add_temp_14__138_carry__1_i_6_n_0\,
S(1) => \add_temp_14__138_carry__1_i_7_n_0\,
S(0) => \add_temp_14__138_carry__1_i_8_n_0\
);
\add_temp_14__138_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(10),
I1 => RESIZE26(10),
I2 => RESIZE28(10),
O => \add_temp_14__138_carry__1_i_1_n_0\
);
\add_temp_14__138_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(9),
I1 => RESIZE26(9),
I2 => RESIZE28(9),
O => \add_temp_14__138_carry__1_i_2_n_0\
);
\add_temp_14__138_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(8),
I1 => RESIZE26(8),
I2 => RESIZE28(8),
O => \add_temp_14__138_carry__1_i_3_n_0\
);
\add_temp_14__138_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(7),
I1 => RESIZE26(7),
I2 => RESIZE28(7),
O => \add_temp_14__138_carry__1_i_4_n_0\
);
\add_temp_14__138_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(11),
I1 => RESIZE26(11),
I2 => RESIZE28(11),
I3 => \add_temp_14__138_carry__1_i_1_n_0\,
O => \add_temp_14__138_carry__1_i_5_n_0\
);
\add_temp_14__138_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(10),
I1 => RESIZE26(10),
I2 => RESIZE28(10),
I3 => \add_temp_14__138_carry__1_i_2_n_0\,
O => \add_temp_14__138_carry__1_i_6_n_0\
);
\add_temp_14__138_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(9),
I1 => RESIZE26(9),
I2 => RESIZE28(9),
I3 => \add_temp_14__138_carry__1_i_3_n_0\,
O => \add_temp_14__138_carry__1_i_7_n_0\
);
\add_temp_14__138_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(8),
I1 => RESIZE26(8),
I2 => RESIZE28(8),
I3 => \add_temp_14__138_carry__1_i_4_n_0\,
O => \add_temp_14__138_carry__1_i_8_n_0\
);
\add_temp_14__138_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__138_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__138_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__138_carry__2_n_1\,
CO(1) => \add_temp_14__138_carry__2_n_2\,
CO(0) => \add_temp_14__138_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__138_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__138_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__138_carry__2_i_3_n_0\,
O(3) => \add_temp_14__138_carry__2_n_4\,
O(2) => \add_temp_14__138_carry__2_n_5\,
O(1) => \add_temp_14__138_carry__2_n_6\,
O(0) => \add_temp_14__138_carry__2_n_7\,
S(3) => \add_temp_14__138_carry__2_i_4_n_0\,
S(2) => \add_temp_14__138_carry__2_i_5_n_0\,
S(1) => \add_temp_14__138_carry__2_i_6_n_0\,
S(0) => \add_temp_14__138_carry__2_i_7_n_0\
);
\add_temp_14__138_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(13),
I1 => RESIZE26(13),
I2 => RESIZE28(13),
O => \add_temp_14__138_carry__2_i_1_n_0\
);
\add_temp_14__138_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(12),
I1 => RESIZE26(12),
I2 => RESIZE28(12),
O => \add_temp_14__138_carry__2_i_2_n_0\
);
\add_temp_14__138_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(11),
I1 => RESIZE26(11),
I2 => RESIZE28(11),
O => \add_temp_14__138_carry__2_i_3_n_0\
);
\add_temp_14__138_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE28(14),
I1 => RESIZE26(14),
I2 => RESIZE24(14),
I3 => RESIZE26(15),
I4 => RESIZE24(15),
I5 => RESIZE28(15),
O => \add_temp_14__138_carry__2_i_4_n_0\
);
\add_temp_14__138_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__138_carry__2_i_1_n_0\,
I1 => RESIZE26(14),
I2 => RESIZE24(14),
I3 => RESIZE28(14),
O => \add_temp_14__138_carry__2_i_5_n_0\
);
\add_temp_14__138_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(13),
I1 => RESIZE26(13),
I2 => RESIZE28(13),
I3 => \add_temp_14__138_carry__2_i_2_n_0\,
O => \add_temp_14__138_carry__2_i_6_n_0\
);
\add_temp_14__138_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(12),
I1 => RESIZE26(12),
I2 => RESIZE28(12),
I3 => \add_temp_14__138_carry__2_i_3_n_0\,
O => \add_temp_14__138_carry__2_i_7_n_0\
);
\add_temp_14__138_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(2),
I1 => RESIZE28(2),
I2 => RESIZE24(2),
O => \add_temp_14__138_carry_i_1_n_0\
);
\add_temp_14__138_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(1),
I1 => RESIZE28(1),
I2 => RESIZE24(1),
O => \add_temp_14__138_carry_i_2_n_0\
);
\add_temp_14__138_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(0),
I1 => RESIZE28(0),
I2 => RESIZE24(0),
O => \add_temp_14__138_carry_i_3_n_0\
);
\add_temp_14__138_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE26(3),
I1 => RESIZE28(3),
I2 => RESIZE24(3),
I3 => \add_temp_14__138_carry_i_1_n_0\,
O => \add_temp_14__138_carry_i_4_n_0\
);
\add_temp_14__138_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE26(2),
I1 => RESIZE28(2),
I2 => RESIZE24(2),
I3 => \add_temp_14__138_carry_i_2_n_0\,
O => \add_temp_14__138_carry_i_5_n_0\
);
\add_temp_14__138_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE26(1),
I1 => RESIZE28(1),
I2 => RESIZE24(1),
I3 => \add_temp_14__138_carry_i_3_n_0\,
O => \add_temp_14__138_carry_i_6_n_0\
);
\add_temp_14__138_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE26(0),
I1 => RESIZE28(0),
I2 => RESIZE24(0),
O => \add_temp_14__138_carry_i_7_n_0\
);
\add_temp_14__184_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__184_carry_n_0\,
CO(2) => \add_temp_14__184_carry_n_1\,
CO(1) => \add_temp_14__184_carry_n_2\,
CO(0) => \add_temp_14__184_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__184_carry_i_1_n_0\,
DI(2) => \add_temp_14__184_carry_i_2_n_0\,
DI(1) => \add_temp_14__184_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__184_carry_n_4\,
O(2) => \add_temp_14__184_carry_n_5\,
O(1) => \add_temp_14__184_carry_n_6\,
O(0) => \add_temp_14__184_carry_n_7\,
S(3) => \add_temp_14__184_carry_i_4_n_0\,
S(2) => \add_temp_14__184_carry_i_5_n_0\,
S(1) => \add_temp_14__184_carry_i_6_n_0\,
S(0) => \add_temp_14__184_carry_i_7_n_0\
);
\add_temp_14__184_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__184_carry_n_0\,
CO(3) => \add_temp_14__184_carry__0_n_0\,
CO(2) => \add_temp_14__184_carry__0_n_1\,
CO(1) => \add_temp_14__184_carry__0_n_2\,
CO(0) => \add_temp_14__184_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__184_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__184_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__184_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__184_carry__0_i_4_n_0\,
O(3) => \add_temp_14__184_carry__0_n_4\,
O(2) => \add_temp_14__184_carry__0_n_5\,
O(1) => \add_temp_14__184_carry__0_n_6\,
O(0) => \add_temp_14__184_carry__0_n_7\,
S(3) => \add_temp_14__184_carry__0_i_5_n_0\,
S(2) => \add_temp_14__184_carry__0_i_6_n_0\,
S(1) => \add_temp_14__184_carry__0_i_7_n_0\,
S(0) => \add_temp_14__184_carry__0_i_8_n_0\
);
\add_temp_14__184_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(6),
I1 => RESIZE18(6),
I2 => RESIZE22(6),
O => \add_temp_14__184_carry__0_i_1_n_0\
);
\add_temp_14__184_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(5),
I1 => RESIZE18(5),
I2 => RESIZE22(5),
O => \add_temp_14__184_carry__0_i_2_n_0\
);
\add_temp_14__184_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(4),
I1 => RESIZE18(4),
I2 => RESIZE22(4),
O => \add_temp_14__184_carry__0_i_3_n_0\
);
\add_temp_14__184_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(3),
I1 => RESIZE22(3),
I2 => RESIZE20(3),
O => \add_temp_14__184_carry__0_i_4_n_0\
);
\add_temp_14__184_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(7),
I1 => RESIZE18(7),
I2 => RESIZE22(7),
I3 => \add_temp_14__184_carry__0_i_1_n_0\,
O => \add_temp_14__184_carry__0_i_5_n_0\
);
\add_temp_14__184_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(6),
I1 => RESIZE18(6),
I2 => RESIZE22(6),
I3 => \add_temp_14__184_carry__0_i_2_n_0\,
O => \add_temp_14__184_carry__0_i_6_n_0\
);
\add_temp_14__184_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(5),
I1 => RESIZE18(5),
I2 => RESIZE22(5),
I3 => \add_temp_14__184_carry__0_i_3_n_0\,
O => \add_temp_14__184_carry__0_i_7_n_0\
);
\add_temp_14__184_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(4),
I1 => RESIZE18(4),
I2 => RESIZE22(4),
I3 => \add_temp_14__184_carry__0_i_4_n_0\,
O => \add_temp_14__184_carry__0_i_8_n_0\
);
\add_temp_14__184_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__184_carry__0_n_0\,
CO(3) => \add_temp_14__184_carry__1_n_0\,
CO(2) => \add_temp_14__184_carry__1_n_1\,
CO(1) => \add_temp_14__184_carry__1_n_2\,
CO(0) => \add_temp_14__184_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__184_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__184_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__184_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__184_carry__1_i_4_n_0\,
O(3) => \add_temp_14__184_carry__1_n_4\,
O(2) => \add_temp_14__184_carry__1_n_5\,
O(1) => \add_temp_14__184_carry__1_n_6\,
O(0) => \add_temp_14__184_carry__1_n_7\,
S(3) => \add_temp_14__184_carry__1_i_5_n_0\,
S(2) => \add_temp_14__184_carry__1_i_6_n_0\,
S(1) => \add_temp_14__184_carry__1_i_7_n_0\,
S(0) => \add_temp_14__184_carry__1_i_8_n_0\
);
\add_temp_14__184_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(10),
I1 => RESIZE22(10),
I2 => RESIZE20(10),
O => \add_temp_14__184_carry__1_i_1_n_0\
);
\add_temp_14__184_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(9),
I1 => RESIZE22(9),
I2 => RESIZE20(9),
O => \add_temp_14__184_carry__1_i_2_n_0\
);
\add_temp_14__184_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(8),
I1 => RESIZE22(8),
I2 => RESIZE20(8),
O => \add_temp_14__184_carry__1_i_3_n_0\
);
\add_temp_14__184_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(7),
I1 => RESIZE18(7),
I2 => RESIZE22(7),
O => \add_temp_14__184_carry__1_i_4_n_0\
);
\add_temp_14__184_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(11),
I1 => RESIZE22(11),
I2 => RESIZE20(11),
I3 => \add_temp_14__184_carry__1_i_1_n_0\,
O => \add_temp_14__184_carry__1_i_5_n_0\
);
\add_temp_14__184_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(10),
I1 => RESIZE22(10),
I2 => RESIZE20(10),
I3 => \add_temp_14__184_carry__1_i_2_n_0\,
O => \add_temp_14__184_carry__1_i_6_n_0\
);
\add_temp_14__184_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(9),
I1 => RESIZE22(9),
I2 => RESIZE20(9),
I3 => \add_temp_14__184_carry__1_i_3_n_0\,
O => \add_temp_14__184_carry__1_i_7_n_0\
);
\add_temp_14__184_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(8),
I1 => RESIZE22(8),
I2 => RESIZE20(8),
I3 => \add_temp_14__184_carry__1_i_4_n_0\,
O => \add_temp_14__184_carry__1_i_8_n_0\
);
\add_temp_14__184_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__184_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__184_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__184_carry__2_n_1\,
CO(1) => \add_temp_14__184_carry__2_n_2\,
CO(0) => \add_temp_14__184_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__184_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__184_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__184_carry__2_i_3_n_0\,
O(3) => \add_temp_14__184_carry__2_n_4\,
O(2) => \add_temp_14__184_carry__2_n_5\,
O(1) => \add_temp_14__184_carry__2_n_6\,
O(0) => \add_temp_14__184_carry__2_n_7\,
S(3) => \add_temp_14__184_carry__2_i_4_n_0\,
S(2) => \add_temp_14__184_carry__2_i_5_n_0\,
S(1) => \add_temp_14__184_carry__2_i_6_n_0\,
S(0) => \add_temp_14__184_carry__2_i_7_n_0\
);
\add_temp_14__184_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(13),
I1 => RESIZE22(13),
I2 => RESIZE20(13),
O => \add_temp_14__184_carry__2_i_1_n_0\
);
\add_temp_14__184_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(12),
I1 => RESIZE22(12),
I2 => RESIZE20(12),
O => \add_temp_14__184_carry__2_i_2_n_0\
);
\add_temp_14__184_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(11),
I1 => RESIZE22(11),
I2 => RESIZE20(11),
O => \add_temp_14__184_carry__2_i_3_n_0\
);
\add_temp_14__184_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE20(14),
I1 => RESIZE22(14),
I2 => RESIZE18(14),
I3 => RESIZE20(15),
I4 => RESIZE18(15),
I5 => RESIZE22(15),
O => \add_temp_14__184_carry__2_i_4_n_0\
);
\add_temp_14__184_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__184_carry__2_i_1_n_0\,
I1 => RESIZE20(14),
I2 => RESIZE18(14),
I3 => RESIZE22(14),
O => \add_temp_14__184_carry__2_i_5_n_0\
);
\add_temp_14__184_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(13),
I1 => RESIZE22(13),
I2 => RESIZE20(13),
I3 => \add_temp_14__184_carry__2_i_2_n_0\,
O => \add_temp_14__184_carry__2_i_6_n_0\
);
\add_temp_14__184_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(12),
I1 => RESIZE22(12),
I2 => RESIZE20(12),
I3 => \add_temp_14__184_carry__2_i_3_n_0\,
O => \add_temp_14__184_carry__2_i_7_n_0\
);
\add_temp_14__184_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE22(2),
I1 => RESIZE18(2),
I2 => RESIZE20(2),
O => \add_temp_14__184_carry_i_1_n_0\
);
\add_temp_14__184_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(1),
I1 => RESIZE18(1),
I2 => RESIZE22(1),
O => \add_temp_14__184_carry_i_2_n_0\
);
\add_temp_14__184_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(0),
I1 => RESIZE22(0),
I2 => RESIZE20(0),
O => \add_temp_14__184_carry_i_3_n_0\
);
\add_temp_14__184_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(3),
I1 => RESIZE22(3),
I2 => RESIZE20(3),
I3 => \add_temp_14__184_carry_i_1_n_0\,
O => \add_temp_14__184_carry_i_4_n_0\
);
\add_temp_14__184_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE22(2),
I1 => RESIZE18(2),
I2 => RESIZE20(2),
I3 => \add_temp_14__184_carry_i_2_n_0\,
O => \add_temp_14__184_carry_i_5_n_0\
);
\add_temp_14__184_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(1),
I1 => RESIZE18(1),
I2 => RESIZE22(1),
I3 => \add_temp_14__184_carry_i_3_n_0\,
O => \add_temp_14__184_carry_i_6_n_0\
);
\add_temp_14__184_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE18(0),
I1 => RESIZE22(0),
I2 => RESIZE20(0),
O => \add_temp_14__184_carry_i_7_n_0\
);
\add_temp_14__230_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__230_carry_n_0\,
CO(2) => \add_temp_14__230_carry_n_1\,
CO(1) => \add_temp_14__230_carry_n_2\,
CO(0) => \add_temp_14__230_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__230_carry_i_1_n_0\,
DI(2) => \add_temp_14__230_carry_i_2_n_0\,
DI(1) => \add_temp_14__230_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__230_carry_n_4\,
O(2) => \add_temp_14__230_carry_n_5\,
O(1) => \add_temp_14__230_carry_n_6\,
O(0) => \add_temp_14__230_carry_n_7\,
S(3) => \add_temp_14__230_carry_i_4_n_0\,
S(2) => \add_temp_14__230_carry_i_5_n_0\,
S(1) => \add_temp_14__230_carry_i_6_n_0\,
S(0) => \add_temp_14__230_carry_i_7_n_0\
);
\add_temp_14__230_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__230_carry_n_0\,
CO(3) => \add_temp_14__230_carry__0_n_0\,
CO(2) => \add_temp_14__230_carry__0_n_1\,
CO(1) => \add_temp_14__230_carry__0_n_2\,
CO(0) => \add_temp_14__230_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__230_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__230_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__230_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__230_carry__0_i_4_n_0\,
O(3) => \add_temp_14__230_carry__0_n_4\,
O(2) => \add_temp_14__230_carry__0_n_5\,
O(1) => \add_temp_14__230_carry__0_n_6\,
O(0) => \add_temp_14__230_carry__0_n_7\,
S(3) => \add_temp_14__230_carry__0_i_5_n_0\,
S(2) => \add_temp_14__230_carry__0_i_6_n_0\,
S(1) => \add_temp_14__230_carry__0_i_7_n_0\,
S(0) => \add_temp_14__230_carry__0_i_8_n_0\
);
\add_temp_14__230_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(6),
I1 => \add_temp_14__0_carry__0_n_5\,
I2 => \add_temp_14__46_carry__0_n_5\,
O => \add_temp_14__230_carry__0_i_1_n_0\
);
\add_temp_14__230_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(5),
I1 => \add_temp_14__46_carry__0_n_6\,
I2 => \add_temp_14__0_carry__0_n_6\,
O => \add_temp_14__230_carry__0_i_2_n_0\
);
\add_temp_14__230_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry__0_n_7\,
I1 => \add_temp_14__46_carry__0_n_7\,
I2 => RESIZE16(4),
O => \add_temp_14__230_carry__0_i_3_n_0\
);
\add_temp_14__230_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry_n_4\,
I1 => \add_temp_14__46_carry_n_4\,
I2 => RESIZE16(3),
O => \add_temp_14__230_carry__0_i_4_n_0\
);
\add_temp_14__230_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__0_n_4\,
I1 => \add_temp_14__46_carry__0_n_4\,
I2 => RESIZE16(7),
I3 => \add_temp_14__230_carry__0_i_1_n_0\,
O => \add_temp_14__230_carry__0_i_5_n_0\
);
\add_temp_14__230_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(6),
I1 => \add_temp_14__0_carry__0_n_5\,
I2 => \add_temp_14__46_carry__0_n_5\,
I3 => \add_temp_14__230_carry__0_i_2_n_0\,
O => \add_temp_14__230_carry__0_i_6_n_0\
);
\add_temp_14__230_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(5),
I1 => \add_temp_14__46_carry__0_n_6\,
I2 => \add_temp_14__0_carry__0_n_6\,
I3 => \add_temp_14__230_carry__0_i_3_n_0\,
O => \add_temp_14__230_carry__0_i_7_n_0\
);
\add_temp_14__230_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__0_n_7\,
I1 => \add_temp_14__46_carry__0_n_7\,
I2 => RESIZE16(4),
I3 => \add_temp_14__230_carry__0_i_4_n_0\,
O => \add_temp_14__230_carry__0_i_8_n_0\
);
\add_temp_14__230_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__230_carry__0_n_0\,
CO(3) => \add_temp_14__230_carry__1_n_0\,
CO(2) => \add_temp_14__230_carry__1_n_1\,
CO(1) => \add_temp_14__230_carry__1_n_2\,
CO(0) => \add_temp_14__230_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__230_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__230_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__230_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__230_carry__1_i_4_n_0\,
O(3) => \add_temp_14__230_carry__1_n_4\,
O(2) => \add_temp_14__230_carry__1_n_5\,
O(1) => \add_temp_14__230_carry__1_n_6\,
O(0) => \add_temp_14__230_carry__1_n_7\,
S(3) => \add_temp_14__230_carry__1_i_5_n_0\,
S(2) => \add_temp_14__230_carry__1_i_6_n_0\,
S(1) => \add_temp_14__230_carry__1_i_7_n_0\,
S(0) => \add_temp_14__230_carry__1_i_8_n_0\
);
\add_temp_14__230_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(10),
I1 => \add_temp_14__0_carry__1_n_5\,
I2 => \add_temp_14__46_carry__1_n_5\,
O => \add_temp_14__230_carry__1_i_1_n_0\
);
\add_temp_14__230_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry__1_n_6\,
I1 => \add_temp_14__46_carry__1_n_6\,
I2 => RESIZE16(9),
O => \add_temp_14__230_carry__1_i_2_n_0\
);
\add_temp_14__230_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry__1_n_7\,
I1 => RESIZE16(8),
I2 => \add_temp_14__46_carry__1_n_7\,
O => \add_temp_14__230_carry__1_i_3_n_0\
);
\add_temp_14__230_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry__0_n_4\,
I1 => \add_temp_14__46_carry__0_n_4\,
I2 => RESIZE16(7),
O => \add_temp_14__230_carry__1_i_4_n_0\
);
\add_temp_14__230_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(11),
I1 => \add_temp_14__0_carry__1_n_4\,
I2 => \add_temp_14__46_carry__1_n_4\,
I3 => \add_temp_14__230_carry__1_i_1_n_0\,
O => \add_temp_14__230_carry__1_i_5_n_0\
);
\add_temp_14__230_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(10),
I1 => \add_temp_14__0_carry__1_n_5\,
I2 => \add_temp_14__46_carry__1_n_5\,
I3 => \add_temp_14__230_carry__1_i_2_n_0\,
O => \add_temp_14__230_carry__1_i_6_n_0\
);
\add_temp_14__230_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__1_n_6\,
I1 => \add_temp_14__46_carry__1_n_6\,
I2 => RESIZE16(9),
I3 => \add_temp_14__230_carry__1_i_3_n_0\,
O => \add_temp_14__230_carry__1_i_7_n_0\
);
\add_temp_14__230_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__1_n_7\,
I1 => RESIZE16(8),
I2 => \add_temp_14__46_carry__1_n_7\,
I3 => \add_temp_14__230_carry__1_i_4_n_0\,
O => \add_temp_14__230_carry__1_i_8_n_0\
);
\add_temp_14__230_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__230_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__230_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__230_carry__2_n_1\,
CO(1) => \add_temp_14__230_carry__2_n_2\,
CO(0) => \add_temp_14__230_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__230_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__230_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__230_carry__2_i_3_n_0\,
O(3) => \add_temp_14__230_carry__2_n_4\,
O(2) => \add_temp_14__230_carry__2_n_5\,
O(1) => \add_temp_14__230_carry__2_n_6\,
O(0) => \add_temp_14__230_carry__2_n_7\,
S(3) => \add_temp_14__230_carry__2_i_4_n_0\,
S(2) => \add_temp_14__230_carry__2_i_5_n_0\,
S(1) => \add_temp_14__230_carry__2_i_6_n_0\,
S(0) => \add_temp_14__230_carry__2_i_7_n_0\
);
\add_temp_14__230_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(13),
I1 => \add_temp_14__0_carry__2_n_6\,
I2 => \add_temp_14__46_carry__2_n_6\,
O => \add_temp_14__230_carry__2_i_1_n_0\
);
\add_temp_14__230_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(12),
I1 => \add_temp_14__0_carry__2_n_7\,
I2 => \add_temp_14__46_carry__2_n_7\,
O => \add_temp_14__230_carry__2_i_2_n_0\
);
\add_temp_14__230_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(11),
I1 => \add_temp_14__0_carry__1_n_4\,
I2 => \add_temp_14__46_carry__1_n_4\,
O => \add_temp_14__230_carry__2_i_3_n_0\
);
\add_temp_14__230_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => \add_temp_14__46_carry__2_n_5\,
I1 => \add_temp_14__0_carry__2_n_5\,
I2 => RESIZE16(14),
I3 => \add_temp_14__0_carry__2_n_4\,
I4 => \add_temp_14__46_carry__2_n_4\,
I5 => RESIZE16(15),
O => \add_temp_14__230_carry__2_i_4_n_0\
);
\add_temp_14__230_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__230_carry__2_i_1_n_0\,
I1 => \add_temp_14__0_carry__2_n_5\,
I2 => \add_temp_14__46_carry__2_n_5\,
I3 => RESIZE16(14),
O => \add_temp_14__230_carry__2_i_5_n_0\
);
\add_temp_14__230_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(13),
I1 => \add_temp_14__0_carry__2_n_6\,
I2 => \add_temp_14__46_carry__2_n_6\,
I3 => \add_temp_14__230_carry__2_i_2_n_0\,
O => \add_temp_14__230_carry__2_i_6_n_0\
);
\add_temp_14__230_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(12),
I1 => \add_temp_14__0_carry__2_n_7\,
I2 => \add_temp_14__46_carry__2_n_7\,
I3 => \add_temp_14__230_carry__2_i_3_n_0\,
O => \add_temp_14__230_carry__2_i_7_n_0\
);
\add_temp_14__230_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__46_carry_n_5\,
I1 => \add_temp_14__0_carry_n_5\,
I2 => RESIZE16(2),
O => \add_temp_14__230_carry_i_1_n_0\
);
\add_temp_14__230_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry_n_6\,
I1 => RESIZE16(1),
I2 => \add_temp_14__46_carry_n_6\,
O => \add_temp_14__230_carry_i_2_n_0\
);
\add_temp_14__230_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__46_carry_n_7\,
I1 => \add_temp_14__0_carry_n_7\,
I2 => RESIZE16(0),
O => \add_temp_14__230_carry_i_3_n_0\
);
\add_temp_14__230_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry_n_4\,
I1 => \add_temp_14__46_carry_n_4\,
I2 => RESIZE16(3),
I3 => \add_temp_14__230_carry_i_1_n_0\,
O => \add_temp_14__230_carry_i_4_n_0\
);
\add_temp_14__230_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__46_carry_n_5\,
I1 => \add_temp_14__0_carry_n_5\,
I2 => RESIZE16(2),
I3 => \add_temp_14__230_carry_i_2_n_0\,
O => \add_temp_14__230_carry_i_5_n_0\
);
\add_temp_14__230_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry_n_6\,
I1 => RESIZE16(1),
I2 => \add_temp_14__46_carry_n_6\,
I3 => \add_temp_14__230_carry_i_3_n_0\,
O => \add_temp_14__230_carry_i_6_n_0\
);
\add_temp_14__230_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__46_carry_n_7\,
I1 => \add_temp_14__0_carry_n_7\,
I2 => RESIZE16(0),
O => \add_temp_14__230_carry_i_7_n_0\
);
\add_temp_14__278_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__278_carry_n_0\,
CO(2) => \add_temp_14__278_carry_n_1\,
CO(1) => \add_temp_14__278_carry_n_2\,
CO(0) => \add_temp_14__278_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__278_carry_i_1_n_0\,
DI(2) => \add_temp_14__278_carry_i_2_n_0\,
DI(1) => \add_temp_14__278_carry_i_3_n_0\,
DI(0) => \add_temp_14__92_carry_n_7\,
O(3 downto 0) => filter_sum(3 downto 0),
S(3) => \add_temp_14__278_carry_i_4_n_0\,
S(2) => \add_temp_14__278_carry_i_5_n_0\,
S(1) => \add_temp_14__278_carry_i_6_n_0\,
S(0) => \add_temp_14__278_carry_i_7_n_0\
);
\add_temp_14__278_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__278_carry_n_0\,
CO(3) => \add_temp_14__278_carry__0_n_0\,
CO(2) => \add_temp_14__278_carry__0_n_1\,
CO(1) => \add_temp_14__278_carry__0_n_2\,
CO(0) => \add_temp_14__278_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__278_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__278_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__278_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__278_carry__0_i_4_n_0\,
O(3 downto 0) => filter_sum(7 downto 4),
S(3) => \add_temp_14__278_carry__0_i_5_n_0\,
S(2) => \add_temp_14__278_carry__0_i_6_n_0\,
S(1) => \add_temp_14__278_carry__0_i_7_n_0\,
S(0) => \add_temp_14__278_carry__0_i_8_n_0\
);
\add_temp_14__278_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__0_n_5\,
I1 => \add_temp_14__230_carry__0_n_5\,
I2 => \add_temp_14__184_carry__0_n_5\,
I3 => \add_temp_14__278_carry__0_i_9_n_0\,
I4 => \add_temp_14__92_carry__0_n_5\,
O => \add_temp_14__278_carry__0_i_1_n_0\
);
\add_temp_14__278_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__230_carry__0_n_7\,
I1 => \add_temp_14__184_carry__0_n_7\,
I2 => \add_temp_14__138_carry__0_n_7\,
O => \add_temp_14__278_carry__0_i_10_n_0\
);
\add_temp_14__278_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__230_carry_n_4\,
I1 => \add_temp_14__184_carry_n_4\,
I2 => \add_temp_14__138_carry_n_4\,
O => \add_temp_14__278_carry__0_i_11_n_0\
);
\add_temp_14__278_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry__0_n_4\,
I1 => \add_temp_14__230_carry__0_n_4\,
I2 => \add_temp_14__184_carry__0_n_4\,
O => \add_temp_14__278_carry__0_i_12_n_0\
);
\add_temp_14__278_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__0_n_6\,
I1 => \add_temp_14__230_carry__0_n_6\,
I2 => \add_temp_14__184_carry__0_n_6\,
I3 => \add_temp_14__278_carry__0_i_10_n_0\,
I4 => \add_temp_14__92_carry__0_n_6\,
O => \add_temp_14__278_carry__0_i_2_n_0\
);
\add_temp_14__278_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__0_n_7\,
I1 => \add_temp_14__230_carry__0_n_7\,
I2 => \add_temp_14__184_carry__0_n_7\,
I3 => \add_temp_14__278_carry__0_i_11_n_0\,
I4 => \add_temp_14__92_carry__0_n_7\,
O => \add_temp_14__278_carry__0_i_3_n_0\
);
\add_temp_14__278_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry_n_4\,
I1 => \add_temp_14__230_carry_n_4\,
I2 => \add_temp_14__184_carry_n_4\,
I3 => \add_temp_14__278_carry_i_9_n_0\,
I4 => \add_temp_14__92_carry_n_4\,
O => \add_temp_14__278_carry__0_i_4_n_0\
);
\add_temp_14__278_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699669969696"
)
port map (
I0 => \add_temp_14__278_carry__0_i_1_n_0\,
I1 => \add_temp_14__278_carry__0_i_12_n_0\,
I2 => \add_temp_14__92_carry__0_n_4\,
I3 => \add_temp_14__138_carry__0_n_5\,
I4 => \add_temp_14__184_carry__0_n_5\,
I5 => \add_temp_14__230_carry__0_n_5\,
O => \add_temp_14__278_carry__0_i_5_n_0\
);
\add_temp_14__278_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__0_i_2_n_0\,
I1 => \add_temp_14__184_carry__0_n_5\,
I2 => \add_temp_14__230_carry__0_n_5\,
I3 => \add_temp_14__138_carry__0_n_5\,
I4 => \add_temp_14__92_carry__0_n_5\,
I5 => \add_temp_14__278_carry__0_i_9_n_0\,
O => \add_temp_14__278_carry__0_i_6_n_0\
);
\add_temp_14__278_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__0_i_3_n_0\,
I1 => \add_temp_14__184_carry__0_n_6\,
I2 => \add_temp_14__230_carry__0_n_6\,
I3 => \add_temp_14__138_carry__0_n_6\,
I4 => \add_temp_14__92_carry__0_n_6\,
I5 => \add_temp_14__278_carry__0_i_10_n_0\,
O => \add_temp_14__278_carry__0_i_7_n_0\
);
\add_temp_14__278_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__0_i_4_n_0\,
I1 => \add_temp_14__184_carry__0_n_7\,
I2 => \add_temp_14__230_carry__0_n_7\,
I3 => \add_temp_14__138_carry__0_n_7\,
I4 => \add_temp_14__92_carry__0_n_7\,
I5 => \add_temp_14__278_carry__0_i_11_n_0\,
O => \add_temp_14__278_carry__0_i_8_n_0\
);
\add_temp_14__278_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__138_carry__0_n_6\,
I1 => \add_temp_14__184_carry__0_n_6\,
I2 => \add_temp_14__230_carry__0_n_6\,
O => \add_temp_14__278_carry__0_i_9_n_0\
);
\add_temp_14__278_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__278_carry__0_n_0\,
CO(3) => \add_temp_14__278_carry__1_n_0\,
CO(2) => \add_temp_14__278_carry__1_n_1\,
CO(1) => \add_temp_14__278_carry__1_n_2\,
CO(0) => \add_temp_14__278_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__278_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__278_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__278_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__278_carry__1_i_4_n_0\,
O(3 downto 0) => filter_sum(11 downto 8),
S(3) => \add_temp_14__278_carry__1_i_5_n_0\,
S(2) => \add_temp_14__278_carry__1_i_6_n_0\,
S(1) => \add_temp_14__278_carry__1_i_7_n_0\,
S(0) => \add_temp_14__278_carry__1_i_8_n_0\
);
\add_temp_14__278_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__1_n_5\,
I1 => \add_temp_14__230_carry__1_n_5\,
I2 => \add_temp_14__184_carry__1_n_5\,
I3 => \add_temp_14__278_carry__1_i_9_n_0\,
I4 => \add_temp_14__92_carry__1_n_5\,
O => \add_temp_14__278_carry__1_i_1_n_0\
);
\add_temp_14__278_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry__1_n_7\,
I1 => \add_temp_14__138_carry__1_n_7\,
I2 => \add_temp_14__230_carry__1_n_7\,
O => \add_temp_14__278_carry__1_i_10_n_0\
);
\add_temp_14__278_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry__1_n_7\,
I1 => \add_temp_14__230_carry__1_n_7\,
I2 => \add_temp_14__184_carry__1_n_7\,
O => \add_temp_14__278_carry__1_i_11_n_0\
);
\add_temp_14__278_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry__1_n_4\,
I1 => \add_temp_14__230_carry__1_n_4\,
I2 => \add_temp_14__184_carry__1_n_4\,
O => \add_temp_14__278_carry__1_i_12_n_0\
);
\add_temp_14__278_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__1_n_6\,
I1 => \add_temp_14__230_carry__1_n_6\,
I2 => \add_temp_14__184_carry__1_n_6\,
I3 => \add_temp_14__278_carry__1_i_10_n_0\,
I4 => \add_temp_14__92_carry__1_n_6\,
O => \add_temp_14__278_carry__1_i_2_n_0\
);
\add_temp_14__278_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEAA880"
)
port map (
I0 => \add_temp_14__92_carry__1_n_7\,
I1 => \add_temp_14__138_carry__0_n_4\,
I2 => \add_temp_14__184_carry__0_n_4\,
I3 => \add_temp_14__230_carry__0_n_4\,
I4 => \add_temp_14__278_carry__1_i_11_n_0\,
O => \add_temp_14__278_carry__1_i_3_n_0\
);
\add_temp_14__278_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEAA880"
)
port map (
I0 => \add_temp_14__92_carry__0_n_4\,
I1 => \add_temp_14__230_carry__0_n_5\,
I2 => \add_temp_14__184_carry__0_n_5\,
I3 => \add_temp_14__138_carry__0_n_5\,
I4 => \add_temp_14__278_carry__0_i_12_n_0\,
O => \add_temp_14__278_carry__1_i_4_n_0\
);
\add_temp_14__278_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699669969696"
)
port map (
I0 => \add_temp_14__278_carry__1_i_1_n_0\,
I1 => \add_temp_14__278_carry__1_i_12_n_0\,
I2 => \add_temp_14__92_carry__1_n_4\,
I3 => \add_temp_14__230_carry__1_n_5\,
I4 => \add_temp_14__184_carry__1_n_5\,
I5 => \add_temp_14__138_carry__1_n_5\,
O => \add_temp_14__278_carry__1_i_5_n_0\
);
\add_temp_14__278_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__1_i_2_n_0\,
I1 => \add_temp_14__184_carry__1_n_5\,
I2 => \add_temp_14__230_carry__1_n_5\,
I3 => \add_temp_14__138_carry__1_n_5\,
I4 => \add_temp_14__92_carry__1_n_5\,
I5 => \add_temp_14__278_carry__1_i_9_n_0\,
O => \add_temp_14__278_carry__1_i_6_n_0\
);
\add_temp_14__278_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__1_i_3_n_0\,
I1 => \add_temp_14__184_carry__1_n_6\,
I2 => \add_temp_14__230_carry__1_n_6\,
I3 => \add_temp_14__138_carry__1_n_6\,
I4 => \add_temp_14__92_carry__1_n_6\,
I5 => \add_temp_14__278_carry__1_i_10_n_0\,
O => \add_temp_14__278_carry__1_i_7_n_0\
);
\add_temp_14__278_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699669969696"
)
port map (
I0 => \add_temp_14__278_carry__1_i_4_n_0\,
I1 => \add_temp_14__278_carry__1_i_11_n_0\,
I2 => \add_temp_14__92_carry__1_n_7\,
I3 => \add_temp_14__230_carry__0_n_4\,
I4 => \add_temp_14__184_carry__0_n_4\,
I5 => \add_temp_14__138_carry__0_n_4\,
O => \add_temp_14__278_carry__1_i_8_n_0\
);
\add_temp_14__278_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry__1_n_6\,
I1 => \add_temp_14__230_carry__1_n_6\,
I2 => \add_temp_14__138_carry__1_n_6\,
O => \add_temp_14__278_carry__1_i_9_n_0\
);
\add_temp_14__278_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__278_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__278_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__278_carry__2_n_1\,
CO(1) => \add_temp_14__278_carry__2_n_2\,
CO(0) => \add_temp_14__278_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__278_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__278_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__278_carry__2_i_3_n_0\,
O(3 downto 0) => filter_sum(15 downto 12),
S(3) => \add_temp_14__278_carry__2_i_4_n_0\,
S(2) => \add_temp_14__278_carry__2_i_5_n_0\,
S(1) => \add_temp_14__278_carry__2_i_6_n_0\,
S(0) => \add_temp_14__278_carry__2_i_7_n_0\
);
\add_temp_14__278_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__2_n_6\,
I1 => \add_temp_14__230_carry__2_n_6\,
I2 => \add_temp_14__184_carry__2_n_6\,
I3 => \add_temp_14__278_carry__2_i_8_n_0\,
I4 => \add_temp_14__92_carry__2_n_6\,
O => \add_temp_14__278_carry__2_i_1_n_0\
);
\add_temp_14__278_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry__2_n_6\,
I1 => \add_temp_14__230_carry__2_n_6\,
I2 => \add_temp_14__138_carry__2_n_6\,
O => \add_temp_14__278_carry__2_i_10_n_0\
);
\add_temp_14__278_carry__2_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__184_carry__2_n_4\,
I1 => \add_temp_14__230_carry__2_n_4\,
I2 => \add_temp_14__138_carry__2_n_4\,
I3 => \add_temp_14__92_carry__2_n_4\,
O => \add_temp_14__278_carry__2_i_11_n_0\
);
\add_temp_14__278_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEAA880"
)
port map (
I0 => \add_temp_14__92_carry__2_n_7\,
I1 => \add_temp_14__138_carry__1_n_4\,
I2 => \add_temp_14__184_carry__1_n_4\,
I3 => \add_temp_14__230_carry__1_n_4\,
I4 => \add_temp_14__278_carry__2_i_9_n_0\,
O => \add_temp_14__278_carry__2_i_2_n_0\
);
\add_temp_14__278_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEAA880"
)
port map (
I0 => \add_temp_14__92_carry__1_n_4\,
I1 => \add_temp_14__138_carry__1_n_5\,
I2 => \add_temp_14__184_carry__1_n_5\,
I3 => \add_temp_14__230_carry__1_n_5\,
I4 => \add_temp_14__278_carry__1_i_12_n_0\,
O => \add_temp_14__278_carry__2_i_3_n_0\
);
\add_temp_14__278_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"E187871E871E1E78"
)
port map (
I0 => \add_temp_14__92_carry__2_n_5\,
I1 => \add_temp_14__278_carry__2_i_10_n_0\,
I2 => \add_temp_14__278_carry__2_i_11_n_0\,
I3 => \add_temp_14__138_carry__2_n_5\,
I4 => \add_temp_14__184_carry__2_n_5\,
I5 => \add_temp_14__230_carry__2_n_5\,
O => \add_temp_14__278_carry__2_i_4_n_0\
);
\add_temp_14__278_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__2_i_1_n_0\,
I1 => \add_temp_14__184_carry__2_n_5\,
I2 => \add_temp_14__230_carry__2_n_5\,
I3 => \add_temp_14__138_carry__2_n_5\,
I4 => \add_temp_14__92_carry__2_n_5\,
I5 => \add_temp_14__278_carry__2_i_10_n_0\,
O => \add_temp_14__278_carry__2_i_5_n_0\
);
\add_temp_14__278_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__2_i_2_n_0\,
I1 => \add_temp_14__184_carry__2_n_6\,
I2 => \add_temp_14__230_carry__2_n_6\,
I3 => \add_temp_14__138_carry__2_n_6\,
I4 => \add_temp_14__92_carry__2_n_6\,
I5 => \add_temp_14__278_carry__2_i_8_n_0\,
O => \add_temp_14__278_carry__2_i_6_n_0\
);
\add_temp_14__278_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699669969696"
)
port map (
I0 => \add_temp_14__278_carry__2_i_3_n_0\,
I1 => \add_temp_14__278_carry__2_i_9_n_0\,
I2 => \add_temp_14__92_carry__2_n_7\,
I3 => \add_temp_14__230_carry__1_n_4\,
I4 => \add_temp_14__184_carry__1_n_4\,
I5 => \add_temp_14__138_carry__1_n_4\,
O => \add_temp_14__278_carry__2_i_7_n_0\
);
\add_temp_14__278_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry__2_n_7\,
I1 => \add_temp_14__138_carry__2_n_7\,
I2 => \add_temp_14__230_carry__2_n_7\,
O => \add_temp_14__278_carry__2_i_8_n_0\
);
\add_temp_14__278_carry__2_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry__2_n_7\,
I1 => \add_temp_14__230_carry__2_n_7\,
I2 => \add_temp_14__184_carry__2_n_7\,
O => \add_temp_14__278_carry__2_i_9_n_0\
);
\add_temp_14__278_carry_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry_n_5\,
I1 => \add_temp_14__230_carry_n_5\,
I2 => \add_temp_14__184_carry_n_5\,
I3 => \add_temp_14__278_carry_i_8_n_0\,
I4 => \add_temp_14__92_carry_n_5\,
O => \add_temp_14__278_carry_i_1_n_0\
);
\add_temp_14__278_carry_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry_n_5\,
I1 => \add_temp_14__230_carry_n_5\,
I2 => \add_temp_14__184_carry_n_5\,
O => \add_temp_14__278_carry_i_10_n_0\
);
\add_temp_14__278_carry_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \add_temp_14__278_carry_i_8_n_0\,
I1 => \add_temp_14__92_carry_n_5\,
I2 => \add_temp_14__138_carry_n_5\,
I3 => \add_temp_14__230_carry_n_5\,
I4 => \add_temp_14__184_carry_n_5\,
O => \add_temp_14__278_carry_i_2_n_0\
);
\add_temp_14__278_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__184_carry_n_6\,
I1 => \add_temp_14__230_carry_n_6\,
I2 => \add_temp_14__138_carry_n_6\,
I3 => \add_temp_14__92_carry_n_6\,
O => \add_temp_14__278_carry_i_3_n_0\
);
\add_temp_14__278_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry_i_1_n_0\,
I1 => \add_temp_14__184_carry_n_4\,
I2 => \add_temp_14__230_carry_n_4\,
I3 => \add_temp_14__138_carry_n_4\,
I4 => \add_temp_14__92_carry_n_4\,
I5 => \add_temp_14__278_carry_i_9_n_0\,
O => \add_temp_14__278_carry_i_4_n_0\
);
\add_temp_14__278_carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6999999699969666"
)
port map (
I0 => \add_temp_14__278_carry_i_10_n_0\,
I1 => \add_temp_14__92_carry_n_5\,
I2 => \add_temp_14__138_carry_n_6\,
I3 => \add_temp_14__230_carry_n_6\,
I4 => \add_temp_14__184_carry_n_6\,
I5 => \add_temp_14__92_carry_n_6\,
O => \add_temp_14__278_carry_i_5_n_0\
);
\add_temp_14__278_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"566A"
)
port map (
I0 => \add_temp_14__278_carry_i_3_n_0\,
I1 => \add_temp_14__230_carry_n_7\,
I2 => \add_temp_14__184_carry_n_7\,
I3 => \add_temp_14__138_carry_n_7\,
O => \add_temp_14__278_carry_i_6_n_0\
);
\add_temp_14__278_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__184_carry_n_7\,
I1 => \add_temp_14__230_carry_n_7\,
I2 => \add_temp_14__138_carry_n_7\,
I3 => \add_temp_14__92_carry_n_7\,
O => \add_temp_14__278_carry_i_7_n_0\
);
\add_temp_14__278_carry_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__138_carry_n_6\,
I1 => \add_temp_14__230_carry_n_6\,
I2 => \add_temp_14__184_carry_n_6\,
O => \add_temp_14__278_carry_i_8_n_0\
);
\add_temp_14__278_carry_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry_n_5\,
I1 => \add_temp_14__138_carry_n_5\,
I2 => \add_temp_14__230_carry_n_5\,
O => \add_temp_14__278_carry_i_9_n_0\
);
\add_temp_14__46_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__46_carry_n_0\,
CO(2) => \add_temp_14__46_carry_n_1\,
CO(1) => \add_temp_14__46_carry_n_2\,
CO(0) => \add_temp_14__46_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__46_carry_i_1_n_0\,
DI(2) => \add_temp_14__46_carry_i_2_n_0\,
DI(1) => \add_temp_14__46_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__46_carry_n_4\,
O(2) => \add_temp_14__46_carry_n_5\,
O(1) => \add_temp_14__46_carry_n_6\,
O(0) => \add_temp_14__46_carry_n_7\,
S(3) => \add_temp_14__46_carry_i_4_n_0\,
S(2) => \add_temp_14__46_carry_i_5_n_0\,
S(1) => \add_temp_14__46_carry_i_6_n_0\,
S(0) => \add_temp_14__46_carry_i_7_n_0\
);
\add_temp_14__46_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__46_carry_n_0\,
CO(3) => \add_temp_14__46_carry__0_n_0\,
CO(2) => \add_temp_14__46_carry__0_n_1\,
CO(1) => \add_temp_14__46_carry__0_n_2\,
CO(0) => \add_temp_14__46_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__46_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__46_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__46_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__46_carry__0_i_4_n_0\,
O(3) => \add_temp_14__46_carry__0_n_4\,
O(2) => \add_temp_14__46_carry__0_n_5\,
O(1) => \add_temp_14__46_carry__0_n_6\,
O(0) => \add_temp_14__46_carry__0_n_7\,
S(3) => \add_temp_14__46_carry__0_i_5_n_0\,
S(2) => \add_temp_14__46_carry__0_i_6_n_0\,
S(1) => \add_temp_14__46_carry__0_i_7_n_0\,
S(0) => \add_temp_14__46_carry__0_i_8_n_0\
);
\add_temp_14__46_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(6),
I1 => RESIZE40(6),
I2 => RESIZE36(6),
O => \add_temp_14__46_carry__0_i_1_n_0\
);
\add_temp_14__46_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(5),
I1 => RESIZE40(5),
I2 => RESIZE36(5),
O => \add_temp_14__46_carry__0_i_2_n_0\
);
\add_temp_14__46_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(4),
I1 => RESIZE40(4),
I2 => RESIZE36(4),
O => \add_temp_14__46_carry__0_i_3_n_0\
);
\add_temp_14__46_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(3),
I1 => RESIZE40(3),
I2 => RESIZE36(3),
O => \add_temp_14__46_carry__0_i_4_n_0\
);
\add_temp_14__46_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(7),
I1 => RESIZE40(7),
I2 => RESIZE36(7),
I3 => \add_temp_14__46_carry__0_i_1_n_0\,
O => \add_temp_14__46_carry__0_i_5_n_0\
);
\add_temp_14__46_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(6),
I1 => RESIZE40(6),
I2 => RESIZE36(6),
I3 => \add_temp_14__46_carry__0_i_2_n_0\,
O => \add_temp_14__46_carry__0_i_6_n_0\
);
\add_temp_14__46_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(5),
I1 => RESIZE40(5),
I2 => RESIZE36(5),
I3 => \add_temp_14__46_carry__0_i_3_n_0\,
O => \add_temp_14__46_carry__0_i_7_n_0\
);
\add_temp_14__46_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(4),
I1 => RESIZE40(4),
I2 => RESIZE36(4),
I3 => \add_temp_14__46_carry__0_i_4_n_0\,
O => \add_temp_14__46_carry__0_i_8_n_0\
);
\add_temp_14__46_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__46_carry__0_n_0\,
CO(3) => \add_temp_14__46_carry__1_n_0\,
CO(2) => \add_temp_14__46_carry__1_n_1\,
CO(1) => \add_temp_14__46_carry__1_n_2\,
CO(0) => \add_temp_14__46_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__46_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__46_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__46_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__46_carry__1_i_4_n_0\,
O(3) => \add_temp_14__46_carry__1_n_4\,
O(2) => \add_temp_14__46_carry__1_n_5\,
O(1) => \add_temp_14__46_carry__1_n_6\,
O(0) => \add_temp_14__46_carry__1_n_7\,
S(3) => \add_temp_14__46_carry__1_i_5_n_0\,
S(2) => \add_temp_14__46_carry__1_i_6_n_0\,
S(1) => \add_temp_14__46_carry__1_i_7_n_0\,
S(0) => \add_temp_14__46_carry__1_i_8_n_0\
);
\add_temp_14__46_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE40(10),
I1 => RESIZE36(10),
I2 => RESIZE38(10),
O => \add_temp_14__46_carry__1_i_1_n_0\
);
\add_temp_14__46_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(9),
I1 => RESIZE40(9),
I2 => RESIZE36(9),
O => \add_temp_14__46_carry__1_i_2_n_0\
);
\add_temp_14__46_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(8),
I1 => RESIZE40(8),
I2 => RESIZE36(8),
O => \add_temp_14__46_carry__1_i_3_n_0\
);
\add_temp_14__46_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(7),
I1 => RESIZE40(7),
I2 => RESIZE36(7),
O => \add_temp_14__46_carry__1_i_4_n_0\
);
\add_temp_14__46_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE36(11),
I1 => RESIZE38(11),
I2 => RESIZE40(11),
I3 => \add_temp_14__46_carry__1_i_1_n_0\,
O => \add_temp_14__46_carry__1_i_5_n_0\
);
\add_temp_14__46_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE40(10),
I1 => RESIZE36(10),
I2 => RESIZE38(10),
I3 => \add_temp_14__46_carry__1_i_2_n_0\,
O => \add_temp_14__46_carry__1_i_6_n_0\
);
\add_temp_14__46_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(9),
I1 => RESIZE40(9),
I2 => RESIZE36(9),
I3 => \add_temp_14__46_carry__1_i_3_n_0\,
O => \add_temp_14__46_carry__1_i_7_n_0\
);
\add_temp_14__46_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(8),
I1 => RESIZE40(8),
I2 => RESIZE36(8),
I3 => \add_temp_14__46_carry__1_i_4_n_0\,
O => \add_temp_14__46_carry__1_i_8_n_0\
);
\add_temp_14__46_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__46_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__46_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__46_carry__2_n_1\,
CO(1) => \add_temp_14__46_carry__2_n_2\,
CO(0) => \add_temp_14__46_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__46_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__46_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__46_carry__2_i_3_n_0\,
O(3) => \add_temp_14__46_carry__2_n_4\,
O(2) => \add_temp_14__46_carry__2_n_5\,
O(1) => \add_temp_14__46_carry__2_n_6\,
O(0) => \add_temp_14__46_carry__2_n_7\,
S(3) => \add_temp_14__46_carry__2_i_4_n_0\,
S(2) => \add_temp_14__46_carry__2_i_5_n_0\,
S(1) => \add_temp_14__46_carry__2_i_6_n_0\,
S(0) => \add_temp_14__46_carry__2_i_7_n_0\
);
\add_temp_14__46_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE36(13),
I1 => RESIZE38(13),
I2 => RESIZE40(13),
O => \add_temp_14__46_carry__2_i_1_n_0\
);
\add_temp_14__46_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE36(12),
I1 => RESIZE38(12),
I2 => RESIZE40(12),
O => \add_temp_14__46_carry__2_i_2_n_0\
);
\add_temp_14__46_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE36(11),
I1 => RESIZE38(11),
I2 => RESIZE40(11),
O => \add_temp_14__46_carry__2_i_3_n_0\
);
\add_temp_14__46_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE40(14),
I1 => RESIZE38(14),
I2 => RESIZE36(14),
I3 => RESIZE38(15),
I4 => RESIZE36(15),
I5 => RESIZE40(15),
O => \add_temp_14__46_carry__2_i_4_n_0\
);
\add_temp_14__46_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__46_carry__2_i_1_n_0\,
I1 => RESIZE38(14),
I2 => RESIZE36(14),
I3 => RESIZE40(14),
O => \add_temp_14__46_carry__2_i_5_n_0\
);
\add_temp_14__46_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE36(13),
I1 => RESIZE38(13),
I2 => RESIZE40(13),
I3 => \add_temp_14__46_carry__2_i_2_n_0\,
O => \add_temp_14__46_carry__2_i_6_n_0\
);
\add_temp_14__46_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE36(12),
I1 => RESIZE38(12),
I2 => RESIZE40(12),
I3 => \add_temp_14__46_carry__2_i_3_n_0\,
O => \add_temp_14__46_carry__2_i_7_n_0\
);
\add_temp_14__46_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(2),
I1 => RESIZE40(2),
I2 => RESIZE36(2),
O => \add_temp_14__46_carry_i_1_n_0\
);
\add_temp_14__46_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(1),
I1 => RESIZE40(1),
I2 => RESIZE36(1),
O => \add_temp_14__46_carry_i_2_n_0\
);
\add_temp_14__46_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(0),
I1 => RESIZE40(0),
I2 => RESIZE36(0),
O => \add_temp_14__46_carry_i_3_n_0\
);
\add_temp_14__46_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(3),
I1 => RESIZE40(3),
I2 => RESIZE36(3),
I3 => \add_temp_14__46_carry_i_1_n_0\,
O => \add_temp_14__46_carry_i_4_n_0\
);
\add_temp_14__46_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(2),
I1 => RESIZE40(2),
I2 => RESIZE36(2),
I3 => \add_temp_14__46_carry_i_2_n_0\,
O => \add_temp_14__46_carry_i_5_n_0\
);
\add_temp_14__46_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(1),
I1 => RESIZE40(1),
I2 => RESIZE36(1),
I3 => \add_temp_14__46_carry_i_3_n_0\,
O => \add_temp_14__46_carry_i_6_n_0\
);
\add_temp_14__46_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE38(0),
I1 => RESIZE40(0),
I2 => RESIZE36(0),
O => \add_temp_14__46_carry_i_7_n_0\
);
\add_temp_14__92_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__92_carry_n_0\,
CO(2) => \add_temp_14__92_carry_n_1\,
CO(1) => \add_temp_14__92_carry_n_2\,
CO(0) => \add_temp_14__92_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__92_carry_i_1_n_0\,
DI(2) => \add_temp_14__92_carry_i_2_n_0\,
DI(1) => \add_temp_14__92_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__92_carry_n_4\,
O(2) => \add_temp_14__92_carry_n_5\,
O(1) => \add_temp_14__92_carry_n_6\,
O(0) => \add_temp_14__92_carry_n_7\,
S(3) => \add_temp_14__92_carry_i_4_n_0\,
S(2) => \add_temp_14__92_carry_i_5_n_0\,
S(1) => \add_temp_14__92_carry_i_6_n_0\,
S(0) => \add_temp_14__92_carry_i_7_n_0\
);
\add_temp_14__92_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__92_carry_n_0\,
CO(3) => \add_temp_14__92_carry__0_n_0\,
CO(2) => \add_temp_14__92_carry__0_n_1\,
CO(1) => \add_temp_14__92_carry__0_n_2\,
CO(0) => \add_temp_14__92_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__92_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__92_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__92_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__92_carry__0_i_4_n_0\,
O(3) => \add_temp_14__92_carry__0_n_4\,
O(2) => \add_temp_14__92_carry__0_n_5\,
O(1) => \add_temp_14__92_carry__0_n_6\,
O(0) => \add_temp_14__92_carry__0_n_7\,
S(3) => \add_temp_14__92_carry__0_i_5_n_0\,
S(2) => \add_temp_14__92_carry__0_i_6_n_0\,
S(1) => \add_temp_14__92_carry__0_i_7_n_0\,
S(0) => \add_temp_14__92_carry__0_i_8_n_0\
);
\add_temp_14__92_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(6),
I1 => RESIZE34(6),
I2 => RESIZE30(6),
O => \add_temp_14__92_carry__0_i_1_n_0\
);
\add_temp_14__92_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(5),
I1 => RESIZE34(5),
I2 => RESIZE30(5),
O => \add_temp_14__92_carry__0_i_2_n_0\
);
\add_temp_14__92_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(4),
I1 => RESIZE34(4),
I2 => RESIZE30(4),
O => \add_temp_14__92_carry__0_i_3_n_0\
);
\add_temp_14__92_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(3),
I1 => RESIZE34(3),
I2 => RESIZE30(3),
O => \add_temp_14__92_carry__0_i_4_n_0\
);
\add_temp_14__92_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE34(7),
I1 => RESIZE30(7),
I2 => RESIZE32(7),
I3 => \add_temp_14__92_carry__0_i_1_n_0\,
O => \add_temp_14__92_carry__0_i_5_n_0\
);
\add_temp_14__92_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(6),
I1 => RESIZE34(6),
I2 => RESIZE30(6),
I3 => \add_temp_14__92_carry__0_i_2_n_0\,
O => \add_temp_14__92_carry__0_i_6_n_0\
);
\add_temp_14__92_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(5),
I1 => RESIZE34(5),
I2 => RESIZE30(5),
I3 => \add_temp_14__92_carry__0_i_3_n_0\,
O => \add_temp_14__92_carry__0_i_7_n_0\
);
\add_temp_14__92_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(4),
I1 => RESIZE34(4),
I2 => RESIZE30(4),
I3 => \add_temp_14__92_carry__0_i_4_n_0\,
O => \add_temp_14__92_carry__0_i_8_n_0\
);
\add_temp_14__92_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__92_carry__0_n_0\,
CO(3) => \add_temp_14__92_carry__1_n_0\,
CO(2) => \add_temp_14__92_carry__1_n_1\,
CO(1) => \add_temp_14__92_carry__1_n_2\,
CO(0) => \add_temp_14__92_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__92_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__92_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__92_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__92_carry__1_i_4_n_0\,
O(3) => \add_temp_14__92_carry__1_n_4\,
O(2) => \add_temp_14__92_carry__1_n_5\,
O(1) => \add_temp_14__92_carry__1_n_6\,
O(0) => \add_temp_14__92_carry__1_n_7\,
S(3) => \add_temp_14__92_carry__1_i_5_n_0\,
S(2) => \add_temp_14__92_carry__1_i_6_n_0\,
S(1) => \add_temp_14__92_carry__1_i_7_n_0\,
S(0) => \add_temp_14__92_carry__1_i_8_n_0\
);
\add_temp_14__92_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(10),
I1 => RESIZE32(10),
I2 => RESIZE34(10),
O => \add_temp_14__92_carry__1_i_1_n_0\
);
\add_temp_14__92_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(9),
I1 => RESIZE32(9),
I2 => RESIZE34(9),
O => \add_temp_14__92_carry__1_i_2_n_0\
);
\add_temp_14__92_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(8),
I1 => RESIZE32(8),
I2 => RESIZE34(8),
O => \add_temp_14__92_carry__1_i_3_n_0\
);
\add_temp_14__92_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE34(7),
I1 => RESIZE30(7),
I2 => RESIZE32(7),
O => \add_temp_14__92_carry__1_i_4_n_0\
);
\add_temp_14__92_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(11),
I1 => RESIZE32(11),
I2 => RESIZE34(11),
I3 => \add_temp_14__92_carry__1_i_1_n_0\,
O => \add_temp_14__92_carry__1_i_5_n_0\
);
\add_temp_14__92_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(10),
I1 => RESIZE32(10),
I2 => RESIZE34(10),
I3 => \add_temp_14__92_carry__1_i_2_n_0\,
O => \add_temp_14__92_carry__1_i_6_n_0\
);
\add_temp_14__92_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(9),
I1 => RESIZE32(9),
I2 => RESIZE34(9),
I3 => \add_temp_14__92_carry__1_i_3_n_0\,
O => \add_temp_14__92_carry__1_i_7_n_0\
);
\add_temp_14__92_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(8),
I1 => RESIZE32(8),
I2 => RESIZE34(8),
I3 => \add_temp_14__92_carry__1_i_4_n_0\,
O => \add_temp_14__92_carry__1_i_8_n_0\
);
\add_temp_14__92_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__92_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__92_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__92_carry__2_n_1\,
CO(1) => \add_temp_14__92_carry__2_n_2\,
CO(0) => \add_temp_14__92_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__92_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__92_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__92_carry__2_i_3_n_0\,
O(3) => \add_temp_14__92_carry__2_n_4\,
O(2) => \add_temp_14__92_carry__2_n_5\,
O(1) => \add_temp_14__92_carry__2_n_6\,
O(0) => \add_temp_14__92_carry__2_n_7\,
S(3) => \add_temp_14__92_carry__2_i_4_n_0\,
S(2) => \add_temp_14__92_carry__2_i_5_n_0\,
S(1) => \add_temp_14__92_carry__2_i_6_n_0\,
S(0) => \add_temp_14__92_carry__2_i_7_n_0\
);
\add_temp_14__92_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(13),
I1 => RESIZE32(13),
I2 => RESIZE34(13),
O => \add_temp_14__92_carry__2_i_1_n_0\
);
\add_temp_14__92_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(12),
I1 => RESIZE32(12),
I2 => RESIZE34(12),
O => \add_temp_14__92_carry__2_i_2_n_0\
);
\add_temp_14__92_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(11),
I1 => RESIZE32(11),
I2 => RESIZE34(11),
O => \add_temp_14__92_carry__2_i_3_n_0\
);
\add_temp_14__92_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE34(14),
I1 => RESIZE32(14),
I2 => RESIZE30(14),
I3 => RESIZE32(15),
I4 => RESIZE30(15),
I5 => RESIZE34(15),
O => \add_temp_14__92_carry__2_i_4_n_0\
);
\add_temp_14__92_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__92_carry__2_i_1_n_0\,
I1 => RESIZE32(14),
I2 => RESIZE30(14),
I3 => RESIZE34(14),
O => \add_temp_14__92_carry__2_i_5_n_0\
);
\add_temp_14__92_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(13),
I1 => RESIZE32(13),
I2 => RESIZE34(13),
I3 => \add_temp_14__92_carry__2_i_2_n_0\,
O => \add_temp_14__92_carry__2_i_6_n_0\
);
\add_temp_14__92_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(12),
I1 => RESIZE32(12),
I2 => RESIZE34(12),
I3 => \add_temp_14__92_carry__2_i_3_n_0\,
O => \add_temp_14__92_carry__2_i_7_n_0\
);
\add_temp_14__92_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(2),
I1 => RESIZE34(2),
I2 => RESIZE30(2),
O => \add_temp_14__92_carry_i_1_n_0\
);
\add_temp_14__92_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(1),
I1 => RESIZE34(1),
I2 => RESIZE30(1),
O => \add_temp_14__92_carry_i_2_n_0\
);
\add_temp_14__92_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(0),
I1 => RESIZE34(0),
I2 => RESIZE30(0),
O => \add_temp_14__92_carry_i_3_n_0\
);
\add_temp_14__92_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(3),
I1 => RESIZE34(3),
I2 => RESIZE30(3),
I3 => \add_temp_14__92_carry_i_1_n_0\,
O => \add_temp_14__92_carry_i_4_n_0\
);
\add_temp_14__92_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(2),
I1 => RESIZE34(2),
I2 => RESIZE30(2),
I3 => \add_temp_14__92_carry_i_2_n_0\,
O => \add_temp_14__92_carry_i_5_n_0\
);
\add_temp_14__92_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(1),
I1 => RESIZE34(1),
I2 => RESIZE30(1),
I3 => \add_temp_14__92_carry_i_3_n_0\,
O => \add_temp_14__92_carry_i_6_n_0\
);
\add_temp_14__92_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE32(0),
I1 => RESIZE34(0),
I2 => RESIZE30(0),
O => \add_temp_14__92_carry_i_7_n_0\
);
\data_pipeline_tmp_reg[0][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(0),
Q => \data_pipeline_tmp_reg[0]\(0)
);
\data_pipeline_tmp_reg[0][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(10),
Q => \data_pipeline_tmp_reg[0]\(10)
);
\data_pipeline_tmp_reg[0][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(11),
Q => \data_pipeline_tmp_reg[0]\(11)
);
\data_pipeline_tmp_reg[0][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(12),
Q => \data_pipeline_tmp_reg[0]\(12)
);
\data_pipeline_tmp_reg[0][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(13),
Q => \data_pipeline_tmp_reg[0]\(13)
);
\data_pipeline_tmp_reg[0][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(14),
Q => \data_pipeline_tmp_reg[0]\(14)
);
\data_pipeline_tmp_reg[0][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(15),
Q => \data_pipeline_tmp_reg[0]\(15)
);
\data_pipeline_tmp_reg[0][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(1),
Q => \data_pipeline_tmp_reg[0]\(1)
);
\data_pipeline_tmp_reg[0][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(2),
Q => \data_pipeline_tmp_reg[0]\(2)
);
\data_pipeline_tmp_reg[0][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(3),
Q => \data_pipeline_tmp_reg[0]\(3)
);
\data_pipeline_tmp_reg[0][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(4),
Q => \data_pipeline_tmp_reg[0]\(4)
);
\data_pipeline_tmp_reg[0][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(5),
Q => \data_pipeline_tmp_reg[0]\(5)
);
\data_pipeline_tmp_reg[0][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(6),
Q => \data_pipeline_tmp_reg[0]\(6)
);
\data_pipeline_tmp_reg[0][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(7),
Q => \data_pipeline_tmp_reg[0]\(7)
);
\data_pipeline_tmp_reg[0][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(8),
Q => \data_pipeline_tmp_reg[0]\(8)
);
\data_pipeline_tmp_reg[0][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(9),
Q => \data_pipeline_tmp_reg[0]\(9)
);
\data_pipeline_tmp_reg[10][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(0),
Q => \data_pipeline_tmp_reg[10]\(0)
);
\data_pipeline_tmp_reg[10][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(10),
Q => \data_pipeline_tmp_reg[10]\(10)
);
\data_pipeline_tmp_reg[10][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(11),
Q => \data_pipeline_tmp_reg[10]\(11)
);
\data_pipeline_tmp_reg[10][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(12),
Q => \data_pipeline_tmp_reg[10]\(12)
);
\data_pipeline_tmp_reg[10][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(13),
Q => \data_pipeline_tmp_reg[10]\(13)
);
\data_pipeline_tmp_reg[10][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(14),
Q => \data_pipeline_tmp_reg[10]\(14)
);
\data_pipeline_tmp_reg[10][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(15),
Q => \data_pipeline_tmp_reg[10]\(15)
);
\data_pipeline_tmp_reg[10][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(1),
Q => \data_pipeline_tmp_reg[10]\(1)
);
\data_pipeline_tmp_reg[10][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(2),
Q => \data_pipeline_tmp_reg[10]\(2)
);
\data_pipeline_tmp_reg[10][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(3),
Q => \data_pipeline_tmp_reg[10]\(3)
);
\data_pipeline_tmp_reg[10][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(4),
Q => \data_pipeline_tmp_reg[10]\(4)
);
\data_pipeline_tmp_reg[10][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(5),
Q => \data_pipeline_tmp_reg[10]\(5)
);
\data_pipeline_tmp_reg[10][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(6),
Q => \data_pipeline_tmp_reg[10]\(6)
);
\data_pipeline_tmp_reg[10][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(7),
Q => \data_pipeline_tmp_reg[10]\(7)
);
\data_pipeline_tmp_reg[10][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(8),
Q => \data_pipeline_tmp_reg[10]\(8)
);
\data_pipeline_tmp_reg[10][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(9),
Q => \data_pipeline_tmp_reg[10]\(9)
);
\data_pipeline_tmp_reg[11][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(0),
Q => \data_pipeline_tmp_reg[11]\(0)
);
\data_pipeline_tmp_reg[11][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(10),
Q => \data_pipeline_tmp_reg[11]\(10)
);
\data_pipeline_tmp_reg[11][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(11),
Q => \data_pipeline_tmp_reg[11]\(11)
);
\data_pipeline_tmp_reg[11][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(12),
Q => \data_pipeline_tmp_reg[11]\(12)
);
\data_pipeline_tmp_reg[11][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(13),
Q => \data_pipeline_tmp_reg[11]\(13)
);
\data_pipeline_tmp_reg[11][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(14),
Q => \data_pipeline_tmp_reg[11]\(14)
);
\data_pipeline_tmp_reg[11][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(15),
Q => \data_pipeline_tmp_reg[11]\(15)
);
\data_pipeline_tmp_reg[11][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(1),
Q => \data_pipeline_tmp_reg[11]\(1)
);
\data_pipeline_tmp_reg[11][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(2),
Q => \data_pipeline_tmp_reg[11]\(2)
);
\data_pipeline_tmp_reg[11][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(3),
Q => \data_pipeline_tmp_reg[11]\(3)
);
\data_pipeline_tmp_reg[11][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(4),
Q => \data_pipeline_tmp_reg[11]\(4)
);
\data_pipeline_tmp_reg[11][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(5),
Q => \data_pipeline_tmp_reg[11]\(5)
);
\data_pipeline_tmp_reg[11][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(6),
Q => \data_pipeline_tmp_reg[11]\(6)
);
\data_pipeline_tmp_reg[11][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(7),
Q => \data_pipeline_tmp_reg[11]\(7)
);
\data_pipeline_tmp_reg[11][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(8),
Q => \data_pipeline_tmp_reg[11]\(8)
);
\data_pipeline_tmp_reg[11][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(9),
Q => \data_pipeline_tmp_reg[11]\(9)
);
\data_pipeline_tmp_reg[12][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(0),
Q => \data_pipeline_tmp_reg[12]\(0)
);
\data_pipeline_tmp_reg[12][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(10),
Q => \data_pipeline_tmp_reg[12]\(10)
);
\data_pipeline_tmp_reg[12][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(11),
Q => \data_pipeline_tmp_reg[12]\(11)
);
\data_pipeline_tmp_reg[12][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(12),
Q => \data_pipeline_tmp_reg[12]\(12)
);
\data_pipeline_tmp_reg[12][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(13),
Q => \data_pipeline_tmp_reg[12]\(13)
);
\data_pipeline_tmp_reg[12][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(14),
Q => \data_pipeline_tmp_reg[12]\(14)
);
\data_pipeline_tmp_reg[12][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(15),
Q => \data_pipeline_tmp_reg[12]\(15)
);
\data_pipeline_tmp_reg[12][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(1),
Q => \data_pipeline_tmp_reg[12]\(1)
);
\data_pipeline_tmp_reg[12][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(2),
Q => \data_pipeline_tmp_reg[12]\(2)
);
\data_pipeline_tmp_reg[12][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(3),
Q => \data_pipeline_tmp_reg[12]\(3)
);
\data_pipeline_tmp_reg[12][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(4),
Q => \data_pipeline_tmp_reg[12]\(4)
);
\data_pipeline_tmp_reg[12][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(5),
Q => \data_pipeline_tmp_reg[12]\(5)
);
\data_pipeline_tmp_reg[12][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(6),
Q => \data_pipeline_tmp_reg[12]\(6)
);
\data_pipeline_tmp_reg[12][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(7),
Q => \data_pipeline_tmp_reg[12]\(7)
);
\data_pipeline_tmp_reg[12][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(8),
Q => \data_pipeline_tmp_reg[12]\(8)
);
\data_pipeline_tmp_reg[12][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(9),
Q => \data_pipeline_tmp_reg[12]\(9)
);
\data_pipeline_tmp_reg[13][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(0),
Q => \data_pipeline_tmp_reg[13]\(0)
);
\data_pipeline_tmp_reg[13][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(10),
Q => \data_pipeline_tmp_reg[13]\(10)
);
\data_pipeline_tmp_reg[13][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(11),
Q => \data_pipeline_tmp_reg[13]\(11)
);
\data_pipeline_tmp_reg[13][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(12),
Q => \data_pipeline_tmp_reg[13]\(12)
);
\data_pipeline_tmp_reg[13][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(13),
Q => \data_pipeline_tmp_reg[13]\(13)
);
\data_pipeline_tmp_reg[13][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(14),
Q => \data_pipeline_tmp_reg[13]\(14)
);
\data_pipeline_tmp_reg[13][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(15),
Q => \data_pipeline_tmp_reg[13]\(15)
);
\data_pipeline_tmp_reg[13][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(1),
Q => \data_pipeline_tmp_reg[13]\(1)
);
\data_pipeline_tmp_reg[13][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(2),
Q => \data_pipeline_tmp_reg[13]\(2)
);
\data_pipeline_tmp_reg[13][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(3),
Q => \data_pipeline_tmp_reg[13]\(3)
);
\data_pipeline_tmp_reg[13][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(4),
Q => \data_pipeline_tmp_reg[13]\(4)
);
\data_pipeline_tmp_reg[13][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(5),
Q => \data_pipeline_tmp_reg[13]\(5)
);
\data_pipeline_tmp_reg[13][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(6),
Q => \data_pipeline_tmp_reg[13]\(6)
);
\data_pipeline_tmp_reg[13][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(7),
Q => \data_pipeline_tmp_reg[13]\(7)
);
\data_pipeline_tmp_reg[13][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(8),
Q => \data_pipeline_tmp_reg[13]\(8)
);
\data_pipeline_tmp_reg[13][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(9),
Q => \data_pipeline_tmp_reg[13]\(9)
);
\data_pipeline_tmp_reg[14][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(0),
Q => \data_pipeline_tmp_reg[14]\(0)
);
\data_pipeline_tmp_reg[14][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(10),
Q => \data_pipeline_tmp_reg[14]\(10)
);
\data_pipeline_tmp_reg[14][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(11),
Q => \data_pipeline_tmp_reg[14]\(11)
);
\data_pipeline_tmp_reg[14][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(12),
Q => \data_pipeline_tmp_reg[14]\(12)
);
\data_pipeline_tmp_reg[14][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(13),
Q => \data_pipeline_tmp_reg[14]\(13)
);
\data_pipeline_tmp_reg[14][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(14),
Q => \data_pipeline_tmp_reg[14]\(14)
);
\data_pipeline_tmp_reg[14][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(15),
Q => \data_pipeline_tmp_reg[14]\(15)
);
\data_pipeline_tmp_reg[14][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(1),
Q => \data_pipeline_tmp_reg[14]\(1)
);
\data_pipeline_tmp_reg[14][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(2),
Q => \data_pipeline_tmp_reg[14]\(2)
);
\data_pipeline_tmp_reg[14][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(3),
Q => \data_pipeline_tmp_reg[14]\(3)
);
\data_pipeline_tmp_reg[14][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(4),
Q => \data_pipeline_tmp_reg[14]\(4)
);
\data_pipeline_tmp_reg[14][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(5),
Q => \data_pipeline_tmp_reg[14]\(5)
);
\data_pipeline_tmp_reg[14][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(6),
Q => \data_pipeline_tmp_reg[14]\(6)
);
\data_pipeline_tmp_reg[14][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(7),
Q => \data_pipeline_tmp_reg[14]\(7)
);
\data_pipeline_tmp_reg[14][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(8),
Q => \data_pipeline_tmp_reg[14]\(8)
);
\data_pipeline_tmp_reg[14][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(9),
Q => \data_pipeline_tmp_reg[14]\(9)
);
\data_pipeline_tmp_reg[1][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(0),
Q => \data_pipeline_tmp_reg[1]\(0)
);
\data_pipeline_tmp_reg[1][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(10),
Q => \data_pipeline_tmp_reg[1]\(10)
);
\data_pipeline_tmp_reg[1][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(11),
Q => \data_pipeline_tmp_reg[1]\(11)
);
\data_pipeline_tmp_reg[1][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(12),
Q => \data_pipeline_tmp_reg[1]\(12)
);
\data_pipeline_tmp_reg[1][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(13),
Q => \data_pipeline_tmp_reg[1]\(13)
);
\data_pipeline_tmp_reg[1][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(14),
Q => \data_pipeline_tmp_reg[1]\(14)
);
\data_pipeline_tmp_reg[1][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(15),
Q => \data_pipeline_tmp_reg[1]\(15)
);
\data_pipeline_tmp_reg[1][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(1),
Q => \data_pipeline_tmp_reg[1]\(1)
);
\data_pipeline_tmp_reg[1][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(2),
Q => \data_pipeline_tmp_reg[1]\(2)
);
\data_pipeline_tmp_reg[1][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(3),
Q => \data_pipeline_tmp_reg[1]\(3)
);
\data_pipeline_tmp_reg[1][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(4),
Q => \data_pipeline_tmp_reg[1]\(4)
);
\data_pipeline_tmp_reg[1][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(5),
Q => \data_pipeline_tmp_reg[1]\(5)
);
\data_pipeline_tmp_reg[1][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(6),
Q => \data_pipeline_tmp_reg[1]\(6)
);
\data_pipeline_tmp_reg[1][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(7),
Q => \data_pipeline_tmp_reg[1]\(7)
);
\data_pipeline_tmp_reg[1][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(8),
Q => \data_pipeline_tmp_reg[1]\(8)
);
\data_pipeline_tmp_reg[1][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(9),
Q => \data_pipeline_tmp_reg[1]\(9)
);
\data_pipeline_tmp_reg[2][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(0),
Q => \data_pipeline_tmp_reg[2]\(0)
);
\data_pipeline_tmp_reg[2][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(10),
Q => \data_pipeline_tmp_reg[2]\(10)
);
\data_pipeline_tmp_reg[2][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(11),
Q => \data_pipeline_tmp_reg[2]\(11)
);
\data_pipeline_tmp_reg[2][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(12),
Q => \data_pipeline_tmp_reg[2]\(12)
);
\data_pipeline_tmp_reg[2][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(13),
Q => \data_pipeline_tmp_reg[2]\(13)
);
\data_pipeline_tmp_reg[2][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(14),
Q => \data_pipeline_tmp_reg[2]\(14)
);
\data_pipeline_tmp_reg[2][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(15),
Q => \data_pipeline_tmp_reg[2]\(15)
);
\data_pipeline_tmp_reg[2][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(1),
Q => \data_pipeline_tmp_reg[2]\(1)
);
\data_pipeline_tmp_reg[2][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(2),
Q => \data_pipeline_tmp_reg[2]\(2)
);
\data_pipeline_tmp_reg[2][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(3),
Q => \data_pipeline_tmp_reg[2]\(3)
);
\data_pipeline_tmp_reg[2][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(4),
Q => \data_pipeline_tmp_reg[2]\(4)
);
\data_pipeline_tmp_reg[2][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(5),
Q => \data_pipeline_tmp_reg[2]\(5)
);
\data_pipeline_tmp_reg[2][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(6),
Q => \data_pipeline_tmp_reg[2]\(6)
);
\data_pipeline_tmp_reg[2][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(7),
Q => \data_pipeline_tmp_reg[2]\(7)
);
\data_pipeline_tmp_reg[2][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(8),
Q => \data_pipeline_tmp_reg[2]\(8)
);
\data_pipeline_tmp_reg[2][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(9),
Q => \data_pipeline_tmp_reg[2]\(9)
);
\data_pipeline_tmp_reg[3][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(0),
Q => \data_pipeline_tmp_reg[3]\(0)
);
\data_pipeline_tmp_reg[3][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(10),
Q => \data_pipeline_tmp_reg[3]\(10)
);
\data_pipeline_tmp_reg[3][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(11),
Q => \data_pipeline_tmp_reg[3]\(11)
);
\data_pipeline_tmp_reg[3][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(12),
Q => \data_pipeline_tmp_reg[3]\(12)
);
\data_pipeline_tmp_reg[3][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(13),
Q => \data_pipeline_tmp_reg[3]\(13)
);
\data_pipeline_tmp_reg[3][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(14),
Q => \data_pipeline_tmp_reg[3]\(14)
);
\data_pipeline_tmp_reg[3][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(15),
Q => \data_pipeline_tmp_reg[3]\(15)
);
\data_pipeline_tmp_reg[3][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(1),
Q => \data_pipeline_tmp_reg[3]\(1)
);
\data_pipeline_tmp_reg[3][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(2),
Q => \data_pipeline_tmp_reg[3]\(2)
);
\data_pipeline_tmp_reg[3][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(3),
Q => \data_pipeline_tmp_reg[3]\(3)
);
\data_pipeline_tmp_reg[3][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(4),
Q => \data_pipeline_tmp_reg[3]\(4)
);
\data_pipeline_tmp_reg[3][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(5),
Q => \data_pipeline_tmp_reg[3]\(5)
);
\data_pipeline_tmp_reg[3][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(6),
Q => \data_pipeline_tmp_reg[3]\(6)
);
\data_pipeline_tmp_reg[3][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(7),
Q => \data_pipeline_tmp_reg[3]\(7)
);
\data_pipeline_tmp_reg[3][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(8),
Q => \data_pipeline_tmp_reg[3]\(8)
);
\data_pipeline_tmp_reg[3][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(9),
Q => \data_pipeline_tmp_reg[3]\(9)
);
\data_pipeline_tmp_reg[4][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(0),
Q => \data_pipeline_tmp_reg[4]\(0)
);
\data_pipeline_tmp_reg[4][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(10),
Q => \data_pipeline_tmp_reg[4]\(10)
);
\data_pipeline_tmp_reg[4][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(11),
Q => \data_pipeline_tmp_reg[4]\(11)
);
\data_pipeline_tmp_reg[4][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(12),
Q => \data_pipeline_tmp_reg[4]\(12)
);
\data_pipeline_tmp_reg[4][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(13),
Q => \data_pipeline_tmp_reg[4]\(13)
);
\data_pipeline_tmp_reg[4][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(14),
Q => \data_pipeline_tmp_reg[4]\(14)
);
\data_pipeline_tmp_reg[4][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(15),
Q => \data_pipeline_tmp_reg[4]\(15)
);
\data_pipeline_tmp_reg[4][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(1),
Q => \data_pipeline_tmp_reg[4]\(1)
);
\data_pipeline_tmp_reg[4][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(2),
Q => \data_pipeline_tmp_reg[4]\(2)
);
\data_pipeline_tmp_reg[4][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(3),
Q => \data_pipeline_tmp_reg[4]\(3)
);
\data_pipeline_tmp_reg[4][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(4),
Q => \data_pipeline_tmp_reg[4]\(4)
);
\data_pipeline_tmp_reg[4][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(5),
Q => \data_pipeline_tmp_reg[4]\(5)
);
\data_pipeline_tmp_reg[4][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(6),
Q => \data_pipeline_tmp_reg[4]\(6)
);
\data_pipeline_tmp_reg[4][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(7),
Q => \data_pipeline_tmp_reg[4]\(7)
);
\data_pipeline_tmp_reg[4][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(8),
Q => \data_pipeline_tmp_reg[4]\(8)
);
\data_pipeline_tmp_reg[4][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(9),
Q => \data_pipeline_tmp_reg[4]\(9)
);
\data_pipeline_tmp_reg[5][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(0),
Q => \data_pipeline_tmp_reg[5]\(0)
);
\data_pipeline_tmp_reg[5][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(10),
Q => \data_pipeline_tmp_reg[5]\(10)
);
\data_pipeline_tmp_reg[5][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(11),
Q => \data_pipeline_tmp_reg[5]\(11)
);
\data_pipeline_tmp_reg[5][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(12),
Q => \data_pipeline_tmp_reg[5]\(12)
);
\data_pipeline_tmp_reg[5][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(13),
Q => \data_pipeline_tmp_reg[5]\(13)
);
\data_pipeline_tmp_reg[5][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(14),
Q => \data_pipeline_tmp_reg[5]\(14)
);
\data_pipeline_tmp_reg[5][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(15),
Q => \data_pipeline_tmp_reg[5]\(15)
);
\data_pipeline_tmp_reg[5][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(1),
Q => \data_pipeline_tmp_reg[5]\(1)
);
\data_pipeline_tmp_reg[5][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(2),
Q => \data_pipeline_tmp_reg[5]\(2)
);
\data_pipeline_tmp_reg[5][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(3),
Q => \data_pipeline_tmp_reg[5]\(3)
);
\data_pipeline_tmp_reg[5][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(4),
Q => \data_pipeline_tmp_reg[5]\(4)
);
\data_pipeline_tmp_reg[5][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(5),
Q => \data_pipeline_tmp_reg[5]\(5)
);
\data_pipeline_tmp_reg[5][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(6),
Q => \data_pipeline_tmp_reg[5]\(6)
);
\data_pipeline_tmp_reg[5][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(7),
Q => \data_pipeline_tmp_reg[5]\(7)
);
\data_pipeline_tmp_reg[5][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(8),
Q => \data_pipeline_tmp_reg[5]\(8)
);
\data_pipeline_tmp_reg[5][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(9),
Q => \data_pipeline_tmp_reg[5]\(9)
);
\data_pipeline_tmp_reg[6][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(0),
Q => \data_pipeline_tmp_reg[6]\(0)
);
\data_pipeline_tmp_reg[6][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(10),
Q => \data_pipeline_tmp_reg[6]\(10)
);
\data_pipeline_tmp_reg[6][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(11),
Q => \data_pipeline_tmp_reg[6]\(11)
);
\data_pipeline_tmp_reg[6][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(12),
Q => \data_pipeline_tmp_reg[6]\(12)
);
\data_pipeline_tmp_reg[6][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(13),
Q => \data_pipeline_tmp_reg[6]\(13)
);
\data_pipeline_tmp_reg[6][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(14),
Q => \data_pipeline_tmp_reg[6]\(14)
);
\data_pipeline_tmp_reg[6][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(15),
Q => \data_pipeline_tmp_reg[6]\(15)
);
\data_pipeline_tmp_reg[6][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(1),
Q => \data_pipeline_tmp_reg[6]\(1)
);
\data_pipeline_tmp_reg[6][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(2),
Q => \data_pipeline_tmp_reg[6]\(2)
);
\data_pipeline_tmp_reg[6][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(3),
Q => \data_pipeline_tmp_reg[6]\(3)
);
\data_pipeline_tmp_reg[6][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(4),
Q => \data_pipeline_tmp_reg[6]\(4)
);
\data_pipeline_tmp_reg[6][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(5),
Q => \data_pipeline_tmp_reg[6]\(5)
);
\data_pipeline_tmp_reg[6][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(6),
Q => \data_pipeline_tmp_reg[6]\(6)
);
\data_pipeline_tmp_reg[6][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(7),
Q => \data_pipeline_tmp_reg[6]\(7)
);
\data_pipeline_tmp_reg[6][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(8),
Q => \data_pipeline_tmp_reg[6]\(8)
);
\data_pipeline_tmp_reg[6][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(9),
Q => \data_pipeline_tmp_reg[6]\(9)
);
\data_pipeline_tmp_reg[7][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(0),
Q => \data_pipeline_tmp_reg[7]\(0)
);
\data_pipeline_tmp_reg[7][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(10),
Q => \data_pipeline_tmp_reg[7]\(10)
);
\data_pipeline_tmp_reg[7][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(11),
Q => \data_pipeline_tmp_reg[7]\(11)
);
\data_pipeline_tmp_reg[7][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(12),
Q => \data_pipeline_tmp_reg[7]\(12)
);
\data_pipeline_tmp_reg[7][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(13),
Q => \data_pipeline_tmp_reg[7]\(13)
);
\data_pipeline_tmp_reg[7][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(14),
Q => \data_pipeline_tmp_reg[7]\(14)
);
\data_pipeline_tmp_reg[7][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(15),
Q => \data_pipeline_tmp_reg[7]\(15)
);
\data_pipeline_tmp_reg[7][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(1),
Q => \data_pipeline_tmp_reg[7]\(1)
);
\data_pipeline_tmp_reg[7][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(2),
Q => \data_pipeline_tmp_reg[7]\(2)
);
\data_pipeline_tmp_reg[7][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(3),
Q => \data_pipeline_tmp_reg[7]\(3)
);
\data_pipeline_tmp_reg[7][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(4),
Q => \data_pipeline_tmp_reg[7]\(4)
);
\data_pipeline_tmp_reg[7][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(5),
Q => \data_pipeline_tmp_reg[7]\(5)
);
\data_pipeline_tmp_reg[7][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(6),
Q => \data_pipeline_tmp_reg[7]\(6)
);
\data_pipeline_tmp_reg[7][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(7),
Q => \data_pipeline_tmp_reg[7]\(7)
);
\data_pipeline_tmp_reg[7][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(8),
Q => \data_pipeline_tmp_reg[7]\(8)
);
\data_pipeline_tmp_reg[7][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(9),
Q => \data_pipeline_tmp_reg[7]\(9)
);
\data_pipeline_tmp_reg[8][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(0),
Q => \data_pipeline_tmp_reg[8]\(0)
);
\data_pipeline_tmp_reg[8][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(10),
Q => \data_pipeline_tmp_reg[8]\(10)
);
\data_pipeline_tmp_reg[8][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(11),
Q => \data_pipeline_tmp_reg[8]\(11)
);
\data_pipeline_tmp_reg[8][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(12),
Q => \data_pipeline_tmp_reg[8]\(12)
);
\data_pipeline_tmp_reg[8][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(13),
Q => \data_pipeline_tmp_reg[8]\(13)
);
\data_pipeline_tmp_reg[8][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(14),
Q => \data_pipeline_tmp_reg[8]\(14)
);
\data_pipeline_tmp_reg[8][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(15),
Q => \data_pipeline_tmp_reg[8]\(15)
);
\data_pipeline_tmp_reg[8][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(1),
Q => \data_pipeline_tmp_reg[8]\(1)
);
\data_pipeline_tmp_reg[8][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(2),
Q => \data_pipeline_tmp_reg[8]\(2)
);
\data_pipeline_tmp_reg[8][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(3),
Q => \data_pipeline_tmp_reg[8]\(3)
);
\data_pipeline_tmp_reg[8][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(4),
Q => \data_pipeline_tmp_reg[8]\(4)
);
\data_pipeline_tmp_reg[8][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(5),
Q => \data_pipeline_tmp_reg[8]\(5)
);
\data_pipeline_tmp_reg[8][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(6),
Q => \data_pipeline_tmp_reg[8]\(6)
);
\data_pipeline_tmp_reg[8][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(7),
Q => \data_pipeline_tmp_reg[8]\(7)
);
\data_pipeline_tmp_reg[8][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(8),
Q => \data_pipeline_tmp_reg[8]\(8)
);
\data_pipeline_tmp_reg[8][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(9),
Q => \data_pipeline_tmp_reg[8]\(9)
);
\data_pipeline_tmp_reg[9][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(0),
Q => \data_pipeline_tmp_reg[9]\(0)
);
\data_pipeline_tmp_reg[9][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(10),
Q => \data_pipeline_tmp_reg[9]\(10)
);
\data_pipeline_tmp_reg[9][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(11),
Q => \data_pipeline_tmp_reg[9]\(11)
);
\data_pipeline_tmp_reg[9][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(12),
Q => \data_pipeline_tmp_reg[9]\(12)
);
\data_pipeline_tmp_reg[9][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(13),
Q => \data_pipeline_tmp_reg[9]\(13)
);
\data_pipeline_tmp_reg[9][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(14),
Q => \data_pipeline_tmp_reg[9]\(14)
);
\data_pipeline_tmp_reg[9][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(15),
Q => \data_pipeline_tmp_reg[9]\(15)
);
\data_pipeline_tmp_reg[9][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(1),
Q => \data_pipeline_tmp_reg[9]\(1)
);
\data_pipeline_tmp_reg[9][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(2),
Q => \data_pipeline_tmp_reg[9]\(2)
);
\data_pipeline_tmp_reg[9][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(3),
Q => \data_pipeline_tmp_reg[9]\(3)
);
\data_pipeline_tmp_reg[9][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(4),
Q => \data_pipeline_tmp_reg[9]\(4)
);
\data_pipeline_tmp_reg[9][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(5),
Q => \data_pipeline_tmp_reg[9]\(5)
);
\data_pipeline_tmp_reg[9][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(6),
Q => \data_pipeline_tmp_reg[9]\(6)
);
\data_pipeline_tmp_reg[9][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(7),
Q => \data_pipeline_tmp_reg[9]\(7)
);
\data_pipeline_tmp_reg[9][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(8),
Q => \data_pipeline_tmp_reg[9]\(8)
);
\data_pipeline_tmp_reg[9][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(9),
Q => \data_pipeline_tmp_reg[9]\(9)
);
mul_temp: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[0]\(15),
A(28) => \data_pipeline_tmp_reg[0]\(15),
A(27) => \data_pipeline_tmp_reg[0]\(15),
A(26) => \data_pipeline_tmp_reg[0]\(15),
A(25) => \data_pipeline_tmp_reg[0]\(15),
A(24) => \data_pipeline_tmp_reg[0]\(15),
A(23) => \data_pipeline_tmp_reg[0]\(15),
A(22) => \data_pipeline_tmp_reg[0]\(15),
A(21) => \data_pipeline_tmp_reg[0]\(15),
A(20) => \data_pipeline_tmp_reg[0]\(15),
A(19) => \data_pipeline_tmp_reg[0]\(15),
A(18) => \data_pipeline_tmp_reg[0]\(15),
A(17) => \data_pipeline_tmp_reg[0]\(15),
A(16) => \data_pipeline_tmp_reg[0]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[0]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[0]_15\(15),
B(16) => \weight_reg[0]_15\(15),
B(15 downto 0) => \weight_reg[0]_15\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_n_74,
P(30) => mul_temp_n_75,
P(29) => mul_temp_n_76,
P(28) => mul_temp_n_77,
P(27) => mul_temp_n_78,
P(26) => mul_temp_n_79,
P(25) => mul_temp_n_80,
P(24) => mul_temp_n_81,
P(23) => mul_temp_n_82,
P(22) => mul_temp_n_83,
P(21) => mul_temp_n_84,
P(20) => mul_temp_n_85,
P(19) => mul_temp_n_86,
P(18) => mul_temp_n_87,
P(17) => mul_temp_n_88,
P(16) => mul_temp_n_89,
P(15) => mul_temp_n_90,
P(14) => \^mul_temp\(14),
P(13) => mul_temp_n_92,
P(12) => mul_temp_n_93,
P(11) => mul_temp_n_94,
P(10) => mul_temp_n_95,
P(9) => mul_temp_n_96,
P(8) => mul_temp_n_97,
P(7) => mul_temp_n_98,
P(6) => mul_temp_n_99,
P(5) => mul_temp_n_100,
P(4) => mul_temp_n_101,
P(3) => mul_temp_n_102,
P(2) => mul_temp_n_103,
P(1) => mul_temp_n_104,
P(0) => mul_temp_n_105,
PATTERNBDETECT => NLW_mul_temp_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_UNDERFLOW_UNCONNECTED
);
mul_temp_1: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[1]\(15),
A(28) => \data_pipeline_tmp_reg[1]\(15),
A(27) => \data_pipeline_tmp_reg[1]\(15),
A(26) => \data_pipeline_tmp_reg[1]\(15),
A(25) => \data_pipeline_tmp_reg[1]\(15),
A(24) => \data_pipeline_tmp_reg[1]\(15),
A(23) => \data_pipeline_tmp_reg[1]\(15),
A(22) => \data_pipeline_tmp_reg[1]\(15),
A(21) => \data_pipeline_tmp_reg[1]\(15),
A(20) => \data_pipeline_tmp_reg[1]\(15),
A(19) => \data_pipeline_tmp_reg[1]\(15),
A(18) => \data_pipeline_tmp_reg[1]\(15),
A(17) => \data_pipeline_tmp_reg[1]\(15),
A(16) => \data_pipeline_tmp_reg[1]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[1]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_1_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[1]_0\(15),
B(16) => \weight_reg[1]_0\(15),
B(15 downto 0) => \weight_reg[1]_0\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_1_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_1_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_1_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_1_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_1_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_1_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_1_n_74,
P(30) => mul_temp_1_n_75,
P(29) => mul_temp_1_n_76,
P(28) => mul_temp_1_n_77,
P(27) => mul_temp_1_n_78,
P(26) => mul_temp_1_n_79,
P(25) => mul_temp_1_n_80,
P(24) => mul_temp_1_n_81,
P(23) => mul_temp_1_n_82,
P(22) => mul_temp_1_n_83,
P(21) => mul_temp_1_n_84,
P(20) => mul_temp_1_n_85,
P(19) => mul_temp_1_n_86,
P(18) => mul_temp_1_n_87,
P(17) => mul_temp_1_n_88,
P(16) => mul_temp_1_n_89,
P(15) => mul_temp_1_n_90,
P(14) => \^mul_temp_1\(14),
P(13) => mul_temp_1_n_92,
P(12) => mul_temp_1_n_93,
P(11) => mul_temp_1_n_94,
P(10) => mul_temp_1_n_95,
P(9) => mul_temp_1_n_96,
P(8) => mul_temp_1_n_97,
P(7) => mul_temp_1_n_98,
P(6) => mul_temp_1_n_99,
P(5) => mul_temp_1_n_100,
P(4) => mul_temp_1_n_101,
P(3) => mul_temp_1_n_102,
P(2) => mul_temp_1_n_103,
P(1) => mul_temp_1_n_104,
P(0) => mul_temp_1_n_105,
PATTERNBDETECT => NLW_mul_temp_1_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_1_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_1_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_1_UNDERFLOW_UNCONNECTED
);
mul_temp_10: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[10]\(15),
A(28) => \data_pipeline_tmp_reg[10]\(15),
A(27) => \data_pipeline_tmp_reg[10]\(15),
A(26) => \data_pipeline_tmp_reg[10]\(15),
A(25) => \data_pipeline_tmp_reg[10]\(15),
A(24) => \data_pipeline_tmp_reg[10]\(15),
A(23) => \data_pipeline_tmp_reg[10]\(15),
A(22) => \data_pipeline_tmp_reg[10]\(15),
A(21) => \data_pipeline_tmp_reg[10]\(15),
A(20) => \data_pipeline_tmp_reg[10]\(15),
A(19) => \data_pipeline_tmp_reg[10]\(15),
A(18) => \data_pipeline_tmp_reg[10]\(15),
A(17) => \data_pipeline_tmp_reg[10]\(15),
A(16) => \data_pipeline_tmp_reg[10]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[10]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_10_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[10]_9\(15),
B(16) => \weight_reg[10]_9\(15),
B(15 downto 0) => \weight_reg[10]_9\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_10_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_10_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_10_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_10_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_10_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_10_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_10_n_74,
P(30) => mul_temp_10_n_75,
P(29) => mul_temp_10_n_76,
P(28) => mul_temp_10_n_77,
P(27) => mul_temp_10_n_78,
P(26) => mul_temp_10_n_79,
P(25) => mul_temp_10_n_80,
P(24) => mul_temp_10_n_81,
P(23) => mul_temp_10_n_82,
P(22) => mul_temp_10_n_83,
P(21) => mul_temp_10_n_84,
P(20) => mul_temp_10_n_85,
P(19) => mul_temp_10_n_86,
P(18) => mul_temp_10_n_87,
P(17) => mul_temp_10_n_88,
P(16) => mul_temp_10_n_89,
P(15) => mul_temp_10_n_90,
P(14) => \^mul_temp_10\(14),
P(13) => mul_temp_10_n_92,
P(12) => mul_temp_10_n_93,
P(11) => mul_temp_10_n_94,
P(10) => mul_temp_10_n_95,
P(9) => mul_temp_10_n_96,
P(8) => mul_temp_10_n_97,
P(7) => mul_temp_10_n_98,
P(6) => mul_temp_10_n_99,
P(5) => mul_temp_10_n_100,
P(4) => mul_temp_10_n_101,
P(3) => mul_temp_10_n_102,
P(2) => mul_temp_10_n_103,
P(1) => mul_temp_10_n_104,
P(0) => mul_temp_10_n_105,
PATTERNBDETECT => NLW_mul_temp_10_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_10_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_10_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_10_UNDERFLOW_UNCONNECTED
);
mul_temp_11: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[11]\(15),
A(28) => \data_pipeline_tmp_reg[11]\(15),
A(27) => \data_pipeline_tmp_reg[11]\(15),
A(26) => \data_pipeline_tmp_reg[11]\(15),
A(25) => \data_pipeline_tmp_reg[11]\(15),
A(24) => \data_pipeline_tmp_reg[11]\(15),
A(23) => \data_pipeline_tmp_reg[11]\(15),
A(22) => \data_pipeline_tmp_reg[11]\(15),
A(21) => \data_pipeline_tmp_reg[11]\(15),
A(20) => \data_pipeline_tmp_reg[11]\(15),
A(19) => \data_pipeline_tmp_reg[11]\(15),
A(18) => \data_pipeline_tmp_reg[11]\(15),
A(17) => \data_pipeline_tmp_reg[11]\(15),
A(16) => \data_pipeline_tmp_reg[11]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[11]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_11_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[11]_10\(15),
B(16) => \weight_reg[11]_10\(15),
B(15 downto 0) => \weight_reg[11]_10\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_11_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_11_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_11_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_11_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_11_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_11_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_11_n_74,
P(30) => mul_temp_11_n_75,
P(29) => mul_temp_11_n_76,
P(28) => mul_temp_11_n_77,
P(27) => mul_temp_11_n_78,
P(26) => mul_temp_11_n_79,
P(25) => mul_temp_11_n_80,
P(24) => mul_temp_11_n_81,
P(23) => mul_temp_11_n_82,
P(22) => mul_temp_11_n_83,
P(21) => mul_temp_11_n_84,
P(20) => mul_temp_11_n_85,
P(19) => mul_temp_11_n_86,
P(18) => mul_temp_11_n_87,
P(17) => mul_temp_11_n_88,
P(16) => mul_temp_11_n_89,
P(15) => mul_temp_11_n_90,
P(14) => \^mul_temp_11\(14),
P(13) => mul_temp_11_n_92,
P(12) => mul_temp_11_n_93,
P(11) => mul_temp_11_n_94,
P(10) => mul_temp_11_n_95,
P(9) => mul_temp_11_n_96,
P(8) => mul_temp_11_n_97,
P(7) => mul_temp_11_n_98,
P(6) => mul_temp_11_n_99,
P(5) => mul_temp_11_n_100,
P(4) => mul_temp_11_n_101,
P(3) => mul_temp_11_n_102,
P(2) => mul_temp_11_n_103,
P(1) => mul_temp_11_n_104,
P(0) => mul_temp_11_n_105,
PATTERNBDETECT => NLW_mul_temp_11_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_11_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_11_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_11_UNDERFLOW_UNCONNECTED
);
mul_temp_12: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[12]\(15),
A(28) => \data_pipeline_tmp_reg[12]\(15),
A(27) => \data_pipeline_tmp_reg[12]\(15),
A(26) => \data_pipeline_tmp_reg[12]\(15),
A(25) => \data_pipeline_tmp_reg[12]\(15),
A(24) => \data_pipeline_tmp_reg[12]\(15),
A(23) => \data_pipeline_tmp_reg[12]\(15),
A(22) => \data_pipeline_tmp_reg[12]\(15),
A(21) => \data_pipeline_tmp_reg[12]\(15),
A(20) => \data_pipeline_tmp_reg[12]\(15),
A(19) => \data_pipeline_tmp_reg[12]\(15),
A(18) => \data_pipeline_tmp_reg[12]\(15),
A(17) => \data_pipeline_tmp_reg[12]\(15),
A(16) => \data_pipeline_tmp_reg[12]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[12]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_12_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[12]_11\(15),
B(16) => \weight_reg[12]_11\(15),
B(15 downto 0) => \weight_reg[12]_11\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_12_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_12_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_12_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_12_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_12_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_12_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_12_n_74,
P(30) => mul_temp_12_n_75,
P(29) => mul_temp_12_n_76,
P(28) => mul_temp_12_n_77,
P(27) => mul_temp_12_n_78,
P(26) => mul_temp_12_n_79,
P(25) => mul_temp_12_n_80,
P(24) => mul_temp_12_n_81,
P(23) => mul_temp_12_n_82,
P(22) => mul_temp_12_n_83,
P(21) => mul_temp_12_n_84,
P(20) => mul_temp_12_n_85,
P(19) => mul_temp_12_n_86,
P(18) => mul_temp_12_n_87,
P(17) => mul_temp_12_n_88,
P(16) => mul_temp_12_n_89,
P(15) => mul_temp_12_n_90,
P(14) => \^mul_temp_12\(14),
P(13) => mul_temp_12_n_92,
P(12) => mul_temp_12_n_93,
P(11) => mul_temp_12_n_94,
P(10) => mul_temp_12_n_95,
P(9) => mul_temp_12_n_96,
P(8) => mul_temp_12_n_97,
P(7) => mul_temp_12_n_98,
P(6) => mul_temp_12_n_99,
P(5) => mul_temp_12_n_100,
P(4) => mul_temp_12_n_101,
P(3) => mul_temp_12_n_102,
P(2) => mul_temp_12_n_103,
P(1) => mul_temp_12_n_104,
P(0) => mul_temp_12_n_105,
PATTERNBDETECT => NLW_mul_temp_12_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_12_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_12_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_12_UNDERFLOW_UNCONNECTED
);
mul_temp_13: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[13]\(15),
A(28) => \data_pipeline_tmp_reg[13]\(15),
A(27) => \data_pipeline_tmp_reg[13]\(15),
A(26) => \data_pipeline_tmp_reg[13]\(15),
A(25) => \data_pipeline_tmp_reg[13]\(15),
A(24) => \data_pipeline_tmp_reg[13]\(15),
A(23) => \data_pipeline_tmp_reg[13]\(15),
A(22) => \data_pipeline_tmp_reg[13]\(15),
A(21) => \data_pipeline_tmp_reg[13]\(15),
A(20) => \data_pipeline_tmp_reg[13]\(15),
A(19) => \data_pipeline_tmp_reg[13]\(15),
A(18) => \data_pipeline_tmp_reg[13]\(15),
A(17) => \data_pipeline_tmp_reg[13]\(15),
A(16) => \data_pipeline_tmp_reg[13]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[13]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_13_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[13]_12\(15),
B(16) => \weight_reg[13]_12\(15),
B(15 downto 0) => \weight_reg[13]_12\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_13_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_13_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_13_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_13_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_13_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_13_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_13_n_74,
P(30) => mul_temp_13_n_75,
P(29) => mul_temp_13_n_76,
P(28) => mul_temp_13_n_77,
P(27) => mul_temp_13_n_78,
P(26) => mul_temp_13_n_79,
P(25) => mul_temp_13_n_80,
P(24) => mul_temp_13_n_81,
P(23) => mul_temp_13_n_82,
P(22) => mul_temp_13_n_83,
P(21) => mul_temp_13_n_84,
P(20) => mul_temp_13_n_85,
P(19) => mul_temp_13_n_86,
P(18) => mul_temp_13_n_87,
P(17) => mul_temp_13_n_88,
P(16) => mul_temp_13_n_89,
P(15) => mul_temp_13_n_90,
P(14) => \^mul_temp_13\(14),
P(13) => mul_temp_13_n_92,
P(12) => mul_temp_13_n_93,
P(11) => mul_temp_13_n_94,
P(10) => mul_temp_13_n_95,
P(9) => mul_temp_13_n_96,
P(8) => mul_temp_13_n_97,
P(7) => mul_temp_13_n_98,
P(6) => mul_temp_13_n_99,
P(5) => mul_temp_13_n_100,
P(4) => mul_temp_13_n_101,
P(3) => mul_temp_13_n_102,
P(2) => mul_temp_13_n_103,
P(1) => mul_temp_13_n_104,
P(0) => mul_temp_13_n_105,
PATTERNBDETECT => NLW_mul_temp_13_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_13_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_13_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_13_UNDERFLOW_UNCONNECTED
);
mul_temp_14: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[14]\(15),
A(28) => \data_pipeline_tmp_reg[14]\(15),
A(27) => \data_pipeline_tmp_reg[14]\(15),
A(26) => \data_pipeline_tmp_reg[14]\(15),
A(25) => \data_pipeline_tmp_reg[14]\(15),
A(24) => \data_pipeline_tmp_reg[14]\(15),
A(23) => \data_pipeline_tmp_reg[14]\(15),
A(22) => \data_pipeline_tmp_reg[14]\(15),
A(21) => \data_pipeline_tmp_reg[14]\(15),
A(20) => \data_pipeline_tmp_reg[14]\(15),
A(19) => \data_pipeline_tmp_reg[14]\(15),
A(18) => \data_pipeline_tmp_reg[14]\(15),
A(17) => \data_pipeline_tmp_reg[14]\(15),
A(16) => \data_pipeline_tmp_reg[14]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[14]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_14_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[14]_13\(15),
B(16) => \weight_reg[14]_13\(15),
B(15 downto 0) => \weight_reg[14]_13\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_14_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_14_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_14_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_14_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_14_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_14_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_14_n_74,
P(30) => mul_temp_14_n_75,
P(29) => mul_temp_14_n_76,
P(28) => mul_temp_14_n_77,
P(27) => mul_temp_14_n_78,
P(26) => mul_temp_14_n_79,
P(25) => mul_temp_14_n_80,
P(24) => mul_temp_14_n_81,
P(23) => mul_temp_14_n_82,
P(22) => mul_temp_14_n_83,
P(21) => mul_temp_14_n_84,
P(20) => mul_temp_14_n_85,
P(19) => mul_temp_14_n_86,
P(18) => mul_temp_14_n_87,
P(17) => mul_temp_14_n_88,
P(16) => mul_temp_14_n_89,
P(15) => mul_temp_14_n_90,
P(14) => \^mul_temp_14\(14),
P(13) => mul_temp_14_n_92,
P(12) => mul_temp_14_n_93,
P(11) => mul_temp_14_n_94,
P(10) => mul_temp_14_n_95,
P(9) => mul_temp_14_n_96,
P(8) => mul_temp_14_n_97,
P(7) => mul_temp_14_n_98,
P(6) => mul_temp_14_n_99,
P(5) => mul_temp_14_n_100,
P(4) => mul_temp_14_n_101,
P(3) => mul_temp_14_n_102,
P(2) => mul_temp_14_n_103,
P(1) => mul_temp_14_n_104,
P(0) => mul_temp_14_n_105,
PATTERNBDETECT => NLW_mul_temp_14_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_14_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_14_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_14_UNDERFLOW_UNCONNECTED
);
mul_temp_15: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \write_reg_x_k_reg[15]\(15),
A(28) => \write_reg_x_k_reg[15]\(15),
A(27) => \write_reg_x_k_reg[15]\(15),
A(26) => \write_reg_x_k_reg[15]\(15),
A(25) => \write_reg_x_k_reg[15]\(15),
A(24) => \write_reg_x_k_reg[15]\(15),
A(23) => \write_reg_x_k_reg[15]\(15),
A(22) => \write_reg_x_k_reg[15]\(15),
A(21) => \write_reg_x_k_reg[15]\(15),
A(20) => \write_reg_x_k_reg[15]\(15),
A(19) => \write_reg_x_k_reg[15]\(15),
A(18) => \write_reg_x_k_reg[15]\(15),
A(17) => \write_reg_x_k_reg[15]\(15),
A(16) => \write_reg_x_k_reg[15]\(15),
A(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_15_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[15]_14\(15),
B(16) => \weight_reg[15]_14\(15),
B(15 downto 0) => \weight_reg[15]_14\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_15_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_15_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_15_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_15_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_15_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_15_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_15_n_74,
P(30) => mul_temp_15_n_75,
P(29) => mul_temp_15_n_76,
P(28) => mul_temp_15_n_77,
P(27) => mul_temp_15_n_78,
P(26) => mul_temp_15_n_79,
P(25) => mul_temp_15_n_80,
P(24) => mul_temp_15_n_81,
P(23) => mul_temp_15_n_82,
P(22) => mul_temp_15_n_83,
P(21) => mul_temp_15_n_84,
P(20) => mul_temp_15_n_85,
P(19) => mul_temp_15_n_86,
P(18) => mul_temp_15_n_87,
P(17) => mul_temp_15_n_88,
P(16) => mul_temp_15_n_89,
P(15) => mul_temp_15_n_90,
P(14) => \^mul_temp_15\(14),
P(13) => mul_temp_15_n_92,
P(12) => mul_temp_15_n_93,
P(11) => mul_temp_15_n_94,
P(10) => mul_temp_15_n_95,
P(9) => mul_temp_15_n_96,
P(8) => mul_temp_15_n_97,
P(7) => mul_temp_15_n_98,
P(6) => mul_temp_15_n_99,
P(5) => mul_temp_15_n_100,
P(4) => mul_temp_15_n_101,
P(3) => mul_temp_15_n_102,
P(2) => mul_temp_15_n_103,
P(1) => mul_temp_15_n_104,
P(0) => mul_temp_15_n_105,
PATTERNBDETECT => NLW_mul_temp_15_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_15_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_15_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_15_UNDERFLOW_UNCONNECTED
);
mul_temp_17: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[0]\(15),
A(28) => \data_pipeline_tmp_reg[0]\(15),
A(27) => \data_pipeline_tmp_reg[0]\(15),
A(26) => \data_pipeline_tmp_reg[0]\(15),
A(25) => \data_pipeline_tmp_reg[0]\(15),
A(24) => \data_pipeline_tmp_reg[0]\(15),
A(23) => \data_pipeline_tmp_reg[0]\(15),
A(22) => \data_pipeline_tmp_reg[0]\(15),
A(21) => \data_pipeline_tmp_reg[0]\(15),
A(20) => \data_pipeline_tmp_reg[0]\(15),
A(19) => \data_pipeline_tmp_reg[0]\(15),
A(18) => \data_pipeline_tmp_reg[0]\(15),
A(17) => \data_pipeline_tmp_reg[0]\(15),
A(16) => \data_pipeline_tmp_reg[0]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[0]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_17_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_17_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_17_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_17_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_17_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_17_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_17_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_17_n_74,
P(30) => mul_temp_17_n_75,
P(29) => mul_temp_17_n_76,
P(28) => mul_temp_17_n_77,
P(27) => mul_temp_17_n_78,
P(26) => mul_temp_17_n_79,
P(25) => mul_temp_17_n_80,
P(24) => mul_temp_17_n_81,
P(23) => mul_temp_17_n_82,
P(22) => mul_temp_17_n_83,
P(21) => mul_temp_17_n_84,
P(20) => mul_temp_17_n_85,
P(19) => mul_temp_17_n_86,
P(18) => mul_temp_17_n_87,
P(17) => mul_temp_17_n_88,
P(16) => mul_temp_17_n_89,
P(15) => mul_temp_17_n_90,
P(14) => \^mul_temp_17\(14),
P(13) => mul_temp_17_n_92,
P(12) => mul_temp_17_n_93,
P(11) => mul_temp_17_n_94,
P(10) => mul_temp_17_n_95,
P(9) => mul_temp_17_n_96,
P(8) => mul_temp_17_n_97,
P(7) => mul_temp_17_n_98,
P(6) => mul_temp_17_n_99,
P(5) => mul_temp_17_n_100,
P(4) => mul_temp_17_n_101,
P(3) => mul_temp_17_n_102,
P(2) => mul_temp_17_n_103,
P(1) => mul_temp_17_n_104,
P(0) => mul_temp_17_n_105,
PATTERNBDETECT => NLW_mul_temp_17_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_17_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_17_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_17_UNDERFLOW_UNCONNECTED
);
mul_temp_18: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[1]\(15),
A(28) => \data_pipeline_tmp_reg[1]\(15),
A(27) => \data_pipeline_tmp_reg[1]\(15),
A(26) => \data_pipeline_tmp_reg[1]\(15),
A(25) => \data_pipeline_tmp_reg[1]\(15),
A(24) => \data_pipeline_tmp_reg[1]\(15),
A(23) => \data_pipeline_tmp_reg[1]\(15),
A(22) => \data_pipeline_tmp_reg[1]\(15),
A(21) => \data_pipeline_tmp_reg[1]\(15),
A(20) => \data_pipeline_tmp_reg[1]\(15),
A(19) => \data_pipeline_tmp_reg[1]\(15),
A(18) => \data_pipeline_tmp_reg[1]\(15),
A(17) => \data_pipeline_tmp_reg[1]\(15),
A(16) => \data_pipeline_tmp_reg[1]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[1]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_18_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_18_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_18_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_18_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_18_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_18_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_18_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_18_n_74,
P(30) => mul_temp_18_n_75,
P(29) => mul_temp_18_n_76,
P(28) => mul_temp_18_n_77,
P(27) => mul_temp_18_n_78,
P(26) => mul_temp_18_n_79,
P(25) => mul_temp_18_n_80,
P(24) => mul_temp_18_n_81,
P(23) => mul_temp_18_n_82,
P(22) => mul_temp_18_n_83,
P(21) => mul_temp_18_n_84,
P(20) => mul_temp_18_n_85,
P(19) => mul_temp_18_n_86,
P(18) => mul_temp_18_n_87,
P(17) => mul_temp_18_n_88,
P(16) => mul_temp_18_n_89,
P(15) => mul_temp_18_n_90,
P(14) => \^mul_temp_18\(14),
P(13) => mul_temp_18_n_92,
P(12) => mul_temp_18_n_93,
P(11) => mul_temp_18_n_94,
P(10) => mul_temp_18_n_95,
P(9) => mul_temp_18_n_96,
P(8) => mul_temp_18_n_97,
P(7) => mul_temp_18_n_98,
P(6) => mul_temp_18_n_99,
P(5) => mul_temp_18_n_100,
P(4) => mul_temp_18_n_101,
P(3) => mul_temp_18_n_102,
P(2) => mul_temp_18_n_103,
P(1) => mul_temp_18_n_104,
P(0) => mul_temp_18_n_105,
PATTERNBDETECT => NLW_mul_temp_18_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_18_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_18_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_18_UNDERFLOW_UNCONNECTED
);
mul_temp_19: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[2]\(15),
A(28) => \data_pipeline_tmp_reg[2]\(15),
A(27) => \data_pipeline_tmp_reg[2]\(15),
A(26) => \data_pipeline_tmp_reg[2]\(15),
A(25) => \data_pipeline_tmp_reg[2]\(15),
A(24) => \data_pipeline_tmp_reg[2]\(15),
A(23) => \data_pipeline_tmp_reg[2]\(15),
A(22) => \data_pipeline_tmp_reg[2]\(15),
A(21) => \data_pipeline_tmp_reg[2]\(15),
A(20) => \data_pipeline_tmp_reg[2]\(15),
A(19) => \data_pipeline_tmp_reg[2]\(15),
A(18) => \data_pipeline_tmp_reg[2]\(15),
A(17) => \data_pipeline_tmp_reg[2]\(15),
A(16) => \data_pipeline_tmp_reg[2]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[2]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_19_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_19_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_19_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_19_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_19_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_19_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_19_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_19_n_74,
P(30) => mul_temp_19_n_75,
P(29) => mul_temp_19_n_76,
P(28) => mul_temp_19_n_77,
P(27) => mul_temp_19_n_78,
P(26) => mul_temp_19_n_79,
P(25) => mul_temp_19_n_80,
P(24) => mul_temp_19_n_81,
P(23) => mul_temp_19_n_82,
P(22) => mul_temp_19_n_83,
P(21) => mul_temp_19_n_84,
P(20) => mul_temp_19_n_85,
P(19) => mul_temp_19_n_86,
P(18) => mul_temp_19_n_87,
P(17) => mul_temp_19_n_88,
P(16) => mul_temp_19_n_89,
P(15) => mul_temp_19_n_90,
P(14) => \^mul_temp_19\(14),
P(13) => mul_temp_19_n_92,
P(12) => mul_temp_19_n_93,
P(11) => mul_temp_19_n_94,
P(10) => mul_temp_19_n_95,
P(9) => mul_temp_19_n_96,
P(8) => mul_temp_19_n_97,
P(7) => mul_temp_19_n_98,
P(6) => mul_temp_19_n_99,
P(5) => mul_temp_19_n_100,
P(4) => mul_temp_19_n_101,
P(3) => mul_temp_19_n_102,
P(2) => mul_temp_19_n_103,
P(1) => mul_temp_19_n_104,
P(0) => mul_temp_19_n_105,
PATTERNBDETECT => NLW_mul_temp_19_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_19_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_19_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_19_UNDERFLOW_UNCONNECTED
);
mul_temp_2: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[2]\(15),
A(28) => \data_pipeline_tmp_reg[2]\(15),
A(27) => \data_pipeline_tmp_reg[2]\(15),
A(26) => \data_pipeline_tmp_reg[2]\(15),
A(25) => \data_pipeline_tmp_reg[2]\(15),
A(24) => \data_pipeline_tmp_reg[2]\(15),
A(23) => \data_pipeline_tmp_reg[2]\(15),
A(22) => \data_pipeline_tmp_reg[2]\(15),
A(21) => \data_pipeline_tmp_reg[2]\(15),
A(20) => \data_pipeline_tmp_reg[2]\(15),
A(19) => \data_pipeline_tmp_reg[2]\(15),
A(18) => \data_pipeline_tmp_reg[2]\(15),
A(17) => \data_pipeline_tmp_reg[2]\(15),
A(16) => \data_pipeline_tmp_reg[2]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[2]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_2_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[2]_1\(15),
B(16) => \weight_reg[2]_1\(15),
B(15 downto 0) => \weight_reg[2]_1\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_2_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_2_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_2_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_2_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_2_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_2_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_2_n_74,
P(30) => mul_temp_2_n_75,
P(29) => mul_temp_2_n_76,
P(28) => mul_temp_2_n_77,
P(27) => mul_temp_2_n_78,
P(26) => mul_temp_2_n_79,
P(25) => mul_temp_2_n_80,
P(24) => mul_temp_2_n_81,
P(23) => mul_temp_2_n_82,
P(22) => mul_temp_2_n_83,
P(21) => mul_temp_2_n_84,
P(20) => mul_temp_2_n_85,
P(19) => mul_temp_2_n_86,
P(18) => mul_temp_2_n_87,
P(17) => mul_temp_2_n_88,
P(16) => mul_temp_2_n_89,
P(15) => mul_temp_2_n_90,
P(14) => \^mul_temp_2\(14),
P(13) => mul_temp_2_n_92,
P(12) => mul_temp_2_n_93,
P(11) => mul_temp_2_n_94,
P(10) => mul_temp_2_n_95,
P(9) => mul_temp_2_n_96,
P(8) => mul_temp_2_n_97,
P(7) => mul_temp_2_n_98,
P(6) => mul_temp_2_n_99,
P(5) => mul_temp_2_n_100,
P(4) => mul_temp_2_n_101,
P(3) => mul_temp_2_n_102,
P(2) => mul_temp_2_n_103,
P(1) => mul_temp_2_n_104,
P(0) => mul_temp_2_n_105,
PATTERNBDETECT => NLW_mul_temp_2_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_2_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_2_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_2_UNDERFLOW_UNCONNECTED
);
mul_temp_20: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[3]\(15),
A(28) => \data_pipeline_tmp_reg[3]\(15),
A(27) => \data_pipeline_tmp_reg[3]\(15),
A(26) => \data_pipeline_tmp_reg[3]\(15),
A(25) => \data_pipeline_tmp_reg[3]\(15),
A(24) => \data_pipeline_tmp_reg[3]\(15),
A(23) => \data_pipeline_tmp_reg[3]\(15),
A(22) => \data_pipeline_tmp_reg[3]\(15),
A(21) => \data_pipeline_tmp_reg[3]\(15),
A(20) => \data_pipeline_tmp_reg[3]\(15),
A(19) => \data_pipeline_tmp_reg[3]\(15),
A(18) => \data_pipeline_tmp_reg[3]\(15),
A(17) => \data_pipeline_tmp_reg[3]\(15),
A(16) => \data_pipeline_tmp_reg[3]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[3]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_20_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_20_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_20_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_20_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_20_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_20_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_20_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_20_n_74,
P(30) => mul_temp_20_n_75,
P(29) => mul_temp_20_n_76,
P(28) => mul_temp_20_n_77,
P(27) => mul_temp_20_n_78,
P(26) => mul_temp_20_n_79,
P(25) => mul_temp_20_n_80,
P(24) => mul_temp_20_n_81,
P(23) => mul_temp_20_n_82,
P(22) => mul_temp_20_n_83,
P(21) => mul_temp_20_n_84,
P(20) => mul_temp_20_n_85,
P(19) => mul_temp_20_n_86,
P(18) => mul_temp_20_n_87,
P(17) => mul_temp_20_n_88,
P(16) => mul_temp_20_n_89,
P(15) => mul_temp_20_n_90,
P(14) => \^mul_temp_20\(14),
P(13) => mul_temp_20_n_92,
P(12) => mul_temp_20_n_93,
P(11) => mul_temp_20_n_94,
P(10) => mul_temp_20_n_95,
P(9) => mul_temp_20_n_96,
P(8) => mul_temp_20_n_97,
P(7) => mul_temp_20_n_98,
P(6) => mul_temp_20_n_99,
P(5) => mul_temp_20_n_100,
P(4) => mul_temp_20_n_101,
P(3) => mul_temp_20_n_102,
P(2) => mul_temp_20_n_103,
P(1) => mul_temp_20_n_104,
P(0) => mul_temp_20_n_105,
PATTERNBDETECT => NLW_mul_temp_20_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_20_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_20_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_20_UNDERFLOW_UNCONNECTED
);
mul_temp_21: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[4]\(15),
A(28) => \data_pipeline_tmp_reg[4]\(15),
A(27) => \data_pipeline_tmp_reg[4]\(15),
A(26) => \data_pipeline_tmp_reg[4]\(15),
A(25) => \data_pipeline_tmp_reg[4]\(15),
A(24) => \data_pipeline_tmp_reg[4]\(15),
A(23) => \data_pipeline_tmp_reg[4]\(15),
A(22) => \data_pipeline_tmp_reg[4]\(15),
A(21) => \data_pipeline_tmp_reg[4]\(15),
A(20) => \data_pipeline_tmp_reg[4]\(15),
A(19) => \data_pipeline_tmp_reg[4]\(15),
A(18) => \data_pipeline_tmp_reg[4]\(15),
A(17) => \data_pipeline_tmp_reg[4]\(15),
A(16) => \data_pipeline_tmp_reg[4]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[4]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_21_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_21_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_21_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_21_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_21_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_21_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_21_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_21_n_74,
P(30) => mul_temp_21_n_75,
P(29) => mul_temp_21_n_76,
P(28) => mul_temp_21_n_77,
P(27) => mul_temp_21_n_78,
P(26) => mul_temp_21_n_79,
P(25) => mul_temp_21_n_80,
P(24) => mul_temp_21_n_81,
P(23) => mul_temp_21_n_82,
P(22) => mul_temp_21_n_83,
P(21) => mul_temp_21_n_84,
P(20) => mul_temp_21_n_85,
P(19) => mul_temp_21_n_86,
P(18) => mul_temp_21_n_87,
P(17) => mul_temp_21_n_88,
P(16) => mul_temp_21_n_89,
P(15) => mul_temp_21_n_90,
P(14) => \^mul_temp_21\(14),
P(13) => mul_temp_21_n_92,
P(12) => mul_temp_21_n_93,
P(11) => mul_temp_21_n_94,
P(10) => mul_temp_21_n_95,
P(9) => mul_temp_21_n_96,
P(8) => mul_temp_21_n_97,
P(7) => mul_temp_21_n_98,
P(6) => mul_temp_21_n_99,
P(5) => mul_temp_21_n_100,
P(4) => mul_temp_21_n_101,
P(3) => mul_temp_21_n_102,
P(2) => mul_temp_21_n_103,
P(1) => mul_temp_21_n_104,
P(0) => mul_temp_21_n_105,
PATTERNBDETECT => NLW_mul_temp_21_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_21_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_21_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_21_UNDERFLOW_UNCONNECTED
);
mul_temp_22: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[5]\(15),
A(28) => \data_pipeline_tmp_reg[5]\(15),
A(27) => \data_pipeline_tmp_reg[5]\(15),
A(26) => \data_pipeline_tmp_reg[5]\(15),
A(25) => \data_pipeline_tmp_reg[5]\(15),
A(24) => \data_pipeline_tmp_reg[5]\(15),
A(23) => \data_pipeline_tmp_reg[5]\(15),
A(22) => \data_pipeline_tmp_reg[5]\(15),
A(21) => \data_pipeline_tmp_reg[5]\(15),
A(20) => \data_pipeline_tmp_reg[5]\(15),
A(19) => \data_pipeline_tmp_reg[5]\(15),
A(18) => \data_pipeline_tmp_reg[5]\(15),
A(17) => \data_pipeline_tmp_reg[5]\(15),
A(16) => \data_pipeline_tmp_reg[5]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[5]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_22_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_22_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_22_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_22_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_22_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_22_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_22_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_22_n_74,
P(30) => mul_temp_22_n_75,
P(29) => mul_temp_22_n_76,
P(28) => mul_temp_22_n_77,
P(27) => mul_temp_22_n_78,
P(26) => mul_temp_22_n_79,
P(25) => mul_temp_22_n_80,
P(24) => mul_temp_22_n_81,
P(23) => mul_temp_22_n_82,
P(22) => mul_temp_22_n_83,
P(21) => mul_temp_22_n_84,
P(20) => mul_temp_22_n_85,
P(19) => mul_temp_22_n_86,
P(18) => mul_temp_22_n_87,
P(17) => mul_temp_22_n_88,
P(16) => mul_temp_22_n_89,
P(15) => mul_temp_22_n_90,
P(14) => \^mul_temp_22\(14),
P(13) => mul_temp_22_n_92,
P(12) => mul_temp_22_n_93,
P(11) => mul_temp_22_n_94,
P(10) => mul_temp_22_n_95,
P(9) => mul_temp_22_n_96,
P(8) => mul_temp_22_n_97,
P(7) => mul_temp_22_n_98,
P(6) => mul_temp_22_n_99,
P(5) => mul_temp_22_n_100,
P(4) => mul_temp_22_n_101,
P(3) => mul_temp_22_n_102,
P(2) => mul_temp_22_n_103,
P(1) => mul_temp_22_n_104,
P(0) => mul_temp_22_n_105,
PATTERNBDETECT => NLW_mul_temp_22_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_22_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_22_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_22_UNDERFLOW_UNCONNECTED
);
mul_temp_23: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[6]\(15),
A(28) => \data_pipeline_tmp_reg[6]\(15),
A(27) => \data_pipeline_tmp_reg[6]\(15),
A(26) => \data_pipeline_tmp_reg[6]\(15),
A(25) => \data_pipeline_tmp_reg[6]\(15),
A(24) => \data_pipeline_tmp_reg[6]\(15),
A(23) => \data_pipeline_tmp_reg[6]\(15),
A(22) => \data_pipeline_tmp_reg[6]\(15),
A(21) => \data_pipeline_tmp_reg[6]\(15),
A(20) => \data_pipeline_tmp_reg[6]\(15),
A(19) => \data_pipeline_tmp_reg[6]\(15),
A(18) => \data_pipeline_tmp_reg[6]\(15),
A(17) => \data_pipeline_tmp_reg[6]\(15),
A(16) => \data_pipeline_tmp_reg[6]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[6]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_23_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_23_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_23_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_23_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_23_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_23_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_23_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_23_n_74,
P(30) => mul_temp_23_n_75,
P(29) => mul_temp_23_n_76,
P(28) => mul_temp_23_n_77,
P(27) => mul_temp_23_n_78,
P(26) => mul_temp_23_n_79,
P(25) => mul_temp_23_n_80,
P(24) => mul_temp_23_n_81,
P(23) => mul_temp_23_n_82,
P(22) => mul_temp_23_n_83,
P(21) => mul_temp_23_n_84,
P(20) => mul_temp_23_n_85,
P(19) => mul_temp_23_n_86,
P(18) => mul_temp_23_n_87,
P(17) => mul_temp_23_n_88,
P(16) => mul_temp_23_n_89,
P(15) => mul_temp_23_n_90,
P(14) => \^mul_temp_23\(14),
P(13) => mul_temp_23_n_92,
P(12) => mul_temp_23_n_93,
P(11) => mul_temp_23_n_94,
P(10) => mul_temp_23_n_95,
P(9) => mul_temp_23_n_96,
P(8) => mul_temp_23_n_97,
P(7) => mul_temp_23_n_98,
P(6) => mul_temp_23_n_99,
P(5) => mul_temp_23_n_100,
P(4) => mul_temp_23_n_101,
P(3) => mul_temp_23_n_102,
P(2) => mul_temp_23_n_103,
P(1) => mul_temp_23_n_104,
P(0) => mul_temp_23_n_105,
PATTERNBDETECT => NLW_mul_temp_23_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_23_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_23_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_23_UNDERFLOW_UNCONNECTED
);
mul_temp_24: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[7]\(15),
A(28) => \data_pipeline_tmp_reg[7]\(15),
A(27) => \data_pipeline_tmp_reg[7]\(15),
A(26) => \data_pipeline_tmp_reg[7]\(15),
A(25) => \data_pipeline_tmp_reg[7]\(15),
A(24) => \data_pipeline_tmp_reg[7]\(15),
A(23) => \data_pipeline_tmp_reg[7]\(15),
A(22) => \data_pipeline_tmp_reg[7]\(15),
A(21) => \data_pipeline_tmp_reg[7]\(15),
A(20) => \data_pipeline_tmp_reg[7]\(15),
A(19) => \data_pipeline_tmp_reg[7]\(15),
A(18) => \data_pipeline_tmp_reg[7]\(15),
A(17) => \data_pipeline_tmp_reg[7]\(15),
A(16) => \data_pipeline_tmp_reg[7]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[7]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_24_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_24_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_24_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_24_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_24_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_24_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_24_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_24_n_74,
P(30) => mul_temp_24_n_75,
P(29) => mul_temp_24_n_76,
P(28) => mul_temp_24_n_77,
P(27) => mul_temp_24_n_78,
P(26) => mul_temp_24_n_79,
P(25) => mul_temp_24_n_80,
P(24) => mul_temp_24_n_81,
P(23) => mul_temp_24_n_82,
P(22) => mul_temp_24_n_83,
P(21) => mul_temp_24_n_84,
P(20) => mul_temp_24_n_85,
P(19) => mul_temp_24_n_86,
P(18) => mul_temp_24_n_87,
P(17) => mul_temp_24_n_88,
P(16) => mul_temp_24_n_89,
P(15) => mul_temp_24_n_90,
P(14) => \^mul_temp_24\(14),
P(13) => mul_temp_24_n_92,
P(12) => mul_temp_24_n_93,
P(11) => mul_temp_24_n_94,
P(10) => mul_temp_24_n_95,
P(9) => mul_temp_24_n_96,
P(8) => mul_temp_24_n_97,
P(7) => mul_temp_24_n_98,
P(6) => mul_temp_24_n_99,
P(5) => mul_temp_24_n_100,
P(4) => mul_temp_24_n_101,
P(3) => mul_temp_24_n_102,
P(2) => mul_temp_24_n_103,
P(1) => mul_temp_24_n_104,
P(0) => mul_temp_24_n_105,
PATTERNBDETECT => NLW_mul_temp_24_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_24_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_24_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_24_UNDERFLOW_UNCONNECTED
);
mul_temp_25: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[8]\(15),
A(28) => \data_pipeline_tmp_reg[8]\(15),
A(27) => \data_pipeline_tmp_reg[8]\(15),
A(26) => \data_pipeline_tmp_reg[8]\(15),
A(25) => \data_pipeline_tmp_reg[8]\(15),
A(24) => \data_pipeline_tmp_reg[8]\(15),
A(23) => \data_pipeline_tmp_reg[8]\(15),
A(22) => \data_pipeline_tmp_reg[8]\(15),
A(21) => \data_pipeline_tmp_reg[8]\(15),
A(20) => \data_pipeline_tmp_reg[8]\(15),
A(19) => \data_pipeline_tmp_reg[8]\(15),
A(18) => \data_pipeline_tmp_reg[8]\(15),
A(17) => \data_pipeline_tmp_reg[8]\(15),
A(16) => \data_pipeline_tmp_reg[8]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[8]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_25_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_25_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_25_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_25_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_25_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_25_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_25_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_25_n_74,
P(30) => mul_temp_25_n_75,
P(29) => mul_temp_25_n_76,
P(28) => mul_temp_25_n_77,
P(27) => mul_temp_25_n_78,
P(26) => mul_temp_25_n_79,
P(25) => mul_temp_25_n_80,
P(24) => mul_temp_25_n_81,
P(23) => mul_temp_25_n_82,
P(22) => mul_temp_25_n_83,
P(21) => mul_temp_25_n_84,
P(20) => mul_temp_25_n_85,
P(19) => mul_temp_25_n_86,
P(18) => mul_temp_25_n_87,
P(17) => mul_temp_25_n_88,
P(16) => mul_temp_25_n_89,
P(15) => mul_temp_25_n_90,
P(14) => \^mul_temp_25\(14),
P(13) => mul_temp_25_n_92,
P(12) => mul_temp_25_n_93,
P(11) => mul_temp_25_n_94,
P(10) => mul_temp_25_n_95,
P(9) => mul_temp_25_n_96,
P(8) => mul_temp_25_n_97,
P(7) => mul_temp_25_n_98,
P(6) => mul_temp_25_n_99,
P(5) => mul_temp_25_n_100,
P(4) => mul_temp_25_n_101,
P(3) => mul_temp_25_n_102,
P(2) => mul_temp_25_n_103,
P(1) => mul_temp_25_n_104,
P(0) => mul_temp_25_n_105,
PATTERNBDETECT => NLW_mul_temp_25_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_25_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_25_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_25_UNDERFLOW_UNCONNECTED
);
mul_temp_26: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[9]\(15),
A(28) => \data_pipeline_tmp_reg[9]\(15),
A(27) => \data_pipeline_tmp_reg[9]\(15),
A(26) => \data_pipeline_tmp_reg[9]\(15),
A(25) => \data_pipeline_tmp_reg[9]\(15),
A(24) => \data_pipeline_tmp_reg[9]\(15),
A(23) => \data_pipeline_tmp_reg[9]\(15),
A(22) => \data_pipeline_tmp_reg[9]\(15),
A(21) => \data_pipeline_tmp_reg[9]\(15),
A(20) => \data_pipeline_tmp_reg[9]\(15),
A(19) => \data_pipeline_tmp_reg[9]\(15),
A(18) => \data_pipeline_tmp_reg[9]\(15),
A(17) => \data_pipeline_tmp_reg[9]\(15),
A(16) => \data_pipeline_tmp_reg[9]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[9]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_26_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_26_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_26_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_26_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_26_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_26_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_26_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_26_n_74,
P(30) => mul_temp_26_n_75,
P(29) => mul_temp_26_n_76,
P(28) => mul_temp_26_n_77,
P(27) => mul_temp_26_n_78,
P(26) => mul_temp_26_n_79,
P(25) => mul_temp_26_n_80,
P(24) => mul_temp_26_n_81,
P(23) => mul_temp_26_n_82,
P(22) => mul_temp_26_n_83,
P(21) => mul_temp_26_n_84,
P(20) => mul_temp_26_n_85,
P(19) => mul_temp_26_n_86,
P(18) => mul_temp_26_n_87,
P(17) => mul_temp_26_n_88,
P(16) => mul_temp_26_n_89,
P(15) => mul_temp_26_n_90,
P(14) => \^mul_temp_26\(14),
P(13) => mul_temp_26_n_92,
P(12) => mul_temp_26_n_93,
P(11) => mul_temp_26_n_94,
P(10) => mul_temp_26_n_95,
P(9) => mul_temp_26_n_96,
P(8) => mul_temp_26_n_97,
P(7) => mul_temp_26_n_98,
P(6) => mul_temp_26_n_99,
P(5) => mul_temp_26_n_100,
P(4) => mul_temp_26_n_101,
P(3) => mul_temp_26_n_102,
P(2) => mul_temp_26_n_103,
P(1) => mul_temp_26_n_104,
P(0) => mul_temp_26_n_105,
PATTERNBDETECT => NLW_mul_temp_26_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_26_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_26_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_26_UNDERFLOW_UNCONNECTED
);
mul_temp_27: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[10]\(15),
A(28) => \data_pipeline_tmp_reg[10]\(15),
A(27) => \data_pipeline_tmp_reg[10]\(15),
A(26) => \data_pipeline_tmp_reg[10]\(15),
A(25) => \data_pipeline_tmp_reg[10]\(15),
A(24) => \data_pipeline_tmp_reg[10]\(15),
A(23) => \data_pipeline_tmp_reg[10]\(15),
A(22) => \data_pipeline_tmp_reg[10]\(15),
A(21) => \data_pipeline_tmp_reg[10]\(15),
A(20) => \data_pipeline_tmp_reg[10]\(15),
A(19) => \data_pipeline_tmp_reg[10]\(15),
A(18) => \data_pipeline_tmp_reg[10]\(15),
A(17) => \data_pipeline_tmp_reg[10]\(15),
A(16) => \data_pipeline_tmp_reg[10]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[10]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_27_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_27_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_27_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_27_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_27_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_27_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_27_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_27_n_74,
P(30) => mul_temp_27_n_75,
P(29) => mul_temp_27_n_76,
P(28) => mul_temp_27_n_77,
P(27) => mul_temp_27_n_78,
P(26) => mul_temp_27_n_79,
P(25) => mul_temp_27_n_80,
P(24) => mul_temp_27_n_81,
P(23) => mul_temp_27_n_82,
P(22) => mul_temp_27_n_83,
P(21) => mul_temp_27_n_84,
P(20) => mul_temp_27_n_85,
P(19) => mul_temp_27_n_86,
P(18) => mul_temp_27_n_87,
P(17) => mul_temp_27_n_88,
P(16) => mul_temp_27_n_89,
P(15) => mul_temp_27_n_90,
P(14) => \^mul_temp_27\(14),
P(13) => mul_temp_27_n_92,
P(12) => mul_temp_27_n_93,
P(11) => mul_temp_27_n_94,
P(10) => mul_temp_27_n_95,
P(9) => mul_temp_27_n_96,
P(8) => mul_temp_27_n_97,
P(7) => mul_temp_27_n_98,
P(6) => mul_temp_27_n_99,
P(5) => mul_temp_27_n_100,
P(4) => mul_temp_27_n_101,
P(3) => mul_temp_27_n_102,
P(2) => mul_temp_27_n_103,
P(1) => mul_temp_27_n_104,
P(0) => mul_temp_27_n_105,
PATTERNBDETECT => NLW_mul_temp_27_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_27_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_27_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_27_UNDERFLOW_UNCONNECTED
);
mul_temp_28: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[11]\(15),
A(28) => \data_pipeline_tmp_reg[11]\(15),
A(27) => \data_pipeline_tmp_reg[11]\(15),
A(26) => \data_pipeline_tmp_reg[11]\(15),
A(25) => \data_pipeline_tmp_reg[11]\(15),
A(24) => \data_pipeline_tmp_reg[11]\(15),
A(23) => \data_pipeline_tmp_reg[11]\(15),
A(22) => \data_pipeline_tmp_reg[11]\(15),
A(21) => \data_pipeline_tmp_reg[11]\(15),
A(20) => \data_pipeline_tmp_reg[11]\(15),
A(19) => \data_pipeline_tmp_reg[11]\(15),
A(18) => \data_pipeline_tmp_reg[11]\(15),
A(17) => \data_pipeline_tmp_reg[11]\(15),
A(16) => \data_pipeline_tmp_reg[11]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[11]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_28_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_28_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_28_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_28_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_28_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_28_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_28_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_28_n_74,
P(30) => mul_temp_28_n_75,
P(29) => mul_temp_28_n_76,
P(28) => mul_temp_28_n_77,
P(27) => mul_temp_28_n_78,
P(26) => mul_temp_28_n_79,
P(25) => mul_temp_28_n_80,
P(24) => mul_temp_28_n_81,
P(23) => mul_temp_28_n_82,
P(22) => mul_temp_28_n_83,
P(21) => mul_temp_28_n_84,
P(20) => mul_temp_28_n_85,
P(19) => mul_temp_28_n_86,
P(18) => mul_temp_28_n_87,
P(17) => mul_temp_28_n_88,
P(16) => mul_temp_28_n_89,
P(15) => mul_temp_28_n_90,
P(14) => \^mul_temp_28\(14),
P(13) => mul_temp_28_n_92,
P(12) => mul_temp_28_n_93,
P(11) => mul_temp_28_n_94,
P(10) => mul_temp_28_n_95,
P(9) => mul_temp_28_n_96,
P(8) => mul_temp_28_n_97,
P(7) => mul_temp_28_n_98,
P(6) => mul_temp_28_n_99,
P(5) => mul_temp_28_n_100,
P(4) => mul_temp_28_n_101,
P(3) => mul_temp_28_n_102,
P(2) => mul_temp_28_n_103,
P(1) => mul_temp_28_n_104,
P(0) => mul_temp_28_n_105,
PATTERNBDETECT => NLW_mul_temp_28_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_28_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_28_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_28_UNDERFLOW_UNCONNECTED
);
mul_temp_29: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[12]\(15),
A(28) => \data_pipeline_tmp_reg[12]\(15),
A(27) => \data_pipeline_tmp_reg[12]\(15),
A(26) => \data_pipeline_tmp_reg[12]\(15),
A(25) => \data_pipeline_tmp_reg[12]\(15),
A(24) => \data_pipeline_tmp_reg[12]\(15),
A(23) => \data_pipeline_tmp_reg[12]\(15),
A(22) => \data_pipeline_tmp_reg[12]\(15),
A(21) => \data_pipeline_tmp_reg[12]\(15),
A(20) => \data_pipeline_tmp_reg[12]\(15),
A(19) => \data_pipeline_tmp_reg[12]\(15),
A(18) => \data_pipeline_tmp_reg[12]\(15),
A(17) => \data_pipeline_tmp_reg[12]\(15),
A(16) => \data_pipeline_tmp_reg[12]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[12]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_29_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_29_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_29_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_29_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_29_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_29_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_29_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_29_n_74,
P(30) => mul_temp_29_n_75,
P(29) => mul_temp_29_n_76,
P(28) => mul_temp_29_n_77,
P(27) => mul_temp_29_n_78,
P(26) => mul_temp_29_n_79,
P(25) => mul_temp_29_n_80,
P(24) => mul_temp_29_n_81,
P(23) => mul_temp_29_n_82,
P(22) => mul_temp_29_n_83,
P(21) => mul_temp_29_n_84,
P(20) => mul_temp_29_n_85,
P(19) => mul_temp_29_n_86,
P(18) => mul_temp_29_n_87,
P(17) => mul_temp_29_n_88,
P(16) => mul_temp_29_n_89,
P(15) => mul_temp_29_n_90,
P(14) => \^mul_temp_29\(14),
P(13) => mul_temp_29_n_92,
P(12) => mul_temp_29_n_93,
P(11) => mul_temp_29_n_94,
P(10) => mul_temp_29_n_95,
P(9) => mul_temp_29_n_96,
P(8) => mul_temp_29_n_97,
P(7) => mul_temp_29_n_98,
P(6) => mul_temp_29_n_99,
P(5) => mul_temp_29_n_100,
P(4) => mul_temp_29_n_101,
P(3) => mul_temp_29_n_102,
P(2) => mul_temp_29_n_103,
P(1) => mul_temp_29_n_104,
P(0) => mul_temp_29_n_105,
PATTERNBDETECT => NLW_mul_temp_29_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_29_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_29_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_29_UNDERFLOW_UNCONNECTED
);
mul_temp_3: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[3]\(15),
A(28) => \data_pipeline_tmp_reg[3]\(15),
A(27) => \data_pipeline_tmp_reg[3]\(15),
A(26) => \data_pipeline_tmp_reg[3]\(15),
A(25) => \data_pipeline_tmp_reg[3]\(15),
A(24) => \data_pipeline_tmp_reg[3]\(15),
A(23) => \data_pipeline_tmp_reg[3]\(15),
A(22) => \data_pipeline_tmp_reg[3]\(15),
A(21) => \data_pipeline_tmp_reg[3]\(15),
A(20) => \data_pipeline_tmp_reg[3]\(15),
A(19) => \data_pipeline_tmp_reg[3]\(15),
A(18) => \data_pipeline_tmp_reg[3]\(15),
A(17) => \data_pipeline_tmp_reg[3]\(15),
A(16) => \data_pipeline_tmp_reg[3]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[3]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_3_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[3]_2\(15),
B(16) => \weight_reg[3]_2\(15),
B(15 downto 0) => \weight_reg[3]_2\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_3_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_3_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_3_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_3_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_3_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_3_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_3_n_74,
P(30) => mul_temp_3_n_75,
P(29) => mul_temp_3_n_76,
P(28) => mul_temp_3_n_77,
P(27) => mul_temp_3_n_78,
P(26) => mul_temp_3_n_79,
P(25) => mul_temp_3_n_80,
P(24) => mul_temp_3_n_81,
P(23) => mul_temp_3_n_82,
P(22) => mul_temp_3_n_83,
P(21) => mul_temp_3_n_84,
P(20) => mul_temp_3_n_85,
P(19) => mul_temp_3_n_86,
P(18) => mul_temp_3_n_87,
P(17) => mul_temp_3_n_88,
P(16) => mul_temp_3_n_89,
P(15) => mul_temp_3_n_90,
P(14) => \^mul_temp_3\(14),
P(13) => mul_temp_3_n_92,
P(12) => mul_temp_3_n_93,
P(11) => mul_temp_3_n_94,
P(10) => mul_temp_3_n_95,
P(9) => mul_temp_3_n_96,
P(8) => mul_temp_3_n_97,
P(7) => mul_temp_3_n_98,
P(6) => mul_temp_3_n_99,
P(5) => mul_temp_3_n_100,
P(4) => mul_temp_3_n_101,
P(3) => mul_temp_3_n_102,
P(2) => mul_temp_3_n_103,
P(1) => mul_temp_3_n_104,
P(0) => mul_temp_3_n_105,
PATTERNBDETECT => NLW_mul_temp_3_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_3_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_3_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_3_UNDERFLOW_UNCONNECTED
);
mul_temp_30: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[13]\(15),
A(28) => \data_pipeline_tmp_reg[13]\(15),
A(27) => \data_pipeline_tmp_reg[13]\(15),
A(26) => \data_pipeline_tmp_reg[13]\(15),
A(25) => \data_pipeline_tmp_reg[13]\(15),
A(24) => \data_pipeline_tmp_reg[13]\(15),
A(23) => \data_pipeline_tmp_reg[13]\(15),
A(22) => \data_pipeline_tmp_reg[13]\(15),
A(21) => \data_pipeline_tmp_reg[13]\(15),
A(20) => \data_pipeline_tmp_reg[13]\(15),
A(19) => \data_pipeline_tmp_reg[13]\(15),
A(18) => \data_pipeline_tmp_reg[13]\(15),
A(17) => \data_pipeline_tmp_reg[13]\(15),
A(16) => \data_pipeline_tmp_reg[13]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[13]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_30_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_30_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_30_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_30_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_30_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_30_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_30_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_30_n_74,
P(30) => mul_temp_30_n_75,
P(29) => mul_temp_30_n_76,
P(28) => mul_temp_30_n_77,
P(27) => mul_temp_30_n_78,
P(26) => mul_temp_30_n_79,
P(25) => mul_temp_30_n_80,
P(24) => mul_temp_30_n_81,
P(23) => mul_temp_30_n_82,
P(22) => mul_temp_30_n_83,
P(21) => mul_temp_30_n_84,
P(20) => mul_temp_30_n_85,
P(19) => mul_temp_30_n_86,
P(18) => mul_temp_30_n_87,
P(17) => mul_temp_30_n_88,
P(16) => mul_temp_30_n_89,
P(15) => mul_temp_30_n_90,
P(14) => \^mul_temp_30\(14),
P(13) => mul_temp_30_n_92,
P(12) => mul_temp_30_n_93,
P(11) => mul_temp_30_n_94,
P(10) => mul_temp_30_n_95,
P(9) => mul_temp_30_n_96,
P(8) => mul_temp_30_n_97,
P(7) => mul_temp_30_n_98,
P(6) => mul_temp_30_n_99,
P(5) => mul_temp_30_n_100,
P(4) => mul_temp_30_n_101,
P(3) => mul_temp_30_n_102,
P(2) => mul_temp_30_n_103,
P(1) => mul_temp_30_n_104,
P(0) => mul_temp_30_n_105,
PATTERNBDETECT => NLW_mul_temp_30_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_30_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_30_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_30_UNDERFLOW_UNCONNECTED
);
mul_temp_31: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[14]\(15),
A(28) => \data_pipeline_tmp_reg[14]\(15),
A(27) => \data_pipeline_tmp_reg[14]\(15),
A(26) => \data_pipeline_tmp_reg[14]\(15),
A(25) => \data_pipeline_tmp_reg[14]\(15),
A(24) => \data_pipeline_tmp_reg[14]\(15),
A(23) => \data_pipeline_tmp_reg[14]\(15),
A(22) => \data_pipeline_tmp_reg[14]\(15),
A(21) => \data_pipeline_tmp_reg[14]\(15),
A(20) => \data_pipeline_tmp_reg[14]\(15),
A(19) => \data_pipeline_tmp_reg[14]\(15),
A(18) => \data_pipeline_tmp_reg[14]\(15),
A(17) => \data_pipeline_tmp_reg[14]\(15),
A(16) => \data_pipeline_tmp_reg[14]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[14]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_31_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_31_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_31_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_31_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_31_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_31_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_31_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_31_n_74,
P(30) => mul_temp_31_n_75,
P(29) => mul_temp_31_n_76,
P(28) => mul_temp_31_n_77,
P(27) => mul_temp_31_n_78,
P(26) => mul_temp_31_n_79,
P(25) => mul_temp_31_n_80,
P(24) => mul_temp_31_n_81,
P(23) => mul_temp_31_n_82,
P(22) => mul_temp_31_n_83,
P(21) => mul_temp_31_n_84,
P(20) => mul_temp_31_n_85,
P(19) => mul_temp_31_n_86,
P(18) => mul_temp_31_n_87,
P(17) => mul_temp_31_n_88,
P(16) => mul_temp_31_n_89,
P(15) => mul_temp_31_n_90,
P(14) => \^mul_temp_31\(14),
P(13) => mul_temp_31_n_92,
P(12) => mul_temp_31_n_93,
P(11) => mul_temp_31_n_94,
P(10) => mul_temp_31_n_95,
P(9) => mul_temp_31_n_96,
P(8) => mul_temp_31_n_97,
P(7) => mul_temp_31_n_98,
P(6) => mul_temp_31_n_99,
P(5) => mul_temp_31_n_100,
P(4) => mul_temp_31_n_101,
P(3) => mul_temp_31_n_102,
P(2) => mul_temp_31_n_103,
P(1) => mul_temp_31_n_104,
P(0) => mul_temp_31_n_105,
PATTERNBDETECT => NLW_mul_temp_31_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_31_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_31_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_31_UNDERFLOW_UNCONNECTED
);
mul_temp_32: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \write_reg_x_k_reg[15]\(15),
A(28) => \write_reg_x_k_reg[15]\(15),
A(27) => \write_reg_x_k_reg[15]\(15),
A(26) => \write_reg_x_k_reg[15]\(15),
A(25) => \write_reg_x_k_reg[15]\(15),
A(24) => \write_reg_x_k_reg[15]\(15),
A(23) => \write_reg_x_k_reg[15]\(15),
A(22) => \write_reg_x_k_reg[15]\(15),
A(21) => \write_reg_x_k_reg[15]\(15),
A(20) => \write_reg_x_k_reg[15]\(15),
A(19) => \write_reg_x_k_reg[15]\(15),
A(18) => \write_reg_x_k_reg[15]\(15),
A(17) => \write_reg_x_k_reg[15]\(15),
A(16) => \write_reg_x_k_reg[15]\(15),
A(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_32_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_32_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_32_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_32_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_32_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_32_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_32_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_32_n_74,
P(30) => mul_temp_32_n_75,
P(29) => mul_temp_32_n_76,
P(28) => mul_temp_32_n_77,
P(27) => mul_temp_32_n_78,
P(26) => mul_temp_32_n_79,
P(25) => mul_temp_32_n_80,
P(24) => mul_temp_32_n_81,
P(23) => mul_temp_32_n_82,
P(22) => mul_temp_32_n_83,
P(21) => mul_temp_32_n_84,
P(20) => mul_temp_32_n_85,
P(19) => mul_temp_32_n_86,
P(18) => mul_temp_32_n_87,
P(17) => mul_temp_32_n_88,
P(16) => mul_temp_32_n_89,
P(15) => mul_temp_32_n_90,
P(14) => \^mul_temp_32\(14),
P(13) => mul_temp_32_n_92,
P(12) => mul_temp_32_n_93,
P(11) => mul_temp_32_n_94,
P(10) => mul_temp_32_n_95,
P(9) => mul_temp_32_n_96,
P(8) => mul_temp_32_n_97,
P(7) => mul_temp_32_n_98,
P(6) => mul_temp_32_n_99,
P(5) => mul_temp_32_n_100,
P(4) => mul_temp_32_n_101,
P(3) => mul_temp_32_n_102,
P(2) => mul_temp_32_n_103,
P(1) => mul_temp_32_n_104,
P(0) => mul_temp_32_n_105,
PATTERNBDETECT => NLW_mul_temp_32_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_32_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_32_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_32_UNDERFLOW_UNCONNECTED
);
mul_temp_4: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[4]\(15),
A(28) => \data_pipeline_tmp_reg[4]\(15),
A(27) => \data_pipeline_tmp_reg[4]\(15),
A(26) => \data_pipeline_tmp_reg[4]\(15),
A(25) => \data_pipeline_tmp_reg[4]\(15),
A(24) => \data_pipeline_tmp_reg[4]\(15),
A(23) => \data_pipeline_tmp_reg[4]\(15),
A(22) => \data_pipeline_tmp_reg[4]\(15),
A(21) => \data_pipeline_tmp_reg[4]\(15),
A(20) => \data_pipeline_tmp_reg[4]\(15),
A(19) => \data_pipeline_tmp_reg[4]\(15),
A(18) => \data_pipeline_tmp_reg[4]\(15),
A(17) => \data_pipeline_tmp_reg[4]\(15),
A(16) => \data_pipeline_tmp_reg[4]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[4]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_4_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[4]_3\(15),
B(16) => \weight_reg[4]_3\(15),
B(15 downto 0) => \weight_reg[4]_3\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_4_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_4_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_4_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_4_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_4_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_4_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_4_n_74,
P(30) => mul_temp_4_n_75,
P(29) => mul_temp_4_n_76,
P(28) => mul_temp_4_n_77,
P(27) => mul_temp_4_n_78,
P(26) => mul_temp_4_n_79,
P(25) => mul_temp_4_n_80,
P(24) => mul_temp_4_n_81,
P(23) => mul_temp_4_n_82,
P(22) => mul_temp_4_n_83,
P(21) => mul_temp_4_n_84,
P(20) => mul_temp_4_n_85,
P(19) => mul_temp_4_n_86,
P(18) => mul_temp_4_n_87,
P(17) => mul_temp_4_n_88,
P(16) => mul_temp_4_n_89,
P(15) => mul_temp_4_n_90,
P(14) => \^mul_temp_4\(14),
P(13) => mul_temp_4_n_92,
P(12) => mul_temp_4_n_93,
P(11) => mul_temp_4_n_94,
P(10) => mul_temp_4_n_95,
P(9) => mul_temp_4_n_96,
P(8) => mul_temp_4_n_97,
P(7) => mul_temp_4_n_98,
P(6) => mul_temp_4_n_99,
P(5) => mul_temp_4_n_100,
P(4) => mul_temp_4_n_101,
P(3) => mul_temp_4_n_102,
P(2) => mul_temp_4_n_103,
P(1) => mul_temp_4_n_104,
P(0) => mul_temp_4_n_105,
PATTERNBDETECT => NLW_mul_temp_4_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_4_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_4_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_4_UNDERFLOW_UNCONNECTED
);
mul_temp_5: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[5]\(15),
A(28) => \data_pipeline_tmp_reg[5]\(15),
A(27) => \data_pipeline_tmp_reg[5]\(15),
A(26) => \data_pipeline_tmp_reg[5]\(15),
A(25) => \data_pipeline_tmp_reg[5]\(15),
A(24) => \data_pipeline_tmp_reg[5]\(15),
A(23) => \data_pipeline_tmp_reg[5]\(15),
A(22) => \data_pipeline_tmp_reg[5]\(15),
A(21) => \data_pipeline_tmp_reg[5]\(15),
A(20) => \data_pipeline_tmp_reg[5]\(15),
A(19) => \data_pipeline_tmp_reg[5]\(15),
A(18) => \data_pipeline_tmp_reg[5]\(15),
A(17) => \data_pipeline_tmp_reg[5]\(15),
A(16) => \data_pipeline_tmp_reg[5]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[5]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_5_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[5]_4\(15),
B(16) => \weight_reg[5]_4\(15),
B(15 downto 0) => \weight_reg[5]_4\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_5_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_5_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_5_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_5_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_5_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_5_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_5_n_74,
P(30) => mul_temp_5_n_75,
P(29) => mul_temp_5_n_76,
P(28) => mul_temp_5_n_77,
P(27) => mul_temp_5_n_78,
P(26) => mul_temp_5_n_79,
P(25) => mul_temp_5_n_80,
P(24) => mul_temp_5_n_81,
P(23) => mul_temp_5_n_82,
P(22) => mul_temp_5_n_83,
P(21) => mul_temp_5_n_84,
P(20) => mul_temp_5_n_85,
P(19) => mul_temp_5_n_86,
P(18) => mul_temp_5_n_87,
P(17) => mul_temp_5_n_88,
P(16) => mul_temp_5_n_89,
P(15) => mul_temp_5_n_90,
P(14) => \^mul_temp_5\(14),
P(13) => mul_temp_5_n_92,
P(12) => mul_temp_5_n_93,
P(11) => mul_temp_5_n_94,
P(10) => mul_temp_5_n_95,
P(9) => mul_temp_5_n_96,
P(8) => mul_temp_5_n_97,
P(7) => mul_temp_5_n_98,
P(6) => mul_temp_5_n_99,
P(5) => mul_temp_5_n_100,
P(4) => mul_temp_5_n_101,
P(3) => mul_temp_5_n_102,
P(2) => mul_temp_5_n_103,
P(1) => mul_temp_5_n_104,
P(0) => mul_temp_5_n_105,
PATTERNBDETECT => NLW_mul_temp_5_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_5_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_5_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_5_UNDERFLOW_UNCONNECTED
);
mul_temp_6: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[6]\(15),
A(28) => \data_pipeline_tmp_reg[6]\(15),
A(27) => \data_pipeline_tmp_reg[6]\(15),
A(26) => \data_pipeline_tmp_reg[6]\(15),
A(25) => \data_pipeline_tmp_reg[6]\(15),
A(24) => \data_pipeline_tmp_reg[6]\(15),
A(23) => \data_pipeline_tmp_reg[6]\(15),
A(22) => \data_pipeline_tmp_reg[6]\(15),
A(21) => \data_pipeline_tmp_reg[6]\(15),
A(20) => \data_pipeline_tmp_reg[6]\(15),
A(19) => \data_pipeline_tmp_reg[6]\(15),
A(18) => \data_pipeline_tmp_reg[6]\(15),
A(17) => \data_pipeline_tmp_reg[6]\(15),
A(16) => \data_pipeline_tmp_reg[6]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[6]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_6_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[6]_5\(15),
B(16) => \weight_reg[6]_5\(15),
B(15 downto 0) => \weight_reg[6]_5\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_6_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_6_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_6_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_6_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_6_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_6_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_6_n_74,
P(30) => mul_temp_6_n_75,
P(29) => mul_temp_6_n_76,
P(28) => mul_temp_6_n_77,
P(27) => mul_temp_6_n_78,
P(26) => mul_temp_6_n_79,
P(25) => mul_temp_6_n_80,
P(24) => mul_temp_6_n_81,
P(23) => mul_temp_6_n_82,
P(22) => mul_temp_6_n_83,
P(21) => mul_temp_6_n_84,
P(20) => mul_temp_6_n_85,
P(19) => mul_temp_6_n_86,
P(18) => mul_temp_6_n_87,
P(17) => mul_temp_6_n_88,
P(16) => mul_temp_6_n_89,
P(15) => mul_temp_6_n_90,
P(14) => \^mul_temp_6\(14),
P(13) => mul_temp_6_n_92,
P(12) => mul_temp_6_n_93,
P(11) => mul_temp_6_n_94,
P(10) => mul_temp_6_n_95,
P(9) => mul_temp_6_n_96,
P(8) => mul_temp_6_n_97,
P(7) => mul_temp_6_n_98,
P(6) => mul_temp_6_n_99,
P(5) => mul_temp_6_n_100,
P(4) => mul_temp_6_n_101,
P(3) => mul_temp_6_n_102,
P(2) => mul_temp_6_n_103,
P(1) => mul_temp_6_n_104,
P(0) => mul_temp_6_n_105,
PATTERNBDETECT => NLW_mul_temp_6_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_6_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_6_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_6_UNDERFLOW_UNCONNECTED
);
mul_temp_7: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[7]\(15),
A(28) => \data_pipeline_tmp_reg[7]\(15),
A(27) => \data_pipeline_tmp_reg[7]\(15),
A(26) => \data_pipeline_tmp_reg[7]\(15),
A(25) => \data_pipeline_tmp_reg[7]\(15),
A(24) => \data_pipeline_tmp_reg[7]\(15),
A(23) => \data_pipeline_tmp_reg[7]\(15),
A(22) => \data_pipeline_tmp_reg[7]\(15),
A(21) => \data_pipeline_tmp_reg[7]\(15),
A(20) => \data_pipeline_tmp_reg[7]\(15),
A(19) => \data_pipeline_tmp_reg[7]\(15),
A(18) => \data_pipeline_tmp_reg[7]\(15),
A(17) => \data_pipeline_tmp_reg[7]\(15),
A(16) => \data_pipeline_tmp_reg[7]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[7]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_7_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[7]_6\(15),
B(16) => \weight_reg[7]_6\(15),
B(15 downto 0) => \weight_reg[7]_6\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_7_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_7_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_7_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_7_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_7_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_7_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_7_n_74,
P(30) => mul_temp_7_n_75,
P(29) => mul_temp_7_n_76,
P(28) => mul_temp_7_n_77,
P(27) => mul_temp_7_n_78,
P(26) => mul_temp_7_n_79,
P(25) => mul_temp_7_n_80,
P(24) => mul_temp_7_n_81,
P(23) => mul_temp_7_n_82,
P(22) => mul_temp_7_n_83,
P(21) => mul_temp_7_n_84,
P(20) => mul_temp_7_n_85,
P(19) => mul_temp_7_n_86,
P(18) => mul_temp_7_n_87,
P(17) => mul_temp_7_n_88,
P(16) => mul_temp_7_n_89,
P(15) => mul_temp_7_n_90,
P(14) => \^mul_temp_7\(14),
P(13) => mul_temp_7_n_92,
P(12) => mul_temp_7_n_93,
P(11) => mul_temp_7_n_94,
P(10) => mul_temp_7_n_95,
P(9) => mul_temp_7_n_96,
P(8) => mul_temp_7_n_97,
P(7) => mul_temp_7_n_98,
P(6) => mul_temp_7_n_99,
P(5) => mul_temp_7_n_100,
P(4) => mul_temp_7_n_101,
P(3) => mul_temp_7_n_102,
P(2) => mul_temp_7_n_103,
P(1) => mul_temp_7_n_104,
P(0) => mul_temp_7_n_105,
PATTERNBDETECT => NLW_mul_temp_7_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_7_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_7_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_7_UNDERFLOW_UNCONNECTED
);
mul_temp_8: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[8]\(15),
A(28) => \data_pipeline_tmp_reg[8]\(15),
A(27) => \data_pipeline_tmp_reg[8]\(15),
A(26) => \data_pipeline_tmp_reg[8]\(15),
A(25) => \data_pipeline_tmp_reg[8]\(15),
A(24) => \data_pipeline_tmp_reg[8]\(15),
A(23) => \data_pipeline_tmp_reg[8]\(15),
A(22) => \data_pipeline_tmp_reg[8]\(15),
A(21) => \data_pipeline_tmp_reg[8]\(15),
A(20) => \data_pipeline_tmp_reg[8]\(15),
A(19) => \data_pipeline_tmp_reg[8]\(15),
A(18) => \data_pipeline_tmp_reg[8]\(15),
A(17) => \data_pipeline_tmp_reg[8]\(15),
A(16) => \data_pipeline_tmp_reg[8]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[8]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_8_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[8]_7\(15),
B(16) => \weight_reg[8]_7\(15),
B(15 downto 0) => \weight_reg[8]_7\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_8_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_8_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_8_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_8_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_8_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_8_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_8_n_74,
P(30) => mul_temp_8_n_75,
P(29) => mul_temp_8_n_76,
P(28) => mul_temp_8_n_77,
P(27) => mul_temp_8_n_78,
P(26) => mul_temp_8_n_79,
P(25) => mul_temp_8_n_80,
P(24) => mul_temp_8_n_81,
P(23) => mul_temp_8_n_82,
P(22) => mul_temp_8_n_83,
P(21) => mul_temp_8_n_84,
P(20) => mul_temp_8_n_85,
P(19) => mul_temp_8_n_86,
P(18) => mul_temp_8_n_87,
P(17) => mul_temp_8_n_88,
P(16) => mul_temp_8_n_89,
P(15) => mul_temp_8_n_90,
P(14) => \^mul_temp_8\(14),
P(13) => mul_temp_8_n_92,
P(12) => mul_temp_8_n_93,
P(11) => mul_temp_8_n_94,
P(10) => mul_temp_8_n_95,
P(9) => mul_temp_8_n_96,
P(8) => mul_temp_8_n_97,
P(7) => mul_temp_8_n_98,
P(6) => mul_temp_8_n_99,
P(5) => mul_temp_8_n_100,
P(4) => mul_temp_8_n_101,
P(3) => mul_temp_8_n_102,
P(2) => mul_temp_8_n_103,
P(1) => mul_temp_8_n_104,
P(0) => mul_temp_8_n_105,
PATTERNBDETECT => NLW_mul_temp_8_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_8_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_8_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_8_UNDERFLOW_UNCONNECTED
);
mul_temp_9: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[9]\(15),
A(28) => \data_pipeline_tmp_reg[9]\(15),
A(27) => \data_pipeline_tmp_reg[9]\(15),
A(26) => \data_pipeline_tmp_reg[9]\(15),
A(25) => \data_pipeline_tmp_reg[9]\(15),
A(24) => \data_pipeline_tmp_reg[9]\(15),
A(23) => \data_pipeline_tmp_reg[9]\(15),
A(22) => \data_pipeline_tmp_reg[9]\(15),
A(21) => \data_pipeline_tmp_reg[9]\(15),
A(20) => \data_pipeline_tmp_reg[9]\(15),
A(19) => \data_pipeline_tmp_reg[9]\(15),
A(18) => \data_pipeline_tmp_reg[9]\(15),
A(17) => \data_pipeline_tmp_reg[9]\(15),
A(16) => \data_pipeline_tmp_reg[9]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[9]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_9_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[9]_8\(15),
B(16) => \weight_reg[9]_8\(15),
B(15 downto 0) => \weight_reg[9]_8\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_9_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_9_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_9_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_9_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_9_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_9_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_9_n_74,
P(30) => mul_temp_9_n_75,
P(29) => mul_temp_9_n_76,
P(28) => mul_temp_9_n_77,
P(27) => mul_temp_9_n_78,
P(26) => mul_temp_9_n_79,
P(25) => mul_temp_9_n_80,
P(24) => mul_temp_9_n_81,
P(23) => mul_temp_9_n_82,
P(22) => mul_temp_9_n_83,
P(21) => mul_temp_9_n_84,
P(20) => mul_temp_9_n_85,
P(19) => mul_temp_9_n_86,
P(18) => mul_temp_9_n_87,
P(17) => mul_temp_9_n_88,
P(16) => mul_temp_9_n_89,
P(15) => mul_temp_9_n_90,
P(14) => \^mul_temp_9\(14),
P(13) => mul_temp_9_n_92,
P(12) => mul_temp_9_n_93,
P(11) => mul_temp_9_n_94,
P(10) => mul_temp_9_n_95,
P(9) => mul_temp_9_n_96,
P(8) => mul_temp_9_n_97,
P(7) => mul_temp_9_n_98,
P(6) => mul_temp_9_n_99,
P(5) => mul_temp_9_n_100,
P(4) => mul_temp_9_n_101,
P(3) => mul_temp_9_n_102,
P(2) => mul_temp_9_n_103,
P(1) => mul_temp_9_n_104,
P(0) => mul_temp_9_n_105,
PATTERNBDETECT => NLW_mul_temp_9_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_9_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_9_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_9_UNDERFLOW_UNCONNECTED
);
sub_temp_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => sub_temp_carry_n_0,
CO(2) => sub_temp_carry_n_1,
CO(1) => sub_temp_carry_n_2,
CO(0) => sub_temp_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => Q(3 downto 0),
O(3 downto 0) => \^mul_temp_16\(3 downto 0),
S(3 downto 0) => \write_reg_d_k_reg[3]_0\(3 downto 0)
);
\sub_temp_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => sub_temp_carry_n_0,
CO(3) => \sub_temp_carry__0_n_0\,
CO(2) => \sub_temp_carry__0_n_1\,
CO(1) => \sub_temp_carry__0_n_2\,
CO(0) => \sub_temp_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => Q(7 downto 4),
O(3 downto 0) => \^mul_temp_16\(7 downto 4),
S(3 downto 0) => \write_reg_d_k_reg[7]\(3 downto 0)
);
\sub_temp_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \sub_temp_carry__0_n_0\,
CO(3) => \sub_temp_carry__1_n_0\,
CO(2) => \sub_temp_carry__1_n_1\,
CO(1) => \sub_temp_carry__1_n_2\,
CO(0) => \sub_temp_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => Q(11 downto 8),
O(3 downto 0) => \^mul_temp_16\(11 downto 8),
S(3 downto 0) => \write_reg_d_k_reg[11]\(3 downto 0)
);
\sub_temp_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \sub_temp_carry__1_n_0\,
CO(3) => \NLW_sub_temp_carry__2_CO_UNCONNECTED\(3),
CO(2) => \sub_temp_carry__2_n_1\,
CO(1) => \sub_temp_carry__2_n_2\,
CO(0) => \sub_temp_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => Q(14 downto 12),
O(3 downto 0) => \^mul_temp_16\(15 downto 12),
S(3 downto 0) => S(3 downto 0)
);
\weight[0][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_88\,
I1 => \weight_reg[0]_15\(3),
O => \weight[0][0]_i_2_n_0\
);
\weight[0][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_89\,
I1 => \weight_reg[0]_15\(2),
O => \weight[0][0]_i_3_n_0\
);
\weight[0][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_90\,
I1 => \weight_reg[0]_15\(1),
O => \weight[0][0]_i_4_n_0\
);
\weight[0][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_91\,
I1 => \weight_reg[0]_15\(0),
O => \weight[0][0]_i_5_n_0\
);
\weight[0][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_76\,
I1 => \weight_reg[0]_15\(15),
O => \weight[0][12]_i_2_n_0\
);
\weight[0][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_77\,
I1 => \weight_reg[0]_15\(14),
O => \weight[0][12]_i_3_n_0\
);
\weight[0][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_78\,
I1 => \weight_reg[0]_15\(13),
O => \weight[0][12]_i_4_n_0\
);
\weight[0][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_79\,
I1 => \weight_reg[0]_15\(12),
O => \weight[0][12]_i_5_n_0\
);
\weight[0][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_84\,
I1 => \weight_reg[0]_15\(7),
O => \weight[0][4]_i_2_n_0\
);
\weight[0][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_85\,
I1 => \weight_reg[0]_15\(6),
O => \weight[0][4]_i_3_n_0\
);
\weight[0][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_86\,
I1 => \weight_reg[0]_15\(5),
O => \weight[0][4]_i_4_n_0\
);
\weight[0][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_87\,
I1 => \weight_reg[0]_15\(4),
O => \weight[0][4]_i_5_n_0\
);
\weight[0][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_80\,
I1 => \weight_reg[0]_15\(11),
O => \weight[0][8]_i_2_n_0\
);
\weight[0][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_81\,
I1 => \weight_reg[0]_15\(10),
O => \weight[0][8]_i_3_n_0\
);
\weight[0][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_82\,
I1 => \weight_reg[0]_15\(9),
O => \weight[0][8]_i_4_n_0\
);
\weight[0][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_83\,
I1 => \weight_reg[0]_15\(8),
O => \weight[0][8]_i_5_n_0\
);
\weight[10][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_88\,
I1 => \weight_reg[10]_9\(3),
O => \weight[10][0]_i_2_n_0\
);
\weight[10][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_89\,
I1 => \weight_reg[10]_9\(2),
O => \weight[10][0]_i_3_n_0\
);
\weight[10][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_90\,
I1 => \weight_reg[10]_9\(1),
O => \weight[10][0]_i_4_n_0\
);
\weight[10][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_91\,
I1 => \weight_reg[10]_9\(0),
O => \weight[10][0]_i_5_n_0\
);
\weight[10][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_76\,
I1 => \weight_reg[10]_9\(15),
O => \weight[10][12]_i_2_n_0\
);
\weight[10][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_77\,
I1 => \weight_reg[10]_9\(14),
O => \weight[10][12]_i_3_n_0\
);
\weight[10][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_78\,
I1 => \weight_reg[10]_9\(13),
O => \weight[10][12]_i_4_n_0\
);
\weight[10][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_79\,
I1 => \weight_reg[10]_9\(12),
O => \weight[10][12]_i_5_n_0\
);
\weight[10][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_84\,
I1 => \weight_reg[10]_9\(7),
O => \weight[10][4]_i_2_n_0\
);
\weight[10][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_85\,
I1 => \weight_reg[10]_9\(6),
O => \weight[10][4]_i_3_n_0\
);
\weight[10][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_86\,
I1 => \weight_reg[10]_9\(5),
O => \weight[10][4]_i_4_n_0\
);
\weight[10][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_87\,
I1 => \weight_reg[10]_9\(4),
O => \weight[10][4]_i_5_n_0\
);
\weight[10][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_80\,
I1 => \weight_reg[10]_9\(11),
O => \weight[10][8]_i_2_n_0\
);
\weight[10][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_81\,
I1 => \weight_reg[10]_9\(10),
O => \weight[10][8]_i_3_n_0\
);
\weight[10][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_82\,
I1 => \weight_reg[10]_9\(9),
O => \weight[10][8]_i_4_n_0\
);
\weight[10][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_83\,
I1 => \weight_reg[10]_9\(8),
O => \weight[10][8]_i_5_n_0\
);
\weight[11][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_88\,
I1 => \weight_reg[11]_10\(3),
O => \weight[11][0]_i_2_n_0\
);
\weight[11][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_89\,
I1 => \weight_reg[11]_10\(2),
O => \weight[11][0]_i_3_n_0\
);
\weight[11][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_90\,
I1 => \weight_reg[11]_10\(1),
O => \weight[11][0]_i_4_n_0\
);
\weight[11][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_91\,
I1 => \weight_reg[11]_10\(0),
O => \weight[11][0]_i_5_n_0\
);
\weight[11][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_76\,
I1 => \weight_reg[11]_10\(15),
O => \weight[11][12]_i_2_n_0\
);
\weight[11][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_77\,
I1 => \weight_reg[11]_10\(14),
O => \weight[11][12]_i_3_n_0\
);
\weight[11][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_78\,
I1 => \weight_reg[11]_10\(13),
O => \weight[11][12]_i_4_n_0\
);
\weight[11][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_79\,
I1 => \weight_reg[11]_10\(12),
O => \weight[11][12]_i_5_n_0\
);
\weight[11][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_84\,
I1 => \weight_reg[11]_10\(7),
O => \weight[11][4]_i_2_n_0\
);
\weight[11][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_85\,
I1 => \weight_reg[11]_10\(6),
O => \weight[11][4]_i_3_n_0\
);
\weight[11][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_86\,
I1 => \weight_reg[11]_10\(5),
O => \weight[11][4]_i_4_n_0\
);
\weight[11][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_87\,
I1 => \weight_reg[11]_10\(4),
O => \weight[11][4]_i_5_n_0\
);
\weight[11][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_80\,
I1 => \weight_reg[11]_10\(11),
O => \weight[11][8]_i_2_n_0\
);
\weight[11][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_81\,
I1 => \weight_reg[11]_10\(10),
O => \weight[11][8]_i_3_n_0\
);
\weight[11][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_82\,
I1 => \weight_reg[11]_10\(9),
O => \weight[11][8]_i_4_n_0\
);
\weight[11][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_83\,
I1 => \weight_reg[11]_10\(8),
O => \weight[11][8]_i_5_n_0\
);
\weight[12][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_88\,
I1 => \weight_reg[12]_11\(3),
O => \weight[12][0]_i_2_n_0\
);
\weight[12][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_89\,
I1 => \weight_reg[12]_11\(2),
O => \weight[12][0]_i_3_n_0\
);
\weight[12][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_90\,
I1 => \weight_reg[12]_11\(1),
O => \weight[12][0]_i_4_n_0\
);
\weight[12][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_91\,
I1 => \weight_reg[12]_11\(0),
O => \weight[12][0]_i_5_n_0\
);
\weight[12][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_76\,
I1 => \weight_reg[12]_11\(15),
O => \weight[12][12]_i_2_n_0\
);
\weight[12][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_77\,
I1 => \weight_reg[12]_11\(14),
O => \weight[12][12]_i_3_n_0\
);
\weight[12][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_78\,
I1 => \weight_reg[12]_11\(13),
O => \weight[12][12]_i_4_n_0\
);
\weight[12][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_79\,
I1 => \weight_reg[12]_11\(12),
O => \weight[12][12]_i_5_n_0\
);
\weight[12][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_84\,
I1 => \weight_reg[12]_11\(7),
O => \weight[12][4]_i_2_n_0\
);
\weight[12][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_85\,
I1 => \weight_reg[12]_11\(6),
O => \weight[12][4]_i_3_n_0\
);
\weight[12][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_86\,
I1 => \weight_reg[12]_11\(5),
O => \weight[12][4]_i_4_n_0\
);
\weight[12][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_87\,
I1 => \weight_reg[12]_11\(4),
O => \weight[12][4]_i_5_n_0\
);
\weight[12][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_80\,
I1 => \weight_reg[12]_11\(11),
O => \weight[12][8]_i_2_n_0\
);
\weight[12][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_81\,
I1 => \weight_reg[12]_11\(10),
O => \weight[12][8]_i_3_n_0\
);
\weight[12][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_82\,
I1 => \weight_reg[12]_11\(9),
O => \weight[12][8]_i_4_n_0\
);
\weight[12][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_83\,
I1 => \weight_reg[12]_11\(8),
O => \weight[12][8]_i_5_n_0\
);
\weight[13][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_88\,
I1 => \weight_reg[13]_12\(3),
O => \weight[13][0]_i_2_n_0\
);
\weight[13][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_89\,
I1 => \weight_reg[13]_12\(2),
O => \weight[13][0]_i_3_n_0\
);
\weight[13][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_90\,
I1 => \weight_reg[13]_12\(1),
O => \weight[13][0]_i_4_n_0\
);
\weight[13][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_91\,
I1 => \weight_reg[13]_12\(0),
O => \weight[13][0]_i_5_n_0\
);
\weight[13][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_76\,
I1 => \weight_reg[13]_12\(15),
O => \weight[13][12]_i_2_n_0\
);
\weight[13][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_77\,
I1 => \weight_reg[13]_12\(14),
O => \weight[13][12]_i_3_n_0\
);
\weight[13][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_78\,
I1 => \weight_reg[13]_12\(13),
O => \weight[13][12]_i_4_n_0\
);
\weight[13][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_79\,
I1 => \weight_reg[13]_12\(12),
O => \weight[13][12]_i_5_n_0\
);
\weight[13][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_84\,
I1 => \weight_reg[13]_12\(7),
O => \weight[13][4]_i_2_n_0\
);
\weight[13][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_85\,
I1 => \weight_reg[13]_12\(6),
O => \weight[13][4]_i_3_n_0\
);
\weight[13][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_86\,
I1 => \weight_reg[13]_12\(5),
O => \weight[13][4]_i_4_n_0\
);
\weight[13][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_87\,
I1 => \weight_reg[13]_12\(4),
O => \weight[13][4]_i_5_n_0\
);
\weight[13][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_80\,
I1 => \weight_reg[13]_12\(11),
O => \weight[13][8]_i_2_n_0\
);
\weight[13][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_81\,
I1 => \weight_reg[13]_12\(10),
O => \weight[13][8]_i_3_n_0\
);
\weight[13][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_82\,
I1 => \weight_reg[13]_12\(9),
O => \weight[13][8]_i_4_n_0\
);
\weight[13][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_83\,
I1 => \weight_reg[13]_12\(8),
O => \weight[13][8]_i_5_n_0\
);
\weight[14][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_88\,
I1 => \weight_reg[14]_13\(3),
O => \weight[14][0]_i_2_n_0\
);
\weight[14][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_89\,
I1 => \weight_reg[14]_13\(2),
O => \weight[14][0]_i_3_n_0\
);
\weight[14][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_90\,
I1 => \weight_reg[14]_13\(1),
O => \weight[14][0]_i_4_n_0\
);
\weight[14][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_91\,
I1 => \weight_reg[14]_13\(0),
O => \weight[14][0]_i_5_n_0\
);
\weight[14][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_76\,
I1 => \weight_reg[14]_13\(15),
O => \weight[14][12]_i_2_n_0\
);
\weight[14][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_77\,
I1 => \weight_reg[14]_13\(14),
O => \weight[14][12]_i_3_n_0\
);
\weight[14][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_78\,
I1 => \weight_reg[14]_13\(13),
O => \weight[14][12]_i_4_n_0\
);
\weight[14][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_79\,
I1 => \weight_reg[14]_13\(12),
O => \weight[14][12]_i_5_n_0\
);
\weight[14][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_84\,
I1 => \weight_reg[14]_13\(7),
O => \weight[14][4]_i_2_n_0\
);
\weight[14][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_85\,
I1 => \weight_reg[14]_13\(6),
O => \weight[14][4]_i_3_n_0\
);
\weight[14][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_86\,
I1 => \weight_reg[14]_13\(5),
O => \weight[14][4]_i_4_n_0\
);
\weight[14][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_87\,
I1 => \weight_reg[14]_13\(4),
O => \weight[14][4]_i_5_n_0\
);
\weight[14][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_80\,
I1 => \weight_reg[14]_13\(11),
O => \weight[14][8]_i_2_n_0\
);
\weight[14][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_81\,
I1 => \weight_reg[14]_13\(10),
O => \weight[14][8]_i_3_n_0\
);
\weight[14][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_82\,
I1 => \weight_reg[14]_13\(9),
O => \weight[14][8]_i_4_n_0\
);
\weight[14][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_83\,
I1 => \weight_reg[14]_13\(8),
O => \weight[14][8]_i_5_n_0\
);
\weight[15][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_88\,
I1 => \weight_reg[15]_14\(3),
O => \weight[15][0]_i_2_n_0\
);
\weight[15][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_89\,
I1 => \weight_reg[15]_14\(2),
O => \weight[15][0]_i_3_n_0\
);
\weight[15][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_90\,
I1 => \weight_reg[15]_14\(1),
O => \weight[15][0]_i_4_n_0\
);
\weight[15][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_91\,
I1 => \weight_reg[15]_14\(0),
O => \weight[15][0]_i_5_n_0\
);
\weight[15][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_76\,
I1 => \weight_reg[15]_14\(15),
O => \weight[15][12]_i_2_n_0\
);
\weight[15][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_77\,
I1 => \weight_reg[15]_14\(14),
O => \weight[15][12]_i_3_n_0\
);
\weight[15][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_78\,
I1 => \weight_reg[15]_14\(13),
O => \weight[15][12]_i_4_n_0\
);
\weight[15][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_79\,
I1 => \weight_reg[15]_14\(12),
O => \weight[15][12]_i_5_n_0\
);
\weight[15][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_84\,
I1 => \weight_reg[15]_14\(7),
O => \weight[15][4]_i_2_n_0\
);
\weight[15][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_85\,
I1 => \weight_reg[15]_14\(6),
O => \weight[15][4]_i_3_n_0\
);
\weight[15][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_86\,
I1 => \weight_reg[15]_14\(5),
O => \weight[15][4]_i_4_n_0\
);
\weight[15][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_87\,
I1 => \weight_reg[15]_14\(4),
O => \weight[15][4]_i_5_n_0\
);
\weight[15][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_80\,
I1 => \weight_reg[15]_14\(11),
O => \weight[15][8]_i_2_n_0\
);
\weight[15][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_81\,
I1 => \weight_reg[15]_14\(10),
O => \weight[15][8]_i_3_n_0\
);
\weight[15][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_82\,
I1 => \weight_reg[15]_14\(9),
O => \weight[15][8]_i_4_n_0\
);
\weight[15][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_83\,
I1 => \weight_reg[15]_14\(8),
O => \weight[15][8]_i_5_n_0\
);
\weight[1][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(3),
I1 => \weight_reg[1]_0\(3),
O => \weight[1][0]_i_2_n_0\
);
\weight[1][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(2),
I1 => \weight_reg[1]_0\(2),
O => \weight[1][0]_i_3_n_0\
);
\weight[1][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(1),
I1 => \weight_reg[1]_0\(1),
O => \weight[1][0]_i_4_n_0\
);
\weight[1][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(0),
I1 => \weight_reg[1]_0\(0),
O => \weight[1][0]_i_5_n_0\
);
\weight[1][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(15),
I1 => \weight_reg[1]_0\(15),
O => \weight[1][12]_i_2_n_0\
);
\weight[1][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(14),
I1 => \weight_reg[1]_0\(14),
O => \weight[1][12]_i_3_n_0\
);
\weight[1][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(13),
I1 => \weight_reg[1]_0\(13),
O => \weight[1][12]_i_4_n_0\
);
\weight[1][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(12),
I1 => \weight_reg[1]_0\(12),
O => \weight[1][12]_i_5_n_0\
);
\weight[1][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(7),
I1 => \weight_reg[1]_0\(7),
O => \weight[1][4]_i_2_n_0\
);
\weight[1][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(6),
I1 => \weight_reg[1]_0\(6),
O => \weight[1][4]_i_3_n_0\
);
\weight[1][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(5),
I1 => \weight_reg[1]_0\(5),
O => \weight[1][4]_i_4_n_0\
);
\weight[1][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(4),
I1 => \weight_reg[1]_0\(4),
O => \weight[1][4]_i_5_n_0\
);
\weight[1][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(11),
I1 => \weight_reg[1]_0\(11),
O => \weight[1][8]_i_2_n_0\
);
\weight[1][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(10),
I1 => \weight_reg[1]_0\(10),
O => \weight[1][8]_i_3_n_0\
);
\weight[1][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(9),
I1 => \weight_reg[1]_0\(9),
O => \weight[1][8]_i_4_n_0\
);
\weight[1][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(8),
I1 => \weight_reg[1]_0\(8),
O => \weight[1][8]_i_5_n_0\
);
\weight[2][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_88\,
I1 => \weight_reg[2]_1\(3),
O => \weight[2][0]_i_2_n_0\
);
\weight[2][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_89\,
I1 => \weight_reg[2]_1\(2),
O => \weight[2][0]_i_3_n_0\
);
\weight[2][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_90\,
I1 => \weight_reg[2]_1\(1),
O => \weight[2][0]_i_4_n_0\
);
\weight[2][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_91\,
I1 => \weight_reg[2]_1\(0),
O => \weight[2][0]_i_5_n_0\
);
\weight[2][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_76\,
I1 => \weight_reg[2]_1\(15),
O => \weight[2][12]_i_2_n_0\
);
\weight[2][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_77\,
I1 => \weight_reg[2]_1\(14),
O => \weight[2][12]_i_3_n_0\
);
\weight[2][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_78\,
I1 => \weight_reg[2]_1\(13),
O => \weight[2][12]_i_4_n_0\
);
\weight[2][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_79\,
I1 => \weight_reg[2]_1\(12),
O => \weight[2][12]_i_5_n_0\
);
\weight[2][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_84\,
I1 => \weight_reg[2]_1\(7),
O => \weight[2][4]_i_2_n_0\
);
\weight[2][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_85\,
I1 => \weight_reg[2]_1\(6),
O => \weight[2][4]_i_3_n_0\
);
\weight[2][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_86\,
I1 => \weight_reg[2]_1\(5),
O => \weight[2][4]_i_4_n_0\
);
\weight[2][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_87\,
I1 => \weight_reg[2]_1\(4),
O => \weight[2][4]_i_5_n_0\
);
\weight[2][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_80\,
I1 => \weight_reg[2]_1\(11),
O => \weight[2][8]_i_2_n_0\
);
\weight[2][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_81\,
I1 => \weight_reg[2]_1\(10),
O => \weight[2][8]_i_3_n_0\
);
\weight[2][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_82\,
I1 => \weight_reg[2]_1\(9),
O => \weight[2][8]_i_4_n_0\
);
\weight[2][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_83\,
I1 => \weight_reg[2]_1\(8),
O => \weight[2][8]_i_5_n_0\
);
\weight[3][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_88\,
I1 => \weight_reg[3]_2\(3),
O => \weight[3][0]_i_2_n_0\
);
\weight[3][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_89\,
I1 => \weight_reg[3]_2\(2),
O => \weight[3][0]_i_3_n_0\
);
\weight[3][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_90\,
I1 => \weight_reg[3]_2\(1),
O => \weight[3][0]_i_4_n_0\
);
\weight[3][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_91\,
I1 => \weight_reg[3]_2\(0),
O => \weight[3][0]_i_5_n_0\
);
\weight[3][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_76\,
I1 => \weight_reg[3]_2\(15),
O => \weight[3][12]_i_2_n_0\
);
\weight[3][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_77\,
I1 => \weight_reg[3]_2\(14),
O => \weight[3][12]_i_3_n_0\
);
\weight[3][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_78\,
I1 => \weight_reg[3]_2\(13),
O => \weight[3][12]_i_4_n_0\
);
\weight[3][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_79\,
I1 => \weight_reg[3]_2\(12),
O => \weight[3][12]_i_5_n_0\
);
\weight[3][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_84\,
I1 => \weight_reg[3]_2\(7),
O => \weight[3][4]_i_2_n_0\
);
\weight[3][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_85\,
I1 => \weight_reg[3]_2\(6),
O => \weight[3][4]_i_3_n_0\
);
\weight[3][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_86\,
I1 => \weight_reg[3]_2\(5),
O => \weight[3][4]_i_4_n_0\
);
\weight[3][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_87\,
I1 => \weight_reg[3]_2\(4),
O => \weight[3][4]_i_5_n_0\
);
\weight[3][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_80\,
I1 => \weight_reg[3]_2\(11),
O => \weight[3][8]_i_2_n_0\
);
\weight[3][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_81\,
I1 => \weight_reg[3]_2\(10),
O => \weight[3][8]_i_3_n_0\
);
\weight[3][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_82\,
I1 => \weight_reg[3]_2\(9),
O => \weight[3][8]_i_4_n_0\
);
\weight[3][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_83\,
I1 => \weight_reg[3]_2\(8),
O => \weight[3][8]_i_5_n_0\
);
\weight[4][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_88\,
I1 => \weight_reg[4]_3\(3),
O => \weight[4][0]_i_2_n_0\
);
\weight[4][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_89\,
I1 => \weight_reg[4]_3\(2),
O => \weight[4][0]_i_3_n_0\
);
\weight[4][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_90\,
I1 => \weight_reg[4]_3\(1),
O => \weight[4][0]_i_4_n_0\
);
\weight[4][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_91\,
I1 => \weight_reg[4]_3\(0),
O => \weight[4][0]_i_5_n_0\
);
\weight[4][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_76\,
I1 => \weight_reg[4]_3\(15),
O => \weight[4][12]_i_2_n_0\
);
\weight[4][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_77\,
I1 => \weight_reg[4]_3\(14),
O => \weight[4][12]_i_3_n_0\
);
\weight[4][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_78\,
I1 => \weight_reg[4]_3\(13),
O => \weight[4][12]_i_4_n_0\
);
\weight[4][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_79\,
I1 => \weight_reg[4]_3\(12),
O => \weight[4][12]_i_5_n_0\
);
\weight[4][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_84\,
I1 => \weight_reg[4]_3\(7),
O => \weight[4][4]_i_2_n_0\
);
\weight[4][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_85\,
I1 => \weight_reg[4]_3\(6),
O => \weight[4][4]_i_3_n_0\
);
\weight[4][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_86\,
I1 => \weight_reg[4]_3\(5),
O => \weight[4][4]_i_4_n_0\
);
\weight[4][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_87\,
I1 => \weight_reg[4]_3\(4),
O => \weight[4][4]_i_5_n_0\
);
\weight[4][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_80\,
I1 => \weight_reg[4]_3\(11),
O => \weight[4][8]_i_2_n_0\
);
\weight[4][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_81\,
I1 => \weight_reg[4]_3\(10),
O => \weight[4][8]_i_3_n_0\
);
\weight[4][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_82\,
I1 => \weight_reg[4]_3\(9),
O => \weight[4][8]_i_4_n_0\
);
\weight[4][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_83\,
I1 => \weight_reg[4]_3\(8),
O => \weight[4][8]_i_5_n_0\
);
\weight[5][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_88\,
I1 => \weight_reg[5]_4\(3),
O => \weight[5][0]_i_2_n_0\
);
\weight[5][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_89\,
I1 => \weight_reg[5]_4\(2),
O => \weight[5][0]_i_3_n_0\
);
\weight[5][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_90\,
I1 => \weight_reg[5]_4\(1),
O => \weight[5][0]_i_4_n_0\
);
\weight[5][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_91\,
I1 => \weight_reg[5]_4\(0),
O => \weight[5][0]_i_5_n_0\
);
\weight[5][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_76\,
I1 => \weight_reg[5]_4\(15),
O => \weight[5][12]_i_2_n_0\
);
\weight[5][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_77\,
I1 => \weight_reg[5]_4\(14),
O => \weight[5][12]_i_3_n_0\
);
\weight[5][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_78\,
I1 => \weight_reg[5]_4\(13),
O => \weight[5][12]_i_4_n_0\
);
\weight[5][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_79\,
I1 => \weight_reg[5]_4\(12),
O => \weight[5][12]_i_5_n_0\
);
\weight[5][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_84\,
I1 => \weight_reg[5]_4\(7),
O => \weight[5][4]_i_2_n_0\
);
\weight[5][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_85\,
I1 => \weight_reg[5]_4\(6),
O => \weight[5][4]_i_3_n_0\
);
\weight[5][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_86\,
I1 => \weight_reg[5]_4\(5),
O => \weight[5][4]_i_4_n_0\
);
\weight[5][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_87\,
I1 => \weight_reg[5]_4\(4),
O => \weight[5][4]_i_5_n_0\
);
\weight[5][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_80\,
I1 => \weight_reg[5]_4\(11),
O => \weight[5][8]_i_2_n_0\
);
\weight[5][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_81\,
I1 => \weight_reg[5]_4\(10),
O => \weight[5][8]_i_3_n_0\
);
\weight[5][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_82\,
I1 => \weight_reg[5]_4\(9),
O => \weight[5][8]_i_4_n_0\
);
\weight[5][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_83\,
I1 => \weight_reg[5]_4\(8),
O => \weight[5][8]_i_5_n_0\
);
\weight[6][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_88\,
I1 => \weight_reg[6]_5\(3),
O => \weight[6][0]_i_2_n_0\
);
\weight[6][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_89\,
I1 => \weight_reg[6]_5\(2),
O => \weight[6][0]_i_3_n_0\
);
\weight[6][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_90\,
I1 => \weight_reg[6]_5\(1),
O => \weight[6][0]_i_4_n_0\
);
\weight[6][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_91\,
I1 => \weight_reg[6]_5\(0),
O => \weight[6][0]_i_5_n_0\
);
\weight[6][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_76\,
I1 => \weight_reg[6]_5\(15),
O => \weight[6][12]_i_2_n_0\
);
\weight[6][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_77\,
I1 => \weight_reg[6]_5\(14),
O => \weight[6][12]_i_3_n_0\
);
\weight[6][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_78\,
I1 => \weight_reg[6]_5\(13),
O => \weight[6][12]_i_4_n_0\
);
\weight[6][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_79\,
I1 => \weight_reg[6]_5\(12),
O => \weight[6][12]_i_5_n_0\
);
\weight[6][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_84\,
I1 => \weight_reg[6]_5\(7),
O => \weight[6][4]_i_2_n_0\
);
\weight[6][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_85\,
I1 => \weight_reg[6]_5\(6),
O => \weight[6][4]_i_3_n_0\
);
\weight[6][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_86\,
I1 => \weight_reg[6]_5\(5),
O => \weight[6][4]_i_4_n_0\
);
\weight[6][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_87\,
I1 => \weight_reg[6]_5\(4),
O => \weight[6][4]_i_5_n_0\
);
\weight[6][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_80\,
I1 => \weight_reg[6]_5\(11),
O => \weight[6][8]_i_2_n_0\
);
\weight[6][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_81\,
I1 => \weight_reg[6]_5\(10),
O => \weight[6][8]_i_3_n_0\
);
\weight[6][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_82\,
I1 => \weight_reg[6]_5\(9),
O => \weight[6][8]_i_4_n_0\
);
\weight[6][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_83\,
I1 => \weight_reg[6]_5\(8),
O => \weight[6][8]_i_5_n_0\
);
\weight[7][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_88\,
I1 => \weight_reg[7]_6\(3),
O => \weight[7][0]_i_2_n_0\
);
\weight[7][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_89\,
I1 => \weight_reg[7]_6\(2),
O => \weight[7][0]_i_3_n_0\
);
\weight[7][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_90\,
I1 => \weight_reg[7]_6\(1),
O => \weight[7][0]_i_4_n_0\
);
\weight[7][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_91\,
I1 => \weight_reg[7]_6\(0),
O => \weight[7][0]_i_5_n_0\
);
\weight[7][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_76\,
I1 => \weight_reg[7]_6\(15),
O => \weight[7][12]_i_2_n_0\
);
\weight[7][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_77\,
I1 => \weight_reg[7]_6\(14),
O => \weight[7][12]_i_3_n_0\
);
\weight[7][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_78\,
I1 => \weight_reg[7]_6\(13),
O => \weight[7][12]_i_4_n_0\
);
\weight[7][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_79\,
I1 => \weight_reg[7]_6\(12),
O => \weight[7][12]_i_5_n_0\
);
\weight[7][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_84\,
I1 => \weight_reg[7]_6\(7),
O => \weight[7][4]_i_2_n_0\
);
\weight[7][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_85\,
I1 => \weight_reg[7]_6\(6),
O => \weight[7][4]_i_3_n_0\
);
\weight[7][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_86\,
I1 => \weight_reg[7]_6\(5),
O => \weight[7][4]_i_4_n_0\
);
\weight[7][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_87\,
I1 => \weight_reg[7]_6\(4),
O => \weight[7][4]_i_5_n_0\
);
\weight[7][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_80\,
I1 => \weight_reg[7]_6\(11),
O => \weight[7][8]_i_2_n_0\
);
\weight[7][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_81\,
I1 => \weight_reg[7]_6\(10),
O => \weight[7][8]_i_3_n_0\
);
\weight[7][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_82\,
I1 => \weight_reg[7]_6\(9),
O => \weight[7][8]_i_4_n_0\
);
\weight[7][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_83\,
I1 => \weight_reg[7]_6\(8),
O => \weight[7][8]_i_5_n_0\
);
\weight[8][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_88\,
I1 => \weight_reg[8]_7\(3),
O => \weight[8][0]_i_2_n_0\
);
\weight[8][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_89\,
I1 => \weight_reg[8]_7\(2),
O => \weight[8][0]_i_3_n_0\
);
\weight[8][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_90\,
I1 => \weight_reg[8]_7\(1),
O => \weight[8][0]_i_4_n_0\
);
\weight[8][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_91\,
I1 => \weight_reg[8]_7\(0),
O => \weight[8][0]_i_5_n_0\
);
\weight[8][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_76\,
I1 => \weight_reg[8]_7\(15),
O => \weight[8][12]_i_2_n_0\
);
\weight[8][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_77\,
I1 => \weight_reg[8]_7\(14),
O => \weight[8][12]_i_3_n_0\
);
\weight[8][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_78\,
I1 => \weight_reg[8]_7\(13),
O => \weight[8][12]_i_4_n_0\
);
\weight[8][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_79\,
I1 => \weight_reg[8]_7\(12),
O => \weight[8][12]_i_5_n_0\
);
\weight[8][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_84\,
I1 => \weight_reg[8]_7\(7),
O => \weight[8][4]_i_2_n_0\
);
\weight[8][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_85\,
I1 => \weight_reg[8]_7\(6),
O => \weight[8][4]_i_3_n_0\
);
\weight[8][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_86\,
I1 => \weight_reg[8]_7\(5),
O => \weight[8][4]_i_4_n_0\
);
\weight[8][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_87\,
I1 => \weight_reg[8]_7\(4),
O => \weight[8][4]_i_5_n_0\
);
\weight[8][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_80\,
I1 => \weight_reg[8]_7\(11),
O => \weight[8][8]_i_2_n_0\
);
\weight[8][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_81\,
I1 => \weight_reg[8]_7\(10),
O => \weight[8][8]_i_3_n_0\
);
\weight[8][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_82\,
I1 => \weight_reg[8]_7\(9),
O => \weight[8][8]_i_4_n_0\
);
\weight[8][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_83\,
I1 => \weight_reg[8]_7\(8),
O => \weight[8][8]_i_5_n_0\
);
\weight[9][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_88\,
I1 => \weight_reg[9]_8\(3),
O => \weight[9][0]_i_2_n_0\
);
\weight[9][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_89\,
I1 => \weight_reg[9]_8\(2),
O => \weight[9][0]_i_3_n_0\
);
\weight[9][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_90\,
I1 => \weight_reg[9]_8\(1),
O => \weight[9][0]_i_4_n_0\
);
\weight[9][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_91\,
I1 => \weight_reg[9]_8\(0),
O => \weight[9][0]_i_5_n_0\
);
\weight[9][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_76\,
I1 => \weight_reg[9]_8\(15),
O => \weight[9][12]_i_2_n_0\
);
\weight[9][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_77\,
I1 => \weight_reg[9]_8\(14),
O => \weight[9][12]_i_3_n_0\
);
\weight[9][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_78\,
I1 => \weight_reg[9]_8\(13),
O => \weight[9][12]_i_4_n_0\
);
\weight[9][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_79\,
I1 => \weight_reg[9]_8\(12),
O => \weight[9][12]_i_5_n_0\
);
\weight[9][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_84\,
I1 => \weight_reg[9]_8\(7),
O => \weight[9][4]_i_2_n_0\
);
\weight[9][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_85\,
I1 => \weight_reg[9]_8\(6),
O => \weight[9][4]_i_3_n_0\
);
\weight[9][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_86\,
I1 => \weight_reg[9]_8\(5),
O => \weight[9][4]_i_4_n_0\
);
\weight[9][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_87\,
I1 => \weight_reg[9]_8\(4),
O => \weight[9][4]_i_5_n_0\
);
\weight[9][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_80\,
I1 => \weight_reg[9]_8\(11),
O => \weight[9][8]_i_2_n_0\
);
\weight[9][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_81\,
I1 => \weight_reg[9]_8\(10),
O => \weight[9][8]_i_3_n_0\
);
\weight[9][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_82\,
I1 => \weight_reg[9]_8\(9),
O => \weight[9][8]_i_4_n_0\
);
\weight[9][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_83\,
I1 => \weight_reg[9]_8\(8),
O => \weight[9][8]_i_5_n_0\
);
\weight_reg[0][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][0]_i_1_n_7\,
Q => \weight_reg[0]_15\(0)
);
\weight_reg[0][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[0][0]_i_1_n_0\,
CO(2) => \weight_reg[0][0]_i_1_n_1\,
CO(1) => \weight_reg[0][0]_i_1_n_2\,
CO(0) => \weight_reg[0][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__29_n_88\,
DI(2) => \ARG__29_n_89\,
DI(1) => \ARG__29_n_90\,
DI(0) => \ARG__29_n_91\,
O(3) => \weight_reg[0][0]_i_1_n_4\,
O(2) => \weight_reg[0][0]_i_1_n_5\,
O(1) => \weight_reg[0][0]_i_1_n_6\,
O(0) => \weight_reg[0][0]_i_1_n_7\,
S(3) => \weight[0][0]_i_2_n_0\,
S(2) => \weight[0][0]_i_3_n_0\,
S(1) => \weight[0][0]_i_4_n_0\,
S(0) => \weight[0][0]_i_5_n_0\
);
\weight_reg[0][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][8]_i_1_n_5\,
Q => \weight_reg[0]_15\(10)
);
\weight_reg[0][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][8]_i_1_n_4\,
Q => \weight_reg[0]_15\(11)
);
\weight_reg[0][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][12]_i_1_n_7\,
Q => \weight_reg[0]_15\(12)
);
\weight_reg[0][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[0][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[0][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[0][12]_i_1_n_1\,
CO(1) => \weight_reg[0][12]_i_1_n_2\,
CO(0) => \weight_reg[0][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__29_n_77\,
DI(1) => \ARG__29_n_78\,
DI(0) => \ARG__29_n_79\,
O(3) => \weight_reg[0][12]_i_1_n_4\,
O(2) => \weight_reg[0][12]_i_1_n_5\,
O(1) => \weight_reg[0][12]_i_1_n_6\,
O(0) => \weight_reg[0][12]_i_1_n_7\,
S(3) => \weight[0][12]_i_2_n_0\,
S(2) => \weight[0][12]_i_3_n_0\,
S(1) => \weight[0][12]_i_4_n_0\,
S(0) => \weight[0][12]_i_5_n_0\
);
\weight_reg[0][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][12]_i_1_n_6\,
Q => \weight_reg[0]_15\(13)
);
\weight_reg[0][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][12]_i_1_n_5\,
Q => \weight_reg[0]_15\(14)
);
\weight_reg[0][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][12]_i_1_n_4\,
Q => \weight_reg[0]_15\(15)
);
\weight_reg[0][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][0]_i_1_n_6\,
Q => \weight_reg[0]_15\(1)
);
\weight_reg[0][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][0]_i_1_n_5\,
Q => \weight_reg[0]_15\(2)
);
\weight_reg[0][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][0]_i_1_n_4\,
Q => \weight_reg[0]_15\(3)
);
\weight_reg[0][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][4]_i_1_n_7\,
Q => \weight_reg[0]_15\(4)
);
\weight_reg[0][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[0][0]_i_1_n_0\,
CO(3) => \weight_reg[0][4]_i_1_n_0\,
CO(2) => \weight_reg[0][4]_i_1_n_1\,
CO(1) => \weight_reg[0][4]_i_1_n_2\,
CO(0) => \weight_reg[0][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__29_n_84\,
DI(2) => \ARG__29_n_85\,
DI(1) => \ARG__29_n_86\,
DI(0) => \ARG__29_n_87\,
O(3) => \weight_reg[0][4]_i_1_n_4\,
O(2) => \weight_reg[0][4]_i_1_n_5\,
O(1) => \weight_reg[0][4]_i_1_n_6\,
O(0) => \weight_reg[0][4]_i_1_n_7\,
S(3) => \weight[0][4]_i_2_n_0\,
S(2) => \weight[0][4]_i_3_n_0\,
S(1) => \weight[0][4]_i_4_n_0\,
S(0) => \weight[0][4]_i_5_n_0\
);
\weight_reg[0][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][4]_i_1_n_6\,
Q => \weight_reg[0]_15\(5)
);
\weight_reg[0][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][4]_i_1_n_5\,
Q => \weight_reg[0]_15\(6)
);
\weight_reg[0][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][4]_i_1_n_4\,
Q => \weight_reg[0]_15\(7)
);
\weight_reg[0][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][8]_i_1_n_7\,
Q => \weight_reg[0]_15\(8)
);
\weight_reg[0][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[0][4]_i_1_n_0\,
CO(3) => \weight_reg[0][8]_i_1_n_0\,
CO(2) => \weight_reg[0][8]_i_1_n_1\,
CO(1) => \weight_reg[0][8]_i_1_n_2\,
CO(0) => \weight_reg[0][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__29_n_80\,
DI(2) => \ARG__29_n_81\,
DI(1) => \ARG__29_n_82\,
DI(0) => \ARG__29_n_83\,
O(3) => \weight_reg[0][8]_i_1_n_4\,
O(2) => \weight_reg[0][8]_i_1_n_5\,
O(1) => \weight_reg[0][8]_i_1_n_6\,
O(0) => \weight_reg[0][8]_i_1_n_7\,
S(3) => \weight[0][8]_i_2_n_0\,
S(2) => \weight[0][8]_i_3_n_0\,
S(1) => \weight[0][8]_i_4_n_0\,
S(0) => \weight[0][8]_i_5_n_0\
);
\weight_reg[0][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][8]_i_1_n_6\,
Q => \weight_reg[0]_15\(9)
);
\weight_reg[10][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][0]_i_1_n_7\,
Q => \weight_reg[10]_9\(0)
);
\weight_reg[10][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[10][0]_i_1_n_0\,
CO(2) => \weight_reg[10][0]_i_1_n_1\,
CO(1) => \weight_reg[10][0]_i_1_n_2\,
CO(0) => \weight_reg[10][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__17_n_88\,
DI(2) => \ARG__17_n_89\,
DI(1) => \ARG__17_n_90\,
DI(0) => \ARG__17_n_91\,
O(3) => \weight_reg[10][0]_i_1_n_4\,
O(2) => \weight_reg[10][0]_i_1_n_5\,
O(1) => \weight_reg[10][0]_i_1_n_6\,
O(0) => \weight_reg[10][0]_i_1_n_7\,
S(3) => \weight[10][0]_i_2_n_0\,
S(2) => \weight[10][0]_i_3_n_0\,
S(1) => \weight[10][0]_i_4_n_0\,
S(0) => \weight[10][0]_i_5_n_0\
);
\weight_reg[10][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][8]_i_1_n_5\,
Q => \weight_reg[10]_9\(10)
);
\weight_reg[10][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][8]_i_1_n_4\,
Q => \weight_reg[10]_9\(11)
);
\weight_reg[10][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][12]_i_1_n_7\,
Q => \weight_reg[10]_9\(12)
);
\weight_reg[10][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[10][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[10][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[10][12]_i_1_n_1\,
CO(1) => \weight_reg[10][12]_i_1_n_2\,
CO(0) => \weight_reg[10][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__17_n_77\,
DI(1) => \ARG__17_n_78\,
DI(0) => \ARG__17_n_79\,
O(3) => \weight_reg[10][12]_i_1_n_4\,
O(2) => \weight_reg[10][12]_i_1_n_5\,
O(1) => \weight_reg[10][12]_i_1_n_6\,
O(0) => \weight_reg[10][12]_i_1_n_7\,
S(3) => \weight[10][12]_i_2_n_0\,
S(2) => \weight[10][12]_i_3_n_0\,
S(1) => \weight[10][12]_i_4_n_0\,
S(0) => \weight[10][12]_i_5_n_0\
);
\weight_reg[10][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][12]_i_1_n_6\,
Q => \weight_reg[10]_9\(13)
);
\weight_reg[10][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][12]_i_1_n_5\,
Q => \weight_reg[10]_9\(14)
);
\weight_reg[10][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][12]_i_1_n_4\,
Q => \weight_reg[10]_9\(15)
);
\weight_reg[10][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][0]_i_1_n_6\,
Q => \weight_reg[10]_9\(1)
);
\weight_reg[10][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][0]_i_1_n_5\,
Q => \weight_reg[10]_9\(2)
);
\weight_reg[10][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][0]_i_1_n_4\,
Q => \weight_reg[10]_9\(3)
);
\weight_reg[10][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][4]_i_1_n_7\,
Q => \weight_reg[10]_9\(4)
);
\weight_reg[10][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[10][0]_i_1_n_0\,
CO(3) => \weight_reg[10][4]_i_1_n_0\,
CO(2) => \weight_reg[10][4]_i_1_n_1\,
CO(1) => \weight_reg[10][4]_i_1_n_2\,
CO(0) => \weight_reg[10][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__17_n_84\,
DI(2) => \ARG__17_n_85\,
DI(1) => \ARG__17_n_86\,
DI(0) => \ARG__17_n_87\,
O(3) => \weight_reg[10][4]_i_1_n_4\,
O(2) => \weight_reg[10][4]_i_1_n_5\,
O(1) => \weight_reg[10][4]_i_1_n_6\,
O(0) => \weight_reg[10][4]_i_1_n_7\,
S(3) => \weight[10][4]_i_2_n_0\,
S(2) => \weight[10][4]_i_3_n_0\,
S(1) => \weight[10][4]_i_4_n_0\,
S(0) => \weight[10][4]_i_5_n_0\
);
\weight_reg[10][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][4]_i_1_n_6\,
Q => \weight_reg[10]_9\(5)
);
\weight_reg[10][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][4]_i_1_n_5\,
Q => \weight_reg[10]_9\(6)
);
\weight_reg[10][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][4]_i_1_n_4\,
Q => \weight_reg[10]_9\(7)
);
\weight_reg[10][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][8]_i_1_n_7\,
Q => \weight_reg[10]_9\(8)
);
\weight_reg[10][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[10][4]_i_1_n_0\,
CO(3) => \weight_reg[10][8]_i_1_n_0\,
CO(2) => \weight_reg[10][8]_i_1_n_1\,
CO(1) => \weight_reg[10][8]_i_1_n_2\,
CO(0) => \weight_reg[10][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__17_n_80\,
DI(2) => \ARG__17_n_81\,
DI(1) => \ARG__17_n_82\,
DI(0) => \ARG__17_n_83\,
O(3) => \weight_reg[10][8]_i_1_n_4\,
O(2) => \weight_reg[10][8]_i_1_n_5\,
O(1) => \weight_reg[10][8]_i_1_n_6\,
O(0) => \weight_reg[10][8]_i_1_n_7\,
S(3) => \weight[10][8]_i_2_n_0\,
S(2) => \weight[10][8]_i_3_n_0\,
S(1) => \weight[10][8]_i_4_n_0\,
S(0) => \weight[10][8]_i_5_n_0\
);
\weight_reg[10][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][8]_i_1_n_6\,
Q => \weight_reg[10]_9\(9)
);
\weight_reg[11][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][0]_i_1_n_7\,
Q => \weight_reg[11]_10\(0)
);
\weight_reg[11][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[11][0]_i_1_n_0\,
CO(2) => \weight_reg[11][0]_i_1_n_1\,
CO(1) => \weight_reg[11][0]_i_1_n_2\,
CO(0) => \weight_reg[11][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__19_n_88\,
DI(2) => \ARG__19_n_89\,
DI(1) => \ARG__19_n_90\,
DI(0) => \ARG__19_n_91\,
O(3) => \weight_reg[11][0]_i_1_n_4\,
O(2) => \weight_reg[11][0]_i_1_n_5\,
O(1) => \weight_reg[11][0]_i_1_n_6\,
O(0) => \weight_reg[11][0]_i_1_n_7\,
S(3) => \weight[11][0]_i_2_n_0\,
S(2) => \weight[11][0]_i_3_n_0\,
S(1) => \weight[11][0]_i_4_n_0\,
S(0) => \weight[11][0]_i_5_n_0\
);
\weight_reg[11][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][8]_i_1_n_5\,
Q => \weight_reg[11]_10\(10)
);
\weight_reg[11][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][8]_i_1_n_4\,
Q => \weight_reg[11]_10\(11)
);
\weight_reg[11][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][12]_i_1_n_7\,
Q => \weight_reg[11]_10\(12)
);
\weight_reg[11][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[11][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[11][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[11][12]_i_1_n_1\,
CO(1) => \weight_reg[11][12]_i_1_n_2\,
CO(0) => \weight_reg[11][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__19_n_77\,
DI(1) => \ARG__19_n_78\,
DI(0) => \ARG__19_n_79\,
O(3) => \weight_reg[11][12]_i_1_n_4\,
O(2) => \weight_reg[11][12]_i_1_n_5\,
O(1) => \weight_reg[11][12]_i_1_n_6\,
O(0) => \weight_reg[11][12]_i_1_n_7\,
S(3) => \weight[11][12]_i_2_n_0\,
S(2) => \weight[11][12]_i_3_n_0\,
S(1) => \weight[11][12]_i_4_n_0\,
S(0) => \weight[11][12]_i_5_n_0\
);
\weight_reg[11][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][12]_i_1_n_6\,
Q => \weight_reg[11]_10\(13)
);
\weight_reg[11][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][12]_i_1_n_5\,
Q => \weight_reg[11]_10\(14)
);
\weight_reg[11][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][12]_i_1_n_4\,
Q => \weight_reg[11]_10\(15)
);
\weight_reg[11][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][0]_i_1_n_6\,
Q => \weight_reg[11]_10\(1)
);
\weight_reg[11][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][0]_i_1_n_5\,
Q => \weight_reg[11]_10\(2)
);
\weight_reg[11][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][0]_i_1_n_4\,
Q => \weight_reg[11]_10\(3)
);
\weight_reg[11][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][4]_i_1_n_7\,
Q => \weight_reg[11]_10\(4)
);
\weight_reg[11][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[11][0]_i_1_n_0\,
CO(3) => \weight_reg[11][4]_i_1_n_0\,
CO(2) => \weight_reg[11][4]_i_1_n_1\,
CO(1) => \weight_reg[11][4]_i_1_n_2\,
CO(0) => \weight_reg[11][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__19_n_84\,
DI(2) => \ARG__19_n_85\,
DI(1) => \ARG__19_n_86\,
DI(0) => \ARG__19_n_87\,
O(3) => \weight_reg[11][4]_i_1_n_4\,
O(2) => \weight_reg[11][4]_i_1_n_5\,
O(1) => \weight_reg[11][4]_i_1_n_6\,
O(0) => \weight_reg[11][4]_i_1_n_7\,
S(3) => \weight[11][4]_i_2_n_0\,
S(2) => \weight[11][4]_i_3_n_0\,
S(1) => \weight[11][4]_i_4_n_0\,
S(0) => \weight[11][4]_i_5_n_0\
);
\weight_reg[11][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][4]_i_1_n_6\,
Q => \weight_reg[11]_10\(5)
);
\weight_reg[11][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][4]_i_1_n_5\,
Q => \weight_reg[11]_10\(6)
);
\weight_reg[11][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][4]_i_1_n_4\,
Q => \weight_reg[11]_10\(7)
);
\weight_reg[11][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][8]_i_1_n_7\,
Q => \weight_reg[11]_10\(8)
);
\weight_reg[11][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[11][4]_i_1_n_0\,
CO(3) => \weight_reg[11][8]_i_1_n_0\,
CO(2) => \weight_reg[11][8]_i_1_n_1\,
CO(1) => \weight_reg[11][8]_i_1_n_2\,
CO(0) => \weight_reg[11][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__19_n_80\,
DI(2) => \ARG__19_n_81\,
DI(1) => \ARG__19_n_82\,
DI(0) => \ARG__19_n_83\,
O(3) => \weight_reg[11][8]_i_1_n_4\,
O(2) => \weight_reg[11][8]_i_1_n_5\,
O(1) => \weight_reg[11][8]_i_1_n_6\,
O(0) => \weight_reg[11][8]_i_1_n_7\,
S(3) => \weight[11][8]_i_2_n_0\,
S(2) => \weight[11][8]_i_3_n_0\,
S(1) => \weight[11][8]_i_4_n_0\,
S(0) => \weight[11][8]_i_5_n_0\
);
\weight_reg[11][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][8]_i_1_n_6\,
Q => \weight_reg[11]_10\(9)
);
\weight_reg[12][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][0]_i_1_n_7\,
Q => \weight_reg[12]_11\(0)
);
\weight_reg[12][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[12][0]_i_1_n_0\,
CO(2) => \weight_reg[12][0]_i_1_n_1\,
CO(1) => \weight_reg[12][0]_i_1_n_2\,
CO(0) => \weight_reg[12][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__21_n_88\,
DI(2) => \ARG__21_n_89\,
DI(1) => \ARG__21_n_90\,
DI(0) => \ARG__21_n_91\,
O(3) => \weight_reg[12][0]_i_1_n_4\,
O(2) => \weight_reg[12][0]_i_1_n_5\,
O(1) => \weight_reg[12][0]_i_1_n_6\,
O(0) => \weight_reg[12][0]_i_1_n_7\,
S(3) => \weight[12][0]_i_2_n_0\,
S(2) => \weight[12][0]_i_3_n_0\,
S(1) => \weight[12][0]_i_4_n_0\,
S(0) => \weight[12][0]_i_5_n_0\
);
\weight_reg[12][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][8]_i_1_n_5\,
Q => \weight_reg[12]_11\(10)
);
\weight_reg[12][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][8]_i_1_n_4\,
Q => \weight_reg[12]_11\(11)
);
\weight_reg[12][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][12]_i_1_n_7\,
Q => \weight_reg[12]_11\(12)
);
\weight_reg[12][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[12][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[12][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[12][12]_i_1_n_1\,
CO(1) => \weight_reg[12][12]_i_1_n_2\,
CO(0) => \weight_reg[12][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__21_n_77\,
DI(1) => \ARG__21_n_78\,
DI(0) => \ARG__21_n_79\,
O(3) => \weight_reg[12][12]_i_1_n_4\,
O(2) => \weight_reg[12][12]_i_1_n_5\,
O(1) => \weight_reg[12][12]_i_1_n_6\,
O(0) => \weight_reg[12][12]_i_1_n_7\,
S(3) => \weight[12][12]_i_2_n_0\,
S(2) => \weight[12][12]_i_3_n_0\,
S(1) => \weight[12][12]_i_4_n_0\,
S(0) => \weight[12][12]_i_5_n_0\
);
\weight_reg[12][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][12]_i_1_n_6\,
Q => \weight_reg[12]_11\(13)
);
\weight_reg[12][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][12]_i_1_n_5\,
Q => \weight_reg[12]_11\(14)
);
\weight_reg[12][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][12]_i_1_n_4\,
Q => \weight_reg[12]_11\(15)
);
\weight_reg[12][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][0]_i_1_n_6\,
Q => \weight_reg[12]_11\(1)
);
\weight_reg[12][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][0]_i_1_n_5\,
Q => \weight_reg[12]_11\(2)
);
\weight_reg[12][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][0]_i_1_n_4\,
Q => \weight_reg[12]_11\(3)
);
\weight_reg[12][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][4]_i_1_n_7\,
Q => \weight_reg[12]_11\(4)
);
\weight_reg[12][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[12][0]_i_1_n_0\,
CO(3) => \weight_reg[12][4]_i_1_n_0\,
CO(2) => \weight_reg[12][4]_i_1_n_1\,
CO(1) => \weight_reg[12][4]_i_1_n_2\,
CO(0) => \weight_reg[12][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__21_n_84\,
DI(2) => \ARG__21_n_85\,
DI(1) => \ARG__21_n_86\,
DI(0) => \ARG__21_n_87\,
O(3) => \weight_reg[12][4]_i_1_n_4\,
O(2) => \weight_reg[12][4]_i_1_n_5\,
O(1) => \weight_reg[12][4]_i_1_n_6\,
O(0) => \weight_reg[12][4]_i_1_n_7\,
S(3) => \weight[12][4]_i_2_n_0\,
S(2) => \weight[12][4]_i_3_n_0\,
S(1) => \weight[12][4]_i_4_n_0\,
S(0) => \weight[12][4]_i_5_n_0\
);
\weight_reg[12][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][4]_i_1_n_6\,
Q => \weight_reg[12]_11\(5)
);
\weight_reg[12][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][4]_i_1_n_5\,
Q => \weight_reg[12]_11\(6)
);
\weight_reg[12][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][4]_i_1_n_4\,
Q => \weight_reg[12]_11\(7)
);
\weight_reg[12][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][8]_i_1_n_7\,
Q => \weight_reg[12]_11\(8)
);
\weight_reg[12][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[12][4]_i_1_n_0\,
CO(3) => \weight_reg[12][8]_i_1_n_0\,
CO(2) => \weight_reg[12][8]_i_1_n_1\,
CO(1) => \weight_reg[12][8]_i_1_n_2\,
CO(0) => \weight_reg[12][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__21_n_80\,
DI(2) => \ARG__21_n_81\,
DI(1) => \ARG__21_n_82\,
DI(0) => \ARG__21_n_83\,
O(3) => \weight_reg[12][8]_i_1_n_4\,
O(2) => \weight_reg[12][8]_i_1_n_5\,
O(1) => \weight_reg[12][8]_i_1_n_6\,
O(0) => \weight_reg[12][8]_i_1_n_7\,
S(3) => \weight[12][8]_i_2_n_0\,
S(2) => \weight[12][8]_i_3_n_0\,
S(1) => \weight[12][8]_i_4_n_0\,
S(0) => \weight[12][8]_i_5_n_0\
);
\weight_reg[12][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][8]_i_1_n_6\,
Q => \weight_reg[12]_11\(9)
);
\weight_reg[13][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][0]_i_1_n_7\,
Q => \weight_reg[13]_12\(0)
);
\weight_reg[13][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[13][0]_i_1_n_0\,
CO(2) => \weight_reg[13][0]_i_1_n_1\,
CO(1) => \weight_reg[13][0]_i_1_n_2\,
CO(0) => \weight_reg[13][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__23_n_88\,
DI(2) => \ARG__23_n_89\,
DI(1) => \ARG__23_n_90\,
DI(0) => \ARG__23_n_91\,
O(3) => \weight_reg[13][0]_i_1_n_4\,
O(2) => \weight_reg[13][0]_i_1_n_5\,
O(1) => \weight_reg[13][0]_i_1_n_6\,
O(0) => \weight_reg[13][0]_i_1_n_7\,
S(3) => \weight[13][0]_i_2_n_0\,
S(2) => \weight[13][0]_i_3_n_0\,
S(1) => \weight[13][0]_i_4_n_0\,
S(0) => \weight[13][0]_i_5_n_0\
);
\weight_reg[13][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][8]_i_1_n_5\,
Q => \weight_reg[13]_12\(10)
);
\weight_reg[13][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][8]_i_1_n_4\,
Q => \weight_reg[13]_12\(11)
);
\weight_reg[13][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][12]_i_1_n_7\,
Q => \weight_reg[13]_12\(12)
);
\weight_reg[13][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[13][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[13][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[13][12]_i_1_n_1\,
CO(1) => \weight_reg[13][12]_i_1_n_2\,
CO(0) => \weight_reg[13][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__23_n_77\,
DI(1) => \ARG__23_n_78\,
DI(0) => \ARG__23_n_79\,
O(3) => \weight_reg[13][12]_i_1_n_4\,
O(2) => \weight_reg[13][12]_i_1_n_5\,
O(1) => \weight_reg[13][12]_i_1_n_6\,
O(0) => \weight_reg[13][12]_i_1_n_7\,
S(3) => \weight[13][12]_i_2_n_0\,
S(2) => \weight[13][12]_i_3_n_0\,
S(1) => \weight[13][12]_i_4_n_0\,
S(0) => \weight[13][12]_i_5_n_0\
);
\weight_reg[13][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][12]_i_1_n_6\,
Q => \weight_reg[13]_12\(13)
);
\weight_reg[13][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][12]_i_1_n_5\,
Q => \weight_reg[13]_12\(14)
);
\weight_reg[13][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][12]_i_1_n_4\,
Q => \weight_reg[13]_12\(15)
);
\weight_reg[13][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][0]_i_1_n_6\,
Q => \weight_reg[13]_12\(1)
);
\weight_reg[13][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][0]_i_1_n_5\,
Q => \weight_reg[13]_12\(2)
);
\weight_reg[13][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][0]_i_1_n_4\,
Q => \weight_reg[13]_12\(3)
);
\weight_reg[13][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][4]_i_1_n_7\,
Q => \weight_reg[13]_12\(4)
);
\weight_reg[13][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[13][0]_i_1_n_0\,
CO(3) => \weight_reg[13][4]_i_1_n_0\,
CO(2) => \weight_reg[13][4]_i_1_n_1\,
CO(1) => \weight_reg[13][4]_i_1_n_2\,
CO(0) => \weight_reg[13][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__23_n_84\,
DI(2) => \ARG__23_n_85\,
DI(1) => \ARG__23_n_86\,
DI(0) => \ARG__23_n_87\,
O(3) => \weight_reg[13][4]_i_1_n_4\,
O(2) => \weight_reg[13][4]_i_1_n_5\,
O(1) => \weight_reg[13][4]_i_1_n_6\,
O(0) => \weight_reg[13][4]_i_1_n_7\,
S(3) => \weight[13][4]_i_2_n_0\,
S(2) => \weight[13][4]_i_3_n_0\,
S(1) => \weight[13][4]_i_4_n_0\,
S(0) => \weight[13][4]_i_5_n_0\
);
\weight_reg[13][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][4]_i_1_n_6\,
Q => \weight_reg[13]_12\(5)
);
\weight_reg[13][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][4]_i_1_n_5\,
Q => \weight_reg[13]_12\(6)
);
\weight_reg[13][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][4]_i_1_n_4\,
Q => \weight_reg[13]_12\(7)
);
\weight_reg[13][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][8]_i_1_n_7\,
Q => \weight_reg[13]_12\(8)
);
\weight_reg[13][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[13][4]_i_1_n_0\,
CO(3) => \weight_reg[13][8]_i_1_n_0\,
CO(2) => \weight_reg[13][8]_i_1_n_1\,
CO(1) => \weight_reg[13][8]_i_1_n_2\,
CO(0) => \weight_reg[13][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__23_n_80\,
DI(2) => \ARG__23_n_81\,
DI(1) => \ARG__23_n_82\,
DI(0) => \ARG__23_n_83\,
O(3) => \weight_reg[13][8]_i_1_n_4\,
O(2) => \weight_reg[13][8]_i_1_n_5\,
O(1) => \weight_reg[13][8]_i_1_n_6\,
O(0) => \weight_reg[13][8]_i_1_n_7\,
S(3) => \weight[13][8]_i_2_n_0\,
S(2) => \weight[13][8]_i_3_n_0\,
S(1) => \weight[13][8]_i_4_n_0\,
S(0) => \weight[13][8]_i_5_n_0\
);
\weight_reg[13][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][8]_i_1_n_6\,
Q => \weight_reg[13]_12\(9)
);
\weight_reg[14][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][0]_i_1_n_7\,
Q => \weight_reg[14]_13\(0)
);
\weight_reg[14][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[14][0]_i_1_n_0\,
CO(2) => \weight_reg[14][0]_i_1_n_1\,
CO(1) => \weight_reg[14][0]_i_1_n_2\,
CO(0) => \weight_reg[14][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__25_n_88\,
DI(2) => \ARG__25_n_89\,
DI(1) => \ARG__25_n_90\,
DI(0) => \ARG__25_n_91\,
O(3) => \weight_reg[14][0]_i_1_n_4\,
O(2) => \weight_reg[14][0]_i_1_n_5\,
O(1) => \weight_reg[14][0]_i_1_n_6\,
O(0) => \weight_reg[14][0]_i_1_n_7\,
S(3) => \weight[14][0]_i_2_n_0\,
S(2) => \weight[14][0]_i_3_n_0\,
S(1) => \weight[14][0]_i_4_n_0\,
S(0) => \weight[14][0]_i_5_n_0\
);
\weight_reg[14][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][8]_i_1_n_5\,
Q => \weight_reg[14]_13\(10)
);
\weight_reg[14][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][8]_i_1_n_4\,
Q => \weight_reg[14]_13\(11)
);
\weight_reg[14][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][12]_i_1_n_7\,
Q => \weight_reg[14]_13\(12)
);
\weight_reg[14][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[14][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[14][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[14][12]_i_1_n_1\,
CO(1) => \weight_reg[14][12]_i_1_n_2\,
CO(0) => \weight_reg[14][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__25_n_77\,
DI(1) => \ARG__25_n_78\,
DI(0) => \ARG__25_n_79\,
O(3) => \weight_reg[14][12]_i_1_n_4\,
O(2) => \weight_reg[14][12]_i_1_n_5\,
O(1) => \weight_reg[14][12]_i_1_n_6\,
O(0) => \weight_reg[14][12]_i_1_n_7\,
S(3) => \weight[14][12]_i_2_n_0\,
S(2) => \weight[14][12]_i_3_n_0\,
S(1) => \weight[14][12]_i_4_n_0\,
S(0) => \weight[14][12]_i_5_n_0\
);
\weight_reg[14][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][12]_i_1_n_6\,
Q => \weight_reg[14]_13\(13)
);
\weight_reg[14][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][12]_i_1_n_5\,
Q => \weight_reg[14]_13\(14)
);
\weight_reg[14][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][12]_i_1_n_4\,
Q => \weight_reg[14]_13\(15)
);
\weight_reg[14][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][0]_i_1_n_6\,
Q => \weight_reg[14]_13\(1)
);
\weight_reg[14][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][0]_i_1_n_5\,
Q => \weight_reg[14]_13\(2)
);
\weight_reg[14][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][0]_i_1_n_4\,
Q => \weight_reg[14]_13\(3)
);
\weight_reg[14][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][4]_i_1_n_7\,
Q => \weight_reg[14]_13\(4)
);
\weight_reg[14][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[14][0]_i_1_n_0\,
CO(3) => \weight_reg[14][4]_i_1_n_0\,
CO(2) => \weight_reg[14][4]_i_1_n_1\,
CO(1) => \weight_reg[14][4]_i_1_n_2\,
CO(0) => \weight_reg[14][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__25_n_84\,
DI(2) => \ARG__25_n_85\,
DI(1) => \ARG__25_n_86\,
DI(0) => \ARG__25_n_87\,
O(3) => \weight_reg[14][4]_i_1_n_4\,
O(2) => \weight_reg[14][4]_i_1_n_5\,
O(1) => \weight_reg[14][4]_i_1_n_6\,
O(0) => \weight_reg[14][4]_i_1_n_7\,
S(3) => \weight[14][4]_i_2_n_0\,
S(2) => \weight[14][4]_i_3_n_0\,
S(1) => \weight[14][4]_i_4_n_0\,
S(0) => \weight[14][4]_i_5_n_0\
);
\weight_reg[14][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][4]_i_1_n_6\,
Q => \weight_reg[14]_13\(5)
);
\weight_reg[14][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][4]_i_1_n_5\,
Q => \weight_reg[14]_13\(6)
);
\weight_reg[14][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][4]_i_1_n_4\,
Q => \weight_reg[14]_13\(7)
);
\weight_reg[14][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][8]_i_1_n_7\,
Q => \weight_reg[14]_13\(8)
);
\weight_reg[14][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[14][4]_i_1_n_0\,
CO(3) => \weight_reg[14][8]_i_1_n_0\,
CO(2) => \weight_reg[14][8]_i_1_n_1\,
CO(1) => \weight_reg[14][8]_i_1_n_2\,
CO(0) => \weight_reg[14][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__25_n_80\,
DI(2) => \ARG__25_n_81\,
DI(1) => \ARG__25_n_82\,
DI(0) => \ARG__25_n_83\,
O(3) => \weight_reg[14][8]_i_1_n_4\,
O(2) => \weight_reg[14][8]_i_1_n_5\,
O(1) => \weight_reg[14][8]_i_1_n_6\,
O(0) => \weight_reg[14][8]_i_1_n_7\,
S(3) => \weight[14][8]_i_2_n_0\,
S(2) => \weight[14][8]_i_3_n_0\,
S(1) => \weight[14][8]_i_4_n_0\,
S(0) => \weight[14][8]_i_5_n_0\
);
\weight_reg[14][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][8]_i_1_n_6\,
Q => \weight_reg[14]_13\(9)
);
\weight_reg[15][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][0]_i_1_n_7\,
Q => \weight_reg[15]_14\(0)
);
\weight_reg[15][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[15][0]_i_1_n_0\,
CO(2) => \weight_reg[15][0]_i_1_n_1\,
CO(1) => \weight_reg[15][0]_i_1_n_2\,
CO(0) => \weight_reg[15][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__27_n_88\,
DI(2) => \ARG__27_n_89\,
DI(1) => \ARG__27_n_90\,
DI(0) => \ARG__27_n_91\,
O(3) => \weight_reg[15][0]_i_1_n_4\,
O(2) => \weight_reg[15][0]_i_1_n_5\,
O(1) => \weight_reg[15][0]_i_1_n_6\,
O(0) => \weight_reg[15][0]_i_1_n_7\,
S(3) => \weight[15][0]_i_2_n_0\,
S(2) => \weight[15][0]_i_3_n_0\,
S(1) => \weight[15][0]_i_4_n_0\,
S(0) => \weight[15][0]_i_5_n_0\
);
\weight_reg[15][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][8]_i_1_n_5\,
Q => \weight_reg[15]_14\(10)
);
\weight_reg[15][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][8]_i_1_n_4\,
Q => \weight_reg[15]_14\(11)
);
\weight_reg[15][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][12]_i_1_n_7\,
Q => \weight_reg[15]_14\(12)
);
\weight_reg[15][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[15][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[15][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[15][12]_i_1_n_1\,
CO(1) => \weight_reg[15][12]_i_1_n_2\,
CO(0) => \weight_reg[15][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__27_n_77\,
DI(1) => \ARG__27_n_78\,
DI(0) => \ARG__27_n_79\,
O(3) => \weight_reg[15][12]_i_1_n_4\,
O(2) => \weight_reg[15][12]_i_1_n_5\,
O(1) => \weight_reg[15][12]_i_1_n_6\,
O(0) => \weight_reg[15][12]_i_1_n_7\,
S(3) => \weight[15][12]_i_2_n_0\,
S(2) => \weight[15][12]_i_3_n_0\,
S(1) => \weight[15][12]_i_4_n_0\,
S(0) => \weight[15][12]_i_5_n_0\
);
\weight_reg[15][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][12]_i_1_n_6\,
Q => \weight_reg[15]_14\(13)
);
\weight_reg[15][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][12]_i_1_n_5\,
Q => \weight_reg[15]_14\(14)
);
\weight_reg[15][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][12]_i_1_n_4\,
Q => \weight_reg[15]_14\(15)
);
\weight_reg[15][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][0]_i_1_n_6\,
Q => \weight_reg[15]_14\(1)
);
\weight_reg[15][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][0]_i_1_n_5\,
Q => \weight_reg[15]_14\(2)
);
\weight_reg[15][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][0]_i_1_n_4\,
Q => \weight_reg[15]_14\(3)
);
\weight_reg[15][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][4]_i_1_n_7\,
Q => \weight_reg[15]_14\(4)
);
\weight_reg[15][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[15][0]_i_1_n_0\,
CO(3) => \weight_reg[15][4]_i_1_n_0\,
CO(2) => \weight_reg[15][4]_i_1_n_1\,
CO(1) => \weight_reg[15][4]_i_1_n_2\,
CO(0) => \weight_reg[15][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__27_n_84\,
DI(2) => \ARG__27_n_85\,
DI(1) => \ARG__27_n_86\,
DI(0) => \ARG__27_n_87\,
O(3) => \weight_reg[15][4]_i_1_n_4\,
O(2) => \weight_reg[15][4]_i_1_n_5\,
O(1) => \weight_reg[15][4]_i_1_n_6\,
O(0) => \weight_reg[15][4]_i_1_n_7\,
S(3) => \weight[15][4]_i_2_n_0\,
S(2) => \weight[15][4]_i_3_n_0\,
S(1) => \weight[15][4]_i_4_n_0\,
S(0) => \weight[15][4]_i_5_n_0\
);
\weight_reg[15][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][4]_i_1_n_6\,
Q => \weight_reg[15]_14\(5)
);
\weight_reg[15][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][4]_i_1_n_5\,
Q => \weight_reg[15]_14\(6)
);
\weight_reg[15][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][4]_i_1_n_4\,
Q => \weight_reg[15]_14\(7)
);
\weight_reg[15][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][8]_i_1_n_7\,
Q => \weight_reg[15]_14\(8)
);
\weight_reg[15][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[15][4]_i_1_n_0\,
CO(3) => \weight_reg[15][8]_i_1_n_0\,
CO(2) => \weight_reg[15][8]_i_1_n_1\,
CO(1) => \weight_reg[15][8]_i_1_n_2\,
CO(0) => \weight_reg[15][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__27_n_80\,
DI(2) => \ARG__27_n_81\,
DI(1) => \ARG__27_n_82\,
DI(0) => \ARG__27_n_83\,
O(3) => \weight_reg[15][8]_i_1_n_4\,
O(2) => \weight_reg[15][8]_i_1_n_5\,
O(1) => \weight_reg[15][8]_i_1_n_6\,
O(0) => \weight_reg[15][8]_i_1_n_7\,
S(3) => \weight[15][8]_i_2_n_0\,
S(2) => \weight[15][8]_i_3_n_0\,
S(1) => \weight[15][8]_i_4_n_0\,
S(0) => \weight[15][8]_i_5_n_0\
);
\weight_reg[15][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][8]_i_1_n_6\,
Q => \weight_reg[15]_14\(9)
);
\weight_reg[1][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][0]_i_1_n_7\,
Q => \weight_reg[1]_0\(0)
);
\weight_reg[1][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[1][0]_i_1_n_0\,
CO(2) => \weight_reg[1][0]_i_1_n_1\,
CO(1) => \weight_reg[1][0]_i_1_n_2\,
CO(0) => \weight_reg[1][0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \in\(3 downto 0),
O(3) => \weight_reg[1][0]_i_1_n_4\,
O(2) => \weight_reg[1][0]_i_1_n_5\,
O(1) => \weight_reg[1][0]_i_1_n_6\,
O(0) => \weight_reg[1][0]_i_1_n_7\,
S(3) => \weight[1][0]_i_2_n_0\,
S(2) => \weight[1][0]_i_3_n_0\,
S(1) => \weight[1][0]_i_4_n_0\,
S(0) => \weight[1][0]_i_5_n_0\
);
\weight_reg[1][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][8]_i_1_n_5\,
Q => \weight_reg[1]_0\(10)
);
\weight_reg[1][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][8]_i_1_n_4\,
Q => \weight_reg[1]_0\(11)
);
\weight_reg[1][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][12]_i_1_n_7\,
Q => \weight_reg[1]_0\(12)
);
\weight_reg[1][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[1][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[1][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[1][12]_i_1_n_1\,
CO(1) => \weight_reg[1][12]_i_1_n_2\,
CO(0) => \weight_reg[1][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => \in\(14 downto 12),
O(3) => \weight_reg[1][12]_i_1_n_4\,
O(2) => \weight_reg[1][12]_i_1_n_5\,
O(1) => \weight_reg[1][12]_i_1_n_6\,
O(0) => \weight_reg[1][12]_i_1_n_7\,
S(3) => \weight[1][12]_i_2_n_0\,
S(2) => \weight[1][12]_i_3_n_0\,
S(1) => \weight[1][12]_i_4_n_0\,
S(0) => \weight[1][12]_i_5_n_0\
);
\weight_reg[1][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][12]_i_1_n_6\,
Q => \weight_reg[1]_0\(13)
);
\weight_reg[1][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][12]_i_1_n_5\,
Q => \weight_reg[1]_0\(14)
);
\weight_reg[1][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][12]_i_1_n_4\,
Q => \weight_reg[1]_0\(15)
);
\weight_reg[1][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][0]_i_1_n_6\,
Q => \weight_reg[1]_0\(1)
);
\weight_reg[1][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][0]_i_1_n_5\,
Q => \weight_reg[1]_0\(2)
);
\weight_reg[1][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][0]_i_1_n_4\,
Q => \weight_reg[1]_0\(3)
);
\weight_reg[1][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][4]_i_1_n_7\,
Q => \weight_reg[1]_0\(4)
);
\weight_reg[1][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[1][0]_i_1_n_0\,
CO(3) => \weight_reg[1][4]_i_1_n_0\,
CO(2) => \weight_reg[1][4]_i_1_n_1\,
CO(1) => \weight_reg[1][4]_i_1_n_2\,
CO(0) => \weight_reg[1][4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \in\(7 downto 4),
O(3) => \weight_reg[1][4]_i_1_n_4\,
O(2) => \weight_reg[1][4]_i_1_n_5\,
O(1) => \weight_reg[1][4]_i_1_n_6\,
O(0) => \weight_reg[1][4]_i_1_n_7\,
S(3) => \weight[1][4]_i_2_n_0\,
S(2) => \weight[1][4]_i_3_n_0\,
S(1) => \weight[1][4]_i_4_n_0\,
S(0) => \weight[1][4]_i_5_n_0\
);
\weight_reg[1][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][4]_i_1_n_6\,
Q => \weight_reg[1]_0\(5)
);
\weight_reg[1][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][4]_i_1_n_5\,
Q => \weight_reg[1]_0\(6)
);
\weight_reg[1][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][4]_i_1_n_4\,
Q => \weight_reg[1]_0\(7)
);
\weight_reg[1][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][8]_i_1_n_7\,
Q => \weight_reg[1]_0\(8)
);
\weight_reg[1][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[1][4]_i_1_n_0\,
CO(3) => \weight_reg[1][8]_i_1_n_0\,
CO(2) => \weight_reg[1][8]_i_1_n_1\,
CO(1) => \weight_reg[1][8]_i_1_n_2\,
CO(0) => \weight_reg[1][8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \in\(11 downto 8),
O(3) => \weight_reg[1][8]_i_1_n_4\,
O(2) => \weight_reg[1][8]_i_1_n_5\,
O(1) => \weight_reg[1][8]_i_1_n_6\,
O(0) => \weight_reg[1][8]_i_1_n_7\,
S(3) => \weight[1][8]_i_2_n_0\,
S(2) => \weight[1][8]_i_3_n_0\,
S(1) => \weight[1][8]_i_4_n_0\,
S(0) => \weight[1][8]_i_5_n_0\
);
\weight_reg[1][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][8]_i_1_n_6\,
Q => \weight_reg[1]_0\(9)
);
\weight_reg[2][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][0]_i_1_n_7\,
Q => \weight_reg[2]_1\(0)
);
\weight_reg[2][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[2][0]_i_1_n_0\,
CO(2) => \weight_reg[2][0]_i_1_n_1\,
CO(1) => \weight_reg[2][0]_i_1_n_2\,
CO(0) => \weight_reg[2][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__1_n_88\,
DI(2) => \ARG__1_n_89\,
DI(1) => \ARG__1_n_90\,
DI(0) => \ARG__1_n_91\,
O(3) => \weight_reg[2][0]_i_1_n_4\,
O(2) => \weight_reg[2][0]_i_1_n_5\,
O(1) => \weight_reg[2][0]_i_1_n_6\,
O(0) => \weight_reg[2][0]_i_1_n_7\,
S(3) => \weight[2][0]_i_2_n_0\,
S(2) => \weight[2][0]_i_3_n_0\,
S(1) => \weight[2][0]_i_4_n_0\,
S(0) => \weight[2][0]_i_5_n_0\
);
\weight_reg[2][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][8]_i_1_n_5\,
Q => \weight_reg[2]_1\(10)
);
\weight_reg[2][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][8]_i_1_n_4\,
Q => \weight_reg[2]_1\(11)
);
\weight_reg[2][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][12]_i_1_n_7\,
Q => \weight_reg[2]_1\(12)
);
\weight_reg[2][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[2][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[2][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[2][12]_i_1_n_1\,
CO(1) => \weight_reg[2][12]_i_1_n_2\,
CO(0) => \weight_reg[2][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__1_n_77\,
DI(1) => \ARG__1_n_78\,
DI(0) => \ARG__1_n_79\,
O(3) => \weight_reg[2][12]_i_1_n_4\,
O(2) => \weight_reg[2][12]_i_1_n_5\,
O(1) => \weight_reg[2][12]_i_1_n_6\,
O(0) => \weight_reg[2][12]_i_1_n_7\,
S(3) => \weight[2][12]_i_2_n_0\,
S(2) => \weight[2][12]_i_3_n_0\,
S(1) => \weight[2][12]_i_4_n_0\,
S(0) => \weight[2][12]_i_5_n_0\
);
\weight_reg[2][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][12]_i_1_n_6\,
Q => \weight_reg[2]_1\(13)
);
\weight_reg[2][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][12]_i_1_n_5\,
Q => \weight_reg[2]_1\(14)
);
\weight_reg[2][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][12]_i_1_n_4\,
Q => \weight_reg[2]_1\(15)
);
\weight_reg[2][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][0]_i_1_n_6\,
Q => \weight_reg[2]_1\(1)
);
\weight_reg[2][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][0]_i_1_n_5\,
Q => \weight_reg[2]_1\(2)
);
\weight_reg[2][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][0]_i_1_n_4\,
Q => \weight_reg[2]_1\(3)
);
\weight_reg[2][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][4]_i_1_n_7\,
Q => \weight_reg[2]_1\(4)
);
\weight_reg[2][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[2][0]_i_1_n_0\,
CO(3) => \weight_reg[2][4]_i_1_n_0\,
CO(2) => \weight_reg[2][4]_i_1_n_1\,
CO(1) => \weight_reg[2][4]_i_1_n_2\,
CO(0) => \weight_reg[2][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__1_n_84\,
DI(2) => \ARG__1_n_85\,
DI(1) => \ARG__1_n_86\,
DI(0) => \ARG__1_n_87\,
O(3) => \weight_reg[2][4]_i_1_n_4\,
O(2) => \weight_reg[2][4]_i_1_n_5\,
O(1) => \weight_reg[2][4]_i_1_n_6\,
O(0) => \weight_reg[2][4]_i_1_n_7\,
S(3) => \weight[2][4]_i_2_n_0\,
S(2) => \weight[2][4]_i_3_n_0\,
S(1) => \weight[2][4]_i_4_n_0\,
S(0) => \weight[2][4]_i_5_n_0\
);
\weight_reg[2][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][4]_i_1_n_6\,
Q => \weight_reg[2]_1\(5)
);
\weight_reg[2][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][4]_i_1_n_5\,
Q => \weight_reg[2]_1\(6)
);
\weight_reg[2][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][4]_i_1_n_4\,
Q => \weight_reg[2]_1\(7)
);
\weight_reg[2][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][8]_i_1_n_7\,
Q => \weight_reg[2]_1\(8)
);
\weight_reg[2][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[2][4]_i_1_n_0\,
CO(3) => \weight_reg[2][8]_i_1_n_0\,
CO(2) => \weight_reg[2][8]_i_1_n_1\,
CO(1) => \weight_reg[2][8]_i_1_n_2\,
CO(0) => \weight_reg[2][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__1_n_80\,
DI(2) => \ARG__1_n_81\,
DI(1) => \ARG__1_n_82\,
DI(0) => \ARG__1_n_83\,
O(3) => \weight_reg[2][8]_i_1_n_4\,
O(2) => \weight_reg[2][8]_i_1_n_5\,
O(1) => \weight_reg[2][8]_i_1_n_6\,
O(0) => \weight_reg[2][8]_i_1_n_7\,
S(3) => \weight[2][8]_i_2_n_0\,
S(2) => \weight[2][8]_i_3_n_0\,
S(1) => \weight[2][8]_i_4_n_0\,
S(0) => \weight[2][8]_i_5_n_0\
);
\weight_reg[2][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][8]_i_1_n_6\,
Q => \weight_reg[2]_1\(9)
);
\weight_reg[3][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][0]_i_1_n_7\,
Q => \weight_reg[3]_2\(0)
);
\weight_reg[3][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[3][0]_i_1_n_0\,
CO(2) => \weight_reg[3][0]_i_1_n_1\,
CO(1) => \weight_reg[3][0]_i_1_n_2\,
CO(0) => \weight_reg[3][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__3_n_88\,
DI(2) => \ARG__3_n_89\,
DI(1) => \ARG__3_n_90\,
DI(0) => \ARG__3_n_91\,
O(3) => \weight_reg[3][0]_i_1_n_4\,
O(2) => \weight_reg[3][0]_i_1_n_5\,
O(1) => \weight_reg[3][0]_i_1_n_6\,
O(0) => \weight_reg[3][0]_i_1_n_7\,
S(3) => \weight[3][0]_i_2_n_0\,
S(2) => \weight[3][0]_i_3_n_0\,
S(1) => \weight[3][0]_i_4_n_0\,
S(0) => \weight[3][0]_i_5_n_0\
);
\weight_reg[3][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][8]_i_1_n_5\,
Q => \weight_reg[3]_2\(10)
);
\weight_reg[3][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][8]_i_1_n_4\,
Q => \weight_reg[3]_2\(11)
);
\weight_reg[3][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][12]_i_1_n_7\,
Q => \weight_reg[3]_2\(12)
);
\weight_reg[3][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[3][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[3][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[3][12]_i_1_n_1\,
CO(1) => \weight_reg[3][12]_i_1_n_2\,
CO(0) => \weight_reg[3][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__3_n_77\,
DI(1) => \ARG__3_n_78\,
DI(0) => \ARG__3_n_79\,
O(3) => \weight_reg[3][12]_i_1_n_4\,
O(2) => \weight_reg[3][12]_i_1_n_5\,
O(1) => \weight_reg[3][12]_i_1_n_6\,
O(0) => \weight_reg[3][12]_i_1_n_7\,
S(3) => \weight[3][12]_i_2_n_0\,
S(2) => \weight[3][12]_i_3_n_0\,
S(1) => \weight[3][12]_i_4_n_0\,
S(0) => \weight[3][12]_i_5_n_0\
);
\weight_reg[3][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][12]_i_1_n_6\,
Q => \weight_reg[3]_2\(13)
);
\weight_reg[3][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][12]_i_1_n_5\,
Q => \weight_reg[3]_2\(14)
);
\weight_reg[3][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][12]_i_1_n_4\,
Q => \weight_reg[3]_2\(15)
);
\weight_reg[3][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][0]_i_1_n_6\,
Q => \weight_reg[3]_2\(1)
);
\weight_reg[3][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][0]_i_1_n_5\,
Q => \weight_reg[3]_2\(2)
);
\weight_reg[3][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][0]_i_1_n_4\,
Q => \weight_reg[3]_2\(3)
);
\weight_reg[3][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][4]_i_1_n_7\,
Q => \weight_reg[3]_2\(4)
);
\weight_reg[3][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[3][0]_i_1_n_0\,
CO(3) => \weight_reg[3][4]_i_1_n_0\,
CO(2) => \weight_reg[3][4]_i_1_n_1\,
CO(1) => \weight_reg[3][4]_i_1_n_2\,
CO(0) => \weight_reg[3][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__3_n_84\,
DI(2) => \ARG__3_n_85\,
DI(1) => \ARG__3_n_86\,
DI(0) => \ARG__3_n_87\,
O(3) => \weight_reg[3][4]_i_1_n_4\,
O(2) => \weight_reg[3][4]_i_1_n_5\,
O(1) => \weight_reg[3][4]_i_1_n_6\,
O(0) => \weight_reg[3][4]_i_1_n_7\,
S(3) => \weight[3][4]_i_2_n_0\,
S(2) => \weight[3][4]_i_3_n_0\,
S(1) => \weight[3][4]_i_4_n_0\,
S(0) => \weight[3][4]_i_5_n_0\
);
\weight_reg[3][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][4]_i_1_n_6\,
Q => \weight_reg[3]_2\(5)
);
\weight_reg[3][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][4]_i_1_n_5\,
Q => \weight_reg[3]_2\(6)
);
\weight_reg[3][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][4]_i_1_n_4\,
Q => \weight_reg[3]_2\(7)
);
\weight_reg[3][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][8]_i_1_n_7\,
Q => \weight_reg[3]_2\(8)
);
\weight_reg[3][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[3][4]_i_1_n_0\,
CO(3) => \weight_reg[3][8]_i_1_n_0\,
CO(2) => \weight_reg[3][8]_i_1_n_1\,
CO(1) => \weight_reg[3][8]_i_1_n_2\,
CO(0) => \weight_reg[3][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__3_n_80\,
DI(2) => \ARG__3_n_81\,
DI(1) => \ARG__3_n_82\,
DI(0) => \ARG__3_n_83\,
O(3) => \weight_reg[3][8]_i_1_n_4\,
O(2) => \weight_reg[3][8]_i_1_n_5\,
O(1) => \weight_reg[3][8]_i_1_n_6\,
O(0) => \weight_reg[3][8]_i_1_n_7\,
S(3) => \weight[3][8]_i_2_n_0\,
S(2) => \weight[3][8]_i_3_n_0\,
S(1) => \weight[3][8]_i_4_n_0\,
S(0) => \weight[3][8]_i_5_n_0\
);
\weight_reg[3][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][8]_i_1_n_6\,
Q => \weight_reg[3]_2\(9)
);
\weight_reg[4][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][0]_i_1_n_7\,
Q => \weight_reg[4]_3\(0)
);
\weight_reg[4][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[4][0]_i_1_n_0\,
CO(2) => \weight_reg[4][0]_i_1_n_1\,
CO(1) => \weight_reg[4][0]_i_1_n_2\,
CO(0) => \weight_reg[4][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__5_n_88\,
DI(2) => \ARG__5_n_89\,
DI(1) => \ARG__5_n_90\,
DI(0) => \ARG__5_n_91\,
O(3) => \weight_reg[4][0]_i_1_n_4\,
O(2) => \weight_reg[4][0]_i_1_n_5\,
O(1) => \weight_reg[4][0]_i_1_n_6\,
O(0) => \weight_reg[4][0]_i_1_n_7\,
S(3) => \weight[4][0]_i_2_n_0\,
S(2) => \weight[4][0]_i_3_n_0\,
S(1) => \weight[4][0]_i_4_n_0\,
S(0) => \weight[4][0]_i_5_n_0\
);
\weight_reg[4][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][8]_i_1_n_5\,
Q => \weight_reg[4]_3\(10)
);
\weight_reg[4][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][8]_i_1_n_4\,
Q => \weight_reg[4]_3\(11)
);
\weight_reg[4][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][12]_i_1_n_7\,
Q => \weight_reg[4]_3\(12)
);
\weight_reg[4][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[4][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[4][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[4][12]_i_1_n_1\,
CO(1) => \weight_reg[4][12]_i_1_n_2\,
CO(0) => \weight_reg[4][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__5_n_77\,
DI(1) => \ARG__5_n_78\,
DI(0) => \ARG__5_n_79\,
O(3) => \weight_reg[4][12]_i_1_n_4\,
O(2) => \weight_reg[4][12]_i_1_n_5\,
O(1) => \weight_reg[4][12]_i_1_n_6\,
O(0) => \weight_reg[4][12]_i_1_n_7\,
S(3) => \weight[4][12]_i_2_n_0\,
S(2) => \weight[4][12]_i_3_n_0\,
S(1) => \weight[4][12]_i_4_n_0\,
S(0) => \weight[4][12]_i_5_n_0\
);
\weight_reg[4][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][12]_i_1_n_6\,
Q => \weight_reg[4]_3\(13)
);
\weight_reg[4][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][12]_i_1_n_5\,
Q => \weight_reg[4]_3\(14)
);
\weight_reg[4][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][12]_i_1_n_4\,
Q => \weight_reg[4]_3\(15)
);
\weight_reg[4][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][0]_i_1_n_6\,
Q => \weight_reg[4]_3\(1)
);
\weight_reg[4][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][0]_i_1_n_5\,
Q => \weight_reg[4]_3\(2)
);
\weight_reg[4][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][0]_i_1_n_4\,
Q => \weight_reg[4]_3\(3)
);
\weight_reg[4][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][4]_i_1_n_7\,
Q => \weight_reg[4]_3\(4)
);
\weight_reg[4][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[4][0]_i_1_n_0\,
CO(3) => \weight_reg[4][4]_i_1_n_0\,
CO(2) => \weight_reg[4][4]_i_1_n_1\,
CO(1) => \weight_reg[4][4]_i_1_n_2\,
CO(0) => \weight_reg[4][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__5_n_84\,
DI(2) => \ARG__5_n_85\,
DI(1) => \ARG__5_n_86\,
DI(0) => \ARG__5_n_87\,
O(3) => \weight_reg[4][4]_i_1_n_4\,
O(2) => \weight_reg[4][4]_i_1_n_5\,
O(1) => \weight_reg[4][4]_i_1_n_6\,
O(0) => \weight_reg[4][4]_i_1_n_7\,
S(3) => \weight[4][4]_i_2_n_0\,
S(2) => \weight[4][4]_i_3_n_0\,
S(1) => \weight[4][4]_i_4_n_0\,
S(0) => \weight[4][4]_i_5_n_0\
);
\weight_reg[4][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][4]_i_1_n_6\,
Q => \weight_reg[4]_3\(5)
);
\weight_reg[4][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][4]_i_1_n_5\,
Q => \weight_reg[4]_3\(6)
);
\weight_reg[4][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][4]_i_1_n_4\,
Q => \weight_reg[4]_3\(7)
);
\weight_reg[4][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][8]_i_1_n_7\,
Q => \weight_reg[4]_3\(8)
);
\weight_reg[4][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[4][4]_i_1_n_0\,
CO(3) => \weight_reg[4][8]_i_1_n_0\,
CO(2) => \weight_reg[4][8]_i_1_n_1\,
CO(1) => \weight_reg[4][8]_i_1_n_2\,
CO(0) => \weight_reg[4][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__5_n_80\,
DI(2) => \ARG__5_n_81\,
DI(1) => \ARG__5_n_82\,
DI(0) => \ARG__5_n_83\,
O(3) => \weight_reg[4][8]_i_1_n_4\,
O(2) => \weight_reg[4][8]_i_1_n_5\,
O(1) => \weight_reg[4][8]_i_1_n_6\,
O(0) => \weight_reg[4][8]_i_1_n_7\,
S(3) => \weight[4][8]_i_2_n_0\,
S(2) => \weight[4][8]_i_3_n_0\,
S(1) => \weight[4][8]_i_4_n_0\,
S(0) => \weight[4][8]_i_5_n_0\
);
\weight_reg[4][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][8]_i_1_n_6\,
Q => \weight_reg[4]_3\(9)
);
\weight_reg[5][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][0]_i_1_n_7\,
Q => \weight_reg[5]_4\(0)
);
\weight_reg[5][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[5][0]_i_1_n_0\,
CO(2) => \weight_reg[5][0]_i_1_n_1\,
CO(1) => \weight_reg[5][0]_i_1_n_2\,
CO(0) => \weight_reg[5][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__7_n_88\,
DI(2) => \ARG__7_n_89\,
DI(1) => \ARG__7_n_90\,
DI(0) => \ARG__7_n_91\,
O(3) => \weight_reg[5][0]_i_1_n_4\,
O(2) => \weight_reg[5][0]_i_1_n_5\,
O(1) => \weight_reg[5][0]_i_1_n_6\,
O(0) => \weight_reg[5][0]_i_1_n_7\,
S(3) => \weight[5][0]_i_2_n_0\,
S(2) => \weight[5][0]_i_3_n_0\,
S(1) => \weight[5][0]_i_4_n_0\,
S(0) => \weight[5][0]_i_5_n_0\
);
\weight_reg[5][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][8]_i_1_n_5\,
Q => \weight_reg[5]_4\(10)
);
\weight_reg[5][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][8]_i_1_n_4\,
Q => \weight_reg[5]_4\(11)
);
\weight_reg[5][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][12]_i_1_n_7\,
Q => \weight_reg[5]_4\(12)
);
\weight_reg[5][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[5][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[5][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[5][12]_i_1_n_1\,
CO(1) => \weight_reg[5][12]_i_1_n_2\,
CO(0) => \weight_reg[5][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__7_n_77\,
DI(1) => \ARG__7_n_78\,
DI(0) => \ARG__7_n_79\,
O(3) => \weight_reg[5][12]_i_1_n_4\,
O(2) => \weight_reg[5][12]_i_1_n_5\,
O(1) => \weight_reg[5][12]_i_1_n_6\,
O(0) => \weight_reg[5][12]_i_1_n_7\,
S(3) => \weight[5][12]_i_2_n_0\,
S(2) => \weight[5][12]_i_3_n_0\,
S(1) => \weight[5][12]_i_4_n_0\,
S(0) => \weight[5][12]_i_5_n_0\
);
\weight_reg[5][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][12]_i_1_n_6\,
Q => \weight_reg[5]_4\(13)
);
\weight_reg[5][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][12]_i_1_n_5\,
Q => \weight_reg[5]_4\(14)
);
\weight_reg[5][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][12]_i_1_n_4\,
Q => \weight_reg[5]_4\(15)
);
\weight_reg[5][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][0]_i_1_n_6\,
Q => \weight_reg[5]_4\(1)
);
\weight_reg[5][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][0]_i_1_n_5\,
Q => \weight_reg[5]_4\(2)
);
\weight_reg[5][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][0]_i_1_n_4\,
Q => \weight_reg[5]_4\(3)
);
\weight_reg[5][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][4]_i_1_n_7\,
Q => \weight_reg[5]_4\(4)
);
\weight_reg[5][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[5][0]_i_1_n_0\,
CO(3) => \weight_reg[5][4]_i_1_n_0\,
CO(2) => \weight_reg[5][4]_i_1_n_1\,
CO(1) => \weight_reg[5][4]_i_1_n_2\,
CO(0) => \weight_reg[5][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__7_n_84\,
DI(2) => \ARG__7_n_85\,
DI(1) => \ARG__7_n_86\,
DI(0) => \ARG__7_n_87\,
O(3) => \weight_reg[5][4]_i_1_n_4\,
O(2) => \weight_reg[5][4]_i_1_n_5\,
O(1) => \weight_reg[5][4]_i_1_n_6\,
O(0) => \weight_reg[5][4]_i_1_n_7\,
S(3) => \weight[5][4]_i_2_n_0\,
S(2) => \weight[5][4]_i_3_n_0\,
S(1) => \weight[5][4]_i_4_n_0\,
S(0) => \weight[5][4]_i_5_n_0\
);
\weight_reg[5][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][4]_i_1_n_6\,
Q => \weight_reg[5]_4\(5)
);
\weight_reg[5][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][4]_i_1_n_5\,
Q => \weight_reg[5]_4\(6)
);
\weight_reg[5][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][4]_i_1_n_4\,
Q => \weight_reg[5]_4\(7)
);
\weight_reg[5][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][8]_i_1_n_7\,
Q => \weight_reg[5]_4\(8)
);
\weight_reg[5][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[5][4]_i_1_n_0\,
CO(3) => \weight_reg[5][8]_i_1_n_0\,
CO(2) => \weight_reg[5][8]_i_1_n_1\,
CO(1) => \weight_reg[5][8]_i_1_n_2\,
CO(0) => \weight_reg[5][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__7_n_80\,
DI(2) => \ARG__7_n_81\,
DI(1) => \ARG__7_n_82\,
DI(0) => \ARG__7_n_83\,
O(3) => \weight_reg[5][8]_i_1_n_4\,
O(2) => \weight_reg[5][8]_i_1_n_5\,
O(1) => \weight_reg[5][8]_i_1_n_6\,
O(0) => \weight_reg[5][8]_i_1_n_7\,
S(3) => \weight[5][8]_i_2_n_0\,
S(2) => \weight[5][8]_i_3_n_0\,
S(1) => \weight[5][8]_i_4_n_0\,
S(0) => \weight[5][8]_i_5_n_0\
);
\weight_reg[5][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][8]_i_1_n_6\,
Q => \weight_reg[5]_4\(9)
);
\weight_reg[6][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][0]_i_1_n_7\,
Q => \weight_reg[6]_5\(0)
);
\weight_reg[6][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[6][0]_i_1_n_0\,
CO(2) => \weight_reg[6][0]_i_1_n_1\,
CO(1) => \weight_reg[6][0]_i_1_n_2\,
CO(0) => \weight_reg[6][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__9_n_88\,
DI(2) => \ARG__9_n_89\,
DI(1) => \ARG__9_n_90\,
DI(0) => \ARG__9_n_91\,
O(3) => \weight_reg[6][0]_i_1_n_4\,
O(2) => \weight_reg[6][0]_i_1_n_5\,
O(1) => \weight_reg[6][0]_i_1_n_6\,
O(0) => \weight_reg[6][0]_i_1_n_7\,
S(3) => \weight[6][0]_i_2_n_0\,
S(2) => \weight[6][0]_i_3_n_0\,
S(1) => \weight[6][0]_i_4_n_0\,
S(0) => \weight[6][0]_i_5_n_0\
);
\weight_reg[6][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][8]_i_1_n_5\,
Q => \weight_reg[6]_5\(10)
);
\weight_reg[6][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][8]_i_1_n_4\,
Q => \weight_reg[6]_5\(11)
);
\weight_reg[6][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][12]_i_1_n_7\,
Q => \weight_reg[6]_5\(12)
);
\weight_reg[6][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[6][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[6][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[6][12]_i_1_n_1\,
CO(1) => \weight_reg[6][12]_i_1_n_2\,
CO(0) => \weight_reg[6][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__9_n_77\,
DI(1) => \ARG__9_n_78\,
DI(0) => \ARG__9_n_79\,
O(3) => \weight_reg[6][12]_i_1_n_4\,
O(2) => \weight_reg[6][12]_i_1_n_5\,
O(1) => \weight_reg[6][12]_i_1_n_6\,
O(0) => \weight_reg[6][12]_i_1_n_7\,
S(3) => \weight[6][12]_i_2_n_0\,
S(2) => \weight[6][12]_i_3_n_0\,
S(1) => \weight[6][12]_i_4_n_0\,
S(0) => \weight[6][12]_i_5_n_0\
);
\weight_reg[6][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][12]_i_1_n_6\,
Q => \weight_reg[6]_5\(13)
);
\weight_reg[6][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][12]_i_1_n_5\,
Q => \weight_reg[6]_5\(14)
);
\weight_reg[6][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][12]_i_1_n_4\,
Q => \weight_reg[6]_5\(15)
);
\weight_reg[6][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][0]_i_1_n_6\,
Q => \weight_reg[6]_5\(1)
);
\weight_reg[6][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][0]_i_1_n_5\,
Q => \weight_reg[6]_5\(2)
);
\weight_reg[6][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][0]_i_1_n_4\,
Q => \weight_reg[6]_5\(3)
);
\weight_reg[6][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][4]_i_1_n_7\,
Q => \weight_reg[6]_5\(4)
);
\weight_reg[6][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[6][0]_i_1_n_0\,
CO(3) => \weight_reg[6][4]_i_1_n_0\,
CO(2) => \weight_reg[6][4]_i_1_n_1\,
CO(1) => \weight_reg[6][4]_i_1_n_2\,
CO(0) => \weight_reg[6][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__9_n_84\,
DI(2) => \ARG__9_n_85\,
DI(1) => \ARG__9_n_86\,
DI(0) => \ARG__9_n_87\,
O(3) => \weight_reg[6][4]_i_1_n_4\,
O(2) => \weight_reg[6][4]_i_1_n_5\,
O(1) => \weight_reg[6][4]_i_1_n_6\,
O(0) => \weight_reg[6][4]_i_1_n_7\,
S(3) => \weight[6][4]_i_2_n_0\,
S(2) => \weight[6][4]_i_3_n_0\,
S(1) => \weight[6][4]_i_4_n_0\,
S(0) => \weight[6][4]_i_5_n_0\
);
\weight_reg[6][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][4]_i_1_n_6\,
Q => \weight_reg[6]_5\(5)
);
\weight_reg[6][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][4]_i_1_n_5\,
Q => \weight_reg[6]_5\(6)
);
\weight_reg[6][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][4]_i_1_n_4\,
Q => \weight_reg[6]_5\(7)
);
\weight_reg[6][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][8]_i_1_n_7\,
Q => \weight_reg[6]_5\(8)
);
\weight_reg[6][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[6][4]_i_1_n_0\,
CO(3) => \weight_reg[6][8]_i_1_n_0\,
CO(2) => \weight_reg[6][8]_i_1_n_1\,
CO(1) => \weight_reg[6][8]_i_1_n_2\,
CO(0) => \weight_reg[6][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__9_n_80\,
DI(2) => \ARG__9_n_81\,
DI(1) => \ARG__9_n_82\,
DI(0) => \ARG__9_n_83\,
O(3) => \weight_reg[6][8]_i_1_n_4\,
O(2) => \weight_reg[6][8]_i_1_n_5\,
O(1) => \weight_reg[6][8]_i_1_n_6\,
O(0) => \weight_reg[6][8]_i_1_n_7\,
S(3) => \weight[6][8]_i_2_n_0\,
S(2) => \weight[6][8]_i_3_n_0\,
S(1) => \weight[6][8]_i_4_n_0\,
S(0) => \weight[6][8]_i_5_n_0\
);
\weight_reg[6][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][8]_i_1_n_6\,
Q => \weight_reg[6]_5\(9)
);
\weight_reg[7][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][0]_i_1_n_7\,
Q => \weight_reg[7]_6\(0)
);
\weight_reg[7][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[7][0]_i_1_n_0\,
CO(2) => \weight_reg[7][0]_i_1_n_1\,
CO(1) => \weight_reg[7][0]_i_1_n_2\,
CO(0) => \weight_reg[7][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__11_n_88\,
DI(2) => \ARG__11_n_89\,
DI(1) => \ARG__11_n_90\,
DI(0) => \ARG__11_n_91\,
O(3) => \weight_reg[7][0]_i_1_n_4\,
O(2) => \weight_reg[7][0]_i_1_n_5\,
O(1) => \weight_reg[7][0]_i_1_n_6\,
O(0) => \weight_reg[7][0]_i_1_n_7\,
S(3) => \weight[7][0]_i_2_n_0\,
S(2) => \weight[7][0]_i_3_n_0\,
S(1) => \weight[7][0]_i_4_n_0\,
S(0) => \weight[7][0]_i_5_n_0\
);
\weight_reg[7][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][8]_i_1_n_5\,
Q => \weight_reg[7]_6\(10)
);
\weight_reg[7][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][8]_i_1_n_4\,
Q => \weight_reg[7]_6\(11)
);
\weight_reg[7][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][12]_i_1_n_7\,
Q => \weight_reg[7]_6\(12)
);
\weight_reg[7][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[7][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[7][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[7][12]_i_1_n_1\,
CO(1) => \weight_reg[7][12]_i_1_n_2\,
CO(0) => \weight_reg[7][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__11_n_77\,
DI(1) => \ARG__11_n_78\,
DI(0) => \ARG__11_n_79\,
O(3) => \weight_reg[7][12]_i_1_n_4\,
O(2) => \weight_reg[7][12]_i_1_n_5\,
O(1) => \weight_reg[7][12]_i_1_n_6\,
O(0) => \weight_reg[7][12]_i_1_n_7\,
S(3) => \weight[7][12]_i_2_n_0\,
S(2) => \weight[7][12]_i_3_n_0\,
S(1) => \weight[7][12]_i_4_n_0\,
S(0) => \weight[7][12]_i_5_n_0\
);
\weight_reg[7][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][12]_i_1_n_6\,
Q => \weight_reg[7]_6\(13)
);
\weight_reg[7][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][12]_i_1_n_5\,
Q => \weight_reg[7]_6\(14)
);
\weight_reg[7][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][12]_i_1_n_4\,
Q => \weight_reg[7]_6\(15)
);
\weight_reg[7][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][0]_i_1_n_6\,
Q => \weight_reg[7]_6\(1)
);
\weight_reg[7][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][0]_i_1_n_5\,
Q => \weight_reg[7]_6\(2)
);
\weight_reg[7][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][0]_i_1_n_4\,
Q => \weight_reg[7]_6\(3)
);
\weight_reg[7][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][4]_i_1_n_7\,
Q => \weight_reg[7]_6\(4)
);
\weight_reg[7][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[7][0]_i_1_n_0\,
CO(3) => \weight_reg[7][4]_i_1_n_0\,
CO(2) => \weight_reg[7][4]_i_1_n_1\,
CO(1) => \weight_reg[7][4]_i_1_n_2\,
CO(0) => \weight_reg[7][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__11_n_84\,
DI(2) => \ARG__11_n_85\,
DI(1) => \ARG__11_n_86\,
DI(0) => \ARG__11_n_87\,
O(3) => \weight_reg[7][4]_i_1_n_4\,
O(2) => \weight_reg[7][4]_i_1_n_5\,
O(1) => \weight_reg[7][4]_i_1_n_6\,
O(0) => \weight_reg[7][4]_i_1_n_7\,
S(3) => \weight[7][4]_i_2_n_0\,
S(2) => \weight[7][4]_i_3_n_0\,
S(1) => \weight[7][4]_i_4_n_0\,
S(0) => \weight[7][4]_i_5_n_0\
);
\weight_reg[7][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][4]_i_1_n_6\,
Q => \weight_reg[7]_6\(5)
);
\weight_reg[7][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][4]_i_1_n_5\,
Q => \weight_reg[7]_6\(6)
);
\weight_reg[7][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][4]_i_1_n_4\,
Q => \weight_reg[7]_6\(7)
);
\weight_reg[7][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][8]_i_1_n_7\,
Q => \weight_reg[7]_6\(8)
);
\weight_reg[7][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[7][4]_i_1_n_0\,
CO(3) => \weight_reg[7][8]_i_1_n_0\,
CO(2) => \weight_reg[7][8]_i_1_n_1\,
CO(1) => \weight_reg[7][8]_i_1_n_2\,
CO(0) => \weight_reg[7][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__11_n_80\,
DI(2) => \ARG__11_n_81\,
DI(1) => \ARG__11_n_82\,
DI(0) => \ARG__11_n_83\,
O(3) => \weight_reg[7][8]_i_1_n_4\,
O(2) => \weight_reg[7][8]_i_1_n_5\,
O(1) => \weight_reg[7][8]_i_1_n_6\,
O(0) => \weight_reg[7][8]_i_1_n_7\,
S(3) => \weight[7][8]_i_2_n_0\,
S(2) => \weight[7][8]_i_3_n_0\,
S(1) => \weight[7][8]_i_4_n_0\,
S(0) => \weight[7][8]_i_5_n_0\
);
\weight_reg[7][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][8]_i_1_n_6\,
Q => \weight_reg[7]_6\(9)
);
\weight_reg[8][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][0]_i_1_n_7\,
Q => \weight_reg[8]_7\(0)
);
\weight_reg[8][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[8][0]_i_1_n_0\,
CO(2) => \weight_reg[8][0]_i_1_n_1\,
CO(1) => \weight_reg[8][0]_i_1_n_2\,
CO(0) => \weight_reg[8][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__13_n_88\,
DI(2) => \ARG__13_n_89\,
DI(1) => \ARG__13_n_90\,
DI(0) => \ARG__13_n_91\,
O(3) => \weight_reg[8][0]_i_1_n_4\,
O(2) => \weight_reg[8][0]_i_1_n_5\,
O(1) => \weight_reg[8][0]_i_1_n_6\,
O(0) => \weight_reg[8][0]_i_1_n_7\,
S(3) => \weight[8][0]_i_2_n_0\,
S(2) => \weight[8][0]_i_3_n_0\,
S(1) => \weight[8][0]_i_4_n_0\,
S(0) => \weight[8][0]_i_5_n_0\
);
\weight_reg[8][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][8]_i_1_n_5\,
Q => \weight_reg[8]_7\(10)
);
\weight_reg[8][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][8]_i_1_n_4\,
Q => \weight_reg[8]_7\(11)
);
\weight_reg[8][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][12]_i_1_n_7\,
Q => \weight_reg[8]_7\(12)
);
\weight_reg[8][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[8][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[8][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[8][12]_i_1_n_1\,
CO(1) => \weight_reg[8][12]_i_1_n_2\,
CO(0) => \weight_reg[8][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__13_n_77\,
DI(1) => \ARG__13_n_78\,
DI(0) => \ARG__13_n_79\,
O(3) => \weight_reg[8][12]_i_1_n_4\,
O(2) => \weight_reg[8][12]_i_1_n_5\,
O(1) => \weight_reg[8][12]_i_1_n_6\,
O(0) => \weight_reg[8][12]_i_1_n_7\,
S(3) => \weight[8][12]_i_2_n_0\,
S(2) => \weight[8][12]_i_3_n_0\,
S(1) => \weight[8][12]_i_4_n_0\,
S(0) => \weight[8][12]_i_5_n_0\
);
\weight_reg[8][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][12]_i_1_n_6\,
Q => \weight_reg[8]_7\(13)
);
\weight_reg[8][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][12]_i_1_n_5\,
Q => \weight_reg[8]_7\(14)
);
\weight_reg[8][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][12]_i_1_n_4\,
Q => \weight_reg[8]_7\(15)
);
\weight_reg[8][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][0]_i_1_n_6\,
Q => \weight_reg[8]_7\(1)
);
\weight_reg[8][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][0]_i_1_n_5\,
Q => \weight_reg[8]_7\(2)
);
\weight_reg[8][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][0]_i_1_n_4\,
Q => \weight_reg[8]_7\(3)
);
\weight_reg[8][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][4]_i_1_n_7\,
Q => \weight_reg[8]_7\(4)
);
\weight_reg[8][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[8][0]_i_1_n_0\,
CO(3) => \weight_reg[8][4]_i_1_n_0\,
CO(2) => \weight_reg[8][4]_i_1_n_1\,
CO(1) => \weight_reg[8][4]_i_1_n_2\,
CO(0) => \weight_reg[8][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__13_n_84\,
DI(2) => \ARG__13_n_85\,
DI(1) => \ARG__13_n_86\,
DI(0) => \ARG__13_n_87\,
O(3) => \weight_reg[8][4]_i_1_n_4\,
O(2) => \weight_reg[8][4]_i_1_n_5\,
O(1) => \weight_reg[8][4]_i_1_n_6\,
O(0) => \weight_reg[8][4]_i_1_n_7\,
S(3) => \weight[8][4]_i_2_n_0\,
S(2) => \weight[8][4]_i_3_n_0\,
S(1) => \weight[8][4]_i_4_n_0\,
S(0) => \weight[8][4]_i_5_n_0\
);
\weight_reg[8][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][4]_i_1_n_6\,
Q => \weight_reg[8]_7\(5)
);
\weight_reg[8][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][4]_i_1_n_5\,
Q => \weight_reg[8]_7\(6)
);
\weight_reg[8][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][4]_i_1_n_4\,
Q => \weight_reg[8]_7\(7)
);
\weight_reg[8][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][8]_i_1_n_7\,
Q => \weight_reg[8]_7\(8)
);
\weight_reg[8][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[8][4]_i_1_n_0\,
CO(3) => \weight_reg[8][8]_i_1_n_0\,
CO(2) => \weight_reg[8][8]_i_1_n_1\,
CO(1) => \weight_reg[8][8]_i_1_n_2\,
CO(0) => \weight_reg[8][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__13_n_80\,
DI(2) => \ARG__13_n_81\,
DI(1) => \ARG__13_n_82\,
DI(0) => \ARG__13_n_83\,
O(3) => \weight_reg[8][8]_i_1_n_4\,
O(2) => \weight_reg[8][8]_i_1_n_5\,
O(1) => \weight_reg[8][8]_i_1_n_6\,
O(0) => \weight_reg[8][8]_i_1_n_7\,
S(3) => \weight[8][8]_i_2_n_0\,
S(2) => \weight[8][8]_i_3_n_0\,
S(1) => \weight[8][8]_i_4_n_0\,
S(0) => \weight[8][8]_i_5_n_0\
);
\weight_reg[8][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][8]_i_1_n_6\,
Q => \weight_reg[8]_7\(9)
);
\weight_reg[9][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][0]_i_1_n_7\,
Q => \weight_reg[9]_8\(0)
);
\weight_reg[9][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[9][0]_i_1_n_0\,
CO(2) => \weight_reg[9][0]_i_1_n_1\,
CO(1) => \weight_reg[9][0]_i_1_n_2\,
CO(0) => \weight_reg[9][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__15_n_88\,
DI(2) => \ARG__15_n_89\,
DI(1) => \ARG__15_n_90\,
DI(0) => \ARG__15_n_91\,
O(3) => \weight_reg[9][0]_i_1_n_4\,
O(2) => \weight_reg[9][0]_i_1_n_5\,
O(1) => \weight_reg[9][0]_i_1_n_6\,
O(0) => \weight_reg[9][0]_i_1_n_7\,
S(3) => \weight[9][0]_i_2_n_0\,
S(2) => \weight[9][0]_i_3_n_0\,
S(1) => \weight[9][0]_i_4_n_0\,
S(0) => \weight[9][0]_i_5_n_0\
);
\weight_reg[9][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][8]_i_1_n_5\,
Q => \weight_reg[9]_8\(10)
);
\weight_reg[9][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][8]_i_1_n_4\,
Q => \weight_reg[9]_8\(11)
);
\weight_reg[9][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][12]_i_1_n_7\,
Q => \weight_reg[9]_8\(12)
);
\weight_reg[9][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[9][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[9][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[9][12]_i_1_n_1\,
CO(1) => \weight_reg[9][12]_i_1_n_2\,
CO(0) => \weight_reg[9][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__15_n_77\,
DI(1) => \ARG__15_n_78\,
DI(0) => \ARG__15_n_79\,
O(3) => \weight_reg[9][12]_i_1_n_4\,
O(2) => \weight_reg[9][12]_i_1_n_5\,
O(1) => \weight_reg[9][12]_i_1_n_6\,
O(0) => \weight_reg[9][12]_i_1_n_7\,
S(3) => \weight[9][12]_i_2_n_0\,
S(2) => \weight[9][12]_i_3_n_0\,
S(1) => \weight[9][12]_i_4_n_0\,
S(0) => \weight[9][12]_i_5_n_0\
);
\weight_reg[9][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][12]_i_1_n_6\,
Q => \weight_reg[9]_8\(13)
);
\weight_reg[9][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][12]_i_1_n_5\,
Q => \weight_reg[9]_8\(14)
);
\weight_reg[9][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][12]_i_1_n_4\,
Q => \weight_reg[9]_8\(15)
);
\weight_reg[9][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][0]_i_1_n_6\,
Q => \weight_reg[9]_8\(1)
);
\weight_reg[9][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][0]_i_1_n_5\,
Q => \weight_reg[9]_8\(2)
);
\weight_reg[9][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][0]_i_1_n_4\,
Q => \weight_reg[9]_8\(3)
);
\weight_reg[9][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][4]_i_1_n_7\,
Q => \weight_reg[9]_8\(4)
);
\weight_reg[9][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[9][0]_i_1_n_0\,
CO(3) => \weight_reg[9][4]_i_1_n_0\,
CO(2) => \weight_reg[9][4]_i_1_n_1\,
CO(1) => \weight_reg[9][4]_i_1_n_2\,
CO(0) => \weight_reg[9][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__15_n_84\,
DI(2) => \ARG__15_n_85\,
DI(1) => \ARG__15_n_86\,
DI(0) => \ARG__15_n_87\,
O(3) => \weight_reg[9][4]_i_1_n_4\,
O(2) => \weight_reg[9][4]_i_1_n_5\,
O(1) => \weight_reg[9][4]_i_1_n_6\,
O(0) => \weight_reg[9][4]_i_1_n_7\,
S(3) => \weight[9][4]_i_2_n_0\,
S(2) => \weight[9][4]_i_3_n_0\,
S(1) => \weight[9][4]_i_4_n_0\,
S(0) => \weight[9][4]_i_5_n_0\
);
\weight_reg[9][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][4]_i_1_n_6\,
Q => \weight_reg[9]_8\(5)
);
\weight_reg[9][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][4]_i_1_n_5\,
Q => \weight_reg[9]_8\(6)
);
\weight_reg[9][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][4]_i_1_n_4\,
Q => \weight_reg[9]_8\(7)
);
\weight_reg[9][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][8]_i_1_n_7\,
Q => \weight_reg[9]_8\(8)
);
\weight_reg[9][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[9][4]_i_1_n_0\,
CO(3) => \weight_reg[9][8]_i_1_n_0\,
CO(2) => \weight_reg[9][8]_i_1_n_1\,
CO(1) => \weight_reg[9][8]_i_1_n_2\,
CO(0) => \weight_reg[9][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__15_n_80\,
DI(2) => \ARG__15_n_81\,
DI(1) => \ARG__15_n_82\,
DI(0) => \ARG__15_n_83\,
O(3) => \weight_reg[9][8]_i_1_n_4\,
O(2) => \weight_reg[9][8]_i_1_n_5\,
O(1) => \weight_reg[9][8]_i_1_n_6\,
O(0) => \weight_reg[9][8]_i_1_n_7\,
S(3) => \weight[9][8]_i_2_n_0\,
S(2) => \weight[9][8]_i_3_n_0\,
S(1) => \weight[9][8]_i_4_n_0\,
S(0) => \weight[9][8]_i_5_n_0\
);
\weight_reg[9][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][8]_i_1_n_6\,
Q => \weight_reg[9]_8\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_addr_decoder is
port (
read_reg_cop_out_ready : out STD_LOGIC;
write_reg_axi_enable : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 14 downto 0 );
\sync_reg_e_k_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\sync_reg_e_k_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\sync_reg_e_k_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
DI : out STD_LOGIC_VECTOR ( 0 to 0 );
\ARG__29\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\cp_controller_cpstate_reg[0]\ : out STD_LOGIC;
\ARG__28\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
\AXI4_Lite_RDATA_tmp_reg[31]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
strobe_sw_cop_in_strobe : in STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
cop_out_ready : in STD_LOGIC;
\wdata_reg[0]\ : in STD_LOGIC;
filter_sum : in STD_LOGIC_VECTOR ( 15 downto 0 );
mul_temp_16 : in STD_LOGIC_VECTOR ( 15 downto 0 );
cp_controller_cpstate : in STD_LOGIC_VECTOR ( 1 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\wdata_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
wr_enb_1_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_addr_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_addr_decoder is
signal \^q\ : STD_LOGIC_VECTOR ( 14 downto 0 );
signal in_strobe : STD_LOGIC;
signal \^write_reg_axi_enable\ : STD_LOGIC;
signal write_reg_d_k : STD_LOGIC_VECTOR ( 15 to 15 );
begin
Q(14 downto 0) <= \^q\(14 downto 0);
write_reg_axi_enable <= \^write_reg_axi_enable\;
\ARG_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => mul_temp_16(3),
O => DI(0)
);
ARG_carry_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => mul_temp_16(1),
O => \ARG__29\(2)
);
ARG_carry_i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => mul_temp_16(0),
O => \ARG__29\(1)
);
ARG_carry_i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => mul_temp_16(3),
O => \ARG__29\(0)
);
\cp_controller_cpstate[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0F20"
)
port map (
I0 => in_strobe,
I1 => cp_controller_cpstate(1),
I2 => \^write_reg_axi_enable\,
I3 => cp_controller_cpstate(0),
O => \cp_controller_cpstate_reg[0]\
);
read_reg_cop_out_ready_reg: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => AR(0),
D => cop_out_ready,
Q => read_reg_cop_out_ready
);
strobe_reg_cop_in_strobe_reg: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => AR(0),
D => strobe_sw_cop_in_strobe,
Q => in_strobe
);
\sub_temp_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(7),
I1 => filter_sum(7),
O => \sync_reg_e_k_reg[7]_0\(3)
);
\sub_temp_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(6),
I1 => filter_sum(6),
O => \sync_reg_e_k_reg[7]_0\(2)
);
\sub_temp_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(5),
I1 => filter_sum(5),
O => \sync_reg_e_k_reg[7]_0\(1)
);
\sub_temp_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => filter_sum(4),
O => \sync_reg_e_k_reg[7]_0\(0)
);
\sub_temp_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(11),
I1 => filter_sum(11),
O => \sync_reg_e_k_reg[11]_0\(3)
);
\sub_temp_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(10),
I1 => filter_sum(10),
O => \sync_reg_e_k_reg[11]_0\(2)
);
\sub_temp_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(9),
I1 => filter_sum(9),
O => \sync_reg_e_k_reg[11]_0\(1)
);
\sub_temp_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => filter_sum(8),
O => \sync_reg_e_k_reg[11]_0\(0)
);
\sub_temp_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => write_reg_d_k(15),
I1 => filter_sum(15),
O => S(3)
);
\sub_temp_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(14),
I1 => filter_sum(14),
O => S(2)
);
\sub_temp_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(13),
I1 => filter_sum(13),
O => S(1)
);
\sub_temp_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(12),
I1 => filter_sum(12),
O => S(0)
);
sub_temp_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => filter_sum(3),
O => \sync_reg_e_k_reg[3]_0\(3)
);
sub_temp_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => filter_sum(2),
O => \sync_reg_e_k_reg[3]_0\(2)
);
sub_temp_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => filter_sum(1),
O => \sync_reg_e_k_reg[3]_0\(1)
);
sub_temp_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(0),
I1 => filter_sum(0),
O => \sync_reg_e_k_reg[3]_0\(0)
);
\sync_reg_e_k_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(0),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(0)
);
\sync_reg_e_k_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(10),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(10)
);
\sync_reg_e_k_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(11),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(11)
);
\sync_reg_e_k_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(12),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(12)
);
\sync_reg_e_k_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(13),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(13)
);
\sync_reg_e_k_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(14),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(14)
);
\sync_reg_e_k_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(15),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(15)
);
\sync_reg_e_k_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(1),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(1)
);
\sync_reg_e_k_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(2),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(2)
);
\sync_reg_e_k_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(3),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(3)
);
\sync_reg_e_k_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(4),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(4)
);
\sync_reg_e_k_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(5),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(5)
);
\sync_reg_e_k_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(6),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(6)
);
\sync_reg_e_k_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(7),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(7)
);
\sync_reg_e_k_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(8),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(8)
);
\sync_reg_e_k_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(9),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(9)
);
write_reg_axi_enable_reg: unisim.vcomponents.FDPE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
D => \wdata_reg[0]\,
PRE => AR(0),
Q => \^write_reg_axi_enable\
);
\write_reg_d_k_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(0),
Q => \^q\(0)
);
\write_reg_d_k_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(10),
Q => \^q\(10)
);
\write_reg_d_k_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(11),
Q => \^q\(11)
);
\write_reg_d_k_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(12),
Q => \^q\(12)
);
\write_reg_d_k_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(13),
Q => \^q\(13)
);
\write_reg_d_k_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(14),
Q => \^q\(14)
);
\write_reg_d_k_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(15),
Q => write_reg_d_k(15)
);
\write_reg_d_k_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(1),
Q => \^q\(1)
);
\write_reg_d_k_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(2),
Q => \^q\(2)
);
\write_reg_d_k_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(3),
Q => \^q\(3)
);
\write_reg_d_k_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(4),
Q => \^q\(4)
);
\write_reg_d_k_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(5),
Q => \^q\(5)
);
\write_reg_d_k_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(6),
Q => \^q\(6)
);
\write_reg_d_k_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(7),
Q => \^q\(7)
);
\write_reg_d_k_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(8),
Q => \^q\(8)
);
\write_reg_d_k_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(9),
Q => \^q\(9)
);
\write_reg_x_k_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(0),
Q => \ARG__28\(0)
);
\write_reg_x_k_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(10),
Q => \ARG__28\(10)
);
\write_reg_x_k_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(11),
Q => \ARG__28\(11)
);
\write_reg_x_k_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(12),
Q => \ARG__28\(12)
);
\write_reg_x_k_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(13),
Q => \ARG__28\(13)
);
\write_reg_x_k_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(14),
Q => \ARG__28\(14)
);
\write_reg_x_k_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(15),
Q => \ARG__28\(15)
);
\write_reg_x_k_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(1),
Q => \ARG__28\(1)
);
\write_reg_x_k_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(2),
Q => \ARG__28\(2)
);
\write_reg_x_k_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(3),
Q => \ARG__28\(3)
);
\write_reg_x_k_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(4),
Q => \ARG__28\(4)
);
\write_reg_x_k_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(5),
Q => \ARG__28\(5)
);
\write_reg_x_k_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(6),
Q => \ARG__28\(6)
);
\write_reg_x_k_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(7),
Q => \ARG__28\(7)
);
\write_reg_x_k_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(8),
Q => \ARG__28\(8)
);
\write_reg_x_k_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(9),
Q => \ARG__28\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite_module is
port (
AXI4_Lite_RVALID : out STD_LOGIC;
write_reg_axi_enable_reg : out STD_LOGIC;
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BVALID : out STD_LOGIC;
write_reg_axi_enable_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWREADY : out STD_LOGIC;
strobe_sw_cop_in_strobe : out STD_LOGIC;
\write_reg_d_k_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
write_reg_axi_enable : in STD_LOGIC;
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
AXI4_Lite_BREADY : in STD_LOGIC;
\sync_reg_e_k_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
read_reg_cop_out_ready : in STD_LOGIC;
AXI4_Lite_RREADY : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite_module;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite_module is
signal \AXI4_Lite_RDATA_tmp[0]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[0]_i_3_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_10_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_11_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_12_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_9_n_0\ : STD_LOGIC;
signal \^axi4_lite_rvalid\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal aw_transfer : STD_LOGIC;
signal \axi_lite_rstate[0]_i_1_n_0\ : STD_LOGIC;
signal axi_lite_wstate : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axi_lite_wstate[0]_i_1_n_0\ : STD_LOGIC;
signal \axi_lite_wstate_next_inferred__1/i__n_0\ : STD_LOGIC;
signal data_read : STD_LOGIC_VECTOR ( 31 downto 0 );
signal reset : STD_LOGIC;
signal sel0 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal soft_reset : STD_LOGIC;
signal soft_reset_i_2_n_0 : STD_LOGIC;
signal soft_reset_i_3_n_0 : STD_LOGIC;
signal soft_reset_i_4_n_0 : STD_LOGIC;
signal strobe_reg_cop_in_strobe_i_3_n_0 : STD_LOGIC;
signal strobe_sw : STD_LOGIC;
signal top_rd_enb : STD_LOGIC;
signal top_wr_enb : STD_LOGIC;
signal w_transfer : STD_LOGIC;
signal write_reg_axi_enable_i_2_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of AXI4_Lite_BVALID_INST_0 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \AXI4_Lite_RDATA_tmp[0]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \AXI4_Lite_RDATA_tmp[31]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \AXI4_Lite_RDATA_tmp[31]_i_6\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \AXI4_Lite_RDATA_tmp[31]_i_7\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of AXI4_Lite_WREADY_INST_0 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \axi_lite_rstate[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axi_lite_wstate[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \axi_lite_wstate_next_inferred__1/i_\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of strobe_reg_cop_in_strobe_i_3 : label is "soft_lutpair1";
begin
AXI4_Lite_RVALID <= \^axi4_lite_rvalid\;
Q(15 downto 0) <= \^q\(15 downto 0);
AXI4_Lite_ARREADY_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axi4_lite_rvalid\,
O => AXI4_Lite_ARREADY
);
AXI4_Lite_AWREADY_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_lite_wstate(0),
I1 => axi_lite_wstate(1),
O => AXI4_Lite_AWREADY
);
AXI4_Lite_BVALID_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_lite_wstate(1),
I1 => axi_lite_wstate(0),
O => AXI4_Lite_BVALID
);
\AXI4_Lite_RDATA_tmp[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00008CCC00008000"
)
port map (
I0 => \sync_reg_e_k_reg[15]\(0),
I1 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[0]_i_2_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I5 => \AXI4_Lite_RDATA_tmp[0]_i_3_n_0\,
O => data_read(0)
);
\AXI4_Lite_RDATA_tmp[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => sel0(6),
I1 => AXI4_Lite_ARADDR(6),
I2 => sel0(0),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(0),
O => \AXI4_Lite_RDATA_tmp[0]_i_2_n_0\
);
\AXI4_Lite_RDATA_tmp[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000B80000000000"
)
port map (
I0 => AXI4_Lite_ARADDR(0),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(0),
I3 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I5 => read_reg_cop_out_ready,
O => \AXI4_Lite_RDATA_tmp[0]_i_3_n_0\
);
\AXI4_Lite_RDATA_tmp[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(10),
O => data_read(10)
);
\AXI4_Lite_RDATA_tmp[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(11),
O => data_read(11)
);
\AXI4_Lite_RDATA_tmp[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(12),
O => data_read(12)
);
\AXI4_Lite_RDATA_tmp[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(13),
O => data_read(13)
);
\AXI4_Lite_RDATA_tmp[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(14),
O => data_read(14)
);
\AXI4_Lite_RDATA_tmp[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(1),
O => data_read(1)
);
\AXI4_Lite_RDATA_tmp[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(2),
O => data_read(2)
);
\AXI4_Lite_RDATA_tmp[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => AXI4_Lite_ARVALID,
I1 => \^axi4_lite_rvalid\,
O => top_rd_enb
);
\AXI4_Lite_RDATA_tmp[31]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEEF0EE"
)
port map (
I0 => sel0(5),
I1 => sel0(4),
I2 => AXI4_Lite_ARADDR(5),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(4),
O => \AXI4_Lite_RDATA_tmp[31]_i_10_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEEF0EE"
)
port map (
I0 => sel0(3),
I1 => sel0(2),
I2 => AXI4_Lite_ARADDR(3),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(2),
O => \AXI4_Lite_RDATA_tmp[31]_i_11_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEEF0EE"
)
port map (
I0 => sel0(9),
I1 => sel0(8),
I2 => AXI4_Lite_ARADDR(9),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(8),
O => \AXI4_Lite_RDATA_tmp[31]_i_12_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(15),
O => data_read(31)
);
\AXI4_Lite_RDATA_tmp[31]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => AXI4_Lite_ARESETN,
O => reset
);
\AXI4_Lite_RDATA_tmp[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEFEFFFFAEFEA"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_9_n_0\,
I1 => AXI4_Lite_ARADDR(10),
I2 => AXI4_Lite_ARVALID,
I3 => sel0(10),
I4 => AXI4_Lite_ARADDR(11),
I5 => sel0(11),
O => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => AXI4_Lite_ARADDR(1),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(1),
O => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => AXI4_Lite_ARADDR(6),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(6),
O => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => AXI4_Lite_ARADDR(0),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(0),
O => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"00011101"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_10_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_11_n_0\,
I2 => sel0(7),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(7),
O => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFBBFCB8"
)
port map (
I0 => AXI4_Lite_ARADDR(13),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(13),
I3 => AXI4_Lite_ARADDR(12),
I4 => sel0(12),
I5 => \AXI4_Lite_RDATA_tmp[31]_i_12_n_0\,
O => \AXI4_Lite_RDATA_tmp[31]_i_9_n_0\
);
\AXI4_Lite_RDATA_tmp[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(3),
O => data_read(3)
);
\AXI4_Lite_RDATA_tmp[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(4),
O => data_read(4)
);
\AXI4_Lite_RDATA_tmp[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(5),
O => data_read(5)
);
\AXI4_Lite_RDATA_tmp[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(6),
O => data_read(6)
);
\AXI4_Lite_RDATA_tmp[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(7),
O => data_read(7)
);
\AXI4_Lite_RDATA_tmp[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(8),
O => data_read(8)
);
\AXI4_Lite_RDATA_tmp[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(9),
O => data_read(9)
);
\AXI4_Lite_RDATA_tmp_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(0),
Q => AXI4_Lite_RDATA(0)
);
\AXI4_Lite_RDATA_tmp_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(10),
Q => AXI4_Lite_RDATA(10)
);
\AXI4_Lite_RDATA_tmp_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(11),
Q => AXI4_Lite_RDATA(11)
);
\AXI4_Lite_RDATA_tmp_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(12),
Q => AXI4_Lite_RDATA(12)
);
\AXI4_Lite_RDATA_tmp_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(13),
Q => AXI4_Lite_RDATA(13)
);
\AXI4_Lite_RDATA_tmp_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(14),
Q => AXI4_Lite_RDATA(14)
);
\AXI4_Lite_RDATA_tmp_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(1),
Q => AXI4_Lite_RDATA(1)
);
\AXI4_Lite_RDATA_tmp_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(2),
Q => AXI4_Lite_RDATA(2)
);
\AXI4_Lite_RDATA_tmp_reg[31]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(31),
Q => AXI4_Lite_RDATA(15)
);
\AXI4_Lite_RDATA_tmp_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(3),
Q => AXI4_Lite_RDATA(3)
);
\AXI4_Lite_RDATA_tmp_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(4),
Q => AXI4_Lite_RDATA(4)
);
\AXI4_Lite_RDATA_tmp_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(5),
Q => AXI4_Lite_RDATA(5)
);
\AXI4_Lite_RDATA_tmp_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(6),
Q => AXI4_Lite_RDATA(6)
);
\AXI4_Lite_RDATA_tmp_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(7),
Q => AXI4_Lite_RDATA(7)
);
\AXI4_Lite_RDATA_tmp_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(8),
Q => AXI4_Lite_RDATA(8)
);
\AXI4_Lite_RDATA_tmp_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(9),
Q => AXI4_Lite_RDATA(9)
);
AXI4_Lite_WREADY_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_lite_wstate(0),
I1 => axi_lite_wstate(1),
O => AXI4_Lite_WREADY
);
\axi_lite_rstate[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => AXI4_Lite_RREADY,
I1 => \^axi4_lite_rvalid\,
I2 => AXI4_Lite_ARVALID,
O => \axi_lite_rstate[0]_i_1_n_0\
);
\axi_lite_rstate_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => \axi_lite_rstate[0]_i_1_n_0\,
Q => \^axi4_lite_rvalid\
);
\axi_lite_wstate[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"002E"
)
port map (
I0 => AXI4_Lite_AWVALID,
I1 => axi_lite_wstate(0),
I2 => AXI4_Lite_WVALID,
I3 => axi_lite_wstate(1),
O => \axi_lite_wstate[0]_i_1_n_0\
);
\axi_lite_wstate_next_inferred__1/i_\: unisim.vcomponents.LUT4
generic map(
INIT => X"0838"
)
port map (
I0 => AXI4_Lite_WVALID,
I1 => axi_lite_wstate(0),
I2 => axi_lite_wstate(1),
I3 => AXI4_Lite_BREADY,
O => \axi_lite_wstate_next_inferred__1/i__n_0\
);
\axi_lite_wstate_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => \axi_lite_wstate[0]_i_1_n_0\,
Q => axi_lite_wstate(0)
);
\axi_lite_wstate_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => \axi_lite_wstate_next_inferred__1/i__n_0\,
Q => axi_lite_wstate(1)
);
soft_reset_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200000000"
)
port map (
I0 => soft_reset_i_2_n_0,
I1 => sel0(1),
I2 => sel0(0),
I3 => sel0(7),
I4 => sel0(6),
I5 => soft_reset_i_3_n_0,
O => strobe_sw
);
soft_reset_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => sel0(13),
I1 => sel0(12),
I2 => sel0(11),
I3 => sel0(10),
O => soft_reset_i_2_n_0
);
soft_reset_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00010000"
)
port map (
I0 => sel0(2),
I1 => sel0(3),
I2 => sel0(8),
I3 => sel0(9),
I4 => soft_reset_i_4_n_0,
O => soft_reset_i_3_n_0
);
soft_reset_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => top_wr_enb,
I1 => \^q\(0),
I2 => sel0(5),
I3 => sel0(4),
O => soft_reset_i_4_n_0
);
soft_reset_reg: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => strobe_sw,
Q => soft_reset
);
strobe_reg_cop_in_strobe_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020000000"
)
port map (
I0 => \^q\(0),
I1 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I2 => strobe_reg_cop_in_strobe_i_3_n_0,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I4 => top_wr_enb,
I5 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
O => strobe_sw_cop_in_strobe
);
strobe_reg_cop_in_strobe_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => AXI4_Lite_ARESETN,
I1 => soft_reset,
I2 => IPCORE_RESETN,
O => write_reg_axi_enable_reg
);
strobe_reg_cop_in_strobe_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => sel0(1),
I1 => AXI4_Lite_ARADDR(1),
I2 => sel0(0),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(0),
O => strobe_reg_cop_in_strobe_i_3_n_0
);
\waddr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => AXI4_Lite_AWVALID,
I1 => axi_lite_wstate(1),
I2 => axi_lite_wstate(0),
O => aw_transfer
);
\waddr_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(8),
Q => sel0(8)
);
\waddr_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(9),
Q => sel0(9)
);
\waddr_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(10),
Q => sel0(10)
);
\waddr_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(11),
Q => sel0(11)
);
\waddr_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(12),
Q => sel0(12)
);
\waddr_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(13),
Q => sel0(13)
);
\waddr_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(0),
Q => sel0(0)
);
\waddr_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(1),
Q => sel0(1)
);
\waddr_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(2),
Q => sel0(2)
);
\waddr_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(3),
Q => sel0(3)
);
\waddr_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(4),
Q => sel0(4)
);
\waddr_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(5),
Q => sel0(5)
);
\waddr_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(6),
Q => sel0(6)
);
\waddr_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(7),
Q => sel0(7)
);
\wdata[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => AXI4_Lite_WVALID,
I1 => axi_lite_wstate(1),
I2 => axi_lite_wstate(0),
O => w_transfer
);
\wdata_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(0),
Q => \^q\(0)
);
\wdata_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(10),
Q => \^q\(10)
);
\wdata_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(11),
Q => \^q\(11)
);
\wdata_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(12),
Q => \^q\(12)
);
\wdata_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(13),
Q => \^q\(13)
);
\wdata_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(14),
Q => \^q\(14)
);
\wdata_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(15),
Q => \^q\(15)
);
\wdata_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(1),
Q => \^q\(1)
);
\wdata_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(2),
Q => \^q\(2)
);
\wdata_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(3),
Q => \^q\(3)
);
\wdata_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(4),
Q => \^q\(4)
);
\wdata_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(5),
Q => \^q\(5)
);
\wdata_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(6),
Q => \^q\(6)
);
\wdata_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(7),
Q => \^q\(7)
);
\wdata_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(8),
Q => \^q\(8)
);
\wdata_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(9),
Q => \^q\(9)
);
wr_enb_1_reg: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => w_transfer,
Q => top_wr_enb
);
write_reg_axi_enable_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFFF00008000"
)
port map (
I0 => \^q\(0),
I1 => write_reg_axi_enable_i_2_n_0,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I3 => top_wr_enb,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I5 => write_reg_axi_enable,
O => write_reg_axi_enable_reg_0
);
write_reg_axi_enable_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000047034400"
)
port map (
I0 => AXI4_Lite_ARADDR(6),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(6),
I3 => AXI4_Lite_ARADDR(0),
I4 => sel0(0),
I5 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
O => write_reg_axi_enable_i_2_n_0
);
\write_reg_d_k[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I4 => top_wr_enb,
I5 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
O => \write_reg_d_k_reg[15]\(0)
);
\write_reg_x_k[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I4 => top_wr_enb,
I5 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
O => E(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_cop is
port (
cp_controller_cpstate : out STD_LOGIC_VECTOR ( 1 downto 0 );
cop_out_ready : out STD_LOGIC;
cop_dut_enable : out STD_LOGIC;
strobe_reg_cop_in_strobe_reg : in STD_LOGIC;
IPCORE_CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
write_reg_axi_enable : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_cop;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_cop is
signal \^cp_controller_cpstate\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cp_controller_cpstate[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cp_controller_cpstate[1]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of read_reg_cop_out_ready_i_1 : label is "soft_lutpair5";
begin
cp_controller_cpstate(1 downto 0) <= \^cp_controller_cpstate\(1 downto 0);
\cp_controller_cpstate[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"38"
)
port map (
I0 => \^cp_controller_cpstate\(0),
I1 => write_reg_axi_enable,
I2 => \^cp_controller_cpstate\(1),
O => \cp_controller_cpstate[1]_i_1_n_0\
);
\cp_controller_cpstate_reg[0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => '1',
CLR => AR(0),
D => strobe_reg_cop_in_strobe_reg,
Q => \^cp_controller_cpstate\(0)
);
\cp_controller_cpstate_reg[1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => '1',
CLR => AR(0),
D => \cp_controller_cpstate[1]_i_1_n_0\,
Q => \^cp_controller_cpstate\(1)
);
\data_pipeline_tmp[14][15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^cp_controller_cpstate\(0),
I1 => \^cp_controller_cpstate\(1),
O => cop_dut_enable
);
read_reg_cop_out_ready_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cp_controller_cpstate\(0),
I1 => \^cp_controller_cpstate\(1),
O => cop_out_ready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite is
port (
write_reg_axi_enable_reg : out STD_LOGIC;
AXI4_Lite_RVALID : out STD_LOGIC;
write_reg_axi_enable : out STD_LOGIC;
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BVALID : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 14 downto 0 );
\sync_reg_e_k_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\sync_reg_e_k_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\sync_reg_e_k_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
DI : out STD_LOGIC_VECTOR ( 0 to 0 );
\ARG__29\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\cp_controller_cpstate_reg[0]\ : out STD_LOGIC;
\ARG__28\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWREADY : out STD_LOGIC;
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
cop_out_ready : in STD_LOGIC;
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
filter_sum : in STD_LOGIC_VECTOR ( 15 downto 0 );
mul_temp_16 : in STD_LOGIC_VECTOR ( 15 downto 0 );
cp_controller_cpstate : in STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
AXI4_Lite_BREADY : in STD_LOGIC;
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
AXI4_Lite_RREADY : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite is
signal read_reg_cop_out_ready : STD_LOGIC;
signal reg_enb_d_k : STD_LOGIC;
signal reg_enb_x_k : STD_LOGIC;
signal strobe_sw_cop_in_strobe : STD_LOGIC;
signal sync_reg_e_k : STD_LOGIC_VECTOR ( 15 downto 0 );
signal top_data_write : STD_LOGIC_VECTOR ( 0 to 0 );
signal u_lms_pcore_axi_lite_module_inst_n_10 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_11 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_12 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_13 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_14 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_15 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_16 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_17 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_18 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_19 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_4 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_5 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_6 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_7 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_8 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_9 : STD_LOGIC;
signal \^write_reg_axi_enable\ : STD_LOGIC;
signal \^write_reg_axi_enable_reg\ : STD_LOGIC;
begin
write_reg_axi_enable <= \^write_reg_axi_enable\;
write_reg_axi_enable_reg <= \^write_reg_axi_enable_reg\;
u_lms_pcore_addr_decoder_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_addr_decoder
port map (
AR(0) => \^write_reg_axi_enable_reg\,
\ARG__28\(15 downto 0) => \ARG__28\(15 downto 0),
\ARG__29\(2 downto 0) => \ARG__29\(2 downto 0),
AXI4_Lite_ACLK => AXI4_Lite_ACLK,
\AXI4_Lite_RDATA_tmp_reg[31]\(15 downto 0) => sync_reg_e_k(15 downto 0),
DI(0) => DI(0),
E(0) => reg_enb_x_k,
Q(14 downto 0) => Q(14 downto 0),
S(3 downto 0) => S(3 downto 0),
cop_out_ready => cop_out_ready,
cp_controller_cpstate(1 downto 0) => cp_controller_cpstate(1 downto 0),
\cp_controller_cpstate_reg[0]\ => \cp_controller_cpstate_reg[0]\,
filter_sum(15 downto 0) => filter_sum(15 downto 0),
mul_temp_16(15 downto 0) => mul_temp_16(15 downto 0),
read_reg_cop_out_ready => read_reg_cop_out_ready,
strobe_sw_cop_in_strobe => strobe_sw_cop_in_strobe,
\sync_reg_e_k_reg[11]_0\(3 downto 0) => \sync_reg_e_k_reg[11]\(3 downto 0),
\sync_reg_e_k_reg[3]_0\(3 downto 0) => \sync_reg_e_k_reg[3]\(3 downto 0),
\sync_reg_e_k_reg[7]_0\(3 downto 0) => \sync_reg_e_k_reg[7]\(3 downto 0),
\wdata_reg[0]\ => u_lms_pcore_axi_lite_module_inst_n_4,
\wdata_reg[15]\(15) => u_lms_pcore_axi_lite_module_inst_n_5,
\wdata_reg[15]\(14) => u_lms_pcore_axi_lite_module_inst_n_6,
\wdata_reg[15]\(13) => u_lms_pcore_axi_lite_module_inst_n_7,
\wdata_reg[15]\(12) => u_lms_pcore_axi_lite_module_inst_n_8,
\wdata_reg[15]\(11) => u_lms_pcore_axi_lite_module_inst_n_9,
\wdata_reg[15]\(10) => u_lms_pcore_axi_lite_module_inst_n_10,
\wdata_reg[15]\(9) => u_lms_pcore_axi_lite_module_inst_n_11,
\wdata_reg[15]\(8) => u_lms_pcore_axi_lite_module_inst_n_12,
\wdata_reg[15]\(7) => u_lms_pcore_axi_lite_module_inst_n_13,
\wdata_reg[15]\(6) => u_lms_pcore_axi_lite_module_inst_n_14,
\wdata_reg[15]\(5) => u_lms_pcore_axi_lite_module_inst_n_15,
\wdata_reg[15]\(4) => u_lms_pcore_axi_lite_module_inst_n_16,
\wdata_reg[15]\(3) => u_lms_pcore_axi_lite_module_inst_n_17,
\wdata_reg[15]\(2) => u_lms_pcore_axi_lite_module_inst_n_18,
\wdata_reg[15]\(1) => u_lms_pcore_axi_lite_module_inst_n_19,
\wdata_reg[15]\(0) => top_data_write(0),
wr_enb_1_reg(0) => reg_enb_d_k,
write_reg_axi_enable => \^write_reg_axi_enable\
);
u_lms_pcore_axi_lite_module_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite_module
port map (
AXI4_Lite_ACLK => AXI4_Lite_ACLK,
AXI4_Lite_ARADDR(13 downto 0) => AXI4_Lite_ARADDR(13 downto 0),
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN,
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY,
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID,
AXI4_Lite_AWADDR(13 downto 0) => AXI4_Lite_AWADDR(13 downto 0),
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY,
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID,
AXI4_Lite_BREADY => AXI4_Lite_BREADY,
AXI4_Lite_BVALID => AXI4_Lite_BVALID,
AXI4_Lite_RDATA(15 downto 0) => AXI4_Lite_RDATA(15 downto 0),
AXI4_Lite_RREADY => AXI4_Lite_RREADY,
AXI4_Lite_RVALID => AXI4_Lite_RVALID,
AXI4_Lite_WDATA(15 downto 0) => AXI4_Lite_WDATA(15 downto 0),
AXI4_Lite_WREADY => AXI4_Lite_WREADY,
AXI4_Lite_WVALID => AXI4_Lite_WVALID,
E(0) => reg_enb_x_k,
IPCORE_RESETN => IPCORE_RESETN,
Q(15) => u_lms_pcore_axi_lite_module_inst_n_5,
Q(14) => u_lms_pcore_axi_lite_module_inst_n_6,
Q(13) => u_lms_pcore_axi_lite_module_inst_n_7,
Q(12) => u_lms_pcore_axi_lite_module_inst_n_8,
Q(11) => u_lms_pcore_axi_lite_module_inst_n_9,
Q(10) => u_lms_pcore_axi_lite_module_inst_n_10,
Q(9) => u_lms_pcore_axi_lite_module_inst_n_11,
Q(8) => u_lms_pcore_axi_lite_module_inst_n_12,
Q(7) => u_lms_pcore_axi_lite_module_inst_n_13,
Q(6) => u_lms_pcore_axi_lite_module_inst_n_14,
Q(5) => u_lms_pcore_axi_lite_module_inst_n_15,
Q(4) => u_lms_pcore_axi_lite_module_inst_n_16,
Q(3) => u_lms_pcore_axi_lite_module_inst_n_17,
Q(2) => u_lms_pcore_axi_lite_module_inst_n_18,
Q(1) => u_lms_pcore_axi_lite_module_inst_n_19,
Q(0) => top_data_write(0),
read_reg_cop_out_ready => read_reg_cop_out_ready,
strobe_sw_cop_in_strobe => strobe_sw_cop_in_strobe,
\sync_reg_e_k_reg[15]\(15 downto 0) => sync_reg_e_k(15 downto 0),
write_reg_axi_enable => \^write_reg_axi_enable\,
write_reg_axi_enable_reg => \^write_reg_axi_enable_reg\,
write_reg_axi_enable_reg_0 => u_lms_pcore_axi_lite_module_inst_n_4,
\write_reg_d_k_reg[15]\(0) => reg_enb_d_k
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_dut is
port (
mul_temp_16 : out STD_LOGIC_VECTOR ( 15 downto 0 );
filter_sum : out STD_LOGIC_VECTOR ( 15 downto 0 );
\write_reg_x_k_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
cop_dut_enable : in STD_LOGIC;
IPCORE_CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\write_reg_d_k_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
DI : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 14 downto 0 );
\write_reg_d_k_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\write_reg_d_k_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\write_reg_d_k_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_dut;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_dut is
begin
u_LMS: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_LMS
port map (
AR(0) => AR(0),
DI(0) => DI(0),
IPCORE_CLK => IPCORE_CLK,
Q(14 downto 0) => Q(14 downto 0),
S(3 downto 0) => S(3 downto 0),
cop_dut_enable => cop_dut_enable,
filter_sum(15 downto 0) => filter_sum(15 downto 0),
mul_temp_16(15 downto 0) => mul_temp_16(15 downto 0),
\write_reg_d_k_reg[11]\(3 downto 0) => \write_reg_d_k_reg[11]\(3 downto 0),
\write_reg_d_k_reg[3]\(2 downto 0) => \write_reg_d_k_reg[3]\(2 downto 0),
\write_reg_d_k_reg[3]_0\(3 downto 0) => \write_reg_d_k_reg[3]_0\(3 downto 0),
\write_reg_d_k_reg[7]\(3 downto 0) => \write_reg_d_k_reg[7]\(3 downto 0),
\write_reg_x_k_reg[15]\(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore is
port (
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BVALID : out STD_LOGIC;
AXI4_Lite_RVALID : out STD_LOGIC;
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_AWREADY : out STD_LOGIC;
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ACLK : in STD_LOGIC;
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
IPCORE_CLK : in STD_LOGIC;
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
AXI4_Lite_RREADY : in STD_LOGIC;
AXI4_Lite_BREADY : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore is
signal cop_dut_enable : STD_LOGIC;
signal cop_out_ready : STD_LOGIC;
signal cp_controller_cpstate : STD_LOGIC_VECTOR ( 1 downto 0 );
signal filter_sum : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \u_LMS/mul_temp_16\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal u_lms_pcore_axi_lite_inst_n_0 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_24 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_25 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_26 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_27 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_28 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_29 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_30 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_31 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_32 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_33 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_34 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_35 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_36 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_37 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_38 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_39 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_40 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_5 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_6 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_7 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_8 : STD_LOGIC;
signal write_reg_axi_enable : STD_LOGIC;
signal write_reg_d_k : STD_LOGIC_VECTOR ( 14 downto 0 );
signal write_reg_x_k : STD_LOGIC_VECTOR ( 15 downto 0 );
begin
u_lms_pcore_axi_lite_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite
port map (
\ARG__28\(15 downto 0) => write_reg_x_k(15 downto 0),
\ARG__29\(2) => u_lms_pcore_axi_lite_inst_n_37,
\ARG__29\(1) => u_lms_pcore_axi_lite_inst_n_38,
\ARG__29\(0) => u_lms_pcore_axi_lite_inst_n_39,
AXI4_Lite_ACLK => AXI4_Lite_ACLK,
AXI4_Lite_ARADDR(13 downto 0) => AXI4_Lite_ARADDR(13 downto 0),
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN,
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY,
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID,
AXI4_Lite_AWADDR(13 downto 0) => AXI4_Lite_AWADDR(13 downto 0),
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY,
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID,
AXI4_Lite_BREADY => AXI4_Lite_BREADY,
AXI4_Lite_BVALID => AXI4_Lite_BVALID,
AXI4_Lite_RDATA(15 downto 0) => AXI4_Lite_RDATA(15 downto 0),
AXI4_Lite_RREADY => AXI4_Lite_RREADY,
AXI4_Lite_RVALID => AXI4_Lite_RVALID,
AXI4_Lite_WDATA(15 downto 0) => AXI4_Lite_WDATA(15 downto 0),
AXI4_Lite_WREADY => AXI4_Lite_WREADY,
AXI4_Lite_WVALID => AXI4_Lite_WVALID,
DI(0) => u_lms_pcore_axi_lite_inst_n_36,
IPCORE_RESETN => IPCORE_RESETN,
Q(14 downto 0) => write_reg_d_k(14 downto 0),
S(3) => u_lms_pcore_axi_lite_inst_n_5,
S(2) => u_lms_pcore_axi_lite_inst_n_6,
S(1) => u_lms_pcore_axi_lite_inst_n_7,
S(0) => u_lms_pcore_axi_lite_inst_n_8,
cop_out_ready => cop_out_ready,
cp_controller_cpstate(1 downto 0) => cp_controller_cpstate(1 downto 0),
\cp_controller_cpstate_reg[0]\ => u_lms_pcore_axi_lite_inst_n_40,
filter_sum(15 downto 0) => filter_sum(15 downto 0),
mul_temp_16(15 downto 0) => \u_LMS/mul_temp_16\(15 downto 0),
\sync_reg_e_k_reg[11]\(3) => u_lms_pcore_axi_lite_inst_n_24,
\sync_reg_e_k_reg[11]\(2) => u_lms_pcore_axi_lite_inst_n_25,
\sync_reg_e_k_reg[11]\(1) => u_lms_pcore_axi_lite_inst_n_26,
\sync_reg_e_k_reg[11]\(0) => u_lms_pcore_axi_lite_inst_n_27,
\sync_reg_e_k_reg[3]\(3) => u_lms_pcore_axi_lite_inst_n_32,
\sync_reg_e_k_reg[3]\(2) => u_lms_pcore_axi_lite_inst_n_33,
\sync_reg_e_k_reg[3]\(1) => u_lms_pcore_axi_lite_inst_n_34,
\sync_reg_e_k_reg[3]\(0) => u_lms_pcore_axi_lite_inst_n_35,
\sync_reg_e_k_reg[7]\(3) => u_lms_pcore_axi_lite_inst_n_28,
\sync_reg_e_k_reg[7]\(2) => u_lms_pcore_axi_lite_inst_n_29,
\sync_reg_e_k_reg[7]\(1) => u_lms_pcore_axi_lite_inst_n_30,
\sync_reg_e_k_reg[7]\(0) => u_lms_pcore_axi_lite_inst_n_31,
write_reg_axi_enable => write_reg_axi_enable,
write_reg_axi_enable_reg => u_lms_pcore_axi_lite_inst_n_0
);
u_lms_pcore_cop_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_cop
port map (
AR(0) => u_lms_pcore_axi_lite_inst_n_0,
IPCORE_CLK => IPCORE_CLK,
cop_dut_enable => cop_dut_enable,
cop_out_ready => cop_out_ready,
cp_controller_cpstate(1 downto 0) => cp_controller_cpstate(1 downto 0),
strobe_reg_cop_in_strobe_reg => u_lms_pcore_axi_lite_inst_n_40,
write_reg_axi_enable => write_reg_axi_enable
);
u_lms_pcore_dut_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_dut
port map (
AR(0) => u_lms_pcore_axi_lite_inst_n_0,
DI(0) => u_lms_pcore_axi_lite_inst_n_36,
IPCORE_CLK => IPCORE_CLK,
Q(14 downto 0) => write_reg_d_k(14 downto 0),
S(3) => u_lms_pcore_axi_lite_inst_n_5,
S(2) => u_lms_pcore_axi_lite_inst_n_6,
S(1) => u_lms_pcore_axi_lite_inst_n_7,
S(0) => u_lms_pcore_axi_lite_inst_n_8,
cop_dut_enable => cop_dut_enable,
filter_sum(15 downto 0) => filter_sum(15 downto 0),
mul_temp_16(15 downto 0) => \u_LMS/mul_temp_16\(15 downto 0),
\write_reg_d_k_reg[11]\(3) => u_lms_pcore_axi_lite_inst_n_24,
\write_reg_d_k_reg[11]\(2) => u_lms_pcore_axi_lite_inst_n_25,
\write_reg_d_k_reg[11]\(1) => u_lms_pcore_axi_lite_inst_n_26,
\write_reg_d_k_reg[11]\(0) => u_lms_pcore_axi_lite_inst_n_27,
\write_reg_d_k_reg[3]\(2) => u_lms_pcore_axi_lite_inst_n_37,
\write_reg_d_k_reg[3]\(1) => u_lms_pcore_axi_lite_inst_n_38,
\write_reg_d_k_reg[3]\(0) => u_lms_pcore_axi_lite_inst_n_39,
\write_reg_d_k_reg[3]_0\(3) => u_lms_pcore_axi_lite_inst_n_32,
\write_reg_d_k_reg[3]_0\(2) => u_lms_pcore_axi_lite_inst_n_33,
\write_reg_d_k_reg[3]_0\(1) => u_lms_pcore_axi_lite_inst_n_34,
\write_reg_d_k_reg[3]_0\(0) => u_lms_pcore_axi_lite_inst_n_35,
\write_reg_d_k_reg[7]\(3) => u_lms_pcore_axi_lite_inst_n_28,
\write_reg_d_k_reg[7]\(2) => u_lms_pcore_axi_lite_inst_n_29,
\write_reg_d_k_reg[7]\(1) => u_lms_pcore_axi_lite_inst_n_30,
\write_reg_d_k_reg[7]\(0) => u_lms_pcore_axi_lite_inst_n_31,
\write_reg_x_k_reg[15]\(15 downto 0) => write_reg_x_k(15 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
IPCORE_CLK : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
AXI4_Lite_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_BREADY : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_RREADY : in STD_LOGIC;
AXI4_Lite_AWREADY : out STD_LOGIC;
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_BVALID : out STD_LOGIC;
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
AXI4_Lite_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_RVALID : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_lms_pcore_0_0,lms_pcore,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "lms_pcore,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal \<const0>\ : STD_LOGIC;
signal \^axi4_lite_rdata\ : STD_LOGIC_VECTOR ( 30 downto 0 );
attribute x_interface_info : string;
attribute x_interface_info of AXI4_Lite_ACLK : signal is "xilinx.com:signal:clock:1.0 AXI4_Lite_ACLK CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of AXI4_Lite_ACLK : signal is "XIL_INTERFACENAME AXI4_Lite_ACLK, ASSOCIATED_RESET AXI4_Lite_ARESETN, ASSOCIATED_BUSIF AXI4_Lite, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of AXI4_Lite_ARESETN : signal is "xilinx.com:signal:reset:1.0 AXI4_Lite_ARESETN RST";
attribute x_interface_parameter of AXI4_Lite_ARESETN : signal is "XIL_INTERFACENAME AXI4_Lite_ARESETN, POLARITY ACTIVE_LOW";
attribute x_interface_info of AXI4_Lite_ARREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite ARREADY";
attribute x_interface_info of AXI4_Lite_ARVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite ARVALID";
attribute x_interface_info of AXI4_Lite_AWREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite AWREADY";
attribute x_interface_info of AXI4_Lite_AWVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite AWVALID";
attribute x_interface_info of AXI4_Lite_BREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite BREADY";
attribute x_interface_info of AXI4_Lite_BVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite BVALID";
attribute x_interface_info of AXI4_Lite_RREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite RREADY";
attribute x_interface_info of AXI4_Lite_RVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite RVALID";
attribute x_interface_info of AXI4_Lite_WREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite WREADY";
attribute x_interface_info of AXI4_Lite_WVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite WVALID";
attribute x_interface_info of IPCORE_CLK : signal is "xilinx.com:signal:clock:1.0 IPCORE_CLK CLK";
attribute x_interface_parameter of IPCORE_CLK : signal is "XIL_INTERFACENAME IPCORE_CLK, ASSOCIATED_RESET IPCORE_RESETN, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of IPCORE_RESETN : signal is "xilinx.com:signal:reset:1.0 IPCORE_RESETN RST";
attribute x_interface_parameter of IPCORE_RESETN : signal is "XIL_INTERFACENAME IPCORE_RESETN, POLARITY ACTIVE_LOW";
attribute x_interface_info of AXI4_Lite_ARADDR : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite ARADDR";
attribute x_interface_info of AXI4_Lite_AWADDR : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite AWADDR";
attribute x_interface_parameter of AXI4_Lite_AWADDR : signal is "XIL_INTERFACENAME AXI4_Lite, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute x_interface_info of AXI4_Lite_BRESP : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite BRESP";
attribute x_interface_info of AXI4_Lite_RDATA : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite RDATA";
attribute x_interface_info of AXI4_Lite_RRESP : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite RRESP";
attribute x_interface_info of AXI4_Lite_WDATA : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite WDATA";
attribute x_interface_info of AXI4_Lite_WSTRB : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite WSTRB";
begin
AXI4_Lite_BRESP(1) <= \<const0>\;
AXI4_Lite_BRESP(0) <= \<const0>\;
AXI4_Lite_RDATA(31) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(30) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(29) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(28) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(27) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(26) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(25) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(24) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(23) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(22) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(21) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(20) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(19) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(18) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(17) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(16) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(15) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(14 downto 0) <= \^axi4_lite_rdata\(14 downto 0);
AXI4_Lite_RRESP(1) <= \<const0>\;
AXI4_Lite_RRESP(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore
port map (
AXI4_Lite_ACLK => AXI4_Lite_ACLK,
AXI4_Lite_ARADDR(13 downto 0) => AXI4_Lite_ARADDR(15 downto 2),
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN,
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY,
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID,
AXI4_Lite_AWADDR(13 downto 0) => AXI4_Lite_AWADDR(15 downto 2),
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY,
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID,
AXI4_Lite_BREADY => AXI4_Lite_BREADY,
AXI4_Lite_BVALID => AXI4_Lite_BVALID,
AXI4_Lite_RDATA(15) => \^axi4_lite_rdata\(30),
AXI4_Lite_RDATA(14 downto 0) => \^axi4_lite_rdata\(14 downto 0),
AXI4_Lite_RREADY => AXI4_Lite_RREADY,
AXI4_Lite_RVALID => AXI4_Lite_RVALID,
AXI4_Lite_WDATA(15 downto 0) => AXI4_Lite_WDATA(15 downto 0),
AXI4_Lite_WREADY => AXI4_Lite_WREADY,
AXI4_Lite_WVALID => AXI4_Lite_WVALID,
IPCORE_CLK => IPCORE_CLK,
IPCORE_RESETN => IPCORE_RESETN
);
end STRUCTURE;
| mit | 86da6b775f25bda02070c9fea8011435 | 0.528968 | 2.58885 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/ddr/ddr2spax.vhd | 1 | 8,952 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2spax
-- File: ddr2spax.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: DDR2 memory controller with asynch AHB interface
-- Based on ddr2sp(16/32/64)a, generalized and expanded
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
library techmap;
use techmap.gencomp.ddr2phy_has_datavalid;
use techmap.gencomp.ddr2phy_ptctrl;
entity ddr2spax is
generic (
memtech : integer := 0;
phytech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
TRFC : integer := 130;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0;
octen : integer := 0;
-- dqsgating : integer := 0;
nosync : integer := 0;
dqsgating : integer := 0;
eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4
dqsse : integer range 0 to 1 := 0; -- single ended DQS
ddr_syncrst: integer range 0 to 1 := 0;
ahbbits : integer := ahbdw;
ft : integer range 0 to 1 := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
hwidthen : integer range 0 to 1 := 0;
rstdel : integer := 200;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
ahb_rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
hwidth : in std_ulogic
);
end ddr2spax;
architecture rtl of ddr2spax is
constant REVISION : integer := 1;
constant ramwt: integer := 0;
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ddrw: integer := log2(ddrbits*2);
function pick(choice: boolean; t,f: integer) return integer is
begin
if choice then return t; else return f; end if;
end;
constant xahbw: integer := pick(ft/=0 and ahbbits<64, 64, ahbbits);
constant l2ahbw: integer := log2(xahbw);
-- For non-FT, write buffer has room for two write bursts and is addressable
-- down to 32-bit level on write (AHB) side.
-- For FT, the write buffer has room for one write burst and is addressable
-- down to 64-bit level on write side.
-- Write buffer dimensions
constant wbuf_rabits_s: integer := 1+l2blen-l2ddrw;
constant wbuf_rabits_r: integer := wbuf_rabits_s-FT;
constant wbuf_rdbits: integer := pick(ft/=0, 3*ddrbits, 2*ddrbits);
constant wbuf_wabits: integer := pick(ft/=0, l2blen-6, 1+l2blen-5);
constant wbuf_wdbits: integer := pick(ft/=0, xahbw+xahbw/2, xahbw);
-- Read buffer dimensions
constant rbuf_rabits: integer := l2blen-l2ahbw;
constant rbuf_rdbits: integer := wbuf_wdbits;
constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant rbuf_wdbits: integer := pick(ft/=0, 3*ddrbits, 2*ddrbits);
signal request : ddr_request_type;
signal start_tog : std_logic;
signal response : ddr_response_type;
signal wbwaddr: std_logic_vector(wbuf_wabits-1 downto 0);
signal wbwdata: std_logic_vector(wbuf_wdbits-1 downto 0);
signal wbraddr: std_logic_vector(wbuf_rabits_s-1 downto 0);
signal wbrdata: std_logic_vector(wbuf_rdbits-1 downto 0);
signal rbwaddr: std_logic_vector(rbuf_wabits-1 downto 0);
signal rbwdata: std_logic_vector(rbuf_wdbits-1 downto 0);
signal rbraddr: std_logic_vector(rbuf_rabits-1 downto 0);
signal rbrdata: std_logic_vector(rbuf_rdbits-1 downto 0);
signal wbwrite,wbwritebig,rbwrite: std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep of rbwdata : signal is true;
attribute syn_keep of rbwdata : signal is true;
attribute syn_preserve of rbwdata : signal is true;
signal vcc: std_ulogic;
signal sdox: ddrctrl_out_type;
signal ce: std_logic;
begin
vcc <= '1';
gft0: if ft=0 generate
ahbc : ddr2spax_ahb
generic map (hindex => hindex, haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
nosync => nosync, burstlen => burstlen, ahbbits => xahbw, revision => revision,
ddrbits => ddrbits, regarea => 0)
port map (ahb_rst, clk_ahb, ahbsi, ahbso, request, start_tog, response,
wbwaddr, wbwdata, wbwrite, wbwritebig, rbraddr, rbrdata, hwidth, FTFE_BEID_DDR2);
ce <= '0';
end generate;
gft1: if ft/=0 generate
ftc: ft_ddr2spax_ahb
generic map (hindex => hindex, haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
nosync => nosync, burstlen => burstlen, ahbbits => xahbw, bufbits => xahbw+xahbw/2,
ddrbits => ddrbits, hwidthen => hwidthen, devid => GAISLER_DDR2SP, revision => revision)
port map (ahb_rst, clk_ahb, ahbsi, ahbso, ce, request, start_tog, response,
wbwaddr, wbwdata, wbwrite, wbwritebig, rbraddr, rbrdata, hwidth, '0', open, open, FTFE_BEID_DDR2);
end generate;
ddrc : ddr2spax_ddr
generic map (ddrbits => ddrbits,
pwron => pwron, MHz => MHz, TRFC => TRFC, col => col, Mbyte => Mbyte,
readdly => readdly, odten => odten, octen => octen, dqsgating => dqsgating,
nosync => nosync, eightbanks => eightbanks, dqsse => dqsse, burstlen => burstlen,
chkbits => ft*ddrbits/2, bigmem => bigmem, raspipe => raspipe,
hwidthen => hwidthen, phytech => phytech, hasdqvalid => ddr2phy_has_datavalid(phytech),
rstdel => rstdel, phyptctrl => ddr2phy_ptctrl(phytech), scantest => scantest,
ddr_syncrst => ddr_syncrst)
port map (ddr_rst, clk_ddr, request, start_tog, response, sdi, sdox,
wbraddr, wbrdata, rbwaddr, rbwdata, rbwrite, hwidth,
'0', ddr_request_none, open, ahbsi.testen, ahbsi.testrst, ahbsi.testoen);
sdoproc: process(sdox,ce)
variable o: ddrctrl_out_type;
begin
o := sdox;
o.ce := ce;
sdo <= o;
end process;
wbuf: ddr2buf
generic map (tech => memtech, wabits => wbuf_wabits, wdbits => wbuf_wdbits,
rabits => wbuf_rabits_r, rdbits => wbuf_rdbits,
sepclk => 1, wrfst => ramwt)
port map ( rclk => clk_ddr, renable => vcc, raddress => wbraddr(wbuf_rabits_r-1 downto 0),
dataout => wbrdata, wclk => clk_ahb, write => wbwrite,
writebig => wbwritebig, waddress => wbwaddr, datain => wbwdata);
rbuf: ddr2buf
generic map (tech => memtech, wabits => rbuf_wabits, wdbits => rbuf_wdbits,
rabits => rbuf_rabits, rdbits => rbuf_rdbits,
sepclk => 1, wrfst => ramwt)
port map ( rclk => clk_ahb, renable => vcc, raddress => rbraddr,
dataout => rbrdata,
wclk => clk_ddr, write => rbwrite,
writebig => '0', waddress => rbwaddr, datain => rbwdata);
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ddr2spa: DDR2 controller rev " &
tost(REVISION) & ", " & tost(ddrbits) & " bit width, " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
| gpl-2.0 | 830fa0e0039cc9706c46471628c3c090 | 0.599531 | 3.893867 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-3/src/DELAR.vhd | 1 | 380 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DELAR is port(
D : in std_logic;
E : in std_logic;
CLR : in std_logic;
Q : out std_logic
);
end DELAR;
architecture behavior of DELAR is
signal S : std_logic;
begin
Main : process (D, E, CLR)
begin
if(CLR = '1') then
S <= '0';
elsif(E='1') then
S <= D;
end if;
end process;
Q <= S;
end behavior;
| mit | ffca51943b4a90d52d852e46eac57397 | 0.6 | 2.467532 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/uart/libdcom.vhd | 1 | 5,314 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libdcom
-- File: libdcom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Types, functions and components for DSU uart
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.uart.all;
use gaisler.misc.all;
package libdcom is
type dcom_uart_in_type is record
read : std_ulogic;
write : std_ulogic;
data : std_logic_vector(7 downto 0);
end record;
type dcom_uart_out_type is record
dready : std_ulogic;
tsempty : std_ulogic;
thempty : std_ulogic;
lock : std_ulogic;
enable : std_ulogic;
data : std_logic_vector(7 downto 0);
end record;
component dcom_uart
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ui : in uart_in_type;
uo : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in dcom_uart_in_type;
uarto : out dcom_uart_out_type
);
end component;
component dcom
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : out ahb_dma_in_type;
dmao : in ahb_dma_out_type;
uarti : out dcom_uart_in_type;
uarto : in dcom_uart_out_type;
ahbi : in ahb_mst_in_type
);
end component;
-- pragma translate_off
procedure rxc(signal rxd : in std_logic; d: out std_logic_vector;
txperiod : time);
procedure rxi(signal rxd : in std_logic; d: out std_logic_vector;
txperiod : time; lresp : boolean);
procedure txc(signal txd : out std_logic; td : integer;
txperiod : time);
procedure txa(signal txd : out std_logic; td1, td2, td3, td4 : integer;
txperiod : time);
procedure txi(signal rxd : in std_logic; signal txd : out std_logic;
td1, td2, td3, td4 : integer; txperiod : time;
lresp : boolean);
-- pragma translate_on
end;
-- pragma translate_off
package body libdcom is
procedure rxc(signal rxd : in std_logic; d: out std_logic_vector;
txperiod : time) is
variable rxdata : std_logic_vector(7 downto 0);
begin
wait until rxd = '0'; wait for TXPERIOD/2;
for i in 0 to 7 loop wait for TXPERIOD; rxdata(i):= rxd; end loop;
wait for TXPERIOD ;
d := rxdata;
end;
procedure rxi(signal rxd : in std_logic; d: out std_logic_vector;
txperiod : time; lresp : boolean) is
variable rxdata : std_logic_vector(31 downto 0);
variable resp : std_logic_vector(7 downto 0);
begin
for i in 3 downto 0 loop
rxc(rxd, rxdata((i*8 +7) downto i*8), txperiod);
end loop;
d := rxdata;
if LRESP then
rxc(rxd, resp, txperiod);
-- print("RESP : 0x" & tosth(resp));
end if;
end;
procedure txc(signal txd : out std_logic; td : integer;
txperiod : time) is
variable txdata : std_logic_vector(10 downto 0);
begin
txdata := "11" & conv_std_logic_vector(td, 8) & '0';
for i in 0 to 10 loop wait for TXPERIOD ; txd <= txdata(i); end loop;
end;
procedure txa(signal txd : out std_logic; td1, td2, td3, td4 : integer;
txperiod : time) is
variable txdata : std_logic_vector(43 downto 0);
begin
txdata := "11" & conv_std_logic_vector(td4, 8) & '0'
& "11" & conv_std_logic_vector(td3, 8) & '0'
& "11" & conv_std_logic_vector(td2, 8) & '0'
& "11" & conv_std_logic_vector(td1, 8) & '0';
for i in 0 to 43 loop wait for TXPERIOD ; txd <= txdata(i); end loop;
end;
procedure txi(signal rxd : in std_logic; signal txd : out std_logic;
td1, td2, td3, td4 : integer; txperiod : time;
lresp : boolean) is
variable txdata : std_logic_vector(43 downto 0);
begin
txdata := "11" & conv_std_logic_vector(td4, 8) & '0'
& "11" & conv_std_logic_vector(td3, 8) & '0'
& "11" & conv_std_logic_vector(td2, 8) & '0'
& "11" & conv_std_logic_vector(td1, 8) & '0';
for i in 0 to 43 loop wait for TXPERIOD ; txd <= txdata(i); end loop;
if LRESP then
rxc(rxd, txdata(7 downto 0), txperiod);
-- print("RESP : 0x" & tosth(txdata(7 downto 0)));
end if;
end;
end;
-- pragma translate_on
| gpl-2.0 | 249d2fc39c202e63864c3b49e7db0760 | 0.605947 | 3.315034 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_blk_mem_gen_0_2/synth/design_1_blk_mem_gen_0_2.vhd | 1 | 15,971 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_4_0;
USE blk_mem_gen_v8_4_0.blk_mem_gen_v8_4_0;
ENTITY design_1_blk_mem_gen_0_2 IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_blk_mem_gen_0_2;
ARCHITECTURE design_1_blk_mem_gen_0_2_arch OF design_1_blk_mem_gen_0_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_blk_mem_gen_0_2_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_4_0 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_4_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_blk_mem_gen_0_2_arch: ARCHITECTURE IS "blk_mem_gen_v8_4_0,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_blk_mem_gen_0_2_arch : ARCHITECTURE IS "design_1_blk_mem_gen_0_2,blk_mem_gen_v8_4_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_blk_mem_gen_0_2_arch: ARCHITECTURE IS "design_1_blk_mem_gen_0_2,blk_mem_gen_v8_4_0,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.4,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=1,C_ENABLE_32BIT_ADDRESS=1,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAM" &
"E=no_coe_file_loaded,C_INIT_FILE=NONE,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=32,C_HAS_RSTB=1,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_" &
"WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=32,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C" &
"_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 10.7492 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF rstb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF clkb: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 900, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF clka: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE";
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
BEGIN
U0 : blk_mem_gen_v8_4_0
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 1,
C_ENABLE_32BIT_ADDRESS => 1,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "NONE",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 1,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 4,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 32,
C_HAS_RSTB => 1,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 4,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 32,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "2",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 10.7492 mW"
)
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => rstb,
enb => enb,
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END design_1_blk_mem_gen_0_2_arch;
| mit | da389fd0b386319503173cdb10b202d1 | 0.635903 | 3.022521 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/inferred/lpddr2_phy_inferred.vhd | 1 | 10,205 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: generic_lpddr2phy_wo_pads
-- File: lpddr2_phy_inferred.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Generic LPDDR2/LPDDR3 PHY (simulation only), without pads
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity clkswitch is
port (clk1,clk2,sel: in std_ulogic;
clko: out std_ulogic);
end;
architecture sim of clkswitch is
signal c1en,c2en: std_ulogic := '0';
begin
clko <= (clk1 and c1en) or (clk2 and c2en);
p1: process(clk1)
begin
if falling_edge(clk1) then
c1en <= (not sel) and (not c2en);
end if;
end process;
p2: process(clk2)
begin
if falling_edge(clk2) then
c2en <= (sel) and (not c1en);
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity generic_lpddr2phy_wo_pads is
generic (
tech : integer := 0;
dbits : integer := 16;
nclk: integer := 3;
ncs: integer := 2;
clkratio: integer := 1;
scantest: integer := 0;
oepol: integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2 : in std_ulogic;
clkout : out std_ulogic;
clkoutret : in std_ulogic; -- clkout returned
clkout2 : out std_ulogic;
lock : out std_ulogic;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0);
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ca : in std_logic_vector (10*2*clkratio-1 downto 0);
cke : in std_logic_vector (ncs*clkratio-1 downto 0);
csn : in std_logic_vector (ncs*clkratio-1 downto 0);
dqin : out std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4*clkratio-1 downto 0); -- data mask
ckstop : in std_ulogic;
boot : in std_ulogic;
wrpend : in std_logic_vector(7 downto 0);
rdpend : in std_logic_vector(7 downto 0);
wrreq : out std_logic_vector(clkratio-1 downto 0);
rdvalid : out std_logic_vector(clkratio-1 downto 0);
refcal : in std_ulogic;
refcalwu : in std_ulogic;
refcaldone : out std_ulogic;
phycmd : in std_logic_vector(7 downto 0);
phycmden : in std_ulogic;
phycmdin : in std_logic_vector(31 downto 0);
phycmdout : out std_logic_vector(31 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture beh of generic_lpddr2phy_wo_pads is
component sim_pll
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
signal extclkb,extclkn,extclk,intclkb,intclkn,intclk: std_ulogic;
signal gextclk,gextclkn: std_ulogic;
signal clkoutb,clkoutn: std_ulogic;
signal llockb,llockn,llock: std_ulogic;
signal dqsout,dqsoen,dqsand,dqoen,dqsien,dqsiend: std_ulogic;
signal dqsin,dqsind: std_logic_vector(dbits/8-1 downto 0);
signal tmeas: time := 0 ns;
signal tdqsck: time := 0 ns;
begin
bootpll: sim_pll
generic map (clkmul => clkratio,
clkdiv1 => 1, clkphase1 => 180,
clkdiv2 => 1, clkphase2 => 90,
clkdiv3 => clkratio, clkphase3 => 0)
port map (i => clkin2, o1 => extclkb, o2 => intclkb,
o3 => clkoutb, lock => llockb, rst => rst);
pll0: sim_pll
generic map (clkmul => clkratio,
clkdiv1 => 1, clkphase1 => 180,
clkdiv2 => 1, clkphase2 => 90,
clkdiv3 => clkratio, clkphase3 => 0)
port map (i => clkin, o1 => extclkn, o2 => intclkn,
o3 => clkoutn, lock => llockn, rst => rst);
llock <= llockb and llockn;
lock <= llock;
clkout2 <= '0';
cs0: entity work.clkswitch port map (extclkn, extclkb, boot, extclk);
cs1: entity work.clkswitch port map (intclkn, intclkb, boot, intclk);
cs2: entity work.clkswitch port map (clkoutn, clkoutb, boot, clkout);
gextclk <= extclk and (llock and not ckstop);
gextclkn <= not gextclk;
dqsout <= gextclk and dqsand;
ddr_dqs_out <= (others => dqsout);
ddr_dqs_oen <= (others => dqsoen);
ddr_dqs_oen <= (others => dqsoen or (not rst) or (not llock)) when oepol=0 else
(others => (not dqsoen) and rst and llock);
ddr_dq_oen <= (others => dqoen or (not rst) or (not llock)) when oepol=0 else
(others => (not dqoen) and rst and llock);
ddr_clk <= (others => gextclk);
ddr_clkb <= (others => gextclkn);
dqsiend <= dqsien after tdqsck;
dqsin <= ddr_dqs_in when dqsiend='1' else (others => '0');
dqsind <= dqsin after tmeas * 0.25;
wrreq <= wrpend(1+clkratio-1-1 downto 1-1);
outregs: process(clkoutret,intclk,dqsind)
variable phase: integer;
variable wrpend_samp: std_logic_vector(1 downto 0);
variable rdpend_prev: std_ulogic;
type intarr is array(natural range <>) of integer;
variable dl: intarr(dbits/8-1 downto 0) := (others => 0);
variable dqq: std_logic_vector(3*dbits*2-1 downto 0);
variable lt: time := 0 ns;
variable dqsind_prev: std_logic_vector(dbits/8-1 downto 0) := (others => '0');
variable i: integer;
begin
if dqsind /= dqsind_prev then
for x in dqsind'range loop
if (dqsind(x)='1' and dqsind_prev(x)='0') or (dqsind(x)='0' and dqsind_prev(x)='1') then
for y in 5 downto 1 loop
dqq(x*8+dbits*y+7 downto x*8+dbits*y) := dqq(x*8+dbits*(y-1)+7 downto x*8+dbits*(y-1));
end loop;
dqq(x*8+7 downto x*8) := ddr_dq_in(x*8+7 downto x*8);
if dqsind(x)='0' then
dl(x) := dl(x)+1;
end if;
end if;
end loop;
dqsind_prev := dqsind;
end if;
if rising_edge(clkoutret) then
dqsien <= rdpend(1);
phase := 0;
wrpend_samp := wrpend(1 downto 0);
rdvalid <= (others => '0');
dqin <= (others => '-');
i := clkratio;
for x in dl'range loop
if dl(x)<i then i:=dl(x); end if;
end loop;
for x in dl'range loop
dl(x) := dl(x)-i;
end loop;
for x in 2*i-1 downto 0 loop
for y in dbits/8-1 downto 0 loop
dqin(x*dbits+y*8+7 downto x*dbits+y*8) <= dqq((x+dl(y))*dbits+y*8+7 downto (x+dl(y))*dbits+y*8);
end loop;
end loop;
rdvalid(i-1 downto 0) <= (others => '1');
end if;
if falling_edge(clkoutret) then
dqsoen <= not (wrpend_samp(1) or wrpend_samp(0));
rdpend_prev := rdpend(0);
end if;
if rising_edge(intclk) then
dqsand <= wrpend_samp(0);
dqoen <= not wrpend_samp(0);
tmeas <= now - lt;
lt := now;
end if;
if rising_edge(intclk) or falling_edge(intclk) then
-- DDR outputs
ddr_ca <= ca(ca'high-10*phase downto ca'high-10*phase-9);
ddr_dm <= dm(dm'high-dbits/8*phase downto dm'high+1-dbits/8*(phase+1));
ddr_dq_out <= dqout(dqout'high-dbits*phase downto dqout'high+1-dbits*(phase+1));
if rising_edge(intclk) then
-- SDR outputs
ddr_cke <= cke(cke'high-ncs*(phase/2) downto cke'high+1-ncs*(phase/2+1));
ddr_csb <= csn(csn'high-ncs*(phase/2) downto csn'high+1-ncs*(phase/2+1));
end if;
if phase < 2*clkratio-1 then
phase := phase+1;
end if;
end if;
end process;
dqsckproc: process
variable t: time;
begin
wait until dqsien='1';
loop
t := now;
if dqsin/=(dqsin'range => '0') then
wait until dqsin=(dqsin'range => '0');
end if;
wait until dqsin=(dqsin'range => '1');
tdqsck <= tdqsck + (now-t)-0.25*tmeas;
wait until dqsin=(dqsin'range => 'X') and dqsien='1';
end loop;
end process;
end;
| gpl-2.0 | 38025cdd8b15974a6b060596d8a229b5 | 0.571191 | 3.374669 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-avnet-eval-xc4vlx60/config.vhd | 1 | 6,154 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex4;
constant CFG_MEMTECH : integer := virtex4;
constant CFG_PADTECH : integer := virtex4;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex4;
constant CFG_CLKMUL : integer := (7);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 4;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#010a#;
constant CFG_ETH_ENM : integer := 16#020060#;
constant CFG_ETH_ENL : integer := 16#000015#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 0;
constant CFG_DDRSP_INIT : integer := 0;
constant CFG_DDRSP_FREQ : integer := 100;
constant CFG_DDRSP_COL : integer := 9;
constant CFG_DDRSP_SIZE : integer := 8;
constant CFG_DDRSP_RSKEW : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#FE0#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | ba596e8ce05fd29ce174da61b25e86f7 | 0.643646 | 3.607268 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/c47de30114c88d53/ip_design_rst_ps7_0_100M_0_sim_netlist.vhdl | 1 | 35,666 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:29 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_rst_ps7_0_100M_0_sim_netlist.vhdl
-- Design : ip_design_rst_ps7_0_100M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 : entity is "cdc_sync";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mb_debug_sys_rst,
I1 => ext_reset_in,
O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute box_type : string;
attribute box_type of POR_SRL_I : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => Q,
I1 => lpf_asr,
I2 => dcm_locked,
I3 => lpf_exr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
port (
MB_out : out STD_LOGIC;
Bsr_out : out STD_LOGIC;
Pr_out : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
signal \^bsr_out\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^mb_out\ : STD_LOGIC;
signal \^pr_out\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Bsr_out <= \^bsr_out\;
MB_out <= \^mb_out\;
Pr_out <= \^pr_out\;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr_out\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr_out\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^mb_out\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^mb_out\,
S => lpf_int
);
SEQ_COUNTER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr_out\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr_out\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^mb_out\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr_out\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr_out\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
signal Bsr_out : STD_LOGIC;
signal MB_out : STD_LOGIC;
signal Pr_out : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal lpf_int : STD_LOGIC;
attribute box_type : string;
attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE";
attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE";
attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE";
attribute box_type of FDRE_inst : label is "PRIMITIVE";
attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Bsr_out,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
FDRE_inst: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => MB_out,
Q => mb_reset,
R => '0'
);
\PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Pr_out,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ => SEQ_n_4,
Bsr_out => Bsr_out,
MB_out => MB_out,
Pr_out => Pr_out,
lpf_int => lpf_int,
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_rst_ps7_0_100M_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "proc_sys_reset,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
attribute x_interface_info : string;
attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST";
attribute x_interface_parameter : string;
attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST";
attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW";
attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST";
attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST";
attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK";
attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
| mit | 32ad5c9cac5861a3a026e0b6791019ec | 0.589637 | 2.911748 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/i2c/i2c2ahb.vhd | 1 | 3,031 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb
-- File: i2c2ahb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple I2C-slave providing a bridge to AMBA AHB
-- See i2c2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.conv_std_logic_vector;
library gaisler;
use gaisler.i2c.all;
entity i2c2ahb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2c2ahb;
architecture rtl of i2c2ahb is
signal i2c2ahbi : i2c2ahb_in_type;
begin
bridge : i2c2ahbx
generic map (
hindex => hindex,
oepol => oepol,
filter => filter)
port map (
rstn => rstn,
clk => clk,
ahbi => ahbi,
ahbo => ahbo,
i2ci => i2ci,
i2co => i2co,
i2c2ahbi => i2c2ahbi,
i2c2ahbo => open);
i2c2ahbi.en <= '1';
i2c2ahbi.haddr <= conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
i2c2ahbi.hmask <= conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
i2c2ahbi.slvaddr <= conv_std_logic_vector(i2cslvaddr, 7);
i2c2ahbi.cfgaddr <= conv_std_logic_vector(i2ccfgaddr, 7);
end architecture rtl;
| gpl-2.0 | 95977e797868406a0cbd25bc00cea511 | 0.584955 | 3.582742 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep2s60-sdr/config.vhd | 1 | 5,584 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FFFF#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 5ec8a458c798afc86e92f5a4fd796d48 | 0.645415 | 3.668857 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep2sgx90-av/config.vhd | 1 | 6,966 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4;
constant CFG_ATBSZ : integer := 4;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 1;
constant CFG_AHB_MONERR : integer := 1;
constant CFG_AHB_MONWAR : integer := 1;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#02007A#;
constant CFG_ETH_ENL : integer := 16#CC0001#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (200);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (512);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 64;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FFFF#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 1;
end;
| gpl-2.0 | 4dd61a03828abd4fd93402407be1183e | 0.654895 | 3.603725 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep1c20/leon3mp.vhd | 1 | 21,066 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 25 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
clkout : out std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
-- Shared bus
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
-- SRAM
ramsn : out std_ulogic;
ramoen : out std_ulogic;
rwen : out std_ulogic;
mben : out std_logic_vector(3 downto 0);
iosn : out std_ulogic;
-- FLASH
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
sa : out std_logic_vector(11 downto 0);
sd : inout std_logic_vector(31 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic; -- sdram clock enable
sdcsn : out std_logic; -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
sdba : out std_logic_vector(1 downto 0); -- sdram bank address
-- debug support unit
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- for smsc lan chip
eth_aen : out std_logic;
eth_readn : out std_logic;
eth_writen: out std_logic;
eth_nbe : out std_logic_vector(3 downto 0);
eth_lclk : out std_ulogic;
eth_nads : out std_logic;
eth_ncycle : out std_logic;
eth_wnr : out std_logic;
eth_nvlbus : out std_logic;
eth_nrdyrtn : out std_logic;
eth_ndatacs : out std_logic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2 : sdctrl_out_type;
--for smc lan chip
signal s_eth_aen : std_logic;
signal s_eth_readn : std_logic;
signal s_eth_writen: std_logic;
signal s_eth_nbe : std_logic_vector(3 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, sdclkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN ;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
signal lclk, lclkout : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal dsubre : std_ulogic;
component clkgen_ep1c20board is
generic (
tech : integer := DEFFABTECH;
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
freq : integer := 50000);
port (
clkin : in std_logic;
clkout : out std_logic;
clk : out std_logic;
clkn : out std_logic;
sdclk : out std_logic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component smc_mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type;
eth_aen : out std_ulogic; -- for smsc lan chip
eth_readn : out std_ulogic; -- for smsc lan chip
eth_writen: out std_ulogic; -- for smsc lan chip
eth_nbe : out std_logic_vector(3 downto 0) -- for smsc lan chip
);
end component;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; --cgi.pllref <= lclk; --pllref; -- clk; --'0';
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkout_pad : outpad generic map (tech => padtech, slew => 1) port map (clkout, lclkout);
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clkgen0 : clkgen_ep1c20board
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN, CFG_CLK_NOFB)
port map (lclk, lclkout, clkm, open, sdclkl, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24) port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo2);
apbo(0) <= apb_none;
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo,
s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 12) port map (sa, memo.sa(11 downto 0));
sdba_pad : outpadv generic map (width => 2) port map (sdba, memo.sa(14 downto 13));
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>4, tech => padtech)
port map (sddqm, sdo.dqm(3 downto 0));
end generate;
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, sdo.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, sdo.sdcsn(0));
end generate;
nosd0 : if (CFG_MCTRL_LEON2 = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, sdo2.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, sdo2.sdcsn(0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
mg0 : if not ((CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1)) generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, vcc(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpad generic map (tech => padtech)
port map (rwen, memo.wrn(0));
roen_pad : outpad generic map (tech => padtech)
port map (ramoen, memo.ramoen(0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- for smc lan chip
eth_aen_pad : outpad generic map (tech => padtech)
port map (eth_aen, s_eth_aen);
eth_readn_pad : outpad generic map (tech => padtech)
port map (eth_readn, s_eth_readn);
eth_writen_pad : outpad generic map (tech => padtech)
port map (eth_writen, s_eth_writen);
eth_nbe_pad : outpadv generic map (width => 4, tech => padtech)
port map (eth_nbe, s_eth_nbe);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
----
----
-- invert signal for input via a key
dsubre <= not dsubren;
-- for smc lan chip
eth_lclk <= vcc(0);
eth_nads <= gnd(0);
eth_ncycle <= vcc(0);
eth_wnr <= vcc(0);
eth_nvlbus <= vcc(0);
eth_nrdyrtn <= vcc(0);
eth_ndatacs <= vcc(0);
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP1C20 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | c673f2ea7231f32d1187a4016bbca4bf | 0.538261 | 3.753742 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/leon3v3/leon3x.vhd | 1 | 9,779 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Entity: leon3x
-- File: leon3x.vhd
-- Author: Jiri Gaisler, Jan Andersson, Aeroflex Gaisler
-- Description: Top-level LEON3v3 component with all options
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
use gaisler.arith.all;
entity leon3x is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0;
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
clk2x : integer := 1;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
clken : in std_ulogic
);
end;
architecture rtl of leon3x is
constant IRFBITS : integer range 6 to 10 := log2(NWINDOWS+1) + 4;
constant IREGNUM : integer := NWINDOWS * 16 + 8;
constant IRFWT : integer := 1;--regfile_3p_write_through(memtech);
constant fpuarch : integer := fpu mod 16;
constant fpunet : integer := (fpu mod 32) / 16;
constant fpushared : boolean := (fpu / 32) /= 0;
constant FTSUP : integer := 0
;
-- Create an array length mismatch error if the user tries to enable FT
-- features in non-FT release.
constant dummy_ft_consistency_check:
std_logic_vector(FTSUP*(iuft+fpft+cmft) downto (iuft+fpft+cmft)) := "0";
signal holdn : std_logic;
signal rfi : iregfile_in_type;
signal rfo : iregfile_out_type;
signal crami : cram_in_type;
signal cramo : cram_out_type;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal rst : std_ulogic;
signal fpi : fpc_in_type;
signal fpo : fpc_out_type;
signal cpi : fpc_in_type;
signal cpo : fpc_out_type;
signal gnd, vcc : std_logic;
attribute sync_set_reset : string;
attribute sync_set_reset of rst : signal is "true";
begin
gnd <= '0'; vcc <= '1';
-- leon3 processor core (iu, caches & mul/div)
p0 : proc3
generic map (
hindex, fabtech, memtech, nwindows, dsu, fpuarch, v8, cp, mac, pclow,
notag, nwp, icen, irepl, isets, ilinesize, isetsize, isetlock, dcen,
drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram, ilramsize,
ilramstart, dlram, dlramsize, dlramstart, mmuen, itlbnum, dtlbnum,
tlb_type, tlb_rep, lddel, disas, tbuf, pwd, svt, rstaddr, smp,
cached, clk2x, scantest, mmupgsz, bp)
port map (gclk2, rst, holdn, ahbi, ahbo, ahbsi, ahbso, rfi, rfo, crami, cramo,
tbi, tbo, fpi, fpo, cpi, cpo, irqi, irqo, dbgi, dbgo, clk, clk2, clken);
-- IU register file
rf0 : regfile_3p_l3 generic map (memtech, IRFBITS, 32, IRFWT, IREGNUM,
scantest)
port map (gclk2, rfi.waddr(IRFBITS-1 downto 0), rfi.wdata, rfi.wren,
gclk2, rfi.raddr1(IRFBITS-1 downto 0), rfi.ren1, rfo.data1,
rfi.raddr2(IRFBITS-1 downto 0), rfi.ren2, rfo.data2,
rfi.diag
);
-- cache memory
cmem0 : cachemem
generic map (memtech, icen, irepl, isets, ilinesize, isetsize, isetlock, dcen,
drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram,
ilramsize, dlram, dlramsize, mmuen, scantest
)
port map (gclk2, crami, cramo, clk2);
-- instruction trace buffer memory
tbmem_gen : if (tbuf /= 0) generate
tbmem0 : tbufmem generic map (memtech, tbuf, scantest)
port map (gclk2, tbi, tbo);
end generate;
-- FPU
fpu0 : if (fpu = 0) generate fpo <= fpc_out_none; end generate;
fpshare : if fpushared generate
grfpw0gen : if (fpuarch > 0) and (fpuarch < 8) generate
fpu0: grfpwxsh
generic map (memtech, pclow, dsu, disas, hindex
)
port map (rst, gclk2, holdn, fpi, fpo, fpui, fpuo);
end generate;
nogrfpw0gen : if not ((fpuarch > 0) and (fpuarch < 8)) generate
fpui <= grfpu_in_none;
end generate;
end generate;
nofpshare : if not fpushared generate
grfpw1gen : if (fpuarch > 0) and (fpuarch < 8) generate
fpu0: grfpwx
generic map (fabtech, memtech, (fpuarch-1), pclow, dsu, disas,
fpunet, hindex)
port map (rst, gfclk2, holdn, fpi, fpo);
end generate;
mfpw1gen : if (fpuarch = 15) generate
fpu0 : mfpwx
generic map (memtech, pclow, dsu, disas
)
port map (rst, gfclk2, holdn, fpi, fpo);
end generate;
grlfpc1gen : if (fpuarch >=8) and (fpuarch < 15) generate
fpu0 : grlfpwx
generic map (memtech, pclow, dsu, disas,
(fpuarch-8), fpunet, hindex)
port map (rst, gfclk2, holdn, fpi, fpo);
end generate;
fpui <= grfpu_in_none;
end generate;
-- CP
cpo <= fpc_out_none;
-- 1-clock reset delay
rstreg : process(gclk2)
begin if rising_edge(gclk2) then rst <= rstn; end if; end process;
-- pragma translate_off
bootmsg : report_version
generic map (
"leon3_" & tost(hindex) & ": LEON3 SPARC V8 processor rev " & tost(LEON3_VERSION)
, "leon3_" & tost(hindex) & ": icache " & tost(isets*icen) & "*" & tost(isetsize*icen) &
" kbyte, dcache " & tost(dsets*dcen) & "*" & tost(dsetsize*dcen) & " kbyte"
);
-- pragma translate_on
end;
| gpl-2.0 | 8fd2ec4516a136c627106edc1fdaae48 | 0.548318 | 3.644801 | false | false | false | false |
dsaves/dsaves-hdl | crypto/sha_256/sha_256_core.vhdl | 1 | 13,524 | --MIT License
--
--Copyright (c) 2017 Danny Savory
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
-- ############################################################################
-- The official specifications of the SHA-256 algorithm can be found here:
-- http://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.180-4.pdf
-- ##################################################################
-- This SHA_256_CORE module reads in PADDED message blocks (from
-- an external source) and hashes the resulting message
-- ##################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sha_256_pkg.all;
entity sha_256_core is
generic(
RESET_VALUE : std_logic := '0' --reset enable value
);
port(
clk : in std_logic;
rst : in std_logic;
data_ready : in std_logic; --the edge of this signal triggers the capturing of input data and hashing it.
n_blocks : in natural; --N, the number of (padded) message blocks
msg_block_in : in std_logic_vector(0 to (16 * WORD_SIZE)-1);
--mode_in : in std_logic;
finished : out std_logic;
data_out : out std_logic_vector((WORD_SIZE * 8)-1 downto 0) --SHA-256 results in a 256-bit hash value
);
end entity;
architecture sha_256_core_ARCH of sha_256_core is
signal HASH_ROUND_COUNTER : natural := 0;
signal MSG_BLOCK_COUNTER : natural := 0;
signal HASH_02_COUNTER : natural := 0;
constant HASH_02_COUNT_LIMIT : natural := 64;
--Temporary words
signal T1 : std_logic_vector(WORD_SIZE-1 downto 0) := (others => '0');
signal T2 : std_logic_vector(WORD_SIZE-1 downto 0) := (others => '0');
--Working variables, 8 32-bit words
signal a : std_logic_vector(WORD_SIZE-1 downto 0) := (others => '0');
signal b : std_logic_vector(WORD_SIZE-1 downto 0) := (others => '0');
signal c : std_logic_vector(WORD_SIZE-1 downto 0) := (others => '0');
signal d : std_logic_vector(WORD_SIZE-1 downto 0) := (others => '0');
signal e : std_logic_vector(WORD_SIZE-1 downto 0) := (others => '0');
signal f : std_logic_vector(WORD_SIZE-1 downto 0) := (others => '0');
signal g : std_logic_vector(WORD_SIZE-1 downto 0) := (others => '0');
signal h : std_logic_vector(WORD_SIZE-1 downto 0) := (others => '0');
constant K : K_DATA := (
--address 0
X"428a2f98", X"71374491", X"b5c0fbcf", X"e9b5dba5",
X"3956c25b", X"59f111f1", X"923f82a4", X"ab1c5ed5",
X"d807aa98", X"12835b01", X"243185be", X"550c7dc3",
X"72be5d74", X"80deb1fe", X"9bdc06a7", X"c19bf174",
X"e49b69c1", X"efbe4786", X"0fc19dc6", X"240ca1cc",
X"2de92c6f", X"4a7484aa", X"5cb0a9dc", X"76f988da",
X"983e5152", X"a831c66d", X"b00327c8", X"bf597fc7",
X"c6e00bf3", X"d5a79147", X"06ca6351", X"14292967",
X"27b70a85", X"2e1b2138", X"4d2c6dfc", X"53380d13",
X"650a7354", X"766a0abb", X"81c2c92e", X"92722c85",
X"a2bfe8a1", X"a81a664b", X"c24b8b70", X"c76c51a3",
X"d192e819", X"d6990624", X"f40e3585", X"106aa070",
X"19a4c116", X"1e376c08", X"2748774c", X"34b0bcb5",
X"391c0cb3", X"4ed8aa4a", X"5b9cca4f", X"682e6ff3",
X"748f82ee", X"78a5636f", X"84c87814", X"8cc70208",
X"90befffa", X"a4506ceb", X"bef9a3f7", X"c67178f2"
);
--Message schedule, W(00), W(01), ...W(63) (64 32-bit words)
signal W : K_DATA := (
--address 0
X"00000000", X"00000000", X"00000000", X"00000000",
X"00000000", X"00000000", X"00000000", X"00000000",
X"00000000", X"00000000", X"00000000", X"00000000",
X"00000000", X"00000000", X"00000000", X"00000000",
X"00000000", X"00000000", X"00000000", X"00000000",
X"00000000", X"00000000", X"00000000", X"00000000",
X"00000000", X"00000000", X"00000000", X"00000000",
X"00000000", X"00000000", X"00000000", X"00000000",
X"00000000", X"00000000", X"00000000", X"00000000",
X"00000000", X"00000000", X"00000000", X"00000000",
X"00000000", X"00000000", X"00000000", X"00000000",
X"00000000", X"00000000", X"00000000", X"00000000",
X"00000000", X"00000000", X"00000000", X"00000000",
X"00000000", X"00000000", X"00000000", X"00000000",
X"00000000", X"00000000", X"00000000", X"00000000",
X"00000000", X"00000000", X"00000000", X"00000000"
);
--Message blocks, the padded message should be a multiple of 512 bits,
signal M : M_DATA;
--Hash values w/ initial hash values; 8 32-bit words
signal HV : H_DATA;
signal HV_INITIAL_VALUES : H_DATA := (X"6a09e667", X"bb67ae85", X"3c6ef372",
X"a54ff53a", X"510e527f", X"9b05688c",
X"1f83d9ab", X"5be0cd19");
--intermediate Message block values; for use with a for-generate loop;
signal M_INT : M_DATA;
--intermediate Message Schedule values; for use with a for-generate loop;
signal W_INT : K_DATA;
type SHA_256_HASH_CORE_STATE is ( RESET, IDLE, READ_MSG_BLOCK, PREP_MSG_SCHEDULE_00, PREP_MSG_SCHEDULE_01, PREP_MSG_SCHEDULE_02, PREP_MSG_SCHEDULE_03, HASH_01, HASH_02, HASH_02b, HASH_02c, HASH_03, DONE );
signal CURRENT_STATE, NEXT_STATE : SHA_256_HASH_CORE_STATE;
signal PREVIOUS_STATE : SHA_256_HASH_CORE_STATE := READ_MSG_BLOCK;
begin
--current state logic
process(clk, rst)
begin
if(rst=RESET_VALUE) then
CURRENT_STATE <= RESET;
elsif(clk'event and clk='1') then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
--next state logic
process(CURRENT_STATE, rst, n_blocks, HASH_ROUND_COUNTER, HASH_02_COUNTER, data_ready)
begin
case CURRENT_STATE is
when RESET =>
if(rst=RESET_VALUE) then
NEXT_STATE <= RESET;
else
NEXT_STATE <= IDLE;
end if;
when IDLE =>
if(data_ready='1') then
NEXT_STATE <= READ_MSG_BLOCK;
else
NEXT_STATE <= IDLE;
end if;
when READ_MSG_BLOCK =>
NEXT_STATE <= PREP_MSG_SCHEDULE_00;
when PREP_MSG_SCHEDULE_00 =>
NEXT_STATE <= PREP_MSG_SCHEDULE_01;
when PREP_MSG_SCHEDULE_01 =>
NEXT_STATE <= PREP_MSG_SCHEDULE_02;
when PREP_MSG_SCHEDULE_02 =>
NEXT_STATE <= PREP_MSG_SCHEDULE_03;
when PREP_MSG_SCHEDULE_03 =>
NEXT_STATE <= HASH_01;
when HASH_01 =>
NEXT_STATE <= HASH_02;
when HASH_02 =>
if(HASH_02_COUNTER = HASH_02_COUNT_LIMIT) then
NEXT_STATE <= HASH_03;
else
NEXT_STATE <= HASH_02b;
end if;
when HASH_02b =>
NEXT_STATE <= HASH_02c;
when HASH_02c =>
NEXT_STATE <= HASH_02;
when HASH_03 =>
if(HASH_ROUND_COUNTER = n_blocks-1) then
NEXT_STATE <= DONE;
else
NEXT_STATE <= IDLE;
end if;
when DONE =>
NEXT_STATE <= DONE; --stay in done state unless reset
end case;
end process;
--hash logic
process(clk, rst, CURRENT_STATE)
begin
if(rst=RESET_VALUE) then
HASH_ROUND_COUNTER <= 0;
MSG_BLOCK_COUNTER <= 0;
elsif(clk'event and clk='1') then
a <= a; b <= b; c <= c; d <= d;
e <= e; f <= f; g <= g; h <= h;
T1 <= T1; T2 <= T2;
W <= W; M <= M; HV <= HV;
HASH_02_COUNTER <= HASH_02_COUNTER;
HASH_ROUND_COUNTER <= HASH_ROUND_COUNTER;
case CURRENT_STATE is
when RESET =>
HV <= HV_INITIAL_VALUES;
HASH_02_COUNTER <= 0;
HASH_ROUND_COUNTER <= 0;
when IDLE => --the IDLE stage is a stall stage, perhaps waiting for new message block to arrive.
when READ_MSG_BLOCK =>
if(HASH_ROUND_COUNTER = 0) then
HV <= HV_INITIAL_VALUES;
end if;
M <= M_INT;
when PREP_MSG_SCHEDULE_00 =>
W(0 to 15) <= W_INT(0 to 15);
when PREP_MSG_SCHEDULE_01 =>
W(16 to 31) <= W_INT(16 to 31);
when PREP_MSG_SCHEDULE_02 =>
W(32 to 47) <= W_INT(32 to 47);
when PREP_MSG_SCHEDULE_03 =>
W(48 to 63) <= W_INT(48 to 63);
when HASH_01 =>
a <= HV(0);
b <= HV(1);
c <= HV(2);
d <= HV(3);
e <= HV(4);
f <= HV(5);
g <= HV(6);
h <= HV(7);
when HASH_02 =>
if(HASH_02_COUNTER = HASH_02_COUNT_LIMIT) then
HASH_02_COUNTER <= 0;
else
--you have to set T1 and T2 in a different state, due to how
--VHDL sequential/process statements are evaluated.
T1 <= std_logic_vector(unsigned(h) + unsigned(SIGMA_UCASE_1(e)) + unsigned(CH(e, f, g)) + unsigned(K(HASH_02_COUNTER)) + unsigned(W(HASH_02_COUNTER)));
T2 <= std_logic_vector(unsigned(SIGMA_UCASE_0(a)) + unsigned(MAJ(a, b, c)));
end if;
when HASH_02b =>
h <= g;
g <= f;
f <= e;
e <= std_logic_vector(unsigned(d) + unsigned(T1));
d <= c;
c <= b;
b <= a;
a <= std_logic_vector(unsigned(T1) + unsigned(T2));
when HASH_02c =>
HASH_02_COUNTER <= HASH_02_COUNTER + 1; --increment counter
when HASH_03 =>
HV(0) <= std_logic_vector(unsigned(a) + unsigned(HV(0)));
HV(1) <= std_logic_vector(unsigned(b) + unsigned(HV(1)));
HV(2) <= std_logic_vector(unsigned(c) + unsigned(HV(2)));
HV(3) <= std_logic_vector(unsigned(d) + unsigned(HV(3)));
HV(4) <= std_logic_vector(unsigned(e) + unsigned(HV(4)));
HV(5) <= std_logic_vector(unsigned(f) + unsigned(HV(5)));
HV(6) <= std_logic_vector(unsigned(g) + unsigned(HV(6)));
HV(7) <= std_logic_vector(unsigned(h) + unsigned(HV(7)));
if(HASH_ROUND_COUNTER = n_blocks-1) then
HASH_ROUND_COUNTER <= 0;
else
HASH_ROUND_COUNTER <= HASH_ROUND_COUNTER + 1; --increment counter, read in next message block
end if;
when DONE =>
end case;
end if;
end process;
MESSAGE_BLOCK_INTERMEDIATE :
for i in 0 to 15 generate
begin
--M_INT(i) <= msg_block_in((WORD_SIZE * (i+1))-1 downto WORD_SIZE * i);
M_INT(i) <= msg_block_in((WORD_SIZE * i) to WORD_SIZE * (i+1)-1);
end generate;
MESSAGE_SCHEDULE_INTERMEDIATE_00:
for i in 0 to 15 generate
begin
W_INT(i) <= M(i);
end generate;
MESSAGE_SCHEDULE_INTERMEDIATE_01:
for i in 16 to 63 generate
begin
W_INT(i) <= std_logic_vector(unsigned(SIGMA_LCASE_1(W_INT(i-2))) + unsigned(W_INT(i-7)) + unsigned(SIGMA_LCASE_0(W_INT(i-15))) + unsigned(W_INT(i-16)));
end generate;
--FINISHED signal asserts when hashing is done
finished <= '1' when CURRENT_STATE = DONE else
'0';
data_out <= HV(0) & HV(1) & HV(2) & HV(3) & HV(4) & HV(5) & HV(6) & HV(7);
end architecture;
| mit | 04facecc6779a6e6f82802682addf51e | 0.50976 | 3.590125 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/ddr/ddrspa.vhd | 1 | 5,345 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrspm
-- File: ddrspm.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 16-, 32- or 64-bit DDR266 memory controller module.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.ddrpkg.all;
library techmap;
use techmap.gencomp.all;
entity ddrspa is
generic (
fabtech : integer := virtex2;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
regoutput : integer := 0;
nosync : integer := 0;
ddr400 : integer := 1;
scantest: integer := 0;
phyiconf : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (ddrbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits-1 downto 0) -- ddr data
);
end;
architecture rtl of ddrspa is
constant DDR_FREQ : integer := (clkmul * MHz) / clkdiv;
signal sdi : ddrctrl_in_type;
signal sdo : ddrctrl_out_type;
signal clkread : std_ulogic;
signal ilock: std_ulogic;
signal ddr_rst: std_logic;
signal ddr_rst_gen: std_logic_vector(3 downto 0);
constant ddr_syncrst: integer := 0;
begin
lock <= ilock;
ddr_rst <= (ddr_rst_gen(3) and ddr_rst_gen(2) and ddr_rst_gen(1) and rst_ahb); -- Reset signal in DDR clock domain
ddrrstproc: process(clkddri, ilock)
begin
if rising_edge(clkddri) then
ddr_rst_gen <= ddr_rst_gen(2 downto 0) & '1';
if ddr_syncrst /= 0 and rst_ahb='0' then
ddr_rst_gen <= "0000";
end if;
end if;
if ddr_syncrst=0 and ilock='0' then
ddr_rst_gen <= "0000";
end if;
end process;
ddr_phy0 : ddrphy_wrap_cbd generic map (tech => fabtech, MHz => MHz,
dbits => ddrbits, rstdelay => 0, clk_mul => clkmul,
clk_div => clkdiv, rskew => rskew, mobile => mobile,
scantest => scantest, phyiconf => phyiconf)
port map (
rst_ddr, clk_ddr, clkddro, clkddri, clkread, ilock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq, sdi, sdo,
ahbsi.testen, ahbsi.testrst, ahbsi.scanen, ahbsi.testoen);
ddrc : ddr1spax generic map (ddrbits => ddrbits, memtech => memtech, phytech => fabtech,
hindex => hindex, haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
pwron => pwron, MHz => DDR_FREQ, col => col, Mbyte => Mbyte,
mobile => mobile, confapi => confapi, conf0 => conf0,
conf1 => conf1, regoutput => regoutput, nosync => nosync, ddr400 => ddr400, ahbbits => 32,
rstdel => rstdel, scantest => scantest)
port map (ddr_rst, rst_ahb, clkddri, clk_ahb, ahbsi, ahbso, sdi, sdo);
end;
| gpl-2.0 | 8a3e9409b9fa4a7b1604bf916b01e4ac | 0.591955 | 3.493464 | false | true | false | false |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/Stack/src/TestBench/dpath_TB.vhd | 1 | 3,076 | library stack;
use stack.OneHotStack.all;
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-- Add your library and packages declaration here ...
entity dpath_tb is
end dpath_tb;
architecture TB_ARCHITECTURE of dpath_tb is
-- Component declaration of the tested unit
component dpath
port(
EN : in STD_LOGIC;
CLK : in STD_LOGIC;
OT : in operation;
OP : in operand;
RES : out operand;
ZF : out STD_LOGIC;
Stop : out STD_LOGIC );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal EN : STD_LOGIC;
signal CLK : STD_LOGIC;
signal OT : operation;
signal OP : operand;
-- Observed signals - signals mapped to the output ports of tested entity
signal RES : operand;
signal ZF : STD_LOGIC;
signal Stop : STD_LOGIC;
constant CLK_Period: time := 10 ns;
constant Stop_WAIT: time := 5 * CLK_Period;
begin
-- Unit Under Test port map
UUT : dpath
port map (
EN => EN,
CLK => CLK,
OT => OT,
OP => OP,
RES => RES,
ZF => ZF,
Stop => Stop
);
CLK_Process: process
begin
CLK <= '0';
wait for CLK_Period/2;
CLK <= '1';
wait for CLK_Period/2;
end process;
MAIN: process
begin
wait for clk_period;
en <= '0';
op <= "0000000000000010";
ot <= PUSH;
wait for clk_period;
en <= '1';
wait for clk_period;
en <= '0';
wait for Stop_WAIT;
en <= '1';
wait for clk_period;
en <= '0';
wait for Stop_WAIT;
ot <= ADD;
wait for clk_period;
en <= '1';
wait for clk_period;
en <= '0';
wait for Stop_WAIT;
ot <= POP;
wait for clk_period;
en <= '1';
wait for clk_period;
en <= '0';
wait for Stop_WAIT;
ot <= PUSH;
wait for clk_period;
en <= '1';
wait for clk_period;
en <= '0';
wait for Stop_WAIT;
en <= '1';
wait for clk_period;
en <= '0';
wait for Stop_WAIT;
ot <= SUBT;
wait for clk_period;
en <= '1';
wait for clk_period;
en <= '0';
wait for Stop_WAIT;
ot <= POP;
wait for clk_period;
en <= '1';
wait for clk_period;
en <= '0';
wait for Stop_WAIT;
ot <= PUSH;
wait for clk_period;
en <= '1';
wait for clk_period;
en <= '0';
wait for Stop_WAIT;
ot <= SHIFT;
wait for clk_period;
en <= '1';
wait for clk_period;
en <= '0';
wait for Stop_WAIT;
ot <= POP;
wait for clk_period;
en <= '1';
wait for clk_period;
en <= '0';
wait for Stop_WAIT;
wait;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_dpath of dpath_tb is
for TB_ARCHITECTURE
for UUT : dpath
use entity work.dpath(beh_stack);
end for;
end for;
end TESTBENCH_FOR_dpath;
| mit | 1a3ec1bbdf74f08ddfedd16e82b8fe87 | 0.529584 | 3.38022 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/misc/grgpreg.vhd | 1 | 4,665 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grgpreg
-- File: grgpreg.vhd
-- Author: Kristoffer Glembo - Aeroflex Gaisler
-- Description: General purpose register
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity grgpreg is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
nbits : integer range 1 to 64 := 16;
rstval : integer := 0;
rstval2 : integer := 0;
extrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gprego : out std_logic_vector(nbits-1 downto 0);
resval : in std_logic_vector(nbits-1 downto 0) := (others => '0')
);
end;
architecture rtl of grgpreg is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_GPREG, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type registers is record
reg : std_logic_vector(nbits-1 downto 0);
end record;
signal r, rin : registers;
begin
comb : process(rst, r, apbi, resval)
variable readdata : std_logic_vector(31 downto 0);
variable v : registers;
begin
v := r;
-- read register
readdata := (others => '0');
case apbi.paddr(4 downto 2) is
when "000" =>
if nbits > 32 then
readdata := r.reg(31 downto 0);
else
readdata(nbits-1 downto 0) := r.reg;
end if;
when "001" =>
if nbits > 32 then
readdata(nbits-33 downto 0) := r.reg(nbits-1 downto 32);
end if;
when others =>
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
if nbits > 32 then
v.reg(31 downto 0) := apbi.pwdata;
else
v.reg := apbi.pwdata(nbits-1 downto 0);
end if;
when "001" =>
if nbits > 32 then
v.reg(nbits-1 downto 32) := apbi.pwdata(nbits-33 downto 0);
end if;
when others =>
end case;
end if;
if rst = '0' then
if extrst = 0 then
v.reg := conv_std_logic_vector(rstval, nbits);
if nbits > 32 then
v.reg(nbits-1 downto 32) := conv_std_logic_vector(rstval2, nbits-32);
end if;
else
v.reg := resval;
end if;
end if;
rin <= v;
apbo.prdata <= readdata; -- drive apb read bus
end process;
gprego <= r.reg;
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- registers
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("grgpreg" & tost(pindex) &
": " & tost(nbits) & "-bit GPREG Unit rev " & tost(REVISION));
-- pragma translate_on
end;
| gpl-2.0 | 569f15056deb234feae7a57c78cbb90b | 0.524973 | 4.060052 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/Zynq_Book/hls/tut3C/matrix_mult_prj/solution1/syn/vhdl/matrix_mult_mac_mbkb.vhd | 3 | 3,020 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity matrix_mult_mac_mbkb_DSP48_0 is
port (
clk: in std_logic;
rst: in std_logic;
ce: in std_logic;
in0: in std_logic_vector(8 - 1 downto 0);
in1: in std_logic_vector(8 - 1 downto 0);
in2: in std_logic_vector(16 - 1 downto 0);
dout: out std_logic_vector(16 - 1 downto 0));
attribute use_dsp48 : string;
attribute use_dsp48 of matrix_mult_mac_mbkb_DSP48_0 : entity is "yes";
end entity;
architecture behav of matrix_mult_mac_mbkb_DSP48_0 is
signal a : signed(25-1 downto 0);
signal b : signed(18-1 downto 0);
signal c : signed(48-1 downto 0);
signal m : signed(43-1 downto 0);
signal p : signed(48-1 downto 0);
signal m_reg : signed(43-1 downto 0);
signal a_reg : signed(25-1 downto 0);
signal b_reg : signed(18-1 downto 0);
begin
a <= signed(resize(signed(in0), 25));
b <= signed(resize(signed(in1), 18));
c <= signed(resize(unsigned(in2), 48));
m <= a_reg * b_reg;
p <= m_reg + c;
process (clk) begin
if (clk'event and clk = '1') then
if (ce = '1') then
m_reg <= m;
a_reg <= a;
b_reg <= b;
end if;
end if;
end process;
dout <= std_logic_vector(resize(unsigned(p), 16));
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity matrix_mult_mac_mbkb is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
din2 : IN STD_LOGIC_VECTOR(din2_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of matrix_mult_mac_mbkb is
component matrix_mult_mac_mbkb_DSP48_0 is
port (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
ce : IN STD_LOGIC;
in0 : IN STD_LOGIC_VECTOR;
in1 : IN STD_LOGIC_VECTOR;
in2 : IN STD_LOGIC_VECTOR;
dout : OUT STD_LOGIC_VECTOR);
end component;
begin
matrix_mult_mac_mbkb_DSP48_0_U : component matrix_mult_mac_mbkb_DSP48_0
port map (
clk => clk,
rst => reset,
ce => ce,
in0 => din0,
in1 => din1,
in2 => din2,
dout => dout);
end architecture;
| mit | e45d21e45937de478ecc10db4cbbc5cd | 0.527152 | 3.28976 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/stratixiii/serdes_stratixiii.vhd | 1 | 9,311 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: serdes_stratixiii
-- File: serdes_stratixiii.vhd
-- Author: Andrea Gianarro - Aeroflex Gaisler AB
-- Description: Stratix III and IV SGMII Gigabit Ethernet Serdes
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity serdes_stratixiii is
port (
clk_125 : in std_logic;
rst_125 : in std_logic;
rx_in : in std_logic; -- SER IN
rx_out : out std_logic_vector(9 downto 0); -- PAR OUT
rx_clk : out std_logic;
rx_rstn : out std_logic;
rx_pll_clk : out std_logic;
rx_pll_rstn : out std_logic;
tx_pll_clk : out std_logic;
tx_pll_rstn : out std_logic;
tx_in : in std_logic_vector(9 downto 0) ; -- PAR IN
tx_out : out std_logic; -- SER OUT
bitslip : in std_logic
);
end entity;
architecture rtl of serdes_stratixiii is
component altera_tse_lvds_reset_sequencer is
port (
clk : in std_logic;
reset : in std_logic;
rx_locked : in std_logic;
rx_channel_data_align : out std_logic;
pll_areset : out std_logic; -- can be ignored
rx_reset : out std_logic;
rx_cda_reset : out std_logic;
rx_reset_sequence_done : out std_logic
);
end component;
signal rx_clk_int, rx_pll_clk_int, tx_pll_clk_int, rst_int, pll_areset_int, rx_locked_int, rx_rstn_int_0, tx_locked_int : std_logic;
signal rx_cda_reset_int, bitslip_int, rx_in_int, rx_rst_int, rx_divfwdclk_int, tx_out_int : std_logic_vector(0 downto 0) ;
signal rx_clk_rstn_int, rx_pll_rstn_int, tx_pll_rstn_int, rx_cda_reset_int_0 : std_logic;
signal rx_out_int, tx_in_int : std_logic_vector(9 downto 0) ;
signal r0, r1, r2 : std_logic_vector(4 downto 0);
signal r3 : std_logic_vector(5 downto 0);
signal r4 : std_logic_vector(1 downto 0);
begin
bitslip_int(0) <= bitslip;
rx_in_int(0) <= rx_in;
tx_in_int <= tx_in;
rx_out <= rx_out_int;
tx_out <= tx_out_int(0);
-- output clocks
rx_clk <= rx_clk_int;
rx_pll_clk <= rx_pll_clk_int;
tx_pll_clk <= tx_pll_clk_int;
-- output synchronized resets
rx_rstn <= rx_clk_rstn_int;
rx_pll_rstn <= rx_pll_rstn_int;
tx_pll_rstn <= tx_pll_rstn_int;
--rx_cda_reset_int(0) <= rx_cda_reset_int_0;
rx_rst_int(0) <= not rx_rstn_int_0;
rx_clk_int <= rx_divfwdclk_int(0);
-- reset synchronizers
rst0 : process (rx_clk_int, rst_125) begin
if rising_edge(rx_clk_int) then
r0 <= r0(3 downto 0) & rx_locked_int;
rx_clk_rstn_int <= r0(4) and r0(3) and r0(2);
end if;
if (rst_125 = '1') then r0 <= "00000"; rx_clk_rstn_int <= '0'; end if;
end process;
rst1 : process (rx_pll_clk_int, rx_clk_rstn_int) begin
if rising_edge(rx_pll_clk_int) then
r1 <= r1(3 downto 0) & rx_locked_int;
rx_pll_rstn_int <= r1(4) and r1(3) and r1(2);
end if;
if (rx_clk_rstn_int = '0') then r1 <= "00000"; rx_pll_rstn_int <= '0'; end if;
end process;
rst2 : process (tx_pll_clk_int, rx_clk_rstn_int) begin
if rising_edge(tx_pll_clk_int) then
r2 <= r2(3 downto 0) & tx_locked_int;
tx_pll_rstn_int <= r2(4) and r2(3) and r2(2);
end if;
if (rx_clk_rstn_int = '0') then r2 <= "00000"; tx_pll_rstn_int <= '0'; end if;
end process;
-- 6 stages reset synchronizer
rst3 : process (clk_125, rst_125) begin
if rising_edge(clk_125) then
r3 <= r3(4 downto 0) & rx_locked_int;
rx_rstn_int_0 <= r3(5) and r3(4) and r3(3);
end if;
if (rst_125 = '1') then r3 <= "000000"; rx_rstn_int_0 <= '0'; end if;
end process;
lvds_rx0: altlvds_rx
generic map (
buffer_implementation => "RAM",
cds_mode => "UNUSED",
--clk_src_is_pll => "off",
common_rx_tx_pll => "ON",
data_align_rollover => 10,
--data_rate => "1250.0 Mbps",
deserialization_factor => 10,
dpa_initial_phase_value => 0,
dpll_lock_count => 0,
dpll_lock_window => 0,
--enable_clock_pin_mode => "UNUSED",
enable_dpa_align_to_rising_edge_only => "OFF",
enable_dpa_calibration => "ON",
enable_dpa_fifo => "UNUSED",
enable_dpa_initial_phase_selection => "OFF",
enable_dpa_mode => "ON",
enable_dpa_pll_calibration => "OFF",
enable_soft_cdr_mode => "ON",
implement_in_les => "OFF",
inclock_boost => 0,
inclock_data_alignment => "EDGE_ALIGNED",
inclock_period => 8000,
inclock_phase_shift => 0,
input_data_rate => 1250,
intended_device_family => "Stratix IV",
lose_lock_on_one_change => "UNUSED",
lpm_hint => "UNUSED",
lpm_type => "altlvds_rx",
number_of_channels => 1,
outclock_resource => "AUTO",
pll_operation_mode => "UNUSED",
pll_self_reset_on_loss_lock => "UNUSED",
port_rx_channel_data_align => "PORT_USED",
port_rx_data_align => "PORT_UNUSED",
--refclk_frequency => "125.000000 MHz",
registered_data_align_input => "UNUSED",
registered_output => "ON",
reset_fifo_at_first_lock => "UNUSED",
rx_align_data_reg => "UNUSED",
sim_dpa_is_negative_ppm_drift => "OFF",
sim_dpa_net_ppm_variation => 0,
sim_dpa_output_clock_phase_shift => 0,
use_coreclock_input => "OFF",
use_dpll_rawperror => "OFF",
use_external_pll => "OFF",
use_no_phase_shift => "ON",
x_on_bitslip => "ON"
)
port map (
pll_areset => rst_125, --pll_areset_int,
rx_channel_data_align => bitslip_int,
rx_in => rx_in_int,
rx_inclock => clk_125,
rx_reset => rx_rst_int,
rx_divfwdclk => rx_divfwdclk_int,
rx_locked => rx_locked_int,
rx_out => rx_out_int,
rx_outclock => rx_pll_clk_int,
dpa_pll_cal_busy => open,
dpa_pll_recal => '0',
pll_phasecounterselect => open,
pll_phasedone => '1',
pll_phasestep => open,
pll_phaseupdown => open,
pll_scanclk => open,
rx_cda_max => open,
rx_cda_reset => (others => '0'),
rx_coreclk => (others => '1'),
rx_data_align => '0',
rx_data_align_reset => '0',
--rx_data_reset => '0',
rx_deskew => '0',
rx_dpa_lock_reset => (others => '0'),
rx_dpa_locked => open,
--rx_dpaclock => '0',
rx_dpll_enable => (others => '1'),
rx_dpll_hold => (others => '0'),
rx_dpll_reset => (others => '0'),
rx_enable => '1',
rx_fifo_reset => (others => '0'),
rx_pll_enable => '1',
rx_readclock => '0',
rx_syncclock => '0'
);
lvds_tx0: altlvds_tx
generic map (
center_align_msb => "UNUSED",
--clk_src_is_pll => "off",
common_rx_tx_pll => "ON",
coreclock_divide_by => 1,
--data_rate => "1250.0 Mbps",
deserialization_factor => 10,
differential_drive => 0,
implement_in_les => "OFF",
inclock_boost => 0,
inclock_data_alignment => "EDGE_ALIGNED",
inclock_period => 8000,
inclock_phase_shift => 0,
intended_device_family => "Stratix IV",
lpm_hint => "UNUSED",
lpm_type => "altlvds_tx",
multi_clock => "OFF",
number_of_channels => 1,
outclock_alignment => "EDGE_ALIGNED",
outclock_divide_by => 10,
outclock_duty_cycle => 50,
outclock_multiply_by => 1,
outclock_phase_shift => 0,
outclock_resource => "AUTO",
output_data_rate => 1250,
pll_self_reset_on_loss_lock => "OFF",
preemphasis_setting => 0,
--refclk_frequency => "125.00 MHz",
registered_input => "TX_CORECLK",
use_external_pll => "OFF",
use_no_phase_shift => "ON",
vod_setting => 0
)
port map (
pll_areset => rst_125, --pll_areset_int,
tx_in => tx_in_int,
tx_inclock => clk_125,
tx_out => tx_out_int,
tx_locked => tx_locked_int,
tx_coreclock => tx_pll_clk_int,
sync_inclock => '0',
--tx_data_reset => '0',
tx_enable => '1',
tx_outclock => open,
tx_pll_enable => '1',
tx_syncclock => '0'
);
end architecture ; | gpl-2.0 | 06cbaea658ab378dbb1447c29e71fa4a | 0.563312 | 2.774434 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-6/src/TB/RAM_Ham_T.vhd | 1 | 1,375 | library ieee;
use ieee.std_logic_1164.all;
entity RAM_HAM_T is
end RAM_HAM_T;
architecture Beh of RAM_HAM_T is
component RAM_Ham is
generic(
-- øèíà àäðåñà
m: integer := 2;
-- øèíà äàííûõ
n: integer := 4
);
port (
-- ñèíõðîíèçàöèÿ
CLK: in std_logic;
-- ñèãíàë óïðàâëåíèÿ ÷òåíèåì/çàïèñüþ
WR: in std_logic;
-- øèíà àäðåñà
AB: in std_logic_vector (m-1 downto 0);
-- äâóíàïðàâëåííàÿ øèíà äàííûõ
DB: inout std_logic_vector (n-1 downto 0);
ER: out std_logic
);
end component;
signal CLK: std_logic := '0';
signal WR: std_logic := '0';
signal AB: std_logic_vector (1 downto 0);
signal DB: std_logic_vector (3 downto 0);
signal ER: std_logic := '0';
constant CLK_period: time := 10 ns;
begin
URAM: RAM_Ham port map(
CLK => CLK,
WR => WR,
AB => AB,
DB => DB,
ER => ER
);
CLK_Process: process
begin
CLK <= '0';
wait for CLK_Period/2;
CLK <= '1';
wait for CLK_Period/2;
end process;
main: process
begin
wait for CLK_Period;
AB <= "01";
DB <= "1000";
wait for CLK_Period;
AB <= "10";
DB <= "0100";
wait for CLK_Period;
WR <= '1';
DB <= "ZZZZ";
AB <= "01";
wait for CLK_Period;
DB <= "ZZZZ";
AB <= "10";
wait for CLK_Period;
wait;
end process;
end Beh;
configuration config of RAM_Ham_T is
for Beh
for uram : RAM_Ham
use entity work.RAM_Ham(Beh);
end for;
end for;
end config; | mit | c73cea1a95863637f17ccb9d310b039b | 0.610909 | 2.490942 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/misc/grgpio.vhd | 1 | 11,578 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grgpio
-- File: grgpio.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Scalable general-purpose I/O port
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity grgpio is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
imask : integer := 16#0000#;
nbits : integer := 16; -- GPIO bits
oepol : integer := 0; -- Output enable polarity
syncrst : integer := 0; -- Only synchronous reset
bypass : integer := 16#0000#;
scantest : integer := 0;
bpdir : integer := 16#0000#;
pirq : integer := 0;
irqgen : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpioi : in gpio_in_type;
gpioo : out gpio_out_type
);
end;
architecture rtl of grgpio is
constant REVISION : integer := 2;
constant PIMASK : std_logic_vector(31 downto 0) := '0' & conv_std_logic_vector(imask, 31);
constant BPMASK : std_logic_vector(31 downto 0) := conv_std_logic_vector(bypass, 32);
constant BPDIRM : std_logic_vector(31 downto 0) := conv_std_logic_vector(bpdir, 32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GPIO, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
-- Prevent tools from issuing index errors for unused code
function calc_nirqmux return integer is
begin
if irqgen = 0 then return 1; end if;
return irqgen;
end;
constant NIRQMUX : integer := calc_nirqmux;
subtype irqmap_type is std_logic_vector(log2x(NIRQMUX)-1 downto 0);
type irqmap_array_type is array (natural range <>) of irqmap_type;
type registers is record
din1 : std_logic_vector(nbits-1 downto 0);
din2 : std_logic_vector(nbits-1 downto 0);
dout : std_logic_vector(nbits-1 downto 0);
imask : std_logic_vector(nbits-1 downto 0);
level : std_logic_vector(nbits-1 downto 0);
edge : std_logic_vector(nbits-1 downto 0);
ilat : std_logic_vector(nbits-1 downto 0);
dir : std_logic_vector(nbits-1 downto 0);
bypass : std_logic_vector(nbits-1 downto 0);
irqmap : irqmap_array_type(nbits-1 downto 0);
end record;
constant nbitszero : std_logic_vector(nbits-1 downto 0) := (others => '0');
constant irqmapzero : irqmap_array_type(nbits-1 downto 0) := (others => (others => '0'));
function dirzero_func return std_logic_vector is
variable vres : std_logic_vector(nbits-1 downto 0);
begin
vres := (others => '0');
if oepol = 0 then vres := (others => '1'); end if;
return vres;
end function dirzero_func;
constant dirzero : std_logic_vector(nbits-1 downto 0) := dirzero_func;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : registers := (
din1 => nbitszero, din2 => nbitszero, -- Sync. regs, not reset
dout => nbitszero,imask => nbitszero, level => nbitszero, edge => nbitszero,
ilat => nbitszero, dir => dirzero, bypass => nbitszero, irqmap => irqmapzero);
signal r, rin : registers;
signal arst : std_ulogic;
begin
arst <= apbi.testrst when (scantest = 1) and (apbi.testen = '1') else rst;
comb : process(rst, r, apbi, gpioi)
variable readdata, tmp2, dout, dir, pval, din : std_logic_vector(31 downto 0);
variable v : registers;
variable xirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
din := (others => '0');
din(nbits-1 downto 0) := gpioi.din(nbits-1 downto 0);
v := r; v.din2 := r.din1; v.din1 := din(nbits-1 downto 0);
v.ilat := r.din2; dout := (others => '0'); dir := (others => '0');
dir(nbits-1 downto 0) := r.dir(nbits-1 downto 0);
if (syncrst = 1) and (rst = '0') then
if oepol = 0 then dir(nbits-1 downto 0) := (others => '1');
else dir(nbits-1 downto 0) := (others => '0'); end if;
end if;
dout(nbits-1 downto 0) := r.dout(nbits-1 downto 0);
-- read registers
readdata := (others => '0');
case apbi.paddr(5 downto 2) is
when "0000" => readdata(nbits-1 downto 0) := r.din2;
when "0001" => readdata(nbits-1 downto 0) := r.dout;
when "0010" =>
if oepol = 0 then readdata(nbits-1 downto 0) := not r.dir;
else readdata(nbits-1 downto 0) := r.dir; end if;
when "0011" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.imask(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "0100" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.level(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "0101" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.edge(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "0110" =>
if (bypass /= 0) then
readdata(nbits-1 downto 0) :=
r.bypass(nbits-1 downto 0) and BPMASK(nbits-1 downto 0);
end if;
when "0111" =>
readdata(12 downto 8) := conv_std_logic_vector(irqgen, 5);
readdata(4 downto 0) := conv_std_logic_vector(nbits-1, 5);
when others =>
if irqgen > 1 then
for i in 0 to (nbits+3)/4-1 loop
if i = conv_integer(apbi.paddr(4 downto 2)) then
for j in 0 to 3 loop
if (j+i*4) > (nbits-1) then
exit;
end if;
readdata((24+log2x(NIRQMUX)-1-j*8) downto (24-j*8)) := r.irqmap(i*4+j);
end loop;
end if;
end loop;
end if;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(5 downto 2) is
when "0000" => null;
when "0001" => v.dout := apbi.pwdata(nbits-1 downto 0);
when "0010" =>
if oepol = 0 then v.dir := not apbi.pwdata(nbits-1 downto 0);
else v.dir := apbi.pwdata(nbits-1 downto 0); end if;
when "0011" =>
if (imask /= 0) then
v.imask := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "0100" =>
if (imask /= 0) then
v.level := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "0101" =>
if (imask /= 0) then
v.edge := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "0110" =>
if (bypass /= 0) then
v.bypass := apbi.pwdata(nbits-1 downto 0) and BPMASK(nbits-1 downto 0);
end if;
when "0111" =>
null;
when others =>
if irqgen > 1 then
for i in 0 to (nbits+3)/4-1 loop
if i = conv_integer(apbi.paddr(4 downto 2)) then
for j in 0 to 3 loop
if (j+i*4) > (nbits-1) then
exit;
end if;
v.irqmap(i*4+j) := apbi.pwdata((24+log2x(NIRQMUX)-1-j*8) downto (24-j*8));
end loop;
end if;
end loop;
end if;
end case;
end if;
-- interrupt filtering and routing
xirq := (others => '0'); tmp2 := (others => '0');
if (imask /= 0) then
tmp2(nbits-1 downto 0) := r.din2;
for i in 0 to nbits-1 loop
if (PIMASK(i) and r.imask(i)) = '1' then
if r.edge(i) = '1' then
if r.level(i) = '1' then tmp2(i) := r.din2(i) and not r.ilat(i);
else tmp2(i) := not r.din2(i) and r.ilat(i); end if;
else tmp2(i) := r.din2(i) xor not r.level(i); end if;
else
tmp2(i) := '0';
end if;
end loop;
for i in 0 to nbits-1 loop
if irqgen = 0 then
-- IRQ for line i = i + pirq
if (i+pirq) > NAHBIRQ-1 then
exit;
end if;
xirq(i+pirq) := tmp2(i);
else
-- IRQ for line i determined by irq select register i
for j in 0 to NIRQMUX-1 loop
if (j+pirq) > NAHBIRQ-1 then
exit;
end if;
if (irqgen = 1) or (j = conv_integer(r.irqmap(i))) then
xirq(j+pirq) := xirq(j+pirq) or tmp2(i);
end if;
end loop;
end if;
end loop;
end if;
-- drive filtered inputs on the output record
pval := (others => '0');
pval(nbits-1 downto 0) := r.din2;
-- Drive output with gpioi.sig_in for bypassed registers
if bypass /= 0 then
for i in 0 to nbits-1 loop
if r.bypass(i) = '1' then
dout(i) := gpioi.sig_in(i);
end if;
end loop;
end if;
-- Drive output with gpioi.sig_in for bypassed registers
if bpdir /= 0 then
for i in 0 to nbits-1 loop
if (BPDIRM(i) and gpioi.sig_en(i)) = '1' then
dout(i) := gpioi.sig_in(i);
if oepol = 0 then dir(i) := '0'; else dir(i) := '1'; end if;
end if;
end loop;
end if;
-- reset operation
if (not RESET_ALL) and (rst = '0') then
v.imask := RES.imask; v.bypass := RES.bypass;
v.dir := RES.dir; v.dout := RES.dout;
v.irqmap := RES.irqmap;
end if;
if irqgen < 2 then v.irqmap := (others => (others => '0')); end if;
rin <= v;
apbo.prdata <= readdata; -- drive apb read bus
apbo.pirq <= xirq;
if (scantest = 1) and (apbi.testen = '1') then
dir := (others => apbi.testoen);
elsif (syncrst = 1 ) and (rst = '0') then
if oepol = 1 then dir := (others => '0');
else dir := (others => '1'); end if;
end if;
gpioo.dout <= dout;
gpioo.oen <= dir;
gpioo.val <= pval;
-- non filtered input
gpioo.sig_out <= din;
end process;
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- registers
regs : process(clk, arst)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
-- Sync. registers din1 and din2 not reset
r.din1 <= rin.din1;
r.din2 <= rin.din2;
end if;
end if;
if (syncrst = 0 ) and (arst = '0') then
if oepol = 1 then r.dir <= (others => '0');
else r.dir <= (others => '1'); end if;
end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("grgpio" & tost(pindex) &
": " & tost(nbits) & "-bit GPIO Unit rev " & tost(REVISION));
-- pragma translate_on
end;
| gpl-2.0 | fb60c577d97c67270f043b9c97a26ccb | 0.567369 | 3.329882 | false | false | false | false |
JimLewis/OSVVM | TranscriptPkg.vhd | 1 | 7,730 | --
-- File Name: TranscriptPkg.vhd
-- Design Unit Name: TranscriptPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis [email protected]
--
--
-- Description:
-- Define file identifier TranscriptFile
-- provide subprograms to open, close, and print to it.
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 01/2015 2015.01 Initial revision
-- 01/2016 2016.01 TranscriptOpen function now calls procedure of same name
-- 11/2016 2016.l1 Added procedure BlankLine
-- 01/2020 2020.01 Updated Licenses to Apache
-- 12/2020 2020.12 Updated TranscriptOpen parameter Status to InOut to work around simulator bug.
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2015 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
package TranscriptPkg is
-- File Identifier to facilitate usage of one transcript file
file TranscriptFile : text ;
-- Cause compile errors if READ_MODE is passed to TranscriptOpen
subtype WRITE_APPEND_OPEN_KIND is FILE_OPEN_KIND range WRITE_MODE to APPEND_MODE ;
-- Open and close TranscriptFile. Function allows declarative opens
procedure TranscriptOpen (Status: InOut FILE_OPEN_STATUS; ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) ;
procedure TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) ;
impure function TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS ;
procedure TranscriptClose ;
impure function IsTranscriptOpen return boolean ;
alias IsTranscriptEnabled is IsTranscriptOpen [return boolean] ;
-- Mirroring. When using TranscriptPkw WriteLine and Print, uses both TranscriptFile and OUTPUT
procedure SetTranscriptMirror (A : boolean := TRUE) ;
impure function IsTranscriptMirrored return boolean ;
alias GetTranscriptMirror is IsTranscriptMirrored [return boolean] ;
-- Write to TranscriptFile when open. Write to OUTPUT when not open or IsTranscriptMirrored
procedure WriteLine(buf : inout line) ;
procedure Print(s : string) ;
-- Create "count" number of blank lines
procedure BlankLine (count : integer := 1) ;
end TranscriptPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body TranscriptPkg is
------------------------------------------------------------
type LocalBooleanPType is protected
procedure Set (A : boolean) ;
impure function get return boolean ;
end protected LocalBooleanPType ;
type LocalBooleanPType is protected body
variable GlobalVar : boolean := FALSE ;
procedure Set (A : boolean) is
begin
GlobalVar := A ;
end procedure Set ;
impure function get return boolean is
begin
return GlobalVar ;
end function get ;
end protected body LocalBooleanPType ;
------------------------------------------------------------
shared variable TranscriptEnable : LocalBooleanPType ;
shared variable TranscriptMirror : LocalBooleanPType ;
------------------------------------------------------------
procedure TranscriptOpen (Status: InOut FILE_OPEN_STATUS; ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) is
------------------------------------------------------------
begin
file_open(Status, TranscriptFile, ExternalName, OpenKind) ;
if Status = OPEN_OK then
TranscriptEnable.Set(TRUE) ;
end if ;
end procedure TranscriptOpen ;
------------------------------------------------------------
procedure TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) is
------------------------------------------------------------
variable Status : FILE_OPEN_STATUS ;
begin
TranscriptOpen(Status, ExternalName, OpenKind) ;
if Status /= OPEN_OK then
report "TranscriptPkg.TranscriptOpen file: " &
ExternalName & " status is: " & to_string(status) & " and is not OPEN_OK" severity FAILURE ;
end if ;
end procedure TranscriptOpen ;
------------------------------------------------------------
impure function TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS is
------------------------------------------------------------
variable Status : FILE_OPEN_STATUS ;
begin
TranscriptOpen(Status, ExternalName, OpenKind) ;
return Status ;
end function TranscriptOpen ;
------------------------------------------------------------
procedure TranscriptClose is
------------------------------------------------------------
begin
if TranscriptEnable.Get then
file_close(TranscriptFile) ;
end if ;
TranscriptEnable.Set(FALSE) ;
end procedure TranscriptClose ;
------------------------------------------------------------
impure function IsTranscriptOpen return boolean is
------------------------------------------------------------
begin
return TranscriptEnable.Get ;
end function IsTranscriptOpen ;
------------------------------------------------------------
procedure SetTranscriptMirror (A : boolean := TRUE) is
------------------------------------------------------------
begin
TranscriptMirror.Set(A) ;
end procedure SetTranscriptMirror ;
------------------------------------------------------------
impure function IsTranscriptMirrored return boolean is
------------------------------------------------------------
begin
return TranscriptMirror.Get ;
end function IsTranscriptMirrored ;
------------------------------------------------------------
procedure WriteLine(buf : inout line) is
------------------------------------------------------------
begin
if not TranscriptEnable.Get then
WriteLine(OUTPUT, buf) ;
elsif TranscriptMirror.Get then
TEE(TranscriptFile, buf) ;
else
WriteLine(TranscriptFile, buf) ;
end if ;
end procedure WriteLine ;
------------------------------------------------------------
procedure Print(s : string) is
------------------------------------------------------------
variable buf : line ;
begin
write(buf, s) ;
WriteLine(buf) ;
end procedure Print ;
------------------------------------------------------------
procedure BlankLine (count : integer := 1) is
------------------------------------------------------------
begin
for i in 1 to count loop
print("") ;
end loop ;
end procedure Blankline ;
end package body TranscriptPkg ; | artistic-2.0 | d101e983b5ac2937eb8aac497b0a130a | 0.545537 | 5.215924 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/unisim/clkgen_virtex.vhd | 1 | 21,645 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: clkgen_xilinx.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Author: Richard Pender, Pender Electronic Design
-- Description: Clock generators for Virtex and Virtex-2 fpgas
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.CLKDLL;
use unisim.BUFGDLL;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_virtex is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type
);
end;
architecture rtl of clkgen_virtex is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component CLKDLL
port (
CLK0 : out std_ulogic;
CLK180 : out std_ulogic;
CLK270 : out std_ulogic;
CLK2X : out std_ulogic;
CLK90 : out std_ulogic;
CLKDV : out std_ulogic;
LOCKED : out std_ulogic;
CLKFB : in std_ulogic;
CLKIN : in std_ulogic;
RST : in std_ulogic);
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
signal gnd, clk_i, clk_j, clk_k, dll0rst, dll0lock, dll1lock : std_logic;
signal dll1rst : std_logic_vector(0 to 3);
signal clk0B, clkint, CLK2XL, CLKDV, CLK180, pciclkint : std_logic;
begin
gnd <= '0'; clk <= clk_i; clkn <= not clk_i;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
dll0rst <= not cgi.pllrst;
dll0 : CLKDLL
port map (CLKIN => clkint, CLKFB => clk_k, CLK0 => clk_j, CLK180 => CLK180,
CLK2X => CLK2XL, CLKDV => CLKDV, LOCKED => dll0lock, RST => dll0rst);
clk0B <= CLK2XL when clk_mul/clk_div = 2
else CLKDV when clk_div/clk_mul = 2 else clk_j;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB = 0) generate
cgo.clklock <= dll1lock;
dll1 : CLKDLL
port map (CLKIN => clk_i, CLKFB => cgi.pllref, RST => dll1rst(0), CLK0 => sdclk,
CLK2X => clk2x, LOCKED => dll1lock);
rstdel : process (clk_i)
begin
if dll0lock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_i) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if not ((SDRAMEN /= 0) and (NOCLKFB = 0)) generate
sdclk <= clk_i; cgo.clklock <= dll0lock;
end generate;
cgo.pcilock <= '1';
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.IBUFG;
use unisim.BUFG;
use unisim.DCM;
use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex2 clock generator ---------------------------------------
------------------------------------------------------------------
entity clkgen_virtex2 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_virtex2 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component IBUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
--constant CLKIN_PERIOD_ST : string := "20.0";
--attribute CLKIN_PERIOD : string;
--attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r, dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint, pciclkl, pciclkfb, pciclk0 : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= clk_m; clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
p2 : if (PCIDLL /= 0) and ( PCIDLL /= 1) generate
x1 : IBUFG port map (I => pciclkint, O => pciclkl);
dll0 : DCM
generic map (CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => PCIDLL)
port map ( CLKIN => pciclkint, CLKFB => pciclkfb,
DSSEN => gnd, PSCLK => gnd,
RST => gnd, PSEN => gnd, PSINCDEC => gnd, CLK0 => pciclk0);
x2 : BUFG port map (I => pciclk0, O => pciclkfb);
pciclk <= pciclkfb;
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_k;
clk2xu <= clk_x;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
bufg2 : BUFG port map (I => clk_l, O => clk_m);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
clk2xgen : if (CLK2XEN /= 0) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
bufg3 : BUFG port map (I => clk_x, O => clk_i2);
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => sdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_virtex2" & ": virtex-2 sdram/pci clock generator, version " & tost(VERSION),
"clkgen_virtex2" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkmul_virtex2 is
generic ( clk_mul : integer := 2 ; clk_div : integer := 2);
port (
resetin : in std_logic;
clkin : in std_logic;
clk : out std_logic;
resetout: out std_logic
);
end;
architecture struct of clkmul_virtex2 is
-- attribute CLKFX_MULTIPLY : string;
-- attribute CLKFX_DIVIDE : string;
-- attribute CLKIN_PERIOD : string;
--
-- attribute CLKFX_MULTIPLY of dll0: label is "5";
-- attribute CLKFX_DIVIDE of dll0: label is "4";
-- attribute CLKIN_PERIOD of dll0: label is "20";
--
-- attribute CLKFX_MULTIPLY of dll1: label is "4";
-- attribute CLKFX_DIVIDE of dll1: label is "4";
-- attribute CLKIN_PERIOD of dll1: label is "25";
--
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port ( O : out std_logic; I : in std_logic); end component;
signal gnd, clk_i, clk_j, clk_k, clk_l : std_logic;
signal clk0B, clk_FB, dll0rst, lock : std_logic;
begin
gnd <= '0'; clk <= clk_i;
dll0rst <= not resetin;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clkin, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
LOCKED => resetout, CLKFX => clk0B );
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_spartan3 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 50000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_spartan3 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
--constant CLKIN_PERIOD_ST : string := "20.0";
--attribute CLKIN_PERIOD : string;
--attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r, dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= not clk_i when (CLK2XEN = 0) else not clk_p;
clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_j;
clk2xu <= clk_k;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_x, O => clk_k);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLK_FEEDBACK => "2X")
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
clk2xgen : if (CLK2XEN /= 0) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
clk_i2 <= clk_k;
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => sdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_spartan3e" & ": spartan3/e sdram/pci clock generator, version " & tost(VERSION),
"clkgen_spartan3e" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
| gpl-2.0 | 86bbf110e02d5a8d8869b4a9b21cea0e | 0.586602 | 3.281037 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/nandtree.vhd | 1 | 2,422 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: nandtree
-- File: nandtree.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Nand-tree with tech mapping
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity nandtree is
generic(
tech : integer := inferred;
width : integer := 2;
imp : integer := 0 );
port( i : in std_logic_vector(width-1 downto 0);
o : out std_ulogic;
en : in std_ulogic
);
end entity;
architecture rtl of nandtree is
component rh_lib18t_nand_tree
generic (npins : integer := 2);
port(
-- Input Signlas: --
TEST_MODE : in std_logic;
IN_PINS_BUS : in std_logic_vector(npins-1 downto 0);
NAND_TREE_OUT : out std_logic
);
end component;
function fnandtree(v : std_logic_vector) return std_ulogic is
variable a : std_logic_vector(v'length-1 downto 0);
variable b : std_logic_vector(v'length downto 0);
begin
a := v; b(0) := '1';
for i in 0 to v'length-1 loop
b(i+1) := a(i) nand b(i);
end loop;
return b(v'length);
end;
begin
behav : if tech /= rhlib18t generate
o <= fnandtree(i);
end generate;
rhlib : if tech = rhlib18t generate
rhnand : rh_lib18t_nand_tree generic map (width)
port map (en, i, o);
end generate;
end;
| gpl-2.0 | 703b9f0ab33f048931313950da4f03ed | 0.598679 | 3.749226 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ml50x/config.vhd | 1 | 7,602 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2012 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.devices.all;
package config is
-- Board selection
constant CFG_BOARD_SELECTION : system_device_type := XILINX_ML505;
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex5;
constant CFG_MEMTECH : integer := virtex5;
constant CFG_PADTECH : integer := virtex5;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex5;
constant CFG_CLKMUL : integer := (6);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 8;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000505#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 0;
constant CFG_MIG_RANKS : integer := 1;
constant CFG_MIG_COLBITS : integer := 10;
constant CFG_MIG_ROWBITS : integer := 13;
constant CFG_MIG_BANKBITS: integer := 2;
constant CFG_MIG_HMASK : integer := 16#F00#;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (190);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (256);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0FFFE#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- AMBA Wrapper for Xilinx System Monitor
constant CFG_GRSYSMON : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- PCIEXP interface
constant CFG_PCIEXP : integer := 0;
constant CFG_PCIE_TYPE : integer := 0;
constant CFG_PCIE_SIM_MAS : integer := 0;
constant CFG_PCIEXPVID : integer := 16#0#;
constant CFG_PCIEXPDID : integer := 16#0#;
constant CFG_NO_OF_LANES : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 420b899ebd8f22d47caa2eb8cc016bb3 | 0.652328 | 3.544056 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/unisim/clkgen_unisim.vhd | 1 | 18,422 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: clkgen_xilinx.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Author: Richard Pender, Pender Electronic Design
-- Description: Clock generators for Virtex and Virtex-2 fpgas
------------------------------------------------------------------------------
------------------------------------------------------------------
-- Virtex5 clock generator ---------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
--use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_virtex5 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_virtex5 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
-- component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
--constant CLKIN_PERIOD_ST : string := "20.0";
constant FREQ_MHZ : integer := freq/1000;
--attribute CLKIN_PERIOD : string;
--attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, lsdclk : std_logic;
signal clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r: std_logic;
signal dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= clk_m; clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
-- x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
--pragma translate_off
assert false report "PCIDLL = 1 currently not supported for virtex5_clkgen"
severity failure;
--pragma translate_on
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_k;
clk2xu <= clk_x;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
bufg2 : BUFG port map (I => clk_l, O => clk_m);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
-- HMODE_dll0 : if (((FREQ_MHZ*clk_mul)/clk_div >= 140) or (FREQ_MHZ >= 120)) generate
-- dll0 : DCM
-- generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
-- DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH")
-- port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
-- PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
-- CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
-- end generate;
-- LMODE_dll0 : if not (((FREQ_MHZ*clk_mul)/clk_div >= 140) or (FREQ_MHZ >= 120)) generate
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
-- end generate;
clk2xgen : if (CLK2XEN /= 0) generate
-- HMODE_dll2x : if ((FREQ_MHZ*clk_mul)/clk_div >= 120) generate
-- dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
-- DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH")
-- port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
-- PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
-- CLK2X => clk_n, LOCKED => dll2xlock);
-- end generate;
-- LMODE_dll2x : if not ((FREQ_MHZ*clk_mul)/clk_div >= 120) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
-- end generate;
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
clk_i2 <= clk_x;
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
-- HMODE_dll1 : if ((FREQ_MHZ*clk_mul)/clk_div >= (120-60*(CLK2XEN/2))) generate
-- dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
-- DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH",
-- DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
-- port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
-- PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => lsdclk, --CLK2X => clk2x,
-- LOCKED => dll1lock);
-- end generate;
-- LMODE_dll1 : if not ((FREQ_MHZ*clk_mul)/clk_div >= (120-60*(CLK2XEN/2))) generate
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW",
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => lsdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
-- end generate;
bufgx : BUFG port map (I => lsdclk, O => sdclk);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_virtex5" & ": virtex-5 sdram/pci clock generator, version " & tost(VERSION),
"clkgen_virtex5" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
------------------------------------------------------------------
-- Virtex7 clock generator ---------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use UNISIM.vcomponents.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_virtex7 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
freq : integer := 200000 -- clock frequency in KHz
);
port (
clkin : in std_ulogic;
clk : out std_ulogic; -- main clock
clk90 : out std_ulogic; -- main clock 90deg
clkio : out std_ulogic; -- IO ref clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type
);
end;
architecture struct of clkgen_virtex7 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
----- component PLLE2_ADV -----
component PLLE2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT : integer := 5;
CLKFBOUT_PHASE : real := 0.0;
CLKIN1_PERIOD : real := 0.0;
CLKIN2_PERIOD : real := 0.0;
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 0.0;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 0.0;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 0.0;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 0.0;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 0.0;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 0.0;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
STARTUP_WAIT : string := "FALSE"
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
constant VERSION : integer := 1;
constant period : real := 1000000.0/real(freq);
constant clkio_div : integer := freq*clk_mul/200000;
signal CLKFBOUT : std_logic;
signal CLKFBIN : std_logic;
signal int_rst : std_logic;
signal clk_nobuf : std_logic;
signal clk90_nobuf : std_logic;
signal clkio_nobuf : std_logic;
begin
CLKFBIN <= CLKFBOUT;
int_rst <= not cgi.pllrst;
PLLE2_ADV_inst : PLLE2_ADV
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => clk_mul, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => period,
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => clk_div,
CLKOUT1_DIVIDE => clk_div,
CLKOUT2_DIVIDE => clkio_div,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 90.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => "TRUE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => clk_nobuf,
CLKOUT1 => clk90_nobuf,
CLKOUT2 => clkio_nobuf,
CLKOUT3 => OPEN,
CLKOUT4 => OPEN,
CLKOUT5 => OPEN,
-- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
DO => OPEN,
DRDY => OPEN,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => CLKFBOUT,
-- Status Ports: 1-bit (each) output: PLL status ports
LOCKED => cgo.clklock,
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => clkin,
CLKIN2 => '0',
-- Con trol Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => int_rst,
-- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => CLKFBIN
);
cgo.pcilock <= '0';
bufgclk0 : BUFG port map (I => clk_nobuf, O => clk);
bufgclk90 : BUFG port map (I => clk90_nobuf, O => clk90);
bufgclkio : BUFG port map (I => clkio_nobuf, O => clkio);
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_virtex7" & ": virtex-7 sdram/pci clock generator, version " & tost(VERSION),
"clkgen_virtex7" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkand_unisim is
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkand_unisim is
component BUFGCE
port(
O : out STD_ULOGIC;
CE: in STD_ULOGIC;
I : in STD_ULOGIC
);
end component;
begin
buf : bufgce port map(I => i, CE => en, O => o);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkmux_unisim is
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkmux_unisim is
component bufgmux is
port(
i0, i1 : in std_ulogic;
s : in std_ulogic;
o : out std_ulogic);
end component;
signal sel0, sel1, cg0, cg1 : std_ulogic;
begin
buf : bufgmux port map(S => sel, I0 => i0, I1 => i1, O => o);
end architecture;
| gpl-2.0 | fe56651215483b2503da5d7e1b599316 | 0.56438 | 3.417177 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/Zynq_Book/hls/tut3A/matrix_mult_prj/solution5/syn/vhdl/matrix_mult_mul_8bkb.vhd | 3 | 2,935 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity matrix_mult_mul_8bkb_Mul5S_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(8 - 1 downto 0);
b: in std_logic_vector(8 - 1 downto 0);
p: out std_logic_vector(16 - 1 downto 0));
end entity;
architecture behav of matrix_mult_mul_8bkb_Mul5S_0 is
signal tmp_product : std_logic_vector(16 - 1 downto 0);
signal a_i : std_logic_vector(8 - 1 downto 0);
signal b_i : std_logic_vector(8 - 1 downto 0);
signal p_tmp : std_logic_vector(16 - 1 downto 0);
signal a_reg0 : std_logic_vector(8 - 1 downto 0);
signal b_reg0 : std_logic_vector(8 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(16 - 1 downto 0);
signal buff1 : std_logic_vector(16 - 1 downto 0);
signal buff2 : std_logic_vector(16 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff2;
tmp_product <= std_logic_vector(resize(unsigned(std_logic_vector(signed(a_reg0) * signed(b_reg0))), 16));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
buff1 <= buff0;
buff2 <= buff1;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity matrix_mult_mul_8bkb is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of matrix_mult_mul_8bkb is
component matrix_mult_mul_8bkb_Mul5S_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
matrix_mult_mul_8bkb_Mul5S_0_U : component matrix_mult_mul_8bkb_Mul5S_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| mit | 5a838a282b14d7d021d56d98d771e556 | 0.52879 | 3.393064 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_auto_pc_3/zqynq_lab_1_design_auto_pc_3_sim_netlist.vhdl | 2 | 29,664 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:13:47 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top zqynq_lab_1_design_auto_pc_3 -prefix
-- zqynq_lab_1_design_auto_pc_3_ zqynq_lab_1_design_auto_pc_3_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_auto_pc_3
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_arready\ : STD_LOGIC;
signal \^m_axi_awready\ : STD_LOGIC;
signal \^m_axi_bid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_buser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_bvalid\ : STD_LOGIC;
signal \^m_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^m_axi_rid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_rlast\ : STD_LOGIC;
signal \^m_axi_rresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_ruser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_rvalid\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_araddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_arburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_arlen\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arlock\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_arqos\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_aruser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_arvalid\ : STD_LOGIC;
signal \^s_axi_awaddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_awburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_awlen\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awlock\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_awprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_awqos\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_awuser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_awvalid\ : STD_LOGIC;
signal \^s_axi_bready\ : STD_LOGIC;
signal \^s_axi_rready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wlast\ : STD_LOGIC;
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wuser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_arready\ <= m_axi_arready;
\^m_axi_awready\ <= m_axi_awready;
\^m_axi_bid\(11 downto 0) <= m_axi_bid(11 downto 0);
\^m_axi_bresp\(1 downto 0) <= m_axi_bresp(1 downto 0);
\^m_axi_buser\(0) <= m_axi_buser(0);
\^m_axi_bvalid\ <= m_axi_bvalid;
\^m_axi_rdata\(31 downto 0) <= m_axi_rdata(31 downto 0);
\^m_axi_rid\(11 downto 0) <= m_axi_rid(11 downto 0);
\^m_axi_rlast\ <= m_axi_rlast;
\^m_axi_rresp\(1 downto 0) <= m_axi_rresp(1 downto 0);
\^m_axi_ruser\(0) <= m_axi_ruser(0);
\^m_axi_rvalid\ <= m_axi_rvalid;
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_araddr\(31 downto 0) <= s_axi_araddr(31 downto 0);
\^s_axi_arburst\(1 downto 0) <= s_axi_arburst(1 downto 0);
\^s_axi_arcache\(3 downto 0) <= s_axi_arcache(3 downto 0);
\^s_axi_arid\(11 downto 0) <= s_axi_arid(11 downto 0);
\^s_axi_arlen\(3 downto 0) <= s_axi_arlen(3 downto 0);
\^s_axi_arlock\(0) <= s_axi_arlock(0);
\^s_axi_arprot\(2 downto 0) <= s_axi_arprot(2 downto 0);
\^s_axi_arqos\(3 downto 0) <= s_axi_arqos(3 downto 0);
\^s_axi_arsize\(2 downto 0) <= s_axi_arsize(2 downto 0);
\^s_axi_aruser\(0) <= s_axi_aruser(0);
\^s_axi_arvalid\ <= s_axi_arvalid;
\^s_axi_awaddr\(31 downto 0) <= s_axi_awaddr(31 downto 0);
\^s_axi_awburst\(1 downto 0) <= s_axi_awburst(1 downto 0);
\^s_axi_awcache\(3 downto 0) <= s_axi_awcache(3 downto 0);
\^s_axi_awid\(11 downto 0) <= s_axi_awid(11 downto 0);
\^s_axi_awlen\(3 downto 0) <= s_axi_awlen(3 downto 0);
\^s_axi_awlock\(0) <= s_axi_awlock(0);
\^s_axi_awprot\(2 downto 0) <= s_axi_awprot(2 downto 0);
\^s_axi_awqos\(3 downto 0) <= s_axi_awqos(3 downto 0);
\^s_axi_awsize\(2 downto 0) <= s_axi_awsize(2 downto 0);
\^s_axi_awuser\(0) <= s_axi_awuser(0);
\^s_axi_awvalid\ <= s_axi_awvalid;
\^s_axi_bready\ <= s_axi_bready;
\^s_axi_rready\ <= s_axi_rready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wlast\ <= s_axi_wlast;
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wuser\(0) <= s_axi_wuser(0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_araddr(31 downto 0) <= \^s_axi_araddr\(31 downto 0);
m_axi_arburst(1 downto 0) <= \^s_axi_arburst\(1 downto 0);
m_axi_arcache(3 downto 0) <= \^s_axi_arcache\(3 downto 0);
m_axi_arid(11 downto 0) <= \^s_axi_arid\(11 downto 0);
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3 downto 0) <= \^s_axi_arlen\(3 downto 0);
m_axi_arlock(0) <= \^s_axi_arlock\(0);
m_axi_arprot(2 downto 0) <= \^s_axi_arprot\(2 downto 0);
m_axi_arqos(3 downto 0) <= \^s_axi_arqos\(3 downto 0);
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2 downto 0) <= \^s_axi_arsize\(2 downto 0);
m_axi_aruser(0) <= \^s_axi_aruser\(0);
m_axi_arvalid <= \^s_axi_arvalid\;
m_axi_awaddr(31 downto 0) <= \^s_axi_awaddr\(31 downto 0);
m_axi_awburst(1 downto 0) <= \^s_axi_awburst\(1 downto 0);
m_axi_awcache(3 downto 0) <= \^s_axi_awcache\(3 downto 0);
m_axi_awid(11 downto 0) <= \^s_axi_awid\(11 downto 0);
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3 downto 0) <= \^s_axi_awlen\(3 downto 0);
m_axi_awlock(0) <= \^s_axi_awlock\(0);
m_axi_awprot(2 downto 0) <= \^s_axi_awprot\(2 downto 0);
m_axi_awqos(3 downto 0) <= \^s_axi_awqos\(3 downto 0);
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2 downto 0) <= \^s_axi_awsize\(2 downto 0);
m_axi_awuser(0) <= \^s_axi_awuser\(0);
m_axi_awvalid <= \^s_axi_awvalid\;
m_axi_bready <= \^s_axi_bready\;
m_axi_rready <= \^s_axi_rready\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \^s_axi_wlast\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \^s_axi_wuser\(0);
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_arready <= \^m_axi_arready\;
s_axi_awready <= \^m_axi_awready\;
s_axi_bid(11 downto 0) <= \^m_axi_bid\(11 downto 0);
s_axi_bresp(1 downto 0) <= \^m_axi_bresp\(1 downto 0);
s_axi_buser(0) <= \^m_axi_buser\(0);
s_axi_bvalid <= \^m_axi_bvalid\;
s_axi_rdata(31 downto 0) <= \^m_axi_rdata\(31 downto 0);
s_axi_rid(11 downto 0) <= \^m_axi_rid\(11 downto 0);
s_axi_rlast <= \^m_axi_rlast\;
s_axi_rresp(1 downto 0) <= \^m_axi_rresp\(1 downto 0);
s_axi_ruser(0) <= \^m_axi_ruser\(0);
s_axi_rvalid <= \^m_axi_rvalid\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_3 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zqynq_lab_1_design_auto_pc_3 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_auto_pc_3 : entity is "zqynq_lab_1_design_auto_pc_3,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zqynq_lab_1_design_auto_pc_3 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zqynq_lab_1_design_auto_pc_3 : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
end zqynq_lab_1_design_auto_pc_3;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_3 is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 0;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.zqynq_lab_1_design_auto_pc_3_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arid(11 downto 0) => m_axi_arid(11 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(11 downto 0) => m_axi_awid(11 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => m_axi_bid(11 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | be3770dbdc59036ce7f88557827e65ca | 0.640743 | 2.871358 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/1134498f5baab19e/ip_design_processing_system7_0_0_sim_netlist.vhdl | 1 | 207,197 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Wed Oct 18 15:15:21 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_processing_system7_0_0_sim_netlist.vhdl
-- Design : ip_design_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "ip_design_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 1 downto 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_1.FCLK_CLK_1_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2);
M_AXI_GP0_ARCACHE(1) <= \<const1>\;
M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0);
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2);
M_AXI_GP0_AWCACHE(1) <= \<const1>\;
M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2);
M_AXI_GP1_ARCACHE(1) <= \<const1>\;
M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2);
M_AXI_GP1_AWCACHE(1) <= \<const1>\;
M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1 downto 0) => FCLK_CLK_unbuffered(1 downto 0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2),
MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1),
MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2),
MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1),
MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2),
MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1),
MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2),
MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1),
MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\buffer_fclk_clk_1.FCLK_CLK_1_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(1),
O => FCLK_CLK1
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "processing_system7_v5_5_processing_system7,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "ip_design_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N";
attribute X_INTERFACE_INFO of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE";
attribute X_INTERFACE_INFO of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N";
attribute X_INTERFACE_INFO of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P";
attribute X_INTERFACE_INFO of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N";
attribute X_INTERFACE_INFO of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N";
attribute X_INTERFACE_INFO of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT";
attribute X_INTERFACE_INFO of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N";
attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of FCLK_CLK1 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK";
attribute X_INTERFACE_PARAMETER of FCLK_CLK1 : signal is "XIL_INTERFACENAME FCLK_CLK1, FREQ_HZ 10000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK1";
attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST";
attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of I2C0_SCL_I : signal is "xilinx.com:interface:iic:1.0 IIC_0 SCL_I";
attribute X_INTERFACE_INFO of I2C0_SCL_O : signal is "xilinx.com:interface:iic:1.0 IIC_0 SCL_O";
attribute X_INTERFACE_INFO of I2C0_SCL_T : signal is "xilinx.com:interface:iic:1.0 IIC_0 SCL_T";
attribute X_INTERFACE_INFO of I2C0_SDA_I : signal is "xilinx.com:interface:iic:1.0 IIC_0 SDA_I";
attribute X_INTERFACE_INFO of I2C0_SDA_O : signal is "xilinx.com:interface:iic:1.0 IIC_0 SDA_O";
attribute X_INTERFACE_INFO of I2C0_SDA_T : signal is "xilinx.com:interface:iic:1.0 IIC_0 SDA_T";
attribute X_INTERFACE_INFO of M_AXI_GP0_ACLK : signal is "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK";
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_ACLK : signal is "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_BREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_BVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_RLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST";
attribute X_INTERFACE_INFO of M_AXI_GP0_RREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_RVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_WLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST";
attribute X_INTERFACE_INFO of M_AXI_GP0_WREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_WVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID";
attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
attribute X_INTERFACE_INFO of USB0_VBUS_PWRFAULT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT";
attribute X_INTERFACE_INFO of USB0_VBUS_PWRSELECT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT";
attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR";
attribute X_INTERFACE_INFO of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA";
attribute X_INTERFACE_INFO of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM";
attribute X_INTERFACE_INFO of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ";
attribute X_INTERFACE_INFO of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P";
attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11";
attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE";
attribute X_INTERFACE_INFO of M_AXI_GP0_BID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID";
attribute X_INTERFACE_INFO of M_AXI_GP0_BRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP";
attribute X_INTERFACE_INFO of M_AXI_GP0_RDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA";
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_RDATA : signal is "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of M_AXI_GP0_RID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID";
attribute X_INTERFACE_INFO of M_AXI_GP0_RRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP";
attribute X_INTERFACE_INFO of M_AXI_GP0_WDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA";
attribute X_INTERFACE_INFO of M_AXI_GP0_WID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID";
attribute X_INTERFACE_INFO of M_AXI_GP0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB";
attribute X_INTERFACE_INFO of USB0_PORT_INDCTL : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => FCLK_CLK1,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => I2C0_SCL_I,
I2C0_SCL_O => I2C0_SCL_O,
I2C0_SCL_T => I2C0_SCL_T,
I2C0_SDA_I => I2C0_SDA_I,
I2C0_SDA_O => I2C0_SDA_O,
I2C0_SDA_T => I2C0_SDA_T,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => '0',
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | 487a0580dab3ff40c4dfd1ec0d29f3a0 | 0.639681 | 2.763916 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_bram_0/synth/zqynq_lab_1_design_axi_bram_ctrl_0_bram_0.vhd | 1 | 15,765 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_6;
USE blk_mem_gen_v8_3_6.blk_mem_gen_v8_3_6;
ENTITY zqynq_lab_1_design_axi_bram_ctrl_0_bram_0 IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END zqynq_lab_1_design_axi_bram_ctrl_0_bram_0;
ARCHITECTURE zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_arch OF zqynq_lab_1_design_axi_bram_ctrl_0_bram_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_6 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_6;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_6,Vivado 2017.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_arch : ARCHITECTURE IS "zqynq_lab_1_design_axi_bram_ctrl_0_bram_0,blk_mem_gen_v8_3_6,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_arch: ARCHITECTURE IS "zqynq_lab_1_design_axi_bram_ctrl_0_bram_0,blk_mem_gen_v8_3_6,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=1,C_ENABLE_32BIT_ADDRESS=1,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=" &
"0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=NONE,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=16384,C_READ_DEPTH_A=16384,C_ADDRA_WIDTH=32,C_HAS_RSTB=1,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C" &
"_READ_WIDTH_B=32,C_WRITE_DEPTH_B=16384,C_READ_DEPTH_B=16384,C_ADDRB_WIDTH=32,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=" &
"0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=16,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 20.388 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF rstb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_6
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 1,
C_ENABLE_32BIT_ADDRESS => 1,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "NONE",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 1,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 4,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 16384,
C_READ_DEPTH_A => 16384,
C_ADDRA_WIDTH => 32,
C_HAS_RSTB => 1,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 4,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 16384,
C_READ_DEPTH_B => 16384,
C_ADDRB_WIDTH => 32,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "16",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 20.388 mW"
)
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => rstb,
enb => enb,
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_arch;
| mit | 9d33d54499de94e667dae3176e886a30 | 0.634887 | 3.004574 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/impl/vhdl/project.srcs/sources_1/ip/convolve_kernel_ap_fadd_12_no_dsp_32/synth/convolve_kernel_ap_fadd_12_no_dsp_32.vhd | 3 | 12,824 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY convolve_kernel_ap_fadd_12_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END convolve_kernel_ap_fadd_12_no_dsp_32;
ARCHITECTURE convolve_kernel_ap_fadd_12_no_dsp_32_arch OF convolve_kernel_ap_fadd_12_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fadd_12_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fadd_12_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_4,Vivado 2017.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fadd_12_no_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fadd_12_no_dsp_32,floating_point_v7_1_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fadd_12_no_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fadd_12_no_dsp_32,floating_point_v7_1_4,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=" &
"0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=12,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C" &
"_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 12,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END convolve_kernel_ap_fadd_12_no_dsp_32_arch;
| mit | 57a7e8bcfad2ff45efeca9f262bf7d97 | 0.651591 | 3.007505 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.ip_user_files/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_gpio_1_0/zqynq_lab_1_design_axi_gpio_1_0_sim_netlist.vhdl | 1 | 111,727 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:28:59 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_gpio_1_0/zqynq_lab_1_design_axi_gpio_1_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_gpio_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_gpio_1_0_address_decoder is
port (
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[4]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
Read_Reg_Rst : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]_0\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
start2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
is_read : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
\bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 4 downto 0 );
\Not_Dual.gpio_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
bus2ip_reset : in STD_LOGIC;
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_gpio_1_0_address_decoder : entity is "address_decoder";
end zqynq_lab_1_design_axi_gpio_1_0_address_decoder;
architecture STRUCTURE of zqynq_lab_1_design_axi_gpio_1_0_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\ : STD_LOGIC;
signal \^not_dual.gpio_data_out_reg[4]\ : STD_LOGIC;
signal \^ip2bus_data_i_d1_reg[0]\ : STD_LOGIC;
signal \^ip_irpt_enable_reg_reg[0]\ : STD_LOGIC;
signal p_10_in : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_11_out : STD_LOGIC;
signal p_12_in : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_15_out : STD_LOGIC;
signal p_16_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in_0 : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_in : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pselect_hit_i_1 : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of intr2bus_rdack_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of intr2bus_wrack_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of irpt_rdack_d1_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of irpt_wrack_d1_i_1 : label is "soft_lutpair1";
begin
\Not_Dual.gpio_Data_Out_reg[4]\ <= \^not_dual.gpio_data_out_reg[4]\;
\ip2bus_data_i_D1_reg[0]\ <= \^ip2bus_data_i_d1_reg[0]\;
\ip_irpt_enable_reg_reg[0]\ <= \^ip_irpt_enable_reg_reg[0]\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => start2,
I2 => \^ip_irpt_enable_reg_reg[0]\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^ip_irpt_enable_reg_reg[0]\,
R => '0'
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_9_out
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_9_out,
Q => p_10_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_8_out
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_8_out,
Q => p_9_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_7_out
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_7_out,
Q => \^ip2bus_data_i_d1_reg[0]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_6_out
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_6_out,
Q => p_7_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_5_out
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_5_out,
Q => p_6_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_4_out
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_4_out,
Q => p_5_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\,
Q => p_4_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\,
Q => p_3_in_0,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\,
Q => p_2_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => s_axi_aresetn,
I1 => \^s_axi_arready\,
I2 => \^s_axi_wready\,
O => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_15_out
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_15_out,
Q => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\,
Q => p_16_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_14_out
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_14_out,
Q => p_15_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_13_out
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_13_out,
Q => p_14_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0200000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_12_out
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_12_out,
Q => p_13_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_11_out
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_11_out,
Q => p_12_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_10_out
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_10_out,
Q => p_11_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => intr_rd_ce_or_reduce
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FE0000"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => ip2Bus_RdAck_intr_reg_hole_d1,
I4 => \^ip_irpt_enable_reg_reg[0]\,
O => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FE"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => intr_wr_ce_or_reduce
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => p_16_in,
I1 => p_2_in,
I2 => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\,
I3 => p_14_in,
I4 => p_15_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_12_in,
I1 => p_13_in,
I2 => p_10_in,
I3 => p_11_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_5_in,
I1 => p_7_in,
I2 => p_3_in_0,
I3 => p_4_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000FE"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ip_irpt_enable_reg_reg[0]\,
I4 => ip2Bus_WrAck_intr_reg_hole_d1,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\
);
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => start2,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(4),
I3 => \bus2ip_addr_i_reg[8]\(5),
I4 => \bus2ip_addr_i_reg[8]\(3),
I5 => \bus2ip_addr_i_reg[8]\(2),
O => pselect_hit_i_1
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => pselect_hit_i_1,
Q => \^not_dual.gpio_data_out_reg[4]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(4),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(4),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[4]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => GPIO_DBus_i(0)
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(3),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(3),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[4]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(2),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(2),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[4]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(1),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(1),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[4]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^not_dual.gpio_data_out_reg[4]\,
I1 => GPIO_xferAck_i,
I2 => bus2ip_rnw_i_reg,
I3 => gpio_xferAck_Reg,
O => Read_Reg_Rst
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(0),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(0),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[4]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\
);
\Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000100"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^not_dual.gpio_data_out_reg[4]\,
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => bus2ip_reset,
O => \Not_Dual.gpio_Data_Out_reg[0]\(0)
);
\Not_Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(9),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[4]\,
I3 => s_axi_wdata(4),
O => D(4)
);
\Not_Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(8),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[4]\,
I3 => s_axi_wdata(3),
O => D(3)
);
\Not_Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(7),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[4]\,
I3 => s_axi_wdata(2),
O => D(2)
);
\Not_Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(6),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[4]\,
I3 => s_axi_wdata(1),
O => D(1)
);
\Not_Dual.gpio_Data_Out[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(5),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[4]\,
I3 => s_axi_wdata(0),
O => D(0)
);
\Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF01000000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^not_dual.gpio_data_out_reg[4]\,
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => bus2ip_reset,
O => E(0)
);
intr2bus_rdack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"44444440"
)
port map (
I0 => irpt_rdack_d1,
I1 => \^ip_irpt_enable_reg_reg[0]\,
I2 => p_9_in,
I3 => \^ip2bus_data_i_d1_reg[0]\,
I4 => p_6_in,
O => intr2bus_rdack0
);
intr2bus_wrack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000FE"
)
port map (
I0 => p_9_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => p_6_in,
I3 => \^ip_irpt_enable_reg_reg[0]\,
I4 => irpt_wrack_d1,
O => interrupt_wrce_strb
);
\ip2bus_data_i_D1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => p_0_in(0),
I1 => p_9_in,
I2 => \^ip_irpt_enable_reg_reg[0]\,
I3 => p_6_in,
I4 => \^ip2bus_data_i_d1_reg[0]\,
O => \ip2bus_data_i_D1_reg[0]_0\(1)
);
\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEAAAAFAAAAAAA"
)
port map (
I0 => ip2bus_data(0),
I1 => p_3_in(0),
I2 => p_1_in(0),
I3 => p_6_in,
I4 => \^ip_irpt_enable_reg_reg[0]\,
I5 => \^ip2bus_data_i_d1_reg[0]\,
O => \ip2bus_data_i_D1_reg[0]_0\(0)
);
\ip_irpt_enable_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => p_6_in,
I2 => \^ip_irpt_enable_reg_reg[0]\,
I3 => p_1_in(0),
O => \ip_irpt_enable_reg_reg[0]_0\
);
ipif_glbl_irpt_enable_reg_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(9),
I1 => p_9_in,
I2 => \^ip_irpt_enable_reg_reg[0]\,
I3 => p_0_in(0),
O => ipif_glbl_irpt_enable_reg_reg
);
irpt_rdack_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => p_9_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => p_6_in,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => irpt_rdack
);
irpt_wrack_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00FE"
)
port map (
I0 => p_9_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => p_6_in,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => irpt_wrack
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_read,
I5 => ip2bus_rdack_i_D1,
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_write_reg,
I5 => ip2bus_wrack_i_D1,
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_gpio_1_0_cdc_sync is
port (
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
scndry_vect_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_gpio_1_0_cdc_sync : entity is "cdc_sync";
end zqynq_lab_1_design_axi_gpio_1_0_cdc_sync;
architecture STRUCTURE of zqynq_lab_1_design_axi_gpio_1_0_cdc_sync is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_4 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d2_4 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
signal s_level_out_bus_d3_4 : STD_LOGIC;
signal \^scndry_vect_out\ : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
scndry_vect_out(4 downto 0) <= \^scndry_vect_out\(4 downto 0);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_4,
Q => s_level_out_bus_d2_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_4,
Q => s_level_out_bus_d3_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => \^scndry_vect_out\(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => \^scndry_vect_out\(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => \^scndry_vect_out\(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => \^scndry_vect_out\(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_4,
Q => \^scndry_vect_out\(4),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(4),
Q => s_level_out_bus_d1_cdc_to_4,
R => '0'
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => \^scndry_vect_out\(4),
O => D(4)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => \^scndry_vect_out\(3),
O => D(3)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => \^scndry_vect_out\(2),
O => D(2)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => \^scndry_vect_out\(1),
O => D(1)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => \^scndry_vect_out\(0),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_gpio_1_0_interrupt_control is
port (
irpt_wrack_d1 : out STD_LOGIC;
p_3_in : out STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
p_0_in : out STD_LOGIC_VECTOR ( 0 to 0 );
IP2INTC_Irpt_i : out STD_LOGIC;
ip2bus_wrack_i : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
bus2ip_reset : in STD_LOGIC;
irpt_wrack : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
GPIO_intr : in STD_LOGIC;
interrupt_wrce_strb : in STD_LOGIC;
irpt_rdack : in STD_LOGIC;
intr2bus_rdack0 : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ : in STD_LOGIC;
p_8_in : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole : in STD_LOGIC;
bus2ip_rnw : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_gpio_1_0_interrupt_control : entity is "interrupt_control";
end zqynq_lab_1_design_axi_gpio_1_0_interrupt_control;
architecture STRUCTURE of zqynq_lab_1_design_axi_gpio_1_0_interrupt_control is
signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\ : STD_LOGIC;
signal intr2bus_rdack : STD_LOGIC;
signal intr2bus_wrack : STD_LOGIC;
signal irpt_dly1 : STD_LOGIC;
signal irpt_dly2 : STD_LOGIC;
signal \^irpt_wrack_d1\ : STD_LOGIC;
signal \^p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^p_1_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^p_3_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
irpt_wrack_d1 <= \^irpt_wrack_d1\;
p_0_in(0) <= \^p_0_in\(0);
p_1_in(0) <= \^p_1_in\(0);
p_3_in(0) <= \^p_3_in\(0);
\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_intr,
Q => irpt_dly1,
S => bus2ip_reset
);
\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_dly1,
Q => irpt_dly2,
S => bus2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4F4F4F44FF4F4F4"
)
port map (
I0 => irpt_dly2,
I1 => irpt_dly1,
I2 => \^p_3_in\(0),
I3 => p_8_in,
I4 => s_axi_wdata(0),
I5 => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\,
O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^irpt_wrack_d1\,
I1 => Bus_RNW_reg,
O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\,
Q => \^p_3_in\(0),
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2intc_irpt_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^p_3_in\(0),
I1 => \^p_1_in\(0),
I2 => \^p_0_in\(0),
O => IP2INTC_Irpt_i
);
intr2bus_rdack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr2bus_rdack0,
Q => intr2bus_rdack,
R => bus2ip_reset
);
intr2bus_wrack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => interrupt_wrce_strb,
Q => intr2bus_wrack,
R => bus2ip_reset
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FEEE"
)
port map (
I0 => ip2Bus_RdAck_intr_reg_hole,
I1 => intr2bus_rdack,
I2 => bus2ip_rnw,
I3 => GPIO_xferAck_i,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"EFEE"
)
port map (
I0 => ip2Bus_WrAck_intr_reg_hole,
I1 => intr2bus_wrack,
I2 => bus2ip_rnw,
I3 => GPIO_xferAck_i,
O => ip2bus_wrack_i
);
\ip_irpt_enable_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\,
Q => \^p_1_in\(0),
R => bus2ip_reset
);
ipif_glbl_irpt_enable_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\,
Q => \^p_0_in\(0),
R => bus2ip_reset
);
irpt_rdack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_rdack,
Q => irpt_rdack_d1,
R => bus2ip_reset
);
irpt_wrack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_wrack,
Q => \^irpt_wrack_d1\,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_gpio_1_0_GPIO_Core is
port (
ip2bus_data : out STD_LOGIC_VECTOR ( 4 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
GPIO_intr : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 4 downto 0 );
Read_Reg_Rst : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[4]_0\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[3]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[2]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[1]_0\ : in STD_LOGIC;
GPIO_DBus_i : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_reset : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC_VECTOR ( 0 to 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 4 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_gpio_1_0_GPIO_Core : entity is "GPIO_Core";
end zqynq_lab_1_design_axi_gpio_1_0_GPIO_Core;
architecture STRUCTURE of zqynq_lab_1_design_axi_gpio_1_0_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[4]\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal gpio_data_in_xor : STD_LOGIC_VECTOR ( 0 to 4 );
signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 4 );
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
signal or_ints : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
Q(4 downto 0) <= \^q\(4 downto 0);
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus_i(0),
Q => ip2bus_data(4),
R => Read_Reg_Rst
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[1]_0\,
Q => ip2bus_data(3),
R => Read_Reg_Rst
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[2]_0\,
Q => ip2bus_data(2),
R => Read_Reg_Rst
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[3]_0\,
Q => ip2bus_data(1),
R => Read_Reg_Rst
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[4]_0\,
Q => ip2bus_data(0),
R => Read_Reg_Rst
);
\Not_Dual.GEN_INTERRUPT.GPIO_intr_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => or_ints,
Q => GPIO_intr,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(0),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(1),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(2),
Q => p_1_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(3),
Q => p_2_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(4),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[4]\,
R => bus2ip_reset
);
\Not_Dual.INPUT_DOUBLE_REGS3\: entity work.zqynq_lab_1_design_axi_gpio_1_0_cdc_sync
port map (
D(4) => gpio_data_in_xor(0),
D(3) => gpio_data_in_xor(1),
D(2) => gpio_data_in_xor(2),
D(1) => gpio_data_in_xor(3),
D(0) => gpio_data_in_xor(4),
Q(4 downto 0) => \^q\(4 downto 0),
gpio_io_i(4 downto 0) => gpio_io_i(4 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(4) => gpio_io_i_d2(0),
scndry_vect_out(3) => gpio_io_i_d2(1),
scndry_vect_out(2) => gpio_io_i_d2(2),
scndry_vect_out(1) => gpio_io_i_d2(3),
scndry_vect_out(0) => gpio_io_i_d2(4)
);
\Not_Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(0),
Q => \^q\(4),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(1),
Q => \^q\(3),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(2),
Q => \^q\(2),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(3),
Q => \^q\(1),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(4),
Q => \^q\(0),
R => '0'
);
\Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(4),
Q => gpio_io_o(4),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(3),
Q => gpio_io_o(3),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(2),
Q => gpio_io_o(2),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(1),
Q => gpio_io_o(1),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(0),
Q => gpio_io_o(0),
R => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(4),
Q => gpio_io_t(4),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(3),
Q => gpio_io_t(3),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(2),
Q => gpio_io_t(2),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(1),
Q => gpio_io_t(1),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(0),
Q => gpio_io_t(0),
S => bus2ip_reset
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => bus2ip_reset
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => \^gpio_xferack_reg\,
I1 => \^gpio_xferack_i\,
I2 => bus2ip_cs(0),
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => bus2ip_reset
);
or_reduce: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => p_1_in,
I1 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[4]\,
I2 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\,
I3 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\,
I4 => p_2_in,
O => or_ints
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_gpio_1_0_slave_attachment is
port (
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[4]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
Read_Reg_Rst : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]_0\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 5 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
\ip2bus_data_i_D1_reg[0]_1\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_gpio_1_0_slave_attachment : entity is "slave_attachment";
end zqynq_lab_1_design_axi_gpio_1_0_slave_attachment;
architecture STRUCTURE of zqynq_lab_1_design_axi_gpio_1_0_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^not_dual.gpio_oe_reg[0]\ : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 );
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal \p_0_out__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 8 downto 2 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \bus2ip_addr_i[4]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair4";
begin
\Not_Dual.gpio_OE_reg[0]\ <= \^not_dual.gpio_oe_reg[0]\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(1),
I1 => state(0),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.zqynq_lab_1_design_axi_gpio_1_0_address_decoder
port map (
D(4 downto 0) => D(4 downto 0),
E(0) => E(0),
GPIO_DBus_i(0) => GPIO_DBus_i(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\,
\Not_Dual.gpio_Data_In_reg[0]\(4 downto 0) => Q(4 downto 0),
\Not_Dual.gpio_Data_Out_reg[0]\(0) => \Not_Dual.gpio_Data_Out_reg[0]\(0),
\Not_Dual.gpio_Data_Out_reg[4]\ => \Not_Dual.gpio_Data_Out_reg[4]\,
Q(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
Read_Reg_Rst => Read_Reg_Rst,
\bus2ip_addr_i_reg[8]\(6) => bus2ip_addr(0),
\bus2ip_addr_i_reg[8]\(5) => bus2ip_addr(1),
\bus2ip_addr_i_reg[8]\(4) => bus2ip_addr(2),
\bus2ip_addr_i_reg[8]\(3) => bus2ip_addr(3),
\bus2ip_addr_i_reg[8]\(2) => bus2ip_addr(4),
\bus2ip_addr_i_reg[8]\(1) => bus2ip_addr(5),
\bus2ip_addr_i_reg[8]\(0) => bus2ip_addr(6),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw_i_reg => \^not_dual.gpio_oe_reg[0]\,
gpio_io_t(4 downto 0) => gpio_io_t(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_data(0) => ip2bus_data(0),
\ip2bus_data_i_D1_reg[0]\ => \ip2bus_data_i_D1_reg[0]\,
\ip2bus_data_i_D1_reg[0]_0\(1 downto 0) => \ip2bus_data_i_D1_reg[0]_0\(1 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => \ip_irpt_enable_reg_reg[0]\,
\ip_irpt_enable_reg_reg[0]_0\ => \ip_irpt_enable_reg_reg[0]_0\,
ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
p_0_in(0) => p_0_in(0),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0),
s_axi_wready => \^s_axi_wready\,
start2 => start2
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(0),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(0),
O => \p_1_in__0\(2)
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(1),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(1),
O => \p_1_in__0\(3)
);
\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(2),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(2),
O => \p_1_in__0\(4)
);
\bus2ip_addr_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(3),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(3),
O => \p_1_in__0\(5)
);
\bus2ip_addr_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(4),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(4),
O => \p_1_in__0\(6)
);
\bus2ip_addr_i[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(5),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(5),
O => \p_1_in__0\(7)
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(6),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(6),
O => \p_1_in__0\(8)
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(2),
Q => bus2ip_addr(6),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(3),
Q => bus2ip_addr(5),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(4),
Q => bus2ip_addr(4),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(5),
Q => bus2ip_addr(3),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(6),
Q => bus2ip_addr(2),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(7),
Q => bus2ip_addr(1),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(8),
Q => bus2ip_addr(0),
R => bus2ip_reset
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => s_axi_arvalid,
I1 => state(0),
I2 => state(1),
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => bus2ip_rnw_i06_out,
Q => \^not_dual.gpio_oe_reg[0]\,
R => bus2ip_reset
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state[1]_i_2_n_0\,
I2 => state(1),
I3 => state(0),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => bus2ip_reset
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1000FFFF10000000"
)
port map (
I0 => state(1),
I1 => s_axi_arvalid,
I2 => s_axi_wvalid,
I3 => s_axi_awvalid,
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
I4 => state(1),
I5 => state(0),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => bus2ip_reset
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => bus2ip_reset
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(0),
Q => s_axi_rdata(0),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(1),
Q => s_axi_rdata(1),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(2),
Q => s_axi_rdata(2),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(5),
Q => s_axi_rdata(5),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(3),
Q => s_axi_rdata(3),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(4),
Q => s_axi_rdata(4),
R => bus2ip_reset
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => bus2ip_reset
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(0),
I4 => state(1),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => bus2ip_reset
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FFFAACC"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_arvalid,
I2 => \state[1]_i_2_n_0\,
I3 => state(1),
I4 => state(0),
O => \p_0_out__0\(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2E2E2E2ECCCCFFCC"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(1),
I2 => \state[1]_i_2_n_0\,
I3 => \state[1]_i_3_n_0\,
I4 => s_axi_arvalid,
I5 => state(0),
O => \p_0_out__0\(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \p_0_out__0\(0),
Q => state(0),
R => bus2ip_reset
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \p_0_out__0\(1),
Q => state(1),
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_gpio_1_0_axi_lite_ipif is
port (
p_8_in : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
Read_Reg_Rst : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 5 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
\ip2bus_data_i_D1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_gpio_1_0_axi_lite_ipif : entity is "axi_lite_ipif";
end zqynq_lab_1_design_axi_gpio_1_0_axi_lite_ipif;
architecture STRUCTURE of zqynq_lab_1_design_axi_gpio_1_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.zqynq_lab_1_design_axi_gpio_1_0_slave_attachment
port map (
D(4 downto 0) => D(4 downto 0),
E(0) => E(0),
GPIO_DBus_i(0) => GPIO_DBus_i(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\,
\Not_Dual.gpio_Data_Out_reg[0]\(0) => \Not_Dual.gpio_Data_Out_reg[0]\(0),
\Not_Dual.gpio_Data_Out_reg[4]\ => bus2ip_cs(0),
\Not_Dual.gpio_OE_reg[0]\ => bus2ip_rnw,
Q(4 downto 0) => Q(4 downto 0),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_reset => bus2ip_reset,
gpio_io_t(4 downto 0) => gpio_io_t(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_data(0) => ip2bus_data(0),
\ip2bus_data_i_D1_reg[0]\ => p_8_in,
\ip2bus_data_i_D1_reg[0]_0\(1 downto 0) => \ip2bus_data_i_D1_reg[0]\(1 downto 0),
\ip2bus_data_i_D1_reg[0]_1\(5 downto 0) => \ip2bus_data_i_D1_reg[0]_0\(5 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => Bus_RNW_reg,
\ip_irpt_enable_reg_reg[0]_0\ => \ip_irpt_enable_reg_reg[0]\,
ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(0),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(6 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(6 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(5 downto 0) => s_axi_rdata(5 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_gpio_1_0_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of zqynq_lab_1_design_axi_gpio_1_0_axi_gpio : entity is 1;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of zqynq_lab_1_design_axi_gpio_1_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of zqynq_lab_1_design_axi_gpio_1_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of zqynq_lab_1_design_axi_gpio_1_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of zqynq_lab_1_design_axi_gpio_1_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of zqynq_lab_1_design_axi_gpio_1_0_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of zqynq_lab_1_design_axi_gpio_1_0_axi_gpio : entity is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of zqynq_lab_1_design_axi_gpio_1_0_axi_gpio : entity is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of zqynq_lab_1_design_axi_gpio_1_0_axi_gpio : entity is 5;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of zqynq_lab_1_design_axi_gpio_1_0_axi_gpio : entity is 1;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of zqynq_lab_1_design_axi_gpio_1_0_axi_gpio : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of zqynq_lab_1_design_axi_gpio_1_0_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of zqynq_lab_1_design_axi_gpio_1_0_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of zqynq_lab_1_design_axi_gpio_1_0_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of zqynq_lab_1_design_axi_gpio_1_0_axi_gpio : entity is -1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_gpio_1_0_axi_gpio : entity is "axi_gpio";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_gpio_1_0_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of zqynq_lab_1_design_axi_gpio_1_0_axi_gpio : entity is "LOGICORE";
end zqynq_lab_1_design_axi_gpio_1_0_axi_gpio;
architecture STRUCTURE of zqynq_lab_1_design_axi_gpio_1_0_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_14 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_15 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_16 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_18 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_19 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_27 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_29 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_31 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_32 : STD_LOGIC;
signal DBus_Reg : STD_LOGIC_VECTOR ( 0 to 4 );
signal GPIO_DBus_i : STD_LOGIC_VECTOR ( 27 to 27 );
signal GPIO_intr : STD_LOGIC;
signal GPIO_xferAck_i : STD_LOGIC;
signal IP2INTC_Irpt_i : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\ : STD_LOGIC;
signal Read_Reg_Rst : STD_LOGIC;
signal bus2ip_cs : STD_LOGIC_VECTOR ( 1 to 1 );
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_reset_i_1_n_0 : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 4 );
signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal gpio_xferAck_Reg : STD_LOGIC;
signal interrupt_wrce_strb : STD_LOGIC;
signal intr2bus_rdack0 : STD_LOGIC;
signal intr_rd_ce_or_reduce : STD_LOGIC;
signal intr_wr_ce_or_reduce : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole_d1 : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole_d1 : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 27 to 31 );
signal ip2bus_data_i : STD_LOGIC_VECTOR ( 31 to 31 );
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 0 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal irpt_rdack : STD_LOGIC;
signal irpt_rdack_d1 : STD_LOGIC;
signal irpt_wrack : STD_LOGIC;
signal irpt_wrack_d1 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 31 to 31 );
signal p_0_out : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_3_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
attribute sigis : string;
attribute sigis of \INTR_CTRLR_GEN.ip2intc_irpt_reg\ : label is "INTR_LEVEL_HIGH";
begin
gpio2_io_o(31) <= \<const0>\;
gpio2_io_o(30) <= \<const0>\;
gpio2_io_o(29) <= \<const0>\;
gpio2_io_o(28) <= \<const0>\;
gpio2_io_o(27) <= \<const0>\;
gpio2_io_o(26) <= \<const0>\;
gpio2_io_o(25) <= \<const0>\;
gpio2_io_o(24) <= \<const0>\;
gpio2_io_o(23) <= \<const0>\;
gpio2_io_o(22) <= \<const0>\;
gpio2_io_o(21) <= \<const0>\;
gpio2_io_o(20) <= \<const0>\;
gpio2_io_o(19) <= \<const0>\;
gpio2_io_o(18) <= \<const0>\;
gpio2_io_o(17) <= \<const0>\;
gpio2_io_o(16) <= \<const0>\;
gpio2_io_o(15) <= \<const0>\;
gpio2_io_o(14) <= \<const0>\;
gpio2_io_o(13) <= \<const0>\;
gpio2_io_o(12) <= \<const0>\;
gpio2_io_o(11) <= \<const0>\;
gpio2_io_o(10) <= \<const0>\;
gpio2_io_o(9) <= \<const0>\;
gpio2_io_o(8) <= \<const0>\;
gpio2_io_o(7) <= \<const0>\;
gpio2_io_o(6) <= \<const0>\;
gpio2_io_o(5) <= \<const0>\;
gpio2_io_o(4) <= \<const0>\;
gpio2_io_o(3) <= \<const0>\;
gpio2_io_o(2) <= \<const0>\;
gpio2_io_o(1) <= \<const0>\;
gpio2_io_o(0) <= \<const0>\;
gpio2_io_t(31) <= \<const1>\;
gpio2_io_t(30) <= \<const1>\;
gpio2_io_t(29) <= \<const1>\;
gpio2_io_t(28) <= \<const1>\;
gpio2_io_t(27) <= \<const1>\;
gpio2_io_t(26) <= \<const1>\;
gpio2_io_t(25) <= \<const1>\;
gpio2_io_t(24) <= \<const1>\;
gpio2_io_t(23) <= \<const1>\;
gpio2_io_t(22) <= \<const1>\;
gpio2_io_t(21) <= \<const1>\;
gpio2_io_t(20) <= \<const1>\;
gpio2_io_t(19) <= \<const1>\;
gpio2_io_t(18) <= \<const1>\;
gpio2_io_t(17) <= \<const1>\;
gpio2_io_t(16) <= \<const1>\;
gpio2_io_t(15) <= \<const1>\;
gpio2_io_t(14) <= \<const1>\;
gpio2_io_t(13) <= \<const1>\;
gpio2_io_t(12) <= \<const1>\;
gpio2_io_t(11) <= \<const1>\;
gpio2_io_t(10) <= \<const1>\;
gpio2_io_t(9) <= \<const1>\;
gpio2_io_t(8) <= \<const1>\;
gpio2_io_t(7) <= \<const1>\;
gpio2_io_t(6) <= \<const1>\;
gpio2_io_t(5) <= \<const1>\;
gpio2_io_t(4) <= \<const1>\;
gpio2_io_t(3) <= \<const1>\;
gpio2_io_t(2) <= \<const1>\;
gpio2_io_t(1) <= \<const1>\;
gpio2_io_t(0) <= \<const1>\;
gpio_io_t(4 downto 0) <= \^gpio_io_t\(4 downto 0);
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \^s_axi_rdata\(31);
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4 downto 0) <= \^s_axi_rdata\(4 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.zqynq_lab_1_design_axi_gpio_1_0_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
D(4) => DBus_Reg(0),
D(3) => DBus_Reg(1),
D(2) => DBus_Reg(2),
D(1) => DBus_Reg(3),
D(0) => DBus_Reg(4),
E(0) => AXI_LITE_IPIF_I_n_18,
GPIO_DBus_i(0) => GPIO_DBus_i(27),
GPIO_xferAck_i => GPIO_xferAck_i,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => AXI_LITE_IPIF_I_n_27,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => AXI_LITE_IPIF_I_n_29,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ => AXI_LITE_IPIF_I_n_16,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ => AXI_LITE_IPIF_I_n_15,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ => AXI_LITE_IPIF_I_n_14,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ => AXI_LITE_IPIF_I_n_13,
\Not_Dual.gpio_Data_Out_reg[0]\(0) => AXI_LITE_IPIF_I_n_19,
Q(4) => gpio_Data_In(0),
Q(3) => gpio_Data_In(1),
Q(2) => gpio_Data_In(2),
Q(1) => gpio_Data_In(3),
Q(0) => gpio_Data_In(4),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_cs(0) => bus2ip_cs(1),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio_io_t(4 downto 0) => \^gpio_io_t\(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_data(0) => ip2bus_data(31),
\ip2bus_data_i_D1_reg[0]\(1) => p_0_out(0),
\ip2bus_data_i_D1_reg[0]\(0) => ip2bus_data_i(31),
\ip2bus_data_i_D1_reg[0]_0\(5) => ip2bus_data_i_D1(0),
\ip2bus_data_i_D1_reg[0]_0\(4) => ip2bus_data_i_D1(27),
\ip2bus_data_i_D1_reg[0]_0\(3) => ip2bus_data_i_D1(28),
\ip2bus_data_i_D1_reg[0]_0\(2) => ip2bus_data_i_D1(29),
\ip2bus_data_i_D1_reg[0]_0\(1) => ip2bus_data_i_D1(30),
\ip2bus_data_i_D1_reg[0]_0\(0) => ip2bus_data_i_D1(31),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => AXI_LITE_IPIF_I_n_31,
ipif_glbl_irpt_enable_reg_reg => AXI_LITE_IPIF_I_n_32,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(31),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
p_8_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(8 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(8 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(5) => \^s_axi_rdata\(31),
s_axi_rdata(4 downto 0) => \^s_axi_rdata\(4 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(9 downto 5) => s_axi_wdata(31 downto 27),
s_axi_wdata(4 downto 0) => s_axi_wdata(4 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I\: entity work.zqynq_lab_1_design_axi_gpio_1_0_interrupt_control
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ => AXI_LITE_IPIF_I_n_32,
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\ => AXI_LITE_IPIF_I_n_31,
GPIO_intr => GPIO_intr,
GPIO_xferAck_i => GPIO_xferAck_i,
IP2INTC_Irpt_i => IP2INTC_Irpt_i,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
ip2Bus_RdAck_intr_reg_hole => ip2Bus_RdAck_intr_reg_hole,
ip2Bus_WrAck_intr_reg_hole => ip2Bus_WrAck_intr_reg_hole,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i => ip2bus_wrack_i,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(31),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
p_8_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(0) => s_axi_wdata(0)
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_rd_ce_or_reduce,
Q => ip2Bus_RdAck_intr_reg_hole_d1,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_LITE_IPIF_I_n_27,
Q => ip2Bus_RdAck_intr_reg_hole,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_wr_ce_or_reduce,
Q => ip2Bus_WrAck_intr_reg_hole_d1,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_LITE_IPIF_I_n_29,
Q => ip2Bus_WrAck_intr_reg_hole,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2intc_irpt_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => IP2INTC_Irpt_i,
Q => ip2intc_irpt,
R => bus2ip_reset
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
bus2ip_reset_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => bus2ip_reset_i_1_n_0
);
bus2ip_reset_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_reset_i_1_n_0,
Q => bus2ip_reset,
R => '0'
);
gpio_core_1: entity work.zqynq_lab_1_design_axi_gpio_1_0_GPIO_Core
port map (
D(4) => DBus_Reg(0),
D(3) => DBus_Reg(1),
D(2) => DBus_Reg(2),
D(1) => DBus_Reg(3),
D(0) => DBus_Reg(4),
E(0) => AXI_LITE_IPIF_I_n_19,
GPIO_DBus_i(0) => GPIO_DBus_i(27),
GPIO_intr => GPIO_intr,
GPIO_xferAck_i => GPIO_xferAck_i,
\Not_Dual.gpio_OE_reg[1]_0\ => AXI_LITE_IPIF_I_n_16,
\Not_Dual.gpio_OE_reg[2]_0\ => AXI_LITE_IPIF_I_n_15,
\Not_Dual.gpio_OE_reg[3]_0\ => AXI_LITE_IPIF_I_n_14,
\Not_Dual.gpio_OE_reg[4]_0\ => AXI_LITE_IPIF_I_n_13,
Q(4) => gpio_Data_In(0),
Q(3) => gpio_Data_In(1),
Q(2) => gpio_Data_In(2),
Q(1) => gpio_Data_In(3),
Q(0) => gpio_Data_In(4),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_cs(0) => bus2ip_cs(1),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw_i_reg(0) => AXI_LITE_IPIF_I_n_18,
gpio_io_i(4 downto 0) => gpio_io_i(4 downto 0),
gpio_io_o(4 downto 0) => gpio_io_o(4 downto 0),
gpio_io_t(4 downto 0) => \^gpio_io_t\(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_data(4) => ip2bus_data(27),
ip2bus_data(3) => ip2bus_data(28),
ip2bus_data(2) => ip2bus_data(29),
ip2bus_data(1) => ip2bus_data(30),
ip2bus_data(0) => ip2bus_data(31),
s_axi_aclk => s_axi_aclk
);
\ip2bus_data_i_D1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(0),
Q => ip2bus_data_i_D1(0),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(27),
Q => ip2bus_data_i_D1(27),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(28),
Q => ip2bus_data_i_D1(28),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(29),
Q => ip2bus_data_i_D1(29),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_i(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_wrack_i,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_gpio_1_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zqynq_lab_1_design_axi_gpio_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_axi_gpio_1_0 : entity is "zqynq_lab_1_design_axi_gpio_1_0,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_gpio_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of zqynq_lab_1_design_axi_gpio_1_0 : entity is "axi_gpio,Vivado 2017.2";
end zqynq_lab_1_design_axi_gpio_1_0;
architecture STRUCTURE of zqynq_lab_1_design_axi_gpio_1_0 is
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_gpio_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 1;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 5;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 1;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
begin
U0: entity work.zqynq_lab_1_design_axi_gpio_1_0_axi_gpio
port map (
gpio2_io_i(31 downto 0) => B"00000000000000000000000000000000",
gpio2_io_o(31 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(31 downto 0),
gpio2_io_t(31 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(31 downto 0),
gpio_io_i(4 downto 0) => gpio_io_i(4 downto 0),
gpio_io_o(4 downto 0) => NLW_U0_gpio_io_o_UNCONNECTED(4 downto 0),
gpio_io_t(4 downto 0) => NLW_U0_gpio_io_t_UNCONNECTED(4 downto 0),
ip2intc_irpt => ip2intc_irpt,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | d47407492a4e5eabed21cf39f97584cb | 0.578195 | 2.557677 | false | false | false | false |
offox/offox-fpga-projects | digital-watch/clock_divisor.vhd | 1 | 810 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clock_divisor is
Port (
clk_in : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out: out STD_LOGIC
);
end clock_divisor;
architecture behavioral of clock_divisor is
signal temporal: STD_LOGIC;
signal counter : integer range 0 to 833333 := 0;
begin
frequency_divider: process (reset, clk_in) begin
if (reset = '1') then
temporal <= '0';
counter <= 0;
elsif rising_edge(clk_in) then
if (counter = 833333) then
temporal <= NOT(temporal);
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= temporal;
end behavioral; | gpl-2.0 | 60a670806bb7fe5d89363587e6950a03 | 0.520988 | 4.111675 | false | false | false | false |
eamadio/fpgaMSP430 | fmsp430/core/fmsp_execution_unit.vhd | 1 | 25,135 | ------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_execution_unit.vhd
--!
--! @brief fpgaMSP430 Execution unit
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fmsp_core_package.all;
use work.fmsp_functions.all;
entity fmsp_execution_unit is
port (
mclk : in std_logic; --! Main system clock
mrst : in std_logic; --! Main system reset
--! INPUTs
dbg_halt_st : in std_logic; --! Halt/Run status from CPU
dbg_mem_dout : in std_logic_vector(15 downto 0); --! Debug unit data output
dbg_reg_wr : in std_logic; --! Debug unit CPU register write
e_state : in std_logic_vector(3 downto 0); --! Execution state
exec_done : in std_logic; --! Execution completed
inst_ad : in std_logic_vector(7 downto 0); --! Decoded Inst: destination addressing mode
inst_as : in std_logic_vector(7 downto 0); --! Decoded Inst: source addressing mode
inst_alu : in std_logic_vector(11 downto 0); --! ALU control signals
inst_bw : in std_logic; --! Decoded Inst: byte width
inst_dest : in std_logic_vector(15 downto 0); --! Decoded Inst: destination (one hot)
inst_dext : in std_logic_vector(15 downto 0); --! Decoded Inst: destination extended instruction word
inst_irq_rst : in std_logic; --! Decoded Inst: reset interrupt
inst_jmp : in std_logic_vector(7 downto 0); --! Decoded Inst: Conditional jump
inst_mov : in std_logic; --! Decoded Inst: mov instruction
inst_sext : in std_logic_vector(15 downto 0); --! Decoded Inst: source extended instruction word
inst_so : in std_logic_vector(7 downto 0); --! Decoded Inst: Single-operand arithmetic
inst_src : in std_logic_vector(15 downto 0); --! Decoded Inst: source (one hot)
inst_type : in std_logic_vector(2 downto 0); --! Decoded Instruction type
mdb_in : in std_logic_vector(15 downto 0); --! Memory data bus input
pc : in std_logic_vector(15 downto 0); --! Program counter
pc_nxt : in std_logic_vector(15 downto 0); --! Next d.pc value (for CALL & IRQ)
--! OUTPUTs
cpuoff : out std_logic; --! Turns off the CPU
dbg_reg_din : out std_logic_vector(15 downto 0); --! Debug unit CPU register data input
gie : out std_logic; --! General interrupt enable
mab : out std_logic_vector(15 downto 0); --! Memory address bus
mb_en : out std_logic; --! Memory bus enable
mb_wr : out std_logic_vector(1 downto 0); --! Memory bus write transfer
mdb_out : out std_logic_vector(15 downto 0); --! Memory data bus output
oscoff : out std_logic; --! Turns off LFXT1 clock input
pc_sw : out std_logic_vector(15 downto 0); --! Program counter software value
pc_sw_wr : out std_logic; --! Program counter software write
scg0 : out std_logic; --! System clock generator 1. Turns off te DCO
scg1 : out std_logic --! System clock generator 1. Turns off the SMCLK
);
end entity fmsp_execution_unit;
architecture RTL of fmsp_execution_unit is
type fmsp_execution_unit_in_type is record
dbg_halt_st : std_logic; --! Halt/Run status from CPU
dbg_mem_dout : std_logic_vector(15 downto 0); --! Debug unit data output
dbg_reg_wr : std_logic; --! Debug unit CPU register write
e_state : std_logic_vector(3 downto 0); --! Execution state
exec_done : std_logic; --! Execution completed
inst_ad : std_logic_vector(7 downto 0); --! Decoded Inst: destination addressing mode
inst_as : std_logic_vector(7 downto 0); --! Decoded Inst: source addressing mode
inst_alu : std_logic_vector(11 downto 0); --! ALU control signals
inst_bw : std_logic; --! Decoded Inst: byte width
inst_dest : std_logic_vector(15 downto 0); --! Decoded Inst: destination (one hot)
inst_dext : std_logic_vector(15 downto 0); --! Decoded Inst: destination extended instruction word
inst_irq_rst : std_logic; --! Decoded Inst: reset interrupt
inst_jmp : std_logic_vector(7 downto 0); --! Decoded Inst: Conditional jump
inst_mov : std_logic; --! Decoded Inst: mov instruction
inst_sext : std_logic_vector(15 downto 0); --! Decoded Inst: source extended instruction word
inst_so : std_logic_vector(7 downto 0); --! Decoded Inst: Single-operand arithmetic
inst_src : std_logic_vector(15 downto 0); --! Decoded Inst: source (one hot)
inst_type : std_logic_vector(2 downto 0); --! Decoded Instruction type
mdb_in : std_logic_vector(15 downto 0); --! Memory data bus input
pc : std_logic_vector(15 downto 0); --! Program counter
pc_nxt : std_logic_vector(15 downto 0); --! Next pc value (for CALL & IRQ)
reg_dest : std_logic_vector(15 downto 0);
reg_src : std_logic_vector(15 downto 0);
alu_stat : std_logic_vector(3 downto 0);
alu_stat_wr : std_logic_vector(3 downto 0);
alu_out : std_logic_vector(15 downto 0);
alu_out_add : std_logic_vector(15 downto 0);
end record;
type reg_type is record
mdb_out_nxt : std_logic_vector(15 downto 0); --! Memory data bus output
mab_lsb : std_logic; --! Format memory data bus input depending on BW
mdb_in_buf_en : std_logic; --! Memory data bus input buffer (buffer after a source read)
mdb_in_buf_valid : std_logic;
mdb_in_buf : std_logic_vector(15 downto 0);
end record;
signal d : fmsp_execution_unit_in_type;
signal r : reg_type := ( mdb_out_nxt => x"0000", --! Memory data bus output
mab_lsb => '0',--! Format memory data bus input depending on BW
mdb_in_buf_en => '0',--! Memory data bus input buffer (buffer after a source read)
mdb_in_buf_valid => '0',
mdb_in_buf => x"0000"
);
signal rin : reg_type;
signal reg_dest_wr : std_logic;
signal reg_sp_wr : std_logic;
signal reg_sr_wr : std_logic;
signal reg_sr_clr : std_logic;
signal reg_pc_call : std_logic;
signal reg_incr : std_logic;
signal exec_cycle : std_logic;
signal status : std_logic_vector(3 downto 0);
signal op_dst : std_logic_vector(15 downto 0);
signal op_src : std_logic_vector(15 downto 0);
begin
d.dbg_halt_st <= dbg_halt_st;
d.dbg_mem_dout <= dbg_mem_dout;
d.dbg_reg_wr <= dbg_reg_wr;
d.e_state <= e_state;
d.exec_done <= exec_done;
d.inst_ad <= inst_ad;
d.inst_as <= inst_as;
d.inst_alu <= inst_alu;
d.inst_bw <= inst_bw;
d.inst_dest <= inst_dest;
d.inst_dext <= inst_dext;
d.inst_irq_rst <= inst_irq_rst;
d.inst_jmp <= inst_jmp;
d.inst_mov <= inst_mov;
d.inst_sext <= inst_sext;
d.inst_so <= inst_so;
d.inst_src <= inst_src;
d.inst_type <= inst_type;
d.mdb_in <= mdb_in;
d.pc <= pc;
d.pc_nxt <= pc_nxt;
COMB : process (all)
variable v : reg_type;
variable v_alu_stat : std_logic_vector(3 downto 0);
variable v_alu_stat_wr : std_logic_vector(3 downto 0);
variable v_op_dst : std_logic_vector(15 downto 0);
variable v_op_src : std_logic_vector(15 downto 0);
variable v_status : std_logic_vector(3 downto 0);
variable v_reg_dest_wr : std_logic;
variable v_reg_sp_wr : std_logic;
variable v_reg_sr_wr : std_logic;
variable v_reg_sr_clr : std_logic;
variable v_reg_pc_call : std_logic;
variable v_reg_incr : std_logic;
variable v_dbg_reg_din : std_logic_vector(15 downto 0);
variable v_src_reg_src_sel : std_logic;
variable v_src_reg_dest_sel : std_logic;
variable v_src_mdb_in_val_sel : std_logic;
variable v_src_inst_dext_sel : std_logic;
variable v_src_inst_sext_sel : std_logic;
variable v_dst_inst_sext_sel : std_logic;
variable v_dst_mdb_in_bw_sel : std_logic;
variable v_dst_fffe_sel : std_logic;
variable v_dst_reg_dest_sel : std_logic;
variable v_exec_cycle : std_logic;
--! Detect memory read/write access
variable v_mb_wr_det : std_logic;
variable v_mb_rd_det : std_logic;
variable v_mb_en : std_logic;
variable v_mb_wr_msk : std_logic_vector(1 downto 0);
variable v_mb_wr : std_logic_vector(1 downto 0);
--! Memory address bus
variable v_mab : std_logic_vector(15 downto 0);
variable v_mdb_out : std_logic_vector(15 downto 0);
variable v_mdb_in_bw : std_logic_vector(15 downto 0);
variable v_mdb_in_val : std_logic_vector(15 downto 0);
begin
--! default assignment
v := r;
--! overriding assignments
--=============================================================================
--! 2) REGISTER FILE
--=============================================================================
if ( ((d.e_state = E_EXEC) and (
((d.inst_type(C_INST_TO) = '1') and (d.inst_ad(C_DIR) = '1') and not (d.inst_alu(C_EXEC_NO_WR) = '1')) or
((d.inst_type(C_INST_SO) = '1') and (d.inst_as(C_DIR) = '1') and not ((d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') or (d.inst_so(C_RETI) = '1') )) or
(d.inst_type(C_INST_JMP) = '1'))) or (d.dbg_reg_wr = '1') ) then
v_reg_dest_wr := '1';
else
v_reg_dest_wr:= '0';
end if;
if ( ( ( (d.e_state = E_IRQ_1)
or (d.e_state = E_IRQ_3) )
and (not(d.inst_irq_rst) = '1') )
or ( (d.e_state = E_DST_RD)
and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') )
and (not(d.inst_as(C_IDX)) = '1')
and not( ( (d.inst_as(C_INDIR) = '1') or (d.inst_as(C_INDIR_I) = '1') ) and (d.inst_src(1) = '1') ) )
or ( (d.e_state = E_SRC_AD)
and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') )
and (d.inst_as(C_IDX) = '1') )
or ( (d.e_state = E_SRC_RD)
and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') )
and ( ((d.inst_as(C_INDIR) = '1') or (d.inst_as(C_INDIR_I) = '1')) and (d.inst_src(1) = '1') ) ) ) then
v_reg_sp_wr := '1';
else
v_reg_sp_wr := '0';
end if;
if ( (d.e_state = E_DST_RD) and (d.inst_so(C_RETI) = '1') ) then
v_reg_sr_wr := '1';
else
v_reg_sr_wr := '0';
end if;
if ( (d.e_state = E_IRQ_2) ) then
v_reg_sr_clr := '1';
else
v_reg_sr_clr := '0';
end if;
if ( ((d.e_state = E_EXEC) and (d.inst_so(C_CALL) = '1')) or
((d.e_state = E_DST_WR) and (d.inst_so(C_RETI) = '1')) ) then
v_reg_pc_call := '1';
else
v_reg_pc_call := '0';
end if;
if ( ((d.exec_done = '1') and (d.inst_as(C_INDIR_I) = '1')) or
((d.e_state = E_SRC_RD) and (d.inst_so(C_RETI) = '1')) or
((d.e_state = E_EXEC) and (d.inst_so(C_RETI) = '1')) ) then
v_reg_incr := '1';
else
v_reg_incr := '0';
end if;
v_dbg_reg_din := d.reg_dest;
--=============================================================================
--! 3) SOURCE OPERAND MUXING
--=============================================================================
--! d.inst_as(C_DIR) = '1') : Register direct. -> Source is in register
--! d.inst_as(C_IDX) = '1') : Register indexed. -> Source is in memory, address is register+offset
--! d.inst_as(C_INDIR) = '1') : Register indirect.
--! d.inst_as(C_INDIR_I) = '1'): Register indirect autoincrement.
--! d.inst_as(C_SYMB) = '1') : Symbolic (operand is in memory at address d.pc+x).
--! d.inst_as(C_IMM) = '1') : Immediate (operand is next word in the instruction stream).
--! d.inst_as(C_ABS) = '1') : Absolute (operand is in memory at address x).
--! d.inst_as(C_CONST) = '1') : Constant.
if ( ( (d.e_state = E_IRQ_0) or (d.e_state = E_IRQ_2) )
or ( (d.e_state = E_SRC_RD) and not(d.inst_as(C_ABS) = '1') )
or ( (d.e_state = E_SRC_WR) and not(d.inst_as(C_ABS) = '1') )
or ( (d.e_state = E_EXEC) and (d.inst_as(C_DIR) = '1') and not(d.inst_type(C_INST_JMP) = '1') ) ) then
v_src_reg_src_sel := '1';
else
v_src_reg_src_sel := '0';
end if;
if ( ( (d.e_state = E_IRQ_1) or (d.e_state = E_IRQ_3) )
or ( (d.e_state = E_DST_RD) and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') ) )
or ( (d.e_state = E_SRC_AD) and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') ) and (d.inst_as(C_IDX) = '1') ) ) then
v_src_reg_dest_sel := '1';
else
v_src_reg_dest_sel := '0';
end if;
if ( ( (d.e_state = E_DST_RD) and (d.inst_so(C_RETI) = '1') )
or ( (d.e_state = E_EXEC) and ( (d.inst_as(C_INDIR) = '1') or (d.inst_as(C_INDIR_I) = '1')
or (d.inst_as(C_IDX) = '1') or (d.inst_as(C_SYMB) = '1')
or (d.inst_as(C_ABS) = '1') ) ) ) then
v_src_mdb_in_val_sel := '1';
else
v_src_mdb_in_val_sel := '0';
end if;
if ( ( (d.e_state = E_DST_RD) and not( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') ) )
or ( (d.e_state = E_DST_WR) and not( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1')
or (d.inst_as(C_IDX) = '1') or (d.inst_as(C_SYMB) = '1')
or (d.inst_so(C_RETI) = '1') ) ) ) then
v_src_inst_dext_sel := '1';
else
v_src_inst_dext_sel := '0';
end if;
if ( (d.e_state = E_EXEC) and ( (d.inst_type(C_INST_JMP) = '1') or (d.inst_as(C_IMM) = '1') or (d.inst_as(C_CONST) = '1')
or (d.inst_so(C_RETI) = '1') ) ) then
v_src_inst_sext_sel := '1';
else
v_src_inst_sext_sel := '0';
end if;
if (v_src_reg_src_sel = '1') then
v_op_src := d.reg_src;
elsif (v_src_reg_dest_sel = '1') then
v_op_src := d.reg_dest;
elsif (v_src_mdb_in_val_sel = '1') then
v_op_src := v_mdb_in_val;
elsif (v_src_inst_dext_sel = '1') then
v_op_src := d.inst_dext;
elsif (v_src_inst_sext_sel = '1') then
v_op_src := d.inst_sext;
else
v_op_src := x"0000";
end if;
--=============================================================================
--! 4) DESTINATION OPERAND MUXING
--=============================================================================
--! d.inst_ad(C_DIR) = '1') : Register direct.
--! d.inst_ad(C_IDX) = '1') : Register indexed.
--! d.inst_ad(C_SYMB) = '1') : Symbolic (operand is in memory at address d.pc+x).
--! d.inst_ad(C_ABS) = '1') : Absolute (operand is in memory at address x).
if ( ( (d.e_state = E_SRC_RD) and ( (d.inst_as(C_IDX) = '1') or (d.inst_as(C_SYMB) = '1')
or (d.inst_as(C_ABS) = '1') ) )
or ( (d.e_state = E_SRC_RD) and ( (d.inst_as(C_IDX) = '1') or (d.inst_as(C_SYMB) = '1')
or (d.inst_as(C_ABS) = '1') ) ) ) then
v_dst_inst_sext_sel := '1';
else
v_dst_inst_sext_sel := '0';
end if;
if ( ( (d.e_state = E_DST_WR) and (d.inst_so(C_RETI) = '1') )
or ( (d.e_state = E_EXEC) and not( (d.inst_ad(C_IDX) = '1') or (d.inst_type(C_INST_JMP) = '1')
or (d.inst_type(C_INST_SO) = '1') ) and not(d.inst_so(C_RETI) = '1') ) ) then
v_dst_mdb_in_bw_sel := '1';
else
v_dst_mdb_in_bw_sel := '0';
end if;
if ( ( (d.e_state = E_IRQ_0) or (d.e_state = E_IRQ_0) or (d.e_state = E_IRQ_3) )
or ( (d.e_state = E_DST_RD) and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') ) and not(d.inst_so(C_RETI) = '1') )
or ( (d.e_state = E_SRC_AD) and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') ) and (d.inst_as(C_IDX) = '1') )
or ( (d.e_state = E_SRC_RD) and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') ) and ( (d.inst_as(C_INDIR) = '1') or (d.inst_as(C_INDIR_I) = '1') ) and (d.inst_src(1) = '1') ) ) then
v_dst_fffe_sel := '1';
else
v_dst_fffe_sel := '0';
end if;
if ( ( (d.e_state = E_DST_RD) and not( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') or (d.inst_ad(C_ABS) = '1') or (d.inst_so(C_RETI) = '1') ) )
or ( (d.e_state = E_DST_WR) and not(d.inst_ad(C_ABS) = '1') )
or ( (d.e_state = E_EXEC) and ( (d.inst_ad(C_DIR) = '1') or (d.inst_type(C_INST_JMP) = '1') or (d.inst_type(C_INST_SO) = '1') ) and not(d.inst_so(C_RETI) = '1') ) ) then
v_dst_reg_dest_sel := '1';
else
v_dst_reg_dest_sel := '0';
end if;
if (d.dbg_halt_st = '1') then
v_op_dst := d.dbg_mem_dout;
elsif (v_dst_inst_sext_sel = '1') then
v_op_dst := d.inst_sext;
elsif (v_dst_mdb_in_bw_sel = '1') then
v_op_dst := v_mdb_in_bw;
elsif (v_dst_reg_dest_sel = '1') then
v_op_dst := d.reg_dest;
elsif (v_dst_fffe_sel = '1') then
v_op_dst := x"FFFE";
else
v_op_dst := x"0000";
end if;
--=============================================================================
--! 5) ALU
--=============================================================================
if (d.e_state = E_EXEC) then
v_exec_cycle := '1';
else
v_exec_cycle := '0';
end if;
--=============================================================================
--! 6) MEMORY INTERFACE
--=============================================================================
--! Detect memory read/write access
if ( ( (d.e_state = E_SRC_RD) and (d.inst_as(C_IMM) = '0') )
or ( (d.e_state = E_EXEC) and (d.inst_so(C_RETI) = '0') )
or ( (d.e_state = E_SRC_RD) and (d.inst_type(C_INST_SO) = '0') and (d.inst_mov = '0') )
) then
v_mb_rd_det := '1';
else
v_mb_rd_det := '0';
end if;
--! Detect memory read/write access
if ( ( (d.e_state = E_IRQ_1) and (not(d.inst_irq_rst) = '0') )
or ( (d.e_state = E_IRQ_3) and (not(d.inst_irq_rst) = '0') )
or ( (d.e_state = E_DST_WR) and (not(d.inst_so(C_RETI)) = '0') )
or (d.e_state = E_SRC_WR) ) then
v_mb_wr_det := '1';
else
v_mb_wr_det := '0';
end if;
if (d.inst_alu(C_EXEC_NO_WR) = '1') then
v_mb_wr_msk := "00";
elsif (d.inst_bw = '0') then
v_mb_wr_msk := "11";
elsif (d.alu_out_add(0) = '1') then
v_mb_wr_msk := "10";
else
v_mb_wr_msk := "01";
end if;
if ( ( (not(d.inst_alu(C_EXEC_NO_WR)) = '1') and (v_mb_wr_det= '1') )
or (v_mb_rd_det= '1')
) then
v_mb_en := '1';
else
v_mb_en := '0';
end if;
if (v_mb_wr_det = '1') then
v_mb_wr := v_mb_wr_msk;
else
v_mb_wr := "00";
end if;
--! Memory address bus
v_mab := d.alu_out_add;
--! Memory data bus output
if (d.e_state = E_DST_RD) then
v.mdb_out_nxt := d.pc_nxt;
elsif ( ( (d.e_state = E_EXEC) and (not(d.inst_so(C_CALL)) = '1') )
or (d.e_state = E_IRQ_0) or (d.e_state = E_IRQ_2) ) then
v.mdb_out_nxt := d.alu_out;
end if;
if (d.inst_bw = '1') then
v_mdb_out := r.mdb_out_nxt(7 downto 0) & r.mdb_out_nxt(7 downto 0);
else
v_mdb_out := r.mdb_out_nxt;
end if;
--! Format memory data bus input depending on BW
if (v_mb_en = '1') then
v.mab_lsb := d.alu_out_add(0);
end if;
if (not(d.inst_bw) = '1') then
v_mdb_in_bw := d.mdb_in;
elsif (r.mab_lsb = '1') then
v_mdb_in_bw := d.mdb_in(15 downto 8) & d.mdb_in(15 downto 8);
else
v_mdb_in_bw := d.mdb_in;
end if;
--! Memory data bus input buffer (buffer after a source read)
if (d.e_state = E_SRC_RD) then
v.mdb_in_buf_en := '1';
else
v.mdb_in_buf_en := '0';
end if;
if (d.e_state = E_EXEC) then
v.mdb_in_buf_valid := '0';
elsif (r.mdb_in_buf_en) then
v.mdb_in_buf_valid := '1';
end if;
if (r.mdb_in_buf_en = '1') then
v.mdb_in_buf := v_mdb_in_bw;
end if;
if (r.mdb_in_buf_valid = '1') then
v_mdb_in_val := r.mdb_in_buf;
else
v_mdb_in_val := v_mdb_in_bw;
end if;
--! drive register inputs
rin <= v;
--! drive module outputs
reg_dest_wr <= v_reg_dest_wr;
reg_sp_wr <= v_reg_sp_wr;
reg_sr_wr <= v_reg_sr_wr;
reg_sr_clr <= v_reg_sr_clr;
reg_pc_call <= v_reg_pc_call;
reg_incr <= v_reg_incr;
exec_cycle <= v_exec_cycle;
-- signal status : std_logic_vector(3 downto 0);
op_dst <= v_op_dst;
op_src <= v_op_src;
--! OUTPUTs
-- cpuoff : out std_logic; --! Turns off the CPU
dbg_reg_din <= v_dbg_reg_din; --! Debug unit CPU register data input
-- gie : out std_logic; --! General interrupt enable
mab <= v_mab; --! Memory address bus
mb_en <= v_mb_en; --! Memory bus enable
mb_wr <= v_mb_wr; --! Memory bus write transfer
mdb_out <= v_mdb_out; --! Memory data bus output
-- oscoff : out std_logic; --! Turns off LFXT1 clock input
-- pc_sw <= v_dbg_reg_di; --! Program counter software value
-- pc_sw_wr <= v_dbg_reg_di; --! Program counter software write
-- scg0 : out std_logic; --! System clock generator 1. Turns off hte DCO
-- scg1 : out std_logic; --! System clock generator 1. Turns off the SMCLK
end process COMB;
REGS : process (mclk,mrst)
begin
if (mrst = '1') then
r <= ( mdb_out_nxt => x"0000", --! Memory data bus output
mab_lsb => '0',--! Format memory data bus input depending on BW
mdb_in_buf_en => '0',--! Memory data bus input buffer (buffer after a source read)
mdb_in_buf_valid => '0',
mdb_in_buf => x"0000"
);
elsif rising_edge(mclk) then
r <= rin;
end if;
end process REGS;
register_file : fmsp_register_file
port map(
mclk => mclk, --! Main system clock
mrst => mrst, --! Main system reset
--! INPUTs
alu_stat => d.alu_stat, --! ALU Status {V,N,Z,C}
alu_stat_wr => d.alu_stat_wr, --! ALU Status write {V,N,Z,C}
inst_bw => d.inst_bw, --! Decoded Inst: byte width
inst_dest => d.inst_dest, --! Register destination selection
inst_src => d.inst_src, --! Register source selection
pc => d.pc, --! Program counter
reg_dest_val => d.alu_out, --! Selected register destination value
reg_dest_wr => reg_dest_wr, --! Write selected register destination
reg_pc_call => reg_pc_call, --! Trigger pc update for a CALL instruction
reg_sp_val => d.alu_out_add, --! Stack Pointer next value
reg_sp_wr => reg_sp_wr, --! Stack Pointer write
reg_sr_clr => reg_sr_clr, --! Status register clear for interrupts
reg_sr_wr => reg_sr_wr, --! Status Register update for RETI instruction
reg_incr => reg_incr, --! Increment source register
--! OUTPUTs
cpuoff => cpuoff, --! Turns off the CPU
gie => gie, --! General interrupt enable
oscoff => oscoff, --! Turns off LFXT1 clock input
pc_sw => pc_sw, --! Program counter software value
pc_sw_wr => pc_sw_wr, --! Program counter software write
reg_dest => d.reg_dest, --! Selected register destination content
reg_src => d.reg_src, --! Selected register source content
scg0 => scg0, --! System clock generator 1. Turns off the DCOK
scg1 => scg1, --! System clock generator 1. Turns off the SMCLK
status => status --! R2 Status {V,N,Z,C}
);
alu : fmsp_alu
port map(
--! INPUTs
dbg_halt_st => d.dbg_halt_st, --! Halt/Run status from CPU
exec_cycle => exec_cycle, --! Instruction execution cycle
inst_alu => d.inst_alu, --! ALU control signals
inst_bw => d.inst_bw, --! Decoded Inst: byte width
inst_jmp => d.inst_jmp, --! Decoded Inst: Conditional jump
inst_so => d.inst_so, --! Single-operand arithmetic
op_dst => op_dst, --! Destination operand
op_src => op_src, --! Source operand
status => status, --! R2 Status {V,N,Z,C}
--! OUTPUTs
alu_out => d.alu_out, --! ALU output value
alu_out_add => d.alu_out_add, --! ALU adder output value
alu_stat => d.alu_stat, --! ALU Status {V,N,Z,C}
alu_stat_wr => d.alu_stat_wr --! ALU Status write {V,N,Z,C}
);
end RTL;
| bsd-3-clause | f0f677b0b8e7b9a1920527a59b33c699 | 0.558345 | 2.526639 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-avnet-xc2v1500/testbench.vhd | 1 | 8,138 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 25; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal errorn : std_logic;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(15 downto 0);
signal xdata : std_logic_vector(31 downto 0);
signal romsn : std_logic;
signal writen, read : std_logic;
signal oen : std_logic;
signal flash_rstn : std_logic;
signal ddr_clk : std_logic_vector(1 downto 0);
signal ddr_clkb : std_logic_vector(1 downto 0);
signal ddr_clk_fb : std_logic;
signal ddr_clk_fb_out : std_logic;
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_web : std_logic; -- ddr write enable
signal ddr_rasb : std_logic; -- ddr ras
signal ddr_casb : std_logic; -- ddr cas
signal ddr_dm : std_logic_vector (7 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (63 downto 0); -- ddr data
signal txd1 : std_logic; -- UART1 tx data
signal rxd1 : std_logic; -- UART1 rx data
signal gpio : std_logic_vector(31 downto 0); -- I/O port
signal flash_cex : std_logic;
signal clk125 : std_logic := '0';
signal GND : std_logic := '0';
signal VCC : std_logic := '1';
signal NC : std_logic := 'Z';
constant lresp : boolean := false;
signal dsuen : std_logic;
signal dsubre : std_logic;
signal dsuact : std_logic;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
rxd1 <= 'H'; errorn <= 'H';
ddr_clk_fb <= ddr_clk_fb_out;
clk125 <= not clk125 after 6.75 ns;
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map ( sys_rst_in, sys_clk, clk125, errorn, flash_rstn, address,
data, dsuen, dsubre, dsuact, oen, writen, read, romsn,
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_clk_fb_out, ddr_cke, ddr_csb,
ddr_web, ddr_rasb, ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
txd1, rxd1,
-- gpio,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66
);
ddrmem : for i in 0 to 1 generate
-- u3 : mt46v16m16
-- generic map (index => 3, fname => sdramfile, bbits => 64)
-- PORT MAP(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
-- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
-- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
-- u2 : mt46v16m16
-- generic map (index => 2, fname => sdramfile, bbits => 64)
-- PORT MAP(
-- Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad,
-- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
-- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(3 downto 2));
-- u1 : mt46v16m16
-- generic map (index => 1, fname => sdramfile, bbits => 64)
-- PORT MAP(
-- Dq => ddr_dq(47 downto 32), Dqs => ddr_dqs(5 downto 4), Addr => ddr_ad,
-- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
-- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(5 downto 4));
-- u0 : mt46v16m16
-- generic map (index => 0, fname => sdramfile, bbits => 64)
-- PORT MAP(
-- Dq => ddr_dq(63 downto 48), Dqs => ddr_dqs(7 downto 6), Addr => ddr_ad,
-- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
-- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(7 downto 6));
ddr0 : ddrram
generic map(width => 64, abits => 13, colbits => 9, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 1)
port map (ck => ddr_clk(i), cke => ddr_cke(i), csn => ddr_csb(i),
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
end generate;
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data,
gnd, gnd, romsn, writen, oen);
iuerr : process
begin
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
xdata <= "0000000000000000" & data;
data <= buskeep(data), (others => 'H') after 250 ns;
ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
end ;
| gpl-2.0 | 4d5be2c69a2ad3aab18bd56a5d158acd | 0.586385 | 3.178906 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-terasic-de2-115/testbench.vhd | 1 | 10,406 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romdepth : integer := 20; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal sma_clkout : std_ulogic;
signal address : std_logic_vector(22 downto 0);
signal data : std_logic_vector(31 downto 24);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic;
signal iosn : std_logic;
signal oen : std_logic;
signal read : std_logic;
signal writen : std_logic;
signal brdyn : std_logic;
signal bexcn : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal test : std_logic;
signal error : std_logic;
signal gpio : std_logic_vector(35 downto 0);
signal GND : std_logic := '0';
signal VCC : std_logic := '1';
signal NC : std_logic := 'Z';
signal clk2 : std_logic := '1';
signal sdcke : std_logic;
signal sdcsn : std_logic;
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal txd1, rxd1 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col : std_logic := '0';
signal eth_gtxclk, erx_crs, etx_en, etx_er : std_logic :='0';
signal eth_macclk : std_logic := '0';
signal erxd, etxd : std_logic_vector(7 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal emdintn : std_logic := '1';
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
signal can_txd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_rxd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_stb : std_logic_vector(0 to CFG_CAN_NUM-1);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1';
dsubre <= '1'; -- inverted on the board
rxd1 <= '1';
can_rxd <= (others => 'H'); bexcn <= '1';
gpio(2 downto 0) <= "LHL";
gpio(CFG_GRGPIO_WIDTH-1 downto 3) <= (others => 'H');
eth_macclk <= not eth_macclk after 4 ns;
ereset <= 'H';
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (rst, clk, sma_clkout, error, address(22 downto 0), data,
sa(12 downto 0), sa(14 downto 13), sd, sdclk, sdcke, sdcsn, sdwen,
sdrasn, sdcasn, sddqm, dsutx, dsurx, dsubre, dsuact,
oen, writen, open, open, romsn, gpio,
emdio, eth_macclk, etx_clk, erx_clk, erxd(3 downto 0), erx_dv, erx_er,
erx_col, erx_crs, emdintn, ereset, etxd(3 downto 0), etx_en, etx_er, emdc,
can_txd, can_rxd, can_stb
);
sd1 : if ((CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 1)) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
writen, oen);
-- sram0 : for i in 0 to (sramwidth/8)-1 generate
-- sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
-- port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
-- rwen(0), ramoen(0));
-- end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map(address => 16)
port map(ereset, emdio, etx_clk, erx_clk, erxd, erx_dv,
erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, eth_macclk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
-- test0 : grtestmod
-- port map ( rst, clk, error, address(21 downto 2), data,
-- iosn, oen, writen, brdyn);
-- data <= buskeep(data), (others => 'H') after 250 ns;
data <= buskeep(data) after 5 ns;
-- sd <= buskeep(sd), (others => 'H') after 250 ns;
sd <= buskeep(sd) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 | 9379fe9e6d0d3b56eb97b5f976453dff | 0.582068 | 3.071429 | false | false | false | false |
quicky2000/top_optim_sharp_driver | testbench/tb_driver_compare.vhd | 1 | 2,345 | --
-- This file is part of top_optim_sharp_driver
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_driver_compare IS
END tb_driver_compare;
ARCHITECTURE behavior OF tb_driver_compare IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT driver_compare
PORT(
clk : IN std_logic;
rst : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 40 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: driver_compare PORT MAP (
clk => clk,
rst => rst
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | f456ac5ef09b5eacd91660cf703c8d33 | 0.659701 | 4.092496 | false | true | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/tech/altera_mf/simprims/altera_mf_components.vhd | 1 | 111,362 | -- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 9.0 Build 235 03/01/2009
----------------------------------------------------------------------------
-- ALtera Megafunction Component Declaration File
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package altera_mf_components is
type altera_mf_logic_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
component lcell
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
component altcam
generic (
width : natural := 1;
widthad : natural := 1;
numwords : natural := 1;
lpm_file : string := "UNUSED";
lpm_filex : string := "UNUSED";
match_mode : string := "MULTIPLE";
output_reg : string := "UNREGISTERED";
output_aclr : string := "ON";
pattern_reg : string := "INCLOCK";
pattern_aclr : string := "ON";
wraddress_aclr : string := "ON";
wrx_reg : string := "INCLOCK";
wrx_aclr : string := "ON";
wrcontrol_aclr : string := "ON";
use_eab : string := "ON";
lpm_hint : string := "UNUSED";
lpm_type : string := "altcam" );
port (
pattern : in std_logic_vector(width-1 downto 0);
wrx : in std_logic_vector(width-1 downto 0) := (others => 'Z');
wrxused : in std_logic := '1';
wrdelete : in std_logic := '0';
wraddress : in std_logic_vector(widthad-1 downto 0);
wren : in std_logic;
inclock : in std_logic;
inclocken : in std_logic := '1';
inaclr : in std_logic := '0';
outclock : in std_logic := '0';
outclocken : in std_logic := '1';
outaclr : in std_logic := '0';
mstart : in std_logic := 'X';
mnext : in std_logic := '0';
maddress : out std_logic_vector(widthad-1 downto 0);
mbits : out std_logic_vector(numwords-1 downto 0);
mfound : out std_logic;
mcount : out std_logic_vector(widthad-1 downto 0);
rdbusy : out std_logic;
wrbusy : out std_logic );
end component;
component altclklock
generic (
inclock_period : natural := 10000; -- units in ps
inclock_settings : string := "UNUSED";
valid_lock_cycles : natural := 5;
invalid_lock_cycles : natural := 5;
valid_lock_multiplier : natural := 5;
invalid_lock_multiplier : natural := 5;
operation_mode : string := "NORMAL";
clock0_boost : natural := 1;
clock0_divide : natural := 1;
clock0_settings : string := "UNUSED";
clock0_time_delay : string := "0";
clock1_boost : natural := 1;
clock1_divide : natural := 1;
clock1_settings : string := "UNUSED";
clock1_time_delay : string := "0";
clock2_boost : natural := 1;
clock2_divide : natural := 1;
clock2_settings : string := "UNUSED";
clock2_time_delay : string := "0";
clock_ext_boost : natural := 1;
clock_ext_divide : natural := 1;
clock_ext_settings : string := "UNUSED";
clock_ext_time_delay : string := "0";
outclock_phase_shift : natural := 0; -- units in ps
intended_device_family : string := "APEX20KE" ;
lpm_hint : string := "UNUSED";
lpm_type : string := "altclklock" );
port(
inclock : in std_logic; -- required port, input reference clock
inclocken : in std_logic := '1'; -- PLL enable signal
fbin : in std_logic := '1'; -- feedback input for the PLL
clock0 : out std_logic; -- clock0 output
clock1 : out std_logic; -- clock1 output
clock2 : out std_logic; -- clock2 output
clock_ext : out std_logic; -- external clock output
locked : out std_logic ); -- PLL lock signal
end component;
component altlvds_rx
generic (
number_of_channels : natural; -- Required parameter
deserialization_factor : natural; -- Required parameter
registered_output : string := "ON";
inclock_period : natural := 10000; -- Required parameter
inclock_boost : natural := 0;
cds_mode : string := "UNUSED";
intended_device_family : string := "APEX20KE";
input_data_rate : natural := 0;
inclock_data_alignment : string := "EDGE_ALIGNED";
registered_data_align_input : string := "ON";
common_rx_tx_pll : string := "ON";
enable_dpa_mode : string := "OFF";
enable_dpa_pll_calibration : string := "OFF";
enable_dpa_calibration : string := "ON";
enable_dpa_fifo : string := "ON";
use_dpll_rawperror : string := "OFF";
use_coreclock_input : string := "OFF";
dpll_lock_count : natural := 0;
dpll_lock_window : natural := 0;
outclock_resource : string := "AUTO";
data_align_rollover : natural := 10;
lose_lock_on_one_change : string := "OFF";
reset_fifo_at_first_lock : string := "ON";
use_external_pll : string := "OFF";
implement_in_les : string := "OFF";
buffer_implementation : string := "RAM";
port_rx_data_align : string := "PORT_CONNECTIVITY";
port_rx_channel_data_align : string := "PORT_CONNECTIVITY";
pll_operation_mode : string := "NORMAL";
x_on_bitslip : string := "ON";
use_no_phase_shift : string := "ON";
rx_align_data_reg : string := "RISING_EDGE";
inclock_phase_shift : integer := 0;
enable_soft_cdr_mode : string := "OFF";
sim_dpa_output_clock_phase_shift : integer := 0;
sim_dpa_is_negative_ppm_drift : string := "OFF";
sim_dpa_net_ppm_variation : natural := 0;
enable_dpa_align_to_rising_edge_only : string := "OFF";
enable_dpa_initial_phase_selection : string := "OFF";
dpa_initial_phase_value :natural := 0;
pll_self_reset_on_loss_lock : string := "OFF";
lpm_hint : string := "UNUSED";
lpm_type : string := "altlvds_rx";
-- Specifies whether the source of the input clock is from the PLL
clk_src_is_pll : string := "off" );
-- PORT DECLARATION
port (
--INPUT PORT DECLARATION
rx_in : in std_logic_vector(number_of_channels-1 downto 0); --Required port
rx_inclock : in std_logic := '0';
rx_syncclock : in std_logic := '0';
rx_readclock : in std_logic := '0';
rx_enable : in std_logic := '0';
rx_deskew : in std_logic := '0';
rx_pll_enable : in std_logic := '1';
rx_data_align : in std_logic := 'Z';
rx_data_align_reset : in std_logic := '0';
rx_reset : in std_logic_vector(number_of_channels-1 downto 0):= (others => '0');
rx_dpll_reset : in std_logic_vector(number_of_channels-1 downto 0):= (others => '0');
rx_dpll_hold : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_dpll_enable : in std_logic_vector(number_of_channels-1 downto 0) := (others => '1');
rx_fifo_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_channel_data_align : in std_logic_vector(number_of_channels-1 downto 0) := (others => 'Z');
rx_cda_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_coreclk : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
pll_areset : in std_logic := '0';
dpa_pll_recal : in std_logic := '0';
pll_phasedone : in std_logic := '1';
rx_dpa_lock_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
-- OUTPUT PORT DECLARATION
rx_out : out std_logic_vector(deserialization_factor*number_of_channels -1 downto 0);
rx_outclock : out std_logic;
rx_locked : out std_logic;
rx_dpa_locked : out std_logic_vector(number_of_channels-1 downto 0);
rx_cda_max : out std_logic_vector(number_of_channels-1 downto 0);
rx_divfwdclk : out std_logic_vector(number_of_channels-1 downto 0);
dpa_pll_cal_busy : out std_logic;
pll_phasestep : out std_logic;
pll_phaseupdown : out std_logic;
pll_phasecounterselect: out std_logic_Vector(3 downto 0);
pll_scanclk : out std_logic
);
end component;
component altlvds_tx
generic (
-- Specifies the number of LVDS channels (required)
number_of_channels : natural;
-- Specifies the number of bits per channel (required)
deserialization_factor : natural := 4;
-- Indicates whether the tx_in[] and tx_outclock ports should be
-- registered. Choices for STRATIX are ON, OFF, TX_CLKIN or TX_CORECLK
registered_input : string := "ON";
-- "ON" means that sync_inclock is also used
-- (not used for Stratix and Stratix GX.)
multi_clock : string := "OFF";
-- Specifies the period of the input clock in ps (Required)
inclock_period : natural := 10000;
-- Specifies the period of the tx_outclock port as
-- [INCLOCK_PERIOD * OUTCLOCK_DIVIDE_BY]
outclock_divide_by : positive := 1;
-- The effective clock period used to sample output data
inclock_boost : natural := 0;
-- Aligns the Most Significant Bit(MSB) to the falling edge of the
-- clock instead of the rising edge (only for APEX II devices)
center_align_msb : string := "OFF";
-- Specifies the device family to be used
intended_device_family : string := "APEX20KE";
-- Specifies the data rate out of the PLL.
-- (required and only for Stratix and Stratix GX devices)
output_data_rate : natural := 0;
-- Specifies the alignment of the input data with respect to the
-- tx_inclock port. (required and only available for Stratix and
-- Stratix GX devices)
inclock_data_alignment : string := "EDGE_ALIGNED";
-- Specifies the alignment of the output data with respect to the
-- tx_outclock port. (required and only available for Stratix and
-- Stratix GX devices)
outclock_alignment : string := "EDGE_ALIGNED";
-- Specifies whether the compiler uses the same PLL for both the LVDS
-- receiver and the LVDS transmitter
common_rx_tx_pll : string := "ON";
outclock_resource : string := "AUTO";
use_external_pll : string := "OFF";
implement_in_les : STRING := "OFF";
preemphasis_setting : natural := 0;
vod_setting : natural := 0;
differential_drive : natural := 0;
outclock_multiply_by : natural := 1;
coreclock_divide_by : natural := 2;
outclock_duty_cycle : natural := 50;
inclock_phase_shift : integer := 0;
outclock_phase_shift : integer := 0;
use_no_phase_shift : string := "ON";
pll_self_reset_on_loss_lock : string := "OFF";
lpm_type : string := "altlvds_tx";
lpm_hint : string := "UNUSED";
-- Specifies whether the source of the input clock is from the PLL
clk_src_is_pll : string := "off" );
-- PORT DECLARATION
port (
-- INPUT PORT DECLARATION
-- Input data (required)
tx_in : in std_logic_vector(deserialization_factor*
number_of_channels -1 downto 0);
-- Input clock (required)
tx_inclock : in std_logic := '0';
tx_syncclock : in std_logic := '0';
tx_enable : in std_logic := '1';
-- Optional clock for input registers (Required if "multi_clock"
-- parameters is turned on)
sync_inclock : in std_logic := '0';
-- Enable control for the LVDS PLL
tx_pll_enable : in std_logic := '1';
-- Asynchronously resets all counters to initial values (only for
--Stratix and Stratix GX devices)
pll_areset : in std_logic := '0';
-- OUTPUT PORT DECLARATION
-- Serialized data signal(required)
tx_out : out std_logic_vector(number_of_channels-1 downto 0)
:= (others => '0');
-- External reference clock
tx_outclock : out std_logic;
-- Output clock used to feed non-peripheral logic.
-- Only available for Stratix, and Stratix GX devices only.
tx_coreclock : out std_logic;
-- Gives the status of the LVDS PLL
-- (when the PLL is locked, this signal is VCC. GND otherwise)
tx_locked : out std_logic
);
end component;
component altdpram
generic (
width : natural;
widthad : natural;
numwords : natural := 0;
lpm_file : string := "UNUSED";
lpm_hint : string := "USE_EAB=ON";
use_eab : string := "ON";
indata_reg : string := "INCLOCK";
indata_aclr : string := "ON";
wraddress_reg : string := "INCLOCK";
wraddress_aclr : string := "ON";
wrcontrol_reg : string := "INCLOCK";
wrcontrol_aclr : string := "ON";
rdaddress_reg : string := "OUTCLOCK";
rdaddress_aclr : string := "ON";
rdcontrol_reg : string := "OUTCLOCK";
rdcontrol_aclr : string := "ON";
outdata_reg : string := "UNREGISTERED";
outdata_aclr : string := "ON";
ram_block_type : string := "AUTO";
width_byteena : natural := 1;
byte_size : natural := 5;
read_during_write_mode_mixed_ports : string := "DONT_CARE";
intended_device_family : string := "APEX20KE";
lpm_type : string := "altdpram" );
port(
wren : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0);
wraddress : in std_logic_vector(widthad-1 downto 0);
wraddressstall : in std_logic := '0';
inclock : in std_logic := '1';
inclocken : in std_logic := '1';
rden : in std_logic := '1';
rdaddress : in std_logic_vector(widthad-1 downto 0);
rdaddressstall : in std_logic := '0';
byteena : in std_logic_vector(width_byteena-1 downto 0) := (others => '1');
outclock : in std_logic := '1';
outclocken : in std_logic := '1';
aclr : in std_logic := '0';
q : out std_logic_vector(width-1 downto 0) );
end component;
component alt3pram
generic (
width : natural;
widthad : natural;
numwords : natural := 0;
lpm_file : string := "UNUSED";
lpm_hint : string := "USE_EAB=ON";
indata_reg : string := "UNREGISTERED";
indata_aclr : string := "OFF";
write_reg : string := "UNREGISTERED";
write_aclr : string := "OFF";
rdaddress_reg_a : string := "UNREGISTERED";
rdaddress_aclr_a : string := "OFF";
rdaddress_reg_b : string := "UNREGISTERED";
rdaddress_aclr_b : string := "OFF";
rdcontrol_reg_a : string := "UNREGISTERED";
rdcontrol_aclr_a : string := "OFF";
rdcontrol_reg_b : string := "UNREGISTERED";
rdcontrol_aclr_b : string := "OFF";
outdata_reg_a : string := "UNREGISTERED";
outdata_aclr_a : string := "OFF";
outdata_reg_b : string := "UNREGISTERED";
outdata_aclr_b : string := "OFF";
intended_device_family : string := "APEX20KE";
ram_block_type : string := "AUTO";
maximum_depth : integer := 0;
lpm_type : string := "alt3pram" );
port (
wren : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0);
wraddress : in std_logic_vector(widthad-1 downto 0);
inclock : in std_logic := '0';
inclocken : in std_logic := '1';
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
rdaddress_a : in std_logic_vector(widthad-1 downto 0);
rdaddress_b : in std_logic_vector(widthad-1 downto 0);
outclock : in std_logic := '0';
outclocken : in std_logic := '1';
aclr : in std_logic := '0';
qa : out std_logic_vector(width-1 downto 0);
qb : out std_logic_vector(width-1 downto 0) );
end component;
component altqpram
generic (
operation_mode : string := "QUAD_PORT";
width_write_a : natural := 1;
widthad_write_a : natural := 1;
numwords_write_a : natural := 0; -- default = 2^widthad_write_a
indata_reg_a : string := "INCLOCK_A";
indata_aclr_a : string := "INACLR_A";
wrcontrol_wraddress_reg_a : string := "INCLOCK_A";
wrcontrol_aclr_a : string := "INACLR_A";
wraddress_aclr_a : string := "INACLR_A";
width_write_b : natural := 1; -- default = width_write_a
widthad_write_b : natural := 1; -- default = widthad_write_a
numwords_write_b : natural := 0; -- default = 2^widthad_write_b
indata_reg_b : string := "INCLOCK_B";
indata_aclr_b : string := "INACLR_B";
wrcontrol_wraddress_reg_b : string := "INCLOCK_B";
wrcontrol_aclr_b : string := "INACLR_B";
wraddress_aclr_b : string := "INACLR_B";
width_read_a : natural := 1;
widthad_read_a : natural := 1;
numwords_read_a : natural := 0; -- default = 2^widthad_read_a
rdcontrol_reg_a : string := "OUTCLOCK_A";
rdcontrol_aclr_a : string := "OUTACLR_A";
rdaddress_reg_a : string := "OUTCLOCK_A";
rdaddress_aclr_a : string := "OUTACLR_A";
outdata_reg_a : string := "UNREGISTERED";
outdata_aclr_a : string := "OUTACLR_A";
width_read_b : natural := 1; -- default = width_read_a
widthad_read_b : natural := 1; -- default = widthad_read_a
numwords_read_b : natural := 0; -- default = 2^widthad_read_b
rdcontrol_reg_b : string := "OUTCLOCK_B";
rdcontrol_aclr_b : string := "OUTACLR_B";
rdaddress_reg_b : string := "OUTCLOCK_B";
rdaddress_aclr_b : string := "OUTACLR_B";
outdata_reg_b : string := "UNREGISTERED";
outdata_aclr_b : string := "OUTACLR_B";
init_file : string := "UNUSED";
lpm_hint : string := "UNUSED";
lpm_type : string := "altqpram" );
port (
wren_a : in std_logic := '0';
wren_b : in std_logic := '0';
data_a : in std_logic_vector(width_write_a-1 downto 0) := (OTHERS => '0');
data_b : in std_logic_vector(width_write_b-1 downto 0) := (OTHERS => '0');
wraddress_a : in std_logic_vector(widthad_write_a-1 downto 0) := (OTHERS => '0');
wraddress_b : in std_logic_vector(widthad_write_b-1 downto 0) := (OTHERS => '0');
inclock_a : in std_logic := '0';
inclock_b : in std_logic := '0';
inclocken_a : in std_logic := '1';
inclocken_b : in std_logic := '1';
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
rdaddress_a : in std_logic_vector(widthad_read_a-1 downto 0) := (OTHERS => '0');
rdaddress_b : in std_logic_vector(widthad_read_b-1 downto 0) := (OTHERS => '0');
outclock_a : in std_logic := '0';
outclock_b : in std_logic := '0';
outclocken_a : in std_logic := '1';
outclocken_b : in std_logic := '1';
inaclr_a : in std_logic := '0';
inaclr_b : in std_logic := '0';
outaclr_a : in std_logic := '0';
outaclr_b : in std_logic := '0';
q_a : out std_logic_vector(width_read_a-1 downto 0);
q_b : out std_logic_vector(width_read_b-1 downto 0) );
end component;
component scfifo
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
lpm_hint : string := "USE_EAB=ON";
intended_device_family : string := "NON_STRATIX";
almost_full_value : natural := 0;
almost_empty_value : natural := 0;
overflow_checking : string := "ON";
underflow_checking : string := "ON";
allow_rwcycle_when_full : string := "OFF";
add_ram_output_register : string := "OFF";
use_eab : string := "ON";
lpm_type : string := "scfifo";
maximum_depth : natural := 0 );
port (
data : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic;
wrreq : in std_logic;
rdreq : in std_logic;
aclr : in std_logic := '0';
sclr : in std_logic := '0';
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
almost_empty : out std_logic;
q : out std_logic_vector(lpm_width-1 downto 0);
usedw : out std_logic_vector(lpm_widthu-1 downto 0) );
end component;
component dcfifo_mixed_widths
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_width_r : natural := 0;
lpm_widthu_r : natural := 0;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
lpm_hint : string := "USE_EAB=ON";
overflow_checking : string := "ON";
underflow_checking : string := "ON";
delay_rdusedw : natural := 1;
delay_wrusedw : natural := 1;
rdsync_delaypipe : natural := 0;
wrsync_delaypipe : natural := 0;
use_eab : string := "ON";
add_ram_output_register : string := "OFF";
add_width : natural := 1;
clocks_are_synchronized : string := "FALSE";
ram_block_type : string := "AUTO";
add_usedw_msb_bit : string := "OFF";
write_aclr_synch : string := "OFF";
lpm_type : string := "dcfifo_mixed_widths";
intended_device_family : string := "NON_STRATIX" );
port (
data : in std_logic_vector(lpm_width-1 downto 0);
rdclk : in std_logic;
wrclk : in std_logic;
wrreq : in std_logic;
rdreq : in std_logic;
aclr : in std_logic := '0';
rdfull : out std_logic;
wrfull : out std_logic;
wrempty : out std_logic;
rdempty : out std_logic;
q : out std_logic_vector(lpm_width_r-1 downto 0);
rdusedw : out std_logic_vector(lpm_widthu_r-1 downto 0);
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0) );
end component;
component dcfifo
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
lpm_hint : string := "USE_EAB=ON";
overflow_checking : string := "ON";
underflow_checking : string := "ON";
delay_rdusedw : natural := 1;
delay_wrusedw : natural := 1;
rdsync_delaypipe : natural := 0;
wrsync_delaypipe : natural := 0;
use_eab : string := "ON";
add_ram_output_register : string := "OFF";
add_width : natural := 1;
clocks_are_synchronized : string := "FALSE";
ram_block_type : string := "AUTO";
add_usedw_msb_bit : string := "OFF";
write_aclr_synch : string := "OFF";
lpm_type : string := "dcfifo";
intended_device_family : string := "NON_STRATIX" );
port (
data : in std_logic_vector(lpm_width-1 downto 0);
rdclk : in std_logic;
wrclk : in std_logic;
wrreq : in std_logic;
rdreq : in std_logic;
aclr : in std_logic := '0';
rdfull : out std_logic;
wrfull : out std_logic;
wrempty : out std_logic;
rdempty : out std_logic;
q : out std_logic_vector(lpm_width-1 downto 0);
rdusedw : out std_logic_vector(lpm_widthu-1 downto 0);
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0) );
end component;
component altddio_in
generic (
width : positive; -- required parameter
invert_input_clocks : string := "OFF";
intended_device_family : string := "Stratix";
power_up_high : string := "OFF";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_in" );
port (
datain : in std_logic_vector(width-1 downto 0);
inclock : in std_logic;
inclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
dataout_h : out std_logic_vector(width-1 downto 0);
dataout_l : out std_logic_vector(width-1 downto 0) );
end component;
component altddio_out
generic (
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "Stratix";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_out" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
oe : in std_logic := '1';
dataout : out std_logic_vector(width-1 downto 0);
oe_out : out std_logic_vector(width-1 downto 0) );
end component;
component altddio_bidir
generic(
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
implement_input_in_lcell : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "Stratix";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_bidir" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
inclock : in std_logic := '0';
inclocken : in std_logic := '1';
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
oe : in std_logic := '1';
dataout_h : out std_logic_vector(width-1 downto 0);
dataout_l : out std_logic_vector(width-1 downto 0);
combout : out std_logic_vector(width-1 downto 0);
oe_out : out std_logic_vector(width-1 downto 0);
dqsundelayedout : out std_logic_vector(width-1 downto 0);
padio : inout std_logic_vector(width-1 downto 0) );
end component;
component altshift_taps
generic (
number_of_taps : integer := 4;
tap_distance : integer := 3;
width : integer := 8;
power_up_state : string := "CLEARED";
lpm_hint : string := "UNUSED";
lpm_type : string := "altshift_taps" );
port (
shiftin : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
clken : in std_logic := '1';
aclr : in std_logic := '0';
shiftout : out std_logic_vector (width-1 downto 0);
taps : out std_logic_vector ((width*number_of_taps)-1 downto 0));
end component;
component altmult_add
generic (
WIDTH_A : integer := 1;
WIDTH_B : integer := 1;
WIDTH_RESULT : integer := 1;
NUMBER_OF_MULTIPLIERS : integer := 1;
-- A inputs
INPUT_REGISTER_A0 : string := "CLOCK0";
INPUT_ACLR_A0 : string := "ACLR3";
INPUT_SOURCE_A0 : string := "DATAA";
INPUT_REGISTER_A1 : string := "CLOCK0";
INPUT_ACLR_A1 : string := "ACLR3";
INPUT_SOURCE_A1 : string := "DATAA";
INPUT_REGISTER_A2 : string := "CLOCK0";
INPUT_ACLR_A2 : string := "ACLR3";
INPUT_SOURCE_A2 : string := "DATAA";
INPUT_REGISTER_A3 : string := "CLOCK0";
INPUT_ACLR_A3 : string := "ACLR3";
INPUT_SOURCE_A3 : string := "DATAA";
PORT_SIGNA : string := "PORT_CONNECTIVITY";
REPRESENTATION_A : string := "UNSIGNED";
SIGNED_REGISTER_A : string := "CLOCK0";
SIGNED_ACLR_A : string := "ACLR3";
SIGNED_PIPELINE_REGISTER_A : string := "CLOCK0";
SIGNED_PIPELINE_ACLR_A : string := "ACLR3";
-- B inputs
INPUT_REGISTER_B0 : string := "CLOCK0";
INPUT_ACLR_B0 : string := "ACLR3";
INPUT_SOURCE_B0 : string := "DATAB";
INPUT_REGISTER_B1 : string := "CLOCK0";
INPUT_ACLR_B1 : string := "ACLR3";
INPUT_SOURCE_B1 : string := "DATAB";
INPUT_REGISTER_B2 : string := "CLOCK0";
INPUT_ACLR_B2 : string := "ACLR3";
INPUT_SOURCE_B2 : string := "DATAB";
INPUT_REGISTER_B3 : string := "CLOCK0";
INPUT_ACLR_B3 : string := "ACLR3";
INPUT_SOURCE_B3 : string := "DATAB";
PORT_SIGNB : string := "PORT_CONNECTIVITY";
REPRESENTATION_B : string := "UNSIGNED";
SIGNED_REGISTER_B : string := "CLOCK0";
SIGNED_ACLR_B : string := "ACLR3";
SIGNED_PIPELINE_REGISTER_B : string := "CLOCK0";
SIGNED_PIPELINE_ACLR_B : string := "ACLR3";
MULTIPLIER_REGISTER0 : string := "CLOCK0";
MULTIPLIER_ACLR0 : string := "ACLR3";
MULTIPLIER_REGISTER1 : string := "CLOCK0";
MULTIPLIER_ACLR1 : string := "ACLR3";
MULTIPLIER_REGISTER2 : string := "CLOCK0";
MULTIPLIER_ACLR2 : string := "ACLR3";
MULTIPLIER_REGISTER3 : string := "CLOCK0";
MULTIPLIER_ACLR3 : string := "ACLR3";
PORT_ADDNSUB1 : string := "PORT_CONNECTIVITY";
ADDNSUB_MULTIPLIER_REGISTER1 : string := "CLOCK0";
ADDNSUB_MULTIPLIER_ACLR1 : string := "ACLR3";
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 : string := "CLOCK0";
ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 : string := "ACLR3";
PORT_ADDNSUB3 : string := "PORT_CONNECTIVITY";
ADDNSUB_MULTIPLIER_REGISTER3 : string := "CLOCK0";
ADDNSUB_MULTIPLIER_ACLR3 : string := "ACLR3";
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3: string := "CLOCK0";
ADDNSUB_MULTIPLIER_PIPELINE_ACLR3 : string := "ACLR3";
ADDNSUB1_ROUND_ACLR : string := "ACLR3";
ADDNSUB1_ROUND_PIPELINE_ACLR : string := "ACLR3";
ADDNSUB1_ROUND_REGISTER : string := "CLOCK0";
ADDNSUB1_ROUND_PIPELINE_REGISTER : string := "CLOCK0";
ADDNSUB3_ROUND_ACLR : string := "ACLR3";
ADDNSUB3_ROUND_PIPELINE_ACLR : string := "ACLR3";
ADDNSUB3_ROUND_REGISTER : string := "CLOCK0";
ADDNSUB3_ROUND_PIPELINE_REGISTER : string := "CLOCK0";
MULT01_ROUND_ACLR : string := "ACLR3";
MULT01_ROUND_REGISTER : string := "CLOCK0";
MULT01_SATURATION_REGISTER : string := "CLOCK0";
MULT01_SATURATION_ACLR : string := "ACLR3";
MULT23_ROUND_REGISTER : string := "CLOCK0";
MULT23_ROUND_ACLR : string := "ACLR3";
MULT23_SATURATION_REGISTER : string := "CLOCK0";
MULT23_SATURATION_ACLR : string := "ACLR3";
multiplier1_direction : string := "ADD";
multiplier3_direction : string := "ADD";
OUTPUT_REGISTER : string := "CLOCK0";
OUTPUT_ACLR : string := "ACLR0";
-- StratixII parameters
multiplier01_rounding : string := "NO";
multiplier01_saturation : string := "NO";
multiplier23_rounding : string := "NO";
multiplier23_saturation : string := "NO";
adder1_rounding : string := "NO";
adder3_rounding : string := "NO";
port_mult0_is_saturated : string := "UNUSED";
port_mult1_is_saturated : string := "UNUSED";
port_mult2_is_saturated : string := "UNUSED";
port_mult3_is_saturated : string := "UNUSED";
-- Stratix III parameters
scanouta_register : string := "UNREGISTERED";
scanouta_aclr : string := "NONE";
-- Rounding parameters
output_rounding : string := "NO";
output_round_type : string := "NEAREST_INTEGER";
width_msb : integer := 17;
output_round_register : string := "UNREGISTERED";
output_round_aclr : string := "NONE";
output_round_pipeline_register : string := "UNREGISTERED";
output_round_pipeline_aclr : string := "NONE";
chainout_rounding : string := "NO";
chainout_round_register : string := "UNREGISTERED";
chainout_round_aclr : string := "NONE";
chainout_round_pipeline_register : string := "UNREGISTERED";
chainout_round_pipeline_aclr : string := "NONE";
chainout_round_output_register : string := "UNREGISTERED";
chainout_round_output_aclr : string := "NONE";
-- saturation parameters
port_output_is_overflow : string := "PORT_UNUSED";
port_chainout_sat_is_overflow : string := "PORT_UNUSED";
output_saturation : string := "NO";
output_saturate_type : string := "ASYMMETRIC";
width_saturate_sign : integer := 1;
output_saturate_register : string := "UNREGISTERED";
output_saturate_aclr : string := "NONE";
output_saturate_pipeline_register : string := "UNREGISTERED";
output_saturate_pipeline_aclr : string := "NONE";
chainout_saturation : string := "NO";
chainout_saturate_register : string := "UNREGISTERED";
chainout_saturate_aclr : string := "NONE";
chainout_saturate_pipeline_register : string := "UNREGISTERED";
chainout_saturate_pipeline_aclr : string := "NONE";
chainout_saturate_output_register : string := "UNREGISTERED";
chainout_saturate_output_aclr : string := "NONE";
-- chainout parameters
chainout_adder : string := "NO";
chainout_register : string := "UNREGISTERED";
chainout_aclr : string := "NONE";
width_chainin : integer := 1;
zero_chainout_output_register : string := "UNREGISTERED";
zero_chainout_output_aclr : string := "NONE";
-- rotate & shift parameters
shift_mode : string := "NO";
rotate_aclr : string := "NONE";
rotate_register : string := "UNREGISTERED";
rotate_pipeline_register : string := "UNREGISTERED";
rotate_pipeline_aclr : string := "NONE";
rotate_output_register : string := "UNREGISTERED";
rotate_output_aclr : string := "NONE";
shift_right_register : string := "UNREGISTERED";
shift_right_aclr : string := "NONE";
shift_right_pipeline_register : string := "UNREGISTERED";
shift_right_pipeline_aclr : string := "NONE";
shift_right_output_register : string := "UNREGISTERED";
shift_right_output_aclr : string := "NONE";
-- loopback parameters
zero_loopback_register : string := "UNREGISTERED";
zero_loopback_aclr : string := "NONE";
zero_loopback_pipeline_register : string := "UNREGISTERED";
zero_loopback_pipeline_aclr : string := "NONE";
zero_loopback_output_register : string := "UNREGISTERED";
zero_loopback_output_aclr : string := "NONE";
-- accumulator parameters
accum_sload_register : string := "UNREGISTERED";
accum_sload_aclr : string := "NONE";
accum_sload_pipeline_register : string := "UNREGISTERED";
accum_sload_pipeline_aclr : string := "NONE";
accum_direction : string := "ADD";
accumulator : string := "NO";
EXTRA_LATENCY : integer :=0;
DEDICATED_MULTIPLIER_CIRCUITRY:string := "AUTO";
DSP_BLOCK_BALANCING : string := "AUTO";
lpm_hint : string := "UNUSED";
lpm_type : string := "altmult_add";
intended_device_family : string := "Stratix" );
port (
dataa : in std_logic_vector(NUMBER_OF_MULTIPLIERS * WIDTH_A -1 downto 0);
datab : in std_logic_vector(NUMBER_OF_MULTIPLIERS * WIDTH_B -1 downto 0);
scanina : in std_logic_vector(width_a -1 downto 0) := (others => '0');
scaninb : in std_logic_vector(width_b -1 downto 0) := (others => '0');
sourcea : in std_logic_vector(NUMBER_OF_MULTIPLIERS -1 downto 0) := (others => '0');
sourceb : in std_logic_vector(NUMBER_OF_MULTIPLIERS -1 downto 0) := (others => '0');
-- clock ports
clock3 : in std_logic := '1';
clock2 : in std_logic := '1';
clock1 : in std_logic := '1';
clock0 : in std_logic := '1';
aclr3 : in std_logic := '0';
aclr2 : in std_logic := '0';
aclr1 : in std_logic := '0';
aclr0 : in std_logic := '0';
ena3 : in std_logic := '1';
ena2 : in std_logic := '1';
ena1 : in std_logic := '1';
ena0 : in std_logic := '1';
-- control signals
signa : in std_logic := 'Z';
signb : in std_logic := 'Z';
addnsub1 : in std_logic := 'Z';
addnsub3 : in std_logic := 'Z';
-- StratixII only input ports
mult01_round : in std_logic := '0';
mult23_round : in std_logic := '0';
mult01_saturation : in std_logic := '0';
mult23_saturation : in std_logic := '0';
addnsub1_round : in std_logic := '0';
addnsub3_round : in std_logic := '0';
-- Stratix III only input ports
output_round : in std_logic := '0';
chainout_round : in std_logic := '0';
output_saturate : in std_logic := '0';
chainout_saturate : in std_logic := '0';
chainin : in std_logic_vector (width_chainin - 1 downto 0) := (others => '0');
zero_chainout : in std_logic := '0';
rotate : in std_logic := '0';
shift_right : in std_logic := '0';
zero_loopback : in std_logic := '0';
accum_sload : in std_logic := '0';
-- output ports
result : out std_logic_vector(WIDTH_RESULT -1 downto 0);
scanouta : out std_logic_vector (WIDTH_A -1 downto 0);
scanoutb : out std_logic_vector (WIDTH_B -1 downto 0);
-- StratixII only output ports
mult0_is_saturated : out std_logic := '0';
mult1_is_saturated : out std_logic := '0';
mult2_is_saturated : out std_logic := '0';
mult3_is_saturated : out std_logic := '0';
-- Stratix III only output ports
overflow : out std_logic := '0';
chainout_sat_overflow : out std_logic := '0');
end component;
component altmult_accum
generic (
width_a : integer := 1;
width_b : integer := 1;
width_result : integer := 2;
width_upper_data : integer := 1;
input_source_a : string := "DATAA";
input_source_b : string := "DATAB";
input_reg_a : string := "CLOCK0";
input_aclr_a : string := "ACLR3";
input_reg_b : string := "CLOCK0";
input_aclr_b : string := "ACLR3";
port_addnsub : string := "PORT_CONNECTIVITY";
addnsub_reg : string := "CLOCK0";
addnsub_aclr : string := "ACLR3";
addnsub_pipeline_reg : string := "CLOCK0";
addnsub_pipeline_aclr : string := "ACLR3";
accum_direction : string := "ADD";
accum_sload_reg : string := "CLOCK0";
accum_sload_aclr : string := "ACLR3";
accum_sload_pipeline_reg : string := "CLOCK0";
accum_sload_pipeline_aclr : string := "ACLR3";
representation_a : string := "UNSIGNED";
port_signa : string := "PORT_CONNECTIVITY";
sign_reg_a : string := "CLOCK0";
sign_aclr_a : string := "ACLR3";
sign_pipeline_reg_a : string := "CLOCK0";
sign_pipeline_aclr_a : string := "ACLR3";
representation_b : string := "UNSIGNED";
port_signb : string := "PORT_CONNECTIVITY";
sign_reg_b : string := "CLOCK0";
sign_aclr_b : string := "ACLR3";
sign_pipeline_reg_b : string := "CLOCK0";
sign_pipeline_aclr_b : string := "ACLR3";
multiplier_reg : string := "CLOCK0";
multiplier_aclr : string := "ACLR3";
output_reg : string := "CLOCK0";
output_aclr : string := "ACLR0";
extra_multiplier_latency : integer := 0;
extra_accumulator_latency : integer := 0;
dedicated_multiplier_circuitry : string := "AUTO";
dsp_block_balancing : string := "AUTO";
lpm_hint : string := "UNUSED";
lpm_type : string := "altmult_accum";
intended_device_family : string := "Stratix";
multiplier_rounding : string := "NO";
multiplier_saturation : string := "NO";
accumulator_rounding : string := "NO";
accumulator_saturation : string := "NO";
port_mult_is_saturated : string := "UNUSED";
port_accum_is_saturated : string := "UNUSED";
mult_round_aclr : string := "ACLR3";
mult_round_reg : string := "CLOCK0";
mult_saturation_aclr : string := "ACLR3";
mult_saturation_reg : string := "CLOCK0";
accum_round_aclr : string := "ACLR3";
accum_round_reg : string := "CLOCK3";
accum_round_pipeline_aclr : string := "ACLR3";
accum_round_pipeline_reg : string := "CLOCK0";
accum_saturation_aclr : string := "ACLR3";
accum_saturation_reg : string := "CLOCK0";
accum_saturation_pipeline_aclr : string := "ACLR3";
accum_saturation_pipeline_reg : string := "CLOCK0";
accum_sload_upper_data_aclr : string := "ACLR3";
accum_sload_upper_data_pipeline_aclr : string := "ACLR3";
accum_sload_upper_data_pipeline_reg : string := "CLOCK0";
accum_sload_upper_data_reg : string := "CLOCK0" );
port (
dataa : in std_logic_vector(width_a -1 downto 0) := (others => '0');
datab : in std_logic_vector(width_b -1 downto 0) := (others => '0');
scanina : in std_logic_vector(width_a -1 downto 0) := (others => 'Z');
scaninb : in std_logic_vector(width_b -1 downto 0) := (others => 'Z');
accum_sload_upper_data : in std_logic_vector(width_result -1 downto width_result - width_upper_data) := (others => '0');
sourcea : in std_logic := '1';
sourceb : in std_logic := '1';
-- control signals
addnsub : in std_logic := 'Z';
accum_sload : in std_logic := '0';
signa : in std_logic := 'Z';
signb : in std_logic := 'Z';
-- clock ports
clock0 : in std_logic := '1';
clock1 : in std_logic := '1';
clock2 : in std_logic := '1';
clock3 : in std_logic := '1';
ena0 : in std_logic := '1';
ena1 : in std_logic := '1';
ena2 : in std_logic := '1';
ena3 : in std_logic := '1';
aclr0 : in std_logic := '0';
aclr1 : in std_logic := '0';
aclr2 : in std_logic := '0';
aclr3 : in std_logic := '0';
-- round and saturation ports
mult_round : in std_logic := '0';
mult_saturation : in std_logic := '0';
accum_round : in std_logic := '0';
accum_saturation : in std_logic := '0';
-- output ports
result : out std_logic_vector(width_result -1 downto 0);
overflow : out std_logic;
scanouta : out std_logic_vector (width_a -1 downto 0);
scanoutb : out std_logic_vector (width_b -1 downto 0);
mult_is_saturated : out std_logic := '0';
accum_is_saturated : out std_logic := '0' );
end component;
component altaccumulate
generic (
width_in : integer:= 4;
width_out : integer:= 8;
lpm_representation : string := "UNSIGNED";
extra_latency : integer:= 0;
use_wys : string := "ON";
lpm_hint : string := "UNUSED";
lpm_type : string := "altaccumulate" );
port (
-- Input ports
cin : in std_logic := 'Z';
data : in std_logic_vector(width_in -1 downto 0); -- Required port
add_sub : in std_logic := '1';
clock : in std_logic; -- Required port
sload : in std_logic := '0';
clken : in std_logic := '1';
sign_data : in std_logic := '0';
aclr : in std_logic := '0';
-- Output ports
result : out std_logic_vector(width_out -1 downto 0) := (others => '0');
cout : out std_logic := '0';
overflow : out std_logic := '0' );
end component;
component altsyncram
generic (
operation_mode : string := "BIDIR_DUAL_PORT";
-- port a parameters
width_a : integer := 1;
widthad_a : integer := 1;
numwords_a : integer := 0;
-- registering parameters
-- port a read parameters
outdata_reg_a : string := "UNREGISTERED";
-- clearing parameters
address_aclr_a : string := "NONE";
outdata_aclr_a : string := "NONE";
-- clearing parameters
-- port a write parameters
indata_aclr_a : string := "NONE";
wrcontrol_aclr_a : string := "NONE";
-- clear for the byte enable port reigsters which are clocked by clk0
byteena_aclr_a : string := "NONE";
-- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9
width_byteena_a : integer := 1;
-- port b parameters
width_b : integer := 1;
widthad_b : integer := 1;
numwords_b : integer := 0;
-- registering parameters
-- port b read parameters
rdcontrol_reg_b : string := "CLOCK1";
address_reg_b : string := "CLOCK1";
outdata_reg_b : string := "UNREGISTERED";
-- clearing parameters
outdata_aclr_b : string := "NONE";
rdcontrol_aclr_b : string := "NONE";
-- registering parameters
-- port b write parameters
indata_reg_b : string := "CLOCK1";
wrcontrol_wraddress_reg_b : string := "CLOCK1";
-- registering parameter for the byte enable reister for port b
byteena_reg_b : string := "CLOCK1";
-- clearing parameters
indata_aclr_b : string := "NONE";
wrcontrol_aclr_b : string := "NONE";
address_aclr_b : string := "NONE";
-- clear parameter for byte enable port register
byteena_aclr_b : string := "NONE";
-- StratixII only : to bypass clock enable or using clock enable
clock_enable_input_a : string := "NORMAL";
clock_enable_output_a : string := "NORMAL";
clock_enable_input_b : string := "NORMAL";
clock_enable_output_b : string := "NORMAL";
-- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9
width_byteena_b : integer := 1;
-- clock enable setting for the core
clock_enable_core_a : string := "USE_INPUT_CLKEN";
clock_enable_core_b : string := "USE_INPUT_CLKEN";
-- read-during-write-same-port setting
read_during_write_mode_port_a : string := "NEW_DATA_NO_NBE_READ";
read_during_write_mode_port_b : string := "NEW_DATA_NO_NBE_READ";
-- ECC status ports setting
enable_ecc : string := "FALSE";
-- global parameters
-- width of a byte for byte enables
byte_size : integer := 0;
read_during_write_mode_mixed_ports: string := "DONT_CARE";
-- ram block type choices are "AUTO", "M512", "M4K" and "MEGARAM"
ram_block_type : string := "AUTO";
-- determine whether LE support is turned on or off for altsyncram
implement_in_les : string := "OFF";
-- determine whether RAM would be power up to uninitialized or not
power_up_uninitialized : string := "FALSE";
sim_show_memory_data_in_port_b_layout : string := "OFF";
-- general operation parameters
init_file : string := "UNUSED";
init_file_layout : string := "UNUSED";
maximum_depth : integer := 0;
intended_device_family : string := "Stratix";
lpm_hint : string := "UNUSED";
lpm_type : string := "altsyncram" );
port (
wren_a : in std_logic := '0';
wren_b : in std_logic := '0';
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
data_a : in std_logic_vector(width_a - 1 downto 0):= (others => '1');
data_b : in std_logic_vector(width_b - 1 downto 0):= (others => '1');
address_a : in std_logic_vector(widthad_a - 1 downto 0);
address_b : in std_logic_vector(widthad_b - 1 downto 0) := (others => '1');
clock0 : in std_logic := '1';
clock1 : in std_logic := 'Z';
clocken0 : in std_logic := '1';
clocken1 : in std_logic := '1';
clocken2 : in std_logic := '1';
clocken3 : in std_logic := '1';
aclr0 : in std_logic := '0';
aclr1 : in std_logic := '0';
byteena_a : in std_logic_vector( (width_byteena_a - 1) downto 0) := (others => '1');
byteena_b : in std_logic_vector( (width_byteena_b - 1) downto 0) := (others => 'Z');
addressstall_a : in std_logic := '0';
addressstall_b : in std_logic := '0';
q_a : out std_logic_vector(width_a - 1 downto 0);
q_b : out std_logic_vector(width_b - 1 downto 0);
eccstatus : out std_logic_vector(2 downto 0) );
end component;
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
pll_type : string := "AUTO" ;
qualify_conf_done : string := "OFF" ;
compensate_clock : string := "CLK0" ;
scan_chain : string := "LONG";
primary_clock : string := "inclk0" ;
inclk0_input_frequency : natural; -- required parameter
inclk1_input_frequency : natural := 0;
gate_lock_signal : string := "NO";
gate_lock_counter : integer := 0;
lock_high : natural := 1;
lock_low : natural := 5;
valid_lock_multiplier : natural := 1;
invalid_lock_multiplier : natural := 5;
switch_over_type : string := "AUTO";
switch_over_on_lossclk : string := "OFF" ;
switch_over_on_gated_lock : string := "OFF" ;
enable_switch_over_counter : string := "OFF";
switch_over_counter : natural := 0;
feedback_source : string := "EXTCLK0" ;
bandwidth : natural := 0;
bandwidth_type : string := "UNUSED";
spread_frequency : natural := 0;
down_spread : string := "0.0";
self_reset_on_gated_loss_lock : string := "OFF";
self_reset_on_loss_lock : string := "OFF";
lock_window_ui : string := "0.05";
width_clock : natural := 6;
width_phasecounterselect : natural := 4;
charge_pump_current_bits : natural := 9999;
loop_filter_c_bits : natural := 9999;
loop_filter_r_bits : natural := 9999;
scan_chain_mif_file : string := "UNUSED";
-- simulation-only parameters
simulation_type : string := "functional";
source_is_pll : string := "off";
skip_vco : string := "off";
-- internal clock specifications
clk9_multiply_by : natural := 1;
clk8_multiply_by : natural := 1;
clk7_multiply_by : natural := 1;
clk6_multiply_by : natural := 1;
clk5_multiply_by : natural := 1;
clk4_multiply_by : natural := 1;
clk3_multiply_by : natural := 1;
clk2_multiply_by : natural := 1;
clk1_multiply_by : natural := 1;
clk0_multiply_by : natural := 1;
clk9_divide_by : natural := 1;
clk8_divide_by : natural := 1;
clk7_divide_by : natural := 1;
clk6_divide_by : natural := 1;
clk5_divide_by : natural := 1;
clk4_divide_by : natural := 1;
clk3_divide_by : natural := 1;
clk2_divide_by : natural := 1;
clk1_divide_by : natural := 1;
clk0_divide_by : natural := 1;
clk9_phase_shift : string := "0";
clk8_phase_shift : string := "0";
clk7_phase_shift : string := "0";
clk6_phase_shift : string := "0";
clk5_phase_shift : string := "0";
clk4_phase_shift : string := "0";
clk3_phase_shift : string := "0";
clk2_phase_shift : string := "0";
clk1_phase_shift : string := "0";
clk0_phase_shift : string := "0";
clk5_time_delay : string := "0";
clk4_time_delay : string := "0";
clk3_time_delay : string := "0";
clk2_time_delay : string := "0";
clk1_time_delay : string := "0";
clk0_time_delay : string := "0";
clk9_duty_cycle : natural := 50;
clk8_duty_cycle : natural := 50;
clk7_duty_cycle : natural := 50;
clk6_duty_cycle : natural := 50;
clk5_duty_cycle : natural := 50;
clk4_duty_cycle : natural := 50;
clk3_duty_cycle : natural := 50;
clk2_duty_cycle : natural := 50;
clk1_duty_cycle : natural := 50;
clk0_duty_cycle : natural := 50;
clk2_output_frequency : natural := 0;
clk1_output_frequency : natural := 0;
clk0_output_frequency : natural := 0;
clk9_use_even_counter_mode : string := "OFF";
clk8_use_even_counter_mode : string := "OFF";
clk7_use_even_counter_mode : string := "OFF";
clk6_use_even_counter_mode : string := "OFF";
clk5_use_even_counter_mode : string := "OFF";
clk4_use_even_counter_mode : string := "OFF";
clk3_use_even_counter_mode : string := "OFF";
clk2_use_even_counter_mode : string := "OFF";
clk1_use_even_counter_mode : string := "OFF";
clk0_use_even_counter_mode : string := "OFF";
clk9_use_even_counter_value : string := "OFF";
clk8_use_even_counter_value : string := "OFF";
clk7_use_even_counter_value : string := "OFF";
clk6_use_even_counter_value : string := "OFF";
clk5_use_even_counter_value : string := "OFF";
clk4_use_even_counter_value : string := "OFF";
clk3_use_even_counter_value : string := "OFF";
clk2_use_even_counter_value : string := "OFF";
clk1_use_even_counter_value : string := "OFF";
clk0_use_even_counter_value : string := "OFF";
-- external clock specifications
extclk3_multiply_by : natural := 1;
extclk2_multiply_by : natural := 1;
extclk1_multiply_by : natural := 1;
extclk0_multiply_by : natural := 1;
extclk3_divide_by : natural := 1;
extclk2_divide_by : natural := 1;
extclk1_divide_by : natural := 1;
extclk0_divide_by : natural := 1;
extclk3_phase_shift : string := "0";
extclk2_phase_shift : string := "0";
extclk1_phase_shift : string := "0";
extclk0_phase_shift : string := "0";
extclk3_time_delay : string := "0";
extclk2_time_delay : string := "0";
extclk1_time_delay : string := "0";
extclk0_time_delay : string := "0";
extclk3_duty_cycle : natural := 50;
extclk2_duty_cycle : natural := 50;
extclk1_duty_cycle : natural := 50;
extclk0_duty_cycle : natural := 50;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
sclkout0_phase_shift : string := "0";
sclkout1_phase_shift : string := "0";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
-- advanced user parameters
vco_min : natural := 0;
vco_max : natural := 0;
vco_center : natural := 0;
pfd_min : natural := 0;
pfd_max : natural := 0;
m_initial : natural := 1;
m : natural := 0; -- m must default to 0 to force altpll to calculate the internal parameters for itself
n : natural := 1;
m2 : natural := 1;
n2 : natural := 1;
ss : natural := 0;
c0_high : natural := 1;
c1_high : natural := 1;
c2_high : natural := 1;
c3_high : natural := 1;
c4_high : natural := 1;
c5_high : natural := 1;
c6_high : natural := 1;
c7_high : natural := 1;
c8_high : natural := 1;
c9_high : natural := 1;
l0_high : natural := 1;
l1_high : natural := 1;
g0_high : natural := 1;
g1_high : natural := 1;
g2_high : natural := 1;
g3_high : natural := 1;
e0_high : natural := 1;
e1_high : natural := 1;
e2_high : natural := 1;
e3_high : natural := 1;
c0_low : natural := 1;
c1_low : natural := 1;
c2_low : natural := 1;
c3_low : natural := 1;
c4_low : natural := 1;
c5_low : natural := 1;
c6_low : natural := 1;
c7_low : natural := 1;
c8_low : natural := 1;
c9_low : natural := 1;
l0_low : natural := 1;
l1_low : natural := 1;
g0_low : natural := 1;
g1_low : natural := 1;
g2_low : natural := 1;
g3_low : natural := 1;
e0_low : natural := 1;
e1_low : natural := 1;
e2_low : natural := 1;
e3_low : natural := 1;
c0_initial : natural := 1;
c1_initial : natural := 1;
c2_initial : natural := 1;
c3_initial : natural := 1;
c4_initial : natural := 1;
c5_initial : natural := 1;
c6_initial : natural := 1;
c7_initial : natural := 1;
c8_initial : natural := 1;
c9_initial : natural := 1;
l0_initial : natural := 1;
l1_initial : natural := 1;
g0_initial : natural := 1;
g1_initial : natural := 1;
g2_initial : natural := 1;
g3_initial : natural := 1;
e0_initial : natural := 1;
e1_initial : natural := 1;
e2_initial : natural := 1;
e3_initial : natural := 1;
c0_mode : string := "bypass" ;
c1_mode : string := "bypass" ;
c2_mode : string := "bypass" ;
c3_mode : string := "bypass" ;
c4_mode : string := "bypass" ;
c5_mode : string := "bypass" ;
c6_mode : string := "bypass" ;
c7_mode : string := "bypass" ;
c8_mode : string := "bypass" ;
c9_mode : string := "bypass" ;
l0_mode : string := "bypass" ;
l1_mode : string := "bypass" ;
g0_mode : string := "bypass" ;
g1_mode : string := "bypass" ;
g2_mode : string := "bypass" ;
g3_mode : string := "bypass" ;
e0_mode : string := "bypass" ;
e1_mode : string := "bypass" ;
e2_mode : string := "bypass" ;
e3_mode : string := "bypass" ;
c0_ph : natural := 0;
c1_ph : natural := 0;
c2_ph : natural := 0;
c3_ph : natural := 0;
c4_ph : natural := 0;
c5_ph : natural := 0;
c6_ph : natural := 0;
c7_ph : natural := 0;
c8_ph : natural := 0;
c9_ph : natural := 0;
l0_ph : natural := 0;
l1_ph : natural := 0;
g0_ph : natural := 0;
g1_ph : natural := 0;
g2_ph : natural := 0;
g3_ph : natural := 0;
e0_ph : natural := 0;
e1_ph : natural := 0;
e2_ph : natural := 0;
e3_ph : natural := 0;
m_ph : natural := 0;
l0_time_delay : natural := 0;
l1_time_delay : natural := 0;
g0_time_delay : natural := 0;
g1_time_delay : natural := 0;
g2_time_delay : natural := 0;
g3_time_delay : natural := 0;
e0_time_delay : natural := 0;
e1_time_delay : natural := 0;
e2_time_delay : natural := 0;
e3_time_delay : natural := 0;
m_time_delay : natural := 0;
n_time_delay : natural := 0;
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := 5;
c0_test_source : integer := 5;
c1_test_source : integer := 5;
c2_test_source : integer := 5;
c3_test_source : integer := 5;
c4_test_source : integer := 5;
c5_test_source : integer := 5;
c6_test_source : integer := 5;
c7_test_source : integer := 5;
c8_test_source : integer := 5;
c9_test_source : integer := 5;
extclk3_counter : string := "e3" ;
extclk2_counter : string := "e2" ;
extclk1_counter : string := "e1" ;
extclk0_counter : string := "e0" ;
clk9_counter : string := "c9" ;
clk8_counter : string := "c8" ;
clk7_counter : string := "c7" ;
clk6_counter : string := "c6" ;
clk5_counter : string := "l1" ;
clk4_counter : string := "l0" ;
clk3_counter : string := "g3" ;
clk2_counter : string := "g2" ;
clk1_counter : string := "g1" ;
clk0_counter : string := "g0" ;
enable0_counter : string := "l0";
enable1_counter : string := "l0";
charge_pump_current : natural := 2;
loop_filter_r : string := " 1.000000";
loop_filter_c : natural := 5;
vco_post_scale : natural := 0;
vco_frequency_control : string := "AUTO";
vco_phase_shift_step : natural := 0;
lpm_hint : string := "UNUSED";
lpm_type : string := "altpll";
port_clkena0 : string := "PORT_CONNECTIVITY";
port_clkena1 : string := "PORT_CONNECTIVITY";
port_clkena2 : string := "PORT_CONNECTIVITY";
port_clkena3 : string := "PORT_CONNECTIVITY";
port_clkena4 : string := "PORT_CONNECTIVITY";
port_clkena5 : string := "PORT_CONNECTIVITY";
port_extclkena0 : string := "PORT_CONNECTIVITY";
port_extclkena1 : string := "PORT_CONNECTIVITY";
port_extclkena2 : string := "PORT_CONNECTIVITY";
port_extclkena3 : string := "PORT_CONNECTIVITY";
port_extclk0 : string := "PORT_CONNECTIVITY";
port_extclk1 : string := "PORT_CONNECTIVITY";
port_extclk2 : string := "PORT_CONNECTIVITY";
port_extclk3 : string := "PORT_CONNECTIVITY";
port_clkbad0 : string := "PORT_CONNECTIVITY";
port_clkbad1 : string := "PORT_CONNECTIVITY";
port_clk0 : string := "PORT_CONNECTIVITY";
port_clk1 : string := "PORT_CONNECTIVITY";
port_clk2 : string := "PORT_CONNECTIVITY";
port_clk3 : string := "PORT_CONNECTIVITY";
port_clk4 : string := "PORT_CONNECTIVITY";
port_clk5 : string := "PORT_CONNECTIVITY";
port_clk6 : string := "PORT_CONNECTIVITY";
port_clk7 : string := "PORT_CONNECTIVITY";
port_clk8 : string := "PORT_CONNECTIVITY";
port_clk9 : string := "PORT_CONNECTIVITY";
port_scandata : string := "PORT_CONNECTIVITY";
port_scandataout : string := "PORT_CONNECTIVITY";
port_scandone : string := "PORT_CONNECTIVITY";
port_sclkout1 : string := "PORT_CONNECTIVITY";
port_sclkout0 : string := "PORT_CONNECTIVITY";
port_activeclock : string := "PORT_CONNECTIVITY";
port_clkloss : string := "PORT_CONNECTIVITY";
port_inclk1 : string := "PORT_CONNECTIVITY";
port_inclk0 : string := "PORT_CONNECTIVITY";
port_fbin : string := "PORT_CONNECTIVITY";
port_fbout : string := "PORT_CONNECTIVITY";
port_pllena : string := "PORT_CONNECTIVITY";
port_clkswitch : string := "PORT_CONNECTIVITY";
port_areset : string := "PORT_CONNECTIVITY";
port_pfdena : string := "PORT_CONNECTIVITY";
port_scanclk : string := "PORT_CONNECTIVITY";
port_scanaclr : string := "PORT_CONNECTIVITY";
port_scanread : string := "PORT_CONNECTIVITY";
port_scanwrite : string := "PORT_CONNECTIVITY";
port_enable0 : string := "PORT_CONNECTIVITY";
port_enable1 : string := "PORT_CONNECTIVITY";
port_locked : string := "PORT_CONNECTIVITY";
port_configupdate : string := "PORT_CONNECTIVITY";
port_phasecounterselect : string := "PORT_CONNECTIVITY";
port_phasedone : string := "PORT_CONNECTIVITY";
port_phasestep : string := "PORT_CONNECTIVITY";
port_phaseupdown : string := "PORT_CONNECTIVITY";
port_vcooverrange : string := "PORT_CONNECTIVITY";
port_vcounderrange : string := "PORT_CONNECTIVITY";
port_scanclkena : string := "PORT_CONNECTIVITY";
using_fbmimicbidir_port : string := "ON";
sim_gate_lock_device_behavior : string := "OFF" );
port (
inclk : in std_logic_vector(1 downto 0) := (others => '0');
fbin : in std_logic := '0';
pllena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
clkena : in std_logic_vector(5 downto 0) := (others => '1');
extclkena : in std_logic_vector(3 downto 0) := (others => '1');
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
scanaclr : in std_logic := '0';
scanread : in std_logic := '0';
scanwrite : in std_logic := '0';
scandata : in std_logic := '0';
phasecounterselect : in std_logic_vector(width_phasecounterselect-1 downto 0) := (others => '0');
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
configupdate : in std_logic := '0';
fbmimicbidir : inout std_logic := '1';
clk : out std_logic_vector(width_clock-1 downto 0);
extclk : out std_logic_vector(3 downto 0);
clkbad : out std_logic_vector(1 downto 0);
enable0 : out std_logic;
enable1 : out std_logic;
activeclock : out std_logic;
clkloss : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
sclkout0 : out std_logic;
sclkout1 : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic;
fbout : out std_logic );
end component;
component altfp_mult
generic (
width_exp : integer := 11;
width_man : integer := 31;
dedicated_multiplier_circuitry : string := "AUTO";
reduced_functionality : string := "NO";
pipeline : natural := 5;
denormal_support : string := "YES";
exception_handling : string := "YES";
lpm_hint : string := "UNUSED";
lpm_type : string := "altfp_mult" );
port (
clock : in std_logic;
clk_en : in std_logic := '1';
aclr : in std_logic := '0';
dataa : in std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ;
datab : in std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ;
result : out std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ;
overflow : out std_logic ;
underflow : out std_logic ;
zero : out std_logic ;
denormal : out std_logic ;
indefinite : out std_logic ;
nan : out std_logic );
end component;
component altsqrt
generic (
q_port_width : integer := 1;
r_port_width : integer := 1;
width : integer := 1;
pipeline : integer := 0;
lpm_hint : string := "UNUSED";
lpm_type : string := "altsqrt" );
port (
radical : in std_logic_vector(width - 1 downto 0) ;
clk : in std_logic := '1';
ena : in std_logic := '1';
aclr : in std_logic := '0';
q : out std_logic_vector( q_port_width - 1 downto 0) ;
remainder : out std_logic_vector( r_port_width - 1 downto 0) );
end component;
component parallel_add
generic (
width : natural := 4;
size : natural := 2;
widthr : natural := 4;
shift : natural := 0;
msw_subtract : string := "NO";
representation : string := "UNSIGNED";
pipeline : natural := 0;
result_alignment : string := "LSB";
lpm_hint : string := "UNUSED";
lpm_type : string := "parallel_add" );
port (
data : in altera_mf_logic_2D(size - 1 downto 0, width - 1 downto 0);
clock : in std_logic := '1';
aclr : in std_logic := '0';
clken : in std_logic := '1';
result : out std_logic_vector(widthr - 1 downto 0) );
end component;
component a_graycounter
generic (
width : natural;
pvalue : natural;
lpm_hint : string := "UNUSED";
lpm_type : string := "a_graycounter" );
port (
clock : in std_logic;
clk_en : in std_logic := '1';
cnt_en : in std_logic := '1';
updown : in std_logic := '1';
aclr : in std_logic := '0';
sclr : in std_logic := '0';
qbin : out std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0) );
end component;
component altsquare
generic (
data_width : natural;
pipeline : natural;
representation : string := "UNSIGNED";
result_alignment : string := "LSB";
result_width : natural;
lpm_hint : string := "UNUSED";
lpm_type : string := "altsquare"
);
port(
aclr : in std_logic := '0';
clock : in std_logic := '1';
data : in std_logic_vector(data_width-1 downto 0);
ena : in std_logic := '1';
result : out std_logic_vector(result_width-1 downto 0)
);
end component;
component sld_virtual_jtag
generic (
lpm_type : string;
lpm_hint : string;
sld_auto_instance_index : string;
sld_instance_index : integer;
sld_ir_width : integer;
sld_sim_n_scan : integer;
sld_sim_total_length : integer;
sld_sim_action : string);
port (
tdo : in std_logic := '0';
ir_out : in std_logic_vector(sld_ir_width - 1 downto 0) := (others => '0');
tck : out std_logic;
tdi : out std_logic;
ir_in : out std_logic_vector(sld_ir_width - 1 downto 0);
virtual_state_cdr : out std_logic;
virtual_state_sdr : out std_logic;
virtual_state_e1dr : out std_logic;
virtual_state_pdr : out std_logic;
virtual_state_e2dr : out std_logic;
virtual_state_udr : out std_logic;
virtual_state_cir : out std_logic;
virtual_state_uir : out std_logic;
jtag_state_tlr : out std_logic;
jtag_state_rti : out std_logic;
jtag_state_sdrs : out std_logic;
jtag_state_cdr : out std_logic;
jtag_state_sdr : out std_logic;
jtag_state_e1dr : out std_logic;
jtag_state_pdr : out std_logic;
jtag_state_e2dr : out std_logic;
jtag_state_udr : out std_logic;
jtag_state_sirs : out std_logic;
jtag_state_cir : out std_logic;
jtag_state_sir : out std_logic;
jtag_state_e1ir : out std_logic;
jtag_state_pir : out std_logic;
jtag_state_e2ir : out std_logic;
jtag_state_uir : out std_logic;
tms : out std_logic);
end component;
component sld_virtual_jtag_basic
generic (
lpm_type : string;
lpm_hint : string;
sld_mfg_id : natural range 0 to 2047;
sld_type_id : natural range 0 to 255;
sld_version : natural range 0 to 31;
sld_auto_instance_index : string;
sld_instance_index : integer;
sld_ir_width : integer;
sld_sim_n_scan : integer;
sld_sim_total_length : integer;
sld_sim_action : string);
port (
tdo : in std_logic := '0';
ir_out : in std_logic_vector(sld_ir_width - 1 downto 0) := (others => '0');
tck : out std_logic;
tdi : out std_logic;
ir_in : out std_logic_vector(sld_ir_width - 1 downto 0);
virtual_state_cdr : out std_logic;
virtual_state_sdr : out std_logic;
virtual_state_e1dr : out std_logic;
virtual_state_pdr : out std_logic;
virtual_state_e2dr : out std_logic;
virtual_state_udr : out std_logic;
virtual_state_cir : out std_logic;
virtual_state_uir : out std_logic;
jtag_state_tlr : out std_logic;
jtag_state_rti : out std_logic;
jtag_state_sdrs : out std_logic;
jtag_state_cdr : out std_logic;
jtag_state_sdr : out std_logic;
jtag_state_e1dr : out std_logic;
jtag_state_pdr : out std_logic;
jtag_state_e2dr : out std_logic;
jtag_state_udr : out std_logic;
jtag_state_sirs : out std_logic;
jtag_state_cir : out std_logic;
jtag_state_sir : out std_logic;
jtag_state_e1ir : out std_logic;
jtag_state_pir : out std_logic;
jtag_state_e2ir : out std_logic;
jtag_state_uir : out std_logic;
tms : out std_logic);
end component;
component altdq_dqs
generic (
delay_buffer_mode : string := "LOW";
delay_dqs_enable_by_half_cycle : string := "FALSE";
intended_device_family : string := "UNUSED";
dq_half_rate_use_dataoutbypass : string := "FALSE";
dq_input_reg_async_mode : string := "NONE";
dq_input_reg_clk_source : string := "DQS_BUS";
dq_input_reg_mode : string := "NONE";
dq_input_reg_power_up : string := "LOW";
dq_input_reg_sync_mode : string := "NONE";
dq_input_reg_use_clkn : string := "FALSE";
dq_ipa_add_input_cycle_delay : string := "FALSE";
dq_ipa_add_phase_transfer_reg : string := "FALSE";
dq_ipa_bypass_output_register : string := "FALSE";
dq_ipa_invert_phase : string := "FALSE";
dq_ipa_phase_setting : integer := 0;
dq_oe_reg_async_mode : string := "NONE";
dq_oe_reg_mode : string := "NONE";
dq_oe_reg_power_up : string := "LOW";
dq_oe_reg_sync_mode : string := "NONE";
dq_output_reg_async_mode : string := "NONE";
dq_output_reg_mode : string := "NONE";
dq_output_reg_power_up : string := "LOW";
dq_output_reg_sync_mode : string := "NONE";
dqs_ctrl_latches_enable : string := "FALSE";
dqs_delay_chain_delayctrlin_source : string := "CORE";
dqs_delay_chain_phase_setting : integer := 0;
dqs_dqsn_mode : string := "NONE";
dqs_enable_ctrl_add_phase_transfer_reg : string := "FALSE";
dqs_enable_ctrl_invert_phase : string := "FALSE";
dqs_enable_ctrl_phase_setting : integer := 0;
dqs_input_frequency : string := "UNUSED";
dqs_oe_reg_async_mode : string := "NONE";
dqs_oe_reg_mode : string := "NONE";
dqs_oe_reg_power_up : string := "LOW";
dqs_oe_reg_sync_mode : string := "NONE";
dqs_offsetctrl_enable : string := "FALSE";
dqs_output_reg_async_mode : string := "NONE";
dqs_output_reg_mode : string := "NONE";
dqs_output_reg_power_up : string := "LOW";
dqs_output_reg_sync_mode : string := "NONE";
dqs_phase_shift : integer := 0;
io_clock_divider_clk_source : string := "CORE";
io_clock_divider_invert_phase : string := "FALSE";
io_clock_divider_phase_setting : integer := 0;
level_dqs_enable : string := "FALSE";
number_of_bidir_dq : integer := 1;
number_of_clk_divider : integer := 1;
number_of_input_dq : integer := 1;
number_of_output_dq : integer := 1;
oct_reg_mode : string := "NONE";
use_dq_input_delay_chain : string := "FALSE";
use_dq_ipa : string := "FALSE";
use_dq_ipa_phasectrlin : string := "TRUE";
use_dq_oe_delay_chain1 : string := "FALSE";
use_dq_oe_delay_chain2 : string := "FALSE";
use_dq_oe_path : string := "FALSE";
use_dq_output_delay_chain1 : string := "FALSE";
use_dq_output_delay_chain2 : string := "FALSE";
use_dqs : string := "FALSE";
use_dqs_delay_chain : string := "FALSE";
use_dqs_delay_chain_phasectrlin : string := "FALSE";
use_dqs_enable : string := "FALSE";
use_dqs_enable_ctrl : string := "FALSE";
use_dqs_enable_ctrl_phasectrlin : string := "TRUE";
use_dqs_input_delay_chain : string := "FALSE";
use_dqs_input_path : string := "FALSE";
use_dqs_oe_delay_chain1 : string := "FALSE";
use_dqs_oe_delay_chain2 : string := "FALSE";
use_dqs_oe_path : string := "FALSE";
use_dqs_output_delay_chain1 : string := "FALSE";
use_dqs_output_delay_chain2 : string := "FALSE";
use_dqs_output_path : string := "FALSE";
use_dqsbusout_delay_chain : string := "FALSE";
use_dqsenable_delay_chain : string := "FALSE";
use_dynamic_oct : string := "FALSE";
use_half_rate : string := "FALSE";
use_io_clock_divider_masterin : string := "FALSE";
use_io_clock_divider_phasectrlin : string := "TRUE";
use_oct_delay_chain1 : string := "FALSE";
use_oct_delay_chain2 : string := "FALSE";
lpm_hint : string := "UNUSED";
lpm_type : string := "altdq_dqs");
port (
bidir_dq_areset : in std_logic_vector(number_of_bidir_dq - 1 downto 0) := (others => '0');
bidir_dq_hr_oct_in : in std_logic_vector(2 * number_of_bidir_dq - 1 downto 0) := (others => '0');
bidir_dq_hr_oe_in : in std_logic_vector(2 * number_of_bidir_dq - 1 downto 0) := (others => '0');
bidir_dq_hr_output_data_in : in std_logic_vector(4 * number_of_bidir_dq - 1 downto 0) := (others => '0');
bidir_dq_input_data_in : in std_logic_vector(number_of_bidir_dq - 1 downto 0) := (others => '0');
bidir_dq_io_config_ena : in std_logic_vector(number_of_bidir_dq - 1 downto 0) := (others => '1');
bidir_dq_oct_in : in std_logic_vector(number_of_bidir_dq - 1 downto 0) := (others => '0');
bidir_dq_oe_in : in std_logic_vector(number_of_bidir_dq - 1 downto 0) := (others => '0');
bidir_dq_output_data_in : in std_logic_vector(number_of_bidir_dq - 1 downto 0) := (others => '0');
bidir_dq_output_data_in_high : in std_logic_vector(number_of_bidir_dq - 1 downto 0) := (others => '0');
bidir_dq_output_data_in_low : in std_logic_vector(number_of_bidir_dq - 1 downto 0) := (others => '0');
bidir_dq_sreset : in std_logic_vector(number_of_bidir_dq - 1 downto 0) := (others => '0');
config_clk : in std_logic := '0';
config_datain : in std_logic := '0';
config_update : in std_logic := '0';
core_delayctrlin : in std_logic_vector(5 downto 0) := (others => '0');
dll_delayctrlin : in std_logic_vector(5 downto 0) := (others => '0');
dq_hr_output_reg_clk : in std_logic := '0';
dq_input_reg_clk : in std_logic := '0';
dq_input_reg_clkena : in std_logic := '1';
dq_ipa_clk : in std_logic := '0';
dq_output_reg_clk : in std_logic := '0';
dq_output_reg_clkena : in std_logic := '1';
dqs_areset : in std_logic := '0';
dqs_config_ena : in std_logic := '1';
dqs_enable_ctrl_clk : in std_logic := '1';
dqs_enable_ctrl_hr_datainhi : in std_logic := '0';
dqs_enable_ctrl_hr_datainlo : in std_logic := '0';
dqs_enable_ctrl_in : in std_logic := '1';
dqs_enable_in : in std_logic := '1';
dqs_hr_oct_in : in std_logic_vector(1 downto 0) := (others => '0');
dqs_hr_oe_in : in std_logic_vector(1 downto 0) := (others => '0');
dqs_hr_output_data_in : in std_logic_vector(3 downto 0) := (others => '0');
dqs_hr_output_reg_clk : in std_logic := '0';
dqs_input_data_in : in std_logic := '0';
dqs_io_config_ena : in std_logic := '1';
dqs_oct_in : in std_logic := '0';
dqs_oe_in : in std_logic := '0';
dqs_output_data_in : in std_logic := '0';
dqs_output_data_in_high : in std_logic := '0';
dqs_output_data_in_low : in std_logic := '0';
dqs_output_reg_clk : in std_logic := '0';
dqs_output_reg_clkena : in std_logic := '1';
dqs_sreset : in std_logic := '0';
dqsn_areset : in std_logic := '0';
dqsn_hr_oct_in : in std_logic_vector(1 downto 0) := (others => '0');
dqsn_hr_oe_in : in std_logic_vector(1 downto 0) := (others => '0');
dqsn_hr_output_data_in : in std_logic_vector(3 downto 0) := (others => '0');
dqsn_input_data_in : in std_logic := '0';
dqsn_io_config_ena : in std_logic := '1';
dqsn_oct_in : in std_logic := '0';
dqsn_oe_in : in std_logic := '0';
dqsn_output_data_in : in std_logic := '0';
dqsn_output_data_in_high : in std_logic := '0';
dqsn_output_data_in_low : in std_logic := '0';
dqsn_sreset : in std_logic := '0';
dqsupdateen : in std_logic := '0';
hr_oct_reg_clk : in std_logic := '0';
input_dq_areset : in std_logic_vector(number_of_input_dq - 1 downto 0) := (others => '0');
input_dq_hr_oct_in : in std_logic_vector(2 * number_of_input_dq - 1 downto 0) := (others => '0');
input_dq_input_data_in : in std_logic_vector(number_of_input_dq - 1 downto 0) := (others => '0');
input_dq_io_config_ena : in std_logic_vector(number_of_input_dq - 1 downto 0) := (others => '1');
input_dq_oct_in : in std_logic_vector(number_of_input_dq - 1 downto 0) := (others => '0');
input_dq_sreset : in std_logic_vector(number_of_input_dq - 1 downto 0) := (others => '0');
io_clock_divider_clk : in std_logic := '0';
io_clock_divider_masterin : in std_logic := '0';
oct_reg_clk : in std_logic := '0';
offsetctrlin : in std_logic_vector(5 downto 0) := (others => '0');
output_dq_areset : in std_logic_vector(number_of_output_dq - 1 downto 0) := (others => '0');
output_dq_hr_oct_in : in std_logic_vector(2 * number_of_output_dq - 1 downto 0) := (others => '0');
output_dq_hr_oe_in : in std_logic_vector(2 * number_of_output_dq - 1 downto 0) := (others => '0');
output_dq_hr_output_data_in : in std_logic_vector(4 * number_of_output_dq - 1 downto 0) := (others => '0');
output_dq_io_config_ena : in std_logic_vector(number_of_output_dq - 1 downto 0) := (others => '1');
output_dq_oct_in : in std_logic_vector(number_of_output_dq - 1 downto 0) := (others => '0');
output_dq_oe_in : in std_logic_vector(number_of_output_dq - 1 downto 0) := (others => '0');
output_dq_output_data_in : in std_logic_vector(number_of_output_dq - 1 downto 0) := (others => '0');
output_dq_output_data_in_high : in std_logic_vector(number_of_output_dq - 1 downto 0) := (others => '0');
output_dq_output_data_in_low : in std_logic_vector(number_of_output_dq - 1 downto 0) := (others => '0');
output_dq_sreset : in std_logic_vector(number_of_output_dq - 1 downto 0) := (others => '0');
bidir_dq_hr_input_data_out : out std_logic_vector(4 * number_of_bidir_dq - 1 downto 0);
bidir_dq_input_data_out : out std_logic_vector(number_of_bidir_dq - 1 downto 0);
bidir_dq_input_data_out_high : out std_logic_vector(number_of_bidir_dq - 1 downto 0);
bidir_dq_input_data_out_low : out std_logic_vector(number_of_bidir_dq - 1 downto 0);
bidir_dq_oct_out : out std_logic_vector(number_of_bidir_dq - 1 downto 0);
bidir_dq_oe_out : out std_logic_vector(number_of_bidir_dq - 1 downto 0);
bidir_dq_output_data_out : out std_logic_vector(number_of_bidir_dq - 1 downto 0);
dqs_bus_out : out std_logic;
dqs_input_data_out : out std_logic;
dqs_oct_out : out std_logic;
dqs_oe_out : out std_logic;
dqs_output_data_out : out std_logic;
dqsn_bus_out : out std_logic;
dqsn_input_data_out : out std_logic;
dqsn_oct_out : out std_logic;
dqsn_oe_out : out std_logic;
dqsn_output_data_out : out std_logic;
input_dq_hr_input_data_out : out std_logic_vector(4 * number_of_input_dq - 1 downto 0);
input_dq_input_data_out : out std_logic_vector(number_of_input_dq - 1 downto 0);
input_dq_input_data_out_high : out std_logic_vector(number_of_input_dq - 1 downto 0);
input_dq_input_data_out_low : out std_logic_vector(number_of_input_dq - 1 downto 0);
input_dq_oct_out : out std_logic_vector(number_of_input_dq - 1 downto 0);
io_clock_divider_clkout : out std_logic_vector(number_of_clk_divider - 1 downto 0);
io_clock_divider_slaveout : out std_logic;
output_dq_oct_out : out std_logic_vector(number_of_output_dq - 1 downto 0);
output_dq_oe_out : out std_logic_vector(number_of_output_dq - 1 downto 0);
output_dq_output_data_out : out std_logic_vector(number_of_output_dq - 1 downto 0));
end component;
component altera_std_synchronizer
generic (depth : integer := 3);
port (
clk : in std_logic;
reset_n : in std_logic;
din : in std_logic;
dout : out std_logic
);
end component;
component altera_std_synchronizer_bundle
generic (depth : integer := 3;
width : integer := 1);
port (
clk : in std_logic;
reset_n : in std_logic;
din : in std_logic_vector(width-1 downto 0);
dout : out std_logic_vector(width-1 downto 0)
);
end component;
component alt_cal
generic (
number_of_channels : integer := 1;
channel_address_width : integer := 1;
sim_model_mode : string := "TRUE";
lpm_hint : string := "UNUSED";
lpm_type : string := "alt_cal"
);
PORT
(
busy : OUT STD_LOGIC;
cal_error : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
clock : IN STD_LOGIC;
dprio_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
dprio_busy : IN STD_LOGIC;
dprio_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
dprio_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
dprio_rden : OUT STD_LOGIC;
dprio_wren : OUT STD_LOGIC;
quad_addr : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
remap_addr : IN STD_LOGIC_VECTOR (9 DOWNTO 0) := (OTHERS => '0');
reset : IN STD_LOGIC := '0';
retain_addr : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
start : IN STD_LOGIC := '0';
testbuses : IN STD_LOGIC_VECTOR (4 * number_of_channels - 1 DOWNTO 0) := (OTHERS => '0')
);
end component;
constant ELA_STATUS_BITS : natural := 4;
constant N_ELA_INSTRS : natural := 8;
constant SLD_IR_BITS : natural := N_ELA_INSTRS;
component sld_signaltap
generic (
SLD_CURRENT_RESOURCE_WIDTH : natural := 0;
SLD_INVERSION_MASK : std_logic_vector := "0";
SLD_POWER_UP_TRIGGER : natural := 0;
SLD_ADVANCED_TRIGGER_6 : string := "NONE";
SLD_ADVANCED_TRIGGER_9 : string := "NONE";
SLD_ADVANCED_TRIGGER_7 : string := "NONE";
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY : string := "basic";
SLD_STORAGE_QUALIFIER_GAP_RECORD : natural := 0;
SLD_INCREMENTAL_ROUTING : natural := 0;
SLD_STORAGE_QUALIFIER_PIPELINE : natural := 0;
SLD_TRIGGER_IN_ENABLED : natural := 0;
SLD_STATE_BITS : natural := 11;
SLD_STATE_FLOW_USE_GENERATED : natural := 0;
SLD_INVERSION_MASK_LENGTH : integer := 1;
SLD_DATA_BITS : natural := 1;
SLD_BUFFER_FULL_STOP : natural := 1;
SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH : natural := 0;
SLD_ATTRIBUTE_MEM_MODE : string := "OFF";
SLD_STORAGE_QUALIFIER_MODE : string := "OFF";
SLD_STATE_FLOW_MGR_ENTITY : string := "state_flow_mgr_entity.vhd";
SLD_NODE_CRC_LOWORD : natural := 50132;
SLD_ADVANCED_TRIGGER_5 : string := "NONE";
SLD_TRIGGER_BITS : natural := 1;
SLD_STORAGE_QUALIFIER_BITS : natural := 1;
SLD_ADVANCED_TRIGGER_10 : string := "NONE";
SLD_MEM_ADDRESS_BITS : natural := 7;
SLD_ADVANCED_TRIGGER_ENTITY : string := "basic";
SLD_ADVANCED_TRIGGER_4 : string := "NONE";
SLD_TRIGGER_LEVEL : natural := 10;
SLD_ADVANCED_TRIGGER_8 : string := "NONE";
SLD_RAM_BLOCK_TYPE : string := "AUTO";
SLD_ADVANCED_TRIGGER_2 : string := "NONE";
SLD_ADVANCED_TRIGGER_1 : string := "NONE";
SLD_DATA_BIT_CNTR_BITS : natural := 4;
lpm_type : string := "sld_signaltap";
SLD_NODE_CRC_BITS : natural := 32;
SLD_SAMPLE_DEPTH : natural := 16;
SLD_ENABLE_ADVANCED_TRIGGER : natural := 0;
SLD_SEGMENT_SIZE : natural := 0;
SLD_NODE_INFO : natural := 0;
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION : natural := 0;
SLD_NODE_CRC_HIWORD : natural := 41394;
SLD_TRIGGER_LEVEL_PIPELINE : natural := 1;
SLD_ADVANCED_TRIGGER_3 : string := "NONE"
);
port (
jtag_state_sdr : in std_logic := '0';
ir_out : out std_logic_vector(SLD_IR_BITS-1 downto 0);
jtag_state_cdr : in std_logic := '0';
ir_in : in std_logic_vector(SLD_IR_BITS-1 downto 0) := (others => '0');
tdi : in std_logic := '0';
acq_trigger_out : out std_logic_vector(SLD_TRIGGER_BITS-1 downto 0);
jtag_state_uir : in std_logic := '0';
acq_trigger_in : in std_logic_vector(SLD_TRIGGER_BITS-1 downto 0) := (others => '0');
trigger_out : out std_logic;
storage_enable : in std_logic := '0';
acq_data_out : out std_logic_vector(SLD_DATA_BITS-1 downto 0);
acq_data_in : in std_logic_vector(SLD_DATA_BITS-1 downto 0) := (others => '0');
acq_storage_qualifier_in : in std_logic_vector(SLD_STORAGE_QUALIFIER_BITS-1 downto 0) := (others => '0');
jtag_state_udr : in std_logic := '0';
tdo : out std_logic;
crc : in std_logic_vector(SLD_NODE_CRC_BITS-1 downto 0) := (others => '0');
jtag_state_e1dr : in std_logic := '0';
raw_tck : in std_logic := '0';
usr1 : in std_logic := '0';
acq_clk : in std_logic;
shift : in std_logic := '0';
ena : in std_logic := '0';
clr : in std_logic := '0';
trigger_in : in std_logic := '0';
update : in std_logic := '0';
rti : in std_logic := '0'
);
end component; --sld_signaltap
component altstratixii_oct
generic (
lpm_type : string := "altstratixii_oct"
);
port (
terminationenable : in std_logic;
terminationclock : in std_logic;
rdn : in std_logic;
rup : in std_logic
);
end component; --altstratixii_oct
constant TOP_PFL_IR_BITS : natural := 5;
constant N_FLASH_BITS : natural := 4;
component altparallel_flash_loader
generic (
flash_data_width : natural := 16;
normal_mode : natural := 1;
fifo_size : natural := 16;
safe_mode_revert : natural := 0;
dclk_divisor : natural := 1;
safe_mode_retry : natural := 1;
features_cfg : natural := 1;
burst_mode_numonyx : natural := 0;
burst_mode_intel : natural := 0;
burst_mode : natural := 0;
clk_divisor : natural := 1;
addr_width : natural := 20;
option_bits_start_address : natural := 0;
safe_mode_revert_addr : natural := 0;
enhanced_flash_programming : natural := 0;
page_mode : natural := 0;
lpm_type : string := "ALTPARALLEL_FLASH_LOADER";
features_pgm : natural := 1;
n_flash : natural := 1;
burst_mode_spansion : natural := 0;
auto_restart : STRING := "OFF";
page_clk_divisor : natural := 1;
conf_data_width : natural := 1;
TRISTATE_CHECKBOX : natural := 0;
safe_mode_halt : natural := 0
);
port (
fpga_data : out std_logic_vector(conf_data_width-1 downto 0);
fpga_dclk : out std_logic;
flash_nce : out std_logic;
fpga_nstatus : in std_logic := '0';
pfl_clk : in std_logic := '0';
fpga_nconfig : out std_logic;
flash_noe : out std_logic;
flash_nwe : out std_logic;
fpga_conf_done : in std_logic := '0';
pfl_flash_access_granted : in std_logic := '0';
pfl_nreconfigure : in std_logic := '1';
flash_nreset : out std_logic;
pfl_nreset : in std_logic := '0';
flash_data : inout std_logic_vector(flash_data_width-1 downto 0);
flash_nadv : out std_logic;
flash_clk : out std_logic;
flash_addr : out std_logic_vector(addr_width-1 downto 0);
pfl_flash_access_request : out std_logic;
fpga_pgm : in std_logic_vector(2 downto 0) := (others => '0')
);
end component; --altparallel_flash_loader
component altserial_flash_loader
generic (
enhanced_mode : natural := 0;
intended_device_family : STRING := "Cyclone";
enable_shared_access : STRING := "OFF";
lpm_type : STRING := "ALTSERIAL_FLASH_LOADER"
);
port (
noe : in std_logic := '0';
asmi_access_granted : in std_logic := '1';
sdoin : in std_logic := '0';
asmi_access_request : out std_logic;
data0out : out std_logic;
scein : in std_logic := '0';
dclkin : in std_logic := '0'
);
end component; --altserial_flash_loader
component altsource_probe
generic (
probe_width : natural := 1;
lpm_hint : string := "UNUSED";
source_width : natural := 1;
instance_id : string := "UNUSED";
sld_instance_index : natural := 0;
source_initial_value : string := "0";
sld_ir_width : natural := 4;
lpm_type : string := "altsource_probe";
sld_auto_instance_index : string := "YES";
SLD_NODE_INFO : natural := 4746752;
enable_metastability : string := "NO"
);
port (
jtag_state_sdr : in std_logic;
source : out std_logic_vector(source_width-1 downto 0);
ir_out : out std_logic_vector(sld_ir_width-1 downto 0);
jtag_state_cdr : in std_logic;
ir_in : in std_logic_vector(sld_ir_width-1 downto 0);
jtag_state_tlr : in std_logic;
tdi : in std_logic;
jtag_state_uir : in std_logic;
source_ena : in std_logic;
jtag_state_cir : in std_logic;
jtag_state_udr : in std_logic;
tdo : out std_logic;
clrn : in std_logic;
jtag_state_e1dr : in std_logic;
source_clk : in std_logic;
raw_tck : in std_logic;
usr1 : in std_logic;
ena : in std_logic;
probe : in std_logic_vector(probe_width-1 downto 0)
);
end component; --altsource_probe
end altera_mf_components;
| gpl-2.0 | 130e3f67f6d579a30758d0e663f0f75b | 0.476078 | 3.862043 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_lms_pcore_0_0/ip_design_lms_pcore_0_0_sim_netlist.vhdl | 1 | 878,119 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:39 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_lms_pcore_0_0/ip_design_lms_pcore_0_0_sim_netlist.vhdl
-- Design : ip_design_lms_pcore_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_lms_pcore_0_0_LMS is
port (
mul_temp_16 : out STD_LOGIC_VECTOR ( 15 downto 0 );
filter_sum : out STD_LOGIC_VECTOR ( 15 downto 0 );
\write_reg_x_k_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
cop_dut_enable : in STD_LOGIC;
IPCORE_CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\write_reg_d_k_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
DI : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 14 downto 0 );
\write_reg_d_k_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\write_reg_d_k_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\write_reg_d_k_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_lms_pcore_0_0_LMS : entity is "LMS";
end ip_design_lms_pcore_0_0_LMS;
architecture STRUCTURE of ip_design_lms_pcore_0_0_LMS is
signal \ARG__0_i_1_n_0\ : STD_LOGIC;
signal \ARG__0_n_100\ : STD_LOGIC;
signal \ARG__0_n_101\ : STD_LOGIC;
signal \ARG__0_n_102\ : STD_LOGIC;
signal \ARG__0_n_103\ : STD_LOGIC;
signal \ARG__0_n_104\ : STD_LOGIC;
signal \ARG__0_n_105\ : STD_LOGIC;
signal \ARG__0_n_92\ : STD_LOGIC;
signal \ARG__0_n_93\ : STD_LOGIC;
signal \ARG__0_n_94\ : STD_LOGIC;
signal \ARG__0_n_95\ : STD_LOGIC;
signal \ARG__0_n_96\ : STD_LOGIC;
signal \ARG__0_n_97\ : STD_LOGIC;
signal \ARG__0_n_98\ : STD_LOGIC;
signal \ARG__0_n_99\ : STD_LOGIC;
signal \ARG__10_i_1_n_0\ : STD_LOGIC;
signal \ARG__10_n_100\ : STD_LOGIC;
signal \ARG__10_n_101\ : STD_LOGIC;
signal \ARG__10_n_102\ : STD_LOGIC;
signal \ARG__10_n_103\ : STD_LOGIC;
signal \ARG__10_n_104\ : STD_LOGIC;
signal \ARG__10_n_105\ : STD_LOGIC;
signal \ARG__10_n_92\ : STD_LOGIC;
signal \ARG__10_n_93\ : STD_LOGIC;
signal \ARG__10_n_94\ : STD_LOGIC;
signal \ARG__10_n_95\ : STD_LOGIC;
signal \ARG__10_n_96\ : STD_LOGIC;
signal \ARG__10_n_97\ : STD_LOGIC;
signal \ARG__10_n_98\ : STD_LOGIC;
signal \ARG__10_n_99\ : STD_LOGIC;
signal \ARG__11_i_1_n_0\ : STD_LOGIC;
signal \ARG__11_n_100\ : STD_LOGIC;
signal \ARG__11_n_101\ : STD_LOGIC;
signal \ARG__11_n_102\ : STD_LOGIC;
signal \ARG__11_n_103\ : STD_LOGIC;
signal \ARG__11_n_104\ : STD_LOGIC;
signal \ARG__11_n_105\ : STD_LOGIC;
signal \ARG__11_n_76\ : STD_LOGIC;
signal \ARG__11_n_77\ : STD_LOGIC;
signal \ARG__11_n_78\ : STD_LOGIC;
signal \ARG__11_n_79\ : STD_LOGIC;
signal \ARG__11_n_80\ : STD_LOGIC;
signal \ARG__11_n_81\ : STD_LOGIC;
signal \ARG__11_n_82\ : STD_LOGIC;
signal \ARG__11_n_83\ : STD_LOGIC;
signal \ARG__11_n_84\ : STD_LOGIC;
signal \ARG__11_n_85\ : STD_LOGIC;
signal \ARG__11_n_86\ : STD_LOGIC;
signal \ARG__11_n_87\ : STD_LOGIC;
signal \ARG__11_n_88\ : STD_LOGIC;
signal \ARG__11_n_89\ : STD_LOGIC;
signal \ARG__11_n_90\ : STD_LOGIC;
signal \ARG__11_n_91\ : STD_LOGIC;
signal \ARG__11_n_92\ : STD_LOGIC;
signal \ARG__11_n_93\ : STD_LOGIC;
signal \ARG__11_n_94\ : STD_LOGIC;
signal \ARG__11_n_95\ : STD_LOGIC;
signal \ARG__11_n_96\ : STD_LOGIC;
signal \ARG__11_n_97\ : STD_LOGIC;
signal \ARG__11_n_98\ : STD_LOGIC;
signal \ARG__11_n_99\ : STD_LOGIC;
signal \ARG__12_i_1_n_0\ : STD_LOGIC;
signal \ARG__12_n_100\ : STD_LOGIC;
signal \ARG__12_n_101\ : STD_LOGIC;
signal \ARG__12_n_102\ : STD_LOGIC;
signal \ARG__12_n_103\ : STD_LOGIC;
signal \ARG__12_n_104\ : STD_LOGIC;
signal \ARG__12_n_105\ : STD_LOGIC;
signal \ARG__12_n_92\ : STD_LOGIC;
signal \ARG__12_n_93\ : STD_LOGIC;
signal \ARG__12_n_94\ : STD_LOGIC;
signal \ARG__12_n_95\ : STD_LOGIC;
signal \ARG__12_n_96\ : STD_LOGIC;
signal \ARG__12_n_97\ : STD_LOGIC;
signal \ARG__12_n_98\ : STD_LOGIC;
signal \ARG__12_n_99\ : STD_LOGIC;
signal \ARG__13_i_1_n_0\ : STD_LOGIC;
signal \ARG__13_n_100\ : STD_LOGIC;
signal \ARG__13_n_101\ : STD_LOGIC;
signal \ARG__13_n_102\ : STD_LOGIC;
signal \ARG__13_n_103\ : STD_LOGIC;
signal \ARG__13_n_104\ : STD_LOGIC;
signal \ARG__13_n_105\ : STD_LOGIC;
signal \ARG__13_n_76\ : STD_LOGIC;
signal \ARG__13_n_77\ : STD_LOGIC;
signal \ARG__13_n_78\ : STD_LOGIC;
signal \ARG__13_n_79\ : STD_LOGIC;
signal \ARG__13_n_80\ : STD_LOGIC;
signal \ARG__13_n_81\ : STD_LOGIC;
signal \ARG__13_n_82\ : STD_LOGIC;
signal \ARG__13_n_83\ : STD_LOGIC;
signal \ARG__13_n_84\ : STD_LOGIC;
signal \ARG__13_n_85\ : STD_LOGIC;
signal \ARG__13_n_86\ : STD_LOGIC;
signal \ARG__13_n_87\ : STD_LOGIC;
signal \ARG__13_n_88\ : STD_LOGIC;
signal \ARG__13_n_89\ : STD_LOGIC;
signal \ARG__13_n_90\ : STD_LOGIC;
signal \ARG__13_n_91\ : STD_LOGIC;
signal \ARG__13_n_92\ : STD_LOGIC;
signal \ARG__13_n_93\ : STD_LOGIC;
signal \ARG__13_n_94\ : STD_LOGIC;
signal \ARG__13_n_95\ : STD_LOGIC;
signal \ARG__13_n_96\ : STD_LOGIC;
signal \ARG__13_n_97\ : STD_LOGIC;
signal \ARG__13_n_98\ : STD_LOGIC;
signal \ARG__13_n_99\ : STD_LOGIC;
signal \ARG__14_i_1_n_0\ : STD_LOGIC;
signal \ARG__14_n_100\ : STD_LOGIC;
signal \ARG__14_n_101\ : STD_LOGIC;
signal \ARG__14_n_102\ : STD_LOGIC;
signal \ARG__14_n_103\ : STD_LOGIC;
signal \ARG__14_n_104\ : STD_LOGIC;
signal \ARG__14_n_105\ : STD_LOGIC;
signal \ARG__14_n_92\ : STD_LOGIC;
signal \ARG__14_n_93\ : STD_LOGIC;
signal \ARG__14_n_94\ : STD_LOGIC;
signal \ARG__14_n_95\ : STD_LOGIC;
signal \ARG__14_n_96\ : STD_LOGIC;
signal \ARG__14_n_97\ : STD_LOGIC;
signal \ARG__14_n_98\ : STD_LOGIC;
signal \ARG__14_n_99\ : STD_LOGIC;
signal \ARG__15_i_1_n_0\ : STD_LOGIC;
signal \ARG__15_n_100\ : STD_LOGIC;
signal \ARG__15_n_101\ : STD_LOGIC;
signal \ARG__15_n_102\ : STD_LOGIC;
signal \ARG__15_n_103\ : STD_LOGIC;
signal \ARG__15_n_104\ : STD_LOGIC;
signal \ARG__15_n_105\ : STD_LOGIC;
signal \ARG__15_n_76\ : STD_LOGIC;
signal \ARG__15_n_77\ : STD_LOGIC;
signal \ARG__15_n_78\ : STD_LOGIC;
signal \ARG__15_n_79\ : STD_LOGIC;
signal \ARG__15_n_80\ : STD_LOGIC;
signal \ARG__15_n_81\ : STD_LOGIC;
signal \ARG__15_n_82\ : STD_LOGIC;
signal \ARG__15_n_83\ : STD_LOGIC;
signal \ARG__15_n_84\ : STD_LOGIC;
signal \ARG__15_n_85\ : STD_LOGIC;
signal \ARG__15_n_86\ : STD_LOGIC;
signal \ARG__15_n_87\ : STD_LOGIC;
signal \ARG__15_n_88\ : STD_LOGIC;
signal \ARG__15_n_89\ : STD_LOGIC;
signal \ARG__15_n_90\ : STD_LOGIC;
signal \ARG__15_n_91\ : STD_LOGIC;
signal \ARG__15_n_92\ : STD_LOGIC;
signal \ARG__15_n_93\ : STD_LOGIC;
signal \ARG__15_n_94\ : STD_LOGIC;
signal \ARG__15_n_95\ : STD_LOGIC;
signal \ARG__15_n_96\ : STD_LOGIC;
signal \ARG__15_n_97\ : STD_LOGIC;
signal \ARG__15_n_98\ : STD_LOGIC;
signal \ARG__15_n_99\ : STD_LOGIC;
signal \ARG__16_i_1_n_0\ : STD_LOGIC;
signal \ARG__16_n_100\ : STD_LOGIC;
signal \ARG__16_n_101\ : STD_LOGIC;
signal \ARG__16_n_102\ : STD_LOGIC;
signal \ARG__16_n_103\ : STD_LOGIC;
signal \ARG__16_n_104\ : STD_LOGIC;
signal \ARG__16_n_105\ : STD_LOGIC;
signal \ARG__16_n_92\ : STD_LOGIC;
signal \ARG__16_n_93\ : STD_LOGIC;
signal \ARG__16_n_94\ : STD_LOGIC;
signal \ARG__16_n_95\ : STD_LOGIC;
signal \ARG__16_n_96\ : STD_LOGIC;
signal \ARG__16_n_97\ : STD_LOGIC;
signal \ARG__16_n_98\ : STD_LOGIC;
signal \ARG__16_n_99\ : STD_LOGIC;
signal \ARG__17_i_1_n_0\ : STD_LOGIC;
signal \ARG__17_n_100\ : STD_LOGIC;
signal \ARG__17_n_101\ : STD_LOGIC;
signal \ARG__17_n_102\ : STD_LOGIC;
signal \ARG__17_n_103\ : STD_LOGIC;
signal \ARG__17_n_104\ : STD_LOGIC;
signal \ARG__17_n_105\ : STD_LOGIC;
signal \ARG__17_n_76\ : STD_LOGIC;
signal \ARG__17_n_77\ : STD_LOGIC;
signal \ARG__17_n_78\ : STD_LOGIC;
signal \ARG__17_n_79\ : STD_LOGIC;
signal \ARG__17_n_80\ : STD_LOGIC;
signal \ARG__17_n_81\ : STD_LOGIC;
signal \ARG__17_n_82\ : STD_LOGIC;
signal \ARG__17_n_83\ : STD_LOGIC;
signal \ARG__17_n_84\ : STD_LOGIC;
signal \ARG__17_n_85\ : STD_LOGIC;
signal \ARG__17_n_86\ : STD_LOGIC;
signal \ARG__17_n_87\ : STD_LOGIC;
signal \ARG__17_n_88\ : STD_LOGIC;
signal \ARG__17_n_89\ : STD_LOGIC;
signal \ARG__17_n_90\ : STD_LOGIC;
signal \ARG__17_n_91\ : STD_LOGIC;
signal \ARG__17_n_92\ : STD_LOGIC;
signal \ARG__17_n_93\ : STD_LOGIC;
signal \ARG__17_n_94\ : STD_LOGIC;
signal \ARG__17_n_95\ : STD_LOGIC;
signal \ARG__17_n_96\ : STD_LOGIC;
signal \ARG__17_n_97\ : STD_LOGIC;
signal \ARG__17_n_98\ : STD_LOGIC;
signal \ARG__17_n_99\ : STD_LOGIC;
signal \ARG__18_i_1_n_0\ : STD_LOGIC;
signal \ARG__18_n_100\ : STD_LOGIC;
signal \ARG__18_n_101\ : STD_LOGIC;
signal \ARG__18_n_102\ : STD_LOGIC;
signal \ARG__18_n_103\ : STD_LOGIC;
signal \ARG__18_n_104\ : STD_LOGIC;
signal \ARG__18_n_105\ : STD_LOGIC;
signal \ARG__18_n_92\ : STD_LOGIC;
signal \ARG__18_n_93\ : STD_LOGIC;
signal \ARG__18_n_94\ : STD_LOGIC;
signal \ARG__18_n_95\ : STD_LOGIC;
signal \ARG__18_n_96\ : STD_LOGIC;
signal \ARG__18_n_97\ : STD_LOGIC;
signal \ARG__18_n_98\ : STD_LOGIC;
signal \ARG__18_n_99\ : STD_LOGIC;
signal \ARG__19_i_1_n_0\ : STD_LOGIC;
signal \ARG__19_n_100\ : STD_LOGIC;
signal \ARG__19_n_101\ : STD_LOGIC;
signal \ARG__19_n_102\ : STD_LOGIC;
signal \ARG__19_n_103\ : STD_LOGIC;
signal \ARG__19_n_104\ : STD_LOGIC;
signal \ARG__19_n_105\ : STD_LOGIC;
signal \ARG__19_n_76\ : STD_LOGIC;
signal \ARG__19_n_77\ : STD_LOGIC;
signal \ARG__19_n_78\ : STD_LOGIC;
signal \ARG__19_n_79\ : STD_LOGIC;
signal \ARG__19_n_80\ : STD_LOGIC;
signal \ARG__19_n_81\ : STD_LOGIC;
signal \ARG__19_n_82\ : STD_LOGIC;
signal \ARG__19_n_83\ : STD_LOGIC;
signal \ARG__19_n_84\ : STD_LOGIC;
signal \ARG__19_n_85\ : STD_LOGIC;
signal \ARG__19_n_86\ : STD_LOGIC;
signal \ARG__19_n_87\ : STD_LOGIC;
signal \ARG__19_n_88\ : STD_LOGIC;
signal \ARG__19_n_89\ : STD_LOGIC;
signal \ARG__19_n_90\ : STD_LOGIC;
signal \ARG__19_n_91\ : STD_LOGIC;
signal \ARG__19_n_92\ : STD_LOGIC;
signal \ARG__19_n_93\ : STD_LOGIC;
signal \ARG__19_n_94\ : STD_LOGIC;
signal \ARG__19_n_95\ : STD_LOGIC;
signal \ARG__19_n_96\ : STD_LOGIC;
signal \ARG__19_n_97\ : STD_LOGIC;
signal \ARG__19_n_98\ : STD_LOGIC;
signal \ARG__19_n_99\ : STD_LOGIC;
signal \ARG__1_i_1_n_0\ : STD_LOGIC;
signal \ARG__1_n_100\ : STD_LOGIC;
signal \ARG__1_n_101\ : STD_LOGIC;
signal \ARG__1_n_102\ : STD_LOGIC;
signal \ARG__1_n_103\ : STD_LOGIC;
signal \ARG__1_n_104\ : STD_LOGIC;
signal \ARG__1_n_105\ : STD_LOGIC;
signal \ARG__1_n_76\ : STD_LOGIC;
signal \ARG__1_n_77\ : STD_LOGIC;
signal \ARG__1_n_78\ : STD_LOGIC;
signal \ARG__1_n_79\ : STD_LOGIC;
signal \ARG__1_n_80\ : STD_LOGIC;
signal \ARG__1_n_81\ : STD_LOGIC;
signal \ARG__1_n_82\ : STD_LOGIC;
signal \ARG__1_n_83\ : STD_LOGIC;
signal \ARG__1_n_84\ : STD_LOGIC;
signal \ARG__1_n_85\ : STD_LOGIC;
signal \ARG__1_n_86\ : STD_LOGIC;
signal \ARG__1_n_87\ : STD_LOGIC;
signal \ARG__1_n_88\ : STD_LOGIC;
signal \ARG__1_n_89\ : STD_LOGIC;
signal \ARG__1_n_90\ : STD_LOGIC;
signal \ARG__1_n_91\ : STD_LOGIC;
signal \ARG__1_n_92\ : STD_LOGIC;
signal \ARG__1_n_93\ : STD_LOGIC;
signal \ARG__1_n_94\ : STD_LOGIC;
signal \ARG__1_n_95\ : STD_LOGIC;
signal \ARG__1_n_96\ : STD_LOGIC;
signal \ARG__1_n_97\ : STD_LOGIC;
signal \ARG__1_n_98\ : STD_LOGIC;
signal \ARG__1_n_99\ : STD_LOGIC;
signal \ARG__20_i_1_n_0\ : STD_LOGIC;
signal \ARG__20_n_100\ : STD_LOGIC;
signal \ARG__20_n_101\ : STD_LOGIC;
signal \ARG__20_n_102\ : STD_LOGIC;
signal \ARG__20_n_103\ : STD_LOGIC;
signal \ARG__20_n_104\ : STD_LOGIC;
signal \ARG__20_n_105\ : STD_LOGIC;
signal \ARG__20_n_92\ : STD_LOGIC;
signal \ARG__20_n_93\ : STD_LOGIC;
signal \ARG__20_n_94\ : STD_LOGIC;
signal \ARG__20_n_95\ : STD_LOGIC;
signal \ARG__20_n_96\ : STD_LOGIC;
signal \ARG__20_n_97\ : STD_LOGIC;
signal \ARG__20_n_98\ : STD_LOGIC;
signal \ARG__20_n_99\ : STD_LOGIC;
signal \ARG__21_i_1_n_0\ : STD_LOGIC;
signal \ARG__21_n_100\ : STD_LOGIC;
signal \ARG__21_n_101\ : STD_LOGIC;
signal \ARG__21_n_102\ : STD_LOGIC;
signal \ARG__21_n_103\ : STD_LOGIC;
signal \ARG__21_n_104\ : STD_LOGIC;
signal \ARG__21_n_105\ : STD_LOGIC;
signal \ARG__21_n_76\ : STD_LOGIC;
signal \ARG__21_n_77\ : STD_LOGIC;
signal \ARG__21_n_78\ : STD_LOGIC;
signal \ARG__21_n_79\ : STD_LOGIC;
signal \ARG__21_n_80\ : STD_LOGIC;
signal \ARG__21_n_81\ : STD_LOGIC;
signal \ARG__21_n_82\ : STD_LOGIC;
signal \ARG__21_n_83\ : STD_LOGIC;
signal \ARG__21_n_84\ : STD_LOGIC;
signal \ARG__21_n_85\ : STD_LOGIC;
signal \ARG__21_n_86\ : STD_LOGIC;
signal \ARG__21_n_87\ : STD_LOGIC;
signal \ARG__21_n_88\ : STD_LOGIC;
signal \ARG__21_n_89\ : STD_LOGIC;
signal \ARG__21_n_90\ : STD_LOGIC;
signal \ARG__21_n_91\ : STD_LOGIC;
signal \ARG__21_n_92\ : STD_LOGIC;
signal \ARG__21_n_93\ : STD_LOGIC;
signal \ARG__21_n_94\ : STD_LOGIC;
signal \ARG__21_n_95\ : STD_LOGIC;
signal \ARG__21_n_96\ : STD_LOGIC;
signal \ARG__21_n_97\ : STD_LOGIC;
signal \ARG__21_n_98\ : STD_LOGIC;
signal \ARG__21_n_99\ : STD_LOGIC;
signal \ARG__22_i_1_n_0\ : STD_LOGIC;
signal \ARG__22_n_100\ : STD_LOGIC;
signal \ARG__22_n_101\ : STD_LOGIC;
signal \ARG__22_n_102\ : STD_LOGIC;
signal \ARG__22_n_103\ : STD_LOGIC;
signal \ARG__22_n_104\ : STD_LOGIC;
signal \ARG__22_n_105\ : STD_LOGIC;
signal \ARG__22_n_92\ : STD_LOGIC;
signal \ARG__22_n_93\ : STD_LOGIC;
signal \ARG__22_n_94\ : STD_LOGIC;
signal \ARG__22_n_95\ : STD_LOGIC;
signal \ARG__22_n_96\ : STD_LOGIC;
signal \ARG__22_n_97\ : STD_LOGIC;
signal \ARG__22_n_98\ : STD_LOGIC;
signal \ARG__22_n_99\ : STD_LOGIC;
signal \ARG__23_i_1_n_0\ : STD_LOGIC;
signal \ARG__23_n_100\ : STD_LOGIC;
signal \ARG__23_n_101\ : STD_LOGIC;
signal \ARG__23_n_102\ : STD_LOGIC;
signal \ARG__23_n_103\ : STD_LOGIC;
signal \ARG__23_n_104\ : STD_LOGIC;
signal \ARG__23_n_105\ : STD_LOGIC;
signal \ARG__23_n_76\ : STD_LOGIC;
signal \ARG__23_n_77\ : STD_LOGIC;
signal \ARG__23_n_78\ : STD_LOGIC;
signal \ARG__23_n_79\ : STD_LOGIC;
signal \ARG__23_n_80\ : STD_LOGIC;
signal \ARG__23_n_81\ : STD_LOGIC;
signal \ARG__23_n_82\ : STD_LOGIC;
signal \ARG__23_n_83\ : STD_LOGIC;
signal \ARG__23_n_84\ : STD_LOGIC;
signal \ARG__23_n_85\ : STD_LOGIC;
signal \ARG__23_n_86\ : STD_LOGIC;
signal \ARG__23_n_87\ : STD_LOGIC;
signal \ARG__23_n_88\ : STD_LOGIC;
signal \ARG__23_n_89\ : STD_LOGIC;
signal \ARG__23_n_90\ : STD_LOGIC;
signal \ARG__23_n_91\ : STD_LOGIC;
signal \ARG__23_n_92\ : STD_LOGIC;
signal \ARG__23_n_93\ : STD_LOGIC;
signal \ARG__23_n_94\ : STD_LOGIC;
signal \ARG__23_n_95\ : STD_LOGIC;
signal \ARG__23_n_96\ : STD_LOGIC;
signal \ARG__23_n_97\ : STD_LOGIC;
signal \ARG__23_n_98\ : STD_LOGIC;
signal \ARG__23_n_99\ : STD_LOGIC;
signal \ARG__24_i_1_n_0\ : STD_LOGIC;
signal \ARG__24_n_100\ : STD_LOGIC;
signal \ARG__24_n_101\ : STD_LOGIC;
signal \ARG__24_n_102\ : STD_LOGIC;
signal \ARG__24_n_103\ : STD_LOGIC;
signal \ARG__24_n_104\ : STD_LOGIC;
signal \ARG__24_n_105\ : STD_LOGIC;
signal \ARG__24_n_92\ : STD_LOGIC;
signal \ARG__24_n_93\ : STD_LOGIC;
signal \ARG__24_n_94\ : STD_LOGIC;
signal \ARG__24_n_95\ : STD_LOGIC;
signal \ARG__24_n_96\ : STD_LOGIC;
signal \ARG__24_n_97\ : STD_LOGIC;
signal \ARG__24_n_98\ : STD_LOGIC;
signal \ARG__24_n_99\ : STD_LOGIC;
signal \ARG__25_i_1_n_0\ : STD_LOGIC;
signal \ARG__25_n_100\ : STD_LOGIC;
signal \ARG__25_n_101\ : STD_LOGIC;
signal \ARG__25_n_102\ : STD_LOGIC;
signal \ARG__25_n_103\ : STD_LOGIC;
signal \ARG__25_n_104\ : STD_LOGIC;
signal \ARG__25_n_105\ : STD_LOGIC;
signal \ARG__25_n_76\ : STD_LOGIC;
signal \ARG__25_n_77\ : STD_LOGIC;
signal \ARG__25_n_78\ : STD_LOGIC;
signal \ARG__25_n_79\ : STD_LOGIC;
signal \ARG__25_n_80\ : STD_LOGIC;
signal \ARG__25_n_81\ : STD_LOGIC;
signal \ARG__25_n_82\ : STD_LOGIC;
signal \ARG__25_n_83\ : STD_LOGIC;
signal \ARG__25_n_84\ : STD_LOGIC;
signal \ARG__25_n_85\ : STD_LOGIC;
signal \ARG__25_n_86\ : STD_LOGIC;
signal \ARG__25_n_87\ : STD_LOGIC;
signal \ARG__25_n_88\ : STD_LOGIC;
signal \ARG__25_n_89\ : STD_LOGIC;
signal \ARG__25_n_90\ : STD_LOGIC;
signal \ARG__25_n_91\ : STD_LOGIC;
signal \ARG__25_n_92\ : STD_LOGIC;
signal \ARG__25_n_93\ : STD_LOGIC;
signal \ARG__25_n_94\ : STD_LOGIC;
signal \ARG__25_n_95\ : STD_LOGIC;
signal \ARG__25_n_96\ : STD_LOGIC;
signal \ARG__25_n_97\ : STD_LOGIC;
signal \ARG__25_n_98\ : STD_LOGIC;
signal \ARG__25_n_99\ : STD_LOGIC;
signal \ARG__26_i_1_n_0\ : STD_LOGIC;
signal \ARG__26_n_100\ : STD_LOGIC;
signal \ARG__26_n_101\ : STD_LOGIC;
signal \ARG__26_n_102\ : STD_LOGIC;
signal \ARG__26_n_103\ : STD_LOGIC;
signal \ARG__26_n_104\ : STD_LOGIC;
signal \ARG__26_n_105\ : STD_LOGIC;
signal \ARG__26_n_92\ : STD_LOGIC;
signal \ARG__26_n_93\ : STD_LOGIC;
signal \ARG__26_n_94\ : STD_LOGIC;
signal \ARG__26_n_95\ : STD_LOGIC;
signal \ARG__26_n_96\ : STD_LOGIC;
signal \ARG__26_n_97\ : STD_LOGIC;
signal \ARG__26_n_98\ : STD_LOGIC;
signal \ARG__26_n_99\ : STD_LOGIC;
signal \ARG__27_i_1_n_0\ : STD_LOGIC;
signal \ARG__27_n_100\ : STD_LOGIC;
signal \ARG__27_n_101\ : STD_LOGIC;
signal \ARG__27_n_102\ : STD_LOGIC;
signal \ARG__27_n_103\ : STD_LOGIC;
signal \ARG__27_n_104\ : STD_LOGIC;
signal \ARG__27_n_105\ : STD_LOGIC;
signal \ARG__27_n_76\ : STD_LOGIC;
signal \ARG__27_n_77\ : STD_LOGIC;
signal \ARG__27_n_78\ : STD_LOGIC;
signal \ARG__27_n_79\ : STD_LOGIC;
signal \ARG__27_n_80\ : STD_LOGIC;
signal \ARG__27_n_81\ : STD_LOGIC;
signal \ARG__27_n_82\ : STD_LOGIC;
signal \ARG__27_n_83\ : STD_LOGIC;
signal \ARG__27_n_84\ : STD_LOGIC;
signal \ARG__27_n_85\ : STD_LOGIC;
signal \ARG__27_n_86\ : STD_LOGIC;
signal \ARG__27_n_87\ : STD_LOGIC;
signal \ARG__27_n_88\ : STD_LOGIC;
signal \ARG__27_n_89\ : STD_LOGIC;
signal \ARG__27_n_90\ : STD_LOGIC;
signal \ARG__27_n_91\ : STD_LOGIC;
signal \ARG__27_n_92\ : STD_LOGIC;
signal \ARG__27_n_93\ : STD_LOGIC;
signal \ARG__27_n_94\ : STD_LOGIC;
signal \ARG__27_n_95\ : STD_LOGIC;
signal \ARG__27_n_96\ : STD_LOGIC;
signal \ARG__27_n_97\ : STD_LOGIC;
signal \ARG__27_n_98\ : STD_LOGIC;
signal \ARG__27_n_99\ : STD_LOGIC;
signal \ARG__28_i_1_n_0\ : STD_LOGIC;
signal \ARG__28_n_100\ : STD_LOGIC;
signal \ARG__28_n_101\ : STD_LOGIC;
signal \ARG__28_n_102\ : STD_LOGIC;
signal \ARG__28_n_103\ : STD_LOGIC;
signal \ARG__28_n_104\ : STD_LOGIC;
signal \ARG__28_n_105\ : STD_LOGIC;
signal \ARG__28_n_92\ : STD_LOGIC;
signal \ARG__28_n_93\ : STD_LOGIC;
signal \ARG__28_n_94\ : STD_LOGIC;
signal \ARG__28_n_95\ : STD_LOGIC;
signal \ARG__28_n_96\ : STD_LOGIC;
signal \ARG__28_n_97\ : STD_LOGIC;
signal \ARG__28_n_98\ : STD_LOGIC;
signal \ARG__28_n_99\ : STD_LOGIC;
signal \ARG__29_i_1_n_0\ : STD_LOGIC;
signal \ARG__29_n_100\ : STD_LOGIC;
signal \ARG__29_n_101\ : STD_LOGIC;
signal \ARG__29_n_102\ : STD_LOGIC;
signal \ARG__29_n_103\ : STD_LOGIC;
signal \ARG__29_n_104\ : STD_LOGIC;
signal \ARG__29_n_105\ : STD_LOGIC;
signal \ARG__29_n_76\ : STD_LOGIC;
signal \ARG__29_n_77\ : STD_LOGIC;
signal \ARG__29_n_78\ : STD_LOGIC;
signal \ARG__29_n_79\ : STD_LOGIC;
signal \ARG__29_n_80\ : STD_LOGIC;
signal \ARG__29_n_81\ : STD_LOGIC;
signal \ARG__29_n_82\ : STD_LOGIC;
signal \ARG__29_n_83\ : STD_LOGIC;
signal \ARG__29_n_84\ : STD_LOGIC;
signal \ARG__29_n_85\ : STD_LOGIC;
signal \ARG__29_n_86\ : STD_LOGIC;
signal \ARG__29_n_87\ : STD_LOGIC;
signal \ARG__29_n_88\ : STD_LOGIC;
signal \ARG__29_n_89\ : STD_LOGIC;
signal \ARG__29_n_90\ : STD_LOGIC;
signal \ARG__29_n_91\ : STD_LOGIC;
signal \ARG__29_n_92\ : STD_LOGIC;
signal \ARG__29_n_93\ : STD_LOGIC;
signal \ARG__29_n_94\ : STD_LOGIC;
signal \ARG__29_n_95\ : STD_LOGIC;
signal \ARG__29_n_96\ : STD_LOGIC;
signal \ARG__29_n_97\ : STD_LOGIC;
signal \ARG__29_n_98\ : STD_LOGIC;
signal \ARG__29_n_99\ : STD_LOGIC;
signal \ARG__2_i_1_n_0\ : STD_LOGIC;
signal \ARG__2_n_100\ : STD_LOGIC;
signal \ARG__2_n_101\ : STD_LOGIC;
signal \ARG__2_n_102\ : STD_LOGIC;
signal \ARG__2_n_103\ : STD_LOGIC;
signal \ARG__2_n_104\ : STD_LOGIC;
signal \ARG__2_n_105\ : STD_LOGIC;
signal \ARG__2_n_92\ : STD_LOGIC;
signal \ARG__2_n_93\ : STD_LOGIC;
signal \ARG__2_n_94\ : STD_LOGIC;
signal \ARG__2_n_95\ : STD_LOGIC;
signal \ARG__2_n_96\ : STD_LOGIC;
signal \ARG__2_n_97\ : STD_LOGIC;
signal \ARG__2_n_98\ : STD_LOGIC;
signal \ARG__2_n_99\ : STD_LOGIC;
signal \ARG__30_i_1_n_0\ : STD_LOGIC;
signal \ARG__30_n_100\ : STD_LOGIC;
signal \ARG__30_n_101\ : STD_LOGIC;
signal \ARG__30_n_102\ : STD_LOGIC;
signal \ARG__30_n_103\ : STD_LOGIC;
signal \ARG__30_n_104\ : STD_LOGIC;
signal \ARG__30_n_105\ : STD_LOGIC;
signal \ARG__30_n_92\ : STD_LOGIC;
signal \ARG__30_n_93\ : STD_LOGIC;
signal \ARG__30_n_94\ : STD_LOGIC;
signal \ARG__30_n_95\ : STD_LOGIC;
signal \ARG__30_n_96\ : STD_LOGIC;
signal \ARG__30_n_97\ : STD_LOGIC;
signal \ARG__30_n_98\ : STD_LOGIC;
signal \ARG__30_n_99\ : STD_LOGIC;
signal \ARG__31\ : STD_LOGIC_VECTOR ( 32 downto 17 );
signal \ARG__3_i_1_n_0\ : STD_LOGIC;
signal \ARG__3_n_100\ : STD_LOGIC;
signal \ARG__3_n_101\ : STD_LOGIC;
signal \ARG__3_n_102\ : STD_LOGIC;
signal \ARG__3_n_103\ : STD_LOGIC;
signal \ARG__3_n_104\ : STD_LOGIC;
signal \ARG__3_n_105\ : STD_LOGIC;
signal \ARG__3_n_76\ : STD_LOGIC;
signal \ARG__3_n_77\ : STD_LOGIC;
signal \ARG__3_n_78\ : STD_LOGIC;
signal \ARG__3_n_79\ : STD_LOGIC;
signal \ARG__3_n_80\ : STD_LOGIC;
signal \ARG__3_n_81\ : STD_LOGIC;
signal \ARG__3_n_82\ : STD_LOGIC;
signal \ARG__3_n_83\ : STD_LOGIC;
signal \ARG__3_n_84\ : STD_LOGIC;
signal \ARG__3_n_85\ : STD_LOGIC;
signal \ARG__3_n_86\ : STD_LOGIC;
signal \ARG__3_n_87\ : STD_LOGIC;
signal \ARG__3_n_88\ : STD_LOGIC;
signal \ARG__3_n_89\ : STD_LOGIC;
signal \ARG__3_n_90\ : STD_LOGIC;
signal \ARG__3_n_91\ : STD_LOGIC;
signal \ARG__3_n_92\ : STD_LOGIC;
signal \ARG__3_n_93\ : STD_LOGIC;
signal \ARG__3_n_94\ : STD_LOGIC;
signal \ARG__3_n_95\ : STD_LOGIC;
signal \ARG__3_n_96\ : STD_LOGIC;
signal \ARG__3_n_97\ : STD_LOGIC;
signal \ARG__3_n_98\ : STD_LOGIC;
signal \ARG__3_n_99\ : STD_LOGIC;
signal \ARG__4_i_1_n_0\ : STD_LOGIC;
signal \ARG__4_n_100\ : STD_LOGIC;
signal \ARG__4_n_101\ : STD_LOGIC;
signal \ARG__4_n_102\ : STD_LOGIC;
signal \ARG__4_n_103\ : STD_LOGIC;
signal \ARG__4_n_104\ : STD_LOGIC;
signal \ARG__4_n_105\ : STD_LOGIC;
signal \ARG__4_n_92\ : STD_LOGIC;
signal \ARG__4_n_93\ : STD_LOGIC;
signal \ARG__4_n_94\ : STD_LOGIC;
signal \ARG__4_n_95\ : STD_LOGIC;
signal \ARG__4_n_96\ : STD_LOGIC;
signal \ARG__4_n_97\ : STD_LOGIC;
signal \ARG__4_n_98\ : STD_LOGIC;
signal \ARG__4_n_99\ : STD_LOGIC;
signal \ARG__5_i_1_n_0\ : STD_LOGIC;
signal \ARG__5_n_100\ : STD_LOGIC;
signal \ARG__5_n_101\ : STD_LOGIC;
signal \ARG__5_n_102\ : STD_LOGIC;
signal \ARG__5_n_103\ : STD_LOGIC;
signal \ARG__5_n_104\ : STD_LOGIC;
signal \ARG__5_n_105\ : STD_LOGIC;
signal \ARG__5_n_76\ : STD_LOGIC;
signal \ARG__5_n_77\ : STD_LOGIC;
signal \ARG__5_n_78\ : STD_LOGIC;
signal \ARG__5_n_79\ : STD_LOGIC;
signal \ARG__5_n_80\ : STD_LOGIC;
signal \ARG__5_n_81\ : STD_LOGIC;
signal \ARG__5_n_82\ : STD_LOGIC;
signal \ARG__5_n_83\ : STD_LOGIC;
signal \ARG__5_n_84\ : STD_LOGIC;
signal \ARG__5_n_85\ : STD_LOGIC;
signal \ARG__5_n_86\ : STD_LOGIC;
signal \ARG__5_n_87\ : STD_LOGIC;
signal \ARG__5_n_88\ : STD_LOGIC;
signal \ARG__5_n_89\ : STD_LOGIC;
signal \ARG__5_n_90\ : STD_LOGIC;
signal \ARG__5_n_91\ : STD_LOGIC;
signal \ARG__5_n_92\ : STD_LOGIC;
signal \ARG__5_n_93\ : STD_LOGIC;
signal \ARG__5_n_94\ : STD_LOGIC;
signal \ARG__5_n_95\ : STD_LOGIC;
signal \ARG__5_n_96\ : STD_LOGIC;
signal \ARG__5_n_97\ : STD_LOGIC;
signal \ARG__5_n_98\ : STD_LOGIC;
signal \ARG__5_n_99\ : STD_LOGIC;
signal \ARG__6_i_1_n_0\ : STD_LOGIC;
signal \ARG__6_n_100\ : STD_LOGIC;
signal \ARG__6_n_101\ : STD_LOGIC;
signal \ARG__6_n_102\ : STD_LOGIC;
signal \ARG__6_n_103\ : STD_LOGIC;
signal \ARG__6_n_104\ : STD_LOGIC;
signal \ARG__6_n_105\ : STD_LOGIC;
signal \ARG__6_n_92\ : STD_LOGIC;
signal \ARG__6_n_93\ : STD_LOGIC;
signal \ARG__6_n_94\ : STD_LOGIC;
signal \ARG__6_n_95\ : STD_LOGIC;
signal \ARG__6_n_96\ : STD_LOGIC;
signal \ARG__6_n_97\ : STD_LOGIC;
signal \ARG__6_n_98\ : STD_LOGIC;
signal \ARG__6_n_99\ : STD_LOGIC;
signal \ARG__7_i_1_n_0\ : STD_LOGIC;
signal \ARG__7_n_100\ : STD_LOGIC;
signal \ARG__7_n_101\ : STD_LOGIC;
signal \ARG__7_n_102\ : STD_LOGIC;
signal \ARG__7_n_103\ : STD_LOGIC;
signal \ARG__7_n_104\ : STD_LOGIC;
signal \ARG__7_n_105\ : STD_LOGIC;
signal \ARG__7_n_76\ : STD_LOGIC;
signal \ARG__7_n_77\ : STD_LOGIC;
signal \ARG__7_n_78\ : STD_LOGIC;
signal \ARG__7_n_79\ : STD_LOGIC;
signal \ARG__7_n_80\ : STD_LOGIC;
signal \ARG__7_n_81\ : STD_LOGIC;
signal \ARG__7_n_82\ : STD_LOGIC;
signal \ARG__7_n_83\ : STD_LOGIC;
signal \ARG__7_n_84\ : STD_LOGIC;
signal \ARG__7_n_85\ : STD_LOGIC;
signal \ARG__7_n_86\ : STD_LOGIC;
signal \ARG__7_n_87\ : STD_LOGIC;
signal \ARG__7_n_88\ : STD_LOGIC;
signal \ARG__7_n_89\ : STD_LOGIC;
signal \ARG__7_n_90\ : STD_LOGIC;
signal \ARG__7_n_91\ : STD_LOGIC;
signal \ARG__7_n_92\ : STD_LOGIC;
signal \ARG__7_n_93\ : STD_LOGIC;
signal \ARG__7_n_94\ : STD_LOGIC;
signal \ARG__7_n_95\ : STD_LOGIC;
signal \ARG__7_n_96\ : STD_LOGIC;
signal \ARG__7_n_97\ : STD_LOGIC;
signal \ARG__7_n_98\ : STD_LOGIC;
signal \ARG__7_n_99\ : STD_LOGIC;
signal \ARG__8_i_1_n_0\ : STD_LOGIC;
signal \ARG__8_n_100\ : STD_LOGIC;
signal \ARG__8_n_101\ : STD_LOGIC;
signal \ARG__8_n_102\ : STD_LOGIC;
signal \ARG__8_n_103\ : STD_LOGIC;
signal \ARG__8_n_104\ : STD_LOGIC;
signal \ARG__8_n_105\ : STD_LOGIC;
signal \ARG__8_n_92\ : STD_LOGIC;
signal \ARG__8_n_93\ : STD_LOGIC;
signal \ARG__8_n_94\ : STD_LOGIC;
signal \ARG__8_n_95\ : STD_LOGIC;
signal \ARG__8_n_96\ : STD_LOGIC;
signal \ARG__8_n_97\ : STD_LOGIC;
signal \ARG__8_n_98\ : STD_LOGIC;
signal \ARG__8_n_99\ : STD_LOGIC;
signal \ARG__9_i_1_n_0\ : STD_LOGIC;
signal \ARG__9_n_100\ : STD_LOGIC;
signal \ARG__9_n_101\ : STD_LOGIC;
signal \ARG__9_n_102\ : STD_LOGIC;
signal \ARG__9_n_103\ : STD_LOGIC;
signal \ARG__9_n_104\ : STD_LOGIC;
signal \ARG__9_n_105\ : STD_LOGIC;
signal \ARG__9_n_76\ : STD_LOGIC;
signal \ARG__9_n_77\ : STD_LOGIC;
signal \ARG__9_n_78\ : STD_LOGIC;
signal \ARG__9_n_79\ : STD_LOGIC;
signal \ARG__9_n_80\ : STD_LOGIC;
signal \ARG__9_n_81\ : STD_LOGIC;
signal \ARG__9_n_82\ : STD_LOGIC;
signal \ARG__9_n_83\ : STD_LOGIC;
signal \ARG__9_n_84\ : STD_LOGIC;
signal \ARG__9_n_85\ : STD_LOGIC;
signal \ARG__9_n_86\ : STD_LOGIC;
signal \ARG__9_n_87\ : STD_LOGIC;
signal \ARG__9_n_88\ : STD_LOGIC;
signal \ARG__9_n_89\ : STD_LOGIC;
signal \ARG__9_n_90\ : STD_LOGIC;
signal \ARG__9_n_91\ : STD_LOGIC;
signal \ARG__9_n_92\ : STD_LOGIC;
signal \ARG__9_n_93\ : STD_LOGIC;
signal \ARG__9_n_94\ : STD_LOGIC;
signal \ARG__9_n_95\ : STD_LOGIC;
signal \ARG__9_n_96\ : STD_LOGIC;
signal \ARG__9_n_97\ : STD_LOGIC;
signal \ARG__9_n_98\ : STD_LOGIC;
signal \ARG__9_n_99\ : STD_LOGIC;
signal \ARG_carry__0_i_2_n_0\ : STD_LOGIC;
signal \ARG_carry__0_i_3_n_0\ : STD_LOGIC;
signal \ARG_carry__0_i_4_n_0\ : STD_LOGIC;
signal \ARG_carry__0_n_0\ : STD_LOGIC;
signal \ARG_carry__0_n_1\ : STD_LOGIC;
signal \ARG_carry__0_n_2\ : STD_LOGIC;
signal \ARG_carry__0_n_3\ : STD_LOGIC;
signal \ARG_carry__1_i_1_n_0\ : STD_LOGIC;
signal \ARG_carry__1_i_2_n_0\ : STD_LOGIC;
signal \ARG_carry__1_i_3_n_0\ : STD_LOGIC;
signal \ARG_carry__1_i_4_n_0\ : STD_LOGIC;
signal \ARG_carry__1_n_0\ : STD_LOGIC;
signal \ARG_carry__1_n_1\ : STD_LOGIC;
signal \ARG_carry__1_n_2\ : STD_LOGIC;
signal \ARG_carry__1_n_3\ : STD_LOGIC;
signal \ARG_carry__2_i_1_n_0\ : STD_LOGIC;
signal \ARG_carry__2_i_2_n_0\ : STD_LOGIC;
signal \ARG_carry__2_i_3_n_0\ : STD_LOGIC;
signal \ARG_carry__2_i_4_n_0\ : STD_LOGIC;
signal \ARG_carry__2_n_0\ : STD_LOGIC;
signal \ARG_carry__2_n_1\ : STD_LOGIC;
signal \ARG_carry__2_n_2\ : STD_LOGIC;
signal \ARG_carry__2_n_3\ : STD_LOGIC;
signal \ARG_carry__3_i_1_n_0\ : STD_LOGIC;
signal \ARG_carry__3_n_3\ : STD_LOGIC;
signal ARG_carry_n_0 : STD_LOGIC;
signal ARG_carry_n_1 : STD_LOGIC;
signal ARG_carry_n_2 : STD_LOGIC;
signal ARG_carry_n_3 : STD_LOGIC;
signal ARG_i_1_n_0 : STD_LOGIC;
signal ARG_n_100 : STD_LOGIC;
signal ARG_n_101 : STD_LOGIC;
signal ARG_n_102 : STD_LOGIC;
signal ARG_n_103 : STD_LOGIC;
signal ARG_n_104 : STD_LOGIC;
signal ARG_n_105 : STD_LOGIC;
signal ARG_n_92 : STD_LOGIC;
signal ARG_n_93 : STD_LOGIC;
signal ARG_n_94 : STD_LOGIC;
signal ARG_n_95 : STD_LOGIC;
signal ARG_n_96 : STD_LOGIC;
signal ARG_n_97 : STD_LOGIC;
signal ARG_n_98 : STD_LOGIC;
signal ARG_n_99 : STD_LOGIC;
signal RESIZE15 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE16 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE18 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE20 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE22 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE24 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE26 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE28 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE30 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE32 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE34 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE36 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE38 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE40 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE42 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE44 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \add_temp_14__0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_10_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_11_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_12_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_9_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_10_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_11_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_12_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_9_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_10_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_11_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_9_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_10_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_9_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__278_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__278_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_7\ : STD_LOGIC;
signal \data_pipeline_tmp_reg[0]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[10]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[11]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[12]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[13]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[14]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[1]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[2]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[3]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[4]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[5]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[6]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[7]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[8]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[9]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \in\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^mul_temp\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mul_temp_1\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mul_temp_10\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_10_n_100 : STD_LOGIC;
signal mul_temp_10_n_101 : STD_LOGIC;
signal mul_temp_10_n_102 : STD_LOGIC;
signal mul_temp_10_n_103 : STD_LOGIC;
signal mul_temp_10_n_104 : STD_LOGIC;
signal mul_temp_10_n_105 : STD_LOGIC;
signal mul_temp_10_n_74 : STD_LOGIC;
signal mul_temp_10_n_75 : STD_LOGIC;
signal mul_temp_10_n_76 : STD_LOGIC;
signal mul_temp_10_n_77 : STD_LOGIC;
signal mul_temp_10_n_78 : STD_LOGIC;
signal mul_temp_10_n_79 : STD_LOGIC;
signal mul_temp_10_n_80 : STD_LOGIC;
signal mul_temp_10_n_81 : STD_LOGIC;
signal mul_temp_10_n_82 : STD_LOGIC;
signal mul_temp_10_n_83 : STD_LOGIC;
signal mul_temp_10_n_84 : STD_LOGIC;
signal mul_temp_10_n_85 : STD_LOGIC;
signal mul_temp_10_n_86 : STD_LOGIC;
signal mul_temp_10_n_87 : STD_LOGIC;
signal mul_temp_10_n_88 : STD_LOGIC;
signal mul_temp_10_n_89 : STD_LOGIC;
signal mul_temp_10_n_90 : STD_LOGIC;
signal mul_temp_10_n_92 : STD_LOGIC;
signal mul_temp_10_n_93 : STD_LOGIC;
signal mul_temp_10_n_94 : STD_LOGIC;
signal mul_temp_10_n_95 : STD_LOGIC;
signal mul_temp_10_n_96 : STD_LOGIC;
signal mul_temp_10_n_97 : STD_LOGIC;
signal mul_temp_10_n_98 : STD_LOGIC;
signal mul_temp_10_n_99 : STD_LOGIC;
signal \^mul_temp_11\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_11_n_100 : STD_LOGIC;
signal mul_temp_11_n_101 : STD_LOGIC;
signal mul_temp_11_n_102 : STD_LOGIC;
signal mul_temp_11_n_103 : STD_LOGIC;
signal mul_temp_11_n_104 : STD_LOGIC;
signal mul_temp_11_n_105 : STD_LOGIC;
signal mul_temp_11_n_74 : STD_LOGIC;
signal mul_temp_11_n_75 : STD_LOGIC;
signal mul_temp_11_n_76 : STD_LOGIC;
signal mul_temp_11_n_77 : STD_LOGIC;
signal mul_temp_11_n_78 : STD_LOGIC;
signal mul_temp_11_n_79 : STD_LOGIC;
signal mul_temp_11_n_80 : STD_LOGIC;
signal mul_temp_11_n_81 : STD_LOGIC;
signal mul_temp_11_n_82 : STD_LOGIC;
signal mul_temp_11_n_83 : STD_LOGIC;
signal mul_temp_11_n_84 : STD_LOGIC;
signal mul_temp_11_n_85 : STD_LOGIC;
signal mul_temp_11_n_86 : STD_LOGIC;
signal mul_temp_11_n_87 : STD_LOGIC;
signal mul_temp_11_n_88 : STD_LOGIC;
signal mul_temp_11_n_89 : STD_LOGIC;
signal mul_temp_11_n_90 : STD_LOGIC;
signal mul_temp_11_n_92 : STD_LOGIC;
signal mul_temp_11_n_93 : STD_LOGIC;
signal mul_temp_11_n_94 : STD_LOGIC;
signal mul_temp_11_n_95 : STD_LOGIC;
signal mul_temp_11_n_96 : STD_LOGIC;
signal mul_temp_11_n_97 : STD_LOGIC;
signal mul_temp_11_n_98 : STD_LOGIC;
signal mul_temp_11_n_99 : STD_LOGIC;
signal \^mul_temp_12\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_12_n_100 : STD_LOGIC;
signal mul_temp_12_n_101 : STD_LOGIC;
signal mul_temp_12_n_102 : STD_LOGIC;
signal mul_temp_12_n_103 : STD_LOGIC;
signal mul_temp_12_n_104 : STD_LOGIC;
signal mul_temp_12_n_105 : STD_LOGIC;
signal mul_temp_12_n_74 : STD_LOGIC;
signal mul_temp_12_n_75 : STD_LOGIC;
signal mul_temp_12_n_76 : STD_LOGIC;
signal mul_temp_12_n_77 : STD_LOGIC;
signal mul_temp_12_n_78 : STD_LOGIC;
signal mul_temp_12_n_79 : STD_LOGIC;
signal mul_temp_12_n_80 : STD_LOGIC;
signal mul_temp_12_n_81 : STD_LOGIC;
signal mul_temp_12_n_82 : STD_LOGIC;
signal mul_temp_12_n_83 : STD_LOGIC;
signal mul_temp_12_n_84 : STD_LOGIC;
signal mul_temp_12_n_85 : STD_LOGIC;
signal mul_temp_12_n_86 : STD_LOGIC;
signal mul_temp_12_n_87 : STD_LOGIC;
signal mul_temp_12_n_88 : STD_LOGIC;
signal mul_temp_12_n_89 : STD_LOGIC;
signal mul_temp_12_n_90 : STD_LOGIC;
signal mul_temp_12_n_92 : STD_LOGIC;
signal mul_temp_12_n_93 : STD_LOGIC;
signal mul_temp_12_n_94 : STD_LOGIC;
signal mul_temp_12_n_95 : STD_LOGIC;
signal mul_temp_12_n_96 : STD_LOGIC;
signal mul_temp_12_n_97 : STD_LOGIC;
signal mul_temp_12_n_98 : STD_LOGIC;
signal mul_temp_12_n_99 : STD_LOGIC;
signal \^mul_temp_13\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_13_n_100 : STD_LOGIC;
signal mul_temp_13_n_101 : STD_LOGIC;
signal mul_temp_13_n_102 : STD_LOGIC;
signal mul_temp_13_n_103 : STD_LOGIC;
signal mul_temp_13_n_104 : STD_LOGIC;
signal mul_temp_13_n_105 : STD_LOGIC;
signal mul_temp_13_n_74 : STD_LOGIC;
signal mul_temp_13_n_75 : STD_LOGIC;
signal mul_temp_13_n_76 : STD_LOGIC;
signal mul_temp_13_n_77 : STD_LOGIC;
signal mul_temp_13_n_78 : STD_LOGIC;
signal mul_temp_13_n_79 : STD_LOGIC;
signal mul_temp_13_n_80 : STD_LOGIC;
signal mul_temp_13_n_81 : STD_LOGIC;
signal mul_temp_13_n_82 : STD_LOGIC;
signal mul_temp_13_n_83 : STD_LOGIC;
signal mul_temp_13_n_84 : STD_LOGIC;
signal mul_temp_13_n_85 : STD_LOGIC;
signal mul_temp_13_n_86 : STD_LOGIC;
signal mul_temp_13_n_87 : STD_LOGIC;
signal mul_temp_13_n_88 : STD_LOGIC;
signal mul_temp_13_n_89 : STD_LOGIC;
signal mul_temp_13_n_90 : STD_LOGIC;
signal mul_temp_13_n_92 : STD_LOGIC;
signal mul_temp_13_n_93 : STD_LOGIC;
signal mul_temp_13_n_94 : STD_LOGIC;
signal mul_temp_13_n_95 : STD_LOGIC;
signal mul_temp_13_n_96 : STD_LOGIC;
signal mul_temp_13_n_97 : STD_LOGIC;
signal mul_temp_13_n_98 : STD_LOGIC;
signal mul_temp_13_n_99 : STD_LOGIC;
signal \^mul_temp_14\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_14_n_100 : STD_LOGIC;
signal mul_temp_14_n_101 : STD_LOGIC;
signal mul_temp_14_n_102 : STD_LOGIC;
signal mul_temp_14_n_103 : STD_LOGIC;
signal mul_temp_14_n_104 : STD_LOGIC;
signal mul_temp_14_n_105 : STD_LOGIC;
signal mul_temp_14_n_74 : STD_LOGIC;
signal mul_temp_14_n_75 : STD_LOGIC;
signal mul_temp_14_n_76 : STD_LOGIC;
signal mul_temp_14_n_77 : STD_LOGIC;
signal mul_temp_14_n_78 : STD_LOGIC;
signal mul_temp_14_n_79 : STD_LOGIC;
signal mul_temp_14_n_80 : STD_LOGIC;
signal mul_temp_14_n_81 : STD_LOGIC;
signal mul_temp_14_n_82 : STD_LOGIC;
signal mul_temp_14_n_83 : STD_LOGIC;
signal mul_temp_14_n_84 : STD_LOGIC;
signal mul_temp_14_n_85 : STD_LOGIC;
signal mul_temp_14_n_86 : STD_LOGIC;
signal mul_temp_14_n_87 : STD_LOGIC;
signal mul_temp_14_n_88 : STD_LOGIC;
signal mul_temp_14_n_89 : STD_LOGIC;
signal mul_temp_14_n_90 : STD_LOGIC;
signal mul_temp_14_n_92 : STD_LOGIC;
signal mul_temp_14_n_93 : STD_LOGIC;
signal mul_temp_14_n_94 : STD_LOGIC;
signal mul_temp_14_n_95 : STD_LOGIC;
signal mul_temp_14_n_96 : STD_LOGIC;
signal mul_temp_14_n_97 : STD_LOGIC;
signal mul_temp_14_n_98 : STD_LOGIC;
signal mul_temp_14_n_99 : STD_LOGIC;
signal \^mul_temp_15\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_15_n_100 : STD_LOGIC;
signal mul_temp_15_n_101 : STD_LOGIC;
signal mul_temp_15_n_102 : STD_LOGIC;
signal mul_temp_15_n_103 : STD_LOGIC;
signal mul_temp_15_n_104 : STD_LOGIC;
signal mul_temp_15_n_105 : STD_LOGIC;
signal mul_temp_15_n_74 : STD_LOGIC;
signal mul_temp_15_n_75 : STD_LOGIC;
signal mul_temp_15_n_76 : STD_LOGIC;
signal mul_temp_15_n_77 : STD_LOGIC;
signal mul_temp_15_n_78 : STD_LOGIC;
signal mul_temp_15_n_79 : STD_LOGIC;
signal mul_temp_15_n_80 : STD_LOGIC;
signal mul_temp_15_n_81 : STD_LOGIC;
signal mul_temp_15_n_82 : STD_LOGIC;
signal mul_temp_15_n_83 : STD_LOGIC;
signal mul_temp_15_n_84 : STD_LOGIC;
signal mul_temp_15_n_85 : STD_LOGIC;
signal mul_temp_15_n_86 : STD_LOGIC;
signal mul_temp_15_n_87 : STD_LOGIC;
signal mul_temp_15_n_88 : STD_LOGIC;
signal mul_temp_15_n_89 : STD_LOGIC;
signal mul_temp_15_n_90 : STD_LOGIC;
signal mul_temp_15_n_92 : STD_LOGIC;
signal mul_temp_15_n_93 : STD_LOGIC;
signal mul_temp_15_n_94 : STD_LOGIC;
signal mul_temp_15_n_95 : STD_LOGIC;
signal mul_temp_15_n_96 : STD_LOGIC;
signal mul_temp_15_n_97 : STD_LOGIC;
signal mul_temp_15_n_98 : STD_LOGIC;
signal mul_temp_15_n_99 : STD_LOGIC;
signal \^mul_temp_16\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^mul_temp_17\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_17_n_100 : STD_LOGIC;
signal mul_temp_17_n_101 : STD_LOGIC;
signal mul_temp_17_n_102 : STD_LOGIC;
signal mul_temp_17_n_103 : STD_LOGIC;
signal mul_temp_17_n_104 : STD_LOGIC;
signal mul_temp_17_n_105 : STD_LOGIC;
signal mul_temp_17_n_74 : STD_LOGIC;
signal mul_temp_17_n_75 : STD_LOGIC;
signal mul_temp_17_n_76 : STD_LOGIC;
signal mul_temp_17_n_77 : STD_LOGIC;
signal mul_temp_17_n_78 : STD_LOGIC;
signal mul_temp_17_n_79 : STD_LOGIC;
signal mul_temp_17_n_80 : STD_LOGIC;
signal mul_temp_17_n_81 : STD_LOGIC;
signal mul_temp_17_n_82 : STD_LOGIC;
signal mul_temp_17_n_83 : STD_LOGIC;
signal mul_temp_17_n_84 : STD_LOGIC;
signal mul_temp_17_n_85 : STD_LOGIC;
signal mul_temp_17_n_86 : STD_LOGIC;
signal mul_temp_17_n_87 : STD_LOGIC;
signal mul_temp_17_n_88 : STD_LOGIC;
signal mul_temp_17_n_89 : STD_LOGIC;
signal mul_temp_17_n_90 : STD_LOGIC;
signal mul_temp_17_n_92 : STD_LOGIC;
signal mul_temp_17_n_93 : STD_LOGIC;
signal mul_temp_17_n_94 : STD_LOGIC;
signal mul_temp_17_n_95 : STD_LOGIC;
signal mul_temp_17_n_96 : STD_LOGIC;
signal mul_temp_17_n_97 : STD_LOGIC;
signal mul_temp_17_n_98 : STD_LOGIC;
signal mul_temp_17_n_99 : STD_LOGIC;
signal \^mul_temp_18\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_18_n_100 : STD_LOGIC;
signal mul_temp_18_n_101 : STD_LOGIC;
signal mul_temp_18_n_102 : STD_LOGIC;
signal mul_temp_18_n_103 : STD_LOGIC;
signal mul_temp_18_n_104 : STD_LOGIC;
signal mul_temp_18_n_105 : STD_LOGIC;
signal mul_temp_18_n_74 : STD_LOGIC;
signal mul_temp_18_n_75 : STD_LOGIC;
signal mul_temp_18_n_76 : STD_LOGIC;
signal mul_temp_18_n_77 : STD_LOGIC;
signal mul_temp_18_n_78 : STD_LOGIC;
signal mul_temp_18_n_79 : STD_LOGIC;
signal mul_temp_18_n_80 : STD_LOGIC;
signal mul_temp_18_n_81 : STD_LOGIC;
signal mul_temp_18_n_82 : STD_LOGIC;
signal mul_temp_18_n_83 : STD_LOGIC;
signal mul_temp_18_n_84 : STD_LOGIC;
signal mul_temp_18_n_85 : STD_LOGIC;
signal mul_temp_18_n_86 : STD_LOGIC;
signal mul_temp_18_n_87 : STD_LOGIC;
signal mul_temp_18_n_88 : STD_LOGIC;
signal mul_temp_18_n_89 : STD_LOGIC;
signal mul_temp_18_n_90 : STD_LOGIC;
signal mul_temp_18_n_92 : STD_LOGIC;
signal mul_temp_18_n_93 : STD_LOGIC;
signal mul_temp_18_n_94 : STD_LOGIC;
signal mul_temp_18_n_95 : STD_LOGIC;
signal mul_temp_18_n_96 : STD_LOGIC;
signal mul_temp_18_n_97 : STD_LOGIC;
signal mul_temp_18_n_98 : STD_LOGIC;
signal mul_temp_18_n_99 : STD_LOGIC;
signal \^mul_temp_19\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_19_n_100 : STD_LOGIC;
signal mul_temp_19_n_101 : STD_LOGIC;
signal mul_temp_19_n_102 : STD_LOGIC;
signal mul_temp_19_n_103 : STD_LOGIC;
signal mul_temp_19_n_104 : STD_LOGIC;
signal mul_temp_19_n_105 : STD_LOGIC;
signal mul_temp_19_n_74 : STD_LOGIC;
signal mul_temp_19_n_75 : STD_LOGIC;
signal mul_temp_19_n_76 : STD_LOGIC;
signal mul_temp_19_n_77 : STD_LOGIC;
signal mul_temp_19_n_78 : STD_LOGIC;
signal mul_temp_19_n_79 : STD_LOGIC;
signal mul_temp_19_n_80 : STD_LOGIC;
signal mul_temp_19_n_81 : STD_LOGIC;
signal mul_temp_19_n_82 : STD_LOGIC;
signal mul_temp_19_n_83 : STD_LOGIC;
signal mul_temp_19_n_84 : STD_LOGIC;
signal mul_temp_19_n_85 : STD_LOGIC;
signal mul_temp_19_n_86 : STD_LOGIC;
signal mul_temp_19_n_87 : STD_LOGIC;
signal mul_temp_19_n_88 : STD_LOGIC;
signal mul_temp_19_n_89 : STD_LOGIC;
signal mul_temp_19_n_90 : STD_LOGIC;
signal mul_temp_19_n_92 : STD_LOGIC;
signal mul_temp_19_n_93 : STD_LOGIC;
signal mul_temp_19_n_94 : STD_LOGIC;
signal mul_temp_19_n_95 : STD_LOGIC;
signal mul_temp_19_n_96 : STD_LOGIC;
signal mul_temp_19_n_97 : STD_LOGIC;
signal mul_temp_19_n_98 : STD_LOGIC;
signal mul_temp_19_n_99 : STD_LOGIC;
signal mul_temp_1_n_100 : STD_LOGIC;
signal mul_temp_1_n_101 : STD_LOGIC;
signal mul_temp_1_n_102 : STD_LOGIC;
signal mul_temp_1_n_103 : STD_LOGIC;
signal mul_temp_1_n_104 : STD_LOGIC;
signal mul_temp_1_n_105 : STD_LOGIC;
signal mul_temp_1_n_74 : STD_LOGIC;
signal mul_temp_1_n_75 : STD_LOGIC;
signal mul_temp_1_n_76 : STD_LOGIC;
signal mul_temp_1_n_77 : STD_LOGIC;
signal mul_temp_1_n_78 : STD_LOGIC;
signal mul_temp_1_n_79 : STD_LOGIC;
signal mul_temp_1_n_80 : STD_LOGIC;
signal mul_temp_1_n_81 : STD_LOGIC;
signal mul_temp_1_n_82 : STD_LOGIC;
signal mul_temp_1_n_83 : STD_LOGIC;
signal mul_temp_1_n_84 : STD_LOGIC;
signal mul_temp_1_n_85 : STD_LOGIC;
signal mul_temp_1_n_86 : STD_LOGIC;
signal mul_temp_1_n_87 : STD_LOGIC;
signal mul_temp_1_n_88 : STD_LOGIC;
signal mul_temp_1_n_89 : STD_LOGIC;
signal mul_temp_1_n_90 : STD_LOGIC;
signal mul_temp_1_n_92 : STD_LOGIC;
signal mul_temp_1_n_93 : STD_LOGIC;
signal mul_temp_1_n_94 : STD_LOGIC;
signal mul_temp_1_n_95 : STD_LOGIC;
signal mul_temp_1_n_96 : STD_LOGIC;
signal mul_temp_1_n_97 : STD_LOGIC;
signal mul_temp_1_n_98 : STD_LOGIC;
signal mul_temp_1_n_99 : STD_LOGIC;
signal \^mul_temp_2\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mul_temp_20\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_20_n_100 : STD_LOGIC;
signal mul_temp_20_n_101 : STD_LOGIC;
signal mul_temp_20_n_102 : STD_LOGIC;
signal mul_temp_20_n_103 : STD_LOGIC;
signal mul_temp_20_n_104 : STD_LOGIC;
signal mul_temp_20_n_105 : STD_LOGIC;
signal mul_temp_20_n_74 : STD_LOGIC;
signal mul_temp_20_n_75 : STD_LOGIC;
signal mul_temp_20_n_76 : STD_LOGIC;
signal mul_temp_20_n_77 : STD_LOGIC;
signal mul_temp_20_n_78 : STD_LOGIC;
signal mul_temp_20_n_79 : STD_LOGIC;
signal mul_temp_20_n_80 : STD_LOGIC;
signal mul_temp_20_n_81 : STD_LOGIC;
signal mul_temp_20_n_82 : STD_LOGIC;
signal mul_temp_20_n_83 : STD_LOGIC;
signal mul_temp_20_n_84 : STD_LOGIC;
signal mul_temp_20_n_85 : STD_LOGIC;
signal mul_temp_20_n_86 : STD_LOGIC;
signal mul_temp_20_n_87 : STD_LOGIC;
signal mul_temp_20_n_88 : STD_LOGIC;
signal mul_temp_20_n_89 : STD_LOGIC;
signal mul_temp_20_n_90 : STD_LOGIC;
signal mul_temp_20_n_92 : STD_LOGIC;
signal mul_temp_20_n_93 : STD_LOGIC;
signal mul_temp_20_n_94 : STD_LOGIC;
signal mul_temp_20_n_95 : STD_LOGIC;
signal mul_temp_20_n_96 : STD_LOGIC;
signal mul_temp_20_n_97 : STD_LOGIC;
signal mul_temp_20_n_98 : STD_LOGIC;
signal mul_temp_20_n_99 : STD_LOGIC;
signal \^mul_temp_21\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_21_n_100 : STD_LOGIC;
signal mul_temp_21_n_101 : STD_LOGIC;
signal mul_temp_21_n_102 : STD_LOGIC;
signal mul_temp_21_n_103 : STD_LOGIC;
signal mul_temp_21_n_104 : STD_LOGIC;
signal mul_temp_21_n_105 : STD_LOGIC;
signal mul_temp_21_n_74 : STD_LOGIC;
signal mul_temp_21_n_75 : STD_LOGIC;
signal mul_temp_21_n_76 : STD_LOGIC;
signal mul_temp_21_n_77 : STD_LOGIC;
signal mul_temp_21_n_78 : STD_LOGIC;
signal mul_temp_21_n_79 : STD_LOGIC;
signal mul_temp_21_n_80 : STD_LOGIC;
signal mul_temp_21_n_81 : STD_LOGIC;
signal mul_temp_21_n_82 : STD_LOGIC;
signal mul_temp_21_n_83 : STD_LOGIC;
signal mul_temp_21_n_84 : STD_LOGIC;
signal mul_temp_21_n_85 : STD_LOGIC;
signal mul_temp_21_n_86 : STD_LOGIC;
signal mul_temp_21_n_87 : STD_LOGIC;
signal mul_temp_21_n_88 : STD_LOGIC;
signal mul_temp_21_n_89 : STD_LOGIC;
signal mul_temp_21_n_90 : STD_LOGIC;
signal mul_temp_21_n_92 : STD_LOGIC;
signal mul_temp_21_n_93 : STD_LOGIC;
signal mul_temp_21_n_94 : STD_LOGIC;
signal mul_temp_21_n_95 : STD_LOGIC;
signal mul_temp_21_n_96 : STD_LOGIC;
signal mul_temp_21_n_97 : STD_LOGIC;
signal mul_temp_21_n_98 : STD_LOGIC;
signal mul_temp_21_n_99 : STD_LOGIC;
signal \^mul_temp_22\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_22_n_100 : STD_LOGIC;
signal mul_temp_22_n_101 : STD_LOGIC;
signal mul_temp_22_n_102 : STD_LOGIC;
signal mul_temp_22_n_103 : STD_LOGIC;
signal mul_temp_22_n_104 : STD_LOGIC;
signal mul_temp_22_n_105 : STD_LOGIC;
signal mul_temp_22_n_74 : STD_LOGIC;
signal mul_temp_22_n_75 : STD_LOGIC;
signal mul_temp_22_n_76 : STD_LOGIC;
signal mul_temp_22_n_77 : STD_LOGIC;
signal mul_temp_22_n_78 : STD_LOGIC;
signal mul_temp_22_n_79 : STD_LOGIC;
signal mul_temp_22_n_80 : STD_LOGIC;
signal mul_temp_22_n_81 : STD_LOGIC;
signal mul_temp_22_n_82 : STD_LOGIC;
signal mul_temp_22_n_83 : STD_LOGIC;
signal mul_temp_22_n_84 : STD_LOGIC;
signal mul_temp_22_n_85 : STD_LOGIC;
signal mul_temp_22_n_86 : STD_LOGIC;
signal mul_temp_22_n_87 : STD_LOGIC;
signal mul_temp_22_n_88 : STD_LOGIC;
signal mul_temp_22_n_89 : STD_LOGIC;
signal mul_temp_22_n_90 : STD_LOGIC;
signal mul_temp_22_n_92 : STD_LOGIC;
signal mul_temp_22_n_93 : STD_LOGIC;
signal mul_temp_22_n_94 : STD_LOGIC;
signal mul_temp_22_n_95 : STD_LOGIC;
signal mul_temp_22_n_96 : STD_LOGIC;
signal mul_temp_22_n_97 : STD_LOGIC;
signal mul_temp_22_n_98 : STD_LOGIC;
signal mul_temp_22_n_99 : STD_LOGIC;
signal \^mul_temp_23\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_23_n_100 : STD_LOGIC;
signal mul_temp_23_n_101 : STD_LOGIC;
signal mul_temp_23_n_102 : STD_LOGIC;
signal mul_temp_23_n_103 : STD_LOGIC;
signal mul_temp_23_n_104 : STD_LOGIC;
signal mul_temp_23_n_105 : STD_LOGIC;
signal mul_temp_23_n_74 : STD_LOGIC;
signal mul_temp_23_n_75 : STD_LOGIC;
signal mul_temp_23_n_76 : STD_LOGIC;
signal mul_temp_23_n_77 : STD_LOGIC;
signal mul_temp_23_n_78 : STD_LOGIC;
signal mul_temp_23_n_79 : STD_LOGIC;
signal mul_temp_23_n_80 : STD_LOGIC;
signal mul_temp_23_n_81 : STD_LOGIC;
signal mul_temp_23_n_82 : STD_LOGIC;
signal mul_temp_23_n_83 : STD_LOGIC;
signal mul_temp_23_n_84 : STD_LOGIC;
signal mul_temp_23_n_85 : STD_LOGIC;
signal mul_temp_23_n_86 : STD_LOGIC;
signal mul_temp_23_n_87 : STD_LOGIC;
signal mul_temp_23_n_88 : STD_LOGIC;
signal mul_temp_23_n_89 : STD_LOGIC;
signal mul_temp_23_n_90 : STD_LOGIC;
signal mul_temp_23_n_92 : STD_LOGIC;
signal mul_temp_23_n_93 : STD_LOGIC;
signal mul_temp_23_n_94 : STD_LOGIC;
signal mul_temp_23_n_95 : STD_LOGIC;
signal mul_temp_23_n_96 : STD_LOGIC;
signal mul_temp_23_n_97 : STD_LOGIC;
signal mul_temp_23_n_98 : STD_LOGIC;
signal mul_temp_23_n_99 : STD_LOGIC;
signal \^mul_temp_24\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_24_n_100 : STD_LOGIC;
signal mul_temp_24_n_101 : STD_LOGIC;
signal mul_temp_24_n_102 : STD_LOGIC;
signal mul_temp_24_n_103 : STD_LOGIC;
signal mul_temp_24_n_104 : STD_LOGIC;
signal mul_temp_24_n_105 : STD_LOGIC;
signal mul_temp_24_n_74 : STD_LOGIC;
signal mul_temp_24_n_75 : STD_LOGIC;
signal mul_temp_24_n_76 : STD_LOGIC;
signal mul_temp_24_n_77 : STD_LOGIC;
signal mul_temp_24_n_78 : STD_LOGIC;
signal mul_temp_24_n_79 : STD_LOGIC;
signal mul_temp_24_n_80 : STD_LOGIC;
signal mul_temp_24_n_81 : STD_LOGIC;
signal mul_temp_24_n_82 : STD_LOGIC;
signal mul_temp_24_n_83 : STD_LOGIC;
signal mul_temp_24_n_84 : STD_LOGIC;
signal mul_temp_24_n_85 : STD_LOGIC;
signal mul_temp_24_n_86 : STD_LOGIC;
signal mul_temp_24_n_87 : STD_LOGIC;
signal mul_temp_24_n_88 : STD_LOGIC;
signal mul_temp_24_n_89 : STD_LOGIC;
signal mul_temp_24_n_90 : STD_LOGIC;
signal mul_temp_24_n_92 : STD_LOGIC;
signal mul_temp_24_n_93 : STD_LOGIC;
signal mul_temp_24_n_94 : STD_LOGIC;
signal mul_temp_24_n_95 : STD_LOGIC;
signal mul_temp_24_n_96 : STD_LOGIC;
signal mul_temp_24_n_97 : STD_LOGIC;
signal mul_temp_24_n_98 : STD_LOGIC;
signal mul_temp_24_n_99 : STD_LOGIC;
signal \^mul_temp_25\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_25_n_100 : STD_LOGIC;
signal mul_temp_25_n_101 : STD_LOGIC;
signal mul_temp_25_n_102 : STD_LOGIC;
signal mul_temp_25_n_103 : STD_LOGIC;
signal mul_temp_25_n_104 : STD_LOGIC;
signal mul_temp_25_n_105 : STD_LOGIC;
signal mul_temp_25_n_74 : STD_LOGIC;
signal mul_temp_25_n_75 : STD_LOGIC;
signal mul_temp_25_n_76 : STD_LOGIC;
signal mul_temp_25_n_77 : STD_LOGIC;
signal mul_temp_25_n_78 : STD_LOGIC;
signal mul_temp_25_n_79 : STD_LOGIC;
signal mul_temp_25_n_80 : STD_LOGIC;
signal mul_temp_25_n_81 : STD_LOGIC;
signal mul_temp_25_n_82 : STD_LOGIC;
signal mul_temp_25_n_83 : STD_LOGIC;
signal mul_temp_25_n_84 : STD_LOGIC;
signal mul_temp_25_n_85 : STD_LOGIC;
signal mul_temp_25_n_86 : STD_LOGIC;
signal mul_temp_25_n_87 : STD_LOGIC;
signal mul_temp_25_n_88 : STD_LOGIC;
signal mul_temp_25_n_89 : STD_LOGIC;
signal mul_temp_25_n_90 : STD_LOGIC;
signal mul_temp_25_n_92 : STD_LOGIC;
signal mul_temp_25_n_93 : STD_LOGIC;
signal mul_temp_25_n_94 : STD_LOGIC;
signal mul_temp_25_n_95 : STD_LOGIC;
signal mul_temp_25_n_96 : STD_LOGIC;
signal mul_temp_25_n_97 : STD_LOGIC;
signal mul_temp_25_n_98 : STD_LOGIC;
signal mul_temp_25_n_99 : STD_LOGIC;
signal \^mul_temp_26\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_26_n_100 : STD_LOGIC;
signal mul_temp_26_n_101 : STD_LOGIC;
signal mul_temp_26_n_102 : STD_LOGIC;
signal mul_temp_26_n_103 : STD_LOGIC;
signal mul_temp_26_n_104 : STD_LOGIC;
signal mul_temp_26_n_105 : STD_LOGIC;
signal mul_temp_26_n_74 : STD_LOGIC;
signal mul_temp_26_n_75 : STD_LOGIC;
signal mul_temp_26_n_76 : STD_LOGIC;
signal mul_temp_26_n_77 : STD_LOGIC;
signal mul_temp_26_n_78 : STD_LOGIC;
signal mul_temp_26_n_79 : STD_LOGIC;
signal mul_temp_26_n_80 : STD_LOGIC;
signal mul_temp_26_n_81 : STD_LOGIC;
signal mul_temp_26_n_82 : STD_LOGIC;
signal mul_temp_26_n_83 : STD_LOGIC;
signal mul_temp_26_n_84 : STD_LOGIC;
signal mul_temp_26_n_85 : STD_LOGIC;
signal mul_temp_26_n_86 : STD_LOGIC;
signal mul_temp_26_n_87 : STD_LOGIC;
signal mul_temp_26_n_88 : STD_LOGIC;
signal mul_temp_26_n_89 : STD_LOGIC;
signal mul_temp_26_n_90 : STD_LOGIC;
signal mul_temp_26_n_92 : STD_LOGIC;
signal mul_temp_26_n_93 : STD_LOGIC;
signal mul_temp_26_n_94 : STD_LOGIC;
signal mul_temp_26_n_95 : STD_LOGIC;
signal mul_temp_26_n_96 : STD_LOGIC;
signal mul_temp_26_n_97 : STD_LOGIC;
signal mul_temp_26_n_98 : STD_LOGIC;
signal mul_temp_26_n_99 : STD_LOGIC;
signal \^mul_temp_27\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_27_n_100 : STD_LOGIC;
signal mul_temp_27_n_101 : STD_LOGIC;
signal mul_temp_27_n_102 : STD_LOGIC;
signal mul_temp_27_n_103 : STD_LOGIC;
signal mul_temp_27_n_104 : STD_LOGIC;
signal mul_temp_27_n_105 : STD_LOGIC;
signal mul_temp_27_n_74 : STD_LOGIC;
signal mul_temp_27_n_75 : STD_LOGIC;
signal mul_temp_27_n_76 : STD_LOGIC;
signal mul_temp_27_n_77 : STD_LOGIC;
signal mul_temp_27_n_78 : STD_LOGIC;
signal mul_temp_27_n_79 : STD_LOGIC;
signal mul_temp_27_n_80 : STD_LOGIC;
signal mul_temp_27_n_81 : STD_LOGIC;
signal mul_temp_27_n_82 : STD_LOGIC;
signal mul_temp_27_n_83 : STD_LOGIC;
signal mul_temp_27_n_84 : STD_LOGIC;
signal mul_temp_27_n_85 : STD_LOGIC;
signal mul_temp_27_n_86 : STD_LOGIC;
signal mul_temp_27_n_87 : STD_LOGIC;
signal mul_temp_27_n_88 : STD_LOGIC;
signal mul_temp_27_n_89 : STD_LOGIC;
signal mul_temp_27_n_90 : STD_LOGIC;
signal mul_temp_27_n_92 : STD_LOGIC;
signal mul_temp_27_n_93 : STD_LOGIC;
signal mul_temp_27_n_94 : STD_LOGIC;
signal mul_temp_27_n_95 : STD_LOGIC;
signal mul_temp_27_n_96 : STD_LOGIC;
signal mul_temp_27_n_97 : STD_LOGIC;
signal mul_temp_27_n_98 : STD_LOGIC;
signal mul_temp_27_n_99 : STD_LOGIC;
signal \^mul_temp_28\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_28_n_100 : STD_LOGIC;
signal mul_temp_28_n_101 : STD_LOGIC;
signal mul_temp_28_n_102 : STD_LOGIC;
signal mul_temp_28_n_103 : STD_LOGIC;
signal mul_temp_28_n_104 : STD_LOGIC;
signal mul_temp_28_n_105 : STD_LOGIC;
signal mul_temp_28_n_74 : STD_LOGIC;
signal mul_temp_28_n_75 : STD_LOGIC;
signal mul_temp_28_n_76 : STD_LOGIC;
signal mul_temp_28_n_77 : STD_LOGIC;
signal mul_temp_28_n_78 : STD_LOGIC;
signal mul_temp_28_n_79 : STD_LOGIC;
signal mul_temp_28_n_80 : STD_LOGIC;
signal mul_temp_28_n_81 : STD_LOGIC;
signal mul_temp_28_n_82 : STD_LOGIC;
signal mul_temp_28_n_83 : STD_LOGIC;
signal mul_temp_28_n_84 : STD_LOGIC;
signal mul_temp_28_n_85 : STD_LOGIC;
signal mul_temp_28_n_86 : STD_LOGIC;
signal mul_temp_28_n_87 : STD_LOGIC;
signal mul_temp_28_n_88 : STD_LOGIC;
signal mul_temp_28_n_89 : STD_LOGIC;
signal mul_temp_28_n_90 : STD_LOGIC;
signal mul_temp_28_n_92 : STD_LOGIC;
signal mul_temp_28_n_93 : STD_LOGIC;
signal mul_temp_28_n_94 : STD_LOGIC;
signal mul_temp_28_n_95 : STD_LOGIC;
signal mul_temp_28_n_96 : STD_LOGIC;
signal mul_temp_28_n_97 : STD_LOGIC;
signal mul_temp_28_n_98 : STD_LOGIC;
signal mul_temp_28_n_99 : STD_LOGIC;
signal \^mul_temp_29\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_29_n_100 : STD_LOGIC;
signal mul_temp_29_n_101 : STD_LOGIC;
signal mul_temp_29_n_102 : STD_LOGIC;
signal mul_temp_29_n_103 : STD_LOGIC;
signal mul_temp_29_n_104 : STD_LOGIC;
signal mul_temp_29_n_105 : STD_LOGIC;
signal mul_temp_29_n_74 : STD_LOGIC;
signal mul_temp_29_n_75 : STD_LOGIC;
signal mul_temp_29_n_76 : STD_LOGIC;
signal mul_temp_29_n_77 : STD_LOGIC;
signal mul_temp_29_n_78 : STD_LOGIC;
signal mul_temp_29_n_79 : STD_LOGIC;
signal mul_temp_29_n_80 : STD_LOGIC;
signal mul_temp_29_n_81 : STD_LOGIC;
signal mul_temp_29_n_82 : STD_LOGIC;
signal mul_temp_29_n_83 : STD_LOGIC;
signal mul_temp_29_n_84 : STD_LOGIC;
signal mul_temp_29_n_85 : STD_LOGIC;
signal mul_temp_29_n_86 : STD_LOGIC;
signal mul_temp_29_n_87 : STD_LOGIC;
signal mul_temp_29_n_88 : STD_LOGIC;
signal mul_temp_29_n_89 : STD_LOGIC;
signal mul_temp_29_n_90 : STD_LOGIC;
signal mul_temp_29_n_92 : STD_LOGIC;
signal mul_temp_29_n_93 : STD_LOGIC;
signal mul_temp_29_n_94 : STD_LOGIC;
signal mul_temp_29_n_95 : STD_LOGIC;
signal mul_temp_29_n_96 : STD_LOGIC;
signal mul_temp_29_n_97 : STD_LOGIC;
signal mul_temp_29_n_98 : STD_LOGIC;
signal mul_temp_29_n_99 : STD_LOGIC;
signal mul_temp_2_n_100 : STD_LOGIC;
signal mul_temp_2_n_101 : STD_LOGIC;
signal mul_temp_2_n_102 : STD_LOGIC;
signal mul_temp_2_n_103 : STD_LOGIC;
signal mul_temp_2_n_104 : STD_LOGIC;
signal mul_temp_2_n_105 : STD_LOGIC;
signal mul_temp_2_n_74 : STD_LOGIC;
signal mul_temp_2_n_75 : STD_LOGIC;
signal mul_temp_2_n_76 : STD_LOGIC;
signal mul_temp_2_n_77 : STD_LOGIC;
signal mul_temp_2_n_78 : STD_LOGIC;
signal mul_temp_2_n_79 : STD_LOGIC;
signal mul_temp_2_n_80 : STD_LOGIC;
signal mul_temp_2_n_81 : STD_LOGIC;
signal mul_temp_2_n_82 : STD_LOGIC;
signal mul_temp_2_n_83 : STD_LOGIC;
signal mul_temp_2_n_84 : STD_LOGIC;
signal mul_temp_2_n_85 : STD_LOGIC;
signal mul_temp_2_n_86 : STD_LOGIC;
signal mul_temp_2_n_87 : STD_LOGIC;
signal mul_temp_2_n_88 : STD_LOGIC;
signal mul_temp_2_n_89 : STD_LOGIC;
signal mul_temp_2_n_90 : STD_LOGIC;
signal mul_temp_2_n_92 : STD_LOGIC;
signal mul_temp_2_n_93 : STD_LOGIC;
signal mul_temp_2_n_94 : STD_LOGIC;
signal mul_temp_2_n_95 : STD_LOGIC;
signal mul_temp_2_n_96 : STD_LOGIC;
signal mul_temp_2_n_97 : STD_LOGIC;
signal mul_temp_2_n_98 : STD_LOGIC;
signal mul_temp_2_n_99 : STD_LOGIC;
signal \^mul_temp_3\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mul_temp_30\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_30_n_100 : STD_LOGIC;
signal mul_temp_30_n_101 : STD_LOGIC;
signal mul_temp_30_n_102 : STD_LOGIC;
signal mul_temp_30_n_103 : STD_LOGIC;
signal mul_temp_30_n_104 : STD_LOGIC;
signal mul_temp_30_n_105 : STD_LOGIC;
signal mul_temp_30_n_74 : STD_LOGIC;
signal mul_temp_30_n_75 : STD_LOGIC;
signal mul_temp_30_n_76 : STD_LOGIC;
signal mul_temp_30_n_77 : STD_LOGIC;
signal mul_temp_30_n_78 : STD_LOGIC;
signal mul_temp_30_n_79 : STD_LOGIC;
signal mul_temp_30_n_80 : STD_LOGIC;
signal mul_temp_30_n_81 : STD_LOGIC;
signal mul_temp_30_n_82 : STD_LOGIC;
signal mul_temp_30_n_83 : STD_LOGIC;
signal mul_temp_30_n_84 : STD_LOGIC;
signal mul_temp_30_n_85 : STD_LOGIC;
signal mul_temp_30_n_86 : STD_LOGIC;
signal mul_temp_30_n_87 : STD_LOGIC;
signal mul_temp_30_n_88 : STD_LOGIC;
signal mul_temp_30_n_89 : STD_LOGIC;
signal mul_temp_30_n_90 : STD_LOGIC;
signal mul_temp_30_n_92 : STD_LOGIC;
signal mul_temp_30_n_93 : STD_LOGIC;
signal mul_temp_30_n_94 : STD_LOGIC;
signal mul_temp_30_n_95 : STD_LOGIC;
signal mul_temp_30_n_96 : STD_LOGIC;
signal mul_temp_30_n_97 : STD_LOGIC;
signal mul_temp_30_n_98 : STD_LOGIC;
signal mul_temp_30_n_99 : STD_LOGIC;
signal \^mul_temp_31\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_31_n_100 : STD_LOGIC;
signal mul_temp_31_n_101 : STD_LOGIC;
signal mul_temp_31_n_102 : STD_LOGIC;
signal mul_temp_31_n_103 : STD_LOGIC;
signal mul_temp_31_n_104 : STD_LOGIC;
signal mul_temp_31_n_105 : STD_LOGIC;
signal mul_temp_31_n_74 : STD_LOGIC;
signal mul_temp_31_n_75 : STD_LOGIC;
signal mul_temp_31_n_76 : STD_LOGIC;
signal mul_temp_31_n_77 : STD_LOGIC;
signal mul_temp_31_n_78 : STD_LOGIC;
signal mul_temp_31_n_79 : STD_LOGIC;
signal mul_temp_31_n_80 : STD_LOGIC;
signal mul_temp_31_n_81 : STD_LOGIC;
signal mul_temp_31_n_82 : STD_LOGIC;
signal mul_temp_31_n_83 : STD_LOGIC;
signal mul_temp_31_n_84 : STD_LOGIC;
signal mul_temp_31_n_85 : STD_LOGIC;
signal mul_temp_31_n_86 : STD_LOGIC;
signal mul_temp_31_n_87 : STD_LOGIC;
signal mul_temp_31_n_88 : STD_LOGIC;
signal mul_temp_31_n_89 : STD_LOGIC;
signal mul_temp_31_n_90 : STD_LOGIC;
signal mul_temp_31_n_92 : STD_LOGIC;
signal mul_temp_31_n_93 : STD_LOGIC;
signal mul_temp_31_n_94 : STD_LOGIC;
signal mul_temp_31_n_95 : STD_LOGIC;
signal mul_temp_31_n_96 : STD_LOGIC;
signal mul_temp_31_n_97 : STD_LOGIC;
signal mul_temp_31_n_98 : STD_LOGIC;
signal mul_temp_31_n_99 : STD_LOGIC;
signal \^mul_temp_32\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_32_n_100 : STD_LOGIC;
signal mul_temp_32_n_101 : STD_LOGIC;
signal mul_temp_32_n_102 : STD_LOGIC;
signal mul_temp_32_n_103 : STD_LOGIC;
signal mul_temp_32_n_104 : STD_LOGIC;
signal mul_temp_32_n_105 : STD_LOGIC;
signal mul_temp_32_n_74 : STD_LOGIC;
signal mul_temp_32_n_75 : STD_LOGIC;
signal mul_temp_32_n_76 : STD_LOGIC;
signal mul_temp_32_n_77 : STD_LOGIC;
signal mul_temp_32_n_78 : STD_LOGIC;
signal mul_temp_32_n_79 : STD_LOGIC;
signal mul_temp_32_n_80 : STD_LOGIC;
signal mul_temp_32_n_81 : STD_LOGIC;
signal mul_temp_32_n_82 : STD_LOGIC;
signal mul_temp_32_n_83 : STD_LOGIC;
signal mul_temp_32_n_84 : STD_LOGIC;
signal mul_temp_32_n_85 : STD_LOGIC;
signal mul_temp_32_n_86 : STD_LOGIC;
signal mul_temp_32_n_87 : STD_LOGIC;
signal mul_temp_32_n_88 : STD_LOGIC;
signal mul_temp_32_n_89 : STD_LOGIC;
signal mul_temp_32_n_90 : STD_LOGIC;
signal mul_temp_32_n_92 : STD_LOGIC;
signal mul_temp_32_n_93 : STD_LOGIC;
signal mul_temp_32_n_94 : STD_LOGIC;
signal mul_temp_32_n_95 : STD_LOGIC;
signal mul_temp_32_n_96 : STD_LOGIC;
signal mul_temp_32_n_97 : STD_LOGIC;
signal mul_temp_32_n_98 : STD_LOGIC;
signal mul_temp_32_n_99 : STD_LOGIC;
signal mul_temp_3_n_100 : STD_LOGIC;
signal mul_temp_3_n_101 : STD_LOGIC;
signal mul_temp_3_n_102 : STD_LOGIC;
signal mul_temp_3_n_103 : STD_LOGIC;
signal mul_temp_3_n_104 : STD_LOGIC;
signal mul_temp_3_n_105 : STD_LOGIC;
signal mul_temp_3_n_74 : STD_LOGIC;
signal mul_temp_3_n_75 : STD_LOGIC;
signal mul_temp_3_n_76 : STD_LOGIC;
signal mul_temp_3_n_77 : STD_LOGIC;
signal mul_temp_3_n_78 : STD_LOGIC;
signal mul_temp_3_n_79 : STD_LOGIC;
signal mul_temp_3_n_80 : STD_LOGIC;
signal mul_temp_3_n_81 : STD_LOGIC;
signal mul_temp_3_n_82 : STD_LOGIC;
signal mul_temp_3_n_83 : STD_LOGIC;
signal mul_temp_3_n_84 : STD_LOGIC;
signal mul_temp_3_n_85 : STD_LOGIC;
signal mul_temp_3_n_86 : STD_LOGIC;
signal mul_temp_3_n_87 : STD_LOGIC;
signal mul_temp_3_n_88 : STD_LOGIC;
signal mul_temp_3_n_89 : STD_LOGIC;
signal mul_temp_3_n_90 : STD_LOGIC;
signal mul_temp_3_n_92 : STD_LOGIC;
signal mul_temp_3_n_93 : STD_LOGIC;
signal mul_temp_3_n_94 : STD_LOGIC;
signal mul_temp_3_n_95 : STD_LOGIC;
signal mul_temp_3_n_96 : STD_LOGIC;
signal mul_temp_3_n_97 : STD_LOGIC;
signal mul_temp_3_n_98 : STD_LOGIC;
signal mul_temp_3_n_99 : STD_LOGIC;
signal \^mul_temp_4\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_4_n_100 : STD_LOGIC;
signal mul_temp_4_n_101 : STD_LOGIC;
signal mul_temp_4_n_102 : STD_LOGIC;
signal mul_temp_4_n_103 : STD_LOGIC;
signal mul_temp_4_n_104 : STD_LOGIC;
signal mul_temp_4_n_105 : STD_LOGIC;
signal mul_temp_4_n_74 : STD_LOGIC;
signal mul_temp_4_n_75 : STD_LOGIC;
signal mul_temp_4_n_76 : STD_LOGIC;
signal mul_temp_4_n_77 : STD_LOGIC;
signal mul_temp_4_n_78 : STD_LOGIC;
signal mul_temp_4_n_79 : STD_LOGIC;
signal mul_temp_4_n_80 : STD_LOGIC;
signal mul_temp_4_n_81 : STD_LOGIC;
signal mul_temp_4_n_82 : STD_LOGIC;
signal mul_temp_4_n_83 : STD_LOGIC;
signal mul_temp_4_n_84 : STD_LOGIC;
signal mul_temp_4_n_85 : STD_LOGIC;
signal mul_temp_4_n_86 : STD_LOGIC;
signal mul_temp_4_n_87 : STD_LOGIC;
signal mul_temp_4_n_88 : STD_LOGIC;
signal mul_temp_4_n_89 : STD_LOGIC;
signal mul_temp_4_n_90 : STD_LOGIC;
signal mul_temp_4_n_92 : STD_LOGIC;
signal mul_temp_4_n_93 : STD_LOGIC;
signal mul_temp_4_n_94 : STD_LOGIC;
signal mul_temp_4_n_95 : STD_LOGIC;
signal mul_temp_4_n_96 : STD_LOGIC;
signal mul_temp_4_n_97 : STD_LOGIC;
signal mul_temp_4_n_98 : STD_LOGIC;
signal mul_temp_4_n_99 : STD_LOGIC;
signal \^mul_temp_5\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_5_n_100 : STD_LOGIC;
signal mul_temp_5_n_101 : STD_LOGIC;
signal mul_temp_5_n_102 : STD_LOGIC;
signal mul_temp_5_n_103 : STD_LOGIC;
signal mul_temp_5_n_104 : STD_LOGIC;
signal mul_temp_5_n_105 : STD_LOGIC;
signal mul_temp_5_n_74 : STD_LOGIC;
signal mul_temp_5_n_75 : STD_LOGIC;
signal mul_temp_5_n_76 : STD_LOGIC;
signal mul_temp_5_n_77 : STD_LOGIC;
signal mul_temp_5_n_78 : STD_LOGIC;
signal mul_temp_5_n_79 : STD_LOGIC;
signal mul_temp_5_n_80 : STD_LOGIC;
signal mul_temp_5_n_81 : STD_LOGIC;
signal mul_temp_5_n_82 : STD_LOGIC;
signal mul_temp_5_n_83 : STD_LOGIC;
signal mul_temp_5_n_84 : STD_LOGIC;
signal mul_temp_5_n_85 : STD_LOGIC;
signal mul_temp_5_n_86 : STD_LOGIC;
signal mul_temp_5_n_87 : STD_LOGIC;
signal mul_temp_5_n_88 : STD_LOGIC;
signal mul_temp_5_n_89 : STD_LOGIC;
signal mul_temp_5_n_90 : STD_LOGIC;
signal mul_temp_5_n_92 : STD_LOGIC;
signal mul_temp_5_n_93 : STD_LOGIC;
signal mul_temp_5_n_94 : STD_LOGIC;
signal mul_temp_5_n_95 : STD_LOGIC;
signal mul_temp_5_n_96 : STD_LOGIC;
signal mul_temp_5_n_97 : STD_LOGIC;
signal mul_temp_5_n_98 : STD_LOGIC;
signal mul_temp_5_n_99 : STD_LOGIC;
signal \^mul_temp_6\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_6_n_100 : STD_LOGIC;
signal mul_temp_6_n_101 : STD_LOGIC;
signal mul_temp_6_n_102 : STD_LOGIC;
signal mul_temp_6_n_103 : STD_LOGIC;
signal mul_temp_6_n_104 : STD_LOGIC;
signal mul_temp_6_n_105 : STD_LOGIC;
signal mul_temp_6_n_74 : STD_LOGIC;
signal mul_temp_6_n_75 : STD_LOGIC;
signal mul_temp_6_n_76 : STD_LOGIC;
signal mul_temp_6_n_77 : STD_LOGIC;
signal mul_temp_6_n_78 : STD_LOGIC;
signal mul_temp_6_n_79 : STD_LOGIC;
signal mul_temp_6_n_80 : STD_LOGIC;
signal mul_temp_6_n_81 : STD_LOGIC;
signal mul_temp_6_n_82 : STD_LOGIC;
signal mul_temp_6_n_83 : STD_LOGIC;
signal mul_temp_6_n_84 : STD_LOGIC;
signal mul_temp_6_n_85 : STD_LOGIC;
signal mul_temp_6_n_86 : STD_LOGIC;
signal mul_temp_6_n_87 : STD_LOGIC;
signal mul_temp_6_n_88 : STD_LOGIC;
signal mul_temp_6_n_89 : STD_LOGIC;
signal mul_temp_6_n_90 : STD_LOGIC;
signal mul_temp_6_n_92 : STD_LOGIC;
signal mul_temp_6_n_93 : STD_LOGIC;
signal mul_temp_6_n_94 : STD_LOGIC;
signal mul_temp_6_n_95 : STD_LOGIC;
signal mul_temp_6_n_96 : STD_LOGIC;
signal mul_temp_6_n_97 : STD_LOGIC;
signal mul_temp_6_n_98 : STD_LOGIC;
signal mul_temp_6_n_99 : STD_LOGIC;
signal \^mul_temp_7\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_7_n_100 : STD_LOGIC;
signal mul_temp_7_n_101 : STD_LOGIC;
signal mul_temp_7_n_102 : STD_LOGIC;
signal mul_temp_7_n_103 : STD_LOGIC;
signal mul_temp_7_n_104 : STD_LOGIC;
signal mul_temp_7_n_105 : STD_LOGIC;
signal mul_temp_7_n_74 : STD_LOGIC;
signal mul_temp_7_n_75 : STD_LOGIC;
signal mul_temp_7_n_76 : STD_LOGIC;
signal mul_temp_7_n_77 : STD_LOGIC;
signal mul_temp_7_n_78 : STD_LOGIC;
signal mul_temp_7_n_79 : STD_LOGIC;
signal mul_temp_7_n_80 : STD_LOGIC;
signal mul_temp_7_n_81 : STD_LOGIC;
signal mul_temp_7_n_82 : STD_LOGIC;
signal mul_temp_7_n_83 : STD_LOGIC;
signal mul_temp_7_n_84 : STD_LOGIC;
signal mul_temp_7_n_85 : STD_LOGIC;
signal mul_temp_7_n_86 : STD_LOGIC;
signal mul_temp_7_n_87 : STD_LOGIC;
signal mul_temp_7_n_88 : STD_LOGIC;
signal mul_temp_7_n_89 : STD_LOGIC;
signal mul_temp_7_n_90 : STD_LOGIC;
signal mul_temp_7_n_92 : STD_LOGIC;
signal mul_temp_7_n_93 : STD_LOGIC;
signal mul_temp_7_n_94 : STD_LOGIC;
signal mul_temp_7_n_95 : STD_LOGIC;
signal mul_temp_7_n_96 : STD_LOGIC;
signal mul_temp_7_n_97 : STD_LOGIC;
signal mul_temp_7_n_98 : STD_LOGIC;
signal mul_temp_7_n_99 : STD_LOGIC;
signal \^mul_temp_8\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_8_n_100 : STD_LOGIC;
signal mul_temp_8_n_101 : STD_LOGIC;
signal mul_temp_8_n_102 : STD_LOGIC;
signal mul_temp_8_n_103 : STD_LOGIC;
signal mul_temp_8_n_104 : STD_LOGIC;
signal mul_temp_8_n_105 : STD_LOGIC;
signal mul_temp_8_n_74 : STD_LOGIC;
signal mul_temp_8_n_75 : STD_LOGIC;
signal mul_temp_8_n_76 : STD_LOGIC;
signal mul_temp_8_n_77 : STD_LOGIC;
signal mul_temp_8_n_78 : STD_LOGIC;
signal mul_temp_8_n_79 : STD_LOGIC;
signal mul_temp_8_n_80 : STD_LOGIC;
signal mul_temp_8_n_81 : STD_LOGIC;
signal mul_temp_8_n_82 : STD_LOGIC;
signal mul_temp_8_n_83 : STD_LOGIC;
signal mul_temp_8_n_84 : STD_LOGIC;
signal mul_temp_8_n_85 : STD_LOGIC;
signal mul_temp_8_n_86 : STD_LOGIC;
signal mul_temp_8_n_87 : STD_LOGIC;
signal mul_temp_8_n_88 : STD_LOGIC;
signal mul_temp_8_n_89 : STD_LOGIC;
signal mul_temp_8_n_90 : STD_LOGIC;
signal mul_temp_8_n_92 : STD_LOGIC;
signal mul_temp_8_n_93 : STD_LOGIC;
signal mul_temp_8_n_94 : STD_LOGIC;
signal mul_temp_8_n_95 : STD_LOGIC;
signal mul_temp_8_n_96 : STD_LOGIC;
signal mul_temp_8_n_97 : STD_LOGIC;
signal mul_temp_8_n_98 : STD_LOGIC;
signal mul_temp_8_n_99 : STD_LOGIC;
signal \^mul_temp_9\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_9_n_100 : STD_LOGIC;
signal mul_temp_9_n_101 : STD_LOGIC;
signal mul_temp_9_n_102 : STD_LOGIC;
signal mul_temp_9_n_103 : STD_LOGIC;
signal mul_temp_9_n_104 : STD_LOGIC;
signal mul_temp_9_n_105 : STD_LOGIC;
signal mul_temp_9_n_74 : STD_LOGIC;
signal mul_temp_9_n_75 : STD_LOGIC;
signal mul_temp_9_n_76 : STD_LOGIC;
signal mul_temp_9_n_77 : STD_LOGIC;
signal mul_temp_9_n_78 : STD_LOGIC;
signal mul_temp_9_n_79 : STD_LOGIC;
signal mul_temp_9_n_80 : STD_LOGIC;
signal mul_temp_9_n_81 : STD_LOGIC;
signal mul_temp_9_n_82 : STD_LOGIC;
signal mul_temp_9_n_83 : STD_LOGIC;
signal mul_temp_9_n_84 : STD_LOGIC;
signal mul_temp_9_n_85 : STD_LOGIC;
signal mul_temp_9_n_86 : STD_LOGIC;
signal mul_temp_9_n_87 : STD_LOGIC;
signal mul_temp_9_n_88 : STD_LOGIC;
signal mul_temp_9_n_89 : STD_LOGIC;
signal mul_temp_9_n_90 : STD_LOGIC;
signal mul_temp_9_n_92 : STD_LOGIC;
signal mul_temp_9_n_93 : STD_LOGIC;
signal mul_temp_9_n_94 : STD_LOGIC;
signal mul_temp_9_n_95 : STD_LOGIC;
signal mul_temp_9_n_96 : STD_LOGIC;
signal mul_temp_9_n_97 : STD_LOGIC;
signal mul_temp_9_n_98 : STD_LOGIC;
signal mul_temp_9_n_99 : STD_LOGIC;
signal mul_temp_n_100 : STD_LOGIC;
signal mul_temp_n_101 : STD_LOGIC;
signal mul_temp_n_102 : STD_LOGIC;
signal mul_temp_n_103 : STD_LOGIC;
signal mul_temp_n_104 : STD_LOGIC;
signal mul_temp_n_105 : STD_LOGIC;
signal mul_temp_n_74 : STD_LOGIC;
signal mul_temp_n_75 : STD_LOGIC;
signal mul_temp_n_76 : STD_LOGIC;
signal mul_temp_n_77 : STD_LOGIC;
signal mul_temp_n_78 : STD_LOGIC;
signal mul_temp_n_79 : STD_LOGIC;
signal mul_temp_n_80 : STD_LOGIC;
signal mul_temp_n_81 : STD_LOGIC;
signal mul_temp_n_82 : STD_LOGIC;
signal mul_temp_n_83 : STD_LOGIC;
signal mul_temp_n_84 : STD_LOGIC;
signal mul_temp_n_85 : STD_LOGIC;
signal mul_temp_n_86 : STD_LOGIC;
signal mul_temp_n_87 : STD_LOGIC;
signal mul_temp_n_88 : STD_LOGIC;
signal mul_temp_n_89 : STD_LOGIC;
signal mul_temp_n_90 : STD_LOGIC;
signal mul_temp_n_92 : STD_LOGIC;
signal mul_temp_n_93 : STD_LOGIC;
signal mul_temp_n_94 : STD_LOGIC;
signal mul_temp_n_95 : STD_LOGIC;
signal mul_temp_n_96 : STD_LOGIC;
signal mul_temp_n_97 : STD_LOGIC;
signal mul_temp_n_98 : STD_LOGIC;
signal mul_temp_n_99 : STD_LOGIC;
signal \sub_temp_carry__0_n_0\ : STD_LOGIC;
signal \sub_temp_carry__0_n_1\ : STD_LOGIC;
signal \sub_temp_carry__0_n_2\ : STD_LOGIC;
signal \sub_temp_carry__0_n_3\ : STD_LOGIC;
signal \sub_temp_carry__1_n_0\ : STD_LOGIC;
signal \sub_temp_carry__1_n_1\ : STD_LOGIC;
signal \sub_temp_carry__1_n_2\ : STD_LOGIC;
signal \sub_temp_carry__1_n_3\ : STD_LOGIC;
signal \sub_temp_carry__2_n_1\ : STD_LOGIC;
signal \sub_temp_carry__2_n_2\ : STD_LOGIC;
signal \sub_temp_carry__2_n_3\ : STD_LOGIC;
signal sub_temp_carry_n_0 : STD_LOGIC;
signal sub_temp_carry_n_1 : STD_LOGIC;
signal sub_temp_carry_n_2 : STD_LOGIC;
signal sub_temp_carry_n_3 : STD_LOGIC;
signal \weight[0][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[0][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[0][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[0][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[0][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[0][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[0][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[0][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[0][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[0][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[0][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[0][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[0][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[0][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[0][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[0][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[10][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[10][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[10][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[10][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[10][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[10][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[10][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[10][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[10][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[10][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[10][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[10][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[10][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[10][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[10][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[10][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[11][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[11][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[11][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[11][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[11][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[11][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[11][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[11][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[11][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[11][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[11][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[11][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[11][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[11][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[11][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[11][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[12][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[12][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[12][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[12][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[12][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[12][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[12][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[12][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[12][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[12][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[12][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[12][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[12][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[12][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[12][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[12][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[13][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[13][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[13][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[13][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[13][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[13][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[13][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[13][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[13][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[13][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[13][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[13][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[13][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[13][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[13][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[13][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[14][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[14][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[14][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[14][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[14][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[14][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[14][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[14][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[14][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[14][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[14][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[14][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[14][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[14][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[14][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[14][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[15][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[15][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[15][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[15][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[15][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[15][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[15][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[15][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[15][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[15][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[15][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[15][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[15][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[15][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[15][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[15][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[1][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[1][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[1][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[1][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[1][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[1][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[1][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[1][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[1][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[1][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[1][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[1][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[1][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[1][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[1][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[1][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[2][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[2][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[2][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[2][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[2][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[2][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[2][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[2][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[2][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[2][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[2][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[2][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[2][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[2][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[2][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[2][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[3][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[3][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[3][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[3][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[3][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[3][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[3][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[3][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[3][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[3][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[3][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[3][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[3][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[3][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[3][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[3][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[4][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[4][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[4][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[4][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[4][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[4][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[4][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[4][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[4][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[4][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[4][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[4][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[4][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[4][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[4][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[4][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[5][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[5][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[5][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[5][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[5][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[5][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[5][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[5][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[5][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[5][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[5][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[5][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[5][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[5][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[5][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[5][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[6][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[6][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[6][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[6][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[6][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[6][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[6][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[6][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[6][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[6][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[6][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[6][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[6][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[6][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[6][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[6][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[7][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[7][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[7][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[7][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[7][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[7][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[7][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[7][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[7][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[7][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[7][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[7][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[7][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[7][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[7][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[7][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[8][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[8][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[8][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[8][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[8][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[8][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[8][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[8][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[8][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[8][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[8][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[8][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[8][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[8][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[8][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[8][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[9][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[9][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[9][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[9][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[9][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[9][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[9][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[9][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[9][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[9][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[9][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[9][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[9][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[9][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[9][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[9][8]_i_5_n_0\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[0]_15\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[10][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[10]_9\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[11][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[11]_10\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[12][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[12]_11\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[13][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[13]_12\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[14][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[14]_13\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[15][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[15]_14\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[1][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[1]_0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[2][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[2]_1\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[3][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[3]_2\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[4][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[4]_3\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[5][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[5]_4\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[6][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[6]_5\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[7][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[7]_6\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[8][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[8]_7\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[9][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[9]_8\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_ARG_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_ARG_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_ARG_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_ARG_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 30 );
signal NLW_ARG_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__0_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__1_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__1_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__1_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__1_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__1_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__10_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__10_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__10_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__10_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__10_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__11_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__11_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__11_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__11_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__11_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__12_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__12_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__12_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__12_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__12_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__13_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__13_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__13_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__13_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__13_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__14_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__14_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__14_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__14_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__14_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__15_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__15_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__15_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__15_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__15_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__16_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__16_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__16_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__16_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__16_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__17_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__17_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__17_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__17_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__17_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__18_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__18_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__18_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__18_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__18_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__19_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__19_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__19_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__19_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__19_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__2_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__2_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__2_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__2_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__2_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__20_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__20_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__20_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__20_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__20_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__21_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__21_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__21_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__21_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__21_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__22_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__22_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__22_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__22_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__22_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__23_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__23_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__23_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__23_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__23_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__24_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__24_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__24_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__24_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__24_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__25_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__25_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__25_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__25_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__25_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__26_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__26_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__26_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__26_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__26_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__27_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__27_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__27_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__27_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__27_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__28_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__28_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__28_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__28_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__28_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__29_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__29_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__29_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__29_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__29_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__3_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__3_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__3_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__3_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__3_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__30_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__30_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__30_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__30_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__30_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__4_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__4_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__4_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__4_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__4_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__5_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__5_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__5_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__5_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__5_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__6_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__6_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__6_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__6_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__6_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__7_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__7_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__7_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__7_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__7_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__8_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__8_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__8_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__8_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__8_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__9_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__9_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__9_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__9_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__9_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_ARG_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG_carry__3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_ARG_carry__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_add_temp_14__0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__138_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__184_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__230_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__278_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__46_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__92_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_mul_temp_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_1_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_1_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_1_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_1_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_1_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_10_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_10_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_10_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_10_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_10_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_11_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_11_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_11_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_11_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_11_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_12_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_12_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_12_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_12_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_12_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_13_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_13_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_13_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_13_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_13_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_14_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_14_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_14_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_14_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_14_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_15_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_15_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_15_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_15_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_15_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_17_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_17_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_17_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_17_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_17_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_18_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_18_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_18_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_18_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_18_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_19_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_19_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_19_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_19_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_19_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_2_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_2_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_2_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_2_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_2_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_20_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_20_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_20_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_20_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_20_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_21_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_21_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_21_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_21_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_21_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_22_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_22_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_22_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_22_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_22_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_23_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_23_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_23_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_23_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_23_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_24_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_24_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_24_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_24_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_24_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_25_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_25_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_25_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_25_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_25_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_26_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_26_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_26_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_26_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_26_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_27_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_27_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_27_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_27_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_27_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_28_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_28_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_28_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_28_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_28_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_29_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_29_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_29_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_29_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_29_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_3_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_3_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_3_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_3_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_3_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_30_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_30_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_30_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_30_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_30_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_31_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_31_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_31_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_31_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_31_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_32_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_32_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_32_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_32_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_32_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_4_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_4_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_4_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_4_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_4_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_5_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_5_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_5_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_5_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_5_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_6_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_6_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_6_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_6_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_6_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_7_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_7_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_7_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_7_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_7_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_8_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_8_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_8_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_8_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_8_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_9_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_9_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_9_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_9_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_9_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_sub_temp_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[0][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[10][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[11][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[12][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[13][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[14][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[15][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[1][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[2][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[3][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[4][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[5][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[6][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[7][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[8][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[9][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of ARG : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__0\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__1\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__10\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__11\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__12\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__13\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__14\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__15\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__16\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__17\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__18\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__19\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__2\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__20\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__21\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__22\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__23\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__24\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__25\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__26\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__27\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__28\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__29\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__3\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__30\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__4\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__5\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__6\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__7\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__8\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__9\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute HLUTNM : string;
attribute HLUTNM of \add_temp_14__0_carry__0_i_1\ : label is "lutpair6";
attribute HLUTNM of \add_temp_14__0_carry__0_i_2\ : label is "lutpair5";
attribute HLUTNM of \add_temp_14__0_carry__0_i_3\ : label is "lutpair4";
attribute HLUTNM of \add_temp_14__0_carry__0_i_4\ : label is "lutpair3";
attribute HLUTNM of \add_temp_14__0_carry__0_i_5\ : label is "lutpair7";
attribute HLUTNM of \add_temp_14__0_carry__0_i_6\ : label is "lutpair6";
attribute HLUTNM of \add_temp_14__0_carry__0_i_7\ : label is "lutpair5";
attribute HLUTNM of \add_temp_14__0_carry__0_i_8\ : label is "lutpair4";
attribute HLUTNM of \add_temp_14__0_carry__1_i_1\ : label is "lutpair10";
attribute HLUTNM of \add_temp_14__0_carry__1_i_2\ : label is "lutpair9";
attribute HLUTNM of \add_temp_14__0_carry__1_i_3\ : label is "lutpair8";
attribute HLUTNM of \add_temp_14__0_carry__1_i_4\ : label is "lutpair7";
attribute HLUTNM of \add_temp_14__0_carry__1_i_5\ : label is "lutpair11";
attribute HLUTNM of \add_temp_14__0_carry__1_i_6\ : label is "lutpair10";
attribute HLUTNM of \add_temp_14__0_carry__1_i_7\ : label is "lutpair9";
attribute HLUTNM of \add_temp_14__0_carry__1_i_8\ : label is "lutpair8";
attribute HLUTNM of \add_temp_14__0_carry__2_i_1\ : label is "lutpair13";
attribute HLUTNM of \add_temp_14__0_carry__2_i_2\ : label is "lutpair12";
attribute HLUTNM of \add_temp_14__0_carry__2_i_3\ : label is "lutpair11";
attribute HLUTNM of \add_temp_14__0_carry__2_i_6\ : label is "lutpair13";
attribute HLUTNM of \add_temp_14__0_carry__2_i_7\ : label is "lutpair12";
attribute HLUTNM of \add_temp_14__0_carry_i_1\ : label is "lutpair2";
attribute HLUTNM of \add_temp_14__0_carry_i_2\ : label is "lutpair1";
attribute HLUTNM of \add_temp_14__0_carry_i_3\ : label is "lutpair0";
attribute HLUTNM of \add_temp_14__0_carry_i_4\ : label is "lutpair3";
attribute HLUTNM of \add_temp_14__0_carry_i_5\ : label is "lutpair2";
attribute HLUTNM of \add_temp_14__0_carry_i_6\ : label is "lutpair1";
attribute HLUTNM of \add_temp_14__0_carry_i_7\ : label is "lutpair0";
attribute HLUTNM of \add_temp_14__138_carry__0_i_1\ : label is "lutpair48";
attribute HLUTNM of \add_temp_14__138_carry__0_i_2\ : label is "lutpair47";
attribute HLUTNM of \add_temp_14__138_carry__0_i_3\ : label is "lutpair46";
attribute HLUTNM of \add_temp_14__138_carry__0_i_4\ : label is "lutpair45";
attribute HLUTNM of \add_temp_14__138_carry__0_i_5\ : label is "lutpair49";
attribute HLUTNM of \add_temp_14__138_carry__0_i_6\ : label is "lutpair48";
attribute HLUTNM of \add_temp_14__138_carry__0_i_7\ : label is "lutpair47";
attribute HLUTNM of \add_temp_14__138_carry__0_i_8\ : label is "lutpair46";
attribute HLUTNM of \add_temp_14__138_carry__1_i_1\ : label is "lutpair52";
attribute HLUTNM of \add_temp_14__138_carry__1_i_2\ : label is "lutpair51";
attribute HLUTNM of \add_temp_14__138_carry__1_i_3\ : label is "lutpair50";
attribute HLUTNM of \add_temp_14__138_carry__1_i_4\ : label is "lutpair49";
attribute HLUTNM of \add_temp_14__138_carry__1_i_5\ : label is "lutpair53";
attribute HLUTNM of \add_temp_14__138_carry__1_i_6\ : label is "lutpair52";
attribute HLUTNM of \add_temp_14__138_carry__1_i_7\ : label is "lutpair51";
attribute HLUTNM of \add_temp_14__138_carry__1_i_8\ : label is "lutpair50";
attribute HLUTNM of \add_temp_14__138_carry__2_i_1\ : label is "lutpair55";
attribute HLUTNM of \add_temp_14__138_carry__2_i_2\ : label is "lutpair54";
attribute HLUTNM of \add_temp_14__138_carry__2_i_3\ : label is "lutpair53";
attribute HLUTNM of \add_temp_14__138_carry__2_i_6\ : label is "lutpair55";
attribute HLUTNM of \add_temp_14__138_carry__2_i_7\ : label is "lutpair54";
attribute HLUTNM of \add_temp_14__138_carry_i_1\ : label is "lutpair44";
attribute HLUTNM of \add_temp_14__138_carry_i_2\ : label is "lutpair43";
attribute HLUTNM of \add_temp_14__138_carry_i_3\ : label is "lutpair42";
attribute HLUTNM of \add_temp_14__138_carry_i_4\ : label is "lutpair45";
attribute HLUTNM of \add_temp_14__138_carry_i_5\ : label is "lutpair44";
attribute HLUTNM of \add_temp_14__138_carry_i_6\ : label is "lutpair43";
attribute HLUTNM of \add_temp_14__138_carry_i_7\ : label is "lutpair42";
attribute HLUTNM of \add_temp_14__184_carry__0_i_1\ : label is "lutpair62";
attribute HLUTNM of \add_temp_14__184_carry__0_i_2\ : label is "lutpair61";
attribute HLUTNM of \add_temp_14__184_carry__0_i_3\ : label is "lutpair60";
attribute HLUTNM of \add_temp_14__184_carry__0_i_4\ : label is "lutpair59";
attribute HLUTNM of \add_temp_14__184_carry__0_i_5\ : label is "lutpair63";
attribute HLUTNM of \add_temp_14__184_carry__0_i_6\ : label is "lutpair62";
attribute HLUTNM of \add_temp_14__184_carry__0_i_7\ : label is "lutpair61";
attribute HLUTNM of \add_temp_14__184_carry__0_i_8\ : label is "lutpair60";
attribute HLUTNM of \add_temp_14__184_carry__1_i_1\ : label is "lutpair66";
attribute HLUTNM of \add_temp_14__184_carry__1_i_2\ : label is "lutpair65";
attribute HLUTNM of \add_temp_14__184_carry__1_i_3\ : label is "lutpair64";
attribute HLUTNM of \add_temp_14__184_carry__1_i_4\ : label is "lutpair63";
attribute HLUTNM of \add_temp_14__184_carry__1_i_5\ : label is "lutpair67";
attribute HLUTNM of \add_temp_14__184_carry__1_i_6\ : label is "lutpair66";
attribute HLUTNM of \add_temp_14__184_carry__1_i_7\ : label is "lutpair65";
attribute HLUTNM of \add_temp_14__184_carry__1_i_8\ : label is "lutpair64";
attribute HLUTNM of \add_temp_14__184_carry__2_i_1\ : label is "lutpair69";
attribute HLUTNM of \add_temp_14__184_carry__2_i_2\ : label is "lutpair68";
attribute HLUTNM of \add_temp_14__184_carry__2_i_3\ : label is "lutpair67";
attribute HLUTNM of \add_temp_14__184_carry__2_i_6\ : label is "lutpair69";
attribute HLUTNM of \add_temp_14__184_carry__2_i_7\ : label is "lutpair68";
attribute HLUTNM of \add_temp_14__184_carry_i_1\ : label is "lutpair58";
attribute HLUTNM of \add_temp_14__184_carry_i_2\ : label is "lutpair57";
attribute HLUTNM of \add_temp_14__184_carry_i_3\ : label is "lutpair56";
attribute HLUTNM of \add_temp_14__184_carry_i_4\ : label is "lutpair59";
attribute HLUTNM of \add_temp_14__184_carry_i_5\ : label is "lutpair58";
attribute HLUTNM of \add_temp_14__184_carry_i_6\ : label is "lutpair57";
attribute HLUTNM of \add_temp_14__184_carry_i_7\ : label is "lutpair56";
attribute HLUTNM of \add_temp_14__230_carry__0_i_1\ : label is "lutpair76";
attribute HLUTNM of \add_temp_14__230_carry__0_i_2\ : label is "lutpair75";
attribute HLUTNM of \add_temp_14__230_carry__0_i_3\ : label is "lutpair74";
attribute HLUTNM of \add_temp_14__230_carry__0_i_4\ : label is "lutpair73";
attribute HLUTNM of \add_temp_14__230_carry__0_i_5\ : label is "lutpair77";
attribute HLUTNM of \add_temp_14__230_carry__0_i_6\ : label is "lutpair76";
attribute HLUTNM of \add_temp_14__230_carry__0_i_7\ : label is "lutpair75";
attribute HLUTNM of \add_temp_14__230_carry__0_i_8\ : label is "lutpair74";
attribute HLUTNM of \add_temp_14__230_carry__1_i_1\ : label is "lutpair80";
attribute HLUTNM of \add_temp_14__230_carry__1_i_2\ : label is "lutpair79";
attribute HLUTNM of \add_temp_14__230_carry__1_i_3\ : label is "lutpair78";
attribute HLUTNM of \add_temp_14__230_carry__1_i_4\ : label is "lutpair77";
attribute HLUTNM of \add_temp_14__230_carry__1_i_5\ : label is "lutpair81";
attribute HLUTNM of \add_temp_14__230_carry__1_i_6\ : label is "lutpair80";
attribute HLUTNM of \add_temp_14__230_carry__1_i_7\ : label is "lutpair79";
attribute HLUTNM of \add_temp_14__230_carry__1_i_8\ : label is "lutpair78";
attribute HLUTNM of \add_temp_14__230_carry__2_i_1\ : label is "lutpair83";
attribute HLUTNM of \add_temp_14__230_carry__2_i_2\ : label is "lutpair82";
attribute HLUTNM of \add_temp_14__230_carry__2_i_3\ : label is "lutpair81";
attribute HLUTNM of \add_temp_14__230_carry__2_i_6\ : label is "lutpair83";
attribute HLUTNM of \add_temp_14__230_carry__2_i_7\ : label is "lutpair82";
attribute HLUTNM of \add_temp_14__230_carry_i_1\ : label is "lutpair72";
attribute HLUTNM of \add_temp_14__230_carry_i_2\ : label is "lutpair71";
attribute HLUTNM of \add_temp_14__230_carry_i_3\ : label is "lutpair70";
attribute HLUTNM of \add_temp_14__230_carry_i_4\ : label is "lutpair73";
attribute HLUTNM of \add_temp_14__230_carry_i_5\ : label is "lutpair72";
attribute HLUTNM of \add_temp_14__230_carry_i_6\ : label is "lutpair71";
attribute HLUTNM of \add_temp_14__230_carry_i_7\ : label is "lutpair70";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \add_temp_14__278_carry__1_i_10\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \add_temp_14__278_carry__1_i_11\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \add_temp_14__278_carry__2_i_8\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \add_temp_14__278_carry__2_i_9\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \add_temp_14__278_carry_i_10\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \add_temp_14__278_carry_i_9\ : label is "soft_lutpair6";
attribute HLUTNM of \add_temp_14__46_carry__0_i_1\ : label is "lutpair20";
attribute HLUTNM of \add_temp_14__46_carry__0_i_2\ : label is "lutpair19";
attribute HLUTNM of \add_temp_14__46_carry__0_i_3\ : label is "lutpair18";
attribute HLUTNM of \add_temp_14__46_carry__0_i_4\ : label is "lutpair17";
attribute HLUTNM of \add_temp_14__46_carry__0_i_5\ : label is "lutpair21";
attribute HLUTNM of \add_temp_14__46_carry__0_i_6\ : label is "lutpair20";
attribute HLUTNM of \add_temp_14__46_carry__0_i_7\ : label is "lutpair19";
attribute HLUTNM of \add_temp_14__46_carry__0_i_8\ : label is "lutpair18";
attribute HLUTNM of \add_temp_14__46_carry__1_i_1\ : label is "lutpair24";
attribute HLUTNM of \add_temp_14__46_carry__1_i_2\ : label is "lutpair23";
attribute HLUTNM of \add_temp_14__46_carry__1_i_3\ : label is "lutpair22";
attribute HLUTNM of \add_temp_14__46_carry__1_i_4\ : label is "lutpair21";
attribute HLUTNM of \add_temp_14__46_carry__1_i_5\ : label is "lutpair25";
attribute HLUTNM of \add_temp_14__46_carry__1_i_6\ : label is "lutpair24";
attribute HLUTNM of \add_temp_14__46_carry__1_i_7\ : label is "lutpair23";
attribute HLUTNM of \add_temp_14__46_carry__1_i_8\ : label is "lutpair22";
attribute HLUTNM of \add_temp_14__46_carry__2_i_1\ : label is "lutpair27";
attribute HLUTNM of \add_temp_14__46_carry__2_i_2\ : label is "lutpair26";
attribute HLUTNM of \add_temp_14__46_carry__2_i_3\ : label is "lutpair25";
attribute HLUTNM of \add_temp_14__46_carry__2_i_6\ : label is "lutpair27";
attribute HLUTNM of \add_temp_14__46_carry__2_i_7\ : label is "lutpair26";
attribute HLUTNM of \add_temp_14__46_carry_i_1\ : label is "lutpair16";
attribute HLUTNM of \add_temp_14__46_carry_i_2\ : label is "lutpair15";
attribute HLUTNM of \add_temp_14__46_carry_i_3\ : label is "lutpair14";
attribute HLUTNM of \add_temp_14__46_carry_i_4\ : label is "lutpair17";
attribute HLUTNM of \add_temp_14__46_carry_i_5\ : label is "lutpair16";
attribute HLUTNM of \add_temp_14__46_carry_i_6\ : label is "lutpair15";
attribute HLUTNM of \add_temp_14__46_carry_i_7\ : label is "lutpair14";
attribute HLUTNM of \add_temp_14__92_carry__0_i_1\ : label is "lutpair34";
attribute HLUTNM of \add_temp_14__92_carry__0_i_2\ : label is "lutpair33";
attribute HLUTNM of \add_temp_14__92_carry__0_i_3\ : label is "lutpair32";
attribute HLUTNM of \add_temp_14__92_carry__0_i_4\ : label is "lutpair31";
attribute HLUTNM of \add_temp_14__92_carry__0_i_5\ : label is "lutpair35";
attribute HLUTNM of \add_temp_14__92_carry__0_i_6\ : label is "lutpair34";
attribute HLUTNM of \add_temp_14__92_carry__0_i_7\ : label is "lutpair33";
attribute HLUTNM of \add_temp_14__92_carry__0_i_8\ : label is "lutpair32";
attribute HLUTNM of \add_temp_14__92_carry__1_i_1\ : label is "lutpair38";
attribute HLUTNM of \add_temp_14__92_carry__1_i_2\ : label is "lutpair37";
attribute HLUTNM of \add_temp_14__92_carry__1_i_3\ : label is "lutpair36";
attribute HLUTNM of \add_temp_14__92_carry__1_i_4\ : label is "lutpair35";
attribute HLUTNM of \add_temp_14__92_carry__1_i_5\ : label is "lutpair39";
attribute HLUTNM of \add_temp_14__92_carry__1_i_6\ : label is "lutpair38";
attribute HLUTNM of \add_temp_14__92_carry__1_i_7\ : label is "lutpair37";
attribute HLUTNM of \add_temp_14__92_carry__1_i_8\ : label is "lutpair36";
attribute HLUTNM of \add_temp_14__92_carry__2_i_1\ : label is "lutpair41";
attribute HLUTNM of \add_temp_14__92_carry__2_i_2\ : label is "lutpair40";
attribute HLUTNM of \add_temp_14__92_carry__2_i_3\ : label is "lutpair39";
attribute HLUTNM of \add_temp_14__92_carry__2_i_6\ : label is "lutpair41";
attribute HLUTNM of \add_temp_14__92_carry__2_i_7\ : label is "lutpair40";
attribute HLUTNM of \add_temp_14__92_carry_i_1\ : label is "lutpair30";
attribute HLUTNM of \add_temp_14__92_carry_i_2\ : label is "lutpair29";
attribute HLUTNM of \add_temp_14__92_carry_i_3\ : label is "lutpair28";
attribute HLUTNM of \add_temp_14__92_carry_i_4\ : label is "lutpair31";
attribute HLUTNM of \add_temp_14__92_carry_i_5\ : label is "lutpair30";
attribute HLUTNM of \add_temp_14__92_carry_i_6\ : label is "lutpair29";
attribute HLUTNM of \add_temp_14__92_carry_i_7\ : label is "lutpair28";
attribute METHODOLOGY_DRC_VIOS of mul_temp : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_1 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_10 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_11 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_12 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_13 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_14 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_15 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_17 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_18 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_19 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_2 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_20 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_21 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_22 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_23 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_24 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_25 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_26 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_27 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_28 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_29 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_3 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_30 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_31 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_32 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_4 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_5 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_6 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_7 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_8 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_9 : label is "{SYNTH-13 {cell *THIS*}}";
begin
mul_temp_16(15 downto 0) <= \^mul_temp_16\(15 downto 0);
ARG: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[1]\(15),
A(28) => \data_pipeline_tmp_reg[1]\(15),
A(27) => \data_pipeline_tmp_reg[1]\(15),
A(26) => \data_pipeline_tmp_reg[1]\(15),
A(25) => \data_pipeline_tmp_reg[1]\(15),
A(24) => \data_pipeline_tmp_reg[1]\(15),
A(23) => \data_pipeline_tmp_reg[1]\(15),
A(22) => \data_pipeline_tmp_reg[1]\(15),
A(21) => \data_pipeline_tmp_reg[1]\(15),
A(20) => \data_pipeline_tmp_reg[1]\(15),
A(19) => \data_pipeline_tmp_reg[1]\(15),
A(18) => \data_pipeline_tmp_reg[1]\(15),
A(17) => \data_pipeline_tmp_reg[1]\(15),
A(16) => \data_pipeline_tmp_reg[1]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[1]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_ARG_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_ARG_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_18\(14),
C(12) => ARG_i_1_n_0,
C(11) => ARG_i_1_n_0,
C(10) => ARG_i_1_n_0,
C(9) => ARG_i_1_n_0,
C(8) => ARG_i_1_n_0,
C(7) => ARG_i_1_n_0,
C(6) => ARG_i_1_n_0,
C(5) => ARG_i_1_n_0,
C(4) => ARG_i_1_n_0,
C(3) => ARG_i_1_n_0,
C(2) => ARG_i_1_n_0,
C(1) => ARG_i_1_n_0,
C(0) => ARG_i_1_n_0,
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_ARG_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_ARG_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_ARG_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => NLW_ARG_OVERFLOW_UNCONNECTED,
P(47 downto 30) => NLW_ARG_P_UNCONNECTED(47 downto 30),
P(29 downto 14) => \in\(15 downto 0),
P(13) => ARG_n_92,
P(12) => ARG_n_93,
P(11) => ARG_n_94,
P(10) => ARG_n_95,
P(9) => ARG_n_96,
P(8) => ARG_n_97,
P(7) => ARG_n_98,
P(6) => ARG_n_99,
P(5) => ARG_n_100,
P(4) => ARG_n_101,
P(3) => ARG_n_102,
P(2) => ARG_n_103,
P(1) => ARG_n_104,
P(0) => ARG_n_105,
PATTERNBDETECT => NLW_ARG_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_ARG_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_ARG_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_ARG_UNDERFLOW_UNCONNECTED
);
\ARG__0\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[1]\(15),
A(28) => \data_pipeline_tmp_reg[1]\(15),
A(27) => \data_pipeline_tmp_reg[1]\(15),
A(26) => \data_pipeline_tmp_reg[1]\(15),
A(25) => \data_pipeline_tmp_reg[1]\(15),
A(24) => \data_pipeline_tmp_reg[1]\(15),
A(23) => \data_pipeline_tmp_reg[1]\(15),
A(22) => \data_pipeline_tmp_reg[1]\(15),
A(21) => \data_pipeline_tmp_reg[1]\(15),
A(20) => \data_pipeline_tmp_reg[1]\(15),
A(19) => \data_pipeline_tmp_reg[1]\(15),
A(18) => \data_pipeline_tmp_reg[1]\(15),
A(17) => \data_pipeline_tmp_reg[1]\(15),
A(16) => \data_pipeline_tmp_reg[1]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[1]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__0_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[1]_0\(15),
B(16) => \weight_reg[1]_0\(15),
B(15 downto 0) => \weight_reg[1]_0\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__0_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_1\(14),
C(12) => \ARG__0_i_1_n_0\,
C(11) => \ARG__0_i_1_n_0\,
C(10) => \ARG__0_i_1_n_0\,
C(9) => \ARG__0_i_1_n_0\,
C(8) => \ARG__0_i_1_n_0\,
C(7) => \ARG__0_i_1_n_0\,
C(6) => \ARG__0_i_1_n_0\,
C(5) => \ARG__0_i_1_n_0\,
C(4) => \ARG__0_i_1_n_0\,
C(3) => \ARG__0_i_1_n_0\,
C(2) => \ARG__0_i_1_n_0\,
C(1) => \ARG__0_i_1_n_0\,
C(0) => \ARG__0_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__0_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__0_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__0_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__0_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__0_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE16(15 downto 0),
P(13) => \ARG__0_n_92\,
P(12) => \ARG__0_n_93\,
P(11) => \ARG__0_n_94\,
P(10) => \ARG__0_n_95\,
P(9) => \ARG__0_n_96\,
P(8) => \ARG__0_n_97\,
P(7) => \ARG__0_n_98\,
P(6) => \ARG__0_n_99\,
P(5) => \ARG__0_n_100\,
P(4) => \ARG__0_n_101\,
P(3) => \ARG__0_n_102\,
P(2) => \ARG__0_n_103\,
P(1) => \ARG__0_n_104\,
P(0) => \ARG__0_n_105\,
PATTERNBDETECT => \NLW_ARG__0_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__0_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__0_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__0_UNDERFLOW_UNCONNECTED\
);
\ARG__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_1\(14),
O => \ARG__0_i_1_n_0\
);
\ARG__1\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[2]\(15),
A(28) => \data_pipeline_tmp_reg[2]\(15),
A(27) => \data_pipeline_tmp_reg[2]\(15),
A(26) => \data_pipeline_tmp_reg[2]\(15),
A(25) => \data_pipeline_tmp_reg[2]\(15),
A(24) => \data_pipeline_tmp_reg[2]\(15),
A(23) => \data_pipeline_tmp_reg[2]\(15),
A(22) => \data_pipeline_tmp_reg[2]\(15),
A(21) => \data_pipeline_tmp_reg[2]\(15),
A(20) => \data_pipeline_tmp_reg[2]\(15),
A(19) => \data_pipeline_tmp_reg[2]\(15),
A(18) => \data_pipeline_tmp_reg[2]\(15),
A(17) => \data_pipeline_tmp_reg[2]\(15),
A(16) => \data_pipeline_tmp_reg[2]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[2]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__1_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__1_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_19\(14),
C(12) => \ARG__1_i_1_n_0\,
C(11) => \ARG__1_i_1_n_0\,
C(10) => \ARG__1_i_1_n_0\,
C(9) => \ARG__1_i_1_n_0\,
C(8) => \ARG__1_i_1_n_0\,
C(7) => \ARG__1_i_1_n_0\,
C(6) => \ARG__1_i_1_n_0\,
C(5) => \ARG__1_i_1_n_0\,
C(4) => \ARG__1_i_1_n_0\,
C(3) => \ARG__1_i_1_n_0\,
C(2) => \ARG__1_i_1_n_0\,
C(1) => \ARG__1_i_1_n_0\,
C(0) => \ARG__1_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__1_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__1_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__1_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__1_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__1_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__1_n_76\,
P(28) => \ARG__1_n_77\,
P(27) => \ARG__1_n_78\,
P(26) => \ARG__1_n_79\,
P(25) => \ARG__1_n_80\,
P(24) => \ARG__1_n_81\,
P(23) => \ARG__1_n_82\,
P(22) => \ARG__1_n_83\,
P(21) => \ARG__1_n_84\,
P(20) => \ARG__1_n_85\,
P(19) => \ARG__1_n_86\,
P(18) => \ARG__1_n_87\,
P(17) => \ARG__1_n_88\,
P(16) => \ARG__1_n_89\,
P(15) => \ARG__1_n_90\,
P(14) => \ARG__1_n_91\,
P(13) => \ARG__1_n_92\,
P(12) => \ARG__1_n_93\,
P(11) => \ARG__1_n_94\,
P(10) => \ARG__1_n_95\,
P(9) => \ARG__1_n_96\,
P(8) => \ARG__1_n_97\,
P(7) => \ARG__1_n_98\,
P(6) => \ARG__1_n_99\,
P(5) => \ARG__1_n_100\,
P(4) => \ARG__1_n_101\,
P(3) => \ARG__1_n_102\,
P(2) => \ARG__1_n_103\,
P(1) => \ARG__1_n_104\,
P(0) => \ARG__1_n_105\,
PATTERNBDETECT => \NLW_ARG__1_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__1_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__1_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__1_UNDERFLOW_UNCONNECTED\
);
\ARG__10\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[6]\(15),
A(28) => \data_pipeline_tmp_reg[6]\(15),
A(27) => \data_pipeline_tmp_reg[6]\(15),
A(26) => \data_pipeline_tmp_reg[6]\(15),
A(25) => \data_pipeline_tmp_reg[6]\(15),
A(24) => \data_pipeline_tmp_reg[6]\(15),
A(23) => \data_pipeline_tmp_reg[6]\(15),
A(22) => \data_pipeline_tmp_reg[6]\(15),
A(21) => \data_pipeline_tmp_reg[6]\(15),
A(20) => \data_pipeline_tmp_reg[6]\(15),
A(19) => \data_pipeline_tmp_reg[6]\(15),
A(18) => \data_pipeline_tmp_reg[6]\(15),
A(17) => \data_pipeline_tmp_reg[6]\(15),
A(16) => \data_pipeline_tmp_reg[6]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[6]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__10_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[6]_5\(15),
B(16) => \weight_reg[6]_5\(15),
B(15 downto 0) => \weight_reg[6]_5\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__10_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_6\(14),
C(12) => \ARG__10_i_1_n_0\,
C(11) => \ARG__10_i_1_n_0\,
C(10) => \ARG__10_i_1_n_0\,
C(9) => \ARG__10_i_1_n_0\,
C(8) => \ARG__10_i_1_n_0\,
C(7) => \ARG__10_i_1_n_0\,
C(6) => \ARG__10_i_1_n_0\,
C(5) => \ARG__10_i_1_n_0\,
C(4) => \ARG__10_i_1_n_0\,
C(3) => \ARG__10_i_1_n_0\,
C(2) => \ARG__10_i_1_n_0\,
C(1) => \ARG__10_i_1_n_0\,
C(0) => \ARG__10_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__10_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__10_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__10_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__10_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__10_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE26(15 downto 0),
P(13) => \ARG__10_n_92\,
P(12) => \ARG__10_n_93\,
P(11) => \ARG__10_n_94\,
P(10) => \ARG__10_n_95\,
P(9) => \ARG__10_n_96\,
P(8) => \ARG__10_n_97\,
P(7) => \ARG__10_n_98\,
P(6) => \ARG__10_n_99\,
P(5) => \ARG__10_n_100\,
P(4) => \ARG__10_n_101\,
P(3) => \ARG__10_n_102\,
P(2) => \ARG__10_n_103\,
P(1) => \ARG__10_n_104\,
P(0) => \ARG__10_n_105\,
PATTERNBDETECT => \NLW_ARG__10_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__10_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__10_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__10_UNDERFLOW_UNCONNECTED\
);
\ARG__10_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_6\(14),
O => \ARG__10_i_1_n_0\
);
\ARG__11\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[7]\(15),
A(28) => \data_pipeline_tmp_reg[7]\(15),
A(27) => \data_pipeline_tmp_reg[7]\(15),
A(26) => \data_pipeline_tmp_reg[7]\(15),
A(25) => \data_pipeline_tmp_reg[7]\(15),
A(24) => \data_pipeline_tmp_reg[7]\(15),
A(23) => \data_pipeline_tmp_reg[7]\(15),
A(22) => \data_pipeline_tmp_reg[7]\(15),
A(21) => \data_pipeline_tmp_reg[7]\(15),
A(20) => \data_pipeline_tmp_reg[7]\(15),
A(19) => \data_pipeline_tmp_reg[7]\(15),
A(18) => \data_pipeline_tmp_reg[7]\(15),
A(17) => \data_pipeline_tmp_reg[7]\(15),
A(16) => \data_pipeline_tmp_reg[7]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[7]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__11_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__11_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_24\(14),
C(12) => \ARG__11_i_1_n_0\,
C(11) => \ARG__11_i_1_n_0\,
C(10) => \ARG__11_i_1_n_0\,
C(9) => \ARG__11_i_1_n_0\,
C(8) => \ARG__11_i_1_n_0\,
C(7) => \ARG__11_i_1_n_0\,
C(6) => \ARG__11_i_1_n_0\,
C(5) => \ARG__11_i_1_n_0\,
C(4) => \ARG__11_i_1_n_0\,
C(3) => \ARG__11_i_1_n_0\,
C(2) => \ARG__11_i_1_n_0\,
C(1) => \ARG__11_i_1_n_0\,
C(0) => \ARG__11_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__11_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__11_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__11_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__11_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__11_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__11_n_76\,
P(28) => \ARG__11_n_77\,
P(27) => \ARG__11_n_78\,
P(26) => \ARG__11_n_79\,
P(25) => \ARG__11_n_80\,
P(24) => \ARG__11_n_81\,
P(23) => \ARG__11_n_82\,
P(22) => \ARG__11_n_83\,
P(21) => \ARG__11_n_84\,
P(20) => \ARG__11_n_85\,
P(19) => \ARG__11_n_86\,
P(18) => \ARG__11_n_87\,
P(17) => \ARG__11_n_88\,
P(16) => \ARG__11_n_89\,
P(15) => \ARG__11_n_90\,
P(14) => \ARG__11_n_91\,
P(13) => \ARG__11_n_92\,
P(12) => \ARG__11_n_93\,
P(11) => \ARG__11_n_94\,
P(10) => \ARG__11_n_95\,
P(9) => \ARG__11_n_96\,
P(8) => \ARG__11_n_97\,
P(7) => \ARG__11_n_98\,
P(6) => \ARG__11_n_99\,
P(5) => \ARG__11_n_100\,
P(4) => \ARG__11_n_101\,
P(3) => \ARG__11_n_102\,
P(2) => \ARG__11_n_103\,
P(1) => \ARG__11_n_104\,
P(0) => \ARG__11_n_105\,
PATTERNBDETECT => \NLW_ARG__11_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__11_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__11_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__11_UNDERFLOW_UNCONNECTED\
);
\ARG__11_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_24\(14),
O => \ARG__11_i_1_n_0\
);
\ARG__12\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[7]\(15),
A(28) => \data_pipeline_tmp_reg[7]\(15),
A(27) => \data_pipeline_tmp_reg[7]\(15),
A(26) => \data_pipeline_tmp_reg[7]\(15),
A(25) => \data_pipeline_tmp_reg[7]\(15),
A(24) => \data_pipeline_tmp_reg[7]\(15),
A(23) => \data_pipeline_tmp_reg[7]\(15),
A(22) => \data_pipeline_tmp_reg[7]\(15),
A(21) => \data_pipeline_tmp_reg[7]\(15),
A(20) => \data_pipeline_tmp_reg[7]\(15),
A(19) => \data_pipeline_tmp_reg[7]\(15),
A(18) => \data_pipeline_tmp_reg[7]\(15),
A(17) => \data_pipeline_tmp_reg[7]\(15),
A(16) => \data_pipeline_tmp_reg[7]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[7]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__12_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[7]_6\(15),
B(16) => \weight_reg[7]_6\(15),
B(15 downto 0) => \weight_reg[7]_6\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__12_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_7\(14),
C(12) => \ARG__12_i_1_n_0\,
C(11) => \ARG__12_i_1_n_0\,
C(10) => \ARG__12_i_1_n_0\,
C(9) => \ARG__12_i_1_n_0\,
C(8) => \ARG__12_i_1_n_0\,
C(7) => \ARG__12_i_1_n_0\,
C(6) => \ARG__12_i_1_n_0\,
C(5) => \ARG__12_i_1_n_0\,
C(4) => \ARG__12_i_1_n_0\,
C(3) => \ARG__12_i_1_n_0\,
C(2) => \ARG__12_i_1_n_0\,
C(1) => \ARG__12_i_1_n_0\,
C(0) => \ARG__12_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__12_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__12_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__12_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__12_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__12_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE28(15 downto 0),
P(13) => \ARG__12_n_92\,
P(12) => \ARG__12_n_93\,
P(11) => \ARG__12_n_94\,
P(10) => \ARG__12_n_95\,
P(9) => \ARG__12_n_96\,
P(8) => \ARG__12_n_97\,
P(7) => \ARG__12_n_98\,
P(6) => \ARG__12_n_99\,
P(5) => \ARG__12_n_100\,
P(4) => \ARG__12_n_101\,
P(3) => \ARG__12_n_102\,
P(2) => \ARG__12_n_103\,
P(1) => \ARG__12_n_104\,
P(0) => \ARG__12_n_105\,
PATTERNBDETECT => \NLW_ARG__12_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__12_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__12_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__12_UNDERFLOW_UNCONNECTED\
);
\ARG__12_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_7\(14),
O => \ARG__12_i_1_n_0\
);
\ARG__13\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[8]\(15),
A(28) => \data_pipeline_tmp_reg[8]\(15),
A(27) => \data_pipeline_tmp_reg[8]\(15),
A(26) => \data_pipeline_tmp_reg[8]\(15),
A(25) => \data_pipeline_tmp_reg[8]\(15),
A(24) => \data_pipeline_tmp_reg[8]\(15),
A(23) => \data_pipeline_tmp_reg[8]\(15),
A(22) => \data_pipeline_tmp_reg[8]\(15),
A(21) => \data_pipeline_tmp_reg[8]\(15),
A(20) => \data_pipeline_tmp_reg[8]\(15),
A(19) => \data_pipeline_tmp_reg[8]\(15),
A(18) => \data_pipeline_tmp_reg[8]\(15),
A(17) => \data_pipeline_tmp_reg[8]\(15),
A(16) => \data_pipeline_tmp_reg[8]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[8]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__13_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__13_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_25\(14),
C(12) => \ARG__13_i_1_n_0\,
C(11) => \ARG__13_i_1_n_0\,
C(10) => \ARG__13_i_1_n_0\,
C(9) => \ARG__13_i_1_n_0\,
C(8) => \ARG__13_i_1_n_0\,
C(7) => \ARG__13_i_1_n_0\,
C(6) => \ARG__13_i_1_n_0\,
C(5) => \ARG__13_i_1_n_0\,
C(4) => \ARG__13_i_1_n_0\,
C(3) => \ARG__13_i_1_n_0\,
C(2) => \ARG__13_i_1_n_0\,
C(1) => \ARG__13_i_1_n_0\,
C(0) => \ARG__13_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__13_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__13_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__13_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__13_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__13_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__13_n_76\,
P(28) => \ARG__13_n_77\,
P(27) => \ARG__13_n_78\,
P(26) => \ARG__13_n_79\,
P(25) => \ARG__13_n_80\,
P(24) => \ARG__13_n_81\,
P(23) => \ARG__13_n_82\,
P(22) => \ARG__13_n_83\,
P(21) => \ARG__13_n_84\,
P(20) => \ARG__13_n_85\,
P(19) => \ARG__13_n_86\,
P(18) => \ARG__13_n_87\,
P(17) => \ARG__13_n_88\,
P(16) => \ARG__13_n_89\,
P(15) => \ARG__13_n_90\,
P(14) => \ARG__13_n_91\,
P(13) => \ARG__13_n_92\,
P(12) => \ARG__13_n_93\,
P(11) => \ARG__13_n_94\,
P(10) => \ARG__13_n_95\,
P(9) => \ARG__13_n_96\,
P(8) => \ARG__13_n_97\,
P(7) => \ARG__13_n_98\,
P(6) => \ARG__13_n_99\,
P(5) => \ARG__13_n_100\,
P(4) => \ARG__13_n_101\,
P(3) => \ARG__13_n_102\,
P(2) => \ARG__13_n_103\,
P(1) => \ARG__13_n_104\,
P(0) => \ARG__13_n_105\,
PATTERNBDETECT => \NLW_ARG__13_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__13_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__13_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__13_UNDERFLOW_UNCONNECTED\
);
\ARG__13_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_25\(14),
O => \ARG__13_i_1_n_0\
);
\ARG__14\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[8]\(15),
A(28) => \data_pipeline_tmp_reg[8]\(15),
A(27) => \data_pipeline_tmp_reg[8]\(15),
A(26) => \data_pipeline_tmp_reg[8]\(15),
A(25) => \data_pipeline_tmp_reg[8]\(15),
A(24) => \data_pipeline_tmp_reg[8]\(15),
A(23) => \data_pipeline_tmp_reg[8]\(15),
A(22) => \data_pipeline_tmp_reg[8]\(15),
A(21) => \data_pipeline_tmp_reg[8]\(15),
A(20) => \data_pipeline_tmp_reg[8]\(15),
A(19) => \data_pipeline_tmp_reg[8]\(15),
A(18) => \data_pipeline_tmp_reg[8]\(15),
A(17) => \data_pipeline_tmp_reg[8]\(15),
A(16) => \data_pipeline_tmp_reg[8]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[8]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__14_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[8]_7\(15),
B(16) => \weight_reg[8]_7\(15),
B(15 downto 0) => \weight_reg[8]_7\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__14_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_8\(14),
C(12) => \ARG__14_i_1_n_0\,
C(11) => \ARG__14_i_1_n_0\,
C(10) => \ARG__14_i_1_n_0\,
C(9) => \ARG__14_i_1_n_0\,
C(8) => \ARG__14_i_1_n_0\,
C(7) => \ARG__14_i_1_n_0\,
C(6) => \ARG__14_i_1_n_0\,
C(5) => \ARG__14_i_1_n_0\,
C(4) => \ARG__14_i_1_n_0\,
C(3) => \ARG__14_i_1_n_0\,
C(2) => \ARG__14_i_1_n_0\,
C(1) => \ARG__14_i_1_n_0\,
C(0) => \ARG__14_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__14_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__14_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__14_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__14_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__14_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE30(15 downto 0),
P(13) => \ARG__14_n_92\,
P(12) => \ARG__14_n_93\,
P(11) => \ARG__14_n_94\,
P(10) => \ARG__14_n_95\,
P(9) => \ARG__14_n_96\,
P(8) => \ARG__14_n_97\,
P(7) => \ARG__14_n_98\,
P(6) => \ARG__14_n_99\,
P(5) => \ARG__14_n_100\,
P(4) => \ARG__14_n_101\,
P(3) => \ARG__14_n_102\,
P(2) => \ARG__14_n_103\,
P(1) => \ARG__14_n_104\,
P(0) => \ARG__14_n_105\,
PATTERNBDETECT => \NLW_ARG__14_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__14_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__14_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__14_UNDERFLOW_UNCONNECTED\
);
\ARG__14_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_8\(14),
O => \ARG__14_i_1_n_0\
);
\ARG__15\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[9]\(15),
A(28) => \data_pipeline_tmp_reg[9]\(15),
A(27) => \data_pipeline_tmp_reg[9]\(15),
A(26) => \data_pipeline_tmp_reg[9]\(15),
A(25) => \data_pipeline_tmp_reg[9]\(15),
A(24) => \data_pipeline_tmp_reg[9]\(15),
A(23) => \data_pipeline_tmp_reg[9]\(15),
A(22) => \data_pipeline_tmp_reg[9]\(15),
A(21) => \data_pipeline_tmp_reg[9]\(15),
A(20) => \data_pipeline_tmp_reg[9]\(15),
A(19) => \data_pipeline_tmp_reg[9]\(15),
A(18) => \data_pipeline_tmp_reg[9]\(15),
A(17) => \data_pipeline_tmp_reg[9]\(15),
A(16) => \data_pipeline_tmp_reg[9]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[9]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__15_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__15_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_26\(14),
C(12) => \ARG__15_i_1_n_0\,
C(11) => \ARG__15_i_1_n_0\,
C(10) => \ARG__15_i_1_n_0\,
C(9) => \ARG__15_i_1_n_0\,
C(8) => \ARG__15_i_1_n_0\,
C(7) => \ARG__15_i_1_n_0\,
C(6) => \ARG__15_i_1_n_0\,
C(5) => \ARG__15_i_1_n_0\,
C(4) => \ARG__15_i_1_n_0\,
C(3) => \ARG__15_i_1_n_0\,
C(2) => \ARG__15_i_1_n_0\,
C(1) => \ARG__15_i_1_n_0\,
C(0) => \ARG__15_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__15_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__15_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__15_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__15_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__15_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__15_n_76\,
P(28) => \ARG__15_n_77\,
P(27) => \ARG__15_n_78\,
P(26) => \ARG__15_n_79\,
P(25) => \ARG__15_n_80\,
P(24) => \ARG__15_n_81\,
P(23) => \ARG__15_n_82\,
P(22) => \ARG__15_n_83\,
P(21) => \ARG__15_n_84\,
P(20) => \ARG__15_n_85\,
P(19) => \ARG__15_n_86\,
P(18) => \ARG__15_n_87\,
P(17) => \ARG__15_n_88\,
P(16) => \ARG__15_n_89\,
P(15) => \ARG__15_n_90\,
P(14) => \ARG__15_n_91\,
P(13) => \ARG__15_n_92\,
P(12) => \ARG__15_n_93\,
P(11) => \ARG__15_n_94\,
P(10) => \ARG__15_n_95\,
P(9) => \ARG__15_n_96\,
P(8) => \ARG__15_n_97\,
P(7) => \ARG__15_n_98\,
P(6) => \ARG__15_n_99\,
P(5) => \ARG__15_n_100\,
P(4) => \ARG__15_n_101\,
P(3) => \ARG__15_n_102\,
P(2) => \ARG__15_n_103\,
P(1) => \ARG__15_n_104\,
P(0) => \ARG__15_n_105\,
PATTERNBDETECT => \NLW_ARG__15_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__15_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__15_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__15_UNDERFLOW_UNCONNECTED\
);
\ARG__15_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_26\(14),
O => \ARG__15_i_1_n_0\
);
\ARG__16\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[9]\(15),
A(28) => \data_pipeline_tmp_reg[9]\(15),
A(27) => \data_pipeline_tmp_reg[9]\(15),
A(26) => \data_pipeline_tmp_reg[9]\(15),
A(25) => \data_pipeline_tmp_reg[9]\(15),
A(24) => \data_pipeline_tmp_reg[9]\(15),
A(23) => \data_pipeline_tmp_reg[9]\(15),
A(22) => \data_pipeline_tmp_reg[9]\(15),
A(21) => \data_pipeline_tmp_reg[9]\(15),
A(20) => \data_pipeline_tmp_reg[9]\(15),
A(19) => \data_pipeline_tmp_reg[9]\(15),
A(18) => \data_pipeline_tmp_reg[9]\(15),
A(17) => \data_pipeline_tmp_reg[9]\(15),
A(16) => \data_pipeline_tmp_reg[9]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[9]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__16_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[9]_8\(15),
B(16) => \weight_reg[9]_8\(15),
B(15 downto 0) => \weight_reg[9]_8\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__16_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_9\(14),
C(12) => \ARG__16_i_1_n_0\,
C(11) => \ARG__16_i_1_n_0\,
C(10) => \ARG__16_i_1_n_0\,
C(9) => \ARG__16_i_1_n_0\,
C(8) => \ARG__16_i_1_n_0\,
C(7) => \ARG__16_i_1_n_0\,
C(6) => \ARG__16_i_1_n_0\,
C(5) => \ARG__16_i_1_n_0\,
C(4) => \ARG__16_i_1_n_0\,
C(3) => \ARG__16_i_1_n_0\,
C(2) => \ARG__16_i_1_n_0\,
C(1) => \ARG__16_i_1_n_0\,
C(0) => \ARG__16_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__16_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__16_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__16_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__16_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__16_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE32(15 downto 0),
P(13) => \ARG__16_n_92\,
P(12) => \ARG__16_n_93\,
P(11) => \ARG__16_n_94\,
P(10) => \ARG__16_n_95\,
P(9) => \ARG__16_n_96\,
P(8) => \ARG__16_n_97\,
P(7) => \ARG__16_n_98\,
P(6) => \ARG__16_n_99\,
P(5) => \ARG__16_n_100\,
P(4) => \ARG__16_n_101\,
P(3) => \ARG__16_n_102\,
P(2) => \ARG__16_n_103\,
P(1) => \ARG__16_n_104\,
P(0) => \ARG__16_n_105\,
PATTERNBDETECT => \NLW_ARG__16_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__16_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__16_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__16_UNDERFLOW_UNCONNECTED\
);
\ARG__16_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_9\(14),
O => \ARG__16_i_1_n_0\
);
\ARG__17\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[10]\(15),
A(28) => \data_pipeline_tmp_reg[10]\(15),
A(27) => \data_pipeline_tmp_reg[10]\(15),
A(26) => \data_pipeline_tmp_reg[10]\(15),
A(25) => \data_pipeline_tmp_reg[10]\(15),
A(24) => \data_pipeline_tmp_reg[10]\(15),
A(23) => \data_pipeline_tmp_reg[10]\(15),
A(22) => \data_pipeline_tmp_reg[10]\(15),
A(21) => \data_pipeline_tmp_reg[10]\(15),
A(20) => \data_pipeline_tmp_reg[10]\(15),
A(19) => \data_pipeline_tmp_reg[10]\(15),
A(18) => \data_pipeline_tmp_reg[10]\(15),
A(17) => \data_pipeline_tmp_reg[10]\(15),
A(16) => \data_pipeline_tmp_reg[10]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[10]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__17_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__17_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_27\(14),
C(12) => \ARG__17_i_1_n_0\,
C(11) => \ARG__17_i_1_n_0\,
C(10) => \ARG__17_i_1_n_0\,
C(9) => \ARG__17_i_1_n_0\,
C(8) => \ARG__17_i_1_n_0\,
C(7) => \ARG__17_i_1_n_0\,
C(6) => \ARG__17_i_1_n_0\,
C(5) => \ARG__17_i_1_n_0\,
C(4) => \ARG__17_i_1_n_0\,
C(3) => \ARG__17_i_1_n_0\,
C(2) => \ARG__17_i_1_n_0\,
C(1) => \ARG__17_i_1_n_0\,
C(0) => \ARG__17_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__17_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__17_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__17_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__17_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__17_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__17_n_76\,
P(28) => \ARG__17_n_77\,
P(27) => \ARG__17_n_78\,
P(26) => \ARG__17_n_79\,
P(25) => \ARG__17_n_80\,
P(24) => \ARG__17_n_81\,
P(23) => \ARG__17_n_82\,
P(22) => \ARG__17_n_83\,
P(21) => \ARG__17_n_84\,
P(20) => \ARG__17_n_85\,
P(19) => \ARG__17_n_86\,
P(18) => \ARG__17_n_87\,
P(17) => \ARG__17_n_88\,
P(16) => \ARG__17_n_89\,
P(15) => \ARG__17_n_90\,
P(14) => \ARG__17_n_91\,
P(13) => \ARG__17_n_92\,
P(12) => \ARG__17_n_93\,
P(11) => \ARG__17_n_94\,
P(10) => \ARG__17_n_95\,
P(9) => \ARG__17_n_96\,
P(8) => \ARG__17_n_97\,
P(7) => \ARG__17_n_98\,
P(6) => \ARG__17_n_99\,
P(5) => \ARG__17_n_100\,
P(4) => \ARG__17_n_101\,
P(3) => \ARG__17_n_102\,
P(2) => \ARG__17_n_103\,
P(1) => \ARG__17_n_104\,
P(0) => \ARG__17_n_105\,
PATTERNBDETECT => \NLW_ARG__17_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__17_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__17_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__17_UNDERFLOW_UNCONNECTED\
);
\ARG__17_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_27\(14),
O => \ARG__17_i_1_n_0\
);
\ARG__18\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[10]\(15),
A(28) => \data_pipeline_tmp_reg[10]\(15),
A(27) => \data_pipeline_tmp_reg[10]\(15),
A(26) => \data_pipeline_tmp_reg[10]\(15),
A(25) => \data_pipeline_tmp_reg[10]\(15),
A(24) => \data_pipeline_tmp_reg[10]\(15),
A(23) => \data_pipeline_tmp_reg[10]\(15),
A(22) => \data_pipeline_tmp_reg[10]\(15),
A(21) => \data_pipeline_tmp_reg[10]\(15),
A(20) => \data_pipeline_tmp_reg[10]\(15),
A(19) => \data_pipeline_tmp_reg[10]\(15),
A(18) => \data_pipeline_tmp_reg[10]\(15),
A(17) => \data_pipeline_tmp_reg[10]\(15),
A(16) => \data_pipeline_tmp_reg[10]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[10]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__18_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[10]_9\(15),
B(16) => \weight_reg[10]_9\(15),
B(15 downto 0) => \weight_reg[10]_9\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__18_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_10\(14),
C(12) => \ARG__18_i_1_n_0\,
C(11) => \ARG__18_i_1_n_0\,
C(10) => \ARG__18_i_1_n_0\,
C(9) => \ARG__18_i_1_n_0\,
C(8) => \ARG__18_i_1_n_0\,
C(7) => \ARG__18_i_1_n_0\,
C(6) => \ARG__18_i_1_n_0\,
C(5) => \ARG__18_i_1_n_0\,
C(4) => \ARG__18_i_1_n_0\,
C(3) => \ARG__18_i_1_n_0\,
C(2) => \ARG__18_i_1_n_0\,
C(1) => \ARG__18_i_1_n_0\,
C(0) => \ARG__18_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__18_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__18_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__18_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__18_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__18_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE34(15 downto 0),
P(13) => \ARG__18_n_92\,
P(12) => \ARG__18_n_93\,
P(11) => \ARG__18_n_94\,
P(10) => \ARG__18_n_95\,
P(9) => \ARG__18_n_96\,
P(8) => \ARG__18_n_97\,
P(7) => \ARG__18_n_98\,
P(6) => \ARG__18_n_99\,
P(5) => \ARG__18_n_100\,
P(4) => \ARG__18_n_101\,
P(3) => \ARG__18_n_102\,
P(2) => \ARG__18_n_103\,
P(1) => \ARG__18_n_104\,
P(0) => \ARG__18_n_105\,
PATTERNBDETECT => \NLW_ARG__18_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__18_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__18_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__18_UNDERFLOW_UNCONNECTED\
);
\ARG__18_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_10\(14),
O => \ARG__18_i_1_n_0\
);
\ARG__19\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[11]\(15),
A(28) => \data_pipeline_tmp_reg[11]\(15),
A(27) => \data_pipeline_tmp_reg[11]\(15),
A(26) => \data_pipeline_tmp_reg[11]\(15),
A(25) => \data_pipeline_tmp_reg[11]\(15),
A(24) => \data_pipeline_tmp_reg[11]\(15),
A(23) => \data_pipeline_tmp_reg[11]\(15),
A(22) => \data_pipeline_tmp_reg[11]\(15),
A(21) => \data_pipeline_tmp_reg[11]\(15),
A(20) => \data_pipeline_tmp_reg[11]\(15),
A(19) => \data_pipeline_tmp_reg[11]\(15),
A(18) => \data_pipeline_tmp_reg[11]\(15),
A(17) => \data_pipeline_tmp_reg[11]\(15),
A(16) => \data_pipeline_tmp_reg[11]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[11]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__19_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__19_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_28\(14),
C(12) => \ARG__19_i_1_n_0\,
C(11) => \ARG__19_i_1_n_0\,
C(10) => \ARG__19_i_1_n_0\,
C(9) => \ARG__19_i_1_n_0\,
C(8) => \ARG__19_i_1_n_0\,
C(7) => \ARG__19_i_1_n_0\,
C(6) => \ARG__19_i_1_n_0\,
C(5) => \ARG__19_i_1_n_0\,
C(4) => \ARG__19_i_1_n_0\,
C(3) => \ARG__19_i_1_n_0\,
C(2) => \ARG__19_i_1_n_0\,
C(1) => \ARG__19_i_1_n_0\,
C(0) => \ARG__19_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__19_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__19_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__19_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__19_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__19_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__19_n_76\,
P(28) => \ARG__19_n_77\,
P(27) => \ARG__19_n_78\,
P(26) => \ARG__19_n_79\,
P(25) => \ARG__19_n_80\,
P(24) => \ARG__19_n_81\,
P(23) => \ARG__19_n_82\,
P(22) => \ARG__19_n_83\,
P(21) => \ARG__19_n_84\,
P(20) => \ARG__19_n_85\,
P(19) => \ARG__19_n_86\,
P(18) => \ARG__19_n_87\,
P(17) => \ARG__19_n_88\,
P(16) => \ARG__19_n_89\,
P(15) => \ARG__19_n_90\,
P(14) => \ARG__19_n_91\,
P(13) => \ARG__19_n_92\,
P(12) => \ARG__19_n_93\,
P(11) => \ARG__19_n_94\,
P(10) => \ARG__19_n_95\,
P(9) => \ARG__19_n_96\,
P(8) => \ARG__19_n_97\,
P(7) => \ARG__19_n_98\,
P(6) => \ARG__19_n_99\,
P(5) => \ARG__19_n_100\,
P(4) => \ARG__19_n_101\,
P(3) => \ARG__19_n_102\,
P(2) => \ARG__19_n_103\,
P(1) => \ARG__19_n_104\,
P(0) => \ARG__19_n_105\,
PATTERNBDETECT => \NLW_ARG__19_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__19_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__19_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__19_UNDERFLOW_UNCONNECTED\
);
\ARG__19_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_28\(14),
O => \ARG__19_i_1_n_0\
);
\ARG__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_19\(14),
O => \ARG__1_i_1_n_0\
);
\ARG__2\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[2]\(15),
A(28) => \data_pipeline_tmp_reg[2]\(15),
A(27) => \data_pipeline_tmp_reg[2]\(15),
A(26) => \data_pipeline_tmp_reg[2]\(15),
A(25) => \data_pipeline_tmp_reg[2]\(15),
A(24) => \data_pipeline_tmp_reg[2]\(15),
A(23) => \data_pipeline_tmp_reg[2]\(15),
A(22) => \data_pipeline_tmp_reg[2]\(15),
A(21) => \data_pipeline_tmp_reg[2]\(15),
A(20) => \data_pipeline_tmp_reg[2]\(15),
A(19) => \data_pipeline_tmp_reg[2]\(15),
A(18) => \data_pipeline_tmp_reg[2]\(15),
A(17) => \data_pipeline_tmp_reg[2]\(15),
A(16) => \data_pipeline_tmp_reg[2]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[2]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__2_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[2]_1\(15),
B(16) => \weight_reg[2]_1\(15),
B(15 downto 0) => \weight_reg[2]_1\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__2_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_2\(14),
C(12) => \ARG__2_i_1_n_0\,
C(11) => \ARG__2_i_1_n_0\,
C(10) => \ARG__2_i_1_n_0\,
C(9) => \ARG__2_i_1_n_0\,
C(8) => \ARG__2_i_1_n_0\,
C(7) => \ARG__2_i_1_n_0\,
C(6) => \ARG__2_i_1_n_0\,
C(5) => \ARG__2_i_1_n_0\,
C(4) => \ARG__2_i_1_n_0\,
C(3) => \ARG__2_i_1_n_0\,
C(2) => \ARG__2_i_1_n_0\,
C(1) => \ARG__2_i_1_n_0\,
C(0) => \ARG__2_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__2_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__2_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__2_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__2_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__2_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE18(15 downto 0),
P(13) => \ARG__2_n_92\,
P(12) => \ARG__2_n_93\,
P(11) => \ARG__2_n_94\,
P(10) => \ARG__2_n_95\,
P(9) => \ARG__2_n_96\,
P(8) => \ARG__2_n_97\,
P(7) => \ARG__2_n_98\,
P(6) => \ARG__2_n_99\,
P(5) => \ARG__2_n_100\,
P(4) => \ARG__2_n_101\,
P(3) => \ARG__2_n_102\,
P(2) => \ARG__2_n_103\,
P(1) => \ARG__2_n_104\,
P(0) => \ARG__2_n_105\,
PATTERNBDETECT => \NLW_ARG__2_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__2_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__2_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__2_UNDERFLOW_UNCONNECTED\
);
\ARG__20\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[11]\(15),
A(28) => \data_pipeline_tmp_reg[11]\(15),
A(27) => \data_pipeline_tmp_reg[11]\(15),
A(26) => \data_pipeline_tmp_reg[11]\(15),
A(25) => \data_pipeline_tmp_reg[11]\(15),
A(24) => \data_pipeline_tmp_reg[11]\(15),
A(23) => \data_pipeline_tmp_reg[11]\(15),
A(22) => \data_pipeline_tmp_reg[11]\(15),
A(21) => \data_pipeline_tmp_reg[11]\(15),
A(20) => \data_pipeline_tmp_reg[11]\(15),
A(19) => \data_pipeline_tmp_reg[11]\(15),
A(18) => \data_pipeline_tmp_reg[11]\(15),
A(17) => \data_pipeline_tmp_reg[11]\(15),
A(16) => \data_pipeline_tmp_reg[11]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[11]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__20_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[11]_10\(15),
B(16) => \weight_reg[11]_10\(15),
B(15 downto 0) => \weight_reg[11]_10\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__20_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_11\(14),
C(12) => \ARG__20_i_1_n_0\,
C(11) => \ARG__20_i_1_n_0\,
C(10) => \ARG__20_i_1_n_0\,
C(9) => \ARG__20_i_1_n_0\,
C(8) => \ARG__20_i_1_n_0\,
C(7) => \ARG__20_i_1_n_0\,
C(6) => \ARG__20_i_1_n_0\,
C(5) => \ARG__20_i_1_n_0\,
C(4) => \ARG__20_i_1_n_0\,
C(3) => \ARG__20_i_1_n_0\,
C(2) => \ARG__20_i_1_n_0\,
C(1) => \ARG__20_i_1_n_0\,
C(0) => \ARG__20_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__20_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__20_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__20_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__20_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__20_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE36(15 downto 0),
P(13) => \ARG__20_n_92\,
P(12) => \ARG__20_n_93\,
P(11) => \ARG__20_n_94\,
P(10) => \ARG__20_n_95\,
P(9) => \ARG__20_n_96\,
P(8) => \ARG__20_n_97\,
P(7) => \ARG__20_n_98\,
P(6) => \ARG__20_n_99\,
P(5) => \ARG__20_n_100\,
P(4) => \ARG__20_n_101\,
P(3) => \ARG__20_n_102\,
P(2) => \ARG__20_n_103\,
P(1) => \ARG__20_n_104\,
P(0) => \ARG__20_n_105\,
PATTERNBDETECT => \NLW_ARG__20_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__20_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__20_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__20_UNDERFLOW_UNCONNECTED\
);
\ARG__20_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_11\(14),
O => \ARG__20_i_1_n_0\
);
\ARG__21\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[12]\(15),
A(28) => \data_pipeline_tmp_reg[12]\(15),
A(27) => \data_pipeline_tmp_reg[12]\(15),
A(26) => \data_pipeline_tmp_reg[12]\(15),
A(25) => \data_pipeline_tmp_reg[12]\(15),
A(24) => \data_pipeline_tmp_reg[12]\(15),
A(23) => \data_pipeline_tmp_reg[12]\(15),
A(22) => \data_pipeline_tmp_reg[12]\(15),
A(21) => \data_pipeline_tmp_reg[12]\(15),
A(20) => \data_pipeline_tmp_reg[12]\(15),
A(19) => \data_pipeline_tmp_reg[12]\(15),
A(18) => \data_pipeline_tmp_reg[12]\(15),
A(17) => \data_pipeline_tmp_reg[12]\(15),
A(16) => \data_pipeline_tmp_reg[12]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[12]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__21_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__21_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_29\(14),
C(12) => \ARG__21_i_1_n_0\,
C(11) => \ARG__21_i_1_n_0\,
C(10) => \ARG__21_i_1_n_0\,
C(9) => \ARG__21_i_1_n_0\,
C(8) => \ARG__21_i_1_n_0\,
C(7) => \ARG__21_i_1_n_0\,
C(6) => \ARG__21_i_1_n_0\,
C(5) => \ARG__21_i_1_n_0\,
C(4) => \ARG__21_i_1_n_0\,
C(3) => \ARG__21_i_1_n_0\,
C(2) => \ARG__21_i_1_n_0\,
C(1) => \ARG__21_i_1_n_0\,
C(0) => \ARG__21_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__21_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__21_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__21_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__21_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__21_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__21_n_76\,
P(28) => \ARG__21_n_77\,
P(27) => \ARG__21_n_78\,
P(26) => \ARG__21_n_79\,
P(25) => \ARG__21_n_80\,
P(24) => \ARG__21_n_81\,
P(23) => \ARG__21_n_82\,
P(22) => \ARG__21_n_83\,
P(21) => \ARG__21_n_84\,
P(20) => \ARG__21_n_85\,
P(19) => \ARG__21_n_86\,
P(18) => \ARG__21_n_87\,
P(17) => \ARG__21_n_88\,
P(16) => \ARG__21_n_89\,
P(15) => \ARG__21_n_90\,
P(14) => \ARG__21_n_91\,
P(13) => \ARG__21_n_92\,
P(12) => \ARG__21_n_93\,
P(11) => \ARG__21_n_94\,
P(10) => \ARG__21_n_95\,
P(9) => \ARG__21_n_96\,
P(8) => \ARG__21_n_97\,
P(7) => \ARG__21_n_98\,
P(6) => \ARG__21_n_99\,
P(5) => \ARG__21_n_100\,
P(4) => \ARG__21_n_101\,
P(3) => \ARG__21_n_102\,
P(2) => \ARG__21_n_103\,
P(1) => \ARG__21_n_104\,
P(0) => \ARG__21_n_105\,
PATTERNBDETECT => \NLW_ARG__21_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__21_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__21_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__21_UNDERFLOW_UNCONNECTED\
);
\ARG__21_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_29\(14),
O => \ARG__21_i_1_n_0\
);
\ARG__22\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[12]\(15),
A(28) => \data_pipeline_tmp_reg[12]\(15),
A(27) => \data_pipeline_tmp_reg[12]\(15),
A(26) => \data_pipeline_tmp_reg[12]\(15),
A(25) => \data_pipeline_tmp_reg[12]\(15),
A(24) => \data_pipeline_tmp_reg[12]\(15),
A(23) => \data_pipeline_tmp_reg[12]\(15),
A(22) => \data_pipeline_tmp_reg[12]\(15),
A(21) => \data_pipeline_tmp_reg[12]\(15),
A(20) => \data_pipeline_tmp_reg[12]\(15),
A(19) => \data_pipeline_tmp_reg[12]\(15),
A(18) => \data_pipeline_tmp_reg[12]\(15),
A(17) => \data_pipeline_tmp_reg[12]\(15),
A(16) => \data_pipeline_tmp_reg[12]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[12]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__22_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[12]_11\(15),
B(16) => \weight_reg[12]_11\(15),
B(15 downto 0) => \weight_reg[12]_11\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__22_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_12\(14),
C(12) => \ARG__22_i_1_n_0\,
C(11) => \ARG__22_i_1_n_0\,
C(10) => \ARG__22_i_1_n_0\,
C(9) => \ARG__22_i_1_n_0\,
C(8) => \ARG__22_i_1_n_0\,
C(7) => \ARG__22_i_1_n_0\,
C(6) => \ARG__22_i_1_n_0\,
C(5) => \ARG__22_i_1_n_0\,
C(4) => \ARG__22_i_1_n_0\,
C(3) => \ARG__22_i_1_n_0\,
C(2) => \ARG__22_i_1_n_0\,
C(1) => \ARG__22_i_1_n_0\,
C(0) => \ARG__22_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__22_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__22_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__22_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__22_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__22_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE38(15 downto 0),
P(13) => \ARG__22_n_92\,
P(12) => \ARG__22_n_93\,
P(11) => \ARG__22_n_94\,
P(10) => \ARG__22_n_95\,
P(9) => \ARG__22_n_96\,
P(8) => \ARG__22_n_97\,
P(7) => \ARG__22_n_98\,
P(6) => \ARG__22_n_99\,
P(5) => \ARG__22_n_100\,
P(4) => \ARG__22_n_101\,
P(3) => \ARG__22_n_102\,
P(2) => \ARG__22_n_103\,
P(1) => \ARG__22_n_104\,
P(0) => \ARG__22_n_105\,
PATTERNBDETECT => \NLW_ARG__22_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__22_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__22_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__22_UNDERFLOW_UNCONNECTED\
);
\ARG__22_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_12\(14),
O => \ARG__22_i_1_n_0\
);
\ARG__23\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[13]\(15),
A(28) => \data_pipeline_tmp_reg[13]\(15),
A(27) => \data_pipeline_tmp_reg[13]\(15),
A(26) => \data_pipeline_tmp_reg[13]\(15),
A(25) => \data_pipeline_tmp_reg[13]\(15),
A(24) => \data_pipeline_tmp_reg[13]\(15),
A(23) => \data_pipeline_tmp_reg[13]\(15),
A(22) => \data_pipeline_tmp_reg[13]\(15),
A(21) => \data_pipeline_tmp_reg[13]\(15),
A(20) => \data_pipeline_tmp_reg[13]\(15),
A(19) => \data_pipeline_tmp_reg[13]\(15),
A(18) => \data_pipeline_tmp_reg[13]\(15),
A(17) => \data_pipeline_tmp_reg[13]\(15),
A(16) => \data_pipeline_tmp_reg[13]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[13]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__23_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__23_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_30\(14),
C(12) => \ARG__23_i_1_n_0\,
C(11) => \ARG__23_i_1_n_0\,
C(10) => \ARG__23_i_1_n_0\,
C(9) => \ARG__23_i_1_n_0\,
C(8) => \ARG__23_i_1_n_0\,
C(7) => \ARG__23_i_1_n_0\,
C(6) => \ARG__23_i_1_n_0\,
C(5) => \ARG__23_i_1_n_0\,
C(4) => \ARG__23_i_1_n_0\,
C(3) => \ARG__23_i_1_n_0\,
C(2) => \ARG__23_i_1_n_0\,
C(1) => \ARG__23_i_1_n_0\,
C(0) => \ARG__23_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__23_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__23_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__23_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__23_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__23_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__23_n_76\,
P(28) => \ARG__23_n_77\,
P(27) => \ARG__23_n_78\,
P(26) => \ARG__23_n_79\,
P(25) => \ARG__23_n_80\,
P(24) => \ARG__23_n_81\,
P(23) => \ARG__23_n_82\,
P(22) => \ARG__23_n_83\,
P(21) => \ARG__23_n_84\,
P(20) => \ARG__23_n_85\,
P(19) => \ARG__23_n_86\,
P(18) => \ARG__23_n_87\,
P(17) => \ARG__23_n_88\,
P(16) => \ARG__23_n_89\,
P(15) => \ARG__23_n_90\,
P(14) => \ARG__23_n_91\,
P(13) => \ARG__23_n_92\,
P(12) => \ARG__23_n_93\,
P(11) => \ARG__23_n_94\,
P(10) => \ARG__23_n_95\,
P(9) => \ARG__23_n_96\,
P(8) => \ARG__23_n_97\,
P(7) => \ARG__23_n_98\,
P(6) => \ARG__23_n_99\,
P(5) => \ARG__23_n_100\,
P(4) => \ARG__23_n_101\,
P(3) => \ARG__23_n_102\,
P(2) => \ARG__23_n_103\,
P(1) => \ARG__23_n_104\,
P(0) => \ARG__23_n_105\,
PATTERNBDETECT => \NLW_ARG__23_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__23_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__23_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__23_UNDERFLOW_UNCONNECTED\
);
\ARG__23_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_30\(14),
O => \ARG__23_i_1_n_0\
);
\ARG__24\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[13]\(15),
A(28) => \data_pipeline_tmp_reg[13]\(15),
A(27) => \data_pipeline_tmp_reg[13]\(15),
A(26) => \data_pipeline_tmp_reg[13]\(15),
A(25) => \data_pipeline_tmp_reg[13]\(15),
A(24) => \data_pipeline_tmp_reg[13]\(15),
A(23) => \data_pipeline_tmp_reg[13]\(15),
A(22) => \data_pipeline_tmp_reg[13]\(15),
A(21) => \data_pipeline_tmp_reg[13]\(15),
A(20) => \data_pipeline_tmp_reg[13]\(15),
A(19) => \data_pipeline_tmp_reg[13]\(15),
A(18) => \data_pipeline_tmp_reg[13]\(15),
A(17) => \data_pipeline_tmp_reg[13]\(15),
A(16) => \data_pipeline_tmp_reg[13]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[13]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__24_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[13]_12\(15),
B(16) => \weight_reg[13]_12\(15),
B(15 downto 0) => \weight_reg[13]_12\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__24_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_13\(14),
C(12) => \ARG__24_i_1_n_0\,
C(11) => \ARG__24_i_1_n_0\,
C(10) => \ARG__24_i_1_n_0\,
C(9) => \ARG__24_i_1_n_0\,
C(8) => \ARG__24_i_1_n_0\,
C(7) => \ARG__24_i_1_n_0\,
C(6) => \ARG__24_i_1_n_0\,
C(5) => \ARG__24_i_1_n_0\,
C(4) => \ARG__24_i_1_n_0\,
C(3) => \ARG__24_i_1_n_0\,
C(2) => \ARG__24_i_1_n_0\,
C(1) => \ARG__24_i_1_n_0\,
C(0) => \ARG__24_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__24_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__24_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__24_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__24_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__24_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE40(15 downto 0),
P(13) => \ARG__24_n_92\,
P(12) => \ARG__24_n_93\,
P(11) => \ARG__24_n_94\,
P(10) => \ARG__24_n_95\,
P(9) => \ARG__24_n_96\,
P(8) => \ARG__24_n_97\,
P(7) => \ARG__24_n_98\,
P(6) => \ARG__24_n_99\,
P(5) => \ARG__24_n_100\,
P(4) => \ARG__24_n_101\,
P(3) => \ARG__24_n_102\,
P(2) => \ARG__24_n_103\,
P(1) => \ARG__24_n_104\,
P(0) => \ARG__24_n_105\,
PATTERNBDETECT => \NLW_ARG__24_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__24_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__24_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__24_UNDERFLOW_UNCONNECTED\
);
\ARG__24_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_13\(14),
O => \ARG__24_i_1_n_0\
);
\ARG__25\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[14]\(15),
A(28) => \data_pipeline_tmp_reg[14]\(15),
A(27) => \data_pipeline_tmp_reg[14]\(15),
A(26) => \data_pipeline_tmp_reg[14]\(15),
A(25) => \data_pipeline_tmp_reg[14]\(15),
A(24) => \data_pipeline_tmp_reg[14]\(15),
A(23) => \data_pipeline_tmp_reg[14]\(15),
A(22) => \data_pipeline_tmp_reg[14]\(15),
A(21) => \data_pipeline_tmp_reg[14]\(15),
A(20) => \data_pipeline_tmp_reg[14]\(15),
A(19) => \data_pipeline_tmp_reg[14]\(15),
A(18) => \data_pipeline_tmp_reg[14]\(15),
A(17) => \data_pipeline_tmp_reg[14]\(15),
A(16) => \data_pipeline_tmp_reg[14]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[14]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__25_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__25_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_31\(14),
C(12) => \ARG__25_i_1_n_0\,
C(11) => \ARG__25_i_1_n_0\,
C(10) => \ARG__25_i_1_n_0\,
C(9) => \ARG__25_i_1_n_0\,
C(8) => \ARG__25_i_1_n_0\,
C(7) => \ARG__25_i_1_n_0\,
C(6) => \ARG__25_i_1_n_0\,
C(5) => \ARG__25_i_1_n_0\,
C(4) => \ARG__25_i_1_n_0\,
C(3) => \ARG__25_i_1_n_0\,
C(2) => \ARG__25_i_1_n_0\,
C(1) => \ARG__25_i_1_n_0\,
C(0) => \ARG__25_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__25_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__25_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__25_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__25_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__25_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__25_n_76\,
P(28) => \ARG__25_n_77\,
P(27) => \ARG__25_n_78\,
P(26) => \ARG__25_n_79\,
P(25) => \ARG__25_n_80\,
P(24) => \ARG__25_n_81\,
P(23) => \ARG__25_n_82\,
P(22) => \ARG__25_n_83\,
P(21) => \ARG__25_n_84\,
P(20) => \ARG__25_n_85\,
P(19) => \ARG__25_n_86\,
P(18) => \ARG__25_n_87\,
P(17) => \ARG__25_n_88\,
P(16) => \ARG__25_n_89\,
P(15) => \ARG__25_n_90\,
P(14) => \ARG__25_n_91\,
P(13) => \ARG__25_n_92\,
P(12) => \ARG__25_n_93\,
P(11) => \ARG__25_n_94\,
P(10) => \ARG__25_n_95\,
P(9) => \ARG__25_n_96\,
P(8) => \ARG__25_n_97\,
P(7) => \ARG__25_n_98\,
P(6) => \ARG__25_n_99\,
P(5) => \ARG__25_n_100\,
P(4) => \ARG__25_n_101\,
P(3) => \ARG__25_n_102\,
P(2) => \ARG__25_n_103\,
P(1) => \ARG__25_n_104\,
P(0) => \ARG__25_n_105\,
PATTERNBDETECT => \NLW_ARG__25_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__25_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__25_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__25_UNDERFLOW_UNCONNECTED\
);
\ARG__25_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_31\(14),
O => \ARG__25_i_1_n_0\
);
\ARG__26\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[14]\(15),
A(28) => \data_pipeline_tmp_reg[14]\(15),
A(27) => \data_pipeline_tmp_reg[14]\(15),
A(26) => \data_pipeline_tmp_reg[14]\(15),
A(25) => \data_pipeline_tmp_reg[14]\(15),
A(24) => \data_pipeline_tmp_reg[14]\(15),
A(23) => \data_pipeline_tmp_reg[14]\(15),
A(22) => \data_pipeline_tmp_reg[14]\(15),
A(21) => \data_pipeline_tmp_reg[14]\(15),
A(20) => \data_pipeline_tmp_reg[14]\(15),
A(19) => \data_pipeline_tmp_reg[14]\(15),
A(18) => \data_pipeline_tmp_reg[14]\(15),
A(17) => \data_pipeline_tmp_reg[14]\(15),
A(16) => \data_pipeline_tmp_reg[14]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[14]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__26_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[14]_13\(15),
B(16) => \weight_reg[14]_13\(15),
B(15 downto 0) => \weight_reg[14]_13\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__26_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_14\(14),
C(12) => \ARG__26_i_1_n_0\,
C(11) => \ARG__26_i_1_n_0\,
C(10) => \ARG__26_i_1_n_0\,
C(9) => \ARG__26_i_1_n_0\,
C(8) => \ARG__26_i_1_n_0\,
C(7) => \ARG__26_i_1_n_0\,
C(6) => \ARG__26_i_1_n_0\,
C(5) => \ARG__26_i_1_n_0\,
C(4) => \ARG__26_i_1_n_0\,
C(3) => \ARG__26_i_1_n_0\,
C(2) => \ARG__26_i_1_n_0\,
C(1) => \ARG__26_i_1_n_0\,
C(0) => \ARG__26_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__26_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__26_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__26_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__26_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__26_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE42(15 downto 0),
P(13) => \ARG__26_n_92\,
P(12) => \ARG__26_n_93\,
P(11) => \ARG__26_n_94\,
P(10) => \ARG__26_n_95\,
P(9) => \ARG__26_n_96\,
P(8) => \ARG__26_n_97\,
P(7) => \ARG__26_n_98\,
P(6) => \ARG__26_n_99\,
P(5) => \ARG__26_n_100\,
P(4) => \ARG__26_n_101\,
P(3) => \ARG__26_n_102\,
P(2) => \ARG__26_n_103\,
P(1) => \ARG__26_n_104\,
P(0) => \ARG__26_n_105\,
PATTERNBDETECT => \NLW_ARG__26_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__26_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__26_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__26_UNDERFLOW_UNCONNECTED\
);
\ARG__26_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_14\(14),
O => \ARG__26_i_1_n_0\
);
\ARG__27\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \write_reg_x_k_reg[15]\(15),
A(28) => \write_reg_x_k_reg[15]\(15),
A(27) => \write_reg_x_k_reg[15]\(15),
A(26) => \write_reg_x_k_reg[15]\(15),
A(25) => \write_reg_x_k_reg[15]\(15),
A(24) => \write_reg_x_k_reg[15]\(15),
A(23) => \write_reg_x_k_reg[15]\(15),
A(22) => \write_reg_x_k_reg[15]\(15),
A(21) => \write_reg_x_k_reg[15]\(15),
A(20) => \write_reg_x_k_reg[15]\(15),
A(19) => \write_reg_x_k_reg[15]\(15),
A(18) => \write_reg_x_k_reg[15]\(15),
A(17) => \write_reg_x_k_reg[15]\(15),
A(16) => \write_reg_x_k_reg[15]\(15),
A(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__27_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__27_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_32\(14),
C(12) => \ARG__27_i_1_n_0\,
C(11) => \ARG__27_i_1_n_0\,
C(10) => \ARG__27_i_1_n_0\,
C(9) => \ARG__27_i_1_n_0\,
C(8) => \ARG__27_i_1_n_0\,
C(7) => \ARG__27_i_1_n_0\,
C(6) => \ARG__27_i_1_n_0\,
C(5) => \ARG__27_i_1_n_0\,
C(4) => \ARG__27_i_1_n_0\,
C(3) => \ARG__27_i_1_n_0\,
C(2) => \ARG__27_i_1_n_0\,
C(1) => \ARG__27_i_1_n_0\,
C(0) => \ARG__27_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__27_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__27_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__27_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__27_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__27_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__27_n_76\,
P(28) => \ARG__27_n_77\,
P(27) => \ARG__27_n_78\,
P(26) => \ARG__27_n_79\,
P(25) => \ARG__27_n_80\,
P(24) => \ARG__27_n_81\,
P(23) => \ARG__27_n_82\,
P(22) => \ARG__27_n_83\,
P(21) => \ARG__27_n_84\,
P(20) => \ARG__27_n_85\,
P(19) => \ARG__27_n_86\,
P(18) => \ARG__27_n_87\,
P(17) => \ARG__27_n_88\,
P(16) => \ARG__27_n_89\,
P(15) => \ARG__27_n_90\,
P(14) => \ARG__27_n_91\,
P(13) => \ARG__27_n_92\,
P(12) => \ARG__27_n_93\,
P(11) => \ARG__27_n_94\,
P(10) => \ARG__27_n_95\,
P(9) => \ARG__27_n_96\,
P(8) => \ARG__27_n_97\,
P(7) => \ARG__27_n_98\,
P(6) => \ARG__27_n_99\,
P(5) => \ARG__27_n_100\,
P(4) => \ARG__27_n_101\,
P(3) => \ARG__27_n_102\,
P(2) => \ARG__27_n_103\,
P(1) => \ARG__27_n_104\,
P(0) => \ARG__27_n_105\,
PATTERNBDETECT => \NLW_ARG__27_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__27_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__27_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__27_UNDERFLOW_UNCONNECTED\
);
\ARG__27_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_32\(14),
O => \ARG__27_i_1_n_0\
);
\ARG__28\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \write_reg_x_k_reg[15]\(15),
A(28) => \write_reg_x_k_reg[15]\(15),
A(27) => \write_reg_x_k_reg[15]\(15),
A(26) => \write_reg_x_k_reg[15]\(15),
A(25) => \write_reg_x_k_reg[15]\(15),
A(24) => \write_reg_x_k_reg[15]\(15),
A(23) => \write_reg_x_k_reg[15]\(15),
A(22) => \write_reg_x_k_reg[15]\(15),
A(21) => \write_reg_x_k_reg[15]\(15),
A(20) => \write_reg_x_k_reg[15]\(15),
A(19) => \write_reg_x_k_reg[15]\(15),
A(18) => \write_reg_x_k_reg[15]\(15),
A(17) => \write_reg_x_k_reg[15]\(15),
A(16) => \write_reg_x_k_reg[15]\(15),
A(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__28_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[15]_14\(15),
B(16) => \weight_reg[15]_14\(15),
B(15 downto 0) => \weight_reg[15]_14\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__28_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_15\(14),
C(12) => \ARG__28_i_1_n_0\,
C(11) => \ARG__28_i_1_n_0\,
C(10) => \ARG__28_i_1_n_0\,
C(9) => \ARG__28_i_1_n_0\,
C(8) => \ARG__28_i_1_n_0\,
C(7) => \ARG__28_i_1_n_0\,
C(6) => \ARG__28_i_1_n_0\,
C(5) => \ARG__28_i_1_n_0\,
C(4) => \ARG__28_i_1_n_0\,
C(3) => \ARG__28_i_1_n_0\,
C(2) => \ARG__28_i_1_n_0\,
C(1) => \ARG__28_i_1_n_0\,
C(0) => \ARG__28_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__28_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__28_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__28_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__28_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__28_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE44(15 downto 0),
P(13) => \ARG__28_n_92\,
P(12) => \ARG__28_n_93\,
P(11) => \ARG__28_n_94\,
P(10) => \ARG__28_n_95\,
P(9) => \ARG__28_n_96\,
P(8) => \ARG__28_n_97\,
P(7) => \ARG__28_n_98\,
P(6) => \ARG__28_n_99\,
P(5) => \ARG__28_n_100\,
P(4) => \ARG__28_n_101\,
P(3) => \ARG__28_n_102\,
P(2) => \ARG__28_n_103\,
P(1) => \ARG__28_n_104\,
P(0) => \ARG__28_n_105\,
PATTERNBDETECT => \NLW_ARG__28_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__28_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__28_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__28_UNDERFLOW_UNCONNECTED\
);
\ARG__28_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_15\(14),
O => \ARG__28_i_1_n_0\
);
\ARG__29\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[0]\(15),
A(28) => \data_pipeline_tmp_reg[0]\(15),
A(27) => \data_pipeline_tmp_reg[0]\(15),
A(26) => \data_pipeline_tmp_reg[0]\(15),
A(25) => \data_pipeline_tmp_reg[0]\(15),
A(24) => \data_pipeline_tmp_reg[0]\(15),
A(23) => \data_pipeline_tmp_reg[0]\(15),
A(22) => \data_pipeline_tmp_reg[0]\(15),
A(21) => \data_pipeline_tmp_reg[0]\(15),
A(20) => \data_pipeline_tmp_reg[0]\(15),
A(19) => \data_pipeline_tmp_reg[0]\(15),
A(18) => \data_pipeline_tmp_reg[0]\(15),
A(17) => \data_pipeline_tmp_reg[0]\(15),
A(16) => \data_pipeline_tmp_reg[0]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[0]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__29_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__29_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_17\(14),
C(12) => \ARG__29_i_1_n_0\,
C(11) => \ARG__29_i_1_n_0\,
C(10) => \ARG__29_i_1_n_0\,
C(9) => \ARG__29_i_1_n_0\,
C(8) => \ARG__29_i_1_n_0\,
C(7) => \ARG__29_i_1_n_0\,
C(6) => \ARG__29_i_1_n_0\,
C(5) => \ARG__29_i_1_n_0\,
C(4) => \ARG__29_i_1_n_0\,
C(3) => \ARG__29_i_1_n_0\,
C(2) => \ARG__29_i_1_n_0\,
C(1) => \ARG__29_i_1_n_0\,
C(0) => \ARG__29_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__29_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__29_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__29_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__29_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__29_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__29_n_76\,
P(28) => \ARG__29_n_77\,
P(27) => \ARG__29_n_78\,
P(26) => \ARG__29_n_79\,
P(25) => \ARG__29_n_80\,
P(24) => \ARG__29_n_81\,
P(23) => \ARG__29_n_82\,
P(22) => \ARG__29_n_83\,
P(21) => \ARG__29_n_84\,
P(20) => \ARG__29_n_85\,
P(19) => \ARG__29_n_86\,
P(18) => \ARG__29_n_87\,
P(17) => \ARG__29_n_88\,
P(16) => \ARG__29_n_89\,
P(15) => \ARG__29_n_90\,
P(14) => \ARG__29_n_91\,
P(13) => \ARG__29_n_92\,
P(12) => \ARG__29_n_93\,
P(11) => \ARG__29_n_94\,
P(10) => \ARG__29_n_95\,
P(9) => \ARG__29_n_96\,
P(8) => \ARG__29_n_97\,
P(7) => \ARG__29_n_98\,
P(6) => \ARG__29_n_99\,
P(5) => \ARG__29_n_100\,
P(4) => \ARG__29_n_101\,
P(3) => \ARG__29_n_102\,
P(2) => \ARG__29_n_103\,
P(1) => \ARG__29_n_104\,
P(0) => \ARG__29_n_105\,
PATTERNBDETECT => \NLW_ARG__29_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__29_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__29_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__29_UNDERFLOW_UNCONNECTED\
);
\ARG__29_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_17\(14),
O => \ARG__29_i_1_n_0\
);
\ARG__2_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_2\(14),
O => \ARG__2_i_1_n_0\
);
\ARG__3\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[3]\(15),
A(28) => \data_pipeline_tmp_reg[3]\(15),
A(27) => \data_pipeline_tmp_reg[3]\(15),
A(26) => \data_pipeline_tmp_reg[3]\(15),
A(25) => \data_pipeline_tmp_reg[3]\(15),
A(24) => \data_pipeline_tmp_reg[3]\(15),
A(23) => \data_pipeline_tmp_reg[3]\(15),
A(22) => \data_pipeline_tmp_reg[3]\(15),
A(21) => \data_pipeline_tmp_reg[3]\(15),
A(20) => \data_pipeline_tmp_reg[3]\(15),
A(19) => \data_pipeline_tmp_reg[3]\(15),
A(18) => \data_pipeline_tmp_reg[3]\(15),
A(17) => \data_pipeline_tmp_reg[3]\(15),
A(16) => \data_pipeline_tmp_reg[3]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[3]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__3_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__3_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_20\(14),
C(12) => \ARG__3_i_1_n_0\,
C(11) => \ARG__3_i_1_n_0\,
C(10) => \ARG__3_i_1_n_0\,
C(9) => \ARG__3_i_1_n_0\,
C(8) => \ARG__3_i_1_n_0\,
C(7) => \ARG__3_i_1_n_0\,
C(6) => \ARG__3_i_1_n_0\,
C(5) => \ARG__3_i_1_n_0\,
C(4) => \ARG__3_i_1_n_0\,
C(3) => \ARG__3_i_1_n_0\,
C(2) => \ARG__3_i_1_n_0\,
C(1) => \ARG__3_i_1_n_0\,
C(0) => \ARG__3_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__3_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__3_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__3_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__3_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__3_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__3_n_76\,
P(28) => \ARG__3_n_77\,
P(27) => \ARG__3_n_78\,
P(26) => \ARG__3_n_79\,
P(25) => \ARG__3_n_80\,
P(24) => \ARG__3_n_81\,
P(23) => \ARG__3_n_82\,
P(22) => \ARG__3_n_83\,
P(21) => \ARG__3_n_84\,
P(20) => \ARG__3_n_85\,
P(19) => \ARG__3_n_86\,
P(18) => \ARG__3_n_87\,
P(17) => \ARG__3_n_88\,
P(16) => \ARG__3_n_89\,
P(15) => \ARG__3_n_90\,
P(14) => \ARG__3_n_91\,
P(13) => \ARG__3_n_92\,
P(12) => \ARG__3_n_93\,
P(11) => \ARG__3_n_94\,
P(10) => \ARG__3_n_95\,
P(9) => \ARG__3_n_96\,
P(8) => \ARG__3_n_97\,
P(7) => \ARG__3_n_98\,
P(6) => \ARG__3_n_99\,
P(5) => \ARG__3_n_100\,
P(4) => \ARG__3_n_101\,
P(3) => \ARG__3_n_102\,
P(2) => \ARG__3_n_103\,
P(1) => \ARG__3_n_104\,
P(0) => \ARG__3_n_105\,
PATTERNBDETECT => \NLW_ARG__3_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__3_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__3_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__3_UNDERFLOW_UNCONNECTED\
);
\ARG__30\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[0]\(15),
A(28) => \data_pipeline_tmp_reg[0]\(15),
A(27) => \data_pipeline_tmp_reg[0]\(15),
A(26) => \data_pipeline_tmp_reg[0]\(15),
A(25) => \data_pipeline_tmp_reg[0]\(15),
A(24) => \data_pipeline_tmp_reg[0]\(15),
A(23) => \data_pipeline_tmp_reg[0]\(15),
A(22) => \data_pipeline_tmp_reg[0]\(15),
A(21) => \data_pipeline_tmp_reg[0]\(15),
A(20) => \data_pipeline_tmp_reg[0]\(15),
A(19) => \data_pipeline_tmp_reg[0]\(15),
A(18) => \data_pipeline_tmp_reg[0]\(15),
A(17) => \data_pipeline_tmp_reg[0]\(15),
A(16) => \data_pipeline_tmp_reg[0]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[0]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__30_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[0]_15\(15),
B(16) => \weight_reg[0]_15\(15),
B(15 downto 0) => \weight_reg[0]_15\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__30_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp\(14),
C(12) => \ARG__30_i_1_n_0\,
C(11) => \ARG__30_i_1_n_0\,
C(10) => \ARG__30_i_1_n_0\,
C(9) => \ARG__30_i_1_n_0\,
C(8) => \ARG__30_i_1_n_0\,
C(7) => \ARG__30_i_1_n_0\,
C(6) => \ARG__30_i_1_n_0\,
C(5) => \ARG__30_i_1_n_0\,
C(4) => \ARG__30_i_1_n_0\,
C(3) => \ARG__30_i_1_n_0\,
C(2) => \ARG__30_i_1_n_0\,
C(1) => \ARG__30_i_1_n_0\,
C(0) => \ARG__30_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__30_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__30_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__30_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__30_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__30_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE15(15 downto 0),
P(13) => \ARG__30_n_92\,
P(12) => \ARG__30_n_93\,
P(11) => \ARG__30_n_94\,
P(10) => \ARG__30_n_95\,
P(9) => \ARG__30_n_96\,
P(8) => \ARG__30_n_97\,
P(7) => \ARG__30_n_98\,
P(6) => \ARG__30_n_99\,
P(5) => \ARG__30_n_100\,
P(4) => \ARG__30_n_101\,
P(3) => \ARG__30_n_102\,
P(2) => \ARG__30_n_103\,
P(1) => \ARG__30_n_104\,
P(0) => \ARG__30_n_105\,
PATTERNBDETECT => \NLW_ARG__30_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__30_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__30_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__30_UNDERFLOW_UNCONNECTED\
);
\ARG__30_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp\(14),
O => \ARG__30_i_1_n_0\
);
\ARG__3_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_20\(14),
O => \ARG__3_i_1_n_0\
);
\ARG__4\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[3]\(15),
A(28) => \data_pipeline_tmp_reg[3]\(15),
A(27) => \data_pipeline_tmp_reg[3]\(15),
A(26) => \data_pipeline_tmp_reg[3]\(15),
A(25) => \data_pipeline_tmp_reg[3]\(15),
A(24) => \data_pipeline_tmp_reg[3]\(15),
A(23) => \data_pipeline_tmp_reg[3]\(15),
A(22) => \data_pipeline_tmp_reg[3]\(15),
A(21) => \data_pipeline_tmp_reg[3]\(15),
A(20) => \data_pipeline_tmp_reg[3]\(15),
A(19) => \data_pipeline_tmp_reg[3]\(15),
A(18) => \data_pipeline_tmp_reg[3]\(15),
A(17) => \data_pipeline_tmp_reg[3]\(15),
A(16) => \data_pipeline_tmp_reg[3]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[3]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__4_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[3]_2\(15),
B(16) => \weight_reg[3]_2\(15),
B(15 downto 0) => \weight_reg[3]_2\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__4_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_3\(14),
C(12) => \ARG__4_i_1_n_0\,
C(11) => \ARG__4_i_1_n_0\,
C(10) => \ARG__4_i_1_n_0\,
C(9) => \ARG__4_i_1_n_0\,
C(8) => \ARG__4_i_1_n_0\,
C(7) => \ARG__4_i_1_n_0\,
C(6) => \ARG__4_i_1_n_0\,
C(5) => \ARG__4_i_1_n_0\,
C(4) => \ARG__4_i_1_n_0\,
C(3) => \ARG__4_i_1_n_0\,
C(2) => \ARG__4_i_1_n_0\,
C(1) => \ARG__4_i_1_n_0\,
C(0) => \ARG__4_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__4_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__4_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__4_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__4_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__4_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE20(15 downto 0),
P(13) => \ARG__4_n_92\,
P(12) => \ARG__4_n_93\,
P(11) => \ARG__4_n_94\,
P(10) => \ARG__4_n_95\,
P(9) => \ARG__4_n_96\,
P(8) => \ARG__4_n_97\,
P(7) => \ARG__4_n_98\,
P(6) => \ARG__4_n_99\,
P(5) => \ARG__4_n_100\,
P(4) => \ARG__4_n_101\,
P(3) => \ARG__4_n_102\,
P(2) => \ARG__4_n_103\,
P(1) => \ARG__4_n_104\,
P(0) => \ARG__4_n_105\,
PATTERNBDETECT => \NLW_ARG__4_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__4_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__4_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__4_UNDERFLOW_UNCONNECTED\
);
\ARG__4_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_3\(14),
O => \ARG__4_i_1_n_0\
);
\ARG__5\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[4]\(15),
A(28) => \data_pipeline_tmp_reg[4]\(15),
A(27) => \data_pipeline_tmp_reg[4]\(15),
A(26) => \data_pipeline_tmp_reg[4]\(15),
A(25) => \data_pipeline_tmp_reg[4]\(15),
A(24) => \data_pipeline_tmp_reg[4]\(15),
A(23) => \data_pipeline_tmp_reg[4]\(15),
A(22) => \data_pipeline_tmp_reg[4]\(15),
A(21) => \data_pipeline_tmp_reg[4]\(15),
A(20) => \data_pipeline_tmp_reg[4]\(15),
A(19) => \data_pipeline_tmp_reg[4]\(15),
A(18) => \data_pipeline_tmp_reg[4]\(15),
A(17) => \data_pipeline_tmp_reg[4]\(15),
A(16) => \data_pipeline_tmp_reg[4]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[4]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__5_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__5_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_21\(14),
C(12) => \ARG__5_i_1_n_0\,
C(11) => \ARG__5_i_1_n_0\,
C(10) => \ARG__5_i_1_n_0\,
C(9) => \ARG__5_i_1_n_0\,
C(8) => \ARG__5_i_1_n_0\,
C(7) => \ARG__5_i_1_n_0\,
C(6) => \ARG__5_i_1_n_0\,
C(5) => \ARG__5_i_1_n_0\,
C(4) => \ARG__5_i_1_n_0\,
C(3) => \ARG__5_i_1_n_0\,
C(2) => \ARG__5_i_1_n_0\,
C(1) => \ARG__5_i_1_n_0\,
C(0) => \ARG__5_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__5_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__5_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__5_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__5_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__5_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__5_n_76\,
P(28) => \ARG__5_n_77\,
P(27) => \ARG__5_n_78\,
P(26) => \ARG__5_n_79\,
P(25) => \ARG__5_n_80\,
P(24) => \ARG__5_n_81\,
P(23) => \ARG__5_n_82\,
P(22) => \ARG__5_n_83\,
P(21) => \ARG__5_n_84\,
P(20) => \ARG__5_n_85\,
P(19) => \ARG__5_n_86\,
P(18) => \ARG__5_n_87\,
P(17) => \ARG__5_n_88\,
P(16) => \ARG__5_n_89\,
P(15) => \ARG__5_n_90\,
P(14) => \ARG__5_n_91\,
P(13) => \ARG__5_n_92\,
P(12) => \ARG__5_n_93\,
P(11) => \ARG__5_n_94\,
P(10) => \ARG__5_n_95\,
P(9) => \ARG__5_n_96\,
P(8) => \ARG__5_n_97\,
P(7) => \ARG__5_n_98\,
P(6) => \ARG__5_n_99\,
P(5) => \ARG__5_n_100\,
P(4) => \ARG__5_n_101\,
P(3) => \ARG__5_n_102\,
P(2) => \ARG__5_n_103\,
P(1) => \ARG__5_n_104\,
P(0) => \ARG__5_n_105\,
PATTERNBDETECT => \NLW_ARG__5_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__5_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__5_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__5_UNDERFLOW_UNCONNECTED\
);
\ARG__5_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_21\(14),
O => \ARG__5_i_1_n_0\
);
\ARG__6\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[4]\(15),
A(28) => \data_pipeline_tmp_reg[4]\(15),
A(27) => \data_pipeline_tmp_reg[4]\(15),
A(26) => \data_pipeline_tmp_reg[4]\(15),
A(25) => \data_pipeline_tmp_reg[4]\(15),
A(24) => \data_pipeline_tmp_reg[4]\(15),
A(23) => \data_pipeline_tmp_reg[4]\(15),
A(22) => \data_pipeline_tmp_reg[4]\(15),
A(21) => \data_pipeline_tmp_reg[4]\(15),
A(20) => \data_pipeline_tmp_reg[4]\(15),
A(19) => \data_pipeline_tmp_reg[4]\(15),
A(18) => \data_pipeline_tmp_reg[4]\(15),
A(17) => \data_pipeline_tmp_reg[4]\(15),
A(16) => \data_pipeline_tmp_reg[4]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[4]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__6_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[4]_3\(15),
B(16) => \weight_reg[4]_3\(15),
B(15 downto 0) => \weight_reg[4]_3\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__6_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_4\(14),
C(12) => \ARG__6_i_1_n_0\,
C(11) => \ARG__6_i_1_n_0\,
C(10) => \ARG__6_i_1_n_0\,
C(9) => \ARG__6_i_1_n_0\,
C(8) => \ARG__6_i_1_n_0\,
C(7) => \ARG__6_i_1_n_0\,
C(6) => \ARG__6_i_1_n_0\,
C(5) => \ARG__6_i_1_n_0\,
C(4) => \ARG__6_i_1_n_0\,
C(3) => \ARG__6_i_1_n_0\,
C(2) => \ARG__6_i_1_n_0\,
C(1) => \ARG__6_i_1_n_0\,
C(0) => \ARG__6_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__6_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__6_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__6_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__6_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__6_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE22(15 downto 0),
P(13) => \ARG__6_n_92\,
P(12) => \ARG__6_n_93\,
P(11) => \ARG__6_n_94\,
P(10) => \ARG__6_n_95\,
P(9) => \ARG__6_n_96\,
P(8) => \ARG__6_n_97\,
P(7) => \ARG__6_n_98\,
P(6) => \ARG__6_n_99\,
P(5) => \ARG__6_n_100\,
P(4) => \ARG__6_n_101\,
P(3) => \ARG__6_n_102\,
P(2) => \ARG__6_n_103\,
P(1) => \ARG__6_n_104\,
P(0) => \ARG__6_n_105\,
PATTERNBDETECT => \NLW_ARG__6_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__6_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__6_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__6_UNDERFLOW_UNCONNECTED\
);
\ARG__6_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_4\(14),
O => \ARG__6_i_1_n_0\
);
\ARG__7\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[5]\(15),
A(28) => \data_pipeline_tmp_reg[5]\(15),
A(27) => \data_pipeline_tmp_reg[5]\(15),
A(26) => \data_pipeline_tmp_reg[5]\(15),
A(25) => \data_pipeline_tmp_reg[5]\(15),
A(24) => \data_pipeline_tmp_reg[5]\(15),
A(23) => \data_pipeline_tmp_reg[5]\(15),
A(22) => \data_pipeline_tmp_reg[5]\(15),
A(21) => \data_pipeline_tmp_reg[5]\(15),
A(20) => \data_pipeline_tmp_reg[5]\(15),
A(19) => \data_pipeline_tmp_reg[5]\(15),
A(18) => \data_pipeline_tmp_reg[5]\(15),
A(17) => \data_pipeline_tmp_reg[5]\(15),
A(16) => \data_pipeline_tmp_reg[5]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[5]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__7_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__7_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_22\(14),
C(12) => \ARG__7_i_1_n_0\,
C(11) => \ARG__7_i_1_n_0\,
C(10) => \ARG__7_i_1_n_0\,
C(9) => \ARG__7_i_1_n_0\,
C(8) => \ARG__7_i_1_n_0\,
C(7) => \ARG__7_i_1_n_0\,
C(6) => \ARG__7_i_1_n_0\,
C(5) => \ARG__7_i_1_n_0\,
C(4) => \ARG__7_i_1_n_0\,
C(3) => \ARG__7_i_1_n_0\,
C(2) => \ARG__7_i_1_n_0\,
C(1) => \ARG__7_i_1_n_0\,
C(0) => \ARG__7_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__7_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__7_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__7_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__7_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__7_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__7_n_76\,
P(28) => \ARG__7_n_77\,
P(27) => \ARG__7_n_78\,
P(26) => \ARG__7_n_79\,
P(25) => \ARG__7_n_80\,
P(24) => \ARG__7_n_81\,
P(23) => \ARG__7_n_82\,
P(22) => \ARG__7_n_83\,
P(21) => \ARG__7_n_84\,
P(20) => \ARG__7_n_85\,
P(19) => \ARG__7_n_86\,
P(18) => \ARG__7_n_87\,
P(17) => \ARG__7_n_88\,
P(16) => \ARG__7_n_89\,
P(15) => \ARG__7_n_90\,
P(14) => \ARG__7_n_91\,
P(13) => \ARG__7_n_92\,
P(12) => \ARG__7_n_93\,
P(11) => \ARG__7_n_94\,
P(10) => \ARG__7_n_95\,
P(9) => \ARG__7_n_96\,
P(8) => \ARG__7_n_97\,
P(7) => \ARG__7_n_98\,
P(6) => \ARG__7_n_99\,
P(5) => \ARG__7_n_100\,
P(4) => \ARG__7_n_101\,
P(3) => \ARG__7_n_102\,
P(2) => \ARG__7_n_103\,
P(1) => \ARG__7_n_104\,
P(0) => \ARG__7_n_105\,
PATTERNBDETECT => \NLW_ARG__7_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__7_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__7_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__7_UNDERFLOW_UNCONNECTED\
);
\ARG__7_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_22\(14),
O => \ARG__7_i_1_n_0\
);
\ARG__8\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[5]\(15),
A(28) => \data_pipeline_tmp_reg[5]\(15),
A(27) => \data_pipeline_tmp_reg[5]\(15),
A(26) => \data_pipeline_tmp_reg[5]\(15),
A(25) => \data_pipeline_tmp_reg[5]\(15),
A(24) => \data_pipeline_tmp_reg[5]\(15),
A(23) => \data_pipeline_tmp_reg[5]\(15),
A(22) => \data_pipeline_tmp_reg[5]\(15),
A(21) => \data_pipeline_tmp_reg[5]\(15),
A(20) => \data_pipeline_tmp_reg[5]\(15),
A(19) => \data_pipeline_tmp_reg[5]\(15),
A(18) => \data_pipeline_tmp_reg[5]\(15),
A(17) => \data_pipeline_tmp_reg[5]\(15),
A(16) => \data_pipeline_tmp_reg[5]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[5]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__8_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[5]_4\(15),
B(16) => \weight_reg[5]_4\(15),
B(15 downto 0) => \weight_reg[5]_4\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__8_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_5\(14),
C(12) => \ARG__8_i_1_n_0\,
C(11) => \ARG__8_i_1_n_0\,
C(10) => \ARG__8_i_1_n_0\,
C(9) => \ARG__8_i_1_n_0\,
C(8) => \ARG__8_i_1_n_0\,
C(7) => \ARG__8_i_1_n_0\,
C(6) => \ARG__8_i_1_n_0\,
C(5) => \ARG__8_i_1_n_0\,
C(4) => \ARG__8_i_1_n_0\,
C(3) => \ARG__8_i_1_n_0\,
C(2) => \ARG__8_i_1_n_0\,
C(1) => \ARG__8_i_1_n_0\,
C(0) => \ARG__8_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__8_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__8_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__8_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__8_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__8_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE24(15 downto 0),
P(13) => \ARG__8_n_92\,
P(12) => \ARG__8_n_93\,
P(11) => \ARG__8_n_94\,
P(10) => \ARG__8_n_95\,
P(9) => \ARG__8_n_96\,
P(8) => \ARG__8_n_97\,
P(7) => \ARG__8_n_98\,
P(6) => \ARG__8_n_99\,
P(5) => \ARG__8_n_100\,
P(4) => \ARG__8_n_101\,
P(3) => \ARG__8_n_102\,
P(2) => \ARG__8_n_103\,
P(1) => \ARG__8_n_104\,
P(0) => \ARG__8_n_105\,
PATTERNBDETECT => \NLW_ARG__8_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__8_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__8_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__8_UNDERFLOW_UNCONNECTED\
);
\ARG__8_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_5\(14),
O => \ARG__8_i_1_n_0\
);
\ARG__9\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[6]\(15),
A(28) => \data_pipeline_tmp_reg[6]\(15),
A(27) => \data_pipeline_tmp_reg[6]\(15),
A(26) => \data_pipeline_tmp_reg[6]\(15),
A(25) => \data_pipeline_tmp_reg[6]\(15),
A(24) => \data_pipeline_tmp_reg[6]\(15),
A(23) => \data_pipeline_tmp_reg[6]\(15),
A(22) => \data_pipeline_tmp_reg[6]\(15),
A(21) => \data_pipeline_tmp_reg[6]\(15),
A(20) => \data_pipeline_tmp_reg[6]\(15),
A(19) => \data_pipeline_tmp_reg[6]\(15),
A(18) => \data_pipeline_tmp_reg[6]\(15),
A(17) => \data_pipeline_tmp_reg[6]\(15),
A(16) => \data_pipeline_tmp_reg[6]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[6]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__9_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__9_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_23\(14),
C(12) => \ARG__9_i_1_n_0\,
C(11) => \ARG__9_i_1_n_0\,
C(10) => \ARG__9_i_1_n_0\,
C(9) => \ARG__9_i_1_n_0\,
C(8) => \ARG__9_i_1_n_0\,
C(7) => \ARG__9_i_1_n_0\,
C(6) => \ARG__9_i_1_n_0\,
C(5) => \ARG__9_i_1_n_0\,
C(4) => \ARG__9_i_1_n_0\,
C(3) => \ARG__9_i_1_n_0\,
C(2) => \ARG__9_i_1_n_0\,
C(1) => \ARG__9_i_1_n_0\,
C(0) => \ARG__9_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__9_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__9_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__9_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__9_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__9_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__9_n_76\,
P(28) => \ARG__9_n_77\,
P(27) => \ARG__9_n_78\,
P(26) => \ARG__9_n_79\,
P(25) => \ARG__9_n_80\,
P(24) => \ARG__9_n_81\,
P(23) => \ARG__9_n_82\,
P(22) => \ARG__9_n_83\,
P(21) => \ARG__9_n_84\,
P(20) => \ARG__9_n_85\,
P(19) => \ARG__9_n_86\,
P(18) => \ARG__9_n_87\,
P(17) => \ARG__9_n_88\,
P(16) => \ARG__9_n_89\,
P(15) => \ARG__9_n_90\,
P(14) => \ARG__9_n_91\,
P(13) => \ARG__9_n_92\,
P(12) => \ARG__9_n_93\,
P(11) => \ARG__9_n_94\,
P(10) => \ARG__9_n_95\,
P(9) => \ARG__9_n_96\,
P(8) => \ARG__9_n_97\,
P(7) => \ARG__9_n_98\,
P(6) => \ARG__9_n_99\,
P(5) => \ARG__9_n_100\,
P(4) => \ARG__9_n_101\,
P(3) => \ARG__9_n_102\,
P(2) => \ARG__9_n_103\,
P(1) => \ARG__9_n_104\,
P(0) => \ARG__9_n_105\,
PATTERNBDETECT => \NLW_ARG__9_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__9_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__9_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__9_UNDERFLOW_UNCONNECTED\
);
\ARG__9_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_23\(14),
O => \ARG__9_i_1_n_0\
);
ARG_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => ARG_carry_n_0,
CO(2) => ARG_carry_n_1,
CO(1) => ARG_carry_n_2,
CO(0) => ARG_carry_n_3,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 1) => \^mul_temp_16\(1 downto 0),
DI(0) => '1',
O(3 downto 0) => NLW_ARG_carry_O_UNCONNECTED(3 downto 0),
S(3) => \^mul_temp_16\(2),
S(2 downto 0) => \write_reg_d_k_reg[3]\(2 downto 0)
);
\ARG_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => ARG_carry_n_0,
CO(3) => \ARG_carry__0_n_0\,
CO(2) => \ARG_carry__0_n_1\,
CO(1) => \ARG_carry__0_n_2\,
CO(0) => \ARG_carry__0_n_3\,
CYINIT => '0',
DI(3) => \^mul_temp_16\(5),
DI(2) => \^mul_temp_16\(3),
DI(1) => \^mul_temp_16\(4),
DI(0) => DI(0),
O(3 downto 0) => \ARG__31\(20 downto 17),
S(3) => \ARG_carry__0_i_2_n_0\,
S(2) => \ARG_carry__0_i_3_n_0\,
S(1) => \ARG_carry__0_i_4_n_0\,
S(0) => \^mul_temp_16\(3)
);
\ARG_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(5),
I1 => \^mul_temp_16\(6),
O => \ARG_carry__0_i_2_n_0\
);
\ARG_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(3),
I1 => \^mul_temp_16\(5),
O => \ARG_carry__0_i_3_n_0\
);
\ARG_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(3),
I1 => \^mul_temp_16\(4),
O => \ARG_carry__0_i_4_n_0\
);
\ARG_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \ARG_carry__0_n_0\,
CO(3) => \ARG_carry__1_n_0\,
CO(2) => \ARG_carry__1_n_1\,
CO(1) => \ARG_carry__1_n_2\,
CO(0) => \ARG_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^mul_temp_16\(9 downto 6),
O(3 downto 0) => \ARG__31\(24 downto 21),
S(3) => \ARG_carry__1_i_1_n_0\,
S(2) => \ARG_carry__1_i_2_n_0\,
S(1) => \ARG_carry__1_i_3_n_0\,
S(0) => \ARG_carry__1_i_4_n_0\
);
\ARG_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(9),
I1 => \^mul_temp_16\(10),
O => \ARG_carry__1_i_1_n_0\
);
\ARG_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(8),
I1 => \^mul_temp_16\(9),
O => \ARG_carry__1_i_2_n_0\
);
\ARG_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(7),
I1 => \^mul_temp_16\(8),
O => \ARG_carry__1_i_3_n_0\
);
\ARG_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(6),
I1 => \^mul_temp_16\(7),
O => \ARG_carry__1_i_4_n_0\
);
\ARG_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \ARG_carry__1_n_0\,
CO(3) => \ARG_carry__2_n_0\,
CO(2) => \ARG_carry__2_n_1\,
CO(1) => \ARG_carry__2_n_2\,
CO(0) => \ARG_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^mul_temp_16\(13 downto 10),
O(3 downto 0) => \ARG__31\(28 downto 25),
S(3) => \ARG_carry__2_i_1_n_0\,
S(2) => \ARG_carry__2_i_2_n_0\,
S(1) => \ARG_carry__2_i_3_n_0\,
S(0) => \ARG_carry__2_i_4_n_0\
);
\ARG_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(13),
I1 => \^mul_temp_16\(14),
O => \ARG_carry__2_i_1_n_0\
);
\ARG_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(12),
I1 => \^mul_temp_16\(13),
O => \ARG_carry__2_i_2_n_0\
);
\ARG_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(11),
I1 => \^mul_temp_16\(12),
O => \ARG_carry__2_i_3_n_0\
);
\ARG_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(10),
I1 => \^mul_temp_16\(11),
O => \ARG_carry__2_i_4_n_0\
);
\ARG_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \ARG_carry__2_n_0\,
CO(3 downto 1) => \NLW_ARG_carry__3_CO_UNCONNECTED\(3 downto 1),
CO(0) => \ARG_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \^mul_temp_16\(14),
O(3 downto 2) => \NLW_ARG_carry__3_O_UNCONNECTED\(3 downto 2),
O(1) => \ARG__31\(32),
O(0) => \ARG__31\(29),
S(3 downto 1) => B"001",
S(0) => \ARG_carry__3_i_1_n_0\
);
\ARG_carry__3_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(14),
I1 => \^mul_temp_16\(15),
O => \ARG_carry__3_i_1_n_0\
);
ARG_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_18\(14),
O => ARG_i_1_n_0
);
\add_temp_14__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__0_carry_n_0\,
CO(2) => \add_temp_14__0_carry_n_1\,
CO(1) => \add_temp_14__0_carry_n_2\,
CO(0) => \add_temp_14__0_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__0_carry_i_1_n_0\,
DI(2) => \add_temp_14__0_carry_i_2_n_0\,
DI(1) => \add_temp_14__0_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__0_carry_n_4\,
O(2) => \add_temp_14__0_carry_n_5\,
O(1) => \add_temp_14__0_carry_n_6\,
O(0) => \add_temp_14__0_carry_n_7\,
S(3) => \add_temp_14__0_carry_i_4_n_0\,
S(2) => \add_temp_14__0_carry_i_5_n_0\,
S(1) => \add_temp_14__0_carry_i_6_n_0\,
S(0) => \add_temp_14__0_carry_i_7_n_0\
);
\add_temp_14__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__0_carry_n_0\,
CO(3) => \add_temp_14__0_carry__0_n_0\,
CO(2) => \add_temp_14__0_carry__0_n_1\,
CO(1) => \add_temp_14__0_carry__0_n_2\,
CO(0) => \add_temp_14__0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__0_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__0_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__0_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__0_carry__0_i_4_n_0\,
O(3) => \add_temp_14__0_carry__0_n_4\,
O(2) => \add_temp_14__0_carry__0_n_5\,
O(1) => \add_temp_14__0_carry__0_n_6\,
O(0) => \add_temp_14__0_carry__0_n_7\,
S(3) => \add_temp_14__0_carry__0_i_5_n_0\,
S(2) => \add_temp_14__0_carry__0_i_6_n_0\,
S(1) => \add_temp_14__0_carry__0_i_7_n_0\,
S(0) => \add_temp_14__0_carry__0_i_8_n_0\
);
\add_temp_14__0_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(6),
I1 => RESIZE15(6),
I2 => RESIZE42(6),
O => \add_temp_14__0_carry__0_i_1_n_0\
);
\add_temp_14__0_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(5),
I1 => RESIZE15(5),
I2 => RESIZE42(5),
O => \add_temp_14__0_carry__0_i_2_n_0\
);
\add_temp_14__0_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(4),
I1 => RESIZE15(4),
I2 => RESIZE42(4),
O => \add_temp_14__0_carry__0_i_3_n_0\
);
\add_temp_14__0_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(3),
I1 => RESIZE15(3),
I2 => RESIZE42(3),
O => \add_temp_14__0_carry__0_i_4_n_0\
);
\add_temp_14__0_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(7),
I1 => RESIZE15(7),
I2 => RESIZE42(7),
I3 => \add_temp_14__0_carry__0_i_1_n_0\,
O => \add_temp_14__0_carry__0_i_5_n_0\
);
\add_temp_14__0_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(6),
I1 => RESIZE15(6),
I2 => RESIZE42(6),
I3 => \add_temp_14__0_carry__0_i_2_n_0\,
O => \add_temp_14__0_carry__0_i_6_n_0\
);
\add_temp_14__0_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(5),
I1 => RESIZE15(5),
I2 => RESIZE42(5),
I3 => \add_temp_14__0_carry__0_i_3_n_0\,
O => \add_temp_14__0_carry__0_i_7_n_0\
);
\add_temp_14__0_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(4),
I1 => RESIZE15(4),
I2 => RESIZE42(4),
I3 => \add_temp_14__0_carry__0_i_4_n_0\,
O => \add_temp_14__0_carry__0_i_8_n_0\
);
\add_temp_14__0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__0_carry__0_n_0\,
CO(3) => \add_temp_14__0_carry__1_n_0\,
CO(2) => \add_temp_14__0_carry__1_n_1\,
CO(1) => \add_temp_14__0_carry__1_n_2\,
CO(0) => \add_temp_14__0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__0_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__0_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__0_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__0_carry__1_i_4_n_0\,
O(3) => \add_temp_14__0_carry__1_n_4\,
O(2) => \add_temp_14__0_carry__1_n_5\,
O(1) => \add_temp_14__0_carry__1_n_6\,
O(0) => \add_temp_14__0_carry__1_n_7\,
S(3) => \add_temp_14__0_carry__1_i_5_n_0\,
S(2) => \add_temp_14__0_carry__1_i_6_n_0\,
S(1) => \add_temp_14__0_carry__1_i_7_n_0\,
S(0) => \add_temp_14__0_carry__1_i_8_n_0\
);
\add_temp_14__0_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(10),
I1 => RESIZE42(10),
I2 => RESIZE15(10),
O => \add_temp_14__0_carry__1_i_1_n_0\
);
\add_temp_14__0_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(9),
I1 => RESIZE42(9),
I2 => RESIZE15(9),
O => \add_temp_14__0_carry__1_i_2_n_0\
);
\add_temp_14__0_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(8),
I1 => RESIZE15(8),
I2 => RESIZE42(8),
O => \add_temp_14__0_carry__1_i_3_n_0\
);
\add_temp_14__0_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(7),
I1 => RESIZE15(7),
I2 => RESIZE42(7),
O => \add_temp_14__0_carry__1_i_4_n_0\
);
\add_temp_14__0_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(11),
I1 => RESIZE15(11),
I2 => RESIZE42(11),
I3 => \add_temp_14__0_carry__1_i_1_n_0\,
O => \add_temp_14__0_carry__1_i_5_n_0\
);
\add_temp_14__0_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(10),
I1 => RESIZE42(10),
I2 => RESIZE15(10),
I3 => \add_temp_14__0_carry__1_i_2_n_0\,
O => \add_temp_14__0_carry__1_i_6_n_0\
);
\add_temp_14__0_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(9),
I1 => RESIZE42(9),
I2 => RESIZE15(9),
I3 => \add_temp_14__0_carry__1_i_3_n_0\,
O => \add_temp_14__0_carry__1_i_7_n_0\
);
\add_temp_14__0_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(8),
I1 => RESIZE15(8),
I2 => RESIZE42(8),
I3 => \add_temp_14__0_carry__1_i_4_n_0\,
O => \add_temp_14__0_carry__1_i_8_n_0\
);
\add_temp_14__0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__0_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__0_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__0_carry__2_n_1\,
CO(1) => \add_temp_14__0_carry__2_n_2\,
CO(0) => \add_temp_14__0_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__0_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__0_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__0_carry__2_i_3_n_0\,
O(3) => \add_temp_14__0_carry__2_n_4\,
O(2) => \add_temp_14__0_carry__2_n_5\,
O(1) => \add_temp_14__0_carry__2_n_6\,
O(0) => \add_temp_14__0_carry__2_n_7\,
S(3) => \add_temp_14__0_carry__2_i_4_n_0\,
S(2) => \add_temp_14__0_carry__2_i_5_n_0\,
S(1) => \add_temp_14__0_carry__2_i_6_n_0\,
S(0) => \add_temp_14__0_carry__2_i_7_n_0\
);
\add_temp_14__0_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE15(13),
I1 => RESIZE42(13),
I2 => RESIZE44(13),
O => \add_temp_14__0_carry__2_i_1_n_0\
);
\add_temp_14__0_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(12),
I1 => RESIZE15(12),
I2 => RESIZE42(12),
O => \add_temp_14__0_carry__2_i_2_n_0\
);
\add_temp_14__0_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(11),
I1 => RESIZE15(11),
I2 => RESIZE42(11),
O => \add_temp_14__0_carry__2_i_3_n_0\
);
\add_temp_14__0_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE15(14),
I1 => RESIZE44(14),
I2 => RESIZE42(14),
I3 => RESIZE44(15),
I4 => RESIZE42(15),
I5 => RESIZE15(15),
O => \add_temp_14__0_carry__2_i_4_n_0\
);
\add_temp_14__0_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__2_i_1_n_0\,
I1 => RESIZE44(14),
I2 => RESIZE42(14),
I3 => RESIZE15(14),
O => \add_temp_14__0_carry__2_i_5_n_0\
);
\add_temp_14__0_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE15(13),
I1 => RESIZE42(13),
I2 => RESIZE44(13),
I3 => \add_temp_14__0_carry__2_i_2_n_0\,
O => \add_temp_14__0_carry__2_i_6_n_0\
);
\add_temp_14__0_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(12),
I1 => RESIZE15(12),
I2 => RESIZE42(12),
I3 => \add_temp_14__0_carry__2_i_3_n_0\,
O => \add_temp_14__0_carry__2_i_7_n_0\
);
\add_temp_14__0_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(2),
I1 => RESIZE15(2),
I2 => RESIZE42(2),
O => \add_temp_14__0_carry_i_1_n_0\
);
\add_temp_14__0_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(1),
I1 => RESIZE15(1),
I2 => RESIZE42(1),
O => \add_temp_14__0_carry_i_2_n_0\
);
\add_temp_14__0_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(0),
I1 => RESIZE15(0),
I2 => RESIZE42(0),
O => \add_temp_14__0_carry_i_3_n_0\
);
\add_temp_14__0_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(3),
I1 => RESIZE15(3),
I2 => RESIZE42(3),
I3 => \add_temp_14__0_carry_i_1_n_0\,
O => \add_temp_14__0_carry_i_4_n_0\
);
\add_temp_14__0_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(2),
I1 => RESIZE15(2),
I2 => RESIZE42(2),
I3 => \add_temp_14__0_carry_i_2_n_0\,
O => \add_temp_14__0_carry_i_5_n_0\
);
\add_temp_14__0_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(1),
I1 => RESIZE15(1),
I2 => RESIZE42(1),
I3 => \add_temp_14__0_carry_i_3_n_0\,
O => \add_temp_14__0_carry_i_6_n_0\
);
\add_temp_14__0_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE44(0),
I1 => RESIZE15(0),
I2 => RESIZE42(0),
O => \add_temp_14__0_carry_i_7_n_0\
);
\add_temp_14__138_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__138_carry_n_0\,
CO(2) => \add_temp_14__138_carry_n_1\,
CO(1) => \add_temp_14__138_carry_n_2\,
CO(0) => \add_temp_14__138_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__138_carry_i_1_n_0\,
DI(2) => \add_temp_14__138_carry_i_2_n_0\,
DI(1) => \add_temp_14__138_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__138_carry_n_4\,
O(2) => \add_temp_14__138_carry_n_5\,
O(1) => \add_temp_14__138_carry_n_6\,
O(0) => \add_temp_14__138_carry_n_7\,
S(3) => \add_temp_14__138_carry_i_4_n_0\,
S(2) => \add_temp_14__138_carry_i_5_n_0\,
S(1) => \add_temp_14__138_carry_i_6_n_0\,
S(0) => \add_temp_14__138_carry_i_7_n_0\
);
\add_temp_14__138_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__138_carry_n_0\,
CO(3) => \add_temp_14__138_carry__0_n_0\,
CO(2) => \add_temp_14__138_carry__0_n_1\,
CO(1) => \add_temp_14__138_carry__0_n_2\,
CO(0) => \add_temp_14__138_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__138_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__138_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__138_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__138_carry__0_i_4_n_0\,
O(3) => \add_temp_14__138_carry__0_n_4\,
O(2) => \add_temp_14__138_carry__0_n_5\,
O(1) => \add_temp_14__138_carry__0_n_6\,
O(0) => \add_temp_14__138_carry__0_n_7\,
S(3) => \add_temp_14__138_carry__0_i_5_n_0\,
S(2) => \add_temp_14__138_carry__0_i_6_n_0\,
S(1) => \add_temp_14__138_carry__0_i_7_n_0\,
S(0) => \add_temp_14__138_carry__0_i_8_n_0\
);
\add_temp_14__138_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(6),
I1 => RESIZE26(6),
I2 => RESIZE28(6),
O => \add_temp_14__138_carry__0_i_1_n_0\
);
\add_temp_14__138_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE28(5),
I1 => RESIZE24(5),
I2 => RESIZE26(5),
O => \add_temp_14__138_carry__0_i_2_n_0\
);
\add_temp_14__138_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(4),
I1 => RESIZE24(4),
I2 => RESIZE28(4),
O => \add_temp_14__138_carry__0_i_3_n_0\
);
\add_temp_14__138_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(3),
I1 => RESIZE28(3),
I2 => RESIZE24(3),
O => \add_temp_14__138_carry__0_i_4_n_0\
);
\add_temp_14__138_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(7),
I1 => RESIZE26(7),
I2 => RESIZE28(7),
I3 => \add_temp_14__138_carry__0_i_1_n_0\,
O => \add_temp_14__138_carry__0_i_5_n_0\
);
\add_temp_14__138_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(6),
I1 => RESIZE26(6),
I2 => RESIZE28(6),
I3 => \add_temp_14__138_carry__0_i_2_n_0\,
O => \add_temp_14__138_carry__0_i_6_n_0\
);
\add_temp_14__138_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE28(5),
I1 => RESIZE24(5),
I2 => RESIZE26(5),
I3 => \add_temp_14__138_carry__0_i_3_n_0\,
O => \add_temp_14__138_carry__0_i_7_n_0\
);
\add_temp_14__138_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE26(4),
I1 => RESIZE24(4),
I2 => RESIZE28(4),
I3 => \add_temp_14__138_carry__0_i_4_n_0\,
O => \add_temp_14__138_carry__0_i_8_n_0\
);
\add_temp_14__138_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__138_carry__0_n_0\,
CO(3) => \add_temp_14__138_carry__1_n_0\,
CO(2) => \add_temp_14__138_carry__1_n_1\,
CO(1) => \add_temp_14__138_carry__1_n_2\,
CO(0) => \add_temp_14__138_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__138_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__138_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__138_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__138_carry__1_i_4_n_0\,
O(3) => \add_temp_14__138_carry__1_n_4\,
O(2) => \add_temp_14__138_carry__1_n_5\,
O(1) => \add_temp_14__138_carry__1_n_6\,
O(0) => \add_temp_14__138_carry__1_n_7\,
S(3) => \add_temp_14__138_carry__1_i_5_n_0\,
S(2) => \add_temp_14__138_carry__1_i_6_n_0\,
S(1) => \add_temp_14__138_carry__1_i_7_n_0\,
S(0) => \add_temp_14__138_carry__1_i_8_n_0\
);
\add_temp_14__138_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(10),
I1 => RESIZE26(10),
I2 => RESIZE28(10),
O => \add_temp_14__138_carry__1_i_1_n_0\
);
\add_temp_14__138_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(9),
I1 => RESIZE26(9),
I2 => RESIZE28(9),
O => \add_temp_14__138_carry__1_i_2_n_0\
);
\add_temp_14__138_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(8),
I1 => RESIZE26(8),
I2 => RESIZE28(8),
O => \add_temp_14__138_carry__1_i_3_n_0\
);
\add_temp_14__138_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(7),
I1 => RESIZE26(7),
I2 => RESIZE28(7),
O => \add_temp_14__138_carry__1_i_4_n_0\
);
\add_temp_14__138_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(11),
I1 => RESIZE26(11),
I2 => RESIZE28(11),
I3 => \add_temp_14__138_carry__1_i_1_n_0\,
O => \add_temp_14__138_carry__1_i_5_n_0\
);
\add_temp_14__138_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(10),
I1 => RESIZE26(10),
I2 => RESIZE28(10),
I3 => \add_temp_14__138_carry__1_i_2_n_0\,
O => \add_temp_14__138_carry__1_i_6_n_0\
);
\add_temp_14__138_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(9),
I1 => RESIZE26(9),
I2 => RESIZE28(9),
I3 => \add_temp_14__138_carry__1_i_3_n_0\,
O => \add_temp_14__138_carry__1_i_7_n_0\
);
\add_temp_14__138_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(8),
I1 => RESIZE26(8),
I2 => RESIZE28(8),
I3 => \add_temp_14__138_carry__1_i_4_n_0\,
O => \add_temp_14__138_carry__1_i_8_n_0\
);
\add_temp_14__138_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__138_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__138_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__138_carry__2_n_1\,
CO(1) => \add_temp_14__138_carry__2_n_2\,
CO(0) => \add_temp_14__138_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__138_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__138_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__138_carry__2_i_3_n_0\,
O(3) => \add_temp_14__138_carry__2_n_4\,
O(2) => \add_temp_14__138_carry__2_n_5\,
O(1) => \add_temp_14__138_carry__2_n_6\,
O(0) => \add_temp_14__138_carry__2_n_7\,
S(3) => \add_temp_14__138_carry__2_i_4_n_0\,
S(2) => \add_temp_14__138_carry__2_i_5_n_0\,
S(1) => \add_temp_14__138_carry__2_i_6_n_0\,
S(0) => \add_temp_14__138_carry__2_i_7_n_0\
);
\add_temp_14__138_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(13),
I1 => RESIZE26(13),
I2 => RESIZE28(13),
O => \add_temp_14__138_carry__2_i_1_n_0\
);
\add_temp_14__138_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(12),
I1 => RESIZE26(12),
I2 => RESIZE28(12),
O => \add_temp_14__138_carry__2_i_2_n_0\
);
\add_temp_14__138_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(11),
I1 => RESIZE26(11),
I2 => RESIZE28(11),
O => \add_temp_14__138_carry__2_i_3_n_0\
);
\add_temp_14__138_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE28(14),
I1 => RESIZE26(14),
I2 => RESIZE24(14),
I3 => RESIZE26(15),
I4 => RESIZE24(15),
I5 => RESIZE28(15),
O => \add_temp_14__138_carry__2_i_4_n_0\
);
\add_temp_14__138_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__138_carry__2_i_1_n_0\,
I1 => RESIZE26(14),
I2 => RESIZE24(14),
I3 => RESIZE28(14),
O => \add_temp_14__138_carry__2_i_5_n_0\
);
\add_temp_14__138_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(13),
I1 => RESIZE26(13),
I2 => RESIZE28(13),
I3 => \add_temp_14__138_carry__2_i_2_n_0\,
O => \add_temp_14__138_carry__2_i_6_n_0\
);
\add_temp_14__138_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(12),
I1 => RESIZE26(12),
I2 => RESIZE28(12),
I3 => \add_temp_14__138_carry__2_i_3_n_0\,
O => \add_temp_14__138_carry__2_i_7_n_0\
);
\add_temp_14__138_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(2),
I1 => RESIZE28(2),
I2 => RESIZE24(2),
O => \add_temp_14__138_carry_i_1_n_0\
);
\add_temp_14__138_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(1),
I1 => RESIZE28(1),
I2 => RESIZE24(1),
O => \add_temp_14__138_carry_i_2_n_0\
);
\add_temp_14__138_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(0),
I1 => RESIZE28(0),
I2 => RESIZE24(0),
O => \add_temp_14__138_carry_i_3_n_0\
);
\add_temp_14__138_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE26(3),
I1 => RESIZE28(3),
I2 => RESIZE24(3),
I3 => \add_temp_14__138_carry_i_1_n_0\,
O => \add_temp_14__138_carry_i_4_n_0\
);
\add_temp_14__138_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE26(2),
I1 => RESIZE28(2),
I2 => RESIZE24(2),
I3 => \add_temp_14__138_carry_i_2_n_0\,
O => \add_temp_14__138_carry_i_5_n_0\
);
\add_temp_14__138_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE26(1),
I1 => RESIZE28(1),
I2 => RESIZE24(1),
I3 => \add_temp_14__138_carry_i_3_n_0\,
O => \add_temp_14__138_carry_i_6_n_0\
);
\add_temp_14__138_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE26(0),
I1 => RESIZE28(0),
I2 => RESIZE24(0),
O => \add_temp_14__138_carry_i_7_n_0\
);
\add_temp_14__184_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__184_carry_n_0\,
CO(2) => \add_temp_14__184_carry_n_1\,
CO(1) => \add_temp_14__184_carry_n_2\,
CO(0) => \add_temp_14__184_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__184_carry_i_1_n_0\,
DI(2) => \add_temp_14__184_carry_i_2_n_0\,
DI(1) => \add_temp_14__184_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__184_carry_n_4\,
O(2) => \add_temp_14__184_carry_n_5\,
O(1) => \add_temp_14__184_carry_n_6\,
O(0) => \add_temp_14__184_carry_n_7\,
S(3) => \add_temp_14__184_carry_i_4_n_0\,
S(2) => \add_temp_14__184_carry_i_5_n_0\,
S(1) => \add_temp_14__184_carry_i_6_n_0\,
S(0) => \add_temp_14__184_carry_i_7_n_0\
);
\add_temp_14__184_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__184_carry_n_0\,
CO(3) => \add_temp_14__184_carry__0_n_0\,
CO(2) => \add_temp_14__184_carry__0_n_1\,
CO(1) => \add_temp_14__184_carry__0_n_2\,
CO(0) => \add_temp_14__184_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__184_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__184_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__184_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__184_carry__0_i_4_n_0\,
O(3) => \add_temp_14__184_carry__0_n_4\,
O(2) => \add_temp_14__184_carry__0_n_5\,
O(1) => \add_temp_14__184_carry__0_n_6\,
O(0) => \add_temp_14__184_carry__0_n_7\,
S(3) => \add_temp_14__184_carry__0_i_5_n_0\,
S(2) => \add_temp_14__184_carry__0_i_6_n_0\,
S(1) => \add_temp_14__184_carry__0_i_7_n_0\,
S(0) => \add_temp_14__184_carry__0_i_8_n_0\
);
\add_temp_14__184_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(6),
I1 => RESIZE18(6),
I2 => RESIZE22(6),
O => \add_temp_14__184_carry__0_i_1_n_0\
);
\add_temp_14__184_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(5),
I1 => RESIZE18(5),
I2 => RESIZE22(5),
O => \add_temp_14__184_carry__0_i_2_n_0\
);
\add_temp_14__184_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(4),
I1 => RESIZE18(4),
I2 => RESIZE22(4),
O => \add_temp_14__184_carry__0_i_3_n_0\
);
\add_temp_14__184_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(3),
I1 => RESIZE22(3),
I2 => RESIZE20(3),
O => \add_temp_14__184_carry__0_i_4_n_0\
);
\add_temp_14__184_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(7),
I1 => RESIZE18(7),
I2 => RESIZE22(7),
I3 => \add_temp_14__184_carry__0_i_1_n_0\,
O => \add_temp_14__184_carry__0_i_5_n_0\
);
\add_temp_14__184_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(6),
I1 => RESIZE18(6),
I2 => RESIZE22(6),
I3 => \add_temp_14__184_carry__0_i_2_n_0\,
O => \add_temp_14__184_carry__0_i_6_n_0\
);
\add_temp_14__184_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(5),
I1 => RESIZE18(5),
I2 => RESIZE22(5),
I3 => \add_temp_14__184_carry__0_i_3_n_0\,
O => \add_temp_14__184_carry__0_i_7_n_0\
);
\add_temp_14__184_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(4),
I1 => RESIZE18(4),
I2 => RESIZE22(4),
I3 => \add_temp_14__184_carry__0_i_4_n_0\,
O => \add_temp_14__184_carry__0_i_8_n_0\
);
\add_temp_14__184_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__184_carry__0_n_0\,
CO(3) => \add_temp_14__184_carry__1_n_0\,
CO(2) => \add_temp_14__184_carry__1_n_1\,
CO(1) => \add_temp_14__184_carry__1_n_2\,
CO(0) => \add_temp_14__184_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__184_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__184_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__184_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__184_carry__1_i_4_n_0\,
O(3) => \add_temp_14__184_carry__1_n_4\,
O(2) => \add_temp_14__184_carry__1_n_5\,
O(1) => \add_temp_14__184_carry__1_n_6\,
O(0) => \add_temp_14__184_carry__1_n_7\,
S(3) => \add_temp_14__184_carry__1_i_5_n_0\,
S(2) => \add_temp_14__184_carry__1_i_6_n_0\,
S(1) => \add_temp_14__184_carry__1_i_7_n_0\,
S(0) => \add_temp_14__184_carry__1_i_8_n_0\
);
\add_temp_14__184_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(10),
I1 => RESIZE22(10),
I2 => RESIZE20(10),
O => \add_temp_14__184_carry__1_i_1_n_0\
);
\add_temp_14__184_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(9),
I1 => RESIZE22(9),
I2 => RESIZE20(9),
O => \add_temp_14__184_carry__1_i_2_n_0\
);
\add_temp_14__184_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(8),
I1 => RESIZE22(8),
I2 => RESIZE20(8),
O => \add_temp_14__184_carry__1_i_3_n_0\
);
\add_temp_14__184_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(7),
I1 => RESIZE18(7),
I2 => RESIZE22(7),
O => \add_temp_14__184_carry__1_i_4_n_0\
);
\add_temp_14__184_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(11),
I1 => RESIZE22(11),
I2 => RESIZE20(11),
I3 => \add_temp_14__184_carry__1_i_1_n_0\,
O => \add_temp_14__184_carry__1_i_5_n_0\
);
\add_temp_14__184_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(10),
I1 => RESIZE22(10),
I2 => RESIZE20(10),
I3 => \add_temp_14__184_carry__1_i_2_n_0\,
O => \add_temp_14__184_carry__1_i_6_n_0\
);
\add_temp_14__184_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(9),
I1 => RESIZE22(9),
I2 => RESIZE20(9),
I3 => \add_temp_14__184_carry__1_i_3_n_0\,
O => \add_temp_14__184_carry__1_i_7_n_0\
);
\add_temp_14__184_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(8),
I1 => RESIZE22(8),
I2 => RESIZE20(8),
I3 => \add_temp_14__184_carry__1_i_4_n_0\,
O => \add_temp_14__184_carry__1_i_8_n_0\
);
\add_temp_14__184_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__184_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__184_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__184_carry__2_n_1\,
CO(1) => \add_temp_14__184_carry__2_n_2\,
CO(0) => \add_temp_14__184_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__184_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__184_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__184_carry__2_i_3_n_0\,
O(3) => \add_temp_14__184_carry__2_n_4\,
O(2) => \add_temp_14__184_carry__2_n_5\,
O(1) => \add_temp_14__184_carry__2_n_6\,
O(0) => \add_temp_14__184_carry__2_n_7\,
S(3) => \add_temp_14__184_carry__2_i_4_n_0\,
S(2) => \add_temp_14__184_carry__2_i_5_n_0\,
S(1) => \add_temp_14__184_carry__2_i_6_n_0\,
S(0) => \add_temp_14__184_carry__2_i_7_n_0\
);
\add_temp_14__184_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(13),
I1 => RESIZE22(13),
I2 => RESIZE20(13),
O => \add_temp_14__184_carry__2_i_1_n_0\
);
\add_temp_14__184_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(12),
I1 => RESIZE22(12),
I2 => RESIZE20(12),
O => \add_temp_14__184_carry__2_i_2_n_0\
);
\add_temp_14__184_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(11),
I1 => RESIZE22(11),
I2 => RESIZE20(11),
O => \add_temp_14__184_carry__2_i_3_n_0\
);
\add_temp_14__184_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE20(14),
I1 => RESIZE22(14),
I2 => RESIZE18(14),
I3 => RESIZE20(15),
I4 => RESIZE18(15),
I5 => RESIZE22(15),
O => \add_temp_14__184_carry__2_i_4_n_0\
);
\add_temp_14__184_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__184_carry__2_i_1_n_0\,
I1 => RESIZE20(14),
I2 => RESIZE18(14),
I3 => RESIZE22(14),
O => \add_temp_14__184_carry__2_i_5_n_0\
);
\add_temp_14__184_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(13),
I1 => RESIZE22(13),
I2 => RESIZE20(13),
I3 => \add_temp_14__184_carry__2_i_2_n_0\,
O => \add_temp_14__184_carry__2_i_6_n_0\
);
\add_temp_14__184_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(12),
I1 => RESIZE22(12),
I2 => RESIZE20(12),
I3 => \add_temp_14__184_carry__2_i_3_n_0\,
O => \add_temp_14__184_carry__2_i_7_n_0\
);
\add_temp_14__184_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE22(2),
I1 => RESIZE18(2),
I2 => RESIZE20(2),
O => \add_temp_14__184_carry_i_1_n_0\
);
\add_temp_14__184_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(1),
I1 => RESIZE18(1),
I2 => RESIZE22(1),
O => \add_temp_14__184_carry_i_2_n_0\
);
\add_temp_14__184_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(0),
I1 => RESIZE22(0),
I2 => RESIZE20(0),
O => \add_temp_14__184_carry_i_3_n_0\
);
\add_temp_14__184_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(3),
I1 => RESIZE22(3),
I2 => RESIZE20(3),
I3 => \add_temp_14__184_carry_i_1_n_0\,
O => \add_temp_14__184_carry_i_4_n_0\
);
\add_temp_14__184_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE22(2),
I1 => RESIZE18(2),
I2 => RESIZE20(2),
I3 => \add_temp_14__184_carry_i_2_n_0\,
O => \add_temp_14__184_carry_i_5_n_0\
);
\add_temp_14__184_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(1),
I1 => RESIZE18(1),
I2 => RESIZE22(1),
I3 => \add_temp_14__184_carry_i_3_n_0\,
O => \add_temp_14__184_carry_i_6_n_0\
);
\add_temp_14__184_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE18(0),
I1 => RESIZE22(0),
I2 => RESIZE20(0),
O => \add_temp_14__184_carry_i_7_n_0\
);
\add_temp_14__230_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__230_carry_n_0\,
CO(2) => \add_temp_14__230_carry_n_1\,
CO(1) => \add_temp_14__230_carry_n_2\,
CO(0) => \add_temp_14__230_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__230_carry_i_1_n_0\,
DI(2) => \add_temp_14__230_carry_i_2_n_0\,
DI(1) => \add_temp_14__230_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__230_carry_n_4\,
O(2) => \add_temp_14__230_carry_n_5\,
O(1) => \add_temp_14__230_carry_n_6\,
O(0) => \add_temp_14__230_carry_n_7\,
S(3) => \add_temp_14__230_carry_i_4_n_0\,
S(2) => \add_temp_14__230_carry_i_5_n_0\,
S(1) => \add_temp_14__230_carry_i_6_n_0\,
S(0) => \add_temp_14__230_carry_i_7_n_0\
);
\add_temp_14__230_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__230_carry_n_0\,
CO(3) => \add_temp_14__230_carry__0_n_0\,
CO(2) => \add_temp_14__230_carry__0_n_1\,
CO(1) => \add_temp_14__230_carry__0_n_2\,
CO(0) => \add_temp_14__230_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__230_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__230_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__230_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__230_carry__0_i_4_n_0\,
O(3) => \add_temp_14__230_carry__0_n_4\,
O(2) => \add_temp_14__230_carry__0_n_5\,
O(1) => \add_temp_14__230_carry__0_n_6\,
O(0) => \add_temp_14__230_carry__0_n_7\,
S(3) => \add_temp_14__230_carry__0_i_5_n_0\,
S(2) => \add_temp_14__230_carry__0_i_6_n_0\,
S(1) => \add_temp_14__230_carry__0_i_7_n_0\,
S(0) => \add_temp_14__230_carry__0_i_8_n_0\
);
\add_temp_14__230_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(6),
I1 => \add_temp_14__0_carry__0_n_5\,
I2 => \add_temp_14__46_carry__0_n_5\,
O => \add_temp_14__230_carry__0_i_1_n_0\
);
\add_temp_14__230_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(5),
I1 => \add_temp_14__46_carry__0_n_6\,
I2 => \add_temp_14__0_carry__0_n_6\,
O => \add_temp_14__230_carry__0_i_2_n_0\
);
\add_temp_14__230_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry__0_n_7\,
I1 => \add_temp_14__46_carry__0_n_7\,
I2 => RESIZE16(4),
O => \add_temp_14__230_carry__0_i_3_n_0\
);
\add_temp_14__230_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry_n_4\,
I1 => \add_temp_14__46_carry_n_4\,
I2 => RESIZE16(3),
O => \add_temp_14__230_carry__0_i_4_n_0\
);
\add_temp_14__230_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__0_n_4\,
I1 => \add_temp_14__46_carry__0_n_4\,
I2 => RESIZE16(7),
I3 => \add_temp_14__230_carry__0_i_1_n_0\,
O => \add_temp_14__230_carry__0_i_5_n_0\
);
\add_temp_14__230_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(6),
I1 => \add_temp_14__0_carry__0_n_5\,
I2 => \add_temp_14__46_carry__0_n_5\,
I3 => \add_temp_14__230_carry__0_i_2_n_0\,
O => \add_temp_14__230_carry__0_i_6_n_0\
);
\add_temp_14__230_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(5),
I1 => \add_temp_14__46_carry__0_n_6\,
I2 => \add_temp_14__0_carry__0_n_6\,
I3 => \add_temp_14__230_carry__0_i_3_n_0\,
O => \add_temp_14__230_carry__0_i_7_n_0\
);
\add_temp_14__230_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__0_n_7\,
I1 => \add_temp_14__46_carry__0_n_7\,
I2 => RESIZE16(4),
I3 => \add_temp_14__230_carry__0_i_4_n_0\,
O => \add_temp_14__230_carry__0_i_8_n_0\
);
\add_temp_14__230_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__230_carry__0_n_0\,
CO(3) => \add_temp_14__230_carry__1_n_0\,
CO(2) => \add_temp_14__230_carry__1_n_1\,
CO(1) => \add_temp_14__230_carry__1_n_2\,
CO(0) => \add_temp_14__230_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__230_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__230_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__230_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__230_carry__1_i_4_n_0\,
O(3) => \add_temp_14__230_carry__1_n_4\,
O(2) => \add_temp_14__230_carry__1_n_5\,
O(1) => \add_temp_14__230_carry__1_n_6\,
O(0) => \add_temp_14__230_carry__1_n_7\,
S(3) => \add_temp_14__230_carry__1_i_5_n_0\,
S(2) => \add_temp_14__230_carry__1_i_6_n_0\,
S(1) => \add_temp_14__230_carry__1_i_7_n_0\,
S(0) => \add_temp_14__230_carry__1_i_8_n_0\
);
\add_temp_14__230_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(10),
I1 => \add_temp_14__0_carry__1_n_5\,
I2 => \add_temp_14__46_carry__1_n_5\,
O => \add_temp_14__230_carry__1_i_1_n_0\
);
\add_temp_14__230_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry__1_n_6\,
I1 => \add_temp_14__46_carry__1_n_6\,
I2 => RESIZE16(9),
O => \add_temp_14__230_carry__1_i_2_n_0\
);
\add_temp_14__230_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry__1_n_7\,
I1 => RESIZE16(8),
I2 => \add_temp_14__46_carry__1_n_7\,
O => \add_temp_14__230_carry__1_i_3_n_0\
);
\add_temp_14__230_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry__0_n_4\,
I1 => \add_temp_14__46_carry__0_n_4\,
I2 => RESIZE16(7),
O => \add_temp_14__230_carry__1_i_4_n_0\
);
\add_temp_14__230_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(11),
I1 => \add_temp_14__0_carry__1_n_4\,
I2 => \add_temp_14__46_carry__1_n_4\,
I3 => \add_temp_14__230_carry__1_i_1_n_0\,
O => \add_temp_14__230_carry__1_i_5_n_0\
);
\add_temp_14__230_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(10),
I1 => \add_temp_14__0_carry__1_n_5\,
I2 => \add_temp_14__46_carry__1_n_5\,
I3 => \add_temp_14__230_carry__1_i_2_n_0\,
O => \add_temp_14__230_carry__1_i_6_n_0\
);
\add_temp_14__230_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__1_n_6\,
I1 => \add_temp_14__46_carry__1_n_6\,
I2 => RESIZE16(9),
I3 => \add_temp_14__230_carry__1_i_3_n_0\,
O => \add_temp_14__230_carry__1_i_7_n_0\
);
\add_temp_14__230_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__1_n_7\,
I1 => RESIZE16(8),
I2 => \add_temp_14__46_carry__1_n_7\,
I3 => \add_temp_14__230_carry__1_i_4_n_0\,
O => \add_temp_14__230_carry__1_i_8_n_0\
);
\add_temp_14__230_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__230_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__230_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__230_carry__2_n_1\,
CO(1) => \add_temp_14__230_carry__2_n_2\,
CO(0) => \add_temp_14__230_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__230_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__230_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__230_carry__2_i_3_n_0\,
O(3) => \add_temp_14__230_carry__2_n_4\,
O(2) => \add_temp_14__230_carry__2_n_5\,
O(1) => \add_temp_14__230_carry__2_n_6\,
O(0) => \add_temp_14__230_carry__2_n_7\,
S(3) => \add_temp_14__230_carry__2_i_4_n_0\,
S(2) => \add_temp_14__230_carry__2_i_5_n_0\,
S(1) => \add_temp_14__230_carry__2_i_6_n_0\,
S(0) => \add_temp_14__230_carry__2_i_7_n_0\
);
\add_temp_14__230_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(13),
I1 => \add_temp_14__0_carry__2_n_6\,
I2 => \add_temp_14__46_carry__2_n_6\,
O => \add_temp_14__230_carry__2_i_1_n_0\
);
\add_temp_14__230_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(12),
I1 => \add_temp_14__0_carry__2_n_7\,
I2 => \add_temp_14__46_carry__2_n_7\,
O => \add_temp_14__230_carry__2_i_2_n_0\
);
\add_temp_14__230_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(11),
I1 => \add_temp_14__0_carry__1_n_4\,
I2 => \add_temp_14__46_carry__1_n_4\,
O => \add_temp_14__230_carry__2_i_3_n_0\
);
\add_temp_14__230_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => \add_temp_14__46_carry__2_n_5\,
I1 => \add_temp_14__0_carry__2_n_5\,
I2 => RESIZE16(14),
I3 => \add_temp_14__0_carry__2_n_4\,
I4 => \add_temp_14__46_carry__2_n_4\,
I5 => RESIZE16(15),
O => \add_temp_14__230_carry__2_i_4_n_0\
);
\add_temp_14__230_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__230_carry__2_i_1_n_0\,
I1 => \add_temp_14__0_carry__2_n_5\,
I2 => \add_temp_14__46_carry__2_n_5\,
I3 => RESIZE16(14),
O => \add_temp_14__230_carry__2_i_5_n_0\
);
\add_temp_14__230_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(13),
I1 => \add_temp_14__0_carry__2_n_6\,
I2 => \add_temp_14__46_carry__2_n_6\,
I3 => \add_temp_14__230_carry__2_i_2_n_0\,
O => \add_temp_14__230_carry__2_i_6_n_0\
);
\add_temp_14__230_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(12),
I1 => \add_temp_14__0_carry__2_n_7\,
I2 => \add_temp_14__46_carry__2_n_7\,
I3 => \add_temp_14__230_carry__2_i_3_n_0\,
O => \add_temp_14__230_carry__2_i_7_n_0\
);
\add_temp_14__230_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__46_carry_n_5\,
I1 => \add_temp_14__0_carry_n_5\,
I2 => RESIZE16(2),
O => \add_temp_14__230_carry_i_1_n_0\
);
\add_temp_14__230_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry_n_6\,
I1 => RESIZE16(1),
I2 => \add_temp_14__46_carry_n_6\,
O => \add_temp_14__230_carry_i_2_n_0\
);
\add_temp_14__230_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__46_carry_n_7\,
I1 => \add_temp_14__0_carry_n_7\,
I2 => RESIZE16(0),
O => \add_temp_14__230_carry_i_3_n_0\
);
\add_temp_14__230_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry_n_4\,
I1 => \add_temp_14__46_carry_n_4\,
I2 => RESIZE16(3),
I3 => \add_temp_14__230_carry_i_1_n_0\,
O => \add_temp_14__230_carry_i_4_n_0\
);
\add_temp_14__230_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__46_carry_n_5\,
I1 => \add_temp_14__0_carry_n_5\,
I2 => RESIZE16(2),
I3 => \add_temp_14__230_carry_i_2_n_0\,
O => \add_temp_14__230_carry_i_5_n_0\
);
\add_temp_14__230_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry_n_6\,
I1 => RESIZE16(1),
I2 => \add_temp_14__46_carry_n_6\,
I3 => \add_temp_14__230_carry_i_3_n_0\,
O => \add_temp_14__230_carry_i_6_n_0\
);
\add_temp_14__230_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__46_carry_n_7\,
I1 => \add_temp_14__0_carry_n_7\,
I2 => RESIZE16(0),
O => \add_temp_14__230_carry_i_7_n_0\
);
\add_temp_14__278_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__278_carry_n_0\,
CO(2) => \add_temp_14__278_carry_n_1\,
CO(1) => \add_temp_14__278_carry_n_2\,
CO(0) => \add_temp_14__278_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__278_carry_i_1_n_0\,
DI(2) => \add_temp_14__278_carry_i_2_n_0\,
DI(1) => \add_temp_14__278_carry_i_3_n_0\,
DI(0) => \add_temp_14__92_carry_n_7\,
O(3 downto 0) => filter_sum(3 downto 0),
S(3) => \add_temp_14__278_carry_i_4_n_0\,
S(2) => \add_temp_14__278_carry_i_5_n_0\,
S(1) => \add_temp_14__278_carry_i_6_n_0\,
S(0) => \add_temp_14__278_carry_i_7_n_0\
);
\add_temp_14__278_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__278_carry_n_0\,
CO(3) => \add_temp_14__278_carry__0_n_0\,
CO(2) => \add_temp_14__278_carry__0_n_1\,
CO(1) => \add_temp_14__278_carry__0_n_2\,
CO(0) => \add_temp_14__278_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__278_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__278_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__278_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__278_carry__0_i_4_n_0\,
O(3 downto 0) => filter_sum(7 downto 4),
S(3) => \add_temp_14__278_carry__0_i_5_n_0\,
S(2) => \add_temp_14__278_carry__0_i_6_n_0\,
S(1) => \add_temp_14__278_carry__0_i_7_n_0\,
S(0) => \add_temp_14__278_carry__0_i_8_n_0\
);
\add_temp_14__278_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__0_n_5\,
I1 => \add_temp_14__230_carry__0_n_5\,
I2 => \add_temp_14__184_carry__0_n_5\,
I3 => \add_temp_14__278_carry__0_i_9_n_0\,
I4 => \add_temp_14__92_carry__0_n_5\,
O => \add_temp_14__278_carry__0_i_1_n_0\
);
\add_temp_14__278_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__230_carry__0_n_7\,
I1 => \add_temp_14__184_carry__0_n_7\,
I2 => \add_temp_14__138_carry__0_n_7\,
O => \add_temp_14__278_carry__0_i_10_n_0\
);
\add_temp_14__278_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__230_carry_n_4\,
I1 => \add_temp_14__184_carry_n_4\,
I2 => \add_temp_14__138_carry_n_4\,
O => \add_temp_14__278_carry__0_i_11_n_0\
);
\add_temp_14__278_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry__0_n_4\,
I1 => \add_temp_14__230_carry__0_n_4\,
I2 => \add_temp_14__184_carry__0_n_4\,
O => \add_temp_14__278_carry__0_i_12_n_0\
);
\add_temp_14__278_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__0_n_6\,
I1 => \add_temp_14__230_carry__0_n_6\,
I2 => \add_temp_14__184_carry__0_n_6\,
I3 => \add_temp_14__278_carry__0_i_10_n_0\,
I4 => \add_temp_14__92_carry__0_n_6\,
O => \add_temp_14__278_carry__0_i_2_n_0\
);
\add_temp_14__278_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__0_n_7\,
I1 => \add_temp_14__230_carry__0_n_7\,
I2 => \add_temp_14__184_carry__0_n_7\,
I3 => \add_temp_14__278_carry__0_i_11_n_0\,
I4 => \add_temp_14__92_carry__0_n_7\,
O => \add_temp_14__278_carry__0_i_3_n_0\
);
\add_temp_14__278_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry_n_4\,
I1 => \add_temp_14__230_carry_n_4\,
I2 => \add_temp_14__184_carry_n_4\,
I3 => \add_temp_14__278_carry_i_9_n_0\,
I4 => \add_temp_14__92_carry_n_4\,
O => \add_temp_14__278_carry__0_i_4_n_0\
);
\add_temp_14__278_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699669969696"
)
port map (
I0 => \add_temp_14__278_carry__0_i_1_n_0\,
I1 => \add_temp_14__278_carry__0_i_12_n_0\,
I2 => \add_temp_14__92_carry__0_n_4\,
I3 => \add_temp_14__138_carry__0_n_5\,
I4 => \add_temp_14__184_carry__0_n_5\,
I5 => \add_temp_14__230_carry__0_n_5\,
O => \add_temp_14__278_carry__0_i_5_n_0\
);
\add_temp_14__278_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__0_i_2_n_0\,
I1 => \add_temp_14__184_carry__0_n_5\,
I2 => \add_temp_14__230_carry__0_n_5\,
I3 => \add_temp_14__138_carry__0_n_5\,
I4 => \add_temp_14__92_carry__0_n_5\,
I5 => \add_temp_14__278_carry__0_i_9_n_0\,
O => \add_temp_14__278_carry__0_i_6_n_0\
);
\add_temp_14__278_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__0_i_3_n_0\,
I1 => \add_temp_14__184_carry__0_n_6\,
I2 => \add_temp_14__230_carry__0_n_6\,
I3 => \add_temp_14__138_carry__0_n_6\,
I4 => \add_temp_14__92_carry__0_n_6\,
I5 => \add_temp_14__278_carry__0_i_10_n_0\,
O => \add_temp_14__278_carry__0_i_7_n_0\
);
\add_temp_14__278_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__0_i_4_n_0\,
I1 => \add_temp_14__184_carry__0_n_7\,
I2 => \add_temp_14__230_carry__0_n_7\,
I3 => \add_temp_14__138_carry__0_n_7\,
I4 => \add_temp_14__92_carry__0_n_7\,
I5 => \add_temp_14__278_carry__0_i_11_n_0\,
O => \add_temp_14__278_carry__0_i_8_n_0\
);
\add_temp_14__278_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__138_carry__0_n_6\,
I1 => \add_temp_14__184_carry__0_n_6\,
I2 => \add_temp_14__230_carry__0_n_6\,
O => \add_temp_14__278_carry__0_i_9_n_0\
);
\add_temp_14__278_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__278_carry__0_n_0\,
CO(3) => \add_temp_14__278_carry__1_n_0\,
CO(2) => \add_temp_14__278_carry__1_n_1\,
CO(1) => \add_temp_14__278_carry__1_n_2\,
CO(0) => \add_temp_14__278_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__278_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__278_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__278_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__278_carry__1_i_4_n_0\,
O(3 downto 0) => filter_sum(11 downto 8),
S(3) => \add_temp_14__278_carry__1_i_5_n_0\,
S(2) => \add_temp_14__278_carry__1_i_6_n_0\,
S(1) => \add_temp_14__278_carry__1_i_7_n_0\,
S(0) => \add_temp_14__278_carry__1_i_8_n_0\
);
\add_temp_14__278_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__1_n_5\,
I1 => \add_temp_14__230_carry__1_n_5\,
I2 => \add_temp_14__184_carry__1_n_5\,
I3 => \add_temp_14__278_carry__1_i_9_n_0\,
I4 => \add_temp_14__92_carry__1_n_5\,
O => \add_temp_14__278_carry__1_i_1_n_0\
);
\add_temp_14__278_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry__1_n_7\,
I1 => \add_temp_14__138_carry__1_n_7\,
I2 => \add_temp_14__230_carry__1_n_7\,
O => \add_temp_14__278_carry__1_i_10_n_0\
);
\add_temp_14__278_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry__1_n_7\,
I1 => \add_temp_14__230_carry__1_n_7\,
I2 => \add_temp_14__184_carry__1_n_7\,
O => \add_temp_14__278_carry__1_i_11_n_0\
);
\add_temp_14__278_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry__1_n_4\,
I1 => \add_temp_14__230_carry__1_n_4\,
I2 => \add_temp_14__184_carry__1_n_4\,
O => \add_temp_14__278_carry__1_i_12_n_0\
);
\add_temp_14__278_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__1_n_6\,
I1 => \add_temp_14__230_carry__1_n_6\,
I2 => \add_temp_14__184_carry__1_n_6\,
I3 => \add_temp_14__278_carry__1_i_10_n_0\,
I4 => \add_temp_14__92_carry__1_n_6\,
O => \add_temp_14__278_carry__1_i_2_n_0\
);
\add_temp_14__278_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEAA880"
)
port map (
I0 => \add_temp_14__92_carry__1_n_7\,
I1 => \add_temp_14__138_carry__0_n_4\,
I2 => \add_temp_14__184_carry__0_n_4\,
I3 => \add_temp_14__230_carry__0_n_4\,
I4 => \add_temp_14__278_carry__1_i_11_n_0\,
O => \add_temp_14__278_carry__1_i_3_n_0\
);
\add_temp_14__278_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEAA880"
)
port map (
I0 => \add_temp_14__92_carry__0_n_4\,
I1 => \add_temp_14__230_carry__0_n_5\,
I2 => \add_temp_14__184_carry__0_n_5\,
I3 => \add_temp_14__138_carry__0_n_5\,
I4 => \add_temp_14__278_carry__0_i_12_n_0\,
O => \add_temp_14__278_carry__1_i_4_n_0\
);
\add_temp_14__278_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699669969696"
)
port map (
I0 => \add_temp_14__278_carry__1_i_1_n_0\,
I1 => \add_temp_14__278_carry__1_i_12_n_0\,
I2 => \add_temp_14__92_carry__1_n_4\,
I3 => \add_temp_14__230_carry__1_n_5\,
I4 => \add_temp_14__184_carry__1_n_5\,
I5 => \add_temp_14__138_carry__1_n_5\,
O => \add_temp_14__278_carry__1_i_5_n_0\
);
\add_temp_14__278_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__1_i_2_n_0\,
I1 => \add_temp_14__184_carry__1_n_5\,
I2 => \add_temp_14__230_carry__1_n_5\,
I3 => \add_temp_14__138_carry__1_n_5\,
I4 => \add_temp_14__92_carry__1_n_5\,
I5 => \add_temp_14__278_carry__1_i_9_n_0\,
O => \add_temp_14__278_carry__1_i_6_n_0\
);
\add_temp_14__278_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__1_i_3_n_0\,
I1 => \add_temp_14__184_carry__1_n_6\,
I2 => \add_temp_14__230_carry__1_n_6\,
I3 => \add_temp_14__138_carry__1_n_6\,
I4 => \add_temp_14__92_carry__1_n_6\,
I5 => \add_temp_14__278_carry__1_i_10_n_0\,
O => \add_temp_14__278_carry__1_i_7_n_0\
);
\add_temp_14__278_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699669969696"
)
port map (
I0 => \add_temp_14__278_carry__1_i_4_n_0\,
I1 => \add_temp_14__278_carry__1_i_11_n_0\,
I2 => \add_temp_14__92_carry__1_n_7\,
I3 => \add_temp_14__230_carry__0_n_4\,
I4 => \add_temp_14__184_carry__0_n_4\,
I5 => \add_temp_14__138_carry__0_n_4\,
O => \add_temp_14__278_carry__1_i_8_n_0\
);
\add_temp_14__278_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry__1_n_6\,
I1 => \add_temp_14__230_carry__1_n_6\,
I2 => \add_temp_14__138_carry__1_n_6\,
O => \add_temp_14__278_carry__1_i_9_n_0\
);
\add_temp_14__278_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__278_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__278_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__278_carry__2_n_1\,
CO(1) => \add_temp_14__278_carry__2_n_2\,
CO(0) => \add_temp_14__278_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__278_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__278_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__278_carry__2_i_3_n_0\,
O(3 downto 0) => filter_sum(15 downto 12),
S(3) => \add_temp_14__278_carry__2_i_4_n_0\,
S(2) => \add_temp_14__278_carry__2_i_5_n_0\,
S(1) => \add_temp_14__278_carry__2_i_6_n_0\,
S(0) => \add_temp_14__278_carry__2_i_7_n_0\
);
\add_temp_14__278_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__2_n_6\,
I1 => \add_temp_14__230_carry__2_n_6\,
I2 => \add_temp_14__184_carry__2_n_6\,
I3 => \add_temp_14__278_carry__2_i_8_n_0\,
I4 => \add_temp_14__92_carry__2_n_6\,
O => \add_temp_14__278_carry__2_i_1_n_0\
);
\add_temp_14__278_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry__2_n_6\,
I1 => \add_temp_14__230_carry__2_n_6\,
I2 => \add_temp_14__138_carry__2_n_6\,
O => \add_temp_14__278_carry__2_i_10_n_0\
);
\add_temp_14__278_carry__2_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__184_carry__2_n_4\,
I1 => \add_temp_14__230_carry__2_n_4\,
I2 => \add_temp_14__138_carry__2_n_4\,
I3 => \add_temp_14__92_carry__2_n_4\,
O => \add_temp_14__278_carry__2_i_11_n_0\
);
\add_temp_14__278_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEAA880"
)
port map (
I0 => \add_temp_14__92_carry__2_n_7\,
I1 => \add_temp_14__138_carry__1_n_4\,
I2 => \add_temp_14__184_carry__1_n_4\,
I3 => \add_temp_14__230_carry__1_n_4\,
I4 => \add_temp_14__278_carry__2_i_9_n_0\,
O => \add_temp_14__278_carry__2_i_2_n_0\
);
\add_temp_14__278_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEAA880"
)
port map (
I0 => \add_temp_14__92_carry__1_n_4\,
I1 => \add_temp_14__138_carry__1_n_5\,
I2 => \add_temp_14__184_carry__1_n_5\,
I3 => \add_temp_14__230_carry__1_n_5\,
I4 => \add_temp_14__278_carry__1_i_12_n_0\,
O => \add_temp_14__278_carry__2_i_3_n_0\
);
\add_temp_14__278_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"E187871E871E1E78"
)
port map (
I0 => \add_temp_14__92_carry__2_n_5\,
I1 => \add_temp_14__278_carry__2_i_10_n_0\,
I2 => \add_temp_14__278_carry__2_i_11_n_0\,
I3 => \add_temp_14__138_carry__2_n_5\,
I4 => \add_temp_14__184_carry__2_n_5\,
I5 => \add_temp_14__230_carry__2_n_5\,
O => \add_temp_14__278_carry__2_i_4_n_0\
);
\add_temp_14__278_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__2_i_1_n_0\,
I1 => \add_temp_14__184_carry__2_n_5\,
I2 => \add_temp_14__230_carry__2_n_5\,
I3 => \add_temp_14__138_carry__2_n_5\,
I4 => \add_temp_14__92_carry__2_n_5\,
I5 => \add_temp_14__278_carry__2_i_10_n_0\,
O => \add_temp_14__278_carry__2_i_5_n_0\
);
\add_temp_14__278_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__2_i_2_n_0\,
I1 => \add_temp_14__184_carry__2_n_6\,
I2 => \add_temp_14__230_carry__2_n_6\,
I3 => \add_temp_14__138_carry__2_n_6\,
I4 => \add_temp_14__92_carry__2_n_6\,
I5 => \add_temp_14__278_carry__2_i_8_n_0\,
O => \add_temp_14__278_carry__2_i_6_n_0\
);
\add_temp_14__278_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699669969696"
)
port map (
I0 => \add_temp_14__278_carry__2_i_3_n_0\,
I1 => \add_temp_14__278_carry__2_i_9_n_0\,
I2 => \add_temp_14__92_carry__2_n_7\,
I3 => \add_temp_14__230_carry__1_n_4\,
I4 => \add_temp_14__184_carry__1_n_4\,
I5 => \add_temp_14__138_carry__1_n_4\,
O => \add_temp_14__278_carry__2_i_7_n_0\
);
\add_temp_14__278_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry__2_n_7\,
I1 => \add_temp_14__138_carry__2_n_7\,
I2 => \add_temp_14__230_carry__2_n_7\,
O => \add_temp_14__278_carry__2_i_8_n_0\
);
\add_temp_14__278_carry__2_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry__2_n_7\,
I1 => \add_temp_14__230_carry__2_n_7\,
I2 => \add_temp_14__184_carry__2_n_7\,
O => \add_temp_14__278_carry__2_i_9_n_0\
);
\add_temp_14__278_carry_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry_n_5\,
I1 => \add_temp_14__230_carry_n_5\,
I2 => \add_temp_14__184_carry_n_5\,
I3 => \add_temp_14__278_carry_i_8_n_0\,
I4 => \add_temp_14__92_carry_n_5\,
O => \add_temp_14__278_carry_i_1_n_0\
);
\add_temp_14__278_carry_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry_n_5\,
I1 => \add_temp_14__230_carry_n_5\,
I2 => \add_temp_14__184_carry_n_5\,
O => \add_temp_14__278_carry_i_10_n_0\
);
\add_temp_14__278_carry_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \add_temp_14__278_carry_i_8_n_0\,
I1 => \add_temp_14__92_carry_n_5\,
I2 => \add_temp_14__138_carry_n_5\,
I3 => \add_temp_14__230_carry_n_5\,
I4 => \add_temp_14__184_carry_n_5\,
O => \add_temp_14__278_carry_i_2_n_0\
);
\add_temp_14__278_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__184_carry_n_6\,
I1 => \add_temp_14__230_carry_n_6\,
I2 => \add_temp_14__138_carry_n_6\,
I3 => \add_temp_14__92_carry_n_6\,
O => \add_temp_14__278_carry_i_3_n_0\
);
\add_temp_14__278_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry_i_1_n_0\,
I1 => \add_temp_14__184_carry_n_4\,
I2 => \add_temp_14__230_carry_n_4\,
I3 => \add_temp_14__138_carry_n_4\,
I4 => \add_temp_14__92_carry_n_4\,
I5 => \add_temp_14__278_carry_i_9_n_0\,
O => \add_temp_14__278_carry_i_4_n_0\
);
\add_temp_14__278_carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6999999699969666"
)
port map (
I0 => \add_temp_14__278_carry_i_10_n_0\,
I1 => \add_temp_14__92_carry_n_5\,
I2 => \add_temp_14__138_carry_n_6\,
I3 => \add_temp_14__230_carry_n_6\,
I4 => \add_temp_14__184_carry_n_6\,
I5 => \add_temp_14__92_carry_n_6\,
O => \add_temp_14__278_carry_i_5_n_0\
);
\add_temp_14__278_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"566A"
)
port map (
I0 => \add_temp_14__278_carry_i_3_n_0\,
I1 => \add_temp_14__230_carry_n_7\,
I2 => \add_temp_14__184_carry_n_7\,
I3 => \add_temp_14__138_carry_n_7\,
O => \add_temp_14__278_carry_i_6_n_0\
);
\add_temp_14__278_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__184_carry_n_7\,
I1 => \add_temp_14__230_carry_n_7\,
I2 => \add_temp_14__138_carry_n_7\,
I3 => \add_temp_14__92_carry_n_7\,
O => \add_temp_14__278_carry_i_7_n_0\
);
\add_temp_14__278_carry_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__138_carry_n_6\,
I1 => \add_temp_14__230_carry_n_6\,
I2 => \add_temp_14__184_carry_n_6\,
O => \add_temp_14__278_carry_i_8_n_0\
);
\add_temp_14__278_carry_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry_n_5\,
I1 => \add_temp_14__138_carry_n_5\,
I2 => \add_temp_14__230_carry_n_5\,
O => \add_temp_14__278_carry_i_9_n_0\
);
\add_temp_14__46_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__46_carry_n_0\,
CO(2) => \add_temp_14__46_carry_n_1\,
CO(1) => \add_temp_14__46_carry_n_2\,
CO(0) => \add_temp_14__46_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__46_carry_i_1_n_0\,
DI(2) => \add_temp_14__46_carry_i_2_n_0\,
DI(1) => \add_temp_14__46_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__46_carry_n_4\,
O(2) => \add_temp_14__46_carry_n_5\,
O(1) => \add_temp_14__46_carry_n_6\,
O(0) => \add_temp_14__46_carry_n_7\,
S(3) => \add_temp_14__46_carry_i_4_n_0\,
S(2) => \add_temp_14__46_carry_i_5_n_0\,
S(1) => \add_temp_14__46_carry_i_6_n_0\,
S(0) => \add_temp_14__46_carry_i_7_n_0\
);
\add_temp_14__46_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__46_carry_n_0\,
CO(3) => \add_temp_14__46_carry__0_n_0\,
CO(2) => \add_temp_14__46_carry__0_n_1\,
CO(1) => \add_temp_14__46_carry__0_n_2\,
CO(0) => \add_temp_14__46_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__46_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__46_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__46_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__46_carry__0_i_4_n_0\,
O(3) => \add_temp_14__46_carry__0_n_4\,
O(2) => \add_temp_14__46_carry__0_n_5\,
O(1) => \add_temp_14__46_carry__0_n_6\,
O(0) => \add_temp_14__46_carry__0_n_7\,
S(3) => \add_temp_14__46_carry__0_i_5_n_0\,
S(2) => \add_temp_14__46_carry__0_i_6_n_0\,
S(1) => \add_temp_14__46_carry__0_i_7_n_0\,
S(0) => \add_temp_14__46_carry__0_i_8_n_0\
);
\add_temp_14__46_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(6),
I1 => RESIZE40(6),
I2 => RESIZE36(6),
O => \add_temp_14__46_carry__0_i_1_n_0\
);
\add_temp_14__46_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(5),
I1 => RESIZE40(5),
I2 => RESIZE36(5),
O => \add_temp_14__46_carry__0_i_2_n_0\
);
\add_temp_14__46_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(4),
I1 => RESIZE40(4),
I2 => RESIZE36(4),
O => \add_temp_14__46_carry__0_i_3_n_0\
);
\add_temp_14__46_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(3),
I1 => RESIZE40(3),
I2 => RESIZE36(3),
O => \add_temp_14__46_carry__0_i_4_n_0\
);
\add_temp_14__46_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(7),
I1 => RESIZE40(7),
I2 => RESIZE36(7),
I3 => \add_temp_14__46_carry__0_i_1_n_0\,
O => \add_temp_14__46_carry__0_i_5_n_0\
);
\add_temp_14__46_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(6),
I1 => RESIZE40(6),
I2 => RESIZE36(6),
I3 => \add_temp_14__46_carry__0_i_2_n_0\,
O => \add_temp_14__46_carry__0_i_6_n_0\
);
\add_temp_14__46_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(5),
I1 => RESIZE40(5),
I2 => RESIZE36(5),
I3 => \add_temp_14__46_carry__0_i_3_n_0\,
O => \add_temp_14__46_carry__0_i_7_n_0\
);
\add_temp_14__46_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(4),
I1 => RESIZE40(4),
I2 => RESIZE36(4),
I3 => \add_temp_14__46_carry__0_i_4_n_0\,
O => \add_temp_14__46_carry__0_i_8_n_0\
);
\add_temp_14__46_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__46_carry__0_n_0\,
CO(3) => \add_temp_14__46_carry__1_n_0\,
CO(2) => \add_temp_14__46_carry__1_n_1\,
CO(1) => \add_temp_14__46_carry__1_n_2\,
CO(0) => \add_temp_14__46_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__46_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__46_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__46_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__46_carry__1_i_4_n_0\,
O(3) => \add_temp_14__46_carry__1_n_4\,
O(2) => \add_temp_14__46_carry__1_n_5\,
O(1) => \add_temp_14__46_carry__1_n_6\,
O(0) => \add_temp_14__46_carry__1_n_7\,
S(3) => \add_temp_14__46_carry__1_i_5_n_0\,
S(2) => \add_temp_14__46_carry__1_i_6_n_0\,
S(1) => \add_temp_14__46_carry__1_i_7_n_0\,
S(0) => \add_temp_14__46_carry__1_i_8_n_0\
);
\add_temp_14__46_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE40(10),
I1 => RESIZE36(10),
I2 => RESIZE38(10),
O => \add_temp_14__46_carry__1_i_1_n_0\
);
\add_temp_14__46_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(9),
I1 => RESIZE40(9),
I2 => RESIZE36(9),
O => \add_temp_14__46_carry__1_i_2_n_0\
);
\add_temp_14__46_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(8),
I1 => RESIZE40(8),
I2 => RESIZE36(8),
O => \add_temp_14__46_carry__1_i_3_n_0\
);
\add_temp_14__46_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(7),
I1 => RESIZE40(7),
I2 => RESIZE36(7),
O => \add_temp_14__46_carry__1_i_4_n_0\
);
\add_temp_14__46_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE36(11),
I1 => RESIZE38(11),
I2 => RESIZE40(11),
I3 => \add_temp_14__46_carry__1_i_1_n_0\,
O => \add_temp_14__46_carry__1_i_5_n_0\
);
\add_temp_14__46_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE40(10),
I1 => RESIZE36(10),
I2 => RESIZE38(10),
I3 => \add_temp_14__46_carry__1_i_2_n_0\,
O => \add_temp_14__46_carry__1_i_6_n_0\
);
\add_temp_14__46_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(9),
I1 => RESIZE40(9),
I2 => RESIZE36(9),
I3 => \add_temp_14__46_carry__1_i_3_n_0\,
O => \add_temp_14__46_carry__1_i_7_n_0\
);
\add_temp_14__46_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(8),
I1 => RESIZE40(8),
I2 => RESIZE36(8),
I3 => \add_temp_14__46_carry__1_i_4_n_0\,
O => \add_temp_14__46_carry__1_i_8_n_0\
);
\add_temp_14__46_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__46_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__46_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__46_carry__2_n_1\,
CO(1) => \add_temp_14__46_carry__2_n_2\,
CO(0) => \add_temp_14__46_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__46_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__46_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__46_carry__2_i_3_n_0\,
O(3) => \add_temp_14__46_carry__2_n_4\,
O(2) => \add_temp_14__46_carry__2_n_5\,
O(1) => \add_temp_14__46_carry__2_n_6\,
O(0) => \add_temp_14__46_carry__2_n_7\,
S(3) => \add_temp_14__46_carry__2_i_4_n_0\,
S(2) => \add_temp_14__46_carry__2_i_5_n_0\,
S(1) => \add_temp_14__46_carry__2_i_6_n_0\,
S(0) => \add_temp_14__46_carry__2_i_7_n_0\
);
\add_temp_14__46_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE36(13),
I1 => RESIZE38(13),
I2 => RESIZE40(13),
O => \add_temp_14__46_carry__2_i_1_n_0\
);
\add_temp_14__46_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE36(12),
I1 => RESIZE38(12),
I2 => RESIZE40(12),
O => \add_temp_14__46_carry__2_i_2_n_0\
);
\add_temp_14__46_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE36(11),
I1 => RESIZE38(11),
I2 => RESIZE40(11),
O => \add_temp_14__46_carry__2_i_3_n_0\
);
\add_temp_14__46_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE40(14),
I1 => RESIZE38(14),
I2 => RESIZE36(14),
I3 => RESIZE38(15),
I4 => RESIZE36(15),
I5 => RESIZE40(15),
O => \add_temp_14__46_carry__2_i_4_n_0\
);
\add_temp_14__46_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__46_carry__2_i_1_n_0\,
I1 => RESIZE38(14),
I2 => RESIZE36(14),
I3 => RESIZE40(14),
O => \add_temp_14__46_carry__2_i_5_n_0\
);
\add_temp_14__46_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE36(13),
I1 => RESIZE38(13),
I2 => RESIZE40(13),
I3 => \add_temp_14__46_carry__2_i_2_n_0\,
O => \add_temp_14__46_carry__2_i_6_n_0\
);
\add_temp_14__46_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE36(12),
I1 => RESIZE38(12),
I2 => RESIZE40(12),
I3 => \add_temp_14__46_carry__2_i_3_n_0\,
O => \add_temp_14__46_carry__2_i_7_n_0\
);
\add_temp_14__46_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(2),
I1 => RESIZE40(2),
I2 => RESIZE36(2),
O => \add_temp_14__46_carry_i_1_n_0\
);
\add_temp_14__46_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(1),
I1 => RESIZE40(1),
I2 => RESIZE36(1),
O => \add_temp_14__46_carry_i_2_n_0\
);
\add_temp_14__46_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(0),
I1 => RESIZE40(0),
I2 => RESIZE36(0),
O => \add_temp_14__46_carry_i_3_n_0\
);
\add_temp_14__46_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(3),
I1 => RESIZE40(3),
I2 => RESIZE36(3),
I3 => \add_temp_14__46_carry_i_1_n_0\,
O => \add_temp_14__46_carry_i_4_n_0\
);
\add_temp_14__46_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(2),
I1 => RESIZE40(2),
I2 => RESIZE36(2),
I3 => \add_temp_14__46_carry_i_2_n_0\,
O => \add_temp_14__46_carry_i_5_n_0\
);
\add_temp_14__46_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(1),
I1 => RESIZE40(1),
I2 => RESIZE36(1),
I3 => \add_temp_14__46_carry_i_3_n_0\,
O => \add_temp_14__46_carry_i_6_n_0\
);
\add_temp_14__46_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE38(0),
I1 => RESIZE40(0),
I2 => RESIZE36(0),
O => \add_temp_14__46_carry_i_7_n_0\
);
\add_temp_14__92_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__92_carry_n_0\,
CO(2) => \add_temp_14__92_carry_n_1\,
CO(1) => \add_temp_14__92_carry_n_2\,
CO(0) => \add_temp_14__92_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__92_carry_i_1_n_0\,
DI(2) => \add_temp_14__92_carry_i_2_n_0\,
DI(1) => \add_temp_14__92_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__92_carry_n_4\,
O(2) => \add_temp_14__92_carry_n_5\,
O(1) => \add_temp_14__92_carry_n_6\,
O(0) => \add_temp_14__92_carry_n_7\,
S(3) => \add_temp_14__92_carry_i_4_n_0\,
S(2) => \add_temp_14__92_carry_i_5_n_0\,
S(1) => \add_temp_14__92_carry_i_6_n_0\,
S(0) => \add_temp_14__92_carry_i_7_n_0\
);
\add_temp_14__92_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__92_carry_n_0\,
CO(3) => \add_temp_14__92_carry__0_n_0\,
CO(2) => \add_temp_14__92_carry__0_n_1\,
CO(1) => \add_temp_14__92_carry__0_n_2\,
CO(0) => \add_temp_14__92_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__92_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__92_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__92_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__92_carry__0_i_4_n_0\,
O(3) => \add_temp_14__92_carry__0_n_4\,
O(2) => \add_temp_14__92_carry__0_n_5\,
O(1) => \add_temp_14__92_carry__0_n_6\,
O(0) => \add_temp_14__92_carry__0_n_7\,
S(3) => \add_temp_14__92_carry__0_i_5_n_0\,
S(2) => \add_temp_14__92_carry__0_i_6_n_0\,
S(1) => \add_temp_14__92_carry__0_i_7_n_0\,
S(0) => \add_temp_14__92_carry__0_i_8_n_0\
);
\add_temp_14__92_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(6),
I1 => RESIZE34(6),
I2 => RESIZE30(6),
O => \add_temp_14__92_carry__0_i_1_n_0\
);
\add_temp_14__92_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(5),
I1 => RESIZE34(5),
I2 => RESIZE30(5),
O => \add_temp_14__92_carry__0_i_2_n_0\
);
\add_temp_14__92_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(4),
I1 => RESIZE34(4),
I2 => RESIZE30(4),
O => \add_temp_14__92_carry__0_i_3_n_0\
);
\add_temp_14__92_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(3),
I1 => RESIZE34(3),
I2 => RESIZE30(3),
O => \add_temp_14__92_carry__0_i_4_n_0\
);
\add_temp_14__92_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE34(7),
I1 => RESIZE30(7),
I2 => RESIZE32(7),
I3 => \add_temp_14__92_carry__0_i_1_n_0\,
O => \add_temp_14__92_carry__0_i_5_n_0\
);
\add_temp_14__92_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(6),
I1 => RESIZE34(6),
I2 => RESIZE30(6),
I3 => \add_temp_14__92_carry__0_i_2_n_0\,
O => \add_temp_14__92_carry__0_i_6_n_0\
);
\add_temp_14__92_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(5),
I1 => RESIZE34(5),
I2 => RESIZE30(5),
I3 => \add_temp_14__92_carry__0_i_3_n_0\,
O => \add_temp_14__92_carry__0_i_7_n_0\
);
\add_temp_14__92_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(4),
I1 => RESIZE34(4),
I2 => RESIZE30(4),
I3 => \add_temp_14__92_carry__0_i_4_n_0\,
O => \add_temp_14__92_carry__0_i_8_n_0\
);
\add_temp_14__92_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__92_carry__0_n_0\,
CO(3) => \add_temp_14__92_carry__1_n_0\,
CO(2) => \add_temp_14__92_carry__1_n_1\,
CO(1) => \add_temp_14__92_carry__1_n_2\,
CO(0) => \add_temp_14__92_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__92_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__92_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__92_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__92_carry__1_i_4_n_0\,
O(3) => \add_temp_14__92_carry__1_n_4\,
O(2) => \add_temp_14__92_carry__1_n_5\,
O(1) => \add_temp_14__92_carry__1_n_6\,
O(0) => \add_temp_14__92_carry__1_n_7\,
S(3) => \add_temp_14__92_carry__1_i_5_n_0\,
S(2) => \add_temp_14__92_carry__1_i_6_n_0\,
S(1) => \add_temp_14__92_carry__1_i_7_n_0\,
S(0) => \add_temp_14__92_carry__1_i_8_n_0\
);
\add_temp_14__92_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(10),
I1 => RESIZE32(10),
I2 => RESIZE34(10),
O => \add_temp_14__92_carry__1_i_1_n_0\
);
\add_temp_14__92_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(9),
I1 => RESIZE32(9),
I2 => RESIZE34(9),
O => \add_temp_14__92_carry__1_i_2_n_0\
);
\add_temp_14__92_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(8),
I1 => RESIZE32(8),
I2 => RESIZE34(8),
O => \add_temp_14__92_carry__1_i_3_n_0\
);
\add_temp_14__92_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE34(7),
I1 => RESIZE30(7),
I2 => RESIZE32(7),
O => \add_temp_14__92_carry__1_i_4_n_0\
);
\add_temp_14__92_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(11),
I1 => RESIZE32(11),
I2 => RESIZE34(11),
I3 => \add_temp_14__92_carry__1_i_1_n_0\,
O => \add_temp_14__92_carry__1_i_5_n_0\
);
\add_temp_14__92_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(10),
I1 => RESIZE32(10),
I2 => RESIZE34(10),
I3 => \add_temp_14__92_carry__1_i_2_n_0\,
O => \add_temp_14__92_carry__1_i_6_n_0\
);
\add_temp_14__92_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(9),
I1 => RESIZE32(9),
I2 => RESIZE34(9),
I3 => \add_temp_14__92_carry__1_i_3_n_0\,
O => \add_temp_14__92_carry__1_i_7_n_0\
);
\add_temp_14__92_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(8),
I1 => RESIZE32(8),
I2 => RESIZE34(8),
I3 => \add_temp_14__92_carry__1_i_4_n_0\,
O => \add_temp_14__92_carry__1_i_8_n_0\
);
\add_temp_14__92_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__92_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__92_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__92_carry__2_n_1\,
CO(1) => \add_temp_14__92_carry__2_n_2\,
CO(0) => \add_temp_14__92_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__92_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__92_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__92_carry__2_i_3_n_0\,
O(3) => \add_temp_14__92_carry__2_n_4\,
O(2) => \add_temp_14__92_carry__2_n_5\,
O(1) => \add_temp_14__92_carry__2_n_6\,
O(0) => \add_temp_14__92_carry__2_n_7\,
S(3) => \add_temp_14__92_carry__2_i_4_n_0\,
S(2) => \add_temp_14__92_carry__2_i_5_n_0\,
S(1) => \add_temp_14__92_carry__2_i_6_n_0\,
S(0) => \add_temp_14__92_carry__2_i_7_n_0\
);
\add_temp_14__92_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(13),
I1 => RESIZE32(13),
I2 => RESIZE34(13),
O => \add_temp_14__92_carry__2_i_1_n_0\
);
\add_temp_14__92_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(12),
I1 => RESIZE32(12),
I2 => RESIZE34(12),
O => \add_temp_14__92_carry__2_i_2_n_0\
);
\add_temp_14__92_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(11),
I1 => RESIZE32(11),
I2 => RESIZE34(11),
O => \add_temp_14__92_carry__2_i_3_n_0\
);
\add_temp_14__92_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE34(14),
I1 => RESIZE32(14),
I2 => RESIZE30(14),
I3 => RESIZE32(15),
I4 => RESIZE30(15),
I5 => RESIZE34(15),
O => \add_temp_14__92_carry__2_i_4_n_0\
);
\add_temp_14__92_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__92_carry__2_i_1_n_0\,
I1 => RESIZE32(14),
I2 => RESIZE30(14),
I3 => RESIZE34(14),
O => \add_temp_14__92_carry__2_i_5_n_0\
);
\add_temp_14__92_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(13),
I1 => RESIZE32(13),
I2 => RESIZE34(13),
I3 => \add_temp_14__92_carry__2_i_2_n_0\,
O => \add_temp_14__92_carry__2_i_6_n_0\
);
\add_temp_14__92_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(12),
I1 => RESIZE32(12),
I2 => RESIZE34(12),
I3 => \add_temp_14__92_carry__2_i_3_n_0\,
O => \add_temp_14__92_carry__2_i_7_n_0\
);
\add_temp_14__92_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(2),
I1 => RESIZE34(2),
I2 => RESIZE30(2),
O => \add_temp_14__92_carry_i_1_n_0\
);
\add_temp_14__92_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(1),
I1 => RESIZE34(1),
I2 => RESIZE30(1),
O => \add_temp_14__92_carry_i_2_n_0\
);
\add_temp_14__92_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(0),
I1 => RESIZE34(0),
I2 => RESIZE30(0),
O => \add_temp_14__92_carry_i_3_n_0\
);
\add_temp_14__92_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(3),
I1 => RESIZE34(3),
I2 => RESIZE30(3),
I3 => \add_temp_14__92_carry_i_1_n_0\,
O => \add_temp_14__92_carry_i_4_n_0\
);
\add_temp_14__92_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(2),
I1 => RESIZE34(2),
I2 => RESIZE30(2),
I3 => \add_temp_14__92_carry_i_2_n_0\,
O => \add_temp_14__92_carry_i_5_n_0\
);
\add_temp_14__92_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(1),
I1 => RESIZE34(1),
I2 => RESIZE30(1),
I3 => \add_temp_14__92_carry_i_3_n_0\,
O => \add_temp_14__92_carry_i_6_n_0\
);
\add_temp_14__92_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE32(0),
I1 => RESIZE34(0),
I2 => RESIZE30(0),
O => \add_temp_14__92_carry_i_7_n_0\
);
\data_pipeline_tmp_reg[0][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(0),
Q => \data_pipeline_tmp_reg[0]\(0)
);
\data_pipeline_tmp_reg[0][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(10),
Q => \data_pipeline_tmp_reg[0]\(10)
);
\data_pipeline_tmp_reg[0][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(11),
Q => \data_pipeline_tmp_reg[0]\(11)
);
\data_pipeline_tmp_reg[0][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(12),
Q => \data_pipeline_tmp_reg[0]\(12)
);
\data_pipeline_tmp_reg[0][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(13),
Q => \data_pipeline_tmp_reg[0]\(13)
);
\data_pipeline_tmp_reg[0][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(14),
Q => \data_pipeline_tmp_reg[0]\(14)
);
\data_pipeline_tmp_reg[0][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(15),
Q => \data_pipeline_tmp_reg[0]\(15)
);
\data_pipeline_tmp_reg[0][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(1),
Q => \data_pipeline_tmp_reg[0]\(1)
);
\data_pipeline_tmp_reg[0][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(2),
Q => \data_pipeline_tmp_reg[0]\(2)
);
\data_pipeline_tmp_reg[0][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(3),
Q => \data_pipeline_tmp_reg[0]\(3)
);
\data_pipeline_tmp_reg[0][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(4),
Q => \data_pipeline_tmp_reg[0]\(4)
);
\data_pipeline_tmp_reg[0][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(5),
Q => \data_pipeline_tmp_reg[0]\(5)
);
\data_pipeline_tmp_reg[0][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(6),
Q => \data_pipeline_tmp_reg[0]\(6)
);
\data_pipeline_tmp_reg[0][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(7),
Q => \data_pipeline_tmp_reg[0]\(7)
);
\data_pipeline_tmp_reg[0][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(8),
Q => \data_pipeline_tmp_reg[0]\(8)
);
\data_pipeline_tmp_reg[0][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(9),
Q => \data_pipeline_tmp_reg[0]\(9)
);
\data_pipeline_tmp_reg[10][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(0),
Q => \data_pipeline_tmp_reg[10]\(0)
);
\data_pipeline_tmp_reg[10][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(10),
Q => \data_pipeline_tmp_reg[10]\(10)
);
\data_pipeline_tmp_reg[10][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(11),
Q => \data_pipeline_tmp_reg[10]\(11)
);
\data_pipeline_tmp_reg[10][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(12),
Q => \data_pipeline_tmp_reg[10]\(12)
);
\data_pipeline_tmp_reg[10][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(13),
Q => \data_pipeline_tmp_reg[10]\(13)
);
\data_pipeline_tmp_reg[10][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(14),
Q => \data_pipeline_tmp_reg[10]\(14)
);
\data_pipeline_tmp_reg[10][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(15),
Q => \data_pipeline_tmp_reg[10]\(15)
);
\data_pipeline_tmp_reg[10][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(1),
Q => \data_pipeline_tmp_reg[10]\(1)
);
\data_pipeline_tmp_reg[10][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(2),
Q => \data_pipeline_tmp_reg[10]\(2)
);
\data_pipeline_tmp_reg[10][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(3),
Q => \data_pipeline_tmp_reg[10]\(3)
);
\data_pipeline_tmp_reg[10][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(4),
Q => \data_pipeline_tmp_reg[10]\(4)
);
\data_pipeline_tmp_reg[10][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(5),
Q => \data_pipeline_tmp_reg[10]\(5)
);
\data_pipeline_tmp_reg[10][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(6),
Q => \data_pipeline_tmp_reg[10]\(6)
);
\data_pipeline_tmp_reg[10][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(7),
Q => \data_pipeline_tmp_reg[10]\(7)
);
\data_pipeline_tmp_reg[10][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(8),
Q => \data_pipeline_tmp_reg[10]\(8)
);
\data_pipeline_tmp_reg[10][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(9),
Q => \data_pipeline_tmp_reg[10]\(9)
);
\data_pipeline_tmp_reg[11][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(0),
Q => \data_pipeline_tmp_reg[11]\(0)
);
\data_pipeline_tmp_reg[11][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(10),
Q => \data_pipeline_tmp_reg[11]\(10)
);
\data_pipeline_tmp_reg[11][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(11),
Q => \data_pipeline_tmp_reg[11]\(11)
);
\data_pipeline_tmp_reg[11][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(12),
Q => \data_pipeline_tmp_reg[11]\(12)
);
\data_pipeline_tmp_reg[11][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(13),
Q => \data_pipeline_tmp_reg[11]\(13)
);
\data_pipeline_tmp_reg[11][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(14),
Q => \data_pipeline_tmp_reg[11]\(14)
);
\data_pipeline_tmp_reg[11][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(15),
Q => \data_pipeline_tmp_reg[11]\(15)
);
\data_pipeline_tmp_reg[11][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(1),
Q => \data_pipeline_tmp_reg[11]\(1)
);
\data_pipeline_tmp_reg[11][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(2),
Q => \data_pipeline_tmp_reg[11]\(2)
);
\data_pipeline_tmp_reg[11][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(3),
Q => \data_pipeline_tmp_reg[11]\(3)
);
\data_pipeline_tmp_reg[11][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(4),
Q => \data_pipeline_tmp_reg[11]\(4)
);
\data_pipeline_tmp_reg[11][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(5),
Q => \data_pipeline_tmp_reg[11]\(5)
);
\data_pipeline_tmp_reg[11][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(6),
Q => \data_pipeline_tmp_reg[11]\(6)
);
\data_pipeline_tmp_reg[11][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(7),
Q => \data_pipeline_tmp_reg[11]\(7)
);
\data_pipeline_tmp_reg[11][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(8),
Q => \data_pipeline_tmp_reg[11]\(8)
);
\data_pipeline_tmp_reg[11][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(9),
Q => \data_pipeline_tmp_reg[11]\(9)
);
\data_pipeline_tmp_reg[12][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(0),
Q => \data_pipeline_tmp_reg[12]\(0)
);
\data_pipeline_tmp_reg[12][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(10),
Q => \data_pipeline_tmp_reg[12]\(10)
);
\data_pipeline_tmp_reg[12][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(11),
Q => \data_pipeline_tmp_reg[12]\(11)
);
\data_pipeline_tmp_reg[12][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(12),
Q => \data_pipeline_tmp_reg[12]\(12)
);
\data_pipeline_tmp_reg[12][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(13),
Q => \data_pipeline_tmp_reg[12]\(13)
);
\data_pipeline_tmp_reg[12][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(14),
Q => \data_pipeline_tmp_reg[12]\(14)
);
\data_pipeline_tmp_reg[12][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(15),
Q => \data_pipeline_tmp_reg[12]\(15)
);
\data_pipeline_tmp_reg[12][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(1),
Q => \data_pipeline_tmp_reg[12]\(1)
);
\data_pipeline_tmp_reg[12][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(2),
Q => \data_pipeline_tmp_reg[12]\(2)
);
\data_pipeline_tmp_reg[12][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(3),
Q => \data_pipeline_tmp_reg[12]\(3)
);
\data_pipeline_tmp_reg[12][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(4),
Q => \data_pipeline_tmp_reg[12]\(4)
);
\data_pipeline_tmp_reg[12][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(5),
Q => \data_pipeline_tmp_reg[12]\(5)
);
\data_pipeline_tmp_reg[12][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(6),
Q => \data_pipeline_tmp_reg[12]\(6)
);
\data_pipeline_tmp_reg[12][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(7),
Q => \data_pipeline_tmp_reg[12]\(7)
);
\data_pipeline_tmp_reg[12][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(8),
Q => \data_pipeline_tmp_reg[12]\(8)
);
\data_pipeline_tmp_reg[12][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(9),
Q => \data_pipeline_tmp_reg[12]\(9)
);
\data_pipeline_tmp_reg[13][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(0),
Q => \data_pipeline_tmp_reg[13]\(0)
);
\data_pipeline_tmp_reg[13][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(10),
Q => \data_pipeline_tmp_reg[13]\(10)
);
\data_pipeline_tmp_reg[13][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(11),
Q => \data_pipeline_tmp_reg[13]\(11)
);
\data_pipeline_tmp_reg[13][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(12),
Q => \data_pipeline_tmp_reg[13]\(12)
);
\data_pipeline_tmp_reg[13][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(13),
Q => \data_pipeline_tmp_reg[13]\(13)
);
\data_pipeline_tmp_reg[13][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(14),
Q => \data_pipeline_tmp_reg[13]\(14)
);
\data_pipeline_tmp_reg[13][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(15),
Q => \data_pipeline_tmp_reg[13]\(15)
);
\data_pipeline_tmp_reg[13][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(1),
Q => \data_pipeline_tmp_reg[13]\(1)
);
\data_pipeline_tmp_reg[13][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(2),
Q => \data_pipeline_tmp_reg[13]\(2)
);
\data_pipeline_tmp_reg[13][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(3),
Q => \data_pipeline_tmp_reg[13]\(3)
);
\data_pipeline_tmp_reg[13][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(4),
Q => \data_pipeline_tmp_reg[13]\(4)
);
\data_pipeline_tmp_reg[13][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(5),
Q => \data_pipeline_tmp_reg[13]\(5)
);
\data_pipeline_tmp_reg[13][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(6),
Q => \data_pipeline_tmp_reg[13]\(6)
);
\data_pipeline_tmp_reg[13][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(7),
Q => \data_pipeline_tmp_reg[13]\(7)
);
\data_pipeline_tmp_reg[13][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(8),
Q => \data_pipeline_tmp_reg[13]\(8)
);
\data_pipeline_tmp_reg[13][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(9),
Q => \data_pipeline_tmp_reg[13]\(9)
);
\data_pipeline_tmp_reg[14][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(0),
Q => \data_pipeline_tmp_reg[14]\(0)
);
\data_pipeline_tmp_reg[14][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(10),
Q => \data_pipeline_tmp_reg[14]\(10)
);
\data_pipeline_tmp_reg[14][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(11),
Q => \data_pipeline_tmp_reg[14]\(11)
);
\data_pipeline_tmp_reg[14][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(12),
Q => \data_pipeline_tmp_reg[14]\(12)
);
\data_pipeline_tmp_reg[14][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(13),
Q => \data_pipeline_tmp_reg[14]\(13)
);
\data_pipeline_tmp_reg[14][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(14),
Q => \data_pipeline_tmp_reg[14]\(14)
);
\data_pipeline_tmp_reg[14][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(15),
Q => \data_pipeline_tmp_reg[14]\(15)
);
\data_pipeline_tmp_reg[14][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(1),
Q => \data_pipeline_tmp_reg[14]\(1)
);
\data_pipeline_tmp_reg[14][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(2),
Q => \data_pipeline_tmp_reg[14]\(2)
);
\data_pipeline_tmp_reg[14][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(3),
Q => \data_pipeline_tmp_reg[14]\(3)
);
\data_pipeline_tmp_reg[14][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(4),
Q => \data_pipeline_tmp_reg[14]\(4)
);
\data_pipeline_tmp_reg[14][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(5),
Q => \data_pipeline_tmp_reg[14]\(5)
);
\data_pipeline_tmp_reg[14][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(6),
Q => \data_pipeline_tmp_reg[14]\(6)
);
\data_pipeline_tmp_reg[14][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(7),
Q => \data_pipeline_tmp_reg[14]\(7)
);
\data_pipeline_tmp_reg[14][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(8),
Q => \data_pipeline_tmp_reg[14]\(8)
);
\data_pipeline_tmp_reg[14][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(9),
Q => \data_pipeline_tmp_reg[14]\(9)
);
\data_pipeline_tmp_reg[1][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(0),
Q => \data_pipeline_tmp_reg[1]\(0)
);
\data_pipeline_tmp_reg[1][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(10),
Q => \data_pipeline_tmp_reg[1]\(10)
);
\data_pipeline_tmp_reg[1][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(11),
Q => \data_pipeline_tmp_reg[1]\(11)
);
\data_pipeline_tmp_reg[1][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(12),
Q => \data_pipeline_tmp_reg[1]\(12)
);
\data_pipeline_tmp_reg[1][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(13),
Q => \data_pipeline_tmp_reg[1]\(13)
);
\data_pipeline_tmp_reg[1][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(14),
Q => \data_pipeline_tmp_reg[1]\(14)
);
\data_pipeline_tmp_reg[1][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(15),
Q => \data_pipeline_tmp_reg[1]\(15)
);
\data_pipeline_tmp_reg[1][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(1),
Q => \data_pipeline_tmp_reg[1]\(1)
);
\data_pipeline_tmp_reg[1][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(2),
Q => \data_pipeline_tmp_reg[1]\(2)
);
\data_pipeline_tmp_reg[1][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(3),
Q => \data_pipeline_tmp_reg[1]\(3)
);
\data_pipeline_tmp_reg[1][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(4),
Q => \data_pipeline_tmp_reg[1]\(4)
);
\data_pipeline_tmp_reg[1][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(5),
Q => \data_pipeline_tmp_reg[1]\(5)
);
\data_pipeline_tmp_reg[1][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(6),
Q => \data_pipeline_tmp_reg[1]\(6)
);
\data_pipeline_tmp_reg[1][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(7),
Q => \data_pipeline_tmp_reg[1]\(7)
);
\data_pipeline_tmp_reg[1][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(8),
Q => \data_pipeline_tmp_reg[1]\(8)
);
\data_pipeline_tmp_reg[1][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(9),
Q => \data_pipeline_tmp_reg[1]\(9)
);
\data_pipeline_tmp_reg[2][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(0),
Q => \data_pipeline_tmp_reg[2]\(0)
);
\data_pipeline_tmp_reg[2][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(10),
Q => \data_pipeline_tmp_reg[2]\(10)
);
\data_pipeline_tmp_reg[2][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(11),
Q => \data_pipeline_tmp_reg[2]\(11)
);
\data_pipeline_tmp_reg[2][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(12),
Q => \data_pipeline_tmp_reg[2]\(12)
);
\data_pipeline_tmp_reg[2][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(13),
Q => \data_pipeline_tmp_reg[2]\(13)
);
\data_pipeline_tmp_reg[2][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(14),
Q => \data_pipeline_tmp_reg[2]\(14)
);
\data_pipeline_tmp_reg[2][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(15),
Q => \data_pipeline_tmp_reg[2]\(15)
);
\data_pipeline_tmp_reg[2][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(1),
Q => \data_pipeline_tmp_reg[2]\(1)
);
\data_pipeline_tmp_reg[2][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(2),
Q => \data_pipeline_tmp_reg[2]\(2)
);
\data_pipeline_tmp_reg[2][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(3),
Q => \data_pipeline_tmp_reg[2]\(3)
);
\data_pipeline_tmp_reg[2][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(4),
Q => \data_pipeline_tmp_reg[2]\(4)
);
\data_pipeline_tmp_reg[2][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(5),
Q => \data_pipeline_tmp_reg[2]\(5)
);
\data_pipeline_tmp_reg[2][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(6),
Q => \data_pipeline_tmp_reg[2]\(6)
);
\data_pipeline_tmp_reg[2][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(7),
Q => \data_pipeline_tmp_reg[2]\(7)
);
\data_pipeline_tmp_reg[2][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(8),
Q => \data_pipeline_tmp_reg[2]\(8)
);
\data_pipeline_tmp_reg[2][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(9),
Q => \data_pipeline_tmp_reg[2]\(9)
);
\data_pipeline_tmp_reg[3][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(0),
Q => \data_pipeline_tmp_reg[3]\(0)
);
\data_pipeline_tmp_reg[3][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(10),
Q => \data_pipeline_tmp_reg[3]\(10)
);
\data_pipeline_tmp_reg[3][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(11),
Q => \data_pipeline_tmp_reg[3]\(11)
);
\data_pipeline_tmp_reg[3][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(12),
Q => \data_pipeline_tmp_reg[3]\(12)
);
\data_pipeline_tmp_reg[3][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(13),
Q => \data_pipeline_tmp_reg[3]\(13)
);
\data_pipeline_tmp_reg[3][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(14),
Q => \data_pipeline_tmp_reg[3]\(14)
);
\data_pipeline_tmp_reg[3][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(15),
Q => \data_pipeline_tmp_reg[3]\(15)
);
\data_pipeline_tmp_reg[3][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(1),
Q => \data_pipeline_tmp_reg[3]\(1)
);
\data_pipeline_tmp_reg[3][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(2),
Q => \data_pipeline_tmp_reg[3]\(2)
);
\data_pipeline_tmp_reg[3][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(3),
Q => \data_pipeline_tmp_reg[3]\(3)
);
\data_pipeline_tmp_reg[3][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(4),
Q => \data_pipeline_tmp_reg[3]\(4)
);
\data_pipeline_tmp_reg[3][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(5),
Q => \data_pipeline_tmp_reg[3]\(5)
);
\data_pipeline_tmp_reg[3][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(6),
Q => \data_pipeline_tmp_reg[3]\(6)
);
\data_pipeline_tmp_reg[3][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(7),
Q => \data_pipeline_tmp_reg[3]\(7)
);
\data_pipeline_tmp_reg[3][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(8),
Q => \data_pipeline_tmp_reg[3]\(8)
);
\data_pipeline_tmp_reg[3][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(9),
Q => \data_pipeline_tmp_reg[3]\(9)
);
\data_pipeline_tmp_reg[4][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(0),
Q => \data_pipeline_tmp_reg[4]\(0)
);
\data_pipeline_tmp_reg[4][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(10),
Q => \data_pipeline_tmp_reg[4]\(10)
);
\data_pipeline_tmp_reg[4][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(11),
Q => \data_pipeline_tmp_reg[4]\(11)
);
\data_pipeline_tmp_reg[4][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(12),
Q => \data_pipeline_tmp_reg[4]\(12)
);
\data_pipeline_tmp_reg[4][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(13),
Q => \data_pipeline_tmp_reg[4]\(13)
);
\data_pipeline_tmp_reg[4][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(14),
Q => \data_pipeline_tmp_reg[4]\(14)
);
\data_pipeline_tmp_reg[4][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(15),
Q => \data_pipeline_tmp_reg[4]\(15)
);
\data_pipeline_tmp_reg[4][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(1),
Q => \data_pipeline_tmp_reg[4]\(1)
);
\data_pipeline_tmp_reg[4][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(2),
Q => \data_pipeline_tmp_reg[4]\(2)
);
\data_pipeline_tmp_reg[4][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(3),
Q => \data_pipeline_tmp_reg[4]\(3)
);
\data_pipeline_tmp_reg[4][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(4),
Q => \data_pipeline_tmp_reg[4]\(4)
);
\data_pipeline_tmp_reg[4][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(5),
Q => \data_pipeline_tmp_reg[4]\(5)
);
\data_pipeline_tmp_reg[4][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(6),
Q => \data_pipeline_tmp_reg[4]\(6)
);
\data_pipeline_tmp_reg[4][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(7),
Q => \data_pipeline_tmp_reg[4]\(7)
);
\data_pipeline_tmp_reg[4][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(8),
Q => \data_pipeline_tmp_reg[4]\(8)
);
\data_pipeline_tmp_reg[4][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(9),
Q => \data_pipeline_tmp_reg[4]\(9)
);
\data_pipeline_tmp_reg[5][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(0),
Q => \data_pipeline_tmp_reg[5]\(0)
);
\data_pipeline_tmp_reg[5][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(10),
Q => \data_pipeline_tmp_reg[5]\(10)
);
\data_pipeline_tmp_reg[5][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(11),
Q => \data_pipeline_tmp_reg[5]\(11)
);
\data_pipeline_tmp_reg[5][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(12),
Q => \data_pipeline_tmp_reg[5]\(12)
);
\data_pipeline_tmp_reg[5][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(13),
Q => \data_pipeline_tmp_reg[5]\(13)
);
\data_pipeline_tmp_reg[5][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(14),
Q => \data_pipeline_tmp_reg[5]\(14)
);
\data_pipeline_tmp_reg[5][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(15),
Q => \data_pipeline_tmp_reg[5]\(15)
);
\data_pipeline_tmp_reg[5][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(1),
Q => \data_pipeline_tmp_reg[5]\(1)
);
\data_pipeline_tmp_reg[5][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(2),
Q => \data_pipeline_tmp_reg[5]\(2)
);
\data_pipeline_tmp_reg[5][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(3),
Q => \data_pipeline_tmp_reg[5]\(3)
);
\data_pipeline_tmp_reg[5][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(4),
Q => \data_pipeline_tmp_reg[5]\(4)
);
\data_pipeline_tmp_reg[5][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(5),
Q => \data_pipeline_tmp_reg[5]\(5)
);
\data_pipeline_tmp_reg[5][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(6),
Q => \data_pipeline_tmp_reg[5]\(6)
);
\data_pipeline_tmp_reg[5][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(7),
Q => \data_pipeline_tmp_reg[5]\(7)
);
\data_pipeline_tmp_reg[5][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(8),
Q => \data_pipeline_tmp_reg[5]\(8)
);
\data_pipeline_tmp_reg[5][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(9),
Q => \data_pipeline_tmp_reg[5]\(9)
);
\data_pipeline_tmp_reg[6][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(0),
Q => \data_pipeline_tmp_reg[6]\(0)
);
\data_pipeline_tmp_reg[6][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(10),
Q => \data_pipeline_tmp_reg[6]\(10)
);
\data_pipeline_tmp_reg[6][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(11),
Q => \data_pipeline_tmp_reg[6]\(11)
);
\data_pipeline_tmp_reg[6][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(12),
Q => \data_pipeline_tmp_reg[6]\(12)
);
\data_pipeline_tmp_reg[6][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(13),
Q => \data_pipeline_tmp_reg[6]\(13)
);
\data_pipeline_tmp_reg[6][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(14),
Q => \data_pipeline_tmp_reg[6]\(14)
);
\data_pipeline_tmp_reg[6][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(15),
Q => \data_pipeline_tmp_reg[6]\(15)
);
\data_pipeline_tmp_reg[6][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(1),
Q => \data_pipeline_tmp_reg[6]\(1)
);
\data_pipeline_tmp_reg[6][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(2),
Q => \data_pipeline_tmp_reg[6]\(2)
);
\data_pipeline_tmp_reg[6][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(3),
Q => \data_pipeline_tmp_reg[6]\(3)
);
\data_pipeline_tmp_reg[6][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(4),
Q => \data_pipeline_tmp_reg[6]\(4)
);
\data_pipeline_tmp_reg[6][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(5),
Q => \data_pipeline_tmp_reg[6]\(5)
);
\data_pipeline_tmp_reg[6][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(6),
Q => \data_pipeline_tmp_reg[6]\(6)
);
\data_pipeline_tmp_reg[6][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(7),
Q => \data_pipeline_tmp_reg[6]\(7)
);
\data_pipeline_tmp_reg[6][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(8),
Q => \data_pipeline_tmp_reg[6]\(8)
);
\data_pipeline_tmp_reg[6][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(9),
Q => \data_pipeline_tmp_reg[6]\(9)
);
\data_pipeline_tmp_reg[7][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(0),
Q => \data_pipeline_tmp_reg[7]\(0)
);
\data_pipeline_tmp_reg[7][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(10),
Q => \data_pipeline_tmp_reg[7]\(10)
);
\data_pipeline_tmp_reg[7][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(11),
Q => \data_pipeline_tmp_reg[7]\(11)
);
\data_pipeline_tmp_reg[7][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(12),
Q => \data_pipeline_tmp_reg[7]\(12)
);
\data_pipeline_tmp_reg[7][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(13),
Q => \data_pipeline_tmp_reg[7]\(13)
);
\data_pipeline_tmp_reg[7][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(14),
Q => \data_pipeline_tmp_reg[7]\(14)
);
\data_pipeline_tmp_reg[7][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(15),
Q => \data_pipeline_tmp_reg[7]\(15)
);
\data_pipeline_tmp_reg[7][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(1),
Q => \data_pipeline_tmp_reg[7]\(1)
);
\data_pipeline_tmp_reg[7][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(2),
Q => \data_pipeline_tmp_reg[7]\(2)
);
\data_pipeline_tmp_reg[7][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(3),
Q => \data_pipeline_tmp_reg[7]\(3)
);
\data_pipeline_tmp_reg[7][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(4),
Q => \data_pipeline_tmp_reg[7]\(4)
);
\data_pipeline_tmp_reg[7][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(5),
Q => \data_pipeline_tmp_reg[7]\(5)
);
\data_pipeline_tmp_reg[7][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(6),
Q => \data_pipeline_tmp_reg[7]\(6)
);
\data_pipeline_tmp_reg[7][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(7),
Q => \data_pipeline_tmp_reg[7]\(7)
);
\data_pipeline_tmp_reg[7][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(8),
Q => \data_pipeline_tmp_reg[7]\(8)
);
\data_pipeline_tmp_reg[7][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(9),
Q => \data_pipeline_tmp_reg[7]\(9)
);
\data_pipeline_tmp_reg[8][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(0),
Q => \data_pipeline_tmp_reg[8]\(0)
);
\data_pipeline_tmp_reg[8][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(10),
Q => \data_pipeline_tmp_reg[8]\(10)
);
\data_pipeline_tmp_reg[8][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(11),
Q => \data_pipeline_tmp_reg[8]\(11)
);
\data_pipeline_tmp_reg[8][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(12),
Q => \data_pipeline_tmp_reg[8]\(12)
);
\data_pipeline_tmp_reg[8][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(13),
Q => \data_pipeline_tmp_reg[8]\(13)
);
\data_pipeline_tmp_reg[8][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(14),
Q => \data_pipeline_tmp_reg[8]\(14)
);
\data_pipeline_tmp_reg[8][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(15),
Q => \data_pipeline_tmp_reg[8]\(15)
);
\data_pipeline_tmp_reg[8][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(1),
Q => \data_pipeline_tmp_reg[8]\(1)
);
\data_pipeline_tmp_reg[8][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(2),
Q => \data_pipeline_tmp_reg[8]\(2)
);
\data_pipeline_tmp_reg[8][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(3),
Q => \data_pipeline_tmp_reg[8]\(3)
);
\data_pipeline_tmp_reg[8][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(4),
Q => \data_pipeline_tmp_reg[8]\(4)
);
\data_pipeline_tmp_reg[8][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(5),
Q => \data_pipeline_tmp_reg[8]\(5)
);
\data_pipeline_tmp_reg[8][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(6),
Q => \data_pipeline_tmp_reg[8]\(6)
);
\data_pipeline_tmp_reg[8][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(7),
Q => \data_pipeline_tmp_reg[8]\(7)
);
\data_pipeline_tmp_reg[8][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(8),
Q => \data_pipeline_tmp_reg[8]\(8)
);
\data_pipeline_tmp_reg[8][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(9),
Q => \data_pipeline_tmp_reg[8]\(9)
);
\data_pipeline_tmp_reg[9][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(0),
Q => \data_pipeline_tmp_reg[9]\(0)
);
\data_pipeline_tmp_reg[9][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(10),
Q => \data_pipeline_tmp_reg[9]\(10)
);
\data_pipeline_tmp_reg[9][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(11),
Q => \data_pipeline_tmp_reg[9]\(11)
);
\data_pipeline_tmp_reg[9][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(12),
Q => \data_pipeline_tmp_reg[9]\(12)
);
\data_pipeline_tmp_reg[9][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(13),
Q => \data_pipeline_tmp_reg[9]\(13)
);
\data_pipeline_tmp_reg[9][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(14),
Q => \data_pipeline_tmp_reg[9]\(14)
);
\data_pipeline_tmp_reg[9][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(15),
Q => \data_pipeline_tmp_reg[9]\(15)
);
\data_pipeline_tmp_reg[9][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(1),
Q => \data_pipeline_tmp_reg[9]\(1)
);
\data_pipeline_tmp_reg[9][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(2),
Q => \data_pipeline_tmp_reg[9]\(2)
);
\data_pipeline_tmp_reg[9][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(3),
Q => \data_pipeline_tmp_reg[9]\(3)
);
\data_pipeline_tmp_reg[9][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(4),
Q => \data_pipeline_tmp_reg[9]\(4)
);
\data_pipeline_tmp_reg[9][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(5),
Q => \data_pipeline_tmp_reg[9]\(5)
);
\data_pipeline_tmp_reg[9][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(6),
Q => \data_pipeline_tmp_reg[9]\(6)
);
\data_pipeline_tmp_reg[9][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(7),
Q => \data_pipeline_tmp_reg[9]\(7)
);
\data_pipeline_tmp_reg[9][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(8),
Q => \data_pipeline_tmp_reg[9]\(8)
);
\data_pipeline_tmp_reg[9][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(9),
Q => \data_pipeline_tmp_reg[9]\(9)
);
mul_temp: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[0]\(15),
A(28) => \data_pipeline_tmp_reg[0]\(15),
A(27) => \data_pipeline_tmp_reg[0]\(15),
A(26) => \data_pipeline_tmp_reg[0]\(15),
A(25) => \data_pipeline_tmp_reg[0]\(15),
A(24) => \data_pipeline_tmp_reg[0]\(15),
A(23) => \data_pipeline_tmp_reg[0]\(15),
A(22) => \data_pipeline_tmp_reg[0]\(15),
A(21) => \data_pipeline_tmp_reg[0]\(15),
A(20) => \data_pipeline_tmp_reg[0]\(15),
A(19) => \data_pipeline_tmp_reg[0]\(15),
A(18) => \data_pipeline_tmp_reg[0]\(15),
A(17) => \data_pipeline_tmp_reg[0]\(15),
A(16) => \data_pipeline_tmp_reg[0]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[0]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[0]_15\(15),
B(16) => \weight_reg[0]_15\(15),
B(15 downto 0) => \weight_reg[0]_15\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_n_74,
P(30) => mul_temp_n_75,
P(29) => mul_temp_n_76,
P(28) => mul_temp_n_77,
P(27) => mul_temp_n_78,
P(26) => mul_temp_n_79,
P(25) => mul_temp_n_80,
P(24) => mul_temp_n_81,
P(23) => mul_temp_n_82,
P(22) => mul_temp_n_83,
P(21) => mul_temp_n_84,
P(20) => mul_temp_n_85,
P(19) => mul_temp_n_86,
P(18) => mul_temp_n_87,
P(17) => mul_temp_n_88,
P(16) => mul_temp_n_89,
P(15) => mul_temp_n_90,
P(14) => \^mul_temp\(14),
P(13) => mul_temp_n_92,
P(12) => mul_temp_n_93,
P(11) => mul_temp_n_94,
P(10) => mul_temp_n_95,
P(9) => mul_temp_n_96,
P(8) => mul_temp_n_97,
P(7) => mul_temp_n_98,
P(6) => mul_temp_n_99,
P(5) => mul_temp_n_100,
P(4) => mul_temp_n_101,
P(3) => mul_temp_n_102,
P(2) => mul_temp_n_103,
P(1) => mul_temp_n_104,
P(0) => mul_temp_n_105,
PATTERNBDETECT => NLW_mul_temp_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_UNDERFLOW_UNCONNECTED
);
mul_temp_1: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[1]\(15),
A(28) => \data_pipeline_tmp_reg[1]\(15),
A(27) => \data_pipeline_tmp_reg[1]\(15),
A(26) => \data_pipeline_tmp_reg[1]\(15),
A(25) => \data_pipeline_tmp_reg[1]\(15),
A(24) => \data_pipeline_tmp_reg[1]\(15),
A(23) => \data_pipeline_tmp_reg[1]\(15),
A(22) => \data_pipeline_tmp_reg[1]\(15),
A(21) => \data_pipeline_tmp_reg[1]\(15),
A(20) => \data_pipeline_tmp_reg[1]\(15),
A(19) => \data_pipeline_tmp_reg[1]\(15),
A(18) => \data_pipeline_tmp_reg[1]\(15),
A(17) => \data_pipeline_tmp_reg[1]\(15),
A(16) => \data_pipeline_tmp_reg[1]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[1]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_1_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[1]_0\(15),
B(16) => \weight_reg[1]_0\(15),
B(15 downto 0) => \weight_reg[1]_0\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_1_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_1_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_1_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_1_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_1_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_1_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_1_n_74,
P(30) => mul_temp_1_n_75,
P(29) => mul_temp_1_n_76,
P(28) => mul_temp_1_n_77,
P(27) => mul_temp_1_n_78,
P(26) => mul_temp_1_n_79,
P(25) => mul_temp_1_n_80,
P(24) => mul_temp_1_n_81,
P(23) => mul_temp_1_n_82,
P(22) => mul_temp_1_n_83,
P(21) => mul_temp_1_n_84,
P(20) => mul_temp_1_n_85,
P(19) => mul_temp_1_n_86,
P(18) => mul_temp_1_n_87,
P(17) => mul_temp_1_n_88,
P(16) => mul_temp_1_n_89,
P(15) => mul_temp_1_n_90,
P(14) => \^mul_temp_1\(14),
P(13) => mul_temp_1_n_92,
P(12) => mul_temp_1_n_93,
P(11) => mul_temp_1_n_94,
P(10) => mul_temp_1_n_95,
P(9) => mul_temp_1_n_96,
P(8) => mul_temp_1_n_97,
P(7) => mul_temp_1_n_98,
P(6) => mul_temp_1_n_99,
P(5) => mul_temp_1_n_100,
P(4) => mul_temp_1_n_101,
P(3) => mul_temp_1_n_102,
P(2) => mul_temp_1_n_103,
P(1) => mul_temp_1_n_104,
P(0) => mul_temp_1_n_105,
PATTERNBDETECT => NLW_mul_temp_1_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_1_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_1_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_1_UNDERFLOW_UNCONNECTED
);
mul_temp_10: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[10]\(15),
A(28) => \data_pipeline_tmp_reg[10]\(15),
A(27) => \data_pipeline_tmp_reg[10]\(15),
A(26) => \data_pipeline_tmp_reg[10]\(15),
A(25) => \data_pipeline_tmp_reg[10]\(15),
A(24) => \data_pipeline_tmp_reg[10]\(15),
A(23) => \data_pipeline_tmp_reg[10]\(15),
A(22) => \data_pipeline_tmp_reg[10]\(15),
A(21) => \data_pipeline_tmp_reg[10]\(15),
A(20) => \data_pipeline_tmp_reg[10]\(15),
A(19) => \data_pipeline_tmp_reg[10]\(15),
A(18) => \data_pipeline_tmp_reg[10]\(15),
A(17) => \data_pipeline_tmp_reg[10]\(15),
A(16) => \data_pipeline_tmp_reg[10]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[10]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_10_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[10]_9\(15),
B(16) => \weight_reg[10]_9\(15),
B(15 downto 0) => \weight_reg[10]_9\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_10_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_10_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_10_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_10_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_10_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_10_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_10_n_74,
P(30) => mul_temp_10_n_75,
P(29) => mul_temp_10_n_76,
P(28) => mul_temp_10_n_77,
P(27) => mul_temp_10_n_78,
P(26) => mul_temp_10_n_79,
P(25) => mul_temp_10_n_80,
P(24) => mul_temp_10_n_81,
P(23) => mul_temp_10_n_82,
P(22) => mul_temp_10_n_83,
P(21) => mul_temp_10_n_84,
P(20) => mul_temp_10_n_85,
P(19) => mul_temp_10_n_86,
P(18) => mul_temp_10_n_87,
P(17) => mul_temp_10_n_88,
P(16) => mul_temp_10_n_89,
P(15) => mul_temp_10_n_90,
P(14) => \^mul_temp_10\(14),
P(13) => mul_temp_10_n_92,
P(12) => mul_temp_10_n_93,
P(11) => mul_temp_10_n_94,
P(10) => mul_temp_10_n_95,
P(9) => mul_temp_10_n_96,
P(8) => mul_temp_10_n_97,
P(7) => mul_temp_10_n_98,
P(6) => mul_temp_10_n_99,
P(5) => mul_temp_10_n_100,
P(4) => mul_temp_10_n_101,
P(3) => mul_temp_10_n_102,
P(2) => mul_temp_10_n_103,
P(1) => mul_temp_10_n_104,
P(0) => mul_temp_10_n_105,
PATTERNBDETECT => NLW_mul_temp_10_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_10_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_10_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_10_UNDERFLOW_UNCONNECTED
);
mul_temp_11: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[11]\(15),
A(28) => \data_pipeline_tmp_reg[11]\(15),
A(27) => \data_pipeline_tmp_reg[11]\(15),
A(26) => \data_pipeline_tmp_reg[11]\(15),
A(25) => \data_pipeline_tmp_reg[11]\(15),
A(24) => \data_pipeline_tmp_reg[11]\(15),
A(23) => \data_pipeline_tmp_reg[11]\(15),
A(22) => \data_pipeline_tmp_reg[11]\(15),
A(21) => \data_pipeline_tmp_reg[11]\(15),
A(20) => \data_pipeline_tmp_reg[11]\(15),
A(19) => \data_pipeline_tmp_reg[11]\(15),
A(18) => \data_pipeline_tmp_reg[11]\(15),
A(17) => \data_pipeline_tmp_reg[11]\(15),
A(16) => \data_pipeline_tmp_reg[11]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[11]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_11_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[11]_10\(15),
B(16) => \weight_reg[11]_10\(15),
B(15 downto 0) => \weight_reg[11]_10\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_11_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_11_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_11_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_11_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_11_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_11_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_11_n_74,
P(30) => mul_temp_11_n_75,
P(29) => mul_temp_11_n_76,
P(28) => mul_temp_11_n_77,
P(27) => mul_temp_11_n_78,
P(26) => mul_temp_11_n_79,
P(25) => mul_temp_11_n_80,
P(24) => mul_temp_11_n_81,
P(23) => mul_temp_11_n_82,
P(22) => mul_temp_11_n_83,
P(21) => mul_temp_11_n_84,
P(20) => mul_temp_11_n_85,
P(19) => mul_temp_11_n_86,
P(18) => mul_temp_11_n_87,
P(17) => mul_temp_11_n_88,
P(16) => mul_temp_11_n_89,
P(15) => mul_temp_11_n_90,
P(14) => \^mul_temp_11\(14),
P(13) => mul_temp_11_n_92,
P(12) => mul_temp_11_n_93,
P(11) => mul_temp_11_n_94,
P(10) => mul_temp_11_n_95,
P(9) => mul_temp_11_n_96,
P(8) => mul_temp_11_n_97,
P(7) => mul_temp_11_n_98,
P(6) => mul_temp_11_n_99,
P(5) => mul_temp_11_n_100,
P(4) => mul_temp_11_n_101,
P(3) => mul_temp_11_n_102,
P(2) => mul_temp_11_n_103,
P(1) => mul_temp_11_n_104,
P(0) => mul_temp_11_n_105,
PATTERNBDETECT => NLW_mul_temp_11_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_11_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_11_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_11_UNDERFLOW_UNCONNECTED
);
mul_temp_12: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[12]\(15),
A(28) => \data_pipeline_tmp_reg[12]\(15),
A(27) => \data_pipeline_tmp_reg[12]\(15),
A(26) => \data_pipeline_tmp_reg[12]\(15),
A(25) => \data_pipeline_tmp_reg[12]\(15),
A(24) => \data_pipeline_tmp_reg[12]\(15),
A(23) => \data_pipeline_tmp_reg[12]\(15),
A(22) => \data_pipeline_tmp_reg[12]\(15),
A(21) => \data_pipeline_tmp_reg[12]\(15),
A(20) => \data_pipeline_tmp_reg[12]\(15),
A(19) => \data_pipeline_tmp_reg[12]\(15),
A(18) => \data_pipeline_tmp_reg[12]\(15),
A(17) => \data_pipeline_tmp_reg[12]\(15),
A(16) => \data_pipeline_tmp_reg[12]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[12]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_12_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[12]_11\(15),
B(16) => \weight_reg[12]_11\(15),
B(15 downto 0) => \weight_reg[12]_11\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_12_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_12_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_12_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_12_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_12_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_12_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_12_n_74,
P(30) => mul_temp_12_n_75,
P(29) => mul_temp_12_n_76,
P(28) => mul_temp_12_n_77,
P(27) => mul_temp_12_n_78,
P(26) => mul_temp_12_n_79,
P(25) => mul_temp_12_n_80,
P(24) => mul_temp_12_n_81,
P(23) => mul_temp_12_n_82,
P(22) => mul_temp_12_n_83,
P(21) => mul_temp_12_n_84,
P(20) => mul_temp_12_n_85,
P(19) => mul_temp_12_n_86,
P(18) => mul_temp_12_n_87,
P(17) => mul_temp_12_n_88,
P(16) => mul_temp_12_n_89,
P(15) => mul_temp_12_n_90,
P(14) => \^mul_temp_12\(14),
P(13) => mul_temp_12_n_92,
P(12) => mul_temp_12_n_93,
P(11) => mul_temp_12_n_94,
P(10) => mul_temp_12_n_95,
P(9) => mul_temp_12_n_96,
P(8) => mul_temp_12_n_97,
P(7) => mul_temp_12_n_98,
P(6) => mul_temp_12_n_99,
P(5) => mul_temp_12_n_100,
P(4) => mul_temp_12_n_101,
P(3) => mul_temp_12_n_102,
P(2) => mul_temp_12_n_103,
P(1) => mul_temp_12_n_104,
P(0) => mul_temp_12_n_105,
PATTERNBDETECT => NLW_mul_temp_12_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_12_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_12_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_12_UNDERFLOW_UNCONNECTED
);
mul_temp_13: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[13]\(15),
A(28) => \data_pipeline_tmp_reg[13]\(15),
A(27) => \data_pipeline_tmp_reg[13]\(15),
A(26) => \data_pipeline_tmp_reg[13]\(15),
A(25) => \data_pipeline_tmp_reg[13]\(15),
A(24) => \data_pipeline_tmp_reg[13]\(15),
A(23) => \data_pipeline_tmp_reg[13]\(15),
A(22) => \data_pipeline_tmp_reg[13]\(15),
A(21) => \data_pipeline_tmp_reg[13]\(15),
A(20) => \data_pipeline_tmp_reg[13]\(15),
A(19) => \data_pipeline_tmp_reg[13]\(15),
A(18) => \data_pipeline_tmp_reg[13]\(15),
A(17) => \data_pipeline_tmp_reg[13]\(15),
A(16) => \data_pipeline_tmp_reg[13]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[13]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_13_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[13]_12\(15),
B(16) => \weight_reg[13]_12\(15),
B(15 downto 0) => \weight_reg[13]_12\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_13_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_13_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_13_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_13_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_13_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_13_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_13_n_74,
P(30) => mul_temp_13_n_75,
P(29) => mul_temp_13_n_76,
P(28) => mul_temp_13_n_77,
P(27) => mul_temp_13_n_78,
P(26) => mul_temp_13_n_79,
P(25) => mul_temp_13_n_80,
P(24) => mul_temp_13_n_81,
P(23) => mul_temp_13_n_82,
P(22) => mul_temp_13_n_83,
P(21) => mul_temp_13_n_84,
P(20) => mul_temp_13_n_85,
P(19) => mul_temp_13_n_86,
P(18) => mul_temp_13_n_87,
P(17) => mul_temp_13_n_88,
P(16) => mul_temp_13_n_89,
P(15) => mul_temp_13_n_90,
P(14) => \^mul_temp_13\(14),
P(13) => mul_temp_13_n_92,
P(12) => mul_temp_13_n_93,
P(11) => mul_temp_13_n_94,
P(10) => mul_temp_13_n_95,
P(9) => mul_temp_13_n_96,
P(8) => mul_temp_13_n_97,
P(7) => mul_temp_13_n_98,
P(6) => mul_temp_13_n_99,
P(5) => mul_temp_13_n_100,
P(4) => mul_temp_13_n_101,
P(3) => mul_temp_13_n_102,
P(2) => mul_temp_13_n_103,
P(1) => mul_temp_13_n_104,
P(0) => mul_temp_13_n_105,
PATTERNBDETECT => NLW_mul_temp_13_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_13_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_13_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_13_UNDERFLOW_UNCONNECTED
);
mul_temp_14: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[14]\(15),
A(28) => \data_pipeline_tmp_reg[14]\(15),
A(27) => \data_pipeline_tmp_reg[14]\(15),
A(26) => \data_pipeline_tmp_reg[14]\(15),
A(25) => \data_pipeline_tmp_reg[14]\(15),
A(24) => \data_pipeline_tmp_reg[14]\(15),
A(23) => \data_pipeline_tmp_reg[14]\(15),
A(22) => \data_pipeline_tmp_reg[14]\(15),
A(21) => \data_pipeline_tmp_reg[14]\(15),
A(20) => \data_pipeline_tmp_reg[14]\(15),
A(19) => \data_pipeline_tmp_reg[14]\(15),
A(18) => \data_pipeline_tmp_reg[14]\(15),
A(17) => \data_pipeline_tmp_reg[14]\(15),
A(16) => \data_pipeline_tmp_reg[14]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[14]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_14_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[14]_13\(15),
B(16) => \weight_reg[14]_13\(15),
B(15 downto 0) => \weight_reg[14]_13\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_14_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_14_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_14_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_14_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_14_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_14_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_14_n_74,
P(30) => mul_temp_14_n_75,
P(29) => mul_temp_14_n_76,
P(28) => mul_temp_14_n_77,
P(27) => mul_temp_14_n_78,
P(26) => mul_temp_14_n_79,
P(25) => mul_temp_14_n_80,
P(24) => mul_temp_14_n_81,
P(23) => mul_temp_14_n_82,
P(22) => mul_temp_14_n_83,
P(21) => mul_temp_14_n_84,
P(20) => mul_temp_14_n_85,
P(19) => mul_temp_14_n_86,
P(18) => mul_temp_14_n_87,
P(17) => mul_temp_14_n_88,
P(16) => mul_temp_14_n_89,
P(15) => mul_temp_14_n_90,
P(14) => \^mul_temp_14\(14),
P(13) => mul_temp_14_n_92,
P(12) => mul_temp_14_n_93,
P(11) => mul_temp_14_n_94,
P(10) => mul_temp_14_n_95,
P(9) => mul_temp_14_n_96,
P(8) => mul_temp_14_n_97,
P(7) => mul_temp_14_n_98,
P(6) => mul_temp_14_n_99,
P(5) => mul_temp_14_n_100,
P(4) => mul_temp_14_n_101,
P(3) => mul_temp_14_n_102,
P(2) => mul_temp_14_n_103,
P(1) => mul_temp_14_n_104,
P(0) => mul_temp_14_n_105,
PATTERNBDETECT => NLW_mul_temp_14_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_14_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_14_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_14_UNDERFLOW_UNCONNECTED
);
mul_temp_15: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \write_reg_x_k_reg[15]\(15),
A(28) => \write_reg_x_k_reg[15]\(15),
A(27) => \write_reg_x_k_reg[15]\(15),
A(26) => \write_reg_x_k_reg[15]\(15),
A(25) => \write_reg_x_k_reg[15]\(15),
A(24) => \write_reg_x_k_reg[15]\(15),
A(23) => \write_reg_x_k_reg[15]\(15),
A(22) => \write_reg_x_k_reg[15]\(15),
A(21) => \write_reg_x_k_reg[15]\(15),
A(20) => \write_reg_x_k_reg[15]\(15),
A(19) => \write_reg_x_k_reg[15]\(15),
A(18) => \write_reg_x_k_reg[15]\(15),
A(17) => \write_reg_x_k_reg[15]\(15),
A(16) => \write_reg_x_k_reg[15]\(15),
A(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_15_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[15]_14\(15),
B(16) => \weight_reg[15]_14\(15),
B(15 downto 0) => \weight_reg[15]_14\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_15_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_15_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_15_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_15_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_15_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_15_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_15_n_74,
P(30) => mul_temp_15_n_75,
P(29) => mul_temp_15_n_76,
P(28) => mul_temp_15_n_77,
P(27) => mul_temp_15_n_78,
P(26) => mul_temp_15_n_79,
P(25) => mul_temp_15_n_80,
P(24) => mul_temp_15_n_81,
P(23) => mul_temp_15_n_82,
P(22) => mul_temp_15_n_83,
P(21) => mul_temp_15_n_84,
P(20) => mul_temp_15_n_85,
P(19) => mul_temp_15_n_86,
P(18) => mul_temp_15_n_87,
P(17) => mul_temp_15_n_88,
P(16) => mul_temp_15_n_89,
P(15) => mul_temp_15_n_90,
P(14) => \^mul_temp_15\(14),
P(13) => mul_temp_15_n_92,
P(12) => mul_temp_15_n_93,
P(11) => mul_temp_15_n_94,
P(10) => mul_temp_15_n_95,
P(9) => mul_temp_15_n_96,
P(8) => mul_temp_15_n_97,
P(7) => mul_temp_15_n_98,
P(6) => mul_temp_15_n_99,
P(5) => mul_temp_15_n_100,
P(4) => mul_temp_15_n_101,
P(3) => mul_temp_15_n_102,
P(2) => mul_temp_15_n_103,
P(1) => mul_temp_15_n_104,
P(0) => mul_temp_15_n_105,
PATTERNBDETECT => NLW_mul_temp_15_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_15_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_15_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_15_UNDERFLOW_UNCONNECTED
);
mul_temp_17: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[0]\(15),
A(28) => \data_pipeline_tmp_reg[0]\(15),
A(27) => \data_pipeline_tmp_reg[0]\(15),
A(26) => \data_pipeline_tmp_reg[0]\(15),
A(25) => \data_pipeline_tmp_reg[0]\(15),
A(24) => \data_pipeline_tmp_reg[0]\(15),
A(23) => \data_pipeline_tmp_reg[0]\(15),
A(22) => \data_pipeline_tmp_reg[0]\(15),
A(21) => \data_pipeline_tmp_reg[0]\(15),
A(20) => \data_pipeline_tmp_reg[0]\(15),
A(19) => \data_pipeline_tmp_reg[0]\(15),
A(18) => \data_pipeline_tmp_reg[0]\(15),
A(17) => \data_pipeline_tmp_reg[0]\(15),
A(16) => \data_pipeline_tmp_reg[0]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[0]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_17_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_17_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_17_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_17_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_17_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_17_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_17_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_17_n_74,
P(30) => mul_temp_17_n_75,
P(29) => mul_temp_17_n_76,
P(28) => mul_temp_17_n_77,
P(27) => mul_temp_17_n_78,
P(26) => mul_temp_17_n_79,
P(25) => mul_temp_17_n_80,
P(24) => mul_temp_17_n_81,
P(23) => mul_temp_17_n_82,
P(22) => mul_temp_17_n_83,
P(21) => mul_temp_17_n_84,
P(20) => mul_temp_17_n_85,
P(19) => mul_temp_17_n_86,
P(18) => mul_temp_17_n_87,
P(17) => mul_temp_17_n_88,
P(16) => mul_temp_17_n_89,
P(15) => mul_temp_17_n_90,
P(14) => \^mul_temp_17\(14),
P(13) => mul_temp_17_n_92,
P(12) => mul_temp_17_n_93,
P(11) => mul_temp_17_n_94,
P(10) => mul_temp_17_n_95,
P(9) => mul_temp_17_n_96,
P(8) => mul_temp_17_n_97,
P(7) => mul_temp_17_n_98,
P(6) => mul_temp_17_n_99,
P(5) => mul_temp_17_n_100,
P(4) => mul_temp_17_n_101,
P(3) => mul_temp_17_n_102,
P(2) => mul_temp_17_n_103,
P(1) => mul_temp_17_n_104,
P(0) => mul_temp_17_n_105,
PATTERNBDETECT => NLW_mul_temp_17_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_17_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_17_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_17_UNDERFLOW_UNCONNECTED
);
mul_temp_18: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[1]\(15),
A(28) => \data_pipeline_tmp_reg[1]\(15),
A(27) => \data_pipeline_tmp_reg[1]\(15),
A(26) => \data_pipeline_tmp_reg[1]\(15),
A(25) => \data_pipeline_tmp_reg[1]\(15),
A(24) => \data_pipeline_tmp_reg[1]\(15),
A(23) => \data_pipeline_tmp_reg[1]\(15),
A(22) => \data_pipeline_tmp_reg[1]\(15),
A(21) => \data_pipeline_tmp_reg[1]\(15),
A(20) => \data_pipeline_tmp_reg[1]\(15),
A(19) => \data_pipeline_tmp_reg[1]\(15),
A(18) => \data_pipeline_tmp_reg[1]\(15),
A(17) => \data_pipeline_tmp_reg[1]\(15),
A(16) => \data_pipeline_tmp_reg[1]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[1]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_18_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_18_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_18_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_18_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_18_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_18_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_18_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_18_n_74,
P(30) => mul_temp_18_n_75,
P(29) => mul_temp_18_n_76,
P(28) => mul_temp_18_n_77,
P(27) => mul_temp_18_n_78,
P(26) => mul_temp_18_n_79,
P(25) => mul_temp_18_n_80,
P(24) => mul_temp_18_n_81,
P(23) => mul_temp_18_n_82,
P(22) => mul_temp_18_n_83,
P(21) => mul_temp_18_n_84,
P(20) => mul_temp_18_n_85,
P(19) => mul_temp_18_n_86,
P(18) => mul_temp_18_n_87,
P(17) => mul_temp_18_n_88,
P(16) => mul_temp_18_n_89,
P(15) => mul_temp_18_n_90,
P(14) => \^mul_temp_18\(14),
P(13) => mul_temp_18_n_92,
P(12) => mul_temp_18_n_93,
P(11) => mul_temp_18_n_94,
P(10) => mul_temp_18_n_95,
P(9) => mul_temp_18_n_96,
P(8) => mul_temp_18_n_97,
P(7) => mul_temp_18_n_98,
P(6) => mul_temp_18_n_99,
P(5) => mul_temp_18_n_100,
P(4) => mul_temp_18_n_101,
P(3) => mul_temp_18_n_102,
P(2) => mul_temp_18_n_103,
P(1) => mul_temp_18_n_104,
P(0) => mul_temp_18_n_105,
PATTERNBDETECT => NLW_mul_temp_18_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_18_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_18_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_18_UNDERFLOW_UNCONNECTED
);
mul_temp_19: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[2]\(15),
A(28) => \data_pipeline_tmp_reg[2]\(15),
A(27) => \data_pipeline_tmp_reg[2]\(15),
A(26) => \data_pipeline_tmp_reg[2]\(15),
A(25) => \data_pipeline_tmp_reg[2]\(15),
A(24) => \data_pipeline_tmp_reg[2]\(15),
A(23) => \data_pipeline_tmp_reg[2]\(15),
A(22) => \data_pipeline_tmp_reg[2]\(15),
A(21) => \data_pipeline_tmp_reg[2]\(15),
A(20) => \data_pipeline_tmp_reg[2]\(15),
A(19) => \data_pipeline_tmp_reg[2]\(15),
A(18) => \data_pipeline_tmp_reg[2]\(15),
A(17) => \data_pipeline_tmp_reg[2]\(15),
A(16) => \data_pipeline_tmp_reg[2]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[2]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_19_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_19_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_19_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_19_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_19_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_19_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_19_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_19_n_74,
P(30) => mul_temp_19_n_75,
P(29) => mul_temp_19_n_76,
P(28) => mul_temp_19_n_77,
P(27) => mul_temp_19_n_78,
P(26) => mul_temp_19_n_79,
P(25) => mul_temp_19_n_80,
P(24) => mul_temp_19_n_81,
P(23) => mul_temp_19_n_82,
P(22) => mul_temp_19_n_83,
P(21) => mul_temp_19_n_84,
P(20) => mul_temp_19_n_85,
P(19) => mul_temp_19_n_86,
P(18) => mul_temp_19_n_87,
P(17) => mul_temp_19_n_88,
P(16) => mul_temp_19_n_89,
P(15) => mul_temp_19_n_90,
P(14) => \^mul_temp_19\(14),
P(13) => mul_temp_19_n_92,
P(12) => mul_temp_19_n_93,
P(11) => mul_temp_19_n_94,
P(10) => mul_temp_19_n_95,
P(9) => mul_temp_19_n_96,
P(8) => mul_temp_19_n_97,
P(7) => mul_temp_19_n_98,
P(6) => mul_temp_19_n_99,
P(5) => mul_temp_19_n_100,
P(4) => mul_temp_19_n_101,
P(3) => mul_temp_19_n_102,
P(2) => mul_temp_19_n_103,
P(1) => mul_temp_19_n_104,
P(0) => mul_temp_19_n_105,
PATTERNBDETECT => NLW_mul_temp_19_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_19_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_19_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_19_UNDERFLOW_UNCONNECTED
);
mul_temp_2: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[2]\(15),
A(28) => \data_pipeline_tmp_reg[2]\(15),
A(27) => \data_pipeline_tmp_reg[2]\(15),
A(26) => \data_pipeline_tmp_reg[2]\(15),
A(25) => \data_pipeline_tmp_reg[2]\(15),
A(24) => \data_pipeline_tmp_reg[2]\(15),
A(23) => \data_pipeline_tmp_reg[2]\(15),
A(22) => \data_pipeline_tmp_reg[2]\(15),
A(21) => \data_pipeline_tmp_reg[2]\(15),
A(20) => \data_pipeline_tmp_reg[2]\(15),
A(19) => \data_pipeline_tmp_reg[2]\(15),
A(18) => \data_pipeline_tmp_reg[2]\(15),
A(17) => \data_pipeline_tmp_reg[2]\(15),
A(16) => \data_pipeline_tmp_reg[2]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[2]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_2_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[2]_1\(15),
B(16) => \weight_reg[2]_1\(15),
B(15 downto 0) => \weight_reg[2]_1\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_2_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_2_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_2_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_2_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_2_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_2_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_2_n_74,
P(30) => mul_temp_2_n_75,
P(29) => mul_temp_2_n_76,
P(28) => mul_temp_2_n_77,
P(27) => mul_temp_2_n_78,
P(26) => mul_temp_2_n_79,
P(25) => mul_temp_2_n_80,
P(24) => mul_temp_2_n_81,
P(23) => mul_temp_2_n_82,
P(22) => mul_temp_2_n_83,
P(21) => mul_temp_2_n_84,
P(20) => mul_temp_2_n_85,
P(19) => mul_temp_2_n_86,
P(18) => mul_temp_2_n_87,
P(17) => mul_temp_2_n_88,
P(16) => mul_temp_2_n_89,
P(15) => mul_temp_2_n_90,
P(14) => \^mul_temp_2\(14),
P(13) => mul_temp_2_n_92,
P(12) => mul_temp_2_n_93,
P(11) => mul_temp_2_n_94,
P(10) => mul_temp_2_n_95,
P(9) => mul_temp_2_n_96,
P(8) => mul_temp_2_n_97,
P(7) => mul_temp_2_n_98,
P(6) => mul_temp_2_n_99,
P(5) => mul_temp_2_n_100,
P(4) => mul_temp_2_n_101,
P(3) => mul_temp_2_n_102,
P(2) => mul_temp_2_n_103,
P(1) => mul_temp_2_n_104,
P(0) => mul_temp_2_n_105,
PATTERNBDETECT => NLW_mul_temp_2_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_2_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_2_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_2_UNDERFLOW_UNCONNECTED
);
mul_temp_20: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[3]\(15),
A(28) => \data_pipeline_tmp_reg[3]\(15),
A(27) => \data_pipeline_tmp_reg[3]\(15),
A(26) => \data_pipeline_tmp_reg[3]\(15),
A(25) => \data_pipeline_tmp_reg[3]\(15),
A(24) => \data_pipeline_tmp_reg[3]\(15),
A(23) => \data_pipeline_tmp_reg[3]\(15),
A(22) => \data_pipeline_tmp_reg[3]\(15),
A(21) => \data_pipeline_tmp_reg[3]\(15),
A(20) => \data_pipeline_tmp_reg[3]\(15),
A(19) => \data_pipeline_tmp_reg[3]\(15),
A(18) => \data_pipeline_tmp_reg[3]\(15),
A(17) => \data_pipeline_tmp_reg[3]\(15),
A(16) => \data_pipeline_tmp_reg[3]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[3]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_20_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_20_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_20_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_20_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_20_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_20_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_20_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_20_n_74,
P(30) => mul_temp_20_n_75,
P(29) => mul_temp_20_n_76,
P(28) => mul_temp_20_n_77,
P(27) => mul_temp_20_n_78,
P(26) => mul_temp_20_n_79,
P(25) => mul_temp_20_n_80,
P(24) => mul_temp_20_n_81,
P(23) => mul_temp_20_n_82,
P(22) => mul_temp_20_n_83,
P(21) => mul_temp_20_n_84,
P(20) => mul_temp_20_n_85,
P(19) => mul_temp_20_n_86,
P(18) => mul_temp_20_n_87,
P(17) => mul_temp_20_n_88,
P(16) => mul_temp_20_n_89,
P(15) => mul_temp_20_n_90,
P(14) => \^mul_temp_20\(14),
P(13) => mul_temp_20_n_92,
P(12) => mul_temp_20_n_93,
P(11) => mul_temp_20_n_94,
P(10) => mul_temp_20_n_95,
P(9) => mul_temp_20_n_96,
P(8) => mul_temp_20_n_97,
P(7) => mul_temp_20_n_98,
P(6) => mul_temp_20_n_99,
P(5) => mul_temp_20_n_100,
P(4) => mul_temp_20_n_101,
P(3) => mul_temp_20_n_102,
P(2) => mul_temp_20_n_103,
P(1) => mul_temp_20_n_104,
P(0) => mul_temp_20_n_105,
PATTERNBDETECT => NLW_mul_temp_20_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_20_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_20_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_20_UNDERFLOW_UNCONNECTED
);
mul_temp_21: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[4]\(15),
A(28) => \data_pipeline_tmp_reg[4]\(15),
A(27) => \data_pipeline_tmp_reg[4]\(15),
A(26) => \data_pipeline_tmp_reg[4]\(15),
A(25) => \data_pipeline_tmp_reg[4]\(15),
A(24) => \data_pipeline_tmp_reg[4]\(15),
A(23) => \data_pipeline_tmp_reg[4]\(15),
A(22) => \data_pipeline_tmp_reg[4]\(15),
A(21) => \data_pipeline_tmp_reg[4]\(15),
A(20) => \data_pipeline_tmp_reg[4]\(15),
A(19) => \data_pipeline_tmp_reg[4]\(15),
A(18) => \data_pipeline_tmp_reg[4]\(15),
A(17) => \data_pipeline_tmp_reg[4]\(15),
A(16) => \data_pipeline_tmp_reg[4]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[4]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_21_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_21_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_21_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_21_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_21_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_21_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_21_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_21_n_74,
P(30) => mul_temp_21_n_75,
P(29) => mul_temp_21_n_76,
P(28) => mul_temp_21_n_77,
P(27) => mul_temp_21_n_78,
P(26) => mul_temp_21_n_79,
P(25) => mul_temp_21_n_80,
P(24) => mul_temp_21_n_81,
P(23) => mul_temp_21_n_82,
P(22) => mul_temp_21_n_83,
P(21) => mul_temp_21_n_84,
P(20) => mul_temp_21_n_85,
P(19) => mul_temp_21_n_86,
P(18) => mul_temp_21_n_87,
P(17) => mul_temp_21_n_88,
P(16) => mul_temp_21_n_89,
P(15) => mul_temp_21_n_90,
P(14) => \^mul_temp_21\(14),
P(13) => mul_temp_21_n_92,
P(12) => mul_temp_21_n_93,
P(11) => mul_temp_21_n_94,
P(10) => mul_temp_21_n_95,
P(9) => mul_temp_21_n_96,
P(8) => mul_temp_21_n_97,
P(7) => mul_temp_21_n_98,
P(6) => mul_temp_21_n_99,
P(5) => mul_temp_21_n_100,
P(4) => mul_temp_21_n_101,
P(3) => mul_temp_21_n_102,
P(2) => mul_temp_21_n_103,
P(1) => mul_temp_21_n_104,
P(0) => mul_temp_21_n_105,
PATTERNBDETECT => NLW_mul_temp_21_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_21_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_21_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_21_UNDERFLOW_UNCONNECTED
);
mul_temp_22: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[5]\(15),
A(28) => \data_pipeline_tmp_reg[5]\(15),
A(27) => \data_pipeline_tmp_reg[5]\(15),
A(26) => \data_pipeline_tmp_reg[5]\(15),
A(25) => \data_pipeline_tmp_reg[5]\(15),
A(24) => \data_pipeline_tmp_reg[5]\(15),
A(23) => \data_pipeline_tmp_reg[5]\(15),
A(22) => \data_pipeline_tmp_reg[5]\(15),
A(21) => \data_pipeline_tmp_reg[5]\(15),
A(20) => \data_pipeline_tmp_reg[5]\(15),
A(19) => \data_pipeline_tmp_reg[5]\(15),
A(18) => \data_pipeline_tmp_reg[5]\(15),
A(17) => \data_pipeline_tmp_reg[5]\(15),
A(16) => \data_pipeline_tmp_reg[5]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[5]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_22_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_22_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_22_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_22_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_22_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_22_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_22_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_22_n_74,
P(30) => mul_temp_22_n_75,
P(29) => mul_temp_22_n_76,
P(28) => mul_temp_22_n_77,
P(27) => mul_temp_22_n_78,
P(26) => mul_temp_22_n_79,
P(25) => mul_temp_22_n_80,
P(24) => mul_temp_22_n_81,
P(23) => mul_temp_22_n_82,
P(22) => mul_temp_22_n_83,
P(21) => mul_temp_22_n_84,
P(20) => mul_temp_22_n_85,
P(19) => mul_temp_22_n_86,
P(18) => mul_temp_22_n_87,
P(17) => mul_temp_22_n_88,
P(16) => mul_temp_22_n_89,
P(15) => mul_temp_22_n_90,
P(14) => \^mul_temp_22\(14),
P(13) => mul_temp_22_n_92,
P(12) => mul_temp_22_n_93,
P(11) => mul_temp_22_n_94,
P(10) => mul_temp_22_n_95,
P(9) => mul_temp_22_n_96,
P(8) => mul_temp_22_n_97,
P(7) => mul_temp_22_n_98,
P(6) => mul_temp_22_n_99,
P(5) => mul_temp_22_n_100,
P(4) => mul_temp_22_n_101,
P(3) => mul_temp_22_n_102,
P(2) => mul_temp_22_n_103,
P(1) => mul_temp_22_n_104,
P(0) => mul_temp_22_n_105,
PATTERNBDETECT => NLW_mul_temp_22_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_22_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_22_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_22_UNDERFLOW_UNCONNECTED
);
mul_temp_23: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[6]\(15),
A(28) => \data_pipeline_tmp_reg[6]\(15),
A(27) => \data_pipeline_tmp_reg[6]\(15),
A(26) => \data_pipeline_tmp_reg[6]\(15),
A(25) => \data_pipeline_tmp_reg[6]\(15),
A(24) => \data_pipeline_tmp_reg[6]\(15),
A(23) => \data_pipeline_tmp_reg[6]\(15),
A(22) => \data_pipeline_tmp_reg[6]\(15),
A(21) => \data_pipeline_tmp_reg[6]\(15),
A(20) => \data_pipeline_tmp_reg[6]\(15),
A(19) => \data_pipeline_tmp_reg[6]\(15),
A(18) => \data_pipeline_tmp_reg[6]\(15),
A(17) => \data_pipeline_tmp_reg[6]\(15),
A(16) => \data_pipeline_tmp_reg[6]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[6]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_23_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_23_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_23_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_23_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_23_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_23_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_23_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_23_n_74,
P(30) => mul_temp_23_n_75,
P(29) => mul_temp_23_n_76,
P(28) => mul_temp_23_n_77,
P(27) => mul_temp_23_n_78,
P(26) => mul_temp_23_n_79,
P(25) => mul_temp_23_n_80,
P(24) => mul_temp_23_n_81,
P(23) => mul_temp_23_n_82,
P(22) => mul_temp_23_n_83,
P(21) => mul_temp_23_n_84,
P(20) => mul_temp_23_n_85,
P(19) => mul_temp_23_n_86,
P(18) => mul_temp_23_n_87,
P(17) => mul_temp_23_n_88,
P(16) => mul_temp_23_n_89,
P(15) => mul_temp_23_n_90,
P(14) => \^mul_temp_23\(14),
P(13) => mul_temp_23_n_92,
P(12) => mul_temp_23_n_93,
P(11) => mul_temp_23_n_94,
P(10) => mul_temp_23_n_95,
P(9) => mul_temp_23_n_96,
P(8) => mul_temp_23_n_97,
P(7) => mul_temp_23_n_98,
P(6) => mul_temp_23_n_99,
P(5) => mul_temp_23_n_100,
P(4) => mul_temp_23_n_101,
P(3) => mul_temp_23_n_102,
P(2) => mul_temp_23_n_103,
P(1) => mul_temp_23_n_104,
P(0) => mul_temp_23_n_105,
PATTERNBDETECT => NLW_mul_temp_23_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_23_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_23_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_23_UNDERFLOW_UNCONNECTED
);
mul_temp_24: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[7]\(15),
A(28) => \data_pipeline_tmp_reg[7]\(15),
A(27) => \data_pipeline_tmp_reg[7]\(15),
A(26) => \data_pipeline_tmp_reg[7]\(15),
A(25) => \data_pipeline_tmp_reg[7]\(15),
A(24) => \data_pipeline_tmp_reg[7]\(15),
A(23) => \data_pipeline_tmp_reg[7]\(15),
A(22) => \data_pipeline_tmp_reg[7]\(15),
A(21) => \data_pipeline_tmp_reg[7]\(15),
A(20) => \data_pipeline_tmp_reg[7]\(15),
A(19) => \data_pipeline_tmp_reg[7]\(15),
A(18) => \data_pipeline_tmp_reg[7]\(15),
A(17) => \data_pipeline_tmp_reg[7]\(15),
A(16) => \data_pipeline_tmp_reg[7]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[7]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_24_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_24_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_24_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_24_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_24_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_24_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_24_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_24_n_74,
P(30) => mul_temp_24_n_75,
P(29) => mul_temp_24_n_76,
P(28) => mul_temp_24_n_77,
P(27) => mul_temp_24_n_78,
P(26) => mul_temp_24_n_79,
P(25) => mul_temp_24_n_80,
P(24) => mul_temp_24_n_81,
P(23) => mul_temp_24_n_82,
P(22) => mul_temp_24_n_83,
P(21) => mul_temp_24_n_84,
P(20) => mul_temp_24_n_85,
P(19) => mul_temp_24_n_86,
P(18) => mul_temp_24_n_87,
P(17) => mul_temp_24_n_88,
P(16) => mul_temp_24_n_89,
P(15) => mul_temp_24_n_90,
P(14) => \^mul_temp_24\(14),
P(13) => mul_temp_24_n_92,
P(12) => mul_temp_24_n_93,
P(11) => mul_temp_24_n_94,
P(10) => mul_temp_24_n_95,
P(9) => mul_temp_24_n_96,
P(8) => mul_temp_24_n_97,
P(7) => mul_temp_24_n_98,
P(6) => mul_temp_24_n_99,
P(5) => mul_temp_24_n_100,
P(4) => mul_temp_24_n_101,
P(3) => mul_temp_24_n_102,
P(2) => mul_temp_24_n_103,
P(1) => mul_temp_24_n_104,
P(0) => mul_temp_24_n_105,
PATTERNBDETECT => NLW_mul_temp_24_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_24_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_24_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_24_UNDERFLOW_UNCONNECTED
);
mul_temp_25: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[8]\(15),
A(28) => \data_pipeline_tmp_reg[8]\(15),
A(27) => \data_pipeline_tmp_reg[8]\(15),
A(26) => \data_pipeline_tmp_reg[8]\(15),
A(25) => \data_pipeline_tmp_reg[8]\(15),
A(24) => \data_pipeline_tmp_reg[8]\(15),
A(23) => \data_pipeline_tmp_reg[8]\(15),
A(22) => \data_pipeline_tmp_reg[8]\(15),
A(21) => \data_pipeline_tmp_reg[8]\(15),
A(20) => \data_pipeline_tmp_reg[8]\(15),
A(19) => \data_pipeline_tmp_reg[8]\(15),
A(18) => \data_pipeline_tmp_reg[8]\(15),
A(17) => \data_pipeline_tmp_reg[8]\(15),
A(16) => \data_pipeline_tmp_reg[8]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[8]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_25_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_25_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_25_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_25_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_25_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_25_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_25_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_25_n_74,
P(30) => mul_temp_25_n_75,
P(29) => mul_temp_25_n_76,
P(28) => mul_temp_25_n_77,
P(27) => mul_temp_25_n_78,
P(26) => mul_temp_25_n_79,
P(25) => mul_temp_25_n_80,
P(24) => mul_temp_25_n_81,
P(23) => mul_temp_25_n_82,
P(22) => mul_temp_25_n_83,
P(21) => mul_temp_25_n_84,
P(20) => mul_temp_25_n_85,
P(19) => mul_temp_25_n_86,
P(18) => mul_temp_25_n_87,
P(17) => mul_temp_25_n_88,
P(16) => mul_temp_25_n_89,
P(15) => mul_temp_25_n_90,
P(14) => \^mul_temp_25\(14),
P(13) => mul_temp_25_n_92,
P(12) => mul_temp_25_n_93,
P(11) => mul_temp_25_n_94,
P(10) => mul_temp_25_n_95,
P(9) => mul_temp_25_n_96,
P(8) => mul_temp_25_n_97,
P(7) => mul_temp_25_n_98,
P(6) => mul_temp_25_n_99,
P(5) => mul_temp_25_n_100,
P(4) => mul_temp_25_n_101,
P(3) => mul_temp_25_n_102,
P(2) => mul_temp_25_n_103,
P(1) => mul_temp_25_n_104,
P(0) => mul_temp_25_n_105,
PATTERNBDETECT => NLW_mul_temp_25_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_25_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_25_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_25_UNDERFLOW_UNCONNECTED
);
mul_temp_26: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[9]\(15),
A(28) => \data_pipeline_tmp_reg[9]\(15),
A(27) => \data_pipeline_tmp_reg[9]\(15),
A(26) => \data_pipeline_tmp_reg[9]\(15),
A(25) => \data_pipeline_tmp_reg[9]\(15),
A(24) => \data_pipeline_tmp_reg[9]\(15),
A(23) => \data_pipeline_tmp_reg[9]\(15),
A(22) => \data_pipeline_tmp_reg[9]\(15),
A(21) => \data_pipeline_tmp_reg[9]\(15),
A(20) => \data_pipeline_tmp_reg[9]\(15),
A(19) => \data_pipeline_tmp_reg[9]\(15),
A(18) => \data_pipeline_tmp_reg[9]\(15),
A(17) => \data_pipeline_tmp_reg[9]\(15),
A(16) => \data_pipeline_tmp_reg[9]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[9]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_26_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_26_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_26_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_26_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_26_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_26_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_26_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_26_n_74,
P(30) => mul_temp_26_n_75,
P(29) => mul_temp_26_n_76,
P(28) => mul_temp_26_n_77,
P(27) => mul_temp_26_n_78,
P(26) => mul_temp_26_n_79,
P(25) => mul_temp_26_n_80,
P(24) => mul_temp_26_n_81,
P(23) => mul_temp_26_n_82,
P(22) => mul_temp_26_n_83,
P(21) => mul_temp_26_n_84,
P(20) => mul_temp_26_n_85,
P(19) => mul_temp_26_n_86,
P(18) => mul_temp_26_n_87,
P(17) => mul_temp_26_n_88,
P(16) => mul_temp_26_n_89,
P(15) => mul_temp_26_n_90,
P(14) => \^mul_temp_26\(14),
P(13) => mul_temp_26_n_92,
P(12) => mul_temp_26_n_93,
P(11) => mul_temp_26_n_94,
P(10) => mul_temp_26_n_95,
P(9) => mul_temp_26_n_96,
P(8) => mul_temp_26_n_97,
P(7) => mul_temp_26_n_98,
P(6) => mul_temp_26_n_99,
P(5) => mul_temp_26_n_100,
P(4) => mul_temp_26_n_101,
P(3) => mul_temp_26_n_102,
P(2) => mul_temp_26_n_103,
P(1) => mul_temp_26_n_104,
P(0) => mul_temp_26_n_105,
PATTERNBDETECT => NLW_mul_temp_26_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_26_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_26_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_26_UNDERFLOW_UNCONNECTED
);
mul_temp_27: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[10]\(15),
A(28) => \data_pipeline_tmp_reg[10]\(15),
A(27) => \data_pipeline_tmp_reg[10]\(15),
A(26) => \data_pipeline_tmp_reg[10]\(15),
A(25) => \data_pipeline_tmp_reg[10]\(15),
A(24) => \data_pipeline_tmp_reg[10]\(15),
A(23) => \data_pipeline_tmp_reg[10]\(15),
A(22) => \data_pipeline_tmp_reg[10]\(15),
A(21) => \data_pipeline_tmp_reg[10]\(15),
A(20) => \data_pipeline_tmp_reg[10]\(15),
A(19) => \data_pipeline_tmp_reg[10]\(15),
A(18) => \data_pipeline_tmp_reg[10]\(15),
A(17) => \data_pipeline_tmp_reg[10]\(15),
A(16) => \data_pipeline_tmp_reg[10]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[10]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_27_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_27_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_27_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_27_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_27_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_27_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_27_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_27_n_74,
P(30) => mul_temp_27_n_75,
P(29) => mul_temp_27_n_76,
P(28) => mul_temp_27_n_77,
P(27) => mul_temp_27_n_78,
P(26) => mul_temp_27_n_79,
P(25) => mul_temp_27_n_80,
P(24) => mul_temp_27_n_81,
P(23) => mul_temp_27_n_82,
P(22) => mul_temp_27_n_83,
P(21) => mul_temp_27_n_84,
P(20) => mul_temp_27_n_85,
P(19) => mul_temp_27_n_86,
P(18) => mul_temp_27_n_87,
P(17) => mul_temp_27_n_88,
P(16) => mul_temp_27_n_89,
P(15) => mul_temp_27_n_90,
P(14) => \^mul_temp_27\(14),
P(13) => mul_temp_27_n_92,
P(12) => mul_temp_27_n_93,
P(11) => mul_temp_27_n_94,
P(10) => mul_temp_27_n_95,
P(9) => mul_temp_27_n_96,
P(8) => mul_temp_27_n_97,
P(7) => mul_temp_27_n_98,
P(6) => mul_temp_27_n_99,
P(5) => mul_temp_27_n_100,
P(4) => mul_temp_27_n_101,
P(3) => mul_temp_27_n_102,
P(2) => mul_temp_27_n_103,
P(1) => mul_temp_27_n_104,
P(0) => mul_temp_27_n_105,
PATTERNBDETECT => NLW_mul_temp_27_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_27_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_27_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_27_UNDERFLOW_UNCONNECTED
);
mul_temp_28: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[11]\(15),
A(28) => \data_pipeline_tmp_reg[11]\(15),
A(27) => \data_pipeline_tmp_reg[11]\(15),
A(26) => \data_pipeline_tmp_reg[11]\(15),
A(25) => \data_pipeline_tmp_reg[11]\(15),
A(24) => \data_pipeline_tmp_reg[11]\(15),
A(23) => \data_pipeline_tmp_reg[11]\(15),
A(22) => \data_pipeline_tmp_reg[11]\(15),
A(21) => \data_pipeline_tmp_reg[11]\(15),
A(20) => \data_pipeline_tmp_reg[11]\(15),
A(19) => \data_pipeline_tmp_reg[11]\(15),
A(18) => \data_pipeline_tmp_reg[11]\(15),
A(17) => \data_pipeline_tmp_reg[11]\(15),
A(16) => \data_pipeline_tmp_reg[11]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[11]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_28_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_28_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_28_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_28_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_28_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_28_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_28_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_28_n_74,
P(30) => mul_temp_28_n_75,
P(29) => mul_temp_28_n_76,
P(28) => mul_temp_28_n_77,
P(27) => mul_temp_28_n_78,
P(26) => mul_temp_28_n_79,
P(25) => mul_temp_28_n_80,
P(24) => mul_temp_28_n_81,
P(23) => mul_temp_28_n_82,
P(22) => mul_temp_28_n_83,
P(21) => mul_temp_28_n_84,
P(20) => mul_temp_28_n_85,
P(19) => mul_temp_28_n_86,
P(18) => mul_temp_28_n_87,
P(17) => mul_temp_28_n_88,
P(16) => mul_temp_28_n_89,
P(15) => mul_temp_28_n_90,
P(14) => \^mul_temp_28\(14),
P(13) => mul_temp_28_n_92,
P(12) => mul_temp_28_n_93,
P(11) => mul_temp_28_n_94,
P(10) => mul_temp_28_n_95,
P(9) => mul_temp_28_n_96,
P(8) => mul_temp_28_n_97,
P(7) => mul_temp_28_n_98,
P(6) => mul_temp_28_n_99,
P(5) => mul_temp_28_n_100,
P(4) => mul_temp_28_n_101,
P(3) => mul_temp_28_n_102,
P(2) => mul_temp_28_n_103,
P(1) => mul_temp_28_n_104,
P(0) => mul_temp_28_n_105,
PATTERNBDETECT => NLW_mul_temp_28_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_28_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_28_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_28_UNDERFLOW_UNCONNECTED
);
mul_temp_29: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[12]\(15),
A(28) => \data_pipeline_tmp_reg[12]\(15),
A(27) => \data_pipeline_tmp_reg[12]\(15),
A(26) => \data_pipeline_tmp_reg[12]\(15),
A(25) => \data_pipeline_tmp_reg[12]\(15),
A(24) => \data_pipeline_tmp_reg[12]\(15),
A(23) => \data_pipeline_tmp_reg[12]\(15),
A(22) => \data_pipeline_tmp_reg[12]\(15),
A(21) => \data_pipeline_tmp_reg[12]\(15),
A(20) => \data_pipeline_tmp_reg[12]\(15),
A(19) => \data_pipeline_tmp_reg[12]\(15),
A(18) => \data_pipeline_tmp_reg[12]\(15),
A(17) => \data_pipeline_tmp_reg[12]\(15),
A(16) => \data_pipeline_tmp_reg[12]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[12]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_29_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_29_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_29_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_29_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_29_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_29_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_29_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_29_n_74,
P(30) => mul_temp_29_n_75,
P(29) => mul_temp_29_n_76,
P(28) => mul_temp_29_n_77,
P(27) => mul_temp_29_n_78,
P(26) => mul_temp_29_n_79,
P(25) => mul_temp_29_n_80,
P(24) => mul_temp_29_n_81,
P(23) => mul_temp_29_n_82,
P(22) => mul_temp_29_n_83,
P(21) => mul_temp_29_n_84,
P(20) => mul_temp_29_n_85,
P(19) => mul_temp_29_n_86,
P(18) => mul_temp_29_n_87,
P(17) => mul_temp_29_n_88,
P(16) => mul_temp_29_n_89,
P(15) => mul_temp_29_n_90,
P(14) => \^mul_temp_29\(14),
P(13) => mul_temp_29_n_92,
P(12) => mul_temp_29_n_93,
P(11) => mul_temp_29_n_94,
P(10) => mul_temp_29_n_95,
P(9) => mul_temp_29_n_96,
P(8) => mul_temp_29_n_97,
P(7) => mul_temp_29_n_98,
P(6) => mul_temp_29_n_99,
P(5) => mul_temp_29_n_100,
P(4) => mul_temp_29_n_101,
P(3) => mul_temp_29_n_102,
P(2) => mul_temp_29_n_103,
P(1) => mul_temp_29_n_104,
P(0) => mul_temp_29_n_105,
PATTERNBDETECT => NLW_mul_temp_29_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_29_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_29_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_29_UNDERFLOW_UNCONNECTED
);
mul_temp_3: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[3]\(15),
A(28) => \data_pipeline_tmp_reg[3]\(15),
A(27) => \data_pipeline_tmp_reg[3]\(15),
A(26) => \data_pipeline_tmp_reg[3]\(15),
A(25) => \data_pipeline_tmp_reg[3]\(15),
A(24) => \data_pipeline_tmp_reg[3]\(15),
A(23) => \data_pipeline_tmp_reg[3]\(15),
A(22) => \data_pipeline_tmp_reg[3]\(15),
A(21) => \data_pipeline_tmp_reg[3]\(15),
A(20) => \data_pipeline_tmp_reg[3]\(15),
A(19) => \data_pipeline_tmp_reg[3]\(15),
A(18) => \data_pipeline_tmp_reg[3]\(15),
A(17) => \data_pipeline_tmp_reg[3]\(15),
A(16) => \data_pipeline_tmp_reg[3]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[3]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_3_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[3]_2\(15),
B(16) => \weight_reg[3]_2\(15),
B(15 downto 0) => \weight_reg[3]_2\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_3_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_3_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_3_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_3_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_3_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_3_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_3_n_74,
P(30) => mul_temp_3_n_75,
P(29) => mul_temp_3_n_76,
P(28) => mul_temp_3_n_77,
P(27) => mul_temp_3_n_78,
P(26) => mul_temp_3_n_79,
P(25) => mul_temp_3_n_80,
P(24) => mul_temp_3_n_81,
P(23) => mul_temp_3_n_82,
P(22) => mul_temp_3_n_83,
P(21) => mul_temp_3_n_84,
P(20) => mul_temp_3_n_85,
P(19) => mul_temp_3_n_86,
P(18) => mul_temp_3_n_87,
P(17) => mul_temp_3_n_88,
P(16) => mul_temp_3_n_89,
P(15) => mul_temp_3_n_90,
P(14) => \^mul_temp_3\(14),
P(13) => mul_temp_3_n_92,
P(12) => mul_temp_3_n_93,
P(11) => mul_temp_3_n_94,
P(10) => mul_temp_3_n_95,
P(9) => mul_temp_3_n_96,
P(8) => mul_temp_3_n_97,
P(7) => mul_temp_3_n_98,
P(6) => mul_temp_3_n_99,
P(5) => mul_temp_3_n_100,
P(4) => mul_temp_3_n_101,
P(3) => mul_temp_3_n_102,
P(2) => mul_temp_3_n_103,
P(1) => mul_temp_3_n_104,
P(0) => mul_temp_3_n_105,
PATTERNBDETECT => NLW_mul_temp_3_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_3_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_3_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_3_UNDERFLOW_UNCONNECTED
);
mul_temp_30: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[13]\(15),
A(28) => \data_pipeline_tmp_reg[13]\(15),
A(27) => \data_pipeline_tmp_reg[13]\(15),
A(26) => \data_pipeline_tmp_reg[13]\(15),
A(25) => \data_pipeline_tmp_reg[13]\(15),
A(24) => \data_pipeline_tmp_reg[13]\(15),
A(23) => \data_pipeline_tmp_reg[13]\(15),
A(22) => \data_pipeline_tmp_reg[13]\(15),
A(21) => \data_pipeline_tmp_reg[13]\(15),
A(20) => \data_pipeline_tmp_reg[13]\(15),
A(19) => \data_pipeline_tmp_reg[13]\(15),
A(18) => \data_pipeline_tmp_reg[13]\(15),
A(17) => \data_pipeline_tmp_reg[13]\(15),
A(16) => \data_pipeline_tmp_reg[13]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[13]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_30_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_30_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_30_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_30_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_30_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_30_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_30_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_30_n_74,
P(30) => mul_temp_30_n_75,
P(29) => mul_temp_30_n_76,
P(28) => mul_temp_30_n_77,
P(27) => mul_temp_30_n_78,
P(26) => mul_temp_30_n_79,
P(25) => mul_temp_30_n_80,
P(24) => mul_temp_30_n_81,
P(23) => mul_temp_30_n_82,
P(22) => mul_temp_30_n_83,
P(21) => mul_temp_30_n_84,
P(20) => mul_temp_30_n_85,
P(19) => mul_temp_30_n_86,
P(18) => mul_temp_30_n_87,
P(17) => mul_temp_30_n_88,
P(16) => mul_temp_30_n_89,
P(15) => mul_temp_30_n_90,
P(14) => \^mul_temp_30\(14),
P(13) => mul_temp_30_n_92,
P(12) => mul_temp_30_n_93,
P(11) => mul_temp_30_n_94,
P(10) => mul_temp_30_n_95,
P(9) => mul_temp_30_n_96,
P(8) => mul_temp_30_n_97,
P(7) => mul_temp_30_n_98,
P(6) => mul_temp_30_n_99,
P(5) => mul_temp_30_n_100,
P(4) => mul_temp_30_n_101,
P(3) => mul_temp_30_n_102,
P(2) => mul_temp_30_n_103,
P(1) => mul_temp_30_n_104,
P(0) => mul_temp_30_n_105,
PATTERNBDETECT => NLW_mul_temp_30_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_30_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_30_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_30_UNDERFLOW_UNCONNECTED
);
mul_temp_31: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[14]\(15),
A(28) => \data_pipeline_tmp_reg[14]\(15),
A(27) => \data_pipeline_tmp_reg[14]\(15),
A(26) => \data_pipeline_tmp_reg[14]\(15),
A(25) => \data_pipeline_tmp_reg[14]\(15),
A(24) => \data_pipeline_tmp_reg[14]\(15),
A(23) => \data_pipeline_tmp_reg[14]\(15),
A(22) => \data_pipeline_tmp_reg[14]\(15),
A(21) => \data_pipeline_tmp_reg[14]\(15),
A(20) => \data_pipeline_tmp_reg[14]\(15),
A(19) => \data_pipeline_tmp_reg[14]\(15),
A(18) => \data_pipeline_tmp_reg[14]\(15),
A(17) => \data_pipeline_tmp_reg[14]\(15),
A(16) => \data_pipeline_tmp_reg[14]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[14]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_31_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_31_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_31_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_31_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_31_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_31_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_31_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_31_n_74,
P(30) => mul_temp_31_n_75,
P(29) => mul_temp_31_n_76,
P(28) => mul_temp_31_n_77,
P(27) => mul_temp_31_n_78,
P(26) => mul_temp_31_n_79,
P(25) => mul_temp_31_n_80,
P(24) => mul_temp_31_n_81,
P(23) => mul_temp_31_n_82,
P(22) => mul_temp_31_n_83,
P(21) => mul_temp_31_n_84,
P(20) => mul_temp_31_n_85,
P(19) => mul_temp_31_n_86,
P(18) => mul_temp_31_n_87,
P(17) => mul_temp_31_n_88,
P(16) => mul_temp_31_n_89,
P(15) => mul_temp_31_n_90,
P(14) => \^mul_temp_31\(14),
P(13) => mul_temp_31_n_92,
P(12) => mul_temp_31_n_93,
P(11) => mul_temp_31_n_94,
P(10) => mul_temp_31_n_95,
P(9) => mul_temp_31_n_96,
P(8) => mul_temp_31_n_97,
P(7) => mul_temp_31_n_98,
P(6) => mul_temp_31_n_99,
P(5) => mul_temp_31_n_100,
P(4) => mul_temp_31_n_101,
P(3) => mul_temp_31_n_102,
P(2) => mul_temp_31_n_103,
P(1) => mul_temp_31_n_104,
P(0) => mul_temp_31_n_105,
PATTERNBDETECT => NLW_mul_temp_31_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_31_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_31_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_31_UNDERFLOW_UNCONNECTED
);
mul_temp_32: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \write_reg_x_k_reg[15]\(15),
A(28) => \write_reg_x_k_reg[15]\(15),
A(27) => \write_reg_x_k_reg[15]\(15),
A(26) => \write_reg_x_k_reg[15]\(15),
A(25) => \write_reg_x_k_reg[15]\(15),
A(24) => \write_reg_x_k_reg[15]\(15),
A(23) => \write_reg_x_k_reg[15]\(15),
A(22) => \write_reg_x_k_reg[15]\(15),
A(21) => \write_reg_x_k_reg[15]\(15),
A(20) => \write_reg_x_k_reg[15]\(15),
A(19) => \write_reg_x_k_reg[15]\(15),
A(18) => \write_reg_x_k_reg[15]\(15),
A(17) => \write_reg_x_k_reg[15]\(15),
A(16) => \write_reg_x_k_reg[15]\(15),
A(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_32_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_32_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_32_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_32_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_32_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_32_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_32_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_32_n_74,
P(30) => mul_temp_32_n_75,
P(29) => mul_temp_32_n_76,
P(28) => mul_temp_32_n_77,
P(27) => mul_temp_32_n_78,
P(26) => mul_temp_32_n_79,
P(25) => mul_temp_32_n_80,
P(24) => mul_temp_32_n_81,
P(23) => mul_temp_32_n_82,
P(22) => mul_temp_32_n_83,
P(21) => mul_temp_32_n_84,
P(20) => mul_temp_32_n_85,
P(19) => mul_temp_32_n_86,
P(18) => mul_temp_32_n_87,
P(17) => mul_temp_32_n_88,
P(16) => mul_temp_32_n_89,
P(15) => mul_temp_32_n_90,
P(14) => \^mul_temp_32\(14),
P(13) => mul_temp_32_n_92,
P(12) => mul_temp_32_n_93,
P(11) => mul_temp_32_n_94,
P(10) => mul_temp_32_n_95,
P(9) => mul_temp_32_n_96,
P(8) => mul_temp_32_n_97,
P(7) => mul_temp_32_n_98,
P(6) => mul_temp_32_n_99,
P(5) => mul_temp_32_n_100,
P(4) => mul_temp_32_n_101,
P(3) => mul_temp_32_n_102,
P(2) => mul_temp_32_n_103,
P(1) => mul_temp_32_n_104,
P(0) => mul_temp_32_n_105,
PATTERNBDETECT => NLW_mul_temp_32_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_32_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_32_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_32_UNDERFLOW_UNCONNECTED
);
mul_temp_4: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[4]\(15),
A(28) => \data_pipeline_tmp_reg[4]\(15),
A(27) => \data_pipeline_tmp_reg[4]\(15),
A(26) => \data_pipeline_tmp_reg[4]\(15),
A(25) => \data_pipeline_tmp_reg[4]\(15),
A(24) => \data_pipeline_tmp_reg[4]\(15),
A(23) => \data_pipeline_tmp_reg[4]\(15),
A(22) => \data_pipeline_tmp_reg[4]\(15),
A(21) => \data_pipeline_tmp_reg[4]\(15),
A(20) => \data_pipeline_tmp_reg[4]\(15),
A(19) => \data_pipeline_tmp_reg[4]\(15),
A(18) => \data_pipeline_tmp_reg[4]\(15),
A(17) => \data_pipeline_tmp_reg[4]\(15),
A(16) => \data_pipeline_tmp_reg[4]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[4]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_4_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[4]_3\(15),
B(16) => \weight_reg[4]_3\(15),
B(15 downto 0) => \weight_reg[4]_3\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_4_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_4_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_4_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_4_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_4_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_4_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_4_n_74,
P(30) => mul_temp_4_n_75,
P(29) => mul_temp_4_n_76,
P(28) => mul_temp_4_n_77,
P(27) => mul_temp_4_n_78,
P(26) => mul_temp_4_n_79,
P(25) => mul_temp_4_n_80,
P(24) => mul_temp_4_n_81,
P(23) => mul_temp_4_n_82,
P(22) => mul_temp_4_n_83,
P(21) => mul_temp_4_n_84,
P(20) => mul_temp_4_n_85,
P(19) => mul_temp_4_n_86,
P(18) => mul_temp_4_n_87,
P(17) => mul_temp_4_n_88,
P(16) => mul_temp_4_n_89,
P(15) => mul_temp_4_n_90,
P(14) => \^mul_temp_4\(14),
P(13) => mul_temp_4_n_92,
P(12) => mul_temp_4_n_93,
P(11) => mul_temp_4_n_94,
P(10) => mul_temp_4_n_95,
P(9) => mul_temp_4_n_96,
P(8) => mul_temp_4_n_97,
P(7) => mul_temp_4_n_98,
P(6) => mul_temp_4_n_99,
P(5) => mul_temp_4_n_100,
P(4) => mul_temp_4_n_101,
P(3) => mul_temp_4_n_102,
P(2) => mul_temp_4_n_103,
P(1) => mul_temp_4_n_104,
P(0) => mul_temp_4_n_105,
PATTERNBDETECT => NLW_mul_temp_4_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_4_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_4_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_4_UNDERFLOW_UNCONNECTED
);
mul_temp_5: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[5]\(15),
A(28) => \data_pipeline_tmp_reg[5]\(15),
A(27) => \data_pipeline_tmp_reg[5]\(15),
A(26) => \data_pipeline_tmp_reg[5]\(15),
A(25) => \data_pipeline_tmp_reg[5]\(15),
A(24) => \data_pipeline_tmp_reg[5]\(15),
A(23) => \data_pipeline_tmp_reg[5]\(15),
A(22) => \data_pipeline_tmp_reg[5]\(15),
A(21) => \data_pipeline_tmp_reg[5]\(15),
A(20) => \data_pipeline_tmp_reg[5]\(15),
A(19) => \data_pipeline_tmp_reg[5]\(15),
A(18) => \data_pipeline_tmp_reg[5]\(15),
A(17) => \data_pipeline_tmp_reg[5]\(15),
A(16) => \data_pipeline_tmp_reg[5]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[5]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_5_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[5]_4\(15),
B(16) => \weight_reg[5]_4\(15),
B(15 downto 0) => \weight_reg[5]_4\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_5_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_5_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_5_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_5_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_5_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_5_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_5_n_74,
P(30) => mul_temp_5_n_75,
P(29) => mul_temp_5_n_76,
P(28) => mul_temp_5_n_77,
P(27) => mul_temp_5_n_78,
P(26) => mul_temp_5_n_79,
P(25) => mul_temp_5_n_80,
P(24) => mul_temp_5_n_81,
P(23) => mul_temp_5_n_82,
P(22) => mul_temp_5_n_83,
P(21) => mul_temp_5_n_84,
P(20) => mul_temp_5_n_85,
P(19) => mul_temp_5_n_86,
P(18) => mul_temp_5_n_87,
P(17) => mul_temp_5_n_88,
P(16) => mul_temp_5_n_89,
P(15) => mul_temp_5_n_90,
P(14) => \^mul_temp_5\(14),
P(13) => mul_temp_5_n_92,
P(12) => mul_temp_5_n_93,
P(11) => mul_temp_5_n_94,
P(10) => mul_temp_5_n_95,
P(9) => mul_temp_5_n_96,
P(8) => mul_temp_5_n_97,
P(7) => mul_temp_5_n_98,
P(6) => mul_temp_5_n_99,
P(5) => mul_temp_5_n_100,
P(4) => mul_temp_5_n_101,
P(3) => mul_temp_5_n_102,
P(2) => mul_temp_5_n_103,
P(1) => mul_temp_5_n_104,
P(0) => mul_temp_5_n_105,
PATTERNBDETECT => NLW_mul_temp_5_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_5_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_5_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_5_UNDERFLOW_UNCONNECTED
);
mul_temp_6: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[6]\(15),
A(28) => \data_pipeline_tmp_reg[6]\(15),
A(27) => \data_pipeline_tmp_reg[6]\(15),
A(26) => \data_pipeline_tmp_reg[6]\(15),
A(25) => \data_pipeline_tmp_reg[6]\(15),
A(24) => \data_pipeline_tmp_reg[6]\(15),
A(23) => \data_pipeline_tmp_reg[6]\(15),
A(22) => \data_pipeline_tmp_reg[6]\(15),
A(21) => \data_pipeline_tmp_reg[6]\(15),
A(20) => \data_pipeline_tmp_reg[6]\(15),
A(19) => \data_pipeline_tmp_reg[6]\(15),
A(18) => \data_pipeline_tmp_reg[6]\(15),
A(17) => \data_pipeline_tmp_reg[6]\(15),
A(16) => \data_pipeline_tmp_reg[6]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[6]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_6_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[6]_5\(15),
B(16) => \weight_reg[6]_5\(15),
B(15 downto 0) => \weight_reg[6]_5\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_6_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_6_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_6_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_6_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_6_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_6_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_6_n_74,
P(30) => mul_temp_6_n_75,
P(29) => mul_temp_6_n_76,
P(28) => mul_temp_6_n_77,
P(27) => mul_temp_6_n_78,
P(26) => mul_temp_6_n_79,
P(25) => mul_temp_6_n_80,
P(24) => mul_temp_6_n_81,
P(23) => mul_temp_6_n_82,
P(22) => mul_temp_6_n_83,
P(21) => mul_temp_6_n_84,
P(20) => mul_temp_6_n_85,
P(19) => mul_temp_6_n_86,
P(18) => mul_temp_6_n_87,
P(17) => mul_temp_6_n_88,
P(16) => mul_temp_6_n_89,
P(15) => mul_temp_6_n_90,
P(14) => \^mul_temp_6\(14),
P(13) => mul_temp_6_n_92,
P(12) => mul_temp_6_n_93,
P(11) => mul_temp_6_n_94,
P(10) => mul_temp_6_n_95,
P(9) => mul_temp_6_n_96,
P(8) => mul_temp_6_n_97,
P(7) => mul_temp_6_n_98,
P(6) => mul_temp_6_n_99,
P(5) => mul_temp_6_n_100,
P(4) => mul_temp_6_n_101,
P(3) => mul_temp_6_n_102,
P(2) => mul_temp_6_n_103,
P(1) => mul_temp_6_n_104,
P(0) => mul_temp_6_n_105,
PATTERNBDETECT => NLW_mul_temp_6_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_6_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_6_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_6_UNDERFLOW_UNCONNECTED
);
mul_temp_7: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[7]\(15),
A(28) => \data_pipeline_tmp_reg[7]\(15),
A(27) => \data_pipeline_tmp_reg[7]\(15),
A(26) => \data_pipeline_tmp_reg[7]\(15),
A(25) => \data_pipeline_tmp_reg[7]\(15),
A(24) => \data_pipeline_tmp_reg[7]\(15),
A(23) => \data_pipeline_tmp_reg[7]\(15),
A(22) => \data_pipeline_tmp_reg[7]\(15),
A(21) => \data_pipeline_tmp_reg[7]\(15),
A(20) => \data_pipeline_tmp_reg[7]\(15),
A(19) => \data_pipeline_tmp_reg[7]\(15),
A(18) => \data_pipeline_tmp_reg[7]\(15),
A(17) => \data_pipeline_tmp_reg[7]\(15),
A(16) => \data_pipeline_tmp_reg[7]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[7]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_7_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[7]_6\(15),
B(16) => \weight_reg[7]_6\(15),
B(15 downto 0) => \weight_reg[7]_6\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_7_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_7_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_7_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_7_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_7_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_7_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_7_n_74,
P(30) => mul_temp_7_n_75,
P(29) => mul_temp_7_n_76,
P(28) => mul_temp_7_n_77,
P(27) => mul_temp_7_n_78,
P(26) => mul_temp_7_n_79,
P(25) => mul_temp_7_n_80,
P(24) => mul_temp_7_n_81,
P(23) => mul_temp_7_n_82,
P(22) => mul_temp_7_n_83,
P(21) => mul_temp_7_n_84,
P(20) => mul_temp_7_n_85,
P(19) => mul_temp_7_n_86,
P(18) => mul_temp_7_n_87,
P(17) => mul_temp_7_n_88,
P(16) => mul_temp_7_n_89,
P(15) => mul_temp_7_n_90,
P(14) => \^mul_temp_7\(14),
P(13) => mul_temp_7_n_92,
P(12) => mul_temp_7_n_93,
P(11) => mul_temp_7_n_94,
P(10) => mul_temp_7_n_95,
P(9) => mul_temp_7_n_96,
P(8) => mul_temp_7_n_97,
P(7) => mul_temp_7_n_98,
P(6) => mul_temp_7_n_99,
P(5) => mul_temp_7_n_100,
P(4) => mul_temp_7_n_101,
P(3) => mul_temp_7_n_102,
P(2) => mul_temp_7_n_103,
P(1) => mul_temp_7_n_104,
P(0) => mul_temp_7_n_105,
PATTERNBDETECT => NLW_mul_temp_7_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_7_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_7_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_7_UNDERFLOW_UNCONNECTED
);
mul_temp_8: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[8]\(15),
A(28) => \data_pipeline_tmp_reg[8]\(15),
A(27) => \data_pipeline_tmp_reg[8]\(15),
A(26) => \data_pipeline_tmp_reg[8]\(15),
A(25) => \data_pipeline_tmp_reg[8]\(15),
A(24) => \data_pipeline_tmp_reg[8]\(15),
A(23) => \data_pipeline_tmp_reg[8]\(15),
A(22) => \data_pipeline_tmp_reg[8]\(15),
A(21) => \data_pipeline_tmp_reg[8]\(15),
A(20) => \data_pipeline_tmp_reg[8]\(15),
A(19) => \data_pipeline_tmp_reg[8]\(15),
A(18) => \data_pipeline_tmp_reg[8]\(15),
A(17) => \data_pipeline_tmp_reg[8]\(15),
A(16) => \data_pipeline_tmp_reg[8]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[8]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_8_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[8]_7\(15),
B(16) => \weight_reg[8]_7\(15),
B(15 downto 0) => \weight_reg[8]_7\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_8_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_8_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_8_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_8_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_8_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_8_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_8_n_74,
P(30) => mul_temp_8_n_75,
P(29) => mul_temp_8_n_76,
P(28) => mul_temp_8_n_77,
P(27) => mul_temp_8_n_78,
P(26) => mul_temp_8_n_79,
P(25) => mul_temp_8_n_80,
P(24) => mul_temp_8_n_81,
P(23) => mul_temp_8_n_82,
P(22) => mul_temp_8_n_83,
P(21) => mul_temp_8_n_84,
P(20) => mul_temp_8_n_85,
P(19) => mul_temp_8_n_86,
P(18) => mul_temp_8_n_87,
P(17) => mul_temp_8_n_88,
P(16) => mul_temp_8_n_89,
P(15) => mul_temp_8_n_90,
P(14) => \^mul_temp_8\(14),
P(13) => mul_temp_8_n_92,
P(12) => mul_temp_8_n_93,
P(11) => mul_temp_8_n_94,
P(10) => mul_temp_8_n_95,
P(9) => mul_temp_8_n_96,
P(8) => mul_temp_8_n_97,
P(7) => mul_temp_8_n_98,
P(6) => mul_temp_8_n_99,
P(5) => mul_temp_8_n_100,
P(4) => mul_temp_8_n_101,
P(3) => mul_temp_8_n_102,
P(2) => mul_temp_8_n_103,
P(1) => mul_temp_8_n_104,
P(0) => mul_temp_8_n_105,
PATTERNBDETECT => NLW_mul_temp_8_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_8_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_8_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_8_UNDERFLOW_UNCONNECTED
);
mul_temp_9: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[9]\(15),
A(28) => \data_pipeline_tmp_reg[9]\(15),
A(27) => \data_pipeline_tmp_reg[9]\(15),
A(26) => \data_pipeline_tmp_reg[9]\(15),
A(25) => \data_pipeline_tmp_reg[9]\(15),
A(24) => \data_pipeline_tmp_reg[9]\(15),
A(23) => \data_pipeline_tmp_reg[9]\(15),
A(22) => \data_pipeline_tmp_reg[9]\(15),
A(21) => \data_pipeline_tmp_reg[9]\(15),
A(20) => \data_pipeline_tmp_reg[9]\(15),
A(19) => \data_pipeline_tmp_reg[9]\(15),
A(18) => \data_pipeline_tmp_reg[9]\(15),
A(17) => \data_pipeline_tmp_reg[9]\(15),
A(16) => \data_pipeline_tmp_reg[9]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[9]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_9_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[9]_8\(15),
B(16) => \weight_reg[9]_8\(15),
B(15 downto 0) => \weight_reg[9]_8\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_9_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_9_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_9_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_9_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_9_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_9_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_9_n_74,
P(30) => mul_temp_9_n_75,
P(29) => mul_temp_9_n_76,
P(28) => mul_temp_9_n_77,
P(27) => mul_temp_9_n_78,
P(26) => mul_temp_9_n_79,
P(25) => mul_temp_9_n_80,
P(24) => mul_temp_9_n_81,
P(23) => mul_temp_9_n_82,
P(22) => mul_temp_9_n_83,
P(21) => mul_temp_9_n_84,
P(20) => mul_temp_9_n_85,
P(19) => mul_temp_9_n_86,
P(18) => mul_temp_9_n_87,
P(17) => mul_temp_9_n_88,
P(16) => mul_temp_9_n_89,
P(15) => mul_temp_9_n_90,
P(14) => \^mul_temp_9\(14),
P(13) => mul_temp_9_n_92,
P(12) => mul_temp_9_n_93,
P(11) => mul_temp_9_n_94,
P(10) => mul_temp_9_n_95,
P(9) => mul_temp_9_n_96,
P(8) => mul_temp_9_n_97,
P(7) => mul_temp_9_n_98,
P(6) => mul_temp_9_n_99,
P(5) => mul_temp_9_n_100,
P(4) => mul_temp_9_n_101,
P(3) => mul_temp_9_n_102,
P(2) => mul_temp_9_n_103,
P(1) => mul_temp_9_n_104,
P(0) => mul_temp_9_n_105,
PATTERNBDETECT => NLW_mul_temp_9_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_9_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_9_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_9_UNDERFLOW_UNCONNECTED
);
sub_temp_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => sub_temp_carry_n_0,
CO(2) => sub_temp_carry_n_1,
CO(1) => sub_temp_carry_n_2,
CO(0) => sub_temp_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => Q(3 downto 0),
O(3 downto 0) => \^mul_temp_16\(3 downto 0),
S(3 downto 0) => \write_reg_d_k_reg[3]_0\(3 downto 0)
);
\sub_temp_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => sub_temp_carry_n_0,
CO(3) => \sub_temp_carry__0_n_0\,
CO(2) => \sub_temp_carry__0_n_1\,
CO(1) => \sub_temp_carry__0_n_2\,
CO(0) => \sub_temp_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => Q(7 downto 4),
O(3 downto 0) => \^mul_temp_16\(7 downto 4),
S(3 downto 0) => \write_reg_d_k_reg[7]\(3 downto 0)
);
\sub_temp_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \sub_temp_carry__0_n_0\,
CO(3) => \sub_temp_carry__1_n_0\,
CO(2) => \sub_temp_carry__1_n_1\,
CO(1) => \sub_temp_carry__1_n_2\,
CO(0) => \sub_temp_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => Q(11 downto 8),
O(3 downto 0) => \^mul_temp_16\(11 downto 8),
S(3 downto 0) => \write_reg_d_k_reg[11]\(3 downto 0)
);
\sub_temp_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \sub_temp_carry__1_n_0\,
CO(3) => \NLW_sub_temp_carry__2_CO_UNCONNECTED\(3),
CO(2) => \sub_temp_carry__2_n_1\,
CO(1) => \sub_temp_carry__2_n_2\,
CO(0) => \sub_temp_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => Q(14 downto 12),
O(3 downto 0) => \^mul_temp_16\(15 downto 12),
S(3 downto 0) => S(3 downto 0)
);
\weight[0][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_88\,
I1 => \weight_reg[0]_15\(3),
O => \weight[0][0]_i_2_n_0\
);
\weight[0][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_89\,
I1 => \weight_reg[0]_15\(2),
O => \weight[0][0]_i_3_n_0\
);
\weight[0][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_90\,
I1 => \weight_reg[0]_15\(1),
O => \weight[0][0]_i_4_n_0\
);
\weight[0][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_91\,
I1 => \weight_reg[0]_15\(0),
O => \weight[0][0]_i_5_n_0\
);
\weight[0][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_76\,
I1 => \weight_reg[0]_15\(15),
O => \weight[0][12]_i_2_n_0\
);
\weight[0][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_77\,
I1 => \weight_reg[0]_15\(14),
O => \weight[0][12]_i_3_n_0\
);
\weight[0][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_78\,
I1 => \weight_reg[0]_15\(13),
O => \weight[0][12]_i_4_n_0\
);
\weight[0][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_79\,
I1 => \weight_reg[0]_15\(12),
O => \weight[0][12]_i_5_n_0\
);
\weight[0][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_84\,
I1 => \weight_reg[0]_15\(7),
O => \weight[0][4]_i_2_n_0\
);
\weight[0][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_85\,
I1 => \weight_reg[0]_15\(6),
O => \weight[0][4]_i_3_n_0\
);
\weight[0][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_86\,
I1 => \weight_reg[0]_15\(5),
O => \weight[0][4]_i_4_n_0\
);
\weight[0][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_87\,
I1 => \weight_reg[0]_15\(4),
O => \weight[0][4]_i_5_n_0\
);
\weight[0][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_80\,
I1 => \weight_reg[0]_15\(11),
O => \weight[0][8]_i_2_n_0\
);
\weight[0][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_81\,
I1 => \weight_reg[0]_15\(10),
O => \weight[0][8]_i_3_n_0\
);
\weight[0][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_82\,
I1 => \weight_reg[0]_15\(9),
O => \weight[0][8]_i_4_n_0\
);
\weight[0][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_83\,
I1 => \weight_reg[0]_15\(8),
O => \weight[0][8]_i_5_n_0\
);
\weight[10][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_88\,
I1 => \weight_reg[10]_9\(3),
O => \weight[10][0]_i_2_n_0\
);
\weight[10][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_89\,
I1 => \weight_reg[10]_9\(2),
O => \weight[10][0]_i_3_n_0\
);
\weight[10][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_90\,
I1 => \weight_reg[10]_9\(1),
O => \weight[10][0]_i_4_n_0\
);
\weight[10][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_91\,
I1 => \weight_reg[10]_9\(0),
O => \weight[10][0]_i_5_n_0\
);
\weight[10][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_76\,
I1 => \weight_reg[10]_9\(15),
O => \weight[10][12]_i_2_n_0\
);
\weight[10][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_77\,
I1 => \weight_reg[10]_9\(14),
O => \weight[10][12]_i_3_n_0\
);
\weight[10][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_78\,
I1 => \weight_reg[10]_9\(13),
O => \weight[10][12]_i_4_n_0\
);
\weight[10][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_79\,
I1 => \weight_reg[10]_9\(12),
O => \weight[10][12]_i_5_n_0\
);
\weight[10][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_84\,
I1 => \weight_reg[10]_9\(7),
O => \weight[10][4]_i_2_n_0\
);
\weight[10][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_85\,
I1 => \weight_reg[10]_9\(6),
O => \weight[10][4]_i_3_n_0\
);
\weight[10][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_86\,
I1 => \weight_reg[10]_9\(5),
O => \weight[10][4]_i_4_n_0\
);
\weight[10][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_87\,
I1 => \weight_reg[10]_9\(4),
O => \weight[10][4]_i_5_n_0\
);
\weight[10][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_80\,
I1 => \weight_reg[10]_9\(11),
O => \weight[10][8]_i_2_n_0\
);
\weight[10][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_81\,
I1 => \weight_reg[10]_9\(10),
O => \weight[10][8]_i_3_n_0\
);
\weight[10][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_82\,
I1 => \weight_reg[10]_9\(9),
O => \weight[10][8]_i_4_n_0\
);
\weight[10][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_83\,
I1 => \weight_reg[10]_9\(8),
O => \weight[10][8]_i_5_n_0\
);
\weight[11][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_88\,
I1 => \weight_reg[11]_10\(3),
O => \weight[11][0]_i_2_n_0\
);
\weight[11][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_89\,
I1 => \weight_reg[11]_10\(2),
O => \weight[11][0]_i_3_n_0\
);
\weight[11][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_90\,
I1 => \weight_reg[11]_10\(1),
O => \weight[11][0]_i_4_n_0\
);
\weight[11][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_91\,
I1 => \weight_reg[11]_10\(0),
O => \weight[11][0]_i_5_n_0\
);
\weight[11][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_76\,
I1 => \weight_reg[11]_10\(15),
O => \weight[11][12]_i_2_n_0\
);
\weight[11][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_77\,
I1 => \weight_reg[11]_10\(14),
O => \weight[11][12]_i_3_n_0\
);
\weight[11][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_78\,
I1 => \weight_reg[11]_10\(13),
O => \weight[11][12]_i_4_n_0\
);
\weight[11][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_79\,
I1 => \weight_reg[11]_10\(12),
O => \weight[11][12]_i_5_n_0\
);
\weight[11][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_84\,
I1 => \weight_reg[11]_10\(7),
O => \weight[11][4]_i_2_n_0\
);
\weight[11][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_85\,
I1 => \weight_reg[11]_10\(6),
O => \weight[11][4]_i_3_n_0\
);
\weight[11][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_86\,
I1 => \weight_reg[11]_10\(5),
O => \weight[11][4]_i_4_n_0\
);
\weight[11][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_87\,
I1 => \weight_reg[11]_10\(4),
O => \weight[11][4]_i_5_n_0\
);
\weight[11][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_80\,
I1 => \weight_reg[11]_10\(11),
O => \weight[11][8]_i_2_n_0\
);
\weight[11][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_81\,
I1 => \weight_reg[11]_10\(10),
O => \weight[11][8]_i_3_n_0\
);
\weight[11][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_82\,
I1 => \weight_reg[11]_10\(9),
O => \weight[11][8]_i_4_n_0\
);
\weight[11][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_83\,
I1 => \weight_reg[11]_10\(8),
O => \weight[11][8]_i_5_n_0\
);
\weight[12][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_88\,
I1 => \weight_reg[12]_11\(3),
O => \weight[12][0]_i_2_n_0\
);
\weight[12][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_89\,
I1 => \weight_reg[12]_11\(2),
O => \weight[12][0]_i_3_n_0\
);
\weight[12][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_90\,
I1 => \weight_reg[12]_11\(1),
O => \weight[12][0]_i_4_n_0\
);
\weight[12][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_91\,
I1 => \weight_reg[12]_11\(0),
O => \weight[12][0]_i_5_n_0\
);
\weight[12][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_76\,
I1 => \weight_reg[12]_11\(15),
O => \weight[12][12]_i_2_n_0\
);
\weight[12][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_77\,
I1 => \weight_reg[12]_11\(14),
O => \weight[12][12]_i_3_n_0\
);
\weight[12][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_78\,
I1 => \weight_reg[12]_11\(13),
O => \weight[12][12]_i_4_n_0\
);
\weight[12][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_79\,
I1 => \weight_reg[12]_11\(12),
O => \weight[12][12]_i_5_n_0\
);
\weight[12][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_84\,
I1 => \weight_reg[12]_11\(7),
O => \weight[12][4]_i_2_n_0\
);
\weight[12][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_85\,
I1 => \weight_reg[12]_11\(6),
O => \weight[12][4]_i_3_n_0\
);
\weight[12][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_86\,
I1 => \weight_reg[12]_11\(5),
O => \weight[12][4]_i_4_n_0\
);
\weight[12][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_87\,
I1 => \weight_reg[12]_11\(4),
O => \weight[12][4]_i_5_n_0\
);
\weight[12][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_80\,
I1 => \weight_reg[12]_11\(11),
O => \weight[12][8]_i_2_n_0\
);
\weight[12][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_81\,
I1 => \weight_reg[12]_11\(10),
O => \weight[12][8]_i_3_n_0\
);
\weight[12][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_82\,
I1 => \weight_reg[12]_11\(9),
O => \weight[12][8]_i_4_n_0\
);
\weight[12][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_83\,
I1 => \weight_reg[12]_11\(8),
O => \weight[12][8]_i_5_n_0\
);
\weight[13][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_88\,
I1 => \weight_reg[13]_12\(3),
O => \weight[13][0]_i_2_n_0\
);
\weight[13][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_89\,
I1 => \weight_reg[13]_12\(2),
O => \weight[13][0]_i_3_n_0\
);
\weight[13][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_90\,
I1 => \weight_reg[13]_12\(1),
O => \weight[13][0]_i_4_n_0\
);
\weight[13][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_91\,
I1 => \weight_reg[13]_12\(0),
O => \weight[13][0]_i_5_n_0\
);
\weight[13][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_76\,
I1 => \weight_reg[13]_12\(15),
O => \weight[13][12]_i_2_n_0\
);
\weight[13][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_77\,
I1 => \weight_reg[13]_12\(14),
O => \weight[13][12]_i_3_n_0\
);
\weight[13][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_78\,
I1 => \weight_reg[13]_12\(13),
O => \weight[13][12]_i_4_n_0\
);
\weight[13][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_79\,
I1 => \weight_reg[13]_12\(12),
O => \weight[13][12]_i_5_n_0\
);
\weight[13][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_84\,
I1 => \weight_reg[13]_12\(7),
O => \weight[13][4]_i_2_n_0\
);
\weight[13][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_85\,
I1 => \weight_reg[13]_12\(6),
O => \weight[13][4]_i_3_n_0\
);
\weight[13][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_86\,
I1 => \weight_reg[13]_12\(5),
O => \weight[13][4]_i_4_n_0\
);
\weight[13][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_87\,
I1 => \weight_reg[13]_12\(4),
O => \weight[13][4]_i_5_n_0\
);
\weight[13][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_80\,
I1 => \weight_reg[13]_12\(11),
O => \weight[13][8]_i_2_n_0\
);
\weight[13][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_81\,
I1 => \weight_reg[13]_12\(10),
O => \weight[13][8]_i_3_n_0\
);
\weight[13][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_82\,
I1 => \weight_reg[13]_12\(9),
O => \weight[13][8]_i_4_n_0\
);
\weight[13][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_83\,
I1 => \weight_reg[13]_12\(8),
O => \weight[13][8]_i_5_n_0\
);
\weight[14][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_88\,
I1 => \weight_reg[14]_13\(3),
O => \weight[14][0]_i_2_n_0\
);
\weight[14][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_89\,
I1 => \weight_reg[14]_13\(2),
O => \weight[14][0]_i_3_n_0\
);
\weight[14][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_90\,
I1 => \weight_reg[14]_13\(1),
O => \weight[14][0]_i_4_n_0\
);
\weight[14][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_91\,
I1 => \weight_reg[14]_13\(0),
O => \weight[14][0]_i_5_n_0\
);
\weight[14][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_76\,
I1 => \weight_reg[14]_13\(15),
O => \weight[14][12]_i_2_n_0\
);
\weight[14][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_77\,
I1 => \weight_reg[14]_13\(14),
O => \weight[14][12]_i_3_n_0\
);
\weight[14][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_78\,
I1 => \weight_reg[14]_13\(13),
O => \weight[14][12]_i_4_n_0\
);
\weight[14][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_79\,
I1 => \weight_reg[14]_13\(12),
O => \weight[14][12]_i_5_n_0\
);
\weight[14][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_84\,
I1 => \weight_reg[14]_13\(7),
O => \weight[14][4]_i_2_n_0\
);
\weight[14][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_85\,
I1 => \weight_reg[14]_13\(6),
O => \weight[14][4]_i_3_n_0\
);
\weight[14][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_86\,
I1 => \weight_reg[14]_13\(5),
O => \weight[14][4]_i_4_n_0\
);
\weight[14][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_87\,
I1 => \weight_reg[14]_13\(4),
O => \weight[14][4]_i_5_n_0\
);
\weight[14][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_80\,
I1 => \weight_reg[14]_13\(11),
O => \weight[14][8]_i_2_n_0\
);
\weight[14][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_81\,
I1 => \weight_reg[14]_13\(10),
O => \weight[14][8]_i_3_n_0\
);
\weight[14][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_82\,
I1 => \weight_reg[14]_13\(9),
O => \weight[14][8]_i_4_n_0\
);
\weight[14][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_83\,
I1 => \weight_reg[14]_13\(8),
O => \weight[14][8]_i_5_n_0\
);
\weight[15][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_88\,
I1 => \weight_reg[15]_14\(3),
O => \weight[15][0]_i_2_n_0\
);
\weight[15][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_89\,
I1 => \weight_reg[15]_14\(2),
O => \weight[15][0]_i_3_n_0\
);
\weight[15][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_90\,
I1 => \weight_reg[15]_14\(1),
O => \weight[15][0]_i_4_n_0\
);
\weight[15][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_91\,
I1 => \weight_reg[15]_14\(0),
O => \weight[15][0]_i_5_n_0\
);
\weight[15][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_76\,
I1 => \weight_reg[15]_14\(15),
O => \weight[15][12]_i_2_n_0\
);
\weight[15][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_77\,
I1 => \weight_reg[15]_14\(14),
O => \weight[15][12]_i_3_n_0\
);
\weight[15][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_78\,
I1 => \weight_reg[15]_14\(13),
O => \weight[15][12]_i_4_n_0\
);
\weight[15][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_79\,
I1 => \weight_reg[15]_14\(12),
O => \weight[15][12]_i_5_n_0\
);
\weight[15][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_84\,
I1 => \weight_reg[15]_14\(7),
O => \weight[15][4]_i_2_n_0\
);
\weight[15][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_85\,
I1 => \weight_reg[15]_14\(6),
O => \weight[15][4]_i_3_n_0\
);
\weight[15][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_86\,
I1 => \weight_reg[15]_14\(5),
O => \weight[15][4]_i_4_n_0\
);
\weight[15][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_87\,
I1 => \weight_reg[15]_14\(4),
O => \weight[15][4]_i_5_n_0\
);
\weight[15][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_80\,
I1 => \weight_reg[15]_14\(11),
O => \weight[15][8]_i_2_n_0\
);
\weight[15][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_81\,
I1 => \weight_reg[15]_14\(10),
O => \weight[15][8]_i_3_n_0\
);
\weight[15][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_82\,
I1 => \weight_reg[15]_14\(9),
O => \weight[15][8]_i_4_n_0\
);
\weight[15][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_83\,
I1 => \weight_reg[15]_14\(8),
O => \weight[15][8]_i_5_n_0\
);
\weight[1][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(3),
I1 => \weight_reg[1]_0\(3),
O => \weight[1][0]_i_2_n_0\
);
\weight[1][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(2),
I1 => \weight_reg[1]_0\(2),
O => \weight[1][0]_i_3_n_0\
);
\weight[1][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(1),
I1 => \weight_reg[1]_0\(1),
O => \weight[1][0]_i_4_n_0\
);
\weight[1][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(0),
I1 => \weight_reg[1]_0\(0),
O => \weight[1][0]_i_5_n_0\
);
\weight[1][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(15),
I1 => \weight_reg[1]_0\(15),
O => \weight[1][12]_i_2_n_0\
);
\weight[1][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(14),
I1 => \weight_reg[1]_0\(14),
O => \weight[1][12]_i_3_n_0\
);
\weight[1][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(13),
I1 => \weight_reg[1]_0\(13),
O => \weight[1][12]_i_4_n_0\
);
\weight[1][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(12),
I1 => \weight_reg[1]_0\(12),
O => \weight[1][12]_i_5_n_0\
);
\weight[1][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(7),
I1 => \weight_reg[1]_0\(7),
O => \weight[1][4]_i_2_n_0\
);
\weight[1][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(6),
I1 => \weight_reg[1]_0\(6),
O => \weight[1][4]_i_3_n_0\
);
\weight[1][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(5),
I1 => \weight_reg[1]_0\(5),
O => \weight[1][4]_i_4_n_0\
);
\weight[1][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(4),
I1 => \weight_reg[1]_0\(4),
O => \weight[1][4]_i_5_n_0\
);
\weight[1][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(11),
I1 => \weight_reg[1]_0\(11),
O => \weight[1][8]_i_2_n_0\
);
\weight[1][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(10),
I1 => \weight_reg[1]_0\(10),
O => \weight[1][8]_i_3_n_0\
);
\weight[1][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(9),
I1 => \weight_reg[1]_0\(9),
O => \weight[1][8]_i_4_n_0\
);
\weight[1][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(8),
I1 => \weight_reg[1]_0\(8),
O => \weight[1][8]_i_5_n_0\
);
\weight[2][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_88\,
I1 => \weight_reg[2]_1\(3),
O => \weight[2][0]_i_2_n_0\
);
\weight[2][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_89\,
I1 => \weight_reg[2]_1\(2),
O => \weight[2][0]_i_3_n_0\
);
\weight[2][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_90\,
I1 => \weight_reg[2]_1\(1),
O => \weight[2][0]_i_4_n_0\
);
\weight[2][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_91\,
I1 => \weight_reg[2]_1\(0),
O => \weight[2][0]_i_5_n_0\
);
\weight[2][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_76\,
I1 => \weight_reg[2]_1\(15),
O => \weight[2][12]_i_2_n_0\
);
\weight[2][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_77\,
I1 => \weight_reg[2]_1\(14),
O => \weight[2][12]_i_3_n_0\
);
\weight[2][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_78\,
I1 => \weight_reg[2]_1\(13),
O => \weight[2][12]_i_4_n_0\
);
\weight[2][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_79\,
I1 => \weight_reg[2]_1\(12),
O => \weight[2][12]_i_5_n_0\
);
\weight[2][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_84\,
I1 => \weight_reg[2]_1\(7),
O => \weight[2][4]_i_2_n_0\
);
\weight[2][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_85\,
I1 => \weight_reg[2]_1\(6),
O => \weight[2][4]_i_3_n_0\
);
\weight[2][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_86\,
I1 => \weight_reg[2]_1\(5),
O => \weight[2][4]_i_4_n_0\
);
\weight[2][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_87\,
I1 => \weight_reg[2]_1\(4),
O => \weight[2][4]_i_5_n_0\
);
\weight[2][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_80\,
I1 => \weight_reg[2]_1\(11),
O => \weight[2][8]_i_2_n_0\
);
\weight[2][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_81\,
I1 => \weight_reg[2]_1\(10),
O => \weight[2][8]_i_3_n_0\
);
\weight[2][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_82\,
I1 => \weight_reg[2]_1\(9),
O => \weight[2][8]_i_4_n_0\
);
\weight[2][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_83\,
I1 => \weight_reg[2]_1\(8),
O => \weight[2][8]_i_5_n_0\
);
\weight[3][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_88\,
I1 => \weight_reg[3]_2\(3),
O => \weight[3][0]_i_2_n_0\
);
\weight[3][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_89\,
I1 => \weight_reg[3]_2\(2),
O => \weight[3][0]_i_3_n_0\
);
\weight[3][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_90\,
I1 => \weight_reg[3]_2\(1),
O => \weight[3][0]_i_4_n_0\
);
\weight[3][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_91\,
I1 => \weight_reg[3]_2\(0),
O => \weight[3][0]_i_5_n_0\
);
\weight[3][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_76\,
I1 => \weight_reg[3]_2\(15),
O => \weight[3][12]_i_2_n_0\
);
\weight[3][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_77\,
I1 => \weight_reg[3]_2\(14),
O => \weight[3][12]_i_3_n_0\
);
\weight[3][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_78\,
I1 => \weight_reg[3]_2\(13),
O => \weight[3][12]_i_4_n_0\
);
\weight[3][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_79\,
I1 => \weight_reg[3]_2\(12),
O => \weight[3][12]_i_5_n_0\
);
\weight[3][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_84\,
I1 => \weight_reg[3]_2\(7),
O => \weight[3][4]_i_2_n_0\
);
\weight[3][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_85\,
I1 => \weight_reg[3]_2\(6),
O => \weight[3][4]_i_3_n_0\
);
\weight[3][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_86\,
I1 => \weight_reg[3]_2\(5),
O => \weight[3][4]_i_4_n_0\
);
\weight[3][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_87\,
I1 => \weight_reg[3]_2\(4),
O => \weight[3][4]_i_5_n_0\
);
\weight[3][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_80\,
I1 => \weight_reg[3]_2\(11),
O => \weight[3][8]_i_2_n_0\
);
\weight[3][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_81\,
I1 => \weight_reg[3]_2\(10),
O => \weight[3][8]_i_3_n_0\
);
\weight[3][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_82\,
I1 => \weight_reg[3]_2\(9),
O => \weight[3][8]_i_4_n_0\
);
\weight[3][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_83\,
I1 => \weight_reg[3]_2\(8),
O => \weight[3][8]_i_5_n_0\
);
\weight[4][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_88\,
I1 => \weight_reg[4]_3\(3),
O => \weight[4][0]_i_2_n_0\
);
\weight[4][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_89\,
I1 => \weight_reg[4]_3\(2),
O => \weight[4][0]_i_3_n_0\
);
\weight[4][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_90\,
I1 => \weight_reg[4]_3\(1),
O => \weight[4][0]_i_4_n_0\
);
\weight[4][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_91\,
I1 => \weight_reg[4]_3\(0),
O => \weight[4][0]_i_5_n_0\
);
\weight[4][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_76\,
I1 => \weight_reg[4]_3\(15),
O => \weight[4][12]_i_2_n_0\
);
\weight[4][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_77\,
I1 => \weight_reg[4]_3\(14),
O => \weight[4][12]_i_3_n_0\
);
\weight[4][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_78\,
I1 => \weight_reg[4]_3\(13),
O => \weight[4][12]_i_4_n_0\
);
\weight[4][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_79\,
I1 => \weight_reg[4]_3\(12),
O => \weight[4][12]_i_5_n_0\
);
\weight[4][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_84\,
I1 => \weight_reg[4]_3\(7),
O => \weight[4][4]_i_2_n_0\
);
\weight[4][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_85\,
I1 => \weight_reg[4]_3\(6),
O => \weight[4][4]_i_3_n_0\
);
\weight[4][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_86\,
I1 => \weight_reg[4]_3\(5),
O => \weight[4][4]_i_4_n_0\
);
\weight[4][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_87\,
I1 => \weight_reg[4]_3\(4),
O => \weight[4][4]_i_5_n_0\
);
\weight[4][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_80\,
I1 => \weight_reg[4]_3\(11),
O => \weight[4][8]_i_2_n_0\
);
\weight[4][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_81\,
I1 => \weight_reg[4]_3\(10),
O => \weight[4][8]_i_3_n_0\
);
\weight[4][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_82\,
I1 => \weight_reg[4]_3\(9),
O => \weight[4][8]_i_4_n_0\
);
\weight[4][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_83\,
I1 => \weight_reg[4]_3\(8),
O => \weight[4][8]_i_5_n_0\
);
\weight[5][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_88\,
I1 => \weight_reg[5]_4\(3),
O => \weight[5][0]_i_2_n_0\
);
\weight[5][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_89\,
I1 => \weight_reg[5]_4\(2),
O => \weight[5][0]_i_3_n_0\
);
\weight[5][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_90\,
I1 => \weight_reg[5]_4\(1),
O => \weight[5][0]_i_4_n_0\
);
\weight[5][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_91\,
I1 => \weight_reg[5]_4\(0),
O => \weight[5][0]_i_5_n_0\
);
\weight[5][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_76\,
I1 => \weight_reg[5]_4\(15),
O => \weight[5][12]_i_2_n_0\
);
\weight[5][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_77\,
I1 => \weight_reg[5]_4\(14),
O => \weight[5][12]_i_3_n_0\
);
\weight[5][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_78\,
I1 => \weight_reg[5]_4\(13),
O => \weight[5][12]_i_4_n_0\
);
\weight[5][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_79\,
I1 => \weight_reg[5]_4\(12),
O => \weight[5][12]_i_5_n_0\
);
\weight[5][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_84\,
I1 => \weight_reg[5]_4\(7),
O => \weight[5][4]_i_2_n_0\
);
\weight[5][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_85\,
I1 => \weight_reg[5]_4\(6),
O => \weight[5][4]_i_3_n_0\
);
\weight[5][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_86\,
I1 => \weight_reg[5]_4\(5),
O => \weight[5][4]_i_4_n_0\
);
\weight[5][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_87\,
I1 => \weight_reg[5]_4\(4),
O => \weight[5][4]_i_5_n_0\
);
\weight[5][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_80\,
I1 => \weight_reg[5]_4\(11),
O => \weight[5][8]_i_2_n_0\
);
\weight[5][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_81\,
I1 => \weight_reg[5]_4\(10),
O => \weight[5][8]_i_3_n_0\
);
\weight[5][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_82\,
I1 => \weight_reg[5]_4\(9),
O => \weight[5][8]_i_4_n_0\
);
\weight[5][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_83\,
I1 => \weight_reg[5]_4\(8),
O => \weight[5][8]_i_5_n_0\
);
\weight[6][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_88\,
I1 => \weight_reg[6]_5\(3),
O => \weight[6][0]_i_2_n_0\
);
\weight[6][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_89\,
I1 => \weight_reg[6]_5\(2),
O => \weight[6][0]_i_3_n_0\
);
\weight[6][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_90\,
I1 => \weight_reg[6]_5\(1),
O => \weight[6][0]_i_4_n_0\
);
\weight[6][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_91\,
I1 => \weight_reg[6]_5\(0),
O => \weight[6][0]_i_5_n_0\
);
\weight[6][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_76\,
I1 => \weight_reg[6]_5\(15),
O => \weight[6][12]_i_2_n_0\
);
\weight[6][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_77\,
I1 => \weight_reg[6]_5\(14),
O => \weight[6][12]_i_3_n_0\
);
\weight[6][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_78\,
I1 => \weight_reg[6]_5\(13),
O => \weight[6][12]_i_4_n_0\
);
\weight[6][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_79\,
I1 => \weight_reg[6]_5\(12),
O => \weight[6][12]_i_5_n_0\
);
\weight[6][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_84\,
I1 => \weight_reg[6]_5\(7),
O => \weight[6][4]_i_2_n_0\
);
\weight[6][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_85\,
I1 => \weight_reg[6]_5\(6),
O => \weight[6][4]_i_3_n_0\
);
\weight[6][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_86\,
I1 => \weight_reg[6]_5\(5),
O => \weight[6][4]_i_4_n_0\
);
\weight[6][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_87\,
I1 => \weight_reg[6]_5\(4),
O => \weight[6][4]_i_5_n_0\
);
\weight[6][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_80\,
I1 => \weight_reg[6]_5\(11),
O => \weight[6][8]_i_2_n_0\
);
\weight[6][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_81\,
I1 => \weight_reg[6]_5\(10),
O => \weight[6][8]_i_3_n_0\
);
\weight[6][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_82\,
I1 => \weight_reg[6]_5\(9),
O => \weight[6][8]_i_4_n_0\
);
\weight[6][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_83\,
I1 => \weight_reg[6]_5\(8),
O => \weight[6][8]_i_5_n_0\
);
\weight[7][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_88\,
I1 => \weight_reg[7]_6\(3),
O => \weight[7][0]_i_2_n_0\
);
\weight[7][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_89\,
I1 => \weight_reg[7]_6\(2),
O => \weight[7][0]_i_3_n_0\
);
\weight[7][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_90\,
I1 => \weight_reg[7]_6\(1),
O => \weight[7][0]_i_4_n_0\
);
\weight[7][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_91\,
I1 => \weight_reg[7]_6\(0),
O => \weight[7][0]_i_5_n_0\
);
\weight[7][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_76\,
I1 => \weight_reg[7]_6\(15),
O => \weight[7][12]_i_2_n_0\
);
\weight[7][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_77\,
I1 => \weight_reg[7]_6\(14),
O => \weight[7][12]_i_3_n_0\
);
\weight[7][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_78\,
I1 => \weight_reg[7]_6\(13),
O => \weight[7][12]_i_4_n_0\
);
\weight[7][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_79\,
I1 => \weight_reg[7]_6\(12),
O => \weight[7][12]_i_5_n_0\
);
\weight[7][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_84\,
I1 => \weight_reg[7]_6\(7),
O => \weight[7][4]_i_2_n_0\
);
\weight[7][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_85\,
I1 => \weight_reg[7]_6\(6),
O => \weight[7][4]_i_3_n_0\
);
\weight[7][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_86\,
I1 => \weight_reg[7]_6\(5),
O => \weight[7][4]_i_4_n_0\
);
\weight[7][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_87\,
I1 => \weight_reg[7]_6\(4),
O => \weight[7][4]_i_5_n_0\
);
\weight[7][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_80\,
I1 => \weight_reg[7]_6\(11),
O => \weight[7][8]_i_2_n_0\
);
\weight[7][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_81\,
I1 => \weight_reg[7]_6\(10),
O => \weight[7][8]_i_3_n_0\
);
\weight[7][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_82\,
I1 => \weight_reg[7]_6\(9),
O => \weight[7][8]_i_4_n_0\
);
\weight[7][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_83\,
I1 => \weight_reg[7]_6\(8),
O => \weight[7][8]_i_5_n_0\
);
\weight[8][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_88\,
I1 => \weight_reg[8]_7\(3),
O => \weight[8][0]_i_2_n_0\
);
\weight[8][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_89\,
I1 => \weight_reg[8]_7\(2),
O => \weight[8][0]_i_3_n_0\
);
\weight[8][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_90\,
I1 => \weight_reg[8]_7\(1),
O => \weight[8][0]_i_4_n_0\
);
\weight[8][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_91\,
I1 => \weight_reg[8]_7\(0),
O => \weight[8][0]_i_5_n_0\
);
\weight[8][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_76\,
I1 => \weight_reg[8]_7\(15),
O => \weight[8][12]_i_2_n_0\
);
\weight[8][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_77\,
I1 => \weight_reg[8]_7\(14),
O => \weight[8][12]_i_3_n_0\
);
\weight[8][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_78\,
I1 => \weight_reg[8]_7\(13),
O => \weight[8][12]_i_4_n_0\
);
\weight[8][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_79\,
I1 => \weight_reg[8]_7\(12),
O => \weight[8][12]_i_5_n_0\
);
\weight[8][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_84\,
I1 => \weight_reg[8]_7\(7),
O => \weight[8][4]_i_2_n_0\
);
\weight[8][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_85\,
I1 => \weight_reg[8]_7\(6),
O => \weight[8][4]_i_3_n_0\
);
\weight[8][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_86\,
I1 => \weight_reg[8]_7\(5),
O => \weight[8][4]_i_4_n_0\
);
\weight[8][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_87\,
I1 => \weight_reg[8]_7\(4),
O => \weight[8][4]_i_5_n_0\
);
\weight[8][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_80\,
I1 => \weight_reg[8]_7\(11),
O => \weight[8][8]_i_2_n_0\
);
\weight[8][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_81\,
I1 => \weight_reg[8]_7\(10),
O => \weight[8][8]_i_3_n_0\
);
\weight[8][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_82\,
I1 => \weight_reg[8]_7\(9),
O => \weight[8][8]_i_4_n_0\
);
\weight[8][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_83\,
I1 => \weight_reg[8]_7\(8),
O => \weight[8][8]_i_5_n_0\
);
\weight[9][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_88\,
I1 => \weight_reg[9]_8\(3),
O => \weight[9][0]_i_2_n_0\
);
\weight[9][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_89\,
I1 => \weight_reg[9]_8\(2),
O => \weight[9][0]_i_3_n_0\
);
\weight[9][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_90\,
I1 => \weight_reg[9]_8\(1),
O => \weight[9][0]_i_4_n_0\
);
\weight[9][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_91\,
I1 => \weight_reg[9]_8\(0),
O => \weight[9][0]_i_5_n_0\
);
\weight[9][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_76\,
I1 => \weight_reg[9]_8\(15),
O => \weight[9][12]_i_2_n_0\
);
\weight[9][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_77\,
I1 => \weight_reg[9]_8\(14),
O => \weight[9][12]_i_3_n_0\
);
\weight[9][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_78\,
I1 => \weight_reg[9]_8\(13),
O => \weight[9][12]_i_4_n_0\
);
\weight[9][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_79\,
I1 => \weight_reg[9]_8\(12),
O => \weight[9][12]_i_5_n_0\
);
\weight[9][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_84\,
I1 => \weight_reg[9]_8\(7),
O => \weight[9][4]_i_2_n_0\
);
\weight[9][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_85\,
I1 => \weight_reg[9]_8\(6),
O => \weight[9][4]_i_3_n_0\
);
\weight[9][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_86\,
I1 => \weight_reg[9]_8\(5),
O => \weight[9][4]_i_4_n_0\
);
\weight[9][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_87\,
I1 => \weight_reg[9]_8\(4),
O => \weight[9][4]_i_5_n_0\
);
\weight[9][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_80\,
I1 => \weight_reg[9]_8\(11),
O => \weight[9][8]_i_2_n_0\
);
\weight[9][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_81\,
I1 => \weight_reg[9]_8\(10),
O => \weight[9][8]_i_3_n_0\
);
\weight[9][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_82\,
I1 => \weight_reg[9]_8\(9),
O => \weight[9][8]_i_4_n_0\
);
\weight[9][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_83\,
I1 => \weight_reg[9]_8\(8),
O => \weight[9][8]_i_5_n_0\
);
\weight_reg[0][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][0]_i_1_n_7\,
Q => \weight_reg[0]_15\(0)
);
\weight_reg[0][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[0][0]_i_1_n_0\,
CO(2) => \weight_reg[0][0]_i_1_n_1\,
CO(1) => \weight_reg[0][0]_i_1_n_2\,
CO(0) => \weight_reg[0][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__29_n_88\,
DI(2) => \ARG__29_n_89\,
DI(1) => \ARG__29_n_90\,
DI(0) => \ARG__29_n_91\,
O(3) => \weight_reg[0][0]_i_1_n_4\,
O(2) => \weight_reg[0][0]_i_1_n_5\,
O(1) => \weight_reg[0][0]_i_1_n_6\,
O(0) => \weight_reg[0][0]_i_1_n_7\,
S(3) => \weight[0][0]_i_2_n_0\,
S(2) => \weight[0][0]_i_3_n_0\,
S(1) => \weight[0][0]_i_4_n_0\,
S(0) => \weight[0][0]_i_5_n_0\
);
\weight_reg[0][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][8]_i_1_n_5\,
Q => \weight_reg[0]_15\(10)
);
\weight_reg[0][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][8]_i_1_n_4\,
Q => \weight_reg[0]_15\(11)
);
\weight_reg[0][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][12]_i_1_n_7\,
Q => \weight_reg[0]_15\(12)
);
\weight_reg[0][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[0][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[0][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[0][12]_i_1_n_1\,
CO(1) => \weight_reg[0][12]_i_1_n_2\,
CO(0) => \weight_reg[0][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__29_n_77\,
DI(1) => \ARG__29_n_78\,
DI(0) => \ARG__29_n_79\,
O(3) => \weight_reg[0][12]_i_1_n_4\,
O(2) => \weight_reg[0][12]_i_1_n_5\,
O(1) => \weight_reg[0][12]_i_1_n_6\,
O(0) => \weight_reg[0][12]_i_1_n_7\,
S(3) => \weight[0][12]_i_2_n_0\,
S(2) => \weight[0][12]_i_3_n_0\,
S(1) => \weight[0][12]_i_4_n_0\,
S(0) => \weight[0][12]_i_5_n_0\
);
\weight_reg[0][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][12]_i_1_n_6\,
Q => \weight_reg[0]_15\(13)
);
\weight_reg[0][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][12]_i_1_n_5\,
Q => \weight_reg[0]_15\(14)
);
\weight_reg[0][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][12]_i_1_n_4\,
Q => \weight_reg[0]_15\(15)
);
\weight_reg[0][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][0]_i_1_n_6\,
Q => \weight_reg[0]_15\(1)
);
\weight_reg[0][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][0]_i_1_n_5\,
Q => \weight_reg[0]_15\(2)
);
\weight_reg[0][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][0]_i_1_n_4\,
Q => \weight_reg[0]_15\(3)
);
\weight_reg[0][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][4]_i_1_n_7\,
Q => \weight_reg[0]_15\(4)
);
\weight_reg[0][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[0][0]_i_1_n_0\,
CO(3) => \weight_reg[0][4]_i_1_n_0\,
CO(2) => \weight_reg[0][4]_i_1_n_1\,
CO(1) => \weight_reg[0][4]_i_1_n_2\,
CO(0) => \weight_reg[0][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__29_n_84\,
DI(2) => \ARG__29_n_85\,
DI(1) => \ARG__29_n_86\,
DI(0) => \ARG__29_n_87\,
O(3) => \weight_reg[0][4]_i_1_n_4\,
O(2) => \weight_reg[0][4]_i_1_n_5\,
O(1) => \weight_reg[0][4]_i_1_n_6\,
O(0) => \weight_reg[0][4]_i_1_n_7\,
S(3) => \weight[0][4]_i_2_n_0\,
S(2) => \weight[0][4]_i_3_n_0\,
S(1) => \weight[0][4]_i_4_n_0\,
S(0) => \weight[0][4]_i_5_n_0\
);
\weight_reg[0][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][4]_i_1_n_6\,
Q => \weight_reg[0]_15\(5)
);
\weight_reg[0][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][4]_i_1_n_5\,
Q => \weight_reg[0]_15\(6)
);
\weight_reg[0][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][4]_i_1_n_4\,
Q => \weight_reg[0]_15\(7)
);
\weight_reg[0][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][8]_i_1_n_7\,
Q => \weight_reg[0]_15\(8)
);
\weight_reg[0][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[0][4]_i_1_n_0\,
CO(3) => \weight_reg[0][8]_i_1_n_0\,
CO(2) => \weight_reg[0][8]_i_1_n_1\,
CO(1) => \weight_reg[0][8]_i_1_n_2\,
CO(0) => \weight_reg[0][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__29_n_80\,
DI(2) => \ARG__29_n_81\,
DI(1) => \ARG__29_n_82\,
DI(0) => \ARG__29_n_83\,
O(3) => \weight_reg[0][8]_i_1_n_4\,
O(2) => \weight_reg[0][8]_i_1_n_5\,
O(1) => \weight_reg[0][8]_i_1_n_6\,
O(0) => \weight_reg[0][8]_i_1_n_7\,
S(3) => \weight[0][8]_i_2_n_0\,
S(2) => \weight[0][8]_i_3_n_0\,
S(1) => \weight[0][8]_i_4_n_0\,
S(0) => \weight[0][8]_i_5_n_0\
);
\weight_reg[0][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][8]_i_1_n_6\,
Q => \weight_reg[0]_15\(9)
);
\weight_reg[10][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][0]_i_1_n_7\,
Q => \weight_reg[10]_9\(0)
);
\weight_reg[10][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[10][0]_i_1_n_0\,
CO(2) => \weight_reg[10][0]_i_1_n_1\,
CO(1) => \weight_reg[10][0]_i_1_n_2\,
CO(0) => \weight_reg[10][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__17_n_88\,
DI(2) => \ARG__17_n_89\,
DI(1) => \ARG__17_n_90\,
DI(0) => \ARG__17_n_91\,
O(3) => \weight_reg[10][0]_i_1_n_4\,
O(2) => \weight_reg[10][0]_i_1_n_5\,
O(1) => \weight_reg[10][0]_i_1_n_6\,
O(0) => \weight_reg[10][0]_i_1_n_7\,
S(3) => \weight[10][0]_i_2_n_0\,
S(2) => \weight[10][0]_i_3_n_0\,
S(1) => \weight[10][0]_i_4_n_0\,
S(0) => \weight[10][0]_i_5_n_0\
);
\weight_reg[10][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][8]_i_1_n_5\,
Q => \weight_reg[10]_9\(10)
);
\weight_reg[10][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][8]_i_1_n_4\,
Q => \weight_reg[10]_9\(11)
);
\weight_reg[10][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][12]_i_1_n_7\,
Q => \weight_reg[10]_9\(12)
);
\weight_reg[10][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[10][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[10][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[10][12]_i_1_n_1\,
CO(1) => \weight_reg[10][12]_i_1_n_2\,
CO(0) => \weight_reg[10][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__17_n_77\,
DI(1) => \ARG__17_n_78\,
DI(0) => \ARG__17_n_79\,
O(3) => \weight_reg[10][12]_i_1_n_4\,
O(2) => \weight_reg[10][12]_i_1_n_5\,
O(1) => \weight_reg[10][12]_i_1_n_6\,
O(0) => \weight_reg[10][12]_i_1_n_7\,
S(3) => \weight[10][12]_i_2_n_0\,
S(2) => \weight[10][12]_i_3_n_0\,
S(1) => \weight[10][12]_i_4_n_0\,
S(0) => \weight[10][12]_i_5_n_0\
);
\weight_reg[10][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][12]_i_1_n_6\,
Q => \weight_reg[10]_9\(13)
);
\weight_reg[10][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][12]_i_1_n_5\,
Q => \weight_reg[10]_9\(14)
);
\weight_reg[10][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][12]_i_1_n_4\,
Q => \weight_reg[10]_9\(15)
);
\weight_reg[10][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][0]_i_1_n_6\,
Q => \weight_reg[10]_9\(1)
);
\weight_reg[10][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][0]_i_1_n_5\,
Q => \weight_reg[10]_9\(2)
);
\weight_reg[10][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][0]_i_1_n_4\,
Q => \weight_reg[10]_9\(3)
);
\weight_reg[10][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][4]_i_1_n_7\,
Q => \weight_reg[10]_9\(4)
);
\weight_reg[10][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[10][0]_i_1_n_0\,
CO(3) => \weight_reg[10][4]_i_1_n_0\,
CO(2) => \weight_reg[10][4]_i_1_n_1\,
CO(1) => \weight_reg[10][4]_i_1_n_2\,
CO(0) => \weight_reg[10][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__17_n_84\,
DI(2) => \ARG__17_n_85\,
DI(1) => \ARG__17_n_86\,
DI(0) => \ARG__17_n_87\,
O(3) => \weight_reg[10][4]_i_1_n_4\,
O(2) => \weight_reg[10][4]_i_1_n_5\,
O(1) => \weight_reg[10][4]_i_1_n_6\,
O(0) => \weight_reg[10][4]_i_1_n_7\,
S(3) => \weight[10][4]_i_2_n_0\,
S(2) => \weight[10][4]_i_3_n_0\,
S(1) => \weight[10][4]_i_4_n_0\,
S(0) => \weight[10][4]_i_5_n_0\
);
\weight_reg[10][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][4]_i_1_n_6\,
Q => \weight_reg[10]_9\(5)
);
\weight_reg[10][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][4]_i_1_n_5\,
Q => \weight_reg[10]_9\(6)
);
\weight_reg[10][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][4]_i_1_n_4\,
Q => \weight_reg[10]_9\(7)
);
\weight_reg[10][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][8]_i_1_n_7\,
Q => \weight_reg[10]_9\(8)
);
\weight_reg[10][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[10][4]_i_1_n_0\,
CO(3) => \weight_reg[10][8]_i_1_n_0\,
CO(2) => \weight_reg[10][8]_i_1_n_1\,
CO(1) => \weight_reg[10][8]_i_1_n_2\,
CO(0) => \weight_reg[10][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__17_n_80\,
DI(2) => \ARG__17_n_81\,
DI(1) => \ARG__17_n_82\,
DI(0) => \ARG__17_n_83\,
O(3) => \weight_reg[10][8]_i_1_n_4\,
O(2) => \weight_reg[10][8]_i_1_n_5\,
O(1) => \weight_reg[10][8]_i_1_n_6\,
O(0) => \weight_reg[10][8]_i_1_n_7\,
S(3) => \weight[10][8]_i_2_n_0\,
S(2) => \weight[10][8]_i_3_n_0\,
S(1) => \weight[10][8]_i_4_n_0\,
S(0) => \weight[10][8]_i_5_n_0\
);
\weight_reg[10][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][8]_i_1_n_6\,
Q => \weight_reg[10]_9\(9)
);
\weight_reg[11][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][0]_i_1_n_7\,
Q => \weight_reg[11]_10\(0)
);
\weight_reg[11][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[11][0]_i_1_n_0\,
CO(2) => \weight_reg[11][0]_i_1_n_1\,
CO(1) => \weight_reg[11][0]_i_1_n_2\,
CO(0) => \weight_reg[11][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__19_n_88\,
DI(2) => \ARG__19_n_89\,
DI(1) => \ARG__19_n_90\,
DI(0) => \ARG__19_n_91\,
O(3) => \weight_reg[11][0]_i_1_n_4\,
O(2) => \weight_reg[11][0]_i_1_n_5\,
O(1) => \weight_reg[11][0]_i_1_n_6\,
O(0) => \weight_reg[11][0]_i_1_n_7\,
S(3) => \weight[11][0]_i_2_n_0\,
S(2) => \weight[11][0]_i_3_n_0\,
S(1) => \weight[11][0]_i_4_n_0\,
S(0) => \weight[11][0]_i_5_n_0\
);
\weight_reg[11][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][8]_i_1_n_5\,
Q => \weight_reg[11]_10\(10)
);
\weight_reg[11][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][8]_i_1_n_4\,
Q => \weight_reg[11]_10\(11)
);
\weight_reg[11][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][12]_i_1_n_7\,
Q => \weight_reg[11]_10\(12)
);
\weight_reg[11][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[11][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[11][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[11][12]_i_1_n_1\,
CO(1) => \weight_reg[11][12]_i_1_n_2\,
CO(0) => \weight_reg[11][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__19_n_77\,
DI(1) => \ARG__19_n_78\,
DI(0) => \ARG__19_n_79\,
O(3) => \weight_reg[11][12]_i_1_n_4\,
O(2) => \weight_reg[11][12]_i_1_n_5\,
O(1) => \weight_reg[11][12]_i_1_n_6\,
O(0) => \weight_reg[11][12]_i_1_n_7\,
S(3) => \weight[11][12]_i_2_n_0\,
S(2) => \weight[11][12]_i_3_n_0\,
S(1) => \weight[11][12]_i_4_n_0\,
S(0) => \weight[11][12]_i_5_n_0\
);
\weight_reg[11][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][12]_i_1_n_6\,
Q => \weight_reg[11]_10\(13)
);
\weight_reg[11][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][12]_i_1_n_5\,
Q => \weight_reg[11]_10\(14)
);
\weight_reg[11][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][12]_i_1_n_4\,
Q => \weight_reg[11]_10\(15)
);
\weight_reg[11][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][0]_i_1_n_6\,
Q => \weight_reg[11]_10\(1)
);
\weight_reg[11][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][0]_i_1_n_5\,
Q => \weight_reg[11]_10\(2)
);
\weight_reg[11][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][0]_i_1_n_4\,
Q => \weight_reg[11]_10\(3)
);
\weight_reg[11][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][4]_i_1_n_7\,
Q => \weight_reg[11]_10\(4)
);
\weight_reg[11][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[11][0]_i_1_n_0\,
CO(3) => \weight_reg[11][4]_i_1_n_0\,
CO(2) => \weight_reg[11][4]_i_1_n_1\,
CO(1) => \weight_reg[11][4]_i_1_n_2\,
CO(0) => \weight_reg[11][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__19_n_84\,
DI(2) => \ARG__19_n_85\,
DI(1) => \ARG__19_n_86\,
DI(0) => \ARG__19_n_87\,
O(3) => \weight_reg[11][4]_i_1_n_4\,
O(2) => \weight_reg[11][4]_i_1_n_5\,
O(1) => \weight_reg[11][4]_i_1_n_6\,
O(0) => \weight_reg[11][4]_i_1_n_7\,
S(3) => \weight[11][4]_i_2_n_0\,
S(2) => \weight[11][4]_i_3_n_0\,
S(1) => \weight[11][4]_i_4_n_0\,
S(0) => \weight[11][4]_i_5_n_0\
);
\weight_reg[11][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][4]_i_1_n_6\,
Q => \weight_reg[11]_10\(5)
);
\weight_reg[11][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][4]_i_1_n_5\,
Q => \weight_reg[11]_10\(6)
);
\weight_reg[11][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][4]_i_1_n_4\,
Q => \weight_reg[11]_10\(7)
);
\weight_reg[11][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][8]_i_1_n_7\,
Q => \weight_reg[11]_10\(8)
);
\weight_reg[11][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[11][4]_i_1_n_0\,
CO(3) => \weight_reg[11][8]_i_1_n_0\,
CO(2) => \weight_reg[11][8]_i_1_n_1\,
CO(1) => \weight_reg[11][8]_i_1_n_2\,
CO(0) => \weight_reg[11][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__19_n_80\,
DI(2) => \ARG__19_n_81\,
DI(1) => \ARG__19_n_82\,
DI(0) => \ARG__19_n_83\,
O(3) => \weight_reg[11][8]_i_1_n_4\,
O(2) => \weight_reg[11][8]_i_1_n_5\,
O(1) => \weight_reg[11][8]_i_1_n_6\,
O(0) => \weight_reg[11][8]_i_1_n_7\,
S(3) => \weight[11][8]_i_2_n_0\,
S(2) => \weight[11][8]_i_3_n_0\,
S(1) => \weight[11][8]_i_4_n_0\,
S(0) => \weight[11][8]_i_5_n_0\
);
\weight_reg[11][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][8]_i_1_n_6\,
Q => \weight_reg[11]_10\(9)
);
\weight_reg[12][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][0]_i_1_n_7\,
Q => \weight_reg[12]_11\(0)
);
\weight_reg[12][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[12][0]_i_1_n_0\,
CO(2) => \weight_reg[12][0]_i_1_n_1\,
CO(1) => \weight_reg[12][0]_i_1_n_2\,
CO(0) => \weight_reg[12][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__21_n_88\,
DI(2) => \ARG__21_n_89\,
DI(1) => \ARG__21_n_90\,
DI(0) => \ARG__21_n_91\,
O(3) => \weight_reg[12][0]_i_1_n_4\,
O(2) => \weight_reg[12][0]_i_1_n_5\,
O(1) => \weight_reg[12][0]_i_1_n_6\,
O(0) => \weight_reg[12][0]_i_1_n_7\,
S(3) => \weight[12][0]_i_2_n_0\,
S(2) => \weight[12][0]_i_3_n_0\,
S(1) => \weight[12][0]_i_4_n_0\,
S(0) => \weight[12][0]_i_5_n_0\
);
\weight_reg[12][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][8]_i_1_n_5\,
Q => \weight_reg[12]_11\(10)
);
\weight_reg[12][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][8]_i_1_n_4\,
Q => \weight_reg[12]_11\(11)
);
\weight_reg[12][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][12]_i_1_n_7\,
Q => \weight_reg[12]_11\(12)
);
\weight_reg[12][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[12][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[12][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[12][12]_i_1_n_1\,
CO(1) => \weight_reg[12][12]_i_1_n_2\,
CO(0) => \weight_reg[12][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__21_n_77\,
DI(1) => \ARG__21_n_78\,
DI(0) => \ARG__21_n_79\,
O(3) => \weight_reg[12][12]_i_1_n_4\,
O(2) => \weight_reg[12][12]_i_1_n_5\,
O(1) => \weight_reg[12][12]_i_1_n_6\,
O(0) => \weight_reg[12][12]_i_1_n_7\,
S(3) => \weight[12][12]_i_2_n_0\,
S(2) => \weight[12][12]_i_3_n_0\,
S(1) => \weight[12][12]_i_4_n_0\,
S(0) => \weight[12][12]_i_5_n_0\
);
\weight_reg[12][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][12]_i_1_n_6\,
Q => \weight_reg[12]_11\(13)
);
\weight_reg[12][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][12]_i_1_n_5\,
Q => \weight_reg[12]_11\(14)
);
\weight_reg[12][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][12]_i_1_n_4\,
Q => \weight_reg[12]_11\(15)
);
\weight_reg[12][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][0]_i_1_n_6\,
Q => \weight_reg[12]_11\(1)
);
\weight_reg[12][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][0]_i_1_n_5\,
Q => \weight_reg[12]_11\(2)
);
\weight_reg[12][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][0]_i_1_n_4\,
Q => \weight_reg[12]_11\(3)
);
\weight_reg[12][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][4]_i_1_n_7\,
Q => \weight_reg[12]_11\(4)
);
\weight_reg[12][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[12][0]_i_1_n_0\,
CO(3) => \weight_reg[12][4]_i_1_n_0\,
CO(2) => \weight_reg[12][4]_i_1_n_1\,
CO(1) => \weight_reg[12][4]_i_1_n_2\,
CO(0) => \weight_reg[12][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__21_n_84\,
DI(2) => \ARG__21_n_85\,
DI(1) => \ARG__21_n_86\,
DI(0) => \ARG__21_n_87\,
O(3) => \weight_reg[12][4]_i_1_n_4\,
O(2) => \weight_reg[12][4]_i_1_n_5\,
O(1) => \weight_reg[12][4]_i_1_n_6\,
O(0) => \weight_reg[12][4]_i_1_n_7\,
S(3) => \weight[12][4]_i_2_n_0\,
S(2) => \weight[12][4]_i_3_n_0\,
S(1) => \weight[12][4]_i_4_n_0\,
S(0) => \weight[12][4]_i_5_n_0\
);
\weight_reg[12][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][4]_i_1_n_6\,
Q => \weight_reg[12]_11\(5)
);
\weight_reg[12][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][4]_i_1_n_5\,
Q => \weight_reg[12]_11\(6)
);
\weight_reg[12][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][4]_i_1_n_4\,
Q => \weight_reg[12]_11\(7)
);
\weight_reg[12][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][8]_i_1_n_7\,
Q => \weight_reg[12]_11\(8)
);
\weight_reg[12][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[12][4]_i_1_n_0\,
CO(3) => \weight_reg[12][8]_i_1_n_0\,
CO(2) => \weight_reg[12][8]_i_1_n_1\,
CO(1) => \weight_reg[12][8]_i_1_n_2\,
CO(0) => \weight_reg[12][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__21_n_80\,
DI(2) => \ARG__21_n_81\,
DI(1) => \ARG__21_n_82\,
DI(0) => \ARG__21_n_83\,
O(3) => \weight_reg[12][8]_i_1_n_4\,
O(2) => \weight_reg[12][8]_i_1_n_5\,
O(1) => \weight_reg[12][8]_i_1_n_6\,
O(0) => \weight_reg[12][8]_i_1_n_7\,
S(3) => \weight[12][8]_i_2_n_0\,
S(2) => \weight[12][8]_i_3_n_0\,
S(1) => \weight[12][8]_i_4_n_0\,
S(0) => \weight[12][8]_i_5_n_0\
);
\weight_reg[12][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][8]_i_1_n_6\,
Q => \weight_reg[12]_11\(9)
);
\weight_reg[13][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][0]_i_1_n_7\,
Q => \weight_reg[13]_12\(0)
);
\weight_reg[13][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[13][0]_i_1_n_0\,
CO(2) => \weight_reg[13][0]_i_1_n_1\,
CO(1) => \weight_reg[13][0]_i_1_n_2\,
CO(0) => \weight_reg[13][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__23_n_88\,
DI(2) => \ARG__23_n_89\,
DI(1) => \ARG__23_n_90\,
DI(0) => \ARG__23_n_91\,
O(3) => \weight_reg[13][0]_i_1_n_4\,
O(2) => \weight_reg[13][0]_i_1_n_5\,
O(1) => \weight_reg[13][0]_i_1_n_6\,
O(0) => \weight_reg[13][0]_i_1_n_7\,
S(3) => \weight[13][0]_i_2_n_0\,
S(2) => \weight[13][0]_i_3_n_0\,
S(1) => \weight[13][0]_i_4_n_0\,
S(0) => \weight[13][0]_i_5_n_0\
);
\weight_reg[13][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][8]_i_1_n_5\,
Q => \weight_reg[13]_12\(10)
);
\weight_reg[13][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][8]_i_1_n_4\,
Q => \weight_reg[13]_12\(11)
);
\weight_reg[13][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][12]_i_1_n_7\,
Q => \weight_reg[13]_12\(12)
);
\weight_reg[13][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[13][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[13][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[13][12]_i_1_n_1\,
CO(1) => \weight_reg[13][12]_i_1_n_2\,
CO(0) => \weight_reg[13][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__23_n_77\,
DI(1) => \ARG__23_n_78\,
DI(0) => \ARG__23_n_79\,
O(3) => \weight_reg[13][12]_i_1_n_4\,
O(2) => \weight_reg[13][12]_i_1_n_5\,
O(1) => \weight_reg[13][12]_i_1_n_6\,
O(0) => \weight_reg[13][12]_i_1_n_7\,
S(3) => \weight[13][12]_i_2_n_0\,
S(2) => \weight[13][12]_i_3_n_0\,
S(1) => \weight[13][12]_i_4_n_0\,
S(0) => \weight[13][12]_i_5_n_0\
);
\weight_reg[13][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][12]_i_1_n_6\,
Q => \weight_reg[13]_12\(13)
);
\weight_reg[13][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][12]_i_1_n_5\,
Q => \weight_reg[13]_12\(14)
);
\weight_reg[13][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][12]_i_1_n_4\,
Q => \weight_reg[13]_12\(15)
);
\weight_reg[13][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][0]_i_1_n_6\,
Q => \weight_reg[13]_12\(1)
);
\weight_reg[13][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][0]_i_1_n_5\,
Q => \weight_reg[13]_12\(2)
);
\weight_reg[13][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][0]_i_1_n_4\,
Q => \weight_reg[13]_12\(3)
);
\weight_reg[13][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][4]_i_1_n_7\,
Q => \weight_reg[13]_12\(4)
);
\weight_reg[13][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[13][0]_i_1_n_0\,
CO(3) => \weight_reg[13][4]_i_1_n_0\,
CO(2) => \weight_reg[13][4]_i_1_n_1\,
CO(1) => \weight_reg[13][4]_i_1_n_2\,
CO(0) => \weight_reg[13][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__23_n_84\,
DI(2) => \ARG__23_n_85\,
DI(1) => \ARG__23_n_86\,
DI(0) => \ARG__23_n_87\,
O(3) => \weight_reg[13][4]_i_1_n_4\,
O(2) => \weight_reg[13][4]_i_1_n_5\,
O(1) => \weight_reg[13][4]_i_1_n_6\,
O(0) => \weight_reg[13][4]_i_1_n_7\,
S(3) => \weight[13][4]_i_2_n_0\,
S(2) => \weight[13][4]_i_3_n_0\,
S(1) => \weight[13][4]_i_4_n_0\,
S(0) => \weight[13][4]_i_5_n_0\
);
\weight_reg[13][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][4]_i_1_n_6\,
Q => \weight_reg[13]_12\(5)
);
\weight_reg[13][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][4]_i_1_n_5\,
Q => \weight_reg[13]_12\(6)
);
\weight_reg[13][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][4]_i_1_n_4\,
Q => \weight_reg[13]_12\(7)
);
\weight_reg[13][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][8]_i_1_n_7\,
Q => \weight_reg[13]_12\(8)
);
\weight_reg[13][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[13][4]_i_1_n_0\,
CO(3) => \weight_reg[13][8]_i_1_n_0\,
CO(2) => \weight_reg[13][8]_i_1_n_1\,
CO(1) => \weight_reg[13][8]_i_1_n_2\,
CO(0) => \weight_reg[13][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__23_n_80\,
DI(2) => \ARG__23_n_81\,
DI(1) => \ARG__23_n_82\,
DI(0) => \ARG__23_n_83\,
O(3) => \weight_reg[13][8]_i_1_n_4\,
O(2) => \weight_reg[13][8]_i_1_n_5\,
O(1) => \weight_reg[13][8]_i_1_n_6\,
O(0) => \weight_reg[13][8]_i_1_n_7\,
S(3) => \weight[13][8]_i_2_n_0\,
S(2) => \weight[13][8]_i_3_n_0\,
S(1) => \weight[13][8]_i_4_n_0\,
S(0) => \weight[13][8]_i_5_n_0\
);
\weight_reg[13][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][8]_i_1_n_6\,
Q => \weight_reg[13]_12\(9)
);
\weight_reg[14][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][0]_i_1_n_7\,
Q => \weight_reg[14]_13\(0)
);
\weight_reg[14][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[14][0]_i_1_n_0\,
CO(2) => \weight_reg[14][0]_i_1_n_1\,
CO(1) => \weight_reg[14][0]_i_1_n_2\,
CO(0) => \weight_reg[14][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__25_n_88\,
DI(2) => \ARG__25_n_89\,
DI(1) => \ARG__25_n_90\,
DI(0) => \ARG__25_n_91\,
O(3) => \weight_reg[14][0]_i_1_n_4\,
O(2) => \weight_reg[14][0]_i_1_n_5\,
O(1) => \weight_reg[14][0]_i_1_n_6\,
O(0) => \weight_reg[14][0]_i_1_n_7\,
S(3) => \weight[14][0]_i_2_n_0\,
S(2) => \weight[14][0]_i_3_n_0\,
S(1) => \weight[14][0]_i_4_n_0\,
S(0) => \weight[14][0]_i_5_n_0\
);
\weight_reg[14][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][8]_i_1_n_5\,
Q => \weight_reg[14]_13\(10)
);
\weight_reg[14][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][8]_i_1_n_4\,
Q => \weight_reg[14]_13\(11)
);
\weight_reg[14][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][12]_i_1_n_7\,
Q => \weight_reg[14]_13\(12)
);
\weight_reg[14][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[14][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[14][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[14][12]_i_1_n_1\,
CO(1) => \weight_reg[14][12]_i_1_n_2\,
CO(0) => \weight_reg[14][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__25_n_77\,
DI(1) => \ARG__25_n_78\,
DI(0) => \ARG__25_n_79\,
O(3) => \weight_reg[14][12]_i_1_n_4\,
O(2) => \weight_reg[14][12]_i_1_n_5\,
O(1) => \weight_reg[14][12]_i_1_n_6\,
O(0) => \weight_reg[14][12]_i_1_n_7\,
S(3) => \weight[14][12]_i_2_n_0\,
S(2) => \weight[14][12]_i_3_n_0\,
S(1) => \weight[14][12]_i_4_n_0\,
S(0) => \weight[14][12]_i_5_n_0\
);
\weight_reg[14][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][12]_i_1_n_6\,
Q => \weight_reg[14]_13\(13)
);
\weight_reg[14][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][12]_i_1_n_5\,
Q => \weight_reg[14]_13\(14)
);
\weight_reg[14][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][12]_i_1_n_4\,
Q => \weight_reg[14]_13\(15)
);
\weight_reg[14][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][0]_i_1_n_6\,
Q => \weight_reg[14]_13\(1)
);
\weight_reg[14][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][0]_i_1_n_5\,
Q => \weight_reg[14]_13\(2)
);
\weight_reg[14][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][0]_i_1_n_4\,
Q => \weight_reg[14]_13\(3)
);
\weight_reg[14][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][4]_i_1_n_7\,
Q => \weight_reg[14]_13\(4)
);
\weight_reg[14][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[14][0]_i_1_n_0\,
CO(3) => \weight_reg[14][4]_i_1_n_0\,
CO(2) => \weight_reg[14][4]_i_1_n_1\,
CO(1) => \weight_reg[14][4]_i_1_n_2\,
CO(0) => \weight_reg[14][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__25_n_84\,
DI(2) => \ARG__25_n_85\,
DI(1) => \ARG__25_n_86\,
DI(0) => \ARG__25_n_87\,
O(3) => \weight_reg[14][4]_i_1_n_4\,
O(2) => \weight_reg[14][4]_i_1_n_5\,
O(1) => \weight_reg[14][4]_i_1_n_6\,
O(0) => \weight_reg[14][4]_i_1_n_7\,
S(3) => \weight[14][4]_i_2_n_0\,
S(2) => \weight[14][4]_i_3_n_0\,
S(1) => \weight[14][4]_i_4_n_0\,
S(0) => \weight[14][4]_i_5_n_0\
);
\weight_reg[14][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][4]_i_1_n_6\,
Q => \weight_reg[14]_13\(5)
);
\weight_reg[14][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][4]_i_1_n_5\,
Q => \weight_reg[14]_13\(6)
);
\weight_reg[14][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][4]_i_1_n_4\,
Q => \weight_reg[14]_13\(7)
);
\weight_reg[14][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][8]_i_1_n_7\,
Q => \weight_reg[14]_13\(8)
);
\weight_reg[14][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[14][4]_i_1_n_0\,
CO(3) => \weight_reg[14][8]_i_1_n_0\,
CO(2) => \weight_reg[14][8]_i_1_n_1\,
CO(1) => \weight_reg[14][8]_i_1_n_2\,
CO(0) => \weight_reg[14][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__25_n_80\,
DI(2) => \ARG__25_n_81\,
DI(1) => \ARG__25_n_82\,
DI(0) => \ARG__25_n_83\,
O(3) => \weight_reg[14][8]_i_1_n_4\,
O(2) => \weight_reg[14][8]_i_1_n_5\,
O(1) => \weight_reg[14][8]_i_1_n_6\,
O(0) => \weight_reg[14][8]_i_1_n_7\,
S(3) => \weight[14][8]_i_2_n_0\,
S(2) => \weight[14][8]_i_3_n_0\,
S(1) => \weight[14][8]_i_4_n_0\,
S(0) => \weight[14][8]_i_5_n_0\
);
\weight_reg[14][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][8]_i_1_n_6\,
Q => \weight_reg[14]_13\(9)
);
\weight_reg[15][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][0]_i_1_n_7\,
Q => \weight_reg[15]_14\(0)
);
\weight_reg[15][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[15][0]_i_1_n_0\,
CO(2) => \weight_reg[15][0]_i_1_n_1\,
CO(1) => \weight_reg[15][0]_i_1_n_2\,
CO(0) => \weight_reg[15][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__27_n_88\,
DI(2) => \ARG__27_n_89\,
DI(1) => \ARG__27_n_90\,
DI(0) => \ARG__27_n_91\,
O(3) => \weight_reg[15][0]_i_1_n_4\,
O(2) => \weight_reg[15][0]_i_1_n_5\,
O(1) => \weight_reg[15][0]_i_1_n_6\,
O(0) => \weight_reg[15][0]_i_1_n_7\,
S(3) => \weight[15][0]_i_2_n_0\,
S(2) => \weight[15][0]_i_3_n_0\,
S(1) => \weight[15][0]_i_4_n_0\,
S(0) => \weight[15][0]_i_5_n_0\
);
\weight_reg[15][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][8]_i_1_n_5\,
Q => \weight_reg[15]_14\(10)
);
\weight_reg[15][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][8]_i_1_n_4\,
Q => \weight_reg[15]_14\(11)
);
\weight_reg[15][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][12]_i_1_n_7\,
Q => \weight_reg[15]_14\(12)
);
\weight_reg[15][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[15][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[15][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[15][12]_i_1_n_1\,
CO(1) => \weight_reg[15][12]_i_1_n_2\,
CO(0) => \weight_reg[15][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__27_n_77\,
DI(1) => \ARG__27_n_78\,
DI(0) => \ARG__27_n_79\,
O(3) => \weight_reg[15][12]_i_1_n_4\,
O(2) => \weight_reg[15][12]_i_1_n_5\,
O(1) => \weight_reg[15][12]_i_1_n_6\,
O(0) => \weight_reg[15][12]_i_1_n_7\,
S(3) => \weight[15][12]_i_2_n_0\,
S(2) => \weight[15][12]_i_3_n_0\,
S(1) => \weight[15][12]_i_4_n_0\,
S(0) => \weight[15][12]_i_5_n_0\
);
\weight_reg[15][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][12]_i_1_n_6\,
Q => \weight_reg[15]_14\(13)
);
\weight_reg[15][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][12]_i_1_n_5\,
Q => \weight_reg[15]_14\(14)
);
\weight_reg[15][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][12]_i_1_n_4\,
Q => \weight_reg[15]_14\(15)
);
\weight_reg[15][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][0]_i_1_n_6\,
Q => \weight_reg[15]_14\(1)
);
\weight_reg[15][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][0]_i_1_n_5\,
Q => \weight_reg[15]_14\(2)
);
\weight_reg[15][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][0]_i_1_n_4\,
Q => \weight_reg[15]_14\(3)
);
\weight_reg[15][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][4]_i_1_n_7\,
Q => \weight_reg[15]_14\(4)
);
\weight_reg[15][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[15][0]_i_1_n_0\,
CO(3) => \weight_reg[15][4]_i_1_n_0\,
CO(2) => \weight_reg[15][4]_i_1_n_1\,
CO(1) => \weight_reg[15][4]_i_1_n_2\,
CO(0) => \weight_reg[15][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__27_n_84\,
DI(2) => \ARG__27_n_85\,
DI(1) => \ARG__27_n_86\,
DI(0) => \ARG__27_n_87\,
O(3) => \weight_reg[15][4]_i_1_n_4\,
O(2) => \weight_reg[15][4]_i_1_n_5\,
O(1) => \weight_reg[15][4]_i_1_n_6\,
O(0) => \weight_reg[15][4]_i_1_n_7\,
S(3) => \weight[15][4]_i_2_n_0\,
S(2) => \weight[15][4]_i_3_n_0\,
S(1) => \weight[15][4]_i_4_n_0\,
S(0) => \weight[15][4]_i_5_n_0\
);
\weight_reg[15][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][4]_i_1_n_6\,
Q => \weight_reg[15]_14\(5)
);
\weight_reg[15][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][4]_i_1_n_5\,
Q => \weight_reg[15]_14\(6)
);
\weight_reg[15][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][4]_i_1_n_4\,
Q => \weight_reg[15]_14\(7)
);
\weight_reg[15][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][8]_i_1_n_7\,
Q => \weight_reg[15]_14\(8)
);
\weight_reg[15][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[15][4]_i_1_n_0\,
CO(3) => \weight_reg[15][8]_i_1_n_0\,
CO(2) => \weight_reg[15][8]_i_1_n_1\,
CO(1) => \weight_reg[15][8]_i_1_n_2\,
CO(0) => \weight_reg[15][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__27_n_80\,
DI(2) => \ARG__27_n_81\,
DI(1) => \ARG__27_n_82\,
DI(0) => \ARG__27_n_83\,
O(3) => \weight_reg[15][8]_i_1_n_4\,
O(2) => \weight_reg[15][8]_i_1_n_5\,
O(1) => \weight_reg[15][8]_i_1_n_6\,
O(0) => \weight_reg[15][8]_i_1_n_7\,
S(3) => \weight[15][8]_i_2_n_0\,
S(2) => \weight[15][8]_i_3_n_0\,
S(1) => \weight[15][8]_i_4_n_0\,
S(0) => \weight[15][8]_i_5_n_0\
);
\weight_reg[15][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][8]_i_1_n_6\,
Q => \weight_reg[15]_14\(9)
);
\weight_reg[1][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][0]_i_1_n_7\,
Q => \weight_reg[1]_0\(0)
);
\weight_reg[1][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[1][0]_i_1_n_0\,
CO(2) => \weight_reg[1][0]_i_1_n_1\,
CO(1) => \weight_reg[1][0]_i_1_n_2\,
CO(0) => \weight_reg[1][0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \in\(3 downto 0),
O(3) => \weight_reg[1][0]_i_1_n_4\,
O(2) => \weight_reg[1][0]_i_1_n_5\,
O(1) => \weight_reg[1][0]_i_1_n_6\,
O(0) => \weight_reg[1][0]_i_1_n_7\,
S(3) => \weight[1][0]_i_2_n_0\,
S(2) => \weight[1][0]_i_3_n_0\,
S(1) => \weight[1][0]_i_4_n_0\,
S(0) => \weight[1][0]_i_5_n_0\
);
\weight_reg[1][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][8]_i_1_n_5\,
Q => \weight_reg[1]_0\(10)
);
\weight_reg[1][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][8]_i_1_n_4\,
Q => \weight_reg[1]_0\(11)
);
\weight_reg[1][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][12]_i_1_n_7\,
Q => \weight_reg[1]_0\(12)
);
\weight_reg[1][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[1][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[1][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[1][12]_i_1_n_1\,
CO(1) => \weight_reg[1][12]_i_1_n_2\,
CO(0) => \weight_reg[1][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => \in\(14 downto 12),
O(3) => \weight_reg[1][12]_i_1_n_4\,
O(2) => \weight_reg[1][12]_i_1_n_5\,
O(1) => \weight_reg[1][12]_i_1_n_6\,
O(0) => \weight_reg[1][12]_i_1_n_7\,
S(3) => \weight[1][12]_i_2_n_0\,
S(2) => \weight[1][12]_i_3_n_0\,
S(1) => \weight[1][12]_i_4_n_0\,
S(0) => \weight[1][12]_i_5_n_0\
);
\weight_reg[1][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][12]_i_1_n_6\,
Q => \weight_reg[1]_0\(13)
);
\weight_reg[1][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][12]_i_1_n_5\,
Q => \weight_reg[1]_0\(14)
);
\weight_reg[1][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][12]_i_1_n_4\,
Q => \weight_reg[1]_0\(15)
);
\weight_reg[1][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][0]_i_1_n_6\,
Q => \weight_reg[1]_0\(1)
);
\weight_reg[1][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][0]_i_1_n_5\,
Q => \weight_reg[1]_0\(2)
);
\weight_reg[1][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][0]_i_1_n_4\,
Q => \weight_reg[1]_0\(3)
);
\weight_reg[1][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][4]_i_1_n_7\,
Q => \weight_reg[1]_0\(4)
);
\weight_reg[1][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[1][0]_i_1_n_0\,
CO(3) => \weight_reg[1][4]_i_1_n_0\,
CO(2) => \weight_reg[1][4]_i_1_n_1\,
CO(1) => \weight_reg[1][4]_i_1_n_2\,
CO(0) => \weight_reg[1][4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \in\(7 downto 4),
O(3) => \weight_reg[1][4]_i_1_n_4\,
O(2) => \weight_reg[1][4]_i_1_n_5\,
O(1) => \weight_reg[1][4]_i_1_n_6\,
O(0) => \weight_reg[1][4]_i_1_n_7\,
S(3) => \weight[1][4]_i_2_n_0\,
S(2) => \weight[1][4]_i_3_n_0\,
S(1) => \weight[1][4]_i_4_n_0\,
S(0) => \weight[1][4]_i_5_n_0\
);
\weight_reg[1][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][4]_i_1_n_6\,
Q => \weight_reg[1]_0\(5)
);
\weight_reg[1][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][4]_i_1_n_5\,
Q => \weight_reg[1]_0\(6)
);
\weight_reg[1][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][4]_i_1_n_4\,
Q => \weight_reg[1]_0\(7)
);
\weight_reg[1][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][8]_i_1_n_7\,
Q => \weight_reg[1]_0\(8)
);
\weight_reg[1][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[1][4]_i_1_n_0\,
CO(3) => \weight_reg[1][8]_i_1_n_0\,
CO(2) => \weight_reg[1][8]_i_1_n_1\,
CO(1) => \weight_reg[1][8]_i_1_n_2\,
CO(0) => \weight_reg[1][8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \in\(11 downto 8),
O(3) => \weight_reg[1][8]_i_1_n_4\,
O(2) => \weight_reg[1][8]_i_1_n_5\,
O(1) => \weight_reg[1][8]_i_1_n_6\,
O(0) => \weight_reg[1][8]_i_1_n_7\,
S(3) => \weight[1][8]_i_2_n_0\,
S(2) => \weight[1][8]_i_3_n_0\,
S(1) => \weight[1][8]_i_4_n_0\,
S(0) => \weight[1][8]_i_5_n_0\
);
\weight_reg[1][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][8]_i_1_n_6\,
Q => \weight_reg[1]_0\(9)
);
\weight_reg[2][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][0]_i_1_n_7\,
Q => \weight_reg[2]_1\(0)
);
\weight_reg[2][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[2][0]_i_1_n_0\,
CO(2) => \weight_reg[2][0]_i_1_n_1\,
CO(1) => \weight_reg[2][0]_i_1_n_2\,
CO(0) => \weight_reg[2][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__1_n_88\,
DI(2) => \ARG__1_n_89\,
DI(1) => \ARG__1_n_90\,
DI(0) => \ARG__1_n_91\,
O(3) => \weight_reg[2][0]_i_1_n_4\,
O(2) => \weight_reg[2][0]_i_1_n_5\,
O(1) => \weight_reg[2][0]_i_1_n_6\,
O(0) => \weight_reg[2][0]_i_1_n_7\,
S(3) => \weight[2][0]_i_2_n_0\,
S(2) => \weight[2][0]_i_3_n_0\,
S(1) => \weight[2][0]_i_4_n_0\,
S(0) => \weight[2][0]_i_5_n_0\
);
\weight_reg[2][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][8]_i_1_n_5\,
Q => \weight_reg[2]_1\(10)
);
\weight_reg[2][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][8]_i_1_n_4\,
Q => \weight_reg[2]_1\(11)
);
\weight_reg[2][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][12]_i_1_n_7\,
Q => \weight_reg[2]_1\(12)
);
\weight_reg[2][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[2][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[2][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[2][12]_i_1_n_1\,
CO(1) => \weight_reg[2][12]_i_1_n_2\,
CO(0) => \weight_reg[2][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__1_n_77\,
DI(1) => \ARG__1_n_78\,
DI(0) => \ARG__1_n_79\,
O(3) => \weight_reg[2][12]_i_1_n_4\,
O(2) => \weight_reg[2][12]_i_1_n_5\,
O(1) => \weight_reg[2][12]_i_1_n_6\,
O(0) => \weight_reg[2][12]_i_1_n_7\,
S(3) => \weight[2][12]_i_2_n_0\,
S(2) => \weight[2][12]_i_3_n_0\,
S(1) => \weight[2][12]_i_4_n_0\,
S(0) => \weight[2][12]_i_5_n_0\
);
\weight_reg[2][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][12]_i_1_n_6\,
Q => \weight_reg[2]_1\(13)
);
\weight_reg[2][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][12]_i_1_n_5\,
Q => \weight_reg[2]_1\(14)
);
\weight_reg[2][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][12]_i_1_n_4\,
Q => \weight_reg[2]_1\(15)
);
\weight_reg[2][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][0]_i_1_n_6\,
Q => \weight_reg[2]_1\(1)
);
\weight_reg[2][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][0]_i_1_n_5\,
Q => \weight_reg[2]_1\(2)
);
\weight_reg[2][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][0]_i_1_n_4\,
Q => \weight_reg[2]_1\(3)
);
\weight_reg[2][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][4]_i_1_n_7\,
Q => \weight_reg[2]_1\(4)
);
\weight_reg[2][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[2][0]_i_1_n_0\,
CO(3) => \weight_reg[2][4]_i_1_n_0\,
CO(2) => \weight_reg[2][4]_i_1_n_1\,
CO(1) => \weight_reg[2][4]_i_1_n_2\,
CO(0) => \weight_reg[2][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__1_n_84\,
DI(2) => \ARG__1_n_85\,
DI(1) => \ARG__1_n_86\,
DI(0) => \ARG__1_n_87\,
O(3) => \weight_reg[2][4]_i_1_n_4\,
O(2) => \weight_reg[2][4]_i_1_n_5\,
O(1) => \weight_reg[2][4]_i_1_n_6\,
O(0) => \weight_reg[2][4]_i_1_n_7\,
S(3) => \weight[2][4]_i_2_n_0\,
S(2) => \weight[2][4]_i_3_n_0\,
S(1) => \weight[2][4]_i_4_n_0\,
S(0) => \weight[2][4]_i_5_n_0\
);
\weight_reg[2][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][4]_i_1_n_6\,
Q => \weight_reg[2]_1\(5)
);
\weight_reg[2][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][4]_i_1_n_5\,
Q => \weight_reg[2]_1\(6)
);
\weight_reg[2][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][4]_i_1_n_4\,
Q => \weight_reg[2]_1\(7)
);
\weight_reg[2][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][8]_i_1_n_7\,
Q => \weight_reg[2]_1\(8)
);
\weight_reg[2][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[2][4]_i_1_n_0\,
CO(3) => \weight_reg[2][8]_i_1_n_0\,
CO(2) => \weight_reg[2][8]_i_1_n_1\,
CO(1) => \weight_reg[2][8]_i_1_n_2\,
CO(0) => \weight_reg[2][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__1_n_80\,
DI(2) => \ARG__1_n_81\,
DI(1) => \ARG__1_n_82\,
DI(0) => \ARG__1_n_83\,
O(3) => \weight_reg[2][8]_i_1_n_4\,
O(2) => \weight_reg[2][8]_i_1_n_5\,
O(1) => \weight_reg[2][8]_i_1_n_6\,
O(0) => \weight_reg[2][8]_i_1_n_7\,
S(3) => \weight[2][8]_i_2_n_0\,
S(2) => \weight[2][8]_i_3_n_0\,
S(1) => \weight[2][8]_i_4_n_0\,
S(0) => \weight[2][8]_i_5_n_0\
);
\weight_reg[2][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][8]_i_1_n_6\,
Q => \weight_reg[2]_1\(9)
);
\weight_reg[3][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][0]_i_1_n_7\,
Q => \weight_reg[3]_2\(0)
);
\weight_reg[3][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[3][0]_i_1_n_0\,
CO(2) => \weight_reg[3][0]_i_1_n_1\,
CO(1) => \weight_reg[3][0]_i_1_n_2\,
CO(0) => \weight_reg[3][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__3_n_88\,
DI(2) => \ARG__3_n_89\,
DI(1) => \ARG__3_n_90\,
DI(0) => \ARG__3_n_91\,
O(3) => \weight_reg[3][0]_i_1_n_4\,
O(2) => \weight_reg[3][0]_i_1_n_5\,
O(1) => \weight_reg[3][0]_i_1_n_6\,
O(0) => \weight_reg[3][0]_i_1_n_7\,
S(3) => \weight[3][0]_i_2_n_0\,
S(2) => \weight[3][0]_i_3_n_0\,
S(1) => \weight[3][0]_i_4_n_0\,
S(0) => \weight[3][0]_i_5_n_0\
);
\weight_reg[3][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][8]_i_1_n_5\,
Q => \weight_reg[3]_2\(10)
);
\weight_reg[3][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][8]_i_1_n_4\,
Q => \weight_reg[3]_2\(11)
);
\weight_reg[3][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][12]_i_1_n_7\,
Q => \weight_reg[3]_2\(12)
);
\weight_reg[3][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[3][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[3][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[3][12]_i_1_n_1\,
CO(1) => \weight_reg[3][12]_i_1_n_2\,
CO(0) => \weight_reg[3][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__3_n_77\,
DI(1) => \ARG__3_n_78\,
DI(0) => \ARG__3_n_79\,
O(3) => \weight_reg[3][12]_i_1_n_4\,
O(2) => \weight_reg[3][12]_i_1_n_5\,
O(1) => \weight_reg[3][12]_i_1_n_6\,
O(0) => \weight_reg[3][12]_i_1_n_7\,
S(3) => \weight[3][12]_i_2_n_0\,
S(2) => \weight[3][12]_i_3_n_0\,
S(1) => \weight[3][12]_i_4_n_0\,
S(0) => \weight[3][12]_i_5_n_0\
);
\weight_reg[3][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][12]_i_1_n_6\,
Q => \weight_reg[3]_2\(13)
);
\weight_reg[3][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][12]_i_1_n_5\,
Q => \weight_reg[3]_2\(14)
);
\weight_reg[3][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][12]_i_1_n_4\,
Q => \weight_reg[3]_2\(15)
);
\weight_reg[3][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][0]_i_1_n_6\,
Q => \weight_reg[3]_2\(1)
);
\weight_reg[3][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][0]_i_1_n_5\,
Q => \weight_reg[3]_2\(2)
);
\weight_reg[3][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][0]_i_1_n_4\,
Q => \weight_reg[3]_2\(3)
);
\weight_reg[3][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][4]_i_1_n_7\,
Q => \weight_reg[3]_2\(4)
);
\weight_reg[3][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[3][0]_i_1_n_0\,
CO(3) => \weight_reg[3][4]_i_1_n_0\,
CO(2) => \weight_reg[3][4]_i_1_n_1\,
CO(1) => \weight_reg[3][4]_i_1_n_2\,
CO(0) => \weight_reg[3][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__3_n_84\,
DI(2) => \ARG__3_n_85\,
DI(1) => \ARG__3_n_86\,
DI(0) => \ARG__3_n_87\,
O(3) => \weight_reg[3][4]_i_1_n_4\,
O(2) => \weight_reg[3][4]_i_1_n_5\,
O(1) => \weight_reg[3][4]_i_1_n_6\,
O(0) => \weight_reg[3][4]_i_1_n_7\,
S(3) => \weight[3][4]_i_2_n_0\,
S(2) => \weight[3][4]_i_3_n_0\,
S(1) => \weight[3][4]_i_4_n_0\,
S(0) => \weight[3][4]_i_5_n_0\
);
\weight_reg[3][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][4]_i_1_n_6\,
Q => \weight_reg[3]_2\(5)
);
\weight_reg[3][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][4]_i_1_n_5\,
Q => \weight_reg[3]_2\(6)
);
\weight_reg[3][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][4]_i_1_n_4\,
Q => \weight_reg[3]_2\(7)
);
\weight_reg[3][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][8]_i_1_n_7\,
Q => \weight_reg[3]_2\(8)
);
\weight_reg[3][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[3][4]_i_1_n_0\,
CO(3) => \weight_reg[3][8]_i_1_n_0\,
CO(2) => \weight_reg[3][8]_i_1_n_1\,
CO(1) => \weight_reg[3][8]_i_1_n_2\,
CO(0) => \weight_reg[3][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__3_n_80\,
DI(2) => \ARG__3_n_81\,
DI(1) => \ARG__3_n_82\,
DI(0) => \ARG__3_n_83\,
O(3) => \weight_reg[3][8]_i_1_n_4\,
O(2) => \weight_reg[3][8]_i_1_n_5\,
O(1) => \weight_reg[3][8]_i_1_n_6\,
O(0) => \weight_reg[3][8]_i_1_n_7\,
S(3) => \weight[3][8]_i_2_n_0\,
S(2) => \weight[3][8]_i_3_n_0\,
S(1) => \weight[3][8]_i_4_n_0\,
S(0) => \weight[3][8]_i_5_n_0\
);
\weight_reg[3][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][8]_i_1_n_6\,
Q => \weight_reg[3]_2\(9)
);
\weight_reg[4][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][0]_i_1_n_7\,
Q => \weight_reg[4]_3\(0)
);
\weight_reg[4][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[4][0]_i_1_n_0\,
CO(2) => \weight_reg[4][0]_i_1_n_1\,
CO(1) => \weight_reg[4][0]_i_1_n_2\,
CO(0) => \weight_reg[4][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__5_n_88\,
DI(2) => \ARG__5_n_89\,
DI(1) => \ARG__5_n_90\,
DI(0) => \ARG__5_n_91\,
O(3) => \weight_reg[4][0]_i_1_n_4\,
O(2) => \weight_reg[4][0]_i_1_n_5\,
O(1) => \weight_reg[4][0]_i_1_n_6\,
O(0) => \weight_reg[4][0]_i_1_n_7\,
S(3) => \weight[4][0]_i_2_n_0\,
S(2) => \weight[4][0]_i_3_n_0\,
S(1) => \weight[4][0]_i_4_n_0\,
S(0) => \weight[4][0]_i_5_n_0\
);
\weight_reg[4][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][8]_i_1_n_5\,
Q => \weight_reg[4]_3\(10)
);
\weight_reg[4][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][8]_i_1_n_4\,
Q => \weight_reg[4]_3\(11)
);
\weight_reg[4][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][12]_i_1_n_7\,
Q => \weight_reg[4]_3\(12)
);
\weight_reg[4][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[4][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[4][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[4][12]_i_1_n_1\,
CO(1) => \weight_reg[4][12]_i_1_n_2\,
CO(0) => \weight_reg[4][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__5_n_77\,
DI(1) => \ARG__5_n_78\,
DI(0) => \ARG__5_n_79\,
O(3) => \weight_reg[4][12]_i_1_n_4\,
O(2) => \weight_reg[4][12]_i_1_n_5\,
O(1) => \weight_reg[4][12]_i_1_n_6\,
O(0) => \weight_reg[4][12]_i_1_n_7\,
S(3) => \weight[4][12]_i_2_n_0\,
S(2) => \weight[4][12]_i_3_n_0\,
S(1) => \weight[4][12]_i_4_n_0\,
S(0) => \weight[4][12]_i_5_n_0\
);
\weight_reg[4][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][12]_i_1_n_6\,
Q => \weight_reg[4]_3\(13)
);
\weight_reg[4][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][12]_i_1_n_5\,
Q => \weight_reg[4]_3\(14)
);
\weight_reg[4][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][12]_i_1_n_4\,
Q => \weight_reg[4]_3\(15)
);
\weight_reg[4][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][0]_i_1_n_6\,
Q => \weight_reg[4]_3\(1)
);
\weight_reg[4][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][0]_i_1_n_5\,
Q => \weight_reg[4]_3\(2)
);
\weight_reg[4][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][0]_i_1_n_4\,
Q => \weight_reg[4]_3\(3)
);
\weight_reg[4][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][4]_i_1_n_7\,
Q => \weight_reg[4]_3\(4)
);
\weight_reg[4][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[4][0]_i_1_n_0\,
CO(3) => \weight_reg[4][4]_i_1_n_0\,
CO(2) => \weight_reg[4][4]_i_1_n_1\,
CO(1) => \weight_reg[4][4]_i_1_n_2\,
CO(0) => \weight_reg[4][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__5_n_84\,
DI(2) => \ARG__5_n_85\,
DI(1) => \ARG__5_n_86\,
DI(0) => \ARG__5_n_87\,
O(3) => \weight_reg[4][4]_i_1_n_4\,
O(2) => \weight_reg[4][4]_i_1_n_5\,
O(1) => \weight_reg[4][4]_i_1_n_6\,
O(0) => \weight_reg[4][4]_i_1_n_7\,
S(3) => \weight[4][4]_i_2_n_0\,
S(2) => \weight[4][4]_i_3_n_0\,
S(1) => \weight[4][4]_i_4_n_0\,
S(0) => \weight[4][4]_i_5_n_0\
);
\weight_reg[4][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][4]_i_1_n_6\,
Q => \weight_reg[4]_3\(5)
);
\weight_reg[4][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][4]_i_1_n_5\,
Q => \weight_reg[4]_3\(6)
);
\weight_reg[4][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][4]_i_1_n_4\,
Q => \weight_reg[4]_3\(7)
);
\weight_reg[4][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][8]_i_1_n_7\,
Q => \weight_reg[4]_3\(8)
);
\weight_reg[4][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[4][4]_i_1_n_0\,
CO(3) => \weight_reg[4][8]_i_1_n_0\,
CO(2) => \weight_reg[4][8]_i_1_n_1\,
CO(1) => \weight_reg[4][8]_i_1_n_2\,
CO(0) => \weight_reg[4][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__5_n_80\,
DI(2) => \ARG__5_n_81\,
DI(1) => \ARG__5_n_82\,
DI(0) => \ARG__5_n_83\,
O(3) => \weight_reg[4][8]_i_1_n_4\,
O(2) => \weight_reg[4][8]_i_1_n_5\,
O(1) => \weight_reg[4][8]_i_1_n_6\,
O(0) => \weight_reg[4][8]_i_1_n_7\,
S(3) => \weight[4][8]_i_2_n_0\,
S(2) => \weight[4][8]_i_3_n_0\,
S(1) => \weight[4][8]_i_4_n_0\,
S(0) => \weight[4][8]_i_5_n_0\
);
\weight_reg[4][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][8]_i_1_n_6\,
Q => \weight_reg[4]_3\(9)
);
\weight_reg[5][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][0]_i_1_n_7\,
Q => \weight_reg[5]_4\(0)
);
\weight_reg[5][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[5][0]_i_1_n_0\,
CO(2) => \weight_reg[5][0]_i_1_n_1\,
CO(1) => \weight_reg[5][0]_i_1_n_2\,
CO(0) => \weight_reg[5][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__7_n_88\,
DI(2) => \ARG__7_n_89\,
DI(1) => \ARG__7_n_90\,
DI(0) => \ARG__7_n_91\,
O(3) => \weight_reg[5][0]_i_1_n_4\,
O(2) => \weight_reg[5][0]_i_1_n_5\,
O(1) => \weight_reg[5][0]_i_1_n_6\,
O(0) => \weight_reg[5][0]_i_1_n_7\,
S(3) => \weight[5][0]_i_2_n_0\,
S(2) => \weight[5][0]_i_3_n_0\,
S(1) => \weight[5][0]_i_4_n_0\,
S(0) => \weight[5][0]_i_5_n_0\
);
\weight_reg[5][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][8]_i_1_n_5\,
Q => \weight_reg[5]_4\(10)
);
\weight_reg[5][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][8]_i_1_n_4\,
Q => \weight_reg[5]_4\(11)
);
\weight_reg[5][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][12]_i_1_n_7\,
Q => \weight_reg[5]_4\(12)
);
\weight_reg[5][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[5][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[5][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[5][12]_i_1_n_1\,
CO(1) => \weight_reg[5][12]_i_1_n_2\,
CO(0) => \weight_reg[5][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__7_n_77\,
DI(1) => \ARG__7_n_78\,
DI(0) => \ARG__7_n_79\,
O(3) => \weight_reg[5][12]_i_1_n_4\,
O(2) => \weight_reg[5][12]_i_1_n_5\,
O(1) => \weight_reg[5][12]_i_1_n_6\,
O(0) => \weight_reg[5][12]_i_1_n_7\,
S(3) => \weight[5][12]_i_2_n_0\,
S(2) => \weight[5][12]_i_3_n_0\,
S(1) => \weight[5][12]_i_4_n_0\,
S(0) => \weight[5][12]_i_5_n_0\
);
\weight_reg[5][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][12]_i_1_n_6\,
Q => \weight_reg[5]_4\(13)
);
\weight_reg[5][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][12]_i_1_n_5\,
Q => \weight_reg[5]_4\(14)
);
\weight_reg[5][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][12]_i_1_n_4\,
Q => \weight_reg[5]_4\(15)
);
\weight_reg[5][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][0]_i_1_n_6\,
Q => \weight_reg[5]_4\(1)
);
\weight_reg[5][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][0]_i_1_n_5\,
Q => \weight_reg[5]_4\(2)
);
\weight_reg[5][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][0]_i_1_n_4\,
Q => \weight_reg[5]_4\(3)
);
\weight_reg[5][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][4]_i_1_n_7\,
Q => \weight_reg[5]_4\(4)
);
\weight_reg[5][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[5][0]_i_1_n_0\,
CO(3) => \weight_reg[5][4]_i_1_n_0\,
CO(2) => \weight_reg[5][4]_i_1_n_1\,
CO(1) => \weight_reg[5][4]_i_1_n_2\,
CO(0) => \weight_reg[5][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__7_n_84\,
DI(2) => \ARG__7_n_85\,
DI(1) => \ARG__7_n_86\,
DI(0) => \ARG__7_n_87\,
O(3) => \weight_reg[5][4]_i_1_n_4\,
O(2) => \weight_reg[5][4]_i_1_n_5\,
O(1) => \weight_reg[5][4]_i_1_n_6\,
O(0) => \weight_reg[5][4]_i_1_n_7\,
S(3) => \weight[5][4]_i_2_n_0\,
S(2) => \weight[5][4]_i_3_n_0\,
S(1) => \weight[5][4]_i_4_n_0\,
S(0) => \weight[5][4]_i_5_n_0\
);
\weight_reg[5][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][4]_i_1_n_6\,
Q => \weight_reg[5]_4\(5)
);
\weight_reg[5][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][4]_i_1_n_5\,
Q => \weight_reg[5]_4\(6)
);
\weight_reg[5][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][4]_i_1_n_4\,
Q => \weight_reg[5]_4\(7)
);
\weight_reg[5][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][8]_i_1_n_7\,
Q => \weight_reg[5]_4\(8)
);
\weight_reg[5][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[5][4]_i_1_n_0\,
CO(3) => \weight_reg[5][8]_i_1_n_0\,
CO(2) => \weight_reg[5][8]_i_1_n_1\,
CO(1) => \weight_reg[5][8]_i_1_n_2\,
CO(0) => \weight_reg[5][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__7_n_80\,
DI(2) => \ARG__7_n_81\,
DI(1) => \ARG__7_n_82\,
DI(0) => \ARG__7_n_83\,
O(3) => \weight_reg[5][8]_i_1_n_4\,
O(2) => \weight_reg[5][8]_i_1_n_5\,
O(1) => \weight_reg[5][8]_i_1_n_6\,
O(0) => \weight_reg[5][8]_i_1_n_7\,
S(3) => \weight[5][8]_i_2_n_0\,
S(2) => \weight[5][8]_i_3_n_0\,
S(1) => \weight[5][8]_i_4_n_0\,
S(0) => \weight[5][8]_i_5_n_0\
);
\weight_reg[5][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][8]_i_1_n_6\,
Q => \weight_reg[5]_4\(9)
);
\weight_reg[6][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][0]_i_1_n_7\,
Q => \weight_reg[6]_5\(0)
);
\weight_reg[6][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[6][0]_i_1_n_0\,
CO(2) => \weight_reg[6][0]_i_1_n_1\,
CO(1) => \weight_reg[6][0]_i_1_n_2\,
CO(0) => \weight_reg[6][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__9_n_88\,
DI(2) => \ARG__9_n_89\,
DI(1) => \ARG__9_n_90\,
DI(0) => \ARG__9_n_91\,
O(3) => \weight_reg[6][0]_i_1_n_4\,
O(2) => \weight_reg[6][0]_i_1_n_5\,
O(1) => \weight_reg[6][0]_i_1_n_6\,
O(0) => \weight_reg[6][0]_i_1_n_7\,
S(3) => \weight[6][0]_i_2_n_0\,
S(2) => \weight[6][0]_i_3_n_0\,
S(1) => \weight[6][0]_i_4_n_0\,
S(0) => \weight[6][0]_i_5_n_0\
);
\weight_reg[6][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][8]_i_1_n_5\,
Q => \weight_reg[6]_5\(10)
);
\weight_reg[6][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][8]_i_1_n_4\,
Q => \weight_reg[6]_5\(11)
);
\weight_reg[6][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][12]_i_1_n_7\,
Q => \weight_reg[6]_5\(12)
);
\weight_reg[6][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[6][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[6][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[6][12]_i_1_n_1\,
CO(1) => \weight_reg[6][12]_i_1_n_2\,
CO(0) => \weight_reg[6][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__9_n_77\,
DI(1) => \ARG__9_n_78\,
DI(0) => \ARG__9_n_79\,
O(3) => \weight_reg[6][12]_i_1_n_4\,
O(2) => \weight_reg[6][12]_i_1_n_5\,
O(1) => \weight_reg[6][12]_i_1_n_6\,
O(0) => \weight_reg[6][12]_i_1_n_7\,
S(3) => \weight[6][12]_i_2_n_0\,
S(2) => \weight[6][12]_i_3_n_0\,
S(1) => \weight[6][12]_i_4_n_0\,
S(0) => \weight[6][12]_i_5_n_0\
);
\weight_reg[6][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][12]_i_1_n_6\,
Q => \weight_reg[6]_5\(13)
);
\weight_reg[6][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][12]_i_1_n_5\,
Q => \weight_reg[6]_5\(14)
);
\weight_reg[6][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][12]_i_1_n_4\,
Q => \weight_reg[6]_5\(15)
);
\weight_reg[6][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][0]_i_1_n_6\,
Q => \weight_reg[6]_5\(1)
);
\weight_reg[6][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][0]_i_1_n_5\,
Q => \weight_reg[6]_5\(2)
);
\weight_reg[6][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][0]_i_1_n_4\,
Q => \weight_reg[6]_5\(3)
);
\weight_reg[6][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][4]_i_1_n_7\,
Q => \weight_reg[6]_5\(4)
);
\weight_reg[6][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[6][0]_i_1_n_0\,
CO(3) => \weight_reg[6][4]_i_1_n_0\,
CO(2) => \weight_reg[6][4]_i_1_n_1\,
CO(1) => \weight_reg[6][4]_i_1_n_2\,
CO(0) => \weight_reg[6][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__9_n_84\,
DI(2) => \ARG__9_n_85\,
DI(1) => \ARG__9_n_86\,
DI(0) => \ARG__9_n_87\,
O(3) => \weight_reg[6][4]_i_1_n_4\,
O(2) => \weight_reg[6][4]_i_1_n_5\,
O(1) => \weight_reg[6][4]_i_1_n_6\,
O(0) => \weight_reg[6][4]_i_1_n_7\,
S(3) => \weight[6][4]_i_2_n_0\,
S(2) => \weight[6][4]_i_3_n_0\,
S(1) => \weight[6][4]_i_4_n_0\,
S(0) => \weight[6][4]_i_5_n_0\
);
\weight_reg[6][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][4]_i_1_n_6\,
Q => \weight_reg[6]_5\(5)
);
\weight_reg[6][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][4]_i_1_n_5\,
Q => \weight_reg[6]_5\(6)
);
\weight_reg[6][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][4]_i_1_n_4\,
Q => \weight_reg[6]_5\(7)
);
\weight_reg[6][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][8]_i_1_n_7\,
Q => \weight_reg[6]_5\(8)
);
\weight_reg[6][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[6][4]_i_1_n_0\,
CO(3) => \weight_reg[6][8]_i_1_n_0\,
CO(2) => \weight_reg[6][8]_i_1_n_1\,
CO(1) => \weight_reg[6][8]_i_1_n_2\,
CO(0) => \weight_reg[6][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__9_n_80\,
DI(2) => \ARG__9_n_81\,
DI(1) => \ARG__9_n_82\,
DI(0) => \ARG__9_n_83\,
O(3) => \weight_reg[6][8]_i_1_n_4\,
O(2) => \weight_reg[6][8]_i_1_n_5\,
O(1) => \weight_reg[6][8]_i_1_n_6\,
O(0) => \weight_reg[6][8]_i_1_n_7\,
S(3) => \weight[6][8]_i_2_n_0\,
S(2) => \weight[6][8]_i_3_n_0\,
S(1) => \weight[6][8]_i_4_n_0\,
S(0) => \weight[6][8]_i_5_n_0\
);
\weight_reg[6][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][8]_i_1_n_6\,
Q => \weight_reg[6]_5\(9)
);
\weight_reg[7][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][0]_i_1_n_7\,
Q => \weight_reg[7]_6\(0)
);
\weight_reg[7][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[7][0]_i_1_n_0\,
CO(2) => \weight_reg[7][0]_i_1_n_1\,
CO(1) => \weight_reg[7][0]_i_1_n_2\,
CO(0) => \weight_reg[7][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__11_n_88\,
DI(2) => \ARG__11_n_89\,
DI(1) => \ARG__11_n_90\,
DI(0) => \ARG__11_n_91\,
O(3) => \weight_reg[7][0]_i_1_n_4\,
O(2) => \weight_reg[7][0]_i_1_n_5\,
O(1) => \weight_reg[7][0]_i_1_n_6\,
O(0) => \weight_reg[7][0]_i_1_n_7\,
S(3) => \weight[7][0]_i_2_n_0\,
S(2) => \weight[7][0]_i_3_n_0\,
S(1) => \weight[7][0]_i_4_n_0\,
S(0) => \weight[7][0]_i_5_n_0\
);
\weight_reg[7][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][8]_i_1_n_5\,
Q => \weight_reg[7]_6\(10)
);
\weight_reg[7][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][8]_i_1_n_4\,
Q => \weight_reg[7]_6\(11)
);
\weight_reg[7][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][12]_i_1_n_7\,
Q => \weight_reg[7]_6\(12)
);
\weight_reg[7][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[7][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[7][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[7][12]_i_1_n_1\,
CO(1) => \weight_reg[7][12]_i_1_n_2\,
CO(0) => \weight_reg[7][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__11_n_77\,
DI(1) => \ARG__11_n_78\,
DI(0) => \ARG__11_n_79\,
O(3) => \weight_reg[7][12]_i_1_n_4\,
O(2) => \weight_reg[7][12]_i_1_n_5\,
O(1) => \weight_reg[7][12]_i_1_n_6\,
O(0) => \weight_reg[7][12]_i_1_n_7\,
S(3) => \weight[7][12]_i_2_n_0\,
S(2) => \weight[7][12]_i_3_n_0\,
S(1) => \weight[7][12]_i_4_n_0\,
S(0) => \weight[7][12]_i_5_n_0\
);
\weight_reg[7][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][12]_i_1_n_6\,
Q => \weight_reg[7]_6\(13)
);
\weight_reg[7][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][12]_i_1_n_5\,
Q => \weight_reg[7]_6\(14)
);
\weight_reg[7][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][12]_i_1_n_4\,
Q => \weight_reg[7]_6\(15)
);
\weight_reg[7][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][0]_i_1_n_6\,
Q => \weight_reg[7]_6\(1)
);
\weight_reg[7][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][0]_i_1_n_5\,
Q => \weight_reg[7]_6\(2)
);
\weight_reg[7][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][0]_i_1_n_4\,
Q => \weight_reg[7]_6\(3)
);
\weight_reg[7][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][4]_i_1_n_7\,
Q => \weight_reg[7]_6\(4)
);
\weight_reg[7][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[7][0]_i_1_n_0\,
CO(3) => \weight_reg[7][4]_i_1_n_0\,
CO(2) => \weight_reg[7][4]_i_1_n_1\,
CO(1) => \weight_reg[7][4]_i_1_n_2\,
CO(0) => \weight_reg[7][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__11_n_84\,
DI(2) => \ARG__11_n_85\,
DI(1) => \ARG__11_n_86\,
DI(0) => \ARG__11_n_87\,
O(3) => \weight_reg[7][4]_i_1_n_4\,
O(2) => \weight_reg[7][4]_i_1_n_5\,
O(1) => \weight_reg[7][4]_i_1_n_6\,
O(0) => \weight_reg[7][4]_i_1_n_7\,
S(3) => \weight[7][4]_i_2_n_0\,
S(2) => \weight[7][4]_i_3_n_0\,
S(1) => \weight[7][4]_i_4_n_0\,
S(0) => \weight[7][4]_i_5_n_0\
);
\weight_reg[7][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][4]_i_1_n_6\,
Q => \weight_reg[7]_6\(5)
);
\weight_reg[7][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][4]_i_1_n_5\,
Q => \weight_reg[7]_6\(6)
);
\weight_reg[7][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][4]_i_1_n_4\,
Q => \weight_reg[7]_6\(7)
);
\weight_reg[7][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][8]_i_1_n_7\,
Q => \weight_reg[7]_6\(8)
);
\weight_reg[7][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[7][4]_i_1_n_0\,
CO(3) => \weight_reg[7][8]_i_1_n_0\,
CO(2) => \weight_reg[7][8]_i_1_n_1\,
CO(1) => \weight_reg[7][8]_i_1_n_2\,
CO(0) => \weight_reg[7][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__11_n_80\,
DI(2) => \ARG__11_n_81\,
DI(1) => \ARG__11_n_82\,
DI(0) => \ARG__11_n_83\,
O(3) => \weight_reg[7][8]_i_1_n_4\,
O(2) => \weight_reg[7][8]_i_1_n_5\,
O(1) => \weight_reg[7][8]_i_1_n_6\,
O(0) => \weight_reg[7][8]_i_1_n_7\,
S(3) => \weight[7][8]_i_2_n_0\,
S(2) => \weight[7][8]_i_3_n_0\,
S(1) => \weight[7][8]_i_4_n_0\,
S(0) => \weight[7][8]_i_5_n_0\
);
\weight_reg[7][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][8]_i_1_n_6\,
Q => \weight_reg[7]_6\(9)
);
\weight_reg[8][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][0]_i_1_n_7\,
Q => \weight_reg[8]_7\(0)
);
\weight_reg[8][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[8][0]_i_1_n_0\,
CO(2) => \weight_reg[8][0]_i_1_n_1\,
CO(1) => \weight_reg[8][0]_i_1_n_2\,
CO(0) => \weight_reg[8][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__13_n_88\,
DI(2) => \ARG__13_n_89\,
DI(1) => \ARG__13_n_90\,
DI(0) => \ARG__13_n_91\,
O(3) => \weight_reg[8][0]_i_1_n_4\,
O(2) => \weight_reg[8][0]_i_1_n_5\,
O(1) => \weight_reg[8][0]_i_1_n_6\,
O(0) => \weight_reg[8][0]_i_1_n_7\,
S(3) => \weight[8][0]_i_2_n_0\,
S(2) => \weight[8][0]_i_3_n_0\,
S(1) => \weight[8][0]_i_4_n_0\,
S(0) => \weight[8][0]_i_5_n_0\
);
\weight_reg[8][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][8]_i_1_n_5\,
Q => \weight_reg[8]_7\(10)
);
\weight_reg[8][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][8]_i_1_n_4\,
Q => \weight_reg[8]_7\(11)
);
\weight_reg[8][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][12]_i_1_n_7\,
Q => \weight_reg[8]_7\(12)
);
\weight_reg[8][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[8][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[8][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[8][12]_i_1_n_1\,
CO(1) => \weight_reg[8][12]_i_1_n_2\,
CO(0) => \weight_reg[8][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__13_n_77\,
DI(1) => \ARG__13_n_78\,
DI(0) => \ARG__13_n_79\,
O(3) => \weight_reg[8][12]_i_1_n_4\,
O(2) => \weight_reg[8][12]_i_1_n_5\,
O(1) => \weight_reg[8][12]_i_1_n_6\,
O(0) => \weight_reg[8][12]_i_1_n_7\,
S(3) => \weight[8][12]_i_2_n_0\,
S(2) => \weight[8][12]_i_3_n_0\,
S(1) => \weight[8][12]_i_4_n_0\,
S(0) => \weight[8][12]_i_5_n_0\
);
\weight_reg[8][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][12]_i_1_n_6\,
Q => \weight_reg[8]_7\(13)
);
\weight_reg[8][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][12]_i_1_n_5\,
Q => \weight_reg[8]_7\(14)
);
\weight_reg[8][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][12]_i_1_n_4\,
Q => \weight_reg[8]_7\(15)
);
\weight_reg[8][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][0]_i_1_n_6\,
Q => \weight_reg[8]_7\(1)
);
\weight_reg[8][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][0]_i_1_n_5\,
Q => \weight_reg[8]_7\(2)
);
\weight_reg[8][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][0]_i_1_n_4\,
Q => \weight_reg[8]_7\(3)
);
\weight_reg[8][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][4]_i_1_n_7\,
Q => \weight_reg[8]_7\(4)
);
\weight_reg[8][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[8][0]_i_1_n_0\,
CO(3) => \weight_reg[8][4]_i_1_n_0\,
CO(2) => \weight_reg[8][4]_i_1_n_1\,
CO(1) => \weight_reg[8][4]_i_1_n_2\,
CO(0) => \weight_reg[8][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__13_n_84\,
DI(2) => \ARG__13_n_85\,
DI(1) => \ARG__13_n_86\,
DI(0) => \ARG__13_n_87\,
O(3) => \weight_reg[8][4]_i_1_n_4\,
O(2) => \weight_reg[8][4]_i_1_n_5\,
O(1) => \weight_reg[8][4]_i_1_n_6\,
O(0) => \weight_reg[8][4]_i_1_n_7\,
S(3) => \weight[8][4]_i_2_n_0\,
S(2) => \weight[8][4]_i_3_n_0\,
S(1) => \weight[8][4]_i_4_n_0\,
S(0) => \weight[8][4]_i_5_n_0\
);
\weight_reg[8][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][4]_i_1_n_6\,
Q => \weight_reg[8]_7\(5)
);
\weight_reg[8][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][4]_i_1_n_5\,
Q => \weight_reg[8]_7\(6)
);
\weight_reg[8][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][4]_i_1_n_4\,
Q => \weight_reg[8]_7\(7)
);
\weight_reg[8][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][8]_i_1_n_7\,
Q => \weight_reg[8]_7\(8)
);
\weight_reg[8][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[8][4]_i_1_n_0\,
CO(3) => \weight_reg[8][8]_i_1_n_0\,
CO(2) => \weight_reg[8][8]_i_1_n_1\,
CO(1) => \weight_reg[8][8]_i_1_n_2\,
CO(0) => \weight_reg[8][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__13_n_80\,
DI(2) => \ARG__13_n_81\,
DI(1) => \ARG__13_n_82\,
DI(0) => \ARG__13_n_83\,
O(3) => \weight_reg[8][8]_i_1_n_4\,
O(2) => \weight_reg[8][8]_i_1_n_5\,
O(1) => \weight_reg[8][8]_i_1_n_6\,
O(0) => \weight_reg[8][8]_i_1_n_7\,
S(3) => \weight[8][8]_i_2_n_0\,
S(2) => \weight[8][8]_i_3_n_0\,
S(1) => \weight[8][8]_i_4_n_0\,
S(0) => \weight[8][8]_i_5_n_0\
);
\weight_reg[8][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][8]_i_1_n_6\,
Q => \weight_reg[8]_7\(9)
);
\weight_reg[9][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][0]_i_1_n_7\,
Q => \weight_reg[9]_8\(0)
);
\weight_reg[9][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[9][0]_i_1_n_0\,
CO(2) => \weight_reg[9][0]_i_1_n_1\,
CO(1) => \weight_reg[9][0]_i_1_n_2\,
CO(0) => \weight_reg[9][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__15_n_88\,
DI(2) => \ARG__15_n_89\,
DI(1) => \ARG__15_n_90\,
DI(0) => \ARG__15_n_91\,
O(3) => \weight_reg[9][0]_i_1_n_4\,
O(2) => \weight_reg[9][0]_i_1_n_5\,
O(1) => \weight_reg[9][0]_i_1_n_6\,
O(0) => \weight_reg[9][0]_i_1_n_7\,
S(3) => \weight[9][0]_i_2_n_0\,
S(2) => \weight[9][0]_i_3_n_0\,
S(1) => \weight[9][0]_i_4_n_0\,
S(0) => \weight[9][0]_i_5_n_0\
);
\weight_reg[9][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][8]_i_1_n_5\,
Q => \weight_reg[9]_8\(10)
);
\weight_reg[9][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][8]_i_1_n_4\,
Q => \weight_reg[9]_8\(11)
);
\weight_reg[9][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][12]_i_1_n_7\,
Q => \weight_reg[9]_8\(12)
);
\weight_reg[9][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[9][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[9][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[9][12]_i_1_n_1\,
CO(1) => \weight_reg[9][12]_i_1_n_2\,
CO(0) => \weight_reg[9][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__15_n_77\,
DI(1) => \ARG__15_n_78\,
DI(0) => \ARG__15_n_79\,
O(3) => \weight_reg[9][12]_i_1_n_4\,
O(2) => \weight_reg[9][12]_i_1_n_5\,
O(1) => \weight_reg[9][12]_i_1_n_6\,
O(0) => \weight_reg[9][12]_i_1_n_7\,
S(3) => \weight[9][12]_i_2_n_0\,
S(2) => \weight[9][12]_i_3_n_0\,
S(1) => \weight[9][12]_i_4_n_0\,
S(0) => \weight[9][12]_i_5_n_0\
);
\weight_reg[9][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][12]_i_1_n_6\,
Q => \weight_reg[9]_8\(13)
);
\weight_reg[9][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][12]_i_1_n_5\,
Q => \weight_reg[9]_8\(14)
);
\weight_reg[9][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][12]_i_1_n_4\,
Q => \weight_reg[9]_8\(15)
);
\weight_reg[9][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][0]_i_1_n_6\,
Q => \weight_reg[9]_8\(1)
);
\weight_reg[9][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][0]_i_1_n_5\,
Q => \weight_reg[9]_8\(2)
);
\weight_reg[9][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][0]_i_1_n_4\,
Q => \weight_reg[9]_8\(3)
);
\weight_reg[9][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][4]_i_1_n_7\,
Q => \weight_reg[9]_8\(4)
);
\weight_reg[9][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[9][0]_i_1_n_0\,
CO(3) => \weight_reg[9][4]_i_1_n_0\,
CO(2) => \weight_reg[9][4]_i_1_n_1\,
CO(1) => \weight_reg[9][4]_i_1_n_2\,
CO(0) => \weight_reg[9][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__15_n_84\,
DI(2) => \ARG__15_n_85\,
DI(1) => \ARG__15_n_86\,
DI(0) => \ARG__15_n_87\,
O(3) => \weight_reg[9][4]_i_1_n_4\,
O(2) => \weight_reg[9][4]_i_1_n_5\,
O(1) => \weight_reg[9][4]_i_1_n_6\,
O(0) => \weight_reg[9][4]_i_1_n_7\,
S(3) => \weight[9][4]_i_2_n_0\,
S(2) => \weight[9][4]_i_3_n_0\,
S(1) => \weight[9][4]_i_4_n_0\,
S(0) => \weight[9][4]_i_5_n_0\
);
\weight_reg[9][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][4]_i_1_n_6\,
Q => \weight_reg[9]_8\(5)
);
\weight_reg[9][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][4]_i_1_n_5\,
Q => \weight_reg[9]_8\(6)
);
\weight_reg[9][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][4]_i_1_n_4\,
Q => \weight_reg[9]_8\(7)
);
\weight_reg[9][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][8]_i_1_n_7\,
Q => \weight_reg[9]_8\(8)
);
\weight_reg[9][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[9][4]_i_1_n_0\,
CO(3) => \weight_reg[9][8]_i_1_n_0\,
CO(2) => \weight_reg[9][8]_i_1_n_1\,
CO(1) => \weight_reg[9][8]_i_1_n_2\,
CO(0) => \weight_reg[9][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__15_n_80\,
DI(2) => \ARG__15_n_81\,
DI(1) => \ARG__15_n_82\,
DI(0) => \ARG__15_n_83\,
O(3) => \weight_reg[9][8]_i_1_n_4\,
O(2) => \weight_reg[9][8]_i_1_n_5\,
O(1) => \weight_reg[9][8]_i_1_n_6\,
O(0) => \weight_reg[9][8]_i_1_n_7\,
S(3) => \weight[9][8]_i_2_n_0\,
S(2) => \weight[9][8]_i_3_n_0\,
S(1) => \weight[9][8]_i_4_n_0\,
S(0) => \weight[9][8]_i_5_n_0\
);
\weight_reg[9][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][8]_i_1_n_6\,
Q => \weight_reg[9]_8\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_lms_pcore_0_0_lms_pcore_addr_decoder is
port (
read_reg_cop_out_ready : out STD_LOGIC;
write_reg_axi_enable : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 14 downto 0 );
\sync_reg_e_k_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\sync_reg_e_k_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\sync_reg_e_k_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
DI : out STD_LOGIC_VECTOR ( 0 to 0 );
\ARG__29\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\cp_controller_cpstate_reg[0]\ : out STD_LOGIC;
\ARG__28\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
\AXI4_Lite_RDATA_tmp_reg[31]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
strobe_sw_cop_in_strobe : in STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
cop_out_ready : in STD_LOGIC;
\wdata_reg[0]\ : in STD_LOGIC;
filter_sum : in STD_LOGIC_VECTOR ( 15 downto 0 );
mul_temp_16 : in STD_LOGIC_VECTOR ( 15 downto 0 );
cp_controller_cpstate : in STD_LOGIC_VECTOR ( 1 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\wdata_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
wr_enb_1_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_lms_pcore_0_0_lms_pcore_addr_decoder : entity is "lms_pcore_addr_decoder";
end ip_design_lms_pcore_0_0_lms_pcore_addr_decoder;
architecture STRUCTURE of ip_design_lms_pcore_0_0_lms_pcore_addr_decoder is
signal \^q\ : STD_LOGIC_VECTOR ( 14 downto 0 );
signal in_strobe : STD_LOGIC;
signal \^write_reg_axi_enable\ : STD_LOGIC;
signal write_reg_d_k : STD_LOGIC_VECTOR ( 15 to 15 );
begin
Q(14 downto 0) <= \^q\(14 downto 0);
write_reg_axi_enable <= \^write_reg_axi_enable\;
\ARG_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => mul_temp_16(3),
O => DI(0)
);
ARG_carry_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => mul_temp_16(1),
O => \ARG__29\(2)
);
ARG_carry_i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => mul_temp_16(0),
O => \ARG__29\(1)
);
ARG_carry_i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => mul_temp_16(3),
O => \ARG__29\(0)
);
\cp_controller_cpstate[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0F20"
)
port map (
I0 => in_strobe,
I1 => cp_controller_cpstate(1),
I2 => \^write_reg_axi_enable\,
I3 => cp_controller_cpstate(0),
O => \cp_controller_cpstate_reg[0]\
);
read_reg_cop_out_ready_reg: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => AR(0),
D => cop_out_ready,
Q => read_reg_cop_out_ready
);
strobe_reg_cop_in_strobe_reg: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => AR(0),
D => strobe_sw_cop_in_strobe,
Q => in_strobe
);
\sub_temp_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(7),
I1 => filter_sum(7),
O => \sync_reg_e_k_reg[7]_0\(3)
);
\sub_temp_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(6),
I1 => filter_sum(6),
O => \sync_reg_e_k_reg[7]_0\(2)
);
\sub_temp_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(5),
I1 => filter_sum(5),
O => \sync_reg_e_k_reg[7]_0\(1)
);
\sub_temp_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => filter_sum(4),
O => \sync_reg_e_k_reg[7]_0\(0)
);
\sub_temp_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(11),
I1 => filter_sum(11),
O => \sync_reg_e_k_reg[11]_0\(3)
);
\sub_temp_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(10),
I1 => filter_sum(10),
O => \sync_reg_e_k_reg[11]_0\(2)
);
\sub_temp_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(9),
I1 => filter_sum(9),
O => \sync_reg_e_k_reg[11]_0\(1)
);
\sub_temp_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => filter_sum(8),
O => \sync_reg_e_k_reg[11]_0\(0)
);
\sub_temp_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => write_reg_d_k(15),
I1 => filter_sum(15),
O => S(3)
);
\sub_temp_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(14),
I1 => filter_sum(14),
O => S(2)
);
\sub_temp_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(13),
I1 => filter_sum(13),
O => S(1)
);
\sub_temp_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(12),
I1 => filter_sum(12),
O => S(0)
);
sub_temp_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => filter_sum(3),
O => \sync_reg_e_k_reg[3]_0\(3)
);
sub_temp_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => filter_sum(2),
O => \sync_reg_e_k_reg[3]_0\(2)
);
sub_temp_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => filter_sum(1),
O => \sync_reg_e_k_reg[3]_0\(1)
);
sub_temp_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(0),
I1 => filter_sum(0),
O => \sync_reg_e_k_reg[3]_0\(0)
);
\sync_reg_e_k_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(0),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(0)
);
\sync_reg_e_k_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(10),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(10)
);
\sync_reg_e_k_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(11),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(11)
);
\sync_reg_e_k_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(12),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(12)
);
\sync_reg_e_k_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(13),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(13)
);
\sync_reg_e_k_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(14),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(14)
);
\sync_reg_e_k_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(15),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(15)
);
\sync_reg_e_k_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(1),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(1)
);
\sync_reg_e_k_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(2),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(2)
);
\sync_reg_e_k_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(3),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(3)
);
\sync_reg_e_k_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(4),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(4)
);
\sync_reg_e_k_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(5),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(5)
);
\sync_reg_e_k_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(6),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(6)
);
\sync_reg_e_k_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(7),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(7)
);
\sync_reg_e_k_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(8),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(8)
);
\sync_reg_e_k_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(9),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(9)
);
write_reg_axi_enable_reg: unisim.vcomponents.FDPE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
D => \wdata_reg[0]\,
PRE => AR(0),
Q => \^write_reg_axi_enable\
);
\write_reg_d_k_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(0),
Q => \^q\(0)
);
\write_reg_d_k_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(10),
Q => \^q\(10)
);
\write_reg_d_k_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(11),
Q => \^q\(11)
);
\write_reg_d_k_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(12),
Q => \^q\(12)
);
\write_reg_d_k_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(13),
Q => \^q\(13)
);
\write_reg_d_k_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(14),
Q => \^q\(14)
);
\write_reg_d_k_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(15),
Q => write_reg_d_k(15)
);
\write_reg_d_k_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(1),
Q => \^q\(1)
);
\write_reg_d_k_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(2),
Q => \^q\(2)
);
\write_reg_d_k_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(3),
Q => \^q\(3)
);
\write_reg_d_k_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(4),
Q => \^q\(4)
);
\write_reg_d_k_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(5),
Q => \^q\(5)
);
\write_reg_d_k_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(6),
Q => \^q\(6)
);
\write_reg_d_k_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(7),
Q => \^q\(7)
);
\write_reg_d_k_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(8),
Q => \^q\(8)
);
\write_reg_d_k_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(9),
Q => \^q\(9)
);
\write_reg_x_k_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(0),
Q => \ARG__28\(0)
);
\write_reg_x_k_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(10),
Q => \ARG__28\(10)
);
\write_reg_x_k_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(11),
Q => \ARG__28\(11)
);
\write_reg_x_k_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(12),
Q => \ARG__28\(12)
);
\write_reg_x_k_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(13),
Q => \ARG__28\(13)
);
\write_reg_x_k_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(14),
Q => \ARG__28\(14)
);
\write_reg_x_k_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(15),
Q => \ARG__28\(15)
);
\write_reg_x_k_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(1),
Q => \ARG__28\(1)
);
\write_reg_x_k_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(2),
Q => \ARG__28\(2)
);
\write_reg_x_k_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(3),
Q => \ARG__28\(3)
);
\write_reg_x_k_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(4),
Q => \ARG__28\(4)
);
\write_reg_x_k_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(5),
Q => \ARG__28\(5)
);
\write_reg_x_k_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(6),
Q => \ARG__28\(6)
);
\write_reg_x_k_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(7),
Q => \ARG__28\(7)
);
\write_reg_x_k_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(8),
Q => \ARG__28\(8)
);
\write_reg_x_k_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(9),
Q => \ARG__28\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_lms_pcore_0_0_lms_pcore_axi_lite_module is
port (
AXI4_Lite_RVALID : out STD_LOGIC;
write_reg_axi_enable_reg : out STD_LOGIC;
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BVALID : out STD_LOGIC;
write_reg_axi_enable_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWREADY : out STD_LOGIC;
strobe_sw_cop_in_strobe : out STD_LOGIC;
\write_reg_d_k_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
write_reg_axi_enable : in STD_LOGIC;
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
AXI4_Lite_BREADY : in STD_LOGIC;
\sync_reg_e_k_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
read_reg_cop_out_ready : in STD_LOGIC;
AXI4_Lite_RREADY : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_lms_pcore_0_0_lms_pcore_axi_lite_module : entity is "lms_pcore_axi_lite_module";
end ip_design_lms_pcore_0_0_lms_pcore_axi_lite_module;
architecture STRUCTURE of ip_design_lms_pcore_0_0_lms_pcore_axi_lite_module is
signal \AXI4_Lite_RDATA_tmp[0]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[0]_i_3_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_10_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_11_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_12_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_9_n_0\ : STD_LOGIC;
signal \^axi4_lite_rvalid\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal aw_transfer : STD_LOGIC;
signal \axi_lite_rstate[0]_i_1_n_0\ : STD_LOGIC;
signal axi_lite_wstate : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axi_lite_wstate[0]_i_1_n_0\ : STD_LOGIC;
signal \axi_lite_wstate_next_inferred__1/i__n_0\ : STD_LOGIC;
signal data_read : STD_LOGIC_VECTOR ( 31 downto 0 );
signal reset : STD_LOGIC;
signal sel0 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal soft_reset : STD_LOGIC;
signal soft_reset_i_2_n_0 : STD_LOGIC;
signal soft_reset_i_3_n_0 : STD_LOGIC;
signal soft_reset_i_4_n_0 : STD_LOGIC;
signal strobe_reg_cop_in_strobe_i_3_n_0 : STD_LOGIC;
signal strobe_sw : STD_LOGIC;
signal top_rd_enb : STD_LOGIC;
signal top_wr_enb : STD_LOGIC;
signal w_transfer : STD_LOGIC;
signal write_reg_axi_enable_i_2_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of AXI4_Lite_BVALID_INST_0 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \AXI4_Lite_RDATA_tmp[0]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \AXI4_Lite_RDATA_tmp[31]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \AXI4_Lite_RDATA_tmp[31]_i_6\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \AXI4_Lite_RDATA_tmp[31]_i_7\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of AXI4_Lite_WREADY_INST_0 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \axi_lite_rstate[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axi_lite_wstate[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \axi_lite_wstate_next_inferred__1/i_\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of strobe_reg_cop_in_strobe_i_3 : label is "soft_lutpair1";
begin
AXI4_Lite_RVALID <= \^axi4_lite_rvalid\;
Q(15 downto 0) <= \^q\(15 downto 0);
AXI4_Lite_ARREADY_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axi4_lite_rvalid\,
O => AXI4_Lite_ARREADY
);
AXI4_Lite_AWREADY_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_lite_wstate(0),
I1 => axi_lite_wstate(1),
O => AXI4_Lite_AWREADY
);
AXI4_Lite_BVALID_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_lite_wstate(1),
I1 => axi_lite_wstate(0),
O => AXI4_Lite_BVALID
);
\AXI4_Lite_RDATA_tmp[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00008CCC00008000"
)
port map (
I0 => \sync_reg_e_k_reg[15]\(0),
I1 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[0]_i_2_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I5 => \AXI4_Lite_RDATA_tmp[0]_i_3_n_0\,
O => data_read(0)
);
\AXI4_Lite_RDATA_tmp[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => sel0(6),
I1 => AXI4_Lite_ARADDR(6),
I2 => sel0(0),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(0),
O => \AXI4_Lite_RDATA_tmp[0]_i_2_n_0\
);
\AXI4_Lite_RDATA_tmp[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000B80000000000"
)
port map (
I0 => AXI4_Lite_ARADDR(0),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(0),
I3 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I5 => read_reg_cop_out_ready,
O => \AXI4_Lite_RDATA_tmp[0]_i_3_n_0\
);
\AXI4_Lite_RDATA_tmp[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(10),
O => data_read(10)
);
\AXI4_Lite_RDATA_tmp[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(11),
O => data_read(11)
);
\AXI4_Lite_RDATA_tmp[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(12),
O => data_read(12)
);
\AXI4_Lite_RDATA_tmp[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(13),
O => data_read(13)
);
\AXI4_Lite_RDATA_tmp[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(14),
O => data_read(14)
);
\AXI4_Lite_RDATA_tmp[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(1),
O => data_read(1)
);
\AXI4_Lite_RDATA_tmp[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(2),
O => data_read(2)
);
\AXI4_Lite_RDATA_tmp[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => AXI4_Lite_ARVALID,
I1 => \^axi4_lite_rvalid\,
O => top_rd_enb
);
\AXI4_Lite_RDATA_tmp[31]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEEF0EE"
)
port map (
I0 => sel0(5),
I1 => sel0(4),
I2 => AXI4_Lite_ARADDR(5),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(4),
O => \AXI4_Lite_RDATA_tmp[31]_i_10_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEEF0EE"
)
port map (
I0 => sel0(3),
I1 => sel0(2),
I2 => AXI4_Lite_ARADDR(3),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(2),
O => \AXI4_Lite_RDATA_tmp[31]_i_11_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEEF0EE"
)
port map (
I0 => sel0(9),
I1 => sel0(8),
I2 => AXI4_Lite_ARADDR(9),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(8),
O => \AXI4_Lite_RDATA_tmp[31]_i_12_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(15),
O => data_read(31)
);
\AXI4_Lite_RDATA_tmp[31]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => AXI4_Lite_ARESETN,
O => reset
);
\AXI4_Lite_RDATA_tmp[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEFEFFFFAEFEA"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_9_n_0\,
I1 => AXI4_Lite_ARADDR(10),
I2 => AXI4_Lite_ARVALID,
I3 => sel0(10),
I4 => AXI4_Lite_ARADDR(11),
I5 => sel0(11),
O => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => AXI4_Lite_ARADDR(1),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(1),
O => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => AXI4_Lite_ARADDR(6),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(6),
O => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => AXI4_Lite_ARADDR(0),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(0),
O => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"00011101"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_10_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_11_n_0\,
I2 => sel0(7),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(7),
O => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFBBFCB8"
)
port map (
I0 => AXI4_Lite_ARADDR(13),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(13),
I3 => AXI4_Lite_ARADDR(12),
I4 => sel0(12),
I5 => \AXI4_Lite_RDATA_tmp[31]_i_12_n_0\,
O => \AXI4_Lite_RDATA_tmp[31]_i_9_n_0\
);
\AXI4_Lite_RDATA_tmp[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(3),
O => data_read(3)
);
\AXI4_Lite_RDATA_tmp[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(4),
O => data_read(4)
);
\AXI4_Lite_RDATA_tmp[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(5),
O => data_read(5)
);
\AXI4_Lite_RDATA_tmp[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(6),
O => data_read(6)
);
\AXI4_Lite_RDATA_tmp[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(7),
O => data_read(7)
);
\AXI4_Lite_RDATA_tmp[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(8),
O => data_read(8)
);
\AXI4_Lite_RDATA_tmp[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(9),
O => data_read(9)
);
\AXI4_Lite_RDATA_tmp_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(0),
Q => AXI4_Lite_RDATA(0)
);
\AXI4_Lite_RDATA_tmp_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(10),
Q => AXI4_Lite_RDATA(10)
);
\AXI4_Lite_RDATA_tmp_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(11),
Q => AXI4_Lite_RDATA(11)
);
\AXI4_Lite_RDATA_tmp_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(12),
Q => AXI4_Lite_RDATA(12)
);
\AXI4_Lite_RDATA_tmp_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(13),
Q => AXI4_Lite_RDATA(13)
);
\AXI4_Lite_RDATA_tmp_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(14),
Q => AXI4_Lite_RDATA(14)
);
\AXI4_Lite_RDATA_tmp_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(1),
Q => AXI4_Lite_RDATA(1)
);
\AXI4_Lite_RDATA_tmp_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(2),
Q => AXI4_Lite_RDATA(2)
);
\AXI4_Lite_RDATA_tmp_reg[31]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(31),
Q => AXI4_Lite_RDATA(15)
);
\AXI4_Lite_RDATA_tmp_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(3),
Q => AXI4_Lite_RDATA(3)
);
\AXI4_Lite_RDATA_tmp_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(4),
Q => AXI4_Lite_RDATA(4)
);
\AXI4_Lite_RDATA_tmp_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(5),
Q => AXI4_Lite_RDATA(5)
);
\AXI4_Lite_RDATA_tmp_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(6),
Q => AXI4_Lite_RDATA(6)
);
\AXI4_Lite_RDATA_tmp_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(7),
Q => AXI4_Lite_RDATA(7)
);
\AXI4_Lite_RDATA_tmp_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(8),
Q => AXI4_Lite_RDATA(8)
);
\AXI4_Lite_RDATA_tmp_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(9),
Q => AXI4_Lite_RDATA(9)
);
AXI4_Lite_WREADY_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_lite_wstate(0),
I1 => axi_lite_wstate(1),
O => AXI4_Lite_WREADY
);
\axi_lite_rstate[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => AXI4_Lite_RREADY,
I1 => \^axi4_lite_rvalid\,
I2 => AXI4_Lite_ARVALID,
O => \axi_lite_rstate[0]_i_1_n_0\
);
\axi_lite_rstate_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => \axi_lite_rstate[0]_i_1_n_0\,
Q => \^axi4_lite_rvalid\
);
\axi_lite_wstate[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"002E"
)
port map (
I0 => AXI4_Lite_AWVALID,
I1 => axi_lite_wstate(0),
I2 => AXI4_Lite_WVALID,
I3 => axi_lite_wstate(1),
O => \axi_lite_wstate[0]_i_1_n_0\
);
\axi_lite_wstate_next_inferred__1/i_\: unisim.vcomponents.LUT4
generic map(
INIT => X"0838"
)
port map (
I0 => AXI4_Lite_WVALID,
I1 => axi_lite_wstate(0),
I2 => axi_lite_wstate(1),
I3 => AXI4_Lite_BREADY,
O => \axi_lite_wstate_next_inferred__1/i__n_0\
);
\axi_lite_wstate_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => \axi_lite_wstate[0]_i_1_n_0\,
Q => axi_lite_wstate(0)
);
\axi_lite_wstate_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => \axi_lite_wstate_next_inferred__1/i__n_0\,
Q => axi_lite_wstate(1)
);
soft_reset_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200000000"
)
port map (
I0 => soft_reset_i_2_n_0,
I1 => sel0(1),
I2 => sel0(0),
I3 => sel0(7),
I4 => sel0(6),
I5 => soft_reset_i_3_n_0,
O => strobe_sw
);
soft_reset_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => sel0(13),
I1 => sel0(12),
I2 => sel0(11),
I3 => sel0(10),
O => soft_reset_i_2_n_0
);
soft_reset_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00010000"
)
port map (
I0 => sel0(2),
I1 => sel0(3),
I2 => sel0(8),
I3 => sel0(9),
I4 => soft_reset_i_4_n_0,
O => soft_reset_i_3_n_0
);
soft_reset_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => top_wr_enb,
I1 => \^q\(0),
I2 => sel0(5),
I3 => sel0(4),
O => soft_reset_i_4_n_0
);
soft_reset_reg: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => strobe_sw,
Q => soft_reset
);
strobe_reg_cop_in_strobe_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020000000"
)
port map (
I0 => \^q\(0),
I1 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I2 => strobe_reg_cop_in_strobe_i_3_n_0,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I4 => top_wr_enb,
I5 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
O => strobe_sw_cop_in_strobe
);
strobe_reg_cop_in_strobe_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => AXI4_Lite_ARESETN,
I1 => soft_reset,
I2 => IPCORE_RESETN,
O => write_reg_axi_enable_reg
);
strobe_reg_cop_in_strobe_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => sel0(1),
I1 => AXI4_Lite_ARADDR(1),
I2 => sel0(0),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(0),
O => strobe_reg_cop_in_strobe_i_3_n_0
);
\waddr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => AXI4_Lite_AWVALID,
I1 => axi_lite_wstate(1),
I2 => axi_lite_wstate(0),
O => aw_transfer
);
\waddr_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(8),
Q => sel0(8)
);
\waddr_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(9),
Q => sel0(9)
);
\waddr_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(10),
Q => sel0(10)
);
\waddr_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(11),
Q => sel0(11)
);
\waddr_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(12),
Q => sel0(12)
);
\waddr_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(13),
Q => sel0(13)
);
\waddr_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(0),
Q => sel0(0)
);
\waddr_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(1),
Q => sel0(1)
);
\waddr_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(2),
Q => sel0(2)
);
\waddr_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(3),
Q => sel0(3)
);
\waddr_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(4),
Q => sel0(4)
);
\waddr_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(5),
Q => sel0(5)
);
\waddr_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(6),
Q => sel0(6)
);
\waddr_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(7),
Q => sel0(7)
);
\wdata[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => AXI4_Lite_WVALID,
I1 => axi_lite_wstate(1),
I2 => axi_lite_wstate(0),
O => w_transfer
);
\wdata_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(0),
Q => \^q\(0)
);
\wdata_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(10),
Q => \^q\(10)
);
\wdata_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(11),
Q => \^q\(11)
);
\wdata_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(12),
Q => \^q\(12)
);
\wdata_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(13),
Q => \^q\(13)
);
\wdata_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(14),
Q => \^q\(14)
);
\wdata_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(15),
Q => \^q\(15)
);
\wdata_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(1),
Q => \^q\(1)
);
\wdata_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(2),
Q => \^q\(2)
);
\wdata_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(3),
Q => \^q\(3)
);
\wdata_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(4),
Q => \^q\(4)
);
\wdata_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(5),
Q => \^q\(5)
);
\wdata_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(6),
Q => \^q\(6)
);
\wdata_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(7),
Q => \^q\(7)
);
\wdata_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(8),
Q => \^q\(8)
);
\wdata_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(9),
Q => \^q\(9)
);
wr_enb_1_reg: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => w_transfer,
Q => top_wr_enb
);
write_reg_axi_enable_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFFF00008000"
)
port map (
I0 => \^q\(0),
I1 => write_reg_axi_enable_i_2_n_0,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I3 => top_wr_enb,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I5 => write_reg_axi_enable,
O => write_reg_axi_enable_reg_0
);
write_reg_axi_enable_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000047034400"
)
port map (
I0 => AXI4_Lite_ARADDR(6),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(6),
I3 => AXI4_Lite_ARADDR(0),
I4 => sel0(0),
I5 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
O => write_reg_axi_enable_i_2_n_0
);
\write_reg_d_k[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I4 => top_wr_enb,
I5 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
O => \write_reg_d_k_reg[15]\(0)
);
\write_reg_x_k[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I4 => top_wr_enb,
I5 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
O => E(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_lms_pcore_0_0_lms_pcore_cop is
port (
cp_controller_cpstate : out STD_LOGIC_VECTOR ( 1 downto 0 );
cop_out_ready : out STD_LOGIC;
cop_dut_enable : out STD_LOGIC;
strobe_reg_cop_in_strobe_reg : in STD_LOGIC;
IPCORE_CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
write_reg_axi_enable : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_lms_pcore_0_0_lms_pcore_cop : entity is "lms_pcore_cop";
end ip_design_lms_pcore_0_0_lms_pcore_cop;
architecture STRUCTURE of ip_design_lms_pcore_0_0_lms_pcore_cop is
signal \^cp_controller_cpstate\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cp_controller_cpstate[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cp_controller_cpstate[1]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of read_reg_cop_out_ready_i_1 : label is "soft_lutpair5";
begin
cp_controller_cpstate(1 downto 0) <= \^cp_controller_cpstate\(1 downto 0);
\cp_controller_cpstate[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"38"
)
port map (
I0 => \^cp_controller_cpstate\(0),
I1 => write_reg_axi_enable,
I2 => \^cp_controller_cpstate\(1),
O => \cp_controller_cpstate[1]_i_1_n_0\
);
\cp_controller_cpstate_reg[0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => '1',
CLR => AR(0),
D => strobe_reg_cop_in_strobe_reg,
Q => \^cp_controller_cpstate\(0)
);
\cp_controller_cpstate_reg[1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => '1',
CLR => AR(0),
D => \cp_controller_cpstate[1]_i_1_n_0\,
Q => \^cp_controller_cpstate\(1)
);
\data_pipeline_tmp[14][15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^cp_controller_cpstate\(0),
I1 => \^cp_controller_cpstate\(1),
O => cop_dut_enable
);
read_reg_cop_out_ready_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cp_controller_cpstate\(0),
I1 => \^cp_controller_cpstate\(1),
O => cop_out_ready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_lms_pcore_0_0_lms_pcore_axi_lite is
port (
write_reg_axi_enable_reg : out STD_LOGIC;
AXI4_Lite_RVALID : out STD_LOGIC;
write_reg_axi_enable : out STD_LOGIC;
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BVALID : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 14 downto 0 );
\sync_reg_e_k_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\sync_reg_e_k_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\sync_reg_e_k_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
DI : out STD_LOGIC_VECTOR ( 0 to 0 );
\ARG__29\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\cp_controller_cpstate_reg[0]\ : out STD_LOGIC;
\ARG__28\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWREADY : out STD_LOGIC;
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
cop_out_ready : in STD_LOGIC;
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
filter_sum : in STD_LOGIC_VECTOR ( 15 downto 0 );
mul_temp_16 : in STD_LOGIC_VECTOR ( 15 downto 0 );
cp_controller_cpstate : in STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
AXI4_Lite_BREADY : in STD_LOGIC;
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
AXI4_Lite_RREADY : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_lms_pcore_0_0_lms_pcore_axi_lite : entity is "lms_pcore_axi_lite";
end ip_design_lms_pcore_0_0_lms_pcore_axi_lite;
architecture STRUCTURE of ip_design_lms_pcore_0_0_lms_pcore_axi_lite is
signal read_reg_cop_out_ready : STD_LOGIC;
signal reg_enb_d_k : STD_LOGIC;
signal reg_enb_x_k : STD_LOGIC;
signal strobe_sw_cop_in_strobe : STD_LOGIC;
signal sync_reg_e_k : STD_LOGIC_VECTOR ( 15 downto 0 );
signal top_data_write : STD_LOGIC_VECTOR ( 0 to 0 );
signal u_lms_pcore_axi_lite_module_inst_n_10 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_11 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_12 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_13 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_14 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_15 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_16 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_17 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_18 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_19 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_4 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_5 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_6 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_7 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_8 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_9 : STD_LOGIC;
signal \^write_reg_axi_enable\ : STD_LOGIC;
signal \^write_reg_axi_enable_reg\ : STD_LOGIC;
begin
write_reg_axi_enable <= \^write_reg_axi_enable\;
write_reg_axi_enable_reg <= \^write_reg_axi_enable_reg\;
u_lms_pcore_addr_decoder_inst: entity work.ip_design_lms_pcore_0_0_lms_pcore_addr_decoder
port map (
AR(0) => \^write_reg_axi_enable_reg\,
\ARG__28\(15 downto 0) => \ARG__28\(15 downto 0),
\ARG__29\(2 downto 0) => \ARG__29\(2 downto 0),
AXI4_Lite_ACLK => AXI4_Lite_ACLK,
\AXI4_Lite_RDATA_tmp_reg[31]\(15 downto 0) => sync_reg_e_k(15 downto 0),
DI(0) => DI(0),
E(0) => reg_enb_x_k,
Q(14 downto 0) => Q(14 downto 0),
S(3 downto 0) => S(3 downto 0),
cop_out_ready => cop_out_ready,
cp_controller_cpstate(1 downto 0) => cp_controller_cpstate(1 downto 0),
\cp_controller_cpstate_reg[0]\ => \cp_controller_cpstate_reg[0]\,
filter_sum(15 downto 0) => filter_sum(15 downto 0),
mul_temp_16(15 downto 0) => mul_temp_16(15 downto 0),
read_reg_cop_out_ready => read_reg_cop_out_ready,
strobe_sw_cop_in_strobe => strobe_sw_cop_in_strobe,
\sync_reg_e_k_reg[11]_0\(3 downto 0) => \sync_reg_e_k_reg[11]\(3 downto 0),
\sync_reg_e_k_reg[3]_0\(3 downto 0) => \sync_reg_e_k_reg[3]\(3 downto 0),
\sync_reg_e_k_reg[7]_0\(3 downto 0) => \sync_reg_e_k_reg[7]\(3 downto 0),
\wdata_reg[0]\ => u_lms_pcore_axi_lite_module_inst_n_4,
\wdata_reg[15]\(15) => u_lms_pcore_axi_lite_module_inst_n_5,
\wdata_reg[15]\(14) => u_lms_pcore_axi_lite_module_inst_n_6,
\wdata_reg[15]\(13) => u_lms_pcore_axi_lite_module_inst_n_7,
\wdata_reg[15]\(12) => u_lms_pcore_axi_lite_module_inst_n_8,
\wdata_reg[15]\(11) => u_lms_pcore_axi_lite_module_inst_n_9,
\wdata_reg[15]\(10) => u_lms_pcore_axi_lite_module_inst_n_10,
\wdata_reg[15]\(9) => u_lms_pcore_axi_lite_module_inst_n_11,
\wdata_reg[15]\(8) => u_lms_pcore_axi_lite_module_inst_n_12,
\wdata_reg[15]\(7) => u_lms_pcore_axi_lite_module_inst_n_13,
\wdata_reg[15]\(6) => u_lms_pcore_axi_lite_module_inst_n_14,
\wdata_reg[15]\(5) => u_lms_pcore_axi_lite_module_inst_n_15,
\wdata_reg[15]\(4) => u_lms_pcore_axi_lite_module_inst_n_16,
\wdata_reg[15]\(3) => u_lms_pcore_axi_lite_module_inst_n_17,
\wdata_reg[15]\(2) => u_lms_pcore_axi_lite_module_inst_n_18,
\wdata_reg[15]\(1) => u_lms_pcore_axi_lite_module_inst_n_19,
\wdata_reg[15]\(0) => top_data_write(0),
wr_enb_1_reg(0) => reg_enb_d_k,
write_reg_axi_enable => \^write_reg_axi_enable\
);
u_lms_pcore_axi_lite_module_inst: entity work.ip_design_lms_pcore_0_0_lms_pcore_axi_lite_module
port map (
AXI4_Lite_ACLK => AXI4_Lite_ACLK,
AXI4_Lite_ARADDR(13 downto 0) => AXI4_Lite_ARADDR(13 downto 0),
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN,
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY,
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID,
AXI4_Lite_AWADDR(13 downto 0) => AXI4_Lite_AWADDR(13 downto 0),
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY,
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID,
AXI4_Lite_BREADY => AXI4_Lite_BREADY,
AXI4_Lite_BVALID => AXI4_Lite_BVALID,
AXI4_Lite_RDATA(15 downto 0) => AXI4_Lite_RDATA(15 downto 0),
AXI4_Lite_RREADY => AXI4_Lite_RREADY,
AXI4_Lite_RVALID => AXI4_Lite_RVALID,
AXI4_Lite_WDATA(15 downto 0) => AXI4_Lite_WDATA(15 downto 0),
AXI4_Lite_WREADY => AXI4_Lite_WREADY,
AXI4_Lite_WVALID => AXI4_Lite_WVALID,
E(0) => reg_enb_x_k,
IPCORE_RESETN => IPCORE_RESETN,
Q(15) => u_lms_pcore_axi_lite_module_inst_n_5,
Q(14) => u_lms_pcore_axi_lite_module_inst_n_6,
Q(13) => u_lms_pcore_axi_lite_module_inst_n_7,
Q(12) => u_lms_pcore_axi_lite_module_inst_n_8,
Q(11) => u_lms_pcore_axi_lite_module_inst_n_9,
Q(10) => u_lms_pcore_axi_lite_module_inst_n_10,
Q(9) => u_lms_pcore_axi_lite_module_inst_n_11,
Q(8) => u_lms_pcore_axi_lite_module_inst_n_12,
Q(7) => u_lms_pcore_axi_lite_module_inst_n_13,
Q(6) => u_lms_pcore_axi_lite_module_inst_n_14,
Q(5) => u_lms_pcore_axi_lite_module_inst_n_15,
Q(4) => u_lms_pcore_axi_lite_module_inst_n_16,
Q(3) => u_lms_pcore_axi_lite_module_inst_n_17,
Q(2) => u_lms_pcore_axi_lite_module_inst_n_18,
Q(1) => u_lms_pcore_axi_lite_module_inst_n_19,
Q(0) => top_data_write(0),
read_reg_cop_out_ready => read_reg_cop_out_ready,
strobe_sw_cop_in_strobe => strobe_sw_cop_in_strobe,
\sync_reg_e_k_reg[15]\(15 downto 0) => sync_reg_e_k(15 downto 0),
write_reg_axi_enable => \^write_reg_axi_enable\,
write_reg_axi_enable_reg => \^write_reg_axi_enable_reg\,
write_reg_axi_enable_reg_0 => u_lms_pcore_axi_lite_module_inst_n_4,
\write_reg_d_k_reg[15]\(0) => reg_enb_d_k
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_lms_pcore_0_0_lms_pcore_dut is
port (
mul_temp_16 : out STD_LOGIC_VECTOR ( 15 downto 0 );
filter_sum : out STD_LOGIC_VECTOR ( 15 downto 0 );
\write_reg_x_k_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
cop_dut_enable : in STD_LOGIC;
IPCORE_CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\write_reg_d_k_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
DI : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 14 downto 0 );
\write_reg_d_k_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\write_reg_d_k_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\write_reg_d_k_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_lms_pcore_0_0_lms_pcore_dut : entity is "lms_pcore_dut";
end ip_design_lms_pcore_0_0_lms_pcore_dut;
architecture STRUCTURE of ip_design_lms_pcore_0_0_lms_pcore_dut is
begin
u_LMS: entity work.ip_design_lms_pcore_0_0_LMS
port map (
AR(0) => AR(0),
DI(0) => DI(0),
IPCORE_CLK => IPCORE_CLK,
Q(14 downto 0) => Q(14 downto 0),
S(3 downto 0) => S(3 downto 0),
cop_dut_enable => cop_dut_enable,
filter_sum(15 downto 0) => filter_sum(15 downto 0),
mul_temp_16(15 downto 0) => mul_temp_16(15 downto 0),
\write_reg_d_k_reg[11]\(3 downto 0) => \write_reg_d_k_reg[11]\(3 downto 0),
\write_reg_d_k_reg[3]\(2 downto 0) => \write_reg_d_k_reg[3]\(2 downto 0),
\write_reg_d_k_reg[3]_0\(3 downto 0) => \write_reg_d_k_reg[3]_0\(3 downto 0),
\write_reg_d_k_reg[7]\(3 downto 0) => \write_reg_d_k_reg[7]\(3 downto 0),
\write_reg_x_k_reg[15]\(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_lms_pcore_0_0_lms_pcore is
port (
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BVALID : out STD_LOGIC;
AXI4_Lite_RVALID : out STD_LOGIC;
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_AWREADY : out STD_LOGIC;
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ACLK : in STD_LOGIC;
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
IPCORE_CLK : in STD_LOGIC;
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
AXI4_Lite_RREADY : in STD_LOGIC;
AXI4_Lite_BREADY : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_lms_pcore_0_0_lms_pcore : entity is "lms_pcore";
end ip_design_lms_pcore_0_0_lms_pcore;
architecture STRUCTURE of ip_design_lms_pcore_0_0_lms_pcore is
signal cop_dut_enable : STD_LOGIC;
signal cop_out_ready : STD_LOGIC;
signal cp_controller_cpstate : STD_LOGIC_VECTOR ( 1 downto 0 );
signal filter_sum : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \u_LMS/mul_temp_16\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal u_lms_pcore_axi_lite_inst_n_0 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_24 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_25 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_26 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_27 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_28 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_29 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_30 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_31 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_32 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_33 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_34 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_35 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_36 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_37 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_38 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_39 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_40 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_5 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_6 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_7 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_8 : STD_LOGIC;
signal write_reg_axi_enable : STD_LOGIC;
signal write_reg_d_k : STD_LOGIC_VECTOR ( 14 downto 0 );
signal write_reg_x_k : STD_LOGIC_VECTOR ( 15 downto 0 );
begin
u_lms_pcore_axi_lite_inst: entity work.ip_design_lms_pcore_0_0_lms_pcore_axi_lite
port map (
\ARG__28\(15 downto 0) => write_reg_x_k(15 downto 0),
\ARG__29\(2) => u_lms_pcore_axi_lite_inst_n_37,
\ARG__29\(1) => u_lms_pcore_axi_lite_inst_n_38,
\ARG__29\(0) => u_lms_pcore_axi_lite_inst_n_39,
AXI4_Lite_ACLK => AXI4_Lite_ACLK,
AXI4_Lite_ARADDR(13 downto 0) => AXI4_Lite_ARADDR(13 downto 0),
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN,
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY,
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID,
AXI4_Lite_AWADDR(13 downto 0) => AXI4_Lite_AWADDR(13 downto 0),
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY,
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID,
AXI4_Lite_BREADY => AXI4_Lite_BREADY,
AXI4_Lite_BVALID => AXI4_Lite_BVALID,
AXI4_Lite_RDATA(15 downto 0) => AXI4_Lite_RDATA(15 downto 0),
AXI4_Lite_RREADY => AXI4_Lite_RREADY,
AXI4_Lite_RVALID => AXI4_Lite_RVALID,
AXI4_Lite_WDATA(15 downto 0) => AXI4_Lite_WDATA(15 downto 0),
AXI4_Lite_WREADY => AXI4_Lite_WREADY,
AXI4_Lite_WVALID => AXI4_Lite_WVALID,
DI(0) => u_lms_pcore_axi_lite_inst_n_36,
IPCORE_RESETN => IPCORE_RESETN,
Q(14 downto 0) => write_reg_d_k(14 downto 0),
S(3) => u_lms_pcore_axi_lite_inst_n_5,
S(2) => u_lms_pcore_axi_lite_inst_n_6,
S(1) => u_lms_pcore_axi_lite_inst_n_7,
S(0) => u_lms_pcore_axi_lite_inst_n_8,
cop_out_ready => cop_out_ready,
cp_controller_cpstate(1 downto 0) => cp_controller_cpstate(1 downto 0),
\cp_controller_cpstate_reg[0]\ => u_lms_pcore_axi_lite_inst_n_40,
filter_sum(15 downto 0) => filter_sum(15 downto 0),
mul_temp_16(15 downto 0) => \u_LMS/mul_temp_16\(15 downto 0),
\sync_reg_e_k_reg[11]\(3) => u_lms_pcore_axi_lite_inst_n_24,
\sync_reg_e_k_reg[11]\(2) => u_lms_pcore_axi_lite_inst_n_25,
\sync_reg_e_k_reg[11]\(1) => u_lms_pcore_axi_lite_inst_n_26,
\sync_reg_e_k_reg[11]\(0) => u_lms_pcore_axi_lite_inst_n_27,
\sync_reg_e_k_reg[3]\(3) => u_lms_pcore_axi_lite_inst_n_32,
\sync_reg_e_k_reg[3]\(2) => u_lms_pcore_axi_lite_inst_n_33,
\sync_reg_e_k_reg[3]\(1) => u_lms_pcore_axi_lite_inst_n_34,
\sync_reg_e_k_reg[3]\(0) => u_lms_pcore_axi_lite_inst_n_35,
\sync_reg_e_k_reg[7]\(3) => u_lms_pcore_axi_lite_inst_n_28,
\sync_reg_e_k_reg[7]\(2) => u_lms_pcore_axi_lite_inst_n_29,
\sync_reg_e_k_reg[7]\(1) => u_lms_pcore_axi_lite_inst_n_30,
\sync_reg_e_k_reg[7]\(0) => u_lms_pcore_axi_lite_inst_n_31,
write_reg_axi_enable => write_reg_axi_enable,
write_reg_axi_enable_reg => u_lms_pcore_axi_lite_inst_n_0
);
u_lms_pcore_cop_inst: entity work.ip_design_lms_pcore_0_0_lms_pcore_cop
port map (
AR(0) => u_lms_pcore_axi_lite_inst_n_0,
IPCORE_CLK => IPCORE_CLK,
cop_dut_enable => cop_dut_enable,
cop_out_ready => cop_out_ready,
cp_controller_cpstate(1 downto 0) => cp_controller_cpstate(1 downto 0),
strobe_reg_cop_in_strobe_reg => u_lms_pcore_axi_lite_inst_n_40,
write_reg_axi_enable => write_reg_axi_enable
);
u_lms_pcore_dut_inst: entity work.ip_design_lms_pcore_0_0_lms_pcore_dut
port map (
AR(0) => u_lms_pcore_axi_lite_inst_n_0,
DI(0) => u_lms_pcore_axi_lite_inst_n_36,
IPCORE_CLK => IPCORE_CLK,
Q(14 downto 0) => write_reg_d_k(14 downto 0),
S(3) => u_lms_pcore_axi_lite_inst_n_5,
S(2) => u_lms_pcore_axi_lite_inst_n_6,
S(1) => u_lms_pcore_axi_lite_inst_n_7,
S(0) => u_lms_pcore_axi_lite_inst_n_8,
cop_dut_enable => cop_dut_enable,
filter_sum(15 downto 0) => filter_sum(15 downto 0),
mul_temp_16(15 downto 0) => \u_LMS/mul_temp_16\(15 downto 0),
\write_reg_d_k_reg[11]\(3) => u_lms_pcore_axi_lite_inst_n_24,
\write_reg_d_k_reg[11]\(2) => u_lms_pcore_axi_lite_inst_n_25,
\write_reg_d_k_reg[11]\(1) => u_lms_pcore_axi_lite_inst_n_26,
\write_reg_d_k_reg[11]\(0) => u_lms_pcore_axi_lite_inst_n_27,
\write_reg_d_k_reg[3]\(2) => u_lms_pcore_axi_lite_inst_n_37,
\write_reg_d_k_reg[3]\(1) => u_lms_pcore_axi_lite_inst_n_38,
\write_reg_d_k_reg[3]\(0) => u_lms_pcore_axi_lite_inst_n_39,
\write_reg_d_k_reg[3]_0\(3) => u_lms_pcore_axi_lite_inst_n_32,
\write_reg_d_k_reg[3]_0\(2) => u_lms_pcore_axi_lite_inst_n_33,
\write_reg_d_k_reg[3]_0\(1) => u_lms_pcore_axi_lite_inst_n_34,
\write_reg_d_k_reg[3]_0\(0) => u_lms_pcore_axi_lite_inst_n_35,
\write_reg_d_k_reg[7]\(3) => u_lms_pcore_axi_lite_inst_n_28,
\write_reg_d_k_reg[7]\(2) => u_lms_pcore_axi_lite_inst_n_29,
\write_reg_d_k_reg[7]\(1) => u_lms_pcore_axi_lite_inst_n_30,
\write_reg_d_k_reg[7]\(0) => u_lms_pcore_axi_lite_inst_n_31,
\write_reg_x_k_reg[15]\(15 downto 0) => write_reg_x_k(15 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_lms_pcore_0_0 is
port (
IPCORE_CLK : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
AXI4_Lite_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_BREADY : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_RREADY : in STD_LOGIC;
AXI4_Lite_AWREADY : out STD_LOGIC;
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_BVALID : out STD_LOGIC;
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
AXI4_Lite_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_RVALID : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ip_design_lms_pcore_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of ip_design_lms_pcore_0_0 : entity is "ip_design_lms_pcore_0_0,lms_pcore,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of ip_design_lms_pcore_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of ip_design_lms_pcore_0_0 : entity is "lms_pcore,Vivado 2017.3";
end ip_design_lms_pcore_0_0;
architecture STRUCTURE of ip_design_lms_pcore_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \^axi4_lite_rdata\ : STD_LOGIC_VECTOR ( 30 downto 0 );
attribute x_interface_info : string;
attribute x_interface_info of AXI4_Lite_ACLK : signal is "xilinx.com:signal:clock:1.0 AXI4_Lite_ACLK CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of AXI4_Lite_ACLK : signal is "XIL_INTERFACENAME AXI4_Lite_ACLK, ASSOCIATED_RESET AXI4_Lite_ARESETN, ASSOCIATED_BUSIF AXI4_Lite, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of AXI4_Lite_ARESETN : signal is "xilinx.com:signal:reset:1.0 AXI4_Lite_ARESETN RST";
attribute x_interface_parameter of AXI4_Lite_ARESETN : signal is "XIL_INTERFACENAME AXI4_Lite_ARESETN, POLARITY ACTIVE_LOW";
attribute x_interface_info of AXI4_Lite_ARREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite ARREADY";
attribute x_interface_info of AXI4_Lite_ARVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite ARVALID";
attribute x_interface_info of AXI4_Lite_AWREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite AWREADY";
attribute x_interface_info of AXI4_Lite_AWVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite AWVALID";
attribute x_interface_info of AXI4_Lite_BREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite BREADY";
attribute x_interface_info of AXI4_Lite_BVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite BVALID";
attribute x_interface_info of AXI4_Lite_RREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite RREADY";
attribute x_interface_info of AXI4_Lite_RVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite RVALID";
attribute x_interface_info of AXI4_Lite_WREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite WREADY";
attribute x_interface_info of AXI4_Lite_WVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite WVALID";
attribute x_interface_info of IPCORE_CLK : signal is "xilinx.com:signal:clock:1.0 IPCORE_CLK CLK";
attribute x_interface_parameter of IPCORE_CLK : signal is "XIL_INTERFACENAME IPCORE_CLK, ASSOCIATED_RESET IPCORE_RESETN, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of IPCORE_RESETN : signal is "xilinx.com:signal:reset:1.0 IPCORE_RESETN RST";
attribute x_interface_parameter of IPCORE_RESETN : signal is "XIL_INTERFACENAME IPCORE_RESETN, POLARITY ACTIVE_LOW";
attribute x_interface_info of AXI4_Lite_ARADDR : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite ARADDR";
attribute x_interface_info of AXI4_Lite_AWADDR : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite AWADDR";
attribute x_interface_parameter of AXI4_Lite_AWADDR : signal is "XIL_INTERFACENAME AXI4_Lite, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute x_interface_info of AXI4_Lite_BRESP : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite BRESP";
attribute x_interface_info of AXI4_Lite_RDATA : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite RDATA";
attribute x_interface_info of AXI4_Lite_RRESP : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite RRESP";
attribute x_interface_info of AXI4_Lite_WDATA : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite WDATA";
attribute x_interface_info of AXI4_Lite_WSTRB : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite WSTRB";
begin
AXI4_Lite_BRESP(1) <= \<const0>\;
AXI4_Lite_BRESP(0) <= \<const0>\;
AXI4_Lite_RDATA(31) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(30) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(29) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(28) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(27) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(26) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(25) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(24) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(23) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(22) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(21) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(20) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(19) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(18) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(17) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(16) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(15) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(14 downto 0) <= \^axi4_lite_rdata\(14 downto 0);
AXI4_Lite_RRESP(1) <= \<const0>\;
AXI4_Lite_RRESP(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.ip_design_lms_pcore_0_0_lms_pcore
port map (
AXI4_Lite_ACLK => AXI4_Lite_ACLK,
AXI4_Lite_ARADDR(13 downto 0) => AXI4_Lite_ARADDR(15 downto 2),
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN,
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY,
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID,
AXI4_Lite_AWADDR(13 downto 0) => AXI4_Lite_AWADDR(15 downto 2),
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY,
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID,
AXI4_Lite_BREADY => AXI4_Lite_BREADY,
AXI4_Lite_BVALID => AXI4_Lite_BVALID,
AXI4_Lite_RDATA(15) => \^axi4_lite_rdata\(30),
AXI4_Lite_RDATA(14 downto 0) => \^axi4_lite_rdata\(14 downto 0),
AXI4_Lite_RREADY => AXI4_Lite_RREADY,
AXI4_Lite_RVALID => AXI4_Lite_RVALID,
AXI4_Lite_WDATA(15 downto 0) => AXI4_Lite_WDATA(15 downto 0),
AXI4_Lite_WREADY => AXI4_Lite_WREADY,
AXI4_Lite_WVALID => AXI4_Lite_WVALID,
IPCORE_CLK => IPCORE_CLK,
IPCORE_RESETN => IPCORE_RESETN
);
end STRUCTURE;
| mit | 95e5772bc89fcac5003c1bc8fa21a39e | 0.528944 | 2.587924 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution_OH/impl/verilog/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_3_max_dsp_32/synth/convolve_kernel_ap_fmul_3_max_dsp_32.vhd | 1 | 12,825 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY convolve_kernel_ap_fmul_3_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END convolve_kernel_ap_fmul_3_max_dsp_32;
ARCHITECTURE convolve_kernel_ap_fmul_3_max_dsp_32_arch OF convolve_kernel_ap_fmul_3_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_4,Vivado 2017.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fmul_3_max_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fmul_3_max_dsp_32,floating_point_v7_1_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fmul_3_max_dsp_32,floating_point_v7_1_4,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_F" &
"MS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0" &
",C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END convolve_kernel_ap_fmul_3_max_dsp_32_arch;
| mit | b2f05a2525e6ab624cf47f5519d291ad | 0.651618 | 3.006329 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-c5ekit/lpddr2if.vhd | 1 | 8,335 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
entity lpddr2if is
generic (
hindex: integer;
haddr: integer := 16#400#;
hmask: integer := 16#000#;
burstlen: integer := 8
);
port (
pll_ref_clk: in std_ulogic;
global_reset_n: in std_ulogic;
mem_ca: out std_logic_vector(9 downto 0);
mem_ck: out std_ulogic;
mem_ck_n: out std_ulogic;
mem_cke: out std_ulogic;
mem_cs_n: out std_ulogic;
mem_dm: out std_logic_vector(1 downto 0);
mem_dq: inout std_logic_vector(15 downto 0);
mem_dqs: inout std_logic_vector(1 downto 0);
mem_dqs_n: inout std_logic_vector(1 downto 0);
oct_rzqin: in std_logic;
ahb_clk: in std_ulogic;
ahb_rst: in std_ulogic;
ahbsi: in ahb_slv_in_type;
ahbso: out ahb_slv_out_type
);
end;
architecture rtl of lpddr2if is
component lpddr2ctrl1 is
port (
pll_ref_clk : in std_logic := 'X'; -- clk
global_reset_n : in std_logic := 'X'; -- reset_n
soft_reset_n : in std_logic := 'X'; -- reset_n
afi_clk : out std_logic; -- clk
afi_half_clk : out std_logic; -- clk
afi_reset_n : out std_logic; -- reset_n
afi_reset_export_n : out std_logic; -- reset_n
mem_ca : out std_logic_vector(9 downto 0); -- mem_ca
mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_dm : out std_logic_vector(1 downto 0); -- mem_dm
mem_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs_n
avl_ready : out std_logic; -- waitrequest_n
avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer
avl_addr : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
avl_rdata_valid : out std_logic; -- readdatavalid
avl_rdata : out std_logic_vector(63 downto 0); -- readdata
avl_wdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- writedata
avl_be : in std_logic_vector(7 downto 0) := (others => 'X'); -- byteenable
avl_read_req : in std_logic := 'X'; -- read
avl_write_req : in std_logic := 'X'; -- write
avl_size : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
local_init_done : out std_logic; -- local_init_done
local_cal_success : out std_logic; -- local_cal_success
local_cal_fail : out std_logic; -- local_cal_fail
oct_rzqin : in std_logic := 'X'; -- rzqin
pll_mem_clk : out std_logic; -- pll_mem_clk
pll_write_clk : out std_logic; -- pll_write_clk
pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk
pll_locked : out std_logic; -- pll_locked
pll_avl_clk : out std_logic; -- pll_avl_clk
pll_config_clk : out std_logic; -- pll_config_clk
pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk
afi_phy_clk : out std_logic; -- afi_phy_clk
pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk
);
end component lpddr2ctrl1;
signal vcc: std_ulogic;
signal afi_clk, afi_half_clk, afi_reset_n: std_ulogic;
signal local_init_done, local_cal_success, local_cal_fail: std_ulogic;
signal ck_p_arr, ck_n_arr, cke_arr, cs_arr: std_logic_vector(0 downto 0);
signal avlsi: ddravl_slv_in_type;
signal avlso: ddravl_slv_out_type;
begin
vcc <= '1';
mem_ck <= ck_p_arr(0);
mem_ck_n <= ck_n_arr(0);
mem_cke <= cke_arr(0);
mem_cs_n <= cs_arr(0);
ctrl0: lpddr2ctrl1
port map (
pll_ref_clk => pll_ref_clk,
global_reset_n => global_reset_n,
soft_reset_n => vcc,
afi_clk => afi_clk,
afi_half_clk => afi_half_clk,
afi_reset_n => afi_reset_n,
afi_reset_export_n => open,
mem_ca => mem_ca,
mem_ck => ck_p_arr,
mem_ck_n => ck_n_arr,
mem_cke => cke_arr,
mem_cs_n => cs_arr,
mem_dm => mem_dm,
mem_dq => mem_dq,
mem_dqs => mem_dqs,
mem_dqs_n => mem_dqs_n,
avl_ready => avlso.ready,
avl_burstbegin => avlsi.burstbegin,
avl_addr => avlsi.addr(24 downto 0),
avl_rdata_valid => avlso.rdata_valid,
avl_rdata => avlso.rdata(63 downto 0),
avl_wdata => avlsi.wdata(63 downto 0),
avl_be => avlsi.be(7 downto 0),
avl_read_req => avlsi.read_req,
avl_write_req => avlsi.write_req,
avl_size => avlsi.size(2 downto 0),
local_init_done => local_init_done,
local_cal_success => local_cal_success,
local_cal_fail => local_cal_fail,
oct_rzqin => oct_rzqin,
pll_mem_clk => open,
pll_write_clk => open,
pll_write_clk_pre_phy_clk => open,
pll_addr_cmd_clk => open,
pll_locked => open,
pll_avl_clk => open,
pll_config_clk => open,
pll_mem_phy_clk => open,
afi_phy_clk => open,
pll_avl_phy_clk => open
);
avlso.rdata(avlso.rdata'high downto 64) <= (others => '0');
ahb2avl0: ahb2avl_async
generic map (
hindex => hindex,
haddr => haddr,
hmask => hmask,
burstlen => burstlen,
nosync => 0,
avldbits => 64,
avlabits => 25
)
port map (
rst_ahb => ahb_rst,
clk_ahb => ahb_clk,
ahbsi => ahbsi,
ahbso => ahbso,
rst_avl => afi_reset_n,
clk_avl => afi_clk,
avlsi => avlsi,
avlso => avlso
);
end;
| gpl-2.0 | 32f76fad11bd50deba0ac3061672743a | 0.475225 | 3.658911 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-terasic-de4/testbench.vhd | 1 | 23,633 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use gaisler.net.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romdepth : integer := 25; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
-- clocks
signal OSC_50_BANK2 : std_logic := '0';
signal OSC_50_BANK3 : std_logic := '0';
signal OSC_50_BANK4 : std_logic := '0';
signal OSC_50_BANK5 : std_logic := '0';
signal OSC_50_BANK6 : std_logic := '0';
signal OSC_50_BANK7 : std_logic := '0';
signal PLL_CLKIN_p : std_logic := '0';
signal SMA_CLKIN_p : std_logic := '0';
--signal SMA_GXBCLK_p : std_logic;
signal GCLKIN : std_logic := '0';
-- signal GCLKOUT_FPGA : std_logic := '0';
-- signal SMA_CLKOUT_p : std_logic := '0';
signal clk_125 : std_logic := '0';
-- cpu reset
signal CPU_RESET_n : std_ulogic := '0';
-- max i/o
-- signal MAX_CONF_D : std_logic_vector(3 downto 0);
-- signal MAX_I2C_SCLK : std_logic;
-- signal MAX_I2C_SDAT : std_logic;
-- LEDs
signal LED : std_logic_vector(7 downto 0);
-- buttons
signal BUTTON : std_logic_vector(3 downto 0);
-- switches
signal SW : std_logic_vector(3 downto 0);
-- slide switches
signal SLIDE_SW : std_logic_vector(3 downto 0);
-- temperature
-- signal TEMP_SMCLK : std_logic;
-- signal TEMP_SMDAT : std_logic;
-- signal TEMP_INT_n : std_logic;
-- current
signal CSENSE_ADC_FO : std_logic;
signal CSENSE_SCK : std_logic;
signal CSENSE_SDI : std_logic;
signal CSENSE_SDO : std_logic;
signal CSENSE_CS_n : std_logic_vector(1 downto 0);
-- fan
signal FAN_CTRL : std_logic;
-- eeprom
signal EEP_SCL : std_logic;
signal EEP_SDA : std_logic;
-- sdcard
-- signal SD_CLK : std_logic;
-- signal SD_CMD : std_logic;
-- signal SD_DAT : std_logic_vector(3 downto 0);
-- signal SD_WP_n : std_logic;
-- Ethernet interfaces
signal ETH_INT_n : std_logic_vector(3 downto 0);
signal ETH_MDC : std_logic_vector(3 downto 0);
signal ETH_MDIO : std_logic_vector(3 downto 0);
signal ETH_RST_n : std_ulogic;
signal ETH_RX_p : std_logic_vector(3 downto 0);
signal ETH_TX_p : std_logic_vector(3 downto 0);
-- PCIe interfaces
--signal PCIE_PREST_n : std_ulogic;
--signal PCIE_REFCLK_p : std_ulogic;
--signal PCIE_RX_p : std_logic_vector(7 downto 0);
--signal PCIE_SMBCLK : std_logic;
--signal PCIE_SMBDAT : std_logic;
--signal PCIE_TX_p : std_logic_vector(7 downto 0);
--signal PCIE_WAKE_n : std_logic;
-- Flash and SRAM, shared signals
signal FSM_A : std_logic_vector(25 downto 1);
signal FSM_D : std_logic_vector(15 downto 0);
-- Flash control
signal FLASH_ADV_n : std_ulogic;
signal FLASH_CE_n : std_ulogic;
signal FLASH_CLK : std_ulogic;
signal FLASH_OE_n : std_ulogic;
signal FLASH_RESET_n : std_ulogic;
signal FLASH_RYBY_n : std_ulogic;
signal FLASH_WE_n : std_ulogic;
-- SSRAM control
signal SSRAM_ADV : std_ulogic;
signal SSRAM_BWA_n : std_ulogic;
signal SSRAM_BWB_n : std_ulogic;
signal SSRAM_CE_n : std_ulogic;
signal SSRAM_CKE_n : std_ulogic;
signal SSRAM_CLK : std_ulogic;
signal SSRAM_OE_n : std_ulogic;
signal SSRAM_WE_n : std_ulogic;
-- USB OTG
--signal OTG_A : std_logic_vector(17 downto 1);
--signal OTG_CS_n : std_ulogic;
--signal OTG_D : std_logic_vector(31 downto 0);
--signal OTG_DC_DACK : std_ulogic;
--signal OTG_DC_DREQ : std_ulogic;
--signal OTG_DC_IRQ : std_ulogic;
--signal OTG_HC_DACK : std_ulogic;
--signal OTG_HC_DREQ : std_ulogic;
--signal OTG_HC_IRQ : std_ulogic;
--signal OTG_OE_n : std_ulogic;
--signal OTG_RESET_n : std_ulogic;
--signal OTG_WE_n : std_ulogic;
-- SATA
--signal SATA_REFCLK_p : std_logic;
--signal SATA_HOST_RX_p : std_logic_vector(1 downto 0);
--signal SATA_HOST_TX_p : std_logic_vector(1 downto 0);
--signal SATA_DEVICE_RX_p : std_logic_vector(1 downto 0);
--signal SATA_DEVICE_TX_p : std_logic_vector(1 downto 0);
-- DDR2 SODIMM
signal M1_DDR2_addr : std_logic_vector(15 downto 0);
signal M1_DDR2_ba : std_logic_vector(2 downto 0);
signal M1_DDR2_cas_n : std_logic;
signal M1_DDR2_cke : std_logic_vector(1 downto 0);
signal M1_DDR2_clk : std_logic_vector(1 downto 0);
signal M1_DDR2_clk_n : std_logic_vector(1 downto 0);
signal M1_DDR2_cs_n : std_logic_vector(1 downto 0);
signal M1_DDR2_dm : std_logic_vector(7 downto 0);
signal M1_DDR2_dq : std_logic_vector(63 downto 0);
signal M1_DDR2_dqs : std_logic_vector(7 downto 0);
signal M1_DDR2_dqsn : std_logic_vector(7 downto 0);
signal M1_DDR2_odt : std_logic_vector(1 downto 0);
signal M1_DDR2_ras_n : std_logic;
-- signal M1_DDR2_SA : std_logic_vector(1 downto 0);
-- signal M1_DDR2_SCL : std_logic;
-- signal M1_DDR2_SDA : std_logic;
signal M1_DDR2_we_n : std_logic;
signal M1_DDR2_oct_rdn : std_logic;
signal M1_DDR2_oct_rup : std_logic;
-- DDR2 SODIMM
--signal M2_DDR2_addr : std_logic_vector(15 downto 0);
--signal M2_DDR2_ba : std_logic_vector(2 downto 0);
--signal M2_DDR2_cas_n : std_logic;
--signal M2_DDR2_cke : std_logic_vector(1 downto 0);
--signal M2_DDR2_clk : std_logic_vector(1 downto 0);
--signal M2_DDR2_clk_n : std_logic_vector(1 downto 0);
--signal M2_DDR2_cs_n : std_logic_vector(1 downto 0);
--signal M2_DDR2_dm : std_logic_vector(7 downto 0);
--signal M2_DDR2_dq : std_logic_vector(63 downto 0);
--signal M2_DDR2_dqs : std_logic_vector(7 downto 0);
--signal M2_DDR2_dqsn : std_logic_vector(7 downto 0);
--signal M2_DDR2_odt : std_logic_vector(1 downto 0);
--signal M2_DDR2_ras_n : std_logic;
--signal M2_DDR2_SA : std_logic_vector(1 downto 0);
--signal M2_DDR2_SCL : std_logic;
--signal M2_DDR2_SDA : std_logic;
--signal M2_DDR2_we_n : std_logic;
-- GPIO
signal GPIO0_D : std_logic_vector(35 downto 0);
-- signal GPIO1_D : std_logic_vector(35 downto 0);
-- Ext I/O
signal EXT_IO : std_logic;
-- HSMC A
-- signal HSMA_CLKIN_n1 : std_logic;
-- signal HSMA_CLKIN_n2 : std_logic;
-- signal HSMA_CLKIN_p1 : std_logic;
-- signal HSMA_CLKIN_p2 : std_logic;
-- signal HSMA_CLKIN0 : std_logic;
signal HSMA_CLKOUT_n2 : std_logic;
signal HSMA_CLKOUT_p2 : std_logic;
-- signal HSMA_D : std_logic_vector(3 downto 0);
-- HSMA_GXB_RX_p : std_logic_vector(3 downto 0);
-- HSMA_GXB_TX_p : std_logic_vector(3 downto 0);
-- signal HSMA_OUT_n1 : std_logic;
-- signal HSMA_OUT_p1 : std_logic;
-- signal HSMA_OUT0 : std_logic;
-- HSMA_REFCLK_p : in std_logic;
-- signal HSMA_RX_n : std_logic_vector(16 downto 0);
-- signal HSMA_RX_p : std_logic_vector(16 downto 0);
-- signal HSMA_TX_n : std_logic_vector(16 downto 0);
-- signal HSMA_TX_p : std_logic_vector(16 downto 0);
-- HSMC_B
-- signal HSMB_CLKIN_n1 : std_logic;
-- signal HSMB_CLKIN_n2 : std_logic;
-- signal HSMB_CLKIN_p1 : std_logic;
-- signal HSMB_CLKIN_p2 : std_logic;
-- signal HSMB_CLKIN0 : std_logic;
-- signal HSMB_CLKOUT_n2 : std_logic;
-- signal HSMB_CLKOUT_p2 : std_logic;
-- signal HSMB_D : std_logic_vector(3 downto 0);
-- signal HSMB_GXB_RX_p : in std_logic_vector(3 downto 0);
-- signal HSMB_GXB_TX_p : out std_logic_vector(3 downto 0);
-- signal HSMB_OUT_n1 : std_logic;
-- signal HSMB_OUT_p1 : std_logic;
-- signal HSMB_OUT0 : std_logic;
-- signal HSMB_REFCLK_p : in std_logic;
-- signal HSMB_RX_n : std_logic_vector(16 downto 0);
-- signal HSMB_RX_p : std_logic_vector(16 downto 0);
-- signal HSMB_TX_n : std_logic_vector(16 downto 0);
-- signal HSMB_TX_p : std_logic_vector(16 downto 0);
-- HSMC i2c
-- signal HSMC_SCL : std_logic;
-- signal HSMC_SDA : std_logic;
-- Display
-- signal SEG0_D : std_logic_vector(6 downto 0);
-- signal SEG1_D : std_logic_vector(6 downto 0);
-- signal SEG0_DP : std_ulogic;
-- signal SEG1_DP : std_ulogic;
-- UART
signal UART_CTS : std_ulogic;
signal UART_RTS : std_ulogic;
signal UART_RXD : std_logic;
signal UART_TXD : std_logic;
signal dsuen, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal sgmii_rstn : std_logic;
signal dummy_ethi : eth_in_type;
signal dummy_etho : eth_out_type;
signal sgmii0_rxd : std_logic_vector(7 downto 0);
signal sgmii0_rx_dv : std_logic;
signal sgmii0_rx_er : std_logic;
signal sgmii0_rx_col : std_logic;
signal sgmii0_rx_crs : std_logic;
signal sgmii0_rx_clk : std_logic;
signal phy0_rxd : std_logic_vector(7 downto 0);
signal phy0_rx_dv : std_logic;
signal phy0_rx_er : std_logic;
signal phy0_rx_col : std_logic;
signal phy0_rx_crs : std_logic;
signal phy0_rx_clk : std_logic;
signal sgmii0_txd : std_logic_vector(7 downto 0);
signal sgmii0_tx_en : std_logic;
signal sgmii0_tx_er : std_logic;
signal sgmii0_gtx_clk : std_logic;
signal phy0_txd : std_logic_vector(7 downto 0);
signal phy0_tx_en : std_logic;
signal phy0_tx_er : std_logic;
signal phy0_gtx_clk : std_logic;
signal sgmii1_rxd : std_logic_vector(7 downto 0);
signal sgmii1_rx_dv : std_logic;
signal sgmii1_rx_er : std_logic;
signal sgmii1_rx_col : std_logic;
signal sgmii1_rx_crs : std_logic;
signal sgmii1_rx_clk : std_logic;
signal phy1_rxd : std_logic_vector(7 downto 0);
signal phy1_rx_dv : std_logic;
signal phy1_rx_er : std_logic;
signal phy1_rx_col : std_logic;
signal phy1_rx_crs : std_logic;
signal phy1_rx_clk : std_logic;
signal sgmii1_txd : std_logic_vector(7 downto 0);
signal sgmii1_tx_en : std_logic;
signal sgmii1_tx_er : std_logic;
signal sgmii1_gtx_clk : std_logic;
signal phy1_txd : std_logic_vector(7 downto 0);
signal phy1_tx_en : std_logic;
signal phy1_tx_er : std_logic;
signal phy1_gtx_clk : std_logic;
signal rst_125 : std_logic;
constant lresp : boolean := false;
constant slips : integer := 11;
signal ETH_RX_p_d : std_logic;
begin
-- clock and reset
-- 50 MHz clocks
OSC_50_BANK2 <= not OSC_50_BANK2 after 10 ns;
OSC_50_BANK3 <= not OSC_50_BANK3 after 10 ns;
OSC_50_BANK4 <= not OSC_50_BANK4 after 10 ns;
OSC_50_BANK5 <= not OSC_50_BANK5 after 10 ns;
OSC_50_BANK6 <= not OSC_50_BANK6 after 10 ns;
OSC_50_BANK7 <= not OSC_50_BANK7 after 10 ns;
-- 100 MHz
PLL_CLKIN_p <= not PLL_CLKIN_p after 5 ns;
SMA_CLKIN_p <= not SMA_CLKIN_p after 10 ns;
GCLKIN <= not GCLKIN after 10 ns;
clk_125 <= not clk_125 after 4 ns;
CPU_RESET_n <= '0', '1' after 200 ns;
sgmii_rstn <= '0', '1' after 1000 ns;
-- various interfaces
-- MAX_CONF_D <= (others => 'H');
-- MAX_I2C_SDAT <= 'H';
BUTTON <= "HHHH";
SW <= (others => 'H');
SLIDE_SW <= (others => 'L');
-- TEMP_SMDAT <= 'H';
-- TEMP_INT_n <= 'H';
CSENSE_SCK <= 'H';
CSENSE_SDO <= 'H';
EEP_SDA <= 'H';
-- SD_CMD <= 'H';
-- SD_DAT <= (others => 'H');
-- SD_WP_n <= 'H';
GPIO0_D <= (others => 'H');
-- GPIO1_D <= (others => 'H');
EXT_IO <= 'H';
LED(0) <= 'H';
-- HSMC_SDA <= 'H';
UART_RTS <= '1';
UART_RXD <= 'H';
-- LEON3 SoC
d3 : entity work.leon3mp
generic map (
fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
OSC_50_BANK2, OSC_50_BANK3, OSC_50_BANK4, OSC_50_BANK5, OSC_50_BANK6,
OSC_50_BANK7, PLL_CLKIN_p, SMA_CLKIN_p,
-- SMA_GXBCLK_p
GCLKIN,
-- GCLKOUT_FPGA, SMA_CLKOUT_p,
-- cpu reset
CPU_RESET_n,
-- max i/o
-- MAX_CONF_D, MAX_I2C_SCLK, MAX_I2C_SDAT,
-- LEDs
LED,
-- buttons
BUTTON,
-- switches
SW,
-- slide switches
SLIDE_SW,
-- temperature
-- TEMP_SMCLK, TEMP_SMDAT, TEMP_INT_n,
-- current
CSENSE_ADC_FO, CSENSE_SCK, CSENSE_SDI, CSENSE_SDO, CSENSE_CS_n,
-- fan
FAN_CTRL,
-- eeprom
EEP_SCL, EEP_SDA,
-- sdcard
-- SD_CLK, SD_CMD, SD_DAT, SD_WP_n,
-- Ethernet interfaces
ETH_INT_n, ETH_MDC, ETH_MDIO, ETH_RST_n, ETH_RX_p, ETH_TX_p,
-- PCIe interfaces
-- PCIE_PREST_n, PCIE_REFCLK_p, PCIE_RX_p, PCIE_SMBCLK,
-- PCIE_SMBDAT, PCIE_TX_p PCIE_WAKE_n
-- Flash and SRAM, shared signals
FSM_A, FSM_D,
-- Flash control
FLASH_ADV_n, FLASH_CE_n, FLASH_CLK, FLASH_OE_n,
FLASH_RESET_n, FLASH_RYBY_n, FLASH_WE_n,
-- SSRAM control
SSRAM_ADV, SSRAM_BWA_n, SSRAM_BWB_n, SSRAM_CE_n,
SSRAM_CKE_n, SSRAM_CLK, SSRAM_OE_n, SSRAM_WE_n,
-- USB OTG
-- OTG_A, OTG_CS_n, OTG_D, OTG_DC_DACK, OTG_DC_DRE, OTG_DC_IRQ,
-- OTG_HC_DACK, OTG_HC_DREQ, OTG_HC_IRQ, OTG_OE_n, OTG_RESET_n,
-- OTG_WE_n,
-- SATA
-- SATA_REFCLK_p, SATA_HOST_RX_p, SATA_HOST_TX_p, SATA_DEVICE_RX_p, SATA_DEVICE_TX_p,
-- DDR2 SODIMM
M1_DDR2_addr, M1_DDR2_ba, M1_DDR2_cas_n, M1_DDR2_cke, M1_DDR2_clk, M1_DDR2_clk_n,
M1_DDR2_cs_n, M1_DDR2_dm, M1_DDR2_dq, M1_DDR2_dqs, M1_DDR2_dqsn, M1_DDR2_odt,
M1_DDR2_ras_n,
-- M1_DDR2_SA, M1_DDR2_SCL, M1_DDR2_SDA,
M1_DDR2_we_n,
M1_DDR2_oct_rdn, M1_DDR2_oct_rup,
-- DDR2 SODIMM
-- M2_DDR2_addr, M2_DDR2_ba, M2_DDR2_cas_n, M2_DDR2_cke, M2_DDR2_clk, M2_DDR2_clk_n
-- M2_DDR2_cs_n, M2_DDR2_dm, M2_DDR2_dq, M2_DDR2_dqs, M2_DDR2_dqsn, M2_DDR2_odt,
-- M2_DDR2_ras_n, M2_DDR2_SA, M2_DDR2_SCL, M2_DDR2_SDA M2_DDR2_we_n
-- GPIO
GPIO0_D,
-- GPIO1_D,
-- Ext I/O
-- EXT_IO,
-- HSMC A
-- HSMA_CLKIN_n1, HSMA_CLKIN_n2, HSMA_CLKIN_p1, HSMA_CLKIN_p2, HSMA_CLKIN0,
HSMA_CLKOUT_n2, HSMA_CLKOUT_p2,
-- HSMA_D,
-- HSMA_GXB_RX_p, HSMA_GXB_TX_p,
-- HSMA_OUT_n1, HSMA_OUT_p1, HSMA_OUT0,
-- HSMA_REFCLK_p,
-- HSMA_RX_n, HSMA_RX_p, HSMA_TX_n, HSMA_TX_p,
-- HSMC_B
-- HSMB_CLKIN_n1, HSMB_CLKIN_n2, HSMB_CLKIN_p1, HSMB_CLKIN_p2, HSMB_CLKIN0,
-- HSMB_CLKOUT_n2, HSMB_CLKOUT_p2, HSMB_D,
-- HSMB_GXB_RX_p, HSMB_GXB_TX_p,
-- HSMB_OUT_n1, HSMB_OUT_p1, HSMB_OUT0,
-- HSMB_REFCLK_p,
-- HSMB_RX_n, HSMB_RX_p, HSMB_TX_n, HSMB_TX_p,
-- HSMC i2c
-- HSMC_SCL, HSMC_SDA,
-- Display
-- SEG0_D, SEG1_D, SEG0_DP, SEG1_DP,
-- UART
UART_CTS, UART_RTS, UART_RXD, UART_TXD
);
ethsim0 : if CFG_GRETH /= 0 generate
rst_125 <= not CPU_RESET_n;
-- delaying rx line
ETH_RX_p(0) <= transport ETH_RX_p_d after 0.8 ns * slips;
-- connecting PHY through SGMII to MAC
p0: phy
generic map(
address => 0
)
port map(
rstn => CPU_RESET_n,
mdio => ETH_MDIO(0),
tx_clk => open,
rx_clk => open,
rxd => phy0_rxd,
rx_dv => phy0_rx_dv,
rx_er => phy0_rx_er,
rx_col => phy0_rx_col,
rx_crs => phy0_rx_crs,
txd => phy0_txd,
tx_en => phy0_tx_en,
tx_er => phy0_tx_er,
mdc => ETH_MDC(0),
gtx_clk => phy0_gtx_clk
);
phy0_txd <= sgmii0_rxd;
phy0_tx_en <= sgmii0_rx_dv;
phy0_tx_er <= sgmii0_rx_er;
phy0_gtx_clk <= sgmii0_gtx_clk;
sgmii0_txd <= phy0_rxd;
sgmii0_tx_en <= phy0_rx_dv;
sgmii0_tx_er <= phy0_rx_er;
sgmii0: sgmii
generic map (
fabtech => fabtech
)
port map(
clk_125 => clk_125,
rst_125 => rst_125,
ser_rx_p => ETH_TX_p(0),
ser_tx_p => ETH_RX_p_d,
txd => sgmii0_txd,
tx_en => sgmii0_tx_en,
tx_er => sgmii0_tx_er,
tx_clk => sgmii0_gtx_clk,
rxd => sgmii0_rxd,
rx_dv => sgmii0_rx_dv,
rx_er => sgmii0_rx_er,
rx_col => sgmii0_rx_col,
rx_crs => sgmii0_rx_crs,
rx_clk => sgmii0_rx_clk,
mdc => ETH_MDC(0)
);
end generate;
ethsim1 : if CFG_GRETH2 /= 0 generate
-- connecting PHY through SGMII to MAC
p1: phy
generic map(
address => 1
)
port map(
rstn => CPU_RESET_n,
mdio => ETH_MDIO(1),
tx_clk => open,
rx_clk => open,
rxd => phy1_rxd,
rx_dv => phy1_rx_dv,
rx_er => phy1_rx_er,
rx_col => phy1_rx_col,
rx_crs => phy1_rx_crs,
txd => phy1_txd,
tx_en => phy1_tx_en,
tx_er => phy1_tx_er,
mdc => ETH_MDC(1),
gtx_clk => phy1_gtx_clk
);
phy1_txd <= sgmii1_rxd;
phy1_tx_en <= sgmii1_rx_dv;
phy1_tx_er <= sgmii1_rx_er;
phy1_gtx_clk <= sgmii1_gtx_clk;
sgmii1_txd <= phy1_rxd;
sgmii1_tx_en <= phy1_rx_dv;
sgmii1_tx_er <= phy1_rx_er;
sgmii1: sgmii
generic map (
fabtech => fabtech
)
port map(
clk_125 => clk_125,
rst_125 => rst_125,
ser_rx_p => ETH_TX_p(1),
ser_tx_p => ETH_RX_p(1),
txd => sgmii1_txd,
tx_en => sgmii1_tx_en,
tx_er => sgmii1_tx_er,
tx_clk => sgmii1_gtx_clk,
rxd => sgmii1_rxd,
rx_dv => sgmii1_rx_dv,
rx_er => sgmii1_rx_er,
rx_col => sgmii1_rx_col,
rx_crs => sgmii1_rx_crs,
rx_clk => sgmii1_rx_clk,
mdc => ETH_MDC(1)
);
end generate;
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (FSM_A(romdepth downto 1), FSM_D, FLASH_CE_n, FLASH_CE_n, FLASH_CE_n,
FLASH_WE_n, FLASH_OE_n);
FLASH_RYBY_n <= 'H';
test0 : grtestmod
generic map ( width => 16 )
port map ( CPU_RESET_n, OSC_50_BANK3, LED(0), FSM_A(20 downto 1), FSM_D,
'0', FLASH_OE_n, FLASH_WE_n);
iuerr : process
begin
wait for 2500 ns;
if to_x01(LED(0)) = '1' then wait on LED(0); end if;
assert (to_x01(LED(0)) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
FSM_D <= buskeep(FSM_D) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 2500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);--
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);--
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);--
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);--
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);--
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);--
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);--
end;--
begin--
dsucfg(UART_TXD, UART_RXD);--
wait;
end process;
end ;
| gpl-2.0 | ff35767c28cede23a67f007a37271f14 | 0.567935 | 2.763447 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/grdware/mul_dware.vhd | 1 | 4,078 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: misc
-- File: mul_dware.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Dware multipliers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library Dware;
use DWARE.DWpackages.all;
use DWARE.DW_Foundation_comp_arith.all;
entity mul_dw is
generic (
a_width : positive := 2; -- multiplier word width
b_width : positive := 2; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable
);
port(a : in std_logic_vector(a_width-1 downto 0);
b : in std_logic_vector(b_width-1 downto 0);
clk : in std_logic;
en : in std_logic;
sign : in std_logic;
product : out std_logic_vector(a_width+b_width-1 downto 0));
end;
architecture rtl of mul_dw is
component DW02_mult
generic( A_width: NATURAL; -- multiplier wordlength
B_width: NATURAL); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
signal gnd : std_ulogic;
begin
gnd <= '0';
np : if num_stages = 1 generate
u0 : DW02_mult
generic map ( a_width => a_width, b_width => b_width)
port map (a => a, b => b, TC => sign, product => product);
end generate;
pipe : if num_stages > 1 generate
u0 : DW_mult_pipe
generic map ( a_width => a_width, b_width => b_width,
num_stages => num_stages, stall_mode => stall_mode, rst_mode => 0)
port map (a => a, b => b, TC => sign, clk => clk, product => product,
rst_n => gnd, en => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library Dware;
use DWARE.DWpackages.all;
use DWARE.DW_Foundation_comp_arith.all;
entity dw_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of dw_mul_61x61 is
signal gnd : std_ulogic;
signal pin, p : std_logic_vector(121 downto 0);
begin
gnd <= '0';
-- u0 : DW02_mult_2_stage
-- generic map ( A_width => A'length, B_width => B'length )
-- port map ( A => A, B => B, TC => gnd, CLK => CLK, PRODUCT => pin );
u0 : DW_mult_pipe
generic map ( a_width => 61, b_width => 61,
num_stages => 2, stall_mode => 0, rst_mode => 0)
port map (a => a, b => b, TC => gnd, clk => clk, product => pin,
rst_n => gnd, en => gnd);
reg0 : process(CLK)
begin
if rising_edge(CLK) then
p <= pin;
end if;
end process;
PRODUCT <= p;
end;
| gpl-2.0 | 5e2e3ecc9444db3b063003c4de634c5c | 0.565473 | 3.552265 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/5d5252f58f13bcd8/zqynq_lab_1_design_axi_gpio_0_1_sim_netlist.vhdl | 1 | 51,879 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Fri Sep 22 23:00:32 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_gpio_0_1_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_gpio_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
rst_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal \^gpio_io_o\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of ip2bus_rdack_i_D1_i_1 : label is "soft_lutpair4";
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
gpio_io_o(7 downto 0) <= \^gpio_io_o\(7 downto 0);
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(7),
Q => D(7),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(6),
Q => D(6),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(5),
Q => D(5),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(4),
Q => D(4),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(3),
Q => D(3),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[5].GPIO_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(2),
Q => D(2),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[6].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(1),
Q => D(1),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(0),
Q => D(0),
R => bus2ip_rnw_i_reg
);
\Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7),
Q => \^gpio_io_o\(7),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6),
Q => \^gpio_io_o\(6),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5),
Q => \^gpio_io_o\(5),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4),
Q => \^gpio_io_o\(4),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3),
Q => \^gpio_io_o\(3),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2),
Q => \^gpio_io_o\(2),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1),
Q => \^gpio_io_o\(1),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0),
Q => \^gpio_io_o\(0),
R => SS(0)
);
\Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7),
Q => gpio_io_t(7),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6),
Q => gpio_io_t(6),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5),
Q => gpio_io_t(5),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4),
Q => gpio_io_t(4),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3),
Q => gpio_io_t(3),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2),
Q => gpio_io_t(2),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1),
Q => gpio_io_t(1),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0),
Q => gpio_io_t(0),
S => SS(0)
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => SS(0)
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => bus2ip_cs,
I1 => \^gpio_xferack_reg\,
I2 => \^gpio_xferack_i\,
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => SS(0)
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_wrack_i_D1_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
port (
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
rst_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_read : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ip2bus_wrack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
start2_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC;
signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
begin
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => start2_reg,
I2 => s_axi_aresetn,
I3 => \^s_axi_arready\,
I4 => \^s_axi_wready\,
O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\,
Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
R => '0'
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => gpio_xferAck_Reg,
I3 => GPIO_xferAck_i,
O => \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\
);
\Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAABAAAA"
)
port map (
I0 => rst_reg,
I1 => Q(1),
I2 => bus2ip_rnw_i_reg,
I3 => Q(0),
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => Q(2),
O => E(0)
);
\Not_Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(7),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(15),
O => D(7)
);
\Not_Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(6),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(14),
O => D(6)
);
\Not_Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(5),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(13),
O => D(5)
);
\Not_Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(4),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(12),
O => D(4)
);
\Not_Dual.gpio_Data_Out[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(3),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(11),
O => D(3)
);
\Not_Dual.gpio_Data_Out[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(2),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(10),
O => D(2)
);
\Not_Dual.gpio_Data_Out[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(9),
O => D(1)
);
\Not_Dual.gpio_Data_Out[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(8),
O => D(0)
);
\Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => rst_reg,
I1 => Q(0),
I2 => Q(1),
I3 => bus2ip_rnw_i_reg,
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => Q(2),
O => \Not_Dual.gpio_OE_reg[0]\(0)
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_rdack_i_D1,
I1 => is_read,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_wrack_i_D1,
I1 => is_write_reg,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
port (
SR : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^not_dual.gpio_data_out_reg[0]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC;
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_1_in : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal \s_axi_rdata_i[7]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state1__2\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair1";
begin
\Not_Dual.gpio_Data_Out_reg[0]\ <= \^not_dual.gpio_data_out_reg[0]\;
SR <= \^sr\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
port map (
D(7 downto 0) => D(7 downto 0),
E(0) => E(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ => \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\,
\Not_Dual.gpio_OE_reg[0]\(0) => \Not_Dual.gpio_OE_reg[0]\(0),
Q(2) => bus2ip_addr(0),
Q(1) => bus2ip_addr(5),
Q(0) => bus2ip_addr(6),
bus2ip_rnw_i_reg => \^not_dual.gpio_data_out_reg[0]\,
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
rst_reg => \^sr\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(15 downto 0) => s_axi_wdata(15 downto 0),
s_axi_wready => \^s_axi_wready\,
start2_reg => start2
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_awaddr(0),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_awaddr(1),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000EA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => state(0),
O => \bus2ip_addr_i[8]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_awaddr(2),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[8]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => bus2ip_addr(6),
R => \^sr\
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => bus2ip_addr(5),
R => \^sr\
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[8]_i_2_n_0\,
Q => bus2ip_addr(0),
R => \^sr\
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => state(0),
I1 => state(1),
I2 => s_axi_arvalid,
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => bus2ip_rnw_i06_out,
Q => \^not_dual.gpio_data_out_reg[0]\,
R => \^sr\
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state1__2\,
I2 => state(0),
I3 => state(1),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => \^sr\
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => \^s_axi_bvalid\,
I3 => s_axi_bready,
I4 => state(0),
I5 => state(1),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => \^sr\
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => p_1_in
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_1_in,
Q => \^sr\,
R => '0'
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => \^sr\
);
\s_axi_rdata_i[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => \s_axi_rdata_i[7]_i_1_n_0\
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(0),
Q => s_axi_rdata(0),
R => \^sr\
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(1),
Q => s_axi_rdata(1),
R => \^sr\
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(2),
Q => s_axi_rdata(2),
R => \^sr\
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(3),
Q => s_axi_rdata(3),
R => \^sr\
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(4),
Q => s_axi_rdata(4),
R => \^sr\
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(5),
Q => s_axi_rdata(5),
R => \^sr\
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(6),
Q => s_axi_rdata(6),
R => \^sr\
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(7),
Q => s_axi_rdata(7),
R => \^sr\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => \^sr\
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(1),
I4 => state(0),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => \^sr\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"77FC44FC"
)
port map (
I0 => \state1__2\,
I1 => state(0),
I2 => s_axi_arvalid,
I3 => state(1),
I4 => \^s_axi_wready\,
O => p_0_out(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5FFC50FC"
)
port map (
I0 => \state1__2\,
I1 => \state[1]_i_3_n_0\,
I2 => state(1),
I3 => state(0),
I4 => \^s_axi_arready\,
O => p_0_out(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state1__2\
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(0),
Q => state(0),
R => \^sr\
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(1),
Q => state(1),
R => \^sr\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
port (
bus2ip_reset : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
port map (
D(7 downto 0) => D(7 downto 0),
E(0) => E(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ => \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\,
\Not_Dual.gpio_Data_Out_reg[0]\ => bus2ip_rnw,
\Not_Dual.gpio_OE_reg[0]\(0) => \Not_Dual.gpio_OE_reg[0]\(0),
Q(7 downto 0) => Q(7 downto 0),
SR => bus2ip_reset,
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(7 downto 0) => s_axi_rdata(7 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(15 downto 0) => s_axi_wdata(15 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 1;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 8;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "LOGICORE";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_17 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_6 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_7 : STD_LOGIC;
signal DBus_Reg : STD_LOGIC_VECTOR ( 0 to 7 );
signal GPIO_xferAck_i : STD_LOGIC;
signal bus2ip_cs : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio_core_1_n_19 : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 24 to 31 );
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 24 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
begin
gpio2_io_o(31) <= \<const0>\;
gpio2_io_o(30) <= \<const0>\;
gpio2_io_o(29) <= \<const0>\;
gpio2_io_o(28) <= \<const0>\;
gpio2_io_o(27) <= \<const0>\;
gpio2_io_o(26) <= \<const0>\;
gpio2_io_o(25) <= \<const0>\;
gpio2_io_o(24) <= \<const0>\;
gpio2_io_o(23) <= \<const0>\;
gpio2_io_o(22) <= \<const0>\;
gpio2_io_o(21) <= \<const0>\;
gpio2_io_o(20) <= \<const0>\;
gpio2_io_o(19) <= \<const0>\;
gpio2_io_o(18) <= \<const0>\;
gpio2_io_o(17) <= \<const0>\;
gpio2_io_o(16) <= \<const0>\;
gpio2_io_o(15) <= \<const0>\;
gpio2_io_o(14) <= \<const0>\;
gpio2_io_o(13) <= \<const0>\;
gpio2_io_o(12) <= \<const0>\;
gpio2_io_o(11) <= \<const0>\;
gpio2_io_o(10) <= \<const0>\;
gpio2_io_o(9) <= \<const0>\;
gpio2_io_o(8) <= \<const0>\;
gpio2_io_o(7) <= \<const0>\;
gpio2_io_o(6) <= \<const0>\;
gpio2_io_o(5) <= \<const0>\;
gpio2_io_o(4) <= \<const0>\;
gpio2_io_o(3) <= \<const0>\;
gpio2_io_o(2) <= \<const0>\;
gpio2_io_o(1) <= \<const0>\;
gpio2_io_o(0) <= \<const0>\;
gpio2_io_t(31) <= \<const1>\;
gpio2_io_t(30) <= \<const1>\;
gpio2_io_t(29) <= \<const1>\;
gpio2_io_t(28) <= \<const1>\;
gpio2_io_t(27) <= \<const1>\;
gpio2_io_t(26) <= \<const1>\;
gpio2_io_t(25) <= \<const1>\;
gpio2_io_t(24) <= \<const1>\;
gpio2_io_t(23) <= \<const1>\;
gpio2_io_t(22) <= \<const1>\;
gpio2_io_t(21) <= \<const1>\;
gpio2_io_t(20) <= \<const1>\;
gpio2_io_t(19) <= \<const1>\;
gpio2_io_t(18) <= \<const1>\;
gpio2_io_t(17) <= \<const1>\;
gpio2_io_t(16) <= \<const1>\;
gpio2_io_t(15) <= \<const1>\;
gpio2_io_t(14) <= \<const1>\;
gpio2_io_t(13) <= \<const1>\;
gpio2_io_t(12) <= \<const1>\;
gpio2_io_t(11) <= \<const1>\;
gpio2_io_t(10) <= \<const1>\;
gpio2_io_t(9) <= \<const1>\;
gpio2_io_t(8) <= \<const1>\;
gpio2_io_t(7) <= \<const1>\;
gpio2_io_t(6) <= \<const1>\;
gpio2_io_t(5) <= \<const1>\;
gpio2_io_t(4) <= \<const1>\;
gpio2_io_t(3) <= \<const1>\;
gpio2_io_t(2) <= \<const1>\;
gpio2_io_t(1) <= \<const1>\;
gpio2_io_t(0) <= \<const1>\;
ip2intc_irpt <= \<const0>\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7 downto 0) <= \^s_axi_rdata\(7 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
port map (
D(7) => DBus_Reg(0),
D(6) => DBus_Reg(1),
D(5) => DBus_Reg(2),
D(4) => DBus_Reg(3),
D(3) => DBus_Reg(4),
D(2) => DBus_Reg(5),
D(1) => DBus_Reg(6),
D(0) => DBus_Reg(7),
E(0) => AXI_LITE_IPIF_I_n_6,
GPIO_xferAck_i => GPIO_xferAck_i,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ => AXI_LITE_IPIF_I_n_17,
\Not_Dual.gpio_OE_reg[0]\(0) => AXI_LITE_IPIF_I_n_7,
Q(7) => ip2bus_data_i_D1(24),
Q(6) => ip2bus_data_i_D1(25),
Q(5) => ip2bus_data_i_D1(26),
Q(4) => ip2bus_data_i_D1(27),
Q(3) => ip2bus_data_i_D1(28),
Q(2) => ip2bus_data_i_D1(29),
Q(1) => ip2bus_data_i_D1(30),
Q(0) => ip2bus_data_i_D1(31),
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2) => s_axi_araddr(8),
s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2) => s_axi_awaddr(8),
s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(7 downto 0) => \^s_axi_rdata\(7 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(15 downto 8) => s_axi_wdata(31 downto 24),
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
gpio_core_1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
port map (
D(7) => ip2bus_data(24),
D(6) => ip2bus_data(25),
D(5) => ip2bus_data(26),
D(4) => ip2bus_data(27),
D(3) => ip2bus_data(28),
D(2) => ip2bus_data(29),
D(1) => ip2bus_data(30),
D(0) => ip2bus_data(31),
E(0) => AXI_LITE_IPIF_I_n_6,
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7) => DBus_Reg(0),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6) => DBus_Reg(1),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5) => DBus_Reg(2),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4) => DBus_Reg(3),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3) => DBus_Reg(4),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2) => DBus_Reg(5),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1) => DBus_Reg(6),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0) => DBus_Reg(7),
SS(0) => bus2ip_reset,
bus2ip_cs => bus2ip_cs,
bus2ip_rnw => bus2ip_rnw,
bus2ip_rnw_i_reg => AXI_LITE_IPIF_I_n_17,
gpio_io_o(7 downto 0) => gpio_io_o(7 downto 0),
gpio_io_t(7 downto 0) => gpio_io_t(7 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg => gpio_core_1_n_19,
rst_reg(0) => AXI_LITE_IPIF_I_n_7,
s_axi_aclk => s_axi_aclk
);
\ip2bus_data_i_D1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(24),
Q => ip2bus_data_i_D1(24),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(25),
Q => ip2bus_data_i_D1(25),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(26),
Q => ip2bus_data_i_D1(26),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(27),
Q => ip2bus_data_i_D1(27),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(28),
Q => ip2bus_data_i_D1(28),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(29),
Q => ip2bus_data_i_D1(29),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_core_1_n_19,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_axi_gpio_0_1,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_gpio,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 1;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 8;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
port map (
gpio2_io_i(31 downto 0) => B"00000000000000000000000000000000",
gpio2_io_o(31 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(31 downto 0),
gpio2_io_t(31 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(31 downto 0),
gpio_io_i(7 downto 0) => B"00000000",
gpio_io_o(7 downto 0) => gpio_io_o(7 downto 0),
gpio_io_t(7 downto 0) => NLW_U0_gpio_io_t_UNCONNECTED(7 downto 0),
ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 491f10c6bdb5e5f986ab521ef2b70eda | 0.553769 | 2.668947 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_2/syn/vhdl/convolve_kernel.vhd | 1 | 158,981 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
bufw_0_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_EN_A : OUT STD_LOGIC;
bufw_0_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_0_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_0_Clk_A : OUT STD_LOGIC;
bufw_0_Rst_A : OUT STD_LOGIC;
bufw_1_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_EN_A : OUT STD_LOGIC;
bufw_1_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_1_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_1_Clk_A : OUT STD_LOGIC;
bufw_1_Rst_A : OUT STD_LOGIC;
bufw_2_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_EN_A : OUT STD_LOGIC;
bufw_2_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_2_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_2_Clk_A : OUT STD_LOGIC;
bufw_2_Rst_A : OUT STD_LOGIC;
bufw_3_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_EN_A : OUT STD_LOGIC;
bufw_3_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_3_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_3_Clk_A : OUT STD_LOGIC;
bufw_3_Rst_A : OUT STD_LOGIC;
bufw_4_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_EN_A : OUT STD_LOGIC;
bufw_4_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_4_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_4_Clk_A : OUT STD_LOGIC;
bufw_4_Rst_A : OUT STD_LOGIC;
bufi_0_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_0_EN_A : OUT STD_LOGIC;
bufi_0_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_0_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_0_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_0_Clk_A : OUT STD_LOGIC;
bufi_0_Rst_A : OUT STD_LOGIC;
bufi_1_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_1_EN_A : OUT STD_LOGIC;
bufi_1_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_1_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_1_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_1_Clk_A : OUT STD_LOGIC;
bufi_1_Rst_A : OUT STD_LOGIC;
bufi_2_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_2_EN_A : OUT STD_LOGIC;
bufi_2_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_2_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_2_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_2_Clk_A : OUT STD_LOGIC;
bufi_2_Rst_A : OUT STD_LOGIC;
bufi_3_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_3_EN_A : OUT STD_LOGIC;
bufi_3_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_3_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_3_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_3_Clk_A : OUT STD_LOGIC;
bufi_3_Rst_A : OUT STD_LOGIC;
bufi_4_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_4_EN_A : OUT STD_LOGIC;
bufi_4_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_4_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_4_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_4_Clk_A : OUT STD_LOGIC;
bufi_4_Rst_A : OUT STD_LOGIC;
bufi_5_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_5_EN_A : OUT STD_LOGIC;
bufi_5_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_5_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_5_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_5_Clk_A : OUT STD_LOGIC;
bufi_5_Rst_A : OUT STD_LOGIC;
bufi_6_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_6_EN_A : OUT STD_LOGIC;
bufi_6_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_6_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_6_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_6_Clk_A : OUT STD_LOGIC;
bufi_6_Rst_A : OUT STD_LOGIC;
bufo_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_EN_A : OUT STD_LOGIC;
bufo_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_Clk_A : OUT STD_LOGIC;
bufo_Rst_A : OUT STD_LOGIC );
end;
architecture behav of convolve_kernel is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"convolve_kernel,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.696000,HLS_SYN_LAT=18064,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=5,HLS_SYN_FF=2096,HLS_SYN_LUT=2443}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000000000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000000000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000000001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000000010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000000100000000";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000001000000000";
constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000010000000000";
constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000100000000000";
constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000001000000000000";
constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000010000000000000";
constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000100000000000000";
constant ap_ST_fsm_pp0_stage6 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000001000000000000000";
constant ap_ST_fsm_pp0_stage7 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000010000000000000000";
constant ap_ST_fsm_pp0_stage8 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000100000000000000000";
constant ap_ST_fsm_pp0_stage9 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000001000000000000000000";
constant ap_ST_fsm_pp0_stage10 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000010000000000000000000";
constant ap_ST_fsm_pp0_stage11 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000100000000000000000000";
constant ap_ST_fsm_pp0_stage12 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000001000000000000000000000";
constant ap_ST_fsm_pp0_stage13 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000010000000000000000000000";
constant ap_ST_fsm_pp0_stage14 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000100000000000000000000000";
constant ap_ST_fsm_pp0_stage15 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000001000000000000000000000000";
constant ap_ST_fsm_pp0_stage16 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000010000000000000000000000000";
constant ap_ST_fsm_pp0_stage17 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000100000000000000000000000000";
constant ap_ST_fsm_pp0_stage18 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000001000000000000000000000000000";
constant ap_ST_fsm_pp0_stage19 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000010000000000000000000000000000";
constant ap_ST_fsm_pp0_stage20 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000100000000000000000000000000000";
constant ap_ST_fsm_pp0_stage21 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000001000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage22 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000010000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage23 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000100000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage24 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000001000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage25 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000010000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage26 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000100000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage27 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000001000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage28 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000010000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage29 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000100000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage30 : STD_LOGIC_VECTOR (50 downto 0) := "000000000001000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage31 : STD_LOGIC_VECTOR (50 downto 0) := "000000000010000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage32 : STD_LOGIC_VECTOR (50 downto 0) := "000000000100000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage33 : STD_LOGIC_VECTOR (50 downto 0) := "000000001000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage34 : STD_LOGIC_VECTOR (50 downto 0) := "000000010000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage35 : STD_LOGIC_VECTOR (50 downto 0) := "000000100000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage36 : STD_LOGIC_VECTOR (50 downto 0) := "000001000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage37 : STD_LOGIC_VECTOR (50 downto 0) := "000010000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage38 : STD_LOGIC_VECTOR (50 downto 0) := "000100000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage39 : STD_LOGIC_VECTOR (50 downto 0) := "001000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state63 : STD_LOGIC_VECTOR (50 downto 0) := "010000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state64 : STD_LOGIC_VECTOR (50 downto 0) := "100000000000000000000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100010";
constant ap_const_lv32_27 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100111";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100";
constant ap_const_lv32_2C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101100";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_31 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110001";
constant ap_const_lv32_32 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110010";
constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv7_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv4_1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_const_lv4_2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_const_lv4_3 : STD_LOGIC_VECTOR (3 downto 0) := "0011";
constant ap_const_lv4_4 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
constant ap_const_lv7_51 : STD_LOGIC_VECTOR (6 downto 0) := "1010001";
constant ap_const_lv7_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_const_lv6_1B : STD_LOGIC_VECTOR (5 downto 0) := "011011";
constant ap_const_lv4_9 : STD_LOGIC_VECTOR (3 downto 0) := "1001";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv3_5 : STD_LOGIC_VECTOR (2 downto 0) := "101";
constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_const_lv6_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
signal ap_CS_fsm : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal p_4_reg_294 : STD_LOGIC_VECTOR (2 downto 0);
signal temp1_reg_306 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_5_3_x_s_fu_337_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal reg_371 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_pp0_stage5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none";
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal ap_block_state15_pp0_stage5_iter0 : BOOLEAN;
signal ap_block_state55_pp0_stage5_iter1 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011001 : BOOLEAN;
signal tmp_3_reg_912 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage10 : signal is "none";
signal ap_block_state20_pp0_stage10_iter0 : BOOLEAN;
signal ap_block_state60_pp0_stage10_iter1 : BOOLEAN;
signal ap_block_pp0_stage10_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage15 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage15 : signal is "none";
signal ap_block_state25_pp0_stage15_iter0 : BOOLEAN;
signal ap_block_pp0_stage15_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage20 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage20 : signal is "none";
signal ap_block_state30_pp0_stage20_iter0 : BOOLEAN;
signal ap_block_pp0_stage20_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage25 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage25 : signal is "none";
signal ap_block_state35_pp0_stage25_iter0 : BOOLEAN;
signal ap_block_pp0_stage25_flag00011001 : BOOLEAN;
signal grp_fu_367_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_376 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_381 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_pp0_stage30 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage30 : signal is "none";
signal ap_block_state40_pp0_stage30_iter0 : BOOLEAN;
signal ap_block_pp0_stage30_flag00011001 : BOOLEAN;
signal grp_fu_361_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_pp0_stage19 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage19 : signal is "none";
signal ap_block_state29_pp0_stage19_iter0 : BOOLEAN;
signal ap_block_pp0_stage19_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage27 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage27 : signal is "none";
signal ap_block_state37_pp0_stage27_iter0 : BOOLEAN;
signal ap_block_pp0_stage27_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage35 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage35 : signal is "none";
signal ap_block_state45_pp0_stage35_iter0 : BOOLEAN;
signal ap_block_pp0_stage35_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage3 : signal is "none";
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_block_state13_pp0_stage3_iter0 : BOOLEAN;
signal ap_block_state53_pp0_stage3_iter1 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011001 : BOOLEAN;
signal ap_reg_pp0_iter1_tmp_3_reg_912 : STD_LOGIC_VECTOR (0 downto 0);
signal indvar_flatten_next2_fu_397_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal indvar_flatten_next2_reg_767 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal exitcond_flatten_fu_403_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten_reg_772 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten2_fu_391_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten1_fu_409_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten1_reg_783 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten_mid_fu_432_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten_mid_reg_789 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal tmp_8_mid1_fu_447_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_mid1_reg_796 : STD_LOGIC_VECTOR (0 downto 0);
signal p_1_mid_fu_453_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal p_1_mid_reg_802 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal tmp_2_fu_460_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_reg_808 : STD_LOGIC_VECTOR (0 downto 0);
signal p_2_mid_fu_464_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal p_2_mid_reg_813 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_4_mid2_fu_477_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_4_mid2_reg_819 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal p_3_mid2_fu_497_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal p_3_mid2_reg_827 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_7_mid2_fu_505_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_7_mid2_reg_837 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_11_fu_540_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_11_reg_844 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal tmp_12_fu_544_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_reg_849 : STD_LOGIC_VECTOR (3 downto 0);
signal bufo_addr_reg_854 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal tmp_1_mid2_v_fu_580_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_1_mid2_v_reg_859 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal tmp_1_fu_601_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_1_reg_868 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal tmp_7_cast_mid2_cast_fu_607_p1 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_7_cast_mid2_cast_reg_873 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_48_t_fu_610_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_48_t_reg_883 : STD_LOGIC_VECTOR (2 downto 0);
signal sel_tmp_fu_617_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp_reg_888 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp2_fu_622_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp2_reg_896 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp4_fu_627_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp4_reg_904 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_fu_632_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_block_state10_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state50_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal i_V_fu_638_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal i_V_reg_916 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_9_fu_644_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_9_reg_921 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_CS_fsm_pp0_stage1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage1 : signal is "none";
signal ap_block_state11_pp0_stage1_iter0 : BOOLEAN;
signal ap_block_state51_pp0_stage1_iter1 : BOOLEAN;
signal ap_block_pp0_stage1_flag00011001 : BOOLEAN;
signal tmp_16_fu_652_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_16_reg_927 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_pp0_stage2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage2 : signal is "none";
signal ap_block_state12_pp0_stage2_iter0 : BOOLEAN;
signal ap_block_state52_pp0_stage2_iter1 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011001 : BOOLEAN;
signal bufi_3_load_reg_967 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_pp0_stage4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage4 : signal is "none";
signal ap_block_state14_pp0_stage4_iter0 : BOOLEAN;
signal ap_block_state54_pp0_stage4_iter1 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011001 : BOOLEAN;
signal bufi_0_load_reg_975 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_reg_980 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_reg_986 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_4_load_reg_993 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_5_load_reg_1000 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_6_load_reg_1006 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_load_0_phi_fu_678_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_load_0_phi_reg_1011 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_load_1_phi_fu_695_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_load_1_phi_reg_1016 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_load_2_phi_fu_712_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_load_2_phi_reg_1021 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_load_3_phi_fu_729_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_load_3_phi_reg_1026 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_7_3_x_s_fu_316_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_reg_1031 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_pp0_stage9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage9 : signal is "none";
signal ap_block_state19_pp0_stage9_iter0 : BOOLEAN;
signal ap_block_state59_pp0_stage9_iter1 : BOOLEAN;
signal ap_block_pp0_stage9_flag00011001 : BOOLEAN;
signal tmp_13_3_reg_1036 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_4_reg_1041 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_pp0_stage11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage11 : signal is "none";
signal ap_block_state21_pp0_stage11_iter0 : BOOLEAN;
signal ap_block_state61_pp0_stage11_iter1 : BOOLEAN;
signal ap_block_pp0_stage11_flag00011001 : BOOLEAN;
signal col_b_V_fu_735_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal col_b_V_reg_1047 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_CS_fsm_state63 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state63 : signal is "none";
signal indvar_flatten_op_fu_740_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal indvar_flatten_op_reg_1052 : STD_LOGIC_VECTOR (3 downto 0);
signal indvar_flatten15_op_fu_746_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal indvar_flatten15_op_reg_1057 : STD_LOGIC_VECTOR (5 downto 0);
signal indvar_flatten_next_fu_752_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal ap_CS_fsm_state64 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state64 : signal is "none";
signal indvar_flatten_next1_fu_758_p3 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state10 : STD_LOGIC;
signal ap_block_state49_pp0_stage39_iter0 : BOOLEAN;
signal ap_block_pp0_stage39_flag00011011 : BOOLEAN;
signal ap_CS_fsm_pp0_stage39 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage39 : signal is "none";
signal ap_block_state22_pp0_stage12_iter0 : BOOLEAN;
signal ap_block_state62_pp0_stage12_iter1 : BOOLEAN;
signal ap_block_pp0_stage12_flag00011011 : BOOLEAN;
signal ap_CS_fsm_pp0_stage12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage12 : signal is "none";
signal grp_aesl_mux_load_7_3_x_s_fu_316_ap_start : STD_LOGIC;
signal grp_aesl_mux_load_7_3_x_s_fu_316_ap_done : STD_LOGIC;
signal grp_aesl_mux_load_7_3_x_s_fu_316_ap_idle : STD_LOGIC;
signal grp_aesl_mux_load_7_3_x_s_fu_316_ap_ready : STD_LOGIC;
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_2_Addr_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_2_EN_A : STD_LOGIC;
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_2_WEN_A : STD_LOGIC_VECTOR (3 downto 0);
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_2_Din_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_3_Addr_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_3_EN_A : STD_LOGIC;
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_3_WEN_A : STD_LOGIC_VECTOR (3 downto 0);
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_3_Din_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_4_Addr_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_4_EN_A : STD_LOGIC;
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_4_WEN_A : STD_LOGIC_VECTOR (3 downto 0);
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_4_Din_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_5_Addr_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_5_EN_A : STD_LOGIC;
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_5_WEN_A : STD_LOGIC_VECTOR (3 downto 0);
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_5_Din_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_6_Addr_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_6_EN_A : STD_LOGIC;
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_6_WEN_A : STD_LOGIC_VECTOR (3 downto 0);
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_6_Din_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_7_Addr_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_7_EN_A : STD_LOGIC;
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_7_WEN_A : STD_LOGIC_VECTOR (3 downto 0);
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_7_Din_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_8_Addr_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_8_EN_A : STD_LOGIC;
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_8_WEN_A : STD_LOGIC_VECTOR (3 downto 0);
signal grp_aesl_mux_load_7_3_x_s_fu_316_empty_8_Din_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_5_3_x_s_fu_337_ap_start : STD_LOGIC;
signal grp_aesl_mux_load_5_3_x_s_fu_337_ap_done : STD_LOGIC;
signal grp_aesl_mux_load_5_3_x_s_fu_337_ap_idle : STD_LOGIC;
signal grp_aesl_mux_load_5_3_x_s_fu_337_ap_ready : STD_LOGIC;
signal grp_aesl_mux_load_5_3_x_s_fu_337_empty_11_Addr_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_5_3_x_s_fu_337_empty_11_EN_A : STD_LOGIC;
signal grp_aesl_mux_load_5_3_x_s_fu_337_empty_11_WEN_A : STD_LOGIC_VECTOR (3 downto 0);
signal grp_aesl_mux_load_5_3_x_s_fu_337_empty_11_Din_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_5_3_x_s_fu_337_empty_12_Addr_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_5_3_x_s_fu_337_empty_12_EN_A : STD_LOGIC;
signal grp_aesl_mux_load_5_3_x_s_fu_337_empty_12_WEN_A : STD_LOGIC_VECTOR (3 downto 0);
signal grp_aesl_mux_load_5_3_x_s_fu_337_empty_12_Din_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_5_3_x_s_fu_337_empty_13_Addr_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_5_3_x_s_fu_337_empty_13_EN_A : STD_LOGIC;
signal grp_aesl_mux_load_5_3_x_s_fu_337_empty_13_WEN_A : STD_LOGIC_VECTOR (3 downto 0);
signal grp_aesl_mux_load_5_3_x_s_fu_337_empty_13_Din_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_5_3_x_s_fu_337_empty_14_Addr_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_5_3_x_s_fu_337_empty_14_EN_A : STD_LOGIC;
signal grp_aesl_mux_load_5_3_x_s_fu_337_empty_14_WEN_A : STD_LOGIC_VECTOR (3 downto 0);
signal grp_aesl_mux_load_5_3_x_s_fu_337_empty_14_Din_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_5_3_x_s_fu_337_empty_15_Addr_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_5_3_x_s_fu_337_empty_15_EN_A : STD_LOGIC;
signal grp_aesl_mux_load_5_3_x_s_fu_337_empty_15_WEN_A : STD_LOGIC_VECTOR (3 downto 0);
signal grp_aesl_mux_load_5_3_x_s_fu_337_empty_15_Din_A : STD_LOGIC_VECTOR (31 downto 0);
signal grp_aesl_mux_load_5_3_x_s_fu_337_empty : STD_LOGIC_VECTOR (3 downto 0);
signal indvar_flatten1_reg_211 : STD_LOGIC_VECTOR (6 downto 0);
signal p_s_reg_222 : STD_LOGIC_VECTOR (1 downto 0);
signal indvar_flatten2_reg_234 : STD_LOGIC_VECTOR (5 downto 0);
signal p_1_reg_246 : STD_LOGIC_VECTOR (1 downto 0);
signal indvar_flatten_reg_258 : STD_LOGIC_VECTOR (3 downto 0);
signal p_2_reg_270 : STD_LOGIC_VECTOR (1 downto 0);
signal p_3_reg_282 : STD_LOGIC_VECTOR (1 downto 0);
signal p_4_phi_fu_298_p4 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal temp1_phi_fu_309_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_block_pp0_stage11_flag00000000 : BOOLEAN;
signal ap_reg_grp_aesl_mux_load_7_3_x_s_fu_316_ap_start : STD_LOGIC := '0';
signal ap_CS_fsm_pp0_stage6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage6 : signal is "none";
signal ap_block_state16_pp0_stage6_iter0 : BOOLEAN;
signal ap_block_state56_pp0_stage6_iter1 : BOOLEAN;
signal ap_block_pp0_stage6_flag00011001 : BOOLEAN;
signal ap_block_pp0_stage6_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage7 : signal is "none";
signal ap_block_state17_pp0_stage7_iter0 : BOOLEAN;
signal ap_block_state57_pp0_stage7_iter1 : BOOLEAN;
signal ap_block_pp0_stage7_flag00011001 : BOOLEAN;
signal ap_block_pp0_stage7_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage8 : signal is "none";
signal ap_block_state18_pp0_stage8_iter0 : BOOLEAN;
signal ap_block_state58_pp0_stage8_iter1 : BOOLEAN;
signal ap_block_pp0_stage8_flag00011001 : BOOLEAN;
signal ap_block_pp0_stage8_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage5_flag00000000 : BOOLEAN;
signal ap_reg_grp_aesl_mux_load_5_3_x_s_fu_337_ap_start : STD_LOGIC := '0';
signal ap_block_pp0_stage3_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage4_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage9_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage13 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage13 : signal is "none";
signal ap_block_state23_pp0_stage13_iter0 : BOOLEAN;
signal ap_block_pp0_stage13_flag00011001 : BOOLEAN;
signal ap_block_pp0_stage13_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage14 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage14 : signal is "none";
signal ap_block_state24_pp0_stage14_iter0 : BOOLEAN;
signal ap_block_pp0_stage14_flag00011001 : BOOLEAN;
signal ap_block_pp0_stage14_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage18 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage18 : signal is "none";
signal ap_block_state28_pp0_stage18_iter0 : BOOLEAN;
signal ap_block_pp0_stage18_flag00011001 : BOOLEAN;
signal ap_block_pp0_stage18_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage19_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage23 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage23 : signal is "none";
signal ap_block_state33_pp0_stage23_iter0 : BOOLEAN;
signal ap_block_pp0_stage23_flag00011001 : BOOLEAN;
signal ap_block_pp0_stage23_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage24 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage24 : signal is "none";
signal ap_block_state34_pp0_stage24_iter0 : BOOLEAN;
signal ap_block_pp0_stage24_flag00011001 : BOOLEAN;
signal ap_block_pp0_stage24_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage1_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage16 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage16 : signal is "none";
signal ap_block_pp0_stage16_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage21 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage21 : signal is "none";
signal ap_block_pp0_stage21_flag00000000 : BOOLEAN;
signal tmp_18_cast_fu_569_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_cast_fu_657_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal ap_block_pp0_stage12_flag00011001 : BOOLEAN;
signal ap_block_pp0_stage12_flag00000000 : BOOLEAN;
signal bufi_3_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_4_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_5_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_6_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_361_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_361_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_block_pp0_stage27_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage35_flag00000000 : BOOLEAN;
signal grp_fu_367_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_pp0_stage26 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage26 : signal is "none";
signal ap_block_pp0_stage26_flag00000000 : BOOLEAN;
signal tmp_s_fu_420_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_exitcond_flatten_fu_415_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten_not_fu_437_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_mid_fu_426_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_exitcond_flatten_1_fu_442_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal to_b_V_fu_472_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_5_fu_488_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_fu_492_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal row_b_V_fu_483_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_4_fu_514_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal p_shl8_fu_521_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_mid2_cast_fu_511_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_7_mid2_cast_fu_531_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_fu_525_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_fu_534_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal p_shl_cast_fu_548_p3 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_cast_fu_560_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_14_fu_555_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_15_fu_563_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal ti_b_V_fu_574_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_fu_590_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal p_shl9_cast_fu_597_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_1_mid2_cast_fu_587_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_block_pp0_stage2_flag00000000 : BOOLEAN;
signal tmp_9_cast_cast_fu_649_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal sel_tmp1_fu_667_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp3_fu_672_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp7_fu_684_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp9_fu_689_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp5_fu_701_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp6_fu_706_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp8_fu_718_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp10_fu_723_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (50 downto 0);
signal ap_block_pp0_stage1_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage6_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage7_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage8_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage9_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage10_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage11_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage13_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage14_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage15_flag00011011 : BOOLEAN;
signal ap_block_state26_pp0_stage16_iter0 : BOOLEAN;
signal ap_block_pp0_stage16_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage16_flag00011001 : BOOLEAN;
signal ap_block_state27_pp0_stage17_iter0 : BOOLEAN;
signal ap_block_pp0_stage17_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage17_flag00011001 : BOOLEAN;
signal ap_block_pp0_stage18_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage19_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage20_flag00011011 : BOOLEAN;
signal ap_block_state31_pp0_stage21_iter0 : BOOLEAN;
signal ap_block_pp0_stage21_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage21_flag00011001 : BOOLEAN;
signal ap_block_state32_pp0_stage22_iter0 : BOOLEAN;
signal ap_block_pp0_stage22_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage22_flag00011001 : BOOLEAN;
signal ap_block_pp0_stage23_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage24_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage25_flag00011011 : BOOLEAN;
signal ap_block_state36_pp0_stage26_iter0 : BOOLEAN;
signal ap_block_pp0_stage26_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage26_flag00011001 : BOOLEAN;
signal ap_block_pp0_stage27_flag00011011 : BOOLEAN;
signal ap_block_state38_pp0_stage28_iter0 : BOOLEAN;
signal ap_block_pp0_stage28_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage28_flag00011001 : BOOLEAN;
signal ap_block_state39_pp0_stage29_iter0 : BOOLEAN;
signal ap_block_pp0_stage29_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage29_flag00011001 : BOOLEAN;
signal ap_block_pp0_stage30_flag00011011 : BOOLEAN;
signal ap_block_state41_pp0_stage31_iter0 : BOOLEAN;
signal ap_block_pp0_stage31_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage31_flag00011001 : BOOLEAN;
signal ap_block_state42_pp0_stage32_iter0 : BOOLEAN;
signal ap_block_pp0_stage32_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage32_flag00011001 : BOOLEAN;
signal ap_block_state43_pp0_stage33_iter0 : BOOLEAN;
signal ap_block_pp0_stage33_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage33_flag00011001 : BOOLEAN;
signal ap_block_state44_pp0_stage34_iter0 : BOOLEAN;
signal ap_block_pp0_stage34_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage34_flag00011001 : BOOLEAN;
signal ap_block_pp0_stage35_flag00011011 : BOOLEAN;
signal ap_block_state46_pp0_stage36_iter0 : BOOLEAN;
signal ap_block_pp0_stage36_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage36_flag00011001 : BOOLEAN;
signal ap_block_state47_pp0_stage37_iter0 : BOOLEAN;
signal ap_block_pp0_stage37_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage37_flag00011001 : BOOLEAN;
signal ap_block_state48_pp0_stage38_iter0 : BOOLEAN;
signal ap_block_pp0_stage38_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage38_flag00011001 : BOOLEAN;
signal ap_block_pp0_stage39_flag00011001 : BOOLEAN;
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component aesl_mux_load_7_3_x_s IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
empty_2_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_2_EN_A : OUT STD_LOGIC;
empty_2_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_2_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_2_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_3_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_3_EN_A : OUT STD_LOGIC;
empty_3_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_3_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_3_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_4_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_4_EN_A : OUT STD_LOGIC;
empty_4_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_4_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_4_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_5_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_5_EN_A : OUT STD_LOGIC;
empty_5_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_5_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_5_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_6_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_6_EN_A : OUT STD_LOGIC;
empty_6_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_6_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_6_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_7_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_7_EN_A : OUT STD_LOGIC;
empty_7_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_7_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_7_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_8_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_8_EN_A : OUT STD_LOGIC;
empty_8_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_8_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_8_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_9 : IN STD_LOGIC_VECTOR (2 downto 0);
empty_10 : IN STD_LOGIC_VECTOR (1 downto 0);
empty : IN STD_LOGIC_VECTOR (2 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component aesl_mux_load_5_3_x_s IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
empty_11_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_11_EN_A : OUT STD_LOGIC;
empty_11_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_11_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_11_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_12_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_12_EN_A : OUT STD_LOGIC;
empty_12_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_12_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_12_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_13_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_13_EN_A : OUT STD_LOGIC;
empty_13_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_13_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_13_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_14_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_14_EN_A : OUT STD_LOGIC;
empty_14_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_14_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_14_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_15_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_15_EN_A : OUT STD_LOGIC;
empty_15_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_15_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_15_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_16 : IN STD_LOGIC_VECTOR (2 downto 0);
empty_17 : IN STD_LOGIC_VECTOR (1 downto 0);
empty_18 : IN STD_LOGIC_VECTOR (1 downto 0);
empty : IN STD_LOGIC_VECTOR (3 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_fbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_fcud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
grp_aesl_mux_load_7_3_x_s_fu_316 : component aesl_mux_load_7_3_x_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_aesl_mux_load_7_3_x_s_fu_316_ap_start,
ap_done => grp_aesl_mux_load_7_3_x_s_fu_316_ap_done,
ap_idle => grp_aesl_mux_load_7_3_x_s_fu_316_ap_idle,
ap_ready => grp_aesl_mux_load_7_3_x_s_fu_316_ap_ready,
empty_2_Addr_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_2_Addr_A,
empty_2_EN_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_2_EN_A,
empty_2_WEN_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_2_WEN_A,
empty_2_Din_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_2_Din_A,
empty_2_Dout_A => bufi_0_Dout_A,
empty_3_Addr_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_3_Addr_A,
empty_3_EN_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_3_EN_A,
empty_3_WEN_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_3_WEN_A,
empty_3_Din_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_3_Din_A,
empty_3_Dout_A => bufi_1_Dout_A,
empty_4_Addr_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_4_Addr_A,
empty_4_EN_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_4_EN_A,
empty_4_WEN_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_4_WEN_A,
empty_4_Din_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_4_Din_A,
empty_4_Dout_A => bufi_2_Dout_A,
empty_5_Addr_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_5_Addr_A,
empty_5_EN_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_5_EN_A,
empty_5_WEN_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_5_WEN_A,
empty_5_Din_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_5_Din_A,
empty_5_Dout_A => bufi_3_Dout_A,
empty_6_Addr_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_6_Addr_A,
empty_6_EN_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_6_EN_A,
empty_6_WEN_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_6_WEN_A,
empty_6_Din_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_6_Din_A,
empty_6_Dout_A => bufi_4_Dout_A,
empty_7_Addr_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_7_Addr_A,
empty_7_EN_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_7_EN_A,
empty_7_WEN_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_7_WEN_A,
empty_7_Din_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_7_Din_A,
empty_7_Dout_A => bufi_5_Dout_A,
empty_8_Addr_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_8_Addr_A,
empty_8_EN_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_8_EN_A,
empty_8_WEN_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_8_WEN_A,
empty_8_Din_A => grp_aesl_mux_load_7_3_x_s_fu_316_empty_8_Din_A,
empty_8_Dout_A => bufi_6_Dout_A,
empty_9 => tmp_12_48_t_reg_883,
empty_10 => tmp_1_mid2_v_reg_859,
empty => tmp_9_reg_921,
ap_return => grp_aesl_mux_load_7_3_x_s_fu_316_ap_return);
grp_aesl_mux_load_5_3_x_s_fu_337 : component aesl_mux_load_5_3_x_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_aesl_mux_load_5_3_x_s_fu_337_ap_start,
ap_done => grp_aesl_mux_load_5_3_x_s_fu_337_ap_done,
ap_idle => grp_aesl_mux_load_5_3_x_s_fu_337_ap_idle,
ap_ready => grp_aesl_mux_load_5_3_x_s_fu_337_ap_ready,
ap_ce => ap_const_logic_1,
empty_11_Addr_A => grp_aesl_mux_load_5_3_x_s_fu_337_empty_11_Addr_A,
empty_11_EN_A => grp_aesl_mux_load_5_3_x_s_fu_337_empty_11_EN_A,
empty_11_WEN_A => grp_aesl_mux_load_5_3_x_s_fu_337_empty_11_WEN_A,
empty_11_Din_A => grp_aesl_mux_load_5_3_x_s_fu_337_empty_11_Din_A,
empty_11_Dout_A => bufw_0_Dout_A,
empty_12_Addr_A => grp_aesl_mux_load_5_3_x_s_fu_337_empty_12_Addr_A,
empty_12_EN_A => grp_aesl_mux_load_5_3_x_s_fu_337_empty_12_EN_A,
empty_12_WEN_A => grp_aesl_mux_load_5_3_x_s_fu_337_empty_12_WEN_A,
empty_12_Din_A => grp_aesl_mux_load_5_3_x_s_fu_337_empty_12_Din_A,
empty_12_Dout_A => bufw_1_Dout_A,
empty_13_Addr_A => grp_aesl_mux_load_5_3_x_s_fu_337_empty_13_Addr_A,
empty_13_EN_A => grp_aesl_mux_load_5_3_x_s_fu_337_empty_13_EN_A,
empty_13_WEN_A => grp_aesl_mux_load_5_3_x_s_fu_337_empty_13_WEN_A,
empty_13_Din_A => grp_aesl_mux_load_5_3_x_s_fu_337_empty_13_Din_A,
empty_13_Dout_A => bufw_2_Dout_A,
empty_14_Addr_A => grp_aesl_mux_load_5_3_x_s_fu_337_empty_14_Addr_A,
empty_14_EN_A => grp_aesl_mux_load_5_3_x_s_fu_337_empty_14_EN_A,
empty_14_WEN_A => grp_aesl_mux_load_5_3_x_s_fu_337_empty_14_WEN_A,
empty_14_Din_A => grp_aesl_mux_load_5_3_x_s_fu_337_empty_14_Din_A,
empty_14_Dout_A => bufw_3_Dout_A,
empty_15_Addr_A => grp_aesl_mux_load_5_3_x_s_fu_337_empty_15_Addr_A,
empty_15_EN_A => grp_aesl_mux_load_5_3_x_s_fu_337_empty_15_EN_A,
empty_15_WEN_A => grp_aesl_mux_load_5_3_x_s_fu_337_empty_15_WEN_A,
empty_15_Din_A => grp_aesl_mux_load_5_3_x_s_fu_337_empty_15_Din_A,
empty_15_Dout_A => bufw_4_Dout_A,
empty_16 => p_4_reg_294,
empty_17 => tmp_4_mid2_reg_819,
empty_18 => tmp_1_mid2_v_reg_859,
empty => grp_aesl_mux_load_5_3_x_s_fu_337_empty,
ap_return => grp_aesl_mux_load_5_3_x_s_fu_337_ap_return);
convolve_kernel_fbkb_U7 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_361_p0,
din1 => grp_fu_361_p1,
ce => ap_const_logic_1,
dout => grp_fu_361_p2);
convolve_kernel_fcud_U8 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => reg_371,
din1 => grp_fu_367_p1,
ce => ap_const_logic_1,
dout => grp_fu_367_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state10))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state10) and (((ap_block_pp0_stage39_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39)) or ((ap_block_pp0_stage12_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12))))) then
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state10 xor ap_const_logic_1);
elsif ((((ap_block_pp0_stage39_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39)) or ((ap_block_pp0_stage12_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12)))) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_reg_grp_aesl_mux_load_5_3_x_s_fu_337_ap_start_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_grp_aesl_mux_load_5_3_x_s_fu_337_ap_start <= ap_const_logic_0;
else
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (tmp_3_reg_912 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = tmp_3_fu_632_p2)))) then
ap_reg_grp_aesl_mux_load_5_3_x_s_fu_337_ap_start <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_aesl_mux_load_5_3_x_s_fu_337_ap_ready)) then
ap_reg_grp_aesl_mux_load_5_3_x_s_fu_337_ap_start <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_reg_grp_aesl_mux_load_7_3_x_s_fu_316_ap_start_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_grp_aesl_mux_load_7_3_x_s_fu_316_ap_start <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then
ap_reg_grp_aesl_mux_load_7_3_x_s_fu_316_ap_start <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_aesl_mux_load_7_3_x_s_fu_316_ap_ready)) then
ap_reg_grp_aesl_mux_load_7_3_x_s_fu_316_ap_start <= ap_const_logic_0;
end if;
end if;
end if;
end process;
indvar_flatten1_reg_211_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state64)) then
indvar_flatten1_reg_211 <= indvar_flatten_next2_reg_767;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
indvar_flatten1_reg_211 <= ap_const_lv7_0;
end if;
end if;
end process;
indvar_flatten2_reg_234_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state64)) then
indvar_flatten2_reg_234 <= indvar_flatten_next1_fu_758_p3;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
indvar_flatten2_reg_234 <= ap_const_lv6_0;
end if;
end if;
end process;
indvar_flatten_reg_258_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state64)) then
indvar_flatten_reg_258 <= indvar_flatten_next_fu_752_p3;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
indvar_flatten_reg_258 <= ap_const_lv4_0;
end if;
end if;
end process;
p_1_reg_246_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state64)) then
p_1_reg_246 <= tmp_4_mid2_reg_819;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
p_1_reg_246 <= ap_const_lv2_0;
end if;
end if;
end process;
p_2_reg_270_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state64)) then
p_2_reg_270 <= tmp_7_mid2_reg_837;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
p_2_reg_270 <= ap_const_lv2_0;
end if;
end if;
end process;
p_3_reg_282_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state64)) then
p_3_reg_282 <= col_b_V_reg_1047;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
p_3_reg_282 <= ap_const_lv2_0;
end if;
end if;
end process;
p_4_reg_294_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
p_4_reg_294 <= i_V_reg_916;
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
p_4_reg_294 <= ap_const_lv3_0;
end if;
end if;
end process;
p_s_reg_222_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state64)) then
p_s_reg_222 <= tmp_1_mid2_v_reg_859;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
p_s_reg_222 <= ap_const_lv2_0;
end if;
end if;
end process;
temp1_reg_306_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_3_reg_912) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0))) then
temp1_reg_306 <= grp_fu_361_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
temp1_reg_306 <= bufo_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter1_tmp_3_reg_912 <= tmp_3_reg_912;
tmp_3_reg_912 <= tmp_3_fu_632_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_lv1_0 = sel_tmp2_reg_896) and (sel_tmp_reg_888 = ap_const_lv1_1) and (ap_const_lv1_0 = sel_tmp4_reg_904) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then
bufi_0_load_reg_975 <= bufi_0_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then
bufi_1_load_reg_980 <= bufi_1_Dout_A;
bufi_2_load_reg_986 <= bufi_2_Dout_A;
bufi_3_load_reg_967 <= bufi_3_Dout_A;
bufi_4_load_reg_993 <= bufi_4_Dout_A;
bufi_5_load_reg_1000 <= bufi_5_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_lv1_0 = sel_tmp2_reg_896) and (ap_const_lv1_0 = sel_tmp4_reg_904) and (ap_const_lv1_0 = sel_tmp_reg_888) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then
bufi_6_load_reg_1006 <= bufi_6_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (tmp_3_reg_912 = ap_const_lv1_0))) then
bufi_load_0_phi_reg_1011 <= bufi_load_0_phi_fu_678_p3;
bufi_load_1_phi_reg_1016 <= bufi_load_1_phi_fu_695_p3;
bufi_load_2_phi_reg_1021 <= bufi_load_2_phi_fu_712_p3;
bufi_load_3_phi_reg_1026 <= bufi_load_3_phi_fu_729_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
bufo_addr_reg_854 <= tmp_18_cast_fu_569_p1(5 - 1 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state63)) then
col_b_V_reg_1047 <= col_b_V_fu_735_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv1_0 = exitcond_flatten2_fu_391_p2))) then
exitcond_flatten1_reg_783 <= exitcond_flatten1_fu_409_p2;
exitcond_flatten_reg_772 <= exitcond_flatten_fu_403_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
exitcond_flatten_mid_reg_789 <= exitcond_flatten_mid_fu_432_p2;
tmp_8_mid1_reg_796 <= tmp_8_mid1_fu_447_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
i_V_reg_916 <= i_V_fu_638_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state63) and (ap_const_lv1_0 = exitcond_flatten_reg_772))) then
indvar_flatten15_op_reg_1057 <= indvar_flatten15_op_fu_746_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
indvar_flatten_next2_reg_767 <= indvar_flatten_next2_fu_397_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state63) and (ap_const_lv1_0 = tmp_2_reg_808))) then
indvar_flatten_op_reg_1052 <= indvar_flatten_op_fu_740_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
p_1_mid_reg_802 <= p_1_mid_fu_453_p3;
p_2_mid_reg_813 <= p_2_mid_fu_464_p3;
tmp_2_reg_808 <= tmp_2_fu_460_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
p_3_mid2_reg_827 <= p_3_mid2_fu_497_p3;
tmp_4_mid2_reg_819 <= tmp_4_mid2_fu_477_p3;
tmp_7_mid2_reg_837 <= tmp_7_mid2_fu_505_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (tmp_3_reg_912 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)))) then
reg_371 <= grp_aesl_mux_load_5_3_x_s_fu_337_ap_return;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)))) then
reg_376 <= grp_fu_367_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)))) then
reg_381 <= grp_fu_367_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
sel_tmp2_reg_896 <= sel_tmp2_fu_622_p2;
sel_tmp4_reg_904 <= sel_tmp4_fu_627_p2;
sel_tmp_reg_888 <= sel_tmp_fu_617_p2;
tmp_12_48_t_reg_883(1 downto 0) <= tmp_12_48_t_fu_610_p3(1 downto 0);
tmp_1_reg_868 <= tmp_1_fu_601_p2;
tmp_7_cast_mid2_cast_reg_873(1 downto 0) <= tmp_7_cast_mid2_cast_fu_607_p1(1 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_3_reg_912) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0))) then
temp_2_4_reg_1041 <= grp_fu_361_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state6)) then
tmp_11_reg_844 <= tmp_11_fu_540_p1;
tmp_12_reg_849 <= tmp_12_fu_544_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0))) then
tmp_13_3_reg_1036 <= grp_fu_367_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
tmp_16_reg_927 <= tmp_16_fu_652_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
tmp_1_mid2_v_reg_859 <= tmp_1_mid2_v_fu_580_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0))) then
tmp_22_reg_1031 <= grp_aesl_mux_load_7_3_x_s_fu_316_ap_return;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
tmp_9_reg_921 <= tmp_9_fu_644_p2;
end if;
end if;
end process;
tmp_7_cast_mid2_cast_reg_873(2) <= '0';
tmp_12_48_t_reg_883(2) <= '1';
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_CS_fsm_state2, exitcond_flatten2_fu_391_p2, tmp_3_fu_632_p2, ap_block_pp0_stage0_flag00011011, ap_block_pp0_stage39_flag00011011, ap_block_pp0_stage12_flag00011011, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage1_flag00011011, ap_block_pp0_stage2_flag00011011, ap_block_pp0_stage3_flag00011011, ap_block_pp0_stage4_flag00011011, ap_block_pp0_stage5_flag00011011, ap_block_pp0_stage6_flag00011011, ap_block_pp0_stage7_flag00011011, ap_block_pp0_stage8_flag00011011, ap_block_pp0_stage9_flag00011011, ap_block_pp0_stage10_flag00011011, ap_block_pp0_stage11_flag00011011, ap_block_pp0_stage13_flag00011011, ap_block_pp0_stage14_flag00011011, ap_block_pp0_stage15_flag00011011, ap_block_pp0_stage16_flag00011011, ap_block_pp0_stage17_flag00011011, ap_block_pp0_stage18_flag00011011, ap_block_pp0_stage19_flag00011011, ap_block_pp0_stage20_flag00011011, ap_block_pp0_stage21_flag00011011, ap_block_pp0_stage22_flag00011011, ap_block_pp0_stage23_flag00011011, ap_block_pp0_stage24_flag00011011, ap_block_pp0_stage25_flag00011011, ap_block_pp0_stage26_flag00011011, ap_block_pp0_stage27_flag00011011, ap_block_pp0_stage28_flag00011011, ap_block_pp0_stage29_flag00011011, ap_block_pp0_stage30_flag00011011, ap_block_pp0_stage31_flag00011011, ap_block_pp0_stage32_flag00011011, ap_block_pp0_stage33_flag00011011, ap_block_pp0_stage34_flag00011011, ap_block_pp0_stage35_flag00011011, ap_block_pp0_stage36_flag00011011, ap_block_pp0_stage37_flag00011011, ap_block_pp0_stage38_flag00011011)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (exitcond_flatten2_fu_391_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state6;
when ap_ST_fsm_state6 =>
ap_NS_fsm <= ap_ST_fsm_state7;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_state8;
when ap_ST_fsm_state8 =>
ap_NS_fsm <= ap_ST_fsm_state9;
when ap_ST_fsm_state9 =>
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
when ap_ST_fsm_pp0_stage0 =>
if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (tmp_3_fu_632_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (tmp_3_fu_632_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state63;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage1 =>
if ((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
end if;
when ap_ST_fsm_pp0_stage2 =>
if ((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
end if;
when ap_ST_fsm_pp0_stage3 =>
if ((ap_block_pp0_stage3_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
end if;
when ap_ST_fsm_pp0_stage4 =>
if ((ap_block_pp0_stage4_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
end if;
when ap_ST_fsm_pp0_stage5 =>
if ((ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
end if;
when ap_ST_fsm_pp0_stage6 =>
if ((ap_block_pp0_stage6_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
end if;
when ap_ST_fsm_pp0_stage7 =>
if ((ap_block_pp0_stage7_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage8;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
end if;
when ap_ST_fsm_pp0_stage8 =>
if ((ap_block_pp0_stage8_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage9;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage8;
end if;
when ap_ST_fsm_pp0_stage9 =>
if ((ap_block_pp0_stage9_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage10;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage9;
end if;
when ap_ST_fsm_pp0_stage10 =>
if ((ap_block_pp0_stage10_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage11;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage10;
end if;
when ap_ST_fsm_pp0_stage11 =>
if ((ap_block_pp0_stage11_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage12;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage11;
end if;
when ap_ST_fsm_pp0_stage12 =>
if (((ap_block_pp0_stage12_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage12_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage13;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage12_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state63;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage12;
end if;
when ap_ST_fsm_pp0_stage13 =>
if ((ap_block_pp0_stage13_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage14;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage13;
end if;
when ap_ST_fsm_pp0_stage14 =>
if ((ap_block_pp0_stage14_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage15;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage14;
end if;
when ap_ST_fsm_pp0_stage15 =>
if ((ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage16;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage15;
end if;
when ap_ST_fsm_pp0_stage16 =>
if ((ap_block_pp0_stage16_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage17;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage16;
end if;
when ap_ST_fsm_pp0_stage17 =>
if ((ap_block_pp0_stage17_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage18;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage17;
end if;
when ap_ST_fsm_pp0_stage18 =>
if ((ap_block_pp0_stage18_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage19;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage18;
end if;
when ap_ST_fsm_pp0_stage19 =>
if ((ap_block_pp0_stage19_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage20;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage19;
end if;
when ap_ST_fsm_pp0_stage20 =>
if ((ap_block_pp0_stage20_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage21;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage20;
end if;
when ap_ST_fsm_pp0_stage21 =>
if ((ap_block_pp0_stage21_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage22;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage21;
end if;
when ap_ST_fsm_pp0_stage22 =>
if ((ap_block_pp0_stage22_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage23;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage22;
end if;
when ap_ST_fsm_pp0_stage23 =>
if ((ap_block_pp0_stage23_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage24;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage23;
end if;
when ap_ST_fsm_pp0_stage24 =>
if ((ap_block_pp0_stage24_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage25;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage24;
end if;
when ap_ST_fsm_pp0_stage25 =>
if ((ap_block_pp0_stage25_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage26;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage25;
end if;
when ap_ST_fsm_pp0_stage26 =>
if ((ap_block_pp0_stage26_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage27;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage26;
end if;
when ap_ST_fsm_pp0_stage27 =>
if ((ap_block_pp0_stage27_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage28;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage27;
end if;
when ap_ST_fsm_pp0_stage28 =>
if ((ap_block_pp0_stage28_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage29;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage28;
end if;
when ap_ST_fsm_pp0_stage29 =>
if ((ap_block_pp0_stage29_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage30;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage29;
end if;
when ap_ST_fsm_pp0_stage30 =>
if ((ap_block_pp0_stage30_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage31;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage30;
end if;
when ap_ST_fsm_pp0_stage31 =>
if ((ap_block_pp0_stage31_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage32;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage31;
end if;
when ap_ST_fsm_pp0_stage32 =>
if ((ap_block_pp0_stage32_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage33;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage32;
end if;
when ap_ST_fsm_pp0_stage33 =>
if ((ap_block_pp0_stage33_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage34;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage33;
end if;
when ap_ST_fsm_pp0_stage34 =>
if ((ap_block_pp0_stage34_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage35;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage34;
end if;
when ap_ST_fsm_pp0_stage35 =>
if ((ap_block_pp0_stage35_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage36;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage35;
end if;
when ap_ST_fsm_pp0_stage36 =>
if ((ap_block_pp0_stage36_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage37;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage36;
end if;
when ap_ST_fsm_pp0_stage37 =>
if ((ap_block_pp0_stage37_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage38;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage37;
end if;
when ap_ST_fsm_pp0_stage38 =>
if ((ap_block_pp0_stage38_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage39;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage38;
end if;
when ap_ST_fsm_pp0_stage39 =>
if ((ap_block_pp0_stage39_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage39;
end if;
when ap_ST_fsm_state63 =>
ap_NS_fsm <= ap_ST_fsm_state64;
when ap_ST_fsm_state64 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(9);
ap_CS_fsm_pp0_stage1 <= ap_CS_fsm(10);
ap_CS_fsm_pp0_stage10 <= ap_CS_fsm(19);
ap_CS_fsm_pp0_stage11 <= ap_CS_fsm(20);
ap_CS_fsm_pp0_stage12 <= ap_CS_fsm(21);
ap_CS_fsm_pp0_stage13 <= ap_CS_fsm(22);
ap_CS_fsm_pp0_stage14 <= ap_CS_fsm(23);
ap_CS_fsm_pp0_stage15 <= ap_CS_fsm(24);
ap_CS_fsm_pp0_stage16 <= ap_CS_fsm(25);
ap_CS_fsm_pp0_stage18 <= ap_CS_fsm(27);
ap_CS_fsm_pp0_stage19 <= ap_CS_fsm(28);
ap_CS_fsm_pp0_stage2 <= ap_CS_fsm(11);
ap_CS_fsm_pp0_stage20 <= ap_CS_fsm(29);
ap_CS_fsm_pp0_stage21 <= ap_CS_fsm(30);
ap_CS_fsm_pp0_stage23 <= ap_CS_fsm(32);
ap_CS_fsm_pp0_stage24 <= ap_CS_fsm(33);
ap_CS_fsm_pp0_stage25 <= ap_CS_fsm(34);
ap_CS_fsm_pp0_stage26 <= ap_CS_fsm(35);
ap_CS_fsm_pp0_stage27 <= ap_CS_fsm(36);
ap_CS_fsm_pp0_stage3 <= ap_CS_fsm(12);
ap_CS_fsm_pp0_stage30 <= ap_CS_fsm(39);
ap_CS_fsm_pp0_stage35 <= ap_CS_fsm(44);
ap_CS_fsm_pp0_stage39 <= ap_CS_fsm(48);
ap_CS_fsm_pp0_stage4 <= ap_CS_fsm(13);
ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(14);
ap_CS_fsm_pp0_stage6 <= ap_CS_fsm(15);
ap_CS_fsm_pp0_stage7 <= ap_CS_fsm(16);
ap_CS_fsm_pp0_stage8 <= ap_CS_fsm(17);
ap_CS_fsm_pp0_stage9 <= ap_CS_fsm(18);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state63 <= ap_CS_fsm(49);
ap_CS_fsm_state64 <= ap_CS_fsm(50);
ap_CS_fsm_state7 <= ap_CS_fsm(6);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_CS_fsm_state9 <= ap_CS_fsm(8);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage10_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage10_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage13_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage13_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage13_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage14_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage14_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage14_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage15_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage15_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage16_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage16_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage16_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage17_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage17_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage18_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage18_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage18_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage19_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage19_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage19_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage20_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage20_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage21_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage21_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage21_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage22_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage22_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage23_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage23_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage23_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage24_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage24_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage24_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage25_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage25_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage26_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage26_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage26_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage27_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage27_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage27_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage28_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage28_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage29_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage29_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage30_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage30_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage31_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage31_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage32_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage32_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage33_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage33_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage34_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage34_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage35_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage35_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage35_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage36_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage36_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage37_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage37_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage38_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage38_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage39_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage39_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state10_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state14_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state15_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state16_pp0_stage6_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state17_pp0_stage7_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state18_pp0_stage8_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state19_pp0_stage9_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state20_pp0_stage10_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state21_pp0_stage11_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state22_pp0_stage12_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state23_pp0_stage13_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state24_pp0_stage14_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state25_pp0_stage15_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state26_pp0_stage16_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state27_pp0_stage17_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state28_pp0_stage18_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state29_pp0_stage19_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state30_pp0_stage20_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state31_pp0_stage21_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state32_pp0_stage22_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state33_pp0_stage23_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state34_pp0_stage24_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state35_pp0_stage25_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state36_pp0_stage26_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state37_pp0_stage27_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state38_pp0_stage28_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state39_pp0_stage29_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state40_pp0_stage30_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state41_pp0_stage31_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state42_pp0_stage32_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state43_pp0_stage33_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state44_pp0_stage34_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state45_pp0_stage35_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state46_pp0_stage36_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state47_pp0_stage37_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state48_pp0_stage38_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state49_pp0_stage39_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state50_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state51_pp0_stage1_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state52_pp0_stage2_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state53_pp0_stage3_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state54_pp0_stage4_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state55_pp0_stage5_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state56_pp0_stage6_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state57_pp0_stage7_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state58_pp0_stage8_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state59_pp0_stage9_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state60_pp0_stage10_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state61_pp0_stage11_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state62_pp0_stage12_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_pp0_exit_iter0_state10_assign_proc : process(tmp_3_fu_632_p2)
begin
if ((tmp_3_fu_632_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state10 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state10 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_CS_fsm_state2, exitcond_flatten2_fu_391_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (exitcond_flatten2_fu_391_p2 = ap_const_lv1_1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state2, exitcond_flatten2_fu_391_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (exitcond_flatten2_fu_391_p2 = ap_const_lv1_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
bufi_0_Addr_A_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_3_reg_912, grp_aesl_mux_load_7_3_x_s_fu_316_empty_2_Addr_A, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00000000, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00000000, bufi_0_Addr_A_orig)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0)))) then
bufi_0_Addr_A <= grp_aesl_mux_load_7_3_x_s_fu_316_empty_2_Addr_A;
else
bufi_0_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_0_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
end if;
end process;
bufi_0_Addr_A_orig <= tmp_20_cast_fu_657_p1;
bufi_0_Clk_A <= ap_clk;
bufi_0_Din_A <= ap_const_lv32_0;
bufi_0_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_3_reg_912, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, grp_aesl_mux_load_7_3_x_s_fu_316_empty_2_EN_A, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then
bufi_0_EN_A <= ap_const_logic_1;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)))) then
bufi_0_EN_A <= grp_aesl_mux_load_7_3_x_s_fu_316_empty_2_EN_A;
else
bufi_0_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_0_Rst_A <= ap_rst;
bufi_0_WEN_A <= ap_const_lv4_0;
bufi_1_Addr_A_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_3_reg_912, grp_aesl_mux_load_7_3_x_s_fu_316_empty_3_Addr_A, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00000000, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00000000, bufi_1_Addr_A_orig)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0)))) then
bufi_1_Addr_A <= grp_aesl_mux_load_7_3_x_s_fu_316_empty_3_Addr_A;
else
bufi_1_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_1_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
end if;
end process;
bufi_1_Addr_A_orig <= tmp_20_cast_fu_657_p1;
bufi_1_Clk_A <= ap_clk;
bufi_1_Din_A <= ap_const_lv32_0;
bufi_1_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_3_reg_912, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, grp_aesl_mux_load_7_3_x_s_fu_316_empty_3_EN_A, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then
bufi_1_EN_A <= ap_const_logic_1;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)))) then
bufi_1_EN_A <= grp_aesl_mux_load_7_3_x_s_fu_316_empty_3_EN_A;
else
bufi_1_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_1_Rst_A <= ap_rst;
bufi_1_WEN_A <= ap_const_lv4_0;
bufi_2_Addr_A_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_3_reg_912, grp_aesl_mux_load_7_3_x_s_fu_316_empty_4_Addr_A, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00000000, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00000000, bufi_2_Addr_A_orig)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0)))) then
bufi_2_Addr_A <= grp_aesl_mux_load_7_3_x_s_fu_316_empty_4_Addr_A;
else
bufi_2_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_2_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
end if;
end process;
bufi_2_Addr_A_orig <= tmp_20_cast_fu_657_p1;
bufi_2_Clk_A <= ap_clk;
bufi_2_Din_A <= ap_const_lv32_0;
bufi_2_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_3_reg_912, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, grp_aesl_mux_load_7_3_x_s_fu_316_empty_4_EN_A, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then
bufi_2_EN_A <= ap_const_logic_1;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)))) then
bufi_2_EN_A <= grp_aesl_mux_load_7_3_x_s_fu_316_empty_4_EN_A;
else
bufi_2_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_2_Rst_A <= ap_rst;
bufi_2_WEN_A <= ap_const_lv4_0;
bufi_3_Addr_A_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_3_reg_912, grp_aesl_mux_load_7_3_x_s_fu_316_empty_5_Addr_A, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00000000, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00000000, bufi_3_Addr_A_orig)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0)))) then
bufi_3_Addr_A <= grp_aesl_mux_load_7_3_x_s_fu_316_empty_5_Addr_A;
else
bufi_3_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_3_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
end if;
end process;
bufi_3_Addr_A_orig <= tmp_20_cast_fu_657_p1;
bufi_3_Clk_A <= ap_clk;
bufi_3_Din_A <= ap_const_lv32_0;
bufi_3_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_3_reg_912, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, grp_aesl_mux_load_7_3_x_s_fu_316_empty_5_EN_A, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then
bufi_3_EN_A <= ap_const_logic_1;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)))) then
bufi_3_EN_A <= grp_aesl_mux_load_7_3_x_s_fu_316_empty_5_EN_A;
else
bufi_3_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_3_Rst_A <= ap_rst;
bufi_3_WEN_A <= ap_const_lv4_0;
bufi_4_Addr_A_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_3_reg_912, grp_aesl_mux_load_7_3_x_s_fu_316_empty_6_Addr_A, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00000000, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00000000, bufi_4_Addr_A_orig)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0)))) then
bufi_4_Addr_A <= grp_aesl_mux_load_7_3_x_s_fu_316_empty_6_Addr_A;
else
bufi_4_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_4_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
end if;
end process;
bufi_4_Addr_A_orig <= tmp_20_cast_fu_657_p1;
bufi_4_Clk_A <= ap_clk;
bufi_4_Din_A <= ap_const_lv32_0;
bufi_4_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_3_reg_912, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, grp_aesl_mux_load_7_3_x_s_fu_316_empty_6_EN_A, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then
bufi_4_EN_A <= ap_const_logic_1;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)))) then
bufi_4_EN_A <= grp_aesl_mux_load_7_3_x_s_fu_316_empty_6_EN_A;
else
bufi_4_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_4_Rst_A <= ap_rst;
bufi_4_WEN_A <= ap_const_lv4_0;
bufi_5_Addr_A_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_3_reg_912, grp_aesl_mux_load_7_3_x_s_fu_316_empty_7_Addr_A, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00000000, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00000000, bufi_5_Addr_A_orig)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0)))) then
bufi_5_Addr_A <= grp_aesl_mux_load_7_3_x_s_fu_316_empty_7_Addr_A;
else
bufi_5_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_5_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
end if;
end process;
bufi_5_Addr_A_orig <= tmp_20_cast_fu_657_p1;
bufi_5_Clk_A <= ap_clk;
bufi_5_Din_A <= ap_const_lv32_0;
bufi_5_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_3_reg_912, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, grp_aesl_mux_load_7_3_x_s_fu_316_empty_7_EN_A, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then
bufi_5_EN_A <= ap_const_logic_1;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)))) then
bufi_5_EN_A <= grp_aesl_mux_load_7_3_x_s_fu_316_empty_7_EN_A;
else
bufi_5_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_5_Rst_A <= ap_rst;
bufi_5_WEN_A <= ap_const_lv4_0;
bufi_6_Addr_A_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_3_reg_912, grp_aesl_mux_load_7_3_x_s_fu_316_empty_8_Addr_A, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00000000, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00000000, bufi_6_Addr_A_orig)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0)))) then
bufi_6_Addr_A <= grp_aesl_mux_load_7_3_x_s_fu_316_empty_8_Addr_A;
else
bufi_6_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_6_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
end if;
end process;
bufi_6_Addr_A_orig <= tmp_20_cast_fu_657_p1;
bufi_6_Clk_A <= ap_clk;
bufi_6_Din_A <= ap_const_lv32_0;
bufi_6_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_3_reg_912, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, grp_aesl_mux_load_7_3_x_s_fu_316_empty_8_EN_A, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then
bufi_6_EN_A <= ap_const_logic_1;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)))) then
bufi_6_EN_A <= grp_aesl_mux_load_7_3_x_s_fu_316_empty_8_EN_A;
else
bufi_6_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_6_Rst_A <= ap_rst;
bufi_6_WEN_A <= ap_const_lv4_0;
bufi_load_0_phi_fu_678_p3 <=
bufi_2_load_reg_986 when (sel_tmp4_reg_904(0) = '1') else
sel_tmp3_fu_672_p3;
bufi_load_1_phi_fu_695_p3 <=
bufi_3_load_reg_967 when (sel_tmp4_reg_904(0) = '1') else
sel_tmp9_fu_689_p3;
bufi_load_2_phi_fu_712_p3 <=
bufi_4_load_reg_993 when (sel_tmp4_reg_904(0) = '1') else
sel_tmp6_fu_706_p3;
bufi_load_3_phi_fu_729_p3 <=
bufi_5_load_reg_1000 when (sel_tmp4_reg_904(0) = '1') else
sel_tmp10_fu_723_p3;
bufo_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufo_addr_reg_854),32));
bufo_Clk_A <= ap_clk;
bufo_Din_A <= temp_2_4_reg_1041;
bufo_EN_A_assign_proc : process(ap_enable_reg_pp0_iter1, ap_CS_fsm_state8, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state8) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)))) then
bufo_EN_A <= ap_const_logic_1;
else
bufo_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_Rst_A <= ap_rst;
bufo_WEN_A_assign_proc : process(ap_enable_reg_pp0_iter1, ap_reg_pp0_iter1_tmp_3_reg_912, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_3_reg_912) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0))) then
bufo_WEN_A <= ap_const_lv4_F;
else
bufo_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufw_0_Addr_A <= grp_aesl_mux_load_5_3_x_s_fu_337_empty_11_Addr_A;
bufw_0_Clk_A <= ap_clk;
bufw_0_Din_A <= ap_const_lv32_0;
bufw_0_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_3_reg_912, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, grp_aesl_mux_load_5_3_x_s_fu_337_empty_11_EN_A, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00011001)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)))) then
bufw_0_EN_A <= grp_aesl_mux_load_5_3_x_s_fu_337_empty_11_EN_A;
else
bufw_0_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_0_Rst_A <= ap_rst;
bufw_0_WEN_A <= ap_const_lv4_0;
bufw_1_Addr_A <= grp_aesl_mux_load_5_3_x_s_fu_337_empty_12_Addr_A;
bufw_1_Clk_A <= ap_clk;
bufw_1_Din_A <= ap_const_lv32_0;
bufw_1_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_3_reg_912, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, grp_aesl_mux_load_5_3_x_s_fu_337_empty_12_EN_A, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00011001)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)))) then
bufw_1_EN_A <= grp_aesl_mux_load_5_3_x_s_fu_337_empty_12_EN_A;
else
bufw_1_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_1_Rst_A <= ap_rst;
bufw_1_WEN_A <= ap_const_lv4_0;
bufw_2_Addr_A <= grp_aesl_mux_load_5_3_x_s_fu_337_empty_13_Addr_A;
bufw_2_Clk_A <= ap_clk;
bufw_2_Din_A <= ap_const_lv32_0;
bufw_2_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_3_reg_912, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, grp_aesl_mux_load_5_3_x_s_fu_337_empty_13_EN_A, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00011001)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)))) then
bufw_2_EN_A <= grp_aesl_mux_load_5_3_x_s_fu_337_empty_13_EN_A;
else
bufw_2_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_2_Rst_A <= ap_rst;
bufw_2_WEN_A <= ap_const_lv4_0;
bufw_3_Addr_A <= grp_aesl_mux_load_5_3_x_s_fu_337_empty_14_Addr_A;
bufw_3_Clk_A <= ap_clk;
bufw_3_Din_A <= ap_const_lv32_0;
bufw_3_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_3_reg_912, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, grp_aesl_mux_load_5_3_x_s_fu_337_empty_14_EN_A, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00011001)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)))) then
bufw_3_EN_A <= grp_aesl_mux_load_5_3_x_s_fu_337_empty_14_EN_A;
else
bufw_3_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_3_Rst_A <= ap_rst;
bufw_3_WEN_A <= ap_const_lv4_0;
bufw_4_Addr_A <= grp_aesl_mux_load_5_3_x_s_fu_337_empty_15_Addr_A;
bufw_4_Clk_A <= ap_clk;
bufw_4_Din_A <= ap_const_lv32_0;
bufw_4_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_3_reg_912, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, grp_aesl_mux_load_5_3_x_s_fu_337_empty_15_EN_A, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00011001)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)))) then
bufw_4_EN_A <= grp_aesl_mux_load_5_3_x_s_fu_337_empty_15_EN_A;
else
bufw_4_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_4_Rst_A <= ap_rst;
bufw_4_WEN_A <= ap_const_lv4_0;
col_b_V_fu_735_p2 <= std_logic_vector(unsigned(p_3_mid2_reg_827) + unsigned(ap_const_lv2_1));
exitcond_flatten1_fu_409_p2 <= "1" when (indvar_flatten_reg_258 = ap_const_lv4_9) else "0";
exitcond_flatten2_fu_391_p2 <= "1" when (indvar_flatten1_reg_211 = ap_const_lv7_51) else "0";
exitcond_flatten_fu_403_p2 <= "1" when (indvar_flatten2_reg_234 = ap_const_lv6_1B) else "0";
exitcond_flatten_mid_fu_432_p2 <= (exitcond_flatten1_reg_783 and not_exitcond_flatten_fu_415_p2);
exitcond_flatten_not_fu_437_p2 <= (exitcond_flatten1_reg_783 xor ap_const_lv1_1);
grp_aesl_mux_load_5_3_x_s_fu_337_ap_start <= ap_reg_grp_aesl_mux_load_5_3_x_s_fu_337_ap_start;
grp_aesl_mux_load_5_3_x_s_fu_337_empty_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_3_reg_912, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00000000, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage1_flag00000000, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage16_flag00000000, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage21_flag00000000)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_3_reg_912 = ap_const_lv1_0))) then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0))) then
grp_aesl_mux_load_5_3_x_s_fu_337_empty <= ap_const_lv4_4;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0))) then
grp_aesl_mux_load_5_3_x_s_fu_337_empty <= ap_const_lv4_3;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_aesl_mux_load_5_3_x_s_fu_337_empty <= ap_const_lv4_2;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_aesl_mux_load_5_3_x_s_fu_337_empty <= ap_const_lv4_1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_aesl_mux_load_5_3_x_s_fu_337_empty <= ap_const_lv4_0;
else
grp_aesl_mux_load_5_3_x_s_fu_337_empty <= "XXXX";
end if;
else
grp_aesl_mux_load_5_3_x_s_fu_337_empty <= "XXXX";
end if;
end process;
grp_aesl_mux_load_7_3_x_s_fu_316_ap_start <= ap_reg_grp_aesl_mux_load_7_3_x_s_fu_316_ap_start;
grp_fu_361_p0_assign_proc : process(ap_enable_reg_pp0_iter0, grp_fu_361_p2, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage3, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage11, temp1_phi_fu_309_p4, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage19_flag00000000, ap_block_pp0_stage27_flag00000000, ap_block_pp0_stage35_flag00000000)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0)))) then
grp_fu_361_p0 <= grp_fu_361_p2;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_361_p0 <= temp1_phi_fu_309_p4;
else
grp_fu_361_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_361_p1_assign_proc : process(ap_enable_reg_pp0_iter0, reg_376, reg_381, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage3, ap_enable_reg_pp0_iter1, tmp_13_3_reg_1036, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage19_flag00000000, ap_block_pp0_stage27_flag00000000, ap_block_pp0_stage35_flag00000000)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0))) then
grp_fu_361_p1 <= tmp_13_3_reg_1036;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0)))) then
grp_fu_361_p1 <= reg_381;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0)))) then
grp_fu_361_p1 <= reg_376;
else
grp_fu_361_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_367_p1_assign_proc : process(ap_enable_reg_pp0_iter0, bufi_load_0_phi_reg_1011, bufi_load_1_phi_reg_1016, bufi_load_2_phi_reg_1021, bufi_load_3_phi_reg_1026, tmp_22_reg_1031, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00000000, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00000000, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage16_flag00000000, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage21_flag00000000, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage26_flag00000000)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0))) then
grp_fu_367_p1 <= tmp_22_reg_1031;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0))) then
grp_fu_367_p1 <= bufi_load_3_phi_reg_1026;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0))) then
grp_fu_367_p1 <= bufi_load_2_phi_reg_1021;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
grp_fu_367_p1 <= bufi_load_1_phi_reg_1016;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
grp_fu_367_p1 <= bufi_load_0_phi_reg_1011;
else
grp_fu_367_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_367_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
i_V_fu_638_p2 <= std_logic_vector(unsigned(p_4_phi_fu_298_p4) + unsigned(ap_const_lv3_1));
indvar_flatten15_op_fu_746_p2 <= std_logic_vector(unsigned(indvar_flatten2_reg_234) + unsigned(ap_const_lv6_1));
indvar_flatten_next1_fu_758_p3 <=
ap_const_lv6_1 when (exitcond_flatten_reg_772(0) = '1') else
indvar_flatten15_op_reg_1057;
indvar_flatten_next2_fu_397_p2 <= std_logic_vector(unsigned(indvar_flatten1_reg_211) + unsigned(ap_const_lv7_1));
indvar_flatten_next_fu_752_p3 <=
ap_const_lv4_1 when (tmp_2_reg_808(0) = '1') else
indvar_flatten_op_reg_1052;
indvar_flatten_op_fu_740_p2 <= std_logic_vector(unsigned(indvar_flatten_reg_258) + unsigned(ap_const_lv4_1));
not_exitcond_flatten_1_fu_442_p2 <= (exitcond_flatten_reg_772 or exitcond_flatten_not_fu_437_p2);
not_exitcond_flatten_fu_415_p2 <= (exitcond_flatten_reg_772 xor ap_const_lv1_1);
p_1_mid_fu_453_p3 <=
ap_const_lv2_0 when (exitcond_flatten_reg_772(0) = '1') else
p_1_reg_246;
p_2_mid_fu_464_p3 <=
ap_const_lv2_0 when (tmp_2_fu_460_p2(0) = '1') else
p_2_reg_270;
p_3_mid2_fu_497_p3 <=
ap_const_lv2_0 when (tmp_7_fu_492_p2(0) = '1') else
p_3_reg_282;
p_4_phi_fu_298_p4_assign_proc : process(p_4_reg_294, tmp_3_reg_912, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage0, i_V_reg_916, ap_block_pp0_stage0_flag00000000)
begin
if (((tmp_3_reg_912 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
p_4_phi_fu_298_p4 <= i_V_reg_916;
else
p_4_phi_fu_298_p4 <= p_4_reg_294;
end if;
end process;
p_shl8_fu_521_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_4_fu_514_p3),32));
p_shl9_cast_fu_597_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_fu_590_p3),6));
p_shl_cast_fu_548_p3 <= (tmp_12_reg_849 & ap_const_lv2_0);
row_b_V_fu_483_p2 <= std_logic_vector(unsigned(ap_const_lv2_1) + unsigned(p_2_mid_reg_813));
sel_tmp10_fu_723_p3 <=
bufi_4_load_reg_993 when (sel_tmp2_reg_896(0) = '1') else
sel_tmp8_fu_718_p3;
sel_tmp1_fu_667_p3 <=
bufi_0_load_reg_975 when (sel_tmp_reg_888(0) = '1') else
bufi_3_load_reg_967;
sel_tmp2_fu_622_p2 <= "1" when (p_3_mid2_reg_827 = ap_const_lv2_1) else "0";
sel_tmp3_fu_672_p3 <=
bufi_1_load_reg_980 when (sel_tmp2_reg_896(0) = '1') else
sel_tmp1_fu_667_p3;
sel_tmp4_fu_627_p2 <= "1" when (p_3_mid2_reg_827 = ap_const_lv2_2) else "0";
sel_tmp5_fu_701_p3 <=
bufi_2_load_reg_986 when (sel_tmp_reg_888(0) = '1') else
bufi_5_load_reg_1000;
sel_tmp6_fu_706_p3 <=
bufi_3_load_reg_967 when (sel_tmp2_reg_896(0) = '1') else
sel_tmp5_fu_701_p3;
sel_tmp7_fu_684_p3 <=
bufi_1_load_reg_980 when (sel_tmp_reg_888(0) = '1') else
bufi_4_load_reg_993;
sel_tmp8_fu_718_p3 <=
bufi_3_load_reg_967 when (sel_tmp_reg_888(0) = '1') else
bufi_6_load_reg_1006;
sel_tmp9_fu_689_p3 <=
bufi_2_load_reg_986 when (sel_tmp2_reg_896(0) = '1') else
sel_tmp7_fu_684_p3;
sel_tmp_fu_617_p2 <= "1" when (p_3_mid2_reg_827 = ap_const_lv2_0) else "0";
temp1_phi_fu_309_p4_assign_proc : process(temp1_reg_306, grp_fu_361_p2, ap_enable_reg_pp0_iter1, ap_reg_pp0_iter1_tmp_3_reg_912, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00000000)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_3_reg_912) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
temp1_phi_fu_309_p4 <= grp_fu_361_p2;
else
temp1_phi_fu_309_p4 <= temp1_reg_306;
end if;
end process;
ti_b_V_fu_574_p2 <= std_logic_vector(unsigned(ap_const_lv2_1) + unsigned(p_s_reg_222));
tmp_11_fu_540_p1 <= tmp_8_fu_534_p2(6 - 1 downto 0);
tmp_12_48_t_fu_610_p3 <= (ap_const_lv1_1 & p_3_mid2_reg_827);
tmp_12_fu_544_p1 <= tmp_8_fu_534_p2(4 - 1 downto 0);
tmp_14_fu_555_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_548_p3) - unsigned(tmp_11_reg_844));
tmp_15_fu_563_p2 <= std_logic_vector(unsigned(tmp_cast_fu_560_p1) + unsigned(tmp_14_fu_555_p2));
tmp_16_fu_652_p2 <= std_logic_vector(unsigned(tmp_1_reg_868) + unsigned(tmp_9_cast_cast_fu_649_p1));
tmp_18_cast_fu_569_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_15_fu_563_p2),32));
tmp_1_fu_601_p2 <= std_logic_vector(unsigned(p_shl9_cast_fu_597_p1) - unsigned(tmp_1_mid2_cast_fu_587_p1));
tmp_1_mid2_cast_fu_587_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_1_mid2_v_reg_859),6));
tmp_1_mid2_v_fu_580_p3 <=
ti_b_V_fu_574_p2 when (exitcond_flatten_reg_772(0) = '1') else
p_s_reg_222;
tmp_20_cast_fu_657_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_16_reg_927),32));
tmp_2_fu_460_p2 <= (exitcond_flatten_mid_reg_789 or exitcond_flatten_reg_772);
tmp_3_fu_632_p2 <= "1" when (p_4_phi_fu_298_p4 = ap_const_lv3_5) else "0";
tmp_4_fu_514_p3 <= (tmp_4_mid2_reg_819 & ap_const_lv2_0);
tmp_4_mid2_cast_fu_511_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_4_mid2_reg_819),32));
tmp_4_mid2_fu_477_p3 <=
to_b_V_fu_472_p2 when (exitcond_flatten_mid_reg_789(0) = '1') else
p_1_mid_reg_802;
tmp_5_fu_488_p2 <= (tmp_8_mid1_reg_796 or exitcond_flatten_mid_reg_789);
tmp_6_fu_525_p2 <= std_logic_vector(unsigned(p_shl8_fu_521_p1) - unsigned(tmp_4_mid2_cast_fu_511_p1));
tmp_7_cast_mid2_cast_fu_607_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_mid2_reg_837),3));
tmp_7_fu_492_p2 <= (tmp_5_fu_488_p2 or exitcond_flatten_reg_772);
tmp_7_mid2_cast_fu_531_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_mid2_reg_837),32));
tmp_7_mid2_fu_505_p3 <=
row_b_V_fu_483_p2 when (tmp_8_mid1_reg_796(0) = '1') else
p_2_mid_reg_813;
tmp_8_fu_534_p2 <= std_logic_vector(unsigned(tmp_7_mid2_cast_fu_531_p1) + unsigned(tmp_6_fu_525_p2));
tmp_8_mid1_fu_447_p2 <= (tmp_8_mid_fu_426_p2 and not_exitcond_flatten_1_fu_442_p2);
tmp_8_mid_fu_426_p2 <= (tmp_s_fu_420_p2 and not_exitcond_flatten_fu_415_p2);
tmp_9_cast_cast_fu_649_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_9_reg_921),6));
tmp_9_fu_644_p2 <= std_logic_vector(unsigned(tmp_7_cast_mid2_cast_reg_873) + unsigned(p_4_reg_294));
tmp_cast_fu_560_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_3_mid2_reg_827),6));
tmp_fu_590_p3 <= (tmp_1_mid2_v_reg_859 & ap_const_lv3_0);
tmp_s_fu_420_p2 <= "1" when (p_3_reg_282 = ap_const_lv2_3) else "0";
to_b_V_fu_472_p2 <= std_logic_vector(unsigned(ap_const_lv2_1) + unsigned(p_1_mid_reg_802));
end behav;
| mit | 0b96c8a405154e279bcd389a3fc26454 | 0.625949 | 2.726807 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.ip_user_files/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_0/zqynq_lab_1_design_axi_bram_ctrl_0_0_sim_netlist.vhdl | 1 | 322,300 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 17:40:41 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_0/zqynq_lab_1_design_axi_bram_ctrl_0_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_bram_ctrl_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
bid_gets_fifo_load : out STD_LOGIC;
bvalid_cnt_inc : out STD_LOGIC;
bid_gets_fifo_load_d1_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
axi_wdata_full_cmb114_out : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
\bvalid_cnt_reg[2]\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
\bvalid_cnt_reg[2]_0\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
bram_addr_ld_en : in STD_LOGIC;
bid_gets_fifo_load_d1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
axi_bvalid_int_reg : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
\bvalid_cnt_reg[1]\ : in STD_LOGIC;
aw_active : in STD_LOGIC;
s_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
axi_wr_burst : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO : entity is "SRL_FIFO";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO is
signal \Addr_Counters[0].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[1].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[2].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].XORCY_I_i_1_n_0\ : STD_LOGIC;
signal CI : STD_LOGIC;
signal D_0 : STD_LOGIC;
signal Data_Exists_DFF_i_2_n_0 : STD_LOGIC;
signal Data_Exists_DFF_i_3_n_0 : STD_LOGIC;
signal S : STD_LOGIC;
signal S0_out : STD_LOGIC;
signal S1_out : STD_LOGIC;
signal addr_cy_1 : STD_LOGIC;
signal addr_cy_2 : STD_LOGIC;
signal addr_cy_3 : STD_LOGIC;
signal \axi_bid_int[11]_i_3_n_0\ : STD_LOGIC;
signal axi_bvalid_int_i_4_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_5_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_6_n_0 : STD_LOGIC;
signal \^axi_wdata_full_cmb114_out\ : STD_LOGIC;
signal bid_fifo_ld : STD_LOGIC_VECTOR ( 11 downto 0 );
signal bid_fifo_not_empty : STD_LOGIC;
signal bid_fifo_rd : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^bid_gets_fifo_load\ : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_3_n_0 : STD_LOGIC;
signal \^bid_gets_fifo_load_d1_reg\ : STD_LOGIC;
signal \^bvalid_cnt_inc\ : STD_LOGIC;
signal sum_A_0 : STD_LOGIC;
signal sum_A_1 : STD_LOGIC;
signal sum_A_2 : STD_LOGIC;
signal sum_A_3 : STD_LOGIC;
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \Addr_Counters[0].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "LO:O";
attribute BOX_TYPE of \Addr_Counters[1].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[2].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[3].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of Data_Exists_DFF : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of Data_Exists_DFF : label is "FDR";
attribute BOX_TYPE of \FIFO_RAM[0].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name : string;
attribute srl_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I ";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FIFO_RAM[0].SRL16E_I_i_1\ : label is "soft_lutpair42";
attribute BOX_TYPE of \FIFO_RAM[10].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[10].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[10].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[10].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[10].SRL16E_I_i_1\ : label is "soft_lutpair52";
attribute BOX_TYPE of \FIFO_RAM[11].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[11].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[11].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[11].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[11].SRL16E_I_i_1\ : label is "soft_lutpair53";
attribute BOX_TYPE of \FIFO_RAM[1].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[1].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[1].SRL16E_I_i_1\ : label is "soft_lutpair43";
attribute BOX_TYPE of \FIFO_RAM[2].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[2].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[2].SRL16E_I_i_1\ : label is "soft_lutpair44";
attribute BOX_TYPE of \FIFO_RAM[3].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[3].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[3].SRL16E_I_i_1\ : label is "soft_lutpair45";
attribute BOX_TYPE of \FIFO_RAM[4].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[4].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[4].SRL16E_I_i_1\ : label is "soft_lutpair46";
attribute BOX_TYPE of \FIFO_RAM[5].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[5].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[5].SRL16E_I_i_1\ : label is "soft_lutpair47";
attribute BOX_TYPE of \FIFO_RAM[6].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[6].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[6].SRL16E_I_i_1\ : label is "soft_lutpair48";
attribute BOX_TYPE of \FIFO_RAM[7].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[7].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[7].SRL16E_I_i_1\ : label is "soft_lutpair49";
attribute BOX_TYPE of \FIFO_RAM[8].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[8].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[8].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[8].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[8].SRL16E_I_i_1\ : label is "soft_lutpair50";
attribute BOX_TYPE of \FIFO_RAM[9].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[9].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[9].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[9].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[9].SRL16E_I_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \axi_bid_int[0]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \axi_bid_int[10]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \axi_bid_int[11]_i_2\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \axi_bid_int[1]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \axi_bid_int[2]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \axi_bid_int[3]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \axi_bid_int[4]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \axi_bid_int[5]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axi_bid_int[6]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \axi_bid_int[7]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \axi_bid_int[8]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \axi_bid_int[9]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of axi_bvalid_int_i_3 : label is "soft_lutpair54";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_3 : label is "soft_lutpair54";
begin
axi_wdata_full_cmb114_out <= \^axi_wdata_full_cmb114_out\;
bid_gets_fifo_load <= \^bid_gets_fifo_load\;
bid_gets_fifo_load_d1_reg <= \^bid_gets_fifo_load_d1_reg\;
bvalid_cnt_inc <= \^bvalid_cnt_inc\;
\Addr_Counters[0].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_3,
Q => \Addr_Counters[0].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[0].MUXCY_L_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\(3),
CO(2) => addr_cy_1,
CO(1) => addr_cy_2,
CO(0) => addr_cy_3,
CYINIT => CI,
DI(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\(3),
DI(2) => \Addr_Counters[2].FDRE_I_n_0\,
DI(1) => \Addr_Counters[1].FDRE_I_n_0\,
DI(0) => \Addr_Counters[0].FDRE_I_n_0\,
O(3) => sum_A_0,
O(2) => sum_A_1,
O(1) => sum_A_2,
O(0) => sum_A_3,
S(3) => \Addr_Counters[3].XORCY_I_i_1_n_0\,
S(2) => S0_out,
S(1) => S1_out,
S(0) => S
);
\Addr_Counters[0].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[1].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[0].FDRE_I_n_0\,
O => S
);
\Addr_Counters[0].MUXCY_L_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAAAAAAAAAAAAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => \axi_bid_int[11]_i_3_n_0\,
I2 => \Addr_Counters[0].FDRE_I_n_0\,
I3 => \Addr_Counters[1].FDRE_I_n_0\,
I4 => \Addr_Counters[3].FDRE_I_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => CI
);
\Addr_Counters[1].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_2,
Q => \Addr_Counters[1].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[1].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[1].FDRE_I_n_0\,
O => S1_out
);
\Addr_Counters[2].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_1,
Q => \Addr_Counters[2].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[2].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => S0_out
);
\Addr_Counters[3].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_0,
Q => \Addr_Counters[3].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[3].XORCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[3].FDRE_I_n_0\,
O => \Addr_Counters[3].XORCY_I_i_1_n_0\
);
Data_Exists_DFF: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D_0,
Q => bid_fifo_not_empty,
R => SR(0)
);
Data_Exists_DFF_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE0A"
)
port map (
I0 => bram_addr_ld_en,
I1 => Data_Exists_DFF_i_2_n_0,
I2 => Data_Exists_DFF_i_3_n_0,
I3 => bid_fifo_not_empty,
O => D_0
);
Data_Exists_DFF_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFFD"
)
port map (
I0 => \^bvalid_cnt_inc\,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
I3 => bvalid_cnt(1),
I4 => \^bid_gets_fifo_load_d1_reg\,
I5 => bid_gets_fifo_load_d1,
O => Data_Exists_DFF_i_2_n_0
);
Data_Exists_DFF_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => \Addr_Counters[2].FDRE_I_n_0\,
O => Data_Exists_DFF_i_3_n_0
);
\FIFO_RAM[0].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(11),
Q => bid_fifo_rd(11)
);
\FIFO_RAM[0].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(11),
I1 => axi_awaddr_full,
I2 => s_axi_awid(11),
O => bid_fifo_ld(11)
);
\FIFO_RAM[10].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(1),
Q => bid_fifo_rd(1)
);
\FIFO_RAM[10].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awid(1),
O => bid_fifo_ld(1)
);
\FIFO_RAM[11].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(0),
Q => bid_fifo_rd(0)
);
\FIFO_RAM[11].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awid(0),
O => bid_fifo_ld(0)
);
\FIFO_RAM[1].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(10),
Q => bid_fifo_rd(10)
);
\FIFO_RAM[1].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(10),
I1 => axi_awaddr_full,
I2 => s_axi_awid(10),
O => bid_fifo_ld(10)
);
\FIFO_RAM[2].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(9),
Q => bid_fifo_rd(9)
);
\FIFO_RAM[2].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(9),
I1 => axi_awaddr_full,
I2 => s_axi_awid(9),
O => bid_fifo_ld(9)
);
\FIFO_RAM[3].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(8),
Q => bid_fifo_rd(8)
);
\FIFO_RAM[3].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(8),
I1 => axi_awaddr_full,
I2 => s_axi_awid(8),
O => bid_fifo_ld(8)
);
\FIFO_RAM[4].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(7),
Q => bid_fifo_rd(7)
);
\FIFO_RAM[4].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(7),
I1 => axi_awaddr_full,
I2 => s_axi_awid(7),
O => bid_fifo_ld(7)
);
\FIFO_RAM[5].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(6),
Q => bid_fifo_rd(6)
);
\FIFO_RAM[5].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(6),
I1 => axi_awaddr_full,
I2 => s_axi_awid(6),
O => bid_fifo_ld(6)
);
\FIFO_RAM[6].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(5),
Q => bid_fifo_rd(5)
);
\FIFO_RAM[6].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(5),
I1 => axi_awaddr_full,
I2 => s_axi_awid(5),
O => bid_fifo_ld(5)
);
\FIFO_RAM[7].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(4),
Q => bid_fifo_rd(4)
);
\FIFO_RAM[7].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(4),
I1 => axi_awaddr_full,
I2 => s_axi_awid(4),
O => bid_fifo_ld(4)
);
\FIFO_RAM[8].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(3),
Q => bid_fifo_rd(3)
);
\FIFO_RAM[8].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awid(3),
O => bid_fifo_ld(3)
);
\FIFO_RAM[9].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(2),
Q => bid_fifo_rd(2)
);
\FIFO_RAM[9].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => s_axi_awid(2),
O => bid_fifo_ld(2)
);
\axi_bid_int[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awid(0),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(0),
O => D(0)
);
\axi_bid_int[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(10),
I1 => axi_awaddr_full,
I2 => s_axi_awid(10),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(10),
O => D(10)
);
\axi_bid_int[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^bid_gets_fifo_load\,
I1 => \axi_bid_int[11]_i_3_n_0\,
O => E(0)
);
\axi_bid_int[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(11),
I1 => axi_awaddr_full,
I2 => s_axi_awid(11),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(11),
O => D(11)
);
\axi_bid_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A888AAAAA8888888"
)
port map (
I0 => bid_fifo_not_empty,
I1 => bid_gets_fifo_load_d1,
I2 => s_axi_bready,
I3 => axi_bvalid_int_reg,
I4 => bid_gets_fifo_load_d1_i_3_n_0,
I5 => \^bvalid_cnt_inc\,
O => \axi_bid_int[11]_i_3_n_0\
);
\axi_bid_int[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awid(1),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(1),
O => D(1)
);
\axi_bid_int[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => s_axi_awid(2),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(2),
O => D(2)
);
\axi_bid_int[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awid(3),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(3),
O => D(3)
);
\axi_bid_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(4),
I1 => axi_awaddr_full,
I2 => s_axi_awid(4),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(4),
O => D(4)
);
\axi_bid_int[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(5),
I1 => axi_awaddr_full,
I2 => s_axi_awid(5),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(5),
O => D(5)
);
\axi_bid_int[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(6),
I1 => axi_awaddr_full,
I2 => s_axi_awid(6),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(6),
O => D(6)
);
\axi_bid_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(7),
I1 => axi_awaddr_full,
I2 => s_axi_awid(7),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(7),
O => D(7)
);
\axi_bid_int[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(8),
I1 => axi_awaddr_full,
I2 => s_axi_awid(8),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(8),
O => D(8)
);
\axi_bid_int[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(9),
I1 => axi_awaddr_full,
I2 => s_axi_awid(9),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(9),
O => D(9)
);
axi_bvalid_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000055FD00000000"
)
port map (
I0 => \out\(2),
I1 => \^axi_wdata_full_cmb114_out\,
I2 => axi_bvalid_int_i_4_n_0,
I3 => axi_wr_burst,
I4 => \out\(1),
I5 => axi_bvalid_int_i_5_n_0,
O => \^bvalid_cnt_inc\
);
axi_bvalid_int_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FE000000"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => axi_bvalid_int_reg,
I4 => s_axi_bready,
O => \^bid_gets_fifo_load_d1_reg\
);
axi_bvalid_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"1F11000000000000"
)
port map (
I0 => axi_bvalid_int_i_6_n_0,
I1 => \bvalid_cnt_reg[2]\,
I2 => wr_addr_sm_cs,
I3 => \bvalid_cnt_reg[2]_0\,
I4 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I5 => axi_awaddr_full,
O => axi_bvalid_int_i_4_n_0
);
axi_bvalid_int_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"74446444"
)
port map (
I0 => \out\(0),
I1 => \out\(2),
I2 => s_axi_wvalid,
I3 => s_axi_wlast,
I4 => \^axi_wdata_full_cmb114_out\,
O => axi_bvalid_int_i_5_n_0
);
axi_bvalid_int_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFFFFFF"
)
port map (
I0 => curr_awlen_reg_1_or_2,
I1 => axi_awlen_pipe_1_or_2,
I2 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I3 => axi_awaddr_full,
I4 => last_data_ack_mod,
O => axi_bvalid_int_i_6_n_0
);
axi_wready_int_mod_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"7F7F7F007F007F00"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => aw_active,
I4 => s_axi_awready,
I5 => s_axi_awvalid,
O => \^axi_wdata_full_cmb114_out\
);
bid_gets_fifo_load_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000800AA00AA00"
)
port map (
I0 => bram_addr_ld_en,
I1 => \^bid_gets_fifo_load_d1_reg\,
I2 => bid_fifo_not_empty,
I3 => \^bvalid_cnt_inc\,
I4 => \bvalid_cnt_reg[1]\,
I5 => bid_gets_fifo_load_d1_i_3_n_0,
O => \^bid_gets_fifo_load\
);
bid_gets_fifo_load_d1_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => bid_gets_fifo_load_d1_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst is
port (
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ : out STD_LOGIC;
bram_addr_ld_en_mod : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
\save_init_bram_addr_ld_reg[12]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : out STD_LOGIC;
bram_addr_ld_en : out STD_LOGIC;
\save_init_bram_addr_ld_reg[12]_1\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[12]_2\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[12]_3\ : out STD_LOGIC;
curr_fixed_burst_reg_reg : out STD_LOGIC;
curr_wrap_burst_reg_reg : out STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
bram_addr_inc : in STD_LOGIC;
bram_addr_rst_cmb : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC;
bram_addr_a : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
aw_active : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_awsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
curr_fixed_burst : in STD_LOGIC;
curr_wrap_burst : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst : entity is "wrap_brst";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst is
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[8]\ : STD_LOGIC;
signal bram_addr_ld : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^bram_addr_ld_en_mod\ : STD_LOGIC;
signal save_init_bram_addr_ld : STD_LOGIC_VECTOR ( 12 downto 3 );
signal \save_init_bram_addr_ld[12]_i_6_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[12]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^save_init_bram_addr_ld_reg[12]_1\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[12]_2\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[12]_3\ : STD_LOGIC;
signal wrap_burst_total : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \wrap_burst_total[0]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \curr_fixed_burst_reg_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[12]_i_5\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[12]_i_6\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[3]_i_2__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_2__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_3__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3\ : label is "soft_lutpair55";
begin
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[8]\;
bram_addr_ld_en <= \^bram_addr_ld_en\;
bram_addr_ld_en_mod <= \^bram_addr_ld_en_mod\;
\save_init_bram_addr_ld_reg[12]_0\(0) <= \^save_init_bram_addr_ld_reg[12]_0\(0);
\save_init_bram_addr_ld_reg[12]_1\ <= \^save_init_bram_addr_ld_reg[12]_1\;
\save_init_bram_addr_ld_reg[12]_2\ <= \^save_init_bram_addr_ld_reg[12]_2\;
\save_init_bram_addr_ld_reg[12]_3\ <= \^save_init_bram_addr_ld_reg[12]_3\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB8BBBBB88B88888"
)
port map (
I0 => bram_addr_ld(8),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(7),
I5 => bram_addr_a(8),
O => D(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"4500FFFF"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => bram_addr_inc,
I3 => bram_addr_rst_cmb,
I4 => s_axi_aresetn,
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(9),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(9),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\,
I4 => bram_addr_a(8),
O => D(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0\,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => \^bram_addr_ld_en_mod\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555555FFFFFFDF"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => wrap_burst_total(1),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(0),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00C000"
)
port map (
I0 => bram_addr_a(2),
I1 => bram_addr_a(1),
I2 => wrap_burst_total(1),
I3 => bram_addr_a(0),
I4 => wrap_burst_total(0),
I5 => wrap_burst_total(2),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B800B800FFFF"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
I1 => axi_awaddr_full,
I2 => s_axi_awaddr(0),
I3 => \^bram_addr_ld_en\,
I4 => \^bram_addr_ld_en_mod\,
I5 => bram_addr_a(0),
O => D(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BB8"
)
port map (
I0 => bram_addr_ld(1),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(1),
I3 => bram_addr_a(0),
O => D(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BB8B8B8"
)
port map (
I0 => bram_addr_ld(2),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(2),
I3 => bram_addr_a(0),
I4 => bram_addr_a(1),
O => D(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8BB8B8B8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(3),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(3),
I3 => bram_addr_a(2),
I4 => bram_addr_a(0),
I5 => bram_addr_a(1),
O => D(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B88B"
)
port map (
I0 => bram_addr_ld(4),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(4),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
O => D(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(5),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(5),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I4 => bram_addr_a(4),
O => D(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B88BB8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(6),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => bram_addr_a(4),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => bram_addr_a(5),
O => D(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => bram_addr_a(1),
I1 => bram_addr_a(0),
I2 => bram_addr_a(2),
I3 => bram_addr_a(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(7),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(6),
O => D(7)
);
\curr_fixed_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_fixed_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_fixed_burst,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
O => curr_fixed_burst_reg_reg
);
\curr_wrap_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_wrap_burst,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
O => curr_wrap_burst_reg_reg
);
\save_init_bram_addr_ld[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(10),
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(8),
O => bram_addr_ld(8)
);
\save_init_bram_addr_ld[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(11),
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(9),
O => bram_addr_ld(9)
);
\save_init_bram_addr_ld[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808080808AA0808"
)
port map (
I0 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I1 => \^save_init_bram_addr_ld_reg[12]_1\,
I2 => wr_addr_sm_cs,
I3 => \^save_init_bram_addr_ld_reg[12]_2\,
I4 => last_data_ack_mod,
I5 => \^save_init_bram_addr_ld_reg[12]_3\,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[12]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(12),
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(10),
O => \^save_init_bram_addr_ld_reg[12]_0\(0)
);
\save_init_bram_addr_ld[12]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"007F007F007F0000"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
I3 => aw_active,
I4 => axi_awaddr_full,
I5 => s_axi_awvalid,
O => \^save_init_bram_addr_ld_reg[12]_1\
);
\save_init_bram_addr_ld[12]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => \^save_init_bram_addr_ld_reg[12]_2\
);
\save_init_bram_addr_ld[12]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I2 => axi_awlen_pipe_1_or_2,
I3 => curr_awlen_reg_1_or_2,
O => \^save_init_bram_addr_ld_reg[12]_3\
);
\save_init_bram_addr_ld[12]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0\,
O => \save_init_bram_addr_ld[12]_i_6_n_0\
);
\save_init_bram_addr_ld[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2__0_n_0\,
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(1),
O => bram_addr_ld(1)
);
\save_init_bram_addr_ld[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"C80C"
)
port map (
I0 => wrap_burst_total(0),
I1 => save_init_bram_addr_ld(3),
I2 => wrap_burst_total(1),
I3 => wrap_burst_total(2),
O => \save_init_bram_addr_ld[3]_i_2__0_n_0\
);
\save_init_bram_addr_ld[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2__0_n_0\,
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(2),
O => bram_addr_ld(2)
);
\save_init_bram_addr_ld[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => save_init_bram_addr_ld(4),
I1 => wrap_burst_total(0),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[4]_i_2__0_n_0\
);
\save_init_bram_addr_ld[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F808F8F8F808080"
)
port map (
I0 => save_init_bram_addr_ld(5),
I1 => \save_init_bram_addr_ld[5]_i_2__0_n_0\,
I2 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I3 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
I4 => axi_awaddr_full,
I5 => s_axi_awaddr(3),
O => bram_addr_ld(3)
);
\save_init_bram_addr_ld[5]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => wrap_burst_total(0),
I1 => wrap_burst_total(2),
I2 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[5]_i_2__0_n_0\
);
\save_init_bram_addr_ld[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(6),
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(4),
O => bram_addr_ld(4)
);
\save_init_bram_addr_ld[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(7),
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(5),
O => bram_addr_ld(5)
);
\save_init_bram_addr_ld[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(8),
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(6),
O => bram_addr_ld(6)
);
\save_init_bram_addr_ld[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(9),
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(7),
O => bram_addr_ld(7)
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(8),
Q => save_init_bram_addr_ld(10),
R => SR(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(9),
Q => save_init_bram_addr_ld(11),
R => SR(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^save_init_bram_addr_ld_reg[12]_0\(0),
Q => save_init_bram_addr_ld(12),
R => SR(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(1),
Q => save_init_bram_addr_ld(3),
R => SR(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(2),
Q => save_init_bram_addr_ld(4),
R => SR(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(3),
Q => save_init_bram_addr_ld(5),
R => SR(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(4),
Q => save_init_bram_addr_ld(6),
R => SR(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(5),
Q => save_init_bram_addr_ld(7),
R => SR(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(6),
Q => save_init_bram_addr_ld(8),
R => SR(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(7),
Q => save_init_bram_addr_ld(9),
R => SR(0)
);
\wrap_burst_total[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000A22200000000"
)
port map (
I0 => \wrap_burst_total[0]_i_2__0_n_0\,
I1 => \wrap_burst_total[0]_i_3_n_0\,
I2 => Q(1),
I3 => Q(2),
I4 => \wrap_burst_total[2]_i_2__0_n_0\,
I5 => \wrap_burst_total[1]_i_2__0_n_0\,
O => \wrap_burst_total[0]_i_1__0_n_0\
);
\wrap_burst_total[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCA533A5FFA5FFA5"
)
port map (
I0 => s_axi_awlen(2),
I1 => Q(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => Q(1),
I5 => axi_awsize_pipe(0),
O => \wrap_burst_total[0]_i_2__0_n_0\
);
\wrap_burst_total[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_awaddr_full,
I1 => axi_awsize_pipe(0),
O => \wrap_burst_total[0]_i_3_n_0\
);
\wrap_burst_total[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"08000800F3000000"
)
port map (
I0 => \wrap_burst_total[2]_i_3_n_0\,
I1 => axi_awaddr_full,
I2 => axi_awsize_pipe(0),
I3 => \wrap_burst_total[1]_i_2__0_n_0\,
I4 => \wrap_burst_total[1]_i_3__0_n_0\,
I5 => \wrap_burst_total[2]_i_2__0_n_0\,
O => \wrap_burst_total[1]_i_1__0_n_0\
);
\wrap_burst_total[1]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(0),
O => \wrap_burst_total[1]_i_2__0_n_0\
);
\wrap_burst_total[1]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(1),
O => \wrap_burst_total[1]_i_3__0_n_0\
);
\wrap_burst_total[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A000000088008800"
)
port map (
I0 => \wrap_burst_total[2]_i_2__0_n_0\,
I1 => s_axi_awlen(0),
I2 => Q(0),
I3 => \wrap_burst_total[2]_i_3_n_0\,
I4 => axi_awsize_pipe(0),
I5 => axi_awaddr_full,
O => \wrap_burst_total[2]_i_1__0_n_0\
);
\wrap_burst_total[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(3),
O => \wrap_burst_total[2]_i_2__0_n_0\
);
\wrap_burst_total[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA000A0"
)
port map (
I0 => s_axi_awlen(2),
I1 => Q(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => Q(1),
O => \wrap_burst_total[2]_i_3_n_0\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1__0_n_0\,
Q => wrap_burst_total(0),
R => SR(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1__0_n_0\,
Q => wrap_burst_total(1),
R => SR(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1__0_n_0\,
Q => wrap_burst_total(2),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0 is
port (
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_burst_total_reg[0]_0\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_1\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_2\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_3\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ : out STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
bram_addr_ld_en : out STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[12]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\rd_data_sm_cs_reg[1]\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[12]_1\ : out STD_LOGIC;
axi_b2b_brst_reg : out STD_LOGIC;
\rd_data_sm_cs_reg[3]\ : out STD_LOGIC;
rd_adv_buf67_out : out STD_LOGIC;
end_brst_rd : in STD_LOGIC;
brst_zero : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_rvalid_int_reg : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_arsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
axi_araddr_full : in STD_LOGIC;
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
curr_fixed_burst_reg : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
axi_rd_burst_two_reg : in STD_LOGIC;
axi_rd_burst : in STD_LOGIC;
axi_aresetn_d2 : in STD_LOGIC;
rd_addr_sm_cs : in STD_LOGIC;
last_bram_addr : in STD_LOGIC;
ar_active : in STD_LOGIC;
pend_rd_op : in STD_LOGIC;
no_ar_ack : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
axi_b2b_brst : in STD_LOGIC;
axi_arsize_pipe_max : in STD_LOGIC;
disable_b2b_brst : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_arlen_pipe_1_or_2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0 : entity is "wrap_brst";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0 is
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]_1\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[6]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axi_b2b_brst_reg\ : STD_LOGIC;
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^rd_adv_buf67_out\ : STD_LOGIC;
signal \^rd_data_sm_cs_reg[1]\ : STD_LOGIC;
signal \^rd_data_sm_cs_reg[3]\ : STD_LOGIC;
signal \save_init_bram_addr_ld[10]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[12]_i_3__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[6]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[7]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[8]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[12]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^save_init_bram_addr_ld_reg[12]_1\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[10]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[11]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[12]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[3]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[4]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[5]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[6]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[7]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[8]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_1\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_2\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_3\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[2]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[5]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_3\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_4\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_1\ : label is "soft_lutpair0";
begin
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]_1\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[6]\;
SR(0) <= \^sr\(0);
axi_b2b_brst_reg <= \^axi_b2b_brst_reg\;
bram_addr_ld_en <= \^bram_addr_ld_en\;
rd_adv_buf67_out <= \^rd_adv_buf67_out\;
\rd_data_sm_cs_reg[1]\ <= \^rd_data_sm_cs_reg[1]\;
\rd_data_sm_cs_reg[3]\ <= \^rd_data_sm_cs_reg[3]\;
\save_init_bram_addr_ld_reg[12]_0\(0) <= \^save_init_bram_addr_ld_reg[12]_0\(0);
\save_init_bram_addr_ld_reg[12]_1\ <= \^save_init_bram_addr_ld_reg[12]_1\;
\wrap_burst_total_reg[0]_0\ <= \^wrap_burst_total_reg[0]_0\;
\wrap_burst_total_reg[0]_1\ <= \^wrap_burst_total_reg[0]_1\;
\wrap_burst_total_reg[0]_2\ <= \^wrap_burst_total_reg[0]_2\;
\wrap_burst_total_reg[0]_3\ <= \^wrap_burst_total_reg[0]_3\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"DF20FFFFDF200000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(8),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I5 => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
O => D(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"5D"
)
port map (
I0 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_1\,
I2 => curr_fixed_burst_reg,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(9),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(8),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I4 => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
O => D(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0E0F0F0E0E0FFF0"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\,
I2 => \^rd_data_sm_cs_reg[1]\,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
I4 => Q(1),
I5 => Q(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_1\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg,
I1 => Q(0),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080800080"
)
port map (
I0 => Q(0),
I1 => axi_rvalid_int_reg,
I2 => s_axi_rready,
I3 => end_brst_rd,
I4 => axi_b2b_brst,
I5 => brst_zero,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000A808FD5D"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => s_axi_araddr(0),
I2 => axi_araddr_full,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(0),
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
O => D(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A80000"
)
port map (
I0 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_1\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3_n_0\,
I2 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I4 => curr_wrap_burst_reg,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00A000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(2),
I2 => \wrap_burst_total_reg_n_0_[1]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(0),
I4 => \wrap_burst_total_reg_n_0_[0]\,
I5 => \wrap_burst_total_reg_n_0_[2]\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6F60"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(0),
I2 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I3 => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
O => D(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AFF6A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(2),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(1),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I4 => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
O => D(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAFFFF6AAA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(3),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(2),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(0),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(1),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I5 => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
O => D(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(4),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I3 => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
O => D(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(5),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(4),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I4 => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
O => D(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A6AAFFFFA6AA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(4),
I2 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(5),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I5 => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
O => D(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(2),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(7),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(6),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I4 => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
O => D(7)
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_rvalid_int_reg,
I1 => s_axi_rready,
O => \^rd_adv_buf67_out\
);
axi_b2b_brst_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFDFFFF"
)
port map (
I0 => axi_arsize_pipe_max,
I1 => disable_b2b_brst,
I2 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\,
I3 => axi_arlen_pipe_1_or_2,
I4 => axi_araddr_full,
O => \^axi_b2b_brst_reg\
);
bram_en_int_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => Q(3),
I1 => Q(2),
O => \^rd_data_sm_cs_reg[3]\
);
bram_en_int_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => end_brst_rd,
I1 => brst_zero,
I2 => Q(2),
I3 => Q(0),
I4 => axi_rvalid_int_reg,
I5 => s_axi_rready,
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\
);
bram_rst_b_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\rd_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F000E000F0000"
)
port map (
I0 => axi_rd_burst_two_reg,
I1 => axi_rd_burst,
I2 => Q(3),
I3 => Q(2),
I4 => Q(1),
I5 => Q(0),
O => \^rd_data_sm_cs_reg[1]\
);
\save_init_bram_addr_ld[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[10]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(8),
O => \save_init_bram_addr_ld[10]_i_1__0_n_0\
);
\save_init_bram_addr_ld[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[11]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(9),
O => \save_init_bram_addr_ld[11]_i_1__0_n_0\
);
\save_init_bram_addr_ld[12]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"02AA0202"
)
port map (
I0 => axi_aresetn_d2,
I1 => rd_addr_sm_cs,
I2 => \save_init_bram_addr_ld[12]_i_3__0_n_0\,
I3 => \^save_init_bram_addr_ld_reg[12]_1\,
I4 => last_bram_addr,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[12]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[12]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(10),
O => \^save_init_bram_addr_ld_reg[12]_0\(0)
);
\save_init_bram_addr_ld[12]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFEFEFF"
)
port map (
I0 => ar_active,
I1 => pend_rd_op,
I2 => no_ar_ack,
I3 => s_axi_arvalid,
I4 => axi_araddr_full,
O => \save_init_bram_addr_ld[12]_i_3__0_n_0\
);
\save_init_bram_addr_ld[12]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABAAABAFFFFAABA"
)
port map (
I0 => \^axi_b2b_brst_reg\,
I1 => Q(0),
I2 => Q(1),
I3 => \^rd_data_sm_cs_reg[3]\,
I4 => brst_zero,
I5 => \^rd_adv_buf67_out\,
O => \^save_init_bram_addr_ld_reg[12]_1\
);
\save_init_bram_addr_ld[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(1),
O => \save_init_bram_addr_ld[3]_i_1__0_n_0\
);
\save_init_bram_addr_ld[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A282"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[3]\,
I1 => \wrap_burst_total_reg_n_0_[1]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[0]\,
O => \save_init_bram_addr_ld[3]_i_2_n_0\
);
\save_init_bram_addr_ld[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(2),
O => \save_init_bram_addr_ld[4]_i_1__0_n_0\
);
\save_init_bram_addr_ld[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[4]\,
I1 => \wrap_burst_total_reg_n_0_[0]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[4]_i_2_n_0\
);
\save_init_bram_addr_ld[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F202F2F2F202020"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[5]\,
I1 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
I4 => axi_araddr_full,
I5 => s_axi_araddr(3),
O => \save_init_bram_addr_ld[5]_i_1__0_n_0\
);
\save_init_bram_addr_ld[5]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \wrap_burst_total_reg_n_0_[0]\,
I1 => \wrap_burst_total_reg_n_0_[2]\,
I2 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[5]_i_2_n_0\
);
\save_init_bram_addr_ld[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[6]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(4),
O => \save_init_bram_addr_ld[6]_i_1__0_n_0\
);
\save_init_bram_addr_ld[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[7]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(5),
O => \save_init_bram_addr_ld[7]_i_1__0_n_0\
);
\save_init_bram_addr_ld[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[8]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(6),
O => \save_init_bram_addr_ld[8]_i_1__0_n_0\
);
\save_init_bram_addr_ld[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[9]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(7),
O => \save_init_bram_addr_ld[9]_i_1__0_n_0\
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[10]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[11]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^save_init_bram_addr_ld_reg[12]_0\(0),
Q => \save_init_bram_addr_ld_reg_n_0_[12]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[3]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[4]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[5]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[6]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[7]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[8]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[9]\,
R => \^sr\(0)
);
\wrap_burst_total[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3202010100000000"
)
port map (
I0 => \^wrap_burst_total_reg[0]_0\,
I1 => \^wrap_burst_total_reg[0]_1\,
I2 => \wrap_burst_total[0]_i_3__0_n_0\,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
I4 => \^wrap_burst_total_reg[0]_2\,
I5 => \^wrap_burst_total_reg[0]_3\,
O => \wrap_burst_total[0]_i_1_n_0\
);
\wrap_burst_total[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
I1 => axi_araddr_full,
I2 => s_axi_arlen(2),
O => \^wrap_burst_total_reg[0]_0\
);
\wrap_burst_total[0]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_araddr_full,
I1 => axi_arsize_pipe(0),
O => \wrap_burst_total[0]_i_3__0_n_0\
);
\wrap_burst_total[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"20CF000000000000"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
I1 => axi_arsize_pipe(0),
I2 => axi_araddr_full,
I3 => \^wrap_burst_total_reg[0]_1\,
I4 => \^wrap_burst_total_reg[0]_3\,
I5 => \^wrap_burst_total_reg[0]_2\,
O => \wrap_burst_total[1]_i_1_n_0\
);
\wrap_burst_total[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3),
I1 => axi_araddr_full,
I2 => s_axi_arlen(3),
O => \^wrap_burst_total_reg[0]_1\
);
\wrap_burst_total[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(0),
I1 => axi_araddr_full,
I2 => s_axi_arlen(0),
O => \^wrap_burst_total_reg[0]_3\
);
\wrap_burst_total[1]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
O => \^wrap_burst_total_reg[0]_2\
);
\wrap_burst_total[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000D580"
)
port map (
I0 => axi_araddr_full,
I1 => axi_arsize_pipe(0),
I2 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
I3 => s_axi_arlen(2),
I4 => \wrap_burst_total[2]_i_2_n_0\,
O => \wrap_burst_total[2]_i_1_n_0\
);
\wrap_burst_total[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FFF5F5F3FFFFFFF"
)
port map (
I0 => s_axi_arlen(3),
I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3),
I2 => \^wrap_burst_total_reg[0]_3\,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(1),
I4 => axi_araddr_full,
I5 => s_axi_arlen(1),
O => \wrap_burst_total[2]_i_2_n_0\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[0]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[1]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[2]\,
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl is
port (
bram_rst_a : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_arready : out STD_LOGIC;
bram_addr_b : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_aclk : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
axi_aresetn_d2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
axi_aresetn_re_reg : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl : entity is "rd_chnl";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl is
signal \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \/i__n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_arready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_4_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_5_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp2_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[11]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp_full_i_1_n_0\ : STD_LOGIC;
signal I_WRAP_BRST_n_0 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_13 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_15 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_18 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_21 : STD_LOGIC;
signal I_WRAP_BRST_n_22 : STD_LOGIC;
signal I_WRAP_BRST_n_23 : STD_LOGIC;
signal I_WRAP_BRST_n_24 : STD_LOGIC;
signal I_WRAP_BRST_n_25 : STD_LOGIC;
signal I_WRAP_BRST_n_3 : STD_LOGIC;
signal I_WRAP_BRST_n_4 : STD_LOGIC;
signal I_WRAP_BRST_n_5 : STD_LOGIC;
signal I_WRAP_BRST_n_6 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal act_rd_burst : STD_LOGIC;
signal act_rd_burst_i_1_n_0 : STD_LOGIC;
signal act_rd_burst_i_3_n_0 : STD_LOGIC;
signal act_rd_burst_i_4_n_0 : STD_LOGIC;
signal act_rd_burst_set : STD_LOGIC;
signal act_rd_burst_two : STD_LOGIC;
signal act_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal ar_active : STD_LOGIC;
signal araddr_pipe_ld43_out : STD_LOGIC;
signal axi_araddr_full : STD_LOGIC;
signal axi_arburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_arid_pipe : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_arlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_arlen_pipe_1_or_2 : STD_LOGIC;
signal axi_arready_int : STD_LOGIC;
signal axi_arsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_arsize_pipe_max : STD_LOGIC;
signal axi_arsize_pipe_max_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst : STD_LOGIC;
signal axi_b2b_brst_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst_i_3_n_0 : STD_LOGIC;
signal axi_early_arready_int : STD_LOGIC;
signal axi_rd_burst : STD_LOGIC;
signal axi_rd_burst_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_i_2_n_0 : STD_LOGIC;
signal axi_rd_burst_i_3_n_0 : STD_LOGIC;
signal axi_rd_burst_two : STD_LOGIC;
signal axi_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_two_reg_n_0 : STD_LOGIC;
signal axi_rid_temp : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp2 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp20_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp2_full : STD_LOGIC;
signal axi_rid_temp_full : STD_LOGIC;
signal axi_rid_temp_full_d1 : STD_LOGIC;
signal axi_rlast_int_i_1_n_0 : STD_LOGIC;
signal axi_rlast_set : STD_LOGIC;
signal axi_rvalid_clr_ok : STD_LOGIC;
signal axi_rvalid_clr_ok_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_2_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_3_n_0 : STD_LOGIC;
signal axi_rvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_set : STD_LOGIC;
signal axi_rvalid_set_cmb : STD_LOGIC;
signal \^bram_addr_b\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal bram_addr_ld_en : STD_LOGIC;
signal \^bram_en_b\ : STD_LOGIC;
signal bram_en_int_i_10_n_0 : STD_LOGIC;
signal bram_en_int_i_11_n_0 : STD_LOGIC;
signal bram_en_int_i_1_n_0 : STD_LOGIC;
signal bram_en_int_i_2_n_0 : STD_LOGIC;
signal bram_en_int_i_3_n_0 : STD_LOGIC;
signal bram_en_int_i_4_n_0 : STD_LOGIC;
signal bram_en_int_i_6_n_0 : STD_LOGIC;
signal bram_en_int_i_7_n_0 : STD_LOGIC;
signal bram_en_int_i_9_n_0 : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
signal brst_cnt : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \brst_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal brst_cnt_max : STD_LOGIC;
signal brst_cnt_max_d1 : STD_LOGIC;
signal brst_one : STD_LOGIC;
signal brst_one0 : STD_LOGIC;
signal brst_one_i_1_n_0 : STD_LOGIC;
signal brst_zero : STD_LOGIC;
signal brst_zero_i_1_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal disable_b2b_brst : STD_LOGIC;
signal disable_b2b_brst_cmb : STD_LOGIC;
signal disable_b2b_brst_i_2_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_3_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_4_n_0 : STD_LOGIC;
signal end_brst_rd : STD_LOGIC;
signal end_brst_rd_clr : STD_LOGIC;
signal end_brst_rd_clr_i_1_n_0 : STD_LOGIC;
signal end_brst_rd_i_1_n_0 : STD_LOGIC;
signal last_bram_addr : STD_LOGIC;
signal last_bram_addr0 : STD_LOGIC;
signal last_bram_addr_i_10_n_0 : STD_LOGIC;
signal last_bram_addr_i_2_n_0 : STD_LOGIC;
signal last_bram_addr_i_3_n_0 : STD_LOGIC;
signal last_bram_addr_i_4_n_0 : STD_LOGIC;
signal last_bram_addr_i_5_n_0 : STD_LOGIC;
signal last_bram_addr_i_6_n_0 : STD_LOGIC;
signal last_bram_addr_i_7_n_0 : STD_LOGIC;
signal last_bram_addr_i_8_n_0 : STD_LOGIC;
signal last_bram_addr_i_9_n_0 : STD_LOGIC;
signal no_ar_ack : STD_LOGIC;
signal no_ar_ack_i_1_n_0 : STD_LOGIC;
signal p_0_in13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_26_out : STD_LOGIC;
signal p_48_out : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pend_rd_op : STD_LOGIC;
signal pend_rd_op_i_1_n_0 : STD_LOGIC;
signal pend_rd_op_i_2_n_0 : STD_LOGIC;
signal pend_rd_op_i_3_n_0 : STD_LOGIC;
signal pend_rd_op_i_4_n_0 : STD_LOGIC;
signal pend_rd_op_i_5_n_0 : STD_LOGIC;
signal pend_rd_op_i_6_n_0 : STD_LOGIC;
signal pend_rd_op_i_7_n_0 : STD_LOGIC;
signal rd_addr_sm_cs : STD_LOGIC;
signal rd_adv_buf67_out : STD_LOGIC;
signal rd_data_sm_cs : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \rd_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_6_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_7_n_0\ : STD_LOGIC;
signal rd_data_sm_ns : STD_LOGIC;
signal rd_skid_buf : STD_LOGIC_VECTOR ( 31 downto 0 );
signal rd_skid_buf_ld : STD_LOGIC;
signal rd_skid_buf_ld_cmb : STD_LOGIC;
signal rd_skid_buf_ld_reg : STD_LOGIC;
signal rddata_mux_sel : STD_LOGIC;
signal rddata_mux_sel_cmb : STD_LOGIC;
signal rddata_mux_sel_i_1_n_0 : STD_LOGIC;
signal rddata_mux_sel_i_3_n_0 : STD_LOGIC;
signal rlast_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of rlast_sm_cs : signal is "yes";
signal \^s_axi_rlast\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_arready_int_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_early_arready_int_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_AR_DUAL.ar_active_i_4\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[0]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[10]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[11]_i_2\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[1]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[2]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[3]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[4]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[5]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[6]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[7]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[8]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[9]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of act_rd_burst_i_4 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_2 : label is "soft_lutpair7";
attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_3 : label is "soft_lutpair30";
attribute SOFT_HLUTNM of axi_rvalid_set_i_1 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \brst_cnt[4]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_3\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_4\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of brst_zero_i_1 : label is "soft_lutpair12";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of disable_b2b_brst_i_2 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of last_bram_addr_i_10 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of last_bram_addr_i_3 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of last_bram_addr_i_6 : label is "soft_lutpair19";
attribute SOFT_HLUTNM of last_bram_addr_i_8 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of pend_rd_op_i_5 : label is "soft_lutpair18";
attribute SOFT_HLUTNM of pend_rd_op_i_6 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rd_data_sm_cs[0]_i_3\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_4\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_5\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_4\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_5\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_6\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of rddata_mux_sel_i_1 : label is "soft_lutpair11";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
bram_addr_b(0) <= \^bram_addr_b\(0);
bram_en_b <= \^bram_en_b\;
bram_rst_a <= \^bram_rst_a\;
s_axi_rlast <= \^s_axi_rlast\;
s_axi_rvalid <= \^s_axi_rvalid\;
\/FSM_sequential_rlast_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0011001300130013"
)
port map (
I0 => axi_rd_burst,
I1 => rlast_sm_cs(1),
I2 => act_rd_burst_two,
I3 => axi_rd_burst_two_reg_n_0,
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\
);
\/FSM_sequential_rlast_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"003F007F003F0055"
)
port map (
I0 => axi_rd_burst,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => rlast_sm_cs(1),
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_two,
O => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\
);
\/i_\: unisim.vcomponents.LUT6
generic map(
INIT => X"F000F111F000E000"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(1),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => rlast_sm_cs(0),
I5 => last_bram_addr,
O => \/i__n_0\
);
\/i___0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00008080000F8080"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(1),
I4 => rlast_sm_cs(2),
I5 => \^s_axi_rlast\,
O => axi_rlast_set
);
\FSM_sequential_rlast_sm_cs[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(0),
O => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(1),
O => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A4FFFF00A40000"
)
port map (
I0 => rlast_sm_cs(1),
I1 => p_0_in13_in,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(2),
I4 => \/i__n_0\,
I5 => rlast_sm_cs(2),
O => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst,
O => p_0_in13_in
);
\FSM_sequential_rlast_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\,
Q => rlast_sm_cs(0),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\,
Q => rlast_sm_cs(1),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\,
Q => rlast_sm_cs(2),
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_arready_int_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAEEE"
)
port map (
I0 => p_9_out,
I1 => axi_arready_int,
I2 => s_axi_arvalid,
I3 => axi_araddr_full,
I4 => araddr_pipe_ld43_out,
O => \GEN_ARREADY.axi_arready_int_i_1_n_0\
);
\GEN_ARREADY.axi_arready_int_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BAAA"
)
port map (
I0 => axi_aresetn_re_reg,
I1 => axi_early_arready_int,
I2 => axi_araddr_full,
I3 => bram_addr_ld_en,
O => p_9_out
);
\GEN_ARREADY.axi_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_ARREADY.axi_arready_int_i_1_n_0\,
Q => axi_arready_int,
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_early_arready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000200"
)
port map (
I0 => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\,
I1 => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\,
I2 => rd_data_sm_cs(3),
I3 => brst_one,
I4 => axi_arready_int,
I5 => I_WRAP_BRST_n_23,
O => p_48_out
);
\GEN_ARREADY.axi_early_arready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CC304400000044"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\
);
\GEN_ARREADY.axi_early_arready_int_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => axi_araddr_full,
I1 => s_axi_arvalid,
O => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\
);
\GEN_ARREADY.axi_early_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_48_out,
Q => axi_early_arready_int,
R => \^bram_rst_a\
);
\GEN_AR_DUAL.ar_active_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CDCDCDDDCCCCCCCC"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_2_n_0\,
I1 => bram_addr_ld_en,
I2 => \GEN_AR_DUAL.ar_active_i_3_n_0\,
I3 => end_brst_rd,
I4 => brst_zero,
I5 => ar_active,
O => \GEN_AR_DUAL.ar_active_i_1_n_0\
);
\GEN_AR_DUAL.ar_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"808880808088A280"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_4_n_0\,
I1 => rd_data_sm_cs(1),
I2 => \GEN_AR_DUAL.ar_active_i_5_n_0\,
I3 => rd_data_sm_cs(0),
I4 => axi_rd_burst_two_reg_n_0,
I5 => axi_rd_burst,
O => \GEN_AR_DUAL.ar_active_i_2_n_0\
);
\GEN_AR_DUAL.ar_active_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \GEN_AR_DUAL.ar_active_i_3_n_0\
);
\GEN_AR_DUAL.ar_active_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
O => \GEN_AR_DUAL.ar_active_i_4_n_0\
);
\GEN_AR_DUAL.ar_active_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A88000000000000"
)
port map (
I0 => I_WRAP_BRST_n_24,
I1 => brst_zero,
I2 => axi_b2b_brst,
I3 => end_brst_rd,
I4 => rd_adv_buf67_out,
I5 => rd_data_sm_cs(0),
O => \GEN_AR_DUAL.ar_active_i_5_n_0\
);
\GEN_AR_DUAL.ar_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.ar_active_i_1_n_0\,
Q => ar_active,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_DUAL.rd_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"10001000F0F01000"
)
port map (
I0 => rd_addr_sm_cs,
I1 => axi_araddr_full,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I4 => last_bram_addr,
I5 => I_WRAP_BRST_n_23,
O => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\
);
\GEN_AR_DUAL.rd_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\,
Q => rd_addr_sm_cs,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(8),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(9),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(10),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(0),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(1),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(2),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(3),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(4),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(5),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(6),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(7),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C08888CCCC8888"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => s_axi_aresetn,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I4 => axi_araddr_full,
I5 => bram_addr_ld_en,
O => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\,
Q => axi_araddr_full,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"03AA"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
I1 => s_axi_arburst(0),
I2 => s_axi_arburst(1),
I3 => araddr_pipe_ld43_out,
O => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(0),
Q => axi_arburst_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(1),
Q => axi_arburst_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(0),
Q => axi_arid_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(10),
Q => axi_arid_pipe(10),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(11),
Q => axi_arid_pipe(11),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(1),
Q => axi_arid_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(2),
Q => axi_arid_pipe(2),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(3),
Q => axi_arid_pipe(3),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(4),
Q => axi_arid_pipe(4),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(5),
Q => axi_arid_pipe(5),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(6),
Q => axi_arid_pipe(6),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(7),
Q => axi_arid_pipe(7),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(8),
Q => axi_arid_pipe(8),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(9),
Q => axi_arid_pipe(9),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"220022002A002200"
)
port map (
I0 => axi_aresetn_d2,
I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I2 => rd_addr_sm_cs,
I3 => s_axi_arvalid,
I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I5 => axi_araddr_full,
O => araddr_pipe_ld43_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => I_WRAP_BRST_n_23,
I1 => last_bram_addr,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => no_ar_ack,
I1 => pend_rd_op,
I2 => ar_active,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_arlen(7),
I1 => s_axi_arlen(1),
I2 => s_axi_arlen(3),
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\,
O => p_13_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_axi_arlen(5),
I1 => s_axi_arlen(4),
I2 => s_axi_arlen(2),
I3 => s_axi_arlen(6),
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => p_13_out,
Q => axi_arlen_pipe_1_or_2,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(0),
Q => axi_arlen_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(1),
Q => axi_arlen_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(2),
Q => axi_arlen_pipe(2),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(3),
Q => axi_arlen_pipe(3),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(4),
Q => axi_arlen_pipe(4),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(5),
Q => axi_arlen_pipe(5),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(6),
Q => axi_arlen_pipe(6),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(7),
Q => axi_arlen_pipe(7),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => '1',
Q => axi_arsize_pipe(1),
R => '0'
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BAAA0000"
)
port map (
I0 => brst_cnt_max,
I1 => pend_rd_op,
I2 => ar_active,
I3 => brst_zero,
I4 => s_axi_aresetn,
I5 => bram_addr_ld_en,
O => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\,
Q => brst_cnt_max,
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(4),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(3),
I5 => \^q\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => I_WRAP_BRST_n_20,
I3 => \^q\(5),
I4 => \^q\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E2"
)
port map (
I0 => I_WRAP_BRST_n_21,
I1 => I_WRAP_BRST_n_7,
I2 => \^bram_addr_b\(0),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_10,
Q => \^q\(8),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_9,
Q => \^q\(9),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0\,
Q => \^bram_addr_b\(0),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_18,
Q => \^q\(0),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_17,
Q => \^q\(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_16,
Q => \^q\(2),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_15,
Q => \^q\(3),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_14,
Q => \^q\(4),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_13,
Q => \^q\(5),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_12,
Q => \^q\(6),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_11,
Q => \^q\(7),
R => '0'
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(0),
I1 => bram_rddata_b(0),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\,
Q => s_axi_rdata(0),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(10),
I1 => bram_rddata_b(10),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\,
Q => s_axi_rdata(10),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(11),
I1 => bram_rddata_b(11),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\,
Q => s_axi_rdata(11),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(12),
I1 => bram_rddata_b(12),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\,
Q => s_axi_rdata(12),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(13),
I1 => bram_rddata_b(13),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\,
Q => s_axi_rdata(13),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(14),
I1 => bram_rddata_b(14),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\,
Q => s_axi_rdata(14),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(15),
I1 => bram_rddata_b(15),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\,
Q => s_axi_rdata(15),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(16),
I1 => bram_rddata_b(16),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\,
Q => s_axi_rdata(16),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(17),
I1 => bram_rddata_b(17),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\,
Q => s_axi_rdata(17),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(18),
I1 => bram_rddata_b(18),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\,
Q => s_axi_rdata(18),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(19),
I1 => bram_rddata_b(19),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\,
Q => s_axi_rdata(19),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(1),
I1 => bram_rddata_b(1),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\,
Q => s_axi_rdata(1),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(20),
I1 => bram_rddata_b(20),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\,
Q => s_axi_rdata(20),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(21),
I1 => bram_rddata_b(21),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\,
Q => s_axi_rdata(21),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(22),
I1 => bram_rddata_b(22),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\,
Q => s_axi_rdata(22),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(23),
I1 => bram_rddata_b(23),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\,
Q => s_axi_rdata(23),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(24),
I1 => bram_rddata_b(24),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\,
Q => s_axi_rdata(24),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(25),
I1 => bram_rddata_b(25),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\,
Q => s_axi_rdata(25),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(26),
I1 => bram_rddata_b(26),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\,
Q => s_axi_rdata(26),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(27),
I1 => bram_rddata_b(27),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\,
Q => s_axi_rdata(27),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(28),
I1 => bram_rddata_b(28),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\,
Q => s_axi_rdata(28),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(29),
I1 => bram_rddata_b(29),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\,
Q => s_axi_rdata(29),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(2),
I1 => bram_rddata_b(2),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\,
Q => s_axi_rdata(2),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(30),
I1 => bram_rddata_b(30),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\,
Q => s_axi_rdata(30),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1414545410000404"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\,
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(31),
I1 => bram_rddata_b(31),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
Q => s_axi_rdata(31),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(3),
I1 => bram_rddata_b(3),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\,
Q => s_axi_rdata(3),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(4),
I1 => bram_rddata_b(4),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\,
Q => s_axi_rdata(4),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(5),
I1 => bram_rddata_b(5),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\,
Q => s_axi_rdata(5),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(6),
I1 => bram_rddata_b(6),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\,
Q => s_axi_rdata(6),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(7),
I1 => bram_rddata_b(7),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\,
Q => s_axi_rdata(7),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(8),
I1 => bram_rddata_b(8),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\,
Q => s_axi_rdata(8),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(9),
I1 => bram_rddata_b(9),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\,
Q => s_axi_rdata(9),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAEAA"
)
port map (
I0 => rd_skid_buf_ld_reg,
I1 => rd_adv_buf67_out,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(3),
O => rd_skid_buf_ld
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(0),
Q => rd_skid_buf(0),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(10),
Q => rd_skid_buf(10),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(11),
Q => rd_skid_buf(11),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(12),
Q => rd_skid_buf(12),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(13),
Q => rd_skid_buf(13),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(14),
Q => rd_skid_buf(14),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(15),
Q => rd_skid_buf(15),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(16),
Q => rd_skid_buf(16),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(17),
Q => rd_skid_buf(17),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(18),
Q => rd_skid_buf(18),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(19),
Q => rd_skid_buf(19),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(1),
Q => rd_skid_buf(1),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(20),
Q => rd_skid_buf(20),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(21),
Q => rd_skid_buf(21),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(22),
Q => rd_skid_buf(22),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(23),
Q => rd_skid_buf(23),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(24),
Q => rd_skid_buf(24),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(25),
Q => rd_skid_buf(25),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(26),
Q => rd_skid_buf(26),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(27),
Q => rd_skid_buf(27),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(28),
Q => rd_skid_buf(28),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(29),
Q => rd_skid_buf(29),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(2),
Q => rd_skid_buf(2),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(30),
Q => rd_skid_buf(30),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(31),
Q => rd_skid_buf(31),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(3),
Q => rd_skid_buf(3),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(4),
Q => rd_skid_buf(4),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(5),
Q => rd_skid_buf(5),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(6),
Q => rd_skid_buf(6),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(7),
Q => rd_skid_buf(7),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(8),
Q => rd_skid_buf(8),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(9),
Q => rd_skid_buf(9),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_int[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"08FF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rlast\,
I2 => axi_b2b_brst,
I3 => s_axi_aresetn,
O => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_rvalid_set,
I1 => s_axi_rready,
I2 => \^s_axi_rlast\,
I3 => axi_b2b_brst,
O => p_4_out
);
\GEN_RID.axi_rid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(0),
Q => s_axi_rid(0),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(10),
Q => s_axi_rid(10),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(11),
Q => s_axi_rid(11),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(1),
Q => s_axi_rid(1),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(2),
Q => s_axi_rid(2),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(3),
Q => s_axi_rid(3),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(4),
Q => s_axi_rid(4),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(5),
Q => s_axi_rid(5),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(6),
Q => s_axi_rid(6),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(7),
Q => s_axi_rid(7),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(8),
Q => s_axi_rid(8),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(9),
Q => s_axi_rid(9),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_temp2[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(0),
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
O => axi_rid_temp20_in(0)
);
\GEN_RID.axi_rid_temp2[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(10),
I1 => axi_araddr_full,
I2 => s_axi_arid(10),
O => axi_rid_temp20_in(10)
);
\GEN_RID.axi_rid_temp2[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_rid_temp_full,
I1 => bram_addr_ld_en,
O => p_26_out
);
\GEN_RID.axi_rid_temp2[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(11),
I1 => axi_araddr_full,
I2 => s_axi_arid(11),
O => axi_rid_temp20_in(11)
);
\GEN_RID.axi_rid_temp2[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arid(1),
O => axi_rid_temp20_in(1)
);
\GEN_RID.axi_rid_temp2[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(2),
I1 => axi_araddr_full,
I2 => s_axi_arid(2),
O => axi_rid_temp20_in(2)
);
\GEN_RID.axi_rid_temp2[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(3),
I1 => axi_araddr_full,
I2 => s_axi_arid(3),
O => axi_rid_temp20_in(3)
);
\GEN_RID.axi_rid_temp2[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arid(4),
O => axi_rid_temp20_in(4)
);
\GEN_RID.axi_rid_temp2[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arid(5),
O => axi_rid_temp20_in(5)
);
\GEN_RID.axi_rid_temp2[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arid(6),
O => axi_rid_temp20_in(6)
);
\GEN_RID.axi_rid_temp2[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arid(7),
O => axi_rid_temp20_in(7)
);
\GEN_RID.axi_rid_temp2[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(8),
I1 => axi_araddr_full,
I2 => s_axi_arid(8),
O => axi_rid_temp20_in(8)
);
\GEN_RID.axi_rid_temp2[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(9),
I1 => axi_araddr_full,
I2 => s_axi_arid(9),
O => axi_rid_temp20_in(9)
);
\GEN_RID.axi_rid_temp2_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080000C8C800C0"
)
port map (
I0 => bram_addr_ld_en,
I1 => s_axi_aresetn,
I2 => axi_rid_temp2_full,
I3 => axi_rid_temp_full_d1,
I4 => axi_rid_temp_full,
I5 => p_4_out,
O => \GEN_RID.axi_rid_temp2_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp2_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp2_full_i_1_n_0\,
Q => axi_rid_temp2_full,
R => '0'
);
\GEN_RID.axi_rid_temp2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(0),
Q => axi_rid_temp2(0),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(10),
Q => axi_rid_temp2(10),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(11),
Q => axi_rid_temp2(11),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(1),
Q => axi_rid_temp2(1),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(2),
Q => axi_rid_temp2(2),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(3),
Q => axi_rid_temp2(3),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(4),
Q => axi_rid_temp2(4),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(5),
Q => axi_rid_temp2(5),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(6),
Q => axi_rid_temp2(6),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(7),
Q => axi_rid_temp2(7),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(8),
Q => axi_rid_temp2(8),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(9),
Q => axi_rid_temp2(9),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(0),
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(0),
O => \GEN_RID.axi_rid_temp[0]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(10),
I1 => axi_araddr_full,
I2 => s_axi_arid(10),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(10),
O => \GEN_RID.axi_rid_temp[10]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A0FFA0E0"
)
port map (
I0 => p_4_out,
I1 => axi_rid_temp_full_d1,
I2 => axi_rid_temp2_full,
I3 => axi_rid_temp_full,
I4 => bram_addr_ld_en,
O => \GEN_RID.axi_rid_temp[11]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(11),
I1 => axi_araddr_full,
I2 => s_axi_arid(11),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(11),
O => \GEN_RID.axi_rid_temp[11]_i_2_n_0\
);
\GEN_RID.axi_rid_temp[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arid(1),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(1),
O => \GEN_RID.axi_rid_temp[1]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(2),
I1 => axi_araddr_full,
I2 => s_axi_arid(2),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(2),
O => \GEN_RID.axi_rid_temp[2]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(3),
I1 => axi_araddr_full,
I2 => s_axi_arid(3),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(3),
O => \GEN_RID.axi_rid_temp[3]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arid(4),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(4),
O => \GEN_RID.axi_rid_temp[4]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arid(5),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(5),
O => \GEN_RID.axi_rid_temp[5]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arid(6),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(6),
O => \GEN_RID.axi_rid_temp[6]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arid(7),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(7),
O => \GEN_RID.axi_rid_temp[7]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(8),
I1 => axi_araddr_full,
I2 => s_axi_arid(8),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(8),
O => \GEN_RID.axi_rid_temp[8]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(9),
I1 => axi_araddr_full,
I2 => s_axi_arid(9),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(9),
O => \GEN_RID.axi_rid_temp[9]_i_1_n_0\
);
\GEN_RID.axi_rid_temp_full_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rid_temp_full,
Q => axi_rid_temp_full_d1,
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0E000F0A0A0"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_rid_temp_full_d1,
I2 => s_axi_aresetn,
I3 => p_4_out,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2_full,
O => \GEN_RID.axi_rid_temp_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp_full_i_1_n_0\,
Q => axi_rid_temp_full,
R => '0'
);
\GEN_RID.axi_rid_temp_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[0]_i_1_n_0\,
Q => axi_rid_temp(0),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[10]_i_1_n_0\,
Q => axi_rid_temp(10),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[11]_i_2_n_0\,
Q => axi_rid_temp(11),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[1]_i_1_n_0\,
Q => axi_rid_temp(1),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[2]_i_1_n_0\,
Q => axi_rid_temp(2),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[3]_i_1_n_0\,
Q => axi_rid_temp(3),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[4]_i_1_n_0\,
Q => axi_rid_temp(4),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[5]_i_1_n_0\,
Q => axi_rid_temp(5),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[6]_i_1_n_0\,
Q => axi_rid_temp(6),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[7]_i_1_n_0\,
Q => axi_rid_temp(7),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[8]_i_1_n_0\,
Q => axi_rid_temp(8),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[9]_i_1_n_0\,
Q => axi_rid_temp(9),
R => \^bram_rst_a\
);
I_WRAP_BRST: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0
port map (
D(9) => I_WRAP_BRST_n_9,
D(8) => I_WRAP_BRST_n_10,
D(7) => I_WRAP_BRST_n_11,
D(6) => I_WRAP_BRST_n_12,
D(5) => I_WRAP_BRST_n_13,
D(4) => I_WRAP_BRST_n_14,
D(3) => I_WRAP_BRST_n_15,
D(2) => I_WRAP_BRST_n_16,
D(1) => I_WRAP_BRST_n_17,
D(0) => I_WRAP_BRST_n_18,
E(0) => I_WRAP_BRST_n_6,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3 downto 0) => axi_arlen_pipe(3 downto 0),
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ => I_WRAP_BRST_n_0,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ => I_WRAP_BRST_n_7,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\ => I_WRAP_BRST_n_8,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(9 downto 0) => \^q\(9 downto 0),
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => I_WRAP_BRST_n_20,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0_n_0\,
Q(3 downto 0) => rd_data_sm_cs(3 downto 0),
SR(0) => \^bram_rst_a\,
ar_active => ar_active,
axi_araddr_full => axi_araddr_full,
axi_aresetn_d2 => axi_aresetn_d2,
axi_arlen_pipe_1_or_2 => axi_arlen_pipe_1_or_2,
axi_arsize_pipe(0) => axi_arsize_pipe(1),
axi_arsize_pipe_max => axi_arsize_pipe_max,
axi_b2b_brst => axi_b2b_brst,
axi_b2b_brst_reg => I_WRAP_BRST_n_24,
axi_rd_burst => axi_rd_burst,
axi_rd_burst_two_reg => axi_rd_burst_two_reg_n_0,
axi_rvalid_int_reg => \^s_axi_rvalid\,
bram_addr_ld_en => bram_addr_ld_en,
brst_zero => brst_zero,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_wrap_burst_reg => curr_wrap_burst_reg,
disable_b2b_brst => disable_b2b_brst,
end_brst_rd => end_brst_rd,
last_bram_addr => last_bram_addr,
no_ar_ack => no_ar_ack,
pend_rd_op => pend_rd_op,
rd_addr_sm_cs => rd_addr_sm_cs,
rd_adv_buf67_out => rd_adv_buf67_out,
\rd_data_sm_cs_reg[1]\ => I_WRAP_BRST_n_22,
\rd_data_sm_cs_reg[3]\ => I_WRAP_BRST_n_25,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(10 downto 0) => s_axi_araddr(10 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_rready => s_axi_rready,
\save_init_bram_addr_ld_reg[12]_0\(0) => I_WRAP_BRST_n_21,
\save_init_bram_addr_ld_reg[12]_1\ => I_WRAP_BRST_n_23,
\wrap_burst_total_reg[0]_0\ => I_WRAP_BRST_n_2,
\wrap_burst_total_reg[0]_1\ => I_WRAP_BRST_n_3,
\wrap_burst_total_reg[0]_2\ => I_WRAP_BRST_n_4,
\wrap_burst_total_reg[0]_3\ => I_WRAP_BRST_n_5
);
act_rd_burst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002EEE22E2"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_set,
I2 => bram_addr_ld_en,
I3 => axi_rd_burst_two,
I4 => axi_rd_burst,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_i_1_n_0
);
act_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8AAA8A8A8A8A8"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_4_n_0\,
I1 => act_rd_burst_i_4_n_0,
I2 => axi_b2b_brst_i_3_n_0,
I3 => \rd_data_sm_cs[2]_i_4_n_0\,
I4 => last_bram_addr_i_8_n_0,
I5 => bram_addr_ld_en,
O => act_rd_burst_set
);
act_rd_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"02000004FFFFFFFF"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => \rd_data_sm_cs[3]_i_6_n_0\,
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => s_axi_aresetn,
O => act_rd_burst_i_3_n_0
);
act_rd_burst_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"4440"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
I2 => axi_rd_burst,
I3 => axi_rd_burst_two_reg_n_0,
O => act_rd_burst_i_4_n_0
);
act_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_i_1_n_0,
Q => act_rd_burst,
R => '0'
);
act_rd_burst_two_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2EEE222"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst_set,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_two_i_1_n_0
);
act_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_two_i_1_n_0,
Q => act_rd_burst_two,
R => '0'
);
axi_arsize_pipe_max_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => axi_arsize_pipe_max,
O => axi_arsize_pipe_max_i_1_n_0
);
axi_arsize_pipe_max_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_arsize_pipe_max_i_1_n_0,
Q => axi_arsize_pipe_max,
R => \^bram_rst_a\
);
axi_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CC0CCC55CC0CCCCC"
)
port map (
I0 => I_WRAP_BRST_n_24,
I1 => axi_b2b_brst,
I2 => disable_b2b_brst_i_2_n_0,
I3 => rd_data_sm_cs(3),
I4 => rd_data_sm_cs(2),
I5 => axi_b2b_brst_i_3_n_0,
O => axi_b2b_brst_i_1_n_0
);
axi_b2b_brst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000088880080"
)
port map (
I0 => \rd_data_sm_cs[0]_i_3_n_0\,
I1 => rd_adv_buf67_out,
I2 => end_brst_rd,
I3 => axi_b2b_brst,
I4 => brst_zero,
I5 => I_WRAP_BRST_n_24,
O => axi_b2b_brst_i_3_n_0
);
axi_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_b2b_brst_i_1_n_0,
Q => axi_b2b_brst,
R => \^bram_rst_a\
);
axi_rd_burst_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"303000A0"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_i_2_n_0,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_i_1_n_0
);
axi_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \brst_cnt[6]_i_2_n_0\,
I1 => axi_rd_burst_i_3_n_0,
I2 => I_WRAP_BRST_n_4,
I3 => \brst_cnt[7]_i_3_n_0\,
I4 => I_WRAP_BRST_n_3,
I5 => I_WRAP_BRST_n_2,
O => axi_rd_burst_i_2_n_0
);
axi_rd_burst_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arlen(5),
I1 => axi_arlen_pipe(5),
I2 => s_axi_arlen(4),
I3 => axi_araddr_full,
I4 => axi_arlen_pipe(4),
O => axi_rd_burst_i_3_n_0
);
axi_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_i_1_n_0,
Q => axi_rd_burst,
R => '0'
);
axi_rd_burst_two_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"C0C000A0"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst_two,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_two_i_1_n_0
);
axi_rd_burst_two_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"A808"
)
port map (
I0 => axi_rd_burst_i_2_n_0,
I1 => s_axi_arlen(0),
I2 => axi_araddr_full,
I3 => axi_arlen_pipe(0),
O => axi_rd_burst_two
);
axi_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_two_i_1_n_0,
Q => axi_rd_burst_two_reg_n_0,
R => '0'
);
axi_rlast_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"88A8"
)
port map (
I0 => s_axi_aresetn,
I1 => axi_rlast_set,
I2 => \^s_axi_rlast\,
I3 => s_axi_rready,
O => axi_rlast_int_i_1_n_0
);
axi_rlast_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rlast_int_i_1_n_0,
Q => \^s_axi_rlast\,
R => '0'
);
axi_rvalid_clr_ok_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFEEEA"
)
port map (
I0 => axi_rvalid_clr_ok,
I1 => last_bram_addr,
I2 => disable_b2b_brst,
I3 => disable_b2b_brst_cmb,
I4 => axi_rvalid_clr_ok_i_2_n_0,
I5 => axi_rvalid_clr_ok_i_3_n_0,
O => axi_rvalid_clr_ok_i_1_n_0
);
axi_rvalid_clr_ok_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAABAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
O => axi_rvalid_clr_ok_i_2_n_0
);
axi_rvalid_clr_ok_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => I_WRAP_BRST_n_23,
I1 => bram_addr_ld_en,
I2 => s_axi_aresetn,
O => axi_rvalid_clr_ok_i_3_n_0
);
axi_rvalid_clr_ok_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_clr_ok_i_1_n_0,
Q => axi_rvalid_clr_ok,
R => '0'
);
axi_rvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00E0E0E0E0E0E0E0"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => axi_rvalid_set,
I2 => s_axi_aresetn,
I3 => axi_rvalid_clr_ok,
I4 => \^s_axi_rlast\,
I5 => s_axi_rready,
O => axi_rvalid_int_i_1_n_0
);
axi_rvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_int_i_1_n_0,
Q => \^s_axi_rvalid\,
R => '0'
);
axi_rvalid_set_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
O => axi_rvalid_set_cmb
);
axi_rvalid_set_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_set_cmb,
Q => axi_rvalid_set,
R => \^bram_rst_a\
);
bram_en_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEFFFEEEEE000E"
)
port map (
I0 => bram_en_int_i_2_n_0,
I1 => bram_en_int_i_3_n_0,
I2 => bram_en_int_i_4_n_0,
I3 => I_WRAP_BRST_n_25,
I4 => bram_en_int_i_6_n_0,
I5 => \^bram_en_b\,
O => bram_en_int_i_1_n_0
);
bram_en_int_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF777FFFFFFFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => act_rd_burst,
I3 => act_rd_burst_two,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_10_n_0
);
bram_en_int_i_11: unisim.vcomponents.LUT6
generic map(
INIT => X"D0D000F0D0D0F0F0"
)
port map (
I0 => \rd_data_sm_cs[3]_i_7_n_0\,
I1 => I_WRAP_BRST_n_24,
I2 => rd_data_sm_cs(1),
I3 => brst_one,
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[2]_i_5_n_0\,
O => bram_en_int_i_11_n_0
);
bram_en_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FDF50000"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => pend_rd_op,
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(1),
I5 => bram_en_int_i_7_n_0,
O => bram_en_int_i_2_n_0
);
bram_en_int_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAEEAFAAAAAAEE"
)
port map (
I0 => I_WRAP_BRST_n_0,
I1 => bram_addr_ld_en,
I2 => p_0_in13_in,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_3_n_0
);
bram_en_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"000F007F0000007F"
)
port map (
I0 => pend_rd_op,
I1 => rd_adv_buf67_out,
I2 => \rd_data_sm_cs[0]_i_3_n_0\,
I3 => bram_en_int_i_9_n_0,
I4 => bram_addr_ld_en,
I5 => bram_en_int_i_10_n_0,
O => bram_en_int_i_4_n_0
);
bram_en_int_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"1010111111111110"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => bram_en_int_i_11_n_0,
I3 => bram_addr_ld_en,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_6_n_0
);
bram_en_int_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"3330131003001310"
)
port map (
I0 => \rd_data_sm_cs[2]_i_5_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(0),
I3 => axi_rd_burst_two_reg_n_0,
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[3]_i_7_n_0\,
O => bram_en_int_i_7_n_0
);
bram_en_int_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111111111000"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => brst_zero,
I5 => end_brst_rd,
O => bram_en_int_i_9_n_0
);
bram_en_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_int_i_1_n_0,
Q => \^bram_en_b\,
R => \^bram_rst_a\
);
\brst_cnt[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D1DDD111"
)
port map (
I0 => brst_cnt(0),
I1 => bram_addr_ld_en,
I2 => axi_arlen_pipe(0),
I3 => axi_araddr_full,
I4 => s_axi_arlen(0),
O => \brst_cnt[0]_i_1_n_0\
);
\brst_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB800B800B8FF"
)
port map (
I0 => axi_arlen_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
I3 => bram_addr_ld_en,
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[1]_i_1_n_0\
);
\brst_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_2,
I1 => bram_addr_ld_en,
I2 => brst_cnt(2),
I3 => brst_cnt(1),
I4 => brst_cnt(0),
O => \brst_cnt[2]_i_1_n_0\
);
\brst_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_3,
I1 => bram_addr_ld_en,
I2 => brst_cnt(3),
I3 => brst_cnt(2),
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[3]_i_1_n_0\
);
\brst_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => axi_arlen_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arlen(4),
I3 => bram_addr_ld_en,
I4 => brst_cnt(4),
I5 => \brst_cnt[4]_i_2_n_0\,
O => \brst_cnt[4]_i_1_n_0\
);
\brst_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => brst_cnt(2),
I1 => brst_cnt(0),
I2 => brst_cnt(1),
I3 => brst_cnt(3),
O => \brst_cnt[4]_i_2_n_0\
);
\brst_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => axi_arlen_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arlen(5),
I3 => bram_addr_ld_en,
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[5]_i_1_n_0\
);
\brst_cnt[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => \brst_cnt[6]_i_2_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(6),
I3 => brst_cnt(5),
I4 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[6]_i_1_n_0\
);
\brst_cnt[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arlen(6),
O => \brst_cnt[6]_i_2_n_0\
);
\brst_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => bram_addr_ld_en,
I1 => I_WRAP_BRST_n_8,
O => \brst_cnt[7]_i_1_n_0\
);
\brst_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B88BB8B8B8B8"
)
port map (
I0 => \brst_cnt[7]_i_3_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(7),
I3 => brst_cnt(6),
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[7]_i_2_n_0\
);
\brst_cnt[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arlen(7),
O => \brst_cnt[7]_i_3_n_0\
);
\brst_cnt[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => brst_cnt(3),
I1 => brst_cnt(1),
I2 => brst_cnt(0),
I3 => brst_cnt(2),
I4 => brst_cnt(4),
O => \brst_cnt[7]_i_4_n_0\
);
brst_cnt_max_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_cnt_max,
Q => brst_cnt_max_d1,
R => \^bram_rst_a\
);
\brst_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[0]_i_1_n_0\,
Q => brst_cnt(0),
R => \^bram_rst_a\
);
\brst_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[1]_i_1_n_0\,
Q => brst_cnt(1),
R => \^bram_rst_a\
);
\brst_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[2]_i_1_n_0\,
Q => brst_cnt(2),
R => \^bram_rst_a\
);
\brst_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[3]_i_1_n_0\,
Q => brst_cnt(3),
R => \^bram_rst_a\
);
\brst_cnt_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[4]_i_1_n_0\,
Q => brst_cnt(4),
R => \^bram_rst_a\
);
\brst_cnt_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[5]_i_1_n_0\,
Q => brst_cnt(5),
R => \^bram_rst_a\
);
\brst_cnt_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[6]_i_1_n_0\,
Q => brst_cnt(6),
R => \^bram_rst_a\
);
\brst_cnt_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[7]_i_2_n_0\,
Q => brst_cnt(7),
R => \^bram_rst_a\
);
brst_one_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E0EE0000"
)
port map (
I0 => brst_one,
I1 => brst_one0,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => s_axi_aresetn,
I5 => last_bram_addr_i_7_n_0,
O => brst_one_i_1_n_0
);
brst_one_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => bram_addr_ld_en,
I1 => I_WRAP_BRST_n_5,
I2 => axi_rd_burst_i_2_n_0,
I3 => brst_cnt(0),
I4 => brst_cnt(1),
I5 => last_bram_addr_i_9_n_0,
O => brst_one0
);
brst_one_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_one_i_1_n_0,
Q => brst_one,
R => '0'
);
brst_zero_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => brst_zero,
I1 => last_bram_addr_i_7_n_0,
I2 => s_axi_aresetn,
I3 => last_bram_addr_i_3_n_0,
O => brst_zero_i_1_n_0
);
brst_zero_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_zero_i_1_n_0,
Q => brst_zero,
R => '0'
);
curr_fixed_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arburst(0),
I1 => axi_arburst_pipe(0),
I2 => s_axi_arburst(1),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(1),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_fixed_burst,
Q => curr_fixed_burst_reg,
R => \^bram_rst_a\
);
curr_wrap_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_arburst(1),
I1 => axi_arburst_pipe(1),
I2 => s_axi_arburst(0),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_wrap_burst,
Q => curr_wrap_burst_reg,
R => \^bram_rst_a\
);
disable_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000D0000"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_two_reg_n_0,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(3),
I4 => disable_b2b_brst_i_2_n_0,
I5 => disable_b2b_brst_i_3_n_0,
O => disable_b2b_brst_cmb
);
disable_b2b_brst_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
O => disable_b2b_brst_i_2_n_0
);
disable_b2b_brst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FE7D0000FE7DFE7D"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(3),
I4 => disable_b2b_brst,
I5 => disable_b2b_brst_i_4_n_0,
O => disable_b2b_brst_i_3_n_0
);
disable_b2b_brst_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"DFDFDFDFDFDFDFFF"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_4_n_0\,
I1 => rd_adv_buf67_out,
I2 => rd_data_sm_cs(0),
I3 => brst_zero,
I4 => end_brst_rd,
I5 => brst_one,
O => disable_b2b_brst_i_4_n_0
);
disable_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => disable_b2b_brst_cmb,
Q => disable_b2b_brst,
R => \^bram_rst_a\
);
end_brst_rd_clr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFF10100000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => bram_addr_ld_en,
I4 => rd_data_sm_cs(0),
I5 => end_brst_rd_clr,
O => end_brst_rd_clr_i_1_n_0
);
end_brst_rd_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_clr_i_1_n_0,
Q => end_brst_rd_clr,
R => \^bram_rst_a\
);
end_brst_rd_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0020F020"
)
port map (
I0 => brst_cnt_max,
I1 => brst_cnt_max_d1,
I2 => s_axi_aresetn,
I3 => end_brst_rd,
I4 => end_brst_rd_clr,
O => end_brst_rd_i_1_n_0
);
end_brst_rd_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_i_1_n_0,
Q => end_brst_rd,
R => '0'
);
last_bram_addr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF57550000"
)
port map (
I0 => last_bram_addr_i_2_n_0,
I1 => last_bram_addr_i_3_n_0,
I2 => last_bram_addr_i_4_n_0,
I3 => last_bram_addr_i_5_n_0,
I4 => last_bram_addr_i_6_n_0,
I5 => last_bram_addr_i_7_n_0,
O => last_bram_addr0
);
last_bram_addr_i_10: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => brst_cnt(6),
I1 => brst_cnt(5),
O => last_bram_addr_i_10_n_0
);
last_bram_addr_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"AABFFFBFFFBFFFBF"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => last_bram_addr_i_8_n_0,
I2 => bram_addr_ld_en,
I3 => rd_data_sm_cs(3),
I4 => rd_adv_buf67_out,
I5 => p_0_in13_in,
O => last_bram_addr_i_2_n_0
);
last_bram_addr_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"8A80AAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_arlen_pipe(0),
I2 => axi_araddr_full,
I3 => s_axi_arlen(0),
I4 => axi_rd_burst_i_2_n_0,
O => last_bram_addr_i_3_n_0
);
last_bram_addr_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDDFFFDFFFF"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => axi_rd_burst,
I3 => axi_rd_burst_two_reg_n_0,
I4 => pend_rd_op,
I5 => bram_addr_ld_en,
O => last_bram_addr_i_4_n_0
);
last_bram_addr_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => bram_addr_ld_en,
I3 => pend_rd_op,
O => last_bram_addr_i_5_n_0
);
last_bram_addr_i_6: unisim.vcomponents.LUT3
generic map(
INIT => X"81"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
O => last_bram_addr_i_6_n_0
);
last_bram_addr_i_7: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => last_bram_addr_i_9_n_0,
I1 => brst_cnt(0),
I2 => brst_cnt(1),
O => last_bram_addr_i_7_n_0
);
last_bram_addr_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"02A2"
)
port map (
I0 => axi_rd_burst_i_2_n_0,
I1 => s_axi_arlen(0),
I2 => axi_araddr_full,
I3 => axi_arlen_pipe(0),
O => last_bram_addr_i_8_n_0
);
last_bram_addr_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => I_WRAP_BRST_n_8,
I1 => last_bram_addr_i_10_n_0,
I2 => brst_cnt(3),
I3 => brst_cnt(2),
I4 => brst_cnt(4),
I5 => brst_cnt(7),
O => last_bram_addr_i_9_n_0
);
last_bram_addr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => last_bram_addr0,
Q => last_bram_addr,
R => \^bram_rst_a\
);
no_ar_ack_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA88C8AAAA"
)
port map (
I0 => no_ar_ack,
I1 => rd_data_sm_cs(1),
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(0),
I5 => I_WRAP_BRST_n_25,
O => no_ar_ack_i_1_n_0
);
no_ar_ack_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => no_ar_ack_i_1_n_0,
Q => no_ar_ack,
R => \^bram_rst_a\
);
pend_rd_op_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFFFEAAAA0002"
)
port map (
I0 => pend_rd_op_i_2_n_0,
I1 => pend_rd_op_i_3_n_0,
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(2),
I4 => pend_rd_op_i_4_n_0,
I5 => pend_rd_op,
O => pend_rd_op_i_1_n_0
);
pend_rd_op_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFCC8C80CCCC8C8"
)
port map (
I0 => p_0_in13_in,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => pend_rd_op_i_5_n_0,
O => pend_rd_op_i_2_n_0
);
pend_rd_op_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0303070733F3FFFF"
)
port map (
I0 => p_0_in13_in,
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(1),
I3 => \^s_axi_rlast\,
I4 => pend_rd_op,
I5 => bram_addr_ld_en,
O => pend_rd_op_i_3_n_0
);
pend_rd_op_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BBBABB00"
)
port map (
I0 => pend_rd_op_i_6_n_0,
I1 => rd_data_sm_cs(0),
I2 => pend_rd_op_i_5_n_0,
I3 => bram_addr_ld_en,
I4 => pend_rd_op_i_7_n_0,
I5 => I_WRAP_BRST_n_25,
O => pend_rd_op_i_4_n_0
);
pend_rd_op_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => ar_active,
I1 => end_brst_rd,
O => pend_rd_op_i_5_n_0
);
pend_rd_op_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"8000FFFF"
)
port map (
I0 => pend_rd_op,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
O => pend_rd_op_i_6_n_0
);
pend_rd_op_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF0008888"
)
port map (
I0 => pend_rd_op,
I1 => \^s_axi_rlast\,
I2 => ar_active,
I3 => end_brst_rd,
I4 => rd_data_sm_cs(0),
I5 => rd_data_sm_cs(1),
O => pend_rd_op_i_7_n_0
);
pend_rd_op_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => pend_rd_op_i_1_n_0,
Q => pend_rd_op,
R => \^bram_rst_a\
);
\rd_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF54005555"
)
port map (
I0 => \rd_data_sm_cs[0]_i_2_n_0\,
I1 => pend_rd_op,
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => \rd_data_sm_cs[0]_i_3_n_0\,
I5 => \rd_data_sm_cs[0]_i_4_n_0\,
O => \rd_data_sm_cs[0]_i_1_n_0\
);
\rd_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEAAAAAAFEAAFEAA"
)
port map (
I0 => I_WRAP_BRST_n_25,
I1 => act_rd_burst_two,
I2 => act_rd_burst,
I3 => disable_b2b_brst_i_2_n_0,
I4 => bram_addr_ld_en,
I5 => rd_adv_buf67_out,
O => \rd_data_sm_cs[0]_i_2_n_0\
);
\rd_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[0]_i_3_n_0\
);
\rd_data_sm_cs[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"000300BF0003008F"
)
port map (
I0 => rd_adv_buf67_out,
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(3),
I5 => p_0_in13_in,
O => \rd_data_sm_cs[0]_i_4_n_0\
);
\rd_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABAAABAFFFFAABA"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => I_WRAP_BRST_n_25,
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => rd_data_sm_cs(0),
I4 => I_WRAP_BRST_n_22,
I5 => \rd_data_sm_cs[1]_i_3_n_0\,
O => \rd_data_sm_cs[1]_i_1_n_0\
);
\rd_data_sm_cs[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0CCCCCC88888888"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => I_WRAP_BRST_n_24,
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
I5 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[1]_i_3_n_0\
);
\rd_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAABAEAFAAAB"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(3),
I3 => \rd_data_sm_cs[2]_i_3_n_0\,
I4 => \rd_data_sm_cs[2]_i_4_n_0\,
I5 => \rd_data_sm_cs[2]_i_5_n_0\,
O => \rd_data_sm_cs[2]_i_1_n_0\
);
\rd_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000DF00000"
)
port map (
I0 => bram_addr_ld_en,
I1 => \rd_data_sm_cs[3]_i_6_n_0\,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => rd_data_sm_cs(3),
O => \rd_data_sm_cs[2]_i_2_n_0\
);
\rd_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C0FFFF33F3BBBB"
)
port map (
I0 => axi_rd_burst,
I1 => rd_data_sm_cs(0),
I2 => rd_adv_buf67_out,
I3 => I_WRAP_BRST_n_24,
I4 => rd_data_sm_cs(1),
I5 => axi_rd_burst_two_reg_n_0,
O => \rd_data_sm_cs[2]_i_3_n_0\
);
\rd_data_sm_cs[2]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[2]_i_4_n_0\
);
\rd_data_sm_cs[2]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => brst_zero,
I1 => end_brst_rd,
O => \rd_data_sm_cs[2]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCCCBBBB3000B888"
)
port map (
I0 => \rd_data_sm_cs[3]_i_3_n_0\,
I1 => \rd_data_sm_cs[3]_i_4_n_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
I4 => \rd_data_sm_cs[3]_i_5_n_0\,
I5 => bram_addr_ld_en,
O => rd_data_sm_ns
);
\rd_data_sm_cs[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000004050005040"
)
port map (
I0 => I_WRAP_BRST_n_25,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => \rd_data_sm_cs[3]_i_6_n_0\,
I5 => rd_adv_buf67_out,
O => \rd_data_sm_cs[3]_i_2_n_0\
);
\rd_data_sm_cs[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF5EFFFF"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(3),
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[3]_i_7_n_0\,
O => \rd_data_sm_cs[3]_i_3_n_0\
);
\rd_data_sm_cs[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"BFAD"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_4_n_0\
);
\rd_data_sm_cs[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0035"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"1FFF"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \rd_data_sm_cs[3]_i_6_n_0\
);
\rd_data_sm_cs[3]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => brst_zero,
I1 => axi_b2b_brst,
I2 => end_brst_rd,
O => \rd_data_sm_cs[3]_i_7_n_0\
);
\rd_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[0]_i_1_n_0\,
Q => rd_data_sm_cs(0),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[1]_i_1_n_0\,
Q => rd_data_sm_cs(1),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[2]_i_1_n_0\,
Q => rd_data_sm_cs(2),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[3]_i_2_n_0\,
Q => rd_data_sm_cs(3),
R => \^bram_rst_a\
);
rd_skid_buf_ld_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1110011001100110"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => s_axi_rready,
I5 => \^s_axi_rvalid\,
O => rd_skid_buf_ld_cmb
);
rd_skid_buf_ld_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rd_skid_buf_ld_cmb,
Q => rd_skid_buf_ld_reg,
R => \^bram_rst_a\
);
rddata_mux_sel_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE02"
)
port map (
I0 => rddata_mux_sel_cmb,
I1 => rd_data_sm_cs(3),
I2 => rddata_mux_sel_i_3_n_0,
I3 => rddata_mux_sel,
O => rddata_mux_sel_i_1_n_0
);
rddata_mux_sel_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F010F00F00F000"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
I5 => rd_adv_buf67_out,
O => rddata_mux_sel_cmb
);
rddata_mux_sel_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"F700070FF70F070F"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => axi_rd_burst_two_reg_n_0,
O => rddata_mux_sel_i_3_n_0
);
rddata_mux_sel_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rddata_mux_sel_i_1_n_0,
Q => rddata_mux_sel,
R => \^bram_rst_a\
);
s_axi_arready_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_arready_int,
I1 => \^s_axi_rvalid\,
I2 => s_axi_rready,
I3 => axi_early_arready_int,
O => s_axi_arready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl is
port (
axi_aresetn_d2 : out STD_LOGIC;
axi_aresetn_re_reg : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\GEN_AW_DUAL.aw_active_reg_0\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl : entity is "wr_chnl";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl is
signal BID_FIFO_n_0 : STD_LOGIC;
signal BID_FIFO_n_10 : STD_LOGIC;
signal BID_FIFO_n_11 : STD_LOGIC;
signal BID_FIFO_n_12 : STD_LOGIC;
signal BID_FIFO_n_13 : STD_LOGIC;
signal BID_FIFO_n_14 : STD_LOGIC;
signal BID_FIFO_n_15 : STD_LOGIC;
signal BID_FIFO_n_3 : STD_LOGIC;
signal BID_FIFO_n_4 : STD_LOGIC;
signal BID_FIFO_n_5 : STD_LOGIC;
signal BID_FIFO_n_6 : STD_LOGIC;
signal BID_FIFO_n_7 : STD_LOGIC;
signal BID_FIFO_n_8 : STD_LOGIC;
signal BID_FIFO_n_9 : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.aw_active_i_2_n_0\ : STD_LOGIC;
signal \^gen_aw_dual.aw_active_reg_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\ : STD_LOGIC;
signal \I_RD_CHNL/axi_aresetn_d1\ : STD_LOGIC;
signal I_WRAP_BRST_n_0 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_18 : STD_LOGIC;
signal I_WRAP_BRST_n_19 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_3 : STD_LOGIC;
signal I_WRAP_BRST_n_4 : STD_LOGIC;
signal I_WRAP_BRST_n_5 : STD_LOGIC;
signal I_WRAP_BRST_n_6 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal aw_active : STD_LOGIC;
signal \^axi_aresetn_d2\ : STD_LOGIC;
signal axi_aresetn_re : STD_LOGIC;
signal \^axi_aresetn_re_reg\ : STD_LOGIC;
signal axi_awaddr_full : STD_LOGIC;
signal axi_awburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_awid_pipe : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_awlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_awlen_pipe_1_or_2 : STD_LOGIC;
signal axi_awsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_bvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_wdata_full_cmb : STD_LOGIC;
signal axi_wdata_full_cmb114_out : STD_LOGIC;
signal axi_wdata_full_reg : STD_LOGIC;
signal axi_wr_burst : STD_LOGIC;
signal axi_wr_burst_cmb : STD_LOGIC;
signal axi_wr_burst_cmb0 : STD_LOGIC;
signal axi_wr_burst_i_1_n_0 : STD_LOGIC;
signal axi_wr_burst_i_3_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_1_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_3_n_0 : STD_LOGIC;
signal bid_gets_fifo_load : STD_LOGIC;
signal bid_gets_fifo_load_d1 : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_2_n_0 : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal bram_addr_inc : STD_LOGIC;
signal bram_addr_ld : STD_LOGIC_VECTOR ( 10 to 10 );
signal bram_addr_ld_en : STD_LOGIC;
signal bram_addr_ld_en_mod : STD_LOGIC;
signal bram_addr_rst_cmb : STD_LOGIC;
signal bram_en_cmb : STD_LOGIC;
signal bvalid_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \bvalid_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal bvalid_cnt_inc : STD_LOGIC;
signal bvalid_cnt_inc11_out : STD_LOGIC;
signal clr_bram_we : STD_LOGIC;
signal clr_bram_we_cmb : STD_LOGIC;
signal curr_awlen_reg_1_or_2 : STD_LOGIC;
signal curr_awlen_reg_1_or_20 : STD_LOGIC;
signal curr_awlen_reg_1_or_2_i_2_n_0 : STD_LOGIC;
signal curr_awlen_reg_1_or_2_i_3_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal delay_aw_active_clr : STD_LOGIC;
signal last_data_ack_mod : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal wr_addr_sm_cs : STD_LOGIC;
signal wr_data_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of wr_data_sm_cs : signal is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\ : label is "soft_lutpair63";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \GEN_AW_DUAL.last_data_ack_mod_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_2 : label is "soft_lutpair61";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_2 : label is "soft_lutpair60";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_2 : label is "soft_lutpair60";
begin
\GEN_AW_DUAL.aw_active_reg_0\ <= \^gen_aw_dual.aw_active_reg_0\;
axi_aresetn_d2 <= \^axi_aresetn_d2\;
axi_aresetn_re_reg <= \^axi_aresetn_re_reg\;
bram_addr_a(10 downto 0) <= \^bram_addr_a\(10 downto 0);
s_axi_awready <= \^s_axi_awready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_wready <= \^s_axi_wready\;
BID_FIFO: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO
port map (
D(11) => BID_FIFO_n_4,
D(10) => BID_FIFO_n_5,
D(9) => BID_FIFO_n_6,
D(8) => BID_FIFO_n_7,
D(7) => BID_FIFO_n_8,
D(6) => BID_FIFO_n_9,
D(5) => BID_FIFO_n_10,
D(4) => BID_FIFO_n_11,
D(3) => BID_FIFO_n_12,
D(2) => BID_FIFO_n_13,
D(1) => BID_FIFO_n_14,
D(0) => BID_FIFO_n_15,
E(0) => BID_FIFO_n_0,
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
Q(11 downto 0) => axi_awid_pipe(11 downto 0),
SR(0) => SR(0),
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
axi_bvalid_int_reg => \^s_axi_bvalid\,
axi_wdata_full_cmb114_out => axi_wdata_full_cmb114_out,
axi_wr_burst => axi_wr_burst,
bid_gets_fifo_load => bid_gets_fifo_load,
bid_gets_fifo_load_d1 => bid_gets_fifo_load_d1,
bid_gets_fifo_load_d1_reg => BID_FIFO_n_3,
bram_addr_ld_en => bram_addr_ld_en,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
bvalid_cnt_inc => bvalid_cnt_inc,
\bvalid_cnt_reg[1]\ => bid_gets_fifo_load_d1_i_2_n_0,
\bvalid_cnt_reg[2]\ => I_WRAP_BRST_n_17,
\bvalid_cnt_reg[2]_0\ => I_WRAP_BRST_n_16,
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awready => \^s_axi_awready\,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
wr_addr_sm_cs => wr_addr_sm_cs
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(0),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"05051F1A"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => axi_wr_burst_cmb0,
I2 => wr_data_sm_cs(0),
I3 => axi_wdata_full_cmb114_out,
I4 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"5515"
)
port map (
I0 => I_WRAP_BRST_n_18,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
O => axi_wr_burst_cmb0
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(1),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000554000555540"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => s_axi_wlast,
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(2),
I5 => axi_wr_burst,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"44010001"
)
port map (
I0 => wr_data_sm_cs(2),
I1 => wr_data_sm_cs(1),
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7774777774744444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(0),
I5 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\,
Q => wr_data_sm_cs(0),
R => SR(0)
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\,
Q => wr_data_sm_cs(1),
R => SR(0)
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\,
Q => wr_data_sm_cs(2),
R => SR(0)
);
\GEN_AWREADY.axi_aresetn_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_aresetn,
Q => \I_RD_CHNL/axi_aresetn_d1\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \I_RD_CHNL/axi_aresetn_d1\,
Q => \^axi_aresetn_d2\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_re_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_aresetn,
I1 => \I_RD_CHNL/axi_aresetn_d1\,
O => axi_aresetn_re
);
\GEN_AWREADY.axi_aresetn_re_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_aresetn_re,
Q => \^axi_aresetn_re_reg\,
R => '0'
);
\GEN_AWREADY.axi_awready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFBFFFFFAA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => bram_addr_ld_en,
I4 => \^axi_aresetn_re_reg\,
I5 => \^s_axi_awready\,
O => \GEN_AWREADY.axi_awready_int_i_1_n_0\
);
\GEN_AWREADY.axi_awready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"5444444400000000"
)
port map (
I0 => \GEN_AWREADY.axi_awready_int_i_3_n_0\,
I1 => aw_active,
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => s_axi_awvalid,
O => \GEN_AWREADY.axi_awready_int_i_2_n_0\
);
\GEN_AWREADY.axi_awready_int_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABABABABABABABA"
)
port map (
I0 => wr_addr_sm_cs,
I1 => I_WRAP_BRST_n_18,
I2 => last_data_ack_mod,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \GEN_AWREADY.axi_awready_int_i_3_n_0\
);
\GEN_AWREADY.axi_awready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AWREADY.axi_awready_int_i_1_n_0\,
Q => \^s_axi_awready\,
R => SR(0)
);
\GEN_AW_DUAL.aw_active_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axi_aresetn_d2\,
O => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.aw_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF7FFFFFF0000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => wr_data_sm_cs(2),
I3 => delay_aw_active_clr,
I4 => bram_addr_ld_en,
I5 => aw_active,
O => \GEN_AW_DUAL.aw_active_i_2_n_0\
);
\GEN_AW_DUAL.aw_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.aw_active_i_2_n_0\,
Q => aw_active,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.last_data_ack_mod_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => p_18_out
);
\GEN_AW_DUAL.last_data_ack_mod_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_18_out,
Q => last_data_ack_mod,
R => SR(0)
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000100000"
)
port map (
I0 => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\,
I1 => wr_addr_sm_cs,
I2 => s_axi_awvalid,
I3 => axi_awaddr_full,
I4 => I_WRAP_BRST_n_17,
I5 => aw_active,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => I_WRAP_BRST_n_17,
I1 => last_data_ack_mod,
I2 => axi_awaddr_full,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => axi_awlen_pipe_1_or_2,
I5 => curr_awlen_reg_1_or_2,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\,
Q => wr_addr_sm_cs,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(8),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(9),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(10),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(0),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(1),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(2),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(3),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(4),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(5),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(6),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(7),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4000EA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => s_axi_aresetn,
I4 => bram_addr_ld_en,
O => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\,
Q => axi_awaddr_full,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BF00BF00BF00FF40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => s_axi_awburst(0),
I5 => s_axi_awburst(1),
O => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(0),
Q => axi_awburst_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(1),
Q => axi_awburst_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(0),
Q => axi_awid_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(10),
Q => axi_awid_pipe(10),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(11),
Q => axi_awid_pipe(11),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(1),
Q => axi_awid_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(2),
Q => axi_awid_pipe(2),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(3),
Q => axi_awid_pipe(3),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(4),
Q => axi_awid_pipe(4),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(5),
Q => axi_awid_pipe(5),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(6),
Q => axi_awid_pipe(6),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(7),
Q => axi_awid_pipe(7),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(8),
Q => axi_awid_pipe(8),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(9),
Q => axi_awid_pipe(9),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
I1 => s_axi_awlen(3),
I2 => s_axi_awlen(2),
I3 => s_axi_awlen(1),
O => p_9_out
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_awlen(4),
I1 => s_axi_awlen(6),
I2 => s_axi_awlen(7),
I3 => s_axi_awlen(5),
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => p_9_out,
Q => axi_awlen_pipe_1_or_2,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(0),
Q => axi_awlen_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(1),
Q => axi_awlen_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(2),
Q => axi_awlen_pipe(2),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(3),
Q => axi_awlen_pipe(3),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(4),
Q => axi_awlen_pipe(4),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(5),
Q => axi_awlen_pipe(5),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(6),
Q => axi_awlen_pipe(6),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(7),
Q => axi_awlen_pipe(7),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => '1',
Q => axi_awsize_pipe(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^bram_addr_a\(4),
I1 => \^bram_addr_a\(1),
I2 => \^bram_addr_a\(0),
I3 => \^bram_addr_a\(2),
I4 => \^bram_addr_a\(3),
I5 => \^bram_addr_a\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => s_axi_wvalid,
O => bram_addr_inc
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => wr_data_sm_cs(1),
O => bram_addr_rst_cmb
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^bram_addr_a\(6),
I1 => \^bram_addr_a\(4),
I2 => I_WRAP_BRST_n_14,
I3 => \^bram_addr_a\(5),
I4 => \^bram_addr_a\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => \^bram_addr_a\(10),
I1 => bram_addr_ld_en_mod,
I2 => bram_addr_ld(10),
I3 => I_WRAP_BRST_n_0,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_4,
Q => \^bram_addr_a\(8),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_3,
Q => \^bram_addr_a\(9),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0\,
Q => \^bram_addr_a\(10),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_12,
Q => \^bram_addr_a\(0),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_11,
Q => \^bram_addr_a\(1),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_10,
Q => \^bram_addr_a\(2),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_9,
Q => \^bram_addr_a\(3),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_8,
Q => \^bram_addr_a\(4),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_7,
Q => \^bram_addr_a\(5),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_6,
Q => \^bram_addr_a\(6),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_5,
Q => \^bram_addr_a\(7),
R => I_WRAP_BRST_n_0
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"15FF1500"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
O => axi_wdata_full_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wdata_full_cmb,
Q => axi_wdata_full_reg,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4777477444444444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => s_axi_wvalid,
O => bram_en_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_cmb,
Q => bram_en_a,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000101110"
)
port map (
I0 => wr_data_sm_cs(0),
I1 => wr_data_sm_cs(1),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I5 => axi_wr_burst,
O => clr_bram_we_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => clr_bram_we_cmb,
Q => clr_bram_we,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEAAFEFF02AA0200"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\,
I1 => axi_wr_burst,
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\,
I5 => delay_aw_active_clr,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000222E"
)
port map (
I0 => s_axi_wlast,
I1 => wr_data_sm_cs(2),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(1),
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8B338B0088008800"
)
port map (
I0 => delay_aw_active_clr,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => bvalid_cnt_inc11_out,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_wlast,
O => bvalid_cnt_inc11_out
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\,
Q => delay_aw_active_clr,
R => SR(0)
);
\GEN_WRDATA[0].bram_wrdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(0),
Q => bram_wrdata_a(0),
R => '0'
);
\GEN_WRDATA[10].bram_wrdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(10),
Q => bram_wrdata_a(10),
R => '0'
);
\GEN_WRDATA[11].bram_wrdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(11),
Q => bram_wrdata_a(11),
R => '0'
);
\GEN_WRDATA[12].bram_wrdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(12),
Q => bram_wrdata_a(12),
R => '0'
);
\GEN_WRDATA[13].bram_wrdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(13),
Q => bram_wrdata_a(13),
R => '0'
);
\GEN_WRDATA[14].bram_wrdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(14),
Q => bram_wrdata_a(14),
R => '0'
);
\GEN_WRDATA[15].bram_wrdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(15),
Q => bram_wrdata_a(15),
R => '0'
);
\GEN_WRDATA[16].bram_wrdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(16),
Q => bram_wrdata_a(16),
R => '0'
);
\GEN_WRDATA[17].bram_wrdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(17),
Q => bram_wrdata_a(17),
R => '0'
);
\GEN_WRDATA[18].bram_wrdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(18),
Q => bram_wrdata_a(18),
R => '0'
);
\GEN_WRDATA[19].bram_wrdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(19),
Q => bram_wrdata_a(19),
R => '0'
);
\GEN_WRDATA[1].bram_wrdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(1),
Q => bram_wrdata_a(1),
R => '0'
);
\GEN_WRDATA[20].bram_wrdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(20),
Q => bram_wrdata_a(20),
R => '0'
);
\GEN_WRDATA[21].bram_wrdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(21),
Q => bram_wrdata_a(21),
R => '0'
);
\GEN_WRDATA[22].bram_wrdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(22),
Q => bram_wrdata_a(22),
R => '0'
);
\GEN_WRDATA[23].bram_wrdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(23),
Q => bram_wrdata_a(23),
R => '0'
);
\GEN_WRDATA[24].bram_wrdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(24),
Q => bram_wrdata_a(24),
R => '0'
);
\GEN_WRDATA[25].bram_wrdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(25),
Q => bram_wrdata_a(25),
R => '0'
);
\GEN_WRDATA[26].bram_wrdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(26),
Q => bram_wrdata_a(26),
R => '0'
);
\GEN_WRDATA[27].bram_wrdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(27),
Q => bram_wrdata_a(27),
R => '0'
);
\GEN_WRDATA[28].bram_wrdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(28),
Q => bram_wrdata_a(28),
R => '0'
);
\GEN_WRDATA[29].bram_wrdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(29),
Q => bram_wrdata_a(29),
R => '0'
);
\GEN_WRDATA[2].bram_wrdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(2),
Q => bram_wrdata_a(2),
R => '0'
);
\GEN_WRDATA[30].bram_wrdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(30),
Q => bram_wrdata_a(30),
R => '0'
);
\GEN_WRDATA[31].bram_wrdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(31),
Q => bram_wrdata_a(31),
R => '0'
);
\GEN_WRDATA[3].bram_wrdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(3),
Q => bram_wrdata_a(3),
R => '0'
);
\GEN_WRDATA[4].bram_wrdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(4),
Q => bram_wrdata_a(4),
R => '0'
);
\GEN_WRDATA[5].bram_wrdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(5),
Q => bram_wrdata_a(5),
R => '0'
);
\GEN_WRDATA[6].bram_wrdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(6),
Q => bram_wrdata_a(6),
R => '0'
);
\GEN_WRDATA[7].bram_wrdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(7),
Q => bram_wrdata_a(7),
R => '0'
);
\GEN_WRDATA[8].bram_wrdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(8),
Q => bram_wrdata_a(8),
R => '0'
);
\GEN_WRDATA[9].bram_wrdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(9),
Q => bram_wrdata_a(9),
R => '0'
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"D0FF"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => clr_bram_we,
I3 => s_axi_aresetn,
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(0),
Q => bram_we_a(0),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(1),
Q => bram_we_a(1),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(2),
Q => bram_we_a(2),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(3),
Q => bram_we_a(3),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
I_WRAP_BRST: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst
port map (
D(9) => I_WRAP_BRST_n_3,
D(8) => I_WRAP_BRST_n_4,
D(7) => I_WRAP_BRST_n_5,
D(6) => I_WRAP_BRST_n_6,
D(5) => I_WRAP_BRST_n_7,
D(4) => I_WRAP_BRST_n_8,
D(3) => I_WRAP_BRST_n_9,
D(2) => I_WRAP_BRST_n_10,
D(1) => I_WRAP_BRST_n_11,
D(0) => I_WRAP_BRST_n_12,
E(0) => I_WRAP_BRST_n_2,
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ => I_WRAP_BRST_n_0,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => I_WRAP_BRST_n_14,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0_n_0\,
Q(3 downto 0) => axi_awlen_pipe(3 downto 0),
SR(0) => SR(0),
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
axi_awsize_pipe(0) => axi_awsize_pipe(1),
bram_addr_a(9 downto 0) => \^bram_addr_a\(9 downto 0),
bram_addr_inc => bram_addr_inc,
bram_addr_ld_en => bram_addr_ld_en,
bram_addr_ld_en_mod => bram_addr_ld_en_mod,
bram_addr_rst_cmb => bram_addr_rst_cmb,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
curr_fixed_burst => curr_fixed_burst,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_fixed_burst_reg_reg => I_WRAP_BRST_n_19,
curr_wrap_burst => curr_wrap_burst,
curr_wrap_burst_reg => curr_wrap_burst_reg,
curr_wrap_burst_reg_reg => I_WRAP_BRST_n_20,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr(10 downto 0) => s_axi_awaddr(10 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_wvalid => s_axi_wvalid,
\save_init_bram_addr_ld_reg[12]_0\(0) => bram_addr_ld(10),
\save_init_bram_addr_ld_reg[12]_1\ => I_WRAP_BRST_n_16,
\save_init_bram_addr_ld_reg[12]_2\ => I_WRAP_BRST_n_17,
\save_init_bram_addr_ld_reg[12]_3\ => I_WRAP_BRST_n_18,
wr_addr_sm_cs => wr_addr_sm_cs
);
\axi_bid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_15,
Q => s_axi_bid(0),
R => SR(0)
);
\axi_bid_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_5,
Q => s_axi_bid(10),
R => SR(0)
);
\axi_bid_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_4,
Q => s_axi_bid(11),
R => SR(0)
);
\axi_bid_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_14,
Q => s_axi_bid(1),
R => SR(0)
);
\axi_bid_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_13,
Q => s_axi_bid(2),
R => SR(0)
);
\axi_bid_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_12,
Q => s_axi_bid(3),
R => SR(0)
);
\axi_bid_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_11,
Q => s_axi_bid(4),
R => SR(0)
);
\axi_bid_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_10,
Q => s_axi_bid(5),
R => SR(0)
);
\axi_bid_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_9,
Q => s_axi_bid(6),
R => SR(0)
);
\axi_bid_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_8,
Q => s_axi_bid(7),
R => SR(0)
);
\axi_bid_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_7,
Q => s_axi_bid(8),
R => SR(0)
);
\axi_bid_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_6,
Q => s_axi_bid(9),
R => SR(0)
);
axi_bvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAA8A88"
)
port map (
I0 => s_axi_aresetn,
I1 => bvalid_cnt_inc,
I2 => BID_FIFO_n_3,
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => bvalid_cnt(1),
O => axi_bvalid_int_i_1_n_0
);
axi_bvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_bvalid_int_i_1_n_0,
Q => \^s_axi_bvalid\,
R => '0'
);
axi_wr_burst_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_wr_burst_cmb,
I1 => axi_wr_burst_i_3_n_0,
I2 => axi_wr_burst,
O => axi_wr_burst_i_1_n_0
);
axi_wr_burst_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"3088FCBB"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wlast,
O => axi_wr_burst_cmb
);
axi_wr_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAA222"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(0),
I2 => axi_wr_burst_cmb0,
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(1),
I5 => wr_data_sm_cs(2),
O => axi_wr_burst_i_3_n_0
);
axi_wr_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wr_burst_i_1_n_0,
Q => axi_wr_burst,
R => SR(0)
);
axi_wready_int_mod_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EA00EAFF00000000"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
I5 => s_axi_aresetn,
O => axi_wready_int_mod_i_1_n_0
);
axi_wready_int_mod_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"F8F9F0F0"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => axi_wdata_full_reg,
I3 => axi_wdata_full_cmb114_out,
I4 => s_axi_wvalid,
O => axi_wready_int_mod_i_3_n_0
);
axi_wready_int_mod_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wready_int_mod_i_1_n_0,
Q => \^s_axi_wready\,
R => '0'
);
bid_gets_fifo_load_d1_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
O => bid_gets_fifo_load_d1_i_2_n_0
);
bid_gets_fifo_load_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bid_gets_fifo_load,
Q => bid_gets_fifo_load_d1,
R => SR(0)
);
\bvalid_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"95956A6A95956AAA"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[0]_i_1_n_0\
);
\bvalid_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D5D5BFBF2A2A4000"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[1]_i_1_n_0\
);
\bvalid_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D52AFF00FF00BF00"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[2]_i_1_n_0\
);
\bvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[0]_i_1_n_0\,
Q => bvalid_cnt(0),
R => SR(0)
);
\bvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[1]_i_1_n_0\,
Q => bvalid_cnt(1),
R => SR(0)
);
\bvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[2]_i_1_n_0\,
Q => bvalid_cnt(2),
R => SR(0)
);
curr_awlen_reg_1_or_2_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"5000303050003000"
)
port map (
I0 => axi_awlen_pipe(3),
I1 => s_axi_awlen(3),
I2 => curr_awlen_reg_1_or_2_i_2_n_0,
I3 => curr_awlen_reg_1_or_2_i_3_n_0,
I4 => axi_awaddr_full,
I5 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
O => curr_awlen_reg_1_or_20
);
curr_awlen_reg_1_or_2_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awlen(2),
I1 => axi_awlen_pipe(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => axi_awlen_pipe(1),
O => curr_awlen_reg_1_or_2_i_2_n_0
);
curr_awlen_reg_1_or_2_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00000100"
)
port map (
I0 => axi_awlen_pipe(4),
I1 => axi_awlen_pipe(7),
I2 => axi_awlen_pipe(6),
I3 => axi_awaddr_full,
I4 => axi_awlen_pipe(5),
O => curr_awlen_reg_1_or_2_i_3_n_0
);
curr_awlen_reg_1_or_2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_awlen_reg_1_or_20,
Q => curr_awlen_reg_1_or_2,
R => SR(0)
);
curr_fixed_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_19,
Q => curr_fixed_burst_reg,
R => '0'
);
curr_wrap_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_20,
Q => curr_wrap_burst_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi : entity is "full_axi";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi is
signal I_WR_CHNL_n_36 : STD_LOGIC;
signal axi_aresetn_d2 : STD_LOGIC;
signal axi_aresetn_re_reg : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
begin
bram_rst_a <= \^bram_rst_a\;
I_RD_CHNL: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl
port map (
\GEN_AWREADY.axi_aresetn_d2_reg\ => I_WR_CHNL_n_36,
Q(9 downto 0) => bram_addr_b(9 downto 0),
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_addr_b(0) => bram_addr_b(10),
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(10 downto 0) => s_axi_araddr(10 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
I_WR_CHNL: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl
port map (
\GEN_AW_DUAL.aw_active_reg_0\ => I_WR_CHNL_n_36,
SR(0) => \^bram_rst_a\,
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_addr_a(10 downto 0) => bram_addr_a(10 downto 0),
bram_en_a => bram_en_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr(10 downto 0) => s_axi_awaddr(10 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top : entity is "axi_bram_ctrl_top";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top is
begin
\GEN_AXI4.I_FULL_AXI\: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi
port map (
bram_addr_a(10 downto 0) => bram_addr_a(10 downto 0),
bram_addr_b(10 downto 0) => bram_addr_b(10 downto 0),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(10 downto 0) => s_axi_araddr(10 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(10 downto 0) => s_axi_awaddr(10 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ecc_interrupt : out STD_LOGIC;
ecc_ue : out STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_ctrl_awvalid : in STD_LOGIC;
s_axi_ctrl_awready : out STD_LOGIC;
s_axi_ctrl_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wvalid : in STD_LOGIC;
s_axi_ctrl_wready : out STD_LOGIC;
s_axi_ctrl_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_bvalid : out STD_LOGIC;
s_axi_ctrl_bready : in STD_LOGIC;
s_axi_ctrl_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_arvalid : in STD_LOGIC;
s_axi_ctrl_arready : out STD_LOGIC;
s_axi_ctrl_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_rvalid : out STD_LOGIC;
s_axi_ctrl_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 12 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 12 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 11;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 2048;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 13;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 12;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "axi_bram_ctrl";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "yes";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl is
signal \<const0>\ : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 12 downto 2 );
signal \^bram_addr_b\ : STD_LOGIC_VECTOR ( 12 downto 2 );
signal \^bram_rst_a\ : STD_LOGIC;
signal \^s_axi_aclk\ : STD_LOGIC;
begin
\^s_axi_aclk\ <= s_axi_aclk;
bram_addr_a(12 downto 2) <= \^bram_addr_a\(12 downto 2);
bram_addr_a(1) <= \<const0>\;
bram_addr_a(0) <= \<const0>\;
bram_addr_b(12 downto 2) <= \^bram_addr_b\(12 downto 2);
bram_addr_b(1) <= \<const0>\;
bram_addr_b(0) <= \<const0>\;
bram_clk_a <= \^s_axi_aclk\;
bram_clk_b <= \^s_axi_aclk\;
bram_rst_a <= \^bram_rst_a\;
bram_rst_b <= \^bram_rst_a\;
bram_we_b(3) <= \<const0>\;
bram_we_b(2) <= \<const0>\;
bram_we_b(1) <= \<const0>\;
bram_we_b(0) <= \<const0>\;
bram_wrdata_b(31) <= \<const0>\;
bram_wrdata_b(30) <= \<const0>\;
bram_wrdata_b(29) <= \<const0>\;
bram_wrdata_b(28) <= \<const0>\;
bram_wrdata_b(27) <= \<const0>\;
bram_wrdata_b(26) <= \<const0>\;
bram_wrdata_b(25) <= \<const0>\;
bram_wrdata_b(24) <= \<const0>\;
bram_wrdata_b(23) <= \<const0>\;
bram_wrdata_b(22) <= \<const0>\;
bram_wrdata_b(21) <= \<const0>\;
bram_wrdata_b(20) <= \<const0>\;
bram_wrdata_b(19) <= \<const0>\;
bram_wrdata_b(18) <= \<const0>\;
bram_wrdata_b(17) <= \<const0>\;
bram_wrdata_b(16) <= \<const0>\;
bram_wrdata_b(15) <= \<const0>\;
bram_wrdata_b(14) <= \<const0>\;
bram_wrdata_b(13) <= \<const0>\;
bram_wrdata_b(12) <= \<const0>\;
bram_wrdata_b(11) <= \<const0>\;
bram_wrdata_b(10) <= \<const0>\;
bram_wrdata_b(9) <= \<const0>\;
bram_wrdata_b(8) <= \<const0>\;
bram_wrdata_b(7) <= \<const0>\;
bram_wrdata_b(6) <= \<const0>\;
bram_wrdata_b(5) <= \<const0>\;
bram_wrdata_b(4) <= \<const0>\;
bram_wrdata_b(3) <= \<const0>\;
bram_wrdata_b(2) <= \<const0>\;
bram_wrdata_b(1) <= \<const0>\;
bram_wrdata_b(0) <= \<const0>\;
ecc_interrupt <= \<const0>\;
ecc_ue <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_ctrl_arready <= \<const0>\;
s_axi_ctrl_awready <= \<const0>\;
s_axi_ctrl_bresp(1) <= \<const0>\;
s_axi_ctrl_bresp(0) <= \<const0>\;
s_axi_ctrl_bvalid <= \<const0>\;
s_axi_ctrl_rdata(31) <= \<const0>\;
s_axi_ctrl_rdata(30) <= \<const0>\;
s_axi_ctrl_rdata(29) <= \<const0>\;
s_axi_ctrl_rdata(28) <= \<const0>\;
s_axi_ctrl_rdata(27) <= \<const0>\;
s_axi_ctrl_rdata(26) <= \<const0>\;
s_axi_ctrl_rdata(25) <= \<const0>\;
s_axi_ctrl_rdata(24) <= \<const0>\;
s_axi_ctrl_rdata(23) <= \<const0>\;
s_axi_ctrl_rdata(22) <= \<const0>\;
s_axi_ctrl_rdata(21) <= \<const0>\;
s_axi_ctrl_rdata(20) <= \<const0>\;
s_axi_ctrl_rdata(19) <= \<const0>\;
s_axi_ctrl_rdata(18) <= \<const0>\;
s_axi_ctrl_rdata(17) <= \<const0>\;
s_axi_ctrl_rdata(16) <= \<const0>\;
s_axi_ctrl_rdata(15) <= \<const0>\;
s_axi_ctrl_rdata(14) <= \<const0>\;
s_axi_ctrl_rdata(13) <= \<const0>\;
s_axi_ctrl_rdata(12) <= \<const0>\;
s_axi_ctrl_rdata(11) <= \<const0>\;
s_axi_ctrl_rdata(10) <= \<const0>\;
s_axi_ctrl_rdata(9) <= \<const0>\;
s_axi_ctrl_rdata(8) <= \<const0>\;
s_axi_ctrl_rdata(7) <= \<const0>\;
s_axi_ctrl_rdata(6) <= \<const0>\;
s_axi_ctrl_rdata(5) <= \<const0>\;
s_axi_ctrl_rdata(4) <= \<const0>\;
s_axi_ctrl_rdata(3) <= \<const0>\;
s_axi_ctrl_rdata(2) <= \<const0>\;
s_axi_ctrl_rdata(1) <= \<const0>\;
s_axi_ctrl_rdata(0) <= \<const0>\;
s_axi_ctrl_rresp(1) <= \<const0>\;
s_axi_ctrl_rresp(0) <= \<const0>\;
s_axi_ctrl_rvalid <= \<const0>\;
s_axi_ctrl_wready <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gext_inst.abcv4_0_ext_inst\: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top
port map (
bram_addr_a(10 downto 0) => \^bram_addr_a\(12 downto 2),
bram_addr_b(10 downto 0) => \^bram_addr_b\(12 downto 2),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => \^s_axi_aclk\,
s_axi_araddr(10 downto 0) => s_axi_araddr(12 downto 2),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(10 downto 0) => s_axi_awaddr(12 downto 2),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 12 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 12 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zqynq_lab_1_design_axi_bram_ctrl_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_axi_bram_ctrl_0_0 : entity is "zqynq_lab_1_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_bram_ctrl_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of zqynq_lab_1_design_axi_bram_ctrl_0_0 : entity is "axi_bram_ctrl,Vivado 2017.2.1";
end zqynq_lab_1_design_axi_bram_ctrl_0_0;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0 is
signal NLW_U0_ecc_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_ecc_ue_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ctrl_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_ctrl_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of U0 : label is 11;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of U0 : label is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of U0 : label is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of U0 : label is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of U0 : label is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of U0 : label is 2048;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 13;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of U0 : label is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of U0 : label is 12;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of U0 : label is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of U0 : label is 0;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl
port map (
bram_addr_a(12 downto 0) => bram_addr_a(12 downto 0),
bram_addr_b(12 downto 0) => bram_addr_b(12 downto 0),
bram_clk_a => bram_clk_a,
bram_clk_b => bram_clk_b,
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_a(31 downto 0) => bram_rddata_a(31 downto 0),
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_rst_b => bram_rst_b,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_we_b(3 downto 0) => bram_we_b(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
bram_wrdata_b(31 downto 0) => bram_wrdata_b(31 downto 0),
ecc_interrupt => NLW_U0_ecc_interrupt_UNCONNECTED,
ecc_ue => NLW_U0_ecc_ue_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(12 downto 0) => s_axi_araddr(12 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock => s_axi_arlock,
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(12 downto 0) => s_axi_awaddr(12 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock => s_axi_awlock,
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_ctrl_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_arready => NLW_U0_s_axi_ctrl_arready_UNCONNECTED,
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_awready => NLW_U0_s_axi_ctrl_awready_UNCONNECTED,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_bresp(1 downto 0) => NLW_U0_s_axi_ctrl_bresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_bvalid => NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED,
s_axi_ctrl_rdata(31 downto 0) => NLW_U0_s_axi_ctrl_rdata_UNCONNECTED(31 downto 0),
s_axi_ctrl_rready => '0',
s_axi_ctrl_rresp(1 downto 0) => NLW_U0_s_axi_ctrl_rresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_rvalid => NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED,
s_axi_ctrl_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_wready => NLW_U0_s_axi_ctrl_wready_UNCONNECTED,
s_axi_ctrl_wvalid => '0',
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | b25721177af93151486c82734a3df793 | 0.545731 | 2.559338 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/leon3/leon3.vhd | 1 | 36,542 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: leon3
-- File: leon3.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: LEON3 types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package leon3 is
constant LEON3_VERSION : integer := 3;
type l3_irq_in_type is record
irl : std_logic_vector(3 downto 0);
rst : std_ulogic;
run : std_ulogic;
rstvec : std_logic_vector(31 downto 12);
iact : std_ulogic;
index : std_logic_vector(3 downto 0);
hrdrst : std_ulogic;
end record;
type l3_irq_out_type is record
intack : std_ulogic;
irl : std_logic_vector(3 downto 0);
pwd : std_ulogic;
fpen : std_ulogic;
idle : std_ulogic;
end record;
type l3_debug_in_type is record
dsuen : std_ulogic; -- DSU enable
denable : std_ulogic; -- diagnostic register access enable
dbreak : std_ulogic; -- debug break-in
step : std_ulogic; -- single step
halt : std_ulogic; -- halt processor
reset : std_ulogic; -- reset processor
dwrite : std_ulogic; -- read/write
daddr : std_logic_vector(23 downto 2); -- diagnostic address
ddata : std_logic_vector(31 downto 0); -- diagnostic data
btrapa : std_ulogic; -- break on IU trap
btrape : std_ulogic; -- break on IU trap
berror : std_ulogic; -- break on IU error mode
bwatch : std_ulogic; -- break on IU watchpoint
bsoft : std_ulogic; -- break on software breakpoint (TA 1)
tenable : std_ulogic;
timer : std_logic_vector(30 downto 0); --
end record;
constant dbgi_none : l3_debug_in_type := ('0', '0', '0', '0', '0',
'0', '0', (others => '0'), (others => '0'), '0', '0', '0', '0', '0', '0', (others => '0'));
constant l3_dbgi_none : l3_debug_in_type := dbgi_none;
type l3_cstat_type is record
cmiss : std_ulogic; -- cache miss
tmiss : std_ulogic; -- TLB miss
chold : std_ulogic; -- cache hold
mhold : std_ulogic; -- cache mmu hold
end record;
constant cstat_none : l3_cstat_type := ('0', '0', '0', '0');
type l3_debug_out_type is record
data : std_logic_vector(31 downto 0);
crdy : std_ulogic;
dsu : std_ulogic;
dsumode : std_ulogic;
error : std_ulogic;
halt : std_ulogic;
pwd : std_ulogic;
idle : std_ulogic;
ipend : std_ulogic;
icnt : std_ulogic;
fcnt : std_ulogic;
optype : std_logic_vector(5 downto 0); -- instruction type
bpmiss : std_ulogic; -- branch predict miss
istat : l3_cstat_type;
dstat : l3_cstat_type;
wbhold : std_ulogic; -- write buffer hold
su : std_ulogic; -- supervisor state
end record;
type l3_debug_in_vector is array (natural range <>) of l3_debug_in_type;
type l3_debug_out_vector is array (natural range <>) of l3_debug_out_type;
constant dbgo_none : l3_debug_out_type := (X"00000000", '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', "000000", '0', cstat_none, cstat_none, '0', '0');
constant l3_dbgo_none : l3_debug_out_type := dbgo_none;
type tracebuf_in_type is record
addr : std_logic_vector(11 downto 0);
data : std_logic_vector(127 downto 0);
enable : std_logic;
write : std_logic_vector(3 downto 0);
diag : std_logic_vector(3 downto 0);
end record;
type tracebuf_out_type is record
data : std_logic_vector(127 downto 0);
end record;
component tbufmem
generic ( tech : integer := 0; tbuf : integer := 0; testen: integer := 0);
port (
clk : in std_ulogic;
di : in tracebuf_in_type;
do : out tracebuf_out_type);
end component;
component leon3s
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type
);
end component;
component leon3cg
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic
);
end component;
component leon3ft
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0; -- cacheability table
netlist : integer := 0; -- use netlist
scantest : integer := 0; -- enable scan test support
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic
);
end component;
type grfpu_in_type is record
start : std_logic;
nonstd : std_logic;
flop : std_logic_vector(8 downto 0);
op1 : std_logic_vector(63 downto 0);
op2 : std_logic_vector(63 downto 0);
opid : std_logic_vector(7 downto 0);
flush : std_logic;
flushid : std_logic_vector(5 downto 0);
rndmode : std_logic_vector(1 downto 0);
req : std_logic_vector(2 downto 0);
end record;
constant grfpu_in_none : grfpu_in_type :=
('0', '0', (others => '0'), (others => '0'), (others => '0'),
(others => '0'), '0', (others => '0'), (others => '0'),
(others => '0'));
type grfpu_out_type is record
res : std_logic_vector(63 downto 0);
exc : std_logic_vector(5 downto 0);
allow : std_logic_vector(2 downto 0);
rdy : std_logic;
cc : std_logic_vector(1 downto 0);
idout : std_logic_vector(7 downto 0);
end record;
constant grfpu_out_none : grfpu_out_type :=
((others => '0'), (others => '0'), (others => '0'),
'0', (others => '0'), (others => '0'));
type grfpu_out_vector_type is array (integer range 0 to 7) of grfpu_out_type;
type grfpu_in_vector_type is array (integer range 0 to 7) of grfpu_in_type;
component grfpushwx
generic (mul : integer := 0;
nshare : integer range 0 to 8 := 0;
tech : integer;
arb : integer range 0 to 2 := 1);
port(
clk : in std_logic;
reset : in std_logic;
fpvi : in grfpu_in_vector_type;
fpvo : out grfpu_out_vector_type
);
end component;
component leon3sh
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
component leon3s2x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
clk2x : integer := 1;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
gclk2 : in std_ulogic;
clk2 : in std_ulogic; -- snoop clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
clken : in std_ulogic
);
end component;
component leon3ft2x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
clk2x : integer := 1;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
clken : in std_ulogic
);
end component;
type dsu_in_type is record
enable : std_ulogic;
break : std_ulogic;
end record;
type dsu_out_type is record
active : std_ulogic;
tstop : std_ulogic;
pwd : std_logic_vector(15 downto 0);
end record;
component dsu3
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end component;
component dsu3_2x
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
end component;
component dsu3x
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
clk2x : integer range 0 to 1 := 0;
testen : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
end component;
component dsu3_mb
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end component;
type irq_in_vector is array (Natural range <> ) of l3_irq_in_type;
type irq_out_vector is array (Natural range <> ) of l3_irq_out_type;
component irqmp
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1)
);
end component;
component irqmp2x
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
clkfact : integer := 2
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1);
hclken : in std_ulogic
);
end component;
component irqamp
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
nctrl : integer range 1 to 16 := 1;
tstamp : integer range 0 to 16 := 0;
wdogen : integer range 0 to 1 := 0;
nwdog : integer range 1 to 16 := 1;
dynrstaddr : integer range 0 to 1 := 0;
rstaddr : integer range 0 to 16#fffff# := 0;
extrun : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1);
wdog : in std_logic_vector(nwdog-1 downto 0) := (others => '0');
cpurun : in std_logic_vector(ncpu-1 downto 0) := (others => '0')
);
end component;
component irqamp2x
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
nctrl : integer range 1 to 16 := 1;
tstamp : integer range 0 to 16 := 0;
wdogen : integer range 0 to 1 := 0;
nwdog : integer range 1 to 16 := 1;
dynrstaddr : integer range 0 to 1 := 0;
rstaddr : integer range 0 to 16#fffff# := 0;
extrun : integer range 0 to 1 := 0;
clkfact : integer := 2
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1);
wdog : in std_logic_vector(nwdog-1 downto 0) := (others => '0');
cpurun : in std_logic_vector(ncpu-1 downto 0) := (others => '0');
hclken : in std_ulogic
);
end component;
component leon3ftsh
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic; -- free-running clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic; -- gated clock
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
component leon3x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
clk2x : integer := 1;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
clken : in std_ulogic
);
end component;
-- disassembly dummy module
component cpu_disasx
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result : in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
disas : in std_ulogic);
end component;
end;
| gpl-2.0 | 9b7a5d09fe0dea951478a464b9996abd | 0.525915 | 3.432141 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/leon3v3/leon3cg.vhd | 1 | 6,623 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon3cg
-- File: leon3cg.vhd
-- Author: Jan Andersson, Aeroflex Gaisler
-- Description: Top-level LEON3 component with clock gating
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
entity leon3cg is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic; -- AHB clock (free-running)
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic -- gated clock
);
end;
architecture rtl of leon3cg is
signal gnd, vcc : std_logic;
signal fpuo : grfpu_out_type;
begin
gnd <= '0'; vcc <= '1';
fpuo <= grfpu_out_none;
leon3x0 : leon3x
generic map (
hindex => hindex,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu,
v8 => v8,
cp => cp,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => smp,
iuft => 0,
fpft => 0,
cmft => 0,
iuinj => 0,
ceinj => 0,
cached => cached,
clk2x => 0,
netlist => 0,
scantest => scantest,
mmupgsz => mmupgsz,
bp => bp)
port map (
clk => gnd,
gclk2 => gclk,
gfclk2 => clk,
clk2 => clk,
rstn => rstn,
ahbi => ahbi,
ahbo => ahbo,
ahbsi => ahbsi,
ahbso => ahbso,
irqi => irqi,
irqo => irqo,
dbgi => dbgi,
dbgo => dbgo,
fpui => open,
fpuo => fpuo,
clken => vcc);
end;
| gpl-2.0 | 69571b9e1cd647cc543863c1edae198a | 0.470482 | 3.984958 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/6d8f288943408fbb/zqynq_lab_1_design_rst_ps7_0_100M_0_sim_netlist.vhdl | 1 | 32,640 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:09:13 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_rst_ps7_0_100M_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_rst_ps7_0_100M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
aux_reset_in : in STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 : entity is "cdc_sync";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mb_debug_sys_rst,
I1 => ext_reset_in,
O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute box_type : string;
attribute box_type of POR_SRL_I : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => Q,
I1 => lpf_asr,
I2 => dcm_locked,
I3 => lpf_exr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
port (
Core : out STD_LOGIC;
bsr : out STD_LOGIC;
pr : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
signal \^core\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^bsr\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^pr\ : STD_LOGIC;
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Core <= \^core\;
bsr <= \^bsr\;
pr <= \^pr\;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^core\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^core\,
S => lpf_int
);
SEQ_COUNTER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^core\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
signal Core : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal bsr : STD_LOGIC;
signal lpf_int : STD_LOGIC;
signal pr : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \BSR_OUT_DFF[0].bus_struct_reset_reg[0]\ : label is "no";
attribute equivalent_register_removal of \PR_OUT_DFF[0].peripheral_reset_reg[0]\ : label is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
\PR_OUT_DFF[0].peripheral_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ => SEQ_n_4,
Core => Core,
bsr => bsr,
lpf_int => lpf_int,
pr => pr,
slowest_sync_clk => slowest_sync_clk
);
mb_reset_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core,
Q => mb_reset,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_rst_ps7_0_100M_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "proc_sys_reset,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
| mit | 0e5b557646125d3ca220db75f43ca489 | 0.577543 | 2.876024 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ml510/svga2ch7301c.vhd | 3 | 10,192 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "10.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll1: label is CLKIN_PERIOD_ST;
attribute CLKIN_PERIOD of dll2: label is CLKIN_PERIOD_ST;
signal clk_l, clk_m, clk_n, clk_o : std_logic;
signal dll0lock, dll1lock, dll2lock : std_logic;
signal dllrst : std_ulogic;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk_fb)
begin -- process
if rising_edge(vgaclk_fb) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
-- Clock selection
bufg00 : BUFG port map (I => lvgaclk, O => vgaclk);
lvgaclk <= clk25_fb when clksel(1) = '0' else lclk40_65;
lclk40_65 <= lclk40 when clksel(0) = '0' else lclk65;
bufg01 : BUFG port map (I => clk40_fb, O => lclk40);
bufg02 : BUFG port map (I => clk65_fb, O => lclk65);
dllrst <= not rstn;
-- Generate clocks
clkdiv : process(clk_m, rstn)
begin
if (rstn and dll1lock) = '0' then clkval <= "00";
elsif rising_edge(clk_m) then
clkval <= clkval + 1;
end if;
end process;
clk25 <= clkval(1);
dll0lock <= '1';
bufg03 : BUFG port map (I => clk_l, O => clk_m);
dll1 : DCM
generic map (CLKFX_MULTIPLY => 4, CLKFX_DIVIDE => 10,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_m, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_l,
CLKFX => clk40, LOCKED => dll1lock);
bufg04 : BUFG port map (I => clk_n, O => clk_o);
dll2 : DCM
generic map (CLKFX_MULTIPLY => 13, CLKFX_DIVIDE => 20,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_o, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_n,
CLKFX => clk65, LOCKED => dll2lock);
locked <= dll0lock and dll1lock and dll2lock;
end rtl;
| gpl-2.0 | 7852984813aa889758aca852ef672fa6 | 0.554454 | 3.56613 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/toutpad_ds.vhd | 1 | 4,519 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: toutpad_ds
-- File: toutpad_ds.vhd
-- Author: Jonas Ekergarn - Aeroflex Gaisler
-- Description: tri-state differential output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity toutpad_ds is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end;
architecture rtl of toutpad_ds is
signal oen : std_ulogic;
signal padx, gnd : std_ulogic;
begin
gnd <= '0';
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_ds_pads(tech) = 0 or (is_unisim(tech) = 1) or
tech = axcel or tech = axdsp or tech = rhlib18t or
tech = ut25 or tech = ut130
generate
padp <= i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(en)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
padn <= not i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(en)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
end generate;
pa3 : if (tech = apa3) generate
u0 : apa3_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
fus : if (tech = actfus) generate
u0 : fusion_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpad_dsv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic);
end;
architecture rtl of toutpad_dsv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpad_dsvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0));
end;
architecture rtl of toutpad_dsvv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en(j));
end generate;
end;
| gpl-2.0 | af1913152511ec259d4f9c7518050624 | 0.627351 | 3.497678 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/1_unroll_kernel_traversal/syn/vhdl/convolve_kernel_fbkb.vhd | 2 | 3,080 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fbkb is
generic (
ID : integer := 1;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fbkb is
--------------------- Component ---------------------
component convolve_kernel_ap_fadd_3_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fadd_3_full_dsp_32_u : component convolve_kernel_ap_fadd_3_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| mit | bd7592e43f40c7fcb59eb09217ae27ab | 0.480844 | 3.671037 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-avnet-eval-xc4vlx60/leon3mp.vhd | 1 | 27,300 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.avnet_eval.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
ddrfreq : integer := 100000 -- frequency of ddr clock in kHz
);
port (
resetn : in std_ulogic;
resoutn : out std_logic;
clk_100mhz : in std_ulogic;
clk_50mhz : in std_ulogic;
clk_200p : in std_ulogic;
clk_200n : in std_ulogic;
errorn : out std_ulogic;
-- prom interface
address : out std_logic_vector(21 downto 0);
data : inout std_logic_vector(15 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
romrstn : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
testdata : inout std_logic_vector(15 downto 0);
-- pragma translate_on
-- ddr memory
ddr_clk0 : out std_logic;
ddr_clk0b : out std_logic;
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke0 : out std_logic;
ddr_cs0b : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
-- UART for serial DCL/console I/O
serrx : in std_ulogic;
sertx : out std_ulogic;
rtsn : out std_ulogic;
ctsn : in std_ulogic;
led_rx : out std_ulogic;
led_tx : out std_ulogic;
-- ethernet signals
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
erstn : out std_ulogic;
-- OLED display signals
disp_dcn : out std_ulogic;
disp_csn : out std_ulogic;
disp_rdn : out std_ulogic;
disp_wrn : out std_ulogic;
disp_d : inout std_logic_vector(7 downto 0);
phy_done : out std_ulogic;
rst_done : out std_ulogic
);
end;
architecture rtl of leon3mp is
component mig_36_1
port(
cntrl0_ddr_dq : inout std_logic_vector(15 downto 0);
cntrl0_ddr_a : out std_logic_vector(12 downto 0);
cntrl0_ddr_ba : out std_logic_vector(1 downto 0);
cntrl0_ddr_cke : out std_logic;
cntrl0_ddr_cs_n : out std_logic;
cntrl0_ddr_ras_n : out std_logic;
cntrl0_ddr_cas_n : out std_logic;
cntrl0_ddr_we_n : out std_logic;
cntrl0_ddr_dm : out std_logic_vector(1 downto 0);
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk200_p : in std_logic;
clk200_n : in std_logic;
init_done : out std_logic;
sys_reset_in_n : in std_logic;
cntrl0_clk_tb : out std_logic;
cntrl0_reset_tb : out std_logic;
cntrl0_wdf_almost_full : out std_logic;
cntrl0_af_almost_full : out std_logic;
cntrl0_read_data_valid : out std_logic;
cntrl0_app_wdf_wren : in std_logic;
cntrl0_app_af_wren : in std_logic;
cntrl0_burst_length_div2 : out std_logic_vector(2 downto 0);
cntrl0_app_af_addr : in std_logic_vector(35 downto 0);
cntrl0_app_wdf_data : in std_logic_vector(31 downto 0);
cntrl0_read_data_fifo_out : out std_logic_vector(31 downto 0);
cntrl0_app_mask_data : in std_logic_vector(3 downto 0);
cntrl0_ddr_dqs : inout std_logic_vector(1 downto 0);
cntrl0_ddr_ck : out std_logic_vector(0 downto 0);
cntrl0_ddr_ck_n : out std_logic_vector(0 downto 0)
);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal lclk : std_ulogic;
signal ddrclk, ddrrst, ddrclkfb : std_ulogic;
signal clkm, rstn, clkml, clk2x : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal tck, tms, tdi, tdo : std_ulogic;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
-- signal dsubre : std_logic;
signal duart, ldsuen : std_logic;
signal rsertx, rserrx, rdsuen : std_logic;
signal rstraw : std_logic;
signal rstneg : std_logic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal lock : std_logic;
signal lclk50 : std_logic;
signal rst0_tb, rst0_tbn, clk0_tb : std_logic;
signal migi : mig_app_in_type;
signal migo : mig_app_out_type;
signal init_done : std_ulogic;
signal migrst : std_ulogic;
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector(13 downto 0); -- ddr address
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
romrstn <= rstn;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstneg;
rstneg <= not resetn;
rst0 : rstgen port map (rstneg, clkm, lock, rstn, rstraw);
clk50_pad : clkpad generic map (tech => padtech) port map (clk_50mhz, lclk50);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, 0, 1, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk50, gnd(0), clkm, open, open, open, open, cgi, cgo);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, 0, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
sh : if CFG_GRFPUSH = 1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, 0, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0,
paddr => 0, srbanks => 1, ramaddr => 16#600#, rammask => 16#F00#, ram16 => 1 )
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none; ahbso(5) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (width => 22, tech => padtech)
port map (address, memo.address(22 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
tbdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (testdata(15-i*8 downto 8-i*8), memo.data(15-i*8 downto 8-i*8),
memo.bdrive(i+2), memi.data(15-i*8 downto 8-i*8));
end generate;
-- pragma translate_on
bdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(15-i*8 downto 8-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- DDR memory controller -------------------------------------------
----------------------------------------------------------------------
ddrsp0 : if (CFG_DDRSP /= 0) generate
clk_pad : clkpad generic map (tech => padtech) port map (clk_100mhz, lclk);
ddrc : ddrspa generic map ( fabtech => virtex4, memtech => memtech,
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => 100, rskew => -95
-- pragma translate_off
* 0 -- disable clock skew during simulation
-- pragma translate_on
, clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000, ddrbits => 16)
port map (
rstneg, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(4),
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_clk0 <= ddr_clk(0); ddr_clk0b <= ddr_clkb(0);
ddr_cke0 <= ddr_cke(0); ddr_cs0b <= ddr_csb(0);
ddr_ad <= ddr_adl(12 downto 0);
end generate;
migsp0 : if (CFG_MIG_DDR2 = 1) generate
ahb2mig0 : entity work.ahb2mig_avnet_eval
generic map ( hindex => 0, haddr => 16#400#, hmask => 16#FE0#,
MHz => 100, Mbyte => 32)
port map (
rst_ahb => rstn, rst_ddr => rst0_tbn, rst_50 => rstneg,
clk_ahb => clkm, clk_ddr => clk0_tb, clk_50 => lclk50,
init_done => init_done, ahbsi => ahbsi, ahbso => ahbso(0), migi => migi, migo => migo);
migv5 : mig_36_1
port map(
cntrl0_ddr_dq => ddr_dq,
cntrl0_ddr_a => ddr_ad(12 downto 0),
cntrl0_ddr_ba => ddr_ba,
cntrl0_ddr_cke => ddr_cke0,
cntrl0_ddr_cs_n => ddr_cs0b,
cntrl0_ddr_ras_n => ddr_rasb,
cntrl0_ddr_cas_n => ddr_casb,
cntrl0_ddr_we_n => ddr_web,
cntrl0_ddr_dm => ddr_dm,
sys_clk_p => clk_100mhz, clk200_p => clk_200p,
sys_clk_n => clk_100mhz, clk200_n => clk_200n,
init_done => init_done,
sys_reset_in_n => migi.mig_rst,
cntrl0_reset_tb => rst0_tb, cntrl0_clk_tb => clk0_tb,
cntrl0_wdf_almost_full => migo.app_wdf_afull,
cntrl0_af_almost_full => migo.app_af_afull,
cntrl0_read_data_valid => migo.app_rd_data_valid,
cntrl0_app_wdf_wren => migi.app_wdf_wren,
cntrl0_app_af_wren => migi.app_en,
cntrl0_app_af_addr => migi.app_addr,
cntrl0_app_wdf_data => migi.app_wdf_data,
cntrl0_read_data_fifo_out => migo.app_rd_data,
cntrl0_app_mask_data => migi.app_wdf_mask,
cntrl0_ddr_dqs => ddr_dqs,
cntrl0_ddr_ck => ddr_clk(0 downto 0),
cntrl0_ddr_ck_n => ddr_clkb(0 downto 0)
);
ddr_clk0 <= ddr_clk(0); ddr_clk0b <= ddr_clkb(0);
rst0_tbn <= not rst0_tb;
-- lock <= cgo.clklock;
lock <= init_done and rst0_tbn;
-- led(7) <= init_done;
end generate;
phy_done <= init_done;
rst_done <= migi.mig_rst;
noddr : if (CFG_DDRSP + CFG_MIG_DDR2) = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
nbits => 12 --CFG_GRGPIO_WIDTH
)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
disp_csn_pad : outpad generic map (tech => padtech)
port map (disp_csn, gpioo.dout(8));
disp_dcn_pad : outpad generic map (tech => padtech)
port map (disp_dcn, gpioo.dout(9));
disp_rdn_pad : outpad generic map (tech => padtech)
port map (disp_rdn, gpioo.dout(10));
disp_wrn_pad : outpad generic map (tech => padtech)
port map (disp_wrn, gpioo.dout(11));
disp_d_pads : for i in 0 to 7 generate
pio_pad : iopad generic map (tech => padtech)
port map (disp_d(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
phyrstadr => 3, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
erstn_pad : outpad generic map (tech => padtech)
port map (erstn, rstn);
end generate;
-----------------------------------------------------------------------
--- AHB DMA ----------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH,
-- pindex => 12, paddr => 12, dbuf => 32)
-- port map (rstn, clkm, apbi, apbo(12), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH));
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 9 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
resoutn <= rstn;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 MP Demonstration design for Avnet Virtex4 Eval board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
-- use switch 1 to multiplex DSU UART and UART1
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, ldsuen);
duart <= rdsuen when CFG_AHB_UART /= 0 else '0';
rxd1 <= txd1 when duart = '1' else rserrx;
rsertx <= duo.txd when duart = '1' else txd1;
dui.rxd <= rserrx when duart = '1' else '1';
led_rx <= not rserrx;
p1 : process(clkm)
begin
if rising_edge(clkm) then
sertx <= rsertx; rserrx <= serrx; rdsuen <= ldsuen;
rtsn <= '0';
led_tx <= not rsertx;
end if;
end process;
end rtl;
| gpl-2.0 | e71d2dde5ad4254bdf41844d50721c79 | 0.540769 | 3.570961 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/ambatest/ahbtbp.vhd | 1 | 37,009 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtbp
-- File: ahbtbp.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: AHB Testbench package
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
package ahbtbp is
type ahbtbm_ctrl_type is record
delay : std_logic_vector(7 downto 0);
dbgl : integer;
reset : std_logic;
use128 : integer;
end record;
type ahbtbm_access_type is record
haddr : std_logic_vector(31 downto 0);
hdata : std_logic_vector(31 downto 0);
hdata128 : std_logic_vector(127 downto 0);
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hprot : std_logic_vector(3 downto 0);
hwrite : std_logic;
ctrl : ahbtbm_ctrl_type;
end record;
type ahbtbm_status_type is record
err : std_logic;
ecount : std_logic_vector(15 downto 0);
eaddr : std_logic_vector(31 downto 0);
edatac : std_logic_vector(31 downto 0);
edatar : std_logic_vector(31 downto 0);
hresp : std_logic_vector(1 downto 0);
end record;
type ahbtbm_access_array_type is array (0 to 1) of ahbtbm_access_type;
type ahbtbm_ctrl_in_type is record
ac : ahbtbm_access_type;
end record;
type ahbtbm_ctrl_out_type is record
rst : std_logic;
clk : std_logic;
update : std_logic;
dvalid : std_logic;
hrdata : std_logic_vector(31 downto 0);
hrdata128 : std_logic_vector(127 downto 0);
status : ahbtbm_status_type;
end record;
type ahbtb_ctrl_type is record
i : ahbtbm_ctrl_in_type;
o : ahbtbm_ctrl_out_type;
end record;
constant ac_idle : ahbtbm_access_type :=
(haddr => x"00000000", hdata => x"00000000",
hdata128 => x"00000000000000000000000000000000",
htrans => "00", hburst =>"000", hsize => "000", hprot => "0000", hwrite => '0',
ctrl => (delay => x"00", dbgl => 100, reset =>'0', use128 => 0));
constant ctrli_idle : ahbtbm_ctrl_in_type :=(ac => ac_idle);
constant ctrlo_nodrive : ahbtbm_ctrl_out_type :=(rst => 'H', clk => 'H',
update => 'H', dvalid => 'H', hrdata => (others => 'H'), hrdata128 => (others => 'H'),
status => (err => 'H', ecount => (others => 'H'), eaddr => (others => 'H'),
edatac => (others => 'H'), edatar => (others => 'H'),
hresp => (others => 'H')));
impure function ptime return string;
-- pragma translate_off
-----------------------------------------------------------------------------
-- AHB testbench Master
-----------------------------------------------------------------------------
component ahbtbm is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := 0;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ctrli : in ahbtbm_ctrl_in_type;
ctrlo : out ahbtbm_ctrl_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end component;
-----------------------------------------------------------------------------
-- AHB testbench Slave
-----------------------------------------------------------------------------
component ahbtbs is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
-----------------------------------------------------------------------------
-- dprint (Debug print)
-----------------------------------------------------------------------------
procedure dprint(
constant doprint : in boolean := true;
constant s : in string);
procedure dprint(
constant s : in string);
-----------------------------------------------------------------------------
-- AMBATB Init
-----------------------------------------------------------------------------
procedure ahbtbminit(
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBATB DONE
-----------------------------------------------------------------------------
procedure ahbtbmdone(
constant stop: in integer;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBATB Idle
-----------------------------------------------------------------------------
procedure ahbtbmidle(
constant sync: in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(31 downto 0); -- Data
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(31 downto 0); -- Data
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(31 downto 0); -- Data
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Start address
constant data : in std_logic_vector(31 downto 0); -- Start data
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(127 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(127 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(63 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(63 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
end ahbtbp;
package body ahbtbp is
impure function ptime return string is
variable s : string(1 to 20);
variable length : integer := tost(NOW / 1 ns)'length;
begin
s(1 to length + 9) :="Time: " & tost(NOW / 1 ns) & "ns ";
return s(1 to length + 9);
end function ptime;
-----------------------------------------------------------------------------
-- dprint (Debug print)
-----------------------------------------------------------------------------
procedure dprint(
constant doprint : in boolean := true;
constant s : in string) is
begin
if doprint = true then
print(s);
end if;
end procedure dprint;
procedure dprint(
constant s : in string) is
begin
print(s);
end procedure dprint;
-----------------------------------------------------------------------------
-- AHBTB init
-----------------------------------------------------------------------------
procedure ahbtbminit(
signal ctrl : inout ahbtb_ctrl_type) is
begin
ctrl.o <= ctrlo_nodrive;
ctrl.i <= ctrli_idle;
--ctrli.ac.hburst <= "000"; ctrli.ac.hsize <= "010";
--ctrli.ac.haddr <= x"00000000"; ctrli.ac.hdata <= x"00000000";
--ctrli.ac.htrans <= "00"; ctrli.ac.hwrite <= '0';
wait until ctrl.o.rst = '1';
print("**********************************************************");
print(" AHBTBM Testbench Init");
print("**********************************************************");
end procedure ahbtbminit;
-----------------------------------------------------------------------------
-- AMBTB DONE
-----------------------------------------------------------------------------
procedure ahbtbmdone(
constant stop: in integer;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
print("**********************************************************");
print(" AHBTBM Testbench Done");
print("**********************************************************");
wait for 100 ns;
assert stop = 0
report "ahbtb testbench done!"
severity FAILURE;
end procedure ahbtbmdone;
-----------------------------------------------------------------------------
-- AMBTB Idle
-----------------------------------------------------------------------------
procedure ahbtbmidle(
constant sync: in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
if sync = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
end if;
end procedure ahbtbmidle;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= "10"; ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "000";
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB write access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type) is
variable vaddr : std_logic_vector(31 downto 0);
variable vdata : std_logic_vector(31 downto 0);
variable vhtrans : std_logic_vector(1 downto 0);
begin
--ctrl.o <= ctrlo_nodrive;
vaddr := address; vdata := data; vhtrans := "10";
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "001";
ctrl.i.ac.hprot <= "1110";
for i in 0 to count - 1 loop
ctrl.i.ac.haddr <= vaddr; ctrl.i.ac.hdata <= vdata;
ctrl.i.ac.htrans <= vhtrans;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
vaddr := vaddr + x"4"; vdata := vdata + 1;
vhtrans := "11";
end loop;
ctrl.i <= ctrli_idle;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= "10"; ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "000";
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB read access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type) is
variable vaddr : std_logic_vector(31 downto 0);
variable vdata : std_logic_vector(31 downto 0);
variable vhtrans : std_logic_vector(1 downto 0);
begin
--ctrl.o <= ctrlo_nodrive;
vaddr := address; vdata := data; vhtrans := "10";
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "001";
ctrl.i.ac.hprot <= "1110";
for i in 0 to count - 1 loop
ctrl.i.ac.haddr <= vaddr; ctrl.i.ac.hdata <= vdata;
ctrl.i.ac.htrans <= vhtrans;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
vaddr := vaddr + x"4"; vdata := vdata + 1;
vhtrans := "11";
end loop;
ctrl.i <= ctrli_idle;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128write;
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128write;
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128read;
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128read;
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64write;
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64write;
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64read;
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64read;
-- pragma translate_on
end ahbtbp;
| gpl-2.0 | a8d5da6e8a301b0c49bb470b557559c1 | 0.52544 | 3.83871 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/impl/verilog/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_3_max_dsp_32/synth/convolve_kernel_ap_fmul_3_max_dsp_32.vhd | 1 | 14,025 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_5;
USE floating_point_v7_1_5.floating_point_v7_1_5;
ENTITY convolve_kernel_ap_fmul_3_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END convolve_kernel_ap_fmul_3_max_dsp_32;
ARCHITECTURE convolve_kernel_ap_fmul_3_max_dsp_32_arch OF convolve_kernel_ap_fmul_3_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_5 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_5,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fmul_3_max_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fmul_3_max_dsp_32,floating_point_v7_1_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fmul_3_max_dsp_32,floating_point_v7_1_5,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_F" &
"MS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0" &
",C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_result_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_RESULT, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_b_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_a_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclken: SIGNAL IS "XIL_INTERFACENAME aclken_intf, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_OPERATION:M_AXIS_RESULT:S_AXIS_C:S_AXIS_B:S_AXIS_A, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, PHASE 0.000";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
BEGIN
U0 : floating_point_v7_1_5
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END convolve_kernel_ap_fmul_3_max_dsp_32_arch;
| mit | 0d94793632ee1ba2b3ac742df8d1669c | 0.661105 | 3.029812 | false | false | false | false |
JimLewis/OSVVM | ScoreboardGenericPkg.vhd | 1 | 78,113 | --
-- File Name: ScoreBoardGenericPkg.vhd
-- Design Unit Name: ScoreBoardGenericPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
--
-- Description:
-- Defines types and methods to implement a FIFO based Scoreboard
-- Defines type ScoreBoardPType
-- Defines methods for putting values the scoreboard
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 12/2006 2006.12 Initial revision
-- 08/2010 2010.08 Added Tailpointer
-- 05/2012 2012.05 Changed FIFO to store pointers to ExpectedType
-- Allows usage of unconstrained arrays
-- 08/2012 2012.08 Added Type and Subprogram Generics
-- 08/2013 2013.08 Generics: to_string replaced write, Match replaced check
-- Added Tags - Experimental
-- Added Array of Scoreboards
-- 09/2013 2013.09 Added file handling, Check Count, Finish Status
-- Find, Flush
-- 06/2015 2015.06 Added Alerts, SetAlertLogID, Revised LocalPush, GetDropCount,
-- Deprecated SetFinish and ReportMode - REPORT_NONE, FileOpen
-- Deallocate, Initialized, Function SetName
-- 11/2016 2016.11 Released as part of OSVVM
-- 05/2017 2017.05 First print Actual then only print Expected if mis-match
-- 04/2018 2018.04 Made Pop Functions Visible. Prep for AlertLogIDType being a type.
-- 01/2020 2020.01 Updated Licenses to Apache
-- 05/2020 2020.05 Updated calls to IncAffirmCount
-- Overloaded Check with functions that return pass/fail (T/F)
-- Added GetFifoCount. Added GetPushCount which is same as GetItemCount
-- 10/2020 2020.10 Added Peek
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2006 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use work.TranscriptPkg.all ;
use work.AlertLogPkg.all ;
use work.NamePkg.all ;
package ScoreboardGenericPkg is
generic (
type ExpectedType ;
type ActualType ;
function Match(Actual : ActualType ; -- defaults
Expected : ExpectedType) return boolean ; -- is "=" ;
function expected_to_string(A : ExpectedType) return string ; -- is to_string ;
function actual_to_string (A : ActualType) return string -- is to_string ;
) ;
-- -- For a VHDL-2002 package, comment out the generics and
-- -- uncomment the following, it replaces a generic instance of the package.
-- -- As a result, you will have multiple copies of the entire package.
-- -- Inconvenient, but ok as it still works the same.
-- subtype ExpectedType is std_logic_vector ;
-- subtype ActualType is std_logic_vector ;
-- alias Match is std_match [ActualType, ExpectedType return boolean] ; -- for std_logic_vector
-- alias expected_to_string is to_hstring [ExpectedType return string]; -- VHDL-2008
-- alias actual_to_string is to_hstring [ActualType return string]; -- VHDL-2008
-- ScoreboardReportType is deprecated
-- Replaced by Affirmations. ERROR is the default. ALL turns on PASSED flag
type ScoreboardReportType is (REPORT_ERROR, REPORT_ALL, REPORT_NONE) ; -- replaced by affirmations
type ScoreBoardPType is protected
------------------------------------------------------------
-- Emulate arrays of scoreboards
procedure SetArrayIndex(L, R : integer) ; -- supports integer indices
procedure SetArrayIndex(R : natural) ; -- indicies 1 to R
impure function GetArrayIndex return integer_vector ;
impure function GetArrayLength return natural ;
------------------------------------------------------------
-- Push items into the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Push (Item : in ExpectedType) ;
-- Simple Tagged Scoreboard
procedure Push (
constant Tag : in string ;
constant Item : in ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Push (
constant Index : in integer ;
constant Item : in ExpectedType
) ;
-- Array of Tagged Scoreboards
procedure Push (
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) ;
-- ------------------------------------------------------------
-- -- Push items into the scoreboard/FIFO
-- -- Function form supports chaining of operations
-- -- In 2013, this caused overloading issues in some simulators, will retest later
--
-- -- Simple Scoreboard, no tag
-- impure function Push (Item : ExpectedType) return ExpectedType ;
--
-- -- Simple Tagged Scoreboard
-- impure function Push (
-- constant Tag : in string ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ;
--
-- -- Array of Scoreboards, no tag
-- impure function Push (
-- constant Index : in integer ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ;
--
-- -- Array of Tagged Scoreboards
-- impure function Push (
-- constant Index : in integer ;
-- constant Tag : in string ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ; -- for chaining of operations
------------------------------------------------------------
-- Check received item with item in the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Check (ActualData : ActualType) ;
-- Simple Tagged Scoreboard
procedure Check (
constant Tag : in string ;
constant ActualData : in ActualType
) ;
-- Array of Scoreboards, no tag
procedure Check (
constant Index : in integer ;
constant ActualData : in ActualType
) ;
-- Array of Tagged Scoreboards
procedure Check (
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) ;
-- Simple Scoreboard, no tag
impure function Check (ActualData : ActualType) return boolean ;
-- Simple Tagged Scoreboard
impure function Check (
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean ;
-- Array of Scoreboards, no tag
impure function Check (
constant Index : in integer ;
constant ActualData : in ActualType
) return boolean ;
-- Array of Tagged Scoreboards
impure function Check (
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Pop (variable Item : out ExpectedType) ;
-- Simple Tagged Scoreboard
procedure Pop (
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Pop (
constant Index : in integer ;
variable Item : out ExpectedType
) ;
-- Array of Tagged Scoreboards
procedure Pop (
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Simple Scoreboard, no tag
impure function Pop return ExpectedType ;
-- Simple Tagged Scoreboard
impure function Pop (
constant Tag : in string
) return ExpectedType ;
-- Array of Scoreboards, no tag
impure function Pop (Index : integer) return ExpectedType ;
-- Array of Tagged Scoreboards
impure function Pop (
constant Index : in integer ;
constant Tag : in string
) return ExpectedType ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Array of Tagged Scoreboards
procedure Peek (
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Peek (
constant Index : in integer ;
variable Item : out ExpectedType
) ;
-- Simple Tagged Scoreboard
procedure Peek (
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Simple Scoreboard, no tag
procedure Peek (variable Item : out ExpectedType) ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Array of Tagged Scoreboards
impure function Peek (
constant Index : in integer ;
constant Tag : in string
) return ExpectedType ;
-- Array of Scoreboards, no tag
impure function Peek (Index : integer) return ExpectedType ;
-- Simple Tagged Scoreboard
impure function Peek (
constant Tag : in string
) return ExpectedType ;
-- Simple Scoreboard, no tag
impure function Peek return ExpectedType ;
------------------------------------------------------------
-- Empty - check to see if scoreboard is empty
impure function Empty return boolean ; -- Simple
impure function Empty (Tag : String) return boolean ; -- Simple, Tagged
impure function Empty (Index : integer) return boolean ; -- Array
impure function Empty (Index : integer; Tag : String) return boolean ; -- Array, Tagged
------------------------------------------------------------
-- SetAlertLogID - associate an AlertLogID with a scoreboard to allow integrated error reporting
procedure SetAlertLogID(Index : Integer ; Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) ;
procedure SetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) ;
-- Use when an AlertLogID is used by multiple items (Model or other Scoreboards). See also AlertLogPkg.GetAlertLogID
procedure SetAlertLogID (Index : Integer ; A : AlertLogIDType) ;
procedure SetAlertLogID (A : AlertLogIDType) ;
impure function GetAlertLogID(Index : Integer) return AlertLogIDType ;
impure function GetAlertLogID return AlertLogIDType ;
------------------------------------------------------------
-- Set a scoreboard name.
-- Used when scoreboard AlertLogID is shared between different sources.
procedure SetName (Name : String) ;
impure function SetName (Name : String) return string ;
impure function GetName (DefaultName : string := "Scoreboard") return string ;
------------------------------------------------------------
-- Scoreboard Introspection
-- Number of items put into scoreboard
impure function GetItemCount return integer ; -- Simple, with or without tags
impure function GetItemCount (Index : integer) return integer ; -- Arrays, with or without tags
impure function GetPushCount return integer ; -- Simple, with or without tags
impure function GetPushCount (Index : integer) return integer ; -- Arrays, with or without tags
-- Number of items removed from scoreboard by pop or check
impure function GetPopCount (Index : integer) return integer ;
impure function GetPopCount return integer ;
-- Number of items currently in the scoreboard (= PushCount - PopCount - DropCount)
impure function GetFifoCount (Index : integer) return integer ;
impure function GetFifoCount return integer ;
-- Number of items checked by scoreboard
impure function GetCheckCount return integer ; -- Simple, with or without tags
impure function GetCheckCount (Index : integer) return integer ; -- Arrays, with or without tags
-- Number of items dropped by scoreboard. See Find/Flush
impure function GetDropCount return integer ; -- Simple, with or without tags
impure function GetDropCount (Index : integer) return integer ; -- Arrays, with or without tags
------------------------------------------------------------
-- Find - Returns the ItemNumber for a value and tag (if applicable) in a scoreboard.
-- Find returns integer'left if no match found
-- Also See Flush. Flush will drop items up through the ItemNumber
-- Simple Scoreboard
impure function Find (
constant ActualData : in ActualType
) return integer ;
-- Tagged Scoreboard
impure function Find (
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
-- Array of Simple Scoreboards
impure function Find (
constant Index : in integer ;
constant ActualData : in ActualType
) return integer ;
-- Array of Tagged Scoreboards
impure function Find (
constant Index : in integer ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
------------------------------------------------------------
-- Flush - Remove elements in the scoreboard upto and including the one with ItemNumber
-- See Find to identify an ItemNumber of a particular value and tag (if applicable)
-- Simple Scoreboard
procedure Flush (
constant ItemNumber : in integer
) ;
-- Tagged Scoreboard - only removes items that also match the tag
procedure Flush (
constant Tag : in string ;
constant ItemNumber : in integer
) ;
-- Array of Simple Scoreboards
procedure Flush (
constant Index : in integer ;
constant ItemNumber : in integer
) ;
-- Array of Tagged Scoreboards - only removes items that also match the tag
procedure Flush (
constant Index : in integer ;
constant Tag : in string ;
constant ItemNumber : in integer
) ;
------------------------------------------------------------
-- Generally these are not required. When a simulation ends and
-- another simulation is started, a simulator will release all allocated items.
procedure Deallocate ; -- Deletes all allocated items
procedure Initialize ; -- Creates initial data structure if it was destroyed with Deallocate
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Use alerts directly instead.
-- AlertIF(SB.GetCheckCount < 10, ....) ;
-- AlertIf(Not SB.Empty, ...) ;
------------------------------------------------------------
-- Set alerts if scoreboard not empty or if CheckCount <
-- Use if need to check empty or CheckCount for a specific scoreboard.
-- Simple Scoreboards, with or without tag
procedure CheckFinish (
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
-- Array of Scoreboards, with or without tag
procedure CheckFinish (
Index : integer ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
------------------------------------------------------------
-- Get error count
-- Deprecated, replaced by usage of Alerts
-- AlertFLow: Instead use AlertLogPkg.ReportAlerts or AlertLogPkg.GetAlertCount
-- Not AlertFlow: use GetErrorCount to get total error count
-- Simple Scoreboards, with or without tag
impure function GetErrorCount return integer ;
-- Array of Scoreboards, with or without tag
impure function GetErrorCount(Index : integer) return integer ;
------------------------------------------------------------
-- Error count manipulation
-- IncErrorCount - not recommended, use alerts instead - may be deprecated in the future
procedure IncErrorCount ; -- Simple, with or without tags
procedure IncErrorCount (Index : integer) ; -- Arrays, with or without tags
-- Clear error counter. Caution does not change AlertCounts, must also use AlertLogPkg.ClearAlerts
procedure SetErrorCountZero ; -- Simple, with or without tags
procedure SetErrorCountZero (Index : integer) ; -- Arrays, with or without tags
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Names changed. Maintained for backward compatibility - would prefer an alias
------------------------------------------------------------
procedure FileOpen (FileName : string; OpenKind : File_Open_Kind ) ; -- Replaced by TranscriptPkg.TranscriptOpen
procedure PutExpectedData (ExpectedData : ExpectedType) ; -- Replaced by push
procedure CheckActualData (ActualData : ActualType) ; -- Replaced by Check
impure function GetItemNumber return integer ; -- Replaced by GetItemCount
procedure SetMessage (MessageIn : String) ; -- Replaced by SetName
impure function GetMessage return string ; -- Replaced by GetName
-- Deprecated and may be deleted in a future revision
procedure SetFinish ( -- Replaced by CheckFinish
Index : integer ;
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) ;
procedure SetFinish ( -- Replaced by CheckFinish
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) ;
------------------------------------------------------------
-- SetReportMode
-- Not AlertFlow
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(PASSED, FALSE)
-- REPORT_NONE: Deprecated, do not use.
-- AlertFlow:
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, FALSE)
-- REPORT_NONE: Replaced by AlertLogPkg.SetAlertEnable(AlertLogID, ERROR, FALSE)
procedure SetReportMode (ReportModeIn : ScoreboardReportType) ;
impure function GetReportMode return ScoreboardReportType ;
end protected ScoreBoardPType ;
end ScoreboardGenericPkg ;
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
package body ScoreboardGenericPkg is
type ScoreBoardPType is protected body
type ExpectedPointerType is access ExpectedType ;
type ListType ;
type ListPointerType is access ListType ;
type ListType is record
ItemNumber : integer ;
TagPtr : line ;
ExpectedPtr : ExpectedPointerType ;
NextPtr : ListPointerType ;
end record ;
type ListArrayType is array (integer range <>) of ListPointerType ;
type ListArrayPointerType is access ListArrayType ;
variable ArrayLengthVar : integer := 1 ;
variable HeadPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
variable TailPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
variable PopListPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
type IntegerArrayType is array (integer range <>) of Integer ;
type IntegerArrayPointerType is access IntegerArrayType ;
type AlertLogIDArrayType is array (integer range <>) of AlertLogIDType ;
type AlertLogIDArrayPointerType is access AlertLogIDArrayType ;
variable ErrCntVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable DropCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable ItemNumberVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable PopCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable CheckCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable AlertLogIDVar : AlertLogIDArrayPointerType := new AlertLogIDArrayType'(1 => OSVVM_SCOREBOARD_ALERTLOG_ID) ;
variable NameVar : NamePType ;
variable ReportModeVar : ScoreboardReportType ;
variable FirstIndexVar : integer := 1 ;
------------------------------------------------------------
procedure SetName (Name : String) is
------------------------------------------------------------
begin
NameVar.Set(Name) ;
end procedure SetName ;
------------------------------------------------------------
impure function SetName (Name : String) return string is
------------------------------------------------------------
begin
NameVar.Set(Name) ;
return Name ;
end function SetName ;
------------------------------------------------------------
impure function GetName (DefaultName : string := "Scoreboard") return string is
------------------------------------------------------------
begin
return NameVar.Get(DefaultName) ;
end function GetName ;
------------------------------------------------------------
procedure SetReportMode (ReportModeIn : ScoreboardReportType) is
------------------------------------------------------------
begin
ReportModeVar := ReportModeIn ;
if ReportModeVar = REPORT_ALL then
Alert(OSVVM_SCOREBOARD_ALERTLOG_ID, "ScoreboardGenericPkg.SetReportMode: To turn off REPORT_ALL, use osvvm.AlertLogPkg.SetLogEnable(PASSED, FALSE)", WARNING) ;
for i in AlertLogIDVar'range loop
SetLogEnable(AlertLogIDVar(i), PASSED, TRUE) ;
end loop ;
end if ;
if ReportModeVar = REPORT_NONE then
Alert(OSVVM_SCOREBOARD_ALERTLOG_ID, "ScoreboardGenericPkg.SetReportMode: ReportMode REPORT_NONE has been deprecated and will be removed in next revision. Please contact OSVVM architect Jim Lewis if you need this capability.", WARNING) ;
end if ;
end procedure SetReportMode ;
------------------------------------------------------------
impure function GetReportMode return ScoreboardReportType is
------------------------------------------------------------
begin
return ReportModeVar ;
end function GetReportMode ;
------------------------------------------------------------
procedure SetArrayIndex(L, R : integer) is
------------------------------------------------------------
variable OldHeadPointer, OldTailPointer, OldPopListPointer : ListArrayPointerType ;
variable OldErrCnt, OldDropCount, OldItemNumber, OldPopCount, OldCheckCount : IntegerArrayPointerType ;
variable OldAlertLogIDVar : AlertLogIDArrayPointerType ;
variable Min, Max, Len, OldLen, OldMax : integer ;
begin
Min := minimum(L, R) ;
Max := maximum(L, R) ;
OldLen := ArrayLengthVar ;
OldMax := Min + ArrayLengthVar - 1 ;
Len := Max - Min + 1 ;
ArrayLengthVar := Len ;
if Len >= OldLen then
FirstIndexVar := Min ;
OldHeadPointer := HeadPointer ;
HeadPointer := new ListArrayType(Min to Max) ;
if OldHeadPointer /= NULL then
HeadPointer(Min to OldMax) := OldHeadPointer.all ; -- (OldHeadPointer'range) ;
Deallocate(OldHeadPointer) ;
end if ;
OldTailPointer := TailPointer ;
TailPointer := new ListArrayType(Min to Max) ;
if OldTailPointer /= NULL then
TailPointer(Min to OldMax) := OldTailPointer.all ;
Deallocate(OldTailPointer) ;
end if ;
OldPopListPointer := PopListPointer ;
PopListPointer := new ListArrayType(Min to Max) ;
if OldPopListPointer /= NULL then
PopListPointer(Min to OldMax) := OldPopListPointer.all ;
Deallocate(OldPopListPointer) ;
end if ;
OldErrCnt := ErrCntVar ;
ErrCntVar := new IntegerArrayType'(Min to Max => 0) ;
if OldErrCnt /= NULL then
ErrCntVar(Min to OldMax) := OldErrCnt.all ;
Deallocate(OldErrCnt) ;
end if ;
OldDropCount := DropCountVar ;
DropCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldDropCount /= NULL then
DropCountVar(Min to OldMax) := OldDropCount.all ;
Deallocate(OldDropCount) ;
end if ;
OldItemNumber := ItemNumberVar ;
ItemNumberVar := new IntegerArrayType'(Min to Max => 0) ;
if OldItemNumber /= NULL then
ItemNumberVar(Min to OldMax) := OldItemNumber.all ;
Deallocate(OldItemNumber) ;
end if ;
OldPopCount := PopCountVar ;
PopCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldPopCount /= NULL then
PopCountVar(Min to OldMax) := OldPopCount.all ;
Deallocate(OldPopCount) ;
end if ;
OldCheckCount := CheckCountVar ;
CheckCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldCheckCount /= NULL then
CheckCountVar(Min to OldMax) := OldCheckCount.all ;
Deallocate(OldCheckCount) ;
end if ;
OldAlertLogIDVar := AlertLogIDVar ;
AlertLogIDVar := new AlertLogIDArrayType'(Min to Max => OSVVM_SCOREBOARD_ALERTLOG_ID) ;
if OldAlertLogIDVar /= NULL then
AlertLogIDVar(Min to OldMax) := OldAlertLogIDVar.all ;
Deallocate(OldAlertLogIDVar) ;
end if ;
elsif Len < OldLen then
report "ScoreboardGenericPkg: SetArrayIndex, new array Length <= current array length"
severity failure ;
end if ;
end procedure SetArrayIndex ;
------------------------------------------------------------
procedure SetArrayIndex(R : natural) is
------------------------------------------------------------
begin
SetArrayIndex(1, R) ;
end procedure SetArrayIndex ;
------------------------------------------------------------
procedure Deallocate is
------------------------------------------------------------
variable CurListPtr, LastListPtr : ListPointerType ;
begin
for Index in HeadPointer'range loop
-- Deallocate contents in the scoreboards
CurListPtr := HeadPointer(Index) ;
while CurListPtr /= Null loop
deallocate(CurListPtr.TagPtr) ;
deallocate(CurListPtr.ExpectedPtr) ;
LastListPtr := CurListPtr ;
CurListPtr := CurListPtr.NextPtr ;
Deallocate(LastListPtr) ;
end loop ;
end loop ;
for Index in PopListPointer'range loop
-- Deallocate PopListPointer - only has single element
CurListPtr := PopListPointer(Index) ;
if CurListPtr /= NULL then
deallocate(CurListPtr.TagPtr) ;
deallocate(CurListPtr.ExpectedPtr) ;
deallocate(CurListPtr) ;
end if ;
end loop ;
-- Deallocate arrays of pointers
Deallocate(HeadPointer) ;
Deallocate(TailPointer) ;
Deallocate(PopListPointer) ;
-- Deallocate supporting arrays
Deallocate(ErrCntVar) ;
Deallocate(DropCountVar) ;
Deallocate(ItemNumberVar) ;
Deallocate(PopCountVar) ;
Deallocate(CheckCountVar) ;
Deallocate(AlertLogIDVar) ;
-- Deallocate NameVar - NamePType
NameVar.Deallocate ;
ArrayLengthVar := 0 ;
end procedure Deallocate ;
------------------------------------------------------------
-- Construct initial data structure
procedure Initialize is
------------------------------------------------------------
begin
SetArrayIndex(1, 1) ;
end procedure Initialize ;
------------------------------------------------------------
impure function GetArrayIndex return integer_vector is
------------------------------------------------------------
begin
return (1 => HeadPointer'left, 2 => HeadPointer'right) ;
end function GetArrayIndex ;
------------------------------------------------------------
impure function GetArrayLength return natural is
------------------------------------------------------------
begin
return ArrayLengthVar ; -- HeadPointer'length ;
end function GetArrayLength ;
------------------------------------------------------------
procedure SetAlertLogID (Index : Integer ; A : AlertLogIDType) is
------------------------------------------------------------
begin
AlertLogIDVar(Index) := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID (A : AlertLogIDType) is
------------------------------------------------------------
begin
AlertLogIDVar(FirstIndexVar) := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Index : Integer ; Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) is
------------------------------------------------------------
begin
AlertLogIDVar(Index) := GetAlertLogID(Name, ParentID, CreateHierarchy) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) is
------------------------------------------------------------
begin
AlertLogIDVar(FirstIndexVar) := GetAlertLogID(Name, ParentID, CreateHierarchy) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID(Index : Integer) return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogIDVar(Index) ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogIDVar(FirstIndexVar) ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function LocalOutOfRange(
------------------------------------------------------------
constant Index : in integer ;
constant Name : in string
) return boolean is
begin
return AlertIf(OSVVM_SCOREBOARD_ALERTLOG_ID, Index < HeadPointer'Low or Index > HeadPointer'High,
GetName & " " & Name & " Index: " & to_string(Index) &
"is not in the range (" & to_string(HeadPointer'Low) &
"to " & to_string(HeadPointer'High) & ")",
FAILURE ) ;
end function LocalOutOfRange ;
------------------------------------------------------------
procedure LocalPush (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
variable ExpectedPtr : ExpectedPointerType ;
variable TagPtr : line ;
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
ItemNumberVar(Index) := ItemNumberVar(Index) + 1 ;
ExpectedPtr := new ExpectedType'(Item) ;
TagPtr := new string'(Tag) ;
if HeadPointer(Index) = NULL then
-- 2015.05: allocation using ListTtype'(...) in a protected type does not work in some simulators
-- HeadPointer(Index) := new ListType'(ItemNumberVar(Index), TagPtr, ExpectedPtr, NULL) ;
HeadPointer(Index) := new ListType ;
HeadPointer(Index).ItemNumber := ItemNumberVar(Index) ;
HeadPointer(Index).TagPtr := TagPtr ;
HeadPointer(Index).ExpectedPtr := ExpectedPtr ;
HeadPointer(Index).NextPtr := NULL ;
TailPointer(Index) := HeadPointer(Index) ;
else
-- 2015.05: allocation using ListTtype'(...) in a protected type does not work in some simulators
-- TailPointer(Index).NextPtr := new ListType'(ItemNumberVar(Index), TagPtr, ExpectedPtr, NULL) ;
TailPointer(Index).NextPtr := new ListType ;
TailPointer(Index).NextPtr.ItemNumber := ItemNumberVar(Index) ;
TailPointer(Index).NextPtr.TagPtr := TagPtr ;
TailPointer(Index).NextPtr.ExpectedPtr := ExpectedPtr ;
TailPointer(Index).NextPtr.NextPtr := NULL ;
TailPointer(Index) := TailPointer(Index).NextPtr ;
end if ;
end procedure LocalPush ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Push (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
variable ExpectedPtr : ExpectedPointerType ;
variable TagPtr : line ;
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Push (
------------------------------------------------------------
constant Index : in integer ;
constant Item : in ExpectedType
) is
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, "", Item) ;
end procedure Push ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Push (
------------------------------------------------------------
constant Tag : in string ;
constant Item : in ExpectedType
) is
begin
LocalPush(FirstIndexVar, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Push (Item : in ExpectedType) is
------------------------------------------------------------
begin
LocalPush(FirstIndexVar, "", Item) ;
end procedure Push ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Push (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Push") then
return Item ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, Tag, Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Push (
------------------------------------------------------------
constant Index : in integer ;
constant Item : in ExpectedType
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Push") then
return Item ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, "", Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Push (
------------------------------------------------------------
constant Tag : in string ;
constant Item : in ExpectedType
) return ExpectedType is
begin
LocalPush(FirstIndexVar, Tag, Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Push (Item : ExpectedType) return ExpectedType is
------------------------------------------------------------
begin
LocalPush(FirstIndexVar, "", Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Local Only
-- Pops highest element matching Tag into PopListPointer(Index)
procedure LocalPop (Index : integer ; Tag : string; Name : string) is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Pop/Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
if HeadPointer(Index) = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Empty during " & Name, FAILURE) ;
return ;
end if ;
PopCountVar(Index) := PopCountVar(Index) + 1 ;
-- deallocate previous pointer
if PopListPointer(Index) /= NULL then
deallocate(PopListPointer(Index).TagPtr) ;
deallocate(PopListPointer(Index).ExpectedPtr) ;
deallocate(PopListPointer(Index)) ;
end if ;
-- Descend to find Tag field and extract
CurPtr := HeadPointer(Index) ;
if CurPtr.TagPtr.all = Tag then
-- Non-tagged scoreboards find this one.
PopListPointer(Index) := HeadPointer(Index) ;
HeadPointer(Index) := HeadPointer(Index).NextPtr ;
else
loop
if CurPtr.NextPtr = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Pop/Check (" & Name & "), tag: " & Tag & " not found", FAILURE) ;
exit ;
elsif CurPtr.NextPtr.TagPtr.all = Tag then
PopListPointer(Index) := CurPtr.NextPtr ;
CurPtr.NextPtr := CurPtr.NextPtr.NextPtr ;
if CurPtr.NextPtr = NULL then
TailPointer(Index) := CurPtr ;
end if ;
exit ;
else
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end if ;
end procedure LocalPop ;
------------------------------------------------------------
-- Local Only
procedure LocalCheck (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType ;
variable FoundError : inout boolean
) is
variable ExpectedPtr : ExpectedPointerType ;
variable CurrentItem : integer ;
variable WriteBuf : line ;
variable PassedFlagEnabled : boolean ;
begin
CheckCountVar(Index) := CheckCountVar(Index) + 1 ;
ExpectedPtr := PopListPointer(Index).ExpectedPtr ;
CurrentItem := PopListPointer(Index).ItemNumber ;
PassedFlagEnabled := GetLogEnable(AlertLogIDVar(Index), PASSED) ;
if not Match(ActualData, ExpectedPtr.all) then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
FoundError := TRUE ;
IncAffirmCount(AlertLogIDVar(Index)) ;
else
FoundError := FALSE ;
if not PassedFlagEnabled then
IncAffirmPassedCount(AlertLogIDVar(Index)) ;
end if ;
end if ;
-- IncAffirmCount(AlertLogIDVar(Index)) ;
-- if FoundError or ReportModeVar = REPORT_ALL then
if FoundError or PassedFlagEnabled then
if AlertLogIDVar(Index) = OSVVM_SCOREBOARD_ALERTLOG_ID then
write(WriteBuf, GetName(DefaultName => "Scoreboard")) ;
else
write(WriteBuf, GetName(DefaultName => "")) ;
end if ;
if ArrayLengthVar > 1 then
write(WriteBuf, " (" & to_string(Index) & ") ") ;
end if ;
write(WriteBuf, " Received: " & actual_to_string(ActualData)) ;
if FoundError then
write(WriteBuf, " Expected: " & expected_to_string(ExpectedPtr.all)) ;
end if ;
if PopListPointer(Index).TagPtr.all /= "" then
write(WriteBuf, " Tag: " & PopListPointer(Index).TagPtr.all) ;
end if;
write(WriteBuf, " Item Number: " & to_string(CurrentItem)) ;
if FoundError then
if ReportModeVar /= REPORT_NONE then
-- Affirmation Failed
Alert(AlertLogIDVar(Index), WriteBuf.all, ERROR) ;
else
-- Affirmation Failed, but silent, unless in DEBUG mode
Log(AlertLogIDVar(Index), "ERROR " & WriteBuf.all, DEBUG) ;
IncAlertCount(AlertLogIDVar(Index)) ; -- Silent Counted Alert
end if ;
else
-- Affirmation passed, PASSED flag increments AffirmCount
Log(AlertLogIDVar(Index), WriteBuf.all, PASSED) ;
end if ;
deallocate(WriteBuf) ;
end if ;
end procedure LocalCheck ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Check (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Check (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Check (
------------------------------------------------------------
constant Tag : in string ;
constant ActualData : in ActualType
) is
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, Tag, "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Check (ActualData : ActualType) is
------------------------------------------------------------
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, "", "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Check (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Function Check") then
return FALSE ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Check (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Function Check") then
return FALSE ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Check (
------------------------------------------------------------
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, Tag, "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Check (ActualData : ActualType) return boolean is
------------------------------------------------------------
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, "", "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Pop (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
if LocalOutOfRange(Index, "Pop") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Pop") ;
Item := PopListPointer(Index).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Pop (
------------------------------------------------------------
constant Index : in integer ;
variable Item : out ExpectedType
) is
begin
if LocalOutOfRange(Index, "Pop") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Pop") ;
Item := PopListPointer(Index).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Pop (
------------------------------------------------------------
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
LocalPop(FirstIndexVar, Tag, "Pop") ;
Item := PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Pop (variable Item : out ExpectedType) is
------------------------------------------------------------
begin
LocalPop(FirstIndexVar, "", "Pop") ;
Item := PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Pop (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Pop") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
LocalPop(Index, Tag, "Pop") ;
return PopListPointer(Index).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Pop (Index : integer) return ExpectedType is
------------------------------------------------------------
begin
if LocalOutOfRange(Index, "Pop") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
LocalPop(Index, "", "Pop") ;
return PopListPointer(Index).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Pop (
------------------------------------------------------------
constant Tag : in string
) return ExpectedType is
begin
LocalPop(FirstIndexVar, Tag, "Pop") ;
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Pop return ExpectedType is
------------------------------------------------------------
begin
LocalPop(FirstIndexVar, "", "Pop") ;
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Local Only similar to LocalPop
-- Returns a pointer to the highest element matching Tag
impure function LocalPeek (Index : integer ; Tag : string) return ListPointerType is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
--!! LocalPeek does this, but so do each of the indexed calls
--!! if LocalOutOfRange(Index, "Peek") then
--!! return NULL ; -- error reporting in LocalOutOfRange
--!! end if ;
if HeadPointer(Index) = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Empty during Peek", FAILURE) ;
return NULL ;
end if ;
-- Descend to find Tag field and extract
CurPtr := HeadPointer(Index) ;
if CurPtr.TagPtr.all = Tag then
-- Non-tagged scoreboards find this one.
return CurPtr ;
else
loop
if CurPtr.NextPtr = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Peek, tag: " & Tag & " not found", FAILURE) ;
return NULL ;
elsif CurPtr.NextPtr.TagPtr.all = Tag then
return CurPtr ;
else
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end if ;
end function LocalPeek ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Peek (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := LocalPeek(Index, Tag) ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Peek (
------------------------------------------------------------
constant Index : in integer ;
variable Item : out ExpectedType
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := LocalPeek(Index, "") ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Peek (
------------------------------------------------------------
constant Tag : in string ;
variable Item : out ExpectedType
) is
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, Tag) ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Peek (variable Item : out ExpectedType) is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, "") ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Peek (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string
) return ExpectedType is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
CurPtr := LocalPeek(Index, Tag) ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Peek (Index : integer) return ExpectedType is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
CurPtr := LocalPeek(Index, "") ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Peek (
------------------------------------------------------------
constant Tag : in string
) return ExpectedType is
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, Tag) ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Peek return ExpectedType is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, "") ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Empty (Index : integer; Tag : String) return boolean is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := HeadPointer(Index) ;
while CurPtr /= NULL loop
if CurPtr.TagPtr.all = Tag then
return FALSE ; -- Found Tag
end if ;
CurPtr := CurPtr.NextPtr ;
end loop ;
return TRUE ; -- Tag not found
end function Empty ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Empty (Index : integer) return boolean is
------------------------------------------------------------
begin
return HeadPointer(Index) = NULL ;
end function Empty ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Empty (Tag : String) return boolean is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
return Empty(FirstIndexVar, Tag) ;
end function Empty ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Empty return boolean is
------------------------------------------------------------
begin
return HeadPointer(FirstIndexVar) = NULL ;
end function Empty ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
Index : integer ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
variable EmptyError : Boolean ;
variable WriteBuf : line ;
begin
if AlertLogIDVar(Index) = OSVVM_SCOREBOARD_ALERTLOG_ID then
write(WriteBuf, GetName(DefaultName => "Scoreboard")) ;
else
write(WriteBuf, GetName(DefaultName => "")) ;
end if ;
if ArrayLengthVar > 1 then
if WriteBuf.all /= "" then
swrite(WriteBuf, " ") ;
end if ;
write(WriteBuf, "Index(" & to_string(Index) & "), ") ;
else
if WriteBuf.all /= "" then
swrite(WriteBuf, ", ") ;
end if ;
end if ;
if FinishEmpty then
AffirmIf(AlertLogIDVar(Index), Empty(Index), WriteBuf.all & "Checking Empty: " & to_string(Empty(Index)) &
" FinishEmpty: " & to_string(FinishEmpty)) ;
if not Empty(Index) then
-- Increment internal count on FinishEmpty Error
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
end if ;
end if ;
AffirmIf(AlertLogIDVar(Index), CheckCountVar(Index) >= FinishCheckCount, WriteBuf.all &
"Checking CheckCount: " & to_string(CheckCountVar(Index)) &
" >= Expected: " & to_string(FinishCheckCount)) ;
if not (CheckCountVar(Index) >= FinishCheckCount) then
-- Increment internal count on FinishCheckCount Error
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
end if ;
deallocate(WriteBuf) ;
end procedure CheckFinish ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
begin
for AlertLogID in AlertLogIDVar'range loop
CheckFinish(AlertLogID, FinishCheckCount, FinishEmpty) ;
end loop ;
end procedure CheckFinish ;
------------------------------------------------------------
impure function GetErrorCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ErrCntVar(Index) ;
end function GetErrorCount ;
------------------------------------------------------------
impure function GetErrorCount return integer is
------------------------------------------------------------
variable TotalErrorCount : integer := 0 ;
begin
for Index in AlertLogIDVar'range loop
TotalErrorCount := TotalErrorCount + GetErrorCount(Index) ;
end loop ;
return TotalErrorCount ;
end function GetErrorCount ;
------------------------------------------------------------
procedure IncErrorCount (Index : integer) is
------------------------------------------------------------
begin
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
IncAlertCount(AlertLogIDVar(Index), ERROR) ;
end IncErrorCount ;
------------------------------------------------------------
procedure IncErrorCount is
------------------------------------------------------------
begin
ErrCntVar(FirstIndexVar) := ErrCntVar(FirstIndexVar) + 1 ;
IncAlertCount(AlertLogIDVar(FirstIndexVar), ERROR) ;
end IncErrorCount ;
------------------------------------------------------------
procedure SetErrorCountZero (Index : integer) is
------------------------------------------------------------
begin
ErrCntVar(Index) := 0;
end procedure SetErrorCountZero ;
------------------------------------------------------------
procedure SetErrorCountZero is
------------------------------------------------------------
begin
ErrCntVar(FirstIndexVar) := 0 ;
end procedure SetErrorCountZero ;
------------------------------------------------------------
impure function GetItemCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) ;
end function GetItemCount ;
------------------------------------------------------------
impure function GetItemCount return integer is
------------------------------------------------------------
begin
return ItemNumberVar(FirstIndexVar) ;
end function GetItemCount ;
------------------------------------------------------------
impure function GetPushCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) ;
end function GetPushCount ;
------------------------------------------------------------
impure function GetPushCount return integer is
------------------------------------------------------------
begin
return ItemNumberVar(FirstIndexVar) ;
end function GetPushCount ;
------------------------------------------------------------
impure function GetPopCount (Index : integer) return integer is
------------------------------------------------------------
begin
return PopCountVar(Index) ;
end function GetPopCount ;
------------------------------------------------------------
impure function GetPopCount return integer is
------------------------------------------------------------
begin
return PopCountVar(FirstIndexVar) ;
end function GetPopCount ;
------------------------------------------------------------
impure function GetFifoCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) - PopCountVar(Index) - DropCountVar(Index) ;
end function GetFifoCount ;
------------------------------------------------------------
impure function GetFifoCount return integer is
------------------------------------------------------------
begin
return GetFifoCount(FirstIndexVar) ;
end function GetFifoCount ;
------------------------------------------------------------
impure function GetCheckCount (Index : integer) return integer is
------------------------------------------------------------
begin
return CheckCountVar(Index) ;
end function GetCheckCount ;
------------------------------------------------------------
impure function GetCheckCount return integer is
------------------------------------------------------------
begin
return CheckCountVar(FirstIndexVar) ;
end function GetCheckCount ;
------------------------------------------------------------
impure function GetDropCount (Index : integer) return integer is
------------------------------------------------------------
begin
return DropCountVar(Index) ;
end function GetDropCount ;
------------------------------------------------------------
impure function GetDropCount return integer is
------------------------------------------------------------
begin
return DropCountVar(FirstIndexVar) ;
end function GetDropCount ;
------------------------------------------------------------
procedure SetFinish (
------------------------------------------------------------
Index : integer ;
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) is
begin
Alert(AlertLogIDVar(Index), "OSVVM.ScoreboardGenericPkg.SetFinish: Deprecated and removed. See CheckFinish", ERROR) ;
end procedure SetFinish ;
------------------------------------------------------------
procedure SetFinish (
------------------------------------------------------------
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) is
begin
SetFinish(FirstIndexVar, FCheckCount, FEmpty, FStatus) ;
end procedure SetFinish ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
-- Find Element with Matching Tag and ActualData
-- Returns integer'left if no match found
impure function Find (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return integer'left ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
loop
if CurPtr = NULL then
-- Failed to find it
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
if Tag /= "" then
Alert(AlertLogIDVar(Index),
GetName & " Did not find Tag: " & Tag & " and Actual Data: " & actual_to_string(ActualData),
FAILURE ) ;
else
Alert(AlertLogIDVar(Index),
GetName & " Did not find Actual Data: " & actual_to_string(ActualData),
FAILURE ) ;
end if ;
return integer'left ;
elsif CurPtr.TagPtr.all = Tag and
Match(ActualData, CurPtr.ExpectedPtr.all) then
-- Found it. Return Index.
return CurPtr.ItemNumber ;
else -- Descend
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end function Find ;
------------------------------------------------------------
-- Array of Simple Scoreboards
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) return integer is
begin
return Find(Index, "", ActualData) ;
end function Find ;
------------------------------------------------------------
-- Tagged Scoreboard
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
begin
return Find(FirstIndexVar, Tag, ActualData) ;
end function Find ;
------------------------------------------------------------
-- Simple Scoreboard
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant ActualData : in ActualType
) return integer is
begin
return Find(FirstIndexVar, "", ActualData) ;
end function Find ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
-- Flush Remove elements with tag whose itemNumber is <= ItemNumber parameter
procedure Flush (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ItemNumber : in integer
) is
variable CurPtr, RemovePtr, LastPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
LastPtr := NULL ;
loop
if CurPtr = NULL then
-- Done
return ;
elsif CurPtr.TagPtr.all = Tag then
if ItemNumber >= CurPtr.ItemNumber then
-- remove it
RemovePtr := CurPtr ;
if CurPtr = TailPointer(Index) then
TailPointer(Index) := LastPtr ;
end if ;
if CurPtr = HeadPointer(Index) then
HeadPointer(Index) := CurPtr.NextPtr ;
else -- if LastPtr /= NULL then
LastPtr.NextPtr := LastPtr.NextPtr.NextPtr ;
end if ;
CurPtr := CurPtr.NextPtr ;
-- LastPtr := LastPtr ; -- no change
DropCountVar(Index) := DropCountVar(Index) + 1 ;
deallocate(RemovePtr.TagPtr) ;
deallocate(RemovePtr.ExpectedPtr) ;
deallocate(RemovePtr) ;
else
-- Done
return ;
end if ;
else
-- Descend
LastPtr := CurPtr ;
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end procedure Flush ;
------------------------------------------------------------
-- Tagged Scoreboard
-- Flush Remove elements with tag whose itemNumber is <= ItemNumber parameter
procedure Flush (
------------------------------------------------------------
constant Tag : in string ;
constant ItemNumber : in integer
) is
begin
Flush(FirstIndexVar, Tag, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
-- Array of Simple Scoreboards
-- Flush - Remove Elements upto and including the one with ItemNumber
procedure Flush (
------------------------------------------------------------
constant Index : in integer ;
constant ItemNumber : in integer
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
loop
if CurPtr = NULL then
-- Done
return ;
elsif ItemNumber >= CurPtr.ItemNumber then
-- Descend, Check Tail, Deallocate
HeadPointer(Index) := HeadPointer(Index).NextPtr ;
if CurPtr = TailPointer(Index) then
TailPointer(Index) := NULL ;
end if ;
DropCountVar(Index) := DropCountVar(Index) + 1 ;
deallocate(CurPtr.TagPtr) ;
deallocate(CurPtr.ExpectedPtr) ;
deallocate(CurPtr) ;
CurPtr := HeadPointer(Index) ;
else
-- Done
return ;
end if ;
end loop ;
end procedure Flush ;
------------------------------------------------------------
-- Simple Scoreboard
-- Flush - Remove Elements upto and including the one with ItemNumber
procedure Flush (
------------------------------------------------------------
constant ItemNumber : in integer
) is
begin
Flush(FirstIndexVar, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
------------------------------------------------------------
-- Remaining Deprecated.
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
-- Use TranscriptPkg.TranscriptOpen
procedure FileOpen (FileName : string; OpenKind : File_Open_Kind ) is
------------------------------------------------------------
begin
-- WriteFileInit := TRUE ;
-- file_open( WriteFile , FileName , OpenKind );
TranscriptOpen(FileName, OpenKind) ;
end procedure FileOpen ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure PutExpectedData (ExpectedData : ExpectedType) is
------------------------------------------------------------
begin
Push(ExpectedData) ;
end procedure PutExpectedData ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure CheckActualData (ActualData : ActualType) is
------------------------------------------------------------
begin
Check(ActualData) ;
end procedure CheckActualData ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
impure function GetItemNumber return integer is
------------------------------------------------------------
begin
return GetItemCount(FirstIndexVar) ;
end GetItemNumber ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure SetMessage (MessageIn : String) is
------------------------------------------------------------
begin
-- deallocate(Message) ;
-- Message := new string'(MessageIn) ;
SetName(MessageIn) ;
end procedure SetMessage ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
impure function GetMessage return string is
------------------------------------------------------------
begin
-- return Message.all ;
return GetName("Scoreboard") ;
end function GetMessage ;
end protected body ScoreBoardPType ;
end ScoreboardGenericPkg ; | artistic-2.0 | 4f5c6f2605b3093e98c84454adab9795 | 0.494758 | 5.999462 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/grlib/sparc/sparc_disas.vhd | 1 | 27,693 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: sparc_disas
-- File: sparc_disas.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: SPARC disassembler according to SPARC V8 manual
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.testlib.print;
use std.textio.all;
package sparc_disas is
function tostf(v:std_logic_vector) return string;
procedure print_insn(ndx: integer; pc, op, res : std_logic_vector(31 downto 0);
valid, trap, wr, rest : boolean);
procedure print_fpinsn(ndx: integer; pc, op : std_logic_vector(31 downto 0);
res : std_logic_vector(63 downto 0);
dpres, valid, trap, wr : boolean);
function ins2st(pc, op : std_logic_vector(31 downto 0)) return string;
end;
package body sparc_disas is
type base_type is (hex, dec);
subtype nibble is std_logic_vector(3 downto 0);
type pc_op_type is record
pc, op : std_logic_vector(31 downto 0);
end record;
function tostd(v:std_logic_vector) return string;
function tosth(v:std_logic_vector) return string;
function tostrd(n:integer) return string;
function tohex(n:nibble) return character is
begin
case n is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('a');
when "1011" => return('b');
when "1100" => return('c');
when "1101" => return('d');
when "1110" => return('e');
when "1111" => return('f');
when others => return('X');
end case;
end;
type carr is array (0 to 9) of character;
constant darr : carr := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
function tostd(v:std_logic_vector) return string is
variable s : string(1 to 2);
variable val : integer;
begin
val := conv_integer(v); s(1) := darr(val / 10); s(2) := darr(val mod 10);
return(s);
end;
function tosth(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(vlen-1 downto 0);
variable s : string(1 to slen);
begin
vv := v;
for i in slen downto 1 loop
s(i) := tohex(vv(3 downto 0));
vv(vlen-5 downto 0) := vv(vlen-1 downto 4);
end loop;
return(s);
end;
function tostf(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(vlen-1 downto 0);
variable s : string(1 to slen);
begin
vv := v;
for i in slen downto 1 loop
s(i) := tohex(vv(3 downto 0));
vv(vlen-5 downto 0) := vv(vlen-1 downto 4);
end loop;
return("0x" & s);
end;
function tostrd(n:integer) return string is
variable len : integer := 0;
variable tmp : string(10 downto 1);
variable v : integer := n;
begin
for i in 0 to 9 loop
tmp(i+1) := darr(v mod 10);
if tmp(i+1) /= '0' then
len := i;
end if;
v := v/10;
end loop;
return(tmp(len+1 downto 1));
end;
function ireg2st(v : std_logic_vector) return string is
variable ctmp : character;
variable reg : std_logic_vector(4 downto 0);
begin
reg := v;
case reg(4 downto 3) is
when "00" => ctmp := 'g'; when "01" => ctmp := 'o';
when "10" => ctmp := 'l'; when "11" => ctmp := 'i';
when others => ctmp := 'X';
end case;
if v(4 downto 0) = "11110" then return("%fp");
elsif v(4 downto 0) = "01110" then return("%sp");
else return('%' & ctmp & tost('0' & reg(2 downto 0))); end if;
end;
function simm13dec(insn : pc_op_type; base : base_type; merge : boolean) return string is
variable simm : std_logic_vector(12 downto 0) := insn.op(12 downto 0);
variable rs1 : std_logic_vector(4 downto 0) := insn.op(18 downto 14);
variable i : std_ulogic := insn.op(13);
variable sig : character;
variable fill : std_logic_vector(31 downto 13) := (others => simm(12));
begin
if i = '0' then
return("");
else
if (simm(12) = '1') and (base = dec) then
sig := '-'; simm := (not simm) + 1;
else
sig := '+';
end if;
if base = dec then
if merge then
if rs1 = "00000" then
return(tost(simm));
else
return(sig & tost(simm));
end if;
else
if rs1 = "00000" then
return(tost(simm));
else
if sig = '-' then
return(", " & sig & tost(simm));
else
return(", " & tost(simm));
end if;
end if;
end if;
else
if rs1 = "00000" then
if simm(12) = '1' then return(tost(fill & simm));
else return(tost(simm)); end if;
else
if simm(12) = '1' then return(", " & tost(fill & simm));
else return(", " & tost(simm)); end if;
end if;
end if;
end if;
end;
function freg2(insn : pc_op_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
return("%f" & tostd(rs2) &
", %f" & tostd(rd));
end;
function creg3(insn : pc_op_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
return("%c" & tostd(rs1) & ", %c" & tostd(rs2) & ", %c" & tostd(rd));
end;
function freg3(insn : pc_op_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
return("%f" & tostd(rs1) & ", %f" & tostd(rs2) & ", %f" & tostd(rd));
end;
function fregc(insn : pc_op_type) return string is
variable rs1, rs2 : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
return("%f" & tostd(rs1) & ", %f" & tostd(rs2));
end;
function regimm(insn : pc_op_type; base : base_type; merge : boolean) return string is
variable rs1, rs2 : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
i := insn.op(13);
if i = '0' then
if (rs1 = "00000") then
if (rs2 = "00000") then return("0");
else return(ireg2st(rs2)); end if;
else
if (rs2 = "00000") then return(ireg2st(rs1));
elsif merge then return(ireg2st(rs1) & " + " & ireg2st(rs2));
else return(ireg2st(rs1) & ", " & ireg2st(rs2)); end if;
end if;
else
if (rs1 = "00000") then return(simm13dec(insn, base, merge));
elsif insn.op(12 downto 0) = "0000000000000" then return(ireg2st(rs1));
else return(ireg2st(rs1) & simm13dec(insn, base, merge)); end if;
end if;
end;
function regres(insn : pc_op_type; base : base_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rd := insn.op(29 downto 25);
return(regimm(insn, base,false) & ", " & ireg2st(rd ));
end;
function branchop(insn : pc_op_type) return string is
variable simm : std_logic_vector(31 downto 0);
begin
case insn.op(28 downto 25) is
when "0000" => return("n");
when "0001" => return("e");
when "0010" => return("le");
when "0011" => return("l");
when "0100" => return("leu");
when "0101" => return("cs");
when "0110" => return("neg");
when "0111" => return("vs");
when "1000" => return("a");
when "1001" => return("ne");
when "1010" => return("g");
when "1011" => return("ge");
when "1100" => return("gu");
when "1101" => return("cc");
when "1110" => return("pos");
when "1111" => return("vc");
when others => return("XXX");
end case;
end;
function fbranchop(insn : pc_op_type) return string is
variable simm : std_logic_vector(31 downto 0);
begin
case insn.op(28 downto 25) is
when "0000" => return("n");
when "0001" => return("ne");
when "0010" => return("lg");
when "0011" => return("ul");
when "0100" => return("l");
when "0101" => return("ug");
when "0110" => return("g");
when "0111" => return("u");
when "1000" => return("a");
when "1001" => return("e");
when "1010" => return("ue");
when "1011" => return("ge");
when "1100" => return("uge");
when "1101" => return("le");
when "1110" => return("ule");
when "1111" => return("o");
when others => return("XXX");
end case;
end;
function ldparcp(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & ", " & "%c" & tost(rd));
end;
function ldparf(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & ", " & "%f" & tostd(rd));
end;
function ldpar(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & ", " & ireg2st(rd));
end;
function ldpara(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & " " & tost(insn.op(12 downto 5)) & ", " & ireg2st(rd));
end;
function ldpara_cas(insn : pc_op_type; rs1, rs2, rd : std_logic_vector; base : base_type) return string is
begin
return("[" & ireg2st(rs1) & "]" & " " & tost(insn.op(12 downto 5)) & ", " &
ireg2st(rs2) & ", " & ireg2st(rd));
end;
function stparc(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
if rd = "00000" then
return("[" & regimm(insn,dec,true) & "]");
else
return(ireg2st(rd) & ", [" & regimm(insn,dec,true) & "]");
end if;
end;
function stparcp(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("%c" & tost(rd) & ", [" & regimm(insn,dec,true) & "]");
end;
function stparf(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("%f" & tostd(rd) & ", [" & regimm(insn,dec,true) & "]");
end;
function stpar(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return(ireg2st(rd) & ", [" & regimm(insn,dec,true) & "]");
end;
function stpara(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return(ireg2st(rd) & ", [" & regimm(insn,dec,true) & "]" & " " & tost(insn.op(12 downto 5)));
end;
function ins2st(pc, op : std_logic_vector(31 downto 0)) return string is
constant STMAX : natural := 9;
constant bl2 : string(1 to 2) := (others => ' ');
constant bb : string(1 to 4) := (others => ' ');
variable op1 : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable opf : std_logic_vector(8 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable addr : std_logic_vector(31 downto 0);
variable annul : std_ulogic;
variable i : std_ulogic;
variable simm : std_logic_vector(12 downto 0);
variable insn : pc_op_type;
begin
op1 := op(31 downto 30);
op2 := op(24 downto 22);
op3 := op(24 downto 19);
opf := op(13 downto 5);
cond := op(28 downto 25);
annul := op(29);
rs1 := op(18 downto 14);
rs2 := op(4 downto 0);
rd := op(29 downto 25);
i := op(13);
simm := op(12 downto 0);
insn.op := op;
insn.pc := pc;
case op1 is
when CALL =>
addr := pc + (op(29 downto 0) & "00");
return(tostf(pc) & bb & "call" & bl2 & tost(addr));
when FMT2 =>
case op2 is
when SETHI =>
if rd = "00000" then
return(tostf(pc) & bb & "nop");
else
return(tostf(pc) & bb & "sethi" & bl2 & "%hi(" &
tost(op(21 downto 0) & "0000000000") & "), " & ireg2st(rd));
end if;
when BICC | FBFCC =>
addr(31 downto 24) := (others => '0');
addr(1 downto 0) := (others => '0');
addr(23 downto 2) := op(21 downto 0);
if addr(23) = '1' then
addr(31 downto 24) := (others => '1');
else
addr(31 downto 24) := (others => '0');
end if;
addr := addr + pc;
if op2 = BICC then
if op(29) = '1' then
return(tostf(pc) & bb & 'b' & branchop(insn) & ",a" & bl2 &
tost(addr));
else
return(tostf(pc) & bb & 'b' & branchop(insn) & bl2 &
tost(addr));
end if;
else
if op(29) = '1' then
return(tostf(pc) & bb & "fb" & fbranchop(insn) & ",a" & bl2 &
tost(addr));
else
return(tostf(pc) & bb & "fb" & fbranchop(insn) & bl2 &
tost(addr));
end if;
end if;
-- when CBCCC => cptrap := '1';
when others => return(tostf(pc) & bb & "unimp");
end case;
when FMT3 =>
case op3 is
when IAND => return(tostf(pc) & bb & "and" & bl2 & regres(insn,hex));
when IADD => return(tostf(pc) & bb & "add" & bl2 & regres(insn,dec));
when IOR =>
if ((i = '0') and (rs1 = "00000") and (rs2 = "00000")) then
return(tostf(pc) & bb & "clr" & bl2 & ireg2st(rd));
elsif ((i = '1') and (simm = "0000000000000")) or (rs1 = "00000") then
return(tostf(pc) & bb & "mov" & bl2 & regres(insn,hex));
else
return(tostf(pc) & bb & "or " & bl2 & regres(insn,hex));
end if;
when IXOR => return(tostf(pc) & bb & "xor" & bl2 & regres(insn,hex));
when ISUB => return(tostf(pc) & bb & "sub" & bl2 & regres(insn,dec));
when ANDN => return(tostf(pc) & bb & "andn" & bl2 & regres(insn,hex));
when ORN => return(tostf(pc) & bb & "orn" & bl2 & regres(insn,hex));
when IXNOR =>
if ((i = '0') and ((rs1 = rd) or (rs2 = "00000"))) then
return(tostf(pc) & bb & "not" & bl2 & ireg2st(rd));
else
return(tostf(pc) & bb & "xnor" & bl2 & ireg2st(rd));
end if;
when ADDX => return(tostf(pc) & bb & "addx" & bl2 & regres(insn,dec));
when SUBX => return(tostf(pc) & bb & "subx" & bl2 & regres(insn,dec));
when ADDCC => return(tostf(pc) & bb & "addcc" & bl2 & regres(insn,dec));
when ANDCC => return(tostf(pc) & bb & "andcc" & bl2 & regres(insn,hex));
when ORCC => return(tostf(pc) & bb & "orcc" & bl2 & regres(insn,hex));
when XORCC => return(tostf(pc) & bb & "xorcc" & bl2 & regres(insn,hex));
when SUBCC => return(tostf(pc) & bb & "subcc" & bl2 & regres(insn,dec));
when ANDNCC => return(tostf(pc) & bb & "andncc" & bl2 & regres(insn,hex));
when ORNCC => return(tostf(pc) & bb & "orncc" & bl2 & regres(insn,hex));
when XNORCC => return(tostf(pc) & bb & "xnorcc" & bl2 & regres(insn,hex));
when ADDXCC => return(tostf(pc) & bb & "addxcc" & bl2 & regres(insn,hex));
when UMAC => return(tostf(pc) & bb & "umac" & bl2 & regres(insn,dec));
when SMAC => return(tostf(pc) & bb & "smac" & bl2 & regres(insn,dec));
when UMUL => return(tostf(pc) & bb & "umul" & bl2 & regres(insn,dec));
when SMUL => return(tostf(pc) & bb & "smul" & bl2 & regres(insn,dec));
when UMULCC => return(tostf(pc) & bb & "umulcc" & bl2 & regres(insn,dec));
when SMULCC => return(tostf(pc) & bb & "smulcc" & bl2 & regres(insn,dec));
when SUBXCC => return(tostf(pc) & bb & "subxcc" & bl2 & regres(insn,dec));
when UDIV => return(tostf(pc) & bb & "udiv" & bl2 & regres(insn,dec));
when SDIV => return(tostf(pc) & bb & "sdiv" & bl2 & regres(insn,dec));
when UDIVCC => return(tostf(pc) & bb & "udivcc" & bl2 & regres(insn,dec));
when SDIVCC => return(tostf(pc) & bb & "sdivcc" & bl2 & regres(insn,dec));
when TADDCC => return(tostf(pc) & bb & "taddcc" & bl2 & regres(insn,dec));
when TSUBCC => return(tostf(pc) & bb & "tsubcc" & bl2 & regres(insn,dec));
when TADDCCTV => return(tostf(pc) & bb & "taddcctv" & bl2 & regres(insn,dec));
when TSUBCCTV => return(tostf(pc) & bb & "tsubcctv" & bl2 & regres(insn,dec));
when MULSCC => return(tostf(pc) & bb & "mulscc" & bl2 & regres(insn,dec));
when ISLL => return(tostf(pc) & bb & "sll" & bl2 & regres(insn,dec));
when ISRL => return(tostf(pc) & bb & "srl" & bl2 & regres(insn,dec));
when ISRA => return(tostf(pc) & bb & "sra" & bl2 & regres(insn,dec));
when RDY =>
if rs1 /= "00000" then
return(tostf(pc) & bb & "mov" & bl2 & "%asr" &
tostd(rs1) & ", " & ireg2st(rd));
else
return(tostf(pc) & bb & "mov" & bl2 & "%y, " & ireg2st(rd));
end if;
when RDPSR => return(tostf(pc) & bb & "mov" & bl2 & "%psr, " & ireg2st(rd));
when RDWIM => return(tostf(pc) & bb & "mov" & bl2 & "%wim, " & ireg2st(rd));
when RDTBR => return(tostf(pc) & bb & "mov" & bl2 & "%tbr, " & ireg2st(rd));
when WRY =>
if (rs1 = "00000") or (rs2 = "00000") then
if rd /= "00000" then
return(tostf(pc) & bb & "mov" & bl2
& regimm(insn,hex,false) & ", %asr" & tostd(rd));
else
return(tostf(pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %y");
end if;
else
if rd /= "00000" then
return(tostf(pc) & bb & "wr " & bl2 & "%asr"
& regimm(insn,hex,false) & ", %asr" & tostd(rd));
else
return(tostf(pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %y");
end if;
end if;
when WRPSR =>
if (rs1 = "00000") or (rs2 = "00000") then
return(tostf(pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %psr");
else
return(tostf(pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %psr");
end if;
when WRWIM =>
if (rs1 = "00000") or (rs2 = "00000") then
return(tostf(pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %wim");
else
return(tostf(pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %wim");
end if;
when WRTBR =>
if (rs1 = "00000") or (rs2 = "00000") then
return(tostf(pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %tbr");
else
return(tostf(pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %tbr");
end if;
when JMPL =>
if (rd = "00000") then
if (i = '1') and (simm = "0000000001000") then
if (rs1 = "11111") then return(tostf(pc) & bb & "ret");
elsif (rs1 = "01111") then return(tostf(pc) & bb & "retl");
else return(tostf(pc) & bb & "jmp" & bl2 & regimm(insn,dec,true));
end if;
else return(tostf(pc) & bb & "jmp" & bl2 & regimm(insn,dec,true));
end if;
else return(tostf(pc) & bb & "jmpl" & bl2 & regres(insn,dec));
end if;
when TICC =>
return(tostf(pc) & bb & 't' & branchop(insn) & bl2 & regimm(insn,hex,false));
when FLUSH =>
return(tostf(pc) & bb & "flush" & bl2 & regimm(insn,hex,false));
when RETT =>
return(tostf(pc) & bb & "rett" & bl2 & regimm(insn,dec,true));
when RESTORE =>
if (rd = "00000") then
return(tostf(pc) & bb & "restore");
else
return(tostf(pc) & bb & "restore" & bl2 & regres(insn,hex));
end if;
when SAVE =>
if (rd = "00000") then return(tostf(pc) & bb & "save");
else return(tostf(pc) & bb & "save" & bl2 & regres(insn,dec)); end if;
when FPOP1 =>
case opf is
when FITOS => return(tostf(pc) & bb & "fitos" & bl2 & freg2(insn));
when FITOD => return(tostf(pc) & bb & "fitod" & bl2 & freg2(insn));
when FSTOI => return(tostf(pc) & bb & "fstoi" & bl2 & freg2(insn));
when FDTOI => return(tostf(pc) & bb & "fdtoi" & bl2 & freg2(insn));
when FSTOD => return(tostf(pc) & bb & "fstod" & bl2 & freg2(insn));
when FDTOS => return(tostf(pc) & bb & "fdtos" & bl2 & freg2(insn));
when FMOVS => return(tostf(pc) & bb & "fmovs" & bl2 & freg2(insn));
when FNEGS => return(tostf(pc) & bb & "fnegs" & bl2 & freg2(insn));
when FABSS => return(tostf(pc) & bb & "fabss" & bl2 & freg2(insn));
when FSQRTS => return(tostf(pc) & bb & "fsqrts" & bl2 & freg2(insn));
when FSQRTD => return(tostf(pc) & bb & "fsqrtd" & bl2 & freg2(insn));
when FADDS => return(tostf(pc) & bb & "fadds" & bl2 & freg3(insn));
when FADDD => return(tostf(pc) & bb & "faddd" & bl2 & freg3(insn));
when FSUBS => return(tostf(pc) & bb & "fsubs" & bl2 & freg3(insn));
when FSUBD => return(tostf(pc) & bb & "fsubd" & bl2 & freg3(insn));
when FMULS => return(tostf(pc) & bb & "fmuls" & bl2 & freg3(insn));
when FMULD => return(tostf(pc) & bb & "fmuld" & bl2 & freg3(insn));
when FSMULD => return(tostf(pc) & bb & "fsmuld" & bl2 & freg3(insn));
when FDIVS => return(tostf(pc) & bb & "fdivs" & bl2 & freg3(insn));
when FDIVD => return(tostf(pc) & bb & "fdivd" & bl2 & freg3(insn));
when others => return(tostf(pc) & bb & "unknown FOP1: " & tost(op));
end case;
when FPOP2 =>
case opf is
when FCMPS => return(tostf(pc) & bb & "fcmps" & bl2 & fregc(insn));
when FCMPD => return(tostf(pc) & bb & "fcmpd" & bl2 & fregc(insn));
when FCMPES => return(tostf(pc) & bb & "fcmpes" & bl2 & fregc(insn));
when FCMPED => return(tostf(pc) & bb & "fcmped" & bl2 & fregc(insn));
when others => return(tostf(pc) & bb & "unknown FOP2: " & tost(insn.op));
end case;
when CPOP1 =>
return(tostf(pc) & bb & "cpop1" & bl2 & tost("000"&opf) & ", " &creg3(insn));
when CPOP2 =>
return(tostf(pc) & bb & "cpop2" & bl2 & tost("000"&opf) & ", " &creg3(insn));
when others => return(tostf(pc) & bb & "unknown opcode: " & tost(insn.op));
end case;
when LDST =>
case op3 is
when STC =>
return(tostf(pc) & bb & "st" & bl2 & stparcp(insn, rd, dec));
when STF =>
return(tostf(pc) & bb & "st" & bl2 & stparf(insn, rd, dec));
when ST =>
if rd = "00000" then
return(tostf(pc) & bb & "clr" & bl2 & stparc(insn, rd, dec));
else
return(tostf(pc) & bb & "st" & bl2 & stpar(insn, rd, dec));
end if;
when STB =>
if rd = "00000" then
return(tostf(pc) & bb & "clrb" & bl2 & stparc(insn, rd, dec));
else
return(tostf(pc) & bb & "stb" & bl2 & stpar(insn, rd, dec));
end if;
when STH =>
if rd = "00000" then
return(tostf(pc) & bb & "clrh" & bl2 & stparc(insn, rd, dec));
else
return(tostf(pc) & bb & "sth" & bl2 & stpar(insn, rd, dec));
end if;
when STDC =>
return(tostf(pc) & bb & "std" & bl2 & stparcp(insn, rd, dec));
when STDF =>
return(tostf(pc) & bb & "std" & bl2 & stparf(insn, rd, dec));
when STCSR =>
return(tostf(pc) & bb & "st" & bl2 & "%csr, [" & regimm(insn,dec,true) & "]");
when STFSR =>
return(tostf(pc) & bb & "st" & bl2 & "%fsr, [" & regimm(insn,dec,true) & "]");
when STDCQ =>
return(tostf(pc) & bb & "std" & bl2 & "%cq, [" & regimm(insn,dec,true) & "]");
when STDFQ =>
return(tostf(pc) & bb & "std" & bl2 & "%fq, [" & regimm(insn,dec,true) & "]");
when ISTD =>
return(tostf(pc) & bb & "std" & bl2 & stpar(insn, rd, dec));
when STA =>
return(tostf(pc) & bb & "sta" & bl2 & stpara(insn, rd, dec));
when STBA =>
return(tostf(pc) & bb & "stba" & bl2 & stpara(insn, rd, dec));
when STHA =>
return(tostf(pc) & bb & "stha" & bl2 & stpara(insn, rd, dec));
when STDA =>
return(tostf(pc) & bb & "stda" & bl2 & stpara(insn, rd, dec));
when LDC =>
return(tostf(pc) & bb & "ld" & bl2 & ldparcp(insn, rd, dec));
when LDF =>
return(tostf(pc) & bb & "ld" & bl2 & ldparf(insn, rd, dec));
when LDCSR =>
return(tostf(pc) & bb & "ld" & bl2 & "[" & regimm(insn,dec,true) & "]" & ", %csr");
when LDFSR =>
return(tostf(pc) & bb & "ld" & bl2 & "[" & regimm(insn,dec,true) & "]" & ", %fsr");
when LD =>
return(tostf(pc) & bb & "ld" & bl2 & ldpar(insn, rd, dec));
when LDUB =>
return(tostf(pc) & bb & "ldub" & bl2 & ldpar(insn, rd, dec));
when LDUH =>
return(tostf(pc) & bb & "lduh" & bl2 & ldpar(insn, rd, dec));
when LDDC =>
return(tostf(pc) & bb & "ldd" & bl2 & ldparcp(insn, rd, dec));
when LDDF =>
return(tostf(pc) & bb & "ldd" & bl2 & ldparf(insn, rd, dec));
when LDD =>
return(tostf(pc) & bb & "ldd" & bl2 & ldpar(insn, rd, dec));
when LDSB =>
return(tostf(pc) & bb & "ldsb" & bl2 & ldpar(insn, rd, dec));
when LDSH =>
return(tostf(pc) & bb & "ldsh" & bl2 & ldpar(insn, rd, dec));
when LDSTUB =>
return(tostf(pc) & bb & "ldstub" & bl2 & ldpar(insn, rd, dec));
when SWAP =>
return(tostf(pc) & bb & "swap" & bl2 & ldpar(insn, rd, dec));
when LDA =>
return(tostf(pc) & bb & "lda" & bl2 & ldpara(insn, rd, dec));
when LDUBA =>
return(tostf(pc) & bb & "lduba" & bl2 & ldpara(insn, rd, dec));
when LDUHA =>
return(tostf(pc) & bb & "lduha" & bl2 & ldpara(insn, rd, dec));
when LDDA =>
return(tostf(pc) & bb & "ldda" & bl2 & ldpara(insn, rd, dec));
when LDSBA =>
return(tostf(pc) & bb & "ldsba" & bl2 & ldpara(insn, rd, dec));
when LDSHA =>
return(tostf(pc) & bb & "ldsha" & bl2 & ldpara(insn, rd, dec));
when LDSTUBA =>
return(tostf(pc) & bb & "ldstuba" & bl2 & ldpara(insn, rd, dec));
when SWAPA =>
return(tostf(pc) & bb & "swapa" & bl2 & ldpara(insn, rd, dec));
when CASA =>
return(tostf(pc) & bb & "casa" & bl2 & ldpara_cas(insn, rs1, rs2, rd, dec));
when others => return(tostf(pc) & bb & "unknown opcode: " & tost(op));
end case;
when others => return(tostf(pc) & bb & "unknown opcode: " & tost(op));
end case;
end;
procedure print_insn(ndx: integer; pc, op, res : std_logic_vector(31 downto 0);
valid, trap, wr, rest : boolean) is
begin
if valid then
if rest then grlib.testlib.print ("cpu" & tost(ndx) &": " & ins2st(pc, op) & " (restart)");
elsif trap then grlib.testlib.print ("cpu" & tost(ndx) &": " & ins2st(pc, op) & " (trapped)");
elsif wr then grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op) & " [" & tost(res) & "]");
else grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op)); end if;
end if;
end;
procedure print_fpinsn(ndx: integer; pc, op : std_logic_vector(31 downto 0);
res : std_logic_vector(63 downto 0);
dpres, valid, trap, wr : boolean) is
variable t : natural;
begin
if valid then
t := now / 1 ns;
if trap then grlib.testlib.print ("cpu" & tost(ndx) &": " & ins2st(pc, op) & " (trapped)");
elsif wr then
if dpres then grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op) & " [" & tost(res) & "]");
else grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op) & " [" & tost(res(63 downto 32)) & "]"); end if;
else grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op)); end if;
end if;
end;
end;
-- pragma translate_on
| gpl-2.0 | e53b7c8c4ae3a15020abe7f4a05c474b | 0.563464 | 2.934513 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/jtag/libjtagcom.vhd | 1 | 2,842 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libjtagcom
-- File: libjtagcom.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: JTAG Commulnications link signal and component declarations
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.misc.all;
package libjtagcom is
type tap_in_type is record
en : std_ulogic;
tdo : std_ulogic;
end record;
type tap_out_type is record
tck : std_ulogic;
tdi : std_ulogic;
inst : std_logic_vector(7 downto 0);
asel : std_ulogic;
dsel : std_ulogic;
reset : std_ulogic;
capt : std_ulogic;
shift : std_ulogic;
upd : std_ulogic;
end record;
component jtagcom
generic (
isel : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 2;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3;
reread : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tapo : in tap_out_type;
tapi : out tap_in_type;
dmao : in ahb_dma_out_type;
dmai : out ahb_dma_in_type;
tck : in std_ulogic;
trst : in std_ulogic
);
end component;
component jtagcom2 is
generic (
gatetech: integer := 0;
isel : integer range 0 to 1 := 0;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tapo : in tap_out_type;
tapi : out tap_in_type;
dmao : in ahb_dma_out_type;
dmai : out ahb_dma_in_type;
tckp : in std_ulogic;
tckn : in std_ulogic;
trst : in std_ulogic
);
end component;
end;
| gpl-2.0 | 8a34549b02c2cf166637caf7a1c746ca | 0.580225 | 3.850949 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/irqmp/irqmp.vhd | 1 | 11,203 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: irqmp
-- File: irqmp.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Multi-processor APB interrupt controller. Implements a
-- two-level interrupt controller for 15 interrupts.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
entity irqmp is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1)
);
end;
architecture rtl of irqmp is
constant REVISION : integer := 3;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_IRQMP, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type mask_type is array (0 to ncpu-1) of std_logic_vector(15 downto 1);
type mask2_type is array (0 to ncpu-1) of std_logic_vector(15 downto 0);
type irl_type is array (0 to ncpu-1) of std_logic_vector(3 downto 0);
type irl2_type is array (0 to ncpu-1) of std_logic_vector(4 downto 0);
type reg_type is record
imask : mask_type;
ilevel : std_logic_vector(15 downto 1);
ipend : std_logic_vector(15 downto 1);
iforce : mask_type;
ibroadcast : std_logic_vector(15 downto 1);
irl : irl_type;
cpurst : std_logic_vector(ncpu-1 downto 0);
end record;
type ereg_type is record
imask : mask2_type;
ipend : std_logic_vector(15 downto 0);
irl : irl2_type;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : reg_type := (
imask => (others => (others => '0')), ilevel => (others => '0'),
ipend => (others => '0'), iforce => (others => (others => '0')),
ibroadcast => (others => '0'), irl => (others => (others => '0')),
cpurst => (others => '0'));
constant ERES : ereg_type := (
imask => (others => (others => '0')), ipend => (others => '0'),
irl => (others => (others => '0')));
function prioritize(b : std_logic_vector(15 downto 0)) return std_logic_vector is
variable a : std_logic_vector(15 downto 0);
variable irl : std_logic_vector(3 downto 0);
variable level : integer range 0 to 15;
begin
irl := "0000"; level := 0; a := b;
for i in 15 downto 0 loop
level := i;
if a(i) = '1' then exit; end if;
end loop;
irl := conv_std_logic_vector(level, 4);
return(irl);
end;
signal r, rin : reg_type;
signal r2, r2in : ereg_type;
begin
comb : process(rst, r, r2, apbi, irqi)
variable v : reg_type;
variable temp : mask_type;
variable prdata : std_logic_vector(31 downto 0);
variable tmpirq : std_logic_vector(15 downto 0);
variable tmpvar : std_logic_vector(15 downto 1);
variable cpurun : std_logic_vector(ncpu-1 downto 0);
variable v2 : ereg_type;
variable irl2 : std_logic_vector(3 downto 0);
variable ipend2 : std_logic_vector(ncpu-1 downto 0);
variable temp2 : mask2_type;
variable neirq : integer;
begin
v := r; v.cpurst := (others => '0');
cpurun := (others => '0'); cpurun(0) := '1';
tmpvar := (others => '0'); ipend2 := (others => '0');
v2 := r2;
-- prioritize interrupts
if eirq /= 0 then
for i in 0 to ncpu-1 loop
temp2(i) := r2.ipend and r2.imask(i);
ipend2(i) := orv(temp2(i));
end loop;
end if;
for i in 0 to ncpu-1 loop
temp(i) := ((r.iforce(i) or r.ipend) and r.imask(i));
if eirq /= 0 then temp(i)(eirq) := temp(i)(eirq) or ipend2(i); end if;
v.irl(i) := prioritize((temp(i) and r.ilevel) & '0');
if v.irl(i) = "0000" then
if eirq /= 0 then temp(i)(eirq) := temp(i)(eirq) or ipend2(i); end if;
v.irl(i) := prioritize((temp(i) and not r.ilevel) & '0');
end if;
end loop;
-- register read
prdata := (others => '0');
case apbi.paddr(7 downto 6) is
when "00" =>
case apbi.paddr(4 downto 2) is
when "000" => prdata(15 downto 1) := r.ilevel;
when "001" =>
prdata(15 downto 1) := r.ipend;
if eirq /= 0 then prdata(31 downto 16) := r2.ipend; end if;
when "010" => prdata(15 downto 1) := r.iforce(0);
when "011" =>
when "100" | "101" =>
prdata(31 downto 28) := conv_std_logic_vector(ncpu-1, 4);
prdata(19 downto 16) := conv_std_logic_vector(eirq, 4);
for i in 0 to ncpu -1 loop prdata(i) := irqi(i).pwd; end loop;
if ncpu > 1 then
prdata(27) := '1';
case apbi.paddr(4 downto 2) is
when "101" =>
prdata := (others => '0');
prdata(15 downto 1) := r.ibroadcast;
when others =>
end case;
end if;
when others =>
end case;
when "01" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
prdata(15 downto 1) := r.imask(i);
if eirq /= 0 then prdata(31 downto 16) := r2.imask(i); end if;
end if;
end loop;
when "10" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
prdata(15 downto 1) := r.iforce(i);
end if;
end loop;
when "11" =>
if eirq /= 0 then
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
prdata(4 downto 0) := r2.irl(i);
end if;
end loop;
end if;
when others =>
end case;
-- register write
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(7 downto 6) is
when "00" =>
case apbi.paddr(4 downto 2) is
when "000" => v.ilevel := apbi.pwdata(15 downto 1);
when "001" => v.ipend := apbi.pwdata(15 downto 1);
if eirq /= 0 then v2.ipend := apbi.pwdata(31 downto 16); end if;
when "010" => v.iforce(0) := apbi.pwdata(15 downto 1);
when "011" => v.ipend := r.ipend and not apbi.pwdata(15 downto 1);
if eirq /= 0 then v2.ipend := r2.ipend and not apbi.pwdata(31 downto 16); end if;
when "100" =>
for i in 0 to ncpu -1 loop v.cpurst(i) := apbi.pwdata(i); end loop;
when others =>
if ncpu > 1 then
case apbi.paddr(4 downto 2) is
when "101" =>
v.ibroadcast := apbi.pwdata(15 downto 1);
when others =>
end case;
end if;
end case;
when "01" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
v.imask(i) := apbi.pwdata(15 downto 1);
if eirq /= 0 then v2.imask(i) := apbi.pwdata(31 downto 16); end if;
end if;
end loop;
when "10" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
v.iforce(i) := (r.iforce(i) or apbi.pwdata(15 downto 1)) and
not apbi.pwdata(31 downto 17);
end if;
end loop;
when others =>
end case;
end if;
-- register new interrupts
for i in 1 to 15 loop
if i > NAHBIRQ-1 then
exit;
end if;
if ncpu = 1 then
v.ipend(i) := v.ipend(i) or apbi.pirq(i);
else
v.ipend(i) := v.ipend(i) or (apbi.pirq(i) and not r.ibroadcast(i));
for j in 0 to ncpu-1 loop
tmpvar := v.iforce(j);
tmpvar(i) := tmpvar(i) or (apbi.pirq(i) and r.ibroadcast(i));
v.iforce(j) := tmpvar;
end loop;
end if;
end loop;
if eirq /= 0 then
for i in 16 to 31 loop
if i > NAHBIRQ-1 then exit; end if;
v2.ipend(i-16) := v2.ipend(i-16) or apbi.pirq(i);
end loop;
end if;
-- interrupt acknowledge
for i in 0 to ncpu-1 loop
if irqi(i).intack = '1' then
tmpirq := decode(irqi(i).irl);
temp(i) := tmpirq(15 downto 1);
v.iforce(i) := v.iforce(i) and not temp(i);
v.ipend := v.ipend and not ((not r.iforce(i)) and temp(i));
if eirq /= 0 then
if eirq = conv_integer(irqi(i).irl) then
v2.irl(i) := orv(temp2(i)) & prioritize(temp2(i));
if v2.irl(i)(4) = '1' then
v2.ipend(conv_integer(v2.irl(i)(3 downto 0))) := '0';
end if;
end if;
end if;
end if;
end loop;
-- reset
if (not RESET_ALL) and (rst = '0') then
v.imask := RRES.imask; v.iforce := RRES.iforce; v.ipend := RRES.ipend;
if ncpu > 1 then
v.ibroadcast := RRES.ibroadcast;
end if;
v2.ipend := ERES.ipend; v2.imask := ERES.imask; v2.irl := ERES.irl;
end if;
apbo.prdata <= prdata;
for i in 0 to ncpu-1 loop
irqo(i).irl <= r.irl(i); irqo(i).rst <= r.cpurst(i);
irqo(i).run <= cpurun(i);
irqo(i).rstvec <= (others => '0'); -- Alternate reset vector
irqo(i).iact <= '0';
irqo(i).index <= conv_std_logic_vector(i, 4);
irqo(i).hrdrst <= '0';
end loop;
rin <= v; r2in <= v2;
end process;
apbo.pirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and (rst = '0') then r <= RRES; end if;
end if;
end process;
dor2regs : if eirq /= 0 generate
regs : process(clk)
begin
if rising_edge(clk) then
r2 <= r2in;
if RESET_ALL and (rst = '0') then r2 <= ERES; end if;
end if;
end process;
end generate;
nor2regs : if eirq = 0 generate
-- r2 <= ((others => "0000000000000000"), "0000000000000000", (others => "00000"));
r2.ipend <= (others => '0');
driveregs: for i in 0 to (ncpu-1) generate
r2.imask(i) <= (others => '0');
r2.irl(i) <= (others => '0');
end generate driveregs;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("irqmp" &
": Multi-processor Interrupt Controller rev " & tost(REVISION) &
", #cpu " & tost(NCPU) & ", eirq " & tost(eirq));
-- pragma translate_on
end;
| gpl-2.0 | 1180fc4c586085232f11f3b4e97266b9 | 0.564938 | 3.231324 | false | false | false | false |
dawsonjon/FPGA-TX | synthesis/nexys_4/tx/nco.vhd | 3 | 5,745 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity nco is
generic(
width : integer := 32
);
port(
clk : in std_logic;
rst : in std_logic;
frequency : in std_logic_vector(31 downto 0);
lo_i_0 : out std_logic_vector(width - 1 downto 0);
lo_i_1 : out std_logic_vector(width - 1 downto 0);
lo_i_2 : out std_logic_vector(width - 1 downto 0);
lo_i_3 : out std_logic_vector(width - 1 downto 0);
lo_i_4 : out std_logic_vector(width - 1 downto 0);
lo_i_5 : out std_logic_vector(width - 1 downto 0);
lo_i_6 : out std_logic_vector(width - 1 downto 0);
lo_i_7 : out std_logic_vector(width - 1 downto 0);
lo_q_0 : out std_logic_vector(width - 1 downto 0);
lo_q_1 : out std_logic_vector(width - 1 downto 0);
lo_q_2 : out std_logic_vector(width - 1 downto 0);
lo_q_3 : out std_logic_vector(width - 1 downto 0);
lo_q_4 : out std_logic_vector(width - 1 downto 0);
lo_q_5 : out std_logic_vector(width - 1 downto 0);
lo_q_6 : out std_logic_vector(width - 1 downto 0);
lo_q_7 : out std_logic_vector(width - 1 downto 0)
);
end entity nco;
architecture rtl of nco is
constant sin_bits : integer := width;
constant sin_scale : real := 2.0**real(sin_bits);
constant sin_output_scale : real := ((2.0**real(sin_bits-1))-1.0) / sqrt(2.0);
constant sin_input_scale : real := ((2.0 * math_pi)/sin_scale);
type sin_array_type is array (0 to (2**sin_bits)-1) of std_logic_vector(sin_bits-1 downto 0);
function initialise_sin_array return sin_array_type is
variable x : sin_array_type;
begin
for i in 0 to (2**sin_bits)-1 loop
x(i) := std_logic_vector(to_signed(-integer(round(sin_output_scale * sin(real(i) * sin_input_scale))), sin_bits));
end loop;
return x;
end function;
function initialise_cos_array return sin_array_type is
variable x : sin_array_type;
begin
for i in 0 to (2**sin_bits)-1 loop
x(i) := std_logic_vector(to_signed(integer(round(sin_output_scale * cos(real(i) * sin_input_scale))), sin_bits));
end loop;
return x;
end function;
constant sin_array : sin_array_type := initialise_sin_array;
constant cos_array : sin_array_type := initialise_cos_array;
signal w_0 : unsigned(31 downto 0);
signal w_1 : unsigned(31 downto 0);
signal w_2 : unsigned(31 downto 0);
signal w_3 : unsigned(31 downto 0);
signal w_4 : unsigned(31 downto 0);
signal w_5 : unsigned(31 downto 0);
signal w_6 : unsigned(31 downto 0);
signal w_7 : unsigned(31 downto 0);
signal frequency_d1 : unsigned(31 downto 0) := (others => '0');
signal frequency_d2 : unsigned(31 downto 0) := (others => '0');
signal frequency_d3 : unsigned(31 downto 0) := (others => '0');
signal accum : unsigned(31 downto 0) := (others => '0');
signal tree_0 : unsigned(31 downto 0) := (others => '0');
signal tree_1 : unsigned(31 downto 0) := (others => '0');
signal tree_00 : unsigned(31 downto 0) := (others => '0');
signal tree_01 : unsigned(31 downto 0) := (others => '0');
signal tree_10 : unsigned(31 downto 0) := (others => '0');
signal tree_11 : unsigned(31 downto 0) := (others => '0');
signal tree_000 : unsigned(31 downto 0) := (others => '0');
signal tree_001 : unsigned(31 downto 0) := (others => '0');
signal tree_010 : unsigned(31 downto 0) := (others => '0');
signal tree_011 : unsigned(31 downto 0) := (others => '0');
signal tree_100 : unsigned(31 downto 0) := (others => '0');
signal tree_101 : unsigned(31 downto 0) := (others => '0');
signal tree_110 : unsigned(31 downto 0) := (others => '0');
signal tree_111 : unsigned(31 downto 0) := (others => '0');
begin
process
begin
wait until rising_edge(clk);
frequency_d1 <= unsigned(frequency);
frequency_d2 <= frequency_d1;
frequency_d3 <= frequency_d2;
accum <= accum + (unsigned(frequency(28 downto 0)) & "000");
tree_0 <= accum;
tree_1 <= accum + (frequency_d1(29 downto 0) & "00");
tree_00 <= tree_0;
tree_01 <= tree_0 + (frequency_d2(30 downto 0) & '0');
tree_10 <= tree_1;
tree_11 <= tree_1 + (frequency_d2(30 downto 0) & '0');
tree_000 <= tree_00;
tree_001 <= tree_00 + frequency_d3;
tree_010 <= tree_01;
tree_011 <= tree_01 + frequency_d3;
tree_100 <= tree_10;
tree_101 <= tree_10 + frequency_d3;
tree_110 <= tree_11;
tree_111 <= tree_11 + frequency_d3;
w_0 <= tree_000;
w_1 <= tree_001;
w_2 <= tree_010;
w_3 <= tree_011;
w_4 <= tree_100;
w_5 <= tree_101;
w_6 <= tree_110;
w_7 <= tree_111;
lo_q_0 <= sin_array(to_integer(w_0(31 downto 32-sin_bits)));
lo_q_1 <= sin_array(to_integer(w_1(31 downto 32-sin_bits)));
lo_q_2 <= sin_array(to_integer(w_2(31 downto 32-sin_bits)));
lo_q_3 <= sin_array(to_integer(w_3(31 downto 32-sin_bits)));
lo_q_4 <= sin_array(to_integer(w_4(31 downto 32-sin_bits)));
lo_q_5 <= sin_array(to_integer(w_5(31 downto 32-sin_bits)));
lo_q_6 <= sin_array(to_integer(w_6(31 downto 32-sin_bits)));
lo_q_7 <= sin_array(to_integer(w_7(31 downto 32-sin_bits)));
lo_i_0 <= cos_array(to_integer(w_0(31 downto 32-sin_bits)));
lo_i_1 <= cos_array(to_integer(w_1(31 downto 32-sin_bits)));
lo_i_2 <= cos_array(to_integer(w_2(31 downto 32-sin_bits)));
lo_i_3 <= cos_array(to_integer(w_3(31 downto 32-sin_bits)));
lo_i_4 <= cos_array(to_integer(w_4(31 downto 32-sin_bits)));
lo_i_5 <= cos_array(to_integer(w_5(31 downto 32-sin_bits)));
lo_i_6 <= cos_array(to_integer(w_6(31 downto 32-sin_bits)));
lo_i_7 <= cos_array(to_integer(w_7(31 downto 32-sin_bits)));
end process;
end rtl;
| mit | 1946f1fd87f6f44dbcffb55700bd7cbe | 0.603655 | 2.914764 | false | false | false | false |
JimLewis/OSVVM | TextUtilPkg.vhd | 1 | 17,500 | --
-- File Name: TextUtilPkg.vhd
-- Design Unit Name: TextUtilPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis [email protected]
--
--
-- Description:
-- Shared Utilities for handling text files
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 01/2015 2015.05 Initial revision
-- 01/2016 2016.01 Update for L.all(L'left)
-- 11/2016 2016.11 Added IsUpper, IsLower, to_upper, to_lower
-- 01/2020 2020.01 Updated Licenses to Apache
-- 08/2020 2020.08 Added ReadUntilDelimiterOrEOL and FindDelimiter
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2015 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
package TextUtilPkg is
------------------------------------------------------------
function IsUpper (constant Char : character ) return boolean ;
function IsLower (constant Char : character ) return boolean ;
function to_lower (constant Char : character ) return character ;
function to_lower (constant Str : string ) return string ;
function to_upper (constant Char : character ) return character ;
function to_upper (constant Str : string ) return string ;
function IsHex (constant Char : character ) return boolean ;
function IsNumber (constant Char : character ) return boolean ;
function IsNumber (Name : string ) return boolean ;
function isstd_logic (constant Char : character ) return boolean ;
-- Crutch until VHDL-2019 conditional initialization
function IfElse(Expr : boolean ; A, B : string) return string ;
------------------------------------------------------------
procedure SkipWhiteSpace (
------------------------------------------------------------
variable L : InOut line ;
variable Empty : out boolean
) ;
procedure SkipWhiteSpace (variable L : InOut line) ;
------------------------------------------------------------
procedure EmptyOrCommentLine (
------------------------------------------------------------
variable L : InOut line ;
variable Empty : InOut boolean ;
variable MultiLineComment : inout boolean
) ;
------------------------------------------------------------
procedure ReadUntilDelimiterOrEOL(
------------------------------------------------------------
variable L : InOut line ;
variable Name : InOut line ;
constant Delimiter : In character ;
variable ReadValid : Out boolean
) ;
------------------------------------------------------------
procedure FindDelimiter(
------------------------------------------------------------
variable L : InOut line ;
constant Delimiter : In character ;
variable Found : Out boolean
) ;
------------------------------------------------------------
procedure ReadHexToken (
-- Reads Upto Result'length values, less is ok.
-- Does not skip white space
------------------------------------------------------------
variable L : InOut line ;
variable Result : Out std_logic_vector ;
variable StrLen : Out integer
) ;
------------------------------------------------------------
procedure ReadBinaryToken (
-- Reads Upto Result'length values, less is ok.
-- Does not skip white space
------------------------------------------------------------
variable L : InOut line ;
variable Result : Out std_logic_vector ;
variable StrLen : Out integer
) ;
end TextUtilPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body TextUtilPkg is
constant LOWER_TO_UPPER_OFFSET : integer := character'POS('a') - character'POS('A') ;
------------------------------------------------------------
function "-" (R : character ; L : integer ) return character is
------------------------------------------------------------
begin
return character'VAL(character'pos(R) - L) ;
end function "-" ;
------------------------------------------------------------
function "+" (R : character ; L : integer ) return character is
------------------------------------------------------------
begin
return character'VAL(character'pos(R) + L) ;
end function "+" ;
------------------------------------------------------------
function IsUpper (constant Char : character ) return boolean is
------------------------------------------------------------
begin
if Char >= 'A' and Char <= 'Z' then
return TRUE ;
else
return FALSE ;
end if ;
end function IsUpper ;
------------------------------------------------------------
function IsLower (constant Char : character ) return boolean is
------------------------------------------------------------
begin
if Char >= 'a' and Char <= 'z' then
return TRUE ;
else
return FALSE ;
end if ;
end function IsLower ;
------------------------------------------------------------
function to_lower (constant Char : character ) return character is
------------------------------------------------------------
begin
if IsUpper(Char) then
return Char + LOWER_TO_UPPER_OFFSET ;
else
return Char ;
end if ;
end function to_lower ;
------------------------------------------------------------
function to_lower (constant Str : string ) return string is
------------------------------------------------------------
variable result : string(Str'range) ;
begin
for i in Str'range loop
result(i) := to_lower(Str(i)) ;
end loop ;
return result ;
end function to_lower ;
------------------------------------------------------------
function to_upper (constant Char : character ) return character is
------------------------------------------------------------
begin
if IsLower(Char) then
return Char - LOWER_TO_UPPER_OFFSET ;
else
return Char ;
end if ;
end function to_upper ;
------------------------------------------------------------
function to_upper (constant Str : string ) return string is
------------------------------------------------------------
variable result : string(Str'range) ;
begin
for i in Str'range loop
result(i) := to_upper(Str(i)) ;
end loop ;
return result ;
end function to_upper ;
------------------------------------------------------------
function IsHex (constant Char : character ) return boolean is
------------------------------------------------------------
begin
if Char >= '0' and Char <= '9' then
return TRUE ;
elsif Char >= 'a' and Char <= 'f' then
return TRUE ;
elsif Char >= 'A' and Char <= 'F' then
return TRUE ;
else
return FALSE ;
end if ;
end function IsHex ;
------------------------------------------------------------
function IsNumber (constant Char : character ) return boolean is
------------------------------------------------------------
begin
return Char >= '0' and Char <= '9' ;
end function IsNumber ;
------------------------------------------------------------
function IsNumber (Name : string ) return boolean is
------------------------------------------------------------
begin
for i in Name'range loop
if not IsNumber(Name(i)) then
return FALSE ;
end if ;
end loop ;
return TRUE ;
end function IsNumber ;
------------------------------------------------------------
function isstd_logic (constant Char : character ) return boolean is
------------------------------------------------------------
begin
case Char is
when 'U' | 'X' | '0' | '1' | 'Z' | 'W' | 'L' | 'H' | '-' =>
return TRUE ;
when others =>
return FALSE ;
end case ;
end function isstd_logic ;
------------------------------------------------------------
function IfElse(Expr : boolean ; A, B : string) return string is
------------------------------------------------------------
begin
if Expr then
return A ;
else
return B ;
end if ;
end function IfElse ;
-- ------------------------------------------------------------
-- function iscomment (constant Char : character ) return boolean is
-- ------------------------------------------------------------
-- begin
-- case Char is
-- when '#' | '/' | '-' =>
-- return TRUE ;
-- when others =>
-- return FALSE ;
-- end case ;
-- end function iscomment ;
------------------------------------------------------------
procedure SkipWhiteSpace (
------------------------------------------------------------
variable L : InOut line ;
variable Empty : out boolean
) is
variable Valid : boolean ;
variable Char : character ;
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
begin
Empty := TRUE ;
WhiteSpLoop : while L /= null and L.all'length > 0 loop
if (L.all(L'left) = ' ' or L.all(L'left) = NBSP or L.all(L'left) = HT) then
read (L, Char, Valid) ;
exit when not Valid ;
else
Empty := FALSE ;
return ;
end if ;
end loop WhiteSpLoop ;
end procedure SkipWhiteSpace ;
------------------------------------------------------------
procedure SkipWhiteSpace (
------------------------------------------------------------
variable L : InOut line
) is
variable Empty : boolean ;
begin
SkipWhiteSpace(L, Empty) ;
end procedure SkipWhiteSpace ;
------------------------------------------------------------
-- Package Local
procedure FindCommentEnd (
------------------------------------------------------------
variable L : InOut line ;
variable Empty : out boolean ;
variable MultiLineComment : inout boolean
) is
variable Valid : boolean ;
variable Char : character ;
begin
MultiLineComment := TRUE ;
Empty := TRUE ;
FindEndOfCommentLoop : while L /= null and L.all'length > 1 loop
read(L, Char, Valid) ;
if Char = '*' and L.all(L'left) = '/' then
read(L, Char, Valid) ;
Empty := FALSE ;
MultiLineComment := FALSE ;
exit FindEndOfCommentLoop ;
end if ;
end loop ;
end procedure FindCommentEnd ;
------------------------------------------------------------
procedure EmptyOrCommentLine (
------------------------------------------------------------
variable L : InOut line ;
variable Empty : InOut boolean ;
variable MultiLineComment : inout boolean
) is
variable Valid : boolean ;
variable Next2Char : string(1 to 2) ;
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
begin
if MultiLineComment then
FindCommentEnd(L, Empty, MultiLineComment) ;
end if ;
EmptyCheckLoop : while not MultiLineComment loop
SkipWhiteSpace(L, Empty) ;
exit when Empty ; -- line null or 0 in length detected by SkipWhite
Empty := TRUE ;
exit when L.all(L'left) = '#' ; -- shell style comment
if L.all'length >= 2 then
if L'ascending then
Next2Char := L.all(L'left to L'left+1) ;
else
Next2Char := L.all(L'left downto L'left-1) ;
end if;
exit when Next2Char = "//" ; -- C style comment
exit when Next2Char = "--" ; -- VHDL style comment
if Next2Char = "/*" then -- C style multi line comment
FindCommentEnd(L, Empty, MultiLineComment) ;
exit when Empty ;
next EmptyCheckLoop ; -- Found end of comment, restart processing line
end if ;
end if ;
Empty := FALSE ;
exit ;
end loop EmptyCheckLoop ;
end procedure EmptyOrCommentLine ;
------------------------------------------------------------
procedure ReadUntilDelimiterOrEOL(
------------------------------------------------------------
variable L : InOut line ;
variable Name : InOut line ;
constant Delimiter : In character ;
variable ReadValid : Out boolean
) is
variable NameStr : string(1 to L'length) ;
variable ReadLen : integer := 1 ;
variable Good : boolean ;
begin
ReadValid := TRUE ;
for i in NameStr'range loop
Read(L, NameStr(i), Good) ;
ReadValid := ReadValid and Good ;
if NameStr(i) = Delimiter then
-- Read(L, NameStr(1 to i), ReadValid) ;
Name := new string'(NameStr(1 to i-1)) ;
exit ;
elsif i = NameStr'length then
-- Read(L, NameStr(1 to i), ReadValid) ;
Name := new string'(NameStr(1 to i)) ;
exit ;
end if ;
end loop ;
end procedure ReadUntilDelimiterOrEOL ;
------------------------------------------------------------
procedure FindDelimiter(
------------------------------------------------------------
variable L : InOut line ;
constant Delimiter : In character ;
variable Found : Out boolean
) is
variable Char : Character ;
variable ReadValid : boolean ;
begin
Found := FALSE ;
ReadLoop : loop
if Delimiter /= ' ' then
SkipWhiteSpace(L) ;
end if ;
Read(L, Char, ReadValid) ;
exit when ReadValid = FALSE or Char /= Delimiter ;
Found := TRUE ;
exit ;
end loop ;
end procedure FindDelimiter ;
------------------------------------------------------------
procedure ReadHexToken (
-- Reads Upto Result'length values, less is ok.
-- Does not skip white space
------------------------------------------------------------
variable L : InOut line ;
variable Result : Out std_logic_vector ;
variable StrLen : Out integer
) is
constant NumHexChars : integer := (Result'length+3)/4 ;
constant ResultNormLen : integer := NumHexChars * 4 ;
variable NextChar : character ;
variable CharCount : integer ;
variable ReturnVal : std_logic_vector(ResultNormLen-1 downto 0) ;
variable ReadVal : std_logic_vector(3 downto 0) ;
variable ReadValid : boolean ;
begin
ReturnVal := (others => '0') ;
CharCount := 0 ;
ReadLoop : while L /= null and L.all'length > 0 loop
NextChar := L.all(L'left) ;
if ishex(NextChar) or NextChar = 'X' or NextChar = 'Z' then
hread(L, ReadVal, ReadValid) ;
ReturnVal := ReturnVal(ResultNormLen-5 downto 0) & ReadVal ;
CharCount := CharCount + 1 ;
exit ReadLoop when CharCount >= NumHexChars ;
elsif NextChar = '_' then
read(L, NextChar, ReadValid) ;
else
exit ;
end if ;
end loop ReadLoop ;
if CharCount >= NumHexChars then
StrLen := Result'length ;
else
StrLen := CharCount * 4 ;
end if ;
Result := ReturnVal(Result'length-1 downto 0) ;
end procedure ReadHexToken ;
------------------------------------------------------------
procedure ReadBinaryToken (
-- Reads Upto Result'length values, less is ok.
-- Does not skip white space
------------------------------------------------------------
variable L : InOut line ;
variable Result : Out std_logic_vector ;
variable StrLen : Out integer
) is
variable NextChar : character ;
variable CharCount : integer ;
variable ReadVal : std_logic ;
variable ReturnVal : std_logic_vector(Result'length-1 downto 0) ;
variable ReadValid : boolean ;
begin
ReturnVal := (others => '0') ;
CharCount := 0 ;
ReadLoop : while L /= null and L.all'length > 0 loop
NextChar := L.all(L'left) ;
if isstd_logic(NextChar) then
read(L, ReadVal, ReadValid) ;
ReturnVal := ReturnVal(Result'length-2 downto 0) & ReadVal ;
CharCount := CharCount + 1 ;
exit ReadLoop when CharCount >= Result'length ;
elsif NextChar = '_' then
read(L, NextChar, ReadValid) ;
else
exit ;
end if ;
end loop ReadLoop ;
StrLen := CharCount ;
Result := ReturnVal ;
end procedure ReadBinaryToken ;
end package body TextUtilPkg ; | artistic-2.0 | d7a1fca658d13f287e726b247a5657f8 | 0.469257 | 4.932356 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/eb5e10ceec6d67b2/zqynq_lab_1_design_auto_pc_1_sim_netlist.vhdl | 1 | 454,564 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Sat Sep 23 13:26:01 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_auto_pc_1_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_auto_pc_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_incr_reg : out STD_LOGIC_VECTOR ( 7 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
\m_axi_awaddr[1]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_0 : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
\next\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \axaddr_incr[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_3_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_4_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal next_pending_r_i_5_n_0 : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 1 );
signal \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_3\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_4\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \axlen_cnt[5]_i_2\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of next_pending_r_i_5 : label is "soft_lutpair89";
begin
Q(0) <= \^q\(0);
axaddr_incr_reg(7 downto 0) <= \^axaddr_incr_reg\(7 downto 0);
\axaddr_incr_reg[11]_0\ <= \^axaddr_incr_reg[11]_0\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axlen_cnt_reg[3]_0\ <= \^axlen_cnt_reg[3]_0\;
\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\,
I1 => \next\,
O => \axaddr_incr[0]_i_1_n_0\
);
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \next\,
I2 => \m_payload_i_reg[51]\(5),
I3 => \m_payload_i_reg[51]\(4),
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A6A"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \next\,
I2 => \m_payload_i_reg[51]\(5),
I3 => \m_payload_i_reg[51]\(4),
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"006A"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \next\,
I2 => \m_payload_i_reg[51]\(4),
I3 => \m_payload_i_reg[51]\(5),
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"0006"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \next\,
I2 => \m_payload_i_reg[51]\(5),
I3 => \m_payload_i_reg[51]\(4),
O => S(0)
);
\axaddr_incr[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(3),
O => \axaddr_incr[4]_i_2_n_0\
);
\axaddr_incr[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(2),
O => \axaddr_incr[4]_i_3_n_0\
);
\axaddr_incr[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(1),
O => \axaddr_incr[4]_i_4_n_0\
);
\axaddr_incr[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(0),
O => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(7),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(7),
O => \axaddr_incr[8]_i_2_n_0\
);
\axaddr_incr[8]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(6),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(6),
O => \axaddr_incr[8]_i_3_n_0\
);
\axaddr_incr[8]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(5),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(5),
O => \axaddr_incr[8]_i_4_n_0\
);
\axaddr_incr[8]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(4),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(4),
O => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[8]_i_1_n_5\,
Q => \^axaddr_incr_reg\(6),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[8]_i_1_n_4\,
Q => \^axaddr_incr_reg\(7),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[4]_i_1_n_7\,
Q => \^axaddr_incr_reg\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1_n_7\,
S(3) => \axaddr_incr[4]_i_2_n_0\,
S(2) => \axaddr_incr[4]_i_3_n_0\,
S(1) => \axaddr_incr[4]_i_4_n_0\,
S(0) => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[4]_i_1_n_6\,
Q => \^axaddr_incr_reg\(1),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[4]_i_1_n_5\,
Q => \^axaddr_incr_reg\(2),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[4]_i_1_n_4\,
Q => \^axaddr_incr_reg\(3),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[8]_i_1_n_7\,
Q => \^axaddr_incr_reg\(4),
R => '0'
);
\axaddr_incr_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1_n_7\,
S(3) => \axaddr_incr[8]_i_2_n_0\,
S(2) => \axaddr_incr[8]_i_3_n_0\,
S(1) => \axaddr_incr[8]_i_4_n_0\,
S(0) => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[8]_i_1_n_6\,
Q => \^axaddr_incr_reg\(5),
R => '0'
);
\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(7),
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \^q\(0),
I4 => \^axlen_cnt_reg[3]_0\,
O => p_1_in(1)
);
\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(8),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \^axlen_cnt_reg[3]_0\,
O => p_1_in(2)
);
\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \^axlen_cnt_reg[3]_0\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__0_n_0\
);
\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8B88888B"
)
port map (
I0 => \m_payload_i_reg[51]\(9),
I1 => E(0),
I2 => \axlen_cnt[4]_i_2_n_0\,
I3 => \axlen_cnt[4]_i_3_n_0\,
I4 => \axlen_cnt_reg_n_0_[4]\,
O => p_1_in(4)
);
\axlen_cnt[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[4]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
I4 => \axlen_cnt_reg_n_0_[6]\,
I5 => \axlen_cnt[4]_i_4_n_0\,
O => \axlen_cnt[4]_i_2_n_0\
);
\axlen_cnt[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[4]_i_3_n_0\
);
\axlen_cnt[4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_4_n_0\
);
\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FF88888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(10),
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt[5]_i_2_n_0\,
I4 => \^axlen_cnt_reg[3]_0\,
O => p_1_in(5)
);
\axlen_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[5]_i_2_n_0\
);
\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF282828"
)
port map (
I0 => \^axlen_cnt_reg[3]_0\,
I1 => \axlen_cnt_reg_n_0_[6]\,
I2 => \axlen_cnt[7]_i_3_n_0\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(11),
O => p_1_in(6)
);
\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF828882888288"
)
port map (
I0 => \^axlen_cnt_reg[3]_0\,
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt[7]_i_3_n_0\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(12),
O => p_1_in(7)
);
\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[4]\,
I5 => \axlen_cnt_reg_n_0_[5]\,
O => \axlen_cnt[7]_i_3_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => p_1_in(1),
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => p_1_in(2),
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[3]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => p_1_in(4),
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => p_1_in(5),
Q => \axlen_cnt_reg_n_0_[5]\,
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => p_1_in(6),
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => p_1_in(7),
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_awaddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\,
I1 => \^axaddr_incr_reg[3]_0\(1),
I2 => \m_payload_i_reg[51]\(6),
I3 => \m_payload_i_reg[51]\(1),
O => \m_axi_awaddr[1]\
);
\next_pending_r_i_3__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555554"
)
port map (
I0 => E(0),
I1 => next_pending_r_i_5_n_0,
I2 => \axlen_cnt_reg_n_0_[4]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[5]\,
O => \^axlen_cnt_reg[3]_0\
);
next_pending_r_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
O => next_pending_r_i_5_n_0
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_0,
Q => \^axaddr_incr_reg[11]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
port (
incr_next_pending : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_incr_reg[11]_1\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]_0\ : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axlen_cnt_reg[5]_0\ : out STD_LOGIC;
\m_axi_araddr[6]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
\m_payload_i_reg[47]_0\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_13_b2s_incr_cmd";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5__0_n_0\ : STD_LOGIC;
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 6 to 6 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \^axaddr_incr_reg[11]_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_7\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \next_pending_r_i_5__0_n_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axlen_cnt[5]_i_2__0\ : label is "soft_lutpair3";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\axaddr_incr_reg[11]_0\(6 downto 0) <= \^axaddr_incr_reg[11]_0\(6 downto 0);
\axaddr_incr_reg[11]_1\ <= \^axaddr_incr_reg[11]_1\;
\axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\;
incr_next_pending <= \^incr_next_pending\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A262A2A2A2A2A2A"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A060A0A0A0A0A0A"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \m_payload_i_reg[51]\(5),
I2 => \m_payload_i_reg[51]\(6),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"0201020202020202"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(0)
);
\axaddr_incr[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(2),
O => \axaddr_incr[4]_i_2__0_n_0\
);
\axaddr_incr[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => axaddr_incr_reg(6),
O => \axaddr_incr[4]_i_3__0_n_0\
);
\axaddr_incr[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(1),
O => \axaddr_incr[4]_i_4__0_n_0\
);
\axaddr_incr[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(0),
O => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr[8]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(6),
O => \axaddr_incr[8]_i_2__0_n_0\
);
\axaddr_incr[8]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(5),
O => \axaddr_incr[8]_i_3__0_n_0\
);
\axaddr_incr[8]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(4),
O => \axaddr_incr[8]_i_4__0_n_0\
);
\axaddr_incr[8]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(3),
O => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1__0_n_7\,
S(3) => \axaddr_incr[4]_i_2__0_n_0\,
S(2) => \axaddr_incr[4]_i_3__0_n_0\,
S(1) => \axaddr_incr[4]_i_4__0_n_0\,
S(0) => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_6\,
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_5\,
Q => axaddr_incr_reg(6),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[8]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1__0_n_7\,
S(3) => \axaddr_incr[8]_i_2__0_n_0\,
S(2) => \axaddr_incr[8]_i_3__0_n_0\,
S(1) => \axaddr_incr[8]_i_4__0_n_0\,
S(0) => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_6\,
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(8),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => \axlen_cnt[2]_i_1__1_n_0\
);
\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__1_n_0\
);
\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt[4]_i_2__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(9),
O => \axlen_cnt[4]_i_1__0_n_0\
);
\axlen_cnt[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(1),
I3 => \^q\(0),
O => \axlen_cnt[4]_i_2__0_n_0\
);
\axlen_cnt[5]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt_reg[5]_0\
);
\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F88888F8F888F888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(10),
I2 => \state_reg[0]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
I4 => \^q\(3),
I5 => \^axlen_cnt_reg[7]_0\,
O => \axlen_cnt[7]_i_2__0_n_0\
);
\axlen_cnt[7]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \axlen_cnt_reg_n_0_[4]\,
I5 => \^q\(2),
O => \^axlen_cnt_reg[7]_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(2),
Q => \^q\(2),
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(3),
Q => \^q\(3),
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[7]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_araddr[6]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => axaddr_incr_reg(6),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(4),
O => \m_axi_araddr[6]\
);
\next_pending_r_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDCCFCFFDDFFFC"
)
port map (
I0 => \m_payload_i_reg[48]\,
I1 => \m_payload_i_reg[47]_0\,
I2 => next_pending_r_reg_n_0,
I3 => \state_reg[1]_rep\,
I4 => E(0),
I5 => \^next_pending_r_reg_0\,
O => \^incr_next_pending\
);
\next_pending_r_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \next_pending_r_i_5__0_n_0\,
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \^q\(3),
I3 => \axlen_cnt_reg_n_0_[4]\,
O => \^next_pending_r_reg_0\
);
\next_pending_r_i_5__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^q\(1),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \^q\(2),
O => \next_pending_r_i_5__0_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^incr_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_1\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
port (
\axlen_cnt_reg[5]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[0]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_i : out STD_LOGIC;
\axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axlen_cnt_reg[7]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axburst_eq1_reg : in STD_LOGIC;
\cnt_read_reg[2]\ : in STD_LOGIC;
\axlen_cnt_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[50]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\axlen_cnt_reg[3]\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[35]_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axlen_cnt_reg[5]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \wrap_cnt_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[0]\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \state[1]_i_1__0\ : label is "soft_lutpair0";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair2";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
axaddr_offset(1 downto 0) <= \^axaddr_offset\(1 downto 0);
\axlen_cnt_reg[5]\ <= \^axlen_cnt_reg[5]\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\wrap_cnt_r_reg[0]\ <= \^wrap_cnt_r_reg[0]\;
\wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0);
\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAEA"
)
port map (
I0 => sel_first_reg_2,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAC0AAAA"
)
port map (
I0 => \axaddr_offset_r_reg[3]\(0),
I1 => \m_payload_i_reg[3]\,
I2 => \m_payload_i_reg[50]\(0),
I3 => \^q\(0),
I4 => si_rs_arvalid,
I5 => \^q\(1),
O => \^axaddr_offset\(0)
);
\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]\(1),
I1 => \m_payload_i_reg[50]\(2),
I2 => \^m_payload_i_reg[0]_0\,
I3 => si_rs_arvalid,
I4 => \^m_payload_i_reg[0]\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset\(1)
);
\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_arvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[50]\(0),
I4 => \axlen_cnt_reg[6]\(0),
I5 => \^axlen_cnt_reg[5]\,
O => D(0)
);
\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[50]\(1),
I2 => \axlen_cnt_reg[6]\(1),
I3 => \axlen_cnt_reg[6]\(0),
I4 => \^axlen_cnt_reg[5]\,
O => D(1)
);
\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF282828"
)
port map (
I0 => \^axlen_cnt_reg[5]\,
I1 => \axlen_cnt_reg[6]\(2),
I2 => \axlen_cnt_reg[4]\,
I3 => \^e\(0),
I4 => \m_payload_i_reg[50]\(3),
O => D(2)
);
\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF282828"
)
port map (
I0 => \^axlen_cnt_reg[5]\,
I1 => \axlen_cnt_reg[6]\(3),
I2 => \axlen_cnt_reg[3]\,
I3 => \^e\(0),
I4 => \m_payload_i_reg[50]\(4),
O => D(3)
);
\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00CA"
)
port map (
I0 => si_rs_arvalid,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_wrap_reg[11]\(0)
);
\axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_arvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[7]\,
O => \^axlen_cnt_reg[5]\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
O => m_axi_arvalid
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => si_rs_arvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i_reg[0]_1\(0)
);
r_push_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => m_axi_arready,
O => r_push_r_reg
);
\sel_first_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFFFFFFCCCECCCE"
)
port map (
I0 => si_rs_arvalid,
I1 => areset_d1,
I2 => \^m_payload_i_reg[0]\,
I3 => \^m_payload_i_reg[0]_0\,
I4 => m_axi_arready,
I5 => sel_first_reg_1,
O => sel_first_i
);
\sel_first_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_3,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"003030303E3E3E3E"
)
port map (
I0 => si_rs_arvalid,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => m_axi_arready,
I4 => s_axburst_eq1_reg,
I5 => \cnt_read_reg[2]\,
O => next_state(0)
);
\state[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00AAB000"
)
port map (
I0 => \cnt_read_reg[2]\,
I1 => s_axburst_eq1_reg,
I2 => m_axi_arready,
I3 => \^m_payload_i_reg[0]_0\,
I4 => \^m_payload_i_reg[0]\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^m_payload_i_reg[0]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^m_payload_i_reg[0]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_arvalid,
I2 => \^m_payload_i_reg[0]_0\,
O => \^e\(0)
);
\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8A5575AA8A5545"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^q\(0),
I2 => si_rs_arvalid,
I3 => \^q\(1),
I4 => \^wrap_cnt_r_reg[0]\,
I5 => \^axaddr_offset\(0),
O => \wrap_cnt_r_reg[3]\(0)
);
\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA6AA56AAAAAAAA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \^e\(0),
I3 => \^wrap_cnt_r_reg[0]\,
I4 => \^axaddr_offset\(0),
I5 => \^wrap_second_len_r_reg[3]\(1),
O => \wrap_cnt_r_reg[3]\(1)
);
\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(3),
I1 => \^wrap_second_len_r_reg[3]\(1),
I2 => \wrap_cnt_r[3]_i_2__0_n_0\,
I3 => \^wrap_second_len_r_reg[3]\(2),
O => \wrap_cnt_r_reg[3]\(2)
);
\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"D1D1D1D1D1D1DFD1"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^e\(0),
I2 => \^axaddr_offset\(0),
I3 => \m_payload_i_reg[35]\,
I4 => \m_payload_i_reg[46]\(0),
I5 => \^axaddr_offset\(1),
O => \wrap_cnt_r[3]_i_2__0_n_0\
);
\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8AAA8AAA8AAABA"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^q\(0),
I2 => si_rs_arvalid,
I3 => \^q\(1),
I4 => \^wrap_cnt_r_reg[0]\,
I5 => \^axaddr_offset\(0),
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004000404"
)
port map (
I0 => \^axaddr_offset\(0),
I1 => \m_payload_i_reg[35]\,
I2 => \m_payload_i_reg[46]\(0),
I3 => \^e\(0),
I4 => \axaddr_offset_r_reg[3]\(1),
I5 => \m_payload_i_reg[35]_0\,
O => \^wrap_cnt_r_reg[0]\
);
\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0FE0FFFF0FE00000"
)
port map (
I0 => \^axaddr_offset\(1),
I1 => \m_payload_i_reg[46]\(0),
I2 => \m_payload_i_reg[35]\,
I3 => \^axaddr_offset\(0),
I4 => \^e\(0),
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CC2CFFFFCC2C0000"
)
port map (
I0 => \^axaddr_offset\(1),
I1 => \m_payload_i_reg[46]\(0),
I2 => \m_payload_i_reg[35]\,
I3 => \^axaddr_offset\(0),
I4 => \^e\(0),
I5 => \wrap_second_len_r_reg[3]_0\(2),
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF4FF44444444"
)
port map (
I0 => \^e\(0),
I1 => \wrap_second_len_r_reg[3]_0\(3),
I2 => \^axaddr_offset\(0),
I3 => \m_payload_i_reg[35]\,
I4 => \m_payload_i_reg[46]\(0),
I5 => \m_payload_i_reg[35]_0\,
O => \^wrap_second_len_r_reg[3]\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
port (
\cnt_read_reg[0]_rep_0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__0_0\ : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bresp_push : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
bvalid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
shandshake_r : in STD_LOGIC;
b_push : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
mhandshake_r : in STD_LOGIC;
bvalid_i_reg_0 : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
signal \^bresp_push\ : STD_LOGIC;
signal bvalid_i_i_2_n_0 : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[0]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_rep_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_2__0_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_4_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_5_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_6_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_7_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][4]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][5]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][6]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][7]_srl4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of bvalid_i_i_1 : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair91";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
attribute srl_bus_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][4]_srl4 ";
attribute srl_bus_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][5]_srl4 ";
attribute srl_bus_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][6]_srl4 ";
attribute srl_bus_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][7]_srl4 ";
attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
begin
bresp_push <= \^bresp_push\;
\cnt_read_reg[0]_rep_0\ <= \^cnt_read_reg[0]_rep_0\;
\cnt_read_reg[1]_rep__0_0\ <= \^cnt_read_reg[1]_rep__0_0\;
\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => areset_d1,
I1 => \^bresp_push\,
O => SR(0)
);
bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"002A"
)
port map (
I0 => bvalid_i_i_2_n_0,
I1 => bvalid_i_reg_0,
I2 => si_rs_bready,
I3 => areset_d1,
O => bvalid_i_reg
);
bvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00070707"
)
port map (
I0 => \^cnt_read_reg[0]_rep_0\,
I1 => \^cnt_read_reg[1]_rep__0_0\,
I2 => shandshake_r,
I3 => Q(1),
I4 => Q(0),
I5 => bvalid_i_reg_0,
O => bvalid_i_i_2_n_0
);
\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cnt_read_reg[0]_rep_0\,
I1 => b_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1_n_0\
);
\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^bresp_push\,
I1 => shandshake_r,
I2 => Q(0),
O => D(0)
);
\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DB24"
)
port map (
I0 => \^cnt_read_reg[0]_rep_0\,
I1 => shandshake_r,
I2 => b_push,
I3 => \^cnt_read_reg[1]_rep__0_0\,
O => \cnt_read[1]_i_1_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1_n_0\,
Q => \^cnt_read_reg[0]_rep_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \^cnt_read_reg[1]_rep__0_0\,
S => areset_d1
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(0),
Q => \memory_reg[3][0]_srl4_n_0\
);
\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \memory_reg[3][0]_srl4_i_2__0_n_0\,
I1 => \memory_reg[3][0]_srl4_i_3_n_0\,
I2 => \memory_reg[3][0]_srl4_i_4_n_0\,
I3 => \memory_reg[3][0]_srl4_i_5_n_0\,
O => \^bresp_push\
);
\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \bresp_cnt_reg[7]\(7),
I1 => \memory_reg[3][7]_srl4_n_0\,
I2 => \memory_reg[3][1]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(1),
I4 => \memory_reg[3][0]_srl4_n_0\,
I5 => \bresp_cnt_reg[7]\(0),
O => \memory_reg[3][0]_srl4_i_2__0_n_0\
);
\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF22F2"
)
port map (
I0 => \bresp_cnt_reg[7]\(3),
I1 => \memory_reg[3][3]_srl4_n_0\,
I2 => \memory_reg[3][6]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(6),
I4 => \memory_reg[3][0]_srl4_i_6_n_0\,
O => \memory_reg[3][0]_srl4_i_3_n_0\
);
\memory_reg[3][0]_srl4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF4F4FFF4F"
)
port map (
I0 => \memory_reg[3][6]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(6),
I2 => mhandshake_r,
I3 => \memory_reg[3][3]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(3),
I5 => \memory_reg[3][0]_srl4_i_7_n_0\,
O => \memory_reg[3][0]_srl4_i_4_n_0\
);
\memory_reg[3][0]_srl4_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"66F666F6FFFF66F6"
)
port map (
I0 => \bresp_cnt_reg[7]\(2),
I1 => \memory_reg[3][2]_srl4_n_0\,
I2 => \bresp_cnt_reg[7]\(4),
I3 => \memory_reg[3][4]_srl4_n_0\,
I4 => \memory_reg[3][5]_srl4_n_0\,
I5 => \bresp_cnt_reg[7]\(5),
O => \memory_reg[3][0]_srl4_i_5_n_0\
);
\memory_reg[3][0]_srl4_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \memory_reg[3][5]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(5),
I2 => \bresp_cnt_reg[7]\(4),
I3 => \memory_reg[3][4]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_6_n_0\
);
\memory_reg[3][0]_srl4_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^cnt_read_reg[0]_rep_0\,
I1 => \^cnt_read_reg[1]_rep__0_0\,
O => \memory_reg[3][0]_srl4_i_7_n_0\
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(1),
Q => \memory_reg[3][1]_srl4_n_0\
);
\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(2),
Q => \memory_reg[3][2]_srl4_n_0\
);
\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(3),
Q => \memory_reg[3][3]_srl4_n_0\
);
\memory_reg[3][4]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(4),
Q => \memory_reg[3][4]_srl4_n_0\
);
\memory_reg[3][5]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(5),
Q => \memory_reg[3][5]_srl4_n_0\
);
\memory_reg[3][6]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(6),
Q => \memory_reg[3][6]_srl4_n_0\
);
\memory_reg[3][7]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(7),
Q => \memory_reg[3][7]_srl4_n_0\
);
\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(8),
Q => \out\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
port (
s_bresp_acc : out STD_LOGIC;
mhandshake : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC;
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
mhandshake_r : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
bresp_push : in STD_LOGIC;
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
signal \^mhandshake\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair93";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair93";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
mhandshake <= \^mhandshake\;
\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => shandshake_r,
I3 => bresp_push,
O => \cnt_read[1]_i_1__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \^q\(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__0_n_0\,
Q => \^q\(1),
S => areset_d1
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => mhandshake_r,
O => m_axi_bready
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => bresp_push,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[1]\(0)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => bresp_push,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[1]\(1)
);
mhandshake_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => m_axi_bvalid,
I1 => mhandshake_r,
I2 => \^q\(0),
I3 => \^q\(1),
O => \^mhandshake\
);
\s_bresp_acc[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"2020A220"
)
port map (
I0 => \^mhandshake\,
I1 => \in\(1),
I2 => m_axi_bresp(1),
I3 => m_axi_bresp(0),
I4 => \in\(0),
O => s_bresp_acc
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
port (
\cnt_read_reg[3]_rep__2_0\ : out STD_LOGIC;
wr_en0 : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_ready_i_reg : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[4]_0\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[3]_rep__2_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^wr_en0\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[4]_i_5\ : label is "soft_lutpair9";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair7";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair7";
begin
\cnt_read_reg[3]_rep__2_0\ <= \^cnt_read_reg[3]_rep__2_0\;
\cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\;
\cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\;
wr_en0 <= \^wr_en0\;
\cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => s_ready_i_reg,
I2 => \^wr_en0\,
O => \cnt_read[0]_i_1__1_n_0\
);
\cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \^wr_en0\,
I2 => s_ready_i_reg,
I3 => \cnt_read_reg[0]_rep__2_n_0\,
O => \cnt_read[1]_i_1__1_n_0\
);
\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA6AA9AA"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \^wr_en0\,
I3 => s_ready_i_reg,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => \cnt_read[2]_i_1_n_0\
);
\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[0]_rep__2_n_0\,
I4 => \^wr_en0\,
I5 => s_ready_i_reg,
O => \cnt_read[3]_i_1_n_0\
);
\cnt_read[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA55AAA6A6AAA6AA"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \cnt_read[4]_i_2_n_0\,
I2 => \cnt_read[4]_i_3_n_0\,
I3 => s_ready_i_reg_0,
I4 => \^cnt_read_reg[4]_rep__2_1\,
I5 => \^cnt_read_reg[3]_rep__2_0\,
O => \cnt_read[4]_i_1_n_0\
);
\cnt_read[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
O => \cnt_read[4]_i_2_n_0\
);
\cnt_read[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => si_rs_rready,
I2 => \cnt_read_reg[4]_0\,
I3 => \^wr_en0\,
O => \cnt_read[4]_i_3_n_0\
);
\cnt_read[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
O => \^cnt_read_reg[4]_rep__2_1\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \^cnt_read_reg[3]_rep__2_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \^cnt_read_reg[4]_rep__2_0\,
S => areset_d1
);
m_axi_rready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F77F777F"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => m_axi_rready
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(0),
Q => \out\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA2A2AAA2A2A2AAA"
)
port map (
I0 => m_axi_rvalid,
I1 => \^cnt_read_reg[3]_rep__2_0\,
I2 => \^cnt_read_reg[4]_rep__2_0\,
I3 => \cnt_read_reg[1]_rep__2_n_0\,
I4 => \cnt_read_reg[2]_rep__2_n_0\,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \^wr_en0\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(10),
Q => \out\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(11),
Q => \out\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(12),
Q => \out\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(13),
Q => \out\(13),
Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(14),
Q => \out\(14),
Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(15),
Q => \out\(15),
Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(16),
Q => \out\(16),
Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(17),
Q => \out\(17),
Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(18),
Q => \out\(18),
Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(19),
Q => \out\(19),
Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(1),
Q => \out\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(20),
Q => \out\(20),
Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(21),
Q => \out\(21),
Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(22),
Q => \out\(22),
Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(23),
Q => \out\(23),
Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(24),
Q => \out\(24),
Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(25),
Q => \out\(25),
Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(26),
Q => \out\(26),
Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(27),
Q => \out\(27),
Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(28),
Q => \out\(28),
Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(29),
Q => \out\(29),
Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(2),
Q => \out\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(30),
Q => \out\(30),
Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(31),
Q => \out\(31),
Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(32),
Q => \out\(32),
Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(33),
Q => \out\(33),
Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(3),
Q => \out\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(4),
Q => \out\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(5),
Q => \out\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(6),
Q => \out\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(7),
Q => \out\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(8),
Q => \out\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(9),
Q => \out\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"7C000000"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \^cnt_read_reg[4]_rep__2_0\,
I4 => \^cnt_read_reg[3]_rep__2_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
port (
m_valid_i_reg : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2\ : out STD_LOGIC;
\skid_buffer_reg[35]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_ready_i_reg : in STD_LOGIC;
r_push_r : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[0]_rep__2\ : in STD_LOGIC;
wr_en0 : in STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__2_0\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_4__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_5__0_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \cnt_read[4]_i_4__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \cnt_read[4]_i_5__0\ : label is "soft_lutpair12";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => cnt_read(0),
I1 => s_ready_i_reg,
I2 => r_push_r,
O => \cnt_read[0]_i_1__2_n_0\
);
\cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AA6"
)
port map (
I0 => cnt_read(1),
I1 => s_ready_i_reg,
I2 => r_push_r,
I3 => cnt_read(0),
O => \cnt_read[1]_i_1__2_n_0\
);
\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA96AAA"
)
port map (
I0 => cnt_read(2),
I1 => cnt_read(1),
I2 => cnt_read(0),
I3 => r_push_r,
I4 => s_ready_i_reg,
O => \cnt_read[2]_i_1__0_n_0\
);
\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => cnt_read(3),
I1 => cnt_read(0),
I2 => cnt_read(1),
I3 => cnt_read(2),
I4 => r_push_r,
I5 => s_ready_i_reg,
O => \cnt_read[3]_i_1__0_n_0\
);
\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA55AAA6A6AAA6AA"
)
port map (
I0 => cnt_read(4),
I1 => \cnt_read[4]_i_2__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read[4]_i_4__0_n_0\,
I4 => \cnt_read[4]_i_5__0_n_0\,
I5 => cnt_read(3),
O => \cnt_read[4]_i_1__0_n_0\
);
\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => cnt_read(1),
I1 => cnt_read(2),
O => \cnt_read[4]_i_2__0_n_0\
);
\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => cnt_read(0),
I1 => si_rs_rready,
I2 => \^m_valid_i_reg\,
I3 => r_push_r,
O => \cnt_read[4]_i_3__0_n_0\
);
\cnt_read[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^m_valid_i_reg\,
I1 => si_rs_rready,
I2 => wr_en0,
O => \cnt_read_reg[4]_rep__2\
);
\cnt_read[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^m_valid_i_reg\,
I1 => si_rs_rready,
I2 => r_push_r,
O => \cnt_read[4]_i_4__0_n_0\
);
\cnt_read[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => cnt_read(2),
I1 => cnt_read(1),
I2 => cnt_read(0),
O => \cnt_read[4]_i_5__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => cnt_read(4),
S => areset_d1
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => cnt_read(4),
I1 => cnt_read(3),
I2 => \cnt_read[4]_i_5__0_n_0\,
I3 => \cnt_read_reg[4]_rep__2_0\,
I4 => \cnt_read_reg[3]_rep__2\,
I5 => \cnt_read_reg[0]_rep__2_0\,
O => \^m_valid_i_reg\
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[35]\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[35]\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BEFEAAAAAAAAAAAA"
)
port map (
I0 => \cnt_read_reg[0]_rep__2\,
I1 => cnt_read(2),
I2 => cnt_read(1),
I3 => cnt_read(0),
I4 => cnt_read(3),
I5 => cnt_read(4),
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
port (
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[0]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axlen_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\next\ : out STD_LOGIC;
\axaddr_wrap_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[35]_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\axlen_cnt_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[48]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\m_payload_i_reg[46]_0\ : in STD_LOGIC;
\axlen_cnt_reg[2]\ : in STD_LOGIC;
next_pending_r_reg_0 : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\cnt_read_reg[0]_rep\ : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\sel_first__0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^b_push\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^next\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^sel_first_i\ : STD_LOGIC;
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[0]\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair87";
attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair85";
attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair87";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair86";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
axaddr_offset(1 downto 0) <= \^axaddr_offset\(1 downto 0);
b_push <= \^b_push\;
incr_next_pending <= \^incr_next_pending\;
\next\ <= \^next\;
sel_first_i <= \^sel_first_i\;
\wrap_cnt_r_reg[0]\ <= \^wrap_cnt_r_reg[0]\;
wrap_next_pending <= \^wrap_next_pending\;
\wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0);
\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAC0AAAA"
)
port map (
I0 => \axaddr_offset_r_reg[3]\(0),
I1 => \m_payload_i_reg[3]\,
I2 => \m_payload_i_reg[47]\(1),
I3 => \^q\(0),
I4 => si_rs_awvalid,
I5 => \^q\(1),
O => \^axaddr_offset\(0)
);
\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]\(1),
I1 => \m_payload_i_reg[47]\(2),
I2 => \^q\(0),
I3 => si_rs_awvalid,
I4 => \^q\(1),
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset\(1)
);
\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[47]\(1),
I4 => \axlen_cnt_reg[0]_0\(0),
I5 => \axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[0]\(0)
);
\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF04"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \^next\,
O => \axaddr_wrap_reg[0]\(0)
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => m_axi_awvalid
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^b_push\,
I1 => si_rs_awvalid,
O => \m_payload_i_reg[0]\(0)
);
\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA20AA200000AA20"
)
port map (
I0 => \^q\(0),
I1 => s_axburst_eq1_reg_0,
I2 => m_axi_awready,
I3 => \^q\(1),
I4 => \cnt_read_reg[1]_rep__0\,
I5 => \cnt_read_reg[0]_rep\,
O => \^b_push\
);
next_pending_r_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[48]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[4]\,
I3 => \^next\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
\next_pending_r_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[46]_0\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[2]\,
I3 => \^next\,
I4 => next_pending_r_reg_0,
O => \^wrap_next_pending\
);
next_pending_r_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBFFFF00B00000"
)
port map (
I0 => \cnt_read_reg[0]_rep\,
I1 => \cnt_read_reg[1]_rep__0\,
I2 => m_axi_awready,
I3 => s_axburst_eq1_reg_0,
I4 => \^q\(0),
I5 => \^q\(1),
O => \^next\
);
s_axburst_eq0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
s_axburst_eq1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
sel_first_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FF04FFFFFF04FF04"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
I3 => areset_d1,
I4 => \^next\,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44444F44"
)
port map (
I0 => \^next\,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44444F44"
)
port map (
I0 => \^next\,
I1 => \sel_first__0\,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BBBA"
)
port map (
I0 => \state[0]_i_2_n_0\,
I1 => \^q\(0),
I2 => si_rs_awvalid,
I3 => \^q\(1),
O => next_state(0)
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00F000F055750000"
)
port map (
I0 => m_axi_awready,
I1 => s_axburst_eq1_reg_0,
I2 => \cnt_read_reg[1]_rep__0\,
I3 => \cnt_read_reg[0]_rep\,
I4 => \^q\(0),
I5 => \^q\(1),
O => \state[0]_i_2_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08000800FC000800"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => m_axi_awready,
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \cnt_read_reg[1]_rep__0\,
I5 => \cnt_read_reg[0]_rep\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
O => \^e\(0)
);
\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8A5575AA8A5545"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^q\(0),
I2 => si_rs_awvalid,
I3 => \^q\(1),
I4 => \^wrap_cnt_r_reg[0]\,
I5 => \^axaddr_offset\(0),
O => D(0)
);
\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA6AA56AAAAAAAA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \^e\(0),
I3 => \^wrap_cnt_r_reg[0]\,
I4 => \^axaddr_offset\(0),
I5 => \^wrap_second_len_r_reg[3]\(1),
O => D(1)
);
\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(3),
I1 => \^wrap_second_len_r_reg[3]\(1),
I2 => \wrap_cnt_r[3]_i_2_n_0\,
I3 => \^wrap_second_len_r_reg[3]\(2),
O => D(2)
);
\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"D1D1D1D1D1D1DFD1"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^e\(0),
I2 => \^axaddr_offset\(0),
I3 => \m_payload_i_reg[35]\,
I4 => \m_payload_i_reg[46]\(0),
I5 => \^axaddr_offset\(1),
O => \wrap_cnt_r[3]_i_2_n_0\
);
\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8AAA8AAA8AAABA"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^q\(0),
I2 => si_rs_awvalid,
I3 => \^q\(1),
I4 => \^wrap_cnt_r_reg[0]\,
I5 => \^axaddr_offset\(0),
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004000404"
)
port map (
I0 => \^axaddr_offset\(0),
I1 => \m_payload_i_reg[35]\,
I2 => \m_payload_i_reg[46]\(0),
I3 => \^e\(0),
I4 => \axaddr_offset_r_reg[3]\(1),
I5 => \m_payload_i_reg[35]_0\,
O => \^wrap_cnt_r_reg[0]\
);
\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0FE0FFFF0FE00000"
)
port map (
I0 => \^axaddr_offset\(1),
I1 => \m_payload_i_reg[46]\(0),
I2 => \m_payload_i_reg[35]\,
I3 => \^axaddr_offset\(0),
I4 => \^e\(0),
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CC2CFFFFCC2C0000"
)
port map (
I0 => \^axaddr_offset\(1),
I1 => \m_payload_i_reg[46]\(0),
I2 => \m_payload_i_reg[35]\,
I3 => \^axaddr_offset\(0),
I4 => \^e\(0),
I5 => \wrap_second_len_r_reg[3]_0\(2),
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF4FF44444444"
)
port map (
I0 => \^e\(0),
I1 => \wrap_second_len_r_reg[3]_0\(3),
I2 => \^axaddr_offset\(0),
I3 => \m_payload_i_reg[35]\,
I4 => \m_payload_i_reg[46]\(0),
I5 => \m_payload_i_reg[35]_0\,
O => \^wrap_second_len_r_reg[3]\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 18 downto 0 );
\next\ : in STD_LOGIC;
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
\m_payload_i_reg[35]\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_2\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of next_pending_r_i_3 : label is "soft_lutpair90";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0);
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_2\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_2\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_2\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_2\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(0),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(0),
I3 => \next\,
I4 => Q(0),
O => \axaddr_wrap[0]_i_1_n_0\
);
\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(10),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(10),
I3 => \next\,
I4 => Q(10),
O => \axaddr_wrap[10]_i_1_n_0\
);
\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(11),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(11),
I3 => \next\,
I4 => Q(11),
O => \axaddr_wrap[11]_i_1_n_0\
);
\axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4_n_0\,
I1 => wrap_cnt_r(3),
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2_n_0\
);
\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => wrap_cnt_r(0),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => wrap_cnt_r(2),
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => wrap_cnt_r(1),
O => \axaddr_wrap[11]_i_4_n_0\
);
\axaddr_wrap[11]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(11),
O => \axaddr_wrap[11]_i_5_n_0\
);
\axaddr_wrap[11]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(10),
O => \axaddr_wrap[11]_i_6_n_0\
);
\axaddr_wrap[11]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(9),
O => \axaddr_wrap[11]_i_7_n_0\
);
\axaddr_wrap[11]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(8),
O => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(1),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(1),
I3 => \next\,
I4 => Q(1),
O => \axaddr_wrap[1]_i_1_n_0\
);
\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(2),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(2),
I3 => \next\,
I4 => Q(2),
O => \axaddr_wrap[2]_i_1_n_0\
);
\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(3),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(3),
I3 => \next\,
I4 => Q(3),
O => \axaddr_wrap[3]_i_1_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => axaddr_wrap(3),
I1 => Q(12),
I2 => Q(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(2),
I1 => Q(12),
I2 => Q(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(1),
I1 => Q(13),
I2 => Q(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => axaddr_wrap(0),
I1 => Q(12),
I2 => Q(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(4),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(4),
I3 => \next\,
I4 => Q(4),
O => \axaddr_wrap[4]_i_1_n_0\
);
\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(5),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(5),
I3 => \next\,
I4 => Q(5),
O => \axaddr_wrap[5]_i_1_n_0\
);
\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(6),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(6),
I3 => \next\,
I4 => Q(6),
O => \axaddr_wrap[6]_i_1_n_0\
);
\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(7),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(7),
I3 => \next\,
I4 => Q(7),
O => \axaddr_wrap[7]_i_1_n_0\
);
\axaddr_wrap[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(7),
O => \axaddr_wrap[7]_i_3_n_0\
);
\axaddr_wrap[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(6),
O => \axaddr_wrap[7]_i_4_n_0\
);
\axaddr_wrap[7]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(5),
O => \axaddr_wrap[7]_i_5_n_0\
);
\axaddr_wrap[7]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(4),
O => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(8),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(8),
I3 => \next\,
I4 => Q(8),
O => \axaddr_wrap[8]_i_1_n_0\
);
\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(9),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(9),
I3 => \next\,
I4 => Q(9),
O => \axaddr_wrap[9]_i_1_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[0]_i_1_n_0\,
Q => axaddr_wrap(0),
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[10]_i_1_n_0\,
Q => axaddr_wrap(10),
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[11]_i_1_n_0\,
Q => axaddr_wrap(11),
R => '0'
);
\axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(11 downto 8),
S(3) => \axaddr_wrap[11]_i_5_n_0\,
S(2) => \axaddr_wrap[11]_i_6_n_0\,
S(1) => \axaddr_wrap[11]_i_7_n_0\,
S(0) => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[1]_i_1_n_0\,
Q => axaddr_wrap(1),
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[2]_i_1_n_0\,
Q => axaddr_wrap(2),
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[3]_i_1_n_0\,
Q => axaddr_wrap(3),
R => '0'
);
\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => axaddr_wrap(3 downto 0),
O(3 downto 0) => axaddr_wrap0(3 downto 0),
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[4]_i_1_n_0\,
Q => axaddr_wrap(4),
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[5]_i_1_n_0\,
Q => axaddr_wrap(5),
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[6]_i_1_n_0\,
Q => axaddr_wrap(6),
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[7]_i_1_n_0\,
Q => axaddr_wrap(7),
R => '0'
);
\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(7 downto 4),
S(3) => \axaddr_wrap[7]_i_3_n_0\,
S(2) => \axaddr_wrap[7]_i_4_n_0\,
S(1) => \axaddr_wrap[7]_i_5_n_0\,
S(0) => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[8]_i_1_n_0\,
Q => axaddr_wrap(8),
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[9]_i_1_n_0\,
Q => axaddr_wrap(9),
R => '0'
);
\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => Q(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[0]_i_1_n_0\
);
\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => Q(16),
O => \axlen_cnt[1]_i_1_n_0\
);
\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => Q(17),
O => \axlen_cnt[2]_i_1_n_0\
);
\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => Q(18),
O => \axlen_cnt[3]_i_1_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[0]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[1]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[2]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[3]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(0),
I2 => Q(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => Q(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(10),
I2 => Q(14),
I3 => axaddr_incr_reg(6),
I4 => \m_payload_i_reg[38]\,
I5 => Q(10),
O => m_axi_awaddr(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(11),
I2 => Q(14),
I3 => axaddr_incr_reg(7),
I4 => \m_payload_i_reg[38]\,
I5 => Q(11),
O => m_axi_awaddr(11)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(1),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(1),
I3 => Q(14),
I4 => sel_first_reg_2,
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(2),
I2 => Q(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => Q(2),
O => m_axi_awaddr(2)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(3),
I2 => Q(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => Q(3),
O => m_axi_awaddr(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(4),
I2 => Q(14),
I3 => axaddr_incr_reg(0),
I4 => \m_payload_i_reg[38]\,
I5 => Q(4),
O => m_axi_awaddr(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(5),
I2 => Q(14),
I3 => axaddr_incr_reg(1),
I4 => \m_payload_i_reg[38]\,
I5 => Q(5),
O => m_axi_awaddr(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(6),
I2 => Q(14),
I3 => axaddr_incr_reg(2),
I4 => \m_payload_i_reg[38]\,
I5 => Q(6),
O => m_axi_awaddr(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(7),
I2 => Q(14),
I3 => axaddr_incr_reg(3),
I4 => \m_payload_i_reg[38]\,
I5 => Q(7),
O => m_axi_awaddr(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(8),
I2 => Q(14),
I3 => axaddr_incr_reg(4),
I4 => \m_payload_i_reg[38]\,
I5 => Q(8),
O => m_axi_awaddr(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(9),
I2 => Q(14),
I3 => axaddr_incr_reg(5),
I4 => \m_payload_i_reg[38]\,
I5 => Q(9),
O => m_axi_awaddr(9)
);
next_pending_r_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => wrap_boundary_axaddr_r(0),
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(10),
Q => wrap_boundary_axaddr_r(10),
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(11),
Q => wrap_boundary_axaddr_r(11),
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => wrap_boundary_axaddr_r(1),
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => wrap_boundary_axaddr_r(2),
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => wrap_boundary_axaddr_r(3),
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => wrap_boundary_axaddr_r(4),
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => wrap_boundary_axaddr_r(5),
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => wrap_boundary_axaddr_r(6),
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(7),
Q => wrap_boundary_axaddr_r(7),
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(8),
Q => wrap_boundary_axaddr_r(8),
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(9),
Q => wrap_boundary_axaddr_r(9),
R => '0'
);
\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"313D020E"
)
port map (
I0 => \^wrap_second_len_r_reg[3]_0\(0),
I1 => E(0),
I2 => \axaddr_offset_r_reg[3]_1\,
I3 => \m_payload_i_reg[35]\,
I4 => \^wrap_second_len_r_reg[3]_0\(1),
O => wrap_cnt(1)
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => wrap_cnt_r(0),
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_cnt(1),
Q => wrap_cnt_r(1),
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => wrap_cnt_r(2),
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => wrap_cnt_r(3),
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \^wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \^wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \^wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \^wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
port (
sel_first_reg_0 : out STD_LOGIC;
s_axburst_eq0_reg : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_arvalid : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
incr_next_pending : in STD_LOGIC;
\m_payload_i_reg[47]_0\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
\m_payload_i_reg[35]\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_13_b2s_wrap_cmd";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \next_pending_r_i_2__2_n_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_cnt_r[1]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
signal wrap_next_pending : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair4";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0);
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_2\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_2\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_2\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_2\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1__0_n_0\
);
\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4__0_n_0\,
I1 => \wrap_cnt_r_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2__0_n_0\
);
\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \wrap_cnt_r_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \wrap_cnt_r_reg_n_0_[1]\,
O => \axaddr_wrap[11]_i_4__0_n_0\
);
\axaddr_wrap[11]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[11]\,
O => \axaddr_wrap[11]_i_5__0_n_0\
);
\axaddr_wrap[11]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[10]\,
O => \axaddr_wrap[11]_i_6__0_n_0\
);
\axaddr_wrap[11]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[9]\,
O => \axaddr_wrap[11]_i_7__0_n_0\
);
\axaddr_wrap[11]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[8]\,
O => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1__0_n_0\
);
\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[3]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[2]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[1]\,
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[0]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1__0_n_0\
);
\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1__0_n_0\
);
\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[7]\,
O => \axaddr_wrap[7]_i_3__0_n_0\
);
\axaddr_wrap[7]_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[6]\,
O => \axaddr_wrap[7]_i_4__0_n_0\
);
\axaddr_wrap[7]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[5]\,
O => \axaddr_wrap[7]_i_5__0_n_0\
);
\axaddr_wrap[7]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[4]\,
O => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1__0_n_0\
);
\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1__0_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[0]\,
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[10]\,
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[11]\,
R => '0'
);
\axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\,
O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\,
O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\,
O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\,
S(3) => \axaddr_wrap[11]_i_5__0_n_0\,
S(2) => \axaddr_wrap[11]_i_6__0_n_0\,
S(1) => \axaddr_wrap[11]_i_7__0_n_0\,
S(0) => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[1]\,
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[2]\,
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[3]\,
R => '0'
);
\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_wrap_reg_n_0_[3]\,
DI(2) => \axaddr_wrap_reg_n_0_[2]\,
DI(1) => \axaddr_wrap_reg_n_0_[1]\,
DI(0) => \axaddr_wrap_reg_n_0_[0]\,
O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\,
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[4]\,
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[5]\,
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[6]\,
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[7]\,
R => '0'
);
\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\,
S(3) => \axaddr_wrap[7]_i_3__0_n_0\,
S(2) => \axaddr_wrap[7]_i_4__0_n_0\,
S(1) => \axaddr_wrap[7]_i_5__0_n_0\,
S(0) => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[8]\,
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[9]\,
R => '0'
);
\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[0]_i_1__2_n_0\
);
\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__2_n_0\
);
\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__2_n_0\
);
\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__2_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[0]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[10]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_araddr(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[11]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_araddr(11)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[1]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(1),
O => m_axi_araddr(1)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[2]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(2),
O => m_axi_araddr(2)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[3]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_araddr(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[4]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_araddr(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[5]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(5),
O => m_axi_araddr(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(6),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[6]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_araddr(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[7]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_araddr(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[8]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_araddr(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[9]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_araddr(9)
);
\next_pending_r_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEAAFEAE"
)
port map (
I0 => \m_payload_i_reg[47]_0\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep\,
I3 => \next_pending_r_i_2__2_n_0\,
I4 => E(0),
O => wrap_next_pending
);
\next_pending_r_i_2__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFBFBFB00"
)
port map (
I0 => \state_reg[1]\(0),
I1 => si_rs_arvalid,
I2 => \state_reg[1]\(1),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \next_pending_r_i_2__2_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_n_0,
R => '0'
);
\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(14),
I2 => sel_first_i,
I3 => incr_next_pending,
O => s_axburst_eq0_reg
);
\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(14),
I2 => sel_first_i,
I3 => incr_next_pending,
O => s_axburst_eq1_reg
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
R => '0'
);
\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"313D020E"
)
port map (
I0 => \^wrap_second_len_r_reg[3]_0\(0),
I1 => E(0),
I2 => \axaddr_offset_r_reg[3]_1\,
I3 => \m_payload_i_reg[35]\,
I4 => \^wrap_second_len_r_reg[3]_0\(1),
O => \wrap_cnt_r[1]_i_1__0_n_0\
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => \wrap_cnt_r_reg_n_0_[0]\,
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_cnt_r[1]_i_1__0_n_0\,
Q => \wrap_cnt_r_reg_n_0_[1]\,
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => \wrap_cnt_r_reg_n_0_[2]\,
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => \wrap_cnt_r_reg_n_0_[3]\,
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \^wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \^wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \^wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \^wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
port (
s_axi_arready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 47 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\m_axi_araddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
sel_first_0 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \axaddr_incr[0]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3__0_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[48]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[49]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_3__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair13";
begin
Q(47 downto 0) <= \^q\(47 downto 0);
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^m_valid_i_reg_0\,
R => '0'
);
\axaddr_incr[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(0),
I3 => sel_first_0,
I4 => \axaddr_incr_reg[0]_i_11__0_n_7\,
O => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr[0]_i_12__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12__0_n_0\
);
\axaddr_incr[0]_i_13__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13__0_n_0\
);
\axaddr_incr[0]_i_14__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14__0_n_0\
);
\axaddr_incr[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_0,
O => \axaddr_incr[0]_i_3__0_n_0\
);
\axaddr_incr[0]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_0,
O => \axaddr_incr[0]_i_4__0_n_0\
);
\axaddr_incr[0]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first_0,
O => \axaddr_incr[0]_i_5__0_n_0\
);
\axaddr_incr[0]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_0,
O => \axaddr_incr[0]_i_6__0_n_0\
);
\axaddr_incr[0]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(3),
I3 => sel_first_0,
I4 => \axaddr_incr_reg[0]_i_11__0_n_4\,
O => \axaddr_incr[0]_i_7__0_n_0\
);
\axaddr_incr[0]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(2),
I3 => sel_first_0,
I4 => \axaddr_incr_reg[0]_i_11__0_n_5\,
O => \axaddr_incr[0]_i_8__0_n_0\
);
\axaddr_incr[0]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => \axaddr_incr_reg[3]_0\(1),
I3 => sel_first_0,
I4 => \axaddr_incr_reg[0]_i_11__0_n_6\,
O => \axaddr_incr[0]_i_9__0_n_0\
);
\axaddr_incr[4]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr[4]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7__0_n_0\
);
\axaddr_incr[4]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8__0_n_0\
);
\axaddr_incr[4]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9__0_n_0\
);
\axaddr_incr[8]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_incr[8]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7__0_n_0\
);
\axaddr_incr[8]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8__0_n_0\
);
\axaddr_incr[8]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9__0_n_0\
);
\axaddr_incr_reg[0]_i_11__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11__0_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12__0_n_0\,
DI(1) => \axaddr_incr[0]_i_13__0_n_0\,
DI(0) => \axaddr_incr[0]_i_14__0_n_0\,
O(3) => \axaddr_incr_reg[0]_i_11__0_n_4\,
O(2) => \axaddr_incr_reg[0]_i_11__0_n_5\,
O(1) => \axaddr_incr_reg[0]_i_11__0_n_6\,
O(0) => \axaddr_incr_reg[0]_i_11__0_n_7\,
S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0)
);
\axaddr_incr_reg[0]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[7]_0\(0),
CO(2) => \axaddr_incr_reg[0]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3__0_n_0\,
DI(2) => \axaddr_incr[0]_i_4__0_n_0\,
DI(1) => \axaddr_incr[0]_i_5__0_n_0\,
DI(0) => \axaddr_incr[0]_i_6__0_n_0\,
O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
S(3) => \axaddr_incr[0]_i_7__0_n_0\,
S(2) => \axaddr_incr[0]_i_8__0_n_0\,
S(1) => \axaddr_incr[0]_i_9__0_n_0\,
S(0) => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr_reg[4]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7__0_n_0\,
S(2) => \axaddr_incr[4]_i_8__0_n_0\,
S(1) => \axaddr_incr[4]_i_9__0_n_0\,
S(0) => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr_reg[8]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[8]_i_7__0_n_0\,
S(2) => \axaddr_incr[8]_i_8__0_n_0\,
S(1) => \axaddr_incr[8]_i_9__0_n_0\,
S(0) => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
O => \axaddr_offset_r_reg[2]\(0)
);
\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F7F00004F7FFFFF"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \^q\(35),
I2 => \^q\(40),
I3 => \axaddr_offset_r[1]_i_3__0_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[2]_0\(0),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_3__0_n_0\
);
\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"C808FFFFC8080000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \^q\(41),
I2 => \^q\(35),
I3 => \axaddr_offset_r[2]_i_3__0_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[2]_0\(1),
O => \axaddr_offset_r_reg[2]\(1)
);
\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_3__0_n_0\
);
\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]_rep_0\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first_0,
O => \m_axi_araddr[10]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__0_n_0\
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__0_n_0\
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__0_n_0\
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(12),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__0_n_0\
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(13),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__0_n_0\
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(14),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__0_n_0\
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(15),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__0_n_0\
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(16),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__0_n_0\
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(17),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__0_n_0\
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(18),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__0_n_0\
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(19),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__0_n_0\
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__0_n_0\
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(20),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__0_n_0\
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(21),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__0_n_0\
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(22),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__0_n_0\
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(23),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__0_n_0\
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(24),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__0_n_0\
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(25),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__0_n_0\
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(26),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__0_n_0\
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(27),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__0_n_0\
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(28),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__0_n_0\
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(29),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__0_n_0\
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__0_n_0\
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(30),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__0_n_0\
);
\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(31),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_2__0_n_0\
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__0_n_0\
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__0_n_0\
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__0_n_0\
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__1_n_0\
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__0_n_0\
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__0_n_0\
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__0_n_0\
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__0_n_0\
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__0_n_0\
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__0_n_0\
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1__0_n_0\
);
\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1__0_n_0\
);
\m_payload_i[48]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => \m_payload_i[48]_i_1__0_n_0\
);
\m_payload_i[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => \m_payload_i[49]_i_1__0_n_0\
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__0_n_0\
);
\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1__0_n_0\
);
\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1__0_n_0\
);
\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1__0_n_0\
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__0_n_0\
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__0_n_0\
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__0_n_0\
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__0_n_0\
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[11]_i_1__0_n_0\,
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[12]_i_1__0_n_0\,
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[13]_i_1__0_n_0\,
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[14]_i_1__0_n_0\,
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[15]_i_1__0_n_0\,
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[16]_i_1__0_n_0\,
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[17]_i_1__0_n_0\,
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[18]_i_1__0_n_0\,
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[19]_i_1__0_n_0\,
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[20]_i_1__0_n_0\,
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[21]_i_1__0_n_0\,
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[22]_i_1__0_n_0\,
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[23]_i_1__0_n_0\,
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[24]_i_1__0_n_0\,
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[25]_i_1__0_n_0\,
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[26]_i_1__0_n_0\,
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[27]_i_1__0_n_0\,
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[28]_i_1__0_n_0\,
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[29]_i_1__0_n_0\,
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[30]_i_1__0_n_0\,
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[31]_i_2__0_n_0\,
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[32]_i_1__0_n_0\,
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[33]_i_1__0_n_0\,
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[34]_i_1__0_n_0\,
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[35]_i_1__1_n_0\,
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[36]_i_1__0_n_0\,
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[38]_i_1__0_n_0\,
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[39]_i_1__0_n_0\,
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[44]_i_1__0_n_0\,
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[45]_i_1__0_n_0\,
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[46]_i_1__0_n_0\,
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[47]_i_1__0_n_0\,
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[48]_i_1__0_n_0\,
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[49]_i_1__0_n_0\,
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[50]_i_1__0_n_0\,
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[51]_i_1__0_n_0\,
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[53]_i_1__0_n_0\,
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFBBBB"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \^m_valid_i_reg_0\
);
\next_pending_r_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^q\(43),
I1 => \^q\(45),
I2 => \^q\(44),
I3 => \^q\(46),
O => next_pending_r_reg_0
);
\next_pending_r_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \^q\(42),
I2 => \^q\(40),
I3 => \^q\(39),
I4 => \^q\(41),
O => next_pending_r_reg
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_arready\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888028AAAAA028A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(41),
I3 => \^q\(40),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A222A882AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(41),
I5 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_3__0_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r_reg[3]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 is
port (
s_axi_awready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 47 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\m_axi_awaddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[1]_inv\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]_inv_0\ : in STD_LOGIC;
aresetn : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
b_push : in STD_LOGIC;
sel_first : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 is
signal C : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_incr[0]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 53 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_3\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair39";
begin
Q(47 downto 0) <= \^q\(47 downto 0);
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_awready <= \^s_axi_awready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => aresetn,
O => \aresetn_d_reg[1]_inv\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\axaddr_incr[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(0),
I3 => sel_first,
I4 => C(0),
O => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr[0]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12_n_0\
);
\axaddr_incr[0]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13_n_0\
);
\axaddr_incr[0]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14_n_0\
);
\axaddr_incr[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_3_n_0\
);
\axaddr_incr[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_4_n_0\
);
\axaddr_incr[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first,
O => \axaddr_incr[0]_i_5_n_0\
);
\axaddr_incr[0]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_6_n_0\
);
\axaddr_incr[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(3),
I3 => sel_first,
I4 => C(3),
O => \axaddr_incr[0]_i_7_n_0\
);
\axaddr_incr[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(2),
I3 => sel_first,
I4 => C(2),
O => \axaddr_incr[0]_i_8_n_0\
);
\axaddr_incr[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => axaddr_incr_reg(1),
I3 => sel_first,
I4 => C(1),
O => \axaddr_incr[0]_i_9_n_0\
);
\axaddr_incr[4]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr[4]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7_n_0\
);
\axaddr_incr[4]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8_n_0\
);
\axaddr_incr[4]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9_n_0\
);
\axaddr_incr[8]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_incr[8]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7_n_0\
);
\axaddr_incr[8]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8_n_0\
);
\axaddr_incr[8]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9_n_0\
);
\axaddr_incr_reg[0]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12_n_0\,
DI(1) => \axaddr_incr[0]_i_13_n_0\,
DI(0) => \axaddr_incr[0]_i_14_n_0\,
O(3 downto 0) => C(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\axaddr_incr_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => CO(0),
CO(2) => \axaddr_incr_reg[0]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3_n_0\,
DI(2) => \axaddr_incr[0]_i_4_n_0\,
DI(1) => \axaddr_incr[0]_i_5_n_0\,
DI(0) => \axaddr_incr[0]_i_6_n_0\,
O(3 downto 0) => O(3 downto 0),
S(3) => \axaddr_incr[0]_i_7_n_0\,
S(2) => \axaddr_incr[0]_i_8_n_0\,
S(1) => \axaddr_incr[0]_i_9_n_0\,
S(0) => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr_reg[4]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7_n_0\,
S(2) => \axaddr_incr[4]_i_8_n_0\,
S(1) => \axaddr_incr[4]_i_9_n_0\,
S(0) => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr_reg[8]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(7 downto 4),
S(3) => \axaddr_incr[8]_i_7_n_0\,
S(2) => \axaddr_incr[8]_i_8_n_0\,
S(1) => \axaddr_incr[8]_i_9_n_0\,
S(0) => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
O => D(0)
);
\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F7F00004F7FFFFF"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \^q\(35),
I2 => \^q\(40),
I3 => \axaddr_offset_r[1]_i_3_n_0\,
I4 => \state_reg[1]\,
I5 => \axaddr_offset_r_reg[2]\(0),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_3_n_0\
);
\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C808FFFFC8080000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \^q\(41),
I2 => \^q\(35),
I3 => \axaddr_offset_r[2]_i_3_n_0\,
I4 => \state_reg[1]\,
I5 => \axaddr_offset_r_reg[2]\(1),
O => D(1)
);
\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_2_n_0\
);
\axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_3_n_0\
);
\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[1]_0\(0),
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_0\(1),
O => \^axlen_cnt_reg[3]\
);
\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first,
O => \m_axi_awaddr[10]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(12),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(13),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(14),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(15),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(16),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(17),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(18),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(19),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(20),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(21),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(22),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(23),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(24),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(25),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(26),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(27),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(28),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(29),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(30),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(31),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(48),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(49),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]_inv_0\
);
next_pending_r_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(43),
I2 => \^q\(44),
I3 => \^q\(46),
I4 => \^q\(45),
O => next_pending_r_reg
);
\next_pending_r_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
O => \^s_ready_i_reg_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_awvalid,
I1 => \^s_axi_awready\,
I2 => b_push,
I3 => \^m_valid_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_awready\,
R => \^s_ready_i_reg_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888028AAAAA028A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(41),
I3 => \^q\(40),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A222A882AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(41),
I5 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_3_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r_reg[3]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \m_payload_i[0]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^s_axi_bid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \skid_buffer[1]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \skid_buffer[2]_i_1\ : label is "soft_lutpair65";
begin
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
s_axi_bid(0) <= \^s_axi_bid\(0);
s_axi_bresp(1 downto 0) <= \^s_axi_bresp\(1 downto 0);
s_axi_bvalid <= \^s_axi_bvalid\;
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB8B8B800B8B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^m_valid_i_reg_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
I5 => \^s_axi_bresp\(0),
O => \m_payload_i[0]_i_1_n_0\
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB8B8B800B8B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^m_valid_i_reg_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
I5 => \^s_axi_bresp\(1),
O => \m_payload_i[1]_i_1_n_0\
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB8B8B800B8B8"
)
port map (
I0 => \out\(0),
I1 => \^m_valid_i_reg_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
I5 => \^s_axi_bid\(0),
O => \m_payload_i[2]_i_1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i[0]_i_1_n_0\,
Q => \^s_axi_bresp\(0),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i[1]_i_1_n_0\,
Q => \^s_axi_bresp\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i[2]_i_1_n_0\,
Q => \^s_axi_bid\(0),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => si_rs_bvalid,
I3 => \^m_valid_i_reg_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_axi_bvalid\,
R => \aresetn_d_reg[1]_inv\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => si_rs_bvalid,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^m_valid_i_reg_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\skid_buffer[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^m_valid_i_reg_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\skid_buffer[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(0),
I1 => \^m_valid_i_reg_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
s_axi_rvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\cnt_read_reg[0]\ : out STD_LOGIC;
UNCONN_OUT : out STD_LOGIC_VECTOR ( 35 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\cnt_read_reg[4]\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
r_push_r_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
\cnt_read_reg[4]_0\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__2_n_0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[3]_i_2\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_2\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_valid_i_i_1__2\ : label is "soft_lutpair66";
begin
s_axi_rvalid <= \^s_axi_rvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\cnt_read[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[4]\,
O => \cnt_read_reg[0]\
);
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__1_n_0\
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__1_n_0\
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__1_n_0\
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__1_n_0\
);
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(13),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(14),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__1_n_0\
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(15),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__1_n_0\
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(16),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__1_n_0\
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(17),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__1_n_0\
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(18),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__1_n_0\
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(19),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__1_n_0\
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__1_n_0\
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(20),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__1_n_0\
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(21),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__1_n_0\
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(22),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__1_n_0\
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(23),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__1_n_0\
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(24),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__1_n_0\
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(25),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__1_n_0\
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(26),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__1_n_0\
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(27),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__1_n_0\
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(28),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__1_n_0\
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(29),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__1_n_0\
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(30),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(31),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(32),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__1_n_0\
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(33),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__1_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__1_n_0\
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
O => p_1_in
);
\m_payload_i[35]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_2_n_0\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__1_n_0\
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__1_n_0\
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__1_n_0\
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__1_n_0\
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__1_n_0\
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__1_n_0\,
Q => UNCONN_OUT(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__1_n_0\,
Q => UNCONN_OUT(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__1_n_0\,
Q => UNCONN_OUT(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__1_n_0\,
Q => UNCONN_OUT(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_1__1_n_0\,
Q => UNCONN_OUT(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[14]_i_1__1_n_0\,
Q => UNCONN_OUT(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[15]_i_1__1_n_0\,
Q => UNCONN_OUT(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[16]_i_1__1_n_0\,
Q => UNCONN_OUT(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[17]_i_1__1_n_0\,
Q => UNCONN_OUT(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[18]_i_1__1_n_0\,
Q => UNCONN_OUT(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[19]_i_1__1_n_0\,
Q => UNCONN_OUT(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__1_n_0\,
Q => UNCONN_OUT(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[20]_i_1__1_n_0\,
Q => UNCONN_OUT(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[21]_i_1__1_n_0\,
Q => UNCONN_OUT(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[22]_i_1__1_n_0\,
Q => UNCONN_OUT(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[23]_i_1__1_n_0\,
Q => UNCONN_OUT(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[24]_i_1__1_n_0\,
Q => UNCONN_OUT(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[25]_i_1__1_n_0\,
Q => UNCONN_OUT(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[26]_i_1__1_n_0\,
Q => UNCONN_OUT(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[27]_i_1__1_n_0\,
Q => UNCONN_OUT(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[28]_i_1__1_n_0\,
Q => UNCONN_OUT(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[29]_i_1__1_n_0\,
Q => UNCONN_OUT(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__1_n_0\,
Q => UNCONN_OUT(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[30]_i_1__1_n_0\,
Q => UNCONN_OUT(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[31]_i_1__1_n_0\,
Q => UNCONN_OUT(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[32]_i_1__1_n_0\,
Q => UNCONN_OUT(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[33]_i_1__1_n_0\,
Q => UNCONN_OUT(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[34]_i_1__1_n_0\,
Q => UNCONN_OUT(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[35]_i_2_n_0\,
Q => UNCONN_OUT(35),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__1_n_0\,
Q => UNCONN_OUT(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__1_n_0\,
Q => UNCONN_OUT(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__1_n_0\,
Q => UNCONN_OUT(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__1_n_0\,
Q => UNCONN_OUT(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__1_n_0\,
Q => UNCONN_OUT(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__1_n_0\,
Q => UNCONN_OUT(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__1_n_0\,
Q => UNCONN_OUT(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \cnt_read_reg[4]\,
I3 => \^skid_buffer_reg[0]_0\,
O => \m_valid_i_i_1__2_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__2_n_0\,
Q => \^s_axi_rvalid\,
R => \aresetn_d_reg[1]_inv\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => \cnt_read_reg[4]\,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(1),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel is
port (
si_rs_bvalid : out STD_LOGIC;
\cnt_read_reg[0]_rep\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
aclk : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel is
signal bid_fifo_0_n_4 : STD_LOGIC;
signal bid_fifo_0_n_5 : STD_LOGIC;
signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bresp_push : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mhandshake : STD_LOGIC;
signal mhandshake_r : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_bresp_acc : STD_LOGIC;
signal s_bresp_acc0 : STD_LOGIC;
signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
signal shandshake : STD_LOGIC;
signal shandshake_r : STD_LOGIC;
signal \^si_rs_bvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair95";
begin
si_rs_bvalid <= \^si_rs_bvalid\;
bid_fifo_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo
port map (
D(0) => bid_fifo_0_n_4,
Q(1 downto 0) => cnt_read(1 downto 0),
SR(0) => s_bresp_acc0,
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0),
bresp_push => bresp_push,
bvalid_i_reg => bid_fifo_0_n_5,
bvalid_i_reg_0 => \^si_rs_bvalid\,
\cnt_read_reg[0]_rep_0\ => \cnt_read_reg[0]_rep\,
\cnt_read_reg[1]_rep__0_0\ => \cnt_read_reg[1]_rep__0\,
\in\(8 downto 0) => \in\(8 downto 0),
mhandshake_r => mhandshake_r,
\out\(0) => \out\(0),
shandshake_r => shandshake_r,
si_rs_bready => si_rs_bready
);
\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
O => p_0_in(0)
);
\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(1),
I1 => \bresp_cnt_reg__0\(0),
O => p_0_in(1)
);
\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(2),
I1 => \bresp_cnt_reg__0\(0),
I2 => \bresp_cnt_reg__0\(1),
O => p_0_in(2)
);
\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \bresp_cnt_reg__0\(3),
I1 => \bresp_cnt_reg__0\(1),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(2),
O => p_0_in(3)
);
\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(4),
I1 => \bresp_cnt_reg__0\(2),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(3),
O => p_0_in(4)
);
\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => p_0_in(5)
);
\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(6),
I1 => \bresp_cnt[7]_i_3_n_0\,
O => p_0_in(6)
);
\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(7),
I1 => \bresp_cnt[7]_i_3_n_0\,
I2 => \bresp_cnt_reg__0\(6),
O => p_0_in(7)
);
\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => \bresp_cnt[7]_i_3_n_0\
);
\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(0),
Q => \bresp_cnt_reg__0\(0),
R => s_bresp_acc0
);
\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(1),
Q => \bresp_cnt_reg__0\(1),
R => s_bresp_acc0
);
\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(2),
Q => \bresp_cnt_reg__0\(2),
R => s_bresp_acc0
);
\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(3),
Q => \bresp_cnt_reg__0\(3),
R => s_bresp_acc0
);
\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(4),
Q => \bresp_cnt_reg__0\(4),
R => s_bresp_acc0
);
\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(5),
Q => \bresp_cnt_reg__0\(5),
R => s_bresp_acc0
);
\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(6),
Q => \bresp_cnt_reg__0\(6),
R => s_bresp_acc0
);
\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(7),
Q => \bresp_cnt_reg__0\(7),
R => s_bresp_acc0
);
bresp_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\
port map (
D(0) => bid_fifo_0_n_4,
Q(1 downto 0) => cnt_read(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
bresp_push => bresp_push,
\in\(1) => \s_bresp_acc_reg_n_0_[1]\,
\in\(0) => \s_bresp_acc_reg_n_0_[0]\,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
mhandshake => mhandshake,
mhandshake_r => mhandshake_r,
s_bresp_acc => s_bresp_acc,
shandshake_r => shandshake_r,
\skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
);
bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => bid_fifo_0_n_5,
Q => \^si_rs_bvalid\,
R => '0'
);
mhandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => mhandshake,
Q => mhandshake_r,
R => areset_d1
);
\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E2"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[0]\,
I1 => s_bresp_acc,
I2 => m_axi_bresp(0),
I3 => bresp_push,
I4 => areset_d1,
O => \s_bresp_acc[0]_i_1_n_0\
);
\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E2"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[1]\,
I1 => s_bresp_acc,
I2 => m_axi_bresp(1),
I3 => bresp_push,
I4 => areset_d1,
O => \s_bresp_acc[1]_i_1_n_0\
);
\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[0]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[0]\,
R => '0'
);
\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[1]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[1]\,
R => '0'
);
shandshake_r_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^si_rs_bvalid\,
I1 => si_rs_bready,
O => shandshake
);
shandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => shandshake,
Q => shandshake_r,
R => areset_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
port (
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\sel_first__0\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
\state_reg[1]\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 23 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
\next\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC;
\m_payload_i_reg[35]\ : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_16 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd
port map (
CO(0) => CO(0),
D(0) => D(0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(0) => \axlen_cnt_reg[3]\(0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[11]_0\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axlen_cnt_reg[3]_0\ => \axlen_cnt_reg[3]_0\,
incr_next_pending => incr_next_pending,
\m_axi_awaddr[1]\ => incr_cmd_0_n_16,
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(12 downto 9) => Q(23 downto 20),
\m_payload_i_reg[51]\(8 downto 7) => Q(18 downto 17),
\m_payload_i_reg[51]\(6 downto 4) => Q(14 downto 12),
\m_payload_i_reg[51]\(3 downto 0) => Q(3 downto 0),
\next\ => \next\,
next_pending_r_reg_0 => next_pending_r_reg,
sel_first_reg_0 => sel_first_reg_1,
\state_reg[0]\(0) => \state_reg[0]\(0)
);
\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => Q(15),
I2 => s_axburst_eq0,
O => \state_reg[1]\
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd
port map (
E(0) => E(0),
Q(18 downto 14) => Q(19 downto 15),
Q(13 downto 0) => Q(13 downto 0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[3]\(2 downto 1) => \^axaddr_incr_reg[3]\(3 downto 2),
\axaddr_incr_reg[3]\(0) => \^axaddr_incr_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_2\(3 downto 0) => \axaddr_offset_r_reg[3]_1\(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
\next\ => \next\,
next_pending_r_reg_0 => next_pending_r_reg_0,
next_pending_r_reg_1 => next_pending_r_reg_1,
sel_first_reg_0 => \sel_first__0\,
sel_first_reg_1 => sel_first_reg_2,
sel_first_reg_2 => incr_cmd_0_n_16,
\state_reg[0]\(0) => \state_reg[0]\(0),
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
port (
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
r_rlast : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
\axlen_cnt_reg[5]\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
sel_first_reg_4 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 21 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_arvalid : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]_0\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[48]\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC;
\m_payload_i_reg[35]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_13_b2s_cmd_translator";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_20 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
signal wrap_cmd_0_n_1 : STD_LOGIC;
signal wrap_cmd_0_n_2 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair5";
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2
port map (
CO(0) => CO(0),
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(3 downto 0) => Q(3 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]_0\(6 downto 2) => axaddr_incr_reg(11 downto 7),
\axaddr_incr_reg[11]_0\(1 downto 0) => axaddr_incr_reg(5 downto 4),
\axaddr_incr_reg[11]_1\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axlen_cnt_reg[5]_0\ => \axlen_cnt_reg[5]\,
\axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]\,
incr_next_pending => incr_next_pending,
\m_axi_araddr[6]\ => incr_cmd_0_n_20,
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\,
\m_payload_i_reg[48]\ => \m_payload_i_reg[48]\,
\m_payload_i_reg[51]\(10 downto 9) => \m_payload_i_reg[51]\(21 downto 20),
\m_payload_i_reg[51]\(8) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(7 downto 5) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(4) => \m_payload_i_reg[51]\(6),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
sel_first_reg_0 => sel_first_reg_2,
sel_first_reg_1 => sel_first_reg_3,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\
);
r_rlast_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => s_axburst_eq0,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq1,
O => r_rlast
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_cmd_0_n_1,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_cmd_0_n_2,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3
port map (
E(0) => E(0),
aclk => aclk,
\axaddr_incr_reg[11]\(6 downto 2) => axaddr_incr_reg(11 downto 7),
\axaddr_incr_reg[11]\(1 downto 0) => axaddr_incr_reg(5 downto 4),
\axaddr_incr_reg[3]\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_2\(3 downto 0) => \axaddr_offset_r_reg[3]_1\(3 downto 0),
incr_next_pending => incr_next_pending,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
s_axburst_eq0_reg => wrap_cmd_0_n_1,
s_axburst_eq1_reg => wrap_cmd_0_n_2,
sel_first_i => sel_first_i,
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_4,
sel_first_reg_2 => incr_cmd_0_n_20,
si_rs_arvalid => si_rs_arvalid,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel is
port (
m_valid_i_reg : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\skid_buffer_reg[35]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
r_rlast : in STD_LOGIC;
s_arid_r : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
areset_d1 : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal r_push_r : STD_LOGIC;
signal rd_data_fifo_0_n_0 : STD_LOGIC;
signal rd_data_fifo_0_n_2 : STD_LOGIC;
signal rd_data_fifo_0_n_3 : STD_LOGIC;
signal rd_data_fifo_0_n_5 : STD_LOGIC;
signal trans_in : STD_LOGIC_VECTOR ( 1 downto 0 );
signal transaction_fifo_0_n_2 : STD_LOGIC;
signal wr_en0 : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => s_arid_r,
Q => trans_in(1),
R => '0'
);
r_push_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \state_reg[1]_rep_0\,
Q => r_push_r,
R => '0'
);
r_rlast_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_rlast,
Q => trans_in(0),
R => '0'
);
rd_data_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[3]_rep__2_0\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_0\ => \^m_valid_i_reg\,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_3,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\(33 downto 0) => \out\(33 downto 0),
s_ready_i_reg => s_ready_i_reg,
s_ready_i_reg_0 => transaction_fifo_0_n_2,
si_rs_rready => si_rs_rready,
\state_reg[1]_rep\ => rd_data_fifo_0_n_5,
wr_en0 => wr_en0
);
transaction_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[0]_rep__2\ => rd_data_fifo_0_n_5,
\cnt_read_reg[0]_rep__2_0\ => rd_data_fifo_0_n_3,
\cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2\ => transaction_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\in\(1 downto 0) => trans_in(1 downto 0),
m_valid_i_reg => \^m_valid_i_reg\,
r_push_r => r_push_r,
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[35]\(1 downto 0) => \skid_buffer_reg[35]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wr_en0 => wr_en0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
port (
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
si_rs_awvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
si_rs_bready : out STD_LOGIC;
si_rs_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
si_rs_rready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 47 downto 0 );
\s_arid_r_reg[0]\ : out STD_LOGIC_VECTOR ( 47 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[1]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC;
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\cnt_read_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[0]_0\ : out STD_LOGIC;
\m_axi_awaddr[10]\ : out STD_LOGIC;
\m_axi_araddr[10]\ : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
UNCONN_OUT : out STD_LOGIC_VECTOR ( 35 downto 0 );
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
\cnt_read_reg[4]\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
b_push : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
sel_first : in STD_LOGIC;
sel_first_0 : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
r_push_r_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
\cnt_read_reg[4]_0\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
signal ar_pipe_n_2 : STD_LOGIC;
signal aw_pipe_n_1 : STD_LOGIC;
signal aw_pipe_n_81 : STD_LOGIC;
begin
ar_pipe: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice
port map (
Q(47 downto 0) => \s_arid_r_reg[0]\(47 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[0]_0\ => aw_pipe_n_81,
\axaddr_incr_reg[11]\(3 downto 0) => \axaddr_incr_reg[11]_0\(3 downto 0),
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_incr_reg[3]_0\(3 downto 0) => \axaddr_incr_reg[3]_0\(3 downto 0),
\axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
\axaddr_incr_reg[7]_0\(0) => \axaddr_incr_reg[7]_0\(0),
\axaddr_offset_r_reg[0]\ => \axaddr_offset_r_reg[0]_0\,
\axaddr_offset_r_reg[1]\ => \axaddr_offset_r_reg[1]_0\,
\axaddr_offset_r_reg[2]\(1 downto 0) => \axaddr_offset_r_reg[2]\(1 downto 0),
\axaddr_offset_r_reg[2]_0\(1 downto 0) => \axaddr_offset_r_reg[2]_1\(1 downto 0),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\,
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\,
\m_axi_araddr[10]\ => \m_axi_araddr[10]\,
\m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
m_valid_i_reg_0 => ar_pipe_n_2,
m_valid_i_reg_1(0) => m_valid_i_reg(0),
next_pending_r_reg => next_pending_r_reg_1,
next_pending_r_reg_0 => next_pending_r_reg_2,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => si_rs_arvalid,
sel_first_0 => sel_first_0,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0),
\wrap_second_len_r_reg[3]\ => \wrap_second_len_r_reg[3]_0\
);
aw_pipe: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0
port map (
CO(0) => CO(0),
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(47 downto 0) => Q(47 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]_inv\ => aw_pipe_n_81,
\aresetn_d_reg[1]_inv_0\ => ar_pipe_n_2,
axaddr_incr_reg(3 downto 0) => axaddr_incr_reg(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => \axaddr_incr_reg[11]\(7 downto 0),
\axaddr_offset_r_reg[0]\ => \axaddr_offset_r_reg[0]\,
\axaddr_offset_r_reg[1]\ => \axaddr_offset_r_reg[1]\,
\axaddr_offset_r_reg[2]\(1 downto 0) => \axaddr_offset_r_reg[2]_0\(1 downto 0),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]\,
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\,
b_push => b_push,
\m_axi_awaddr[10]\ => \m_axi_awaddr[10]\,
m_valid_i_reg_0 => si_rs_awvalid,
next_pending_r_reg => next_pending_r_reg,
next_pending_r_reg_0 => next_pending_r_reg_0,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg_0 => aw_pipe_n_1,
sel_first => sel_first,
\state_reg[1]\ => \state_reg[1]\,
\state_reg[1]_0\(1 downto 0) => \state_reg[1]_0\(1 downto 0),
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
\wrap_second_len_r_reg[3]\ => \wrap_second_len_r_reg[3]\
);
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
m_valid_i_reg_0 => si_rs_bready,
\out\(0) => \out\(0),
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0),
si_rs_bvalid => si_rs_bvalid
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
UNCONN_OUT(35 downto 0) => UNCONN_OUT(35 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\cnt_read_reg[0]\ => \cnt_read_reg[0]\,
\cnt_read_reg[4]\ => \cnt_read_reg[4]\,
\cnt_read_reg[4]_0\(33 downto 0) => \cnt_read_reg[4]_0\(33 downto 0),
r_push_r_reg(1 downto 0) => r_push_r_reg(1 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\skid_buffer_reg[0]_0\ => si_rs_rready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel is
port (
s_arid_r : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arvalid : out STD_LOGIC;
r_rlast : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 24 downto 0 );
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[2]\ : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC;
\m_payload_i_reg[35]_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[47]_0\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[48]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel is
signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
signal ar_cmd_fsm_0_n_11 : STD_LOGIC;
signal ar_cmd_fsm_0_n_12 : STD_LOGIC;
signal ar_cmd_fsm_0_n_13 : STD_LOGIC;
signal ar_cmd_fsm_0_n_14 : STD_LOGIC;
signal ar_cmd_fsm_0_n_22 : STD_LOGIC;
signal ar_cmd_fsm_0_n_23 : STD_LOGIC;
signal ar_cmd_fsm_0_n_26 : STD_LOGIC;
signal ar_cmd_fsm_0_n_27 : STD_LOGIC;
signal ar_cmd_fsm_0_n_6 : STD_LOGIC;
signal ar_cmd_fsm_0_n_7 : STD_LOGIC;
signal ar_cmd_fsm_0_n_8 : STD_LOGIC;
signal ar_cmd_fsm_0_n_9 : STD_LOGIC;
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_12 : STD_LOGIC;
signal cmd_translator_0_n_14 : STD_LOGIC;
signal cmd_translator_0_n_15 : STD_LOGIC;
signal cmd_translator_0_n_6 : STD_LOGIC;
signal cmd_translator_0_n_7 : STD_LOGIC;
signal cmd_translator_0_n_8 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
r_push_r_reg <= \^r_push_r_reg\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
ar_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm
port map (
D(3) => ar_cmd_fsm_0_n_6,
D(2) => ar_cmd_fsm_0_n_7,
D(1) => ar_cmd_fsm_0_n_8,
D(0) => ar_cmd_fsm_0_n_9,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => state(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => ar_cmd_fsm_0_n_23,
axaddr_offset(1) => \wrap_cmd_0/axaddr_offset\(3),
axaddr_offset(0) => \wrap_cmd_0/axaddr_offset\(0),
\axaddr_offset_r_reg[3]\(1) => \wrap_cmd_0/axaddr_offset_r\(3),
\axaddr_offset_r_reg[3]\(0) => \wrap_cmd_0/axaddr_offset_r\(0),
\axaddr_wrap_reg[11]\(0) => ar_cmd_fsm_0_n_22,
\axlen_cnt_reg[3]\ => cmd_translator_0_n_11,
\axlen_cnt_reg[4]\ => cmd_translator_0_n_15,
\axlen_cnt_reg[5]\ => ar_cmd_fsm_0_n_0,
\axlen_cnt_reg[6]\(3) => cmd_translator_0_n_7,
\axlen_cnt_reg[6]\(2) => cmd_translator_0_n_8,
\axlen_cnt_reg[6]\(1) => cmd_translator_0_n_9,
\axlen_cnt_reg[6]\(0) => cmd_translator_0_n_10,
\axlen_cnt_reg[7]\ => cmd_translator_0_n_12,
\cnt_read_reg[2]\ => \cnt_read_reg[2]\,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \m_payload_i_reg[0]\,
\m_payload_i_reg[0]_0\ => \m_payload_i_reg[0]_0\,
\m_payload_i_reg[0]_1\(0) => E(0),
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[35]_0\ => \m_payload_i_reg[35]_0\,
\m_payload_i_reg[3]\ => \m_payload_i_reg[3]\,
\m_payload_i_reg[46]\(0) => \m_payload_i_reg[46]\(1),
\m_payload_i_reg[50]\(4 downto 3) => Q(22 downto 21),
\m_payload_i_reg[50]\(2) => Q(19),
\m_payload_i_reg[50]\(1 downto 0) => Q(17 downto 16),
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
r_push_r_reg => \^r_push_r_reg\,
s_axburst_eq1_reg => cmd_translator_0_n_14,
sel_first_i => sel_first_i,
sel_first_reg => ar_cmd_fsm_0_n_26,
sel_first_reg_0 => ar_cmd_fsm_0_n_27,
sel_first_reg_1 => cmd_translator_0_n_0,
sel_first_reg_2 => \^sel_first\,
sel_first_reg_3 => cmd_translator_0_n_6,
si_rs_arvalid => si_rs_arvalid,
\wrap_cnt_r_reg[0]\ => ar_cmd_fsm_0_n_14,
\wrap_cnt_r_reg[3]\(2) => ar_cmd_fsm_0_n_11,
\wrap_cnt_r_reg[3]\(1) => ar_cmd_fsm_0_n_12,
\wrap_cnt_r_reg[3]\(0) => ar_cmd_fsm_0_n_13,
\wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_cmd_0/wrap_second_len\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_cmd_0/wrap_second_len_r\(3 downto 0)
);
cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1
port map (
CO(0) => CO(0),
D(3) => ar_cmd_fsm_0_n_6,
D(2) => ar_cmd_fsm_0_n_7,
D(1) => ar_cmd_fsm_0_n_8,
D(0) => ar_cmd_fsm_0_n_9,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(3) => cmd_translator_0_n_7,
Q(2) => cmd_translator_0_n_8,
Q(1) => cmd_translator_0_n_9,
Q(0) => cmd_translator_0_n_10,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3) => \wrap_cmd_0/axaddr_offset_r\(3),
\axaddr_offset_r_reg[3]\(2 downto 1) => \axaddr_offset_r_reg[2]\(1 downto 0),
\axaddr_offset_r_reg[3]\(0) => \wrap_cmd_0/axaddr_offset_r\(0),
\axaddr_offset_r_reg[3]_0\ => ar_cmd_fsm_0_n_14,
\axaddr_offset_r_reg[3]_1\(3) => \wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_1\(2 downto 1) => \m_payload_i_reg[46]\(1 downto 0),
\axaddr_offset_r_reg[3]_1\(0) => \wrap_cmd_0/axaddr_offset\(0),
\axlen_cnt_reg[5]\ => cmd_translator_0_n_15,
\axlen_cnt_reg[7]\ => cmd_translator_0_n_11,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\,
\m_payload_i_reg[48]\ => \m_payload_i_reg[48]\,
\m_payload_i_reg[51]\(21) => Q(23),
\m_payload_i_reg[51]\(20 downto 0) => Q(20 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => D(6 downto 0),
m_valid_i_reg(0) => ar_cmd_fsm_0_n_22,
next_pending_r_reg => cmd_translator_0_n_12,
r_rlast => r_rlast,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_0,
sel_first_reg_1 => cmd_translator_0_n_6,
sel_first_reg_2 => ar_cmd_fsm_0_n_23,
sel_first_reg_3 => ar_cmd_fsm_0_n_26,
sel_first_reg_4 => ar_cmd_fsm_0_n_27,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]\ => ar_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => cmd_translator_0_n_14,
\state_reg[1]\(1 downto 0) => state(1 downto 0),
\state_reg[1]_rep\ => \^r_push_r_reg\,
\wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_cmd_0/wrap_second_len_r\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_cmd_0/wrap_second_len\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(2) => ar_cmd_fsm_0_n_11,
\wrap_second_len_r_reg[3]_1\(1) => ar_cmd_fsm_0_n_12,
\wrap_second_len_r_reg[3]_1\(0) => ar_cmd_fsm_0_n_13
);
\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(24),
Q => s_arid_r,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel is
port (
\in\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
sel_first_reg : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 24 downto 0 );
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
si_rs_awvalid : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC;
\m_payload_i_reg[35]_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[48]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\cnt_read_reg[0]_rep\ : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel is
signal aw_cmd_fsm_0_n_14 : STD_LOGIC;
signal aw_cmd_fsm_0_n_18 : STD_LOGIC;
signal aw_cmd_fsm_0_n_20 : STD_LOGIC;
signal aw_cmd_fsm_0_n_24 : STD_LOGIC;
signal aw_cmd_fsm_0_n_25 : STD_LOGIC;
signal aw_cmd_fsm_0_n_5 : STD_LOGIC;
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_12 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \next\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sel_first\ : STD_LOGIC;
signal \sel_first__0\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wrap_next_pending : STD_LOGIC;
begin
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
aw_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm
port map (
D(2 downto 1) => wrap_cnt(3 downto 2),
D(0) => wrap_cnt(0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => sel_first_reg(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
axaddr_offset(1) => \wrap_cmd_0/axaddr_offset\(3),
axaddr_offset(0) => \wrap_cmd_0/axaddr_offset\(0),
\axaddr_offset_r_reg[3]\(1) => \wrap_cmd_0/axaddr_offset_r\(3),
\axaddr_offset_r_reg[3]\(0) => \wrap_cmd_0/axaddr_offset_r\(0),
\axaddr_wrap_reg[0]\(0) => aw_cmd_fsm_0_n_20,
\axlen_cnt_reg[0]\(0) => p_1_in(0),
\axlen_cnt_reg[0]_0\(0) => cmd_translator_0_n_9,
\axlen_cnt_reg[2]\ => cmd_translator_0_n_12,
\axlen_cnt_reg[4]\ => cmd_translator_0_n_10,
b_push => b_push,
\cnt_read_reg[0]_rep\ => \cnt_read_reg[0]_rep\,
\cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\,
incr_next_pending => incr_next_pending,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[0]\(0) => E(0),
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[35]_0\ => \m_payload_i_reg[35]_0\,
\m_payload_i_reg[3]\ => \m_payload_i_reg[3]\,
\m_payload_i_reg[46]\(0) => D(1),
\m_payload_i_reg[46]_0\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\(2) => Q(19),
\m_payload_i_reg[47]\(1 downto 0) => Q(16 downto 15),
\m_payload_i_reg[48]\ => \m_payload_i_reg[48]\,
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
s_axburst_eq0_reg => aw_cmd_fsm_0_n_14,
s_axburst_eq1_reg => aw_cmd_fsm_0_n_18,
s_axburst_eq1_reg_0 => cmd_translator_0_n_11,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg => aw_cmd_fsm_0_n_24,
sel_first_reg_0 => aw_cmd_fsm_0_n_25,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
si_rs_awvalid => si_rs_awvalid,
\wrap_cnt_r_reg[0]\ => aw_cmd_fsm_0_n_5,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_cmd_0/wrap_second_len\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_cmd_0/wrap_second_len_r\(3 downto 0)
);
cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator
port map (
CO(0) => CO(0),
D(0) => p_1_in(0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(23 downto 0) => Q(23 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3) => \wrap_cmd_0/axaddr_offset_r\(3),
\axaddr_offset_r_reg[3]\(2 downto 1) => \axaddr_offset_r_reg[2]\(1 downto 0),
\axaddr_offset_r_reg[3]\(0) => \wrap_cmd_0/axaddr_offset_r\(0),
\axaddr_offset_r_reg[3]_0\ => aw_cmd_fsm_0_n_5,
\axaddr_offset_r_reg[3]_1\(3) => \wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_1\(2 downto 1) => D(1 downto 0),
\axaddr_offset_r_reg[3]_1\(0) => \wrap_cmd_0/axaddr_offset\(0),
\axlen_cnt_reg[3]\(0) => cmd_translator_0_n_9,
\axlen_cnt_reg[3]_0\ => cmd_translator_0_n_10,
incr_next_pending => incr_next_pending,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_14,
\m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_18,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
next_pending_r_reg_1 => cmd_translator_0_n_12,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => aw_cmd_fsm_0_n_24,
sel_first_reg_2 => aw_cmd_fsm_0_n_25,
\state_reg[0]\(0) => aw_cmd_fsm_0_n_20,
\state_reg[1]\ => cmd_translator_0_n_11,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_cmd_0/wrap_second_len_r\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => wrap_cnt(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => wrap_cnt(0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_cmd_0/wrap_second_len\(3 downto 0)
);
\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(24),
Q => \in\(8),
R => '0'
);
\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(16),
Q => \in\(0),
R => '0'
);
\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(17),
Q => \in\(1),
R => '0'
);
\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(18),
Q => \in\(2),
R => '0'
);
\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(19),
Q => \in\(3),
R => '0'
);
\s_awlen_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(20),
Q => \in\(4),
R => '0'
);
\s_awlen_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(21),
Q => \in\(5),
R => '0'
);
\s_awlen_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(22),
Q => \in\(6),
R => '0'
);
\s_awlen_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(23),
Q => \in\(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
UNCONN_OUT : out STD_LOGIC_VECTOR ( 35 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_bready : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
aresetn : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s is
signal C : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \RD.ar_channel_0_n_27\ : STD_LOGIC;
signal \RD.ar_channel_0_n_28\ : STD_LOGIC;
signal \RD.ar_channel_0_n_29\ : STD_LOGIC;
signal \RD.ar_channel_0_n_30\ : STD_LOGIC;
signal \RD.ar_channel_0_n_6\ : STD_LOGIC;
signal \RD.ar_channel_0_n_7\ : STD_LOGIC;
signal \RD.ar_channel_0_n_8\ : STD_LOGIC;
signal \RD.ar_channel_0_n_9\ : STD_LOGIC;
signal \RD.r_channel_0_n_0\ : STD_LOGIC;
signal \RD.r_channel_0_n_1\ : STD_LOGIC;
signal SI_REG_n_10 : STD_LOGIC;
signal SI_REG_n_11 : STD_LOGIC;
signal SI_REG_n_112 : STD_LOGIC;
signal SI_REG_n_113 : STD_LOGIC;
signal SI_REG_n_114 : STD_LOGIC;
signal SI_REG_n_115 : STD_LOGIC;
signal SI_REG_n_116 : STD_LOGIC;
signal SI_REG_n_117 : STD_LOGIC;
signal SI_REG_n_118 : STD_LOGIC;
signal SI_REG_n_119 : STD_LOGIC;
signal SI_REG_n_12 : STD_LOGIC;
signal SI_REG_n_120 : STD_LOGIC;
signal SI_REG_n_121 : STD_LOGIC;
signal SI_REG_n_122 : STD_LOGIC;
signal SI_REG_n_123 : STD_LOGIC;
signal SI_REG_n_124 : STD_LOGIC;
signal SI_REG_n_125 : STD_LOGIC;
signal SI_REG_n_126 : STD_LOGIC;
signal SI_REG_n_127 : STD_LOGIC;
signal SI_REG_n_128 : STD_LOGIC;
signal SI_REG_n_129 : STD_LOGIC;
signal SI_REG_n_132 : STD_LOGIC;
signal SI_REG_n_133 : STD_LOGIC;
signal SI_REG_n_134 : STD_LOGIC;
signal SI_REG_n_135 : STD_LOGIC;
signal SI_REG_n_136 : STD_LOGIC;
signal SI_REG_n_139 : STD_LOGIC;
signal SI_REG_n_140 : STD_LOGIC;
signal SI_REG_n_141 : STD_LOGIC;
signal SI_REG_n_142 : STD_LOGIC;
signal SI_REG_n_143 : STD_LOGIC;
signal SI_REG_n_144 : STD_LOGIC;
signal SI_REG_n_145 : STD_LOGIC;
signal SI_REG_n_146 : STD_LOGIC;
signal SI_REG_n_147 : STD_LOGIC;
signal SI_REG_n_148 : STD_LOGIC;
signal SI_REG_n_149 : STD_LOGIC;
signal SI_REG_n_150 : STD_LOGIC;
signal SI_REG_n_151 : STD_LOGIC;
signal SI_REG_n_152 : STD_LOGIC;
signal SI_REG_n_153 : STD_LOGIC;
signal SI_REG_n_154 : STD_LOGIC;
signal SI_REG_n_155 : STD_LOGIC;
signal SI_REG_n_156 : STD_LOGIC;
signal SI_REG_n_157 : STD_LOGIC;
signal SI_REG_n_158 : STD_LOGIC;
signal SI_REG_n_159 : STD_LOGIC;
signal SI_REG_n_160 : STD_LOGIC;
signal SI_REG_n_161 : STD_LOGIC;
signal SI_REG_n_162 : STD_LOGIC;
signal SI_REG_n_163 : STD_LOGIC;
signal SI_REG_n_164 : STD_LOGIC;
signal SI_REG_n_18 : STD_LOGIC;
signal SI_REG_n_57 : STD_LOGIC;
signal SI_REG_n_58 : STD_LOGIC;
signal SI_REG_n_59 : STD_LOGIC;
signal SI_REG_n_60 : STD_LOGIC;
signal SI_REG_n_66 : STD_LOGIC;
signal SI_REG_n_9 : STD_LOGIC;
signal \WR.aw_channel_0_n_14\ : STD_LOGIC;
signal \WR.aw_channel_0_n_34\ : STD_LOGIC;
signal \WR.aw_channel_0_n_35\ : STD_LOGIC;
signal \WR.aw_channel_0_n_36\ : STD_LOGIC;
signal \WR.aw_channel_0_n_37\ : STD_LOGIC;
signal \WR.b_channel_0_n_1\ : STD_LOGIC;
signal \WR.b_channel_0_n_2\ : STD_LOGIC;
signal \ar_pipe/p_1_in\ : STD_LOGIC;
signal areset_d1 : STD_LOGIC;
signal areset_d1_i_1_n_0 : STD_LOGIC;
signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \aw_pipe/p_1_in\ : STD_LOGIC;
signal b_awid : STD_LOGIC;
signal b_awlen : STD_LOGIC_VECTOR ( 7 downto 0 );
signal b_push : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/sel_first\ : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/sel_first_2\ : STD_LOGIC;
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_1\ : STD_LOGIC_VECTOR ( 2 downto 1 );
signal r_rlast : STD_LOGIC;
signal s_arid : STD_LOGIC;
signal s_arid_r : STD_LOGIC;
signal s_awid : STD_LOGIC;
signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_arvalid : STD_LOGIC;
signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_awvalid : STD_LOGIC;
signal si_rs_bid : STD_LOGIC;
signal si_rs_bready : STD_LOGIC;
signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_bvalid : STD_LOGIC;
signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal si_rs_rid : STD_LOGIC;
signal si_rs_rlast : STD_LOGIC;
signal si_rs_rready : STD_LOGIC;
signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\RD.ar_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel
port map (
CO(0) => SI_REG_n_125,
D(6) => SI_REG_n_155,
D(5) => SI_REG_n_156,
D(4) => SI_REG_n_157,
D(3) => SI_REG_n_158,
D(2) => SI_REG_n_159,
D(1) => SI_REG_n_160,
D(0) => SI_REG_n_161,
E(0) => \ar_pipe/p_1_in\,
O(3) => SI_REG_n_126,
O(2) => SI_REG_n_127,
O(1) => SI_REG_n_128,
O(0) => SI_REG_n_129,
Q(24) => s_arid,
Q(23) => SI_REG_n_57,
Q(22) => SI_REG_n_58,
Q(21) => SI_REG_n_59,
Q(20) => SI_REG_n_60,
Q(19 downto 16) => si_rs_arlen(3 downto 0),
Q(15) => si_rs_arburst(1),
Q(14) => SI_REG_n_66,
Q(13 downto 12) => si_rs_arsize(1 downto 0),
Q(11 downto 0) => si_rs_araddr(11 downto 0),
S(3) => \RD.ar_channel_0_n_27\,
S(2) => \RD.ar_channel_0_n_28\,
S(1) => \RD.ar_channel_0_n_29\,
S(0) => \RD.ar_channel_0_n_30\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
\axaddr_offset_r_reg[2]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(2 downto 1),
\cnt_read_reg[2]\ => \RD.r_channel_0_n_1\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \RD.ar_channel_0_n_8\,
\m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_9\,
\m_payload_i_reg[11]\(3) => SI_REG_n_121,
\m_payload_i_reg[11]\(2) => SI_REG_n_122,
\m_payload_i_reg[11]\(1) => SI_REG_n_123,
\m_payload_i_reg[11]\(0) => SI_REG_n_124,
\m_payload_i_reg[35]\ => SI_REG_n_139,
\m_payload_i_reg[35]_0\ => SI_REG_n_141,
\m_payload_i_reg[38]\ => SI_REG_n_164,
\m_payload_i_reg[3]\ => SI_REG_n_162,
\m_payload_i_reg[3]_0\(3) => SI_REG_n_117,
\m_payload_i_reg[3]_0\(2) => SI_REG_n_118,
\m_payload_i_reg[3]_0\(1) => SI_REG_n_119,
\m_payload_i_reg[3]_0\(0) => SI_REG_n_120,
\m_payload_i_reg[46]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 1),
\m_payload_i_reg[47]\ => SI_REG_n_142,
\m_payload_i_reg[47]_0\ => SI_REG_n_140,
\m_payload_i_reg[48]\ => SI_REG_n_143,
\m_payload_i_reg[6]\ => SI_REG_n_154,
r_push_r_reg => \RD.ar_channel_0_n_7\,
r_rlast => r_rlast,
s_arid_r => s_arid_r,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
\wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_6\
);
\RD.r_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \RD.r_channel_0_n_0\,
\out\(33 downto 32) => si_rs_rresp(1 downto 0),
\out\(31 downto 0) => si_rs_rdata(31 downto 0),
r_rlast => r_rlast,
s_arid_r => s_arid_r,
s_ready_i_reg => SI_REG_n_144,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[35]\(1) => si_rs_rid,
\skid_buffer_reg[35]\(0) => si_rs_rlast,
\state_reg[1]_rep\ => \RD.r_channel_0_n_1\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_7\
);
SI_REG: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice
port map (
CO(0) => SI_REG_n_112,
D(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 1),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_113,
O(2) => SI_REG_n_114,
O(1) => SI_REG_n_115,
O(0) => SI_REG_n_116,
Q(47) => s_awid,
Q(46) => SI_REG_n_9,
Q(45) => SI_REG_n_10,
Q(44) => SI_REG_n_11,
Q(43) => SI_REG_n_12,
Q(42 downto 39) => si_rs_awlen(3 downto 0),
Q(38) => si_rs_awburst(1),
Q(37) => SI_REG_n_18,
Q(36 downto 35) => si_rs_awsize(1 downto 0),
Q(34 downto 12) => Q(22 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_34\,
S(2) => \WR.aw_channel_0_n_35\,
S(1) => \WR.aw_channel_0_n_36\,
S(0) => \WR.aw_channel_0_n_37\,
UNCONN_OUT(35 downto 0) => UNCONN_OUT(35 downto 0),
aclk => aclk,
aresetn => aresetn,
axaddr_incr_reg(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_3\(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => C(11 downto 4),
\axaddr_incr_reg[11]_0\(3) => SI_REG_n_121,
\axaddr_incr_reg[11]_0\(2) => SI_REG_n_122,
\axaddr_incr_reg[11]_0\(1) => SI_REG_n_123,
\axaddr_incr_reg[11]_0\(0) => SI_REG_n_124,
\axaddr_incr_reg[3]\(3) => SI_REG_n_126,
\axaddr_incr_reg[3]\(2) => SI_REG_n_127,
\axaddr_incr_reg[3]\(1) => SI_REG_n_128,
\axaddr_incr_reg[3]\(0) => SI_REG_n_129,
\axaddr_incr_reg[3]_0\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
\axaddr_incr_reg[7]\(3) => SI_REG_n_117,
\axaddr_incr_reg[7]\(2) => SI_REG_n_118,
\axaddr_incr_reg[7]\(1) => SI_REG_n_119,
\axaddr_incr_reg[7]\(0) => SI_REG_n_120,
\axaddr_incr_reg[7]_0\(0) => SI_REG_n_125,
\axaddr_offset_r_reg[0]\ => SI_REG_n_153,
\axaddr_offset_r_reg[0]_0\ => SI_REG_n_162,
\axaddr_offset_r_reg[1]\ => SI_REG_n_132,
\axaddr_offset_r_reg[1]_0\ => SI_REG_n_139,
\axaddr_offset_r_reg[2]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 1),
\axaddr_offset_r_reg[2]_0\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_1\(2 downto 1),
\axaddr_offset_r_reg[2]_1\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(2 downto 1),
\axaddr_offset_r_reg[3]\ => SI_REG_n_145,
\axaddr_offset_r_reg[3]_0\ => SI_REG_n_154,
\axlen_cnt_reg[3]\ => SI_REG_n_134,
\axlen_cnt_reg[3]_0\ => SI_REG_n_142,
b_push => b_push,
\cnt_read_reg[0]\ => SI_REG_n_144,
\cnt_read_reg[4]\ => \RD.r_channel_0_n_0\,
\cnt_read_reg[4]_0\(33 downto 32) => si_rs_rresp(1 downto 0),
\cnt_read_reg[4]_0\(31 downto 0) => si_rs_rdata(31 downto 0),
\m_axi_araddr[10]\ => SI_REG_n_164,
\m_axi_awaddr[10]\ => SI_REG_n_163,
\m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_27\,
\m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_28\,
\m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_29\,
\m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_30\,
m_valid_i_reg(0) => \ar_pipe/p_1_in\,
next_pending_r_reg => SI_REG_n_135,
next_pending_r_reg_0 => SI_REG_n_136,
next_pending_r_reg_1 => SI_REG_n_140,
next_pending_r_reg_2 => SI_REG_n_143,
\out\(0) => si_rs_bid,
r_push_r_reg(1) => si_rs_rid,
r_push_r_reg(0) => si_rs_rlast,
\s_arid_r_reg[0]\(47) => s_arid,
\s_arid_r_reg[0]\(46) => SI_REG_n_57,
\s_arid_r_reg[0]\(45) => SI_REG_n_58,
\s_arid_r_reg[0]\(44) => SI_REG_n_59,
\s_arid_r_reg[0]\(43) => SI_REG_n_60,
\s_arid_r_reg[0]\(42 downto 39) => si_rs_arlen(3 downto 0),
\s_arid_r_reg[0]\(38) => si_rs_arburst(1),
\s_arid_r_reg[0]\(37) => SI_REG_n_66,
\s_arid_r_reg[0]\(36 downto 35) => si_rs_arsize(1 downto 0),
\s_arid_r_reg[0]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0),
\s_arid_r_reg[0]\(11 downto 0) => si_rs_araddr(11 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_2\,
sel_first_0 => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
si_rs_awvalid => si_rs_awvalid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
si_rs_rready => si_rs_rready,
\state_reg[0]_rep\ => \RD.ar_channel_0_n_9\,
\state_reg[1]\ => \WR.aw_channel_0_n_14\,
\state_reg[1]_0\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_rep\ => \RD.ar_channel_0_n_6\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_8\,
\wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_146,
\wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_147,
\wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_148,
\wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_149,
\wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_150,
\wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_151,
\wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_152,
\wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_155,
\wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_156,
\wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_157,
\wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_158,
\wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_159,
\wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_160,
\wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_161,
\wrap_second_len_r_reg[3]\ => SI_REG_n_133,
\wrap_second_len_r_reg[3]_0\ => SI_REG_n_141
);
\WR.aw_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel
port map (
CO(0) => SI_REG_n_112,
D(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 1),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_113,
O(2) => SI_REG_n_114,
O(1) => SI_REG_n_115,
O(0) => SI_REG_n_116,
Q(24) => s_awid,
Q(23) => SI_REG_n_9,
Q(22) => SI_REG_n_10,
Q(21) => SI_REG_n_11,
Q(20) => SI_REG_n_12,
Q(19 downto 16) => si_rs_awlen(3 downto 0),
Q(15) => si_rs_awburst(1),
Q(14) => SI_REG_n_18,
Q(13 downto 12) => si_rs_awsize(1 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_34\,
S(2) => \WR.aw_channel_0_n_35\,
S(1) => \WR.aw_channel_0_n_36\,
S(0) => \WR.aw_channel_0_n_37\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_3\(3 downto 0),
\axaddr_offset_r_reg[2]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_1\(2 downto 1),
b_push => b_push,
\cnt_read_reg[0]_rep\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\,
\in\(8) => b_awid,
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[11]\(7 downto 0) => C(11 downto 4),
\m_payload_i_reg[35]\ => SI_REG_n_132,
\m_payload_i_reg[35]_0\ => SI_REG_n_133,
\m_payload_i_reg[38]\ => SI_REG_n_163,
\m_payload_i_reg[3]\ => SI_REG_n_153,
\m_payload_i_reg[46]\ => SI_REG_n_136,
\m_payload_i_reg[47]\ => SI_REG_n_134,
\m_payload_i_reg[48]\ => SI_REG_n_135,
\m_payload_i_reg[6]\ => SI_REG_n_145,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_146,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_147,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_148,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_149,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_150,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_151,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_152,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_2\,
sel_first_reg(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
si_rs_awvalid => si_rs_awvalid,
\wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_14\
);
\WR.b_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\cnt_read_reg[0]_rep\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\,
\in\(8) => b_awid,
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\(0) => si_rs_bid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0)
);
areset_d1_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_d1_i_1_n_0
);
areset_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => areset_d1_i_1_n_0,
Q => areset_d1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const1>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const1>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const1>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const1>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const1>\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s
port map (
Q(22 downto 20) => m_axi_awprot(2 downto 0),
Q(19 downto 0) => m_axi_awaddr(31 downto 12),
UNCONN_OUT(35) => s_axi_rid(0),
UNCONN_OUT(34) => s_axi_rlast,
UNCONN_OUT(33 downto 32) => s_axi_rresp(1 downto 0),
UNCONN_OUT(31 downto 0) => s_axi_rdata(31 downto 0),
aclk => aclk,
aresetn => aresetn,
\in\(33 downto 32) => m_axi_rresp(1 downto 0),
\in\(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0),
\m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_auto_pc_1,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 1;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_inst_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_inst_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(0) => '0',
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(0) => '0',
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(0) => NLW_inst_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(0) => '0',
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 5c78c9aeb2d2b1a52bde4c414824eea8 | 0.532169 | 2.545807 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.cache/ip/2017.2/708f145cb2a4886a/zynq_design_1_processing_system7_0_0_sim_netlist.vhdl | 1 | 197,353 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:30 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_processing_system7_0_0_sim_netlist.vhdl
-- Design : zynq_design_1_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "zynq_design_1_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2);
M_AXI_GP0_ARCACHE(1) <= \<const1>\;
M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0);
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2);
M_AXI_GP0_AWCACHE(1) <= \<const1>\;
M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2);
M_AXI_GP1_ARCACHE(1) <= \<const1>\;
M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2);
M_AXI_GP1_AWCACHE(1) <= \<const1>\;
M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2),
MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1),
MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2),
MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1),
MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2),
MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1),
MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2),
MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1),
MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zynq_design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "processing_system7_v5_5_processing_system7,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "zynq_design_1_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => FTMT_F2P_TRIG_0,
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => FTMT_P2F_TRIG_0,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => '0',
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | 74a4b878df95a173bf42d9243a422936 | 0.634356 | 2.756019 | false | false | false | false |
dawsonjon/FPGA-TX | fpga_tx/bsp_components/transmitter_tb.vhd | 1 | 2,386 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity transmitter_tb is
end entity transmitter_tb;
architecture rtl of transmitter_tb is
component transmitter is
port(
clk : in std_logic;
rst : in std_logic;
frequency : in std_logic_vector(31 downto 0);
frequency_stb : in std_logic;
frequency_ack : out std_logic;
control : in std_logic_vector(31 downto 0);
control_stb : in std_logic;
control_ack : out std_logic;
amplitude : in std_logic_vector(31 downto 0);
amplitude_stb : in std_logic;
amplitude_ack : out std_logic;
rf : out std_logic
);
end component transmitter;
signal clk : std_logic;
signal rst : std_logic;
signal frequency : std_logic_vector(31 downto 0);
signal frequency_stb : std_logic;
signal frequency_ack : std_logic;
signal control : std_logic_vector(31 downto 0);
signal control_stb : std_logic;
signal control_ack : std_logic;
signal amplitude : std_logic_vector(31 downto 0);
signal amplitude_stb : std_logic;
signal amplitude_ack : std_logic;
signal rf : std_logic;
begin
process
begin
clk <= '0';
while True loop
wait for 5 ns;
clk <= not clk;
end loop;
wait;
end process;
process
begin
rst <= '0';
wait for 20 ns;
rst <= '1';
wait;
end process;
process
file stimulus: TEXT open read_mode is "stim.txt";
variable l : LINE;
variable x : integer;
begin
while not endfile(stimulus) loop
readline(stimulus, l);
read(l, x);
amplitude <= (others => '0');
amplitude(7 downto 0) <= std_logic_vector(to_signed(x, 8));
amplitude(23 downto 16) <= std_logic_vector(to_signed(x, 8));
wait until rising_edge(clk) and amplitude_ack = '1';
end loop;
wait;
end process;
frequency <= X"000FFFFF";
control <= X"00000000";
amplitude_stb <= '1';
frequency_stb <= '1';
control_stb <= '1';
uut : transmitter port map(
clk => clk,
rst => rst,
frequency => frequency,
frequency_stb => frequency_stb,
frequency_ack => frequency_ack,
control => control,
control_stb => control_stb,
control_ack => control_ack,
amplitude => amplitude,
amplitude_stb => amplitude_stb,
amplitude_ack => amplitude_ack,
rf => rf
);
end rtl;
| mit | 77576ce6afa2be7f70469a050528cc7e | 0.621123 | 3.609682 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/leon3v3/dsu3_mb.vhd | 1 | 2,553 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dsu
-- File: dsu.vhd
-- Author: Jiri Gaisler, Edvin Catovic - Aeroflex Gaisler AB
-- Description: Combined LEON3 debug support with AHB trace unit
-- connected on separate bus.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
entity dsu3_mb is
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end;
architecture rtl of dsu3_mb is
signal gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
x0 : dsu3x generic map (hindex, haddr, hmask, ncpu, tbits, tech, irq, kbytes, 0, testen)
port map (rst, gnd, clk, ahbmi, ahbsi, ahbso, tahbsi, dbgi, dbgo, dsui, dsuo, vcc);
end;
| gpl-2.0 | fee5c95e21dc7e3b7d7093175fd84b5c | 0.59342 | 3.765487 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/jtag/jtag.vhd | 1 | 7,225 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: jtag
-- File: jtag.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: JTAG components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package jtag is
-- JTAG manufacturer IDs
constant JTAG_MANF_ID_GR : integer range 0 to 2047 := 804;
-- JTAG part numbers
-- Do NOT select an existing part number for your custom design!
constant JTAG_NEXTREME : integer range 0 to 65535 := 16#102#;
constant JTAG_IHP25RH1 : integer range 0 to 65535 := 16#251#;
constant JTAG_NGMP_PROTO : integer range 0 to 65535 := 16#281#;
constant JTAG_NGMP_PROTO2 : integer range 0 to 65535 := 16#282#;
constant JTAG_EXAMPLE_PART : integer range 0 to 65535 := 16#300#;
constant JTAG_ORBITA1 : integer range 0 to 65535 := 16#631#;
constant JTAG_ORBITA_OBTMP : integer range 0 to 65535 := 16#632#;
constant JTAG_UT699RH : integer range 0 to 65535 := 16#699#;
constant JTAG_UT700RH : integer range 0 to 65535 := 16#700#;
constant JTAG_GR702 : integer range 0 to 65535 := 16#702#;
constant JTAG_GR712 : integer range 0 to 65535 := 16#712#;
constant JTAG_SPWRTRASIC : integer range 0 to 65535 := 16#718#;
constant JTAG_UT840 : integer range 0 to 65535 := 16#840#;
component ahbjtag
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3;
scantest : integer := 0;
oepol : integer := 1;
tcknen : integer := 0;
versel : integer range 0 to 1 := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapi_tdo : in std_ulogic;
trst : in std_ulogic := '1';
tdoen : out std_ulogic;
tckn : in std_ulogic := '0';
tapo_tckn : out std_ulogic;
tapo_ninst : out std_logic_vector(7 downto 0);
tapo_iupd : out std_ulogic
);
end component;
component ahbjtag_bsd
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
asel : in std_ulogic;
dsel : in std_ulogic;
tck : in std_ulogic;
regi : in std_ulogic;
shift : in std_ulogic;
rego : out std_ulogic
);
end component;
component bscanctrl
generic (
spinst: integer := 5; -- sample/preload
etinst: integer := 6; -- extest
itinst: integer := 7; --intest
hzinst: integer := 8; -- highz
clinst: integer := 10; -- clamp
mbist : integer := 11; -- clamp
scantest : integer := 0
);
port (
trst : in std_ulogic;
tapo_tck : in std_ulogic;
tapo_tckn : in std_ulogic;
tapo_tdi : in std_ulogic;
tapo_ninst : in std_logic_vector(7 downto 0);
tapo_iupd : in std_ulogic;
tapo_rst : in std_ulogic;
tapo_capt : in std_ulogic;
tapo_shft : in std_ulogic;
tapo_upd : in std_ulogic;
tapi_tdo : out std_ulogic;
chain_tdi : out std_ulogic;
chain_tdo : in std_ulogic;
bsshft : out std_ulogic;
bscapt : out std_ulogic;
bsupdi : out std_ulogic;
bsupdo : out std_ulogic;
bsdrive : out std_ulogic;
bshighz : out std_ulogic;
bsmbist : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic
);
end component;
component bscanregs
generic (
tech: integer := 0;
nsigs: integer range 1 to 30 := 8;
dirmask: integer := 2#00000000#;
enable: integer range 0 to 1 := 1
);
port (
sigi: in std_logic_vector(nsigs-1 downto 0);
sigo: out std_logic_vector(nsigs-1 downto 0);
tck: in std_ulogic;
tckn:in std_ulogic;
tdi: in std_ulogic;
tdo: out std_ulogic;
bsshft: in std_ulogic;
bscapt: in std_ulogic;
bsupdi: in std_ulogic;
bsupdo: in std_ulogic;
bsdrive: in std_ulogic;
bshighz: in std_ulogic
);
end component;
component bscanregsbd
generic (
tech: integer:= 0;
nsigs: integer := 8;
enable: integer range 0 to 1 := 1;
hzsup: integer range 0 to 1 := 1
);
port (
pado : out std_logic_vector(nsigs-1 downto 0);
padoen : out std_logic_vector(nsigs-1 downto 0);
padi : in std_logic_vector(nsigs-1 downto 0);
coreo : in std_logic_vector(nsigs-1 downto 0);
coreoen : in std_logic_vector(nsigs-1 downto 0);
corei : out std_logic_vector(nsigs-1 downto 0);
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signals to scan regs on next tck edge
bsupdi : in std_ulogic; -- update indata reg from scan reg on next tck edge
bsupdo : in std_ulogic; -- update outdata reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive outdata regs to pad,
-- drive datareg(coreoen=0) or coreo(coreoen=1) to corei
bshighz : in std_ulogic -- tri-state output if hzsup, sample 1 on input
);
end component;
end;
| gpl-2.0 | 3adff9c9e1af1d35424db40f2951135a | 0.58436 | 3.62337 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-arrow-bemicro-sdk/leon3mp.vhd | 1 | 29,217 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 - 2012 Jan Andersson, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
cpu_rst_n : in std_ulogic;
clk_fpga_50m : in std_ulogic;
-- DDR SDRAM
ram_a : out std_logic_vector (13 downto 0); -- ddr address
ram_ck_p : out std_logic;
ram_ck_n : out std_logic;
ram_cke : out std_logic;
ram_cs_n : out std_logic;
ram_ws_n : out std_ulogic; -- ddr write enable
ram_ras_n : out std_ulogic; -- ddr ras
ram_cas_n : out std_ulogic; -- ddr cas
ram_dm : out std_logic_vector(1 downto 0); -- ram_udm & ram_ldm
ram_dqs : inout std_logic_vector (1 downto 0); -- ram_udqs & ram_lqds
ram_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ram_d : inout std_logic_vector (15 downto 0); -- ddr data
-- Ethernet PHY
txd : out std_logic_vector(3 downto 0);
rxd : in std_logic_vector(3 downto 0);
tx_clk : in std_logic;
rx_clk : in std_logic;
tx_en : out std_logic;
rx_dv : in std_logic;
eth_crs : in std_logic;
rx_er : in std_logic;
eth_col : in std_logic;
mdio : inout std_logic;
mdc : out std_logic;
eth_reset_n : out std_logic;
-- Temperature sensor
temp_sc : inout std_logic;
temp_cs_n : out std_logic;
temp_sio : inout std_logic;
-- LEDs
f_led : inout std_logic_vector(7 downto 0);
-- User push-button
pbsw_n : in std_logic;
-- Reconfig SW1 and SW2
reconfig_sw : in std_logic_vector(2 downto 1);
-- SD card interface
sd_dat0 : inout std_logic;
sd_dat1 : inout std_logic;
sd_dat2 : inout std_logic;
sd_dat3 : inout std_logic;
sd_cmd : inout std_logic;
sd_clk : inout std_logic;
-- EPCS
epcs_data : in std_ulogic;
epcs_dclk : out std_ulogic;
epcs_csn : out std_ulogic;
epcs_asdi : out std_ulogic
-- Expansion connector on card edge (set as reserved in design's QSF)
--reset_exp_n : out std_logic;
--exp_present : in std_logic;
--p : inout std_logic_vector(64 downto 1)
);
end;
architecture rtl of leon3mp is
constant maxahbm : integer := NCPU+CFG_AHB_JTAG+CFG_GRETH;
constant maxahbs : integer := 6
--pragma translate_off
+1 -- one more in simulation (AHBREP)
--pragma translate_on
;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal clkm, clkml : std_ulogic;
signal lclk, resetn : std_ulogic;
signal clklock, lock : std_ulogic;
signal rstn, rawrstn : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal tck : std_ulogic;
signal tckn : std_ulogic;
signal tms : std_ulogic;
signal tdi : std_ulogic;
signal tdo : std_ulogic;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u0i : uart_in_type;
signal u0o : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spii2 : spi_in_type;
signal spio2 : spi_out_type;
signal slvsel2 : std_logic_vector(0 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal dsu_breakn : std_ulogic;
attribute syn_keep : boolean;
attribute syn_keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
begin
vcc <= (others => '1'); gnd <= (others => '0');
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
cgi.pllctrl <= "00"; cgi.pllrst <= not rawrstn; cgi.pllref <= '0';
clklock <= cgo.clklock and lock;
clk_pad : clkpad generic map (tech => padtech)
port map (clk_fpga_50m, lclk);
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (
tech => CFG_CLKTECH,
clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV,
sdramen => 0,
freq => freq)
port map (
clkin => lclk,
pciclkin => gnd(0),
clk => clkm,
clkn => open,
clk2x => open,
sdclk => open,
pciclk => open,
cgi => cgi,
cgo => cgo);
reset_pad : inpad generic map (tech => padtech) port map (cpu_rst_n, resetn);
rst0 : rstgen -- reset generator
port map (
rstin => resetn,
clk => clkm,
clklock => clklock,
rstout => rstn,
rstoutraw => rawrstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (
defmast => CFG_DEFMST,
split => CFG_SPLIT,
rrobin => CFG_RROBIN,
ioaddr => CFG_AHBIO,
ioen => IOAEN,
nahbm => maxahbm,
nahbs => maxahbs)
port map (
rst => rstn,
clk => clkm,
msti => ahbmi,
msto => ahbmo,
slvi => ahbsi,
slvo => ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (
hindex => i,
fabtech => fabtech,
memtech => memtech,
nwindows => CFG_NWIN,
dsu => CFG_DSU,
fpu => CFG_FPU,
v8 => CFG_V8,
cp => 0,
mac => CFG_MAC,
pclow => pclow,
notag => CFG_NOTAG,
nwp => CFG_NWP,
icen => CFG_ICEN,
irepl => CFG_IREPL,
isets => CFG_ISETS,
ilinesize => CFG_ILINE,
isetsize => CFG_ISETSZ,
isetlock => CFG_ILOCK,
dcen => CFG_DCEN,
drepl => CFG_DREPL,
dsets => CFG_DSETS,
dlinesize => CFG_DLINE,
dsetsize => CFG_DSETSZ,
dsetlock => CFG_DLOCK,
dsnoop => CFG_DSNOOP,
ilram => CFG_ILRAMEN,
ilramsize => CFG_ILRAMSZ,
ilramstart => CFG_ILRAMADDR,
dlram => CFG_DLRAMEN,
dlramsize => CFG_DLRAMSZ,
dlramstart => CFG_DLRAMADDR,
mmuen => CFG_MMUEN,
itlbnum => CFG_ITLBNUM,
dtlbnum => CFG_DTLBNUM,
tlb_type => CFG_TLB_TYPE,
tlb_rep => CFG_TLB_REP,
lddel => CFG_LDDEL,
disas => disas,
tbuf => CFG_ITBSZ,
pwd => CFG_PWD,
svt => CFG_SVT,
rstaddr => CFG_RSTADDR,
smp => NCPU-1,
cached => CFG_DFIXED,
scantest => CFG_SCAN,
mmupgsz => CFG_MMU_PAGE,
bp => CFG_BP)
port map (
clk => clkm,
rstn => rstn,
ahbi => ahbmi,
ahbo => ahbmo(i),
ahbsi => ahbsi,
ahbso => ahbso,
irqi => irqi(i),
irqo => irqo(i),
dbgi => dbgi(i),
dbgo => dbgo(i));
end generate;
errorn_pad : toutpad generic map (tech => padtech) port map (f_led(6), gnd(0), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (
hindex => 2,
haddr => 16#900#,
hmask => 16#F00#,
ncpu => NCPU,
tbits => 30,
tech => memtech,
irq => 0,
kbytes => CFG_ATBSZ)
port map (
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbsi => ahbsi,
ahbso => ahbso(2),
dbgi => dbgo,
dbgo => dbgi,
dsui => dsui,
dsuo => dsuo);
dsui.enable <= '1';
dsui.break <= not dsu_breakn; -- Switch polarity
dsubre_pad : inpad generic map (tech => padtech) port map (pbsw_n, dsu_breakn);
dsuact_pad : toutpad generic map (tech => padtech) port map (f_led(7), gnd(0), dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(
rst => rstn,
clk => clkm,
tck => tck,
tms => tms,
tdi => tdi,
tdo => tdo,
ahbi => ahbmi,
ahbo => ahbmo(NCPU+CFG_AHB_UART),
tapo_tck => open,
tapo_tdi => open,
tapo_inst => open,
tapo_rst => open,
tapo_capt => open,
tapo_shft => open,
tapo_upd => open,
tapi_tdo => gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- DDR memory controller
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc0 : ddrspa
generic map (
fabtech => fabtech,
memtech => memtech,
hindex => 0,
haddr => 16#400#,
hmask => 16#F00#,
ioaddr => 1,
pwron => CFG_DDRSP_INIT,
MHz => BOARD_FREQ/1000,
rskew => CFG_DDRSP_RSKEW,
clkmul => CFG_DDRSP_FREQ/5,
clkdiv => 10,
ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE,
ddrbits => 16,
regoutput => 1,
mobile => 0)
port map (
rst_ddr => rawrstn,
rst_ahb => rstn,
clk_ddr => lclk,
clk_ahb => clkm,
lock => lock,
clkddro => clkml,
clkddri => clkml,
ahbsi => ahbsi,
ahbso => ahbso(0),
ddr_clk => ddr_clkv,
ddr_clkb => ddr_clkbv,
ddr_clk_fb_out => open,
ddr_clk_fb => gnd(0),
ddr_cke => ddr_ckev,
ddr_csb => ddr_csbv,
ddr_web => ram_ws_n,
ddr_rasb => ram_ras_n,
ddr_casb => ram_cas_n,
ddr_dm => ram_dm,
ddr_dqs => ram_dqs,
ddr_ad => ram_a,
ddr_ba => ram_ba,
ddr_dq => ram_d);
end generate;
ram_ck_p <= ddr_clkv(0);
ram_ck_n <= ddr_clkbv(0);
ram_cke <= ddr_ckev(0);
ram_cs_n <= ddr_csbv(0);
ddrsp1 : if (CFG_DDRSP = 0) generate
ahbso(0) <= ahbs_none;
lock <= '1';
ddr_clkv <= (others => '0');
ddr_clkbv <= (others => '0');
ddr_ckev <= (others => '1');
ddr_csbv <= (others => '1');
end generate;
-- SPI Memory Controller
spimc: if CFG_SPIMCTRL /= 0 and CFG_AHBROMEN = 0 generate
spimctrl0 : spimctrl
generic map (
hindex => 4,
hirq => 9,
faddr => 16#000#,
fmask => 16#f00#,
ioaddr => 16#002#,
iomask => 16#fff#,
spliten => CFG_SPLIT,
oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT,
offset => CFG_SPIMCTRL_OFFSET)
port map (
rstn => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(4),
spii => spmi,
spio => spmo);
end generate;
epcs_miso_pad : inpad generic map (tech => padtech)
port map (epcs_data, spmi.miso);
epcs_mosi_pad : outpad generic map (tech => padtech)
port map (epcs_asdi, spmo.mosi);
epcs_sck_pad : outpad generic map (tech => padtech)
port map (epcs_dclk, spmo.sck);
epcs_slvsel0_pad : outpad generic map (tech => padtech)
port map (epcs_csn, spmo.csn);
nospimc : if CFG_SPIMCTRL /= 1 or CFG_AHBROMEN /= 0 generate
spmo <= spimctrl_out_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- AHB/APB bridge
apb0 : apbctrl
generic map (
hindex => 1,
haddr => CFG_APBADDR,
nslaves => 7)
port map (
rst => rstn,
clk => clkm,
ahbi => ahbsi,
ahbo => ahbso(1),
apbi => apbi,
apbo => apbo);
-- 8-bit UART, not connected off-chip, use in loopback with GRMON
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (
pindex => 1,
paddr => 1,
pirq => 2,
console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(1),
uarti => u0i,
uarto => u0o);
end generate;
u0i.rxd <= '0'; u0i.ctsn <= '0'; u0i.extclk <= '0';
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (
pindex => 2,
paddr => 2,
ncpu => NCPU)
port map (
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(2),
irqi => irqo,
irqo => irqi);
end generate;
noirqctrl : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Timer unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (
pindex => 3,
paddr => 3,
pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ,
sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(3),
gpti => gpti,
gpto => open);
end generate;
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
gpti.wdogen <= '0';
notim : if CFG_GPT_ENABLE = 0 generate
apbo(3) <= apb_none;
end generate;
-- GPIO unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(
pindex => 0,
paddr => 0,
imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map(
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(0),
gpioi => gpioi,
gpioo => gpioo);
end generate;
gpio_pads : iopadvv generic map (tech => padtech, width => 6)
port map (f_led(5 downto 0), gpioo.dout(5 downto 0),
gpioo.oen(5 downto 0), gpioi.din(5 downto 0));
gpioi.din(31 downto 6) <= (others => '0');
nogpio : if CFG_GRGPIO_ENABLE = 0 generate
apbo(0) <= apb_none;
end generate;
-- SPI controller connected to temperature sensor
spic: if CFG_SPICTRL_ENABLE /= 0 generate
spi1 : spictrl
generic map (
pindex => 4,
paddr => 4,
pmask => 16#fff#,
pirq => 9,
fdepth => CFG_SPICTRL_FIFO,
slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS,
odmode => CFG_SPICTRL_ODMODE,
automode => CFG_SPICTRL_AM,
aslvsel => CFG_SPICTRL_ASEL,
twen => 1,
maxwlen => CFG_SPICTRL_MAXWLEN,
netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM,
ft => CFG_SPICTRL_FT)
port map (
rstn => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(4),
spii => spii,
spio => spio,
slvsel => slvsel);
end generate spic;
-- MISO signal not used
spii.miso <= '0';
mosi_pad : iopad generic map (tech => padtech)
port map (temp_sio, spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (temp_sc, spio.sck, spio.sckoen, spii.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (temp_cs_n, slvsel(0));
spii.spisel <= '1'; -- Master only
nospic : if CFG_SPICTRL_ENABLE = 0 generate
apbo(4) <= apb_none;
spio.misooen <= '1';
spio.mosioen <= '1';
spio.sckoen <= '1';
slvsel <= (others => '1');
end generate;
-- SPI controller connected to SD card slot
spic2: if CFG_SPICTRL_ENABLE /= 0 and CFG_SPICTRL_NUM > 1 generate
spi1 : spictrl
generic map (
pindex => 5,
paddr => 5,
pmask => 16#fff#,
pirq => 11,
fdepth => CFG_SPICTRL_FIFO,
slvselen => 1,
slvselsz => 1,
odmode => CFG_SPICTRL_ODMODE,
automode => CFG_SPICTRL_AM,
aslvsel => CFG_SPICTRL_ASEL,
twen => 0,
maxwlen => CFG_SPICTRL_MAXWLEN,
netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM,
ft => CFG_SPICTRL_FT)
port map (
rstn => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(5),
spii => spii2,
spio => spio2,
slvsel => slvsel2);
miso_pad : iopad generic map (tech => padtech)
port map (sd_dat0, spio2.miso, spio2.misooen, spii2.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (sd_cmd, spio2.mosi, spio2.mosioen, spii2.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (sd_clk, spio2.sck, spio2.sckoen, spii2.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (sd_dat3, slvsel2(0));
spii2.spisel <= '1'; -- Master only
end generate;
nospic2 : if CFG_SPICTRL_ENABLE = 0 or CFG_SPICTRL_NUM < 2 generate
apbo(5) <= apb_none;
spio2.misooen <= '1';
spio2.mosioen <= '1';
spio2.sckoen <= '1';
slvsel2(0) <= '0';
end generate;
-- SPI Memory Controller
-- Example on how to connect SPI memory controller to SD card. If you want to
-- use this then you need to disable the second SPICTRL core's connections to
-- the same top-level signals above.
--spimc: if false generate
-- spimctrl0 : spimctrl
-- generic map (
-- hindex => 4,
-- hirq => 9,
-- faddr => 16#b00#,
-- fmask => 16#f00#,
-- ioaddr => 16#002#,
-- iomask => 16#fff#,
-- spliten => CFG_SPLIT,
-- oepol => 0,
-- sdcard => CFG_SPIMCTRL_SDCARD,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
-- scaler => CFG_SPIMCTRL_SCALER,
-- altscaler => CFG_SPIMCTRL_ASCALER,
-- pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
-- port map (
-- rstn => rstn,
-- clk => clkm,
-- ahbsi => ahbsi,
-- ahbso => ahbso(4),
-- spii => spmi,
-- spio => spmo);
-- miso_pad : inpad generic map (tech => padtech)
-- port map (sd_dat0, spmi.miso);
-- mosi_pad : outpad generic map (tech => padtech)
-- port map (sd_cmd, spmo.mosi);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (sd_clk, spmo.sck);
-- slvsel0_pad : iopad generic map (tech => padtech)
-- port map (sd_dat3, spmo.csn, spmo.cdcsnoen, spmi.cd);
--end generate;
--nospimc : if false generate
-- spmo.mosi <= '0';
-- spmo.mosioen <= '1';
-- spmo.sck <= '0';
-- spmo.csn <= '1';
-- spmo.cdcsnoen <= '1';
-- spmo.errorn <= '0';
-- spmo.ready <= '0';
-- spmo.initialized <= '0';
--end generate;
-- sd_dat1 and sd_dat2 are unused
unuseddat1_pad : iopad generic map (tech => padtech)
port map (sd_dat1, gnd(0), vcc(1), open);
unuseddat2_pad : iopad generic map (tech => padtech)
port map (sd_dat2, gnd(0), vcc(1), open);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH /= 0 generate -- Gaisler Ethernet MAC
e1 : grethm
generic map(
hindex => CFG_NCPU+CFG_AHB_JTAG,
pindex => 6,
paddr => 6,
pirq => 10,
memtech => memtech,
mdcscaler => CPU_FREQ/(4*1000)-1,
enable_mdio => 1,
fifosize => CFG_ETH_FIFO,
nsync => 1,
edcl => CFG_DSU_ETH,
edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM,
macaddrl => CFG_ETH_ENL,
phyrstadr => 1,
ipaddrh => CFG_ETH_IPM,
ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G)
port map(
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_JTAG),
apbi => apbi,
apbo => apbo(6),
ethi => ethi,
etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (rxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (rx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (eth_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (eth_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (txd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (tx_en, etho.tx_en);
emdc_pad : outpad generic map (tech => padtech)
port map (mdc, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (eth_reset_n, rawrstn);
end generate;
noeth : if CFG_GRETH = 0 generate
apbo(6) <= apb_none;
ethi <= eth_in_none;
etho <= eth_out_none;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (
hindex => 3,
haddr => CFG_AHBRODDR,
pipe => CFG_AHBROPIP)
port map (
rst => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(3));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(3) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (
hindex => 5,
haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (
rst => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(5));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(5) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- AHB Report Module for simulation ----------------------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
driveahbm : for i in maxahbm to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
driveahbs : for i in maxahbs to NAHBSLV-1 generate
ahbso(i) <= ahbs_none;
end generate;
driveapb : for i in 7 to NAPBSLV-1 generate
apbo(i) <= apb_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 BeMicro SDK Design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 42a0307641c7ff2c9d70edc09e67b21d | 0.479207 | 3.910198 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/spictrl_net.vhd | 1 | 6,324 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spictrl_net
-- File: spictrl_net.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: Netlist wrapper for SPICTRL core
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.gencomp.all;
entity spictrl_net is
generic (
tech : integer range 0 to NTECH := 0;
fdepth : integer range 1 to 7 := 1;
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1;
oepol : integer range 0 to 1 := 0;
odmode : integer range 0 to 1 := 0;
automode : integer range 0 to 1 := 0;
acntbits : integer range 1 to 32 := 32;
aslvsel : integer range 0 to 1 := 0;
twen : integer range 0 to 1 := 1;
maxwlen : integer range 0 to 15 := 0;
automask0 : integer := 0;
automask1 : integer := 0;
automask2 : integer := 0;
automask3 : integer := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
-- SPI signals
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0)
);
end entity spictrl_net;
architecture rtl of spictrl_net is
component spictrl_unisim
generic (
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
-- SPI signals
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0));
end component;
begin
xil : if false generate --(is_unisim(tech) = 1) generate
xilctrl : spictrl_unisim
generic map (
slvselen => slvselen,
slvselsz => slvselsz)
port map (
rstn => rstn,
clk => clk,
-- APB signals
apbi_psel => apbi_psel,
apbi_penable => apbi_penable,
apbi_paddr => apbi_paddr,
apbi_pwrite => apbi_pwrite,
apbi_pwdata => apbi_pwdata,
apbi_testen => apbi_testen,
apbi_testrst => apbi_testrst,
apbi_scanen => apbi_scanen,
apbi_testoen => apbi_testoen,
apbo_prdata => apbo_prdata,
apbo_pirq => apbo_pirq,
-- SPI signals
spii_miso => spii_miso,
spii_mosi => spii_mosi,
spii_sck => spii_sck,
spii_spisel => spii_spisel,
spii_astart => spii_astart,
spii_cstart => spii_cstart,
spio_miso => spio_miso,
spio_misooen => spio_misooen,
spio_mosi => spio_mosi,
spio_mosioen => spio_mosioen,
spio_sck => spio_sck,
spio_sckoen => spio_sckoen,
spio_enable => spio_enable,
spio_astart => spio_astart,
spio_aready => spio_aready,
slvsel => slvsel);
end generate;
-- pragma translate_off
nonet : if true generate --not ((is_unisim(tech) = 1)) generate
err : process
begin
assert false report "ERROR : No SPICTRL netlist available for this process!"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end architecture;
| gpl-2.0 | 89c59a3869dca8c2dcc5a0deaf00392b | 0.562619 | 3.77102 | false | true | false | false |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/Accum/src/MROM.vhd | 1 | 1,450 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library accum;
use accum.OneHotAccum.all;
entity MROM is
port (
RE: in std_logic;
ADDR: in mem_addr;
DOUT: out command
);
end MROM;
architecture Beh of MROM is
type tROM is array (0 to 31) of command;
constant STUB: mem_addr := "00000";
constant DATA_START: mem_addr := "00000";
constant LENGTH :mem_addr := "10000";
constant COUNTER: mem_addr := "10001";
constant CURRENT_VALUE: mem_addr := "10010";
constant INIT_VALUE: mem_addr := "10011";
constant ZERO: mem_addr := "10100";
constant ONE: mem_addr := "10101";
constant LOOP_ADDR: mem_addr := "01000";
constant ROM: tROM :=(
-- OP CODE | OP1
-- Init
LOAD & ZERO,
STORE & COUNTER,
LOAD & ZERO,
STORE & DATA_START,
STORE & CURRENT_VALUE,
LOAD & LENGTH,
SUBT & ONE,
STORE & LENGTH,
-- Loop
LOAD & COUNTER,
ADD & ONE,
STORE & COUNTER,
SHIFT & STUB,
STORE & CURRENT_VALUE,
STOREIN & COUNTER,
LOAD & LENGTH,
SUBT & COUNTER,
JNZ & LOOP_ADDR,
others => HALT & STUB
);
signal data: command;
begin
data <= ROM(conv_integer(addr));
zbufs: process (RE, data)
begin
if (RE = '1') then
DOUT <= data;
else
DOUT <= (others => 'Z');
end if;
end process;
end Beh; | mit | 88e8856c8ae67df770d85bfead09aa1d | 0.553793 | 2.929293 | false | false | false | false |
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