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ou-cse-378/vhdl-tetris | GPU.vhd | 1 | 2,455 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: GPU.vhd
-- // Date: 12/9/2004
-- // Description: Main GPU Module
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity GPU is
port(
iClk25MHZ : in std_logic;
iPaused : in std_logic;
iScore : std_logic_vector(15 downto 0);
oBlockAddr : out std_logic_vector(4 downto 0); --Holds static blocks
iBlockData : in std_logic_vector(15 downto 0); --Holds each row
iBlockY : in std_logic_vector(4 downto 0); --top edge of moving block
iBlockX : in std_logic_vector(3 downto 0); --left edge of moving block
iBlockReg : in std_logic_vector(15 downto 0); --encoded dynamic block memory
iClr : in std_logic;
iDiag : in std_logic;
oRGB : out std_logic_vector(2 downto 0);
oVSync : out std_logic;
oHSync : out std_logic);
end GPU;
architecture Behavioral of GPU is
Signal tRGB : std_logic_vector(2 downto 0);
component RGB_Controller is
Port ( oRGB : out std_logic_vector(2 downto 0);
iClk : in std_logic;
iClr : in std_logic;
iPaused : in std_logic;
iBlock: in std_logic_vector(15 downto 0); --Block rows fom Block RAM
oBlockAddr : out std_logic_vector(4 downto 0); --address for block ram
iBlockY : in std_logic_vector(4 downto 0); --encoded Y
iBlockX : in std_logic_vector(3 downto 0); --encoded X
iBlockReg : in std_logic_vector(15 downto 0));
end component;
component VGA is
Port ( oRGB : out std_logic_vector(2 downto 0);
oVSync : out std_logic;
oHSync : out std_logic;
iClk : in std_logic;
iDiag : in std_logic;
iClr : in std_logic;
iRGB : in std_logic_vector(2 downto 0));
end component;
begin
RGB00 : RGB_controller port map(
oRGB => tRGB,
iClk => iClk25Mhz,
iClr => iClr,
iPaused => iPaused,
iBlock => iBlockData,
oBlockAddr => oBlockAddr,
iBlockX => iBlockX,
iBlockY => iBlockY,
iBlockReg => iBlockReg);
VGA00 : VGA port map(
oRGB => oRGB,
iRGB => tRGB,
iDiag => iDiag,
oVSync => oVSync,
oHSync => oHSync,
iClk => iClk25Mhz,
iClr => iClr);
end Behavioral;
| mit | 839827fa51ab755e635fbeca9d726a5c | 0.580448 | 3.151476 | false | false | false | false |
hoglet67/ElectronFpga | src/common/T6502/T65_Pack.vhd | 3 | 5,460 | -- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- See list of changes in T65 top file (T65.vhd)...
--
-- ****
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65_Pack.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
--
-- Copyright (c) 2002...2015
-- Daniel Wallner (jesus <at> opencores <dot> org)
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
-- Morten Leikvoll ()
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author(s), but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- Limitations :
-- See in T65 top file (T65.vhd)...
library IEEE;
use IEEE.std_logic_1164.all;
package T65_Pack is
constant Flag_C : integer := 0;
constant Flag_Z : integer := 1;
constant Flag_I : integer := 2;
constant Flag_D : integer := 3;
constant Flag_B : integer := 4;
constant Flag_1 : integer := 5;
constant Flag_V : integer := 6;
constant Flag_N : integer := 7;
subtype T_Lcycle is std_logic_vector(2 downto 0);
constant Cycle_sync :T_Lcycle:="000";
constant Cycle_1 :T_Lcycle:="001";
constant Cycle_2 :T_Lcycle:="010";
constant Cycle_3 :T_Lcycle:="011";
constant Cycle_4 :T_Lcycle:="100";
constant Cycle_5 :T_Lcycle:="101";
constant Cycle_6 :T_Lcycle:="110";
constant Cycle_7 :T_Lcycle:="111";
function CycleNext(c:T_Lcycle) return T_Lcycle;
type T_Set_BusA_To is
(
Set_BusA_To_DI,
Set_BusA_To_ABC,
Set_BusA_To_X,
Set_BusA_To_Y,
Set_BusA_To_S,
Set_BusA_To_P,
Set_BusA_To_DA,
Set_BusA_To_DAO,
Set_BusA_To_DAX,
Set_BusA_To_AAX,
Set_BusA_To_DONTCARE
);
type T_Set_Addr_To is
(
Set_Addr_To_PBR,
Set_Addr_To_SP,
Set_Addr_To_ZPG,
Set_Addr_To_BA
);
type T_Write_Data is
(
Write_Data_DL,
Write_Data_ABC,
Write_Data_X,
Write_Data_Y,
Write_Data_S,
Write_Data_P,
Write_Data_PCL,
Write_Data_PCH,
Write_Data_AX,
Write_Data_AXB,
Write_Data_XB,
Write_Data_YB,
Write_Data_DONTCARE
);
type T_ALU_OP is
(
ALU_OP_OR, --"0000"
ALU_OP_AND, --"0001"
ALU_OP_EOR, --"0010"
ALU_OP_ADC, --"0011"
ALU_OP_EQ1, --"0100" EQ1 does not change N,Z flags, EQ2/3 does.
ALU_OP_EQ2, --"0101" Not sure yet whats the difference between EQ2&3. They seem to do the same ALU op
ALU_OP_CMP, --"0110"
ALU_OP_SBC, --"0111"
ALU_OP_ASL, --"1000"
ALU_OP_ROL, --"1001"
ALU_OP_LSR, --"1010"
ALU_OP_ROR, --"1011"
ALU_OP_BIT, --"1100"
-- ALU_OP_EQ3, --"1101"
ALU_OP_DEC, --"1110"
ALU_OP_INC, --"1111"
ALU_OP_ARR,
ALU_OP_ANC,
ALU_OP_SAX,
ALU_OP_XAA
-- ALU_OP_UNDEF--"----"--may be replaced with any?
);
type T_t65_dbg is record
I : std_logic_vector(7 downto 0); -- instruction
A : std_logic_vector(7 downto 0); -- A reg
X : std_logic_vector(7 downto 0); -- X reg
Y : std_logic_vector(7 downto 0); -- Y reg
S : std_logic_vector(7 downto 0); -- stack pointer
P : std_logic_vector(7 downto 0); -- processor flags
end record;
end;
package body T65_Pack is
function CycleNext(c:T_Lcycle) return T_Lcycle is
begin
case(c) is
when Cycle_sync=>
return Cycle_1;
when Cycle_1=>
return Cycle_2;
when Cycle_2=>
return Cycle_3;
when Cycle_3=>
return Cycle_4;
when Cycle_4=>
return Cycle_5;
when Cycle_5=>
return Cycle_6;
when Cycle_6=>
return Cycle_7;
when Cycle_7=>
return Cycle_sync;
when others=>
return Cycle_sync;
end case;
end CycleNext;
end T65_Pack;
| gpl-3.0 | a9d34b8766160d57f3613323829d7fc8 | 0.618315 | 3.323189 | false | false | false | false |
DreamIP/GPStudio | support/toolchain/caph/hdl/caph_lib/stream_in.1.vhd | 1 | 2,870 | -----------------------------------------------------------------------------------------
-- --
-- This file is part of the CAPH Compiler distribution --
-- http://caph.univ-bpclermont.fr --
-- --
-- Jocelyn SEROT --
-- [email protected] --
-- --
-- Copyright 2011-2015 Jocelyn SEROT. All rights reserved. --
-- This file is distributed under the terms of the GNU Library General Public License --
-- with the special exception on linking described in file ../LICENSE. --
-- --
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity stream_in is
generic ( filename: string := "input.bin"; size: integer := 10; period: integer := 2; blanking: boolean := false );
port ( full : in std_logic;
dout : out std_logic_vector(size-1 downto 0);
wr : out std_logic; -- write (push) signal, active 1 on clk^
clk : in std_logic;
rst : in std_logic
);
end stream_in;
architecture beh of stream_in is
begin
process
file input_file: text;
variable file_line: line;
variable line_out: line;
variable data: bit_vector(size-1 downto 0);
begin
if ( period < 1 ) then
report "stream_in(" & filename & ") : period < 1"
severity error;
end if;
wr <= '0';
file_open(input_file,filename,READ_MODE);
while not endfile(input_file) loop
readline (input_file,file_line);
read (file_line,data) ;
for i in 0 to period-2 loop
wait until rising_edge(clk);
end loop;
assert (full='0')
report "stream_in(" & filename & ") : cannot write: downstream fifo is full !"
severity warning;
if ( blanking = false or data(size-1 downto size-2) /= "00" ) then
-- Note 2014-10-08, JS
-- This conditionnal is a hack for implementing blanking :
-- Special tokens 00xxxxx are supposed to mean "NO DATA"
-- These tokens will be generated in the input .bin file by the [txt2bin] utility
dout <= to_stdlogicvector(data);
wr <= '1';
wait until rising_edge(clk);
wr <= '0';
end if;
end loop;
file_close(input_file);
wait;
end process;
end;
| gpl-3.0 | ba7bda51bae8f9df9ebadbccda8d9b50 | 0.444948 | 4.720395 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/mems/testbench/mems_tb.vhdl | 1 | 4,278 | --
-- Mems testbench
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.MEMs.all;
use FPGALIB.Simul.all;
entity Mems_tb is
end entity Mems_tb;
architecture TestBench of Mems_tb is
constant AWIDTH: positive:=3;
constant DWIDTH: positive:=8;
constant DEPTH : natural:=5;
signal rst : std_logic;
signal stop : boolean;
signal clk1, clk2 : std_logic;
signal wen1, wen2 : std_logic;
signal addr1, addr2 : std_logic_vector(AWIDTH-1 downto 0):=(others => '0');
signal data1, data2 : std_logic_vector(DWIDTH-1 downto 0);
signal s_out, d_out : std_logic_vector(DWIDTH-1 downto 0);
signal t_out1, t_out2 : std_logic_vector(DWIDTH-1 downto 0);
begin
clock1 : Clock
generic map(FREQUENCY => 2)
port map(clk_o => clk1, rst_o => rst, stop_i => stop);
clock2 : Clock
generic map(FREQUENCY => 3)
port map(clk_o => clk2, rst_o => open, stop_i => stop);
SingleRAM: SinglePortRAM
generic map(AWIDTH => AWIDTH, DWIDTH => DWIDTH, DEPTH => DEPTH)
port map(
clk_i => clk1, wen_i => wen1, addr_i => addr1, data_i => data1, data_o => s_out);
DualRAM: SimpleDualPortRAM
generic map(AWIDTH => AWIDTH, DWIDTH => DWIDTH, DEPTH => DEPTH)
port map(clk1_i => clk1, clk2_i => clk2, wen1_i => wen1,
addr1_i => addr1, addr2_i => addr2, data1_i => data1, data2_o => d_out);
TrueDualRAM: TrueDualPortRAM
generic map(AWIDTH => AWIDTH, DWIDTH => DWIDTH, DEPTH => DEPTH)
port map(clk1_i => clk1, clk2_i => clk2, wen1_i => wen1, wen2_i => wen2,
addr1_i => addr1, addr2_i => addr2,
data1_i => data1, data2_i => data2, data1_o => t_out1, data2_o => t_out2);
side1: process
begin
print("* Start of Test");
wait until rising_edge(clk1) and rst = '0';
print("* Writing Side 1");
wen1 <= '1';
addr1 <= "000";
data1 <= x"CA";
wait until rising_edge(clk1);
addr1 <= "001";
data1 <= x"FE";
wait until rising_edge(clk1);
wen1 <= '0';
print("* Reading Side 1");
addr1 <= "000";
wait until rising_edge(clk1);
addr1 <= "001";
wait until rising_edge(clk1);
assert s_out=x"CA" report "ERROR in SinglePortRAM" severity failure;
assert t_out1=x"CA" report "ERROR in TrueDualPortRAM" severity failure;
wait until rising_edge(clk1);
assert s_out=x"FE" report "ERROR in SinglePortRAM" severity failure;
assert t_out1=x"FE" report "ERROR in TrueDualPortRAM" severity failure;
wait until rising_edge(clk1);
print("* Side 1 is OK in SinglePortRAM and TrueDualPortRAM");
wait;
end process side1;
side2: process
begin
wait until rising_edge(clk2) and rst = '0';
wait until rising_edge(clk2);
wait until rising_edge(clk2);
wait until rising_edge(clk2);
wait until rising_edge(clk2);
wait until rising_edge(clk2);
wait until rising_edge(clk2);
print("* Reading Side 2");
addr2 <= "000";
wait until rising_edge(clk2);
addr2 <= "001";
wait until rising_edge(clk2);
assert d_out=x"CA" report "ERROR in DualPortRAM" severity failure;
wait until rising_edge(clk2);
assert d_out=x"FE" report "ERROR in DualPortRAM" severity failure;
wait until rising_edge(clk2);
print("* Writing Side 2");
wen2 <= '1';
addr2 <= "000";
data2 <= x"B0";
wait until rising_edge(clk2);
addr2 <= "001";
data2 <= x"CA";
wait until rising_edge(clk2);
wen2 <= '0';
print("* Reading Side 2");
addr2 <= "000";
wait until rising_edge(clk2);
addr2 <= "001";
wait until rising_edge(clk2);
assert t_out2=x"B0" report "ERROR in TrueDualPortRAM" severity failure;
wait until rising_edge(clk1);
assert t_out2=x"CA" report "ERROR in TrueDualPortRAM" severity failure;
wait until rising_edge(clk1);
print("* Side 2 is OK in DualPortRAM and TrueDualPortRAM");
print("* End of Test");
stop <= TRUE;
wait;
end process side2;
end architecture TestBench;
| bsd-3-clause | 2ca2125f2d69f7af8a8583a360737878 | 0.604254 | 3.31371 | false | false | false | false |
DreamIP/GPStudio | support/process/roberts/hdl/roberts_slave.vhd | 1 | 3,053 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity roberts_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end roberts_slave;
architecture rtl of roberts_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant WIDTHIMG_REG_REG_ADDR : natural := 1;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal widthimg_reg_width_reg : std_logic_vector (15 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
widthimg_reg_width_reg <= "0000000000000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
status_reg_enable_bit_reg <= datawr_i(0);
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
widthimg_reg_width_reg <= datawr_i(15) & datawr_i(14) & datawr_i(13) & datawr_i(12) & datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000000000000000000" & status_reg_enable_bit_reg;
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000" & widthimg_reg_width_reg(15) & widthimg_reg_width_reg(14) & widthimg_reg_width_reg(13) & widthimg_reg_width_reg(12) & widthimg_reg_width_reg(11) & widthimg_reg_width_reg(10) & widthimg_reg_width_reg(9) & widthimg_reg_width_reg(8) & widthimg_reg_width_reg(7) & widthimg_reg_width_reg(6) & widthimg_reg_width_reg(5) & widthimg_reg_width_reg(4) & widthimg_reg_width_reg(3) & widthimg_reg_width_reg(2) & widthimg_reg_width_reg(1) & widthimg_reg_width_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
widthimg_reg_width <= widthimg_reg_width_reg;
end rtl;
| gpl-3.0 | b8726fbfdc945debe01e80de8a39f47a | 0.592532 | 2.877474 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator.vhd | 1 | 12,740 | -- tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.13.13:59:38
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator is
generic (
AV_ADDRESS_W : integer := 1;
AV_DATA_W : integer := 8;
UAV_DATA_W : integer := 8;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 1;
UAV_BYTEENABLE_W : integer := 1;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 1;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 1;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(0 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(0 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(7 downto 0); -- .readdata
uav_writedata : in std_logic_vector(7 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(0 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(7 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(7 downto 0); -- .writedata
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_chipselect : out std_logic; -- .chipselect
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_byteenable : out std_logic_vector(0 downto 0);
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_writebyteenable : out std_logic_vector(0 downto 0);
uav_clken : in std_logic := '0'
);
end entity tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator;
architecture rtl of tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(7 downto 0); -- readdata
uav_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(0 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(7 downto 0); -- writedata
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component altera_merlin_slave_translator;
begin
character_lcd_0_avalon_lcd_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_waitrequest => av_waitrequest, -- .waitrequest
av_chipselect => av_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
end architecture rtl; -- of tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator
| gpl-2.0 | 0a000ef3789b48028a40e2e31d0cbdee | 0.436028 | 4.275168 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_sram_0.vhd | 1 | 8,215 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module chipselects reads and writes to the sram, with 2-cycle *
-- * read latency and one cycle write latency. *
-- * *
-- ******************************************************************************
ENTITY tracking_camera_system_sram_0 IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
address :IN STD_LOGIC_VECTOR(17 DOWNTO 0);
byteenable :IN STD_LOGIC_VECTOR( 1 DOWNTO 0);
read :IN STD_LOGIC;
write :IN STD_LOGIC;
writedata :IN STD_LOGIC_VECTOR(15 DOWNTO 0);
-- Bi-Directional
SRAM_DQ :INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- SRAM Data bus 16 Bits
-- Outputs
readdata :BUFFER STD_LOGIC_VECTOR(15 DOWNTO 0);
readdatavalid :BUFFER STD_LOGIC;
SRAM_ADDR :BUFFER STD_LOGIC_VECTOR(17 DOWNTO 0); -- SRAM Address bus 18 Bits
SRAM_LB_N :BUFFER STD_LOGIC; -- SRAM Low-byte Data Mask
SRAM_UB_N :BUFFER STD_LOGIC; -- SRAM High-byte Data Mask
SRAM_CE_N :BUFFER STD_LOGIC; -- SRAM Chip chipselect
SRAM_OE_N :BUFFER STD_LOGIC; -- SRAM Output chipselect
SRAM_WE_N :BUFFER STD_LOGIC -- SRAM Write chipselect
);
END tracking_camera_system_sram_0;
ARCHITECTURE Behaviour OF tracking_camera_system_sram_0 IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
-- Internal Registers
SIGNAL is_read :STD_LOGIC;
SIGNAL is_write :STD_LOGIC;
SIGNAL writedata_reg :STD_LOGIC_VECTOR(15 DOWNTO 0);
-- State Machine Registers
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
-- Output Registers
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
readdata <= SRAM_DQ;
readdatavalid <= is_read;
SRAM_ADDR <= address;
SRAM_LB_N <= NOT (byteenable(0) AND (read OR write));
SRAM_UB_N <= NOT (byteenable(1) AND (read OR write));
SRAM_CE_N <= NOT (read OR write);
SRAM_OE_N <= NOT read;
SRAM_WE_N <= NOT write;
END IF;
END PROCESS;
-- Internal Registers
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
is_read <= '0';
ELSE
is_read <= read;
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
is_write <= '0';
ELSE
is_write <= write;
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
writedata_reg <= writedata;
END IF;
END PROCESS;
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
-- Output Assignments
SRAM_DQ <= writedata_reg WHEN (is_write = '1') ELSE (OTHERS => 'Z');
-- Internal Assignments
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
END Behaviour;
| gpl-2.0 | 32d8bd5a0d67f16c68afbfb1777d04b3 | 0.421424 | 4.978788 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/mems/TrueDualPortRAM.vhdl | 1 | 4,990 | --
-- True Dual-Port RAM
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library FPGALIB;
use FPGALIB.MEMS.all;
entity TrueDualPortRAM is
generic (
AWIDTH : positive:=8; -- Address width
DWIDTH : positive:=8; -- Data width
DEPTH : natural:=0; -- Memory depth
SYNCMODE : syncmode_t:=WRITE_FIRST; -- Synchronization Mode
OUTREG : boolean :=FALSE -- Optional Output Register
);
port (
clk1_i : in std_logic;
clk2_i : in std_logic;
wen1_i : in std_logic;
wen2_i : in std_logic;
addr1_i : in std_logic_vector(AWIDTH-1 downto 0);
addr2_i : in std_logic_vector(AWIDTH-1 downto 0);
data1_i : in std_logic_vector(DWIDTH-1 downto 0);
data2_i : in std_logic_vector(DWIDTH-1 downto 0);
data1_o : out std_logic_vector(DWIDTH-1 downto 0);
data2_o : out std_logic_vector(DWIDTH-1 downto 0)
);
end entity TrueDualPortRAM;
architecture RTL of TrueDualPortRAM is
constant SIZE : positive:=getMemorySize(DEPTH,AWIDTH);
type ram_type is array(SIZE-1 downto 0) of std_logic_vector (DWIDTH-1 downto 0);
shared variable ram : ram_type;
signal data1, data2 : std_logic_vector(DWIDTH-1 downto 0);
begin
ram1_p:
process (clk1_i)
begin
if rising_edge(clk1_i) then
case SYNCMODE is
when READ_FIRST =>
if OUTREG then
data1 <= ram(to_integer(unsigned(addr1_i)));
data1_o <= data1;
else
data1_o <= ram(to_integer(unsigned(addr1_i)));
end if;
if wen1_i='1' then
ram(to_integer(unsigned(addr1_i))) := data1_i;
end if;
when WRITE_FIRST =>
if wen1_i='1' then
ram(to_integer(unsigned(addr1_i))) := data1_i;
if OUTREG then
data1 <= data1_i;
data1_o <= data1;
else
data1_o <= data1_i;
end if;
else
if OUTREG then
data1 <= ram(to_integer(unsigned(addr1_i)));
data1_o <= data1;
else
data1_o <= ram(to_integer(unsigned(addr1_i)));
end if;
end if;
when NO_CHANGE =>
if wen1_i='1' then
ram(to_integer(unsigned(addr1_i))) := data1_i;
else
if OUTREG then
data1 <= ram(to_integer(unsigned(addr1_i)));
data1_o <= data1;
else
data1_o <= ram(to_integer(unsigned(addr1_i)));
end if;
end if;
end case;
end if;
end process ram1_p;
ram2_p:
process (clk2_i)
begin
if rising_edge(clk2_i) then
case SYNCMODE is
when READ_FIRST =>
if OUTREG then
data2 <= ram(to_integer(unsigned(addr2_i)));
data2_o <= data2;
else
data2_o <= ram(to_integer(unsigned(addr2_i)));
end if;
if wen2_i='1' then
ram(to_integer(unsigned(addr2_i))) := data2_i;
end if;
when WRITE_FIRST =>
if wen2_i='1' then
ram(to_integer(unsigned(addr2_i))) := data2_i;
if OUTREG then
data2 <= data2_i;
data2_o <= data2;
else
data2_o <= data2_i;
end if;
else
if OUTREG then
data2 <= ram(to_integer(unsigned(addr2_i)));
data2_o <= data2;
else
data2_o <= ram(to_integer(unsigned(addr2_i)));
end if;
end if;
when NO_CHANGE =>
if wen2_i='1' then
ram(to_integer(unsigned(addr2_i))) := data2_i;
else
if OUTREG then
data2 <= ram(to_integer(unsigned(addr2_i)));
data2_o <= data2;
else
data2_o <= ram(to_integer(unsigned(addr2_i)));
end if;
end if;
end case;
end if;
end process ram2_p;
end architecture RTL;
| bsd-3-clause | ea0c940132ab66cdaadafe33c0dc69b3 | 0.429659 | 4.113768 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/mems/testbench/fifo_tb.vhdl | 1 | 16,634 | --
-- FIFO testbench
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.MEMs.all;
use FPGALIB.Simul.all;
entity FIFO_tb is
end entity FIFO_tb;
architecture TestBench of FIFO_tb is
constant DWIDTH : positive:=8;
constant DEPTH : positive:=5;
signal stop : boolean;
signal wclk, rclk : std_logic;
signal wrst, rrst : std_logic;
signal wen, ren : std_logic;
signal datai, datao : std_logic_vector(DWIDTH-1 downto 0);
signal full, empty : std_logic;
signal afull, aempty : std_logic;
signal over, under : std_logic;
signal valid : std_logic;
procedure wr_check(
full: in std_logic; vfull: in std_logic;
afull: in std_logic; vafull: in std_logic;
over: in std_logic; vover: in std_logic
) is
begin
assert full=vfull report "Wrong Full Flag" severity failure;
assert afull=vafull report "Wrong Almost Full Flag" severity failure;
assert over=vover report "Wrong Overflow Flag" severity failure;
end procedure wr_check;
procedure rd_check(
empty: in std_logic; vempty: in std_logic;
aempty: in std_logic; vaempty: in std_logic;
under: in std_logic; vunder: in std_logic
) is
begin
assert empty=vempty report "Wrong Empty Flag" severity failure;
assert aempty=vaempty report "Wrong Almost Empty Flag" severity failure;
assert under=vunder report "Wrong Underflow Flag" severity failure;
end procedure rd_check;
procedure ctrl(
signal clk: in std_logic;
signal wen: out std_logic;
wen_val: in std_logic;
signal ren: out std_logic;
ren_val: in std_logic;
signal data: out std_logic_vector;
data_val: in std_logic_vector;
wr_num: inout natural;
rd_num: inout natural
) is
begin
if wen_val='1' and ren_val='1' then
print("Write "&to_str(wr_num)&" - Read "&to_str(rd_num));
wr_num := wr_num + 1;
rd_num := rd_num + 1;
elsif wen_val='1' then
print("Write "&to_str(wr_num));
wr_num := wr_num + 1;
elsif ren_val='1' then
print("Read "&to_str(rd_num));
rd_num := rd_num + 1;
else
print("Nop");
end if;
wen <= wen_val;
ren <= ren_val;
data <= data_val;
wait until rising_edge(clk);
end procedure ctrl;
begin
wr_clock_i : Clock
generic map(FREQUENCY => 2)
port map(clk_o => wclk, rst_o => wrst, stop_i => stop);
rd_clock_i : Clock
generic map(FREQUENCY => 3)
port map(clk_o => rclk, rst_o => rrst, stop_i => stop);
fifo_sync_i: fifo
generic map (
DWIDTH => DWIDTH,
DEPTH => DEPTH,
OUTREG => FALSE,
AFULLOFFSET => 1,
AEMPTYOFFSET => 2,
ASYNC => FALSE
)
port map (
-- write side
wclk_i => wclk,
wrst_i => wrst,
wen_i => wen,
data_i => datai,
full_o => full,
afull_o => afull,
overflow_o => over,
-- read side
rclk_i => wclk,
rrst_i => wrst,
ren_i => ren,
data_o => datao,
empty_o => empty,
aempty_o => aempty,
underflow_o => under,
valid_o => valid
);
fifo_async_i: fifo
generic map (
DWIDTH => DWIDTH,
DEPTH => DEPTH,
OUTREG => FALSE,
AFULLOFFSET => 1,
AEMPTYOFFSET => 2,
ASYNC => TRUE
)
port map (
-- write side
wclk_i => wclk,
wrst_i => wrst,
wen_i => wen,
data_i => datai,
full_o => open,--full,
afull_o => open,--afull,
overflow_o => open,--over,
-- read side
rclk_i => rclk,
rrst_i => rrst,
ren_i => ren,
data_o => open,--datao,
empty_o => open,--empty,
aempty_o => open,--aempty,
underflow_o => open,--under,
valid_o => open --valid
);
test_p : process
variable wr_num, rd_num: natural:=1;
begin
ctrl(wclk, wen, '0', ren, '0', datai, x"00", wr_num, rd_num);
print("* Start of Test (DEPTH="&to_str(DEPTH)&")");
wait until rising_edge(wclk) and wrst = '0';
wr_check(full, '0', afull, '0', over, '0');
print("* Testing Write");
ctrl(wclk, wen, '1', ren, '0', datai, x"11", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"22", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"33", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"44", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"55", wr_num, rd_num); wr_check(full, '0', afull, '1', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"66", wr_num, rd_num); wr_check(full, '1', afull, '1', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"77", wr_num, rd_num); wr_check(full, '1', afull, '1', over, '1');
ctrl(wclk, wen, '0', ren, '0', datai, datai, wr_num, rd_num); wr_check(full, '1', afull, '1', over, '0');
print("* Testing Read");
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '0', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '0', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '0', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '1');
ctrl(wclk, wen, '0', ren, '0', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '0');
print("* Testing Write");
ctrl(wclk, wen, '1', ren, '0', datai, x"88", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"99", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"AA", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"BB", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"CC", wr_num, rd_num); wr_check(full, '0', afull, '1', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"DD", wr_num, rd_num); wr_check(full, '1', afull, '1', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"EE", wr_num, rd_num); wr_check(full, '1', afull, '1', over, '1');
ctrl(wclk, wen, '0', ren, '0', datai, datai, wr_num, rd_num); wr_check(full, '1', afull, '1', over, '0');
print("* Testing Read");
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '0', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '0', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '0', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '1');
ctrl(wclk, wen, '0', ren, '0', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '0');
print("* Testing Write");
ctrl(wclk, wen, '1', ren, '0', datai, x"FF", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"00", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"11", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"22", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"33", wr_num, rd_num); wr_check(full, '0', afull, '1', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"44", wr_num, rd_num); wr_check(full, '1', afull, '1', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"55", wr_num, rd_num); wr_check(full, '1', afull, '1', over, '1');
ctrl(wclk, wen, '0', ren, '0', datai, datai, wr_num, rd_num); wr_check(full, '1', afull, '1', over, '0');
print("* Testing Read");
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '0', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '0', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '0', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '1');
ctrl(wclk, wen, '0', ren, '0', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '0');
print("* Testing Write+Read");
ctrl(wclk, wen, '1', ren, '0', datai, x"66", wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"77", wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '1', ren, '1', datai, x"88", wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"99", wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '1', ren, '1', datai, x"AA", wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '1', ren, '1', datai, x"BB", wr_num, rd_num);
ctrl(wclk, wen, '1', ren, '1', datai, x"CC", wr_num, rd_num);
ctrl(wclk, wen, '1', ren, '0', datai, x"DD", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"EE", wr_num, rd_num); wr_check(full, '0', afull, '1', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"FF", wr_num, rd_num); wr_check(full, '1', afull, '1', over, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num);
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num);
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '0', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '0', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '0');
print("* End of Test");
stop <= TRUE;
wait;
end process test_p;
read_p : process
begin
wait until rising_edge(wclk) and valid = '1';
assert datao=x"11" report "Received 0x"&to_str(datao,'H')&" but 0x11 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"22" report "Received 0x"&to_str(datao,'H')&" but 0x22 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"33" report "Received 0x"&to_str(datao,'H')&" but 0x33 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"44" report "Received 0x"&to_str(datao,'H')&" but 0x44 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"55" report "Received 0x"&to_str(datao,'H')&" but 0x55 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"66" report "Received 0x"&to_str(datao,'H')&" but 0x77 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
-- x"77" was overflow
assert datao=x"88" report "Received 0x"&to_str(datao,'H')&" but 0x88 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"99" report "Received 0x"&to_str(datao,'H')&" but 0x99 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"AA" report "Received 0x"&to_str(datao,'H')&" but 0xAA awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"BB" report "Received 0x"&to_str(datao,'H')&" but 0xBB awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"CC" report "Received 0x"&to_str(datao,'H')&" but 0xDD awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"DD" report "Received 0x"&to_str(datao,'H')&" but 0xEE awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
-- x"CC" was overflow
assert datao=x"FF" report "Received 0x"&to_str(datao,'H')&" but 0xFF awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"00" report "Received 0x"&to_str(datao,'H')&" but 0x00 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"11" report "Received 0x"&to_str(datao,'H')&" but 0x11 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"22" report "Received 0x"&to_str(datao,'H')&" but 0x33 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"33" report "Received 0x"&to_str(datao,'H')&" but 0x33 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"44" report "Received 0x"&to_str(datao,'H')&" but 0x44 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
-- x"55" was overflow
assert datao=x"66" report "Received 0x"&to_str(datao,'H')&" but 0x66 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"77" report "Received 0x"&to_str(datao,'H')&" but 0x77 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"88" report "Received 0x"&to_str(datao,'H')&" but 0x88 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"99" report "Received 0x"&to_str(datao,'H')&" but 0x99 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"AA" report "Received 0x"&to_str(datao,'H')&" but 0xAA awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"BB" report "Received 0x"&to_str(datao,'H')&" but 0xBB awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"CC" report "Received 0x"&to_str(datao,'H')&" but 0xBB awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"DD" report "Received 0x"&to_str(datao,'H')&" but 0xBB awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"EE" report "Received 0x"&to_str(datao,'H')&" but 0xBB awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"FF" report "Received 0x"&to_str(datao,'H')&" but 0xBB awaited" severity failure;
wait;
end process read_p;
end architecture TestBench;
| bsd-3-clause | 3725a5f56947e71009cfd63435ad8f33 | 0.559757 | 2.883842 | false | false | false | false |
hoglet67/ElectronFpga | src/common/RAM/RAM_20K_DualPort.vhd | 1 | 1,251 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RAM_20K_DualPort is
port (
clka : in std_logic;
wea : in std_logic;
addra : in std_logic_vector(14 downto 0);
dina : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0);
clkb : in std_logic;
web : in std_logic;
addrb : in std_logic_vector(14 downto 0);
dinb : in std_logic_vector(7 downto 0);
doutb : out std_logic_vector(7 downto 0)
);
end;
architecture behavioral of RAM_20K_DualPort is
-- FIXME
type ram_type is array (0 to 20 * 1024 - 1) of std_logic_vector (7 downto 0);
shared variable RAM : ram_type;
begin
process (clka)
begin
if rising_edge(clka) then
if (wea = '1') then
RAM(conv_integer(addra)) := dina;
end if;
douta <= RAM(conv_integer(addra));
end if;
end process;
process (clkb)
begin
if rising_edge(clkb) then
if (web = '1') then
RAM(conv_integer(addrb)) := dinb;
end if;
doutb <= RAM(conv_integer(addrb));
end if;
end process;
end behavioral;
| gpl-3.0 | 817323750200141ab3ff78ba274cc288 | 0.545963 | 3.523944 | false | false | false | false |
ou-cse-378/vhdl-tetris | random.vhd | 1 | 1,411 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: random.vhd
-- // Date: 12/9/2004
-- // Description: Random Number Generator
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity random is
Port ( iClk : in std_logic;
iClr : in std_logic;
oRandom : out std_logic_vector(2 downto 0);
iT : in std_logic_vector(15 downto 0);
iP : in std_logic_vector(15 downto 0);
iM : in std_logic_vector(15 downto 0);
iX : in std_logic_vector(3 downto 0);
iY : in std_logic_vector(4 downto 0));
end random;
architecture Behavioral of random is
begin
Random: process(iClr, iClk)
begin
if iClr = '1' then
oRandom <= "000";
elsif (iClk'event and iClk = '1') then
oRandom(0) <= iT(0) xor iP(1) xor iM(2) xor iX(2) xor iY(1);
oRandom(1) <= iT(1) xor iP(2) xor iM(0) xor iX(1) xor iY(3);
oRandom(2) <= iT(2) xor iP(0) xor iM(1) xor iX(0) xor iY(2);
end if;
end process;
end Behavioral;
| mit | e4dd6a0b78fd678ca5256dd7ee40267c | 0.559178 | 3.273782 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_timer_0.vhd | 1 | 10,474 | --Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tracking_camera_system_timer_0 is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal chipselect : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal write_n : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- outputs:
signal irq : OUT STD_LOGIC;
signal readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end entity tracking_camera_system_timer_0;
architecture europa of tracking_camera_system_timer_0 is
signal clk_en : STD_LOGIC;
signal control_continuous : STD_LOGIC;
signal control_interrupt_enable : STD_LOGIC;
signal control_register : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal control_wr_strobe : STD_LOGIC;
signal counter_is_running : STD_LOGIC;
signal counter_is_zero : STD_LOGIC;
signal counter_load_value : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal counter_snapshot : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal delayed_unxcounter_is_zeroxx0 : STD_LOGIC;
signal do_start_counter : STD_LOGIC;
signal do_stop_counter : STD_LOGIC;
signal force_reload : STD_LOGIC;
signal internal_counter : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal period_h_register : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal period_h_wr_strobe : STD_LOGIC;
signal period_l_register : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal period_l_wr_strobe : STD_LOGIC;
signal read_mux_out : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal snap_h_wr_strobe : STD_LOGIC;
signal snap_l_wr_strobe : STD_LOGIC;
signal snap_read_value : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal snap_strobe : STD_LOGIC;
signal start_strobe : STD_LOGIC;
signal status_wr_strobe : STD_LOGIC;
signal stop_strobe : STD_LOGIC;
signal timeout_event : STD_LOGIC;
signal timeout_occurred : STD_LOGIC;
begin
clk_en <= std_logic'('1');
process (clk, reset_n)
begin
if reset_n = '0' then
internal_counter <= std_logic_vector'("00000000000000011000011010011111");
elsif clk'event and clk = '1' then
if std_logic'((counter_is_running OR force_reload)) = '1' then
if std_logic'((counter_is_zero OR force_reload)) = '1' then
internal_counter <= counter_load_value;
else
internal_counter <= A_EXT (((std_logic_vector'("0") & (internal_counter)) - std_logic_vector'("000000000000000000000000000000001")), 32);
end if;
end if;
end if;
end process;
counter_is_zero <= to_std_logic((internal_counter = std_logic_vector'("00000000000000000000000000000000")));
counter_load_value <= period_h_register & period_l_register;
process (clk, reset_n)
begin
if reset_n = '0' then
force_reload <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
force_reload <= period_h_wr_strobe OR period_l_wr_strobe;
end if;
end if;
end process;
do_start_counter <= start_strobe;
do_stop_counter <= ((stop_strobe) OR (force_reload)) OR ((counter_is_zero AND NOT control_continuous));
process (clk, reset_n)
begin
if reset_n = '0' then
counter_is_running <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
if std_logic'(do_start_counter) = '1' then
counter_is_running <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
elsif std_logic'(do_stop_counter) = '1' then
counter_is_running <= std_logic'('0');
end if;
end if;
end if;
end process;
--delayed_unxcounter_is_zeroxx0, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
delayed_unxcounter_is_zeroxx0 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end if;
end if;
end process;
timeout_event <= (counter_is_zero) AND NOT (delayed_unxcounter_is_zeroxx0);
process (clk, reset_n)
begin
if reset_n = '0' then
timeout_occurred <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
if std_logic'(status_wr_strobe) = '1' then
timeout_occurred <= std_logic'('0');
elsif std_logic'(timeout_event) = '1' then
timeout_occurred <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
end if;
end if;
end if;
end process;
irq <= timeout_occurred AND control_interrupt_enable;
--s1, which is an e_avalon_slave
read_mux_out <= ((((((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000010")))), 16) AND period_l_register)) OR ((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000011")))), 16) AND period_h_register))) OR ((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000100")))), 16) AND snap_read_value(15 DOWNTO 0)))) OR ((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000101")))), 16) AND snap_read_value(31 DOWNTO 16)))) OR ((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000001")))), 16) AND (std_logic_vector'("000000000000") & (control_register))))) OR ((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000")))), 16) AND (std_logic_vector'("00000000000000") & (Std_Logic_Vector'(A_ToStdLogicVector(counter_is_running) & A_ToStdLogicVector(timeout_occurred))))));
process (clk, reset_n)
begin
if reset_n = '0' then
readdata <= std_logic_vector'("0000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
readdata <= read_mux_out;
end if;
end if;
end process;
period_l_wr_strobe <= (chipselect AND NOT write_n) AND to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000010"))));
period_h_wr_strobe <= (chipselect AND NOT write_n) AND to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000011"))));
process (clk, reset_n)
begin
if reset_n = '0' then
period_l_register <= std_logic_vector'("1000011010011111");
elsif clk'event and clk = '1' then
if std_logic'(period_l_wr_strobe) = '1' then
period_l_register <= writedata;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
period_h_register <= std_logic_vector'("0000000000000001");
elsif clk'event and clk = '1' then
if std_logic'(period_h_wr_strobe) = '1' then
period_h_register <= writedata;
end if;
end if;
end process;
snap_l_wr_strobe <= (chipselect AND NOT write_n) AND to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000100"))));
snap_h_wr_strobe <= (chipselect AND NOT write_n) AND to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000101"))));
snap_strobe <= snap_l_wr_strobe OR snap_h_wr_strobe;
process (clk, reset_n)
begin
if reset_n = '0' then
counter_snapshot <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(snap_strobe) = '1' then
counter_snapshot <= internal_counter;
end if;
end if;
end process;
snap_read_value <= counter_snapshot;
control_wr_strobe <= (chipselect AND NOT write_n) AND to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000001"))));
process (clk, reset_n)
begin
if reset_n = '0' then
control_register <= std_logic_vector'("0000");
elsif clk'event and clk = '1' then
if std_logic'(control_wr_strobe) = '1' then
control_register <= writedata(3 DOWNTO 0);
end if;
end if;
end process;
stop_strobe <= writedata(3) AND control_wr_strobe;
start_strobe <= writedata(2) AND control_wr_strobe;
control_continuous <= control_register(1);
control_interrupt_enable <= control_register(0);
status_wr_strobe <= (chipselect AND NOT write_n) AND to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000"))));
end europa;
| gpl-2.0 | 12b1d4387b1fb6b5796640cfc677667c | 0.644357 | 3.879259 | false | false | false | false |
rtucker/nios_codebreaker | vhdl/lfsr_peripheral.vhd | 1 | 7,660 | --************************** VHDL Source Code ****************************
--*************************************************************************
-- vim: set ts=2 sw=2 tw=78 et :
--
-- DESIGNER NAME: Ryan S. Tucker <[email protected]>
--
-- LAB NAME: Lab 7: Game System
--
-- FILE NAME: lfsr_peripheral.vhd
--
---------------------------------------------------------------------------
--
-- DESCRIPTION
--
-- This design will implement a 16-bit Galois linear-feedback shift
-- register for pseudorandom number generation.
--
-- About LFSRs:
-- https://en.wikipedia.org/wiki/Linear_feedback_shift_register
--
-- Addresses of this component:
-- 0 status R bit 0: 1 if LFSR is seeded, 0 if not
-- bit 1: 1 if seed value is nonzero, 0 if zero
-- 1 control W bit 0: 1 to reseed LFSR from seed register
-- (note: status bit 1 MUST be 1 first)
-- 2 lfsr R current 16-bit LFSR value
-- 3 seed RW seed value for LFSR
--
---------------------------------------------------------------------------
--
-- REVISION HISTORY
--
-- ______________________________________________________________________
-- | DATE | USER | Ver | Description |
-- |==========+======+=====+==============================================
-- | | | |
-- | 04/21/13 | RST | 1.0 | Created
-- | | | |
-- |----------|------|-----|----------------------------------------------
--
--*************************************************************************
--*************************************************************************
library IEEE;
use IEEE.std_logic_1164.ALL;
--use IEEE.numeric_std.ALL;
--use IEEE.numeric_std_unsigned.ALL;
use IEEE.std_logic_unsigned.ALL;
entity lfsr_peripheral is
port (
-- inputs
clk : in std_logic;
reset_n : in std_logic;
we_n : in std_logic;
be_n : in std_logic_vector(1 downto 0);
a : in std_logic_vector(1 downto 0);
din : in std_logic_vector(15 downto 0);
-- outputs
dout : out std_logic_vector(15 downto 0)
);
end entity lfsr_peripheral;
architecture rtl of lfsr_peripheral is
-- constants
constant STAT_ADDR : std_logic_vector(1 downto 0) := "00";
constant CTRL_ADDR : std_logic_vector(1 downto 0) := "01";
constant LFSR_ADDR : std_logic_vector(1 downto 0) := "10";
constant SEED_ADDR : std_logic_vector(1 downto 0) := "11";
constant READ : std_logic := '1';
constant WRITE : std_logic := '0';
constant RESET : std_logic := '0';
constant BYTE_EN : std_logic := '0';
constant UNSEEDED : std_logic := '0';
constant SEEDED : std_logic := '1';
constant INVALID : std_logic := '0';
constant VALID : std_logic := '1';
constant NOTNOW : std_logic := '0';
constant DOITNOW : std_logic := '1';
constant ZEROS_8 : std_logic_vector := "00000000";
-- internal signals
signal din_h : std_logic_vector(7 downto 0);
signal din_l : std_logic_vector(7 downto 0);
signal be_n_h : std_logic;
signal be_n_l : std_logic;
-- registers
signal reg_seed_h : std_logic_vector(7 downto 0);
signal reg_seed_l : std_logic_vector(7 downto 0);
signal reg_lfsr : std_logic_vector(15 downto 0);
signal reg_stat : std_logic_vector(15 downto 0);
-- control and status flags
signal is_seeded : std_logic := UNSEEDED;
signal seed_valid : std_logic := INVALID;
signal ctrl_doseed : std_logic := NOTNOW;
begin
-- combinational logic: break down long signals into shorter ones, and
-- vice versa
din_h <= din(15 downto 8);
din_l <= din(7 downto 0);
be_n_h <= be_n(1);
be_n_l <= be_n(0);
-- test seed validity
seed_valid <= INVALID when (reg_seed_h = ZEROS_8 and reg_seed_l = ZEROS_8)
else VALID;
-- process: seed_register_p
-- handle writes to the seed register
-- control inputs: a, we_n, be_n_h
-- bus output: din
-- registers: reg_seed_h, reg_seed_l
seed_register_p : process(clk, reset_n) is
begin
if (reset_n = RESET) then
-- Reset seed register to zero
reg_seed_h <= (others => '0');
reg_seed_l <= (others => '0');
elsif (rising_edge(clk)) then
if (a = SEED_ADDR and we_n = WRITE and be_n_h = BYTE_EN) then
reg_seed_h <= din_h;
end if;
if (a = SEED_ADDR and we_n = WRITE and be_n_l = BYTE_EN) then
reg_seed_l <= din_l;
end if;
end if;
end process seed_register_p;
-- process: lfsr_register_p
-- implements the linear feedback shift register
-- control input: ctrl_doseed
-- status output: is_seeded
-- register: reg_lfsr
lfsr_register_p : process(clk, reset_n) is
variable carry_bit : std_logic;
variable new_lfsr : std_logic_vector(15 downto 0);
begin
if (reset_n = RESET) then
-- Reset LFSR register to all-ones
-- (as 0 is an invalid state)
reg_lfsr <= (others => '1');
is_seeded <= UNSEEDED;
elsif (rising_edge(clk)) then
if (ctrl_doseed = DOITNOW) then
-- replace our LFSR with the seed
reg_lfsr <= reg_seed_h & reg_seed_l;
is_seeded <= SEEDED;
else
-- recirculating shift right, with carry bit xor'd at
-- taps: 16, 14, 13, 11
carry_bit := reg_lfsr(0);
new_lfsr(15) := carry_bit;
new_lfsr(14) := reg_lfsr(15) ;
new_lfsr(13) := reg_lfsr(14) xor carry_bit;
new_lfsr(12) := reg_lfsr(13) xor carry_bit;
new_lfsr(11) := reg_lfsr(12);
new_lfsr(10) := reg_lfsr(11) xor carry_bit;
new_lfsr(9 downto 0) := reg_lfsr(10 downto 1);
-- update register
reg_lfsr <= new_lfsr;
end if;
end if;
end process lfsr_register_p;
-- process: ctrl_register_p
-- implements a write-only control register
-- control inputs: a, we_n, be_n_l, seed_valid
-- control output: ctrl_doseed
ctrl_register_p : process(clk, reset_n) is
begin
if (reset_n = RESET) then
ctrl_doseed <= NOTNOW;
elsif (rising_edge(clk)) then
if (a = CTRL_ADDR and we_n = WRITE and be_n_l = BYTE_EN
and seed_valid = VALID) then
ctrl_doseed <= DOITNOW;
else
ctrl_doseed <= NOTNOW;
end if;
end if;
end process ctrl_register_p;
-- process: stat_register_p
-- updates a read-only status register
-- status inputs: is_seeded, seed_valid
-- register: reg_stat
stat_register_p : process(clk, reset_n) is
begin
if (reset_n = RESET) then
reg_stat <= (others => '0');
elsif (rising_edge(clk)) then
reg_stat <= (others => '0');
reg_stat(0) <= is_seeded;
reg_stat(1) <= seed_valid;
end if;
end process stat_register_p;
-- process: register_read_p
-- selects requested register values to the dout bus
-- control input: a
-- bus output: dout
register_read_p : process(clk, reset_n) is
begin
if (reset_n = RESET) then
dout <= (others => '0');
elsif (rising_edge(clk)) then
case a is
when STAT_ADDR =>
dout <= reg_stat;
when LFSR_ADDR =>
dout <= reg_lfsr;
when SEED_ADDR =>
dout <= reg_seed_h & reg_seed_l;
when others =>
dout <= (others => '0');
end case;
end if;
end process register_read_p;
end architecture rtl;
| mit | f73d596c6e4daf57c9afdcebec01a4dd | 0.510444 | 3.444245 | false | false | false | false |
DreamIP/GPStudio | support/process/debayer33/debayer33.vhd | 1 | 4,826 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity debayer33 is
generic( CLK_PROC_FREQ : integer;
IM_WIDTH : integer := 1280;
IM_HEIGHT : integer := 960;
COLOR_CHANNELS : integer := 3;
DATA_SIZE : integer := 8
);
port(
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(DATA_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_fv : out std_logic;
out_dv : out std_logic;
out_data : out std_logic_vector((COLOR_CHANNELS*DATA_SIZE)-1 downto 0);
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0);
------------------------- for sim -------------------------
sim_en : in std_logic;
bayer_code_sim : in std_logic_vector(1 downto 0);
test_count_x_out : out std_logic_vector(integer(ceil(log2(real(IM_WIDTH))))-1 downto 0);
test_count_y_out : out std_logic_vector(integer(ceil(log2(real(IM_HEIGHT))))-1 downto 0)
);
end entity;
architecture structural of debayer33 is
component debayer33_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
bayer_code : out std_logic_vector(1 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
component debayer33_process is
generic( CLK_PROC_FREQ : integer;
IM_WIDTH : integer := 1280;
IM_HEIGHT : integer := 960;
COLOR_CHANNELS : integer := 3;
DATA_SIZE : integer := 8
);
port(
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- from slave -------------------------
bayer_code_slave : in std_logic_vector(1 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(DATA_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector((COLOR_CHANNELS*DATA_SIZE)-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
------------------------- for sim -------------------------
sim_en : in std_logic;
bayer_code_sim : in std_logic_vector(1 downto 0);
test_count_x_out : out std_logic_vector(integer(ceil(log2(real(IM_WIDTH))))-1 downto 0);
test_count_y_out : out std_logic_vector(integer(ceil(log2(real(IM_HEIGHT))))-1 downto 0)
);
end component;
signal bayer_code_slave_int : std_logic_vector(1 downto 0);
begin
u0 : debayer33_slave
generic map(
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map(
clk_proc => clk_proc,
reset_n => reset_n,
---------------- dynamic parameters ports ---------------
status_reg_enable_bit => open,
bayer_code => bayer_code_slave_int,
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
u1 : debayer33_process
generic map(
CLK_PROC_FREQ => CLK_PROC_FREQ,
IM_WIDTH => IM_WIDTH,
IM_HEIGHT => IM_HEIGHT,
COLOR_CHANNELS => COLOR_CHANNELS,
DATA_SIZE => DATA_SIZE
)
port map(
clk_proc => clk_proc,
reset_n => reset_n,
------------------------- from slave -------------------------
bayer_code_slave=> bayer_code_slave_int,
------------------------- in flow -----------------------
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
------------------------ out flow -----------------------
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv,
------------------------- for sim -------------------------
sim_en => sim_en,
bayer_code_sim => bayer_code_sim,
test_count_x_out => test_count_x_out,
test_count_y_out => test_count_y_out
);
end architecture; | gpl-3.0 | f24f34adb1a0ccb080166ab8fd4dc447 | 0.472234 | 3.202389 | false | true | false | false |
DreamIP/GPStudio | support/process/negate/hdl/negate.vhd | 1 | 3,484 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity negate is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end negate;
architecture rtl of negate is
component negate_process
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component negate_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
begin
negate_process_inst : negate_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
negate_slave_inst : negate_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
| gpl-3.0 | ea82a03c76adbc7b737683797b6ed5ff | 0.438289 | 3.459782 | false | false | false | false |
DreamIP/GPStudio | support/component/gp_com/flow_to_com/write_flow.vhd | 1 | 3,388 | -- **************************************************************************
-- READ FLOW
-- **************************************************************************
-- Ce composant est connecte a un com_flow_fifo en entree et a un processing (FV/LV/Data) en sortie
--
-- 16/10/2014 - creation
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ComFlow_pkg.all;
-- Transform FV/DV/Data en flow
entity write_flow is
generic (
PACKET_SIZE : integer := 255;
FLAGS_CODES : my_array_t := InitFlagCodes
);
port (
clk : in std_logic;
rst_n : in std_logic;
in_data : in std_logic_vector(15 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
enable_i : in std_logic;
fifo_f_i : in std_logic;
data_wr_o : out std_logic;
data_o : out std_logic_vector(15 downto 0);
flag_wr_o : out std_logic;
flag_o : out std_logic_vector(7 downto 0);
fifo_pkt_wr_o : out std_logic;
fifo_pkt_data_o : out std_logic_vector(15 downto 0)
);
end write_flow;
architecture rtl of write_flow is
---------------------------------------------------------
-- SIGNALS
---------------------------------------------------------
signal fv_r : std_logic := '0';
signal dv_r : std_logic := '0';
signal skip : std_logic := '0';
signal flag_wr_cpt_s : std_logic := '0';
signal flag_wr_cpt_s_r : std_logic := '0';
signal flag_wr_fv_s : std_logic := '0';
signal fifo_pkt_data_s : std_logic_vector(15 downto 0) := (others=>'0');
begin
FSM:process (clk, rst_n)
variable cpt : integer range 0 to PACKET_SIZE:=0;
begin
if (rst_n = '0') then
fv_r <='0';
dv_r <='0';
flag_o <= (others=>'0');
skip <= '0';
cpt:=0;
flag_wr_fv_s<='0';
flag_wr_cpt_s<='0';
flag_wr_cpt_s_r <='0';
elsif rising_edge(clk) then
fv_r <= in_fv;
dv_r <= in_dv;
flag_wr_fv_s <= '0';
flag_wr_cpt_s <= '0';
flag_wr_cpt_s_r <= flag_wr_cpt_s;
if(enable_i = '1') then
if (in_dv = '1' and fifo_f_i = '0') then
cpt := cpt + 1;
end if;
if (fv_r = '1' and in_fv = '0') then
flag_wr_fv_s <= '1';
flag_o <= FLAGS_CODES(EoF);
skip <= '0';
fifo_pkt_data_s <= std_logic_vector(to_unsigned(cpt,16));
cpt := 0;
elsif (cpt = (PACKET_SIZE-2) and skip = '1') then
flag_wr_cpt_s <= '1';
flag_o <= FLAGS_CODES(EoL);
fifo_pkt_data_s <= std_logic_vector(to_unsigned(cpt,16));
cpt := 0;
elsif (cpt = (PACKET_SIZE-2) and skip = '0') then
skip <='1';
flag_wr_cpt_s <= '1';
flag_o <= FLAGS_CODES(SoF);
fifo_pkt_data_s <= std_logic_vector(to_unsigned(cpt,16));
cpt := 0;
end if;
end if;
end if;
end process;
-- data_wr_o <= in_dv and enable_i and not(fifo_f_i); -- Add in_fv in condition to avoid data write if fv = 0
data_wr_o <= in_dv and enable_i and not(fifo_f_i) and in_fv;
data_o <= in_data;
flag_wr_o <= flag_wr_fv_s or (flag_wr_cpt_s_r and in_fv);
fifo_pkt_wr_o <= flag_wr_fv_s or (flag_wr_cpt_s_r and in_fv);
fifo_pkt_data_o <= fifo_pkt_data_s;
end rtl;
| gpl-3.0 | 251913888edc1eafce896d1e57c65740 | 0.472255 | 2.918174 | false | false | false | false |
SonicFrog/ArchOrd | piso.vhdl | 1 | 916 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity PISO is
port (
Pattern : in std_logic_vector(7 downto 0);
DataIn : in std_logic;
Load : in std_logic;
Reset : in std_logic;
Clk : in std_logic;
Found : out std_logic
);
end entity; --PISO
architecture synth of piso is
signal content : std_logic_vector(7 downto 0);
signal reg_pattern : std_logic_vector(7 downto 0);
begin
load : process(Clk, Load, DataIn)
begin
if rising_edge(Clk) then
if Reset = '1' then
reg_pattern <= (others => '0')
elsif Load = '1' then
reg_pattern <= Pattern;
end if;
end if;
end process;
input_handle : process(Clk, Pattern)
begin
if rising_edge(Clk) then
content <= content(7 downto 1) & DataIn;
end if;
end process;
Found <= '1' when content = reg_pattern else '0';
end architecture ; -- synth | gpl-2.0 | c1fb3d779fe0fc1868abe86bf56cf131 | 0.648472 | 2.647399 | false | false | false | false |
DreamIP/GPStudio | support/process/laplacian/hdl/laplacian_slave.vhd | 1 | 9,606 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity laplacian_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
w00_reg_m00 : out std_logic_vector(7 downto 0);
w01_reg_m01 : out std_logic_vector(7 downto 0);
w02_reg_m02 : out std_logic_vector(7 downto 0);
w10_reg_m10 : out std_logic_vector(7 downto 0);
w11_reg_m11 : out std_logic_vector(7 downto 0);
w12_reg_m12 : out std_logic_vector(7 downto 0);
w20_reg_m20 : out std_logic_vector(7 downto 0);
w21_reg_m21 : out std_logic_vector(7 downto 0);
w22_reg_m22 : out std_logic_vector(7 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end laplacian_slave;
architecture rtl of laplacian_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant WIDTHIMG_REG_REG_ADDR : natural := 1;
constant W00_REG_REG_ADDR : natural := 2;
constant W01_REG_REG_ADDR : natural := 3;
constant W02_REG_REG_ADDR : natural := 4;
constant W10_REG_REG_ADDR : natural := 5;
constant W11_REG_REG_ADDR : natural := 6;
constant W12_REG_REG_ADDR : natural := 7;
constant W20_REG_REG_ADDR : natural := 8;
constant W21_REG_REG_ADDR : natural := 9;
constant W22_REG_REG_ADDR : natural := 10;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal widthimg_reg_width_reg : std_logic_vector (15 downto 0);
signal w00_reg_m00_reg : std_logic_vector (7 downto 0);
signal w01_reg_m01_reg : std_logic_vector (7 downto 0);
signal w02_reg_m02_reg : std_logic_vector (7 downto 0);
signal w10_reg_m10_reg : std_logic_vector (7 downto 0);
signal w11_reg_m11_reg : std_logic_vector (7 downto 0);
signal w12_reg_m12_reg : std_logic_vector (7 downto 0);
signal w20_reg_m20_reg : std_logic_vector (7 downto 0);
signal w21_reg_m21_reg : std_logic_vector (7 downto 0);
signal w22_reg_m22_reg : std_logic_vector (7 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
widthimg_reg_width_reg <= "0000000000000000";
w00_reg_m00_reg <= "00000000";
w01_reg_m01_reg <= "00000000";
w02_reg_m02_reg <= "00000000";
w10_reg_m10_reg <= "00000000";
w11_reg_m11_reg <= "00000000";
w12_reg_m12_reg <= "00000000";
w20_reg_m20_reg <= "00000000";
w21_reg_m21_reg <= "00000000";
w22_reg_m22_reg <= "00000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
status_reg_enable_bit_reg <= datawr_i(0);
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
widthimg_reg_width_reg <= datawr_i(15) & datawr_i(14) & datawr_i(13) & datawr_i(12) & datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(W00_REG_REG_ADDR, 4))=>
w00_reg_m00_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(W01_REG_REG_ADDR, 4))=>
w01_reg_m01_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(W02_REG_REG_ADDR, 4))=>
w02_reg_m02_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(W10_REG_REG_ADDR, 4))=>
w10_reg_m10_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(W11_REG_REG_ADDR, 4))=>
w11_reg_m11_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(W12_REG_REG_ADDR, 4))=>
w12_reg_m12_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(W20_REG_REG_ADDR, 4))=>
w20_reg_m20_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(W21_REG_REG_ADDR, 4))=>
w21_reg_m21_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(W22_REG_REG_ADDR, 4))=>
w22_reg_m22_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000000000000000000" & status_reg_enable_bit_reg;
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000" & widthimg_reg_width_reg(15) & widthimg_reg_width_reg(14) & widthimg_reg_width_reg(13) & widthimg_reg_width_reg(12) & widthimg_reg_width_reg(11) & widthimg_reg_width_reg(10) & widthimg_reg_width_reg(9) & widthimg_reg_width_reg(8) & widthimg_reg_width_reg(7) & widthimg_reg_width_reg(6) & widthimg_reg_width_reg(5) & widthimg_reg_width_reg(4) & widthimg_reg_width_reg(3) & widthimg_reg_width_reg(2) & widthimg_reg_width_reg(1) & widthimg_reg_width_reg(0);
when std_logic_vector(to_unsigned(W00_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & w00_reg_m00_reg(7) & w00_reg_m00_reg(6) & w00_reg_m00_reg(5) & w00_reg_m00_reg(4) & w00_reg_m00_reg(3) & w00_reg_m00_reg(2) & w00_reg_m00_reg(1) & w00_reg_m00_reg(0);
when std_logic_vector(to_unsigned(W01_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & w01_reg_m01_reg(7) & w01_reg_m01_reg(6) & w01_reg_m01_reg(5) & w01_reg_m01_reg(4) & w01_reg_m01_reg(3) & w01_reg_m01_reg(2) & w01_reg_m01_reg(1) & w01_reg_m01_reg(0);
when std_logic_vector(to_unsigned(W02_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & w02_reg_m02_reg(7) & w02_reg_m02_reg(6) & w02_reg_m02_reg(5) & w02_reg_m02_reg(4) & w02_reg_m02_reg(3) & w02_reg_m02_reg(2) & w02_reg_m02_reg(1) & w02_reg_m02_reg(0);
when std_logic_vector(to_unsigned(W10_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & w10_reg_m10_reg(7) & w10_reg_m10_reg(6) & w10_reg_m10_reg(5) & w10_reg_m10_reg(4) & w10_reg_m10_reg(3) & w10_reg_m10_reg(2) & w10_reg_m10_reg(1) & w10_reg_m10_reg(0);
when std_logic_vector(to_unsigned(W11_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & w11_reg_m11_reg(7) & w11_reg_m11_reg(6) & w11_reg_m11_reg(5) & w11_reg_m11_reg(4) & w11_reg_m11_reg(3) & w11_reg_m11_reg(2) & w11_reg_m11_reg(1) & w11_reg_m11_reg(0);
when std_logic_vector(to_unsigned(W12_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & w12_reg_m12_reg(7) & w12_reg_m12_reg(6) & w12_reg_m12_reg(5) & w12_reg_m12_reg(4) & w12_reg_m12_reg(3) & w12_reg_m12_reg(2) & w12_reg_m12_reg(1) & w12_reg_m12_reg(0);
when std_logic_vector(to_unsigned(W20_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & w20_reg_m20_reg(7) & w20_reg_m20_reg(6) & w20_reg_m20_reg(5) & w20_reg_m20_reg(4) & w20_reg_m20_reg(3) & w20_reg_m20_reg(2) & w20_reg_m20_reg(1) & w20_reg_m20_reg(0);
when std_logic_vector(to_unsigned(W21_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & w21_reg_m21_reg(7) & w21_reg_m21_reg(6) & w21_reg_m21_reg(5) & w21_reg_m21_reg(4) & w21_reg_m21_reg(3) & w21_reg_m21_reg(2) & w21_reg_m21_reg(1) & w21_reg_m21_reg(0);
when std_logic_vector(to_unsigned(W22_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & w22_reg_m22_reg(7) & w22_reg_m22_reg(6) & w22_reg_m22_reg(5) & w22_reg_m22_reg(4) & w22_reg_m22_reg(3) & w22_reg_m22_reg(2) & w22_reg_m22_reg(1) & w22_reg_m22_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
widthimg_reg_width <= widthimg_reg_width_reg;
w00_reg_m00 <= w00_reg_m00_reg;
w01_reg_m01 <= w01_reg_m01_reg;
w02_reg_m02 <= w02_reg_m02_reg;
w10_reg_m10 <= w10_reg_m10_reg;
w11_reg_m11 <= w11_reg_m11_reg;
w12_reg_m12 <= w12_reg_m12_reg;
w20_reg_m20 <= w20_reg_m20_reg;
w21_reg_m21 <= w21_reg_m21_reg;
w22_reg_m22 <= w22_reg_m22_reg;
end rtl;
| gpl-3.0 | 3a14a95cb10f66bca24cdedd4b488277 | 0.600354 | 2.39372 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_nios2_qsys_0_jtag_debug_module_sysclk.vhd | 1 | 6,972 | --Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tracking_camera_system_nios2_qsys_0_jtag_debug_module_sysclk is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal ir_in : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal sr : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal vs_udr : IN STD_LOGIC;
signal vs_uir : IN STD_LOGIC;
-- outputs:
signal jdo : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
signal take_action_break_a : OUT STD_LOGIC;
signal take_action_break_b : OUT STD_LOGIC;
signal take_action_break_c : OUT STD_LOGIC;
signal take_action_ocimem_a : OUT STD_LOGIC;
signal take_action_ocimem_b : OUT STD_LOGIC;
signal take_action_tracectrl : OUT STD_LOGIC;
signal take_action_tracemem_a : OUT STD_LOGIC;
signal take_action_tracemem_b : OUT STD_LOGIC;
signal take_no_action_break_a : OUT STD_LOGIC;
signal take_no_action_break_b : OUT STD_LOGIC;
signal take_no_action_break_c : OUT STD_LOGIC;
signal take_no_action_ocimem_a : OUT STD_LOGIC;
signal take_no_action_tracemem_a : OUT STD_LOGIC
);
end entity tracking_camera_system_nios2_qsys_0_jtag_debug_module_sysclk;
architecture europa of tracking_camera_system_nios2_qsys_0_jtag_debug_module_sysclk is
component altera_std_synchronizer is
GENERIC (
depth : NATURAL
);
PORT (
signal dout : OUT STD_LOGIC;
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal din : IN STD_LOGIC
);
end component altera_std_synchronizer;
signal enable_action_strobe : STD_LOGIC;
signal internal_jdo1 : STD_LOGIC_VECTOR (37 DOWNTO 0);
signal ir : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal jxuir : STD_LOGIC;
signal sync2_udr : STD_LOGIC;
signal sync2_uir : STD_LOGIC;
signal sync_udr : STD_LOGIC;
signal sync_uir : STD_LOGIC;
signal unxunused_resetxx2 : STD_LOGIC;
signal unxunused_resetxx3 : STD_LOGIC;
signal update_jdo_strobe : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of jdo : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
attribute ALTERA_ATTRIBUTE of sync2_udr : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103""";
attribute ALTERA_ATTRIBUTE of sync2_uir : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103""";
begin
unxunused_resetxx2 <= std_logic'('1');
the_altera_std_synchronizer2 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => clk,
din => vs_udr,
dout => sync_udr,
reset_n => unxunused_resetxx2
);
unxunused_resetxx3 <= std_logic'('1');
the_altera_std_synchronizer3 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => clk,
din => vs_uir,
dout => sync_uir,
reset_n => unxunused_resetxx3
);
process (clk)
begin
if clk'event and clk = '1' then
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr AND NOT sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir AND NOT sync2_uir;
end if;
end process;
take_action_ocimem_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("00"))))) AND NOT internal_jdo1(35)) AND internal_jdo1(34);
take_no_action_ocimem_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("00"))))) AND NOT internal_jdo1(35)) AND NOT internal_jdo1(34);
take_action_ocimem_b <= (enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("00"))))) AND internal_jdo1(35);
take_action_tracemem_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("01"))))) AND NOT internal_jdo1(37)) AND internal_jdo1(36);
take_no_action_tracemem_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("01"))))) AND NOT internal_jdo1(37)) AND NOT internal_jdo1(36);
take_action_tracemem_b <= (enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("01"))))) AND internal_jdo1(37);
take_action_break_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND NOT internal_jdo1(36)) AND internal_jdo1(37);
take_no_action_break_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND NOT internal_jdo1(36)) AND NOT internal_jdo1(37);
take_action_break_b <= (((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND internal_jdo1(36)) AND NOT internal_jdo1(35)) AND internal_jdo1(37);
take_no_action_break_b <= (((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND internal_jdo1(36)) AND NOT internal_jdo1(35)) AND NOT internal_jdo1(37);
take_action_break_c <= (((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND internal_jdo1(36)) AND internal_jdo1(35)) AND internal_jdo1(37);
take_no_action_break_c <= (((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND internal_jdo1(36)) AND internal_jdo1(35)) AND NOT internal_jdo1(37);
take_action_tracectrl <= (enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("11"))))) AND internal_jdo1(15);
process (clk)
begin
if clk'event and clk = '1' then
if std_logic'(jxuir) = '1' then
ir <= ir_in;
end if;
if std_logic'(update_jdo_strobe) = '1' then
internal_jdo1 <= sr;
end if;
end if;
end process;
--vhdl renameroo for output signals
jdo <= internal_jdo1;
end europa;
| gpl-2.0 | f6272a24daccf0f8c2c254374bea2e84 | 0.636259 | 3.635036 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/boards/terasic-de2-115/mn-single-hostif-gpio/quartus/toplevel.vhd | 3 | 11,305 | -------------------------------------------------------------------------------
--! @file toplevel.vhd
--
--! @brief Toplevel of Nios MN design Host part
--
--! @details This is the toplevel of the Nios MN FPGA Host design for the
--! INK DE2-115 Evaluation Board.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library libcommon;
use libcommon.global.all;
entity toplevel is
port (
-- 50 MHZ CLK IN
EXT_CLK : in std_logic;
-- EPCS
EPCS_DCLK : out std_logic;
EPCS_SCE : out std_logic;
EPCS_SDO : out std_logic;
EPCS_DATA0 : in std_logic;
-- 64 MBx2 SDRAM
SDRAM_CLK : out std_logic;
SDRAM_CAS_n : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CS_n : out std_logic;
SDRAM_RAS_n : out std_logic;
SDRAM_WE_n : out std_logic;
SDRAM_ADDR : out std_logic_vector(12 downto 0);
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_DQM : out std_logic_vector(3 downto 0);
SDRAM_DQ : inout std_logic_vector(31 downto 0);
-- LED
LEDG : out std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(15 downto 0);
-- KEY
KEY_n : in std_logic_vector(3 downto 0);
-- LCD
LCD_ON : out std_logic;
LCD_BLON : out std_logic;
LCD_DQ : inout std_logic_vector(7 downto 0);
LCD_E : out std_logic;
LCD_RS : out std_logic;
LCD_RW : out std_logic;
-- HOST Interface
HOSTIF_AD : inout std_logic_vector(16 downto 0);
HOSTIF_BE : out std_logic_vector(1 downto 0);
HOSTIF_CS_n : out std_logic;
HOSTIF_WR_n : out std_logic;
HOSTIF_ALE_n : out std_logic;
HOSTIF_RD_n : out std_logic;
HOSTIF_ACK_n : in std_logic;
HOSTIF_IRQ_n : in std_logic
);
end toplevel;
architecture rtl of toplevel is
component mnSingleHostifGpio is
port (
clk25_clk : in std_logic;
clk50_clk : in std_logic := 'X';
clk100_clk : in std_logic;
reset_reset_n : in std_logic := 'X';
host_0_benchmark_pio_export : out std_logic_vector(7 downto 0);
epcs_flash_dclk : out std_logic;
epcs_flash_sce : out std_logic;
epcs_flash_sdo : out std_logic;
epcs_flash_data0 : in std_logic := 'X';
sdram_0_addr : out std_logic_vector(12 downto 0);
sdram_0_ba : out std_logic_vector(1 downto 0);
sdram_0_cas_n : out std_logic;
sdram_0_cke : out std_logic;
sdram_0_cs_n : out std_logic;
sdram_0_dq : inout std_logic_vector(31 downto 0) := (others => 'X');
sdram_0_dqm : out std_logic_vector(3 downto 0);
sdram_0_ras_n : out std_logic;
sdram_0_we_n : out std_logic;
sync_irq_irq : in std_logic := 'X';
lcd_data : inout std_logic_vector(7 downto 0) := (others => 'X');
lcd_E : out std_logic;
lcd_RS : out std_logic;
lcd_RW : out std_logic;
prl0_oPrlMst_cs : out std_logic;
prl0_iPrlMst_ad_i : in std_logic_vector(16 downto 0) := (others => 'X');
prl0_oPrlMst_ad_o : out std_logic_vector(16 downto 0);
prl0_oPrlMst_ad_oen : out std_logic;
prl0_oPrlMst_be : out std_logic_vector(1 downto 0);
prl0_oPrlMst_ale : out std_logic;
prl0_oPrlMst_wr : out std_logic;
prl0_oPrlMst_rd : out std_logic;
prl0_iPrlMst_ack : in std_logic := 'X';
-- Application ports
app_pio_in_port : in std_logic_vector(31 downto 0) := (others => 'X');
app_pio_out_port : out std_logic_vector(31 downto 0)
);
end component mnSingleHostifGpio;
-- PLL component
component pll
port (
inclk0 : in std_logic;
c0 : out std_logic;
c1 : out std_logic;
c2 : out std_logic;
c3 : out std_logic;
locked : out std_logic
);
end component;
signal clk25 : std_logic;
signal clk50 : std_logic;
signal clk100 : std_logic;
signal clk100_p : std_logic;
signal pllLocked : std_logic;
signal hostifCs : std_logic;
signal hostifWr : std_logic;
signal hostifRd : std_logic;
signal hostifAle : std_logic;
signal hostifAck : std_logic;
signal hostifAd_i : std_logic_vector(HOSTIF_AD'range);
signal hostifAd_o : std_logic_vector(HOSTIF_AD'range);
signal hostifAd_oen : std_logic;
signal hostifIrq : std_logic;
signal app_input : std_logic_vector(31 downto 0);
begin
LCD_ON <= '1';
LCD_BLON <= '1';
SDRAM_CLK <= clk100_p;
HOSTIF_CS_n <= not hostifCs;
HOSTIF_WR_n <= not hostifWr;
HOSTIF_RD_n <= not hostifRd;
HOSTIF_ALE_n <= not hostifAle;
hostifAck <= not HOSTIF_ACK_n;
-- TRISTATE Buffer for AD bus
HOSTIF_AD <= hostifAd_o when hostifAd_oen = '1' else (others => 'Z');
hostifAd_i <= HOSTIF_AD;
hostifIrq <= not HOSTIF_IRQ_n;
---------------------------------------------------------------------------
-- Green LED assignments
LEDG <= (others => '0'); -- Reserved
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Red LED assignments
LEDR <= (others => '0'); -- Reserved
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Application Input and Output assignments
-- Input: Map KEY nibble to Application Input
app_input <= x"0000000" & not KEY_n;
---------------------------------------------------------------------------
inst : component mnSingleHostifGpio
port map (
clk25_clk => clk25,
clk50_clk => clk50,
clk100_clk => clk100,
reset_reset_n => pllLocked,
host_0_benchmark_pio_export => open,
epcs_flash_dclk => EPCS_DCLK,
epcs_flash_sce => EPCS_SCE,
epcs_flash_sdo => EPCS_SDO,
epcs_flash_data0 => EPCS_DATA0,
sdram_0_addr => SDRAM_ADDR,
sdram_0_ba => SDRAM_BA,
sdram_0_cas_n => SDRAM_CAS_n,
sdram_0_cke => SDRAM_CKE,
sdram_0_cs_n => SDRAM_CS_n,
sdram_0_dq => SDRAM_DQ,
sdram_0_dqm => SDRAM_DQM,
sdram_0_ras_n => SDRAM_RAS_n,
sdram_0_we_n => SDRAM_WE_n,
prl0_oPrlMst_cs => hostifCs,
prl0_iPrlMst_ad_i => hostifAd_i,
prl0_oPrlMst_ad_o => hostifAd_o,
prl0_oPrlMst_ad_oen => hostifAd_oen,
prl0_oPrlMst_be => HOSTIF_BE,
prl0_oPrlMst_ale => hostifAle,
prl0_oPrlMst_wr => hostifWr,
prl0_oPrlMst_rd => hostifRd,
prl0_iPrlMst_ack => hostifAck,
sync_irq_irq => hostifIrq,
lcd_data => LCD_DQ,
lcd_E => LCD_E,
lcd_RS => LCD_RS,
lcd_RW => LCD_RW,
app_pio_in_port => app_input,
app_pio_out_port => open
);
-- Pll Instance
pllInst : pll
port map (
inclk0 => EXT_CLK,
c0 => clk50,
c1 => clk100,
c2 => clk25,
c3 => clk100_p,
locked => pllLocked
);
end rtl;
| gpl-2.0 | f1a05229f32270e9d4b80b77cd975310 | 0.438125 | 4.378389 | false | false | false | false |
hoglet67/ElectronFpga | src/xilinx/spi_flash.vhd | 2 | 8,551 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- FLASH SPI driver
-- Internal Interface:
-- flash_clk driver clock
-- flash_clken driver clock enable (cannot be enabled every cycle)
-- flash_init active high to init FLASH address and read one byte
-- flash_addr FLASH address to read byte from
-- flash_data byte read from FLASH chip
-- flash_done active high to indicate read of first byte complete
-- after this, a new byte is available every 8 clock cycles
-- External Interface:
-- U_FLASH_CK FLASH chip clock pin
-- U_FLASH_CS FLASH chip select active low
-- U_FLASH_SI FLASH chip serial input pin
-- U_FLASH_SO FLASH chip serial output pin
-- A flash cycle consists of sending out the high speed read command 0x0B
-- followed by a 24 bit address, an 8 bit dummy byte then reading a byte
-- from the FLASH.
--
-- You could then maintain chip select active and continue to clock the
-- FLASH and keep reading bytes from it, as it auto increments the address,
-- or end the cycle by deactivating chip select and a whole new read cycle
-- must be started again
--
-- Data is clocked out from the FPGA and FLASH on the flash_clken1 clock edge
-- Data is latched into the FPGA and FLASH on the flash_clken clock edge.
entity spi_flash is
port (
-- internal interface
flash_clk : in std_logic := '0';
flash_clken : in std_logic := '0';
flash_init : in std_logic := '0';
flash_addr : in std_logic_vector (23 downto 0) := (others => '0');
flash_data : out std_logic_vector ( 7 downto 0) := (others => '0');
flash_done : out std_logic := '1';
-- external interface
U_FLASH_CK : out std_logic;
U_FLASH_CS : out std_logic;
U_FLASH_SI : out std_logic;
U_FLASH_SO : in std_logic
);
end spi_flash;
architecture RTL of spi_flash is
signal flash_clken1 : std_logic;
signal shift : std_logic_vector(7 downto 0) := (others => '0');
signal shift_in : std_logic_vector(7 downto 0) := (others => '0');
signal counter : std_logic_vector(2 downto 0) := (others => '0');
signal spi_ck_en : std_logic := '0';
signal spi_nce : std_logic := '1';
type SPI_STATE_TYPE is
(START, IDLE, TX_CMD, TX_AH, TX_AM, TX_AL, TX_DUMMY1, RX_DATA);
signal spi_state, next_spi_state : SPI_STATE_TYPE;
begin
U_FLASH_CK <= flash_clken1 and spi_ck_en; -- FLASH clock
U_FLASH_CS <= spi_nce; -- active low FLASH chip select/chip enable
U_FLASH_SI <= shift(7); -- MSB output to spi
-- advance state machine from state to state
run_sm : process (flash_clk, flash_init)
begin
if rising_edge(flash_clk) then
flash_clken1 <= flash_clken;
if (flash_clken = '1') then
if (flash_init = '0') then
spi_state <= IDLE; -- Initial state
else
spi_state <= next_spi_state; -- next state
end if;
end if;
end if;
end process;
-- state machine clocks data out to FLASH on alternate clock cycles
process(flash_clk)
begin
if rising_edge(flash_clk) then
if flash_clken1 = '1' then
case spi_state is
when IDLE => -- idle state
spi_ck_en <= '0'; -- Stop clock to FLASH
spi_nce <= '1'; -- Deselect FLASH
flash_done <= '1'; -- FLASH comms done
if flash_init = '1' then
next_spi_state <= START; -- select next state
end if;
when START => -- start state
shift <= x"0b"; -- High Speed Read command
flash_done <= '0'; -- FLASH comms not done
spi_ck_en <= '1'; -- enable FLASH clock
spi_nce <= '0'; -- Select FLASH
counter <= "000"; -- reset counter
next_spi_state <= TX_CMD; -- select next state
when TX_CMD => -- sends 8 bit command
counter <= counter + 1; -- count to next bit
shift <= shift(6 downto 0) & '1'; -- shift other bits left
if counter = "111" then
shift <= flash_addr(23 downto 16); -- load high address to shifter
next_spi_state <= TX_AH; -- select next state
end if;
when TX_AH => -- sends high address bits 23-16
counter <= counter + 1; -- count to next bit
shift <= shift(6 downto 0) & '1'; -- shift other bits left
if counter = "111" then
shift <= flash_addr(15 downto 8); -- load middle address to shifter
next_spi_state <= TX_AM; -- select next state
end if;
when TX_AM => -- sends middle address bits 15-8
counter <= counter + 1; -- count to next bit
shift <= shift(6 downto 0) & '1'; -- shift other bits left
if counter = "111" then
shift <= flash_addr(7 downto 0); -- load low address to shifter
next_spi_state <= TX_AL; -- select next state
end if;
when TX_AL => -- sends low address bits 7-0
counter <= counter + 1; -- count to next bit
shift <= shift(6 downto 0) & '1'; -- shift other bits left
if counter = "111" then
shift <= x"ff"; -- load dummy to shifter
next_spi_state <= TX_DUMMY1; -- select next state
end if;
when TX_DUMMY1 => -- sends dummy byte
counter <= counter + 1; -- count to next bit
shift <= shift(6 downto 0) & '1'; -- shift other bits left
if counter = "111" then
shift <= x"ff"; -- load dummy to shifter
flash_done <= '1'; -- FLASH init done
next_spi_state <= RX_DATA; -- select next state
end if;
when RX_DATA => -- reads byte from FLASH
counter <= counter + 1; -- count to next bit
shift_in <= shift_in(6 downto 0) & U_FLASH_SO; -- shift other bits left
if flash_init = '0' then
next_spi_state <= IDLE; -- on init signal move to INIT state
elsif counter = "000" then
flash_data <= shift_in; -- move byte to data bus
next_spi_state <= RX_DATA; -- stay in this state indefinitely
end if;
when others => -- default
next_spi_state <= IDLE;
end case;
end if;
end if;
end process;
end RTL;
| gpl-3.0 | 61fada8611d7808912e0abb5b182c623 | 0.430359 | 4.914368 | false | false | false | false |
DreamIP/GPStudio | support/io/vga_out/hdl/vga_out.vhd | 1 | 2,674 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity vga_out is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
--------------------- external ports --------------------
vga_blank_n : out std_logic;
vga_r : out std_logic_vector(7 downto 0);
vga_g : out std_logic_vector(7 downto 0);
vga_b : out std_logic_vector(7 downto 0);
vga_clk : out std_logic;
vga_hs : out std_logic;
vga_vs : out std_logic;
vga_sync_n : out std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end vga_out;
architecture rtl of vga_out is
--/*D5M controller */--
component vga_controller
port
(
OSC_50 : in std_logic;
RESET_N : in std_logic;
VGA_HS, VGA_VS : out std_logic;
VGA_SYNC, VGA_BLANK : out std_logic;
VGA_RED, VGA_GREEN, VGA_BLUE : out std_logic_vector(7 downto 0);
CLOCK108 : out std_logic;
x_offset : in integer range 0 to 1280; -- offset of the upper left pixel
y_offset : in integer range 0 to 1024;
data : in std_logic_vector(7 downto 0);
fv : in std_logic; -- frame valid
dv : in std_logic -- data valid
);
end component vga_controller;
signal status_reg_enable_bit : std_logic;
signal vga_clk108 : std_logic;
begin
vga_controller_inst : vga_controller
port map
(
-- External I/Os
OSC_50 => clk_proc,
RESET_N => reset_n,
VGA_HS => vga_hs,
VGA_VS => vga_vs,
VGA_SYNC => vga_sync_n,
VGA_BLANK => vga_blank_n,
VGA_RED => vga_r,
VGA_GREEN => vga_g,
VGA_BLUE => vga_b,
CLOCK108 => vga_clk108,
x_offset => to_integer(X"0190"),
y_offset => to_integer(X"0190"),
-- Input flow
data => in_data,
fv => in_fv,
dv => in_dv
);
vga_clk <= vga_clk108;
end rtl;
| gpl-3.0 | 276985a11392fd9fc8739089cbf9996d | 0.473074 | 3.38481 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/xilinx/openmac/src/axi_openmac-rtl-ea.vhd | 3 | 72,507 | -------------------------------------------------------------------------------
--! @file axi_openmac-rtl-ea.vhd
--
--! @brief OpenMAC toplevel for Xilinx
--
--! @details This is the openMAC toplevel for Xilinx platform with AXI.
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use openmac package
use work.openmacPkg.all;
--! Common Xilinx library
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
--! AXI Lite IPIF library
library axi_lite_ipif_v1_01_a;
--! Use AXI lite ipif
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
--! AXI Master Burst library
library axi_master_burst_v1_00_a;
--! Use AXI master burst
use axi_master_burst_v1_00_a.axi_master_burst;
--! Unisim library
library unisim;
--! Use ODDR2 instance primitive
use unisim.vcomponents.oddr2;
entity axi_openmac is
generic (
-----------------------------------------------------------------------
-- General parameters
-----------------------------------------------------------------------
--! Xilinx FPGA familiy
C_FAMILY : string := "spartan6";
-----------------------------------------------------------------------
-- AXI DMA
-----------------------------------------------------------------------
--! AXI master DMA address width
C_M_AXI_MAC_DMA_ADDR_WIDTH : integer := 32;
--! AXI master DMA data width
C_M_AXI_MAC_DMA_DATA_WIDTH : integer := 32;
--! AXI master DMA native data width
C_M_AXI_MAC_DMA_NATIVE_DWIDTH : integer := 32;
--! AXI master DMA burst length width
C_M_AXI_MAC_DMA_LENGTH_WIDTH : integer := 12;
--! AXI master DMA burst length
C_M_AXI_MAC_DMA_MAX_BURST_LEN : integer := 16;
-----------------------------------------------------------------------
-- AXI REG
-----------------------------------------------------------------------
--! AXI slave REG address ranges
C_S_AXI_MAC_REG_NUM_ADDR_RANGES : integer := 2;
--! AXI slave REG range 0 base
C_S_AXI_MAC_REG_RNG0_BASEADDR : std_logic_vector := x"ffffffff";
--! AXI slave REG range 0 high
C_S_AXI_MAC_REG_RNG0_HIGHADDR : std_logic_vector := x"00000000";
--! AXI slave REG range 1 base
C_S_AXI_MAC_REG_RNG1_BASEADDR : std_logic_vector := x"ffffffff";
--! AXI slave REG range 1 high
C_S_AXI_MAC_REG_RNG1_HIGHADDR : std_logic_vector := x"00000000";
--! AXI slave REG minimum size
C_S_AXI_MAC_REG_MIN_SIZE : std_logic_vector := x"00001fff";
--! AXI slave REG data width
C_S_AXI_MAC_REG_DATA_WIDTH : integer := 32;
--! AXI slave REG address width
C_S_AXI_MAC_REG_ADDR_WIDTH : integer := 32;
--! AXI slave REG clock frequency
C_S_AXI_MAC_REG_ACLK_FREQ_HZ : integer := 50000000;
--! AXI slave REG use write strobes
C_S_AXI_MAC_REG_USE_WSTRB : integer := 1;
--! AXI slave REG enable data phase timeout timer
C_S_AXI_MAC_REG_DPHASE_TIMEOUT : integer := 0;
-----------------------------------------------------------------------
-- AXI REG
-----------------------------------------------------------------------
--! AXI slave PKT base
C_S_AXI_MAC_PKT_BASEADDR : std_logic_vector := x"ffffffff";
--! AXI slave PKT high
C_S_AXI_MAC_PKT_HIGHADDR : std_logic_vector := x"00000000";
--! AXI slave REG minimum size
C_S_AXI_MAC_PKT_MIN_SIZE : std_logic_vector := x"0000ffff";
--! AXI slave PKT data width
C_S_AXI_MAC_PKT_DATA_WIDTH : integer := 32;
--! AXI slave PKT address width
C_S_AXI_MAC_PKT_ADDR_WIDTH : integer := 32;
--! AXI slave PKT use write strobes
C_S_AXI_MAC_PKT_USE_WSTRB : integer := 1;
--! AXI slave PKT enable data phase timeout timer
C_S_AXI_MAC_PKT_DPHASE_TIMEOUT : integer := 0;
-----------------------------------------------------------------------
-- Phy configuration
-----------------------------------------------------------------------
--! Number of Phy ports
gPhyPortCount : natural := 2;
--! Phy port interface type (Rmii or Mii)
gPhyPortType : natural := cPhyPortRmii;
--! Number of SMI phy ports
gSmiPortCount : natural := 1;
-----------------------------------------------------------------------
-- General configuration
-----------------------------------------------------------------------
--! Endianness ("little" or "big")
gEndianness : string := "little";
--! Enable packet activity generator (e.g. connect to LED)
gEnableActivity : natural := cFalse;
--! Enable DMA observer circuit
gEnableDmaObserver : natural := cFalse;
-----------------------------------------------------------------------
-- DMA configuration
-----------------------------------------------------------------------
--! DMA address width (byte-addressing)
gDmaAddrWidth : natural := 32;
--! DMA data width
gDmaDataWidth : natural := 16;
--! DMA burst count width
gDmaBurstCountWidth : natural := 4;
--! DMA write burst length (Rx packets) [words]
gDmaWriteBurstLength : natural := 16;
--! DMA read burst length (Tx packets) [words]
gDmaReadBurstLength : natural := 16;
--! DMA write FIFO length (Rx packets) [words]
gDmaWriteFifoLength : natural := 16;
--! DMA read FIFO length (Tx packets) [words]
gDmaReadFifoLength : natural := 16;
-----------------------------------------------------------------------
-- Packet buffer configuration
-----------------------------------------------------------------------
--! Packet buffer location for Tx packets
gPacketBufferLocTx : natural := cPktBufLocal;
--! Packet buffer location for Rx packets
gPacketBufferLocRx : natural := cPktBufLocal;
--! Packet buffer log2(size) [log2(bytes)]
gPacketBufferLog2Size : natural := 10;
-----------------------------------------------------------------------
-- MAC timer configuration
-----------------------------------------------------------------------
--! Enable pulse timer
gTimerEnablePulse : natural := cFalse;
--! Enable timer pulse width control
gTimerEnablePulseWidth : natural := cFalse;
--! Timer pulse width register width
gTimerPulseRegWidth : natural := 10
);
port (
-----------------------------------------------------------------------
-- Clock and reset signal pairs
-----------------------------------------------------------------------
--! Main clock used for openMAC, openHUB and openFILTER (freq = 50 MHz)
iClk50 : in std_logic;
--! Twice main clock used for Rmii Tx path
iClk100 : in std_logic;
-----------------------------------------------------------------------
-- MAC REG memory mapped slave
-----------------------------------------------------------------------
--! AXI slave REG clock
S_AXI_MAC_REG_ACLK : in std_logic;
--! AXI slave REG reset (low-active)
S_AXI_MAC_REG_ARESETN : in std_logic;
--! AXI slave REG address read valid
S_AXI_MAC_REG_ARVALID : in std_logic;
--! AXI slave REG address write valid
S_AXI_MAC_REG_AWVALID : in std_logic;
--! AXI slave REG response ready
S_AXI_MAC_REG_BREADY : in std_logic;
--! AXI slave REG read ready
S_AXI_MAC_REG_RREADY : in std_logic;
--! AXI slave REG write valid
S_AXI_MAC_REG_WVALID : in std_logic;
--! AXI slave REG read address
S_AXI_MAC_REG_ARADDR : in std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
--! AXI slave REG write address
S_AXI_MAC_REG_AWADDR : in std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
--! AXI slave REG write data
S_AXI_MAC_REG_WDATA : in std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
--! AXI slave REG write strobe
S_AXI_MAC_REG_WSTRB : in std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH/8-1 downto 0);
--! AXI slave REG read address ready
S_AXI_MAC_REG_ARREADY : out std_logic;
--! AXI slave REG write address ready
S_AXI_MAC_REG_AWREADY : out std_logic;
--! AXI slave REG write response valid
S_AXI_MAC_REG_BVALID : out std_logic;
--! AXI slave REG read valid
S_AXI_MAC_REG_RVALID : out std_logic;
--! AXI slave REG write ready
S_AXI_MAC_REG_WREADY : out std_logic;
--! AXI slave REG write response
S_AXI_MAC_REG_BRESP : out std_logic_vector(1 downto 0);
--! AXI slave REG read data
S_AXI_MAC_REG_RDATA : out std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
--! AXI slave REG read response
S_AXI_MAC_REG_RRESP : out std_logic_vector(1 downto 0);
-----------------------------------------------------------------------
-- MAC PACKET BUFFER memory mapped slave
-----------------------------------------------------------------------
--! AXI slave PKT clock
S_AXI_MAC_PKT_ACLK : in std_logic;
--! AXI slave PKT reset (low-active)
S_AXI_MAC_PKT_ARESETN : in std_logic;
--! AXI slave PKT address read valid
S_AXI_MAC_PKT_ARVALID : in std_logic;
--! AXI slave PKT address write valid
S_AXI_MAC_PKT_AWVALID : in std_logic;
--! AXI slave PKT response ready
S_AXI_MAC_PKT_BREADY : in std_logic;
--! AXI slave PKT read ready
S_AXI_MAC_PKT_RREADY : in std_logic;
--! AXI slave PKT write valid
S_AXI_MAC_PKT_WVALID : in std_logic;
--! AXI slave PKT read address
S_AXI_MAC_PKT_ARADDR : in std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
--! AXI slave PKT write address
S_AXI_MAC_PKT_AWADDR : in std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
--! AXI slave PKT write data
S_AXI_MAC_PKT_WDATA : in std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
--! AXI slave PKT write strobe
S_AXI_MAC_PKT_WSTRB : in std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH/8-1 downto 0);
--! AXI slave PKT read address ready
S_AXI_MAC_PKT_ARREADY : out std_logic;
--! AXI slave PKT write address ready
S_AXI_MAC_PKT_AWREADY : out std_logic;
--! AXI slave PKT write response valid
S_AXI_MAC_PKT_BVALID : out std_logic;
--! AXI slave PKT read valid
S_AXI_MAC_PKT_RVALID : out std_logic;
--! AXI slave PKT write ready
S_AXI_MAC_PKT_WREADY : out std_logic;
--! AXI slave PKT write response
S_AXI_MAC_PKT_BRESP : out std_logic_vector(1 downto 0);
--! AXI slave PKT read data
S_AXI_MAC_PKT_RDATA : out std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
--! AXI slave PKT read response
S_AXI_MAC_PKT_RRESP : out std_logic_vector(1 downto 0);
-----------------------------------------------------------------------
-- MAC DMA memory mapped master
-----------------------------------------------------------------------
--! DMA master clock
M_AXI_MAC_DMA_ACLK : in std_logic;
--! DMA master reset (low-active)
M_AXI_MAC_DMA_ARESETN : in std_logic;
--! AXI master DMA error
M_AXI_MAC_DMA_MD_ERROR : out std_logic;
--! AXI master DMA read address ready
M_AXI_MAC_DMA_ARREADY : in std_logic;
--! AXI master DMA write address ready
M_AXI_MAC_DMA_AWREADY : in std_logic;
--! AXI master DMA write response ready
M_AXI_MAC_DMA_BVALID : in std_logic;
--! AXI master DMA read last
M_AXI_MAC_DMA_RLAST : in std_logic;
--! AXI master DMA read valid
M_AXI_MAC_DMA_RVALID : in std_logic;
--! AXI master DMA write ready
M_AXI_MAC_DMA_WREADY : in std_logic;
--! AXI master DMA write response
M_AXI_MAC_DMA_BRESP : in std_logic_vector(1 downto 0);
--! AXI master DMA read data
M_AXI_MAC_DMA_RDATA : in std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
--! AXI master DMA read response
M_AXI_MAC_DMA_RRESP : in std_logic_vector(1 downto 0);
--! AXI master DMA read address valid
M_AXI_MAC_DMA_ARVALID : out std_logic;
--! AXI master DMA write address valid
M_AXI_MAC_DMA_AWVALID : out std_logic;
--! AXI master DMA response ready
M_AXI_MAC_DMA_BREADY : out std_logic;
--! AXI master DMA read ready
M_AXI_MAC_DMA_RREADY : out std_logic;
--! AXI master DMA write last
M_AXI_MAC_DMA_WLAST : out std_logic;
--! AXI master DMA write valid
M_AXI_MAC_DMA_WVALID : out std_logic;
--! AXI master DMA read address
M_AXI_MAC_DMA_ARADDR : out std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
--! AXI master DMA burst type
M_AXI_MAC_DMA_ARBURST : out std_logic_vector(1 downto 0);
--! AXI master DMA memory type
M_AXI_MAC_DMA_ARCACHE : out std_logic_vector(3 downto 0);
--! AXI master DMA burst length
M_AXI_MAC_DMA_ARLEN : out std_logic_vector(7 downto 0);
--! AXI master DMA protection type
M_AXI_MAC_DMA_ARPROT : out std_logic_vector(2 downto 0);
--! AXI master DMA burst size
M_AXI_MAC_DMA_ARSIZE : out std_logic_vector(2 downto 0);
--! AXI master DMA write address
M_AXI_MAC_DMA_AWADDR : out std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
--! AXI master DMA burst type
M_AXI_MAC_DMA_AWBURST : out std_logic_vector(1 downto 0);
--! AXI master DMA memory type
M_AXI_MAC_DMA_AWCACHE : out std_logic_vector(3 downto 0);
--! AXI master DMA burst length
M_AXI_MAC_DMA_AWLEN : out std_logic_vector(7 downto 0);
--! AXI master DMA protection type
M_AXI_MAC_DMA_AWPROT : out std_logic_vector(2 downto 0);
--! AXI master DMA burst size
M_AXI_MAC_DMA_AWSIZE : out std_logic_vector(2 downto 0);
--! AXI master DMA write data
M_AXI_MAC_DMA_WDATA : out std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
--! AXI master DMA write strobe
M_AXI_MAC_DMA_WSTRB : out std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH/8-1 downto 0);
-----------------------------------------------------------------------
-- Interrupts
-----------------------------------------------------------------------
--! MAC TIMER interrupt
TIMER_IRQ : out std_logic;
--! MAC interrupt
MAC_IRQ : out std_logic;
--! MAC TIMER pulse interrupt
TIMER_PULSE_IRQ : out std_logic;
-----------------------------------------------------------------------
-- Rmii Phy ports
-----------------------------------------------------------------------
--! Rmii Clock ports (optional)
oRmii_clk : out std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Rx Crs data valid ports
iRmii_rxCrsDataValid : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Rx data ports
iRmii_rxData : in std_logic_vector(gPhyPortCount*2-1 downto 0);
--! Rmii Rx error ports
iRmii_rxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Tx enable ports
oRmii_txEnable : out std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Tx data ports
oRmii_txData : out std_logic_vector(gPhyPortCount*2-1 downto 0);
-----------------------------------------------------------------------
-- Mii Phy ports
-----------------------------------------------------------------------
--! Mii Rx data valid ports
iMii_rxDataValid : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Rx data ports
iMii_rxData : in std_logic_vector(gPhyPortCount*4-1 downto 0);
--! Mii Rx error ports
iMii_rxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Rx Clocks
iMii_rxClk : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Tx enable ports
oMii_txEnable : out std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Tx data ports
oMii_txData : out std_logic_vector(gPhyPortCount*4-1 downto 0);
--! Mii Tx Clocks
iMii_txClk : in std_logic_vector(gPhyPortCount-1 downto 0);
-----------------------------------------------------------------------
-- Phy management interface
-----------------------------------------------------------------------
--! Phy reset (low-active)
oSmi_nPhyRst : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI clock
oSmi_clk : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data I/O input
iSmi_dio : in std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data I/O output
oSmi_dio : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data I/O tristate
oSmi_dio_tri : out std_logic;
-----------------------------------------------------------------------
-- Other ports
-----------------------------------------------------------------------
--! Packet activity (enabled with gEnableActivity)
oPktActivity : out std_logic
);
end axi_openmac;
architecture rtl of axi_openmac is
--! Address zero padding vector
constant cZeroPadAddress : std_logic_vector(31 downto 0) := (others => cInactivated);
--! Address array for MAC REG IPIF
constant cMacReg_addressArray : SLV64_ARRAY_TYPE := (
(cZeroPadAddress & C_S_AXI_MAC_REG_RNG0_BASEADDR),
(cZeroPadAddress & C_S_AXI_MAC_REG_RNG0_HIGHADDR),
(cZeroPadAddress & C_S_AXI_MAC_REG_RNG1_BASEADDR),
(cZeroPadAddress & C_S_AXI_MAC_REG_RNG1_HIGHADDR)
);
--! Address array for PKT BUF IPIF
constant cPktBuf_addressArray : SLV64_ARRAY_TYPE := (
(cZeroPadAddress & C_S_AXI_MAC_PKT_BASEADDR),
(cZeroPadAddress & C_S_AXI_MAC_PKT_HIGHADDR)
);
--! Chipselect for MAC REG --> MAC REG
constant cMacReg_csMacReg : natural := 1;
--! Chipselect for MAC REG --> MAC TIMER
constant cMacReg_csMacTimer : natural := 0;
--! Chipselect for PKT BUF
constant cPktBuf_cs : natural := 0;
--! Clock Reset type
type tClkRst is record
clk : std_logic;
rst : std_logic;
regClk : std_logic;
regRst : std_logic;
dmaClk : std_logic;
dmaRst : std_logic;
pktClk : std_logic;
pktRst : std_logic;
clk2x : std_logic;
end record;
--! Mac Reg type
type tMacReg is record
chipselect : std_logic;
write : std_logic;
read : std_logic;
waitrequest : std_logic;
byteenable : std_logic_vector(cMacRegDataWidth/cByteLength-1 downto 0);
address : std_logic_vector(cMacRegAddrWidth-1 downto 0);
writedata : std_logic_vector(cMacRegDataWidth-1 downto 0);
readdata : std_logic_vector(cMacRegDataWidth-1 downto 0);
end record;
--! Mac Timer type
type tMacTimer is record
chipselect : std_logic;
write : std_logic;
read : std_logic;
waitrequest : std_logic;
address : std_logic_vector(cMacTimerAddrWidth-1 downto 0);
byteenable : std_logic_vector(cPktBufDataWidth/cByteLength-1 downto 0);
writedata : std_logic_vector(cMacTimerDataWidth-1 downto 0);
readdata : std_logic_vector(cMacTimerDataWidth-1 downto 0);
end record;
--! Pkt Buf type
type tPktBuf is record
chipselect : std_logic;
write : std_logic;
read : std_logic;
waitrequest : std_logic;
byteenable : std_logic_vector(cPktBufDataWidth/cByteLength-1 downto 0);
address : std_logic_vector(gPacketBufferLog2Size-1 downto 0);
writedata : std_logic_vector(cPktBufDataWidth-1 downto 0);
readdata : std_logic_vector(cPktBufDataWidth-1 downto 0);
end record;
--! Dma type
type tDma is record
write : std_logic;
read : std_logic;
waitrequest : std_logic;
readdatavalid : std_logic;
byteenable : std_logic_vector(gDmaDataWidth/cByteLength-1 downto 0);
address : std_logic_vector(gDmaAddrWidth-1 downto 0);
burstcount : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
burstcounter : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
writedata : std_logic_vector(gDmaDataWidth-1 downto 0);
readdata : std_logic_vector(gDmaDataWidth-1 downto 0);
end record;
--! AXI lite slave for MAC REG
type tAxiSlaveMacReg is record
axi_aclk : std_logic;
axi_aresetn : std_logic;
axi_awaddr : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
axi_awvalid : std_logic;
axi_awready : std_logic;
axi_wdata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
axi_wstrb : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH/8-1 downto 0);
axi_wvalid : std_logic;
axi_wready : std_logic;
axi_bresp : std_logic_vector(1 downto 0);
axi_bvalid : std_logic;
axi_bready : std_logic;
axi_araddr : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
axi_arvalid : std_logic;
axi_arready : std_logic;
axi_rdata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
axi_rresp : std_logic_vector(1 downto 0);
axi_rvalid : std_logic;
axi_rready : std_logic;
ipif_clk : std_logic;
ipif_resetn : std_logic;
ipif_addr : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
ipif_rnw : std_logic;
ipif_be : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH/8-1 downto 0);
ipif_cs : std_logic_vector(((cMacReg_addressArray'length)/2-1) downto 0);
ipif_wrdata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
ipif_rddata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
ipif_wrack : std_logic;
ipif_rdack : std_logic;
ipif_error : std_logic;
end record;
--! AXI lite slave for PKT BUF
type tAxiSlavePktBuf is record
axi_aclk : std_logic;
axi_aresetn : std_logic;
axi_awaddr : std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
axi_awvalid : std_logic;
axi_awready : std_logic;
axi_wdata : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
axi_wstrb : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH/8-1 downto 0);
axi_wvalid : std_logic;
axi_wready : std_logic;
axi_bresp : std_logic_vector(1 downto 0);
axi_bvalid : std_logic;
axi_bready : std_logic;
axi_araddr : std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
axi_arvalid : std_logic;
axi_arready : std_logic;
axi_rdata : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
axi_rresp : std_logic_vector(1 downto 0);
axi_rvalid : std_logic;
axi_rready : std_logic;
ipif_clk : std_logic;
ipif_resetn : std_logic;
ipif_addr : std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
ipif_rnw : std_logic;
ipif_be : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH/8-1 downto 0);
ipif_cs : std_logic_vector(((cPktBuf_addressArray'length)/2-1) downto 0);
ipif_wrdata : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
ipif_rddata : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
ipif_wrack : std_logic;
ipif_rdack : std_logic;
ipif_error : std_logic;
end record;
--! AXI master for DMA
type tAxiMasterDma is record
axi_aclk : std_logic;
axi_aresetn : std_logic;
md_error : std_logic;
axi_arready : std_logic;
axi_arvalid : std_logic;
axi_araddr : std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
axi_arlen : std_logic_vector(7 downto 0);
axi_arsize : std_logic_vector(2 downto 0);
axi_arburst : std_logic_vector(1 downto 0);
axi_arprot : std_logic_vector(2 downto 0);
axi_arcache : std_logic_vector(3 downto 0);
axi_rready : std_logic;
axi_rvalid : std_logic;
axi_rdata : std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
axi_rresp : std_logic_vector(1 downto 0);
axi_rlast : std_logic;
axi_awready : std_logic;
axi_awvalid : std_logic;
axi_awaddr : std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
axi_awlen : std_logic_vector(7 downto 0);
axi_awsize : std_logic_vector(2 downto 0);
axi_awburst : std_logic_vector(1 downto 0);
axi_awprot : std_logic_vector(2 downto 0);
axi_awcache : std_logic_vector(3 downto 0);
axi_wready : std_logic;
axi_wvalid : std_logic;
axi_wdata : std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
axi_wstrb : std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH/8-1 downto 0);
axi_wlast : std_logic;
axi_bready : std_logic;
axi_bvalid : std_logic;
axi_bresp : std_logic_vector(1 downto 0);
ipif_mstrd_req : std_logic;
ipif_mstwr_req : std_logic;
ipif_mst_addr : std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
ipif_mst_length : std_logic_vector(C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0);
ipif_mst_be : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8-1 downto 0);
ipif_mst_type : std_logic;
ipif_mst_lock : std_logic;
ipif_mst_reset : std_logic;
ipif_mst_cmdack : std_logic;
ipif_mst_cmplt : std_logic;
ipif_mst_error : std_logic;
ipif_mst_rearbitrate : std_logic;
ipif_mst_cmd_timeout : std_logic;
ipif_mstrd_d : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 );
ipif_mstrd_rem : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8-1 downto 0);
ipif_mstrd_sof_n : std_logic;
ipif_mstrd_eof_n : std_logic;
ipif_mstrd_src_rdy_n : std_logic;
ipif_mstrd_src_dsc_n : std_logic;
ipif_mstrd_dst_rdy_n : std_logic;
ipif_mstrd_dst_dsc_n : std_logic;
ipif_mstwr_d : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0);
ipif_mstwr_rem : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8-1 downto 0);
ipif_mstwr_sof_n : std_logic;
ipif_mstwr_eof_n : std_logic;
ipif_mstwr_src_rdy_n : std_logic;
ipif_mstwr_src_dsc_n : std_logic;
ipif_mstwr_dst_rdy_n : std_logic;
ipif_mstwr_dst_dsc_n : std_logic;
end record;
--! Clock xing for MAC REG port
type tClkXingMacRegPort is record
clk : std_logic;
cs : std_logic_vector(((cMacReg_addressArray'length)/2-1) downto 0);
rnw : std_logic;
readdata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
wrAck : std_logic;
rdAck : std_logic;
end record;
--! Clock xing for MAC REG
type tClkXingMacReg is record
rst : std_logic;
fast : tClkXingMacRegPort;
slow : tClkXingMacRegPort;
end record;
--! Data width converter for MAC REG
type tConvMacReg is record
rst : std_logic;
clk : std_logic;
master_select : std_logic;
master_write : std_logic;
master_read : std_logic;
master_byteenable : std_logic_vector(3 downto 0);
master_writedata : std_logic_vector(31 downto 0);
master_readdata : std_logic_vector(31 downto 0);
master_address : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
master_WriteAck : std_logic;
master_ReadAck : std_logic;
slave_select : std_logic;
slave_write : std_logic;
slave_read : std_logic;
slave_address : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
slave_byteenable : std_logic_vector(1 downto 0);
slave_readdata : std_logic_vector(15 downto 0);
slave_writedata : std_logic_vector(15 downto 0);
slave_ack : std_logic;
end record;
--! IPIF handler for MAC DMA
type tIpifMasterHandler is record
rst : std_logic;
clk : std_logic;
ipif_cmdAck : std_logic;
ipif_cmplt : std_logic;
ipif_error : std_logic;
ipif_rearbitrate : std_logic;
ipif_cmdTimeout : std_logic;
ipif_type : std_logic;
ipif_addr : std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
ipif_length : std_logic_vector(C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0);
ipif_be : std_logic_vector(3 downto 0);
ipif_lock : std_logic;
ipif_reset : std_logic;
ipif_rdData : std_logic_vector(31 downto 0);
ipif_rdRem : std_logic_vector(3 downto 0);
ipif_rdReq : std_logic;
nIpif_rdSof : std_logic;
nIpif_rdEof : std_logic;
nIpif_rdSrcRdy : std_logic;
nIpif_rdSrcDsc : std_logic;
nIpif_rdDstRdy : std_logic;
nIpif_rdDstDsc : std_logic;
ipif_wrData : std_logic_vector(31 downto 0);
ipif_wrRem : std_logic_vector(3 downto 0);
ipif_wrReq : std_logic;
nIpif_wrSof : std_logic;
nIpif_wrEof : std_logic;
nIpif_wrSrcRdy : std_logic;
nIpif_wrSrcDsc : std_logic;
nIpif_wrDstRdy : std_logic;
nIpif_wrDstDsc : std_logic;
masterRead : std_logic;
masterWrite : std_logic;
masterAddress : std_logic_vector(gDmaAddrWidth-1 downto 0);
masterWritedata : std_logic_vector(31 downto 0);
masterBurstcount : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
masterBurstcounter : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
masterReaddata : std_logic_vector(31 downto 0);
masterWaitrequest : std_logic;
masterReaddatavalid : std_logic;
end record;
--! Clock and resets
signal intf_clkRst : tClkRst;
--! Mac Reg
signal intf_macReg : tMacReg;
--! Mac Timer
signal intf_macTimer : tMacTimer;
--! Packet buffer
signal intf_pktBuf : tPktBuf;
--! Dma
signal intf_dma : tDma;
--! Mac Reg IPIF
signal ipif_macReg : tAxiSlaveMacReg;
--! Packet buffer IPIF
signal ipif_pktBuf : tAxiSlavePktBuf;
--! Dma IPIF
signal ipif_dma : tAxiMasterDma;
--! Clock Xing for MAC REG IPIF
signal xing_macReg : tClkXingMacReg;
--! Dara width converter for MAC REG IPIF
signal conv_macReg : tConvMacReg;
--! Dma IPIF master handler
signal ipif_dmaMasterHdler : tIpifMasterHandler;
--! Mac Tx interrupt
signal macTx_interrupt : std_logic;
--! Mac Rx interrupt
signal macRx_interrupt : std_logic;
--! Rmii Tx path
signal rmiiTx : tRmiiPathArray(gPhyPortCount-1 downto 0);
--! Rmii Rx path
signal rmiiRx : tRmiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Tx path
signal miiTx : tMiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Rx path
signal miiRx : tMiiPathArray(gPhyPortCount-1 downto 0);
--! Smi tri-state-buffer input
signal smi_data_in : std_logic_vector(gSmiPortCount-1 downto 0);
--! Smi tri-state-buffer output
signal smi_data_out : std_logic_vector(gSmiPortCount-1 downto 0);
--! Smi tri-state-buffer output enable
signal smi_data_outEnable : std_logic;
begin
---------------------------------------------------------------------------
-- Map outputs
---------------------------------------------------------------------------
-- Mac interrupts are or'd to single line.
MAC_IRQ <= macTx_interrupt or macRx_interrupt;
-- Phy Tx path
rmiiPathArrayToStdLogicVector(
iVector => rmiiTx,
oEnable => oRmii_txEnable,
oData => oRmii_txData
);
miiPathArrayToStdLogicVector(
iVector => miiTx,
oEnable => oMii_txEnable,
oData => oMii_txData
);
---------------------------------------------------------------------------
-- Map inputs
---------------------------------------------------------------------------
-- Clock and resets
intf_clkRst.clk <= iClk50;
intf_clkRst.clk2x <= iClk100;
intf_clkRst.regClk <= S_AXI_MAC_REG_ACLK;
intf_clkRst.pktClk <= S_AXI_MAC_PKT_ACLK;
intf_clkRst.dmaClk <= M_AXI_MAC_DMA_ACLK;
intf_clkRst.rst <= not S_AXI_MAC_REG_ARESETN;
intf_clkRst.regRst <= not S_AXI_MAC_REG_ARESETN;
intf_clkRst.pktRst <= not S_AXI_MAC_PKT_ARESETN;
intf_clkRst.dmaRst <= not M_AXI_MAC_DMA_ARESETN;
-- Phy Rx path
stdLogicVectorToRmiiPathArray(
iEnable => iRmii_rxCrsDataValid,
iData => iRmii_rxData,
oVector => rmiiRx
);
stdLogicVectorToMiiPathArray(
iEnable => iMii_rxDataValid,
iData => iMii_rxData,
oVector => miiRx
);
---------------------------------------------------------------------------
-- Map IOs
---------------------------------------------------------------------------
-- Assign SMI IO (the tristate buffer shall be assigned by toplevel)
oSmi_dio <= smi_data_out;
oSmi_dio_tri <= not smi_data_outEnable;
smi_data_in <= iSmi_dio;
---------------------------------------------------------------------------
-- Map Instances
---------------------------------------------------------------------------
-- MAC REG --> ipif_macReg
ipif_macReg.axi_aclk <= intf_clkRst.regClk;
ipif_macReg.axi_aresetn <= not intf_clkRst.regRst;
ipif_macReg.axi_awaddr <= S_AXI_MAC_REG_AWADDR;
ipif_macReg.axi_awvalid <= S_AXI_MAC_REG_AWVALID;
S_AXI_MAC_REG_AWREADY <= ipif_macReg.axi_awready;
ipif_macReg.axi_wdata <= S_AXI_MAC_REG_WDATA;
ipif_macReg.axi_wstrb <= S_AXI_MAC_REG_WSTRB;
ipif_macReg.axi_wvalid <= S_AXI_MAC_REG_WVALID;
S_AXI_MAC_REG_WREADY <= ipif_macReg.axi_wready;
S_AXI_MAC_REG_BRESP <= ipif_macReg.axi_bresp;
S_AXI_MAC_REG_BVALID <= ipif_macReg.axi_bvalid;
ipif_macReg.axi_bready <= S_AXI_MAC_REG_BREADY;
ipif_macReg.axi_araddr <= S_AXI_MAC_REG_ARADDR;
ipif_macReg.axi_arvalid <= S_AXI_MAC_REG_ARVALID;
S_AXI_MAC_REG_ARREADY <= ipif_macReg.axi_arready;
S_AXI_MAC_REG_RDATA <= ipif_macReg.axi_rdata;
S_AXI_MAC_REG_RRESP <= ipif_macReg.axi_rresp;
S_AXI_MAC_REG_RVALID <= ipif_macReg.axi_rvalid;
ipif_macReg.axi_rready <= S_AXI_MAC_REG_RREADY;
-- xing_macReg <-- conv_macReg or intf_macTimer
--! This process assigns the read and ack path from macReg and macTimer
--! to the clock crossing slow inputs, depending on the selected target.
ASSIGN_XING_MACREG : process (conv_macReg, intf_macTimer)
begin
-- default is MAC REG source
xing_macReg.slow.readdata <= conv_macReg.master_readdata;
xing_macReg.slow.wrAck <= conv_macReg.master_WriteAck;
xing_macReg.slow.rdAck <= conv_macReg.master_ReadAck;
if intf_macTimer.chipselect = cActivated then
xing_macReg.slow.readdata <= intf_macTimer.readdata;
xing_macReg.slow.wrAck <= intf_macTimer.write and not intf_macTimer.waitrequest;
xing_macReg.slow.rdAck <= intf_macTimer.read and not intf_macTimer.waitrequest;
end if;
end process ASSIGN_XING_MACREG;
-- ipif_macReg --> xing_macReg
--unused output: ipif_macReg.ipif_resetn;
xing_macReg.rst <= intf_clkRst.regRst;
xing_macReg.fast.clk <= ipif_macReg.ipif_clk;
xing_macReg.slow.clk <= intf_clkRst.clk;
xing_macReg.fast.rnw <= ipif_macReg.ipif_rnw;
xing_macReg.fast.cs <= ipif_macReg.ipif_cs;
ipif_macReg.ipif_rddata <= xing_macReg.fast.readdata;
ipif_macReg.ipif_wrack <= xing_macReg.fast.wrAck;
ipif_macReg.ipif_rdack <= xing_macReg.fast.rdAck;
ipif_macReg.ipif_error <= cInactivated; --unused
-- ipif_macReg --> conv_macReg | xing_macReg --> conv_macReg
conv_macReg.rst <= intf_clkRst.rst;
conv_macReg.clk <= intf_clkRst.clk;
conv_macReg.master_select <= xing_macReg.slow.cs(cMacReg_csMacReg);
conv_macReg.master_write <= not xing_macReg.slow.rnw;
conv_macReg.master_read <= xing_macReg.slow.rnw;
conv_macReg.master_byteenable <= ipif_macReg.ipif_be;
conv_macReg.master_writedata <= ipif_macReg.ipif_wrdata;
conv_macReg.master_address <= ipif_macReg.ipif_addr(conv_macReg.master_address'range);
-- conv_macReg --> intf_macReg
intf_macReg.chipselect <= conv_macReg.slave_select;
intf_macReg.write <= conv_macReg.slave_write;
intf_macReg.read <= conv_macReg.slave_read;
intf_macReg.address <= conv_macReg.slave_address(intf_macReg.address'range);
intf_macReg.byteenable <= conv_macReg.slave_byteenable;
conv_macReg.slave_readdata <= intf_macReg.readdata;
intf_macReg.writedata <= conv_macReg.slave_writedata;
conv_macReg.slave_ack <= not intf_macReg.waitrequest;
-- ipif_macReg --> intf_macTimer | xing_macReg --> intf_macTimer
intf_macTimer.chipselect <= xing_macReg.slow.cs(cMacReg_csMacTimer);
intf_macTimer.write <= not xing_macReg.slow.rnw;
intf_macTimer.read <= xing_macReg.slow.rnw;
intf_macTimer.address <= ipif_macReg.ipif_addr(intf_macTimer.address'range);
intf_macTimer.byteenable <= ipif_macReg.ipif_be;
intf_macTimer.writedata <= ipif_macReg.ipif_wrdata;
-- MAC PKT --> ipif_pktBuf
ipif_pktBuf.axi_aclk <= intf_clkRst.pktClk;
ipif_pktBuf.axi_aresetn <= not intf_clkRst.pktRst;
ipif_pktBuf.axi_awaddr <= S_AXI_MAC_PKT_AWADDR;
ipif_pktBuf.axi_awvalid <= S_AXI_MAC_PKT_AWVALID;
S_AXI_MAC_PKT_AWREADY <= ipif_pktBuf.axi_awready;
ipif_pktBuf.axi_wdata <= S_AXI_MAC_PKT_WDATA;
ipif_pktBuf.axi_wstrb <= S_AXI_MAC_PKT_WSTRB;
ipif_pktBuf.axi_wvalid <= S_AXI_MAC_PKT_WVALID;
S_AXI_MAC_PKT_WREADY <= ipif_pktBuf.axi_wready;
S_AXI_MAC_PKT_BRESP <= ipif_pktBuf.axi_bresp;
S_AXI_MAC_PKT_BVALID <= ipif_pktBuf.axi_bvalid;
ipif_pktBuf.axi_bready <= S_AXI_MAC_PKT_BREADY;
ipif_pktBuf.axi_araddr <= S_AXI_MAC_PKT_ARADDR;
ipif_pktBuf.axi_arvalid <= S_AXI_MAC_PKT_ARVALID;
S_AXI_MAC_PKT_ARREADY <= ipif_pktBuf.axi_arready;
S_AXI_MAC_PKT_RDATA <= ipif_pktBuf.axi_rdata;
S_AXI_MAC_PKT_RRESP <= ipif_pktBuf.axi_rresp;
S_AXI_MAC_PKT_RVALID <= ipif_pktBuf.axi_rvalid;
ipif_pktBuf.axi_rready <= S_AXI_MAC_PKT_RREADY;
-- ipif_pktBuf --> intf_pktBuf
--unused output: ipif_pktBuf.ipif_clk
--unused output: ipif_pktBuf.ipif_resetn
intf_pktBuf.address <= ipif_pktBuf.ipif_addr(intf_pktBuf.address'range);
intf_pktBuf.write <= not ipif_pktBuf.ipif_rnw;
intf_pktBuf.read <= ipif_pktBuf.ipif_rnw;
intf_pktBuf.byteenable <= ipif_pktBuf.ipif_be;
intf_pktBuf.chipselect <= ipif_pktBuf.ipif_cs(cPktBuf_cs);
intf_pktBuf.writedata <= ipif_pktBuf.ipif_wrdata;
ipif_pktBuf.ipif_rddata <= intf_pktBuf.readdata;
ipif_pktBuf.ipif_wrack <= intf_pktBuf.chipselect and intf_pktBuf.write and not intf_pktBuf.waitrequest;
ipif_pktBuf.ipif_rdack <= intf_pktBuf.chipselect and intf_pktBuf.read and not intf_pktBuf.waitrequest;
ipif_pktBuf.ipif_error <= cInactivated; --unused
-- MAC DMA --> ipif_dma
ipif_dma.axi_aclk <= intf_clkRst.dmaClk;
ipif_dma.axi_aresetn <= not intf_clkRst.dmaRst;
M_AXI_MAC_DMA_MD_ERROR <= ipif_dma.md_error;
ipif_dma.axi_arready <= M_AXI_MAC_DMA_ARREADY;
M_AXI_MAC_DMA_ARVALID <= ipif_dma.axi_arvalid;
M_AXI_MAC_DMA_ARADDR <= ipif_dma.axi_araddr;
M_AXI_MAC_DMA_ARLEN <= ipif_dma.axi_arlen;
M_AXI_MAC_DMA_ARSIZE <= ipif_dma.axi_arsize;
M_AXI_MAC_DMA_ARBURST <= ipif_dma.axi_arburst;
M_AXI_MAC_DMA_ARPROT <= ipif_dma.axi_arprot;
M_AXI_MAC_DMA_ARCACHE <= ipif_dma.axi_arcache;
M_AXI_MAC_DMA_RREADY <= ipif_dma.axi_rready;
ipif_dma.axi_rvalid <= M_AXI_MAC_DMA_RVALID;
ipif_dma.axi_rdata <= M_AXI_MAC_DMA_RDATA;
ipif_dma.axi_rresp <= M_AXI_MAC_DMA_RRESP;
ipif_dma.axi_rlast <= M_AXI_MAC_DMA_RLAST;
ipif_dma.axi_awready <= M_AXI_MAC_DMA_AWREADY;
M_AXI_MAC_DMA_AWVALID <= ipif_dma.axi_awvalid;
M_AXI_MAC_DMA_AWADDR <= ipif_dma.axi_awaddr;
M_AXI_MAC_DMA_AWLEN <= ipif_dma.axi_awlen;
M_AXI_MAC_DMA_AWSIZE <= ipif_dma.axi_awsize;
M_AXI_MAC_DMA_AWBURST <= ipif_dma.axi_awburst;
M_AXI_MAC_DMA_AWPROT <= ipif_dma.axi_awprot;
M_AXI_MAC_DMA_AWCACHE <= ipif_dma.axi_awcache;
ipif_dma.axi_wready <= M_AXI_MAC_DMA_WREADY;
M_AXI_MAC_DMA_WVALID <= ipif_dma.axi_wvalid;
M_AXI_MAC_DMA_WDATA <= ipif_dma.axi_wdata;
M_AXI_MAC_DMA_WSTRB <= ipif_dma.axi_wstrb;
M_AXI_MAC_DMA_WLAST <= ipif_dma.axi_wlast;
M_AXI_MAC_DMA_BREADY <= ipif_dma.axi_bready;
ipif_dma.axi_bvalid <= M_AXI_MAC_DMA_BVALID;
ipif_dma.axi_bresp <= M_AXI_MAC_DMA_BRESP;
-- ipif_dma --> ipif_dmaMasterHdler
ipif_dmaMasterHdler.rst <= intf_clkRst.dmaRst;
ipif_dmaMasterHdler.clk <= intf_clkRst.dmaClk;
ipif_dma.ipif_mstrd_req <= ipif_dmaMasterHdler.ipif_rdReq;
ipif_dma.ipif_mstwr_req <= ipif_dmaMasterHdler.ipif_wrReq;
ipif_dma.ipif_mst_addr <= ipif_dmaMasterHdler.ipif_addr(ipif_dma.ipif_mst_addr'range);
ipif_dma.ipif_mst_length <= ipif_dmaMasterHdler.ipif_length;
ipif_dma.ipif_mst_be <= ipif_dmaMasterHdler.ipif_be;
ipif_dma.ipif_mst_type <= ipif_dmaMasterHdler.ipif_type;
ipif_dma.ipif_mst_lock <= ipif_dmaMasterHdler.ipif_lock;
ipif_dma.ipif_mst_reset <= ipif_dmaMasterHdler.ipif_reset;
ipif_dmaMasterHdler.ipif_cmdAck <= ipif_dma.ipif_mst_cmdack;
ipif_dmaMasterHdler.ipif_cmplt <= ipif_dma.ipif_mst_cmplt;
ipif_dmaMasterHdler.ipif_error <= ipif_dma.ipif_mst_error;
ipif_dmaMasterHdler.ipif_rearbitrate <= ipif_dma.ipif_mst_rearbitrate;
ipif_dmaMasterHdler.ipif_cmdTimeout <= ipif_dma.ipif_mst_cmd_timeout;
ipif_dmaMasterHdler.ipif_rdData <= ipif_dma.ipif_mstrd_d;
ipif_dmaMasterHdler.ipif_rdRem <= ipif_dma.ipif_mstrd_rem;
ipif_dmaMasterHdler.nIpif_rdSof <= ipif_dma.ipif_mstrd_sof_n;
ipif_dmaMasterHdler.nIpif_rdEof <= ipif_dma.ipif_mstrd_eof_n;
ipif_dmaMasterHdler.nIpif_rdSrcRdy <= ipif_dma.ipif_mstrd_src_rdy_n;
ipif_dmaMasterHdler.nIpif_rdSrcDsc <= ipif_dma.ipif_mstrd_src_dsc_n;
ipif_dma.ipif_mstrd_dst_rdy_n <= ipif_dmaMasterHdler.nIpif_rdDstRdy;
ipif_dma.ipif_mstrd_dst_dsc_n <= ipif_dmaMasterHdler.nIpif_rdDstDsc;
ipif_dma.ipif_mstwr_d <= ipif_dmaMasterHdler.ipif_wrData;
ipif_dma.ipif_mstwr_rem <= ipif_dmaMasterHdler.ipif_wrRem;
ipif_dma.ipif_mstwr_sof_n <= ipif_dmaMasterHdler.nIpif_wrSof;
ipif_dma.ipif_mstwr_eof_n <= ipif_dmaMasterHdler.nIpif_wrEof;
ipif_dma.ipif_mstwr_src_rdy_n <= ipif_dmaMasterHdler.nIpif_wrSrcRdy;
ipif_dma.ipif_mstwr_src_dsc_n <= ipif_dmaMasterHdler.nIpif_wrSrcDsc;
ipif_dmaMasterHdler.nIpif_wrDstRdy <= ipif_dma.ipif_mstwr_dst_rdy_n;
ipif_dmaMasterHdler.nIpif_wrDstDsc <= ipif_dma.ipif_mstwr_dst_dsc_n;
-- ipif_dmaMasterHdler --> intf_dma
ipif_dmaMasterHdler.masterRead <= intf_dma.read;
ipif_dmaMasterHdler.masterWrite <= intf_dma.write;
ipif_dmaMasterHdler.masterAddress <= intf_dma.address;
ipif_dmaMasterHdler.masterWritedata <= intf_dma.writedata;
ipif_dmaMasterHdler.masterBurstcount <= intf_dma.burstcount;
ipif_dmaMasterHdler.masterBurstcounter <= intf_dma.burstcounter;
intf_dma.readdata <= ipif_dmaMasterHdler.masterReaddata;
intf_dma.waitrequest <= ipif_dmaMasterHdler.masterWaitrequest;
intf_dma.readdatavalid <= ipif_dmaMasterHdler.masterReaddatavalid;
---------------------------------------------------------------------------
-- Instantiations
---------------------------------------------------------------------------
--! This is the openMAC toplevel instantiation.
THEOPENMACTOP : entity work.openmacTop
generic map (
gPhyPortCount => gPhyPortCount,
gPhyPortType => gPhyPortType,
gSmiPortCount => gSmiPortCount,
gEndianness => gEndianness,
gEnableActivity => gEnableActivity,
gEnableDmaObserver => gEnableDmaObserver,
gDmaAddrWidth => gDmaAddrWidth,
gDmaDataWidth => gDmaDataWidth,
gDmaBurstCountWidth => gDmaBurstCountWidth,
gDmaWriteBurstLength => gDmaWriteBurstLength,
gDmaReadBurstLength => gDmaReadBurstLength,
gDmaWriteFifoLength => gDmaWriteFifoLength,
gDmaReadFifoLength => gDmaReadFifoLength,
gPacketBufferLocTx => gPacketBufferLocTx,
gPacketBufferLocRx => gPacketBufferLocRx,
gPacketBufferLog2Size => gPacketBufferLog2Size,
gTimerEnablePulse => gTimerEnablePulse,
gTimerEnablePulseWidth => gTimerEnablePulseWidth,
gTimerPulseRegWidth => gTimerPulseRegWidth
)
port map (
iClk => intf_clkRst.clk,
iRst => intf_clkRst.rst,
iDmaClk => intf_clkRst.dmaClk,
iDmaRst => intf_clkRst.dmaRst,
iPktBufClk => intf_clkRst.pktClk,
iPktBufRst => intf_clkRst.pktRst,
iClk2x => intf_clkRst.clk2x,
iMacReg_chipselect => intf_macReg.chipselect,
iMacReg_write => intf_macReg.write,
iMacReg_read => intf_macReg.read,
oMacReg_waitrequest => intf_macReg.waitrequest,
iMacReg_byteenable => intf_macReg.byteenable,
iMacReg_address => intf_macReg.address,
iMacReg_writedata => intf_macReg.writedata,
oMacReg_readdata => intf_macReg.readdata,
iMacTimer_chipselect => intf_macTimer.chipselect,
iMacTimer_write => intf_macTimer.write,
iMacTimer_read => intf_macTimer.read,
oMacTimer_waitrequest => intf_macTimer.waitrequest,
iMacTimer_address => intf_macTimer.address,
iMacTimer_byteenable => intf_macTimer.byteenable,
iMacTimer_writedata => intf_macTimer.writedata,
oMacTimer_readdata => intf_macTimer.readdata,
iPktBuf_chipselect => intf_pktBuf.chipselect,
iPktBuf_write => intf_pktBuf.write,
iPktBuf_read => intf_pktBuf.read,
oPktBuf_waitrequest => intf_pktBuf.waitrequest,
iPktBuf_byteenable => intf_pktBuf.byteenable,
iPktBuf_address => intf_pktBuf.address,
iPktBuf_writedata => intf_pktBuf.writedata,
oPktBuf_readdata => intf_pktBuf.readdata,
oDma_write => intf_dma.write,
oDma_read => intf_dma.read,
iDma_waitrequest => intf_dma.waitrequest,
iDma_readdatavalid => intf_dma.readdatavalid,
oDma_byteenable => intf_dma.byteenable,
oDma_address => intf_dma.address,
oDma_burstcount => intf_dma.burstcount,
oDma_burstcounter => intf_dma.burstcounter,
oDma_writedata => intf_dma.writedata,
iDma_readdata => intf_dma.readdata,
oMacTimer_interrupt => TIMER_IRQ,
oMacTimer_pulse => TIMER_PULSE_IRQ,
oMacTx_interrupt => macTx_interrupt,
oMacRx_interrupt => macRx_interrupt,
iRmii_Rx => rmiiRx,
iRmii_RxError => iRmii_rxError,
oRmii_Tx => rmiiTx,
iMii_Rx => miiRx,
iMii_RxError => iMii_rxError,
iMii_RxClk => iMii_rxClk,
oMii_Tx => miiTx,
iMii_TxClk => iMii_txClk,
onPhy_reset => oSmi_nPhyRst,
oSmi_clk => oSmi_clk,
oSmi_data_outEnable => smi_data_outEnable,
oSmi_data_out => smi_data_out,
iSmi_data_in => smi_data_in,
oActivity => oPktActivity
);
--! The MAC REG AXI lite IPIF converts the AXI interface to IPIF.
THEMACREG_AXILITE : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_MAC_REG_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_MAC_REG_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MAC_REG_MIN_SIZE,
C_USE_WSTRB => C_S_AXI_MAC_REG_USE_WSTRB,
C_DPHASE_TIMEOUT => C_S_AXI_MAC_REG_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => cMacReg_addressArray,
C_ARD_NUM_CE_ARRAY => (1, 1),
C_FAMILY => C_FAMILY
)
port map (
S_AXI_ACLK => ipif_macReg.axi_aclk,
S_AXI_ARESETN => ipif_macReg.axi_aresetn,
S_AXI_AWADDR => ipif_macReg.axi_awaddr,
S_AXI_AWVALID => ipif_macReg.axi_awvalid,
S_AXI_AWREADY => ipif_macReg.axi_awready,
S_AXI_WDATA => ipif_macReg.axi_wdata,
S_AXI_WSTRB => ipif_macReg.axi_wstrb,
S_AXI_WVALID => ipif_macReg.axi_wvalid,
S_AXI_WREADY => ipif_macReg.axi_wready,
S_AXI_BRESP => ipif_macReg.axi_bresp,
S_AXI_BVALID => ipif_macReg.axi_bvalid,
S_AXI_BREADY => ipif_macReg.axi_bready,
S_AXI_ARADDR => ipif_macReg.axi_araddr,
S_AXI_ARVALID => ipif_macReg.axi_arvalid,
S_AXI_ARREADY => ipif_macReg.axi_arready,
S_AXI_RDATA => ipif_macReg.axi_rdata,
S_AXI_RRESP => ipif_macReg.axi_rresp,
S_AXI_RVALID => ipif_macReg.axi_rvalid,
S_AXI_RREADY => ipif_macReg.axi_rready,
Bus2IP_Clk => ipif_macReg.ipif_clk,
Bus2IP_Resetn => ipif_macReg.ipif_resetn,
Bus2IP_Addr => ipif_macReg.ipif_addr,
Bus2IP_RNW => ipif_macReg.ipif_rnw,
Bus2IP_BE => ipif_macReg.ipif_be,
Bus2IP_CS => ipif_macReg.ipif_cs,
Bus2IP_RdCE => open, --don't need that feature
Bus2IP_WrCE => open, --don't need that feature
Bus2IP_Data => ipif_macReg.ipif_wrdata,
IP2Bus_Data => ipif_macReg.ipif_rddata,
IP2Bus_WrAck => ipif_macReg.ipif_wrack,
IP2Bus_RdAck => ipif_macReg.ipif_rdack,
IP2Bus_Error => ipif_macReg.ipif_error
);
--! The clock Xing ipcore transfers the signals in the AXI clock domain to
--! the iClk50 domain.
THEMACREG_CLKXING : entity libcommon.clkXing
generic map (
gCsNum => xing_macReg.fast.cs'length,
gDataWidth => xing_macReg.fast.readdata'length
)
port map (
iArst => xing_macReg.rst,
iFastClk => xing_macReg.fast.clk,
iFastCs => xing_macReg.fast.cs,
iFastRNW => xing_macReg.fast.rnw,
oFastReaddata => xing_macReg.fast.readdata,
oFastWrAck => xing_macReg.fast.wrAck,
oFastRdAck => xing_macReg.fast.rdAck,
iSlowClk => xing_macReg.slow.clk,
oSlowCs => xing_macReg.slow.cs,
oSlowRNW => xing_macReg.slow.rnw,
iSlowReaddata => xing_macReg.slow.readdata,
iSlowWrAck => xing_macReg.slow.wrAck,
iSlowRdAck => xing_macReg.slow.rdAck
);
--! The memory mapped slave converter changes from AXI's data width to 16 bit.
THEMACREG_MMCONV : entity work.mmSlaveConv
generic map (
gEndian => gEndianness,
gMasterAddrWidth => conv_macReg.master_address'length
)
port map (
iRst => conv_macReg.rst,
iClk => conv_macReg.clk,
iMaster_select => conv_macReg.master_select,
iMaster_write => conv_macReg.master_write,
iMaster_read => conv_macReg.master_read,
iMaster_byteenable => conv_macReg.master_byteenable,
iMaster_writedata => conv_macReg.master_writedata,
oMaster_readdata => conv_macReg.master_readdata,
iMaster_address => conv_macReg.master_address,
oMaster_WriteAck => conv_macReg.master_WriteAck,
oMaster_ReadAck => conv_macReg.master_ReadAck,
oSlave_select => conv_macReg.slave_select,
oSlave_write => conv_macReg.slave_write,
oSlave_read => conv_macReg.slave_read,
oSlave_address => conv_macReg.slave_address,
oSlave_byteenable => conv_macReg.slave_byteenable,
iSlave_readdata => conv_macReg.slave_readdata,
oSlave_writedata => conv_macReg.slave_writedata,
iSlave_ack => conv_macReg.slave_ack
);
--! Generate the packet buffer IPIF if any location is set to local.
GEN_THEMACPKT : if gPacketBufferLocRx = cPktBufLocal or gPacketBufferLocTx = cPktBufLocal generate
--! The MAC PKT BUF AXI lite IPIF converts the AXI interface to IPIF.
THEMACREG_AXILITE : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_MAC_PKT_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_MAC_PKT_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MAC_PKT_MIN_SIZE,
C_USE_WSTRB => C_S_AXI_MAC_PKT_USE_WSTRB,
C_DPHASE_TIMEOUT => C_S_AXI_MAC_PKT_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => cPktBuf_addressArray,
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_FAMILY => C_FAMILY
)
port map (
S_AXI_ACLK => ipif_pktBuf.axi_aclk,
S_AXI_ARESETN => ipif_pktBuf.axi_aresetn,
S_AXI_AWADDR => ipif_pktBuf.axi_awaddr,
S_AXI_AWVALID => ipif_pktBuf.axi_awvalid,
S_AXI_AWREADY => ipif_pktBuf.axi_awready,
S_AXI_WDATA => ipif_pktBuf.axi_wdata,
S_AXI_WSTRB => ipif_pktBuf.axi_wstrb,
S_AXI_WVALID => ipif_pktBuf.axi_wvalid,
S_AXI_WREADY => ipif_pktBuf.axi_wready,
S_AXI_BRESP => ipif_pktBuf.axi_bresp,
S_AXI_BVALID => ipif_pktBuf.axi_bvalid,
S_AXI_BREADY => ipif_pktBuf.axi_bready,
S_AXI_ARADDR => ipif_pktBuf.axi_araddr,
S_AXI_ARVALID => ipif_pktBuf.axi_arvalid,
S_AXI_ARREADY => ipif_pktBuf.axi_arready,
S_AXI_RDATA => ipif_pktBuf.axi_rdata,
S_AXI_RRESP => ipif_pktBuf.axi_rresp,
S_AXI_RVALID => ipif_pktBuf.axi_rvalid,
S_AXI_RREADY => ipif_pktBuf.axi_rready,
Bus2IP_Clk => ipif_pktBuf.ipif_clk,
Bus2IP_Resetn => ipif_pktBuf.ipif_resetn,
Bus2IP_Addr => ipif_pktBuf.ipif_addr,
Bus2IP_RNW => ipif_pktBuf.ipif_rnw,
Bus2IP_BE => ipif_pktBuf.ipif_be,
Bus2IP_CS => ipif_pktBuf.ipif_cs,
Bus2IP_RdCE => open, --don't need that feature
Bus2IP_WrCE => open, --don't need that feature
Bus2IP_Data => ipif_pktBuf.ipif_wrdata,
IP2Bus_Data => ipif_pktBuf.ipif_rddata,
IP2Bus_WrAck => ipif_pktBuf.ipif_wrack,
IP2Bus_RdAck => ipif_pktBuf.ipif_rdack,
IP2Bus_Error => ipif_pktBuf.ipif_error
);
end generate GEN_THEMACPKT;
GEN_THEMACDMA : if gPacketBufferLocRx = cPktBufExtern or gPacketBufferLocTx = cPktBufExtern generate
--! The MAC DMA AXI master IPIF converts the AXI interface to IPIF.
THEMACDMA_AXI : entity axi_master_burst_v1_00_a.axi_master_burst
generic map (
C_M_AXI_ADDR_WIDTH => C_M_AXI_MAC_DMA_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_MAC_DMA_DATA_WIDTH,
C_MAX_BURST_LEN => C_M_AXI_MAC_DMA_MAX_BURST_LEN,
C_ADDR_PIPE_DEPTH => 1,
C_NATIVE_DATA_WIDTH => C_M_AXI_MAC_DMA_NATIVE_DWIDTH,
C_LENGTH_WIDTH => C_M_AXI_MAC_DMA_LENGTH_WIDTH,
C_FAMILY => C_FAMILY
)
port map (
m_axi_aclk => ipif_dma.axi_aclk,
m_axi_aresetn => ipif_dma.axi_aresetn,
md_error => ipif_dma.md_error,
m_axi_arready => ipif_dma.axi_arready,
m_axi_arvalid => ipif_dma.axi_arvalid,
m_axi_araddr => ipif_dma.axi_araddr,
m_axi_arlen => ipif_dma.axi_arlen,
m_axi_arsize => ipif_dma.axi_arsize,
m_axi_arburst => ipif_dma.axi_arburst,
m_axi_arprot => ipif_dma.axi_arprot,
m_axi_arcache => ipif_dma.axi_arcache,
m_axi_rready => ipif_dma.axi_rready,
m_axi_rvalid => ipif_dma.axi_rvalid,
m_axi_rdata => ipif_dma.axi_rdata,
m_axi_rresp => ipif_dma.axi_rresp,
m_axi_rlast => ipif_dma.axi_rlast,
m_axi_awready => ipif_dma.axi_awready,
m_axi_awvalid => ipif_dma.axi_awvalid,
m_axi_awaddr => ipif_dma.axi_awaddr,
m_axi_awlen => ipif_dma.axi_awlen,
m_axi_awsize => ipif_dma.axi_awsize,
m_axi_awburst => ipif_dma.axi_awburst,
m_axi_awprot => ipif_dma.axi_awprot,
m_axi_awcache => ipif_dma.axi_awcache,
m_axi_wready => ipif_dma.axi_wready,
m_axi_wvalid => ipif_dma.axi_wvalid,
m_axi_wdata => ipif_dma.axi_wdata,
m_axi_wstrb => ipif_dma.axi_wstrb,
m_axi_wlast => ipif_dma.axi_wlast,
m_axi_bready => ipif_dma.axi_bready,
m_axi_bvalid => ipif_dma.axi_bvalid,
m_axi_bresp => ipif_dma.axi_bresp,
ip2bus_mstrd_req => ipif_dma.ipif_mstrd_req,
ip2bus_mstwr_req => ipif_dma.ipif_mstwr_req,
ip2bus_mst_addr => ipif_dma.ipif_mst_addr,
ip2bus_mst_length => ipif_dma.ipif_mst_length,
ip2bus_mst_be => ipif_dma.ipif_mst_be,
ip2bus_mst_type => ipif_dma.ipif_mst_type,
ip2bus_mst_lock => ipif_dma.ipif_mst_lock,
ip2bus_mst_reset => ipif_dma.ipif_mst_reset,
bus2ip_mst_cmdack => ipif_dma.ipif_mst_cmdack,
bus2ip_mst_cmplt => ipif_dma.ipif_mst_cmplt,
bus2ip_mst_error => ipif_dma.ipif_mst_error,
bus2ip_mst_rearbitrate => ipif_dma.ipif_mst_rearbitrate,
bus2ip_mst_cmd_timeout => ipif_dma.ipif_mst_cmd_timeout,
bus2ip_mstrd_d => ipif_dma.ipif_mstrd_d,
bus2ip_mstrd_rem => ipif_dma.ipif_mstrd_rem,
bus2ip_mstrd_sof_n => ipif_dma.ipif_mstrd_sof_n,
bus2ip_mstrd_eof_n => ipif_dma.ipif_mstrd_eof_n,
bus2ip_mstrd_src_rdy_n => ipif_dma.ipif_mstrd_src_rdy_n,
bus2ip_mstrd_src_dsc_n => ipif_dma.ipif_mstrd_src_dsc_n,
ip2bus_mstrd_dst_rdy_n => ipif_dma.ipif_mstrd_dst_rdy_n,
ip2bus_mstrd_dst_dsc_n => ipif_dma.ipif_mstrd_dst_dsc_n,
ip2bus_mstwr_d => ipif_dma.ipif_mstwr_d,
ip2bus_mstwr_rem => ipif_dma.ipif_mstwr_rem,
ip2bus_mstwr_sof_n => ipif_dma.ipif_mstwr_sof_n,
ip2bus_mstwr_eof_n => ipif_dma.ipif_mstwr_eof_n,
ip2bus_mstwr_src_rdy_n => ipif_dma.ipif_mstwr_src_rdy_n,
ip2bus_mstwr_src_dsc_n => ipif_dma.ipif_mstwr_src_dsc_n,
bus2ip_mstwr_dst_rdy_n => ipif_dma.ipif_mstwr_dst_rdy_n,
bus2ip_mstwr_dst_dsc_n => ipif_dma.ipif_mstwr_dst_dsc_n
);
--! The IPIF master handler converts the IPIF master signals to the
--! openMAC's DMA interface.
THEMACDMA_IPIF_HANDLER : entity work.ipifMasterHandler
generic map (
gMasterAddrWidth => ipif_dmaMasterHdler.masterAddress'length,
gMasterBurstCountWidth => ipif_dmaMasterHdler.masterBurstcount'length,
gIpifAddrWidth => ipif_dmaMasterHdler.ipif_addr'length,
gIpifLength => ipif_dmaMasterHdler.ipif_length'length
)
port map (
iRst => ipif_dmaMasterHdler.rst,
iClk => ipif_dmaMasterHdler.clk,
iIpif_cmdAck => ipif_dmaMasterHdler.ipif_cmdAck,
iIpif_cmplt => ipif_dmaMasterHdler.ipif_cmplt,
iIpif_error => ipif_dmaMasterHdler.ipif_error,
iIpif_rearbitrate => ipif_dmaMasterHdler.ipif_rearbitrate,
iIpif_cmdTimeout => ipif_dmaMasterHdler.ipif_cmdTimeout,
oIpif_type => ipif_dmaMasterHdler.ipif_type,
oIpif_addr => ipif_dmaMasterHdler.ipif_addr,
oIpif_length => ipif_dmaMasterHdler.ipif_length,
oIpif_be => ipif_dmaMasterHdler.ipif_be,
oIpif_lock => ipif_dmaMasterHdler.ipif_lock,
oIpif_reset => ipif_dmaMasterHdler.ipif_reset,
iIpif_rdData => ipif_dmaMasterHdler.ipif_rdData,
iIpif_rdRem => ipif_dmaMasterHdler.ipif_rdRem,
oIpif_rdReq => ipif_dmaMasterHdler.ipif_rdReq,
inIpif_rdSof => ipif_dmaMasterHdler.nIpif_rdSof,
inIpif_rdEof => ipif_dmaMasterHdler.nIpif_rdEof,
inIpif_rdSrcRdy => ipif_dmaMasterHdler.nIpif_rdSrcRdy,
inIpif_rdSrcDsc => ipif_dmaMasterHdler.nIpif_rdSrcDsc,
onIpif_rdDstRdy => ipif_dmaMasterHdler.nIpif_rdDstRdy,
onIpif_rdDstDsc => ipif_dmaMasterHdler.nIpif_rdDstDsc,
oIpif_wrData => ipif_dmaMasterHdler.ipif_wrData,
oIpif_wrRem => ipif_dmaMasterHdler.ipif_wrRem,
oIpif_wrReq => ipif_dmaMasterHdler.ipif_wrReq,
onIpif_wrSof => ipif_dmaMasterHdler.nIpif_wrSof,
onIpif_wrEof => ipif_dmaMasterHdler.nIpif_wrEof,
onIpif_wrSrcRdy => ipif_dmaMasterHdler.nIpif_wrSrcRdy,
onIpif_wrSrcDsc => ipif_dmaMasterHdler.nIpif_wrSrcDsc,
inIpif_wrDstRdy => ipif_dmaMasterHdler.nIpif_wrDstRdy,
inIpif_wrDstDsc => ipif_dmaMasterHdler.nIpif_wrDstDsc,
iMasterRead => ipif_dmaMasterHdler.masterRead,
iMasterWrite => ipif_dmaMasterHdler.masterWrite,
iMasterAddress => ipif_dmaMasterHdler.masterAddress,
iMasterWritedata => ipif_dmaMasterHdler.masterWritedata,
iMasterBurstcount => ipif_dmaMasterHdler.masterBurstcount,
iMasterBurstcounter => ipif_dmaMasterHdler.masterBurstcounter,
oMasterReaddata => ipif_dmaMasterHdler.masterReaddata,
oMasterWaitrequest => ipif_dmaMasterHdler.masterWaitrequest,
oMasterReaddatavalid => ipif_dmaMasterHdler.masterReaddatavalid
);
end generate GEN_THEMACDMA;
GEN_RMII_CLK : if gPhyPortType = cPhyPortRmii generate
GEN_ODDR2 : for i in oRmii_clk'range generate
signal rmiiClk : std_logic;
signal nRmiiClk : std_logic;
begin
-- Assign rmii clock (used by openMAC) and the inverted to ODDR2.
rmiiClk <= intf_clkRst.clk;
nRmiiClk <= not rmiiClk;
--! This is a dual data rate output FF used to output the internal
--! RMII clock.
THEODDR2 : oddr2
generic map (
DDR_ALIGNMENT => "NONE", -- align D0 with C0 and D1 with C1 edge
INIT => '0', -- initialize Q with '0'
SRTYPE => "SYNC" -- take default, since RS are unused
)
port map (
D0 => cActivated,
D1 => cInactivated,
C0 => rmiiClk,
C1 => nRmiiClk,
CE => cActivated,
R => cInactivated, --unused
S => cInactivated, --unused
Q => oRmii_clk(i)
);
end generate GEN_ODDR2;
end generate GEN_RMII_CLK;
end rtl;
| gpl-2.0 | d2474b5342cbda71560f75f4cf0c88ef | 0.524929 | 4.047505 | false | false | false | false |
DreamIP/GPStudio | support/process/lbp/hdl/lbp_process.vhd | 1 | 4,087 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.math_real.all;
library std;
entity lbp_process is
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
------------------------- params ------------------------
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0);
theshold_i : in std_logic_vector(7 downto 0)
);
end lbp_process;
architecture rtl of lbp_process is
component matrix_extractor
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer;
OUTVALUE_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector((OUTVALUE_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
------------------------ matrix out ---------------------
p00, p01, p02 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p10, p11, p12 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p20, p21, p22 : out std_logic_vector((PIX_WIDTH-1) downto 0);
matrix_dv : out std_logic;
---------------------- computed value -------------------
value_data : in std_logic_vector((OUTVALUE_WIDTH-1) downto 0);
value_dv : in std_logic;
------------------------- params ------------------------
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0)
);
end component;
signal p00, p01, p02 : std_logic_vector((PIX_WIDTH-1) downto 0);
signal p10, p11, p12 : std_logic_vector((PIX_WIDTH-1) downto 0);
signal p20, p21, p22 : std_logic_vector((PIX_WIDTH-1) downto 0);
signal matrix_dv : std_logic;
signal value_data : std_logic_vector((PIX_WIDTH-1) downto 0);
signal value_dv : std_logic;
begin
matrix_extractor_inst : matrix_extractor
generic map (
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
PIX_WIDTH => PIX_WIDTH,
OUTVALUE_WIDTH => PIX_WIDTH
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
p00 => p00, p01 => p01, p02 => p02,
p10 => p10, p11 => p11, p12 => p12,
p20 => p20, p21 => p21, p22 => p22,
matrix_dv => matrix_dv,
value_data => value_data,
value_dv => value_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv,
enable_i => enable_i,
widthimg_i => widthimg_i
);
process (clk_proc, reset_n, matrix_dv)
begin
if(reset_n='0') then
elsif(rising_edge(clk_proc)) then
value_dv<='0';
if(matrix_dv='1') then
if(unsigned(p11)>unsigned(p00)+unsigned(theshold_i)) then value_data(0) <= '1'; else value_data(0) <= '0'; end if;
if(unsigned(p11)>unsigned(p01)+unsigned(theshold_i)) then value_data(1) <= '1'; else value_data(1) <= '0'; end if;
if(unsigned(p11)>unsigned(p02)+unsigned(theshold_i)) then value_data(2) <= '1'; else value_data(2) <= '0'; end if;
if(unsigned(p11)>unsigned(p10)+unsigned(theshold_i)) then value_data(3) <= '1'; else value_data(3) <= '0'; end if;
if(unsigned(p11)>unsigned(p12)+unsigned(theshold_i)) then value_data(4) <= '1'; else value_data(4) <= '0'; end if;
if(unsigned(p11)>unsigned(p20)+unsigned(theshold_i)) then value_data(5) <= '1'; else value_data(5) <= '0'; end if;
if(unsigned(p11)>unsigned(p21)+unsigned(theshold_i)) then value_data(6) <= '1'; else value_data(6) <= '0'; end if;
if(unsigned(p11)>unsigned(p22)+unsigned(theshold_i)) then value_data(7) <= '1'; else value_data(7) <= '0'; end if;
--~ value_data<=p11;
value_dv<='1';
end if;
end if;
end process;
end rtl;
| gpl-3.0 | 2be5ba631c2c2e99f71cb2118bfecaf0 | 0.574505 | 2.793575 | false | false | false | false |
hoglet67/ElectronFpga | src/xilinx/ElectronFpga_duo.vhd | 1 | 7,719 | --------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : ElectronFpga_duo.vhf
-- /___/ /\ Timestamp : 28/07/2015
-- \ \ / \
-- \___\/\___\
--
--Design Name: ElectronFpga_duo
--Device: Spartan6 LX9
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity ElectronFpga_duo is
port (
clk_32M00 : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
ERST : in std_logic;
red : out std_logic_vector (3 downto 0);
green : out std_logic_vector (3 downto 0);
blue : out std_logic_vector (3 downto 0);
vsync : out std_logic;
hsync : out std_logic;
audioL : out std_logic;
audioR : out std_logic;
casIn : in std_logic;
casOut : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
SRAM_nOE : out std_logic;
SRAM_nWE : out std_logic;
SRAM_nCS : out std_logic;
SRAM_A : out std_logic_vector (20 downto 0);
SRAM_D : inout std_logic_vector (7 downto 0);
ARDUINO_RESET : out std_logic;
SW1 : in std_logic;
FLASH_CS : out std_logic; -- Active low FLASH chip select
FLASH_SI : out std_logic; -- Serial output to FLASH chip SI pin
FLASH_CK : out std_logic; -- FLASH clock
FLASH_SO : in std_logic; -- Serial input from FLASH chip SO pin
SDMISO : in std_logic;
SDSS : out std_logic;
SDCLK : out std_logic;
SDMOSI : out std_logic;
DIP : in std_logic_vector(1 downto 0);
test : out std_logic_vector(7 downto 0);
avr_RxD : in std_logic;
avr_TxD : out std_logic
);
end;
architecture behavioral of ElectronFpga_duo is
signal clock_16 : std_logic;
signal clock_24 : std_logic;
signal clock_32 : std_logic;
signal clock_33 : std_logic;
signal clock_40 : std_logic;
signal hard_reset_n : std_logic;
signal powerup_reset_n : std_logic;
signal reset_counter : std_logic_vector (9 downto 0);
signal RAM_A : std_logic_vector (18 downto 0);
signal RAM_Din : std_logic_vector (7 downto 0);
signal RAM_Dout : std_logic_vector (7 downto 0);
signal RAM_nWE : std_logic;
signal RAM_nOE : std_logic;
signal RAM_nCS : std_logic;
-----------------------------------------------
-- Bootstrap ROM Image from SPI FLASH into SRAM
-----------------------------------------------
-- start address of user data in FLASH as obtained from bitmerge.py
-- this is safely beyond the end of the bitstream
constant user_address : std_logic_vector(23 downto 0) := x"060000";
-- lenth of user data in FLASH = 256KB (16x 16K ROM) images
constant user_length : std_logic_vector(23 downto 0) := x"040000";
-- high when FLASH is being copied to SRAM, can be used by user as active high reset
signal bootstrap_busy : std_logic;
begin
inst_pll1: entity work.pll1 port map(
-- 32 MHz input clock
CLKIN_IN => clk_32M00,
-- the main system clock, and also the video clock in sRGB mode
CLK0_OUT => clock_16,
-- used as a 24.00MHz for the SAA5050 in Mode 7
CLK1_OUT => clock_24,
-- used as a output clock MIST scan doubler for the SAA5050 in Mode 7
CLK2_OUT => clock_32,
-- used as a video clock when the ULA is in 60Hz VGA Mode
CLK3_OUT => clock_40
);
inst_dcm1 : entity work.dcm1 port map(
CLKIN_IN => clk_32M00,
-- used as a video clock when the ULA is in 50Hz VGA Mode
CLKFX_OUT => clock_33
);
electron_core : entity work.ElectronFpga_core
generic map (
IncludeICEDebugger => true,
IncludeABRRegs => true,
IncludeJafaMode7 => true
)
port map (
clk_16M00 => clock_16,
clk_24M00 => clock_24,
clk_32M00 => clock_32,
clk_33M33 => clock_33,
clk_40M00 => clock_40,
hard_reset_n => hard_reset_n,
ps2_clk => ps2_clk,
ps2_data => ps2_data,
video_red => red,
video_green => green,
video_blue => blue,
video_vsync => vsync,
video_hsync => hsync,
audio_l => audioL,
audio_r => audioR,
ext_nOE => RAM_nOE,
ext_nWE => RAM_nWE,
ext_nCS => RAM_nCS,
ext_A => RAM_A,
ext_Dout => RAM_Dout,
ext_Din => RAM_Din,
SDMISO => SDMISO,
SDSS => SDSS,
SDCLK => SDCLK,
SDMOSI => SDMOSI,
caps_led => LED1,
motor_led => LED2,
cassette_in => casIn,
cassette_out => casOut,
vid_mode => DIP,
test => test,
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
cpu_addr => open
);
--------------------------------------------------------
-- Power Up Reset Generation
--------------------------------------------------------
-- Generate a reliable power up reset, as ERST on the Papilio doesn't do this
reset_gen : process(clock_32)
begin
if rising_edge(clock_32) then
if (reset_counter(reset_counter'high) = '0') then
reset_counter <= reset_counter + 1;
end if;
powerup_reset_n <= not ERST and reset_counter(reset_counter'high);
end if;
end process;
-- extend the version seen by the core to hold the 6502 reset during bootstrap
hard_reset_n <= powerup_reset_n and not bootstrap_busy;
--------------------------------------------------------
-- Papilio Duo Misc
--------------------------------------------------------
-- Follow convention for keeping Arduino reset
ARDUINO_RESET <= SW1;
--------------------------------------------------------
-- BOOTSTRAP SPI FLASH to SRAM
--------------------------------------------------------
inst_bootstrap: entity work.bootstrap
generic map (
user_address => user_address,
user_length => user_length
)
port map(
clock => clock_16,
powerup_reset_n => powerup_reset_n,
bootstrap_busy => bootstrap_busy,
RAM_nOE => RAM_nOE,
RAM_nWE => RAM_nWE,
RAM_nCS => RAM_nCS,
RAM_A => RAM_A,
RAM_Din => RAM_Din,
RAM_Dout => RAM_Dout,
SRAM_nOE => SRAM_nOE,
SRAM_nWE => SRAM_nWE,
SRAM_nCS => SRAM_nCS,
SRAM_A => SRAM_A,
SRAM_D => SRAM_D,
FLASH_CS => FLASH_CS,
FLASH_SI => FLASH_SI,
FLASH_CK => FLASH_CK,
FLASH_SO => FLASH_SO
);
end behavioral;
| gpl-3.0 | abd6877394a6ed4b51ea5acbc13eaf5f | 0.455759 | 3.958462 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/boards/terasic-de2-115/mn-single-hostif-drv/quartus/toplevel.vhd | 3 | 13,867 | -------------------------------------------------------------------------------
--! @file toplevel.vhd
--
--! @brief Toplevel of Nios MN design Pcp part
--
--! @details This is the toplevel of the Nios MN FPGA Pcp design for the
--! INK DE2-115 Evaluation Board.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library libcommon;
use libcommon.global.all;
entity toplevel is
port (
-- 50 MHZ CLK IN
EXT_CLK : in std_logic;
-- PHY Interfaces
PHY_GXCLK : out std_logic_vector(1 downto 0);
PHY_LINK_n : in std_logic_vector(1 downto 0);
PHY_RXCLK : in std_logic_vector(1 downto 0);
PHY_RXER : in std_logic_vector(1 downto 0);
PHY_RXDV : in std_logic_vector(1 downto 0);
PHY_RXD : in std_logic_vector(7 downto 0);
PHY_TXCLK : in std_logic_vector(1 downto 0);
PHY_TXER : out std_logic_vector(1 downto 0);
PHY_TXEN : out std_logic_vector(1 downto 0);
PHY_TXD : out std_logic_vector(7 downto 0);
PHY_MDIO : inout std_logic_vector(1 downto 0);
PHY_MDC : out std_logic_vector(1 downto 0);
PHY_RESET_n : out std_logic_vector(1 downto 0);
-- EPCS
EPCS_DCLK : out std_logic;
EPCS_SCE : out std_logic;
EPCS_SDO : out std_logic;
EPCS_DATA0 : in std_logic;
-- 2 MB SRAM
SRAM_CE_n : out std_logic;
SRAM_OE_n : out std_logic;
SRAM_WE_n : out std_logic;
SRAM_ADDR : out std_logic_vector(20 downto 1);
SRAM_BE_n : out std_logic_vector(1 downto 0);
SRAM_DQ : inout std_logic_vector(15 downto 0);
-- HOST Interface
HOSTIF_AD : inout std_logic_vector(16 downto 0);
HOSTIF_BE : in std_logic_vector(1 downto 0);
HOSTIF_CS_n : in std_logic;
HOSTIF_WR_n : in std_logic;
HOSTIF_RD_n : in std_logic;
HOSTIF_ALE_n : in std_logic;
HOSTIF_ACK_n : out std_logic;
HOSTIF_IRQ_n : out std_logic;
-- LED
LEDG : out std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(15 downto 0)
);
end toplevel;
architecture rtl of toplevel is
component mnSingleHostifDrv is
port (
clk25_clk : in std_logic;
clk50_clk : in std_logic := 'X';
clk100_clk : in std_logic;
reset_reset_n : in std_logic := 'X';
tri_state_0_tcm_address_out : out std_logic_vector(20 downto 0);
tri_state_0_tcm_byteenable_n_out : out std_logic_vector(1 downto 0);
tri_state_0_tcm_read_n_out : out std_logic;
tri_state_0_tcm_write_n_out : out std_logic;
tri_state_0_tcm_data_out : inout std_logic_vector(15 downto 0) := (others => 'X');
tri_state_0_tcm_chipselect_n_out : out std_logic;
pcp_0_benchmark_pio_export : out std_logic_vector(7 downto 0);
-- OPENMAC
openmac_0_mii_txEnable : out std_logic_vector(1 downto 0);
openmac_0_mii_txData : out std_logic_vector(7 downto 0);
openmac_0_mii_txClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxError : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxDataValid : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxData : in std_logic_vector(7 downto 0) := (others => 'X');
openmac_0_mii_rxClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_smi_nPhyRst : out std_logic_vector(1 downto 0);
openmac_0_smi_clk : out std_logic_vector(1 downto 0);
openmac_0_smi_dio : inout std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_pktactivity_export : out std_logic;
epcs_flash_dclk : out std_logic;
epcs_flash_sce : out std_logic;
epcs_flash_sdo : out std_logic;
epcs_flash_data0 : in std_logic := 'X';
hostinterface_0_irqout_irq : out std_logic;
prl0_iPrlSlv_cs : in std_logic := 'X';
prl0_iPrlSlv_rd : in std_logic := 'X';
prl0_iPrlSlv_wr : in std_logic := 'X';
prl0_iPrlSlv_ale : in std_logic := 'X';
prl0_oPrlSlv_ack : out std_logic;
prl0_iPrlSlv_be : in std_logic_vector(1 downto 0) := (others => 'X');
prl0_oPrlSlv_ad_o : out std_logic_vector(16 downto 0);
prl0_iPrlSlv_ad_i : in std_logic_vector(16 downto 0) := (others => 'X');
prl0_oPrlSlv_ad_oen : out std_logic;
-- CPU RESET REQUEST
pcp_0_cpu_resetrequest_resetrequest : in std_logic := 'X';
pcp_0_cpu_resetrequest_resettaken : out std_logic;
-- LED green
powerlink_led_export : out std_logic_vector(1 downto 0)
);
end component mnSingleHostifDrv;
-- PLL component
component pll
port (
inclk0 : in std_logic;
c0 : out std_logic;
c1 : out std_logic;
c2 : out std_logic;
c3 : out std_logic;
locked : out std_logic
);
end component;
signal clk25 : std_logic;
signal clk50 : std_logic;
signal clk100 : std_logic;
signal clk100_p : std_logic;
signal pllLocked : std_logic;
signal sramAddr : std_logic_vector(SRAM_ADDR'high downto 0);
signal plk_status_error : std_logic_vector(1 downto 0);
signal openmac_activity : std_logic;
signal parHost_chipselect : std_logic;
signal parHost_read : std_logic;
signal parHost_write : std_logic;
signal parHost_addressLatchEnable : std_logic;
signal parHost_acknowledge : std_logic;
signal parHost_ad_o : std_logic_vector(HOSTIF_AD'range);
signal parHost_ad_i : std_logic_vector(HOSTIF_AD'range);
signal parHost_ad_oen : std_logic;
signal host_irq : std_logic;
begin
SRAM_ADDR <= sramAddr(SRAM_ADDR'range);
PHY_GXCLK <= (others => '0');
PHY_TXER <= (others => '0');
HOSTIF_ACK_n <= not parHost_acknowledge;
HOSTIF_IRQ_n <= not host_irq;
parHost_chipselect <= not HOSTIF_CS_n;
parHost_write <= not HOSTIF_WR_n;
parHost_read <= not HOSTIF_RD_n;
parHost_addressLatchEnable <= not HOSTIF_ALE_n;
-- TRISTATE Buffer for AD bus
HOSTIF_AD <= parHost_ad_o when parHost_ad_oen = '1' else (others => 'Z');
parHost_ad_i <= HOSTIF_AD;
---------------------------------------------------------------------------
-- Green LED assignments
LEDG <= plk_status_error(0) & -- POWERLINK Status LED
"000" & -- Reserved
(openmac_activity and not PHY_LINK_n(0)) & -- Gated activity
not PHY_LINK_n(0) & -- Link
(openmac_activity and not PHY_LINK_n(1)) & -- Gated activity
not PHY_LINK_n(1); -- Link
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Red LED assignments
LEDR <= x"000" & -- Reserved
"000" & -- Reserved
plk_status_error(1); -- POWERLINK Error LED
---------------------------------------------------------------------------
inst : component mnSingleHostifDrv
port map (
clk25_clk => clk25,
clk50_clk => clk50,
clk100_clk => clk100,
reset_reset_n => pllLocked,
pcp_0_cpu_resetrequest_resetrequest => '0',
pcp_0_cpu_resetrequest_resettaken => open,
openmac_0_mii_txEnable => PHY_TXEN,
openmac_0_mii_txData => PHY_TXD,
openmac_0_mii_txClk => PHY_TXCLK,
openmac_0_mii_rxError => PHY_RXER,
openmac_0_mii_rxDataValid => PHY_RXDV,
openmac_0_mii_rxData => PHY_RXD,
openmac_0_mii_rxClk => PHY_RXCLK,
openmac_0_smi_nPhyRst => PHY_RESET_n,
openmac_0_smi_clk => PHY_MDC,
openmac_0_smi_dio => PHY_MDIO,
openmac_0_pktactivity_export => openmac_activity,
tri_state_0_tcm_address_out => sramAddr,
tri_state_0_tcm_read_n_out => SRAM_OE_n,
tri_state_0_tcm_byteenable_n_out => SRAM_BE_n,
tri_state_0_tcm_write_n_out => SRAM_WE_n,
tri_state_0_tcm_data_out => SRAM_DQ,
tri_state_0_tcm_chipselect_n_out => SRAM_CE_n,
pcp_0_benchmark_pio_export => open,
epcs_flash_dclk => EPCS_DCLK,
epcs_flash_sce => EPCS_SCE,
epcs_flash_sdo => EPCS_SDO,
epcs_flash_data0 => EPCS_DATA0,
hostinterface_0_irqout_irq => host_irq,
prl0_iPrlSlv_cs => parHost_chipselect,
prl0_iPrlSlv_rd => parHost_read,
prl0_iPrlSlv_wr => parHost_write,
prl0_iPrlSlv_ale => parHost_addressLatchEnable,
prl0_oPrlSlv_ack => parHost_acknowledge,
prl0_iPrlSlv_be => HOSTIF_BE,
prl0_oPrlSlv_ad_o => parHost_ad_o,
prl0_iPrlSlv_ad_i => parHost_ad_i,
prl0_oPrlSlv_ad_oen => parHost_ad_oen,
powerlink_led_export => plk_status_error
);
-- Pll Instance
pllInst : pll
port map (
inclk0 => EXT_CLK,
c0 => clk50,
c1 => clk100,
c2 => clk25,
c3 => open,
locked => pllLocked
);
end rtl;
| gpl-2.0 | ed088836415d7e47f44a426ecda8df2d | 0.452369 | 4.328027 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/xilinx/parallelinterface/src/parallelInterface-rtl-ea.vhd | 3 | 18,871 | -------------------------------------------------------------------------------
--! @file parallelInterfaceRtl.vhd
--
--! @brief Parallel Interface for Host Interface
--
--! @details This is the parallel interface implementation for
--! the host interface suitable for inbuilt Xilinx EPC.
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014, B&R Industrial Automation GmbH
-- Copyright (c) 2014, Kalycito Infotech Private Limited.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--! Use standard ieee library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Use numerics
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use host interface package for specific types
use work.hostInterfacePkg.all;
entity parallelInterface is
generic (
--! Data bus width
gDataWidth : natural := 16;
--! Address and Data bus are multiplexed (0 = FALSE, otherwise = TRUE)
gMultiplex : natural := 0
);
port (
-- Parallel Interface
--! Chip select
iParHostChipselect : in std_logic := cInactivated;
--! Read strobe
iParHostRead : in std_logic := cInactivated;
--! Write strobe
iParHostWrite : in std_logic := cInactivated;
--! Address Latch enable (Multiplexed only)
iParHostAddressLatchEnable : in std_logic := cInactivated;
--! High active Acknowledge
oParHostAcknowledge : out std_logic := cInactivated;
--! Byte enable
iParHostByteenable : in std_logic_vector(gDataWidth/cByte-1 downto 0) := (others => cInactivated);
--! Address bus (De-multiplexed, word-address)
iParHostAddress : in std_logic_vector(15 downto 0) := (others => cInactivated);
--! Data bus out (De-multiplexed)
oParHostData : out std_logic_vector(gDataWidth-1 downto 0) := (others => cInactivated);
--! Data bus in (De-multiplexed)
iParHostData : in std_logic_vector(gDataWidth-1 downto 0) := (others => cInactivated);
--! Data bus output enable (De-multiplexed)
oParHostDataEnable : out std_logic;
--! Address/Data bus out (Multiplexed, word-address))
oParHostAddressData : out std_logic_vector(gDataWidth-1 downto 0) := (others => cInactivated);
--! Address/Data bus in (Multiplexed, word-address))
iParHostAddressData : in std_logic_vector(gDataWidth-1 downto 0) := (others => cInactivated);
--! Address/Data bus output enable (Multiplexed, word-address))
oParHostAddressDataEnable : out std_logic;
-- Clock/Reset sources
--! Clock Source input
iClk : in std_logic:= cInactivated;
--! Reset Source input
iRst : in std_logic:= cInactivated;
-- Memory Mapped Slave for Host
--! MM slave host address
oHostAddress : out std_logic_vector(16 downto 2) := (others => cInactivated);
--! MM slave host byte enable
oHostByteenable : out std_logic_vector(3 downto 0) := (others => cInactivated);
--! MM slave host read
oHostRead : out std_logic := cInactivated;
--! MM slave host read data
iHostReaddata : in std_logic_vector(31 downto 0) := (others => cInactivated);
--! MM slave host write
oHostWrite : out std_logic := cInactivated;
--! MM slave host write data
oHostWritedata : out std_logic_vector(31 downto 0) := (others => cInactivated);
--! MM slave host wait request
iHostWaitrequest : in std_logic := cInactivated
);
end parallelInterface;
architecture rtl of parallelInterface is
--! address register to store the address populated to the interface
signal addressRegister : std_logic_vector(iParHostAddress'range);
--! register clock enable
signal addressRegClkEnable : std_logic;
--! byte enable register to store byte enable qualifiers
signal byteenableRegister : std_logic_vector(gDataWidth/cByte-1 downto 0);
--! register clock enable
signal byteenableRegClkEnable : std_logic;
--! write data register to store the data populated to the interface
signal writeDataRegister : std_logic_vector(gDataWidth-1 downto 0);
--! register clock enable
signal writeDataRegClkEnable : std_logic;
--! read data register to store the read data populated to the host
signal readDataRegister : std_logic_vector(gDataWidth-1 downto 0);
--! temporary readDataRegister
signal readDataRegister_next : std_logic_vector(gDataWidth-1 downto 0);
-- synchronized signals
--! Synchronized chip select signal
signal hostChipselect : std_logic;
--! Write signal for initialize the transfer
signal hostWrite : std_logic;
--! Synchronized Write signal
signal hostWrite_noCs : std_logic;
--! Read signal for initialize transfer
signal hostRead : std_logic;
--! Synchronized Read signal
signal hostRead_noCs : std_logic;
--! Address latch Enable
signal hostAle : std_logic;
--! Synchronized Address Latch Enable signal
signal hostAle_noCs : std_logic;
--!
signal hostAle_noCsEdge : std_logic;
--! Data Enable
signal hostDataEnable : std_logic;
--! Registered data Enable
signal hostDataEnable_reg : std_logic;
--! Transfer complete Acknowledgement signal
signal hostAck : std_logic;
--! Transfer complete Acknowledgement signal for registering
signal hostAck_reg : std_logic;
-- fsm
--! FSM state for Parallel Interface
type tFsm is (sIdle,
sDo,
sWait,
sDone
);
--! state signal
signal fsm : tFsm;
-- Counter will enable only after the wait request gets activated.
--! timeout counter width
constant cCountWidth : natural := 4;
--! Timeout counter
signal count : std_logic_vector(cCountWidth-1 downto 0);
--! MSB of timeout counter
alias countTc : std_logic is count(cCountWidth-1);
--! Enable counter
signal countEn : std_logic;
--! Reset counter
signal countRst : std_logic;
--! Enable ACK for Write operations
constant cCountWrAckAct : std_logic_vector(count'range) := "0000"; --0
--! Disable ACK for Write operations
constant cCountWrAckDea : std_logic_vector(count'range) := "0111";--1
--! Enable ACK for Read operations
constant cCountRdAckAct : std_logic_vector(count'range) := "0010";--1
--! Disable ACK for Read operations
constant cCountRdAckDea : std_logic_vector(count'range) := "0111";--2
begin
--! The processes describe the register, which store the unsynchronized
--! inputs!
reg : process(iClk)
begin
if rising_edge(iClk) then
if iRst = cActivated then
addressRegister <= (others => cInactivated);
byteenableRegister <= (others => cInactivated);
writeDataRegister <= (others => cInactivated);
readDataRegister <= (others => cInactivated);
hostDataEnable_reg <= cInactivated;
hostAck_reg <= cInactivated;
else
hostDataEnable_reg <= hostDataEnable;
hostAck_reg <= hostAck;
if byteenableRegClkEnable = cActivated then
byteenableRegister <= iParHostByteenable;
end if;
if addressRegClkEnable = cActivated then
if gMultiplex = 0 then
addressRegister <= iParHostAddress;
else
addressRegister <= iParHostAddressData;
end if;
end if;
if writeDataRegClkEnable = cActivated then
if gMultiplex = 0 then
writeDataRegister <= iParHostData;
else
writeDataRegister <= iParHostAddressData;
end if;
end if;
if iHostWaitrequest = cInactivated and hostRead = cActivated then
readDataRegister <= readDataRegister_next;
end if;
end if;
end if;
end process;
oHostAddress <= addressRegister(15 downto 1);
oParHostDataEnable <= hostDataEnable_reg;
oParHostAddressDataEnable <= hostDataEnable_reg;
oParHostAcknowledge <= hostAck_reg;
oParHostAddressData <= readDataRegister;
oParHostData <= readDataRegister;
countRst <= cActivated when fsm = sIdle else cInactivated;
countEn <= cActivated when fsm = sWait else cInactivated;
--! combinatoric process for ack and output enable generation
combProc : process (
count,
hostWrite,
hostRead,
fsm
)
begin
-- default assignments to avoid unwanted latches
hostAck <= cInactivated;
hostDataEnable <= cInactivated;
if fsm = sWait then
if hostRead = cActivated then
-- activate ack signal for read
if count >= cCountRdAckAct and count <= cCountRdAckDea then
hostAck <= cActivated;
end if;
elsif hostWrite = cActivated then
-- activate ack signal for write
if count >= cCountWrAckAct and count <= cCountWrAckDea then
hostAck <= cActivated;
end if;
end if;
end if;
-- Keep Data available at Bus until the read operations ends at Master
-- side
if fsm = sWait or fsm = sDone then
if hostRead = cActivated then
hostDataEnable <= cActivated;
end if;
end if;
end process;
--! Fsm to control access and timeout counter
fsmProc : process(iClk)
begin
if rising_edge(iClk) then
if iRst = cActivated then
fsm <= sIdle;
addressRegClkEnable <= cInactivated;
byteenableRegClkEnable <= cInactivated;
writeDataRegClkEnable <= cInactivated;
oHostWrite <= cInactivated;
oHostRead <= cInactivated;
count <= (others => cInactivated);
else
if countRst = cActivated then
count <= (others => cInactivated);
elsif countEn = cActivated and countTc /= cActivated then
count <= std_logic_vector(unsigned(count) + 1);
end if;
--defaults
addressRegClkEnable <= cInactivated;
byteenableRegClkEnable <= cInactivated;
writeDataRegClkEnable <= cInactivated;
oHostWrite <= cInactivated;
oHostRead <= cInactivated;
if hostAle = cActivated and gMultiplex /= 0 then
addressRegClkEnable <= cActivated;
end if;
case fsm is
--Start the operations if Read/write activated by Master
when sIdle =>
if hostRead = cActivated or hostWrite = cActivated then
fsm <= sDo;
if gMultiplex = 0 then
addressRegClkEnable <= cActivated;
end if;
byteenableRegClkEnable <= cActivated;
writeDataRegClkEnable <= hostWrite;
end if;
--Wait for the response from Avalon side
when sDo =>
oHostRead <= hostRead;
oHostWrite <= hostWrite;
if iHostWaitrequest = cInactivated then
fsm <= sWait;
oHostRead <= cInactivated;
oHostWrite <= cInactivated;
end if;
-- Generate ACK signals
when sWait =>
if countTc = cActivated then
fsm <= sDone;
end if;
--Wait for transfer to end at Parallel Master side
when sDone =>
if (hostRead = cInactivated and hostWrite = cInactivated) then
fsm <= sIdle;
else
fsm <= sDone;
end if;
end case;
end if;
end if;
end process;
-- Generate signals for DWORD data width
genHostBusDword : if gDataWidth = cDword generate
begin
oHostByteenable <= byteenableRegister;
oHostWritedata <= writeDataRegister;
readDataRegister_next <= iHostReaddata;
end generate;
-- Generate signals for WORD data width
genHostBusWord : if gDataWidth = cWord generate
begin
oHostWritedata <= writeDataRegister & writeDataRegister;
--! Create ByteEnable and Read data from WORD based signals
busCombProc : process (
byteenableRegister,
addressRegister,
iHostReaddata
)
begin
--default assignments (to avoid evil latches)
oHostByteenable <= (others => cInactivated);
readDataRegister_next <= (others => cInactivated);
-- assign byte enable to lower/upper word
for i in gDataWidth/8-1 downto 0 loop
if addressRegister(addressRegister'right) = cActivated then
-- upper word is selected
oHostByteenable(cWord/cByte+i) <= byteenableRegister(i);
else
-- lower word is selected
oHostByteenable(i) <= byteenableRegister(i);
end if;
end loop;
-- assign lower/upper word to output
for i in gDataWidth-1 downto 0 loop
if addressRegister(addressRegister'right) = cActivated then
-- upper word is selected
readDataRegister_next(i) <= iHostReaddata(cWord+i);
else
-- lower word is selected
readDataRegister_next(i) <= iHostReaddata(i);
end if;
end loop;
end process;
end generate;
-- synchronize all available control signals
--! Two synchronizer for ChipSelect
syncChipselect : entity libcommon.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iRst,
iClk => iClk,
iAsync => iParHostChipselect,
oSync => hostChipselect
);
--! Two synchronizer for Write
syncWrite : entity libcommon.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iRst,
iClk => iClk,
iAsync => iParHostWrite,
oSync => hostWrite_noCs
);
hostWrite <= hostChipselect and hostWrite_noCs;
--! Two synchronizer for Read
syncRead : entity libcommon.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iRst,
iClk => iClk,
iAsync => iParHostRead,
oSync => hostRead_noCs
);
hostRead <= hostChipselect and hostRead_noCs;
genSyncAle : if gMultiplex /= 0 generate
begin
--! Two synchronizer for ALE
syncAle : entity libcommon.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iRst,
iClk => iClk,
iAsync => iParHostAddressLatchEnable,
oSync => hostAle_noCs
);
--! Edge Detector for ALE
edgeAle : entity libcommon.edgedetector
port map (
iArst => iRst,
iClk => iClk,
iEnable => cActivated,
iData => hostAle_noCs,
oRising => hostAle_noCsEdge,
oFalling => open,
oAny => open
);
hostAle <= hostChipselect and hostAle_noCsEdge;
end generate;
end rtl;
| gpl-2.0 | 023dc43bc95fdbbc1032dd3112ef1671 | 0.556197 | 5.586442 | false | false | false | false |
rtucker/nios_codebreaker | vhdl/seven_segment.vhd | 1 | 7,600 | --**************************************************************************
--************************ VHDL Source Code ******************************
--**************************************************************************
--
-- DESIGNER NAME: Ryan Tucker <[email protected]>
--
-- LAB NAME: Library component
--
-- FILE NAME: seven_segment.vhd
--
----------------------------------------------------------------------------
--
-- DESCRIPTION
--
-- This module converts a four-bit std_logic_vector into a seven-bit
-- active-low vector for a common-anode seven-segment display, as featured
-- on the Altera DE2 board.
--
-- The seven-segment display elements are designated as HEXx_D[0..6]
-- where "x" is a specific digit (numbered 7 through 0). [0..6] translates
-- to [a..g] in the typical seven-segment display arrangement:
--
-- aaaaa
-- f b
-- f b
-- ggggg
-- e c
-- e c
-- ddddd
--
--
-- INPUTS: digit slv input hex digit (0 through F)
-- enable sl active-high enable (off = blank)
-- bank sl bank switch (0 = hex digits, 1 = special)
-- OUTPUTS: sevenseg slv seven-segment display map
--
-- Also requires constants SS_ZERO, SS_ONE, ... SS_NINE, as well
-- as SS_A, SS_B, .. SS_F for hex conditions and SS_SMALL_R for errors.
--
-- Outputs for a given input hex value and bank toggle:
-- (blank = same for both banks)
--
-- Input Hex Code
-- Bank 0 1 2 3 4 5 6 7 8 9 A B C D E F
-------------------------------------------------------------------------
-- 0 0 1 2 3 4 5 6 7 8 9 A B C d E F
-- 1 o L c
--
-------------------------------------------------------------------------------
--
-- REVISION HISTORY
--
-- _______________________________________________________________________
-- | DATE | USER | Ver | Description |
-- |==========+======+=====+================================================
-- | | | |
-- | 01/10/11 | RST | 1.0 | Created as part of Lab 5 code.
-- | | | |
-- |==========+======+=====+================================================
-- | | | |
-- | 01/16/11 | RST | 1.1 | Generalized for use in Lab 6.
-- | | | |
-- |==========+======+=====+================================================
-- | | | |
-- | 01/17/11 | RST | 1.2 | Add an enable input to blank the display.
-- | | | |
-- |==========+======+=====+================================================
-- | | | |
-- | 01/24/11 | RST | 1.3 | Add enable input to process sensitivity list
-- | | | |
-- |==========+======+=====+================================================
-- | | | |
-- | 12/08/12 | RST | 1.4 | Add 'bank' input to allow additional characters
-- | | | |
-- |==========+======+=====+================================================
-- | | | |
-- | 12/11/12 | RST | 1.5 | Correct SS_d pattern
-- | | | |
--
--**************************************************************************
--**************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY seven_segment IS
PORT (
digit : IN std_logic_vector(3 DOWNTO 0);
enable : IN std_logic;
bank : IN std_logic;
--
sevenseg : OUT std_logic_vector(6 DOWNTO 0)
);
END ENTITY seven_segment;
ARCHITECTURE behave OF seven_segment IS
-- CONSTANTS for (active-LOW) seven-segment display outputs
-- Uses "typical" (clockwise from top) a->g lettering:
-- gfedcba
CONSTANT SS_OFF : std_logic_vector(6 DOWNTO 0) := "1111111";
CONSTANT SS_ZERO : std_logic_vector(6 DOWNTO 0) := "1000000";
CONSTANT SS_SMALL_o : std_logic_vector(6 DOWNTO 0) := "0100011";
CONSTANT SS_ONE : std_logic_vector(6 DOWNTO 0) := "1111001";
CONSTANT SS_TWO : std_logic_vector(6 DOWNTO 0) := "0100100";
CONSTANT SS_THREE : std_logic_vector(6 DOWNTO 0) := "0110000";
CONSTANT SS_FOUR : std_logic_vector(6 DOWNTO 0) := "0011001";
CONSTANT SS_FIVE : std_logic_vector(6 DOWNTO 0) := "0010010";
CONSTANT SS_SIX : std_logic_vector(6 DOWNTO 0) := "0000010";
CONSTANT SS_SEVEN : std_logic_vector(6 DOWNTO 0) := "1111000";
CONSTANT SS_EIGHT : std_logic_vector(6 DOWNTO 0) := "0000000";
CONSTANT SS_NINE : std_logic_vector(6 DOWNTO 0) := "0011000";
CONSTANT SS_A : std_logic_vector(6 DOWNTO 0) := "0001000";
CONSTANT SS_b : std_logic_vector(6 DOWNTO 0) := "0000011";
CONSTANT SS_C : std_logic_vector(6 DOWNTO 0) := "1000110";
CONSTANT SS_SMALL_c : std_logic_vector(6 DOWNTO 0) := "0100111";
CONSTANT SS_d : std_logic_vector(6 DOWNTO 0) := "0100001";
CONSTANT SS_E : std_logic_vector(6 DOWNTO 0) := "0000110";
CONSTANT SS_F : std_logic_vector(6 DOWNTO 0) := "0001110";
CONSTANT SS_L : std_logic_Vector(6 DOWNTO 0) := "1000111";
CONSTANT SS_SMALL_R : std_logic_vector(6 DOWNTO 0) := "0101111";
BEGIN
display: PROCESS (bank, digit, enable) IS
BEGIN
IF (enable = '1') THEN
CASE digit IS
WHEN "0000" =>
CASE bank IS
WHEN '1' =>
sevenseg <= SS_SMALL_o;
WHEN OTHERS =>
sevenseg <= SS_ZERO;
END CASE;
WHEN "0001" =>
sevenseg <= SS_ONE;
WHEN "0010" =>
sevenseg <= SS_TWO;
WHEN "0011" =>
sevenseg <= SS_THREE;
WHEN "0100" =>
sevenseg <= SS_FOUR;
WHEN "0101" =>
sevenseg <= SS_FIVE;
WHEN "0110" =>
sevenseg <= SS_SIX;
WHEN "0111" =>
CASE bank IS
WHEN '1' =>
sevenseg <= SS_L;
WHEN OTHERS =>
sevenseg <= SS_SEVEN;
END CASE;
WHEN "1000" =>
sevenseg <= SS_EIGHT;
WHEN "1001" =>
sevenseg <= SS_NINE;
WHEN "1010" =>
sevenseg <= SS_A;
WHEN "1011" =>
sevenseg <= SS_B;
WHEN "1100" =>
CASE bank IS
WHEN '1' =>
sevenseg <= SS_SMALL_c;
WHEN OTHERS =>
sevenseg <= SS_C;
END CASE;
WHEN "1101" =>
sevenseg <= SS_D;
WHEN "1110" =>
sevenseg <= SS_E;
WHEN "1111" =>
sevenseg <= SS_F;
WHEN OTHERS =>
sevenseg <= SS_SMALL_R;
END CASE;
ELSE
sevenseg <= SS_OFF;
END IF;
END PROCESS display;
END ARCHITECTURE behave;
| mit | 1cd30011cb338db212095a7c27ddb9db | 0.374737 | 4.305949 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/openMAC_DMAmaster.vhd | 3 | 20,733 | -------------------------------------------------------------------------------
-- Entity : openMAC_DMAmaster
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity openMAC_DMAmaster is
generic(
simulate : boolean := false;
dma_highadr_g : integer := 31;
gen_tx_fifo_g : boolean := true;
gen_rx_fifo_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : boolean := true;
m_tx_burst_size_g : integer := 16;
m_rx_burst_size_g : integer := 16;
tx_fifo_word_size_g : integer := 32;
rx_fifo_word_size_g : integer := 32;
fifo_data_width_g : integer := 16;
gen_dma_observer_g : boolean := true
);
port(
dma_clk : in std_logic;
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_dout : in std_logic_vector(15 downto 0);
dma_rd_len : in std_logic_vector(11 downto 0);
m_readdata : in std_logic_vector(fifo_data_width_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
dma_din : out std_logic_vector(15 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_writedata : out std_logic_vector(fifo_data_width_g-1 downto 0)
);
end openMAC_DMAmaster;
architecture strct of openMAC_DMAmaster is
---- Component declarations -----
component dma_handler
generic(
dma_highadr_g : integer := 31;
gen_dma_observer_g : boolean := true;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_clk : in std_logic;
dma_rd_len : in std_logic_vector(11 downto 0);
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_wr_clk : in std_logic;
rx_wr_empty : in std_logic;
rx_wr_full : in std_logic;
rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_rd_clk : in std_logic;
tx_rd_empty : in std_logic;
tx_rd_full : in std_logic;
tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_addr_out : out std_logic_vector(dma_highadr_g downto 1);
dma_new_addr_rd : out std_logic;
dma_new_addr_wr : out std_logic;
dma_new_len : out std_logic;
dma_rd_err : out std_logic;
dma_rd_len_out : out std_logic_vector(11 downto 0);
dma_wr_err : out std_logic;
rx_aclr : out std_logic;
rx_wr_req : out std_logic;
tx_rd_req : out std_logic
);
end component;
component master_handler
generic(
dma_highadr_g : integer := 31;
fifo_data_width_g : integer := 16;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burst_wr_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr_in : in std_logic_vector(dma_highadr_g downto 1);
dma_len_rd : in std_logic_vector(11 downto 0);
dma_new_addr_rd : in std_logic;
dma_new_addr_wr : in std_logic;
dma_new_len_rd : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_rd_clk : in std_logic;
rx_rd_empty : in std_logic;
rx_rd_full : in std_logic;
rx_rd_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_wr_clk : in std_logic;
tx_wr_empty : in std_logic;
tx_wr_full : in std_logic;
tx_wr_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_read : out std_logic;
m_write : out std_logic;
rx_rd_req : out std_logic;
tx_aclr : out std_logic;
tx_wr_req : out std_logic
);
end component;
---- Architecture declarations -----
--constants
constant tx_fifo_word_size_c : natural := natural(tx_fifo_word_size_g);
constant tx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(tx_fifo_word_size_c))));
constant rx_fifo_word_size_c : natural := natural(rx_fifo_word_size_g);
constant rx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(rx_fifo_word_size_c))));
---- Signal declarations used on the diagram ----
signal dma_new_addr_rd : std_logic;
signal dma_new_addr_wr : std_logic;
signal dma_new_rd_len : std_logic;
signal m_dma_new_addr_rd : std_logic;
signal m_dma_new_addr_wr : std_logic;
signal m_dma_new_rd_len : std_logic;
signal m_mac_rx_off : std_logic;
signal m_mac_tx_off : std_logic;
signal rx_aclr : std_logic;
signal rx_rd_clk : std_logic;
signal rx_rd_empty : std_logic;
signal rx_rd_full : std_logic;
signal rx_rd_req : std_logic;
signal rx_wr_clk : std_logic;
signal rx_wr_empty : std_logic;
signal rx_wr_full : std_logic;
signal rx_wr_req : std_logic;
signal rx_wr_req_s : std_logic;
signal tx_aclr : std_logic;
signal tx_rd_clk : std_logic;
signal tx_rd_empty : std_logic;
signal tx_rd_empty_s : std_logic;
signal tx_rd_empty_s_l : std_logic;
signal tx_rd_full : std_logic;
signal tx_rd_req : std_logic;
signal tx_rd_req_s : std_logic;
signal tx_rd_sel_word : std_logic;
signal tx_wr_clk : std_logic;
signal tx_wr_empty : std_logic;
signal tx_wr_full : std_logic;
signal tx_wr_req : std_logic;
signal dma_addr_trans : std_logic_vector (dma_highadr_g downto 1);
signal dma_rd_len_trans : std_logic_vector (11 downto 0);
signal rd_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal rx_rd_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal rx_wr_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal tx_rd_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal tx_wr_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal wr_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal wr_data_s : std_logic_vector (fifo_data_width_g/2-1 downto 0);
begin
---- Component instantiations ----
THE_DMA_HANDLER : dma_handler
generic map (
dma_highadr_g => dma_highadr_g,
gen_dma_observer_g => gen_dma_observer_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_ack_rd => dma_ack_rd,
dma_ack_wr => dma_ack_wr,
dma_addr => dma_addr( dma_highadr_g downto 1 ),
dma_addr_out => dma_addr_trans( dma_highadr_g downto 1 ),
dma_clk => dma_clk,
dma_new_addr_rd => dma_new_addr_rd,
dma_new_addr_wr => dma_new_addr_wr,
dma_new_len => dma_new_rd_len,
dma_rd_err => dma_rd_err,
dma_rd_len => dma_rd_len,
dma_rd_len_out => dma_rd_len_trans,
dma_req_overflow => dma_req_overflow,
dma_req_rd => dma_req_rd,
dma_req_wr => dma_req_wr,
dma_wr_err => dma_wr_err,
mac_rx_off => mac_rx_off,
mac_tx_off => mac_tx_off,
rst => rst,
rx_aclr => rx_aclr,
rx_wr_clk => rx_wr_clk,
rx_wr_empty => rx_wr_empty,
rx_wr_full => rx_wr_full,
rx_wr_req => rx_wr_req,
rx_wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_rd_clk => tx_rd_clk,
tx_rd_empty => tx_rd_empty,
tx_rd_full => tx_rd_full,
tx_rd_req => tx_rd_req,
tx_rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
THE_MASTER_HANDLER : master_handler
generic map (
dma_highadr_g => dma_highadr_g,
fifo_data_width_g => fifo_data_width_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
m_burst_wr_const_g => m_burstcount_const_g,
m_burstcount_width_g => m_burstcount_width_g,
m_rx_burst_size_g => m_rx_burst_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_addr_in => dma_addr_trans( dma_highadr_g downto 1 ),
dma_len_rd => dma_rd_len_trans,
dma_new_addr_rd => m_dma_new_addr_rd,
dma_new_addr_wr => m_dma_new_addr_wr,
dma_new_len_rd => m_dma_new_rd_len,
m_address => m_address( dma_highadr_g downto 0 ),
m_burstcount => m_burstcount( m_burstcount_width_g-1 downto 0 ),
m_burstcounter => m_burstcounter( m_burstcount_width_g-1 downto 0 ),
m_byteenable => m_byteenable( fifo_data_width_g/8-1 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
mac_rx_off => m_mac_rx_off,
mac_tx_off => m_mac_tx_off,
rst => rst,
rx_rd_clk => rx_rd_clk,
rx_rd_empty => rx_rd_empty,
rx_rd_full => rx_rd_full,
rx_rd_req => rx_rd_req,
rx_rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_aclr => tx_aclr,
tx_wr_clk => tx_wr_clk,
tx_wr_empty => tx_wr_empty,
tx_wr_full => tx_wr_full,
tx_wr_req => tx_wr_req,
tx_wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
rx_rd_clk <= m_clk;
tx_rd_clk <= dma_clk;
rx_wr_clk <= dma_clk;
tx_wr_clk <= m_clk;
sync1 : entity libcommon.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iSrc_rst => rst,
iSrc_clk => dma_clk,
iSrc_data => mac_tx_off,
iDst_rst => rst,
iDst_clk => m_clk,
oDst_data => m_mac_tx_off
);
sync2 : entity libcommon.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iSrc_rst => rst,
iSrc_clk => dma_clk,
iSrc_data => mac_rx_off,
iDst_rst => rst,
iDst_clk => m_clk,
oDst_data => m_mac_rx_off
);
---- Generate statements ----
gen16bitFifo : if fifo_data_width_g = 16 generate
begin
txFifoGen : if gen_tx_fifo_g generate
begin
TX_FIFO_16 : entity work.asyncFifo
generic map (
gDataWidth => fifo_data_width_g,
gWordSize => tx_fifo_word_size_c,
gSyncStages => 2,
gMemRes => "ON"
)
port map(
iAclr => tx_aclr,
iWrClk => tx_wr_clk,
iWrReq => tx_wr_req,
iWrData => m_readdata,
oWrEmpty => tx_wr_empty,
oWrFull => tx_wr_full,
oWrUsedw => tx_wr_usedw,
iRdClk => tx_rd_clk,
iRdReq => tx_rd_req,
oRdData => rd_data,
oRdEmpty => tx_rd_empty_s,
oRdFull => tx_rd_full,
oRdUsedw => tx_rd_usedw
);
tx_rd_empty_proc :
process(tx_aclr, tx_rd_clk)
begin
if tx_aclr = '1' then
tx_rd_empty_s_l <= '0';
elsif rising_edge(tx_rd_clk) then
if mac_tx_off = '1' then
tx_rd_empty_s_l <= '0';
elsif tx_rd_req = '1' then
if tx_rd_empty_s = '0' then
tx_rd_empty_s_l <= '1';
else
tx_rd_empty_s_l <= '0';
end if;
end if;
end if;
end process;
tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0';
end generate txFifoGen;
rxFifoGen : if gen_rx_fifo_g generate
begin
RX_FIFO_16 : entity work.asyncFifo
generic map (
gDataWidth => fifo_data_width_g,
gWordSize => rx_fifo_word_size_c,
gSyncStages => 2,
gMemRes => "ON"
)
port map(
iAclr => rx_aclr,
iWrClk => rx_wr_clk,
iWrReq => rx_wr_req,
iWrData => wr_data,
oWrEmpty => rx_wr_empty,
oWrFull => rx_wr_full,
oWrUsedw => rx_wr_usedw,
iRdClk => rx_rd_clk,
iRdReq => rx_rd_req,
oRdData => m_writedata,
oRdEmpty => rx_rd_empty,
oRdFull => rx_rd_full,
oRdUsedw => rx_rd_usedw
);
end generate rxFifoGen;
wr_data <= dma_dout;
dma_din <= rd_data;
end generate gen16bitFifo;
genRxAddrSync : if gen_rx_fifo_g generate
begin
sync4 : entity libcommon.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iSrc_rst => rst,
iSrc_clk => dma_clk,
iSrc_data => dma_new_addr_wr,
iDst_rst => rst,
iDst_clk => m_clk,
oDst_data => m_dma_new_addr_wr
);
end generate genRxAddrSync;
genTxAddrSync : if gen_tx_fifo_g generate
begin
sync5 : entity libcommon.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map(
iSrc_rst => rst,
iSrc_clk => dma_clk,
iSrc_data => dma_new_addr_rd,
iDst_rst => rst,
iDst_clk => m_clk,
oDst_data => m_dma_new_addr_rd
);
sync6 : entity libcommon.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map(
iSrc_rst => rst,
iSrc_clk => dma_clk,
iSrc_data => dma_new_rd_len,
iDst_rst => rst,
iDst_clk => m_clk,
oDst_data => m_dma_new_rd_len
);
end generate genTxAddrSync;
gen32bitFifo : if fifo_data_width_g = 32 generate
begin
txFifoGen32 : if gen_tx_fifo_g generate
begin
TX_FIFO_32 : entity work.asyncFifo
generic map (
gDataWidth => fifo_data_width_g,
gWordSize => tx_fifo_word_size_c,
gSyncStages => 2,
gMemRes => "ON"
)
port map(
iAclr => tx_aclr,
iWrClk => tx_wr_clk,
iWrReq => tx_wr_req,
iWrData => m_readdata,
oWrEmpty => tx_wr_empty,
oWrFull => tx_wr_full,
oWrUsedw => tx_wr_usedw,
iRdClk => tx_rd_clk,
iRdReq => tx_rd_req_s,
oRdData => rd_data,
oRdEmpty => tx_rd_empty_s,
oRdFull => tx_rd_full,
oRdUsedw => tx_rd_usedw
);
tx_rd_proc :
process (tx_rd_clk, rst)
begin
if rst = '1' then
tx_rd_sel_word <= '0';
tx_rd_empty_s_l <= '0';
elsif rising_edge(tx_rd_clk) then
if mac_tx_off = '1' then
tx_rd_sel_word <= '0';
tx_rd_empty_s_l <= '0';
elsif tx_rd_req = '1' then
if tx_rd_sel_word = '0' then
tx_rd_sel_word <= '1';
else
tx_rd_sel_word <= '0';
--workaround...
if tx_rd_empty_s = '0' then
tx_rd_empty_s_l <= '1';
else
tx_rd_empty_s_l <= '0';
end if;
end if;
end if;
end if;
end process;
tx_rd_req_s <= tx_rd_req when tx_rd_sel_word = '0' else '0';
tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0';
dma_din <= rd_data(15 downto 0) when tx_rd_sel_word = '1' else
rd_data(31 downto 16);
end generate txFifoGen32;
rxFifoGen32 : if gen_rx_fifo_g generate
begin
RX_FIFO_32 : entity work.asyncFifo
generic map (
gDataWidth => fifo_data_width_g,
gWordSize => rx_fifo_word_size_c,
gSyncStages => rx_fifo_word_size_log2_c,
gMemRes => "ON"
)
port map(
iAclr => rx_aclr,
iWrClk => rx_wr_clk,
iWrReq => rx_wr_req_s,
iWrData => wr_data,
oWrEmpty => rx_wr_empty,
oWrFull => rx_wr_full,
oWrUsedw => rx_wr_usedw,
iRdClk => rx_rd_clk,
iRdReq => rx_rd_req,
oRdData => m_writedata,
oRdEmpty => rx_rd_empty,
oRdFull => rx_rd_full,
oRdUsedw => rx_rd_usedw
);
rx_wr_proc :
process (rx_wr_clk, rst)
variable toggle : std_logic;
begin
if rst = '1' then
wr_data_s <= (others => '0');
toggle := '0';
rx_wr_req_s <= '0';
elsif rising_edge(rx_wr_clk) then
rx_wr_req_s <= '0';
if mac_rx_off = '1' then
if toggle = '1' then
rx_wr_req_s <= '1';
end if;
toggle := '0';
elsif rx_wr_req = '1' then
if toggle = '0' then
--capture data
wr_data_s <= dma_dout;
toggle := '1';
else
rx_wr_req_s <= '1';
toggle := '0';
end if;
end if;
end if;
end process;
wr_data <= dma_dout & wr_data_s;
end generate rxFifoGen32;
end generate gen32bitFifo;
end strct;
| gpl-2.0 | 8cde7b46a340ecf61bb5c7bcdc468f32 | 0.543819 | 3.24765 | false | false | false | false |
DreamIP/GPStudio | support/process/debayer33/debayer33_slave.vhd | 1 | 2,305 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity debayer33_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
bayer_code : out std_logic_vector(1 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end debayer33_slave;
architecture rtl of debayer33_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant BAYER_CODE_REG_REG_ADDR : natural := 1;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal bayer_code_reg : std_logic_vector (1 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
bayer_code_reg <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
status_reg_enable_bit_reg <= datawr_i(0);
when std_logic_vector(to_unsigned(BAYER_CODE_REG_REG_ADDR, 4))=>
bayer_code_reg <= datawr_i(1) & datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
datard_o <= (0 => status_reg_enable_bit_reg, others => '0');
when std_logic_vector(to_unsigned(BAYER_CODE_REG_REG_ADDR, 4))=>
datard_o <= (1 => bayer_code_reg(1), 0 => bayer_code_reg(0), others => '0');
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
bayer_code <= bayer_code_reg;
end rtl;
| gpl-3.0 | 1b151d7b8bcd01d4bedbdca22a0e0e82 | 0.571367 | 2.92142 | false | false | false | false |
freecores/wrimm | WrimmPackage.vhd | 1 | 5,073 | --Propery of Tecphos Inc. See License.txt for license details
--Latest version of all project files available at http://opencores.org/project,wrimm
--See WrimmManual.pdf for the Wishbone Datasheet and implementation details.
--See wrimm subversion project for version history
library ieee;
use ieee.std_logic_1164.all;
package WrimmPackage is
constant WbAddrBits : Integer := 4;
constant WbDataBits : Integer := 8;
subtype WbAddrType is std_logic_vector(0 to WbAddrBits-1);
subtype WbDataType is std_logic_vector(0 to WbDataBits-1);
type WbMasterOutType is record
Strobe : std_logic; --Required
WrEn : std_logic;
Addr : WbAddrType;
Data : WbDataType;
--DataTag : std_logic_vector(0 to 1); --Write,Set,Clear,Toggle
Cyc : std_logic; --Required
--CycType : std_logic_vector(0 to 2); --For Burst Cycles
end record WbMasterOutType;
type WbSlaveOutType is record
Ack : std_logic; --Required
Err : std_logic;
Rty : std_logic;
Data : WbDataType;
end record WbSlaveOutType;
--=============================================================================
-------------------------------------------------------------------------------
-- Master Interfaces
-------------------------------------------------------------------------------
type WbMasterType is (
Q,
P);
type WbMasterOutArray is array (WbMasterType) of WbMasterOutType;
type WbSlaveOutArray is array (WbMasterType) of WbSlaveOutType;
type WbMasterGrantType is Array (WbMasterType'left to WbMasterType'right) of std_logic;
--=============================================================================
-------------------------------------------------------------------------------
-- Status Registers (Report internal results)
-------------------------------------------------------------------------------
type StatusFieldParams is record
BitWidth : integer;
MSBLoc : integer;
Address : WbAddrType;
end record StatusFieldParams;
type StatusFieldType is (
StatusA,
StatusB,
StatusC);
type StatusArrayType is Array (StatusFieldType'left to StatusFieldType'right) of WbDataType;
type StatusArrayBitType is Array (StatusFieldType'left to StatusFieldType'right) of std_logic;
type StatusFieldDefType is Array (StatusFieldType'left to StatusFieldType'right) of StatusFieldParams;
constant StatusParams : StatusFieldDefType :=(
StatusA => (BitWidth => 8, MSBLoc => 0, Address => x"0"),
StatusB => (BitWidth => 8, MSBLoc => 0, Address => x"1"),
StatusC => (BitWidth => 8, MSBLoc => 0, Address => x"2"));
--=============================================================================
-------------------------------------------------------------------------------
-- Setting Registers
-------------------------------------------------------------------------------
type SettingFieldParams is record
BitWidth : integer;
MSBLoc : integer;
Address : WbAddrType;
Default : WbDataType;
end record SettingFieldParams;
type SettingFieldType is (
SettingX,
SettingY,
SettingZ);
type SettingArrayType is Array (SettingFieldType'Left to SettingFieldType'Right) of WbDataType;
type SettingArrayBitType is Array (SettingFieldType'Left to SettingFieldType'Right) of std_logic;
type SettingFieldDefType is Array (SettingFieldType'Left to SettingFieldType'Right) of SettingFieldParams;
constant SettingParams : SettingFieldDefType :=(
SettingX => (BitWidth => 8, MSBLoc => 0, Address => x"6", Default => x"00"),
SettingY => (BitWidth => 8, MSBLoc => 0, Address => x"7", Default => x"00"),
SettingZ => (BitWidth => 8, MSBLoc => 0, Address => x"8", Default => x"00"));
--=============================================================================
-------------------------------------------------------------------------------
-- Trigger Registers (Report internal results)
-------------------------------------------------------------------------------
type TriggerFieldParams is record
BitLoc : integer;
Address : WbAddrType;
end record TriggerFieldParams;
type TriggerFieldType is (
TriggerR,
TriggerS,
TriggerT);
type TriggerArrayType is Array (TriggerFieldType'Left to TriggerFieldType'Right) of std_logic;
type TriggerFieldDefType is Array (TriggerFieldType'Left to TriggerFieldType'Right) of TriggerFieldParams;
constant TriggerParams : TriggerFieldDefType :=(
TriggerR => (BitLoc => 7, Address => x"A"),
TriggerS => (BitLoc => 7, Address => x"B"),
TriggerT => (BitLoc => 7, Address => x"C"));
end package WrimmPackage;
--package body WishBonePackage is
--
--
--
--end package body WishBonePackage;
| bsd-3-clause | b80c561c73451ade1dc8260c4d1e9eda | 0.525133 | 4.599275 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/RGMII_MAC/eth_ddr_out.vhd | 1 | 4,090 | -- megafunction wizard: %ALTDDIO_OUT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTDDIO_OUT
-- ============================================================
-- File Name: eth_ddr_out.vhd
-- Megafunction Name(s):
-- ALTDDIO_OUT
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.0 Build 178 05/31/2012 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY eth_ddr_out IS
PORT
(
datain_h : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
outclock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END eth_ddr_out;
ARCHITECTURE SYN OF eth_ddr_out IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
BEGIN
dataout <= sub_wire0(4 DOWNTO 0);
ALTDDIO_OUT_component : ALTDDIO_OUT
GENERIC MAP (
extend_oe_disable => "OFF",
intended_device_family => "Cyclone IV E",
invert_output => "OFF",
lpm_hint => "UNUSED",
lpm_type => "altddio_out",
oe_reg => "UNREGISTERED",
power_up_high => "OFF",
width => 5
)
PORT MAP (
datain_h => datain_h,
datain_l => datain_l,
outclock => outclock,
dataout => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
-- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH NUMERIC "5"
-- Retrieval info: USED_PORT: datain_h 0 0 5 0 INPUT NODEFVAL "datain_h[4..0]"
-- Retrieval info: CONNECT: @datain_h 0 0 5 0 datain_h 0 0 5 0
-- Retrieval info: USED_PORT: datain_l 0 0 5 0 INPUT NODEFVAL "datain_l[4..0]"
-- Retrieval info: CONNECT: @datain_l 0 0 5 0 datain_l 0 0 5 0
-- Retrieval info: USED_PORT: dataout 0 0 5 0 OUTPUT NODEFVAL "dataout[4..0]"
-- Retrieval info: CONNECT: dataout 0 0 5 0 @dataout 0 0 5 0
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_out.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_out.qip TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_out.bsf FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_out_inst.vhd FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_out.inc FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_out.cmp FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_out.ppf TRUE FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | 557369e78adb8117652bb8969853ba02 | 0.651589 | 3.655049 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/boards/altera-c5soc/common/ipcore/pll/pll.vhd | 5 | 17,978 | -- megafunction wizard: %Altera PLL v14.0%
-- GENERATION: XML
-- pll.vhd
-- Generated using ACDS version 14.0 200 at 2015.05.15.17:45:52
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pll is
port (
refclk : in std_logic := '0'; -- refclk.clk
rst : in std_logic := '0'; -- reset.reset
outclk_0 : out std_logic; -- outclk0.clk
outclk_1 : out std_logic; -- outclk1.clk
locked : out std_logic -- locked.export
);
end entity pll;
architecture rtl of pll is
component pll_0002 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
outclk_1 : out std_logic; -- clk
locked : out std_logic -- export
);
end component pll_0002;
begin
pll_inst : component pll_0002
port map (
refclk => refclk, -- refclk.clk
rst => rst, -- reset.reset
outclk_0 => outclk_0, -- outclk0.clk
outclk_1 => outclk_1, -- outclk1.clk
locked => locked -- locked.export
);
end architecture rtl; -- of pll
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2015 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_pll" version="14.0" >
-- Retrieval info: <generic name="debug_print_output" value="false" />
-- Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
-- Retrieval info: <generic name="device_family" value="Cyclone V" />
-- Retrieval info: <generic name="device" value="Unknown" />
-- Retrieval info: <generic name="gui_device_speed_grade" value="1" />
-- Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
-- Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
-- Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
-- Retrieval info: <generic name="gui_operation_mode" value="direct" />
-- Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
-- Retrieval info: <generic name="gui_fractional_cout" value="32" />
-- Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
-- Retrieval info: <generic name="gui_use_locked" value="true" />
-- Retrieval info: <generic name="gui_en_adv_params" value="false" />
-- Retrieval info: <generic name="gui_number_of_clocks" value="2" />
-- Retrieval info: <generic name="gui_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_divide_factor_n" value="1" />
-- Retrieval info: <generic name="gui_cascade_counter0" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency0" value="50.0" />
-- Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units0" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle0" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter1" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units1" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle1" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter2" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units2" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle2" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter3" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units3" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle3" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter4" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units4" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle4" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter5" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units5" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle5" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter6" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units6" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle6" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter7" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units7" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle7" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter8" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units8" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle8" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter9" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units9" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle9" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter10" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units10" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle10" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter11" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units11" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle11" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter12" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units12" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle12" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter13" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units13" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle13" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter14" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units14" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle14" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter15" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units15" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle15" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter16" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units16" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle16" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter17" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units17" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle17" value="50" />
-- Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
-- Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
-- Retrieval info: <generic name="gui_en_reconf" value="false" />
-- Retrieval info: <generic name="gui_en_dps_ports" value="false" />
-- Retrieval info: <generic name="gui_en_phout_ports" value="false" />
-- Retrieval info: <generic name="gui_phout_division" value="1" />
-- Retrieval info: <generic name="gui_en_lvds_ports" value="false" />
-- Retrieval info: <generic name="gui_mif_generate" value="false" />
-- Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
-- Retrieval info: <generic name="gui_dps_cntr" value="C0" />
-- Retrieval info: <generic name="gui_dps_num" value="1" />
-- Retrieval info: <generic name="gui_dps_dir" value="Positive" />
-- Retrieval info: <generic name="gui_refclk_switch" value="false" />
-- Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
-- Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
-- Retrieval info: <generic name="gui_switchover_delay" value="0" />
-- Retrieval info: <generic name="gui_active_clk" value="false" />
-- Retrieval info: <generic name="gui_clk_bad" value="false" />
-- Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
-- Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
-- Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
-- Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
-- Retrieval info: <generic name="AUTO_REFCLK_CLOCK_RATE" value="-1" />
-- Retrieval info: </instance>
-- IPFS_FILES : pll.vho
-- RELATED_FILES: pll.vhd, pll_0002.v
| gpl-2.0 | 216a15425affa51c32f2c9bea285f406 | 0.675437 | 3.240447 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/dma_handler.vhd | 3 | 8,248 | -------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dma_handler is
generic(
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
dma_highadr_g : integer := 31;
tx_fifo_word_size_log2_g : natural := 5;
rx_fifo_word_size_log2_g : natural := 5;
gen_dma_observer_g : boolean := true
);
port(
dma_clk : in std_logic;
rst : in std_logic;
mac_tx_off : in std_logic;
mac_rx_off : in std_logic;
dma_req_wr : in std_logic;
dma_req_rd : in std_logic;
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_ack_wr : out std_logic;
dma_ack_rd : out std_logic;
dma_rd_len : in std_logic_vector(11 downto 0);
tx_rd_clk : in std_logic;
tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
tx_rd_empty : in std_logic;
tx_rd_full : in std_logic;
tx_rd_req : out std_logic;
rx_wr_full : in std_logic;
rx_wr_empty : in std_logic;
rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
rx_wr_req : out std_logic;
rx_aclr : out std_logic;
rx_wr_clk : in std_logic;
dma_addr_out : out std_logic_vector(dma_highadr_g downto 1);
dma_rd_len_out : out std_logic_vector(11 downto 0);
dma_new_addr_wr : out std_logic;
dma_new_addr_rd : out std_logic;
dma_new_len : out std_logic;
dma_req_overflow : in std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic
);
end dma_handler;
architecture dma_handler of dma_handler is
--clock signal
signal clk : std_logic;
--fsm
type transfer_t is (idle, first, run);
signal tx_fsm, tx_fsm_next, rx_fsm, rx_fsm_next : transfer_t := idle;
--dma signals
signal dma_ack_rd_s, dma_ack_wr_s : std_logic;
--dma observer
signal observ_rd_err, observ_wr_err : std_logic;
signal observ_rd_err_next, observ_wr_err_next : std_logic;
begin
--dma_clk, tx_rd_clk and rx_wr_clk are the same!
clk <= dma_clk; --to ease typing
rx_aclr <= rst;
process(clk, rst)
begin
if rst = '1' then
if gen_tx_fifo_g then
tx_fsm <= idle;
if gen_dma_observer_g then
observ_rd_err <= '0';
end if;
end if;
if gen_rx_fifo_g then
rx_fsm <= idle;
if gen_dma_observer_g then
observ_wr_err <= '0';
end if;
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
tx_fsm <= tx_fsm_next;
if gen_dma_observer_g then
observ_rd_err <= observ_rd_err_next;
end if;
end if;
if gen_rx_fifo_g then
rx_fsm <= rx_fsm_next;
if gen_dma_observer_g then
observ_wr_err <= observ_wr_err_next;
end if;
end if;
end if;
end process;
dma_rd_len_out <= dma_rd_len; --register in openMAC.vhd!
tx_fsm_next <= idle when gen_tx_fifo_g = false else --hang here if generic disables tx handling
first when tx_fsm = idle and dma_req_rd = '1' else
run when tx_fsm = first and dma_ack_rd_s = '1' else
idle when mac_tx_off = '1' else
tx_fsm;
rx_fsm_next <= idle when gen_rx_fifo_g = false else --hang here if generic disables rx handling
first when rx_fsm = idle and dma_req_wr = '1' else
run when rx_fsm = first else
idle when mac_rx_off = '1' else
rx_fsm;
genDmaObserver : if gen_dma_observer_g generate
begin
observ_rd_err_next <= --monoflop (deassertion with rst only)
'0' when gen_tx_fifo_g = false else
'1' when dma_req_rd = '1' and dma_ack_rd_s = '0' and dma_req_overflow = '1' else
observ_rd_err;
observ_wr_err_next <= --monoflop (deassertion with rst only)
'0' when gen_rx_fifo_g = false else
'1' when dma_req_wr = '1' and dma_ack_wr_s = '0' and dma_req_overflow = '1' else
observ_wr_err;
end generate;
dma_rd_err <= observ_rd_err;
dma_wr_err <= observ_wr_err;
--acknowledge dma request (regular or overflow)
dma_ack_rd <= dma_req_rd and (dma_ack_rd_s or dma_req_overflow);
dma_ack_wr <= dma_req_wr and (dma_ack_wr_s or dma_req_overflow);
dma_new_addr_wr <= '1' when rx_fsm = first else '0';
dma_new_addr_rd <= '1' when tx_fsm = first else '0';
dma_new_len <= '1' when tx_fsm = first else '0';
process(clk, rst)
begin
if rst = '1' then
dma_addr_out <= (others => '0');
if gen_tx_fifo_g then
tx_rd_req <= '0';
dma_ack_rd_s <= '0';
end if;
if gen_rx_fifo_g then
rx_wr_req <= '0';
dma_ack_wr_s <= '0';
end if;
elsif clk = '1' and clk'event then
--if the very first address is available, store it over the whole transfer
if tx_fsm = first or rx_fsm = first then
dma_addr_out <= dma_addr;
end if;
if gen_tx_fifo_g then
tx_rd_req <= '0';
dma_ack_rd_s <= '0';
--dma request, TX fifo is not empty and not yet ack'd
if dma_req_rd = '1' and tx_rd_empty = '0' and dma_ack_rd_s = '0' then
tx_rd_req <= '1'; --read from TX fifo
dma_ack_rd_s <= '1'; --ack the read request
end if;
end if;
if gen_rx_fifo_g then
rx_wr_req <= '0';
dma_ack_wr_s <= '0';
--dma request, RX fifo is not full and not yet ack'd
if dma_req_wr = '1' and rx_wr_full = '0' and dma_ack_wr_s = '0' then
rx_wr_req <= '1'; --write to RX fifo
dma_ack_wr_s <= '1'; --ack the read request
end if;
end if;
end if;
end process;
end dma_handler;
| gpl-2.0 | 9e0e9ef655f4e33bb5f53b84a9e7d4b7 | 0.540495 | 3.62072 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/xilinx/memory/src/dpRamOpenmac-rtl-a.vhd | 3 | 5,801 | --! @file dpRam-bhv-a.vhd
--
--! @brief Dual Port Ram Register Transfer Level Architecture
--
--! @details This is the DPRAM intended for synthesis on Xilinx Spartan 6 only.
--! It is specific for the openMAC descriptor DPRAM which require
--! simultaneous write/read from the same address.
--! Timing as follows [clk-cycles]: write=0 / read=1
--! @note Note that only port B reads valid data reliably!
--
-------------------------------------------------------------------------------
-- Architecture : rtl
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2015
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
architecture rtl of dpRamOpenmac is
--! Width of a byte
constant cByte : natural := 8;
--! Address width (used to generate size depending on address width)
constant cAddrWidth : natural := iAddress_A'length;
--! RAM size
constant cRamSize : natural := 2**cAddrWidth;
--! Type for data port
subtype tDataPort is std_logic_vector(gWordWidth-1 downto 0);
--! RAM type with given size
type tRam is array (cRamSize-1 downto 0) of tDataPort;
--! Shared variable to model and synthesize a DPR
shared variable vDpram : tRam := (others => (others => cInactivated));
--! Port A readport
signal readdataA : tDataPort;
--! Port B readport
signal readdataB : tDataPort;
begin
assert (gInitFile = "UNUSED")
report "Memory initialization is not supported in this architecture!"
severity warning;
-- assign readdata to ports
oReaddata_A <= readdataA;
oReaddata_B <= readdataB;
--! This process describes port A of the DPRAM. The write process considers
--! iWriteEnable_A and iByteenable_A. The read process is done with every
--! rising iClk_A edge.
PORTA : process(iClk_A)
begin
if rising_edge(iClk_A) then
if iEnable_A = cActivated then
---------------------------------------------------------------
-- Set write port A to READ_FIRST to enable reliable read at
-- port B!
-- read word from DPRAM
readdataA <= vDpram(to_integer(unsigned(iAddress_A)));
---------------------------------------------------------------
for i in iByteenable_A'range loop
if ((iByteenable_A(i) = cActivated) and (iWriteEnable_A = cActivated)) then
-- write byte to DPRAM
vDpram(to_integer(unsigned(iAddress_A)))(
(i+1)*cByte-1 downto i*cByte
) := iWritedata_A(
(i+1)*cByte-1 downto i*cByte
);
end if; --byteenable
end loop;
end if; --enable
end if;
end process PORTA;
--! This process describes port B of the DPRAM. The write process considers
--! iWriteEnable_B and iByteenable_B. The read process is done with every
--! rising iClk_B edge.
PORTB : process(iClk_B)
begin
if rising_edge(iClk_B) then
if iEnable_B = cActivated then
for i in iByteenable_B'range loop
if ((iByteenable_B(i) = cActivated) and (iWriteEnable_B = cActivated)) then
-- write byte to DPRAM
vDpram(to_integer(unsigned(iAddress_B)))(
(i+1)*cByte-1 downto i*cByte
) := iWritedata_B(
(i+1)*cByte-1 downto i*cByte
);
end if; --byteenable
end loop;
-- read word from DPRAM
readdataB <= vDpram(to_integer(unsigned(iAddress_B)));
end if; --enable
end if;
end process PORTB;
end architecture rtl;
| gpl-2.0 | e4309bc61e271dcb31e2b0808cd181f2 | 0.580245 | 4.911939 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/memory/src/dpRamSplx-e.vhd | 3 | 3,818 | -------------------------------------------------------------------------------
--! @file dpRamSplx-e.vhd
--
--! @brief Simplex Dual Port Ram Entity
--
--! @details This is the Simplex DPRAM entity.
--! The DPRAM has one write and one read port only.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity dpRamSplx is
generic (
--! Word width port A [bit]
gWordWidthA : natural := 16;
--! Byteenable width port A [bit]
gByteenableWidthA : natural := 2;
--! Number of words (reference is port A)
gNumberOfWordsA : natural := 1024;
--! Word width port B [bit]
gWordWidthB : natural := 32;
--! Number of words (reference is port B)
gNumberOfWordsB : natural := 512;
--! Initialization file
gInitFile : string := "UNUSED"
);
port (
-- PORT A
--! Clock of port A
iClk_A : in std_logic;
--! Enable of port A
iEnable_A : in std_logic;
--! Write enable of port A
iWriteEnable_A : in std_logic;
--! Address of port A
iAddress_A : in std_logic_vector(logDualis(gNumberOfWordsA)-1 downto 0);
--! Byteenable of port A
iByteenable_A : in std_logic_vector(gByteenableWidthA-1 downto 0);
--! Writedata of port A
iWritedata_A : in std_logic_vector(gWordWidthA-1 downto 0);
-- PORT B
--! Clock of port B
iClk_B : in std_logic;
--! Enable of port B
iEnable_B : in std_logic;
--! Address of port B
iAddress_B : in std_logic_vector(logDualis(gNumberOfWordsB)-1 downto 0);
--! Readdata of port B
oReaddata_B : out std_logic_vector(gWordWidthB-1 downto 0)
);
end dpRamSplx;
| gpl-2.0 | 0fbf0574563153af47d81503a6b68f76 | 0.600576 | 4.561529 | false | false | false | false |
Reiuiji/ECE368-Lab | Lab 1/MealyFSM/mealy.vhd | 1 | 1,954 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2016
-- Module Name: MEALY
-- Project Name: MEALY MACHINE
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Mealy
-- Finite State Machine (FSM)
-- Mealy: The Output is a function of a present
-- state and inputs
---------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mealy IS -- Mealy machine
PORT ( CLK: in BIT;
RST: in BIT;
X: in BIT;
Z: out BIT);
END mealy;
ARCHITECTURE Behavior OF mealy IS
TYPE STATE_TYPE IS (S0, S1, S2);
SIGNAL CURRENT_STATE, NEXT_STATE: STATE_TYPE;
BEGIN
-- Process to hold combinational logic.
COMBIN: PROCESS(CURRENT_STATE, X)
BEGIN
CASE CURRENT_STATE IS
WHEN S0 =>
IF X = '0' THEN
Z <= '0';
NEXT_STATE <= S0;
ELSE
Z <= '0';
NEXT_STATE <= S1;
END IF;
WHEN S1 =>
IF X = '0' THEN
Z <= '1';
NEXT_STATE <= S0;
ELSE
Z <= '0';
NEXT_STATE <= S1;
END IF;
END CASE;
END PROCESS COMBIN;
-- Pprocess to hold synchronous elements (flip-flops)
SYNCH: PROCESS
BEGIN
IF (RST='1') THEN
CURRENT_STATE <= S0;
ELSIF (CLK'EVENT AND CLK = '1') THEN
CURRENT_STATE <= NEXT_STATE;
END IF;
END PROCESS SYNCH;
END Behavior;
| mit | 1e99fb3eae373ccdd1f54289e88b5790 | 0.455476 | 4.491954 | false | false | false | false |
hoglet67/ElectronFpga | src/common/mode7/mc6845.vhd | 1 | 18,563 | -- BBC Micro for Altera DE1
--
-- Copyright (c) 2011 Mike Stirling
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- * Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- * Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written agreement from the author.
--
-- * License is granted for non-commercial use only. A fee may not be charged
-- for redistributions as source code or in synthesized/hardware form without
-- specific prior written agreement from the author.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- MC6845 CRTC
--
-- Synchronous implementation for FPGA
--
-- (C) 2011 Mike Stirling
--
-- Corrected cursor flash rate
-- Fixed incorrect positioning of cursor when over left most character
-- Fixed timing of VSYNC
-- Fixed interlaced timing (add an extra line)
-- Implemented r05_v_total_adj
-- Implemented delay parts of r08_interlace (see Hitacht HD6845SP datasheet)
--
-- (C) 2015 David Banks
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mc6845 is
port (
CLOCK : in std_logic;
CLKEN : in std_logic;
nRESET : in std_logic;
-- Bus interface
ENABLE : in std_logic;
R_nW : in std_logic;
RS : in std_logic;
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
-- Display interface
VSYNC : out std_logic;
HSYNC : out std_logic;
DE : out std_logic;
CURSOR : out std_logic;
LPSTB : in std_logic;
-- Memory interface
MA : out std_logic_vector(13 downto 0);
RA : out std_logic_vector(4 downto 0)
);
end entity;
architecture rtl of mc6845 is
-- Host-accessible registers
signal addr_reg : std_logic_vector(4 downto 0); -- Currently addressed register
-- These are write-only
signal r00_h_total : unsigned(7 downto 0); -- Horizontal total, chars
signal r01_h_displayed : unsigned(7 downto 0); -- Horizontal active, chars
signal r02_h_sync_pos : unsigned(7 downto 0); -- Horizontal sync position, chars
signal r03_v_sync_width : unsigned(3 downto 0); -- Vertical sync width, scan lines (0=16 lines)
signal r03_h_sync_width : unsigned(3 downto 0); -- Horizontal sync width, chars (0=no sync)
signal r04_v_total : unsigned(6 downto 0); -- Vertical total, character rows
signal r05_v_total_adj : unsigned(4 downto 0); -- Vertical offset, scan lines
signal r06_v_displayed : unsigned(6 downto 0); -- Vertical active, character rows
signal r07_v_sync_pos : unsigned(6 downto 0); -- Vertical sync position, character rows
signal r08_interlace : std_logic_vector(7 downto 0);
signal r09_max_scan_line_addr : unsigned(4 downto 0);
signal r10_cursor_mode : std_logic_vector(1 downto 0);
signal r10_cursor_start : unsigned(4 downto 0); -- Cursor start, scan lines
signal r11_cursor_end : unsigned(4 downto 0); -- Cursor end, scan lines
signal r12_start_addr_h : unsigned(5 downto 0);
signal r13_start_addr_l : unsigned(7 downto 0);
-- These are read/write
signal r14_cursor_h : unsigned(5 downto 0);
signal r15_cursor_l : unsigned(7 downto 0);
-- These are read-only
signal r16_light_pen_h : unsigned(5 downto 0);
signal r17_light_pen_l : unsigned(7 downto 0);
-- Timing generation
-- Horizontal counter counts position on line
signal h_counter : unsigned(7 downto 0);
-- HSYNC counter counts duration of sync pulse
signal h_sync_counter : unsigned(3 downto 0);
-- Row counter counts current character row
signal row_counter : unsigned(6 downto 0);
-- Line counter counts current line within each character row
signal line_counter : unsigned(4 downto 0);
-- VSYNC counter counts duration of sync pulse
signal v_sync_counter : unsigned(3 downto 0);
-- Field counter counts number of complete fields for cursor flash
signal field_counter : unsigned(4 downto 0);
-- Internal signals
signal h_sync_start : std_logic;
signal v_sync_start : std_logic;
signal h_display : std_logic;
signal h_display_early : std_logic;
signal hs : std_logic;
signal v_display : std_logic;
signal v_display_early : std_logic;
signal vs : std_logic;
signal odd_field : std_logic;
signal ma_i : unsigned(13 downto 0);
signal ma_row_start : unsigned(13 downto 0); -- Start address of current character row
signal cursor_i : std_logic;
signal lpstb_i : std_logic;
signal de0 : std_logic;
signal de1 : std_logic;
signal de2 : std_logic;
signal cursor0 : std_logic;
signal cursor1 : std_logic;
signal cursor2 : std_logic;
begin
HSYNC <= hs; -- External HSYNC driven directly from internal signal
VSYNC <= vs; -- External VSYNC driven directly from internal signal
de0 <= h_display and v_display;
-- In Mode 7 DE Delay is set to 01, but in our implementation no delay is needed
-- TODO: Fix SAA5050
DE <= de0 when r08_interlace(5 downto 4) = "00" else
de0 when r08_interlace(5 downto 4) = "01" else -- not accurate, should be de1
de2 when r08_interlace(5 downto 4) = "10" else
'0';
-- Cursor output generated combinatorially from the internal signal in
-- accordance with the currently selected cursor mode
cursor0 <= cursor_i when r10_cursor_mode = "00" else
'0' when r10_cursor_mode = "01" else
(cursor_i and field_counter(3)) when r10_cursor_mode = "10" else
(cursor_i and field_counter(4));
-- In Mode 7 Cursor Delay is set to 10, but in our implementation one one cycle is needed
-- TODO: Fix SAA5050
CURSOR <= cursor0 when r08_interlace(7 downto 6) = "00" else
cursor1 when r08_interlace(7 downto 6) = "01" else
cursor1 when r08_interlace(7 downto 6) = "10" else -- not accurate, should be cursor2
'0';
-- Synchronous register access. Enabled on every clock.
process(CLOCK,nRESET)
begin
if nRESET = '0' then
-- Reset registers to defaults
addr_reg <= (others => '0');
r00_h_total <= (others => '0');
r01_h_displayed <= (others => '0');
r02_h_sync_pos <= (others => '0');
r03_v_sync_width <= (others => '0');
r03_h_sync_width <= (others => '0');
r04_v_total <= (others => '0');
r05_v_total_adj <= (others => '0');
r06_v_displayed <= (others => '0');
r07_v_sync_pos <= (others => '0');
r08_interlace <= (others => '0');
r09_max_scan_line_addr <= (others => '0');
r10_cursor_mode <= (others => '0');
r10_cursor_start <= (others => '0');
r11_cursor_end <= (others => '0');
r12_start_addr_h <= (others => '0');
r13_start_addr_l <= (others => '0');
r14_cursor_h <= (others => '0');
r15_cursor_l <= (others => '0');
DO <= (others => '0');
elsif rising_edge(CLOCK) then
if ENABLE = '1' then
if R_nW = '1' then
-- Read
case addr_reg is
when "01100" =>
DO <= "00" & std_logic_vector(r12_start_addr_h);
when "01101" =>
DO <= std_logic_vector(r13_start_addr_l);
when "01110" =>
DO <= "00" & std_logic_vector(r14_cursor_h);
when "01111" =>
DO <= std_logic_vector(r15_cursor_l);
when "10000" =>
DO <= "00" & std_logic_vector(r16_light_pen_h);
when "10001" =>
DO <= std_logic_vector(r17_light_pen_l);
when others =>
DO <= (others => '0');
end case;
else
-- Write
if RS = '0' then
addr_reg <= DI(4 downto 0);
else
case addr_reg is
when "00000" =>
r00_h_total <= unsigned(DI);
when "00001" =>
r01_h_displayed <= unsigned(DI);
when "00010" =>
r02_h_sync_pos <= unsigned(DI);
when "00011" =>
r03_v_sync_width <= unsigned(DI(7 downto 4));
r03_h_sync_width <= unsigned(DI(3 downto 0));
when "00100" =>
r04_v_total <= unsigned(DI(6 downto 0));
when "00101" =>
r05_v_total_adj <= unsigned(DI(4 downto 0));
when "00110" =>
r06_v_displayed <= unsigned(DI(6 downto 0));
when "00111" =>
r07_v_sync_pos <= unsigned(DI(6 downto 0));
when "01000" =>
r08_interlace <= DI(7 downto 0);
when "01001" =>
r09_max_scan_line_addr <= unsigned(DI(4 downto 0));
when "01010" =>
r10_cursor_mode <= DI(6 downto 5);
r10_cursor_start <= unsigned(DI(4 downto 0));
when "01011" =>
r11_cursor_end <= unsigned(DI(4 downto 0));
when "01100" =>
r12_start_addr_h <= unsigned(DI(5 downto 0));
when "01101" =>
r13_start_addr_l <= unsigned(DI(7 downto 0));
when "01110" =>
r14_cursor_h <= unsigned(DI(5 downto 0));
when "01111" =>
r15_cursor_l <= unsigned(DI(7 downto 0));
when others =>
null;
end case;
end if;
end if;
end if;
end if;
end process; -- registers
-- Horizontal, vertical and address counters
process(CLOCK,nRESET)
variable ma_row_start : unsigned(13 downto 0);
variable max_scan_line : unsigned(4 downto 0);
variable adj_scan_line : unsigned(4 downto 0);
variable in_adj : std_logic;
variable need_adj : std_logic;
begin
if nRESET = '0' then
-- H
h_counter <= (others => '0');
-- V
line_counter <= (others => '0');
row_counter <= (others => '0');
odd_field <= '0';
-- Fields (cursor flash)
field_counter <= (others => '0');
-- Addressing
ma_row_start := (others => '0');
ma_i <= (others => '0');
in_adj := '0';
elsif rising_edge(CLOCK) then
if CLKEN = '1' then
-- Horizontal counter increments on each clock, wrapping at
-- h_total
if h_counter = r00_h_total then
-- h_total reached
h_counter <= (others => '0');
-- Compute
if r05_v_total_adj /= 0 or odd_field = '1' then
need_adj := '1';
else
need_adj := '0';
end if;
-- Compute the max scan line for this row
if in_adj = '0' then
-- This is a normal row, so use r09_max_scan_line_addr
max_scan_line := r09_max_scan_line_addr;
else
-- This is the "adjust" row, so use r05_v_total_adj
max_scan_line := r05_v_total_adj - 1;
-- If interlaced, the odd field contains an additional scan line
if odd_field = '1' then
if r08_interlace(1 downto 0) = "11" then
max_scan_line := max_scan_line + 2;
else
max_scan_line := max_scan_line + 1;
end if;
end if;
end if;
-- In interlace sync + video mode mask off the LSb of the
-- max scan line address
if r08_interlace(1 downto 0) = "11" then
max_scan_line(0) := '0';
end if;
if line_counter = max_scan_line and ((need_adj = '0' and row_counter = r04_v_total) or in_adj = '1') then
line_counter <= (others => '0');
-- If in interlace mode we toggle to the opposite field.
-- Save on some logic by doing this here rather than at the
-- end of v_total_adj - it shouldn't make any difference to the
-- output
if r08_interlace(0) = '1' then
odd_field <= not odd_field;
else
odd_field <= '0';
end if;
-- Address is loaded from start address register at the top of
-- each field and the row counter is reset
ma_row_start := r12_start_addr_h & r13_start_addr_l;
row_counter <= (others => '0');
-- Increment field counter
field_counter <= field_counter + 1;
-- Reset the in extra time flag
in_adj := '0';
elsif in_adj = '0' and line_counter = max_scan_line then
-- Scan line counter increments, wrapping at max_scan_line_addr
-- Next character row
line_counter <= (others => '0');
-- On all other character rows within the field the row start address is
-- increased by h_displayed and the row counter is incremented
ma_row_start := ma_row_start + r01_h_displayed;
row_counter <= row_counter + 1;
-- Test if we are entering the adjust phase, and set
-- in_adj accordingly
if row_counter = r04_v_total and need_adj = '1' then
in_adj := '1';
end if;
else
-- Next scan line. Count in twos in interlaced sync+video mode
if r08_interlace(1 downto 0) = "11" then
line_counter <= line_counter + 2;
line_counter(0) <= '0'; -- Force to even
else
line_counter <= line_counter + 1;
end if;
end if;
-- Memory address preset to row start at the beginning of each
-- scan line
ma_i <= ma_row_start;
else
-- Increment horizontal counter
h_counter <= h_counter + 1;
-- Increment memory address
ma_i <= ma_i + 1;
end if;
end if;
end if;
end process;
-- Signals to mark hsync and and vsync in even and odd fields
process(h_counter, r00_h_total, r02_h_sync_pos, odd_field)
begin
h_sync_start <= '0';
v_sync_start <= '0';
if h_counter = r02_h_sync_pos then
h_sync_start <= '1';
end if;
-- dmb: measurements on a real beeb confirm this is the actual
-- 6845 behaviour. i.e. in non-interlaced mode the start of vsync
-- coinscides with the start of the active display, and in intelaced
-- mode the vsync of the odd field is delayed by half a scan line
if (odd_field = '0' and h_counter = 0) or (odd_field = '1' and h_counter = "0" & r00_h_total(7 downto 1)) then
v_sync_start <= '1';
end if;
end process;
h_display_early <= '1' when h_counter < r01_h_displayed else '0';
v_display_early <= '1' when row_counter < r06_v_displayed else '0';
-- Video timing and sync counters
process(CLOCK,nRESET)
begin
if nRESET = '0' then
-- H
h_display <= '0';
hs <= '0';
h_sync_counter <= (others => '0');
-- V
v_display <= '0';
vs <= '0';
v_sync_counter <= (others => '0');
elsif rising_edge(CLOCK) then
if CLKEN = '1' then
-- Horizontal active video
h_display <= h_display_early;
-- Horizontal sync
if h_sync_start = '1' or hs = '1' then
-- In horizontal sync
hs <= '1';
h_sync_counter <= h_sync_counter + 1;
else
h_sync_counter <= (others => '0');
end if;
if h_sync_counter = r03_h_sync_width then
-- Terminate hsync after h_sync_width (0 means no hsync so this
-- can immediately override the setting above)
hs <= '0';
end if;
-- Vertical active video
v_display <= v_display_early;
-- Vertical sync occurs either at the same time as the horizontal sync (even fields)
-- or half a line later (odd fields)
if (v_sync_start = '1') then
if (row_counter = r07_v_sync_pos and line_counter = 0) or vs = '1' then
-- In vertical sync
vs <= '1';
v_sync_counter <= v_sync_counter + 1;
else
v_sync_counter <= (others => '0');
end if;
if v_sync_counter = r03_v_sync_width and vs = '1' then
-- Terminate vsync after v_sync_width (0 means 16 lines so this is
-- masked by 'vs' to ensure a full turn of the counter in this case)
vs <= '0';
end if;
end if;
end if;
end if;
end process;
-- Address generation
process(CLOCK,nRESET)
variable slv_line : std_logic_vector(4 downto 0);
begin
if nRESET = '0' then
RA <= (others => '0');
MA <= (others => '0');
elsif rising_edge(CLOCK) then
if CLKEN = '1' then
slv_line := std_logic_vector(line_counter);
-- Character row address is just the scan line counter delayed by
-- one clock to line up with the syncs.
if r08_interlace(1 downto 0) = "11" then
-- In interlace sync and video mode the LSb is determined by the
-- field number. The line counter counts up in 2s in this case.
RA <= slv_line(4 downto 1) & (slv_line(0) or odd_field);
else
RA <= slv_line;
end if;
-- Internal memory address delayed by one cycle as well
MA <= std_logic_vector(ma_i);
end if;
end if;
end process;
-- Cursor control
process(CLOCK,nRESET)
variable cursor_line : std_logic;
begin
-- Internal cursor enable signal delayed by 1 clock to line up
-- with address outputs
if nRESET = '0' then
cursor_i <= '0';
cursor_line := '0';
elsif rising_edge(CLOCK) then
if CLKEN = '1' then
if h_display_early = '1' and v_display_early = '1' and ma_i = r14_cursor_h & r15_cursor_l then
if line_counter = 0 then
-- Suppress wrap around if last line is > max scan line
cursor_line := '0';
end if;
if line_counter = r10_cursor_start then
-- First cursor scanline
cursor_line := '1';
end if;
-- Cursor output is asserted within the current cursor character
-- on the selected lines only
cursor_i <= cursor_line;
if line_counter = r11_cursor_end then
-- Last cursor scanline
cursor_line := '0';
end if;
else
-- Cursor is off in all character positions apart from the
-- selected one
cursor_i <= '0';
end if;
end if;
end if;
end process;
-- Light pen capture
process(CLOCK,nRESET)
begin
if nRESET = '0' then
lpstb_i <= '0';
r16_light_pen_h <= (others => '0');
r17_light_pen_l <= (others => '0');
elsif rising_edge(CLOCK) then
if CLKEN = '1' then
-- Register light-pen strobe input
lpstb_i <= LPSTB;
if LPSTB = '1' and lpstb_i = '0' then
-- Capture address on rising edge
r16_light_pen_h <= ma_i(13 downto 8);
r17_light_pen_l <= ma_i(7 downto 0);
end if;
end if;
end if;
end process;
-- Delayed CURSOR and DE (selected by R08)
process(CLOCK,nRESET)
begin
if rising_edge(CLOCK) then
if CLKEN = '1' then
de1 <= de0;
de2 <= de1;
cursor1 <= cursor0;
cursor2 <= cursor1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 88a92d0642045f767cc7bd67e36c4a1d | 0.631956 | 3.086631 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/hostinterface/src/statusControlRegRtl.vhd | 3 | 23,788 | -------------------------------------------------------------------------------
--! @file statusControlReg.vhd
--
--! @brief Host interface Status-/Control Registers
--
--! @details The host interface status/control registers provide memory mapped
--! control of the interrupt generator (irqGen) and bridge (magicBridge).
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use host interface package for specific types
use work.hostInterfacePkg.all;
entity statusControlReg is
generic (
--! Magic
gMagic : natural := 16#504C4B00#;
-- Version
--! Version major
gVersionMajor : natural := 16#FF#;
--! Version minor
gVersionMinor : natural := 16#FF#;
--! Version revision
gVersionRevision : natural := 16#FF#;
--! Version count pattern
gVersionCount : natural := 0;
-- BaseSets
--! BaseSets by Host
gHostBaseSet : natural := 2;
--! BaseSets by Pcp
gPcpBaseSet : natural := 10;
--! Interrupt source number
gIrqSourceCount : natural range 1 to 15 := 3
);
port (
-- Global
--! component wide clock signal
iClk : in std_logic;
--! component wide reset signal
iRst : in std_logic;
-- slave Host interface
--! host read
iHostRead : in std_logic;
--! host write
iHostWrite : in std_logic;
--! host byteenable
iHostByteenable : in std_logic_vector(cDword/8-1 downto 0);
--! host address
iHostAddress : in std_logic_vector(10 downto 2);
--! host readdata
oHostReaddata : out std_logic_vector(cDword-1 downto 0);
--! host writedata
iHostWritedata : in std_logic_vector(cDword-1 downto 0);
--! host waitrequest
oHostWaitrequest : out std_logic;
-- slave PCP interface
--! pcp read
iPcpRead : in std_logic;
--! pcp write
iPcpWrite : in std_logic;
--! pcp byteenable
iPcpByteenable : in std_logic_vector(cDword/8-1 downto 0);
--! pcp address
iPcpAddress : in std_logic_vector(10 downto 2);
--! pcp readdata
oPcpReaddata : out std_logic_vector(cDword-1 downto 0);
--! pcp writedata
iPcpWritedata : in std_logic_vector(cDword-1 downto 0);
--! pcp waitrequest
oPcpWaitrequest : out std_logic;
-- BaseSet link
--! BaseSet write strobe
oBaseSetWrite : out std_logic;
--! BaseSet read strobe
oBaseSetRead : out std_logic;
--! BaseSet byteenable
oBaseSetByteenable : out std_logic_vector;
--! BaseSet address bus
oBaseSetAddress : out std_logic_vector(LogDualis(gHostBaseSet+gPcpBaseSet)+2-1 downto 2);
--! BaseSet read data bus
iBaseSetData : in std_logic_vector;
--! BaseSet write data bus
oBaseSetData : out std_logic_vector;
--! BaseSet acknowledge
iBaseSetAck : in std_logic;
-- Interrupt control
--! master enable
oIrqMasterEnable : out std_logic;
--! interrupt source enable vector ('right is sync)
oIrqSourceEnable : out std_logic_vector(gIrqSourceCount downto 0);
--! interrupt acknowledge (pulse, 'right is sync)
oIrqAcknowledge : out std_logic_vector(gIrqSourceCount downto 0);
--! interrup set (pulse, no sync!)
oIrqSet : out std_logic_vector(gIrqSourceCount downto 1);
--! interrupt source pending
iIrqPending : in std_logic_vector(gIrqSourceCount downto 0);
--! external sync source enable
oExtSyncEnable : out std_logic;
--! external sync source config
oExtSyncConfig : out std_logic_vector(cExtSyncEdgeConfigWidth-1 downto 0);
-- miscellaneous
--! bridge activates
oBridgeEnable : out std_logic
);
end statusControlReg;
architecture Rtl of statusControlReg is
-- base for register content
--! magic base
constant cBaseMagic : natural := 16#0000#;
--! version base
constant cBaseVersion : natural := 16#0004#;
--! boot base
constant cBaseBootBase : natural := 16#0008#;
--! init base
constant cBaseInitBase : natural := 16#000C#;
--! bridge enable base
constant cBaseBridgeEnable : natural := 16#0200#;
--! command base
constant cBaseCommand : natural := 16#0204#;
--! state base
constant cBaseState : natural := 16#0206#;
--! error base
constant cBaseError : natural := 16#0208#;
--! heart beat
constant cBaseHeartBeat : natural := 16#020A#;
--! irq enable base
constant cBaseIrqEnable : natural := 16#0300#;
--! irq pending base
constant cBaseIrqPending : natural := 16#0302#;
--! irq master enable base
constant cBaseIrqMasterEnable : natural := 16#0304#;
--! irq ack base (host only)
constant cBaseIrqAck : natural := 16#0306#;
--! irq set base (pcp only)
constant cBaseIrqSet : natural := 16#0306#;
--! sync config base
constant cBaseSyncConfig : natural := 16#030C#;
--! base for base set
constant cBaseBaseSet : natural := 16#0400#;
--! base reserved
constant cBaseReserved : natural := 16#0500#;
--! type base registers (stored content)
type tRegisterInfo is record
--magic
--version
bootBase : std_logic_vector(cDword-1 downto 0);
initBase : std_logic_vector(cDword-1 downto 0);
end record;
--! type control register (stored content)
type tRegisterControl is record
bridgeEnable : std_logic;
command : std_logic_vector(cWord-1 downto 0);
state : std_logic_vector(cWord-1 downto 0);
error : std_logic_vector(cWord-1 downto 0);
heartBeat : std_logic_vector(cWord-1 downto 0);
end record;
--! type synchronization register (stored content)
type tRegisterSynchronization is record
irqSrcEnableHost : std_logic_vector(gIrqSourceCount downto 0);
irqSrcEnablePcp : std_logic_vector(gIrqSourceCount downto 0);
irqMasterEnable : std_logic;
syncConfig : std_logic_vector(cExtSyncConfigWidth-1 downto 0);
end record;
--! info register
signal regInfo, regInfo_next : tRegisterInfo;
--! info register initialisation
constant cRegInfoInit : tRegisterInfo := (
bootBase => (others => cInactivated),
initBase => (others => cInactivated)
);
--! control register
signal regControl : tRegisterControl;
--! control register next
signal regControl_next : tRegisterControl;
--! control register initialisation
constant cRegControlInit : tRegisterControl := (
bridgeEnable => cInactivated,
command => (others => cInactivated),
state => (others => cInactivated),
error => (others => cInactivated),
heartBeat => (others => cInactivated)
);
--! synchronization register
signal regSynchron : tRegisterSynchronization;
--! synchronization register next
signal regSynchron_next : tRegisterSynchronization;
--! synchronization register initialisation
constant cRegSynchronInit : tRegisterSynchronization := (
irqSrcEnableHost => (others => cInactivated),
irqSrcEnablePcp => (others => cInactivated),
irqMasterEnable => cInactivated,
syncConfig => (others => cInactivated)
);
--! host base writedata
signal hostBaseSetData : std_logic_vector(iBaseSetData'range);
--! host base write
signal hostBaseSetWrite : std_logic;
--! host base read
signal hostBaseSetRead : std_logic;
--! pcp base writedata
signal pcpBaseSetData : std_logic_vector(iBaseSetData'range);
--! pcp base write
signal pcpBaseSetWrite : std_logic;
--! pcp base read
signal pcpBaseSetRead : std_logic;
begin
--! register process creates storage of values
regClk : process(iClk)
begin
if rising_edge(iClk) then
if iRst = cActivated then
regInfo <= cRegInfoInit;
regControl <= cRegControlInit;
regSynchron <= cRegSynchronInit;
else
regInfo <= regInfo_next;
regControl <= regControl_next;
regSynchron <= regSynchron_next;
end if;
end if;
end process;
oHostWaitrequest <= not iBaseSetAck when (hostBaseSetRead = cActivated or
hostBaseSetWrite = cActivated) else
not(iHostWrite or iHostRead);
oPcpWaitrequest <= not iBaseSetAck when (pcpBaseSetRead = cActivated or
pcpBaseSetWrite = cActivated) else
not(iPcpWrite or iPcpRead);
oIrqMasterEnable <= regSynchron.irqMasterEnable;
oIrqSourceEnable <= regSynchron.irqSrcEnableHost and regSynchron.irqSrcEnablePcp;
oExtSyncEnable <= regSynchron.syncConfig(0);
oExtSyncConfig <= regSynchron.syncConfig(2 downto 1);
oBridgeEnable <= regControl.bridgeEnable;
-- pcp overrules host!
oBaseSetData <= pcpBaseSetData when pcpBaseSetWrite = cActivated else
pcpBaseSetData when pcpBaseSetRead = cActivated else
hostBaseSetData;
oBaseSetByteenable <= iPcpByteenable when pcpBaseSetWrite = cActivated else
iPcpByteenable when pcpBaseSetRead = cActivated else
iHostByteenable;
oBaseSetAddress <= std_logic_vector(unsigned(iPcpAddress(oBaseSetAddress'range))+gHostBaseSet)
when pcpBaseSetRead = cActivated or pcpBaseSetWrite = cActivated else
iHostAddress(oBaseSetAddress'range);
oBaseSetWrite <= pcpBaseSetWrite or hostBaseSetWrite;
oBaseSetRead <= pcpBaseSetRead or hostBaseSetRead;
--! register access
regAcc : process (
iHostWrite,
iHostRead,
iHostByteenable,
iHostAddress,
iHostWritedata,
iPcpWrite,
iPcpRead,
iPcpByteenable,
iPcpAddress,
iPcpWritedata,
regInfo,
regControl,
regSynchron,
iIrqPending,
iBaseSetData
)
variable vHostSelAddr : natural;
variable vPcpSelAddr : natural;
begin
-- default
-- registers
regInfo_next <= regInfo;
regControl_next <= regControl;
regSynchron_next <= regSynchron;
-- outputs
oHostReaddata <= (others => cInactivated);
oIrqAcknowledge <= (others => cInactivated);
hostBaseSetData <= (others => cInactivated);
hostBaseSetWrite <= cInactivated;
hostBaseSetRead <= cInactivated;
oIrqSet <= (others => cInactivated);
oPcpReaddata <= (others => cInactivated);
pcpBaseSetData <= (others => cInactivated);
pcpBaseSetWrite <= cInactivated;
pcpBaseSetRead <= cInactivated;
-- HOST
-- select content
-- write to content
-- and read from content
vHostSelAddr := to_integer(unsigned(iHostAddress))*4;
case vHostSelAddr is
when cBaseMagic =>
oHostReaddata <= std_logic_vector(to_unsigned(gMagic, cDword));
--magic is RO
when cBaseVersion =>
oHostReaddata <=
std_logic_vector(to_unsigned(gVersionMajor, cByte)) &
std_logic_vector(to_unsigned(gVersionMinor, cByte)) &
std_logic_vector(to_unsigned(gVersionRevision, cByte)) &
std_logic_vector(to_unsigned(gVersionCount, cByte));
--version is RO
when cBaseBootBase =>
oHostReaddata <= regInfo.bootBase;
--bootBase is RO
when cBaseInitBase =>
oHostReaddata <= regInfo.initBase;
--initBase is RO
when cBaseBridgeEnable =>
oHostReaddata(0) <= regControl.bridgeEnable;
--bridge enable is RO
when cBaseState | cBaseCommand =>
oHostReaddata <= regControl.state & regControl.command;
if iHostWrite = cActivated then
--state is RO
if iHostByteenable(1) = cActivated then
regControl_next.command(cWord-1 downto cByte) <= iHostWritedata(cWord-1 downto cByte);
end if;
if iHostByteenable(0) = cActivated then
regControl_next.command(cByte-1 downto 0) <= iHostWritedata(cByte-1 downto 0);
end if;
end if;
when cBaseHeartBeat | cBaseError =>
oHostReaddata <= regControl.heartBeat & regControl.error;
--heartbeat and error are RO
when cBaseIrqPending | cBaseIrqEnable =>
oHostReaddata(cWord+gIrqSourceCount downto cWord) <= iIrqPending;
oHostReaddata(gIrqSourceCount downto 0) <= regSynchron.irqSrcEnableHost;
if iHostWrite = cActivated then
for i in cWord-1 downto 0 loop
if iHostByteenable(i/cByte) = cActivated and
i <= gIrqSourceCount then
regSynchron_next.irqSrcEnableHost(i) <= iHostWritedata(i);
end if;
end loop;
end if;
when cBaseIrqAck | cBaseIrqMasterEnable =>
-- irq ack is SC
oHostReaddata(0) <= regSynchron.irqMasterEnable;
if iHostWrite = cActivated then
if iHostByteenable(0) = cActivated then
regSynchron_next.irqMasterEnable <= iHostWritedata(0);
end if;
for i in cDword-1 downto cWord loop
if iHostByteenable(i/cByte) = cActivated and
(i-cWord) <= gIrqSourceCount then
oIrqAcknowledge(i-cWord) <= iHostWritedata(i);
end if;
end loop;
end if;
when cBaseSyncConfig =>
oHostReaddata(cExtSyncConfigWidth-1 downto 0) <= regSynchron.syncConfig;
if iHostWrite = cActivated then
for i in cWord-1 downto 0 loop
if iHostByteenable(i/cByte) = cActivated and
i < cExtSyncConfigWidth then
regSynchron_next.syncConfig(i) <= iHostWritedata(i);
end if;
end loop;
end if;
when cBaseBaseSet to cBaseReserved-1 =>
if vHostSelAddr < cBaseBaseSet+gHostBaseSet*cDword/cByte then
oHostReaddata(iBaseSetData'range) <= iBaseSetData;
if iHostWrite = cActivated then
hostBaseSetData <= iHostWritedata(hostBaseSetData'range);
hostBaseSetWrite <= cActivated;
hostBaseSetRead <= cInactivated;
elsif iHostRead = cActivated then
hostBaseSetRead <= cActivated;
hostBaseSetWrite <= cInactivated;
else
hostBaseSetWrite <= cInactivated;
hostBaseSetRead <= cInactivated;
end if;
end if;
when others => null;
end case;
-- PCP
-- select content
-- write to content
-- and read from content
vPcpSelAddr := to_integer(unsigned(iPcpAddress)) * 4;
case vPcpSelAddr is
when cBaseMagic =>
oPcpReaddata <= std_logic_vector(to_unsigned(gMagic, cDword));
--magic is RO
when cBaseVersion =>
oPcpReaddata <=
std_logic_vector(to_unsigned(gVersionMajor, cByte)) &
std_logic_vector(to_unsigned(gVersionMinor, cByte)) &
std_logic_vector(to_unsigned(gVersionRevision, cByte)) &
std_logic_vector(to_unsigned(gVersionCount, cByte));
--version is RO
when cBaseBootBase =>
oPcpReaddata <= regInfo.bootBase;
if iPcpWrite = cActivated then
for i in cDword-1 downto 0 loop
if iPcpByteenable(i/cByte) = cActivated then
regInfo_next.bootBase(i) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseInitBase =>
oPcpReaddata <= regInfo.initBase;
if iPcpWrite = cActivated then
for i in cDword-1 downto 0 loop
if iPcpByteenable(i/cByte) = cActivated then
regInfo_next.initBase(i) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseBridgeEnable =>
oPcpReaddata(0) <= regControl.bridgeEnable;
if iPcpWrite = cActivated then
regControl_next.bridgeEnable <= iPcpWritedata(0);
end if;
when cBaseState | cBaseCommand =>
oPcpReaddata <= regControl.state & regControl.command;
if iPcpWrite = cActivated then
for i in cDword-1 downto cWord loop
if iPcpByteenable(i/cByte) = cActivated then
regControl_next.state(i-cWord) <= iPcpWritedata(i);
end if;
end loop;
for i in cWord-1 downto 0 loop
if iPcpByteenable(i/cByte) = cActivated then
regControl_next.command(i) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseHeartBeat | cBaseError =>
oPcpReaddata <= regControl.heartBeat & regControl.error;
if iPcpWrite = cActivated then
for i in cDword-1 downto cWord loop
if iPcpByteenable(i/cByte) = cActivated then
regControl_next.heartBeat(i-cWord) <= iPcpWritedata(i);
end if;
end loop;
for i in cWord-1 downto 0 loop
if iPcpByteenable(i/cByte) = cActivated then
regControl_next.error(i) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseIrqPending | cBaseIrqEnable =>
oPcpReaddata(cWord+gIrqSourceCount downto cWord) <= iIrqPending;
oPcpReaddata(gIrqSourceCount downto 0) <= regSynchron.irqSrcEnablePcp;
if iPcpWrite = cActivated then
for i in cWord-1 downto 0 loop
if iPcpByteenable(i/cByte) = cActivated and
i <= gIrqSourceCount then
regSynchron_next.irqSrcEnablePcp(i) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseIrqSet | cBaseIrqMasterEnable =>
-- irq set is self-clearing
oPcpReaddata(0) <= regSynchron.irqMasterEnable;
if iPcpWrite = cActivated then
for i in cDword-1 downto cWord+1 loop
if iPcpByteenable(i/cByte) = cActivated and
(i-cWord) <= gIrqSourceCount then
oIrqSet(i-cWord) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseSyncConfig =>
oPcpReaddata(cExtSyncConfigWidth-1 downto 0) <=
regSynchron.syncConfig;
when cBaseBaseSet to cBaseReserved-1 =>
if vPcpSelAddr < cBaseBaseSet+gPcpBaseSet*cDword/cByte then
oPcpReaddata(iBaseSetData'range) <= iBaseSetData;
if iPcpWrite = cActivated then
pcpBaseSetData <= iPcpWritedata(pcpBaseSetData'range);
pcpBaseSetWrite <= cActivated;
pcpBaseSetRead <= cInactivated;
elsif iPcpRead = cActivated then
pcpBaseSetRead <= cActivated;
pcpBaseSetWrite <= cInactivated;
else
pcpBaseSetRead <= cInactivated;
pcpBaseSetWrite <= cInactivated;
end if;
end if;
when others => null;
end case;
end process;
end Rtl;
| gpl-2.0 | 84aa4f1f5c62a38efd30a3f318a896af | 0.548218 | 5.47732 | false | false | false | false |
Reiuiji/ECE368-Lab | Lab 3/VGA Part 2/misc/vga_buffer_ram.vhd | 1 | 32,128 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: VGA Buffer Ram
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Ram for the VGA Display
-- Holds the buffer for the VGA
---------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity VGA_BUFFER_RAM is
generic( ADDR_WIDTH: integer:=13;
DATA_WIDTH:integer:=8
);
port( CLK : in std_logic;
RST : in std_logic;
WE : in std_logic;
ADDR_A : in std_logic_vector(ADDR_WIDTH-1 downto 0);
ADDR_B : in std_logic_vector(ADDR_WIDTH-1 downto 0);
DIN_A : in std_logic_vector(7 downto 0);
DOUT_B : out std_logic_vector(6 downto 0)
);
end VGA_BUFFER_RAM;
architecture Behavioral of VGA_BUFFER_RAM is
type ram_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal addr_b_reg: std_logic_vector(ADDR_WIDTH-1 downto 0);
signal ram: ram_type;-- := (
-- --1: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --2: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --3: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --4: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --5: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --6: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --7: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --8: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --9: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --10: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --11: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --12: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --13: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --14: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --15: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --16: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --17: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --18: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --19: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --20: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --21: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --22: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --23: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --24: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --25: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --26: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --27: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --28: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --29: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --30: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --31: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --32: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --33: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --34: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --35: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --36: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --37: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --38: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --39: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --40: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20"--4096
-- );
begin
process(CLK, WE)
variable tmp_b : integer;
begin
if (CLK'event and CLK = '1') then
if (WE = '1') then
ram(to_integer(unsigned(ADDR_A))) <= DIN_A;
end if;
addr_b_reg <= ADDR_B;
end if;
end process;
DOUT_B <= ram(to_integer(unsigned(addr_b_reg)))(6 downto 0);
end Behavioral;
| mit | 267e5703369865603e006cd1fc1307f2 | 0.442729 | 1.700704 | false | false | false | false |
DreamIP/GPStudio | support/process/roberts/hdl/roberts_process.vhd | 1 | 5,303 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity roberts_process is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer;
WEIGHT_SIZE : integer := 8
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_width : in std_logic_vector(15 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end roberts_process;
architecture rtl of roberts_process is
component matrix_extractor
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer;
OUTVALUE_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
------------------------ matrix out ---------------------
p00, p01, p02 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p10, p11, p12 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p20, p21, p22 : out std_logic_vector((PIX_WIDTH-1) downto 0);
matrix_dv : out std_logic;
---------------------- computed value -------------------
value_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
value_dv : in std_logic;
------------------------- params ------------------------
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0)
);
end component;
-- neighbors extraction
signal p00, p01, p02 : std_logic_vector((IN_SIZE-1) downto 0);
signal p10, p11, p12 : std_logic_vector((IN_SIZE-1) downto 0);
signal p20, p21, p22 : std_logic_vector((IN_SIZE-1) downto 0);
signal matrix_dv : std_logic;
-- products calculation
signal prod00, prod01, prod02 : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
signal prod10, prod11, prod12 : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
signal prod20, prod21, prod22 : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
signal prod_dv : std_logic;
signal value_data : std_logic_vector((IN_SIZE-1) downto 0);
signal value_dv : std_logic;
signal out_fv_s : std_logic;
signal enable_s : std_logic;
begin
matrix_extractor_inst : matrix_extractor
generic map (
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
PIX_WIDTH => IN_SIZE,
OUTVALUE_WIDTH => IN_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
p00 => p00, p01 => p01, p02 => p02,
p10 => p10, p11 => p11, p12 => p12,
p20 => p20, p21 => p21, p22 => p22,
matrix_dv => matrix_dv,
value_data => value_data,
value_dv => value_dv,
out_data => out_data,
out_fv => out_fv_s,
out_dv => out_dv,
enable_i => status_reg_enable_bit,
widthimg_i => widthimg_reg_width
);
process (clk_proc, reset_n, matrix_dv)
variable sum : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
begin
if(reset_n='0') then
enable_s <= '0';
prod_dv <= '0';
value_dv <= '0';
elsif(rising_edge(clk_proc)) then
if(in_fv = '0') then
enable_s <= status_reg_enable_bit;
prod_dv <= '0';
value_dv <= '0';
end if;
-- product calculation pipeline stage
prod_dv <= '0';
if(matrix_dv = '1' and enable_s = '1') then
prod00 <= "00000000" * signed('0' & p00); -- w00 = 0
prod01 <= "00000000" * signed('0' & p01); -- w01 = 0
prod02 <= "00000000" * signed('0' & p02); -- w02 = 0
prod10 <= "00000000" * signed('0' & p10); -- w10 = 0
prod11 <= "11111111" * signed('0' & p11); -- w11 = -1
prod12 <= "11111111" * signed('0' & p12); -- w12 = -1
prod20 <= "00000000" * signed('0' & p20); -- w20 = 0
prod21 <= "00000001" * signed('0' & p21); -- w21 = 1
prod22 <= "00000001" * signed('0' & p22); -- w22 = 1
prod_dv <= '1';
end if;
value_dv <= '0';
if(prod_dv='1' and enable_s = '1') then
sum := prod00 + prod01 + prod02 +
prod10 + prod11 + prod12 +
prod20 + prod21 + prod22;
if (sum(sum'left) = '1') then
sum := (others => '0');
end if;
value_data <= std_logic_vector(unsigned(sum))(OUT_SIZE -1 downto 0);
value_dv <= '1';
end if;
end if;
end process;
out_fv <= enable_s and out_fv_s;
end rtl;
| gpl-3.0 | b4fb4eb3a9109de3bca3ccacf0c9eb02 | 0.497454 | 3.162194 | false | false | false | false |
DreamIP/GPStudio | support/process/fast/hdl/fast_process.vhd | 1 | 4,616 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fast_types.all;
entity fast_process is
generic(
PIXEL_SIZE : integer;
IMAGE_WIDTH : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector ((PIXEL_SIZE-1) downto 0);
in_dv : in std_logic;
in_fv : in std_logic;
out1_data : out std_logic_vector ((PIXEL_SIZE-1) downto 0);
out1_dv : out std_logic;
out1_fv : out std_logic
);
end entity;
architecture structural of fast_process is
--------------------------------------------------------------------------------
-- COMPONENTS
--------------------------------------------------------------------------------
component neighExtractor
generic(
PIXEL_SIZE : integer;
IMAGE_WIDTH : integer;
KERNEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector((PIXEL_SIZE-1) downto 0);
in_dv : in std_logic;
in_fv : in std_logic;
out_data : out pixel_array (0 to (KERNEL_SIZE * KERNEL_SIZE)- 1);
out_dv : out std_logic;
out_fv : out std_logic
);
end component;
--------------------------------------------------------------------------------
component fastElement
generic(
KERNEL_SIZE : integer;
PIXEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in pixel_array (0 to KERNEL_SIZE * KERNEL_SIZE - 1);
in_dv : in std_logic;
in_fv : in std_logic;
in_kernel : in pixel_array (0 to KERNEL_SIZE * KERNEL_SIZE - 1);
--in_norm : in std_logic_vector(PIXEL_SIZE-1 downto 0);
out_data : out std_logic_vector(PIXEL_SIZE-1 downto 0);
out_dv : out std_logic;
out_fv : out std_logic
);
end component;
--------------------------------------------------------------------------------
-- CONSTANTS
--------------------------------------------------------------------------------
constant CONST_C1_KERNEL_SIZE : integer := 7;
constant CONST_C1_NORM : std_logic_vector := std_logic_vector(to_unsigned(7,PIXEL_SIZE));
constant CONST_C1_KERNEL : pixel_array (0 to CONST_C1_KERNEL_SIZE * CONST_C1_KERNEL_SIZE - 1) :=
(others => (std_logic_vector(to_unsigned(1,PIXEL_SIZE))));
--------------------------------------------------------------------------------
-- SIGNALS
--------------------------------------------------------------------------------
signal ne1_data : pixel_array (0 to CONST_C1_KERNEL_SIZE * CONST_C1_KERNEL_SIZE - 1);
signal ne1_dv : std_logic;
signal ne1_fv : std_logic;
--------------------------------------------------------------------------------
-- STRUCTURAL DESCRIPTION
--------------------------------------------------------------------------------
begin
NE1_INST : neighExtractor
generic map(
PIXEL_SIZE => PIXEL_SIZE,
IMAGE_WIDTH => IMAGE_WIDTH,
KERNEL_SIZE => CONST_C1_KERNEL_SIZE
)
port map(
clk => clk,
reset_n => reset_n,
enable => enable,
in_data => in_data,
in_dv => in_dv,
in_fv => in_fv,
out_data => ne1_data,
out_dv => ne1_dv,
out_fv => ne1_fv
);
--------------------------------------------------------------------------------
CE1_INST : fastElement
generic map(
PIXEL_SIZE => PIXEL_SIZE,
KERNEL_SIZE => CONST_C1_KERNEL_SIZE
)
port map(
clk => clk,
reset_n => reset_n,
enable => enable,
in_data => ne1_data,
in_dv => ne1_dv,
in_fv => ne1_fv,
in_kernel => CONST_C1_KERNEL,
--in_norm => CONST_C1_NORM,
out_data => out1_data,
out_dv => out1_dv,
out_fv => out1_fv
);
end structural;
| gpl-3.0 | 8e51dd8f09ddaa5fe0025ab2269782a2 | 0.388865 | 4.020906 | false | false | false | false |
makestuff/get-me-started-with | modelsim-altera-gtkwave/dpram.vhdl | 1 | 9,319 | -- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: dpram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.0 Build 208 07/03/2011 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dpram IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
rdclock : IN STD_LOGIC ;
wraddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
wrclock : IN STD_LOGIC := '1';
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END dpram;
ARCHITECTURE SYN OF dpram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock1 : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(3 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 1024,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
widthad_a => 10,
widthad_b => 10,
width_a => 4,
width_b => 4,
width_byteena_a => 1
)
PORT MAP (
address_a => wraddress,
clock0 => wrclock,
data_a => data,
wren_a => wren,
address_b => rdaddress,
clock1 => rdclock,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "1"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "4"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "4"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "4"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "4"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL "data[3..0]"
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]"
-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
-- Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]"
-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 4 0 data 0 0 4 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q_b 0 0 4 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | bf68d5324ee20bd0d9b4d272e045045a | 0.680545 | 3.465601 | false | false | false | false |
Reiuiji/ECE368-Lab | Lab 3/Keyboard/keycode_to_ascii.vhd | 1 | 6,905 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Keycode to Ascii
-- Project Name: Keyboard Controller
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Keycode to ascii
---------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity KEYCODE_TO_ASCII is
port(
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
KEYCODE : in STD_LOGIC_VECTOR(7 downto 0);
VALID_SIGNAL : in STD_LOGIC;
-- Output
COMPLETE: out STD_LOGIC; -- Hit Key sucessfully
ASCII : out STD_LOGIC_VECTOR(7 downto 0)--;
--KEYBOARD_OUT : out STD_LOGIC_VECTOR(7 downto 0);
--WRITE_KEYBOARD: out STD_LOGIC;
);
end KEYCODE_TO_ASCII;
architecture dataflow of KEYCODE_TO_ASCII is
type StateType is (init, idle, READ_BREAKCODE, READ_EXTENDED, READ_KEYCODE,SEND_COMPLETE);--,SEND_CAPS);
signal STATE : StateType := init;
signal ASCII_LOWER : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ASCII_UPPER : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
shared variable Shift_Key : boolean := false;
shared variable Caps_Lock : boolean := false;
shared variable Extended : boolean := false;
begin
with KEYCODE select
ASCII_LOWER <=
-- Alphabet
x"61" when x"1C", -- a
x"62" when x"32", -- b
x"63" when x"21", -- c
x"64" when x"23", -- d
x"65" when x"24", -- e
x"6C" when x"2B", -- f
x"67" when x"34", -- g
x"68" when x"33", -- h
x"69" when x"43", -- i
x"6A" when x"3B", -- j
x"6B" when x"42", -- k
x"66" when x"4B", -- l
x"6D" when x"3A", -- m
x"6E" when x"31", -- n
x"6F" when x"44", -- o
x"70" when x"4D", -- p
x"71" when x"15", -- q
x"74" when x"2D", -- r
x"73" when x"1B", -- s
x"72" when x"2C", -- t
x"79" when x"3C", -- u
x"76" when x"2A", -- v
x"77" when x"1D", -- w
x"78" when x"22", -- x
x"75" when x"35", -- y
x"7A" when x"1A", -- z
--Top Row
x"60" when x"0E", -- `
x"31" when x"16", -- 1
x"32" when x"1E", -- 2
x"33" when x"26", -- 3
x"34" when x"25", -- 4
x"35" when x"2E", -- 5
x"36" when x"36", -- 6
x"37" when x"3D", -- 7
x"38" when x"3E", -- 8
x"39" when x"46", -- 9
x"30" when x"45", -- 0
x"2D" when x"4E", -- -
x"3D" when x"55", -- =
--Enter Corner
x"5B" when x"54", -- [
x"5D" when x"5B", -- ]
x"5C" when x"5D", -- \
x"3B" when x"4C", -- ;
x"27" when x"52", -- '
x"2C" when x"41", -- ,
x"2E" when x"49", -- .
x"2F" when x"4A", -- /
--Function Keys -- Based on the IBM PC Codes
x"1B" when x"76", -- Esc (Escape)
x"3B" when x"05", -- F1
x"3C" when x"06", -- F2
x"3D" when x"04", -- F3
x"3E" when x"0C", -- F4
x"3F" when x"03", -- F5
x"40" when x"0B", -- F6
x"41" when x"83", -- F7
x"42" when x"0A", -- F8
x"43" when x"01", -- F9
x"44" when x"09", -- F10
x"85" when x"78", -- F11
x"86" when x"07", -- F12
x"09" when x"0D", -- Tab (Horizontal Tab)
x"0D" when x"5A", -- Enter (Carriage Return)
--special characters -- taking up unneaded ascii codes for simplicity
x"05" when x"58", -- Caps Lock
x"06" when x"14", -- Ctrl
x"07" when x"11", -- Alt
x"08" when x"66", -- Back Space
x"20" when x"29", -- Space
--Direction Keys -- taking up unneaded ascii codes for simplicity
x"01" when x"75", -- Up
x"02" when x"72", -- Down
x"03" when x"6B", -- Left
x"04" when x"74", -- Right
--Unknown input
x"00" when OTHERS; -- Null
with KEYCODE select
ASCII_UPPER <=
-- Alphabet
x"41" when x"1C", -- A
x"42" when x"32", -- B
x"43" when x"21", -- C
x"44" when x"23", -- D
x"48" when x"24", -- E
x"46" when x"2B", -- F
x"47" when x"34", -- G
x"45" when x"33", -- H
x"49" when x"43", -- I
x"4A" when x"3B", -- J
x"4B" when x"42", -- K
x"4C" when x"4B", -- L
x"4D" when x"3A", -- M
x"4E" when x"31", -- N
x"4F" when x"44", -- O
x"50" when x"4D", -- P
x"51" when x"15", -- Q
x"52" when x"2D", -- R
x"54" when x"1B", -- S
x"53" when x"2C", -- T
x"55" when x"3C", -- U
x"56" when x"2A", -- V
x"57" when x"1D", -- W
x"58" when x"22", -- X
x"59" when x"35", -- Y
x"5A" when x"1A", -- Z
-- Special Upper case Characters (top left to bottom right)
-- Top Row
x"7E" when x"0E", -- ~
x"21" when x"16", -- !
x"40" when x"1E", -- @
x"23" when x"26", -- #
x"24" when x"25", -- $
x"25" when x"2E", -- %
x"5E" when x"36", -- ^
x"26" when x"3D", -- &
x"2A" when x"3E", -- *
x"28" when x"46", -- (
x"29" when x"45", -- )
x"5F" when x"4E", -- _
x"2B" when x"55", -- +
-- Enter Corner
x"7B" when x"54", -- {
x"7D" when x"5B", -- }
x"7C" when x"5D", -- |
x"3A" when x"4C", -- :
x"22" when x"52", -- "
x"3C" when x"41", -- <
x"3E" when x"49", -- >
x"3F" when x"4A", -- ?
-- Unknown Key
x"00" when OTHERS; -- Null
PROCESS (KEYCODE,CLK, RST)
BEGIN
if (RST = '1') then
STATE <= init;
elsif (CLK'event and CLK= '0' ) then
case STATE is
when init =>
ascii <= (OTHERS => '0');
COMPLETE <= '0';
state <= idle;
when idle =>
COMPLETE <= '0';
if VALID_SIGNAL= '1' then
Extended := false;
if keycode=x"E0" then
state <= READ_EXTENDED;
-- A Key was pressed
elsif keycode=x"F0" then
state <= READ_KEYCODE;
else
-- No break code yet
state <= idle;
end if;
-- Shift Key was press (on)
if (keycode=x"12" or keycode=x"54") then
Shift_Key := true;
end if;
end if;
when READ_EXTENDED =>
if VALID_SIGNAL= '1' then
Extended := true;
if keycode=x"F0" then
state <= READ_KEYCODE;
else
state <= idle;
end if;
end if;
when READ_BREAKCODE =>
if VALID_SIGNAL= '1' then
if keycode=x"F0" then
state <= READ_KEYCODE;
else
state <= idle;
end if;
end if;
when READ_KEYCODE =>
if VALID_SIGNAL= '1' then
-- Shift Key was released (off)
if (keycode=x"12" or keycode=x"54") then
Shift_Key := false;
elsif (keycode=x"46") then
if (Caps_Lock = false) then
Caps_Lock := true;
else
Caps_Lock := false;
end if;
--state <= SEND_CAPS;
else
if (Shift_Key = true or Caps_Lock = true) then
ascii <= ASCII_UPPER;
else
ascii <= ASCII_LOWER;
end if;
end if;
state <= SEND_COMPLETE;
end if;
when SEND_COMPLETE =>
COMPLETE <= '1';
state <= idle;
--when SEND_CAPS =>
when OTHERS =>
state <= idle;
end case;
end if;
end process;
end architecture dataflow;
| mit | 6e8dec95e25447890194962aa17c4e37 | 0.510644 | 2.399236 | false | false | false | false |
DreamIP/GPStudio | support/process/sconv/hdl/pipline_gen.vhd | 1 | 1,477 | -- Author : K. Abdelouahab
-- Company : DREAM - Institut Pascal - Unviersite Clermont Auvergne
library ieee;
use ieee.std_logic_1164.all;
entity pipline_gen is
generic (
PIPLINE_LENGHT : integer;
WORD_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
e : in std_logic;
in_data : in std_logic_vector (WORD_SIZE-1 downto 0);
i0,i1,i2 : out std_logic_vector (WORD_SIZE-1 downto 0);
out_data : out std_logic_vector (WORD_SIZE-1 downto 0)
);
end pipline_gen;
architecture bhv of pipline_gen is
type cell_t is array (0 to (PIPLINE_LENGHT-1)) of std_logic_vector ( (WORD_SIZE-1) downto 0);
signal cell : cell_t;
begin
process(clk_proc)
variable i : integer := 0;
begin
if ( reset_n = '0' ) then
cell <= (others =>(others => '0'));
elsif (rising_edge(clk_proc)) then
if (e='1') then
cell(0) <= in_data;
for i in 1 to (PIPLINE_LENGHT-1) loop
cell(i) <= cell(i-1);
end loop;
out_data<= cell(PIPLINE_LENGHT - 1);
i0 <= cell(0);
i1 <= cell(1);
i2 <= cell(2);
end if;
end if;
end process;
end bhv;
| gpl-3.0 | d1ff6c804263d15d37f2aeb6d1acc578 | 0.462424 | 3.372146 | false | false | false | false |
hoglet67/ElectronFpga | src/xilinx/DCM/dcm1.vhd | 1 | 2,016 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm1 is
port (CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic);
end dcm1;
architecture BEHAVIORAL of dcm1 is
signal CLK0_BUF : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLKFX_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 4.0, -- 33.33 = 32 * 25 / 24
CLKFX_MULTIPLY => 25,
CLKFX_DIVIDE => 24,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => CLK0_BUF,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => CLK0_BUF,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| gpl-3.0 | e583c326cfe27e048247e2072c0cb2c1 | 0.403274 | 4.316916 | false | false | false | false |
hoglet67/ElectronFpga | src/common/AlanD/R65Cx2.vhd | 1 | 61,146 | -- -----------------------------------------------------------------------
--
-- This is a table driven 65Cx2 core by A.Daly
-- This is a derivative of the excellent FPGA64 core see below
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
-- -----------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
entity R65C02 is
port (
reset : in std_logic;
clk : in std_logic;
enable : in std_logic;
nmi_n : in std_logic;
irq_n : in std_logic;
di : in unsigned(7 downto 0);
do : out unsigned(7 downto 0);
addr : out unsigned(15 downto 0);
nwe : out std_logic;
sync : out std_logic;
sync_irq : out std_logic;
-- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB)
Regs : out std_logic_vector(63 downto 0)
);
end R65C02;
-- Store Zp (3) => fetch, cycle2, cycleEnd
-- Store Zp,x (4) => fetch, cycle2, preWrite, cycleEnd
-- Read Zp,x (4) => fetch, cycle2, cycleRead, cycleRead2
-- Rmw Zp,x (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd
-- Store Abs (4) => fetch, cycle2, cycle3, cycleEnd
-- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd
-- Rts (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd
-- Rti (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump
-- Jsr (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump
-- Jmp abs (-) => fetch, cycle2, .., cycleJump
-- Jmp (ind) (-) => fetch, cycle2, .., cycleJump
-- Brk / irq (6) => fetch, cycle2, stack2, stack3, stack4
-- -----------------------------------------------------------------------
architecture Behavioral of R65C02 is
-- signal counter : unsigned(27 downto 0);
-- signal mask_irq : std_logic;
-- signal mask_enable : std_logic;
-- Statemachine
type cpuCycles is (
opcodeFetch, -- New opcode is read and registers updated
cycle2,
cycle3,
cyclePreIndirect,
cycleIndirect,
cycleBranchTaken,
cycleBranchPage,
cyclePreRead, -- Cycle before read while doing zeropage indexed addressing.
cycleRead, -- Read cycle
cycleRead2, -- Second read cycle after page-boundary crossing.
cycleRmw, -- Calculate ALU output for read-modify-write instr.
cyclePreWrite, -- Cycle before write when doing indexed addressing.
cycleWrite, -- Write cycle for zeropage or absolute addressing.
cycleStack1,
cycleStack2,
cycleStack3,
cycleStack4,
cycleJump, -- Last cycle of Jsr, Jmp. Next fetch address is target addr.
cycleEnd
);
signal theCpuCycle : cpuCycles;
signal nextCpuCycle : cpuCycles;
signal updateRegisters : boolean;
signal processIrq : std_logic;
signal nmiReg: std_logic;
signal nmiEdge: std_logic;
signal irqReg : std_logic; -- Delay IRQ input with one clock cycle.
signal soReg : std_logic; -- SO pin edge detection
-- Opcode decoding
constant opcUpdateA : integer := 0;
constant opcUpdateX : integer := 1;
constant opcUpdateY : integer := 2;
constant opcUpdateS : integer := 3;
constant opcUpdateN : integer := 4;
constant opcUpdateV : integer := 5;
constant opcUpdateD : integer := 6;
constant opcUpdateI : integer := 7;
constant opcUpdateZ : integer := 8;
constant opcUpdateC : integer := 9;
constant opcSecondByte : integer := 10;
constant opcAbsolute : integer := 11;
constant opcZeroPage : integer := 12;
constant opcIndirect : integer := 13;
constant opcStackAddr : integer := 14; -- Push/Pop address
constant opcStackData : integer := 15; -- Push/Pop status/data
constant opcJump : integer := 16;
constant opcBranch : integer := 17;
constant indexX : integer := 18;
constant indexY : integer := 19;
constant opcStackUp : integer := 20;
constant opcWrite : integer := 21;
constant opcRmw : integer := 22;
constant opcIncrAfter : integer := 23; -- Insert extra cycle to increment PC (RTS)
constant opcRti : integer := 24;
constant opcIRQ : integer := 25;
constant opcInA : integer := 26;
constant opcInBrk : integer := 27;
constant opcInX : integer := 28;
constant opcInY : integer := 29;
constant opcInS : integer := 30;
constant opcInT : integer := 31;
constant opcInH : integer := 32;
constant opcInClear : integer := 33;
constant aluMode1From : integer := 34;
--
constant aluMode1To : integer := 37;
constant aluMode2From : integer := 38;
--
constant aluMode2To : integer := 40;
--
constant opcInCmp : integer := 41;
constant opcInCpx : integer := 42;
constant opcInCpy : integer := 43;
subtype addrDef is unsigned(0 to 15);
--
-- is Interrupt -----------------+
-- instruction is RTI ----------------+|
-- PC++ on last cycle (RTS) ---------------+||
-- RMW --------------+|||
-- Write -------------+||||
-- Pop/Stack up -------------+|||||
-- Branch ---------+ ||||||
-- Jump ----------+| ||||||
-- Push or Pop data -------+|| ||||||
-- Push or Pop addr ------+||| ||||||
-- Indirect -----+|||| ||||||
-- ZeroPage ----+||||| ||||||
-- Absolute ---+|||||| ||||||
-- PC++ on cycle2 --+||||||| ||||||
-- |AZI||JBXY|WM|||
constant immediate : addrDef := "1000000000000000";
constant implied : addrDef := "0000000000000000";
-- Zero page
constant readZp : addrDef := "1010000000000000";
constant writeZp : addrDef := "1010000000010000";
constant rmwZp : addrDef := "1010000000001000";
-- Zero page indexed
constant readZpX : addrDef := "1010000010000000";
constant writeZpX : addrDef := "1010000010010000";
constant rmwZpX : addrDef := "1010000010001000";
constant readZpY : addrDef := "1010000001000000";
constant writeZpY : addrDef := "1010000001010000";
constant rmwZpY : addrDef := "1010000001001000";
-- Zero page indirect
constant readIndX : addrDef := "1001000010000000";
constant writeIndX : addrDef := "1001000010010000";
constant rmwIndX : addrDef := "1001000010001000";
constant readIndY : addrDef := "1001000001000000";
constant writeIndY : addrDef := "1001000001010000";
constant rmwIndY : addrDef := "1001000001001000";
constant rmwInd : addrDef := "1001000000001000";
constant readInd : addrDef := "1001000000000000";
constant writeInd : addrDef := "1001000000010000";
-- |AZI||JBXY|WM||
-- Absolute
constant readAbs : addrDef := "1100000000000000";
constant writeAbs : addrDef := "1100000000010000";
constant rmwAbs : addrDef := "1100000000001000";
constant readAbsX : addrDef := "1100000010000000";
constant writeAbsX : addrDef := "1100000010010000";
constant rmwAbsX : addrDef := "1100000010001000";
constant readAbsY : addrDef := "1100000001000000";
constant writeAbsY : addrDef := "1100000001010000";
constant rmwAbsY : addrDef := "1100000001001000";
-- PHA PHP
constant push : addrDef := "0000010000000000";
-- PLA PLP
constant pop : addrDef := "0000010000100000";
-- Jumps
constant jsr : addrDef := "1000101000000000";
constant jumpAbs : addrDef := "1000001000000000";
constant jumpInd : addrDef := "1100001000000000";
constant jumpIndX : addrDef := "1100001010000000";
constant relative : addrDef := "1000000100000000";
-- Specials
constant rts : addrDef := "0000101000100100";
constant rti : addrDef := "0000111000100010";
constant brk : addrDef := "1000111000000001";
-- constant irq : addrDef := "0000111000000001";
-- constant : unsigned(0 to 0) := "0";
constant xxxxxxxx : addrDef := "----------0---00";
-- A = accu
-- X = index X
-- Y = index Y
-- S = Stack pointer
-- H = indexH
--
-- AEXYSTHc
constant aluInA : unsigned(0 to 7) := "10000000";
constant aluInBrk : unsigned(0 to 7) := "01000000";
constant aluInX : unsigned(0 to 7) := "00100000";
constant aluInY : unsigned(0 to 7) := "00010000";
constant aluInS : unsigned(0 to 7) := "00001000";
constant aluInT : unsigned(0 to 7) := "00000100";
constant aluInClr : unsigned(0 to 7) := "00000001";
constant aluInSet : unsigned(0 to 7) := "00000000";
constant aluInXXX : unsigned(0 to 7) := "--------";
-- Most of the aluModes are just like the opcodes.
-- aluModeInp -> input is output. calculate N and Z
-- aluModeCmp -> Compare for CMP, CPX, CPY
-- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV
-- aluModeInc -> for INC but also INX, INY
-- aluModeDec -> for DEC but also DEX, DEY
subtype aluMode1 is unsigned(0 to 3);
subtype aluMode2 is unsigned(0 to 2);
subtype aluMode is unsigned(0 to 9);
-- Logic/Shift ALU
constant aluModeInp : aluMode1 := "0000";
constant aluModeP : aluMode1 := "0001";
constant aluModeInc : aluMode1 := "0010";
constant aluModeDec : aluMode1 := "0011";
constant aluModeFlg : aluMode1 := "0100";
constant aluModeBit : aluMode1 := "0101";
-- 0110
-- 0111
constant aluModeLsr : aluMode1 := "1000";
constant aluModeRor : aluMode1 := "1001";
constant aluModeAsl : aluMode1 := "1010";
constant aluModeRol : aluMode1 := "1011";
constant aluModeTSB : aluMode1 := "1100";
constant aluModeTRB : aluMode1 := "1101";
-- 1110
-- 1111;
-- Arithmetic ALU
constant aluModePss : aluMode2 := "000";
constant aluModeCmp : aluMode2 := "001";
constant aluModeAdc : aluMode2 := "010";
constant aluModeSbc : aluMode2 := "011";
constant aluModeAnd : aluMode2 := "100";
constant aluModeOra : aluMode2 := "101";
constant aluModeEor : aluMode2 := "110";
constant aluModeNoF : aluMode2 := "111";
--aluModeBRK
--constant aluBrk : aluMode := aluModeBRK & aluModePss & "---";
--constant aluFix : aluMode := aluModeInp & aluModeNoF & "---";
constant aluInp : aluMode := aluModeInp & aluModePss & "---";
constant aluP : aluMode := aluModeP & aluModePss & "---";
constant aluInc : aluMode := aluModeInc & aluModePss & "---";
constant aluDec : aluMode := aluModeDec & aluModePss & "---";
constant aluFlg : aluMode := aluModeFlg & aluModePss & "---";
constant aluBit : aluMode := aluModeBit & aluModeAnd & "---";
constant aluRor : aluMode := aluModeRor & aluModePss & "---";
constant aluLsr : aluMode := aluModeLsr & aluModePss & "---";
constant aluRol : aluMode := aluModeRol & aluModePss & "---";
constant aluAsl : aluMode := aluModeAsl & aluModePss & "---";
constant aluTSB : aluMode := aluModeTSB & aluModePss & "---";
constant aluTRB : aluMode := aluModeTRB & aluModePss & "---";
constant aluCmp : aluMode := aluModeInp & aluModeCmp & "100";
constant aluCpx : aluMode := aluModeInp & aluModeCmp & "010";
constant aluCpy : aluMode := aluModeInp & aluModeCmp & "001";
constant aluAdc : aluMode := aluModeInp & aluModeAdc & "---";
constant aluSbc : aluMode := aluModeInp & aluModeSbc & "---";
constant aluAnd : aluMode := aluModeInp & aluModeAnd & "---";
constant aluOra : aluMode := aluModeInp & aluModeOra & "---";
constant aluEor : aluMode := aluModeInp & aluModeEor & "---";
constant aluXXX : aluMode := (others => '-');
-- Stack operations. Push/Pop/None
constant stackInc : unsigned(0 to 0) := "0";
constant stackDec : unsigned(0 to 0) := "1";
constant stackXXX : unsigned(0 to 0) := "-";
subtype decodedBitsDef is unsigned(0 to 43);
type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
constant opcodeInfoTable : opcodeInfoTableDef := (
-- +------- Update register A
-- |+------ Update register X
-- ||+----- Update register Y
-- |||+---- Update register S
-- |||| +-- Update Flags
-- |||| |
-- |||| _|__
-- |||| / \
-- AXYS NVDIZC addressing aluInput aluMode
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "001100" & brk & aluInBrk & aluP, -- 00 BRK
"1000" & "100010" & readIndX & aluInT & aluOra, -- 01 ORA (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 02 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 03 NOP ------- 65C02
"0000" & "000010" & rmwZp & aluInT & aluTSB, -- 04 TSB zp ----------- 65C02
"1000" & "100010" & readZp & aluInT & aluOra, -- 05 ORA zp
"0000" & "100011" & rmwZp & aluInT & aluAsl, -- 06 ASL zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 07 NOP ------- 65C02
"0000" & "000000" & push & aluInXXX & aluP, -- 08 PHP
"1000" & "100010" & immediate & aluInT & aluOra, -- 09 ORA imm
"1000" & "100011" & implied & aluInA & aluAsl, -- 0A ASL accu
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 0B NOP ------- 65C02
"0000" & "000010" & rmwAbs & aluInT & aluTSB, -- 0C TSB abs ---------- 65C02
"1000" & "100010" & readAbs & aluInT & aluOra, -- 0D ORA abs
"0000" & "100011" & rmwAbs & aluInT & aluAsl, -- 0E ASL abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 0F NOP ------- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 10 BPL
"1000" & "100010" & readIndY & aluInT & aluOra, -- 11 ORA (zp),y
"1000" & "100010" & readInd & aluInT & aluOra, -- 12 ORA (zp) --------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 13 NOP ------- 65C02
"0000" & "000010" & rmwZp & aluInT & aluTRB, -- 14 TRB zp ~---------- 65C02
"1000" & "100010" & readZpX & aluInT & aluOra, -- 15 ORA zp,x
"0000" & "100011" & rmwZpX & aluInT & aluAsl, -- 16 ASL zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 17 NOP ------- 65C02
"0000" & "000001" & implied & aluInClr & aluFlg, -- 18 CLC
"1000" & "100010" & readAbsY & aluInT & aluOra, -- 19 ORA abs,y
"1000" & "100010" & implied & aluInA & aluInc, -- 1A INC accu --------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 1B NOP ------- 65C02
"0000" & "000010" & rmwAbs & aluInT & aluTRB, -- 1C TRB abs ~----- --- 65C02
"1000" & "100010" & readAbsX & aluInT & aluOra, -- 1D ORA abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluAsl, -- 1E ASL abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 1F NOP ------- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & jsr & aluInXXX & aluXXX, -- 20 JSR
"1000" & "100010" & readIndX & aluInT & aluAnd, -- 21 AND (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 22 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 23 NOP ------- 65C02
"0000" & "110010" & readZp & aluInT & aluBit, -- 24 BIT zp
"1000" & "100010" & readZp & aluInT & aluAnd, -- 25 AND zp
"0000" & "100011" & rmwZp & aluInT & aluRol, -- 26 ROL zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 27 NOP ------- 65C02
"0000" & "111111" & pop & aluInT & aluFlg, -- 28 PLP
"1000" & "100010" & immediate & aluInT & aluAnd, -- 29 AND imm
"1000" & "100011" & implied & aluInA & aluRol, -- 2A ROL accu
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 2B NOP ------- 65C02
"0000" & "110010" & readAbs & aluInT & aluBit, -- 2C BIT abs
"1000" & "100010" & readAbs & aluInT & aluAnd, -- 2D AND abs
"0000" & "100011" & rmwAbs & aluInT & aluRol, -- 2E ROL abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 2F NOP ------- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 30 BMI
"1000" & "100010" & readIndY & aluInT & aluAnd, -- 31 AND (zp),y
"1000" & "100010" & readInd & aluInT & aluAnd, -- 32 AND (zp) -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 33 NOP ------- 65C02
"0000" & "110010" & readZpX & aluInT & aluBit, -- 34 BIT zp,x -------- 65C02
"1000" & "100010" & readZpX & aluInT & aluAnd, -- 35 AND zp,x
"0000" & "100011" & rmwZpX & aluInT & aluRol, -- 36 ROL zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 37 NOP ------- 65C02
"0000" & "000001" & implied & aluInSet & aluFlg, -- 38 SEC
"1000" & "100010" & readAbsY & aluInT & aluAnd, -- 39 AND abs,y
"1000" & "100010" & implied & aluInA & aluDec, -- 3A DEC accu -------- 65C12
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 3B NOP ------- 65C02
"0000" & "110010" & readAbsX & aluInT & aluBit, -- 3C BIT abs,x ------- 65C02
"1000" & "100010" & readAbsX & aluInT & aluAnd, -- 3D AND abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluRol, -- 3E ROL abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 3F NOP ------- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "111111" & rti & aluInT & aluFlg, -- 40 RTI
"1000" & "100010" & readIndX & aluInT & aluEor, -- 41 EOR (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 42 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 43 NOP ------- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 44 NOP ------- 65C02
"1000" & "100010" & readZp & aluInT & aluEor, -- 45 EOR zp
"0000" & "100011" & rmwZp & aluInT & aluLsr, -- 46 LSR zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 47 NOP ------- 65C02
"0000" & "000000" & push & aluInA & aluInp, -- 48 PHA
"1000" & "100010" & immediate & aluInT & aluEor, -- 49 EOR imm
"1000" & "100011" & implied & aluInA & aluLsr, -- 4A LSR accu -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 4B NOP ------- 65C02
"0000" & "000000" & jumpAbs & aluInXXX & aluXXX, -- 4C JMP abs
"1000" & "100010" & readAbs & aluInT & aluEor, -- 4D EOR abs
"0000" & "100011" & rmwAbs & aluInT & aluLsr, -- 4E LSR abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 4F NOP ------- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 50 BVC
"1000" & "100010" & readIndY & aluInT & aluEor, -- 51 EOR (zp),y
"1000" & "100010" & readInd & aluInT & aluEor, -- 52 EOR (zp) -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 53 NOP ------- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 54 NOP ------- 65C02
"1000" & "100010" & readZpX & aluInT & aluEor, -- 55 EOR zp,x
"0000" & "100011" & rmwZpX & aluInT & aluLsr, -- 56 LSR zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 57 NOP ------- 65C02
"0000" & "000100" & implied & aluInClr & aluXXX, -- 58 CLI
"1000" & "100010" & readAbsY & aluInT & aluEor, -- 59 EOR abs,y
"0000" & "000000" & push & aluInY & aluInp, -- 5A PHY ------------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 5B NOP ------- 65C02
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- 5C NOP ------- 65C02
"1000" & "100010" & readAbsX & aluInT & aluEor, -- 5D EOR abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluLsr, -- 5E LSR abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 5F NOP ------- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & rts & aluInXXX & aluXXX, -- 60 RTS
"1000" & "110011" & readIndX & aluInT & aluAdc, -- 61 ADC (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 62 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 63 NOP ------- 65C02
"0000" & "000000" & writeZp & aluInClr & aluInp, -- 64 STZ zp ---------- 65C02
"1000" & "110011" & readZp & aluInT & aluAdc, -- 65 ADC zp
"0000" & "100011" & rmwZp & aluInT & aluRor, -- 66 ROR zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 67 NOP ------- 65C02
"1000" & "100010" & pop & aluInT & aluInp, -- 68 PLA
"1000" & "110011" & immediate & aluInT & aluAdc, -- 69 ADC imm
"1000" & "100011" & implied & aluInA & aluRor, -- 6A ROR accu
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 6B NOP ------ 65C02
"0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect
"1000" & "110011" & readAbs & aluInT & aluAdc, -- 6D ADC abs
"0000" & "100011" & rmwAbs & aluInT & aluRor, -- 6E ROR abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 6F NOP ------ 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 70 BVS
"1000" & "110011" & readIndY & aluInT & aluAdc, -- 71 ADC (zp),y
"1000" & "110011" & readInd & aluInT & aluAdc, -- 72 ADC (zp) -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 73 NOP ------ 65C02
"0000" & "000000" & writeZpX & aluInClr & aluInp, -- 74 STZ zp,x -------- 65C02
"1000" & "110011" & readZpX & aluInT & aluAdc, -- 75 ADC zp,x
"0000" & "100011" & rmwZpX & aluInT & aluRor, -- 76 ROR zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 77 NOP ----- 65C02
"0000" & "000100" & implied & aluInSet & aluXXX, -- 78 SEI
"1000" & "110011" & readAbsY & aluInT & aluAdc, -- 79 ADC abs,y
"0010" & "100010" & pop & aluInT & aluInp, -- 7A PLY ------------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 7B NOP ----- 65C02
"0000" & "000000" & jumpIndX & aluInXXX & aluXXX, -- 7C JMP indirect,x -- 65C02
--"0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect
"1000" & "110011" & readAbsX & aluInT & aluAdc, -- 7D ADC abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluRor, -- 7E ROR abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 7F NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 80 BRA ----------- 65C02
"0000" & "000000" & writeIndX & aluInA & aluInp, -- 81 STA (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 NOP ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 83 NOP ----- 65C02
"0000" & "000000" & writeZp & aluInY & aluInp, -- 84 STY zp
"0000" & "000000" & writeZp & aluInA & aluInp, -- 85 STA zp
"0000" & "000000" & writeZp & aluInX & aluInp, -- 86 STX zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 87 NOP ----- 65C02
"0010" & "100010" & implied & aluInY & aluDec, -- 88 DEY
"0000" & "000010" & immediate & aluInT & aluBit, -- 89 BIT imm ------- 65C02
"1000" & "100010" & implied & aluInX & aluInp, -- 8A TXA
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 8B NOP ----- 65C02
"0000" & "000000" & writeAbs & aluInY & aluInp, -- 8C STY abs ------- 65C02
"0000" & "000000" & writeAbs & aluInA & aluInp, -- 8D STA abs
"0000" & "000000" & writeAbs & aluInX & aluInp, -- 8E STX abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 8F NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 90 BCC
"0000" & "000000" & writeIndY & aluInA & aluInp, -- 91 STA (zp),y
"0000" & "000000" & writeInd & aluInA & aluInp, -- 92 STA (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 93 NOP ----- 65C02
"0000" & "000000" & writeZpX & aluInY & aluInp, -- 94 STY zp,x
"0000" & "000000" & writeZpX & aluInA & aluInp, -- 95 STA zp,x
"0000" & "000000" & writeZpY & aluInX & aluInp, -- 96 STX zp,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 97 NOP ----- 65C02
"1000" & "100010" & implied & aluInY & aluInp, -- 98 TYA
"0000" & "000000" & writeAbsY & aluInA & aluInp, -- 99 STA abs,y
"0001" & "000000" & implied & aluInX & aluInp, -- 9A TXS
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 9B NOP ----- 65C02
"0000" & "000000" & writeAbs & aluInClr & aluInp, -- 9C STZ Abs ------- 65C02
"0000" & "000000" & writeAbsX & aluInA & aluInp, -- 9D STA abs,x
"0000" & "000000" & writeAbsX & aluInClr & aluInp, -- 9C STZ Abs,x ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 9F NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0010" & "100010" & immediate & aluInT & aluInp, -- A0 LDY imm
"1000" & "100010" & readIndX & aluInT & aluInp, -- A1 LDA (zp,x)
"0100" & "100010" & immediate & aluInT & aluInp, -- A2 LDX imm
"0000" & "000000" & implied & aluInXXX & aluXXX, -- A3 NOP ----- 65C02
"0010" & "100010" & readZp & aluInT & aluInp, -- A4 LDY zp
"1000" & "100010" & readZp & aluInT & aluInp, -- A5 LDA zp
"0100" & "100010" & readZp & aluInT & aluInp, -- A6 LDX zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- A7 NOP ----- 65C02
"0010" & "100010" & implied & aluInA & aluInp, -- A8 TAY
"1000" & "100010" & immediate & aluInT & aluInp, -- A9 LDA imm
"0100" & "100010" & implied & aluInA & aluInp, -- AA TAX
"0000" & "000000" & implied & aluInXXX & aluXXX, -- AB NOP ----- 65C02
"0010" & "100010" & readAbs & aluInT & aluInp, -- AC LDY abs
"1000" & "100010" & readAbs & aluInT & aluInp, -- AD LDA abs
"0100" & "100010" & readAbs & aluInT & aluInp, -- AE LDX abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- AF NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- B0 BCS
"1000" & "100010" & readIndY & aluInT & aluInp, -- B1 LDA (zp),y
"1000" & "100010" & readInd & aluInT & aluInp, -- B2 LDA (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- B3 NOP ----- 65C02
"0010" & "100010" & readZpX & aluInT & aluInp, -- B4 LDY zp,x
"1000" & "100010" & readZpX & aluInT & aluInp, -- B5 LDA zp,x
"0100" & "100010" & readZpY & aluInT & aluInp, -- B6 LDX zp,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- B7 NOP ----- 65C02
"0000" & "010000" & implied & aluInClr & aluFlg, -- B8 CLV
"1000" & "100010" & readAbsY & aluInT & aluInp, -- B9 LDA abs,y
"0100" & "100010" & implied & aluInS & aluInp, -- BA TSX
"0000" & "000000" & implied & aluInXXX & aluXXX, -- BB NOP ----- 65C02
"0010" & "100010" & readAbsX & aluInT & aluInp, -- BC LDY abs,x
"1000" & "100010" & readAbsX & aluInT & aluInp, -- BD LDA abs,x
"0100" & "100010" & readAbsY & aluInT & aluInp, -- BE LDX abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- BF NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "100011" & immediate & aluInT & aluCpy, -- C0 CPY imm
"0000" & "100011" & readIndX & aluInT & aluCmp, -- C1 CMP (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 NOP ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- C3 NOP ----- 65C02
"0000" & "100011" & readZp & aluInT & aluCpy, -- C4 CPY zp
"0000" & "100011" & readZp & aluInT & aluCmp, -- C5 CMP zp
"0000" & "100010" & rmwZp & aluInT & aluDec, -- C6 DEC zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- C7 NOP ----- 65C02
"0010" & "100010" & implied & aluInY & aluInc, -- C8 INY
"0000" & "100011" & immediate & aluInT & aluCmp, -- C9 CMP imm
"0100" & "100010" & implied & aluInX & aluDec, -- CA DEX
"0000" & "000000" & implied & aluInXXX & aluXXX, -- CB NOP ----- 65C02
"0000" & "100011" & readAbs & aluInT & aluCpy, -- CC CPY abs
"0000" & "100011" & readAbs & aluInT & aluCmp, -- CD CMP abs
"0000" & "100010" & rmwAbs & aluInT & aluDec, -- CE DEC abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- CF NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- D0 BNE
"0000" & "100011" & readIndY & aluInT & aluCmp, -- D1 CMP (zp),y
"0000" & "100011" & readInd & aluInT & aluCmp, -- D2 CMP (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- D3 NOP ----- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- D4 NOP ----- 65C02
"0000" & "100011" & readZpX & aluInT & aluCmp, -- D5 CMP zp,x
"0000" & "100010" & rmwZpX & aluInT & aluDec, -- D6 DEC zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- D7 NOP ----- 65C02
"0000" & "001000" & implied & aluInClr & aluXXX, -- D8 CLD
"0000" & "100011" & readAbsY & aluInT & aluCmp, -- D9 CMP abs,y
"0000" & "000000" & push & aluInX & aluInp, -- DA PHX ----------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- DB NOP ----- 65C02
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- DC NOP ----- 65C02
"0000" & "100011" & readAbsX & aluInT & aluCmp, -- DD CMP abs,x
"0000" & "100010" & rmwAbsX & aluInT & aluDec, -- DE DEC abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- DF NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "100011" & immediate & aluInT & aluCpx, -- E0 CPX imm
"1000" & "110011" & readIndX & aluInT & aluSbc, -- E1 SBC (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 NOP ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- E3 NOP ----- 65C02
"0000" & "100011" & readZp & aluInT & aluCpx, -- E4 CPX zp
"1000" & "110011" & readZp & aluInT & aluSbc, -- E5 SBC zp
"0000" & "100010" & rmwZp & aluInT & aluInc, -- E6 INC zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- E7 NOP ----- 65C02
"0100" & "100010" & implied & aluInX & aluInc, -- E8 INX
"1000" & "110011" & immediate & aluInT & aluSbc, -- E9 SBC imm
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EA NOP
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EB NOP ----- 65C02
"0000" & "100011" & readAbs & aluInT & aluCpx, -- EC CPX abs
"1000" & "110011" & readAbs & aluInT & aluSbc, -- ED SBC abs
"0000" & "100010" & rmwAbs & aluInT & aluInc, -- EE INC abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EF NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- F0 BEQ
"1000" & "110011" & readIndY & aluInT & aluSbc, -- F1 SBC (zp),y
"1000" & "110011" & readInd & aluInT & aluSbc, -- F2 SBC (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- F3 NOP ----- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- F4 NOP ----- 65C02
"1000" & "110011" & readZpX & aluInT & aluSbc, -- F5 SBC zp,x
"0000" & "100010" & rmwZpX & aluInT & aluInc, -- F6 INC zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- F7 NOP ---- 65C02
"0000" & "001000" & implied & aluInSet & aluXXX, -- F8 SED
"1000" & "110011" & readAbsY & aluInT & aluSbc, -- F9 SBC abs,y
"0100" & "100010" & pop & aluInT & aluInp, -- FA PLX ----------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- FB NOP ----- 65C02
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- FC NOP ----- 65C02
"1000" & "110011" & readAbsX & aluInT & aluSbc, -- FD SBC abs,x
"0000" & "100010" & rmwAbsX & aluInT & aluInc, -- FE INC abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX -- FF NOP ----- 65C02
);
signal opcInfo : decodedBitsDef;
signal nextOpcInfo : decodedBitsDef; -- Next opcode (decoded)
signal nextOpcInfoReg : decodedBitsDef; -- Next opcode (decoded) pipelined
signal theOpcode : unsigned(7 downto 0);
signal nextOpcode : unsigned(7 downto 0);
-- Program counter
signal PC : unsigned(15 downto 0); -- Program counter
-- Address generation
type nextAddrDef is (
nextAddrHold,
nextAddrIncr,
nextAddrIncrL, -- Increment low bits only (zeropage accesses)
nextAddrIncrH, -- Increment high bits only (page-boundary)
nextAddrDecrH, -- Decrement high bits (branch backwards)
nextAddrPc,
nextAddrIrq,
nextAddrReset,
nextAddrAbs,
nextAddrAbsIndexed,
nextAddrZeroPage,
nextAddrZPIndexed,
nextAddrStack,
nextAddrRelative
);
signal nextAddr : nextAddrDef;
signal myAddr : unsigned(15 downto 0);
signal myAddrIncr : unsigned(15 downto 0);
signal myAddrIncrH : unsigned(7 downto 0);
signal myAddrDecrH : unsigned(7 downto 0);
signal theWe : std_logic;
signal irqActive : std_logic;
-- Output register
signal doReg : unsigned(7 downto 0);
-- Buffer register
signal T : unsigned(7 downto 0);
-- General registers
signal A: unsigned(7 downto 0); -- Accumulator
signal X: unsigned(7 downto 0); -- Index X
signal Y: unsigned(7 downto 0); -- Index Y
signal S: unsigned(7 downto 0); -- stack pointer
-- Status register
signal C: std_logic; -- Carry
signal Z: std_logic; -- Zero flag
signal I: std_logic; -- Interrupt flag
signal D: std_logic; -- Decimal mode
signal B: std_logic; -- Break software interrupt
signal R: std_logic; -- always 1
signal V: std_logic; -- Overflow
signal N: std_logic; -- Negative
-- ALU
-- ALU input
signal aluInput : unsigned(7 downto 0);
signal aluCmpInput : unsigned(7 downto 0);
-- ALU output
signal aluRegisterOut : unsigned(7 downto 0);
signal aluRmwOut : unsigned(7 downto 0);
signal aluC : std_logic;
signal aluZ : std_logic;
signal aluV : std_logic;
signal aluN : std_logic;
-- Indexing
signal indexOut : unsigned(8 downto 0);
signal realbrk : std_logic;
begin
processAluInput: process(clk, opcInfo, A, X, Y, T, S)
variable temp : unsigned(7 downto 0);
begin
temp := (others => '1');
if opcInfo(opcInA) = '1' then
temp := temp and A;
end if;
if opcInfo(opcInX) = '1' then
temp := temp and X;
end if;
if opcInfo(opcInY) = '1' then
temp := temp and Y;
end if;
if opcInfo(opcInS) = '1' then
temp := temp and S;
end if;
if opcInfo(opcInT) = '1' then
temp := temp and T;
end if;
if opcInfo(opcInBrk) = '1' then
temp := temp and "11100111"; -- also DMB clear D (bit 3)
end if;
if opcInfo(opcInClear) = '1' then
temp := (others => '0');
end if;
aluInput <= temp;
end process;
processCmpInput: process(clk, opcInfo, A, X, Y)
variable temp : unsigned(7 downto 0);
begin
temp := (others => '1');
if opcInfo(opcInCmp) = '1' then
temp := temp and A;
end if;
if opcInfo(opcInCpx) = '1' then
temp := temp and X;
end if;
if opcInfo(opcInCpy) = '1' then
temp := temp and Y;
end if;
aluCmpInput <= temp;
end process;
-- ALU consists of two parts
-- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL
-- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA
-- Some instructions are both RMW and accumulator so for most
-- instructions the rmw results are routed through accu alu too.
-- The B flag
------------
--No actual "B" flag exists inside the 6502's processor status register. The B
--flag only exists in the status flag byte pushed to the stack. Naturally,
--when the flags are restored (via PLP or RTI), the B bit is discarded.
--
--Depending on the means, the B status flag will be pushed to the stack as
--either 0 or 1.
--
--software instructions BRK & PHP will push the B flag as being 1.
--hardware interrupts IRQ & NMI will push the B flag as being 0.
processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V, R, D, I, Z, C)
variable lowBits: unsigned(5 downto 0);
variable nineBits: unsigned(8 downto 0);
variable rmwBits: unsigned(8 downto 0);
variable tsxBits: unsigned(8 downto 0);
variable varC : std_logic;
variable varZ : std_logic;
variable varV : std_logic;
variable varN : std_logic;
begin
lowBits := (others => '-');
nineBits := (others => '-');
rmwBits := (others => '-');
tsxBits := (others => '-');
R <= '1';
-- Shift unit
case opcInfo(aluMode1From to aluMode1To) is
when aluModeInp => rmwBits := C & aluInput;
when aluModeP => rmwBits := C & N & V & R & (not irqActive) & D & I & Z & C; -- irqActive
when aluModeInc => rmwBits := C & (aluInput + 1);
when aluModeDec => rmwBits := C & (aluInput - 1);
when aluModeAsl => rmwBits := aluInput & "0";
when aluModeTSB => rmwBits := "0" & (aluInput(7 downto 0) or A); -- added by alan for 65c02
tsxBits := "0" & (aluInput(7 downto 0) and A);
when aluModeTRB => rmwBits := "0" & (aluInput(7 downto 0) and (not A)); -- added by alan for 65c02
tsxBits := "0" & (aluInput(7 downto 0) and A);
when aluModeFlg => rmwBits := aluInput(0) & aluInput;
when aluModeLsr => rmwBits := aluInput(0) & "0" & aluInput(7 downto 1);
when aluModeRol => rmwBits := aluInput & C;
when aluModeRoR => rmwBits := aluInput(0) & C & aluInput(7 downto 1);
when others => rmwBits := C & aluInput;
end case;
-- ALU
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc => lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1");
ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8));
when aluModeSbc => lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1");
ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8));
when aluModeCmp => ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001";
when aluModeAnd => ninebits := rmwBits(8) & (A and rmwBits(7 downto 0));
when aluModeEor => ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0));
when aluModeOra => ninebits := rmwBits(8) & (A or rmwBits(7 downto 0));
when aluModeNoF => ninebits := "000110000";
when others => ninebits := rmwBits;
end case;
varV := aluInput(6); -- Default for BIT / PLP / RTI
if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
varZ := rmwBits(1);
elsif (opcInfo(aluMode1From to aluMode1To) = aluModeTSB) or (opcInfo(aluMode1From to aluMode1To) = aluModeTRB) then
if tsxBits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
elsif ninebits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
if (opcInfo(aluMode1From to aluMode1To) = aluModeBit) or (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
varN := rmwBits(7);
else
varN := nineBits(7);
end if;
varC := ninebits(8);
case opcInfo(aluMode2From to aluMode2To) is
-- Flags Affected: n v — — — — z c
-- n Set if most significant bit of result is set; else cleared.
-- v Set if signed overflow; cleared if valid signed result.
-- z Set if result is zero; else cleared.
-- c Set if unsigned overflow; cleared if valid unsigned result
when aluModeAdc =>
-- decimal mode low bits correction, is done after setting Z flag.
if D = '1' then
if lowBits(5 downto 1) > 9 then
ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
if lowBits(5) = '0' then
ninebits(8 downto 4) := ninebits(8 downto 4) + 1;
end if;
end if;
end if;
when others => null;
end case;
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
-- decimal mode high bits correction, is done after setting Z and N flags
varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7));
if D = '1' then
if ninebits(8 downto 4) > 9 then
ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
varC := '1';
end if;
end if;
when aluModeSbc =>
varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7));
if D = '1' then
-- Check for borrow (lower 4 bits)
if lowBits(5) = '0' then
ninebits(7 downto 0) := ninebits(7 downto 0) - 6;
end if;
-- Check for borrow (upper 4 bits)
if ninebits(8) = '0' then
ninebits(8 downto 4) := ninebits(8 downto 4) - 6;
end if;
end if;
when others => null;
end case;
-- fix n and z flag for 65c02 adc sbc instructions in decimal mode
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
if D = '1' then
if ninebits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
varN := ninebits(7);
end if;
when aluModeSbc =>
if D = '1' then
if ninebits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
varN := ninebits(7);
end if;
when others => null;
end case;
-- DMB Remove Pipelining
-- if rising_edge(clk) then
aluRmwOut <= rmwBits(7 downto 0);
aluRegisterOut <= ninebits(7 downto 0);
aluC <= varC;
aluZ <= varZ;
aluV <= varV;
aluN <= varN;
-- end if;
end process;
calcInterrupt: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if theCpuCycle = cycleStack4 or reset = '0' then
nmiReg <= '1';
end if;
if nextCpuCycle /= cycleBranchTaken and nextCpuCycle /= opcodeFetch then
irqReg <= irq_n;
nmiEdge <= nmi_n;
if (nmiEdge = '1') and (nmi_n = '0') then
nmiReg <= '0';
end if;
end if;
-- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
-- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ));
end if;
end if;
end process;
--pipeirq: process(clk)
-- begin
-- if rising_edge(clk) then
-- if enable = '1' then
-- if (reset = '0') or (theCpuCycle = opcodeFetch) then
-- -- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
-- -- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
-- processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ));
-- end if;
-- end if;
-- end if;
-- end process;
calcNextOpcode: process(clk, di, reset, processIrq)
variable myNextOpcode : unsigned(7 downto 0);
begin
-- Next opcode is read from input unless a reset or IRQ is pending.
myNextOpcode := di;
if reset = '0' then
myNextOpcode := X"4C";
elsif processIrq = '1' then
myNextOpcode := X"00";
end if;
nextOpcode <= myNextOpcode;
end process;
nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode));
-- DMB Remove Pipelining
-- process(clk)
-- begin
-- if rising_edge(clk) then
nextOpcInfoReg <= nextOpcInfo;
-- end if;
-- end process;
-- Read bits and flags from opcodeInfoTable and store in opcInfo.
-- This info is used to control the execution of the opcode.
calcOpcInfo: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if (reset = '0') or (theCpuCycle = opcodeFetch) then
opcInfo <= nextOpcInfo;
end if;
end if;
end if;
end process;
calcTheOpcode: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if theCpuCycle = opcodeFetch then
irqActive <= '0';
if processIrq = '1' then
irqActive <= '1';
end if;
-- Fetch opcode
theOpcode <= nextOpcode;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- State machine
-- -----------------------------------------------------------------------
process(enable, theCpuCycle, opcInfo)
begin
updateRegisters <= false;
if enable = '1' then
if opcInfo(opcRti) = '1' then
if theCpuCycle = cycleRead then
updateRegisters <= true;
end if;
elsif theCpuCycle = opcodeFetch then
updateRegisters <= true;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
theCpuCycle <= nextCpuCycle;
end if;
if reset = '0' then
theCpuCycle <= cycle2;
end if;
end if;
end process;
-- Determine the next cpu cycle. After the last cycle we always
-- go to opcodeFetch to get the next opcode.
calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, N, V, C, Z)
begin
nextCpuCycle <= opcodeFetch;
case theCpuCycle is
when opcodeFetch => nextCpuCycle <= cycle2;
when cycle2 => if opcInfo(opcBranch) = '1' then
if (N = theOpcode(5) and theOpcode(7 downto 6) = "00")
or (V = theOpcode(5) and theOpcode(7 downto 6) = "01")
or (C = theOpcode(5) and theOpcode(7 downto 6) = "10")
or (Z = theOpcode(5) and theOpcode(7 downto 6) = "11")
or (theOpcode(7 downto 0) = x"80") then -- Branch condition is true
nextCpuCycle <= cycleBranchTaken;
end if;
elsif (opcInfo(opcStackUp) = '1') then
nextCpuCycle <= cycleStack1;
elsif opcInfo(opcStackAddr) = '1' and opcInfo(opcStackData) = '1' then
nextCpuCycle <= cycleStack2;
elsif opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack1;
elsif opcInfo(opcStackData) = '1' then
nextCpuCycle <= cycleWrite;
elsif opcInfo(opcAbsolute) = '1' then
nextCpuCycle <= cycle3;
elsif opcInfo(opcIndirect) = '1' then
if opcInfo(indexX) = '1' then
nextCpuCycle <= cyclePreIndirect;
else
nextCpuCycle <= cycleIndirect;
end if;
elsif opcInfo(opcZeroPage) = '1' then
if opcInfo(opcWrite) = '1' then
if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreWrite;
else
nextCpuCycle <= cycleWrite;
end if;
else
if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreRead;
else
nextCpuCycle <= cycleRead2;
end if;
end if;
elsif opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump;
end if;
when cycle3 => nextCpuCycle <= cycleRead;
if opcInfo(opcWrite) = '1' then
if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreWrite;
else
nextCpuCycle <= cycleWrite;
end if;
end if;
if (opcInfo(opcIndirect) = '1') and (opcInfo(indexX) = '1') then
if opcInfo(opcWrite) = '1' then
nextCpuCycle <= cycleWrite;
else
nextCpuCycle <= cycleRead2;
end if;
end if;
when cyclePreIndirect => nextCpuCycle <= cycleIndirect;
when cycleIndirect => nextCpuCycle <= cycle3;
when cycleBranchTaken => if indexOut(8) /= T(7) then
nextCpuCycle <= cycleBranchPage;
end if;
when cyclePreRead => if opcInfo(opcZeroPage) = '1' then
nextCpuCycle <= cycleRead2;
end if;
when cycleRead =>
if opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump;
elsif indexOut(8) = '1' then
nextCpuCycle <= cycleRead2;
elsif opcInfo(opcRmw) = '1' then
nextCpuCycle <= cycleRmw;
if opcInfo(indexX) = '1' or opcInfo(indexY) = '1' then
nextCpuCycle <= cycleRead2;
end if;
end if;
when cycleRead2 => if opcInfo(opcRmw) = '1' then
nextCpuCycle <= cycleRmw;
end if;
when cycleRmw => nextCpuCycle <= cycleWrite;
when cyclePreWrite => nextCpuCycle <= cycleWrite;
when cycleStack1 => nextCpuCycle <= cycleRead;
if opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack2;
end if;
when cycleStack2 => nextCpuCycle <= cycleStack3;
if opcInfo(opcRti) = '1' then
nextCpuCycle <= cycleRead;
end if;
if opcInfo(opcStackData) = '0' and opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump;
end if;
when cycleStack3 => nextCpuCycle <= cycleRead;
if opcInfo(opcStackData) = '0' or opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump;
elsif opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack4;
end if;
when cycleStack4 => nextCpuCycle <= cycleRead;
when cycleJump => if opcInfo(opcIncrAfter) = '1' then
nextCpuCycle <= cycleEnd;
end if;
when others => null;
end case;
end process;
-- -----------------------------------------------------------------------
-- T register
-- -----------------------------------------------------------------------
calcT: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case theCpuCycle is
when cycle2 => T <= di;
when cycleStack1 | cycleStack2 =>
if opcInfo(opcStackUp) = '1' then
if theOpcode = x"28" or theOpcode = x"40" then -- plp or rti pulling the flags off the stack
T <= (di or "00110000"); -- Read from stack
else
T <= di;
end if;
end if;
when cycleIndirect | cycleRead | cycleRead2 => T <= di;
when others => null;
end case;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- A register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateA) = '1' then
A <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- X register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateX) = '1' then
X <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Y register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateY) = '1' then
Y <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- C flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateC) = '1' then
C <= aluC;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Z flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateZ) = '1' then
Z <= aluZ;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- I flag interupt flag
-- -----------------------------------------------------------------------
process(clk, reset)
begin
if reset = '0' then
I <= '1';
elsif rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateI) = '1' then
I <= aluInput(2);
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- D flag
-- -----------------------------------------------------------------------
process(clk, reset)
begin
if reset = '0' then
D <= '0';
elsif rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateD) = '1' then
D <= aluInput(3);
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- V flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateV) = '1' then
V <= aluV;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- N flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateN) = '1' then
N <= aluN;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Stack pointer
-- -----------------------------------------------------------------------
process(clk)
variable sIncDec : unsigned(7 downto 0);
variable updateFlag : boolean;
begin
if rising_edge(clk) then
if opcInfo(opcStackUp) = '1' then
sIncDec := S + 1;
else
sIncDec := S - 1;
end if;
if enable = '1' then
updateFlag := false;
case nextCpuCycle is
when cycleStack1 =>
if (opcInfo(opcStackUp) = '1') or (opcInfo(opcStackData) = '1') then
updateFlag := true;
end if;
when cycleStack2 => updateFlag := true;
when cycleStack3 => updateFlag := true;
when cycleStack4 => updateFlag := true;
when cycleRead => if opcInfo(opcRti) = '1' then
updateFlag := true;
end if;
when cycleWrite => if opcInfo(opcStackData) = '1' then
updateFlag := true;
end if;
when others => null;
end case;
if updateFlag then
S <= sIncDec;
end if;
end if;
if updateRegisters then
if opcInfo(opcUpdateS) = '1' then
S <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Data out
-- -----------------------------------------------------------------------
calcDo: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
doReg <= aluRmwOut;
case nextCpuCycle is
when cycleStack2 => if opcInfo(opcIRQ) = '1' and irqActive = '0' then
doReg <= myAddrIncr(15 downto 8);
else
doReg <= PC(15 downto 8);
end if;
when cycleStack3 => doReg <= PC(7 downto 0);
when cycleRmw => doReg <= di; -- Read-modify-write write old value first.
when others => null;
end case;
end if;
end if;
end process;
do <= doReg;
-- -----------------------------------------------------------------------
-- Write enable
-- -----------------------------------------------------------------------
calcWe: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
theWe <= '1';
case nextCpuCycle is
when cycleStack1 =>
if opcInfo(opcStackUp) = '0' and ((opcInfo(opcStackAddr) = '0') or (opcInfo(opcStackData) = '1')) then
theWe <= '0';
end if;
when cycleStack2 | cycleStack3 | cycleStack4 =>
if opcInfo(opcStackUp) = '0' then
theWe <= '0';
end if;
when cycleRmw => theWe <= '0';
when cycleWrite => theWe <= '0';
when others => null;
end case;
end if;
end if;
--nwe <= theWe;
end process;
nwe <= theWe;
-- -----------------------------------------------------------------------
-- Program counter
-- -----------------------------------------------------------------------
calcPC: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case theCpuCycle is
when opcodeFetch => PC <= myAddr;
when cycle2 => if irqActive = '0' then
if opcInfo(opcSecondByte) = '1' then
PC <= myAddrIncr;
else
PC <= myAddr;
end if;
end if;
when cycle3 => if opcInfo(opcAbsolute) = '1' then
PC <= myAddrIncr;
end if;
when others => null;
end case;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Address generation
-- -----------------------------------------------------------------------
calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
begin
nextAddr <= nextAddrIncr;
case theCpuCycle is
when cycle2 => if opcInfo(opcStackAddr) = '1' or opcInfo(opcStackData) = '1' then
nextAddr <= nextAddrStack;
elsif opcInfo(opcAbsolute) = '1' then
nextAddr <= nextAddrIncr;
elsif opcInfo(opcZeroPage) = '1' then
nextAddr <= nextAddrZeroPage;
elsif opcInfo(opcIndirect) = '1' then
nextAddr <= nextAddrZeroPage;
elsif opcInfo(opcSecondByte) = '1' then
nextAddr <= nextAddrIncr;
else
nextAddr <= nextAddrHold;
end if;
when cycle3 => if (opcInfo(opcIndirect) = '1') and (opcInfo(indexX) = '1') then
nextAddr <= nextAddrAbs;
else
nextAddr <= nextAddrAbsIndexed;
end if;
when cyclePreIndirect => nextAddr <= nextAddrZPIndexed;
when cycleIndirect => nextAddr <= nextAddrIncrL;
when cycleBranchTaken => nextAddr <= nextAddrRelative;
when cycleBranchPage => if T(7) = '0' then
nextAddr <= nextAddrIncrH;
else
nextAddr <= nextAddrDecrH;
end if;
when cyclePreRead => nextAddr <= nextAddrZPIndexed;
when cycleRead => nextAddr <= nextAddrPc;
if opcInfo(opcJump) = '1' then
-- Emulate 6510 bug, jmp(xxFF) fetches from same page.
-- Replace with nextAddrIncr if emulating 65C02 or later cpu.
nextAddr <= nextAddrIncr;
--nextAddr <= nextAddrIncrL;
elsif indexOut(8) = '1' then
nextAddr <= nextAddrIncrH;
elsif opcInfo(opcRmw) = '1' then
nextAddr <= nextAddrHold;
end if;
when cycleRead2 => nextAddr <= nextAddrPc;
if opcInfo(opcRmw) = '1' then
nextAddr <= nextAddrHold;
end if;
when cycleRmw => nextAddr <= nextAddrHold;
when cyclePreWrite => nextAddr <= nextAddrHold;
if opcInfo(opcZeroPage) = '1' then
nextAddr <= nextAddrZPIndexed;
elsif indexOut(8) = '1' then
nextAddr <= nextAddrIncrH;
end if;
when cycleWrite => nextAddr <= nextAddrPc;
when cycleStack1 => nextAddr <= nextAddrStack;
when cycleStack2 => nextAddr <= nextAddrStack;
when cycleStack3 => nextAddr <= nextAddrStack;
if opcInfo(opcStackData) = '0' then
nextAddr <= nextAddrPc;
end if;
when cycleStack4 => nextAddr <= nextAddrIrq;
when cycleJump => nextAddr <= nextAddrAbs;
when others => null;
end case;
if reset = '0' then
nextAddr <= nextAddrReset;
end if;
end process;
indexAlu: process(opcInfo, myAddr, T, X, Y)
begin
if opcInfo(indexX) = '1' then
indexOut <= (B"0" & T) + (B"0" & X);
elsif opcInfo(indexY) = '1' then
indexOut <= (B"0" & T) + (B"0" & Y);
elsif opcInfo(opcBranch) = '1' then
indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0));
else
indexOut <= B"0" & T;
end if;
end process;
calcAddr: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case nextAddr is
when nextAddrIncr => myAddr <= myAddrIncr;
when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH;
when nextAddrPc => myAddr <= PC;
when nextAddrIrq =>myAddr <= X"FFFE";
if nmiReg = '0' then
myAddr <= X"FFFA";
end if;
when nextAddrReset => myAddr <= X"FFFC";
when nextAddrAbs => myAddr <= di & T;
when nextAddrAbsIndexed =>--myAddr <= di & indexOut(7 downto 0);
if theOpcode = x"7C" then
myAddr <= (di & T) + (x"00"& X);
else
myAddr <= di & indexOut(7 downto 0);
end if;
when nextAddrZeroPage => myAddr <= "00000000" & di;
when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0);
when nextAddrStack => myAddr <= "00000001" & S;
when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0);
when others => null;
end case;
end if;
end if;
end process;
myAddrIncr <= myAddr + 1;
myAddrIncrH <= myAddr(15 downto 8) + 1;
myAddrDecrH <= myAddr(15 downto 8) - 1;
addr <= myAddr;
-- DMB This looked plain broken and inferred a latch
--
-- calcsync: process(clk)
-- begin
--
-- if enable = '1' then
-- case theCpuCycle is
-- when opcodeFetch => sync <= '1';
-- when others => sync <= '0';
-- end case;
-- end if;
-- end process;
sync <= '1' when theCpuCycle = opcodeFetch else '0';
sync_irq <= irqActive;
Regs <= std_logic_vector(PC) &
"00000001" & std_logic_vector(S)&
N & V & R & B & D & I & Z & C &
std_logic_vector(Y) &
std_logic_vector(X) &
std_logic_vector(A);
end architecture;
| gpl-3.0 | c0bb3ca13a4b0b6b74989d3507e131a0 | 0.549936 | 3.442067 | false | false | false | false |
DreamIP/GPStudio | support/process/roi/hdl/roi_process.vhd | 1 | 3,880 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity roi_process is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
status_reg_bypass_bit : in std_logic;
in_size_reg_in_w_reg : in std_logic_vector(11 downto 0);
in_size_reg_in_h_reg : in std_logic_vector(11 downto 0);
out_size_reg_out_w_reg : in std_logic_vector(11 downto 0);
out_size_reg_out_h_reg : in std_logic_vector(11 downto 0);
out_offset_reg_out_x_reg : in std_logic_vector(11 downto 0);
out_offset_reg_out_y_reg : in std_logic_vector(11 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end roi_process;
architecture rtl of roi_process is
constant X_COUNTER_SIZE : integer := 12;
constant Y_COUNTER_SIZE : integer := 12;
signal x_pos : unsigned(X_COUNTER_SIZE-1 downto 0);
signal y_pos : unsigned(Y_COUNTER_SIZE-1 downto 0);
signal bypass_s : std_logic;
begin
data_process : process (clk_proc, reset_n)
begin
if(reset_n='0') then
out_data <= (others => '0');
out_dv <= '0';
out_fv <= '0';
x_pos <= to_unsigned(0, X_COUNTER_SIZE);
y_pos <= to_unsigned(0, Y_COUNTER_SIZE);
bypass_s <= '0';
elsif(rising_edge(clk_proc)) then
if(in_fv = '1'
and status_reg_enable_bit = '1'
and (unsigned(out_offset_reg_out_x_reg) < unsigned(in_size_reg_in_w_reg))
and (unsigned(out_offset_reg_out_y_reg) < unsigned(in_size_reg_in_h_reg))) then
out_fv <= '1';
else
out_fv <= '0';
end if;
out_dv <= '0';
if(in_fv = '0') then
x_pos <= to_unsigned(0, X_COUNTER_SIZE);
y_pos <= to_unsigned(0, Y_COUNTER_SIZE);
bypass_s <= status_reg_bypass_bit;
else
if(in_dv = '1' and status_reg_enable_bit = '1') then
x_pos <= x_pos + 1;
if(x_pos=unsigned(in_size_reg_in_w_reg)-1) then
y_pos <= y_pos + 1;
x_pos <= to_unsigned(0, X_COUNTER_SIZE);
end if;
if(bypass_s = '0') then
if(y_pos >= unsigned(out_offset_reg_out_y_reg)
and y_pos < (unsigned(out_offset_reg_out_y_reg) + unsigned(out_size_reg_out_h_reg))
and x_pos >= unsigned(out_offset_reg_out_x_reg)
and x_pos < (unsigned(out_offset_reg_out_x_reg) + unsigned(out_size_reg_out_w_reg))) then
out_dv <= '1';
out_data <= in_data;
end if;
else
out_dv <= '1';
out_data <= in_data;
end if;
end if;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | 738915819c4f998fa6bf4de16083feaf | 0.431959 | 3.730769 | false | false | false | false |
hoglet67/ElectronFpga | src/common/ROM/RomBasic2.vhd | 1 | 803,555 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity RomBasic2 is
port (
clk : in std_logic;
addr : in std_logic_vector(13 downto 0);
data : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of RomBasic2 is
signal rom_addr : std_logic_vector(13 downto 0);
begin
p_addr : process(addr)
begin
rom_addr <= (others => '0');
rom_addr(13 downto 0) <= addr;
end process;
p_rom : process
begin
wait until rising_edge(clk);
data <= (others => '0');
case rom_addr is
when "00" & x"000" => data <= x"c9";
when "00" & x"001" => data <= x"01";
when "00" & x"002" => data <= x"f0";
when "00" & x"003" => data <= x"1f";
when "00" & x"004" => data <= x"60";
when "00" & x"005" => data <= x"ea";
when "00" & x"006" => data <= x"60";
when "00" & x"007" => data <= x"0e";
when "00" & x"008" => data <= x"01";
when "00" & x"009" => data <= x"42";
when "00" & x"00a" => data <= x"41";
when "00" & x"00b" => data <= x"53";
when "00" & x"00c" => data <= x"49";
when "00" & x"00d" => data <= x"43";
when "00" & x"00e" => data <= x"00";
when "00" & x"00f" => data <= x"28";
when "00" & x"010" => data <= x"43";
when "00" & x"011" => data <= x"29";
when "00" & x"012" => data <= x"31";
when "00" & x"013" => data <= x"39";
when "00" & x"014" => data <= x"38";
when "00" & x"015" => data <= x"32";
when "00" & x"016" => data <= x"20";
when "00" & x"017" => data <= x"41";
when "00" & x"018" => data <= x"63";
when "00" & x"019" => data <= x"6f";
when "00" & x"01a" => data <= x"72";
when "00" & x"01b" => data <= x"6e";
when "00" & x"01c" => data <= x"0a";
when "00" & x"01d" => data <= x"0d";
when "00" & x"01e" => data <= x"00";
when "00" & x"01f" => data <= x"00";
when "00" & x"020" => data <= x"80";
when "00" & x"021" => data <= x"00";
when "00" & x"022" => data <= x"00";
when "00" & x"023" => data <= x"a9";
when "00" & x"024" => data <= x"84";
when "00" & x"025" => data <= x"20";
when "00" & x"026" => data <= x"f4";
when "00" & x"027" => data <= x"ff";
when "00" & x"028" => data <= x"86";
when "00" & x"029" => data <= x"06";
when "00" & x"02a" => data <= x"84";
when "00" & x"02b" => data <= x"07";
when "00" & x"02c" => data <= x"a9";
when "00" & x"02d" => data <= x"83";
when "00" & x"02e" => data <= x"20";
when "00" & x"02f" => data <= x"f4";
when "00" & x"030" => data <= x"ff";
when "00" & x"031" => data <= x"84";
when "00" & x"032" => data <= x"18";
when "00" & x"033" => data <= x"a2";
when "00" & x"034" => data <= x"00";
when "00" & x"035" => data <= x"86";
when "00" & x"036" => data <= x"1f";
when "00" & x"037" => data <= x"8e";
when "00" & x"038" => data <= x"02";
when "00" & x"039" => data <= x"04";
when "00" & x"03a" => data <= x"8e";
when "00" & x"03b" => data <= x"03";
when "00" & x"03c" => data <= x"04";
when "00" & x"03d" => data <= x"ca";
when "00" & x"03e" => data <= x"86";
when "00" & x"03f" => data <= x"23";
when "00" & x"040" => data <= x"a2";
when "00" & x"041" => data <= x"0a";
when "00" & x"042" => data <= x"8e";
when "00" & x"043" => data <= x"00";
when "00" & x"044" => data <= x"04";
when "00" & x"045" => data <= x"ca";
when "00" & x"046" => data <= x"8e";
when "00" & x"047" => data <= x"01";
when "00" & x"048" => data <= x"04";
when "00" & x"049" => data <= x"a9";
when "00" & x"04a" => data <= x"01";
when "00" & x"04b" => data <= x"25";
when "00" & x"04c" => data <= x"11";
when "00" & x"04d" => data <= x"05";
when "00" & x"04e" => data <= x"0d";
when "00" & x"04f" => data <= x"05";
when "00" & x"050" => data <= x"0e";
when "00" & x"051" => data <= x"05";
when "00" & x"052" => data <= x"0f";
when "00" & x"053" => data <= x"05";
when "00" & x"054" => data <= x"10";
when "00" & x"055" => data <= x"d0";
when "00" & x"056" => data <= x"0c";
when "00" & x"057" => data <= x"a9";
when "00" & x"058" => data <= x"41";
when "00" & x"059" => data <= x"85";
when "00" & x"05a" => data <= x"0d";
when "00" & x"05b" => data <= x"a9";
when "00" & x"05c" => data <= x"52";
when "00" & x"05d" => data <= x"85";
when "00" & x"05e" => data <= x"0e";
when "00" & x"05f" => data <= x"a9";
when "00" & x"060" => data <= x"57";
when "00" & x"061" => data <= x"85";
when "00" & x"062" => data <= x"0f";
when "00" & x"063" => data <= x"a9";
when "00" & x"064" => data <= x"02";
when "00" & x"065" => data <= x"8d";
when "00" & x"066" => data <= x"02";
when "00" & x"067" => data <= x"02";
when "00" & x"068" => data <= x"a9";
when "00" & x"069" => data <= x"b4";
when "00" & x"06a" => data <= x"8d";
when "00" & x"06b" => data <= x"03";
when "00" & x"06c" => data <= x"02";
when "00" & x"06d" => data <= x"58";
when "00" & x"06e" => data <= x"4c";
when "00" & x"06f" => data <= x"dd";
when "00" & x"070" => data <= x"8a";
when "00" & x"071" => data <= x"41";
when "00" & x"072" => data <= x"4e";
when "00" & x"073" => data <= x"44";
when "00" & x"074" => data <= x"80";
when "00" & x"075" => data <= x"00";
when "00" & x"076" => data <= x"41";
when "00" & x"077" => data <= x"42";
when "00" & x"078" => data <= x"53";
when "00" & x"079" => data <= x"94";
when "00" & x"07a" => data <= x"00";
when "00" & x"07b" => data <= x"41";
when "00" & x"07c" => data <= x"43";
when "00" & x"07d" => data <= x"53";
when "00" & x"07e" => data <= x"95";
when "00" & x"07f" => data <= x"00";
when "00" & x"080" => data <= x"41";
when "00" & x"081" => data <= x"44";
when "00" & x"082" => data <= x"56";
when "00" & x"083" => data <= x"41";
when "00" & x"084" => data <= x"4c";
when "00" & x"085" => data <= x"96";
when "00" & x"086" => data <= x"00";
when "00" & x"087" => data <= x"41";
when "00" & x"088" => data <= x"53";
when "00" & x"089" => data <= x"43";
when "00" & x"08a" => data <= x"97";
when "00" & x"08b" => data <= x"00";
when "00" & x"08c" => data <= x"41";
when "00" & x"08d" => data <= x"53";
when "00" & x"08e" => data <= x"4e";
when "00" & x"08f" => data <= x"98";
when "00" & x"090" => data <= x"00";
when "00" & x"091" => data <= x"41";
when "00" & x"092" => data <= x"54";
when "00" & x"093" => data <= x"4e";
when "00" & x"094" => data <= x"99";
when "00" & x"095" => data <= x"00";
when "00" & x"096" => data <= x"41";
when "00" & x"097" => data <= x"55";
when "00" & x"098" => data <= x"54";
when "00" & x"099" => data <= x"4f";
when "00" & x"09a" => data <= x"c6";
when "00" & x"09b" => data <= x"10";
when "00" & x"09c" => data <= x"42";
when "00" & x"09d" => data <= x"47";
when "00" & x"09e" => data <= x"45";
when "00" & x"09f" => data <= x"54";
when "00" & x"0a0" => data <= x"9a";
when "00" & x"0a1" => data <= x"01";
when "00" & x"0a2" => data <= x"42";
when "00" & x"0a3" => data <= x"50";
when "00" & x"0a4" => data <= x"55";
when "00" & x"0a5" => data <= x"54";
when "00" & x"0a6" => data <= x"d5";
when "00" & x"0a7" => data <= x"03";
when "00" & x"0a8" => data <= x"43";
when "00" & x"0a9" => data <= x"4f";
when "00" & x"0aa" => data <= x"4c";
when "00" & x"0ab" => data <= x"4f";
when "00" & x"0ac" => data <= x"55";
when "00" & x"0ad" => data <= x"52";
when "00" & x"0ae" => data <= x"fb";
when "00" & x"0af" => data <= x"02";
when "00" & x"0b0" => data <= x"43";
when "00" & x"0b1" => data <= x"41";
when "00" & x"0b2" => data <= x"4c";
when "00" & x"0b3" => data <= x"4c";
when "00" & x"0b4" => data <= x"d6";
when "00" & x"0b5" => data <= x"02";
when "00" & x"0b6" => data <= x"43";
when "00" & x"0b7" => data <= x"48";
when "00" & x"0b8" => data <= x"41";
when "00" & x"0b9" => data <= x"49";
when "00" & x"0ba" => data <= x"4e";
when "00" & x"0bb" => data <= x"d7";
when "00" & x"0bc" => data <= x"02";
when "00" & x"0bd" => data <= x"43";
when "00" & x"0be" => data <= x"48";
when "00" & x"0bf" => data <= x"52";
when "00" & x"0c0" => data <= x"24";
when "00" & x"0c1" => data <= x"bd";
when "00" & x"0c2" => data <= x"00";
when "00" & x"0c3" => data <= x"43";
when "00" & x"0c4" => data <= x"4c";
when "00" & x"0c5" => data <= x"45";
when "00" & x"0c6" => data <= x"41";
when "00" & x"0c7" => data <= x"52";
when "00" & x"0c8" => data <= x"d8";
when "00" & x"0c9" => data <= x"01";
when "00" & x"0ca" => data <= x"43";
when "00" & x"0cb" => data <= x"4c";
when "00" & x"0cc" => data <= x"4f";
when "00" & x"0cd" => data <= x"53";
when "00" & x"0ce" => data <= x"45";
when "00" & x"0cf" => data <= x"d9";
when "00" & x"0d0" => data <= x"03";
when "00" & x"0d1" => data <= x"43";
when "00" & x"0d2" => data <= x"4c";
when "00" & x"0d3" => data <= x"47";
when "00" & x"0d4" => data <= x"da";
when "00" & x"0d5" => data <= x"01";
when "00" & x"0d6" => data <= x"43";
when "00" & x"0d7" => data <= x"4c";
when "00" & x"0d8" => data <= x"53";
when "00" & x"0d9" => data <= x"db";
when "00" & x"0da" => data <= x"01";
when "00" & x"0db" => data <= x"43";
when "00" & x"0dc" => data <= x"4f";
when "00" & x"0dd" => data <= x"53";
when "00" & x"0de" => data <= x"9b";
when "00" & x"0df" => data <= x"00";
when "00" & x"0e0" => data <= x"43";
when "00" & x"0e1" => data <= x"4f";
when "00" & x"0e2" => data <= x"55";
when "00" & x"0e3" => data <= x"4e";
when "00" & x"0e4" => data <= x"54";
when "00" & x"0e5" => data <= x"9c";
when "00" & x"0e6" => data <= x"01";
when "00" & x"0e7" => data <= x"44";
when "00" & x"0e8" => data <= x"41";
when "00" & x"0e9" => data <= x"54";
when "00" & x"0ea" => data <= x"41";
when "00" & x"0eb" => data <= x"dc";
when "00" & x"0ec" => data <= x"20";
when "00" & x"0ed" => data <= x"44";
when "00" & x"0ee" => data <= x"45";
when "00" & x"0ef" => data <= x"47";
when "00" & x"0f0" => data <= x"9d";
when "00" & x"0f1" => data <= x"00";
when "00" & x"0f2" => data <= x"44";
when "00" & x"0f3" => data <= x"45";
when "00" & x"0f4" => data <= x"46";
when "00" & x"0f5" => data <= x"dd";
when "00" & x"0f6" => data <= x"00";
when "00" & x"0f7" => data <= x"44";
when "00" & x"0f8" => data <= x"45";
when "00" & x"0f9" => data <= x"4c";
when "00" & x"0fa" => data <= x"45";
when "00" & x"0fb" => data <= x"54";
when "00" & x"0fc" => data <= x"45";
when "00" & x"0fd" => data <= x"c7";
when "00" & x"0fe" => data <= x"10";
when "00" & x"0ff" => data <= x"44";
when "00" & x"100" => data <= x"49";
when "00" & x"101" => data <= x"56";
when "00" & x"102" => data <= x"81";
when "00" & x"103" => data <= x"00";
when "00" & x"104" => data <= x"44";
when "00" & x"105" => data <= x"49";
when "00" & x"106" => data <= x"4d";
when "00" & x"107" => data <= x"de";
when "00" & x"108" => data <= x"02";
when "00" & x"109" => data <= x"44";
when "00" & x"10a" => data <= x"52";
when "00" & x"10b" => data <= x"41";
when "00" & x"10c" => data <= x"57";
when "00" & x"10d" => data <= x"df";
when "00" & x"10e" => data <= x"02";
when "00" & x"10f" => data <= x"45";
when "00" & x"110" => data <= x"4e";
when "00" & x"111" => data <= x"44";
when "00" & x"112" => data <= x"50";
when "00" & x"113" => data <= x"52";
when "00" & x"114" => data <= x"4f";
when "00" & x"115" => data <= x"43";
when "00" & x"116" => data <= x"e1";
when "00" & x"117" => data <= x"01";
when "00" & x"118" => data <= x"45";
when "00" & x"119" => data <= x"4e";
when "00" & x"11a" => data <= x"44";
when "00" & x"11b" => data <= x"e0";
when "00" & x"11c" => data <= x"01";
when "00" & x"11d" => data <= x"45";
when "00" & x"11e" => data <= x"4e";
when "00" & x"11f" => data <= x"56";
when "00" & x"120" => data <= x"45";
when "00" & x"121" => data <= x"4c";
when "00" & x"122" => data <= x"4f";
when "00" & x"123" => data <= x"50";
when "00" & x"124" => data <= x"45";
when "00" & x"125" => data <= x"e2";
when "00" & x"126" => data <= x"02";
when "00" & x"127" => data <= x"45";
when "00" & x"128" => data <= x"4c";
when "00" & x"129" => data <= x"53";
when "00" & x"12a" => data <= x"45";
when "00" & x"12b" => data <= x"8b";
when "00" & x"12c" => data <= x"14";
when "00" & x"12d" => data <= x"45";
when "00" & x"12e" => data <= x"56";
when "00" & x"12f" => data <= x"41";
when "00" & x"130" => data <= x"4c";
when "00" & x"131" => data <= x"a0";
when "00" & x"132" => data <= x"00";
when "00" & x"133" => data <= x"45";
when "00" & x"134" => data <= x"52";
when "00" & x"135" => data <= x"4c";
when "00" & x"136" => data <= x"9e";
when "00" & x"137" => data <= x"01";
when "00" & x"138" => data <= x"45";
when "00" & x"139" => data <= x"52";
when "00" & x"13a" => data <= x"52";
when "00" & x"13b" => data <= x"4f";
when "00" & x"13c" => data <= x"52";
when "00" & x"13d" => data <= x"85";
when "00" & x"13e" => data <= x"04";
when "00" & x"13f" => data <= x"45";
when "00" & x"140" => data <= x"4f";
when "00" & x"141" => data <= x"46";
when "00" & x"142" => data <= x"c5";
when "00" & x"143" => data <= x"01";
when "00" & x"144" => data <= x"45";
when "00" & x"145" => data <= x"4f";
when "00" & x"146" => data <= x"52";
when "00" & x"147" => data <= x"82";
when "00" & x"148" => data <= x"00";
when "00" & x"149" => data <= x"45";
when "00" & x"14a" => data <= x"52";
when "00" & x"14b" => data <= x"52";
when "00" & x"14c" => data <= x"9f";
when "00" & x"14d" => data <= x"01";
when "00" & x"14e" => data <= x"45";
when "00" & x"14f" => data <= x"58";
when "00" & x"150" => data <= x"50";
when "00" & x"151" => data <= x"a1";
when "00" & x"152" => data <= x"00";
when "00" & x"153" => data <= x"45";
when "00" & x"154" => data <= x"58";
when "00" & x"155" => data <= x"54";
when "00" & x"156" => data <= x"a2";
when "00" & x"157" => data <= x"01";
when "00" & x"158" => data <= x"46";
when "00" & x"159" => data <= x"4f";
when "00" & x"15a" => data <= x"52";
when "00" & x"15b" => data <= x"e3";
when "00" & x"15c" => data <= x"02";
when "00" & x"15d" => data <= x"46";
when "00" & x"15e" => data <= x"41";
when "00" & x"15f" => data <= x"4c";
when "00" & x"160" => data <= x"53";
when "00" & x"161" => data <= x"45";
when "00" & x"162" => data <= x"a3";
when "00" & x"163" => data <= x"01";
when "00" & x"164" => data <= x"46";
when "00" & x"165" => data <= x"4e";
when "00" & x"166" => data <= x"a4";
when "00" & x"167" => data <= x"08";
when "00" & x"168" => data <= x"47";
when "00" & x"169" => data <= x"4f";
when "00" & x"16a" => data <= x"54";
when "00" & x"16b" => data <= x"4f";
when "00" & x"16c" => data <= x"e5";
when "00" & x"16d" => data <= x"12";
when "00" & x"16e" => data <= x"47";
when "00" & x"16f" => data <= x"45";
when "00" & x"170" => data <= x"54";
when "00" & x"171" => data <= x"24";
when "00" & x"172" => data <= x"be";
when "00" & x"173" => data <= x"00";
when "00" & x"174" => data <= x"47";
when "00" & x"175" => data <= x"45";
when "00" & x"176" => data <= x"54";
when "00" & x"177" => data <= x"a5";
when "00" & x"178" => data <= x"00";
when "00" & x"179" => data <= x"47";
when "00" & x"17a" => data <= x"4f";
when "00" & x"17b" => data <= x"53";
when "00" & x"17c" => data <= x"55";
when "00" & x"17d" => data <= x"42";
when "00" & x"17e" => data <= x"e4";
when "00" & x"17f" => data <= x"12";
when "00" & x"180" => data <= x"47";
when "00" & x"181" => data <= x"43";
when "00" & x"182" => data <= x"4f";
when "00" & x"183" => data <= x"4c";
when "00" & x"184" => data <= x"e6";
when "00" & x"185" => data <= x"02";
when "00" & x"186" => data <= x"48";
when "00" & x"187" => data <= x"49";
when "00" & x"188" => data <= x"4d";
when "00" & x"189" => data <= x"45";
when "00" & x"18a" => data <= x"4d";
when "00" & x"18b" => data <= x"93";
when "00" & x"18c" => data <= x"43";
when "00" & x"18d" => data <= x"49";
when "00" & x"18e" => data <= x"4e";
when "00" & x"18f" => data <= x"50";
when "00" & x"190" => data <= x"55";
when "00" & x"191" => data <= x"54";
when "00" & x"192" => data <= x"e8";
when "00" & x"193" => data <= x"02";
when "00" & x"194" => data <= x"49";
when "00" & x"195" => data <= x"46";
when "00" & x"196" => data <= x"e7";
when "00" & x"197" => data <= x"02";
when "00" & x"198" => data <= x"49";
when "00" & x"199" => data <= x"4e";
when "00" & x"19a" => data <= x"4b";
when "00" & x"19b" => data <= x"45";
when "00" & x"19c" => data <= x"59";
when "00" & x"19d" => data <= x"24";
when "00" & x"19e" => data <= x"bf";
when "00" & x"19f" => data <= x"00";
when "00" & x"1a0" => data <= x"49";
when "00" & x"1a1" => data <= x"4e";
when "00" & x"1a2" => data <= x"4b";
when "00" & x"1a3" => data <= x"45";
when "00" & x"1a4" => data <= x"59";
when "00" & x"1a5" => data <= x"a6";
when "00" & x"1a6" => data <= x"00";
when "00" & x"1a7" => data <= x"49";
when "00" & x"1a8" => data <= x"4e";
when "00" & x"1a9" => data <= x"54";
when "00" & x"1aa" => data <= x"a8";
when "00" & x"1ab" => data <= x"00";
when "00" & x"1ac" => data <= x"49";
when "00" & x"1ad" => data <= x"4e";
when "00" & x"1ae" => data <= x"53";
when "00" & x"1af" => data <= x"54";
when "00" & x"1b0" => data <= x"52";
when "00" & x"1b1" => data <= x"28";
when "00" & x"1b2" => data <= x"a7";
when "00" & x"1b3" => data <= x"00";
when "00" & x"1b4" => data <= x"4c";
when "00" & x"1b5" => data <= x"49";
when "00" & x"1b6" => data <= x"53";
when "00" & x"1b7" => data <= x"54";
when "00" & x"1b8" => data <= x"c9";
when "00" & x"1b9" => data <= x"10";
when "00" & x"1ba" => data <= x"4c";
when "00" & x"1bb" => data <= x"49";
when "00" & x"1bc" => data <= x"4e";
when "00" & x"1bd" => data <= x"45";
when "00" & x"1be" => data <= x"86";
when "00" & x"1bf" => data <= x"00";
when "00" & x"1c0" => data <= x"4c";
when "00" & x"1c1" => data <= x"4f";
when "00" & x"1c2" => data <= x"41";
when "00" & x"1c3" => data <= x"44";
when "00" & x"1c4" => data <= x"c8";
when "00" & x"1c5" => data <= x"02";
when "00" & x"1c6" => data <= x"4c";
when "00" & x"1c7" => data <= x"4f";
when "00" & x"1c8" => data <= x"4d";
when "00" & x"1c9" => data <= x"45";
when "00" & x"1ca" => data <= x"4d";
when "00" & x"1cb" => data <= x"92";
when "00" & x"1cc" => data <= x"43";
when "00" & x"1cd" => data <= x"4c";
when "00" & x"1ce" => data <= x"4f";
when "00" & x"1cf" => data <= x"43";
when "00" & x"1d0" => data <= x"41";
when "00" & x"1d1" => data <= x"4c";
when "00" & x"1d2" => data <= x"ea";
when "00" & x"1d3" => data <= x"02";
when "00" & x"1d4" => data <= x"4c";
when "00" & x"1d5" => data <= x"45";
when "00" & x"1d6" => data <= x"46";
when "00" & x"1d7" => data <= x"54";
when "00" & x"1d8" => data <= x"24";
when "00" & x"1d9" => data <= x"28";
when "00" & x"1da" => data <= x"c0";
when "00" & x"1db" => data <= x"00";
when "00" & x"1dc" => data <= x"4c";
when "00" & x"1dd" => data <= x"45";
when "00" & x"1de" => data <= x"4e";
when "00" & x"1df" => data <= x"a9";
when "00" & x"1e0" => data <= x"00";
when "00" & x"1e1" => data <= x"4c";
when "00" & x"1e2" => data <= x"45";
when "00" & x"1e3" => data <= x"54";
when "00" & x"1e4" => data <= x"e9";
when "00" & x"1e5" => data <= x"04";
when "00" & x"1e6" => data <= x"4c";
when "00" & x"1e7" => data <= x"4f";
when "00" & x"1e8" => data <= x"47";
when "00" & x"1e9" => data <= x"ab";
when "00" & x"1ea" => data <= x"00";
when "00" & x"1eb" => data <= x"4c";
when "00" & x"1ec" => data <= x"4e";
when "00" & x"1ed" => data <= x"aa";
when "00" & x"1ee" => data <= x"00";
when "00" & x"1ef" => data <= x"4d";
when "00" & x"1f0" => data <= x"49";
when "00" & x"1f1" => data <= x"44";
when "00" & x"1f2" => data <= x"24";
when "00" & x"1f3" => data <= x"28";
when "00" & x"1f4" => data <= x"c1";
when "00" & x"1f5" => data <= x"00";
when "00" & x"1f6" => data <= x"4d";
when "00" & x"1f7" => data <= x"4f";
when "00" & x"1f8" => data <= x"44";
when "00" & x"1f9" => data <= x"45";
when "00" & x"1fa" => data <= x"eb";
when "00" & x"1fb" => data <= x"02";
when "00" & x"1fc" => data <= x"4d";
when "00" & x"1fd" => data <= x"4f";
when "00" & x"1fe" => data <= x"44";
when "00" & x"1ff" => data <= x"83";
when "00" & x"200" => data <= x"00";
when "00" & x"201" => data <= x"4d";
when "00" & x"202" => data <= x"4f";
when "00" & x"203" => data <= x"56";
when "00" & x"204" => data <= x"45";
when "00" & x"205" => data <= x"ec";
when "00" & x"206" => data <= x"02";
when "00" & x"207" => data <= x"4e";
when "00" & x"208" => data <= x"45";
when "00" & x"209" => data <= x"58";
when "00" & x"20a" => data <= x"54";
when "00" & x"20b" => data <= x"ed";
when "00" & x"20c" => data <= x"02";
when "00" & x"20d" => data <= x"4e";
when "00" & x"20e" => data <= x"45";
when "00" & x"20f" => data <= x"57";
when "00" & x"210" => data <= x"ca";
when "00" & x"211" => data <= x"01";
when "00" & x"212" => data <= x"4e";
when "00" & x"213" => data <= x"4f";
when "00" & x"214" => data <= x"54";
when "00" & x"215" => data <= x"ac";
when "00" & x"216" => data <= x"00";
when "00" & x"217" => data <= x"4f";
when "00" & x"218" => data <= x"4c";
when "00" & x"219" => data <= x"44";
when "00" & x"21a" => data <= x"cb";
when "00" & x"21b" => data <= x"01";
when "00" & x"21c" => data <= x"4f";
when "00" & x"21d" => data <= x"4e";
when "00" & x"21e" => data <= x"ee";
when "00" & x"21f" => data <= x"02";
when "00" & x"220" => data <= x"4f";
when "00" & x"221" => data <= x"46";
when "00" & x"222" => data <= x"46";
when "00" & x"223" => data <= x"87";
when "00" & x"224" => data <= x"00";
when "00" & x"225" => data <= x"4f";
when "00" & x"226" => data <= x"52";
when "00" & x"227" => data <= x"84";
when "00" & x"228" => data <= x"00";
when "00" & x"229" => data <= x"4f";
when "00" & x"22a" => data <= x"50";
when "00" & x"22b" => data <= x"45";
when "00" & x"22c" => data <= x"4e";
when "00" & x"22d" => data <= x"49";
when "00" & x"22e" => data <= x"4e";
when "00" & x"22f" => data <= x"8e";
when "00" & x"230" => data <= x"00";
when "00" & x"231" => data <= x"4f";
when "00" & x"232" => data <= x"50";
when "00" & x"233" => data <= x"45";
when "00" & x"234" => data <= x"4e";
when "00" & x"235" => data <= x"4f";
when "00" & x"236" => data <= x"55";
when "00" & x"237" => data <= x"54";
when "00" & x"238" => data <= x"ae";
when "00" & x"239" => data <= x"00";
when "00" & x"23a" => data <= x"4f";
when "00" & x"23b" => data <= x"50";
when "00" & x"23c" => data <= x"45";
when "00" & x"23d" => data <= x"4e";
when "00" & x"23e" => data <= x"55";
when "00" & x"23f" => data <= x"50";
when "00" & x"240" => data <= x"ad";
when "00" & x"241" => data <= x"00";
when "00" & x"242" => data <= x"4f";
when "00" & x"243" => data <= x"53";
when "00" & x"244" => data <= x"43";
when "00" & x"245" => data <= x"4c";
when "00" & x"246" => data <= x"49";
when "00" & x"247" => data <= x"ff";
when "00" & x"248" => data <= x"02";
when "00" & x"249" => data <= x"50";
when "00" & x"24a" => data <= x"52";
when "00" & x"24b" => data <= x"49";
when "00" & x"24c" => data <= x"4e";
when "00" & x"24d" => data <= x"54";
when "00" & x"24e" => data <= x"f1";
when "00" & x"24f" => data <= x"02";
when "00" & x"250" => data <= x"50";
when "00" & x"251" => data <= x"41";
when "00" & x"252" => data <= x"47";
when "00" & x"253" => data <= x"45";
when "00" & x"254" => data <= x"90";
when "00" & x"255" => data <= x"43";
when "00" & x"256" => data <= x"50";
when "00" & x"257" => data <= x"54";
when "00" & x"258" => data <= x"52";
when "00" & x"259" => data <= x"8f";
when "00" & x"25a" => data <= x"43";
when "00" & x"25b" => data <= x"50";
when "00" & x"25c" => data <= x"49";
when "00" & x"25d" => data <= x"af";
when "00" & x"25e" => data <= x"01";
when "00" & x"25f" => data <= x"50";
when "00" & x"260" => data <= x"4c";
when "00" & x"261" => data <= x"4f";
when "00" & x"262" => data <= x"54";
when "00" & x"263" => data <= x"f0";
when "00" & x"264" => data <= x"02";
when "00" & x"265" => data <= x"50";
when "00" & x"266" => data <= x"4f";
when "00" & x"267" => data <= x"49";
when "00" & x"268" => data <= x"4e";
when "00" & x"269" => data <= x"54";
when "00" & x"26a" => data <= x"28";
when "00" & x"26b" => data <= x"b0";
when "00" & x"26c" => data <= x"00";
when "00" & x"26d" => data <= x"50";
when "00" & x"26e" => data <= x"52";
when "00" & x"26f" => data <= x"4f";
when "00" & x"270" => data <= x"43";
when "00" & x"271" => data <= x"f2";
when "00" & x"272" => data <= x"0a";
when "00" & x"273" => data <= x"50";
when "00" & x"274" => data <= x"4f";
when "00" & x"275" => data <= x"53";
when "00" & x"276" => data <= x"b1";
when "00" & x"277" => data <= x"01";
when "00" & x"278" => data <= x"52";
when "00" & x"279" => data <= x"45";
when "00" & x"27a" => data <= x"54";
when "00" & x"27b" => data <= x"55";
when "00" & x"27c" => data <= x"52";
when "00" & x"27d" => data <= x"4e";
when "00" & x"27e" => data <= x"f8";
when "00" & x"27f" => data <= x"01";
when "00" & x"280" => data <= x"52";
when "00" & x"281" => data <= x"45";
when "00" & x"282" => data <= x"50";
when "00" & x"283" => data <= x"45";
when "00" & x"284" => data <= x"41";
when "00" & x"285" => data <= x"54";
when "00" & x"286" => data <= x"f5";
when "00" & x"287" => data <= x"00";
when "00" & x"288" => data <= x"52";
when "00" & x"289" => data <= x"45";
when "00" & x"28a" => data <= x"50";
when "00" & x"28b" => data <= x"4f";
when "00" & x"28c" => data <= x"52";
when "00" & x"28d" => data <= x"54";
when "00" & x"28e" => data <= x"f6";
when "00" & x"28f" => data <= x"01";
when "00" & x"290" => data <= x"52";
when "00" & x"291" => data <= x"45";
when "00" & x"292" => data <= x"41";
when "00" & x"293" => data <= x"44";
when "00" & x"294" => data <= x"f3";
when "00" & x"295" => data <= x"02";
when "00" & x"296" => data <= x"52";
when "00" & x"297" => data <= x"45";
when "00" & x"298" => data <= x"4d";
when "00" & x"299" => data <= x"f4";
when "00" & x"29a" => data <= x"20";
when "00" & x"29b" => data <= x"52";
when "00" & x"29c" => data <= x"55";
when "00" & x"29d" => data <= x"4e";
when "00" & x"29e" => data <= x"f9";
when "00" & x"29f" => data <= x"01";
when "00" & x"2a0" => data <= x"52";
when "00" & x"2a1" => data <= x"41";
when "00" & x"2a2" => data <= x"44";
when "00" & x"2a3" => data <= x"b2";
when "00" & x"2a4" => data <= x"00";
when "00" & x"2a5" => data <= x"52";
when "00" & x"2a6" => data <= x"45";
when "00" & x"2a7" => data <= x"53";
when "00" & x"2a8" => data <= x"54";
when "00" & x"2a9" => data <= x"4f";
when "00" & x"2aa" => data <= x"52";
when "00" & x"2ab" => data <= x"45";
when "00" & x"2ac" => data <= x"f7";
when "00" & x"2ad" => data <= x"12";
when "00" & x"2ae" => data <= x"52";
when "00" & x"2af" => data <= x"49";
when "00" & x"2b0" => data <= x"47";
when "00" & x"2b1" => data <= x"48";
when "00" & x"2b2" => data <= x"54";
when "00" & x"2b3" => data <= x"24";
when "00" & x"2b4" => data <= x"28";
when "00" & x"2b5" => data <= x"c2";
when "00" & x"2b6" => data <= x"00";
when "00" & x"2b7" => data <= x"52";
when "00" & x"2b8" => data <= x"4e";
when "00" & x"2b9" => data <= x"44";
when "00" & x"2ba" => data <= x"b3";
when "00" & x"2bb" => data <= x"01";
when "00" & x"2bc" => data <= x"52";
when "00" & x"2bd" => data <= x"45";
when "00" & x"2be" => data <= x"4e";
when "00" & x"2bf" => data <= x"55";
when "00" & x"2c0" => data <= x"4d";
when "00" & x"2c1" => data <= x"42";
when "00" & x"2c2" => data <= x"45";
when "00" & x"2c3" => data <= x"52";
when "00" & x"2c4" => data <= x"cc";
when "00" & x"2c5" => data <= x"10";
when "00" & x"2c6" => data <= x"53";
when "00" & x"2c7" => data <= x"54";
when "00" & x"2c8" => data <= x"45";
when "00" & x"2c9" => data <= x"50";
when "00" & x"2ca" => data <= x"88";
when "00" & x"2cb" => data <= x"00";
when "00" & x"2cc" => data <= x"53";
when "00" & x"2cd" => data <= x"41";
when "00" & x"2ce" => data <= x"56";
when "00" & x"2cf" => data <= x"45";
when "00" & x"2d0" => data <= x"cd";
when "00" & x"2d1" => data <= x"02";
when "00" & x"2d2" => data <= x"53";
when "00" & x"2d3" => data <= x"47";
when "00" & x"2d4" => data <= x"4e";
when "00" & x"2d5" => data <= x"b4";
when "00" & x"2d6" => data <= x"00";
when "00" & x"2d7" => data <= x"53";
when "00" & x"2d8" => data <= x"49";
when "00" & x"2d9" => data <= x"4e";
when "00" & x"2da" => data <= x"b5";
when "00" & x"2db" => data <= x"00";
when "00" & x"2dc" => data <= x"53";
when "00" & x"2dd" => data <= x"51";
when "00" & x"2de" => data <= x"52";
when "00" & x"2df" => data <= x"b6";
when "00" & x"2e0" => data <= x"00";
when "00" & x"2e1" => data <= x"53";
when "00" & x"2e2" => data <= x"50";
when "00" & x"2e3" => data <= x"43";
when "00" & x"2e4" => data <= x"89";
when "00" & x"2e5" => data <= x"00";
when "00" & x"2e6" => data <= x"53";
when "00" & x"2e7" => data <= x"54";
when "00" & x"2e8" => data <= x"52";
when "00" & x"2e9" => data <= x"24";
when "00" & x"2ea" => data <= x"c3";
when "00" & x"2eb" => data <= x"00";
when "00" & x"2ec" => data <= x"53";
when "00" & x"2ed" => data <= x"54";
when "00" & x"2ee" => data <= x"52";
when "00" & x"2ef" => data <= x"49";
when "00" & x"2f0" => data <= x"4e";
when "00" & x"2f1" => data <= x"47";
when "00" & x"2f2" => data <= x"24";
when "00" & x"2f3" => data <= x"28";
when "00" & x"2f4" => data <= x"c4";
when "00" & x"2f5" => data <= x"00";
when "00" & x"2f6" => data <= x"53";
when "00" & x"2f7" => data <= x"4f";
when "00" & x"2f8" => data <= x"55";
when "00" & x"2f9" => data <= x"4e";
when "00" & x"2fa" => data <= x"44";
when "00" & x"2fb" => data <= x"d4";
when "00" & x"2fc" => data <= x"02";
when "00" & x"2fd" => data <= x"53";
when "00" & x"2fe" => data <= x"54";
when "00" & x"2ff" => data <= x"4f";
when "00" & x"300" => data <= x"50";
when "00" & x"301" => data <= x"fa";
when "00" & x"302" => data <= x"01";
when "00" & x"303" => data <= x"54";
when "00" & x"304" => data <= x"41";
when "00" & x"305" => data <= x"4e";
when "00" & x"306" => data <= x"b7";
when "00" & x"307" => data <= x"00";
when "00" & x"308" => data <= x"54";
when "00" & x"309" => data <= x"48";
when "00" & x"30a" => data <= x"45";
when "00" & x"30b" => data <= x"4e";
when "00" & x"30c" => data <= x"8c";
when "00" & x"30d" => data <= x"14";
when "00" & x"30e" => data <= x"54";
when "00" & x"30f" => data <= x"4f";
when "00" & x"310" => data <= x"b8";
when "00" & x"311" => data <= x"00";
when "00" & x"312" => data <= x"54";
when "00" & x"313" => data <= x"41";
when "00" & x"314" => data <= x"42";
when "00" & x"315" => data <= x"28";
when "00" & x"316" => data <= x"8a";
when "00" & x"317" => data <= x"00";
when "00" & x"318" => data <= x"54";
when "00" & x"319" => data <= x"52";
when "00" & x"31a" => data <= x"41";
when "00" & x"31b" => data <= x"43";
when "00" & x"31c" => data <= x"45";
when "00" & x"31d" => data <= x"fc";
when "00" & x"31e" => data <= x"12";
when "00" & x"31f" => data <= x"54";
when "00" & x"320" => data <= x"49";
when "00" & x"321" => data <= x"4d";
when "00" & x"322" => data <= x"45";
when "00" & x"323" => data <= x"91";
when "00" & x"324" => data <= x"43";
when "00" & x"325" => data <= x"54";
when "00" & x"326" => data <= x"52";
when "00" & x"327" => data <= x"55";
when "00" & x"328" => data <= x"45";
when "00" & x"329" => data <= x"b9";
when "00" & x"32a" => data <= x"01";
when "00" & x"32b" => data <= x"55";
when "00" & x"32c" => data <= x"4e";
when "00" & x"32d" => data <= x"54";
when "00" & x"32e" => data <= x"49";
when "00" & x"32f" => data <= x"4c";
when "00" & x"330" => data <= x"fd";
when "00" & x"331" => data <= x"02";
when "00" & x"332" => data <= x"55";
when "00" & x"333" => data <= x"53";
when "00" & x"334" => data <= x"52";
when "00" & x"335" => data <= x"ba";
when "00" & x"336" => data <= x"00";
when "00" & x"337" => data <= x"56";
when "00" & x"338" => data <= x"44";
when "00" & x"339" => data <= x"55";
when "00" & x"33a" => data <= x"ef";
when "00" & x"33b" => data <= x"02";
when "00" & x"33c" => data <= x"56";
when "00" & x"33d" => data <= x"41";
when "00" & x"33e" => data <= x"4c";
when "00" & x"33f" => data <= x"bb";
when "00" & x"340" => data <= x"00";
when "00" & x"341" => data <= x"56";
when "00" & x"342" => data <= x"50";
when "00" & x"343" => data <= x"4f";
when "00" & x"344" => data <= x"53";
when "00" & x"345" => data <= x"bc";
when "00" & x"346" => data <= x"01";
when "00" & x"347" => data <= x"57";
when "00" & x"348" => data <= x"49";
when "00" & x"349" => data <= x"44";
when "00" & x"34a" => data <= x"54";
when "00" & x"34b" => data <= x"48";
when "00" & x"34c" => data <= x"fe";
when "00" & x"34d" => data <= x"02";
when "00" & x"34e" => data <= x"50";
when "00" & x"34f" => data <= x"41";
when "00" & x"350" => data <= x"47";
when "00" & x"351" => data <= x"45";
when "00" & x"352" => data <= x"d0";
when "00" & x"353" => data <= x"00";
when "00" & x"354" => data <= x"50";
when "00" & x"355" => data <= x"54";
when "00" & x"356" => data <= x"52";
when "00" & x"357" => data <= x"cf";
when "00" & x"358" => data <= x"00";
when "00" & x"359" => data <= x"54";
when "00" & x"35a" => data <= x"49";
when "00" & x"35b" => data <= x"4d";
when "00" & x"35c" => data <= x"45";
when "00" & x"35d" => data <= x"d1";
when "00" & x"35e" => data <= x"00";
when "00" & x"35f" => data <= x"4c";
when "00" & x"360" => data <= x"4f";
when "00" & x"361" => data <= x"4d";
when "00" & x"362" => data <= x"45";
when "00" & x"363" => data <= x"4d";
when "00" & x"364" => data <= x"d2";
when "00" & x"365" => data <= x"00";
when "00" & x"366" => data <= x"48";
when "00" & x"367" => data <= x"49";
when "00" & x"368" => data <= x"4d";
when "00" & x"369" => data <= x"45";
when "00" & x"36a" => data <= x"4d";
when "00" & x"36b" => data <= x"d3";
when "00" & x"36c" => data <= x"00";
when "00" & x"36d" => data <= x"78";
when "00" & x"36e" => data <= x"47";
when "00" & x"36f" => data <= x"c0";
when "00" & x"370" => data <= x"b4";
when "00" & x"371" => data <= x"fc";
when "00" & x"372" => data <= x"03";
when "00" & x"373" => data <= x"6a";
when "00" & x"374" => data <= x"d4";
when "00" & x"375" => data <= x"33";
when "00" & x"376" => data <= x"9e";
when "00" & x"377" => data <= x"da";
when "00" & x"378" => data <= x"07";
when "00" & x"379" => data <= x"6f";
when "00" & x"37a" => data <= x"8d";
when "00" & x"37b" => data <= x"f7";
when "00" & x"37c" => data <= x"c2";
when "00" & x"37d" => data <= x"9f";
when "00" & x"37e" => data <= x"a6";
when "00" & x"37f" => data <= x"e9";
when "00" & x"380" => data <= x"91";
when "00" & x"381" => data <= x"46";
when "00" & x"382" => data <= x"ca";
when "00" & x"383" => data <= x"95";
when "00" & x"384" => data <= x"b9";
when "00" & x"385" => data <= x"ad";
when "00" & x"386" => data <= x"e2";
when "00" & x"387" => data <= x"78";
when "00" & x"388" => data <= x"d1";
when "00" & x"389" => data <= x"fe";
when "00" & x"38a" => data <= x"a8";
when "00" & x"38b" => data <= x"d1";
when "00" & x"38c" => data <= x"80";
when "00" & x"38d" => data <= x"7c";
when "00" & x"38e" => data <= x"cb";
when "00" & x"38f" => data <= x"41";
when "00" & x"390" => data <= x"6d";
when "00" & x"391" => data <= x"b1";
when "00" & x"392" => data <= x"49";
when "00" & x"393" => data <= x"88";
when "00" & x"394" => data <= x"98";
when "00" & x"395" => data <= x"b4";
when "00" & x"396" => data <= x"be";
when "00" & x"397" => data <= x"dc";
when "00" & x"398" => data <= x"c4";
when "00" & x"399" => data <= x"d2";
when "00" & x"39a" => data <= x"2f";
when "00" & x"39b" => data <= x"76";
when "00" & x"39c" => data <= x"bd";
when "00" & x"39d" => data <= x"bf";
when "00" & x"39e" => data <= x"26";
when "00" & x"39f" => data <= x"cc";
when "00" & x"3a0" => data <= x"39";
when "00" & x"3a1" => data <= x"ee";
when "00" & x"3a2" => data <= x"94";
when "00" & x"3a3" => data <= x"c2";
when "00" & x"3a4" => data <= x"b8";
when "00" & x"3a5" => data <= x"ac";
when "00" & x"3a6" => data <= x"31";
when "00" & x"3a7" => data <= x"24";
when "00" & x"3a8" => data <= x"9c";
when "00" & x"3a9" => data <= x"da";
when "00" & x"3aa" => data <= x"b6";
when "00" & x"3ab" => data <= x"a3";
when "00" & x"3ac" => data <= x"f3";
when "00" & x"3ad" => data <= x"2a";
when "00" & x"3ae" => data <= x"30";
when "00" & x"3af" => data <= x"83";
when "00" & x"3b0" => data <= x"c9";
when "00" & x"3b1" => data <= x"6f";
when "00" & x"3b2" => data <= x"5d";
when "00" & x"3b3" => data <= x"4c";
when "00" & x"3b4" => data <= x"58";
when "00" & x"3b5" => data <= x"d2";
when "00" & x"3b6" => data <= x"2a";
when "00" & x"3b7" => data <= x"8d";
when "00" & x"3b8" => data <= x"99";
when "00" & x"3b9" => data <= x"bd";
when "00" & x"3ba" => data <= x"c4";
when "00" & x"3bb" => data <= x"7d";
when "00" & x"3bc" => data <= x"7d";
when "00" & x"3bd" => data <= x"2f";
when "00" & x"3be" => data <= x"e8";
when "00" & x"3bf" => data <= x"c8";
when "00" & x"3c0" => data <= x"56";
when "00" & x"3c1" => data <= x"72";
when "00" & x"3c2" => data <= x"c4";
when "00" & x"3c3" => data <= x"88";
when "00" & x"3c4" => data <= x"cc";
when "00" & x"3c5" => data <= x"7a";
when "00" & x"3c6" => data <= x"c2";
when "00" & x"3c7" => data <= x"44";
when "00" & x"3c8" => data <= x"e4";
when "00" & x"3c9" => data <= x"23";
when "00" & x"3ca" => data <= x"9a";
when "00" & x"3cb" => data <= x"e4";
when "00" & x"3cc" => data <= x"95";
when "00" & x"3cd" => data <= x"15";
when "00" & x"3ce" => data <= x"2f";
when "00" & x"3cf" => data <= x"f1";
when "00" & x"3d0" => data <= x"9a";
when "00" & x"3d1" => data <= x"04";
when "00" & x"3d2" => data <= x"1f";
when "00" & x"3d3" => data <= x"7d";
when "00" & x"3d4" => data <= x"e4";
when "00" & x"3d5" => data <= x"e4";
when "00" & x"3d6" => data <= x"e6";
when "00" & x"3d7" => data <= x"b6";
when "00" & x"3d8" => data <= x"11";
when "00" & x"3d9" => data <= x"d0";
when "00" & x"3da" => data <= x"8e";
when "00" & x"3db" => data <= x"95";
when "00" & x"3dc" => data <= x"b1";
when "00" & x"3dd" => data <= x"a0";
when "00" & x"3de" => data <= x"c2";
when "00" & x"3df" => data <= x"bf";
when "00" & x"3e0" => data <= x"bf";
when "00" & x"3e1" => data <= x"ae";
when "00" & x"3e2" => data <= x"ae";
when "00" & x"3e3" => data <= x"ae";
when "00" & x"3e4" => data <= x"af";
when "00" & x"3e5" => data <= x"ad";
when "00" & x"3e6" => data <= x"a8";
when "00" & x"3e7" => data <= x"ab";
when "00" & x"3e8" => data <= x"ac";
when "00" & x"3e9" => data <= x"a8";
when "00" & x"3ea" => data <= x"a9";
when "00" & x"3eb" => data <= x"bf";
when "00" & x"3ec" => data <= x"a9";
when "00" & x"3ed" => data <= x"ae";
when "00" & x"3ee" => data <= x"ab";
when "00" & x"3ef" => data <= x"af";
when "00" & x"3f0" => data <= x"af";
when "00" & x"3f1" => data <= x"ab";
when "00" & x"3f2" => data <= x"aa";
when "00" & x"3f3" => data <= x"bf";
when "00" & x"3f4" => data <= x"ae";
when "00" & x"3f5" => data <= x"b1";
when "00" & x"3f6" => data <= x"af";
when "00" & x"3f7" => data <= x"ac";
when "00" & x"3f8" => data <= x"ac";
when "00" & x"3f9" => data <= x"ac";
when "00" & x"3fa" => data <= x"ae";
when "00" & x"3fb" => data <= x"a7";
when "00" & x"3fc" => data <= x"ab";
when "00" & x"3fd" => data <= x"ac";
when "00" & x"3fe" => data <= x"bf";
when "00" & x"3ff" => data <= x"bf";
when "00" & x"400" => data <= x"ab";
when "00" & x"401" => data <= x"ab";
when "00" & x"402" => data <= x"ab";
when "00" & x"403" => data <= x"ab";
when "00" & x"404" => data <= x"af";
when "00" & x"405" => data <= x"ab";
when "00" & x"406" => data <= x"a9";
when "00" & x"407" => data <= x"a7";
when "00" & x"408" => data <= x"a6";
when "00" & x"409" => data <= x"ae";
when "00" & x"40a" => data <= x"ac";
when "00" & x"40b" => data <= x"ab";
when "00" & x"40c" => data <= x"ac";
when "00" & x"40d" => data <= x"ab";
when "00" & x"40e" => data <= x"b3";
when "00" & x"40f" => data <= x"af";
when "00" & x"410" => data <= x"b0";
when "00" & x"411" => data <= x"af";
when "00" & x"412" => data <= x"b0";
when "00" & x"413" => data <= x"af";
when "00" & x"414" => data <= x"b0";
when "00" & x"415" => data <= x"b0";
when "00" & x"416" => data <= x"ac";
when "00" & x"417" => data <= x"90";
when "00" & x"418" => data <= x"8f";
when "00" & x"419" => data <= x"bf";
when "00" & x"41a" => data <= x"b5";
when "00" & x"41b" => data <= x"8a";
when "00" & x"41c" => data <= x"8a";
when "00" & x"41d" => data <= x"8f";
when "00" & x"41e" => data <= x"be";
when "00" & x"41f" => data <= x"98";
when "00" & x"420" => data <= x"bf";
when "00" & x"421" => data <= x"92";
when "00" & x"422" => data <= x"92";
when "00" & x"423" => data <= x"92";
when "00" & x"424" => data <= x"92";
when "00" & x"425" => data <= x"b4";
when "00" & x"426" => data <= x"bf";
when "00" & x"427" => data <= x"8e";
when "00" & x"428" => data <= x"bf";
when "00" & x"429" => data <= x"92";
when "00" & x"42a" => data <= x"bf";
when "00" & x"42b" => data <= x"8e";
when "00" & x"42c" => data <= x"8e";
when "00" & x"42d" => data <= x"8b";
when "00" & x"42e" => data <= x"8b";
when "00" & x"42f" => data <= x"91";
when "00" & x"430" => data <= x"93";
when "00" & x"431" => data <= x"8a";
when "00" & x"432" => data <= x"93";
when "00" & x"433" => data <= x"b4";
when "00" & x"434" => data <= x"b7";
when "00" & x"435" => data <= x"b8";
when "00" & x"436" => data <= x"b8";
when "00" & x"437" => data <= x"93";
when "00" & x"438" => data <= x"98";
when "00" & x"439" => data <= x"ba";
when "00" & x"43a" => data <= x"8b";
when "00" & x"43b" => data <= x"93";
when "00" & x"43c" => data <= x"93";
when "00" & x"43d" => data <= x"93";
when "00" & x"43e" => data <= x"b6";
when "00" & x"43f" => data <= x"b9";
when "00" & x"440" => data <= x"94";
when "00" & x"441" => data <= x"93";
when "00" & x"442" => data <= x"8d";
when "00" & x"443" => data <= x"93";
when "00" & x"444" => data <= x"bb";
when "00" & x"445" => data <= x"8b";
when "00" & x"446" => data <= x"bb";
when "00" & x"447" => data <= x"bf";
when "00" & x"448" => data <= x"ba";
when "00" & x"449" => data <= x"b8";
when "00" & x"44a" => data <= x"bd";
when "00" & x"44b" => data <= x"8a";
when "00" & x"44c" => data <= x"93";
when "00" & x"44d" => data <= x"92";
when "00" & x"44e" => data <= x"bb";
when "00" & x"44f" => data <= x"b4";
when "00" & x"450" => data <= x"be";
when "00" & x"451" => data <= x"4b";
when "00" & x"452" => data <= x"83";
when "00" & x"453" => data <= x"84";
when "00" & x"454" => data <= x"89";
when "00" & x"455" => data <= x"96";
when "00" & x"456" => data <= x"b8";
when "00" & x"457" => data <= x"b9";
when "00" & x"458" => data <= x"d8";
when "00" & x"459" => data <= x"d9";
when "00" & x"45a" => data <= x"f0";
when "00" & x"45b" => data <= x"01";
when "00" & x"45c" => data <= x"10";
when "00" & x"45d" => data <= x"81";
when "00" & x"45e" => data <= x"90";
when "00" & x"45f" => data <= x"89";
when "00" & x"460" => data <= x"93";
when "00" & x"461" => data <= x"a3";
when "00" & x"462" => data <= x"a4";
when "00" & x"463" => data <= x"a9";
when "00" & x"464" => data <= x"38";
when "00" & x"465" => data <= x"39";
when "00" & x"466" => data <= x"78";
when "00" & x"467" => data <= x"01";
when "00" & x"468" => data <= x"13";
when "00" & x"469" => data <= x"21";
when "00" & x"46a" => data <= x"63";
when "00" & x"46b" => data <= x"73";
when "00" & x"46c" => data <= x"b1";
when "00" & x"46d" => data <= x"a9";
when "00" & x"46e" => data <= x"c5";
when "00" & x"46f" => data <= x"0c";
when "00" & x"470" => data <= x"c3";
when "00" & x"471" => data <= x"d3";
when "00" & x"472" => data <= x"c4";
when "00" & x"473" => data <= x"f2";
when "00" & x"474" => data <= x"41";
when "00" & x"475" => data <= x"83";
when "00" & x"476" => data <= x"b0";
when "00" & x"477" => data <= x"81";
when "00" & x"478" => data <= x"43";
when "00" & x"479" => data <= x"6c";
when "00" & x"47a" => data <= x"72";
when "00" & x"47b" => data <= x"ec";
when "00" & x"47c" => data <= x"f2";
when "00" & x"47d" => data <= x"a3";
when "00" & x"47e" => data <= x"c3";
when "00" & x"47f" => data <= x"18";
when "00" & x"480" => data <= x"19";
when "00" & x"481" => data <= x"34";
when "00" & x"482" => data <= x"b0";
when "00" & x"483" => data <= x"72";
when "00" & x"484" => data <= x"98";
when "00" & x"485" => data <= x"99";
when "00" & x"486" => data <= x"81";
when "00" & x"487" => data <= x"98";
when "00" & x"488" => data <= x"99";
when "00" & x"489" => data <= x"14";
when "00" & x"48a" => data <= x"35";
when "00" & x"48b" => data <= x"0a";
when "00" & x"48c" => data <= x"0d";
when "00" & x"48d" => data <= x"0d";
when "00" & x"48e" => data <= x"0d";
when "00" & x"48f" => data <= x"0d";
when "00" & x"490" => data <= x"10";
when "00" & x"491" => data <= x"10";
when "00" & x"492" => data <= x"25";
when "00" & x"493" => data <= x"25";
when "00" & x"494" => data <= x"39";
when "00" & x"495" => data <= x"41";
when "00" & x"496" => data <= x"41";
when "00" & x"497" => data <= x"41";
when "00" & x"498" => data <= x"41";
when "00" & x"499" => data <= x"4a";
when "00" & x"49a" => data <= x"4a";
when "00" & x"49b" => data <= x"4c";
when "00" & x"49c" => data <= x"4c";
when "00" & x"49d" => data <= x"4c";
when "00" & x"49e" => data <= x"50";
when "00" & x"49f" => data <= x"50";
when "00" & x"4a0" => data <= x"52";
when "00" & x"4a1" => data <= x"53";
when "00" & x"4a2" => data <= x"53";
when "00" & x"4a3" => data <= x"53";
when "00" & x"4a4" => data <= x"08";
when "00" & x"4a5" => data <= x"08";
when "00" & x"4a6" => data <= x"08";
when "00" & x"4a7" => data <= x"09";
when "00" & x"4a8" => data <= x"09";
when "00" & x"4a9" => data <= x"0a";
when "00" & x"4aa" => data <= x"0a";
when "00" & x"4ab" => data <= x"0a";
when "00" & x"4ac" => data <= x"05";
when "00" & x"4ad" => data <= x"15";
when "00" & x"4ae" => data <= x"3e";
when "00" & x"4af" => data <= x"04";
when "00" & x"4b0" => data <= x"0d";
when "00" & x"4b1" => data <= x"30";
when "00" & x"4b2" => data <= x"4c";
when "00" & x"4b3" => data <= x"06";
when "00" & x"4b4" => data <= x"32";
when "00" & x"4b5" => data <= x"49";
when "00" & x"4b6" => data <= x"49";
when "00" & x"4b7" => data <= x"10";
when "00" & x"4b8" => data <= x"25";
when "00" & x"4b9" => data <= x"0e";
when "00" & x"4ba" => data <= x"0e";
when "00" & x"4bb" => data <= x"09";
when "00" & x"4bc" => data <= x"29";
when "00" & x"4bd" => data <= x"2a";
when "00" & x"4be" => data <= x"30";
when "00" & x"4bf" => data <= x"30";
when "00" & x"4c0" => data <= x"4e";
when "00" & x"4c1" => data <= x"4e";
when "00" & x"4c2" => data <= x"4e";
when "00" & x"4c3" => data <= x"3e";
when "00" & x"4c4" => data <= x"16";
when "00" & x"4c5" => data <= x"00";
when "00" & x"4c6" => data <= x"18";
when "00" & x"4c7" => data <= x"d8";
when "00" & x"4c8" => data <= x"58";
when "00" & x"4c9" => data <= x"b8";
when "00" & x"4ca" => data <= x"ca";
when "00" & x"4cb" => data <= x"88";
when "00" & x"4cc" => data <= x"e8";
when "00" & x"4cd" => data <= x"c8";
when "00" & x"4ce" => data <= x"ea";
when "00" & x"4cf" => data <= x"48";
when "00" & x"4d0" => data <= x"08";
when "00" & x"4d1" => data <= x"68";
when "00" & x"4d2" => data <= x"28";
when "00" & x"4d3" => data <= x"40";
when "00" & x"4d4" => data <= x"60";
when "00" & x"4d5" => data <= x"38";
when "00" & x"4d6" => data <= x"f8";
when "00" & x"4d7" => data <= x"78";
when "00" & x"4d8" => data <= x"aa";
when "00" & x"4d9" => data <= x"a8";
when "00" & x"4da" => data <= x"ba";
when "00" & x"4db" => data <= x"8a";
when "00" & x"4dc" => data <= x"9a";
when "00" & x"4dd" => data <= x"98";
when "00" & x"4de" => data <= x"90";
when "00" & x"4df" => data <= x"b0";
when "00" & x"4e0" => data <= x"f0";
when "00" & x"4e1" => data <= x"30";
when "00" & x"4e2" => data <= x"d0";
when "00" & x"4e3" => data <= x"10";
when "00" & x"4e4" => data <= x"50";
when "00" & x"4e5" => data <= x"70";
when "00" & x"4e6" => data <= x"21";
when "00" & x"4e7" => data <= x"41";
when "00" & x"4e8" => data <= x"01";
when "00" & x"4e9" => data <= x"61";
when "00" & x"4ea" => data <= x"c1";
when "00" & x"4eb" => data <= x"a1";
when "00" & x"4ec" => data <= x"e1";
when "00" & x"4ed" => data <= x"06";
when "00" & x"4ee" => data <= x"46";
when "00" & x"4ef" => data <= x"26";
when "00" & x"4f0" => data <= x"66";
when "00" & x"4f1" => data <= x"c6";
when "00" & x"4f2" => data <= x"e6";
when "00" & x"4f3" => data <= x"e0";
when "00" & x"4f4" => data <= x"c0";
when "00" & x"4f5" => data <= x"20";
when "00" & x"4f6" => data <= x"4c";
when "00" & x"4f7" => data <= x"20";
when "00" & x"4f8" => data <= x"a2";
when "00" & x"4f9" => data <= x"a0";
when "00" & x"4fa" => data <= x"81";
when "00" & x"4fb" => data <= x"86";
when "00" & x"4fc" => data <= x"84";
when "00" & x"4fd" => data <= x"a9";
when "00" & x"4fe" => data <= x"ff";
when "00" & x"4ff" => data <= x"85";
when "00" & x"500" => data <= x"28";
when "00" & x"501" => data <= x"4c";
when "00" & x"502" => data <= x"a3";
when "00" & x"503" => data <= x"8b";
when "00" & x"504" => data <= x"a9";
when "00" & x"505" => data <= x"03";
when "00" & x"506" => data <= x"85";
when "00" & x"507" => data <= x"28";
when "00" & x"508" => data <= x"20";
when "00" & x"509" => data <= x"97";
when "00" & x"50a" => data <= x"8a";
when "00" & x"50b" => data <= x"c9";
when "00" & x"50c" => data <= x"5d";
when "00" & x"50d" => data <= x"f0";
when "00" & x"50e" => data <= x"ee";
when "00" & x"50f" => data <= x"20";
when "00" & x"510" => data <= x"6d";
when "00" & x"511" => data <= x"98";
when "00" & x"512" => data <= x"c6";
when "00" & x"513" => data <= x"0a";
when "00" & x"514" => data <= x"20";
when "00" & x"515" => data <= x"ba";
when "00" & x"516" => data <= x"85";
when "00" & x"517" => data <= x"c6";
when "00" & x"518" => data <= x"0a";
when "00" & x"519" => data <= x"a5";
when "00" & x"51a" => data <= x"28";
when "00" & x"51b" => data <= x"4a";
when "00" & x"51c" => data <= x"90";
when "00" & x"51d" => data <= x"60";
when "00" & x"51e" => data <= x"a5";
when "00" & x"51f" => data <= x"1e";
when "00" & x"520" => data <= x"69";
when "00" & x"521" => data <= x"04";
when "00" & x"522" => data <= x"85";
when "00" & x"523" => data <= x"3f";
when "00" & x"524" => data <= x"a5";
when "00" & x"525" => data <= x"38";
when "00" & x"526" => data <= x"20";
when "00" & x"527" => data <= x"45";
when "00" & x"528" => data <= x"b5";
when "00" & x"529" => data <= x"a5";
when "00" & x"52a" => data <= x"37";
when "00" & x"52b" => data <= x"20";
when "00" & x"52c" => data <= x"62";
when "00" & x"52d" => data <= x"b5";
when "00" & x"52e" => data <= x"a2";
when "00" & x"52f" => data <= x"fc";
when "00" & x"530" => data <= x"a4";
when "00" & x"531" => data <= x"39";
when "00" & x"532" => data <= x"10";
when "00" & x"533" => data <= x"02";
when "00" & x"534" => data <= x"a4";
when "00" & x"535" => data <= x"36";
when "00" & x"536" => data <= x"84";
when "00" & x"537" => data <= x"38";
when "00" & x"538" => data <= x"f0";
when "00" & x"539" => data <= x"1c";
when "00" & x"53a" => data <= x"a0";
when "00" & x"53b" => data <= x"00";
when "00" & x"53c" => data <= x"e8";
when "00" & x"53d" => data <= x"d0";
when "00" & x"53e" => data <= x"0d";
when "00" & x"53f" => data <= x"20";
when "00" & x"540" => data <= x"25";
when "00" & x"541" => data <= x"bc";
when "00" & x"542" => data <= x"a6";
when "00" & x"543" => data <= x"3f";
when "00" & x"544" => data <= x"20";
when "00" & x"545" => data <= x"65";
when "00" & x"546" => data <= x"b5";
when "00" & x"547" => data <= x"ca";
when "00" & x"548" => data <= x"d0";
when "00" & x"549" => data <= x"fa";
when "00" & x"54a" => data <= x"a2";
when "00" & x"54b" => data <= x"fd";
when "00" & x"54c" => data <= x"b1";
when "00" & x"54d" => data <= x"3a";
when "00" & x"54e" => data <= x"20";
when "00" & x"54f" => data <= x"62";
when "00" & x"550" => data <= x"b5";
when "00" & x"551" => data <= x"c8";
when "00" & x"552" => data <= x"c6";
when "00" & x"553" => data <= x"38";
when "00" & x"554" => data <= x"d0";
when "00" & x"555" => data <= x"e6";
when "00" & x"556" => data <= x"e8";
when "00" & x"557" => data <= x"10";
when "00" & x"558" => data <= x"0c";
when "00" & x"559" => data <= x"20";
when "00" & x"55a" => data <= x"65";
when "00" & x"55b" => data <= x"b5";
when "00" & x"55c" => data <= x"20";
when "00" & x"55d" => data <= x"58";
when "00" & x"55e" => data <= x"b5";
when "00" & x"55f" => data <= x"20";
when "00" & x"560" => data <= x"58";
when "00" & x"561" => data <= x"b5";
when "00" & x"562" => data <= x"4c";
when "00" & x"563" => data <= x"56";
when "00" & x"564" => data <= x"85";
when "00" & x"565" => data <= x"a0";
when "00" & x"566" => data <= x"00";
when "00" & x"567" => data <= x"b1";
when "00" & x"568" => data <= x"0b";
when "00" & x"569" => data <= x"c9";
when "00" & x"56a" => data <= x"3a";
when "00" & x"56b" => data <= x"f0";
when "00" & x"56c" => data <= x"0a";
when "00" & x"56d" => data <= x"c9";
when "00" & x"56e" => data <= x"0d";
when "00" & x"56f" => data <= x"f0";
when "00" & x"570" => data <= x"0a";
when "00" & x"571" => data <= x"20";
when "00" & x"572" => data <= x"0e";
when "00" & x"573" => data <= x"b5";
when "00" & x"574" => data <= x"c8";
when "00" & x"575" => data <= x"d0";
when "00" & x"576" => data <= x"f0";
when "00" & x"577" => data <= x"c4";
when "00" & x"578" => data <= x"0a";
when "00" & x"579" => data <= x"90";
when "00" & x"57a" => data <= x"f6";
when "00" & x"57b" => data <= x"20";
when "00" & x"57c" => data <= x"25";
when "00" & x"57d" => data <= x"bc";
when "00" & x"57e" => data <= x"a4";
when "00" & x"57f" => data <= x"0a";
when "00" & x"580" => data <= x"88";
when "00" & x"581" => data <= x"c8";
when "00" & x"582" => data <= x"b1";
when "00" & x"583" => data <= x"0b";
when "00" & x"584" => data <= x"c9";
when "00" & x"585" => data <= x"3a";
when "00" & x"586" => data <= x"f0";
when "00" & x"587" => data <= x"04";
when "00" & x"588" => data <= x"c9";
when "00" & x"589" => data <= x"0d";
when "00" & x"58a" => data <= x"d0";
when "00" & x"58b" => data <= x"f5";
when "00" & x"58c" => data <= x"20";
when "00" & x"58d" => data <= x"59";
when "00" & x"58e" => data <= x"98";
when "00" & x"58f" => data <= x"88";
when "00" & x"590" => data <= x"b1";
when "00" & x"591" => data <= x"0b";
when "00" & x"592" => data <= x"c9";
when "00" & x"593" => data <= x"3a";
when "00" & x"594" => data <= x"f0";
when "00" & x"595" => data <= x"0c";
when "00" & x"596" => data <= x"a5";
when "00" & x"597" => data <= x"0c";
when "00" & x"598" => data <= x"c9";
when "00" & x"599" => data <= x"07";
when "00" & x"59a" => data <= x"d0";
when "00" & x"59b" => data <= x"03";
when "00" & x"59c" => data <= x"4c";
when "00" & x"59d" => data <= x"f6";
when "00" & x"59e" => data <= x"8a";
when "00" & x"59f" => data <= x"20";
when "00" & x"5a0" => data <= x"90";
when "00" & x"5a1" => data <= x"98";
when "00" & x"5a2" => data <= x"4c";
when "00" & x"5a3" => data <= x"08";
when "00" & x"5a4" => data <= x"85";
when "00" & x"5a5" => data <= x"20";
when "00" & x"5a6" => data <= x"82";
when "00" & x"5a7" => data <= x"95";
when "00" & x"5a8" => data <= x"f0";
when "00" & x"5a9" => data <= x"5a";
when "00" & x"5aa" => data <= x"b0";
when "00" & x"5ab" => data <= x"58";
when "00" & x"5ac" => data <= x"20";
when "00" & x"5ad" => data <= x"94";
when "00" & x"5ae" => data <= x"bd";
when "00" & x"5af" => data <= x"20";
when "00" & x"5b0" => data <= x"3a";
when "00" & x"5b1" => data <= x"ae";
when "00" & x"5b2" => data <= x"85";
when "00" & x"5b3" => data <= x"27";
when "00" & x"5b4" => data <= x"20";
when "00" & x"5b5" => data <= x"b4";
when "00" & x"5b6" => data <= x"b4";
when "00" & x"5b7" => data <= x"20";
when "00" & x"5b8" => data <= x"27";
when "00" & x"5b9" => data <= x"88";
when "00" & x"5ba" => data <= x"a2";
when "00" & x"5bb" => data <= x"03";
when "00" & x"5bc" => data <= x"20";
when "00" & x"5bd" => data <= x"97";
when "00" & x"5be" => data <= x"8a";
when "00" & x"5bf" => data <= x"a0";
when "00" & x"5c0" => data <= x"00";
when "00" & x"5c1" => data <= x"84";
when "00" & x"5c2" => data <= x"3d";
when "00" & x"5c3" => data <= x"c9";
when "00" & x"5c4" => data <= x"3a";
when "00" & x"5c5" => data <= x"f0";
when "00" & x"5c6" => data <= x"64";
when "00" & x"5c7" => data <= x"c9";
when "00" & x"5c8" => data <= x"0d";
when "00" & x"5c9" => data <= x"f0";
when "00" & x"5ca" => data <= x"60";
when "00" & x"5cb" => data <= x"c9";
when "00" & x"5cc" => data <= x"5c";
when "00" & x"5cd" => data <= x"f0";
when "00" & x"5ce" => data <= x"5c";
when "00" & x"5cf" => data <= x"c9";
when "00" & x"5d0" => data <= x"2e";
when "00" & x"5d1" => data <= x"f0";
when "00" & x"5d2" => data <= x"d2";
when "00" & x"5d3" => data <= x"c6";
when "00" & x"5d4" => data <= x"0a";
when "00" & x"5d5" => data <= x"a4";
when "00" & x"5d6" => data <= x"0a";
when "00" & x"5d7" => data <= x"e6";
when "00" & x"5d8" => data <= x"0a";
when "00" & x"5d9" => data <= x"b1";
when "00" & x"5da" => data <= x"0b";
when "00" & x"5db" => data <= x"30";
when "00" & x"5dc" => data <= x"2a";
when "00" & x"5dd" => data <= x"c9";
when "00" & x"5de" => data <= x"20";
when "00" & x"5df" => data <= x"f0";
when "00" & x"5e0" => data <= x"10";
when "00" & x"5e1" => data <= x"a0";
when "00" & x"5e2" => data <= x"05";
when "00" & x"5e3" => data <= x"0a";
when "00" & x"5e4" => data <= x"0a";
when "00" & x"5e5" => data <= x"0a";
when "00" & x"5e6" => data <= x"0a";
when "00" & x"5e7" => data <= x"26";
when "00" & x"5e8" => data <= x"3d";
when "00" & x"5e9" => data <= x"26";
when "00" & x"5ea" => data <= x"3e";
when "00" & x"5eb" => data <= x"88";
when "00" & x"5ec" => data <= x"d0";
when "00" & x"5ed" => data <= x"f8";
when "00" & x"5ee" => data <= x"ca";
when "00" & x"5ef" => data <= x"d0";
when "00" & x"5f0" => data <= x"e4";
when "00" & x"5f1" => data <= x"a2";
when "00" & x"5f2" => data <= x"3a";
when "00" & x"5f3" => data <= x"a5";
when "00" & x"5f4" => data <= x"3d";
when "00" & x"5f5" => data <= x"dd";
when "00" & x"5f6" => data <= x"50";
when "00" & x"5f7" => data <= x"84";
when "00" & x"5f8" => data <= x"d0";
when "00" & x"5f9" => data <= x"07";
when "00" & x"5fa" => data <= x"bc";
when "00" & x"5fb" => data <= x"8a";
when "00" & x"5fc" => data <= x"84";
when "00" & x"5fd" => data <= x"c4";
when "00" & x"5fe" => data <= x"3e";
when "00" & x"5ff" => data <= x"f0";
when "00" & x"600" => data <= x"1f";
when "00" & x"601" => data <= x"ca";
when "00" & x"602" => data <= x"d0";
when "00" & x"603" => data <= x"f1";
when "00" & x"604" => data <= x"4c";
when "00" & x"605" => data <= x"2a";
when "00" & x"606" => data <= x"98";
when "00" & x"607" => data <= x"a2";
when "00" & x"608" => data <= x"22";
when "00" & x"609" => data <= x"c9";
when "00" & x"60a" => data <= x"80";
when "00" & x"60b" => data <= x"f0";
when "00" & x"60c" => data <= x"13";
when "00" & x"60d" => data <= x"e8";
when "00" & x"60e" => data <= x"c9";
when "00" & x"60f" => data <= x"82";
when "00" & x"610" => data <= x"f0";
when "00" & x"611" => data <= x"0e";
when "00" & x"612" => data <= x"e8";
when "00" & x"613" => data <= x"c9";
when "00" & x"614" => data <= x"84";
when "00" & x"615" => data <= x"d0";
when "00" & x"616" => data <= x"ed";
when "00" & x"617" => data <= x"e6";
when "00" & x"618" => data <= x"0a";
when "00" & x"619" => data <= x"c8";
when "00" & x"61a" => data <= x"b1";
when "00" & x"61b" => data <= x"0b";
when "00" & x"61c" => data <= x"c9";
when "00" & x"61d" => data <= x"41";
when "00" & x"61e" => data <= x"d0";
when "00" & x"61f" => data <= x"e4";
when "00" & x"620" => data <= x"bd";
when "00" & x"621" => data <= x"c4";
when "00" & x"622" => data <= x"84";
when "00" & x"623" => data <= x"85";
when "00" & x"624" => data <= x"29";
when "00" & x"625" => data <= x"a0";
when "00" & x"626" => data <= x"01";
when "00" & x"627" => data <= x"e0";
when "00" & x"628" => data <= x"1a";
when "00" & x"629" => data <= x"b0";
when "00" & x"62a" => data <= x"48";
when "00" & x"62b" => data <= x"ad";
when "00" & x"62c" => data <= x"40";
when "00" & x"62d" => data <= x"04";
when "00" & x"62e" => data <= x"85";
when "00" & x"62f" => data <= x"37";
when "00" & x"630" => data <= x"84";
when "00" & x"631" => data <= x"39";
when "00" & x"632" => data <= x"a6";
when "00" & x"633" => data <= x"28";
when "00" & x"634" => data <= x"e0";
when "00" & x"635" => data <= x"04";
when "00" & x"636" => data <= x"ae";
when "00" & x"637" => data <= x"41";
when "00" & x"638" => data <= x"04";
when "00" & x"639" => data <= x"86";
when "00" & x"63a" => data <= x"38";
when "00" & x"63b" => data <= x"90";
when "00" & x"63c" => data <= x"06";
when "00" & x"63d" => data <= x"ad";
when "00" & x"63e" => data <= x"3c";
when "00" & x"63f" => data <= x"04";
when "00" & x"640" => data <= x"ae";
when "00" & x"641" => data <= x"3d";
when "00" & x"642" => data <= x"04";
when "00" & x"643" => data <= x"85";
when "00" & x"644" => data <= x"3a";
when "00" & x"645" => data <= x"86";
when "00" & x"646" => data <= x"3b";
when "00" & x"647" => data <= x"98";
when "00" & x"648" => data <= x"f0";
when "00" & x"649" => data <= x"28";
when "00" & x"64a" => data <= x"10";
when "00" & x"64b" => data <= x"04";
when "00" & x"64c" => data <= x"a4";
when "00" & x"64d" => data <= x"36";
when "00" & x"64e" => data <= x"f0";
when "00" & x"64f" => data <= x"22";
when "00" & x"650" => data <= x"88";
when "00" & x"651" => data <= x"b9";
when "00" & x"652" => data <= x"29";
when "00" & x"653" => data <= x"00";
when "00" & x"654" => data <= x"24";
when "00" & x"655" => data <= x"39";
when "00" & x"656" => data <= x"10";
when "00" & x"657" => data <= x"03";
when "00" & x"658" => data <= x"b9";
when "00" & x"659" => data <= x"00";
when "00" & x"65a" => data <= x"06";
when "00" & x"65b" => data <= x"91";
when "00" & x"65c" => data <= x"3a";
when "00" & x"65d" => data <= x"ee";
when "00" & x"65e" => data <= x"40";
when "00" & x"65f" => data <= x"04";
when "00" & x"660" => data <= x"d0";
when "00" & x"661" => data <= x"03";
when "00" & x"662" => data <= x"ee";
when "00" & x"663" => data <= x"41";
when "00" & x"664" => data <= x"04";
when "00" & x"665" => data <= x"90";
when "00" & x"666" => data <= x"08";
when "00" & x"667" => data <= x"ee";
when "00" & x"668" => data <= x"3c";
when "00" & x"669" => data <= x"04";
when "00" & x"66a" => data <= x"d0";
when "00" & x"66b" => data <= x"03";
when "00" & x"66c" => data <= x"ee";
when "00" & x"66d" => data <= x"3d";
when "00" & x"66e" => data <= x"04";
when "00" & x"66f" => data <= x"98";
when "00" & x"670" => data <= x"d0";
when "00" & x"671" => data <= x"de";
when "00" & x"672" => data <= x"60";
when "00" & x"673" => data <= x"e0";
when "00" & x"674" => data <= x"22";
when "00" & x"675" => data <= x"b0";
when "00" & x"676" => data <= x"40";
when "00" & x"677" => data <= x"20";
when "00" & x"678" => data <= x"21";
when "00" & x"679" => data <= x"88";
when "00" & x"67a" => data <= x"18";
when "00" & x"67b" => data <= x"a5";
when "00" & x"67c" => data <= x"2a";
when "00" & x"67d" => data <= x"ed";
when "00" & x"67e" => data <= x"40";
when "00" & x"67f" => data <= x"04";
when "00" & x"680" => data <= x"a8";
when "00" & x"681" => data <= x"a5";
when "00" & x"682" => data <= x"2b";
when "00" & x"683" => data <= x"ed";
when "00" & x"684" => data <= x"41";
when "00" & x"685" => data <= x"04";
when "00" & x"686" => data <= x"c0";
when "00" & x"687" => data <= x"01";
when "00" & x"688" => data <= x"88";
when "00" & x"689" => data <= x"e9";
when "00" & x"68a" => data <= x"00";
when "00" & x"68b" => data <= x"f0";
when "00" & x"68c" => data <= x"25";
when "00" & x"68d" => data <= x"c9";
when "00" & x"68e" => data <= x"ff";
when "00" & x"68f" => data <= x"f0";
when "00" & x"690" => data <= x"1c";
when "00" & x"691" => data <= x"a5";
when "00" & x"692" => data <= x"28";
when "00" & x"693" => data <= x"4a";
when "00" & x"694" => data <= x"f0";
when "00" & x"695" => data <= x"0f";
when "00" & x"696" => data <= x"00";
when "00" & x"697" => data <= x"01";
when "00" & x"698" => data <= x"4f";
when "00" & x"699" => data <= x"75";
when "00" & x"69a" => data <= x"74";
when "00" & x"69b" => data <= x"20";
when "00" & x"69c" => data <= x"6f";
when "00" & x"69d" => data <= x"66";
when "00" & x"69e" => data <= x"20";
when "00" & x"69f" => data <= x"72";
when "00" & x"6a0" => data <= x"61";
when "00" & x"6a1" => data <= x"6e";
when "00" & x"6a2" => data <= x"67";
when "00" & x"6a3" => data <= x"65";
when "00" & x"6a4" => data <= x"00";
when "00" & x"6a5" => data <= x"a8";
when "00" & x"6a6" => data <= x"84";
when "00" & x"6a7" => data <= x"2a";
when "00" & x"6a8" => data <= x"a0";
when "00" & x"6a9" => data <= x"02";
when "00" & x"6aa" => data <= x"4c";
when "00" & x"6ab" => data <= x"2b";
when "00" & x"6ac" => data <= x"86";
when "00" & x"6ad" => data <= x"98";
when "00" & x"6ae" => data <= x"30";
when "00" & x"6af" => data <= x"f6";
when "00" & x"6b0" => data <= x"10";
when "00" & x"6b1" => data <= x"df";
when "00" & x"6b2" => data <= x"98";
when "00" & x"6b3" => data <= x"10";
when "00" & x"6b4" => data <= x"f1";
when "00" & x"6b5" => data <= x"30";
when "00" & x"6b6" => data <= x"da";
when "00" & x"6b7" => data <= x"e0";
when "00" & x"6b8" => data <= x"29";
when "00" & x"6b9" => data <= x"b0";
when "00" & x"6ba" => data <= x"18";
when "00" & x"6bb" => data <= x"20";
when "00" & x"6bc" => data <= x"97";
when "00" & x"6bd" => data <= x"8a";
when "00" & x"6be" => data <= x"c9";
when "00" & x"6bf" => data <= x"23";
when "00" & x"6c0" => data <= x"d0";
when "00" & x"6c1" => data <= x"18";
when "00" & x"6c2" => data <= x"20";
when "00" & x"6c3" => data <= x"2f";
when "00" & x"6c4" => data <= x"88";
when "00" & x"6c5" => data <= x"20";
when "00" & x"6c6" => data <= x"21";
when "00" & x"6c7" => data <= x"88";
when "00" & x"6c8" => data <= x"a5";
when "00" & x"6c9" => data <= x"2b";
when "00" & x"6ca" => data <= x"f0";
when "00" & x"6cb" => data <= x"dc";
when "00" & x"6cc" => data <= x"00";
when "00" & x"6cd" => data <= x"02";
when "00" & x"6ce" => data <= x"42";
when "00" & x"6cf" => data <= x"79";
when "00" & x"6d0" => data <= x"74";
when "00" & x"6d1" => data <= x"65";
when "00" & x"6d2" => data <= x"00";
when "00" & x"6d3" => data <= x"e0";
when "00" & x"6d4" => data <= x"36";
when "00" & x"6d5" => data <= x"d0";
when "00" & x"6d6" => data <= x"68";
when "00" & x"6d7" => data <= x"20";
when "00" & x"6d8" => data <= x"97";
when "00" & x"6d9" => data <= x"8a";
when "00" & x"6da" => data <= x"c9";
when "00" & x"6db" => data <= x"28";
when "00" & x"6dc" => data <= x"d0";
when "00" & x"6dd" => data <= x"37";
when "00" & x"6de" => data <= x"20";
when "00" & x"6df" => data <= x"21";
when "00" & x"6e0" => data <= x"88";
when "00" & x"6e1" => data <= x"20";
when "00" & x"6e2" => data <= x"97";
when "00" & x"6e3" => data <= x"8a";
when "00" & x"6e4" => data <= x"c9";
when "00" & x"6e5" => data <= x"29";
when "00" & x"6e6" => data <= x"d0";
when "00" & x"6e7" => data <= x"13";
when "00" & x"6e8" => data <= x"20";
when "00" & x"6e9" => data <= x"97";
when "00" & x"6ea" => data <= x"8a";
when "00" & x"6eb" => data <= x"c9";
when "00" & x"6ec" => data <= x"2c";
when "00" & x"6ed" => data <= x"d0";
when "00" & x"6ee" => data <= x"1e";
when "00" & x"6ef" => data <= x"20";
when "00" & x"6f0" => data <= x"2c";
when "00" & x"6f1" => data <= x"88";
when "00" & x"6f2" => data <= x"20";
when "00" & x"6f3" => data <= x"97";
when "00" & x"6f4" => data <= x"8a";
when "00" & x"6f5" => data <= x"c9";
when "00" & x"6f6" => data <= x"59";
when "00" & x"6f7" => data <= x"d0";
when "00" & x"6f8" => data <= x"14";
when "00" & x"6f9" => data <= x"f0";
when "00" & x"6fa" => data <= x"cd";
when "00" & x"6fb" => data <= x"c9";
when "00" & x"6fc" => data <= x"2c";
when "00" & x"6fd" => data <= x"d0";
when "00" & x"6fe" => data <= x"0e";
when "00" & x"6ff" => data <= x"20";
when "00" & x"700" => data <= x"97";
when "00" & x"701" => data <= x"8a";
when "00" & x"702" => data <= x"c9";
when "00" & x"703" => data <= x"58";
when "00" & x"704" => data <= x"d0";
when "00" & x"705" => data <= x"07";
when "00" & x"706" => data <= x"20";
when "00" & x"707" => data <= x"97";
when "00" & x"708" => data <= x"8a";
when "00" & x"709" => data <= x"c9";
when "00" & x"70a" => data <= x"29";
when "00" & x"70b" => data <= x"f0";
when "00" & x"70c" => data <= x"bb";
when "00" & x"70d" => data <= x"00";
when "00" & x"70e" => data <= x"03";
when "00" & x"70f" => data <= x"49";
when "00" & x"710" => data <= x"6e";
when "00" & x"711" => data <= x"64";
when "00" & x"712" => data <= x"65";
when "00" & x"713" => data <= x"78";
when "00" & x"714" => data <= x"00";
when "00" & x"715" => data <= x"c6";
when "00" & x"716" => data <= x"0a";
when "00" & x"717" => data <= x"20";
when "00" & x"718" => data <= x"21";
when "00" & x"719" => data <= x"88";
when "00" & x"71a" => data <= x"20";
when "00" & x"71b" => data <= x"97";
when "00" & x"71c" => data <= x"8a";
when "00" & x"71d" => data <= x"c9";
when "00" & x"71e" => data <= x"2c";
when "00" & x"71f" => data <= x"d0";
when "00" & x"720" => data <= x"14";
when "00" & x"721" => data <= x"20";
when "00" & x"722" => data <= x"2c";
when "00" & x"723" => data <= x"88";
when "00" & x"724" => data <= x"20";
when "00" & x"725" => data <= x"97";
when "00" & x"726" => data <= x"8a";
when "00" & x"727" => data <= x"c9";
when "00" & x"728" => data <= x"58";
when "00" & x"729" => data <= x"f0";
when "00" & x"72a" => data <= x"0a";
when "00" & x"72b" => data <= x"c9";
when "00" & x"72c" => data <= x"59";
when "00" & x"72d" => data <= x"d0";
when "00" & x"72e" => data <= x"de";
when "00" & x"72f" => data <= x"20";
when "00" & x"730" => data <= x"2f";
when "00" & x"731" => data <= x"88";
when "00" & x"732" => data <= x"4c";
when "00" & x"733" => data <= x"9a";
when "00" & x"734" => data <= x"87";
when "00" & x"735" => data <= x"20";
when "00" & x"736" => data <= x"32";
when "00" & x"737" => data <= x"88";
when "00" & x"738" => data <= x"a5";
when "00" & x"739" => data <= x"2b";
when "00" & x"73a" => data <= x"d0";
when "00" & x"73b" => data <= x"f3";
when "00" & x"73c" => data <= x"4c";
when "00" & x"73d" => data <= x"a8";
when "00" & x"73e" => data <= x"86";
when "00" & x"73f" => data <= x"e0";
when "00" & x"740" => data <= x"2f";
when "00" & x"741" => data <= x"b0";
when "00" & x"742" => data <= x"2b";
when "00" & x"743" => data <= x"e0";
when "00" & x"744" => data <= x"2d";
when "00" & x"745" => data <= x"b0";
when "00" & x"746" => data <= x"09";
when "00" & x"747" => data <= x"20";
when "00" & x"748" => data <= x"97";
when "00" & x"749" => data <= x"8a";
when "00" & x"74a" => data <= x"c9";
when "00" & x"74b" => data <= x"41";
when "00" & x"74c" => data <= x"f0";
when "00" & x"74d" => data <= x"19";
when "00" & x"74e" => data <= x"c6";
when "00" & x"74f" => data <= x"0a";
when "00" & x"750" => data <= x"20";
when "00" & x"751" => data <= x"21";
when "00" & x"752" => data <= x"88";
when "00" & x"753" => data <= x"20";
when "00" & x"754" => data <= x"97";
when "00" & x"755" => data <= x"8a";
when "00" & x"756" => data <= x"c9";
when "00" & x"757" => data <= x"2c";
when "00" & x"758" => data <= x"d0";
when "00" & x"759" => data <= x"de";
when "00" & x"75a" => data <= x"20";
when "00" & x"75b" => data <= x"2c";
when "00" & x"75c" => data <= x"88";
when "00" & x"75d" => data <= x"20";
when "00" & x"75e" => data <= x"97";
when "00" & x"75f" => data <= x"8a";
when "00" & x"760" => data <= x"c9";
when "00" & x"761" => data <= x"58";
when "00" & x"762" => data <= x"f0";
when "00" & x"763" => data <= x"d4";
when "00" & x"764" => data <= x"4c";
when "00" & x"765" => data <= x"0d";
when "00" & x"766" => data <= x"87";
when "00" & x"767" => data <= x"20";
when "00" & x"768" => data <= x"32";
when "00" & x"769" => data <= x"88";
when "00" & x"76a" => data <= x"a0";
when "00" & x"76b" => data <= x"01";
when "00" & x"76c" => data <= x"d0";
when "00" & x"76d" => data <= x"2e";
when "00" & x"76e" => data <= x"e0";
when "00" & x"76f" => data <= x"32";
when "00" & x"770" => data <= x"b0";
when "00" & x"771" => data <= x"16";
when "00" & x"772" => data <= x"e0";
when "00" & x"773" => data <= x"31";
when "00" & x"774" => data <= x"f0";
when "00" & x"775" => data <= x"0c";
when "00" & x"776" => data <= x"20";
when "00" & x"777" => data <= x"97";
when "00" & x"778" => data <= x"8a";
when "00" & x"779" => data <= x"c9";
when "00" & x"77a" => data <= x"23";
when "00" & x"77b" => data <= x"d0";
when "00" & x"77c" => data <= x"03";
when "00" & x"77d" => data <= x"4c";
when "00" & x"77e" => data <= x"c5";
when "00" & x"77f" => data <= x"86";
when "00" & x"780" => data <= x"c6";
when "00" & x"781" => data <= x"0a";
when "00" & x"782" => data <= x"20";
when "00" & x"783" => data <= x"21";
when "00" & x"784" => data <= x"88";
when "00" & x"785" => data <= x"4c";
when "00" & x"786" => data <= x"35";
when "00" & x"787" => data <= x"87";
when "00" & x"788" => data <= x"e0";
when "00" & x"789" => data <= x"33";
when "00" & x"78a" => data <= x"f0";
when "00" & x"78b" => data <= x"0b";
when "00" & x"78c" => data <= x"b0";
when "00" & x"78d" => data <= x"24";
when "00" & x"78e" => data <= x"20";
when "00" & x"78f" => data <= x"97";
when "00" & x"790" => data <= x"8a";
when "00" & x"791" => data <= x"c9";
when "00" & x"792" => data <= x"28";
when "00" & x"793" => data <= x"f0";
when "00" & x"794" => data <= x"0a";
when "00" & x"795" => data <= x"c6";
when "00" & x"796" => data <= x"0a";
when "00" & x"797" => data <= x"20";
when "00" & x"798" => data <= x"21";
when "00" & x"799" => data <= x"88";
when "00" & x"79a" => data <= x"a0";
when "00" & x"79b" => data <= x"03";
when "00" & x"79c" => data <= x"4c";
when "00" & x"79d" => data <= x"2b";
when "00" & x"79e" => data <= x"86";
when "00" & x"79f" => data <= x"20";
when "00" & x"7a0" => data <= x"2c";
when "00" & x"7a1" => data <= x"88";
when "00" & x"7a2" => data <= x"20";
when "00" & x"7a3" => data <= x"2c";
when "00" & x"7a4" => data <= x"88";
when "00" & x"7a5" => data <= x"20";
when "00" & x"7a6" => data <= x"21";
when "00" & x"7a7" => data <= x"88";
when "00" & x"7a8" => data <= x"20";
when "00" & x"7a9" => data <= x"97";
when "00" & x"7aa" => data <= x"8a";
when "00" & x"7ab" => data <= x"c9";
when "00" & x"7ac" => data <= x"29";
when "00" & x"7ad" => data <= x"f0";
when "00" & x"7ae" => data <= x"eb";
when "00" & x"7af" => data <= x"4c";
when "00" & x"7b0" => data <= x"0d";
when "00" & x"7b1" => data <= x"87";
when "00" & x"7b2" => data <= x"e0";
when "00" & x"7b3" => data <= x"39";
when "00" & x"7b4" => data <= x"b0";
when "00" & x"7b5" => data <= x"5d";
when "00" & x"7b6" => data <= x"a5";
when "00" & x"7b7" => data <= x"3d";
when "00" & x"7b8" => data <= x"49";
when "00" & x"7b9" => data <= x"01";
when "00" & x"7ba" => data <= x"29";
when "00" & x"7bb" => data <= x"1f";
when "00" & x"7bc" => data <= x"48";
when "00" & x"7bd" => data <= x"e0";
when "00" & x"7be" => data <= x"37";
when "00" & x"7bf" => data <= x"b0";
when "00" & x"7c0" => data <= x"2f";
when "00" & x"7c1" => data <= x"20";
when "00" & x"7c2" => data <= x"97";
when "00" & x"7c3" => data <= x"8a";
when "00" & x"7c4" => data <= x"c9";
when "00" & x"7c5" => data <= x"23";
when "00" & x"7c6" => data <= x"d0";
when "00" & x"7c7" => data <= x"04";
when "00" & x"7c8" => data <= x"68";
when "00" & x"7c9" => data <= x"4c";
when "00" & x"7ca" => data <= x"c5";
when "00" & x"7cb" => data <= x"86";
when "00" & x"7cc" => data <= x"c6";
when "00" & x"7cd" => data <= x"0a";
when "00" & x"7ce" => data <= x"20";
when "00" & x"7cf" => data <= x"21";
when "00" & x"7d0" => data <= x"88";
when "00" & x"7d1" => data <= x"68";
when "00" & x"7d2" => data <= x"85";
when "00" & x"7d3" => data <= x"37";
when "00" & x"7d4" => data <= x"20";
when "00" & x"7d5" => data <= x"97";
when "00" & x"7d6" => data <= x"8a";
when "00" & x"7d7" => data <= x"c9";
when "00" & x"7d8" => data <= x"2c";
when "00" & x"7d9" => data <= x"f0";
when "00" & x"7da" => data <= x"03";
when "00" & x"7db" => data <= x"4c";
when "00" & x"7dc" => data <= x"35";
when "00" & x"7dd" => data <= x"87";
when "00" & x"7de" => data <= x"20";
when "00" & x"7df" => data <= x"97";
when "00" & x"7e0" => data <= x"8a";
when "00" & x"7e1" => data <= x"29";
when "00" & x"7e2" => data <= x"1f";
when "00" & x"7e3" => data <= x"c5";
when "00" & x"7e4" => data <= x"37";
when "00" & x"7e5" => data <= x"d0";
when "00" & x"7e6" => data <= x"06";
when "00" & x"7e7" => data <= x"20";
when "00" & x"7e8" => data <= x"2c";
when "00" & x"7e9" => data <= x"88";
when "00" & x"7ea" => data <= x"4c";
when "00" & x"7eb" => data <= x"35";
when "00" & x"7ec" => data <= x"87";
when "00" & x"7ed" => data <= x"4c";
when "00" & x"7ee" => data <= x"0d";
when "00" & x"7ef" => data <= x"87";
when "00" & x"7f0" => data <= x"20";
when "00" & x"7f1" => data <= x"21";
when "00" & x"7f2" => data <= x"88";
when "00" & x"7f3" => data <= x"68";
when "00" & x"7f4" => data <= x"85";
when "00" & x"7f5" => data <= x"37";
when "00" & x"7f6" => data <= x"20";
when "00" & x"7f7" => data <= x"97";
when "00" & x"7f8" => data <= x"8a";
when "00" & x"7f9" => data <= x"c9";
when "00" & x"7fa" => data <= x"2c";
when "00" & x"7fb" => data <= x"d0";
when "00" & x"7fc" => data <= x"13";
when "00" & x"7fd" => data <= x"20";
when "00" & x"7fe" => data <= x"97";
when "00" & x"7ff" => data <= x"8a";
when "00" & x"800" => data <= x"29";
when "00" & x"801" => data <= x"1f";
when "00" & x"802" => data <= x"c5";
when "00" & x"803" => data <= x"37";
when "00" & x"804" => data <= x"d0";
when "00" & x"805" => data <= x"e7";
when "00" & x"806" => data <= x"20";
when "00" & x"807" => data <= x"2c";
when "00" & x"808" => data <= x"88";
when "00" & x"809" => data <= x"a5";
when "00" & x"80a" => data <= x"2b";
when "00" & x"80b" => data <= x"f0";
when "00" & x"80c" => data <= x"03";
when "00" & x"80d" => data <= x"4c";
when "00" & x"80e" => data <= x"cc";
when "00" & x"80f" => data <= x"86";
when "00" & x"810" => data <= x"4c";
when "00" & x"811" => data <= x"38";
when "00" & x"812" => data <= x"87";
when "00" & x"813" => data <= x"d0";
when "00" & x"814" => data <= x"25";
when "00" & x"815" => data <= x"20";
when "00" & x"816" => data <= x"21";
when "00" & x"817" => data <= x"88";
when "00" & x"818" => data <= x"a5";
when "00" & x"819" => data <= x"2a";
when "00" & x"81a" => data <= x"85";
when "00" & x"81b" => data <= x"28";
when "00" & x"81c" => data <= x"a0";
when "00" & x"81d" => data <= x"00";
when "00" & x"81e" => data <= x"4c";
when "00" & x"81f" => data <= x"2b";
when "00" & x"820" => data <= x"86";
when "00" & x"821" => data <= x"20";
when "00" & x"822" => data <= x"1d";
when "00" & x"823" => data <= x"9b";
when "00" & x"824" => data <= x"20";
when "00" & x"825" => data <= x"f0";
when "00" & x"826" => data <= x"92";
when "00" & x"827" => data <= x"a4";
when "00" & x"828" => data <= x"1b";
when "00" & x"829" => data <= x"84";
when "00" & x"82a" => data <= x"0a";
when "00" & x"82b" => data <= x"60";
when "00" & x"82c" => data <= x"20";
when "00" & x"82d" => data <= x"2f";
when "00" & x"82e" => data <= x"88";
when "00" & x"82f" => data <= x"20";
when "00" & x"830" => data <= x"32";
when "00" & x"831" => data <= x"88";
when "00" & x"832" => data <= x"a5";
when "00" & x"833" => data <= x"29";
when "00" & x"834" => data <= x"18";
when "00" & x"835" => data <= x"69";
when "00" & x"836" => data <= x"04";
when "00" & x"837" => data <= x"85";
when "00" & x"838" => data <= x"29";
when "00" & x"839" => data <= x"60";
when "00" & x"83a" => data <= x"a2";
when "00" & x"83b" => data <= x"01";
when "00" & x"83c" => data <= x"a4";
when "00" & x"83d" => data <= x"0a";
when "00" & x"83e" => data <= x"e6";
when "00" & x"83f" => data <= x"0a";
when "00" & x"840" => data <= x"b1";
when "00" & x"841" => data <= x"0b";
when "00" & x"842" => data <= x"c9";
when "00" & x"843" => data <= x"42";
when "00" & x"844" => data <= x"f0";
when "00" & x"845" => data <= x"12";
when "00" & x"846" => data <= x"e8";
when "00" & x"847" => data <= x"c9";
when "00" & x"848" => data <= x"57";
when "00" & x"849" => data <= x"f0";
when "00" & x"84a" => data <= x"0d";
when "00" & x"84b" => data <= x"a2";
when "00" & x"84c" => data <= x"04";
when "00" & x"84d" => data <= x"c9";
when "00" & x"84e" => data <= x"44";
when "00" & x"84f" => data <= x"f0";
when "00" & x"850" => data <= x"07";
when "00" & x"851" => data <= x"c9";
when "00" & x"852" => data <= x"53";
when "00" & x"853" => data <= x"f0";
when "00" & x"854" => data <= x"15";
when "00" & x"855" => data <= x"4c";
when "00" & x"856" => data <= x"2a";
when "00" & x"857" => data <= x"98";
when "00" & x"858" => data <= x"8a";
when "00" & x"859" => data <= x"48";
when "00" & x"85a" => data <= x"20";
when "00" & x"85b" => data <= x"21";
when "00" & x"85c" => data <= x"88";
when "00" & x"85d" => data <= x"a2";
when "00" & x"85e" => data <= x"29";
when "00" & x"85f" => data <= x"20";
when "00" & x"860" => data <= x"44";
when "00" & x"861" => data <= x"be";
when "00" & x"862" => data <= x"68";
when "00" & x"863" => data <= x"a8";
when "00" & x"864" => data <= x"4c";
when "00" & x"865" => data <= x"2b";
when "00" & x"866" => data <= x"86";
when "00" & x"867" => data <= x"4c";
when "00" & x"868" => data <= x"0e";
when "00" & x"869" => data <= x"8c";
when "00" & x"86a" => data <= x"a5";
when "00" & x"86b" => data <= x"28";
when "00" & x"86c" => data <= x"48";
when "00" & x"86d" => data <= x"20";
when "00" & x"86e" => data <= x"1d";
when "00" & x"86f" => data <= x"9b";
when "00" & x"870" => data <= x"d0";
when "00" & x"871" => data <= x"f5";
when "00" & x"872" => data <= x"68";
when "00" & x"873" => data <= x"85";
when "00" & x"874" => data <= x"28";
when "00" & x"875" => data <= x"20";
when "00" & x"876" => data <= x"27";
when "00" & x"877" => data <= x"88";
when "00" & x"878" => data <= x"a0";
when "00" & x"879" => data <= x"ff";
when "00" & x"87a" => data <= x"d0";
when "00" & x"87b" => data <= x"e8";
when "00" & x"87c" => data <= x"48";
when "00" & x"87d" => data <= x"18";
when "00" & x"87e" => data <= x"98";
when "00" & x"87f" => data <= x"65";
when "00" & x"880" => data <= x"37";
when "00" & x"881" => data <= x"85";
when "00" & x"882" => data <= x"39";
when "00" & x"883" => data <= x"a0";
when "00" & x"884" => data <= x"00";
when "00" & x"885" => data <= x"98";
when "00" & x"886" => data <= x"65";
when "00" & x"887" => data <= x"38";
when "00" & x"888" => data <= x"85";
when "00" & x"889" => data <= x"3a";
when "00" & x"88a" => data <= x"68";
when "00" & x"88b" => data <= x"91";
when "00" & x"88c" => data <= x"37";
when "00" & x"88d" => data <= x"c8";
when "00" & x"88e" => data <= x"b1";
when "00" & x"88f" => data <= x"39";
when "00" & x"890" => data <= x"91";
when "00" & x"891" => data <= x"37";
when "00" & x"892" => data <= x"c9";
when "00" & x"893" => data <= x"0d";
when "00" & x"894" => data <= x"d0";
when "00" & x"895" => data <= x"f7";
when "00" & x"896" => data <= x"60";
when "00" & x"897" => data <= x"29";
when "00" & x"898" => data <= x"0f";
when "00" & x"899" => data <= x"85";
when "00" & x"89a" => data <= x"3d";
when "00" & x"89b" => data <= x"84";
when "00" & x"89c" => data <= x"3e";
when "00" & x"89d" => data <= x"c8";
when "00" & x"89e" => data <= x"b1";
when "00" & x"89f" => data <= x"37";
when "00" & x"8a0" => data <= x"c9";
when "00" & x"8a1" => data <= x"3a";
when "00" & x"8a2" => data <= x"b0";
when "00" & x"8a3" => data <= x"36";
when "00" & x"8a4" => data <= x"c9";
when "00" & x"8a5" => data <= x"30";
when "00" & x"8a6" => data <= x"90";
when "00" & x"8a7" => data <= x"32";
when "00" & x"8a8" => data <= x"29";
when "00" & x"8a9" => data <= x"0f";
when "00" & x"8aa" => data <= x"48";
when "00" & x"8ab" => data <= x"a6";
when "00" & x"8ac" => data <= x"3e";
when "00" & x"8ad" => data <= x"a5";
when "00" & x"8ae" => data <= x"3d";
when "00" & x"8af" => data <= x"0a";
when "00" & x"8b0" => data <= x"26";
when "00" & x"8b1" => data <= x"3e";
when "00" & x"8b2" => data <= x"30";
when "00" & x"8b3" => data <= x"21";
when "00" & x"8b4" => data <= x"0a";
when "00" & x"8b5" => data <= x"26";
when "00" & x"8b6" => data <= x"3e";
when "00" & x"8b7" => data <= x"30";
when "00" & x"8b8" => data <= x"1c";
when "00" & x"8b9" => data <= x"65";
when "00" & x"8ba" => data <= x"3d";
when "00" & x"8bb" => data <= x"85";
when "00" & x"8bc" => data <= x"3d";
when "00" & x"8bd" => data <= x"8a";
when "00" & x"8be" => data <= x"65";
when "00" & x"8bf" => data <= x"3e";
when "00" & x"8c0" => data <= x"06";
when "00" & x"8c1" => data <= x"3d";
when "00" & x"8c2" => data <= x"2a";
when "00" & x"8c3" => data <= x"30";
when "00" & x"8c4" => data <= x"10";
when "00" & x"8c5" => data <= x"b0";
when "00" & x"8c6" => data <= x"0e";
when "00" & x"8c7" => data <= x"85";
when "00" & x"8c8" => data <= x"3e";
when "00" & x"8c9" => data <= x"68";
when "00" & x"8ca" => data <= x"65";
when "00" & x"8cb" => data <= x"3d";
when "00" & x"8cc" => data <= x"85";
when "00" & x"8cd" => data <= x"3d";
when "00" & x"8ce" => data <= x"90";
when "00" & x"8cf" => data <= x"cd";
when "00" & x"8d0" => data <= x"e6";
when "00" & x"8d1" => data <= x"3e";
when "00" & x"8d2" => data <= x"10";
when "00" & x"8d3" => data <= x"c9";
when "00" & x"8d4" => data <= x"48";
when "00" & x"8d5" => data <= x"68";
when "00" & x"8d6" => data <= x"a0";
when "00" & x"8d7" => data <= x"00";
when "00" & x"8d8" => data <= x"38";
when "00" & x"8d9" => data <= x"60";
when "00" & x"8da" => data <= x"88";
when "00" & x"8db" => data <= x"a9";
when "00" & x"8dc" => data <= x"8d";
when "00" & x"8dd" => data <= x"20";
when "00" & x"8de" => data <= x"7c";
when "00" & x"8df" => data <= x"88";
when "00" & x"8e0" => data <= x"a5";
when "00" & x"8e1" => data <= x"37";
when "00" & x"8e2" => data <= x"69";
when "00" & x"8e3" => data <= x"02";
when "00" & x"8e4" => data <= x"85";
when "00" & x"8e5" => data <= x"39";
when "00" & x"8e6" => data <= x"a5";
when "00" & x"8e7" => data <= x"38";
when "00" & x"8e8" => data <= x"69";
when "00" & x"8e9" => data <= x"00";
when "00" & x"8ea" => data <= x"85";
when "00" & x"8eb" => data <= x"3a";
when "00" & x"8ec" => data <= x"b1";
when "00" & x"8ed" => data <= x"37";
when "00" & x"8ee" => data <= x"91";
when "00" & x"8ef" => data <= x"39";
when "00" & x"8f0" => data <= x"88";
when "00" & x"8f1" => data <= x"d0";
when "00" & x"8f2" => data <= x"f9";
when "00" & x"8f3" => data <= x"a0";
when "00" & x"8f4" => data <= x"03";
when "00" & x"8f5" => data <= x"a5";
when "00" & x"8f6" => data <= x"3e";
when "00" & x"8f7" => data <= x"09";
when "00" & x"8f8" => data <= x"40";
when "00" & x"8f9" => data <= x"91";
when "00" & x"8fa" => data <= x"37";
when "00" & x"8fb" => data <= x"88";
when "00" & x"8fc" => data <= x"a5";
when "00" & x"8fd" => data <= x"3d";
when "00" & x"8fe" => data <= x"29";
when "00" & x"8ff" => data <= x"3f";
when "00" & x"900" => data <= x"09";
when "00" & x"901" => data <= x"40";
when "00" & x"902" => data <= x"91";
when "00" & x"903" => data <= x"37";
when "00" & x"904" => data <= x"88";
when "00" & x"905" => data <= x"a5";
when "00" & x"906" => data <= x"3d";
when "00" & x"907" => data <= x"29";
when "00" & x"908" => data <= x"c0";
when "00" & x"909" => data <= x"85";
when "00" & x"90a" => data <= x"3d";
when "00" & x"90b" => data <= x"a5";
when "00" & x"90c" => data <= x"3e";
when "00" & x"90d" => data <= x"29";
when "00" & x"90e" => data <= x"c0";
when "00" & x"90f" => data <= x"4a";
when "00" & x"910" => data <= x"4a";
when "00" & x"911" => data <= x"05";
when "00" & x"912" => data <= x"3d";
when "00" & x"913" => data <= x"4a";
when "00" & x"914" => data <= x"4a";
when "00" & x"915" => data <= x"49";
when "00" & x"916" => data <= x"54";
when "00" & x"917" => data <= x"91";
when "00" & x"918" => data <= x"37";
when "00" & x"919" => data <= x"20";
when "00" & x"91a" => data <= x"44";
when "00" & x"91b" => data <= x"89";
when "00" & x"91c" => data <= x"20";
when "00" & x"91d" => data <= x"44";
when "00" & x"91e" => data <= x"89";
when "00" & x"91f" => data <= x"20";
when "00" & x"920" => data <= x"44";
when "00" & x"921" => data <= x"89";
when "00" & x"922" => data <= x"a0";
when "00" & x"923" => data <= x"00";
when "00" & x"924" => data <= x"18";
when "00" & x"925" => data <= x"60";
when "00" & x"926" => data <= x"c9";
when "00" & x"927" => data <= x"7b";
when "00" & x"928" => data <= x"b0";
when "00" & x"929" => data <= x"fa";
when "00" & x"92a" => data <= x"c9";
when "00" & x"92b" => data <= x"5f";
when "00" & x"92c" => data <= x"b0";
when "00" & x"92d" => data <= x"0e";
when "00" & x"92e" => data <= x"c9";
when "00" & x"92f" => data <= x"5b";
when "00" & x"930" => data <= x"b0";
when "00" & x"931" => data <= x"f2";
when "00" & x"932" => data <= x"c9";
when "00" & x"933" => data <= x"41";
when "00" & x"934" => data <= x"b0";
when "00" & x"935" => data <= x"06";
when "00" & x"936" => data <= x"c9";
when "00" & x"937" => data <= x"3a";
when "00" & x"938" => data <= x"b0";
when "00" & x"939" => data <= x"ea";
when "00" & x"93a" => data <= x"c9";
when "00" & x"93b" => data <= x"30";
when "00" & x"93c" => data <= x"60";
when "00" & x"93d" => data <= x"c9";
when "00" & x"93e" => data <= x"2e";
when "00" & x"93f" => data <= x"d0";
when "00" & x"940" => data <= x"f5";
when "00" & x"941" => data <= x"60";
when "00" & x"942" => data <= x"b1";
when "00" & x"943" => data <= x"37";
when "00" & x"944" => data <= x"e6";
when "00" & x"945" => data <= x"37";
when "00" & x"946" => data <= x"d0";
when "00" & x"947" => data <= x"02";
when "00" & x"948" => data <= x"e6";
when "00" & x"949" => data <= x"38";
when "00" & x"94a" => data <= x"60";
when "00" & x"94b" => data <= x"20";
when "00" & x"94c" => data <= x"44";
when "00" & x"94d" => data <= x"89";
when "00" & x"94e" => data <= x"b1";
when "00" & x"94f" => data <= x"37";
when "00" & x"950" => data <= x"60";
when "00" & x"951" => data <= x"a0";
when "00" & x"952" => data <= x"00";
when "00" & x"953" => data <= x"84";
when "00" & x"954" => data <= x"3b";
when "00" & x"955" => data <= x"84";
when "00" & x"956" => data <= x"3c";
when "00" & x"957" => data <= x"b1";
when "00" & x"958" => data <= x"37";
when "00" & x"959" => data <= x"c9";
when "00" & x"95a" => data <= x"0d";
when "00" & x"95b" => data <= x"f0";
when "00" & x"95c" => data <= x"ed";
when "00" & x"95d" => data <= x"c9";
when "00" & x"95e" => data <= x"20";
when "00" & x"95f" => data <= x"d0";
when "00" & x"960" => data <= x"05";
when "00" & x"961" => data <= x"20";
when "00" & x"962" => data <= x"44";
when "00" & x"963" => data <= x"89";
when "00" & x"964" => data <= x"d0";
when "00" & x"965" => data <= x"f1";
when "00" & x"966" => data <= x"c9";
when "00" & x"967" => data <= x"26";
when "00" & x"968" => data <= x"d0";
when "00" & x"969" => data <= x"12";
when "00" & x"96a" => data <= x"20";
when "00" & x"96b" => data <= x"4b";
when "00" & x"96c" => data <= x"89";
when "00" & x"96d" => data <= x"20";
when "00" & x"96e" => data <= x"36";
when "00" & x"96f" => data <= x"89";
when "00" & x"970" => data <= x"b0";
when "00" & x"971" => data <= x"f8";
when "00" & x"972" => data <= x"c9";
when "00" & x"973" => data <= x"41";
when "00" & x"974" => data <= x"90";
when "00" & x"975" => data <= x"e1";
when "00" & x"976" => data <= x"c9";
when "00" & x"977" => data <= x"47";
when "00" & x"978" => data <= x"90";
when "00" & x"979" => data <= x"f0";
when "00" & x"97a" => data <= x"b0";
when "00" & x"97b" => data <= x"db";
when "00" & x"97c" => data <= x"c9";
when "00" & x"97d" => data <= x"22";
when "00" & x"97e" => data <= x"d0";
when "00" & x"97f" => data <= x"0c";
when "00" & x"980" => data <= x"20";
when "00" & x"981" => data <= x"4b";
when "00" & x"982" => data <= x"89";
when "00" & x"983" => data <= x"c9";
when "00" & x"984" => data <= x"22";
when "00" & x"985" => data <= x"f0";
when "00" & x"986" => data <= x"da";
when "00" & x"987" => data <= x"c9";
when "00" & x"988" => data <= x"0d";
when "00" & x"989" => data <= x"d0";
when "00" & x"98a" => data <= x"f5";
when "00" & x"98b" => data <= x"60";
when "00" & x"98c" => data <= x"c9";
when "00" & x"98d" => data <= x"3a";
when "00" & x"98e" => data <= x"d0";
when "00" & x"98f" => data <= x"06";
when "00" & x"990" => data <= x"84";
when "00" & x"991" => data <= x"3b";
when "00" & x"992" => data <= x"84";
when "00" & x"993" => data <= x"3c";
when "00" & x"994" => data <= x"f0";
when "00" & x"995" => data <= x"cb";
when "00" & x"996" => data <= x"c9";
when "00" & x"997" => data <= x"2c";
when "00" & x"998" => data <= x"f0";
when "00" & x"999" => data <= x"c7";
when "00" & x"99a" => data <= x"c9";
when "00" & x"99b" => data <= x"2a";
when "00" & x"99c" => data <= x"d0";
when "00" & x"99d" => data <= x"05";
when "00" & x"99e" => data <= x"a5";
when "00" & x"99f" => data <= x"3b";
when "00" & x"9a0" => data <= x"d0";
when "00" & x"9a1" => data <= x"41";
when "00" & x"9a2" => data <= x"60";
when "00" & x"9a3" => data <= x"c9";
when "00" & x"9a4" => data <= x"2e";
when "00" & x"9a5" => data <= x"f0";
when "00" & x"9a6" => data <= x"0e";
when "00" & x"9a7" => data <= x"20";
when "00" & x"9a8" => data <= x"36";
when "00" & x"9a9" => data <= x"89";
when "00" & x"9aa" => data <= x"90";
when "00" & x"9ab" => data <= x"33";
when "00" & x"9ac" => data <= x"a6";
when "00" & x"9ad" => data <= x"3c";
when "00" & x"9ae" => data <= x"f0";
when "00" & x"9af" => data <= x"05";
when "00" & x"9b0" => data <= x"20";
when "00" & x"9b1" => data <= x"97";
when "00" & x"9b2" => data <= x"88";
when "00" & x"9b3" => data <= x"90";
when "00" & x"9b4" => data <= x"34";
when "00" & x"9b5" => data <= x"b1";
when "00" & x"9b6" => data <= x"37";
when "00" & x"9b7" => data <= x"20";
when "00" & x"9b8" => data <= x"3d";
when "00" & x"9b9" => data <= x"89";
when "00" & x"9ba" => data <= x"90";
when "00" & x"9bb" => data <= x"06";
when "00" & x"9bc" => data <= x"20";
when "00" & x"9bd" => data <= x"44";
when "00" & x"9be" => data <= x"89";
when "00" & x"9bf" => data <= x"4c";
when "00" & x"9c0" => data <= x"b5";
when "00" & x"9c1" => data <= x"89";
when "00" & x"9c2" => data <= x"a2";
when "00" & x"9c3" => data <= x"ff";
when "00" & x"9c4" => data <= x"86";
when "00" & x"9c5" => data <= x"3b";
when "00" & x"9c6" => data <= x"84";
when "00" & x"9c7" => data <= x"3c";
when "00" & x"9c8" => data <= x"4c";
when "00" & x"9c9" => data <= x"57";
when "00" & x"9ca" => data <= x"89";
when "00" & x"9cb" => data <= x"20";
when "00" & x"9cc" => data <= x"26";
when "00" & x"9cd" => data <= x"89";
when "00" & x"9ce" => data <= x"90";
when "00" & x"9cf" => data <= x"13";
when "00" & x"9d0" => data <= x"a0";
when "00" & x"9d1" => data <= x"00";
when "00" & x"9d2" => data <= x"b1";
when "00" & x"9d3" => data <= x"37";
when "00" & x"9d4" => data <= x"20";
when "00" & x"9d5" => data <= x"26";
when "00" & x"9d6" => data <= x"89";
when "00" & x"9d7" => data <= x"90";
when "00" & x"9d8" => data <= x"e9";
when "00" & x"9d9" => data <= x"20";
when "00" & x"9da" => data <= x"44";
when "00" & x"9db" => data <= x"89";
when "00" & x"9dc" => data <= x"4c";
when "00" & x"9dd" => data <= x"d2";
when "00" & x"9de" => data <= x"89";
when "00" & x"9df" => data <= x"c9";
when "00" & x"9e0" => data <= x"41";
when "00" & x"9e1" => data <= x"b0";
when "00" & x"9e2" => data <= x"09";
when "00" & x"9e3" => data <= x"a2";
when "00" & x"9e4" => data <= x"ff";
when "00" & x"9e5" => data <= x"86";
when "00" & x"9e6" => data <= x"3b";
when "00" & x"9e7" => data <= x"84";
when "00" & x"9e8" => data <= x"3c";
when "00" & x"9e9" => data <= x"4c";
when "00" & x"9ea" => data <= x"61";
when "00" & x"9eb" => data <= x"89";
when "00" & x"9ec" => data <= x"c9";
when "00" & x"9ed" => data <= x"58";
when "00" & x"9ee" => data <= x"b0";
when "00" & x"9ef" => data <= x"db";
when "00" & x"9f0" => data <= x"a2";
when "00" & x"9f1" => data <= x"71";
when "00" & x"9f2" => data <= x"86";
when "00" & x"9f3" => data <= x"39";
when "00" & x"9f4" => data <= x"a2";
when "00" & x"9f5" => data <= x"80";
when "00" & x"9f6" => data <= x"86";
when "00" & x"9f7" => data <= x"3a";
when "00" & x"9f8" => data <= x"d1";
when "00" & x"9f9" => data <= x"39";
when "00" & x"9fa" => data <= x"90";
when "00" & x"9fb" => data <= x"d6";
when "00" & x"9fc" => data <= x"d0";
when "00" & x"9fd" => data <= x"0f";
when "00" & x"9fe" => data <= x"c8";
when "00" & x"9ff" => data <= x"b1";
when "00" & x"a00" => data <= x"39";
when "00" & x"a01" => data <= x"30";
when "00" & x"a02" => data <= x"34";
when "00" & x"a03" => data <= x"d1";
when "00" & x"a04" => data <= x"37";
when "00" & x"a05" => data <= x"f0";
when "00" & x"a06" => data <= x"f7";
when "00" & x"a07" => data <= x"b1";
when "00" & x"a08" => data <= x"37";
when "00" & x"a09" => data <= x"c9";
when "00" & x"a0a" => data <= x"2e";
when "00" & x"a0b" => data <= x"f0";
when "00" & x"a0c" => data <= x"0b";
when "00" & x"a0d" => data <= x"c8";
when "00" & x"a0e" => data <= x"b1";
when "00" & x"a0f" => data <= x"39";
when "00" & x"a10" => data <= x"10";
when "00" & x"a11" => data <= x"fb";
when "00" & x"a12" => data <= x"c9";
when "00" & x"a13" => data <= x"fe";
when "00" & x"a14" => data <= x"d0";
when "00" & x"a15" => data <= x"0f";
when "00" & x"a16" => data <= x"b0";
when "00" & x"a17" => data <= x"b8";
when "00" & x"a18" => data <= x"c8";
when "00" & x"a19" => data <= x"b1";
when "00" & x"a1a" => data <= x"39";
when "00" & x"a1b" => data <= x"30";
when "00" & x"a1c" => data <= x"1a";
when "00" & x"a1d" => data <= x"e6";
when "00" & x"a1e" => data <= x"39";
when "00" & x"a1f" => data <= x"d0";
when "00" & x"a20" => data <= x"f8";
when "00" & x"a21" => data <= x"e6";
when "00" & x"a22" => data <= x"3a";
when "00" & x"a23" => data <= x"d0";
when "00" & x"a24" => data <= x"f4";
when "00" & x"a25" => data <= x"38";
when "00" & x"a26" => data <= x"c8";
when "00" & x"a27" => data <= x"98";
when "00" & x"a28" => data <= x"65";
when "00" & x"a29" => data <= x"39";
when "00" & x"a2a" => data <= x"85";
when "00" & x"a2b" => data <= x"39";
when "00" & x"a2c" => data <= x"90";
when "00" & x"a2d" => data <= x"02";
when "00" & x"a2e" => data <= x"e6";
when "00" & x"a2f" => data <= x"3a";
when "00" & x"a30" => data <= x"a0";
when "00" & x"a31" => data <= x"00";
when "00" & x"a32" => data <= x"b1";
when "00" & x"a33" => data <= x"37";
when "00" & x"a34" => data <= x"4c";
when "00" & x"a35" => data <= x"f8";
when "00" & x"a36" => data <= x"89";
when "00" & x"a37" => data <= x"aa";
when "00" & x"a38" => data <= x"c8";
when "00" & x"a39" => data <= x"b1";
when "00" & x"a3a" => data <= x"39";
when "00" & x"a3b" => data <= x"85";
when "00" & x"a3c" => data <= x"3d";
when "00" & x"a3d" => data <= x"88";
when "00" & x"a3e" => data <= x"4a";
when "00" & x"a3f" => data <= x"90";
when "00" & x"a40" => data <= x"07";
when "00" & x"a41" => data <= x"b1";
when "00" & x"a42" => data <= x"37";
when "00" & x"a43" => data <= x"20";
when "00" & x"a44" => data <= x"26";
when "00" & x"a45" => data <= x"89";
when "00" & x"a46" => data <= x"b0";
when "00" & x"a47" => data <= x"88";
when "00" & x"a48" => data <= x"8a";
when "00" & x"a49" => data <= x"24";
when "00" & x"a4a" => data <= x"3d";
when "00" & x"a4b" => data <= x"50";
when "00" & x"a4c" => data <= x"07";
when "00" & x"a4d" => data <= x"a6";
when "00" & x"a4e" => data <= x"3b";
when "00" & x"a4f" => data <= x"d0";
when "00" & x"a50" => data <= x"03";
when "00" & x"a51" => data <= x"18";
when "00" & x"a52" => data <= x"69";
when "00" & x"a53" => data <= x"40";
when "00" & x"a54" => data <= x"88";
when "00" & x"a55" => data <= x"20";
when "00" & x"a56" => data <= x"7c";
when "00" & x"a57" => data <= x"88";
when "00" & x"a58" => data <= x"a0";
when "00" & x"a59" => data <= x"00";
when "00" & x"a5a" => data <= x"a2";
when "00" & x"a5b" => data <= x"ff";
when "00" & x"a5c" => data <= x"a5";
when "00" & x"a5d" => data <= x"3d";
when "00" & x"a5e" => data <= x"4a";
when "00" & x"a5f" => data <= x"4a";
when "00" & x"a60" => data <= x"90";
when "00" & x"a61" => data <= x"04";
when "00" & x"a62" => data <= x"86";
when "00" & x"a63" => data <= x"3b";
when "00" & x"a64" => data <= x"84";
when "00" & x"a65" => data <= x"3c";
when "00" & x"a66" => data <= x"4a";
when "00" & x"a67" => data <= x"90";
when "00" & x"a68" => data <= x"04";
when "00" & x"a69" => data <= x"84";
when "00" & x"a6a" => data <= x"3b";
when "00" & x"a6b" => data <= x"84";
when "00" & x"a6c" => data <= x"3c";
when "00" & x"a6d" => data <= x"4a";
when "00" & x"a6e" => data <= x"90";
when "00" & x"a6f" => data <= x"11";
when "00" & x"a70" => data <= x"48";
when "00" & x"a71" => data <= x"c8";
when "00" & x"a72" => data <= x"b1";
when "00" & x"a73" => data <= x"37";
when "00" & x"a74" => data <= x"20";
when "00" & x"a75" => data <= x"26";
when "00" & x"a76" => data <= x"89";
when "00" & x"a77" => data <= x"90";
when "00" & x"a78" => data <= x"06";
when "00" & x"a79" => data <= x"20";
when "00" & x"a7a" => data <= x"44";
when "00" & x"a7b" => data <= x"89";
when "00" & x"a7c" => data <= x"4c";
when "00" & x"a7d" => data <= x"72";
when "00" & x"a7e" => data <= x"8a";
when "00" & x"a7f" => data <= x"88";
when "00" & x"a80" => data <= x"68";
when "00" & x"a81" => data <= x"4a";
when "00" & x"a82" => data <= x"90";
when "00" & x"a83" => data <= x"02";
when "00" & x"a84" => data <= x"86";
when "00" & x"a85" => data <= x"3c";
when "00" & x"a86" => data <= x"4a";
when "00" & x"a87" => data <= x"b0";
when "00" & x"a88" => data <= x"0d";
when "00" & x"a89" => data <= x"4c";
when "00" & x"a8a" => data <= x"61";
when "00" & x"a8b" => data <= x"89";
when "00" & x"a8c" => data <= x"a4";
when "00" & x"a8d" => data <= x"1b";
when "00" & x"a8e" => data <= x"e6";
when "00" & x"a8f" => data <= x"1b";
when "00" & x"a90" => data <= x"b1";
when "00" & x"a91" => data <= x"19";
when "00" & x"a92" => data <= x"c9";
when "00" & x"a93" => data <= x"20";
when "00" & x"a94" => data <= x"f0";
when "00" & x"a95" => data <= x"f6";
when "00" & x"a96" => data <= x"60";
when "00" & x"a97" => data <= x"a4";
when "00" & x"a98" => data <= x"0a";
when "00" & x"a99" => data <= x"e6";
when "00" & x"a9a" => data <= x"0a";
when "00" & x"a9b" => data <= x"b1";
when "00" & x"a9c" => data <= x"0b";
when "00" & x"a9d" => data <= x"c9";
when "00" & x"a9e" => data <= x"20";
when "00" & x"a9f" => data <= x"f0";
when "00" & x"aa0" => data <= x"f6";
when "00" & x"aa1" => data <= x"60";
when "00" & x"aa2" => data <= x"00";
when "00" & x"aa3" => data <= x"05";
when "00" & x"aa4" => data <= x"4d";
when "00" & x"aa5" => data <= x"69";
when "00" & x"aa6" => data <= x"73";
when "00" & x"aa7" => data <= x"73";
when "00" & x"aa8" => data <= x"69";
when "00" & x"aa9" => data <= x"6e";
when "00" & x"aaa" => data <= x"67";
when "00" & x"aab" => data <= x"20";
when "00" & x"aac" => data <= x"2c";
when "00" & x"aad" => data <= x"00";
when "00" & x"aae" => data <= x"20";
when "00" & x"aaf" => data <= x"8c";
when "00" & x"ab0" => data <= x"8a";
when "00" & x"ab1" => data <= x"c9";
when "00" & x"ab2" => data <= x"2c";
when "00" & x"ab3" => data <= x"d0";
when "00" & x"ab4" => data <= x"ed";
when "00" & x"ab5" => data <= x"60";
when "00" & x"ab6" => data <= x"20";
when "00" & x"ab7" => data <= x"57";
when "00" & x"ab8" => data <= x"98";
when "00" & x"ab9" => data <= x"a5";
when "00" & x"aba" => data <= x"18";
when "00" & x"abb" => data <= x"85";
when "00" & x"abc" => data <= x"38";
when "00" & x"abd" => data <= x"a9";
when "00" & x"abe" => data <= x"00";
when "00" & x"abf" => data <= x"85";
when "00" & x"ac0" => data <= x"37";
when "00" & x"ac1" => data <= x"91";
when "00" & x"ac2" => data <= x"37";
when "00" & x"ac3" => data <= x"20";
when "00" & x"ac4" => data <= x"6f";
when "00" & x"ac5" => data <= x"be";
when "00" & x"ac6" => data <= x"d0";
when "00" & x"ac7" => data <= x"2b";
when "00" & x"ac8" => data <= x"20";
when "00" & x"ac9" => data <= x"57";
when "00" & x"aca" => data <= x"98";
when "00" & x"acb" => data <= x"20";
when "00" & x"acc" => data <= x"6f";
when "00" & x"acd" => data <= x"be";
when "00" & x"ace" => data <= x"d0";
when "00" & x"acf" => data <= x"26";
when "00" & x"ad0" => data <= x"20";
when "00" & x"ad1" => data <= x"57";
when "00" & x"ad2" => data <= x"98";
when "00" & x"ad3" => data <= x"00";
when "00" & x"ad4" => data <= x"00";
when "00" & x"ad5" => data <= x"53";
when "00" & x"ad6" => data <= x"54";
when "00" & x"ad7" => data <= x"4f";
when "00" & x"ad8" => data <= x"50";
when "00" & x"ad9" => data <= x"00";
when "00" & x"ada" => data <= x"20";
when "00" & x"adb" => data <= x"57";
when "00" & x"adc" => data <= x"98";
when "00" & x"add" => data <= x"a9";
when "00" & x"ade" => data <= x"0d";
when "00" & x"adf" => data <= x"a4";
when "00" & x"ae0" => data <= x"18";
when "00" & x"ae1" => data <= x"84";
when "00" & x"ae2" => data <= x"13";
when "00" & x"ae3" => data <= x"a0";
when "00" & x"ae4" => data <= x"00";
when "00" & x"ae5" => data <= x"84";
when "00" & x"ae6" => data <= x"12";
when "00" & x"ae7" => data <= x"84";
when "00" & x"ae8" => data <= x"20";
when "00" & x"ae9" => data <= x"91";
when "00" & x"aea" => data <= x"12";
when "00" & x"aeb" => data <= x"a9";
when "00" & x"aec" => data <= x"ff";
when "00" & x"aed" => data <= x"c8";
when "00" & x"aee" => data <= x"91";
when "00" & x"aef" => data <= x"12";
when "00" & x"af0" => data <= x"c8";
when "00" & x"af1" => data <= x"84";
when "00" & x"af2" => data <= x"12";
when "00" & x"af3" => data <= x"20";
when "00" & x"af4" => data <= x"20";
when "00" & x"af5" => data <= x"bd";
when "00" & x"af6" => data <= x"a0";
when "00" & x"af7" => data <= x"07";
when "00" & x"af8" => data <= x"84";
when "00" & x"af9" => data <= x"0c";
when "00" & x"afa" => data <= x"a0";
when "00" & x"afb" => data <= x"00";
when "00" & x"afc" => data <= x"84";
when "00" & x"afd" => data <= x"0b";
when "00" & x"afe" => data <= x"a9";
when "00" & x"aff" => data <= x"33";
when "00" & x"b00" => data <= x"85";
when "00" & x"b01" => data <= x"16";
when "00" & x"b02" => data <= x"a9";
when "00" & x"b03" => data <= x"b4";
when "00" & x"b04" => data <= x"85";
when "00" & x"b05" => data <= x"17";
when "00" & x"b06" => data <= x"a9";
when "00" & x"b07" => data <= x"3e";
when "00" & x"b08" => data <= x"20";
when "00" & x"b09" => data <= x"02";
when "00" & x"b0a" => data <= x"bc";
when "00" & x"b0b" => data <= x"a9";
when "00" & x"b0c" => data <= x"33";
when "00" & x"b0d" => data <= x"85";
when "00" & x"b0e" => data <= x"16";
when "00" & x"b0f" => data <= x"a9";
when "00" & x"b10" => data <= x"b4";
when "00" & x"b11" => data <= x"85";
when "00" & x"b12" => data <= x"17";
when "00" & x"b13" => data <= x"a2";
when "00" & x"b14" => data <= x"ff";
when "00" & x"b15" => data <= x"86";
when "00" & x"b16" => data <= x"28";
when "00" & x"b17" => data <= x"86";
when "00" & x"b18" => data <= x"3c";
when "00" & x"b19" => data <= x"9a";
when "00" & x"b1a" => data <= x"20";
when "00" & x"b1b" => data <= x"3a";
when "00" & x"b1c" => data <= x"bd";
when "00" & x"b1d" => data <= x"a8";
when "00" & x"b1e" => data <= x"a5";
when "00" & x"b1f" => data <= x"0b";
when "00" & x"b20" => data <= x"85";
when "00" & x"b21" => data <= x"37";
when "00" & x"b22" => data <= x"a5";
when "00" & x"b23" => data <= x"0c";
when "00" & x"b24" => data <= x"85";
when "00" & x"b25" => data <= x"38";
when "00" & x"b26" => data <= x"84";
when "00" & x"b27" => data <= x"3b";
when "00" & x"b28" => data <= x"84";
when "00" & x"b29" => data <= x"0a";
when "00" & x"b2a" => data <= x"20";
when "00" & x"b2b" => data <= x"57";
when "00" & x"b2c" => data <= x"89";
when "00" & x"b2d" => data <= x"20";
when "00" & x"b2e" => data <= x"df";
when "00" & x"b2f" => data <= x"97";
when "00" & x"b30" => data <= x"90";
when "00" & x"b31" => data <= x"06";
when "00" & x"b32" => data <= x"20";
when "00" & x"b33" => data <= x"8d";
when "00" & x"b34" => data <= x"bc";
when "00" & x"b35" => data <= x"4c";
when "00" & x"b36" => data <= x"f3";
when "00" & x"b37" => data <= x"8a";
when "00" & x"b38" => data <= x"20";
when "00" & x"b39" => data <= x"97";
when "00" & x"b3a" => data <= x"8a";
when "00" & x"b3b" => data <= x"c9";
when "00" & x"b3c" => data <= x"c6";
when "00" & x"b3d" => data <= x"b0";
when "00" & x"b3e" => data <= x"72";
when "00" & x"b3f" => data <= x"90";
when "00" & x"b40" => data <= x"7e";
when "00" & x"b41" => data <= x"4c";
when "00" & x"b42" => data <= x"f6";
when "00" & x"b43" => data <= x"8a";
when "00" & x"b44" => data <= x"4c";
when "00" & x"b45" => data <= x"04";
when "00" & x"b46" => data <= x"85";
when "00" & x"b47" => data <= x"ba";
when "00" & x"b48" => data <= x"e0";
when "00" & x"b49" => data <= x"fc";
when "00" & x"b4a" => data <= x"b0";
when "00" & x"b4b" => data <= x"0d";
when "00" & x"b4c" => data <= x"ad";
when "00" & x"b4d" => data <= x"ff";
when "00" & x"b4e" => data <= x"01";
when "00" & x"b4f" => data <= x"c9";
when "00" & x"b50" => data <= x"a4";
when "00" & x"b51" => data <= x"d0";
when "00" & x"b52" => data <= x"06";
when "00" & x"b53" => data <= x"20";
when "00" & x"b54" => data <= x"1d";
when "00" & x"b55" => data <= x"9b";
when "00" & x"b56" => data <= x"4c";
when "00" & x"b57" => data <= x"4c";
when "00" & x"b58" => data <= x"98";
when "00" & x"b59" => data <= x"00";
when "00" & x"b5a" => data <= x"07";
when "00" & x"b5b" => data <= x"4e";
when "00" & x"b5c" => data <= x"6f";
when "00" & x"b5d" => data <= x"20";
when "00" & x"b5e" => data <= x"a4";
when "00" & x"b5f" => data <= x"00";
when "00" & x"b60" => data <= x"a4";
when "00" & x"b61" => data <= x"0a";
when "00" & x"b62" => data <= x"88";
when "00" & x"b63" => data <= x"b1";
when "00" & x"b64" => data <= x"0b";
when "00" & x"b65" => data <= x"c9";
when "00" & x"b66" => data <= x"3d";
when "00" & x"b67" => data <= x"f0";
when "00" & x"b68" => data <= x"de";
when "00" & x"b69" => data <= x"c9";
when "00" & x"b6a" => data <= x"2a";
when "00" & x"b6b" => data <= x"f0";
when "00" & x"b6c" => data <= x"06";
when "00" & x"b6d" => data <= x"c9";
when "00" & x"b6e" => data <= x"5b";
when "00" & x"b6f" => data <= x"f0";
when "00" & x"b70" => data <= x"d3";
when "00" & x"b71" => data <= x"d0";
when "00" & x"b72" => data <= x"23";
when "00" & x"b73" => data <= x"20";
when "00" & x"b74" => data <= x"6d";
when "00" & x"b75" => data <= x"98";
when "00" & x"b76" => data <= x"a6";
when "00" & x"b77" => data <= x"0b";
when "00" & x"b78" => data <= x"a4";
when "00" & x"b79" => data <= x"0c";
when "00" & x"b7a" => data <= x"20";
when "00" & x"b7b" => data <= x"f7";
when "00" & x"b7c" => data <= x"ff";
when "00" & x"b7d" => data <= x"a9";
when "00" & x"b7e" => data <= x"0d";
when "00" & x"b7f" => data <= x"a4";
when "00" & x"b80" => data <= x"0a";
when "00" & x"b81" => data <= x"88";
when "00" & x"b82" => data <= x"c8";
when "00" & x"b83" => data <= x"d1";
when "00" & x"b84" => data <= x"0b";
when "00" & x"b85" => data <= x"d0";
when "00" & x"b86" => data <= x"fb";
when "00" & x"b87" => data <= x"c9";
when "00" & x"b88" => data <= x"8b";
when "00" & x"b89" => data <= x"f0";
when "00" & x"b8a" => data <= x"f2";
when "00" & x"b8b" => data <= x"a5";
when "00" & x"b8c" => data <= x"0c";
when "00" & x"b8d" => data <= x"c9";
when "00" & x"b8e" => data <= x"07";
when "00" & x"b8f" => data <= x"f0";
when "00" & x"b90" => data <= x"b0";
when "00" & x"b91" => data <= x"20";
when "00" & x"b92" => data <= x"90";
when "00" & x"b93" => data <= x"98";
when "00" & x"b94" => data <= x"d0";
when "00" & x"b95" => data <= x"0d";
when "00" & x"b96" => data <= x"c6";
when "00" & x"b97" => data <= x"0a";
when "00" & x"b98" => data <= x"20";
when "00" & x"b99" => data <= x"57";
when "00" & x"b9a" => data <= x"98";
when "00" & x"b9b" => data <= x"a0";
when "00" & x"b9c" => data <= x"00";
when "00" & x"b9d" => data <= x"b1";
when "00" & x"b9e" => data <= x"0b";
when "00" & x"b9f" => data <= x"c9";
when "00" & x"ba0" => data <= x"3a";
when "00" & x"ba1" => data <= x"d0";
when "00" & x"ba2" => data <= x"e4";
when "00" & x"ba3" => data <= x"a4";
when "00" & x"ba4" => data <= x"0a";
when "00" & x"ba5" => data <= x"e6";
when "00" & x"ba6" => data <= x"0a";
when "00" & x"ba7" => data <= x"b1";
when "00" & x"ba8" => data <= x"0b";
when "00" & x"ba9" => data <= x"c9";
when "00" & x"baa" => data <= x"20";
when "00" & x"bab" => data <= x"f0";
when "00" & x"bac" => data <= x"f6";
when "00" & x"bad" => data <= x"c9";
when "00" & x"bae" => data <= x"cf";
when "00" & x"baf" => data <= x"90";
when "00" & x"bb0" => data <= x"0e";
when "00" & x"bb1" => data <= x"aa";
when "00" & x"bb2" => data <= x"bd";
when "00" & x"bb3" => data <= x"df";
when "00" & x"bb4" => data <= x"82";
when "00" & x"bb5" => data <= x"85";
when "00" & x"bb6" => data <= x"37";
when "00" & x"bb7" => data <= x"bd";
when "00" & x"bb8" => data <= x"51";
when "00" & x"bb9" => data <= x"83";
when "00" & x"bba" => data <= x"85";
when "00" & x"bbb" => data <= x"38";
when "00" & x"bbc" => data <= x"6c";
when "00" & x"bbd" => data <= x"37";
when "00" & x"bbe" => data <= x"00";
when "00" & x"bbf" => data <= x"a6";
when "00" & x"bc0" => data <= x"0b";
when "00" & x"bc1" => data <= x"86";
when "00" & x"bc2" => data <= x"19";
when "00" & x"bc3" => data <= x"a6";
when "00" & x"bc4" => data <= x"0c";
when "00" & x"bc5" => data <= x"86";
when "00" & x"bc6" => data <= x"1a";
when "00" & x"bc7" => data <= x"84";
when "00" & x"bc8" => data <= x"1b";
when "00" & x"bc9" => data <= x"20";
when "00" & x"bca" => data <= x"dd";
when "00" & x"bcb" => data <= x"95";
when "00" & x"bcc" => data <= x"d0";
when "00" & x"bcd" => data <= x"1b";
when "00" & x"bce" => data <= x"b0";
when "00" & x"bcf" => data <= x"90";
when "00" & x"bd0" => data <= x"86";
when "00" & x"bd1" => data <= x"1b";
when "00" & x"bd2" => data <= x"20";
when "00" & x"bd3" => data <= x"41";
when "00" & x"bd4" => data <= x"98";
when "00" & x"bd5" => data <= x"20";
when "00" & x"bd6" => data <= x"fc";
when "00" & x"bd7" => data <= x"94";
when "00" & x"bd8" => data <= x"a2";
when "00" & x"bd9" => data <= x"05";
when "00" & x"bda" => data <= x"e4";
when "00" & x"bdb" => data <= x"2c";
when "00" & x"bdc" => data <= x"d0";
when "00" & x"bdd" => data <= x"01";
when "00" & x"bde" => data <= x"e8";
when "00" & x"bdf" => data <= x"20";
when "00" & x"be0" => data <= x"31";
when "00" & x"be1" => data <= x"95";
when "00" & x"be2" => data <= x"c6";
when "00" & x"be3" => data <= x"0a";
when "00" & x"be4" => data <= x"20";
when "00" & x"be5" => data <= x"82";
when "00" & x"be6" => data <= x"95";
when "00" & x"be7" => data <= x"f0";
when "00" & x"be8" => data <= x"22";
when "00" & x"be9" => data <= x"90";
when "00" & x"bea" => data <= x"10";
when "00" & x"beb" => data <= x"20";
when "00" & x"bec" => data <= x"94";
when "00" & x"bed" => data <= x"bd";
when "00" & x"bee" => data <= x"20";
when "00" & x"bef" => data <= x"13";
when "00" & x"bf0" => data <= x"98";
when "00" & x"bf1" => data <= x"a5";
when "00" & x"bf2" => data <= x"27";
when "00" & x"bf3" => data <= x"d0";
when "00" & x"bf4" => data <= x"19";
when "00" & x"bf5" => data <= x"20";
when "00" & x"bf6" => data <= x"1e";
when "00" & x"bf7" => data <= x"8c";
when "00" & x"bf8" => data <= x"4c";
when "00" & x"bf9" => data <= x"9b";
when "00" & x"bfa" => data <= x"8b";
when "00" & x"bfb" => data <= x"20";
when "00" & x"bfc" => data <= x"94";
when "00" & x"bfd" => data <= x"bd";
when "00" & x"bfe" => data <= x"20";
when "00" & x"bff" => data <= x"13";
when "00" & x"c00" => data <= x"98";
when "00" & x"c01" => data <= x"a5";
when "00" & x"c02" => data <= x"27";
when "00" & x"c03" => data <= x"f0";
when "00" & x"c04" => data <= x"09";
when "00" & x"c05" => data <= x"20";
when "00" & x"c06" => data <= x"b4";
when "00" & x"c07" => data <= x"b4";
when "00" & x"c08" => data <= x"4c";
when "00" & x"c09" => data <= x"9b";
when "00" & x"c0a" => data <= x"8b";
when "00" & x"c0b" => data <= x"4c";
when "00" & x"c0c" => data <= x"2a";
when "00" & x"c0d" => data <= x"98";
when "00" & x"c0e" => data <= x"00";
when "00" & x"c0f" => data <= x"06";
when "00" & x"c10" => data <= x"54";
when "00" & x"c11" => data <= x"79";
when "00" & x"c12" => data <= x"70";
when "00" & x"c13" => data <= x"65";
when "00" & x"c14" => data <= x"20";
when "00" & x"c15" => data <= x"6d";
when "00" & x"c16" => data <= x"69";
when "00" & x"c17" => data <= x"73";
when "00" & x"c18" => data <= x"6d";
when "00" & x"c19" => data <= x"61";
when "00" & x"c1a" => data <= x"74";
when "00" & x"c1b" => data <= x"63";
when "00" & x"c1c" => data <= x"68";
when "00" & x"c1d" => data <= x"00";
when "00" & x"c1e" => data <= x"20";
when "00" & x"c1f" => data <= x"ea";
when "00" & x"c20" => data <= x"bd";
when "00" & x"c21" => data <= x"a5";
when "00" & x"c22" => data <= x"2c";
when "00" & x"c23" => data <= x"c9";
when "00" & x"c24" => data <= x"80";
when "00" & x"c25" => data <= x"f0";
when "00" & x"c26" => data <= x"7b";
when "00" & x"c27" => data <= x"a0";
when "00" & x"c28" => data <= x"02";
when "00" & x"c29" => data <= x"b1";
when "00" & x"c2a" => data <= x"2a";
when "00" & x"c2b" => data <= x"c5";
when "00" & x"c2c" => data <= x"36";
when "00" & x"c2d" => data <= x"b0";
when "00" & x"c2e" => data <= x"55";
when "00" & x"c2f" => data <= x"a5";
when "00" & x"c30" => data <= x"02";
when "00" & x"c31" => data <= x"85";
when "00" & x"c32" => data <= x"2c";
when "00" & x"c33" => data <= x"a5";
when "00" & x"c34" => data <= x"03";
when "00" & x"c35" => data <= x"85";
when "00" & x"c36" => data <= x"2d";
when "00" & x"c37" => data <= x"a5";
when "00" & x"c38" => data <= x"36";
when "00" & x"c39" => data <= x"c9";
when "00" & x"c3a" => data <= x"08";
when "00" & x"c3b" => data <= x"90";
when "00" & x"c3c" => data <= x"06";
when "00" & x"c3d" => data <= x"69";
when "00" & x"c3e" => data <= x"07";
when "00" & x"c3f" => data <= x"90";
when "00" & x"c40" => data <= x"02";
when "00" & x"c41" => data <= x"a9";
when "00" & x"c42" => data <= x"ff";
when "00" & x"c43" => data <= x"18";
when "00" & x"c44" => data <= x"48";
when "00" & x"c45" => data <= x"aa";
when "00" & x"c46" => data <= x"b1";
when "00" & x"c47" => data <= x"2a";
when "00" & x"c48" => data <= x"a0";
when "00" & x"c49" => data <= x"00";
when "00" & x"c4a" => data <= x"71";
when "00" & x"c4b" => data <= x"2a";
when "00" & x"c4c" => data <= x"45";
when "00" & x"c4d" => data <= x"02";
when "00" & x"c4e" => data <= x"d0";
when "00" & x"c4f" => data <= x"0f";
when "00" & x"c50" => data <= x"c8";
when "00" & x"c51" => data <= x"71";
when "00" & x"c52" => data <= x"2a";
when "00" & x"c53" => data <= x"45";
when "00" & x"c54" => data <= x"03";
when "00" & x"c55" => data <= x"d0";
when "00" & x"c56" => data <= x"08";
when "00" & x"c57" => data <= x"85";
when "00" & x"c58" => data <= x"2d";
when "00" & x"c59" => data <= x"8a";
when "00" & x"c5a" => data <= x"c8";
when "00" & x"c5b" => data <= x"38";
when "00" & x"c5c" => data <= x"f1";
when "00" & x"c5d" => data <= x"2a";
when "00" & x"c5e" => data <= x"aa";
when "00" & x"c5f" => data <= x"8a";
when "00" & x"c60" => data <= x"18";
when "00" & x"c61" => data <= x"65";
when "00" & x"c62" => data <= x"02";
when "00" & x"c63" => data <= x"a8";
when "00" & x"c64" => data <= x"a5";
when "00" & x"c65" => data <= x"03";
when "00" & x"c66" => data <= x"69";
when "00" & x"c67" => data <= x"00";
when "00" & x"c68" => data <= x"c4";
when "00" & x"c69" => data <= x"04";
when "00" & x"c6a" => data <= x"aa";
when "00" & x"c6b" => data <= x"e5";
when "00" & x"c6c" => data <= x"05";
when "00" & x"c6d" => data <= x"b0";
when "00" & x"c6e" => data <= x"48";
when "00" & x"c6f" => data <= x"84";
when "00" & x"c70" => data <= x"02";
when "00" & x"c71" => data <= x"86";
when "00" & x"c72" => data <= x"03";
when "00" & x"c73" => data <= x"68";
when "00" & x"c74" => data <= x"a0";
when "00" & x"c75" => data <= x"02";
when "00" & x"c76" => data <= x"91";
when "00" & x"c77" => data <= x"2a";
when "00" & x"c78" => data <= x"88";
when "00" & x"c79" => data <= x"a5";
when "00" & x"c7a" => data <= x"2d";
when "00" & x"c7b" => data <= x"f0";
when "00" & x"c7c" => data <= x"07";
when "00" & x"c7d" => data <= x"91";
when "00" & x"c7e" => data <= x"2a";
when "00" & x"c7f" => data <= x"88";
when "00" & x"c80" => data <= x"a5";
when "00" & x"c81" => data <= x"2c";
when "00" & x"c82" => data <= x"91";
when "00" & x"c83" => data <= x"2a";
when "00" & x"c84" => data <= x"a0";
when "00" & x"c85" => data <= x"03";
when "00" & x"c86" => data <= x"a5";
when "00" & x"c87" => data <= x"36";
when "00" & x"c88" => data <= x"91";
when "00" & x"c89" => data <= x"2a";
when "00" & x"c8a" => data <= x"f0";
when "00" & x"c8b" => data <= x"15";
when "00" & x"c8c" => data <= x"88";
when "00" & x"c8d" => data <= x"88";
when "00" & x"c8e" => data <= x"b1";
when "00" & x"c8f" => data <= x"2a";
when "00" & x"c90" => data <= x"85";
when "00" & x"c91" => data <= x"2d";
when "00" & x"c92" => data <= x"88";
when "00" & x"c93" => data <= x"b1";
when "00" & x"c94" => data <= x"2a";
when "00" & x"c95" => data <= x"85";
when "00" & x"c96" => data <= x"2c";
when "00" & x"c97" => data <= x"b9";
when "00" & x"c98" => data <= x"00";
when "00" & x"c99" => data <= x"06";
when "00" & x"c9a" => data <= x"91";
when "00" & x"c9b" => data <= x"2c";
when "00" & x"c9c" => data <= x"c8";
when "00" & x"c9d" => data <= x"c4";
when "00" & x"c9e" => data <= x"36";
when "00" & x"c9f" => data <= x"d0";
when "00" & x"ca0" => data <= x"f6";
when "00" & x"ca1" => data <= x"60";
when "00" & x"ca2" => data <= x"20";
when "00" & x"ca3" => data <= x"ba";
when "00" & x"ca4" => data <= x"be";
when "00" & x"ca5" => data <= x"c0";
when "00" & x"ca6" => data <= x"00";
when "00" & x"ca7" => data <= x"f0";
when "00" & x"ca8" => data <= x"0b";
when "00" & x"ca9" => data <= x"b9";
when "00" & x"caa" => data <= x"00";
when "00" & x"cab" => data <= x"06";
when "00" & x"cac" => data <= x"91";
when "00" & x"cad" => data <= x"2a";
when "00" & x"cae" => data <= x"88";
when "00" & x"caf" => data <= x"d0";
when "00" & x"cb0" => data <= x"f8";
when "00" & x"cb1" => data <= x"ad";
when "00" & x"cb2" => data <= x"00";
when "00" & x"cb3" => data <= x"06";
when "00" & x"cb4" => data <= x"91";
when "00" & x"cb5" => data <= x"2a";
when "00" & x"cb6" => data <= x"60";
when "00" & x"cb7" => data <= x"00";
when "00" & x"cb8" => data <= x"00";
when "00" & x"cb9" => data <= x"4e";
when "00" & x"cba" => data <= x"6f";
when "00" & x"cbb" => data <= x"20";
when "00" & x"cbc" => data <= x"72";
when "00" & x"cbd" => data <= x"6f";
when "00" & x"cbe" => data <= x"6f";
when "00" & x"cbf" => data <= x"6d";
when "00" & x"cc0" => data <= x"00";
when "00" & x"cc1" => data <= x"a5";
when "00" & x"cc2" => data <= x"39";
when "00" & x"cc3" => data <= x"c9";
when "00" & x"cc4" => data <= x"80";
when "00" & x"cc5" => data <= x"f0";
when "00" & x"cc6" => data <= x"27";
when "00" & x"cc7" => data <= x"90";
when "00" & x"cc8" => data <= x"3a";
when "00" & x"cc9" => data <= x"a0";
when "00" & x"cca" => data <= x"00";
when "00" & x"ccb" => data <= x"b1";
when "00" & x"ccc" => data <= x"04";
when "00" & x"ccd" => data <= x"aa";
when "00" & x"cce" => data <= x"f0";
when "00" & x"ccf" => data <= x"15";
when "00" & x"cd0" => data <= x"b1";
when "00" & x"cd1" => data <= x"37";
when "00" & x"cd2" => data <= x"e9";
when "00" & x"cd3" => data <= x"01";
when "00" & x"cd4" => data <= x"85";
when "00" & x"cd5" => data <= x"39";
when "00" & x"cd6" => data <= x"c8";
when "00" & x"cd7" => data <= x"b1";
when "00" & x"cd8" => data <= x"37";
when "00" & x"cd9" => data <= x"e9";
when "00" & x"cda" => data <= x"00";
when "00" & x"cdb" => data <= x"85";
when "00" & x"cdc" => data <= x"3a";
when "00" & x"cdd" => data <= x"b1";
when "00" & x"cde" => data <= x"04";
when "00" & x"cdf" => data <= x"91";
when "00" & x"ce0" => data <= x"39";
when "00" & x"ce1" => data <= x"c8";
when "00" & x"ce2" => data <= x"ca";
when "00" & x"ce3" => data <= x"d0";
when "00" & x"ce4" => data <= x"f8";
when "00" & x"ce5" => data <= x"a1";
when "00" & x"ce6" => data <= x"04";
when "00" & x"ce7" => data <= x"a0";
when "00" & x"ce8" => data <= x"03";
when "00" & x"ce9" => data <= x"91";
when "00" & x"cea" => data <= x"37";
when "00" & x"ceb" => data <= x"4c";
when "00" & x"cec" => data <= x"dc";
when "00" & x"ced" => data <= x"bd";
when "00" & x"cee" => data <= x"a0";
when "00" & x"cef" => data <= x"00";
when "00" & x"cf0" => data <= x"b1";
when "00" & x"cf1" => data <= x"04";
when "00" & x"cf2" => data <= x"aa";
when "00" & x"cf3" => data <= x"f0";
when "00" & x"cf4" => data <= x"0a";
when "00" & x"cf5" => data <= x"c8";
when "00" & x"cf6" => data <= x"b1";
when "00" & x"cf7" => data <= x"04";
when "00" & x"cf8" => data <= x"88";
when "00" & x"cf9" => data <= x"91";
when "00" & x"cfa" => data <= x"37";
when "00" & x"cfb" => data <= x"c8";
when "00" & x"cfc" => data <= x"ca";
when "00" & x"cfd" => data <= x"d0";
when "00" & x"cfe" => data <= x"f6";
when "00" & x"cff" => data <= x"a9";
when "00" & x"d00" => data <= x"0d";
when "00" & x"d01" => data <= x"d0";
when "00" & x"d02" => data <= x"e6";
when "00" & x"d03" => data <= x"a0";
when "00" & x"d04" => data <= x"00";
when "00" & x"d05" => data <= x"b1";
when "00" & x"d06" => data <= x"04";
when "00" & x"d07" => data <= x"91";
when "00" & x"d08" => data <= x"37";
when "00" & x"d09" => data <= x"c8";
when "00" & x"d0a" => data <= x"c4";
when "00" & x"d0b" => data <= x"39";
when "00" & x"d0c" => data <= x"b0";
when "00" & x"d0d" => data <= x"18";
when "00" & x"d0e" => data <= x"b1";
when "00" & x"d0f" => data <= x"04";
when "00" & x"d10" => data <= x"91";
when "00" & x"d11" => data <= x"37";
when "00" & x"d12" => data <= x"c8";
when "00" & x"d13" => data <= x"b1";
when "00" & x"d14" => data <= x"04";
when "00" & x"d15" => data <= x"91";
when "00" & x"d16" => data <= x"37";
when "00" & x"d17" => data <= x"c8";
when "00" & x"d18" => data <= x"b1";
when "00" & x"d19" => data <= x"04";
when "00" & x"d1a" => data <= x"91";
when "00" & x"d1b" => data <= x"37";
when "00" & x"d1c" => data <= x"c8";
when "00" & x"d1d" => data <= x"c4";
when "00" & x"d1e" => data <= x"39";
when "00" & x"d1f" => data <= x"b0";
when "00" & x"d20" => data <= x"05";
when "00" & x"d21" => data <= x"b1";
when "00" & x"d22" => data <= x"04";
when "00" & x"d23" => data <= x"91";
when "00" & x"d24" => data <= x"37";
when "00" & x"d25" => data <= x"c8";
when "00" & x"d26" => data <= x"98";
when "00" & x"d27" => data <= x"18";
when "00" & x"d28" => data <= x"4c";
when "00" & x"d29" => data <= x"e1";
when "00" & x"d2a" => data <= x"bd";
when "00" & x"d2b" => data <= x"c6";
when "00" & x"d2c" => data <= x"0a";
when "00" & x"d2d" => data <= x"20";
when "00" & x"d2e" => data <= x"a9";
when "00" & x"d2f" => data <= x"bf";
when "00" & x"d30" => data <= x"98";
when "00" & x"d31" => data <= x"48";
when "00" & x"d32" => data <= x"20";
when "00" & x"d33" => data <= x"8c";
when "00" & x"d34" => data <= x"8a";
when "00" & x"d35" => data <= x"c9";
when "00" & x"d36" => data <= x"2c";
when "00" & x"d37" => data <= x"d0";
when "00" & x"d38" => data <= x"3e";
when "00" & x"d39" => data <= x"20";
when "00" & x"d3a" => data <= x"29";
when "00" & x"d3b" => data <= x"9b";
when "00" & x"d3c" => data <= x"20";
when "00" & x"d3d" => data <= x"85";
when "00" & x"d3e" => data <= x"a3";
when "00" & x"d3f" => data <= x"68";
when "00" & x"d40" => data <= x"a8";
when "00" & x"d41" => data <= x"a5";
when "00" & x"d42" => data <= x"27";
when "00" & x"d43" => data <= x"20";
when "00" & x"d44" => data <= x"d4";
when "00" & x"d45" => data <= x"ff";
when "00" & x"d46" => data <= x"aa";
when "00" & x"d47" => data <= x"f0";
when "00" & x"d48" => data <= x"1b";
when "00" & x"d49" => data <= x"30";
when "00" & x"d4a" => data <= x"0c";
when "00" & x"d4b" => data <= x"a2";
when "00" & x"d4c" => data <= x"03";
when "00" & x"d4d" => data <= x"b5";
when "00" & x"d4e" => data <= x"2a";
when "00" & x"d4f" => data <= x"20";
when "00" & x"d50" => data <= x"d4";
when "00" & x"d51" => data <= x"ff";
when "00" & x"d52" => data <= x"ca";
when "00" & x"d53" => data <= x"10";
when "00" & x"d54" => data <= x"f8";
when "00" & x"d55" => data <= x"30";
when "00" & x"d56" => data <= x"d9";
when "00" & x"d57" => data <= x"a2";
when "00" & x"d58" => data <= x"04";
when "00" & x"d59" => data <= x"bd";
when "00" & x"d5a" => data <= x"6c";
when "00" & x"d5b" => data <= x"04";
when "00" & x"d5c" => data <= x"20";
when "00" & x"d5d" => data <= x"d4";
when "00" & x"d5e" => data <= x"ff";
when "00" & x"d5f" => data <= x"ca";
when "00" & x"d60" => data <= x"10";
when "00" & x"d61" => data <= x"f7";
when "00" & x"d62" => data <= x"30";
when "00" & x"d63" => data <= x"cc";
when "00" & x"d64" => data <= x"a5";
when "00" & x"d65" => data <= x"36";
when "00" & x"d66" => data <= x"20";
when "00" & x"d67" => data <= x"d4";
when "00" & x"d68" => data <= x"ff";
when "00" & x"d69" => data <= x"aa";
when "00" & x"d6a" => data <= x"f0";
when "00" & x"d6b" => data <= x"c4";
when "00" & x"d6c" => data <= x"bd";
when "00" & x"d6d" => data <= x"ff";
when "00" & x"d6e" => data <= x"05";
when "00" & x"d6f" => data <= x"20";
when "00" & x"d70" => data <= x"d4";
when "00" & x"d71" => data <= x"ff";
when "00" & x"d72" => data <= x"ca";
when "00" & x"d73" => data <= x"d0";
when "00" & x"d74" => data <= x"f7";
when "00" & x"d75" => data <= x"f0";
when "00" & x"d76" => data <= x"b9";
when "00" & x"d77" => data <= x"68";
when "00" & x"d78" => data <= x"84";
when "00" & x"d79" => data <= x"0a";
when "00" & x"d7a" => data <= x"4c";
when "00" & x"d7b" => data <= x"98";
when "00" & x"d7c" => data <= x"8b";
when "00" & x"d7d" => data <= x"20";
when "00" & x"d7e" => data <= x"25";
when "00" & x"d7f" => data <= x"bc";
when "00" & x"d80" => data <= x"4c";
when "00" & x"d81" => data <= x"96";
when "00" & x"d82" => data <= x"8b";
when "00" & x"d83" => data <= x"a9";
when "00" & x"d84" => data <= x"00";
when "00" & x"d85" => data <= x"85";
when "00" & x"d86" => data <= x"14";
when "00" & x"d87" => data <= x"85";
when "00" & x"d88" => data <= x"15";
when "00" & x"d89" => data <= x"20";
when "00" & x"d8a" => data <= x"97";
when "00" & x"d8b" => data <= x"8a";
when "00" & x"d8c" => data <= x"c9";
when "00" & x"d8d" => data <= x"3a";
when "00" & x"d8e" => data <= x"f0";
when "00" & x"d8f" => data <= x"f0";
when "00" & x"d90" => data <= x"c9";
when "00" & x"d91" => data <= x"0d";
when "00" & x"d92" => data <= x"f0";
when "00" & x"d93" => data <= x"ec";
when "00" & x"d94" => data <= x"c9";
when "00" & x"d95" => data <= x"8b";
when "00" & x"d96" => data <= x"f0";
when "00" & x"d97" => data <= x"e8";
when "00" & x"d98" => data <= x"d0";
when "00" & x"d99" => data <= x"38";
when "00" & x"d9a" => data <= x"20";
when "00" & x"d9b" => data <= x"97";
when "00" & x"d9c" => data <= x"8a";
when "00" & x"d9d" => data <= x"c9";
when "00" & x"d9e" => data <= x"23";
when "00" & x"d9f" => data <= x"f0";
when "00" & x"da0" => data <= x"8a";
when "00" & x"da1" => data <= x"c6";
when "00" & x"da2" => data <= x"0a";
when "00" & x"da3" => data <= x"4c";
when "00" & x"da4" => data <= x"bb";
when "00" & x"da5" => data <= x"8d";
when "00" & x"da6" => data <= x"ad";
when "00" & x"da7" => data <= x"00";
when "00" & x"da8" => data <= x"04";
when "00" & x"da9" => data <= x"f0";
when "00" & x"daa" => data <= x"10";
when "00" & x"dab" => data <= x"a5";
when "00" & x"dac" => data <= x"1e";
when "00" & x"dad" => data <= x"f0";
when "00" & x"dae" => data <= x"0c";
when "00" & x"daf" => data <= x"ed";
when "00" & x"db0" => data <= x"00";
when "00" & x"db1" => data <= x"04";
when "00" & x"db2" => data <= x"b0";
when "00" & x"db3" => data <= x"f9";
when "00" & x"db4" => data <= x"a8";
when "00" & x"db5" => data <= x"20";
when "00" & x"db6" => data <= x"65";
when "00" & x"db7" => data <= x"b5";
when "00" & x"db8" => data <= x"c8";
when "00" & x"db9" => data <= x"d0";
when "00" & x"dba" => data <= x"fa";
when "00" & x"dbb" => data <= x"18";
when "00" & x"dbc" => data <= x"ad";
when "00" & x"dbd" => data <= x"00";
when "00" & x"dbe" => data <= x"04";
when "00" & x"dbf" => data <= x"85";
when "00" & x"dc0" => data <= x"14";
when "00" & x"dc1" => data <= x"66";
when "00" & x"dc2" => data <= x"15";
when "00" & x"dc3" => data <= x"20";
when "00" & x"dc4" => data <= x"97";
when "00" & x"dc5" => data <= x"8a";
when "00" & x"dc6" => data <= x"c9";
when "00" & x"dc7" => data <= x"3a";
when "00" & x"dc8" => data <= x"f0";
when "00" & x"dc9" => data <= x"b3";
when "00" & x"dca" => data <= x"c9";
when "00" & x"dcb" => data <= x"0d";
when "00" & x"dcc" => data <= x"f0";
when "00" & x"dcd" => data <= x"af";
when "00" & x"dce" => data <= x"c9";
when "00" & x"dcf" => data <= x"8b";
when "00" & x"dd0" => data <= x"f0";
when "00" & x"dd1" => data <= x"ab";
when "00" & x"dd2" => data <= x"c9";
when "00" & x"dd3" => data <= x"7e";
when "00" & x"dd4" => data <= x"f0";
when "00" & x"dd5" => data <= x"eb";
when "00" & x"dd6" => data <= x"c9";
when "00" & x"dd7" => data <= x"2c";
when "00" & x"dd8" => data <= x"f0";
when "00" & x"dd9" => data <= x"cc";
when "00" & x"dda" => data <= x"c9";
when "00" & x"ddb" => data <= x"3b";
when "00" & x"ddc" => data <= x"f0";
when "00" & x"ddd" => data <= x"a5";
when "00" & x"dde" => data <= x"20";
when "00" & x"ddf" => data <= x"70";
when "00" & x"de0" => data <= x"8e";
when "00" & x"de1" => data <= x"90";
when "00" & x"de2" => data <= x"e0";
when "00" & x"de3" => data <= x"a5";
when "00" & x"de4" => data <= x"14";
when "00" & x"de5" => data <= x"48";
when "00" & x"de6" => data <= x"a5";
when "00" & x"de7" => data <= x"15";
when "00" & x"de8" => data <= x"48";
when "00" & x"de9" => data <= x"c6";
when "00" & x"dea" => data <= x"1b";
when "00" & x"deb" => data <= x"20";
when "00" & x"dec" => data <= x"29";
when "00" & x"ded" => data <= x"9b";
when "00" & x"dee" => data <= x"68";
when "00" & x"def" => data <= x"85";
when "00" & x"df0" => data <= x"15";
when "00" & x"df1" => data <= x"68";
when "00" & x"df2" => data <= x"85";
when "00" & x"df3" => data <= x"14";
when "00" & x"df4" => data <= x"a5";
when "00" & x"df5" => data <= x"1b";
when "00" & x"df6" => data <= x"85";
when "00" & x"df7" => data <= x"0a";
when "00" & x"df8" => data <= x"98";
when "00" & x"df9" => data <= x"f0";
when "00" & x"dfa" => data <= x"13";
when "00" & x"dfb" => data <= x"20";
when "00" & x"dfc" => data <= x"df";
when "00" & x"dfd" => data <= x"9e";
when "00" & x"dfe" => data <= x"a5";
when "00" & x"dff" => data <= x"14";
when "00" & x"e00" => data <= x"38";
when "00" & x"e01" => data <= x"e5";
when "00" & x"e02" => data <= x"36";
when "00" & x"e03" => data <= x"90";
when "00" & x"e04" => data <= x"09";
when "00" & x"e05" => data <= x"f0";
when "00" & x"e06" => data <= x"07";
when "00" & x"e07" => data <= x"a8";
when "00" & x"e08" => data <= x"20";
when "00" & x"e09" => data <= x"65";
when "00" & x"e0a" => data <= x"b5";
when "00" & x"e0b" => data <= x"88";
when "00" & x"e0c" => data <= x"d0";
when "00" & x"e0d" => data <= x"fa";
when "00" & x"e0e" => data <= x"a5";
when "00" & x"e0f" => data <= x"36";
when "00" & x"e10" => data <= x"f0";
when "00" & x"e11" => data <= x"b1";
when "00" & x"e12" => data <= x"a0";
when "00" & x"e13" => data <= x"00";
when "00" & x"e14" => data <= x"b9";
when "00" & x"e15" => data <= x"00";
when "00" & x"e16" => data <= x"06";
when "00" & x"e17" => data <= x"20";
when "00" & x"e18" => data <= x"58";
when "00" & x"e19" => data <= x"b5";
when "00" & x"e1a" => data <= x"c8";
when "00" & x"e1b" => data <= x"c4";
when "00" & x"e1c" => data <= x"36";
when "00" & x"e1d" => data <= x"d0";
when "00" & x"e1e" => data <= x"f5";
when "00" & x"e1f" => data <= x"f0";
when "00" & x"e20" => data <= x"a2";
when "00" & x"e21" => data <= x"4c";
when "00" & x"e22" => data <= x"a2";
when "00" & x"e23" => data <= x"8a";
when "00" & x"e24" => data <= x"c9";
when "00" & x"e25" => data <= x"2c";
when "00" & x"e26" => data <= x"d0";
when "00" & x"e27" => data <= x"f9";
when "00" & x"e28" => data <= x"a5";
when "00" & x"e29" => data <= x"2a";
when "00" & x"e2a" => data <= x"48";
when "00" & x"e2b" => data <= x"20";
when "00" & x"e2c" => data <= x"56";
when "00" & x"e2d" => data <= x"ae";
when "00" & x"e2e" => data <= x"20";
when "00" & x"e2f" => data <= x"f0";
when "00" & x"e30" => data <= x"92";
when "00" & x"e31" => data <= x"a9";
when "00" & x"e32" => data <= x"1f";
when "00" & x"e33" => data <= x"20";
when "00" & x"e34" => data <= x"ee";
when "00" & x"e35" => data <= x"ff";
when "00" & x"e36" => data <= x"68";
when "00" & x"e37" => data <= x"20";
when "00" & x"e38" => data <= x"ee";
when "00" & x"e39" => data <= x"ff";
when "00" & x"e3a" => data <= x"20";
when "00" & x"e3b" => data <= x"56";
when "00" & x"e3c" => data <= x"94";
when "00" & x"e3d" => data <= x"4c";
when "00" & x"e3e" => data <= x"6a";
when "00" & x"e3f" => data <= x"8e";
when "00" & x"e40" => data <= x"20";
when "00" & x"e41" => data <= x"dd";
when "00" & x"e42" => data <= x"92";
when "00" & x"e43" => data <= x"20";
when "00" & x"e44" => data <= x"8c";
when "00" & x"e45" => data <= x"8a";
when "00" & x"e46" => data <= x"c9";
when "00" & x"e47" => data <= x"29";
when "00" & x"e48" => data <= x"d0";
when "00" & x"e49" => data <= x"da";
when "00" & x"e4a" => data <= x"a5";
when "00" & x"e4b" => data <= x"2a";
when "00" & x"e4c" => data <= x"e5";
when "00" & x"e4d" => data <= x"1e";
when "00" & x"e4e" => data <= x"f0";
when "00" & x"e4f" => data <= x"1a";
when "00" & x"e50" => data <= x"a8";
when "00" & x"e51" => data <= x"b0";
when "00" & x"e52" => data <= x"0c";
when "00" & x"e53" => data <= x"20";
when "00" & x"e54" => data <= x"25";
when "00" & x"e55" => data <= x"bc";
when "00" & x"e56" => data <= x"f0";
when "00" & x"e57" => data <= x"03";
when "00" & x"e58" => data <= x"20";
when "00" & x"e59" => data <= x"e3";
when "00" & x"e5a" => data <= x"92";
when "00" & x"e5b" => data <= x"a4";
when "00" & x"e5c" => data <= x"2a";
when "00" & x"e5d" => data <= x"f0";
when "00" & x"e5e" => data <= x"0b";
when "00" & x"e5f" => data <= x"20";
when "00" & x"e60" => data <= x"65";
when "00" & x"e61" => data <= x"b5";
when "00" & x"e62" => data <= x"88";
when "00" & x"e63" => data <= x"d0";
when "00" & x"e64" => data <= x"fa";
when "00" & x"e65" => data <= x"f0";
when "00" & x"e66" => data <= x"03";
when "00" & x"e67" => data <= x"20";
when "00" & x"e68" => data <= x"25";
when "00" & x"e69" => data <= x"bc";
when "00" & x"e6a" => data <= x"18";
when "00" & x"e6b" => data <= x"a4";
when "00" & x"e6c" => data <= x"1b";
when "00" & x"e6d" => data <= x"84";
when "00" & x"e6e" => data <= x"0a";
when "00" & x"e6f" => data <= x"60";
when "00" & x"e70" => data <= x"a6";
when "00" & x"e71" => data <= x"0b";
when "00" & x"e72" => data <= x"86";
when "00" & x"e73" => data <= x"19";
when "00" & x"e74" => data <= x"a6";
when "00" & x"e75" => data <= x"0c";
when "00" & x"e76" => data <= x"86";
when "00" & x"e77" => data <= x"1a";
when "00" & x"e78" => data <= x"a6";
when "00" & x"e79" => data <= x"0a";
when "00" & x"e7a" => data <= x"86";
when "00" & x"e7b" => data <= x"1b";
when "00" & x"e7c" => data <= x"c9";
when "00" & x"e7d" => data <= x"27";
when "00" & x"e7e" => data <= x"f0";
when "00" & x"e7f" => data <= x"e7";
when "00" & x"e80" => data <= x"c9";
when "00" & x"e81" => data <= x"8a";
when "00" & x"e82" => data <= x"f0";
when "00" & x"e83" => data <= x"bc";
when "00" & x"e84" => data <= x"c9";
when "00" & x"e85" => data <= x"89";
when "00" & x"e86" => data <= x"f0";
when "00" & x"e87" => data <= x"d0";
when "00" & x"e88" => data <= x"38";
when "00" & x"e89" => data <= x"60";
when "00" & x"e8a" => data <= x"20";
when "00" & x"e8b" => data <= x"97";
when "00" & x"e8c" => data <= x"8a";
when "00" & x"e8d" => data <= x"20";
when "00" & x"e8e" => data <= x"70";
when "00" & x"e8f" => data <= x"8e";
when "00" & x"e90" => data <= x"90";
when "00" & x"e91" => data <= x"f7";
when "00" & x"e92" => data <= x"c9";
when "00" & x"e93" => data <= x"22";
when "00" & x"e94" => data <= x"f0";
when "00" & x"e95" => data <= x"11";
when "00" & x"e96" => data <= x"38";
when "00" & x"e97" => data <= x"60";
when "00" & x"e98" => data <= x"00";
when "00" & x"e99" => data <= x"09";
when "00" & x"e9a" => data <= x"4d";
when "00" & x"e9b" => data <= x"69";
when "00" & x"e9c" => data <= x"73";
when "00" & x"e9d" => data <= x"73";
when "00" & x"e9e" => data <= x"69";
when "00" & x"e9f" => data <= x"6e";
when "00" & x"ea0" => data <= x"67";
when "00" & x"ea1" => data <= x"20";
when "00" & x"ea2" => data <= x"22";
when "00" & x"ea3" => data <= x"00";
when "00" & x"ea4" => data <= x"20";
when "00" & x"ea5" => data <= x"58";
when "00" & x"ea6" => data <= x"b5";
when "00" & x"ea7" => data <= x"c8";
when "00" & x"ea8" => data <= x"b1";
when "00" & x"ea9" => data <= x"19";
when "00" & x"eaa" => data <= x"c9";
when "00" & x"eab" => data <= x"0d";
when "00" & x"eac" => data <= x"f0";
when "00" & x"ead" => data <= x"ea";
when "00" & x"eae" => data <= x"c9";
when "00" & x"eaf" => data <= x"22";
when "00" & x"eb0" => data <= x"d0";
when "00" & x"eb1" => data <= x"f2";
when "00" & x"eb2" => data <= x"c8";
when "00" & x"eb3" => data <= x"84";
when "00" & x"eb4" => data <= x"1b";
when "00" & x"eb5" => data <= x"b1";
when "00" & x"eb6" => data <= x"19";
when "00" & x"eb7" => data <= x"c9";
when "00" & x"eb8" => data <= x"22";
when "00" & x"eb9" => data <= x"d0";
when "00" & x"eba" => data <= x"af";
when "00" & x"ebb" => data <= x"f0";
when "00" & x"ebc" => data <= x"e7";
when "00" & x"ebd" => data <= x"20";
when "00" & x"ebe" => data <= x"57";
when "00" & x"ebf" => data <= x"98";
when "00" & x"ec0" => data <= x"a9";
when "00" & x"ec1" => data <= x"10";
when "00" & x"ec2" => data <= x"d0";
when "00" & x"ec3" => data <= x"08";
when "00" & x"ec4" => data <= x"20";
when "00" & x"ec5" => data <= x"57";
when "00" & x"ec6" => data <= x"98";
when "00" & x"ec7" => data <= x"20";
when "00" & x"ec8" => data <= x"28";
when "00" & x"ec9" => data <= x"bc";
when "00" & x"eca" => data <= x"a9";
when "00" & x"ecb" => data <= x"0c";
when "00" & x"ecc" => data <= x"20";
when "00" & x"ecd" => data <= x"ee";
when "00" & x"ece" => data <= x"ff";
when "00" & x"ecf" => data <= x"4c";
when "00" & x"ed0" => data <= x"9b";
when "00" & x"ed1" => data <= x"8b";
when "00" & x"ed2" => data <= x"20";
when "00" & x"ed3" => data <= x"1d";
when "00" & x"ed4" => data <= x"9b";
when "00" & x"ed5" => data <= x"20";
when "00" & x"ed6" => data <= x"ee";
when "00" & x"ed7" => data <= x"92";
when "00" & x"ed8" => data <= x"20";
when "00" & x"ed9" => data <= x"94";
when "00" & x"eda" => data <= x"bd";
when "00" & x"edb" => data <= x"a0";
when "00" & x"edc" => data <= x"00";
when "00" & x"edd" => data <= x"8c";
when "00" & x"ede" => data <= x"00";
when "00" & x"edf" => data <= x"06";
when "00" & x"ee0" => data <= x"8c";
when "00" & x"ee1" => data <= x"ff";
when "00" & x"ee2" => data <= x"06";
when "00" & x"ee3" => data <= x"20";
when "00" & x"ee4" => data <= x"8c";
when "00" & x"ee5" => data <= x"8a";
when "00" & x"ee6" => data <= x"c9";
when "00" & x"ee7" => data <= x"2c";
when "00" & x"ee8" => data <= x"d0";
when "00" & x"ee9" => data <= x"22";
when "00" & x"eea" => data <= x"a4";
when "00" & x"eeb" => data <= x"1b";
when "00" & x"eec" => data <= x"20";
when "00" & x"eed" => data <= x"d5";
when "00" & x"eee" => data <= x"95";
when "00" & x"eef" => data <= x"f0";
when "00" & x"ef0" => data <= x"2a";
when "00" & x"ef1" => data <= x"ac";
when "00" & x"ef2" => data <= x"ff";
when "00" & x"ef3" => data <= x"06";
when "00" & x"ef4" => data <= x"c8";
when "00" & x"ef5" => data <= x"a5";
when "00" & x"ef6" => data <= x"2a";
when "00" & x"ef7" => data <= x"99";
when "00" & x"ef8" => data <= x"00";
when "00" & x"ef9" => data <= x"06";
when "00" & x"efa" => data <= x"c8";
when "00" & x"efb" => data <= x"a5";
when "00" & x"efc" => data <= x"2b";
when "00" & x"efd" => data <= x"99";
when "00" & x"efe" => data <= x"00";
when "00" & x"eff" => data <= x"06";
when "00" & x"f00" => data <= x"c8";
when "00" & x"f01" => data <= x"a5";
when "00" & x"f02" => data <= x"2c";
when "00" & x"f03" => data <= x"99";
when "00" & x"f04" => data <= x"00";
when "00" & x"f05" => data <= x"06";
when "00" & x"f06" => data <= x"ee";
when "00" & x"f07" => data <= x"00";
when "00" & x"f08" => data <= x"06";
when "00" & x"f09" => data <= x"4c";
when "00" & x"f0a" => data <= x"e0";
when "00" & x"f0b" => data <= x"8e";
when "00" & x"f0c" => data <= x"c6";
when "00" & x"f0d" => data <= x"1b";
when "00" & x"f0e" => data <= x"20";
when "00" & x"f0f" => data <= x"52";
when "00" & x"f10" => data <= x"98";
when "00" & x"f11" => data <= x"20";
when "00" & x"f12" => data <= x"ea";
when "00" & x"f13" => data <= x"bd";
when "00" & x"f14" => data <= x"20";
when "00" & x"f15" => data <= x"1e";
when "00" & x"f16" => data <= x"8f";
when "00" & x"f17" => data <= x"d8";
when "00" & x"f18" => data <= x"4c";
when "00" & x"f19" => data <= x"9b";
when "00" & x"f1a" => data <= x"8b";
when "00" & x"f1b" => data <= x"4c";
when "00" & x"f1c" => data <= x"43";
when "00" & x"f1d" => data <= x"ae";
when "00" & x"f1e" => data <= x"ad";
when "00" & x"f1f" => data <= x"0c";
when "00" & x"f20" => data <= x"04";
when "00" & x"f21" => data <= x"4a";
when "00" & x"f22" => data <= x"ad";
when "00" & x"f23" => data <= x"04";
when "00" & x"f24" => data <= x"04";
when "00" & x"f25" => data <= x"ae";
when "00" & x"f26" => data <= x"60";
when "00" & x"f27" => data <= x"04";
when "00" & x"f28" => data <= x"ac";
when "00" & x"f29" => data <= x"64";
when "00" & x"f2a" => data <= x"04";
when "00" & x"f2b" => data <= x"6c";
when "00" & x"f2c" => data <= x"2a";
when "00" & x"f2d" => data <= x"00";
when "00" & x"f2e" => data <= x"4c";
when "00" & x"f2f" => data <= x"2a";
when "00" & x"f30" => data <= x"98";
when "00" & x"f31" => data <= x"20";
when "00" & x"f32" => data <= x"df";
when "00" & x"f33" => data <= x"97";
when "00" & x"f34" => data <= x"90";
when "00" & x"f35" => data <= x"f8";
when "00" & x"f36" => data <= x"20";
when "00" & x"f37" => data <= x"94";
when "00" & x"f38" => data <= x"bd";
when "00" & x"f39" => data <= x"20";
when "00" & x"f3a" => data <= x"97";
when "00" & x"f3b" => data <= x"8a";
when "00" & x"f3c" => data <= x"c9";
when "00" & x"f3d" => data <= x"2c";
when "00" & x"f3e" => data <= x"d0";
when "00" & x"f3f" => data <= x"ee";
when "00" & x"f40" => data <= x"20";
when "00" & x"f41" => data <= x"df";
when "00" & x"f42" => data <= x"97";
when "00" & x"f43" => data <= x"90";
when "00" & x"f44" => data <= x"e9";
when "00" & x"f45" => data <= x"20";
when "00" & x"f46" => data <= x"57";
when "00" & x"f47" => data <= x"98";
when "00" & x"f48" => data <= x"a5";
when "00" & x"f49" => data <= x"2a";
when "00" & x"f4a" => data <= x"85";
when "00" & x"f4b" => data <= x"39";
when "00" & x"f4c" => data <= x"a5";
when "00" & x"f4d" => data <= x"2b";
when "00" & x"f4e" => data <= x"85";
when "00" & x"f4f" => data <= x"3a";
when "00" & x"f50" => data <= x"20";
when "00" & x"f51" => data <= x"ea";
when "00" & x"f52" => data <= x"bd";
when "00" & x"f53" => data <= x"20";
when "00" & x"f54" => data <= x"2d";
when "00" & x"f55" => data <= x"bc";
when "00" & x"f56" => data <= x"20";
when "00" & x"f57" => data <= x"7b";
when "00" & x"f58" => data <= x"98";
when "00" & x"f59" => data <= x"20";
when "00" & x"f5a" => data <= x"22";
when "00" & x"f5b" => data <= x"92";
when "00" & x"f5c" => data <= x"a5";
when "00" & x"f5d" => data <= x"39";
when "00" & x"f5e" => data <= x"c5";
when "00" & x"f5f" => data <= x"2a";
when "00" & x"f60" => data <= x"a5";
when "00" & x"f61" => data <= x"3a";
when "00" & x"f62" => data <= x"e5";
when "00" & x"f63" => data <= x"2b";
when "00" & x"f64" => data <= x"b0";
when "00" & x"f65" => data <= x"ed";
when "00" & x"f66" => data <= x"4c";
when "00" & x"f67" => data <= x"f3";
when "00" & x"f68" => data <= x"8a";
when "00" & x"f69" => data <= x"a9";
when "00" & x"f6a" => data <= x"0a";
when "00" & x"f6b" => data <= x"20";
when "00" & x"f6c" => data <= x"d8";
when "00" & x"f6d" => data <= x"ae";
when "00" & x"f6e" => data <= x"20";
when "00" & x"f6f" => data <= x"df";
when "00" & x"f70" => data <= x"97";
when "00" & x"f71" => data <= x"20";
when "00" & x"f72" => data <= x"94";
when "00" & x"f73" => data <= x"bd";
when "00" & x"f74" => data <= x"a9";
when "00" & x"f75" => data <= x"0a";
when "00" & x"f76" => data <= x"20";
when "00" & x"f77" => data <= x"d8";
when "00" & x"f78" => data <= x"ae";
when "00" & x"f79" => data <= x"20";
when "00" & x"f7a" => data <= x"97";
when "00" & x"f7b" => data <= x"8a";
when "00" & x"f7c" => data <= x"c9";
when "00" & x"f7d" => data <= x"2c";
when "00" & x"f7e" => data <= x"d0";
when "00" & x"f7f" => data <= x"0d";
when "00" & x"f80" => data <= x"20";
when "00" & x"f81" => data <= x"df";
when "00" & x"f82" => data <= x"97";
when "00" & x"f83" => data <= x"a5";
when "00" & x"f84" => data <= x"2b";
when "00" & x"f85" => data <= x"d0";
when "00" & x"f86" => data <= x"58";
when "00" & x"f87" => data <= x"a5";
when "00" & x"f88" => data <= x"2a";
when "00" & x"f89" => data <= x"f0";
when "00" & x"f8a" => data <= x"54";
when "00" & x"f8b" => data <= x"e6";
when "00" & x"f8c" => data <= x"0a";
when "00" & x"f8d" => data <= x"c6";
when "00" & x"f8e" => data <= x"0a";
when "00" & x"f8f" => data <= x"4c";
when "00" & x"f90" => data <= x"57";
when "00" & x"f91" => data <= x"98";
when "00" & x"f92" => data <= x"a5";
when "00" & x"f93" => data <= x"12";
when "00" & x"f94" => data <= x"85";
when "00" & x"f95" => data <= x"3b";
when "00" & x"f96" => data <= x"a5";
when "00" & x"f97" => data <= x"13";
when "00" & x"f98" => data <= x"85";
when "00" & x"f99" => data <= x"3c";
when "00" & x"f9a" => data <= x"a5";
when "00" & x"f9b" => data <= x"18";
when "00" & x"f9c" => data <= x"85";
when "00" & x"f9d" => data <= x"38";
when "00" & x"f9e" => data <= x"a9";
when "00" & x"f9f" => data <= x"01";
when "00" & x"fa0" => data <= x"85";
when "00" & x"fa1" => data <= x"37";
when "00" & x"fa2" => data <= x"60";
when "00" & x"fa3" => data <= x"20";
when "00" & x"fa4" => data <= x"69";
when "00" & x"fa5" => data <= x"8f";
when "00" & x"fa6" => data <= x"a2";
when "00" & x"fa7" => data <= x"39";
when "00" & x"fa8" => data <= x"20";
when "00" & x"fa9" => data <= x"0d";
when "00" & x"faa" => data <= x"be";
when "00" & x"fab" => data <= x"20";
when "00" & x"fac" => data <= x"6f";
when "00" & x"fad" => data <= x"be";
when "00" & x"fae" => data <= x"20";
when "00" & x"faf" => data <= x"92";
when "00" & x"fb0" => data <= x"8f";
when "00" & x"fb1" => data <= x"a0";
when "00" & x"fb2" => data <= x"00";
when "00" & x"fb3" => data <= x"b1";
when "00" & x"fb4" => data <= x"37";
when "00" & x"fb5" => data <= x"30";
when "00" & x"fb6" => data <= x"30";
when "00" & x"fb7" => data <= x"91";
when "00" & x"fb8" => data <= x"3b";
when "00" & x"fb9" => data <= x"c8";
when "00" & x"fba" => data <= x"b1";
when "00" & x"fbb" => data <= x"37";
when "00" & x"fbc" => data <= x"91";
when "00" & x"fbd" => data <= x"3b";
when "00" & x"fbe" => data <= x"38";
when "00" & x"fbf" => data <= x"98";
when "00" & x"fc0" => data <= x"65";
when "00" & x"fc1" => data <= x"3b";
when "00" & x"fc2" => data <= x"85";
when "00" & x"fc3" => data <= x"3b";
when "00" & x"fc4" => data <= x"aa";
when "00" & x"fc5" => data <= x"a5";
when "00" & x"fc6" => data <= x"3c";
when "00" & x"fc7" => data <= x"69";
when "00" & x"fc8" => data <= x"00";
when "00" & x"fc9" => data <= x"85";
when "00" & x"fca" => data <= x"3c";
when "00" & x"fcb" => data <= x"e4";
when "00" & x"fcc" => data <= x"06";
when "00" & x"fcd" => data <= x"e5";
when "00" & x"fce" => data <= x"07";
when "00" & x"fcf" => data <= x"b0";
when "00" & x"fd0" => data <= x"05";
when "00" & x"fd1" => data <= x"20";
when "00" & x"fd2" => data <= x"9f";
when "00" & x"fd3" => data <= x"90";
when "00" & x"fd4" => data <= x"90";
when "00" & x"fd5" => data <= x"db";
when "00" & x"fd6" => data <= x"00";
when "00" & x"fd7" => data <= x"00";
when "00" & x"fd8" => data <= x"cc";
when "00" & x"fd9" => data <= x"20";
when "00" & x"fda" => data <= x"73";
when "00" & x"fdb" => data <= x"70";
when "00" & x"fdc" => data <= x"61";
when "00" & x"fdd" => data <= x"63";
when "00" & x"fde" => data <= x"65";
when "00" & x"fdf" => data <= x"00";
when "00" & x"fe0" => data <= x"00";
when "00" & x"fe1" => data <= x"53";
when "00" & x"fe2" => data <= x"69";
when "00" & x"fe3" => data <= x"6c";
when "00" & x"fe4" => data <= x"6c";
when "00" & x"fe5" => data <= x"79";
when "00" & x"fe6" => data <= x"00";
when "00" & x"fe7" => data <= x"20";
when "00" & x"fe8" => data <= x"9a";
when "00" & x"fe9" => data <= x"8f";
when "00" & x"fea" => data <= x"a0";
when "00" & x"feb" => data <= x"00";
when "00" & x"fec" => data <= x"b1";
when "00" & x"fed" => data <= x"37";
when "00" & x"fee" => data <= x"30";
when "00" & x"fef" => data <= x"1d";
when "00" & x"ff0" => data <= x"a5";
when "00" & x"ff1" => data <= x"3a";
when "00" & x"ff2" => data <= x"91";
when "00" & x"ff3" => data <= x"37";
when "00" & x"ff4" => data <= x"a5";
when "00" & x"ff5" => data <= x"39";
when "00" & x"ff6" => data <= x"c8";
when "00" & x"ff7" => data <= x"91";
when "00" & x"ff8" => data <= x"37";
when "00" & x"ff9" => data <= x"18";
when "00" & x"ffa" => data <= x"a5";
when "00" & x"ffb" => data <= x"2a";
when "00" & x"ffc" => data <= x"65";
when "00" & x"ffd" => data <= x"39";
when "00" & x"ffe" => data <= x"85";
when "00" & x"fff" => data <= x"39";
when "01" & x"000" => data <= x"a9";
when "01" & x"001" => data <= x"00";
when "01" & x"002" => data <= x"65";
when "01" & x"003" => data <= x"3a";
when "01" & x"004" => data <= x"29";
when "01" & x"005" => data <= x"7f";
when "01" & x"006" => data <= x"85";
when "01" & x"007" => data <= x"3a";
when "01" & x"008" => data <= x"20";
when "01" & x"009" => data <= x"9f";
when "01" & x"00a" => data <= x"90";
when "01" & x"00b" => data <= x"90";
when "01" & x"00c" => data <= x"dd";
when "01" & x"00d" => data <= x"a5";
when "01" & x"00e" => data <= x"18";
when "01" & x"00f" => data <= x"85";
when "01" & x"010" => data <= x"0c";
when "01" & x"011" => data <= x"a0";
when "01" & x"012" => data <= x"00";
when "01" & x"013" => data <= x"84";
when "01" & x"014" => data <= x"0b";
when "01" & x"015" => data <= x"c8";
when "01" & x"016" => data <= x"b1";
when "01" & x"017" => data <= x"0b";
when "01" & x"018" => data <= x"30";
when "01" & x"019" => data <= x"20";
when "01" & x"01a" => data <= x"a0";
when "01" & x"01b" => data <= x"04";
when "01" & x"01c" => data <= x"b1";
when "01" & x"01d" => data <= x"0b";
when "01" & x"01e" => data <= x"c9";
when "01" & x"01f" => data <= x"8d";
when "01" & x"020" => data <= x"f0";
when "01" & x"021" => data <= x"1b";
when "01" & x"022" => data <= x"c8";
when "01" & x"023" => data <= x"c9";
when "01" & x"024" => data <= x"0d";
when "01" & x"025" => data <= x"d0";
when "01" & x"026" => data <= x"f5";
when "01" & x"027" => data <= x"b1";
when "01" & x"028" => data <= x"0b";
when "01" & x"029" => data <= x"30";
when "01" & x"02a" => data <= x"0f";
when "01" & x"02b" => data <= x"a0";
when "01" & x"02c" => data <= x"03";
when "01" & x"02d" => data <= x"b1";
when "01" & x"02e" => data <= x"0b";
when "01" & x"02f" => data <= x"18";
when "01" & x"030" => data <= x"65";
when "01" & x"031" => data <= x"0b";
when "01" & x"032" => data <= x"85";
when "01" & x"033" => data <= x"0b";
when "01" & x"034" => data <= x"90";
when "01" & x"035" => data <= x"e4";
when "01" & x"036" => data <= x"e6";
when "01" & x"037" => data <= x"0c";
when "01" & x"038" => data <= x"b0";
when "01" & x"039" => data <= x"e0";
when "01" & x"03a" => data <= x"4c";
when "01" & x"03b" => data <= x"f3";
when "01" & x"03c" => data <= x"8a";
when "01" & x"03d" => data <= x"20";
when "01" & x"03e" => data <= x"eb";
when "01" & x"03f" => data <= x"97";
when "01" & x"040" => data <= x"20";
when "01" & x"041" => data <= x"92";
when "01" & x"042" => data <= x"8f";
when "01" & x"043" => data <= x"a0";
when "01" & x"044" => data <= x"00";
when "01" & x"045" => data <= x"b1";
when "01" & x"046" => data <= x"37";
when "01" & x"047" => data <= x"30";
when "01" & x"048" => data <= x"37";
when "01" & x"049" => data <= x"b1";
when "01" & x"04a" => data <= x"3b";
when "01" & x"04b" => data <= x"c8";
when "01" & x"04c" => data <= x"c5";
when "01" & x"04d" => data <= x"2b";
when "01" & x"04e" => data <= x"d0";
when "01" & x"04f" => data <= x"21";
when "01" & x"050" => data <= x"b1";
when "01" & x"051" => data <= x"3b";
when "01" & x"052" => data <= x"c5";
when "01" & x"053" => data <= x"2a";
when "01" & x"054" => data <= x"d0";
when "01" & x"055" => data <= x"1b";
when "01" & x"056" => data <= x"b1";
when "01" & x"057" => data <= x"37";
when "01" & x"058" => data <= x"85";
when "01" & x"059" => data <= x"3d";
when "01" & x"05a" => data <= x"88";
when "01" & x"05b" => data <= x"b1";
when "01" & x"05c" => data <= x"37";
when "01" & x"05d" => data <= x"85";
when "01" & x"05e" => data <= x"3e";
when "01" & x"05f" => data <= x"a4";
when "01" & x"060" => data <= x"0a";
when "01" & x"061" => data <= x"88";
when "01" & x"062" => data <= x"a5";
when "01" & x"063" => data <= x"0b";
when "01" & x"064" => data <= x"85";
when "01" & x"065" => data <= x"37";
when "01" & x"066" => data <= x"a5";
when "01" & x"067" => data <= x"0c";
when "01" & x"068" => data <= x"85";
when "01" & x"069" => data <= x"38";
when "01" & x"06a" => data <= x"20";
when "01" & x"06b" => data <= x"f5";
when "01" & x"06c" => data <= x"88";
when "01" & x"06d" => data <= x"a4";
when "01" & x"06e" => data <= x"0a";
when "01" & x"06f" => data <= x"d0";
when "01" & x"070" => data <= x"ab";
when "01" & x"071" => data <= x"20";
when "01" & x"072" => data <= x"9f";
when "01" & x"073" => data <= x"90";
when "01" & x"074" => data <= x"a5";
when "01" & x"075" => data <= x"3b";
when "01" & x"076" => data <= x"69";
when "01" & x"077" => data <= x"02";
when "01" & x"078" => data <= x"85";
when "01" & x"079" => data <= x"3b";
when "01" & x"07a" => data <= x"90";
when "01" & x"07b" => data <= x"c7";
when "01" & x"07c" => data <= x"e6";
when "01" & x"07d" => data <= x"3c";
when "01" & x"07e" => data <= x"b0";
when "01" & x"07f" => data <= x"c3";
when "01" & x"080" => data <= x"20";
when "01" & x"081" => data <= x"cf";
when "01" & x"082" => data <= x"bf";
when "01" & x"083" => data <= x"46";
when "01" & x"084" => data <= x"61";
when "01" & x"085" => data <= x"69";
when "01" & x"086" => data <= x"6c";
when "01" & x"087" => data <= x"65";
when "01" & x"088" => data <= x"64";
when "01" & x"089" => data <= x"20";
when "01" & x"08a" => data <= x"61";
when "01" & x"08b" => data <= x"74";
when "01" & x"08c" => data <= x"20";
when "01" & x"08d" => data <= x"c8";
when "01" & x"08e" => data <= x"b1";
when "01" & x"08f" => data <= x"0b";
when "01" & x"090" => data <= x"85";
when "01" & x"091" => data <= x"2b";
when "01" & x"092" => data <= x"c8";
when "01" & x"093" => data <= x"b1";
when "01" & x"094" => data <= x"0b";
when "01" & x"095" => data <= x"85";
when "01" & x"096" => data <= x"2a";
when "01" & x"097" => data <= x"20";
when "01" & x"098" => data <= x"1f";
when "01" & x"099" => data <= x"99";
when "01" & x"09a" => data <= x"20";
when "01" & x"09b" => data <= x"25";
when "01" & x"09c" => data <= x"bc";
when "01" & x"09d" => data <= x"f0";
when "01" & x"09e" => data <= x"ce";
when "01" & x"09f" => data <= x"c8";
when "01" & x"0a0" => data <= x"b1";
when "01" & x"0a1" => data <= x"37";
when "01" & x"0a2" => data <= x"65";
when "01" & x"0a3" => data <= x"37";
when "01" & x"0a4" => data <= x"85";
when "01" & x"0a5" => data <= x"37";
when "01" & x"0a6" => data <= x"90";
when "01" & x"0a7" => data <= x"03";
when "01" & x"0a8" => data <= x"e6";
when "01" & x"0a9" => data <= x"38";
when "01" & x"0aa" => data <= x"18";
when "01" & x"0ab" => data <= x"60";
when "01" & x"0ac" => data <= x"20";
when "01" & x"0ad" => data <= x"69";
when "01" & x"0ae" => data <= x"8f";
when "01" & x"0af" => data <= x"a5";
when "01" & x"0b0" => data <= x"2a";
when "01" & x"0b1" => data <= x"48";
when "01" & x"0b2" => data <= x"20";
when "01" & x"0b3" => data <= x"ea";
when "01" & x"0b4" => data <= x"bd";
when "01" & x"0b5" => data <= x"20";
when "01" & x"0b6" => data <= x"94";
when "01" & x"0b7" => data <= x"bd";
when "01" & x"0b8" => data <= x"20";
when "01" & x"0b9" => data <= x"23";
when "01" & x"0ba" => data <= x"99";
when "01" & x"0bb" => data <= x"a9";
when "01" & x"0bc" => data <= x"20";
when "01" & x"0bd" => data <= x"20";
when "01" & x"0be" => data <= x"02";
when "01" & x"0bf" => data <= x"bc";
when "01" & x"0c0" => data <= x"20";
when "01" & x"0c1" => data <= x"ea";
when "01" & x"0c2" => data <= x"bd";
when "01" & x"0c3" => data <= x"20";
when "01" & x"0c4" => data <= x"51";
when "01" & x"0c5" => data <= x"89";
when "01" & x"0c6" => data <= x"20";
when "01" & x"0c7" => data <= x"8d";
when "01" & x"0c8" => data <= x"bc";
when "01" & x"0c9" => data <= x"20";
when "01" & x"0ca" => data <= x"20";
when "01" & x"0cb" => data <= x"bd";
when "01" & x"0cc" => data <= x"68";
when "01" & x"0cd" => data <= x"48";
when "01" & x"0ce" => data <= x"18";
when "01" & x"0cf" => data <= x"65";
when "01" & x"0d0" => data <= x"2a";
when "01" & x"0d1" => data <= x"85";
when "01" & x"0d2" => data <= x"2a";
when "01" & x"0d3" => data <= x"90";
when "01" & x"0d4" => data <= x"e0";
when "01" & x"0d5" => data <= x"e6";
when "01" & x"0d6" => data <= x"2b";
when "01" & x"0d7" => data <= x"10";
when "01" & x"0d8" => data <= x"dc";
when "01" & x"0d9" => data <= x"4c";
when "01" & x"0da" => data <= x"f3";
when "01" & x"0db" => data <= x"8a";
when "01" & x"0dc" => data <= x"4c";
when "01" & x"0dd" => data <= x"18";
when "01" & x"0de" => data <= x"92";
when "01" & x"0df" => data <= x"c6";
when "01" & x"0e0" => data <= x"0a";
when "01" & x"0e1" => data <= x"20";
when "01" & x"0e2" => data <= x"82";
when "01" & x"0e3" => data <= x"95";
when "01" & x"0e4" => data <= x"f0";
when "01" & x"0e5" => data <= x"41";
when "01" & x"0e6" => data <= x"b0";
when "01" & x"0e7" => data <= x"3f";
when "01" & x"0e8" => data <= x"20";
when "01" & x"0e9" => data <= x"94";
when "01" & x"0ea" => data <= x"bd";
when "01" & x"0eb" => data <= x"20";
when "01" & x"0ec" => data <= x"dd";
when "01" & x"0ed" => data <= x"92";
when "01" & x"0ee" => data <= x"20";
when "01" & x"0ef" => data <= x"22";
when "01" & x"0f0" => data <= x"92";
when "01" & x"0f1" => data <= x"a5";
when "01" & x"0f2" => data <= x"2d";
when "01" & x"0f3" => data <= x"05";
when "01" & x"0f4" => data <= x"2c";
when "01" & x"0f5" => data <= x"d0";
when "01" & x"0f6" => data <= x"30";
when "01" & x"0f7" => data <= x"18";
when "01" & x"0f8" => data <= x"a5";
when "01" & x"0f9" => data <= x"2a";
when "01" & x"0fa" => data <= x"65";
when "01" & x"0fb" => data <= x"02";
when "01" & x"0fc" => data <= x"a8";
when "01" & x"0fd" => data <= x"a5";
when "01" & x"0fe" => data <= x"2b";
when "01" & x"0ff" => data <= x"65";
when "01" & x"100" => data <= x"03";
when "01" & x"101" => data <= x"aa";
when "01" & x"102" => data <= x"c4";
when "01" & x"103" => data <= x"04";
when "01" & x"104" => data <= x"e5";
when "01" & x"105" => data <= x"05";
when "01" & x"106" => data <= x"b0";
when "01" & x"107" => data <= x"d4";
when "01" & x"108" => data <= x"a5";
when "01" & x"109" => data <= x"02";
when "01" & x"10a" => data <= x"85";
when "01" & x"10b" => data <= x"2a";
when "01" & x"10c" => data <= x"a5";
when "01" & x"10d" => data <= x"03";
when "01" & x"10e" => data <= x"85";
when "01" & x"10f" => data <= x"2b";
when "01" & x"110" => data <= x"84";
when "01" & x"111" => data <= x"02";
when "01" & x"112" => data <= x"86";
when "01" & x"113" => data <= x"03";
when "01" & x"114" => data <= x"a9";
when "01" & x"115" => data <= x"00";
when "01" & x"116" => data <= x"85";
when "01" & x"117" => data <= x"2c";
when "01" & x"118" => data <= x"85";
when "01" & x"119" => data <= x"2d";
when "01" & x"11a" => data <= x"a9";
when "01" & x"11b" => data <= x"40";
when "01" & x"11c" => data <= x"85";
when "01" & x"11d" => data <= x"27";
when "01" & x"11e" => data <= x"20";
when "01" & x"11f" => data <= x"b4";
when "01" & x"120" => data <= x"b4";
when "01" & x"121" => data <= x"20";
when "01" & x"122" => data <= x"27";
when "01" & x"123" => data <= x"88";
when "01" & x"124" => data <= x"4c";
when "01" & x"125" => data <= x"0b";
when "01" & x"126" => data <= x"92";
when "01" & x"127" => data <= x"00";
when "01" & x"128" => data <= x"0a";
when "01" & x"129" => data <= x"42";
when "01" & x"12a" => data <= x"61";
when "01" & x"12b" => data <= x"64";
when "01" & x"12c" => data <= x"20";
when "01" & x"12d" => data <= x"de";
when "01" & x"12e" => data <= x"00";
when "01" & x"12f" => data <= x"20";
when "01" & x"130" => data <= x"97";
when "01" & x"131" => data <= x"8a";
when "01" & x"132" => data <= x"98";
when "01" & x"133" => data <= x"18";
when "01" & x"134" => data <= x"65";
when "01" & x"135" => data <= x"0b";
when "01" & x"136" => data <= x"a6";
when "01" & x"137" => data <= x"0c";
when "01" & x"138" => data <= x"90";
when "01" & x"139" => data <= x"02";
when "01" & x"13a" => data <= x"e8";
when "01" & x"13b" => data <= x"18";
when "01" & x"13c" => data <= x"e9";
when "01" & x"13d" => data <= x"00";
when "01" & x"13e" => data <= x"85";
when "01" & x"13f" => data <= x"37";
when "01" & x"140" => data <= x"8a";
when "01" & x"141" => data <= x"e9";
when "01" & x"142" => data <= x"00";
when "01" & x"143" => data <= x"85";
when "01" & x"144" => data <= x"38";
when "01" & x"145" => data <= x"a2";
when "01" & x"146" => data <= x"05";
when "01" & x"147" => data <= x"86";
when "01" & x"148" => data <= x"3f";
when "01" & x"149" => data <= x"a6";
when "01" & x"14a" => data <= x"0a";
when "01" & x"14b" => data <= x"20";
when "01" & x"14c" => data <= x"59";
when "01" & x"14d" => data <= x"95";
when "01" & x"14e" => data <= x"c0";
when "01" & x"14f" => data <= x"01";
when "01" & x"150" => data <= x"f0";
when "01" & x"151" => data <= x"d5";
when "01" & x"152" => data <= x"c9";
when "01" & x"153" => data <= x"28";
when "01" & x"154" => data <= x"f0";
when "01" & x"155" => data <= x"15";
when "01" & x"156" => data <= x"c9";
when "01" & x"157" => data <= x"24";
when "01" & x"158" => data <= x"f0";
when "01" & x"159" => data <= x"04";
when "01" & x"15a" => data <= x"c9";
when "01" & x"15b" => data <= x"25";
when "01" & x"15c" => data <= x"d0";
when "01" & x"15d" => data <= x"0a";
when "01" & x"15e" => data <= x"c6";
when "01" & x"15f" => data <= x"3f";
when "01" & x"160" => data <= x"c8";
when "01" & x"161" => data <= x"e8";
when "01" & x"162" => data <= x"b1";
when "01" & x"163" => data <= x"37";
when "01" & x"164" => data <= x"c9";
when "01" & x"165" => data <= x"28";
when "01" & x"166" => data <= x"f0";
when "01" & x"167" => data <= x"03";
when "01" & x"168" => data <= x"4c";
when "01" & x"169" => data <= x"df";
when "01" & x"16a" => data <= x"90";
when "01" & x"16b" => data <= x"84";
when "01" & x"16c" => data <= x"39";
when "01" & x"16d" => data <= x"86";
when "01" & x"16e" => data <= x"0a";
when "01" & x"16f" => data <= x"20";
when "01" & x"170" => data <= x"69";
when "01" & x"171" => data <= x"94";
when "01" & x"172" => data <= x"d0";
when "01" & x"173" => data <= x"b3";
when "01" & x"174" => data <= x"20";
when "01" & x"175" => data <= x"fc";
when "01" & x"176" => data <= x"94";
when "01" & x"177" => data <= x"a2";
when "01" & x"178" => data <= x"01";
when "01" & x"179" => data <= x"20";
when "01" & x"17a" => data <= x"31";
when "01" & x"17b" => data <= x"95";
when "01" & x"17c" => data <= x"a5";
when "01" & x"17d" => data <= x"3f";
when "01" & x"17e" => data <= x"48";
when "01" & x"17f" => data <= x"a9";
when "01" & x"180" => data <= x"01";
when "01" & x"181" => data <= x"48";
when "01" & x"182" => data <= x"20";
when "01" & x"183" => data <= x"d8";
when "01" & x"184" => data <= x"ae";
when "01" & x"185" => data <= x"20";
when "01" & x"186" => data <= x"94";
when "01" & x"187" => data <= x"bd";
when "01" & x"188" => data <= x"20";
when "01" & x"189" => data <= x"21";
when "01" & x"18a" => data <= x"88";
when "01" & x"18b" => data <= x"a5";
when "01" & x"18c" => data <= x"2b";
when "01" & x"18d" => data <= x"29";
when "01" & x"18e" => data <= x"c0";
when "01" & x"18f" => data <= x"05";
when "01" & x"190" => data <= x"2c";
when "01" & x"191" => data <= x"05";
when "01" & x"192" => data <= x"2d";
when "01" & x"193" => data <= x"d0";
when "01" & x"194" => data <= x"92";
when "01" & x"195" => data <= x"20";
when "01" & x"196" => data <= x"22";
when "01" & x"197" => data <= x"92";
when "01" & x"198" => data <= x"68";
when "01" & x"199" => data <= x"a8";
when "01" & x"19a" => data <= x"a5";
when "01" & x"19b" => data <= x"2a";
when "01" & x"19c" => data <= x"91";
when "01" & x"19d" => data <= x"02";
when "01" & x"19e" => data <= x"c8";
when "01" & x"19f" => data <= x"a5";
when "01" & x"1a0" => data <= x"2b";
when "01" & x"1a1" => data <= x"91";
when "01" & x"1a2" => data <= x"02";
when "01" & x"1a3" => data <= x"c8";
when "01" & x"1a4" => data <= x"98";
when "01" & x"1a5" => data <= x"48";
when "01" & x"1a6" => data <= x"20";
when "01" & x"1a7" => data <= x"31";
when "01" & x"1a8" => data <= x"92";
when "01" & x"1a9" => data <= x"20";
when "01" & x"1aa" => data <= x"97";
when "01" & x"1ab" => data <= x"8a";
when "01" & x"1ac" => data <= x"c9";
when "01" & x"1ad" => data <= x"2c";
when "01" & x"1ae" => data <= x"f0";
when "01" & x"1af" => data <= x"d5";
when "01" & x"1b0" => data <= x"c9";
when "01" & x"1b1" => data <= x"29";
when "01" & x"1b2" => data <= x"f0";
when "01" & x"1b3" => data <= x"03";
when "01" & x"1b4" => data <= x"4c";
when "01" & x"1b5" => data <= x"27";
when "01" & x"1b6" => data <= x"91";
when "01" & x"1b7" => data <= x"68";
when "01" & x"1b8" => data <= x"85";
when "01" & x"1b9" => data <= x"15";
when "01" & x"1ba" => data <= x"68";
when "01" & x"1bb" => data <= x"85";
when "01" & x"1bc" => data <= x"3f";
when "01" & x"1bd" => data <= x"a9";
when "01" & x"1be" => data <= x"00";
when "01" & x"1bf" => data <= x"85";
when "01" & x"1c0" => data <= x"40";
when "01" & x"1c1" => data <= x"20";
when "01" & x"1c2" => data <= x"36";
when "01" & x"1c3" => data <= x"92";
when "01" & x"1c4" => data <= x"a0";
when "01" & x"1c5" => data <= x"00";
when "01" & x"1c6" => data <= x"a5";
when "01" & x"1c7" => data <= x"15";
when "01" & x"1c8" => data <= x"91";
when "01" & x"1c9" => data <= x"02";
when "01" & x"1ca" => data <= x"65";
when "01" & x"1cb" => data <= x"2a";
when "01" & x"1cc" => data <= x"85";
when "01" & x"1cd" => data <= x"2a";
when "01" & x"1ce" => data <= x"90";
when "01" & x"1cf" => data <= x"02";
when "01" & x"1d0" => data <= x"e6";
when "01" & x"1d1" => data <= x"2b";
when "01" & x"1d2" => data <= x"a5";
when "01" & x"1d3" => data <= x"03";
when "01" & x"1d4" => data <= x"85";
when "01" & x"1d5" => data <= x"38";
when "01" & x"1d6" => data <= x"a5";
when "01" & x"1d7" => data <= x"02";
when "01" & x"1d8" => data <= x"85";
when "01" & x"1d9" => data <= x"37";
when "01" & x"1da" => data <= x"18";
when "01" & x"1db" => data <= x"65";
when "01" & x"1dc" => data <= x"2a";
when "01" & x"1dd" => data <= x"a8";
when "01" & x"1de" => data <= x"a5";
when "01" & x"1df" => data <= x"2b";
when "01" & x"1e0" => data <= x"65";
when "01" & x"1e1" => data <= x"03";
when "01" & x"1e2" => data <= x"b0";
when "01" & x"1e3" => data <= x"34";
when "01" & x"1e4" => data <= x"aa";
when "01" & x"1e5" => data <= x"c4";
when "01" & x"1e6" => data <= x"04";
when "01" & x"1e7" => data <= x"e5";
when "01" & x"1e8" => data <= x"05";
when "01" & x"1e9" => data <= x"b0";
when "01" & x"1ea" => data <= x"2d";
when "01" & x"1eb" => data <= x"84";
when "01" & x"1ec" => data <= x"02";
when "01" & x"1ed" => data <= x"86";
when "01" & x"1ee" => data <= x"03";
when "01" & x"1ef" => data <= x"a5";
when "01" & x"1f0" => data <= x"37";
when "01" & x"1f1" => data <= x"65";
when "01" & x"1f2" => data <= x"15";
when "01" & x"1f3" => data <= x"a8";
when "01" & x"1f4" => data <= x"a9";
when "01" & x"1f5" => data <= x"00";
when "01" & x"1f6" => data <= x"85";
when "01" & x"1f7" => data <= x"37";
when "01" & x"1f8" => data <= x"90";
when "01" & x"1f9" => data <= x"02";
when "01" & x"1fa" => data <= x"e6";
when "01" & x"1fb" => data <= x"38";
when "01" & x"1fc" => data <= x"91";
when "01" & x"1fd" => data <= x"37";
when "01" & x"1fe" => data <= x"c8";
when "01" & x"1ff" => data <= x"d0";
when "01" & x"200" => data <= x"02";
when "01" & x"201" => data <= x"e6";
when "01" & x"202" => data <= x"38";
when "01" & x"203" => data <= x"c4";
when "01" & x"204" => data <= x"02";
when "01" & x"205" => data <= x"d0";
when "01" & x"206" => data <= x"f5";
when "01" & x"207" => data <= x"e4";
when "01" & x"208" => data <= x"38";
when "01" & x"209" => data <= x"d0";
when "01" & x"20a" => data <= x"f1";
when "01" & x"20b" => data <= x"20";
when "01" & x"20c" => data <= x"97";
when "01" & x"20d" => data <= x"8a";
when "01" & x"20e" => data <= x"c9";
when "01" & x"20f" => data <= x"2c";
when "01" & x"210" => data <= x"f0";
when "01" & x"211" => data <= x"03";
when "01" & x"212" => data <= x"4c";
when "01" & x"213" => data <= x"96";
when "01" & x"214" => data <= x"8b";
when "01" & x"215" => data <= x"4c";
when "01" & x"216" => data <= x"2f";
when "01" & x"217" => data <= x"91";
when "01" & x"218" => data <= x"00";
when "01" & x"219" => data <= x"0b";
when "01" & x"21a" => data <= x"de";
when "01" & x"21b" => data <= x"20";
when "01" & x"21c" => data <= x"73";
when "01" & x"21d" => data <= x"70";
when "01" & x"21e" => data <= x"61";
when "01" & x"21f" => data <= x"63";
when "01" & x"220" => data <= x"65";
when "01" & x"221" => data <= x"00";
when "01" & x"222" => data <= x"e6";
when "01" & x"223" => data <= x"2a";
when "01" & x"224" => data <= x"d0";
when "01" & x"225" => data <= x"0a";
when "01" & x"226" => data <= x"e6";
when "01" & x"227" => data <= x"2b";
when "01" & x"228" => data <= x"d0";
when "01" & x"229" => data <= x"06";
when "01" & x"22a" => data <= x"e6";
when "01" & x"22b" => data <= x"2c";
when "01" & x"22c" => data <= x"d0";
when "01" & x"22d" => data <= x"02";
when "01" & x"22e" => data <= x"e6";
when "01" & x"22f" => data <= x"2d";
when "01" & x"230" => data <= x"60";
when "01" & x"231" => data <= x"a2";
when "01" & x"232" => data <= x"3f";
when "01" & x"233" => data <= x"20";
when "01" & x"234" => data <= x"0d";
when "01" & x"235" => data <= x"be";
when "01" & x"236" => data <= x"a2";
when "01" & x"237" => data <= x"00";
when "01" & x"238" => data <= x"a0";
when "01" & x"239" => data <= x"00";
when "01" & x"23a" => data <= x"46";
when "01" & x"23b" => data <= x"40";
when "01" & x"23c" => data <= x"66";
when "01" & x"23d" => data <= x"3f";
when "01" & x"23e" => data <= x"90";
when "01" & x"23f" => data <= x"0b";
when "01" & x"240" => data <= x"18";
when "01" & x"241" => data <= x"98";
when "01" & x"242" => data <= x"65";
when "01" & x"243" => data <= x"2a";
when "01" & x"244" => data <= x"a8";
when "01" & x"245" => data <= x"8a";
when "01" & x"246" => data <= x"65";
when "01" & x"247" => data <= x"2b";
when "01" & x"248" => data <= x"aa";
when "01" & x"249" => data <= x"b0";
when "01" & x"24a" => data <= x"0f";
when "01" & x"24b" => data <= x"06";
when "01" & x"24c" => data <= x"2a";
when "01" & x"24d" => data <= x"26";
when "01" & x"24e" => data <= x"2b";
when "01" & x"24f" => data <= x"a5";
when "01" & x"250" => data <= x"3f";
when "01" & x"251" => data <= x"05";
when "01" & x"252" => data <= x"40";
when "01" & x"253" => data <= x"d0";
when "01" & x"254" => data <= x"e5";
when "01" & x"255" => data <= x"84";
when "01" & x"256" => data <= x"2a";
when "01" & x"257" => data <= x"86";
when "01" & x"258" => data <= x"2b";
when "01" & x"259" => data <= x"60";
when "01" & x"25a" => data <= x"4c";
when "01" & x"25b" => data <= x"27";
when "01" & x"25c" => data <= x"91";
when "01" & x"25d" => data <= x"20";
when "01" & x"25e" => data <= x"eb";
when "01" & x"25f" => data <= x"92";
when "01" & x"260" => data <= x"a5";
when "01" & x"261" => data <= x"2a";
when "01" & x"262" => data <= x"85";
when "01" & x"263" => data <= x"06";
when "01" & x"264" => data <= x"85";
when "01" & x"265" => data <= x"04";
when "01" & x"266" => data <= x"a5";
when "01" & x"267" => data <= x"2b";
when "01" & x"268" => data <= x"85";
when "01" & x"269" => data <= x"07";
when "01" & x"26a" => data <= x"85";
when "01" & x"26b" => data <= x"05";
when "01" & x"26c" => data <= x"4c";
when "01" & x"26d" => data <= x"9b";
when "01" & x"26e" => data <= x"8b";
when "01" & x"26f" => data <= x"20";
when "01" & x"270" => data <= x"eb";
when "01" & x"271" => data <= x"92";
when "01" & x"272" => data <= x"a5";
when "01" & x"273" => data <= x"2a";
when "01" & x"274" => data <= x"85";
when "01" & x"275" => data <= x"00";
when "01" & x"276" => data <= x"85";
when "01" & x"277" => data <= x"02";
when "01" & x"278" => data <= x"a5";
when "01" & x"279" => data <= x"2b";
when "01" & x"27a" => data <= x"85";
when "01" & x"27b" => data <= x"01";
when "01" & x"27c" => data <= x"85";
when "01" & x"27d" => data <= x"03";
when "01" & x"27e" => data <= x"20";
when "01" & x"27f" => data <= x"2f";
when "01" & x"280" => data <= x"bd";
when "01" & x"281" => data <= x"f0";
when "01" & x"282" => data <= x"07";
when "01" & x"283" => data <= x"20";
when "01" & x"284" => data <= x"eb";
when "01" & x"285" => data <= x"92";
when "01" & x"286" => data <= x"a5";
when "01" & x"287" => data <= x"2b";
when "01" & x"288" => data <= x"85";
when "01" & x"289" => data <= x"18";
when "01" & x"28a" => data <= x"4c";
when "01" & x"28b" => data <= x"9b";
when "01" & x"28c" => data <= x"8b";
when "01" & x"28d" => data <= x"20";
when "01" & x"28e" => data <= x"57";
when "01" & x"28f" => data <= x"98";
when "01" & x"290" => data <= x"20";
when "01" & x"291" => data <= x"20";
when "01" & x"292" => data <= x"bd";
when "01" & x"293" => data <= x"f0";
when "01" & x"294" => data <= x"f5";
when "01" & x"295" => data <= x"20";
when "01" & x"296" => data <= x"df";
when "01" & x"297" => data <= x"97";
when "01" & x"298" => data <= x"b0";
when "01" & x"299" => data <= x"0b";
when "01" & x"29a" => data <= x"c9";
when "01" & x"29b" => data <= x"ee";
when "01" & x"29c" => data <= x"f0";
when "01" & x"29d" => data <= x"19";
when "01" & x"29e" => data <= x"c9";
when "01" & x"29f" => data <= x"87";
when "01" & x"2a0" => data <= x"f0";
when "01" & x"2a1" => data <= x"1e";
when "01" & x"2a2" => data <= x"20";
when "01" & x"2a3" => data <= x"21";
when "01" & x"2a4" => data <= x"88";
when "01" & x"2a5" => data <= x"20";
when "01" & x"2a6" => data <= x"57";
when "01" & x"2a7" => data <= x"98";
when "01" & x"2a8" => data <= x"a5";
when "01" & x"2a9" => data <= x"2a";
when "01" & x"2aa" => data <= x"85";
when "01" & x"2ab" => data <= x"21";
when "01" & x"2ac" => data <= x"a5";
when "01" & x"2ad" => data <= x"2b";
when "01" & x"2ae" => data <= x"85";
when "01" & x"2af" => data <= x"22";
when "01" & x"2b0" => data <= x"a9";
when "01" & x"2b1" => data <= x"ff";
when "01" & x"2b2" => data <= x"85";
when "01" & x"2b3" => data <= x"20";
when "01" & x"2b4" => data <= x"4c";
when "01" & x"2b5" => data <= x"9b";
when "01" & x"2b6" => data <= x"8b";
when "01" & x"2b7" => data <= x"e6";
when "01" & x"2b8" => data <= x"0a";
when "01" & x"2b9" => data <= x"20";
when "01" & x"2ba" => data <= x"57";
when "01" & x"2bb" => data <= x"98";
when "01" & x"2bc" => data <= x"a9";
when "01" & x"2bd" => data <= x"ff";
when "01" & x"2be" => data <= x"d0";
when "01" & x"2bf" => data <= x"ee";
when "01" & x"2c0" => data <= x"e6";
when "01" & x"2c1" => data <= x"0a";
when "01" & x"2c2" => data <= x"20";
when "01" & x"2c3" => data <= x"57";
when "01" & x"2c4" => data <= x"98";
when "01" & x"2c5" => data <= x"a9";
when "01" & x"2c6" => data <= x"00";
when "01" & x"2c7" => data <= x"f0";
when "01" & x"2c8" => data <= x"e9";
when "01" & x"2c9" => data <= x"20";
when "01" & x"2ca" => data <= x"eb";
when "01" & x"2cb" => data <= x"92";
when "01" & x"2cc" => data <= x"a2";
when "01" & x"2cd" => data <= x"2a";
when "01" & x"2ce" => data <= x"a0";
when "01" & x"2cf" => data <= x"00";
when "01" & x"2d0" => data <= x"84";
when "01" & x"2d1" => data <= x"2e";
when "01" & x"2d2" => data <= x"a9";
when "01" & x"2d3" => data <= x"02";
when "01" & x"2d4" => data <= x"20";
when "01" & x"2d5" => data <= x"f1";
when "01" & x"2d6" => data <= x"ff";
when "01" & x"2d7" => data <= x"4c";
when "01" & x"2d8" => data <= x"9b";
when "01" & x"2d9" => data <= x"8b";
when "01" & x"2da" => data <= x"20";
when "01" & x"2db" => data <= x"ae";
when "01" & x"2dc" => data <= x"8a";
when "01" & x"2dd" => data <= x"20";
when "01" & x"2de" => data <= x"29";
when "01" & x"2df" => data <= x"9b";
when "01" & x"2e0" => data <= x"4c";
when "01" & x"2e1" => data <= x"f0";
when "01" & x"2e2" => data <= x"92";
when "01" & x"2e3" => data <= x"20";
when "01" & x"2e4" => data <= x"ec";
when "01" & x"2e5" => data <= x"ad";
when "01" & x"2e6" => data <= x"f0";
when "01" & x"2e7" => data <= x"0f";
when "01" & x"2e8" => data <= x"30";
when "01" & x"2e9" => data <= x"0a";
when "01" & x"2ea" => data <= x"60";
when "01" & x"2eb" => data <= x"20";
when "01" & x"2ec" => data <= x"07";
when "01" & x"2ed" => data <= x"98";
when "01" & x"2ee" => data <= x"a5";
when "01" & x"2ef" => data <= x"27";
when "01" & x"2f0" => data <= x"f0";
when "01" & x"2f1" => data <= x"05";
when "01" & x"2f2" => data <= x"10";
when "01" & x"2f3" => data <= x"f6";
when "01" & x"2f4" => data <= x"4c";
when "01" & x"2f5" => data <= x"e4";
when "01" & x"2f6" => data <= x"a3";
when "01" & x"2f7" => data <= x"4c";
when "01" & x"2f8" => data <= x"0e";
when "01" & x"2f9" => data <= x"8c";
when "01" & x"2fa" => data <= x"20";
when "01" & x"2fb" => data <= x"ec";
when "01" & x"2fc" => data <= x"ad";
when "01" & x"2fd" => data <= x"f0";
when "01" & x"2fe" => data <= x"f8";
when "01" & x"2ff" => data <= x"30";
when "01" & x"300" => data <= x"e9";
when "01" & x"301" => data <= x"4c";
when "01" & x"302" => data <= x"be";
when "01" & x"303" => data <= x"a2";
when "01" & x"304" => data <= x"a5";
when "01" & x"305" => data <= x"0b";
when "01" & x"306" => data <= x"85";
when "01" & x"307" => data <= x"19";
when "01" & x"308" => data <= x"a5";
when "01" & x"309" => data <= x"0c";
when "01" & x"30a" => data <= x"85";
when "01" & x"30b" => data <= x"1a";
when "01" & x"30c" => data <= x"a5";
when "01" & x"30d" => data <= x"0a";
when "01" & x"30e" => data <= x"85";
when "01" & x"30f" => data <= x"1b";
when "01" & x"310" => data <= x"a9";
when "01" & x"311" => data <= x"f2";
when "01" & x"312" => data <= x"20";
when "01" & x"313" => data <= x"97";
when "01" & x"314" => data <= x"b1";
when "01" & x"315" => data <= x"20";
when "01" & x"316" => data <= x"52";
when "01" & x"317" => data <= x"98";
when "01" & x"318" => data <= x"4c";
when "01" & x"319" => data <= x"9b";
when "01" & x"31a" => data <= x"8b";
when "01" & x"31b" => data <= x"a0";
when "01" & x"31c" => data <= x"03";
when "01" & x"31d" => data <= x"a9";
when "01" & x"31e" => data <= x"00";
when "01" & x"31f" => data <= x"91";
when "01" & x"320" => data <= x"2a";
when "01" & x"321" => data <= x"f0";
when "01" & x"322" => data <= x"1e";
when "01" & x"323" => data <= x"ba";
when "01" & x"324" => data <= x"e0";
when "01" & x"325" => data <= x"fc";
when "01" & x"326" => data <= x"b0";
when "01" & x"327" => data <= x"43";
when "01" & x"328" => data <= x"20";
when "01" & x"329" => data <= x"82";
when "01" & x"32a" => data <= x"95";
when "01" & x"32b" => data <= x"f0";
when "01" & x"32c" => data <= x"26";
when "01" & x"32d" => data <= x"20";
when "01" & x"32e" => data <= x"0d";
when "01" & x"32f" => data <= x"b3";
when "01" & x"330" => data <= x"a4";
when "01" & x"331" => data <= x"2c";
when "01" & x"332" => data <= x"30";
when "01" & x"333" => data <= x"e7";
when "01" & x"334" => data <= x"20";
when "01" & x"335" => data <= x"94";
when "01" & x"336" => data <= x"bd";
when "01" & x"337" => data <= x"a9";
when "01" & x"338" => data <= x"00";
when "01" & x"339" => data <= x"20";
when "01" & x"33a" => data <= x"d8";
when "01" & x"33b" => data <= x"ae";
when "01" & x"33c" => data <= x"85";
when "01" & x"33d" => data <= x"27";
when "01" & x"33e" => data <= x"20";
when "01" & x"33f" => data <= x"b4";
when "01" & x"340" => data <= x"b4";
when "01" & x"341" => data <= x"ba";
when "01" & x"342" => data <= x"fe";
when "01" & x"343" => data <= x"06";
when "01" & x"344" => data <= x"01";
when "01" & x"345" => data <= x"a4";
when "01" & x"346" => data <= x"1b";
when "01" & x"347" => data <= x"84";
when "01" & x"348" => data <= x"0a";
when "01" & x"349" => data <= x"20";
when "01" & x"34a" => data <= x"97";
when "01" & x"34b" => data <= x"8a";
when "01" & x"34c" => data <= x"c9";
when "01" & x"34d" => data <= x"2c";
when "01" & x"34e" => data <= x"f0";
when "01" & x"34f" => data <= x"d3";
when "01" & x"350" => data <= x"4c";
when "01" & x"351" => data <= x"96";
when "01" & x"352" => data <= x"8b";
when "01" & x"353" => data <= x"4c";
when "01" & x"354" => data <= x"98";
when "01" & x"355" => data <= x"8b";
when "01" & x"356" => data <= x"ba";
when "01" & x"357" => data <= x"e0";
when "01" & x"358" => data <= x"fc";
when "01" & x"359" => data <= x"b0";
when "01" & x"35a" => data <= x"0a";
when "01" & x"35b" => data <= x"ad";
when "01" & x"35c" => data <= x"ff";
when "01" & x"35d" => data <= x"01";
when "01" & x"35e" => data <= x"c9";
when "01" & x"35f" => data <= x"f2";
when "01" & x"360" => data <= x"d0";
when "01" & x"361" => data <= x"03";
when "01" & x"362" => data <= x"4c";
when "01" & x"363" => data <= x"57";
when "01" & x"364" => data <= x"98";
when "01" & x"365" => data <= x"00";
when "01" & x"366" => data <= x"0d";
when "01" & x"367" => data <= x"4e";
when "01" & x"368" => data <= x"6f";
when "01" & x"369" => data <= x"20";
when "01" & x"36a" => data <= x"f2";
when "01" & x"36b" => data <= x"00";
when "01" & x"36c" => data <= x"0c";
when "01" & x"36d" => data <= x"4e";
when "01" & x"36e" => data <= x"6f";
when "01" & x"36f" => data <= x"74";
when "01" & x"370" => data <= x"20";
when "01" & x"371" => data <= x"ea";
when "01" & x"372" => data <= x"00";
when "01" & x"373" => data <= x"19";
when "01" & x"374" => data <= x"42";
when "01" & x"375" => data <= x"61";
when "01" & x"376" => data <= x"64";
when "01" & x"377" => data <= x"20";
when "01" & x"378" => data <= x"eb";
when "01" & x"379" => data <= x"00";
when "01" & x"37a" => data <= x"20";
when "01" & x"37b" => data <= x"21";
when "01" & x"37c" => data <= x"88";
when "01" & x"37d" => data <= x"a5";
when "01" & x"37e" => data <= x"2a";
when "01" & x"37f" => data <= x"48";
when "01" & x"380" => data <= x"20";
when "01" & x"381" => data <= x"da";
when "01" & x"382" => data <= x"92";
when "01" & x"383" => data <= x"20";
when "01" & x"384" => data <= x"52";
when "01" & x"385" => data <= x"98";
when "01" & x"386" => data <= x"a9";
when "01" & x"387" => data <= x"12";
when "01" & x"388" => data <= x"20";
when "01" & x"389" => data <= x"ee";
when "01" & x"38a" => data <= x"ff";
when "01" & x"38b" => data <= x"4c";
when "01" & x"38c" => data <= x"da";
when "01" & x"38d" => data <= x"93";
when "01" & x"38e" => data <= x"a9";
when "01" & x"38f" => data <= x"11";
when "01" & x"390" => data <= x"48";
when "01" & x"391" => data <= x"20";
when "01" & x"392" => data <= x"21";
when "01" & x"393" => data <= x"88";
when "01" & x"394" => data <= x"20";
when "01" & x"395" => data <= x"57";
when "01" & x"396" => data <= x"98";
when "01" & x"397" => data <= x"4c";
when "01" & x"398" => data <= x"da";
when "01" & x"399" => data <= x"93";
when "01" & x"39a" => data <= x"a9";
when "01" & x"39b" => data <= x"16";
when "01" & x"39c" => data <= x"48";
when "01" & x"39d" => data <= x"20";
when "01" & x"39e" => data <= x"21";
when "01" & x"39f" => data <= x"88";
when "01" & x"3a0" => data <= x"20";
when "01" & x"3a1" => data <= x"57";
when "01" & x"3a2" => data <= x"98";
when "01" & x"3a3" => data <= x"20";
when "01" & x"3a4" => data <= x"e7";
when "01" & x"3a5" => data <= x"be";
when "01" & x"3a6" => data <= x"e0";
when "01" & x"3a7" => data <= x"ff";
when "01" & x"3a8" => data <= x"d0";
when "01" & x"3a9" => data <= x"2d";
when "01" & x"3aa" => data <= x"c0";
when "01" & x"3ab" => data <= x"ff";
when "01" & x"3ac" => data <= x"d0";
when "01" & x"3ad" => data <= x"29";
when "01" & x"3ae" => data <= x"a5";
when "01" & x"3af" => data <= x"04";
when "01" & x"3b0" => data <= x"c5";
when "01" & x"3b1" => data <= x"06";
when "01" & x"3b2" => data <= x"d0";
when "01" & x"3b3" => data <= x"be";
when "01" & x"3b4" => data <= x"a5";
when "01" & x"3b5" => data <= x"05";
when "01" & x"3b6" => data <= x"c5";
when "01" & x"3b7" => data <= x"07";
when "01" & x"3b8" => data <= x"d0";
when "01" & x"3b9" => data <= x"b8";
when "01" & x"3ba" => data <= x"a6";
when "01" & x"3bb" => data <= x"2a";
when "01" & x"3bc" => data <= x"a9";
when "01" & x"3bd" => data <= x"85";
when "01" & x"3be" => data <= x"20";
when "01" & x"3bf" => data <= x"f4";
when "01" & x"3c0" => data <= x"ff";
when "01" & x"3c1" => data <= x"e4";
when "01" & x"3c2" => data <= x"02";
when "01" & x"3c3" => data <= x"98";
when "01" & x"3c4" => data <= x"e5";
when "01" & x"3c5" => data <= x"03";
when "01" & x"3c6" => data <= x"90";
when "01" & x"3c7" => data <= x"aa";
when "01" & x"3c8" => data <= x"e4";
when "01" & x"3c9" => data <= x"12";
when "01" & x"3ca" => data <= x"98";
when "01" & x"3cb" => data <= x"e5";
when "01" & x"3cc" => data <= x"13";
when "01" & x"3cd" => data <= x"90";
when "01" & x"3ce" => data <= x"a3";
when "01" & x"3cf" => data <= x"86";
when "01" & x"3d0" => data <= x"06";
when "01" & x"3d1" => data <= x"86";
when "01" & x"3d2" => data <= x"04";
when "01" & x"3d3" => data <= x"84";
when "01" & x"3d4" => data <= x"07";
when "01" & x"3d5" => data <= x"84";
when "01" & x"3d6" => data <= x"05";
when "01" & x"3d7" => data <= x"20";
when "01" & x"3d8" => data <= x"28";
when "01" & x"3d9" => data <= x"bc";
when "01" & x"3da" => data <= x"68";
when "01" & x"3db" => data <= x"20";
when "01" & x"3dc" => data <= x"ee";
when "01" & x"3dd" => data <= x"ff";
when "01" & x"3de" => data <= x"20";
when "01" & x"3df" => data <= x"56";
when "01" & x"3e0" => data <= x"94";
when "01" & x"3e1" => data <= x"4c";
when "01" & x"3e2" => data <= x"9b";
when "01" & x"3e3" => data <= x"8b";
when "01" & x"3e4" => data <= x"a9";
when "01" & x"3e5" => data <= x"04";
when "01" & x"3e6" => data <= x"d0";
when "01" & x"3e7" => data <= x"02";
when "01" & x"3e8" => data <= x"a9";
when "01" & x"3e9" => data <= x"05";
when "01" & x"3ea" => data <= x"48";
when "01" & x"3eb" => data <= x"20";
when "01" & x"3ec" => data <= x"1d";
when "01" & x"3ed" => data <= x"9b";
when "01" & x"3ee" => data <= x"4c";
when "01" & x"3ef" => data <= x"fd";
when "01" & x"3f0" => data <= x"93";
when "01" & x"3f1" => data <= x"20";
when "01" & x"3f2" => data <= x"21";
when "01" & x"3f3" => data <= x"88";
when "01" & x"3f4" => data <= x"a5";
when "01" & x"3f5" => data <= x"2a";
when "01" & x"3f6" => data <= x"48";
when "01" & x"3f7" => data <= x"20";
when "01" & x"3f8" => data <= x"ae";
when "01" & x"3f9" => data <= x"8a";
when "01" & x"3fa" => data <= x"20";
when "01" & x"3fb" => data <= x"29";
when "01" & x"3fc" => data <= x"9b";
when "01" & x"3fd" => data <= x"20";
when "01" & x"3fe" => data <= x"ee";
when "01" & x"3ff" => data <= x"92";
when "01" & x"400" => data <= x"20";
when "01" & x"401" => data <= x"94";
when "01" & x"402" => data <= x"bd";
when "01" & x"403" => data <= x"20";
when "01" & x"404" => data <= x"da";
when "01" & x"405" => data <= x"92";
when "01" & x"406" => data <= x"20";
when "01" & x"407" => data <= x"52";
when "01" & x"408" => data <= x"98";
when "01" & x"409" => data <= x"a9";
when "01" & x"40a" => data <= x"19";
when "01" & x"40b" => data <= x"20";
when "01" & x"40c" => data <= x"ee";
when "01" & x"40d" => data <= x"ff";
when "01" & x"40e" => data <= x"68";
when "01" & x"40f" => data <= x"20";
when "01" & x"410" => data <= x"ee";
when "01" & x"411" => data <= x"ff";
when "01" & x"412" => data <= x"20";
when "01" & x"413" => data <= x"0b";
when "01" & x"414" => data <= x"be";
when "01" & x"415" => data <= x"a5";
when "01" & x"416" => data <= x"37";
when "01" & x"417" => data <= x"20";
when "01" & x"418" => data <= x"ee";
when "01" & x"419" => data <= x"ff";
when "01" & x"41a" => data <= x"a5";
when "01" & x"41b" => data <= x"38";
when "01" & x"41c" => data <= x"20";
when "01" & x"41d" => data <= x"ee";
when "01" & x"41e" => data <= x"ff";
when "01" & x"41f" => data <= x"20";
when "01" & x"420" => data <= x"56";
when "01" & x"421" => data <= x"94";
when "01" & x"422" => data <= x"a5";
when "01" & x"423" => data <= x"2b";
when "01" & x"424" => data <= x"20";
when "01" & x"425" => data <= x"ee";
when "01" & x"426" => data <= x"ff";
when "01" & x"427" => data <= x"4c";
when "01" & x"428" => data <= x"9b";
when "01" & x"429" => data <= x"8b";
when "01" & x"42a" => data <= x"a5";
when "01" & x"42b" => data <= x"2b";
when "01" & x"42c" => data <= x"20";
when "01" & x"42d" => data <= x"ee";
when "01" & x"42e" => data <= x"ff";
when "01" & x"42f" => data <= x"20";
when "01" & x"430" => data <= x"97";
when "01" & x"431" => data <= x"8a";
when "01" & x"432" => data <= x"c9";
when "01" & x"433" => data <= x"3a";
when "01" & x"434" => data <= x"f0";
when "01" & x"435" => data <= x"1d";
when "01" & x"436" => data <= x"c9";
when "01" & x"437" => data <= x"0d";
when "01" & x"438" => data <= x"f0";
when "01" & x"439" => data <= x"19";
when "01" & x"43a" => data <= x"c9";
when "01" & x"43b" => data <= x"8b";
when "01" & x"43c" => data <= x"f0";
when "01" & x"43d" => data <= x"15";
when "01" & x"43e" => data <= x"c6";
when "01" & x"43f" => data <= x"0a";
when "01" & x"440" => data <= x"20";
when "01" & x"441" => data <= x"21";
when "01" & x"442" => data <= x"88";
when "01" & x"443" => data <= x"20";
when "01" & x"444" => data <= x"56";
when "01" & x"445" => data <= x"94";
when "01" & x"446" => data <= x"20";
when "01" & x"447" => data <= x"97";
when "01" & x"448" => data <= x"8a";
when "01" & x"449" => data <= x"c9";
when "01" & x"44a" => data <= x"2c";
when "01" & x"44b" => data <= x"f0";
when "01" & x"44c" => data <= x"e2";
when "01" & x"44d" => data <= x"c9";
when "01" & x"44e" => data <= x"3b";
when "01" & x"44f" => data <= x"d0";
when "01" & x"450" => data <= x"e1";
when "01" & x"451" => data <= x"f0";
when "01" & x"452" => data <= x"d7";
when "01" & x"453" => data <= x"4c";
when "01" & x"454" => data <= x"96";
when "01" & x"455" => data <= x"8b";
when "01" & x"456" => data <= x"a5";
when "01" & x"457" => data <= x"2a";
when "01" & x"458" => data <= x"6c";
when "01" & x"459" => data <= x"0e";
when "01" & x"45a" => data <= x"02";
when "01" & x"45b" => data <= x"a0";
when "01" & x"45c" => data <= x"01";
when "01" & x"45d" => data <= x"b1";
when "01" & x"45e" => data <= x"37";
when "01" & x"45f" => data <= x"a0";
when "01" & x"460" => data <= x"f6";
when "01" & x"461" => data <= x"c9";
when "01" & x"462" => data <= x"f2";
when "01" & x"463" => data <= x"f0";
when "01" & x"464" => data <= x"0a";
when "01" & x"465" => data <= x"a0";
when "01" & x"466" => data <= x"f8";
when "01" & x"467" => data <= x"d0";
when "01" & x"468" => data <= x"06";
when "01" & x"469" => data <= x"a0";
when "01" & x"46a" => data <= x"01";
when "01" & x"46b" => data <= x"b1";
when "01" & x"46c" => data <= x"37";
when "01" & x"46d" => data <= x"0a";
when "01" & x"46e" => data <= x"a8";
when "01" & x"46f" => data <= x"b9";
when "01" & x"470" => data <= x"00";
when "01" & x"471" => data <= x"04";
when "01" & x"472" => data <= x"85";
when "01" & x"473" => data <= x"3a";
when "01" & x"474" => data <= x"b9";
when "01" & x"475" => data <= x"01";
when "01" & x"476" => data <= x"04";
when "01" & x"477" => data <= x"85";
when "01" & x"478" => data <= x"3b";
when "01" & x"479" => data <= x"a5";
when "01" & x"47a" => data <= x"3b";
when "01" & x"47b" => data <= x"f0";
when "01" & x"47c" => data <= x"35";
when "01" & x"47d" => data <= x"a0";
when "01" & x"47e" => data <= x"00";
when "01" & x"47f" => data <= x"b1";
when "01" & x"480" => data <= x"3a";
when "01" & x"481" => data <= x"85";
when "01" & x"482" => data <= x"3c";
when "01" & x"483" => data <= x"c8";
when "01" & x"484" => data <= x"b1";
when "01" & x"485" => data <= x"3a";
when "01" & x"486" => data <= x"85";
when "01" & x"487" => data <= x"3d";
when "01" & x"488" => data <= x"c8";
when "01" & x"489" => data <= x"b1";
when "01" & x"48a" => data <= x"3a";
when "01" & x"48b" => data <= x"d0";
when "01" & x"48c" => data <= x"0d";
when "01" & x"48d" => data <= x"88";
when "01" & x"48e" => data <= x"c4";
when "01" & x"48f" => data <= x"39";
when "01" & x"490" => data <= x"d0";
when "01" & x"491" => data <= x"21";
when "01" & x"492" => data <= x"c8";
when "01" & x"493" => data <= x"b0";
when "01" & x"494" => data <= x"12";
when "01" & x"495" => data <= x"c8";
when "01" & x"496" => data <= x"b1";
when "01" & x"497" => data <= x"3a";
when "01" & x"498" => data <= x"f0";
when "01" & x"499" => data <= x"19";
when "01" & x"49a" => data <= x"d1";
when "01" & x"49b" => data <= x"37";
when "01" & x"49c" => data <= x"d0";
when "01" & x"49d" => data <= x"15";
when "01" & x"49e" => data <= x"c4";
when "01" & x"49f" => data <= x"39";
when "01" & x"4a0" => data <= x"d0";
when "01" & x"4a1" => data <= x"f3";
when "01" & x"4a2" => data <= x"c8";
when "01" & x"4a3" => data <= x"b1";
when "01" & x"4a4" => data <= x"3a";
when "01" & x"4a5" => data <= x"d0";
when "01" & x"4a6" => data <= x"0c";
when "01" & x"4a7" => data <= x"98";
when "01" & x"4a8" => data <= x"65";
when "01" & x"4a9" => data <= x"3a";
when "01" & x"4aa" => data <= x"85";
when "01" & x"4ab" => data <= x"2a";
when "01" & x"4ac" => data <= x"a5";
when "01" & x"4ad" => data <= x"3b";
when "01" & x"4ae" => data <= x"69";
when "01" & x"4af" => data <= x"00";
when "01" & x"4b0" => data <= x"85";
when "01" & x"4b1" => data <= x"2b";
when "01" & x"4b2" => data <= x"60";
when "01" & x"4b3" => data <= x"a5";
when "01" & x"4b4" => data <= x"3d";
when "01" & x"4b5" => data <= x"f0";
when "01" & x"4b6" => data <= x"fb";
when "01" & x"4b7" => data <= x"a0";
when "01" & x"4b8" => data <= x"00";
when "01" & x"4b9" => data <= x"b1";
when "01" & x"4ba" => data <= x"3c";
when "01" & x"4bb" => data <= x"85";
when "01" & x"4bc" => data <= x"3a";
when "01" & x"4bd" => data <= x"c8";
when "01" & x"4be" => data <= x"b1";
when "01" & x"4bf" => data <= x"3c";
when "01" & x"4c0" => data <= x"85";
when "01" & x"4c1" => data <= x"3b";
when "01" & x"4c2" => data <= x"c8";
when "01" & x"4c3" => data <= x"b1";
when "01" & x"4c4" => data <= x"3c";
when "01" & x"4c5" => data <= x"d0";
when "01" & x"4c6" => data <= x"0d";
when "01" & x"4c7" => data <= x"88";
when "01" & x"4c8" => data <= x"c4";
when "01" & x"4c9" => data <= x"39";
when "01" & x"4ca" => data <= x"d0";
when "01" & x"4cb" => data <= x"ad";
when "01" & x"4cc" => data <= x"c8";
when "01" & x"4cd" => data <= x"b0";
when "01" & x"4ce" => data <= x"12";
when "01" & x"4cf" => data <= x"c8";
when "01" & x"4d0" => data <= x"b1";
when "01" & x"4d1" => data <= x"3c";
when "01" & x"4d2" => data <= x"f0";
when "01" & x"4d3" => data <= x"a5";
when "01" & x"4d4" => data <= x"d1";
when "01" & x"4d5" => data <= x"37";
when "01" & x"4d6" => data <= x"d0";
when "01" & x"4d7" => data <= x"a1";
when "01" & x"4d8" => data <= x"c4";
when "01" & x"4d9" => data <= x"39";
when "01" & x"4da" => data <= x"d0";
when "01" & x"4db" => data <= x"f3";
when "01" & x"4dc" => data <= x"c8";
when "01" & x"4dd" => data <= x"b1";
when "01" & x"4de" => data <= x"3c";
when "01" & x"4df" => data <= x"d0";
when "01" & x"4e0" => data <= x"98";
when "01" & x"4e1" => data <= x"98";
when "01" & x"4e2" => data <= x"65";
when "01" & x"4e3" => data <= x"3c";
when "01" & x"4e4" => data <= x"85";
when "01" & x"4e5" => data <= x"2a";
when "01" & x"4e6" => data <= x"a5";
when "01" & x"4e7" => data <= x"3d";
when "01" & x"4e8" => data <= x"69";
when "01" & x"4e9" => data <= x"00";
when "01" & x"4ea" => data <= x"85";
when "01" & x"4eb" => data <= x"2b";
when "01" & x"4ec" => data <= x"60";
when "01" & x"4ed" => data <= x"a0";
when "01" & x"4ee" => data <= x"01";
when "01" & x"4ef" => data <= x"b1";
when "01" & x"4f0" => data <= x"37";
when "01" & x"4f1" => data <= x"aa";
when "01" & x"4f2" => data <= x"a9";
when "01" & x"4f3" => data <= x"f6";
when "01" & x"4f4" => data <= x"e0";
when "01" & x"4f5" => data <= x"f2";
when "01" & x"4f6" => data <= x"f0";
when "01" & x"4f7" => data <= x"09";
when "01" & x"4f8" => data <= x"a9";
when "01" & x"4f9" => data <= x"f8";
when "01" & x"4fa" => data <= x"d0";
when "01" & x"4fb" => data <= x"05";
when "01" & x"4fc" => data <= x"a0";
when "01" & x"4fd" => data <= x"01";
when "01" & x"4fe" => data <= x"b1";
when "01" & x"4ff" => data <= x"37";
when "01" & x"500" => data <= x"0a";
when "01" & x"501" => data <= x"85";
when "01" & x"502" => data <= x"3a";
when "01" & x"503" => data <= x"a9";
when "01" & x"504" => data <= x"04";
when "01" & x"505" => data <= x"85";
when "01" & x"506" => data <= x"3b";
when "01" & x"507" => data <= x"b1";
when "01" & x"508" => data <= x"3a";
when "01" & x"509" => data <= x"f0";
when "01" & x"50a" => data <= x"0b";
when "01" & x"50b" => data <= x"aa";
when "01" & x"50c" => data <= x"88";
when "01" & x"50d" => data <= x"b1";
when "01" & x"50e" => data <= x"3a";
when "01" & x"50f" => data <= x"85";
when "01" & x"510" => data <= x"3a";
when "01" & x"511" => data <= x"86";
when "01" & x"512" => data <= x"3b";
when "01" & x"513" => data <= x"c8";
when "01" & x"514" => data <= x"10";
when "01" & x"515" => data <= x"f1";
when "01" & x"516" => data <= x"a5";
when "01" & x"517" => data <= x"03";
when "01" & x"518" => data <= x"91";
when "01" & x"519" => data <= x"3a";
when "01" & x"51a" => data <= x"a5";
when "01" & x"51b" => data <= x"02";
when "01" & x"51c" => data <= x"88";
when "01" & x"51d" => data <= x"91";
when "01" & x"51e" => data <= x"3a";
when "01" & x"51f" => data <= x"98";
when "01" & x"520" => data <= x"c8";
when "01" & x"521" => data <= x"91";
when "01" & x"522" => data <= x"02";
when "01" & x"523" => data <= x"c4";
when "01" & x"524" => data <= x"39";
when "01" & x"525" => data <= x"f0";
when "01" & x"526" => data <= x"31";
when "01" & x"527" => data <= x"c8";
when "01" & x"528" => data <= x"b1";
when "01" & x"529" => data <= x"37";
when "01" & x"52a" => data <= x"91";
when "01" & x"52b" => data <= x"02";
when "01" & x"52c" => data <= x"c4";
when "01" & x"52d" => data <= x"39";
when "01" & x"52e" => data <= x"d0";
when "01" & x"52f" => data <= x"f7";
when "01" & x"530" => data <= x"60";
when "01" & x"531" => data <= x"a9";
when "01" & x"532" => data <= x"00";
when "01" & x"533" => data <= x"c8";
when "01" & x"534" => data <= x"91";
when "01" & x"535" => data <= x"02";
when "01" & x"536" => data <= x"ca";
when "01" & x"537" => data <= x"d0";
when "01" & x"538" => data <= x"fa";
when "01" & x"539" => data <= x"38";
when "01" & x"53a" => data <= x"98";
when "01" & x"53b" => data <= x"65";
when "01" & x"53c" => data <= x"02";
when "01" & x"53d" => data <= x"90";
when "01" & x"53e" => data <= x"02";
when "01" & x"53f" => data <= x"e6";
when "01" & x"540" => data <= x"03";
when "01" & x"541" => data <= x"a4";
when "01" & x"542" => data <= x"03";
when "01" & x"543" => data <= x"c4";
when "01" & x"544" => data <= x"05";
when "01" & x"545" => data <= x"90";
when "01" & x"546" => data <= x"0f";
when "01" & x"547" => data <= x"d0";
when "01" & x"548" => data <= x"04";
when "01" & x"549" => data <= x"c5";
when "01" & x"54a" => data <= x"04";
when "01" & x"54b" => data <= x"90";
when "01" & x"54c" => data <= x"09";
when "01" & x"54d" => data <= x"a9";
when "01" & x"54e" => data <= x"00";
when "01" & x"54f" => data <= x"a0";
when "01" & x"550" => data <= x"01";
when "01" & x"551" => data <= x"91";
when "01" & x"552" => data <= x"3a";
when "01" & x"553" => data <= x"4c";
when "01" & x"554" => data <= x"b7";
when "01" & x"555" => data <= x"8c";
when "01" & x"556" => data <= x"85";
when "01" & x"557" => data <= x"02";
when "01" & x"558" => data <= x"60";
when "01" & x"559" => data <= x"a0";
when "01" & x"55a" => data <= x"01";
when "01" & x"55b" => data <= x"b1";
when "01" & x"55c" => data <= x"37";
when "01" & x"55d" => data <= x"c9";
when "01" & x"55e" => data <= x"30";
when "01" & x"55f" => data <= x"90";
when "01" & x"560" => data <= x"18";
when "01" & x"561" => data <= x"c9";
when "01" & x"562" => data <= x"40";
when "01" & x"563" => data <= x"b0";
when "01" & x"564" => data <= x"0c";
when "01" & x"565" => data <= x"c9";
when "01" & x"566" => data <= x"3a";
when "01" & x"567" => data <= x"b0";
when "01" & x"568" => data <= x"10";
when "01" & x"569" => data <= x"c0";
when "01" & x"56a" => data <= x"01";
when "01" & x"56b" => data <= x"f0";
when "01" & x"56c" => data <= x"0c";
when "01" & x"56d" => data <= x"e8";
when "01" & x"56e" => data <= x"c8";
when "01" & x"56f" => data <= x"d0";
when "01" & x"570" => data <= x"ea";
when "01" & x"571" => data <= x"c9";
when "01" & x"572" => data <= x"5f";
when "01" & x"573" => data <= x"b0";
when "01" & x"574" => data <= x"05";
when "01" & x"575" => data <= x"c9";
when "01" & x"576" => data <= x"5b";
when "01" & x"577" => data <= x"90";
when "01" & x"578" => data <= x"f4";
when "01" & x"579" => data <= x"60";
when "01" & x"57a" => data <= x"c9";
when "01" & x"57b" => data <= x"7b";
when "01" & x"57c" => data <= x"90";
when "01" & x"57d" => data <= x"ef";
when "01" & x"57e" => data <= x"60";
when "01" & x"57f" => data <= x"20";
when "01" & x"580" => data <= x"31";
when "01" & x"581" => data <= x"95";
when "01" & x"582" => data <= x"20";
when "01" & x"583" => data <= x"c9";
when "01" & x"584" => data <= x"95";
when "01" & x"585" => data <= x"d0";
when "01" & x"586" => data <= x"1d";
when "01" & x"587" => data <= x"b0";
when "01" & x"588" => data <= x"1b";
when "01" & x"589" => data <= x"20";
when "01" & x"58a" => data <= x"fc";
when "01" & x"58b" => data <= x"94";
when "01" & x"58c" => data <= x"a2";
when "01" & x"58d" => data <= x"05";
when "01" & x"58e" => data <= x"e4";
when "01" & x"58f" => data <= x"2c";
when "01" & x"590" => data <= x"d0";
when "01" & x"591" => data <= x"ed";
when "01" & x"592" => data <= x"e8";
when "01" & x"593" => data <= x"d0";
when "01" & x"594" => data <= x"ea";
when "01" & x"595" => data <= x"c9";
when "01" & x"596" => data <= x"21";
when "01" & x"597" => data <= x"f0";
when "01" & x"598" => data <= x"0c";
when "01" & x"599" => data <= x"c9";
when "01" & x"59a" => data <= x"24";
when "01" & x"59b" => data <= x"f0";
when "01" & x"59c" => data <= x"13";
when "01" & x"59d" => data <= x"49";
when "01" & x"59e" => data <= x"3f";
when "01" & x"59f" => data <= x"f0";
when "01" & x"5a0" => data <= x"06";
when "01" & x"5a1" => data <= x"a9";
when "01" & x"5a2" => data <= x"00";
when "01" & x"5a3" => data <= x"38";
when "01" & x"5a4" => data <= x"60";
when "01" & x"5a5" => data <= x"a9";
when "01" & x"5a6" => data <= x"04";
when "01" & x"5a7" => data <= x"48";
when "01" & x"5a8" => data <= x"e6";
when "01" & x"5a9" => data <= x"1b";
when "01" & x"5aa" => data <= x"20";
when "01" & x"5ab" => data <= x"e3";
when "01" & x"5ac" => data <= x"92";
when "01" & x"5ad" => data <= x"4c";
when "01" & x"5ae" => data <= x"9f";
when "01" & x"5af" => data <= x"96";
when "01" & x"5b0" => data <= x"e6";
when "01" & x"5b1" => data <= x"1b";
when "01" & x"5b2" => data <= x"20";
when "01" & x"5b3" => data <= x"e3";
when "01" & x"5b4" => data <= x"92";
when "01" & x"5b5" => data <= x"a5";
when "01" & x"5b6" => data <= x"2b";
when "01" & x"5b7" => data <= x"f0";
when "01" & x"5b8" => data <= x"06";
when "01" & x"5b9" => data <= x"a9";
when "01" & x"5ba" => data <= x"80";
when "01" & x"5bb" => data <= x"85";
when "01" & x"5bc" => data <= x"2c";
when "01" & x"5bd" => data <= x"38";
when "01" & x"5be" => data <= x"60";
when "01" & x"5bf" => data <= x"00";
when "01" & x"5c0" => data <= x"08";
when "01" & x"5c1" => data <= x"24";
when "01" & x"5c2" => data <= x"20";
when "01" & x"5c3" => data <= x"72";
when "01" & x"5c4" => data <= x"61";
when "01" & x"5c5" => data <= x"6e";
when "01" & x"5c6" => data <= x"67";
when "01" & x"5c7" => data <= x"65";
when "01" & x"5c8" => data <= x"00";
when "01" & x"5c9" => data <= x"a5";
when "01" & x"5ca" => data <= x"0b";
when "01" & x"5cb" => data <= x"85";
when "01" & x"5cc" => data <= x"19";
when "01" & x"5cd" => data <= x"a5";
when "01" & x"5ce" => data <= x"0c";
when "01" & x"5cf" => data <= x"85";
when "01" & x"5d0" => data <= x"1a";
when "01" & x"5d1" => data <= x"a4";
when "01" & x"5d2" => data <= x"0a";
when "01" & x"5d3" => data <= x"88";
when "01" & x"5d4" => data <= x"c8";
when "01" & x"5d5" => data <= x"84";
when "01" & x"5d6" => data <= x"1b";
when "01" & x"5d7" => data <= x"b1";
when "01" & x"5d8" => data <= x"19";
when "01" & x"5d9" => data <= x"c9";
when "01" & x"5da" => data <= x"20";
when "01" & x"5db" => data <= x"f0";
when "01" & x"5dc" => data <= x"f7";
when "01" & x"5dd" => data <= x"c9";
when "01" & x"5de" => data <= x"40";
when "01" & x"5df" => data <= x"90";
when "01" & x"5e0" => data <= x"b4";
when "01" & x"5e1" => data <= x"c9";
when "01" & x"5e2" => data <= x"5b";
when "01" & x"5e3" => data <= x"b0";
when "01" & x"5e4" => data <= x"1a";
when "01" & x"5e5" => data <= x"0a";
when "01" & x"5e6" => data <= x"0a";
when "01" & x"5e7" => data <= x"85";
when "01" & x"5e8" => data <= x"2a";
when "01" & x"5e9" => data <= x"a9";
when "01" & x"5ea" => data <= x"04";
when "01" & x"5eb" => data <= x"85";
when "01" & x"5ec" => data <= x"2b";
when "01" & x"5ed" => data <= x"c8";
when "01" & x"5ee" => data <= x"b1";
when "01" & x"5ef" => data <= x"19";
when "01" & x"5f0" => data <= x"c8";
when "01" & x"5f1" => data <= x"c9";
when "01" & x"5f2" => data <= x"25";
when "01" & x"5f3" => data <= x"d0";
when "01" & x"5f4" => data <= x"0a";
when "01" & x"5f5" => data <= x"a2";
when "01" & x"5f6" => data <= x"04";
when "01" & x"5f7" => data <= x"86";
when "01" & x"5f8" => data <= x"2c";
when "01" & x"5f9" => data <= x"b1";
when "01" & x"5fa" => data <= x"19";
when "01" & x"5fb" => data <= x"c9";
when "01" & x"5fc" => data <= x"28";
when "01" & x"5fd" => data <= x"d0";
when "01" & x"5fe" => data <= x"66";
when "01" & x"5ff" => data <= x"a2";
when "01" & x"600" => data <= x"05";
when "01" & x"601" => data <= x"86";
when "01" & x"602" => data <= x"2c";
when "01" & x"603" => data <= x"a5";
when "01" & x"604" => data <= x"1b";
when "01" & x"605" => data <= x"18";
when "01" & x"606" => data <= x"65";
when "01" & x"607" => data <= x"19";
when "01" & x"608" => data <= x"a6";
when "01" & x"609" => data <= x"1a";
when "01" & x"60a" => data <= x"90";
when "01" & x"60b" => data <= x"02";
when "01" & x"60c" => data <= x"e8";
when "01" & x"60d" => data <= x"18";
when "01" & x"60e" => data <= x"e9";
when "01" & x"60f" => data <= x"00";
when "01" & x"610" => data <= x"85";
when "01" & x"611" => data <= x"37";
when "01" & x"612" => data <= x"b0";
when "01" & x"613" => data <= x"01";
when "01" & x"614" => data <= x"ca";
when "01" & x"615" => data <= x"86";
when "01" & x"616" => data <= x"38";
when "01" & x"617" => data <= x"a6";
when "01" & x"618" => data <= x"1b";
when "01" & x"619" => data <= x"a0";
when "01" & x"61a" => data <= x"01";
when "01" & x"61b" => data <= x"b1";
when "01" & x"61c" => data <= x"37";
when "01" & x"61d" => data <= x"c9";
when "01" & x"61e" => data <= x"41";
when "01" & x"61f" => data <= x"b0";
when "01" & x"620" => data <= x"0c";
when "01" & x"621" => data <= x"c9";
when "01" & x"622" => data <= x"30";
when "01" & x"623" => data <= x"90";
when "01" & x"624" => data <= x"1c";
when "01" & x"625" => data <= x"c9";
when "01" & x"626" => data <= x"3a";
when "01" & x"627" => data <= x"b0";
when "01" & x"628" => data <= x"18";
when "01" & x"629" => data <= x"e8";
when "01" & x"62a" => data <= x"c8";
when "01" & x"62b" => data <= x"d0";
when "01" & x"62c" => data <= x"ee";
when "01" & x"62d" => data <= x"c9";
when "01" & x"62e" => data <= x"5b";
when "01" & x"62f" => data <= x"b0";
when "01" & x"630" => data <= x"04";
when "01" & x"631" => data <= x"e8";
when "01" & x"632" => data <= x"c8";
when "01" & x"633" => data <= x"d0";
when "01" & x"634" => data <= x"e6";
when "01" & x"635" => data <= x"c9";
when "01" & x"636" => data <= x"5f";
when "01" & x"637" => data <= x"90";
when "01" & x"638" => data <= x"08";
when "01" & x"639" => data <= x"c9";
when "01" & x"63a" => data <= x"7b";
when "01" & x"63b" => data <= x"b0";
when "01" & x"63c" => data <= x"04";
when "01" & x"63d" => data <= x"e8";
when "01" & x"63e" => data <= x"c8";
when "01" & x"63f" => data <= x"d0";
when "01" & x"640" => data <= x"da";
when "01" & x"641" => data <= x"88";
when "01" & x"642" => data <= x"f0";
when "01" & x"643" => data <= x"2f";
when "01" & x"644" => data <= x"c9";
when "01" & x"645" => data <= x"24";
when "01" & x"646" => data <= x"f0";
when "01" & x"647" => data <= x"67";
when "01" & x"648" => data <= x"c9";
when "01" & x"649" => data <= x"25";
when "01" & x"64a" => data <= x"d0";
when "01" & x"64b" => data <= x"08";
when "01" & x"64c" => data <= x"c6";
when "01" & x"64d" => data <= x"2c";
when "01" & x"64e" => data <= x"c8";
when "01" & x"64f" => data <= x"e8";
when "01" & x"650" => data <= x"c8";
when "01" & x"651" => data <= x"b1";
when "01" & x"652" => data <= x"37";
when "01" & x"653" => data <= x"88";
when "01" & x"654" => data <= x"84";
when "01" & x"655" => data <= x"39";
when "01" & x"656" => data <= x"c9";
when "01" & x"657" => data <= x"28";
when "01" & x"658" => data <= x"f0";
when "01" & x"659" => data <= x"4c";
when "01" & x"65a" => data <= x"20";
when "01" & x"65b" => data <= x"69";
when "01" & x"65c" => data <= x"94";
when "01" & x"65d" => data <= x"f0";
when "01" & x"65e" => data <= x"18";
when "01" & x"65f" => data <= x"86";
when "01" & x"660" => data <= x"1b";
when "01" & x"661" => data <= x"a4";
when "01" & x"662" => data <= x"1b";
when "01" & x"663" => data <= x"b1";
when "01" & x"664" => data <= x"19";
when "01" & x"665" => data <= x"c9";
when "01" & x"666" => data <= x"21";
when "01" & x"667" => data <= x"f0";
when "01" & x"668" => data <= x"16";
when "01" & x"669" => data <= x"c9";
when "01" & x"66a" => data <= x"3f";
when "01" & x"66b" => data <= x"f0";
when "01" & x"66c" => data <= x"0e";
when "01" & x"66d" => data <= x"18";
when "01" & x"66e" => data <= x"84";
when "01" & x"66f" => data <= x"1b";
when "01" & x"670" => data <= x"a9";
when "01" & x"671" => data <= x"ff";
when "01" & x"672" => data <= x"60";
when "01" & x"673" => data <= x"a9";
when "01" & x"674" => data <= x"00";
when "01" & x"675" => data <= x"38";
when "01" & x"676" => data <= x"60";
when "01" & x"677" => data <= x"a9";
when "01" & x"678" => data <= x"00";
when "01" & x"679" => data <= x"18";
when "01" & x"67a" => data <= x"60";
when "01" & x"67b" => data <= x"a9";
when "01" & x"67c" => data <= x"00";
when "01" & x"67d" => data <= x"f0";
when "01" & x"67e" => data <= x"02";
when "01" & x"67f" => data <= x"a9";
when "01" & x"680" => data <= x"04";
when "01" & x"681" => data <= x"48";
when "01" & x"682" => data <= x"c8";
when "01" & x"683" => data <= x"84";
when "01" & x"684" => data <= x"1b";
when "01" & x"685" => data <= x"20";
when "01" & x"686" => data <= x"2c";
when "01" & x"687" => data <= x"b3";
when "01" & x"688" => data <= x"20";
when "01" & x"689" => data <= x"f0";
when "01" & x"68a" => data <= x"92";
when "01" & x"68b" => data <= x"a5";
when "01" & x"68c" => data <= x"2b";
when "01" & x"68d" => data <= x"48";
when "01" & x"68e" => data <= x"a5";
when "01" & x"68f" => data <= x"2a";
when "01" & x"690" => data <= x"48";
when "01" & x"691" => data <= x"20";
when "01" & x"692" => data <= x"e3";
when "01" & x"693" => data <= x"92";
when "01" & x"694" => data <= x"18";
when "01" & x"695" => data <= x"68";
when "01" & x"696" => data <= x"65";
when "01" & x"697" => data <= x"2a";
when "01" & x"698" => data <= x"85";
when "01" & x"699" => data <= x"2a";
when "01" & x"69a" => data <= x"68";
when "01" & x"69b" => data <= x"65";
when "01" & x"69c" => data <= x"2b";
when "01" & x"69d" => data <= x"85";
when "01" & x"69e" => data <= x"2b";
when "01" & x"69f" => data <= x"68";
when "01" & x"6a0" => data <= x"85";
when "01" & x"6a1" => data <= x"2c";
when "01" & x"6a2" => data <= x"18";
when "01" & x"6a3" => data <= x"a9";
when "01" & x"6a4" => data <= x"ff";
when "01" & x"6a5" => data <= x"60";
when "01" & x"6a6" => data <= x"e8";
when "01" & x"6a7" => data <= x"e6";
when "01" & x"6a8" => data <= x"39";
when "01" & x"6a9" => data <= x"20";
when "01" & x"6aa" => data <= x"df";
when "01" & x"6ab" => data <= x"96";
when "01" & x"6ac" => data <= x"4c";
when "01" & x"6ad" => data <= x"61";
when "01" & x"6ae" => data <= x"96";
when "01" & x"6af" => data <= x"e8";
when "01" & x"6b0" => data <= x"c8";
when "01" & x"6b1" => data <= x"84";
when "01" & x"6b2" => data <= x"39";
when "01" & x"6b3" => data <= x"c8";
when "01" & x"6b4" => data <= x"c6";
when "01" & x"6b5" => data <= x"2c";
when "01" & x"6b6" => data <= x"b1";
when "01" & x"6b7" => data <= x"37";
when "01" & x"6b8" => data <= x"c9";
when "01" & x"6b9" => data <= x"28";
when "01" & x"6ba" => data <= x"f0";
when "01" & x"6bb" => data <= x"0d";
when "01" & x"6bc" => data <= x"20";
when "01" & x"6bd" => data <= x"69";
when "01" & x"6be" => data <= x"94";
when "01" & x"6bf" => data <= x"f0";
when "01" & x"6c0" => data <= x"b6";
when "01" & x"6c1" => data <= x"86";
when "01" & x"6c2" => data <= x"1b";
when "01" & x"6c3" => data <= x"a9";
when "01" & x"6c4" => data <= x"81";
when "01" & x"6c5" => data <= x"85";
when "01" & x"6c6" => data <= x"2c";
when "01" & x"6c7" => data <= x"38";
when "01" & x"6c8" => data <= x"60";
when "01" & x"6c9" => data <= x"e8";
when "01" & x"6ca" => data <= x"84";
when "01" & x"6cb" => data <= x"39";
when "01" & x"6cc" => data <= x"c6";
when "01" & x"6cd" => data <= x"2c";
when "01" & x"6ce" => data <= x"20";
when "01" & x"6cf" => data <= x"df";
when "01" & x"6d0" => data <= x"96";
when "01" & x"6d1" => data <= x"a9";
when "01" & x"6d2" => data <= x"81";
when "01" & x"6d3" => data <= x"85";
when "01" & x"6d4" => data <= x"2c";
when "01" & x"6d5" => data <= x"38";
when "01" & x"6d6" => data <= x"60";
when "01" & x"6d7" => data <= x"00";
when "01" & x"6d8" => data <= x"0e";
when "01" & x"6d9" => data <= x"41";
when "01" & x"6da" => data <= x"72";
when "01" & x"6db" => data <= x"72";
when "01" & x"6dc" => data <= x"61";
when "01" & x"6dd" => data <= x"79";
when "01" & x"6de" => data <= x"00";
when "01" & x"6df" => data <= x"20";
when "01" & x"6e0" => data <= x"69";
when "01" & x"6e1" => data <= x"94";
when "01" & x"6e2" => data <= x"f0";
when "01" & x"6e3" => data <= x"f3";
when "01" & x"6e4" => data <= x"86";
when "01" & x"6e5" => data <= x"1b";
when "01" & x"6e6" => data <= x"a5";
when "01" & x"6e7" => data <= x"2c";
when "01" & x"6e8" => data <= x"48";
when "01" & x"6e9" => data <= x"a5";
when "01" & x"6ea" => data <= x"2a";
when "01" & x"6eb" => data <= x"48";
when "01" & x"6ec" => data <= x"a5";
when "01" & x"6ed" => data <= x"2b";
when "01" & x"6ee" => data <= x"48";
when "01" & x"6ef" => data <= x"a0";
when "01" & x"6f0" => data <= x"00";
when "01" & x"6f1" => data <= x"b1";
when "01" & x"6f2" => data <= x"2a";
when "01" & x"6f3" => data <= x"c9";
when "01" & x"6f4" => data <= x"04";
when "01" & x"6f5" => data <= x"90";
when "01" & x"6f6" => data <= x"75";
when "01" & x"6f7" => data <= x"98";
when "01" & x"6f8" => data <= x"20";
when "01" & x"6f9" => data <= x"d8";
when "01" & x"6fa" => data <= x"ae";
when "01" & x"6fb" => data <= x"a9";
when "01" & x"6fc" => data <= x"01";
when "01" & x"6fd" => data <= x"85";
when "01" & x"6fe" => data <= x"2d";
when "01" & x"6ff" => data <= x"20";
when "01" & x"700" => data <= x"94";
when "01" & x"701" => data <= x"bd";
when "01" & x"702" => data <= x"20";
when "01" & x"703" => data <= x"dd";
when "01" & x"704" => data <= x"92";
when "01" & x"705" => data <= x"e6";
when "01" & x"706" => data <= x"1b";
when "01" & x"707" => data <= x"e0";
when "01" & x"708" => data <= x"2c";
when "01" & x"709" => data <= x"d0";
when "01" & x"70a" => data <= x"cc";
when "01" & x"70b" => data <= x"a2";
when "01" & x"70c" => data <= x"39";
when "01" & x"70d" => data <= x"20";
when "01" & x"70e" => data <= x"0d";
when "01" & x"70f" => data <= x"be";
when "01" & x"710" => data <= x"a4";
when "01" & x"711" => data <= x"3c";
when "01" & x"712" => data <= x"68";
when "01" & x"713" => data <= x"85";
when "01" & x"714" => data <= x"38";
when "01" & x"715" => data <= x"68";
when "01" & x"716" => data <= x"85";
when "01" & x"717" => data <= x"37";
when "01" & x"718" => data <= x"48";
when "01" & x"719" => data <= x"a5";
when "01" & x"71a" => data <= x"38";
when "01" & x"71b" => data <= x"48";
when "01" & x"71c" => data <= x"20";
when "01" & x"71d" => data <= x"ba";
when "01" & x"71e" => data <= x"97";
when "01" & x"71f" => data <= x"84";
when "01" & x"720" => data <= x"2d";
when "01" & x"721" => data <= x"b1";
when "01" & x"722" => data <= x"37";
when "01" & x"723" => data <= x"85";
when "01" & x"724" => data <= x"3f";
when "01" & x"725" => data <= x"c8";
when "01" & x"726" => data <= x"b1";
when "01" & x"727" => data <= x"37";
when "01" & x"728" => data <= x"85";
when "01" & x"729" => data <= x"40";
when "01" & x"72a" => data <= x"a5";
when "01" & x"72b" => data <= x"2a";
when "01" & x"72c" => data <= x"65";
when "01" & x"72d" => data <= x"39";
when "01" & x"72e" => data <= x"85";
when "01" & x"72f" => data <= x"2a";
when "01" & x"730" => data <= x"a5";
when "01" & x"731" => data <= x"2b";
when "01" & x"732" => data <= x"65";
when "01" & x"733" => data <= x"3a";
when "01" & x"734" => data <= x"85";
when "01" & x"735" => data <= x"2b";
when "01" & x"736" => data <= x"20";
when "01" & x"737" => data <= x"36";
when "01" & x"738" => data <= x"92";
when "01" & x"739" => data <= x"a0";
when "01" & x"73a" => data <= x"00";
when "01" & x"73b" => data <= x"38";
when "01" & x"73c" => data <= x"b1";
when "01" & x"73d" => data <= x"37";
when "01" & x"73e" => data <= x"e5";
when "01" & x"73f" => data <= x"2d";
when "01" & x"740" => data <= x"c9";
when "01" & x"741" => data <= x"03";
when "01" & x"742" => data <= x"b0";
when "01" & x"743" => data <= x"bb";
when "01" & x"744" => data <= x"20";
when "01" & x"745" => data <= x"94";
when "01" & x"746" => data <= x"bd";
when "01" & x"747" => data <= x"20";
when "01" & x"748" => data <= x"56";
when "01" & x"749" => data <= x"ae";
when "01" & x"74a" => data <= x"20";
when "01" & x"74b" => data <= x"f0";
when "01" & x"74c" => data <= x"92";
when "01" & x"74d" => data <= x"68";
when "01" & x"74e" => data <= x"85";
when "01" & x"74f" => data <= x"38";
when "01" & x"750" => data <= x"68";
when "01" & x"751" => data <= x"85";
when "01" & x"752" => data <= x"37";
when "01" & x"753" => data <= x"a2";
when "01" & x"754" => data <= x"39";
when "01" & x"755" => data <= x"20";
when "01" & x"756" => data <= x"0d";
when "01" & x"757" => data <= x"be";
when "01" & x"758" => data <= x"a4";
when "01" & x"759" => data <= x"3c";
when "01" & x"75a" => data <= x"20";
when "01" & x"75b" => data <= x"ba";
when "01" & x"75c" => data <= x"97";
when "01" & x"75d" => data <= x"18";
when "01" & x"75e" => data <= x"a5";
when "01" & x"75f" => data <= x"39";
when "01" & x"760" => data <= x"65";
when "01" & x"761" => data <= x"2a";
when "01" & x"762" => data <= x"85";
when "01" & x"763" => data <= x"2a";
when "01" & x"764" => data <= x"a5";
when "01" & x"765" => data <= x"3a";
when "01" & x"766" => data <= x"65";
when "01" & x"767" => data <= x"2b";
when "01" & x"768" => data <= x"85";
when "01" & x"769" => data <= x"2b";
when "01" & x"76a" => data <= x"90";
when "01" & x"76b" => data <= x"11";
when "01" & x"76c" => data <= x"20";
when "01" & x"76d" => data <= x"56";
when "01" & x"76e" => data <= x"ae";
when "01" & x"76f" => data <= x"20";
when "01" & x"770" => data <= x"f0";
when "01" & x"771" => data <= x"92";
when "01" & x"772" => data <= x"68";
when "01" & x"773" => data <= x"85";
when "01" & x"774" => data <= x"38";
when "01" & x"775" => data <= x"68";
when "01" & x"776" => data <= x"85";
when "01" & x"777" => data <= x"37";
when "01" & x"778" => data <= x"a0";
when "01" & x"779" => data <= x"01";
when "01" & x"77a" => data <= x"20";
when "01" & x"77b" => data <= x"ba";
when "01" & x"77c" => data <= x"97";
when "01" & x"77d" => data <= x"68";
when "01" & x"77e" => data <= x"85";
when "01" & x"77f" => data <= x"2c";
when "01" & x"780" => data <= x"c9";
when "01" & x"781" => data <= x"05";
when "01" & x"782" => data <= x"d0";
when "01" & x"783" => data <= x"17";
when "01" & x"784" => data <= x"a6";
when "01" & x"785" => data <= x"2b";
when "01" & x"786" => data <= x"a5";
when "01" & x"787" => data <= x"2a";
when "01" & x"788" => data <= x"06";
when "01" & x"789" => data <= x"2a";
when "01" & x"78a" => data <= x"26";
when "01" & x"78b" => data <= x"2b";
when "01" & x"78c" => data <= x"06";
when "01" & x"78d" => data <= x"2a";
when "01" & x"78e" => data <= x"26";
when "01" & x"78f" => data <= x"2b";
when "01" & x"790" => data <= x"65";
when "01" & x"791" => data <= x"2a";
when "01" & x"792" => data <= x"85";
when "01" & x"793" => data <= x"2a";
when "01" & x"794" => data <= x"8a";
when "01" & x"795" => data <= x"65";
when "01" & x"796" => data <= x"2b";
when "01" & x"797" => data <= x"85";
when "01" & x"798" => data <= x"2b";
when "01" & x"799" => data <= x"90";
when "01" & x"79a" => data <= x"08";
when "01" & x"79b" => data <= x"06";
when "01" & x"79c" => data <= x"2a";
when "01" & x"79d" => data <= x"26";
when "01" & x"79e" => data <= x"2b";
when "01" & x"79f" => data <= x"06";
when "01" & x"7a0" => data <= x"2a";
when "01" & x"7a1" => data <= x"26";
when "01" & x"7a2" => data <= x"2b";
when "01" & x"7a3" => data <= x"98";
when "01" & x"7a4" => data <= x"65";
when "01" & x"7a5" => data <= x"2a";
when "01" & x"7a6" => data <= x"85";
when "01" & x"7a7" => data <= x"2a";
when "01" & x"7a8" => data <= x"90";
when "01" & x"7a9" => data <= x"03";
when "01" & x"7aa" => data <= x"e6";
when "01" & x"7ab" => data <= x"2b";
when "01" & x"7ac" => data <= x"18";
when "01" & x"7ad" => data <= x"a5";
when "01" & x"7ae" => data <= x"37";
when "01" & x"7af" => data <= x"65";
when "01" & x"7b0" => data <= x"2a";
when "01" & x"7b1" => data <= x"85";
when "01" & x"7b2" => data <= x"2a";
when "01" & x"7b3" => data <= x"a5";
when "01" & x"7b4" => data <= x"38";
when "01" & x"7b5" => data <= x"65";
when "01" & x"7b6" => data <= x"2b";
when "01" & x"7b7" => data <= x"85";
when "01" & x"7b8" => data <= x"2b";
when "01" & x"7b9" => data <= x"60";
when "01" & x"7ba" => data <= x"a5";
when "01" & x"7bb" => data <= x"2b";
when "01" & x"7bc" => data <= x"29";
when "01" & x"7bd" => data <= x"c0";
when "01" & x"7be" => data <= x"05";
when "01" & x"7bf" => data <= x"2c";
when "01" & x"7c0" => data <= x"05";
when "01" & x"7c1" => data <= x"2d";
when "01" & x"7c2" => data <= x"d0";
when "01" & x"7c3" => data <= x"0d";
when "01" & x"7c4" => data <= x"a5";
when "01" & x"7c5" => data <= x"2a";
when "01" & x"7c6" => data <= x"d1";
when "01" & x"7c7" => data <= x"37";
when "01" & x"7c8" => data <= x"c8";
when "01" & x"7c9" => data <= x"a5";
when "01" & x"7ca" => data <= x"2b";
when "01" & x"7cb" => data <= x"f1";
when "01" & x"7cc" => data <= x"37";
when "01" & x"7cd" => data <= x"b0";
when "01" & x"7ce" => data <= x"02";
when "01" & x"7cf" => data <= x"c8";
when "01" & x"7d0" => data <= x"60";
when "01" & x"7d1" => data <= x"00";
when "01" & x"7d2" => data <= x"0f";
when "01" & x"7d3" => data <= x"53";
when "01" & x"7d4" => data <= x"75";
when "01" & x"7d5" => data <= x"62";
when "01" & x"7d6" => data <= x"73";
when "01" & x"7d7" => data <= x"63";
when "01" & x"7d8" => data <= x"72";
when "01" & x"7d9" => data <= x"69";
when "01" & x"7da" => data <= x"70";
when "01" & x"7db" => data <= x"74";
when "01" & x"7dc" => data <= x"00";
when "01" & x"7dd" => data <= x"e6";
when "01" & x"7de" => data <= x"0a";
when "01" & x"7df" => data <= x"a4";
when "01" & x"7e0" => data <= x"0a";
when "01" & x"7e1" => data <= x"b1";
when "01" & x"7e2" => data <= x"0b";
when "01" & x"7e3" => data <= x"c9";
when "01" & x"7e4" => data <= x"20";
when "01" & x"7e5" => data <= x"f0";
when "01" & x"7e6" => data <= x"f6";
when "01" & x"7e7" => data <= x"c9";
when "01" & x"7e8" => data <= x"8d";
when "01" & x"7e9" => data <= x"d0";
when "01" & x"7ea" => data <= x"1a";
when "01" & x"7eb" => data <= x"c8";
when "01" & x"7ec" => data <= x"b1";
when "01" & x"7ed" => data <= x"0b";
when "01" & x"7ee" => data <= x"0a";
when "01" & x"7ef" => data <= x"0a";
when "01" & x"7f0" => data <= x"aa";
when "01" & x"7f1" => data <= x"29";
when "01" & x"7f2" => data <= x"c0";
when "01" & x"7f3" => data <= x"c8";
when "01" & x"7f4" => data <= x"51";
when "01" & x"7f5" => data <= x"0b";
when "01" & x"7f6" => data <= x"85";
when "01" & x"7f7" => data <= x"2a";
when "01" & x"7f8" => data <= x"8a";
when "01" & x"7f9" => data <= x"0a";
when "01" & x"7fa" => data <= x"0a";
when "01" & x"7fb" => data <= x"c8";
when "01" & x"7fc" => data <= x"51";
when "01" & x"7fd" => data <= x"0b";
when "01" & x"7fe" => data <= x"85";
when "01" & x"7ff" => data <= x"2b";
when "01" & x"800" => data <= x"c8";
when "01" & x"801" => data <= x"84";
when "01" & x"802" => data <= x"0a";
when "01" & x"803" => data <= x"38";
when "01" & x"804" => data <= x"60";
when "01" & x"805" => data <= x"18";
when "01" & x"806" => data <= x"60";
when "01" & x"807" => data <= x"a5";
when "01" & x"808" => data <= x"0b";
when "01" & x"809" => data <= x"85";
when "01" & x"80a" => data <= x"19";
when "01" & x"80b" => data <= x"a5";
when "01" & x"80c" => data <= x"0c";
when "01" & x"80d" => data <= x"85";
when "01" & x"80e" => data <= x"1a";
when "01" & x"80f" => data <= x"a5";
when "01" & x"810" => data <= x"0a";
when "01" & x"811" => data <= x"85";
when "01" & x"812" => data <= x"1b";
when "01" & x"813" => data <= x"a4";
when "01" & x"814" => data <= x"1b";
when "01" & x"815" => data <= x"e6";
when "01" & x"816" => data <= x"1b";
when "01" & x"817" => data <= x"b1";
when "01" & x"818" => data <= x"19";
when "01" & x"819" => data <= x"c9";
when "01" & x"81a" => data <= x"20";
when "01" & x"81b" => data <= x"f0";
when "01" & x"81c" => data <= x"f6";
when "01" & x"81d" => data <= x"c9";
when "01" & x"81e" => data <= x"3d";
when "01" & x"81f" => data <= x"f0";
when "01" & x"820" => data <= x"28";
when "01" & x"821" => data <= x"00";
when "01" & x"822" => data <= x"04";
when "01" & x"823" => data <= x"4d";
when "01" & x"824" => data <= x"69";
when "01" & x"825" => data <= x"73";
when "01" & x"826" => data <= x"74";
when "01" & x"827" => data <= x"61";
when "01" & x"828" => data <= x"6b";
when "01" & x"829" => data <= x"65";
when "01" & x"82a" => data <= x"00";
when "01" & x"82b" => data <= x"10";
when "01" & x"82c" => data <= x"53";
when "01" & x"82d" => data <= x"79";
when "01" & x"82e" => data <= x"6e";
when "01" & x"82f" => data <= x"74";
when "01" & x"830" => data <= x"61";
when "01" & x"831" => data <= x"78";
when "01" & x"832" => data <= x"20";
when "01" & x"833" => data <= x"65";
when "01" & x"834" => data <= x"72";
when "01" & x"835" => data <= x"72";
when "01" & x"836" => data <= x"6f";
when "01" & x"837" => data <= x"72";
when "01" & x"838" => data <= x"00";
when "01" & x"839" => data <= x"11";
when "01" & x"83a" => data <= x"45";
when "01" & x"83b" => data <= x"73";
when "01" & x"83c" => data <= x"63";
when "01" & x"83d" => data <= x"61";
when "01" & x"83e" => data <= x"70";
when "01" & x"83f" => data <= x"65";
when "01" & x"840" => data <= x"00";
when "01" & x"841" => data <= x"20";
when "01" & x"842" => data <= x"8c";
when "01" & x"843" => data <= x"8a";
when "01" & x"844" => data <= x"c9";
when "01" & x"845" => data <= x"3d";
when "01" & x"846" => data <= x"d0";
when "01" & x"847" => data <= x"d9";
when "01" & x"848" => data <= x"60";
when "01" & x"849" => data <= x"20";
when "01" & x"84a" => data <= x"29";
when "01" & x"84b" => data <= x"9b";
when "01" & x"84c" => data <= x"8a";
when "01" & x"84d" => data <= x"a4";
when "01" & x"84e" => data <= x"1b";
when "01" & x"84f" => data <= x"4c";
when "01" & x"850" => data <= x"61";
when "01" & x"851" => data <= x"98";
when "01" & x"852" => data <= x"a4";
when "01" & x"853" => data <= x"1b";
when "01" & x"854" => data <= x"4c";
when "01" & x"855" => data <= x"59";
when "01" & x"856" => data <= x"98";
when "01" & x"857" => data <= x"a4";
when "01" & x"858" => data <= x"0a";
when "01" & x"859" => data <= x"88";
when "01" & x"85a" => data <= x"c8";
when "01" & x"85b" => data <= x"b1";
when "01" & x"85c" => data <= x"0b";
when "01" & x"85d" => data <= x"c9";
when "01" & x"85e" => data <= x"20";
when "01" & x"85f" => data <= x"f0";
when "01" & x"860" => data <= x"f9";
when "01" & x"861" => data <= x"c9";
when "01" & x"862" => data <= x"3a";
when "01" & x"863" => data <= x"f0";
when "01" & x"864" => data <= x"08";
when "01" & x"865" => data <= x"c9";
when "01" & x"866" => data <= x"0d";
when "01" & x"867" => data <= x"f0";
when "01" & x"868" => data <= x"04";
when "01" & x"869" => data <= x"c9";
when "01" & x"86a" => data <= x"8b";
when "01" & x"86b" => data <= x"d0";
when "01" & x"86c" => data <= x"bd";
when "01" & x"86d" => data <= x"18";
when "01" & x"86e" => data <= x"98";
when "01" & x"86f" => data <= x"65";
when "01" & x"870" => data <= x"0b";
when "01" & x"871" => data <= x"85";
when "01" & x"872" => data <= x"0b";
when "01" & x"873" => data <= x"90";
when "01" & x"874" => data <= x"02";
when "01" & x"875" => data <= x"e6";
when "01" & x"876" => data <= x"0c";
when "01" & x"877" => data <= x"a0";
when "01" & x"878" => data <= x"01";
when "01" & x"879" => data <= x"84";
when "01" & x"87a" => data <= x"0a";
when "01" & x"87b" => data <= x"24";
when "01" & x"87c" => data <= x"ff";
when "01" & x"87d" => data <= x"30";
when "01" & x"87e" => data <= x"b9";
when "01" & x"87f" => data <= x"60";
when "01" & x"880" => data <= x"20";
when "01" & x"881" => data <= x"57";
when "01" & x"882" => data <= x"98";
when "01" & x"883" => data <= x"88";
when "01" & x"884" => data <= x"b1";
when "01" & x"885" => data <= x"0b";
when "01" & x"886" => data <= x"c9";
when "01" & x"887" => data <= x"3a";
when "01" & x"888" => data <= x"f0";
when "01" & x"889" => data <= x"f5";
when "01" & x"88a" => data <= x"a5";
when "01" & x"88b" => data <= x"0c";
when "01" & x"88c" => data <= x"c9";
when "01" & x"88d" => data <= x"07";
when "01" & x"88e" => data <= x"f0";
when "01" & x"88f" => data <= x"2c";
when "01" & x"890" => data <= x"c8";
when "01" & x"891" => data <= x"b1";
when "01" & x"892" => data <= x"0b";
when "01" & x"893" => data <= x"30";
when "01" & x"894" => data <= x"27";
when "01" & x"895" => data <= x"a5";
when "01" & x"896" => data <= x"20";
when "01" & x"897" => data <= x"f0";
when "01" & x"898" => data <= x"13";
when "01" & x"899" => data <= x"98";
when "01" & x"89a" => data <= x"48";
when "01" & x"89b" => data <= x"c8";
when "01" & x"89c" => data <= x"b1";
when "01" & x"89d" => data <= x"0b";
when "01" & x"89e" => data <= x"48";
when "01" & x"89f" => data <= x"88";
when "01" & x"8a0" => data <= x"b1";
when "01" & x"8a1" => data <= x"0b";
when "01" & x"8a2" => data <= x"a8";
when "01" & x"8a3" => data <= x"68";
when "01" & x"8a4" => data <= x"20";
when "01" & x"8a5" => data <= x"ea";
when "01" & x"8a6" => data <= x"ae";
when "01" & x"8a7" => data <= x"20";
when "01" & x"8a8" => data <= x"05";
when "01" & x"8a9" => data <= x"99";
when "01" & x"8aa" => data <= x"68";
when "01" & x"8ab" => data <= x"a8";
when "01" & x"8ac" => data <= x"c8";
when "01" & x"8ad" => data <= x"38";
when "01" & x"8ae" => data <= x"98";
when "01" & x"8af" => data <= x"65";
when "01" & x"8b0" => data <= x"0b";
when "01" & x"8b1" => data <= x"85";
when "01" & x"8b2" => data <= x"0b";
when "01" & x"8b3" => data <= x"90";
when "01" & x"8b4" => data <= x"02";
when "01" & x"8b5" => data <= x"e6";
when "01" & x"8b6" => data <= x"0c";
when "01" & x"8b7" => data <= x"a0";
when "01" & x"8b8" => data <= x"01";
when "01" & x"8b9" => data <= x"84";
when "01" & x"8ba" => data <= x"0a";
when "01" & x"8bb" => data <= x"60";
when "01" & x"8bc" => data <= x"4c";
when "01" & x"8bd" => data <= x"f6";
when "01" & x"8be" => data <= x"8a";
when "01" & x"8bf" => data <= x"4c";
when "01" & x"8c0" => data <= x"0e";
when "01" & x"8c1" => data <= x"8c";
when "01" & x"8c2" => data <= x"20";
when "01" & x"8c3" => data <= x"1d";
when "01" & x"8c4" => data <= x"9b";
when "01" & x"8c5" => data <= x"f0";
when "01" & x"8c6" => data <= x"f8";
when "01" & x"8c7" => data <= x"10";
when "01" & x"8c8" => data <= x"03";
when "01" & x"8c9" => data <= x"20";
when "01" & x"8ca" => data <= x"e4";
when "01" & x"8cb" => data <= x"a3";
when "01" & x"8cc" => data <= x"a4";
when "01" & x"8cd" => data <= x"1b";
when "01" & x"8ce" => data <= x"84";
when "01" & x"8cf" => data <= x"0a";
when "01" & x"8d0" => data <= x"a5";
when "01" & x"8d1" => data <= x"2a";
when "01" & x"8d2" => data <= x"05";
when "01" & x"8d3" => data <= x"2b";
when "01" & x"8d4" => data <= x"05";
when "01" & x"8d5" => data <= x"2c";
when "01" & x"8d6" => data <= x"05";
when "01" & x"8d7" => data <= x"2d";
when "01" & x"8d8" => data <= x"f0";
when "01" & x"8d9" => data <= x"17";
when "01" & x"8da" => data <= x"e0";
when "01" & x"8db" => data <= x"8c";
when "01" & x"8dc" => data <= x"f0";
when "01" & x"8dd" => data <= x"03";
when "01" & x"8de" => data <= x"4c";
when "01" & x"8df" => data <= x"a3";
when "01" & x"8e0" => data <= x"8b";
when "01" & x"8e1" => data <= x"e6";
when "01" & x"8e2" => data <= x"0a";
when "01" & x"8e3" => data <= x"20";
when "01" & x"8e4" => data <= x"df";
when "01" & x"8e5" => data <= x"97";
when "01" & x"8e6" => data <= x"90";
when "01" & x"8e7" => data <= x"f6";
when "01" & x"8e8" => data <= x"20";
when "01" & x"8e9" => data <= x"af";
when "01" & x"8ea" => data <= x"b9";
when "01" & x"8eb" => data <= x"20";
when "01" & x"8ec" => data <= x"77";
when "01" & x"8ed" => data <= x"98";
when "01" & x"8ee" => data <= x"4c";
when "01" & x"8ef" => data <= x"d2";
when "01" & x"8f0" => data <= x"b8";
when "01" & x"8f1" => data <= x"a4";
when "01" & x"8f2" => data <= x"0a";
when "01" & x"8f3" => data <= x"b1";
when "01" & x"8f4" => data <= x"0b";
when "01" & x"8f5" => data <= x"c9";
when "01" & x"8f6" => data <= x"0d";
when "01" & x"8f7" => data <= x"f0";
when "01" & x"8f8" => data <= x"09";
when "01" & x"8f9" => data <= x"c8";
when "01" & x"8fa" => data <= x"c9";
when "01" & x"8fb" => data <= x"8b";
when "01" & x"8fc" => data <= x"d0";
when "01" & x"8fd" => data <= x"f5";
when "01" & x"8fe" => data <= x"84";
when "01" & x"8ff" => data <= x"0a";
when "01" & x"900" => data <= x"f0";
when "01" & x"901" => data <= x"e1";
when "01" & x"902" => data <= x"4c";
when "01" & x"903" => data <= x"87";
when "01" & x"904" => data <= x"8b";
when "01" & x"905" => data <= x"a5";
when "01" & x"906" => data <= x"2a";
when "01" & x"907" => data <= x"c5";
when "01" & x"908" => data <= x"21";
when "01" & x"909" => data <= x"a5";
when "01" & x"90a" => data <= x"2b";
when "01" & x"90b" => data <= x"e5";
when "01" & x"90c" => data <= x"22";
when "01" & x"90d" => data <= x"b0";
when "01" & x"90e" => data <= x"ac";
when "01" & x"90f" => data <= x"a9";
when "01" & x"910" => data <= x"5b";
when "01" & x"911" => data <= x"20";
when "01" & x"912" => data <= x"58";
when "01" & x"913" => data <= x"b5";
when "01" & x"914" => data <= x"20";
when "01" & x"915" => data <= x"1f";
when "01" & x"916" => data <= x"99";
when "01" & x"917" => data <= x"a9";
when "01" & x"918" => data <= x"5d";
when "01" & x"919" => data <= x"20";
when "01" & x"91a" => data <= x"58";
when "01" & x"91b" => data <= x"b5";
when "01" & x"91c" => data <= x"4c";
when "01" & x"91d" => data <= x"65";
when "01" & x"91e" => data <= x"b5";
when "01" & x"91f" => data <= x"a9";
when "01" & x"920" => data <= x"00";
when "01" & x"921" => data <= x"f0";
when "01" & x"922" => data <= x"02";
when "01" & x"923" => data <= x"a9";
when "01" & x"924" => data <= x"05";
when "01" & x"925" => data <= x"85";
when "01" & x"926" => data <= x"14";
when "01" & x"927" => data <= x"a2";
when "01" & x"928" => data <= x"04";
when "01" & x"929" => data <= x"a9";
when "01" & x"92a" => data <= x"00";
when "01" & x"92b" => data <= x"95";
when "01" & x"92c" => data <= x"3f";
when "01" & x"92d" => data <= x"38";
when "01" & x"92e" => data <= x"a5";
when "01" & x"92f" => data <= x"2a";
when "01" & x"930" => data <= x"fd";
when "01" & x"931" => data <= x"6b";
when "01" & x"932" => data <= x"99";
when "01" & x"933" => data <= x"a8";
when "01" & x"934" => data <= x"a5";
when "01" & x"935" => data <= x"2b";
when "01" & x"936" => data <= x"fd";
when "01" & x"937" => data <= x"b9";
when "01" & x"938" => data <= x"99";
when "01" & x"939" => data <= x"90";
when "01" & x"93a" => data <= x"08";
when "01" & x"93b" => data <= x"85";
when "01" & x"93c" => data <= x"2b";
when "01" & x"93d" => data <= x"84";
when "01" & x"93e" => data <= x"2a";
when "01" & x"93f" => data <= x"f6";
when "01" & x"940" => data <= x"3f";
when "01" & x"941" => data <= x"d0";
when "01" & x"942" => data <= x"eb";
when "01" & x"943" => data <= x"ca";
when "01" & x"944" => data <= x"10";
when "01" & x"945" => data <= x"e3";
when "01" & x"946" => data <= x"a2";
when "01" & x"947" => data <= x"05";
when "01" & x"948" => data <= x"ca";
when "01" & x"949" => data <= x"f0";
when "01" & x"94a" => data <= x"04";
when "01" & x"94b" => data <= x"b5";
when "01" & x"94c" => data <= x"3f";
when "01" & x"94d" => data <= x"f0";
when "01" & x"94e" => data <= x"f9";
when "01" & x"94f" => data <= x"86";
when "01" & x"950" => data <= x"37";
when "01" & x"951" => data <= x"a5";
when "01" & x"952" => data <= x"14";
when "01" & x"953" => data <= x"f0";
when "01" & x"954" => data <= x"0b";
when "01" & x"955" => data <= x"e5";
when "01" & x"956" => data <= x"37";
when "01" & x"957" => data <= x"f0";
when "01" & x"958" => data <= x"07";
when "01" & x"959" => data <= x"a8";
when "01" & x"95a" => data <= x"20";
when "01" & x"95b" => data <= x"65";
when "01" & x"95c" => data <= x"b5";
when "01" & x"95d" => data <= x"88";
when "01" & x"95e" => data <= x"d0";
when "01" & x"95f" => data <= x"fa";
when "01" & x"960" => data <= x"b5";
when "01" & x"961" => data <= x"3f";
when "01" & x"962" => data <= x"09";
when "01" & x"963" => data <= x"30";
when "01" & x"964" => data <= x"20";
when "01" & x"965" => data <= x"58";
when "01" & x"966" => data <= x"b5";
when "01" & x"967" => data <= x"ca";
when "01" & x"968" => data <= x"10";
when "01" & x"969" => data <= x"f6";
when "01" & x"96a" => data <= x"60";
when "01" & x"96b" => data <= x"01";
when "01" & x"96c" => data <= x"0a";
when "01" & x"96d" => data <= x"64";
when "01" & x"96e" => data <= x"e8";
when "01" & x"96f" => data <= x"10";
when "01" & x"970" => data <= x"a0";
when "01" & x"971" => data <= x"00";
when "01" & x"972" => data <= x"84";
when "01" & x"973" => data <= x"3d";
when "01" & x"974" => data <= x"a5";
when "01" & x"975" => data <= x"18";
when "01" & x"976" => data <= x"85";
when "01" & x"977" => data <= x"3e";
when "01" & x"978" => data <= x"a0";
when "01" & x"979" => data <= x"01";
when "01" & x"97a" => data <= x"b1";
when "01" & x"97b" => data <= x"3d";
when "01" & x"97c" => data <= x"c5";
when "01" & x"97d" => data <= x"2b";
when "01" & x"97e" => data <= x"b0";
when "01" & x"97f" => data <= x"0e";
when "01" & x"980" => data <= x"a0";
when "01" & x"981" => data <= x"03";
when "01" & x"982" => data <= x"b1";
when "01" & x"983" => data <= x"3d";
when "01" & x"984" => data <= x"65";
when "01" & x"985" => data <= x"3d";
when "01" & x"986" => data <= x"85";
when "01" & x"987" => data <= x"3d";
when "01" & x"988" => data <= x"90";
when "01" & x"989" => data <= x"ee";
when "01" & x"98a" => data <= x"e6";
when "01" & x"98b" => data <= x"3e";
when "01" & x"98c" => data <= x"b0";
when "01" & x"98d" => data <= x"ea";
when "01" & x"98e" => data <= x"d0";
when "01" & x"98f" => data <= x"14";
when "01" & x"990" => data <= x"a0";
when "01" & x"991" => data <= x"02";
when "01" & x"992" => data <= x"b1";
when "01" & x"993" => data <= x"3d";
when "01" & x"994" => data <= x"c5";
when "01" & x"995" => data <= x"2a";
when "01" & x"996" => data <= x"90";
when "01" & x"997" => data <= x"e8";
when "01" & x"998" => data <= x"d0";
when "01" & x"999" => data <= x"0a";
when "01" & x"99a" => data <= x"98";
when "01" & x"99b" => data <= x"65";
when "01" & x"99c" => data <= x"3d";
when "01" & x"99d" => data <= x"85";
when "01" & x"99e" => data <= x"3d";
when "01" & x"99f" => data <= x"90";
when "01" & x"9a0" => data <= x"03";
when "01" & x"9a1" => data <= x"e6";
when "01" & x"9a2" => data <= x"3e";
when "01" & x"9a3" => data <= x"18";
when "01" & x"9a4" => data <= x"a0";
when "01" & x"9a5" => data <= x"02";
when "01" & x"9a6" => data <= x"60";
when "01" & x"9a7" => data <= x"00";
when "01" & x"9a8" => data <= x"12";
when "01" & x"9a9" => data <= x"44";
when "01" & x"9aa" => data <= x"69";
when "01" & x"9ab" => data <= x"76";
when "01" & x"9ac" => data <= x"69";
when "01" & x"9ad" => data <= x"73";
when "01" & x"9ae" => data <= x"69";
when "01" & x"9af" => data <= x"6f";
when "01" & x"9b0" => data <= x"6e";
when "01" & x"9b1" => data <= x"20";
when "01" & x"9b2" => data <= x"62";
when "01" & x"9b3" => data <= x"79";
when "01" & x"9b4" => data <= x"20";
when "01" & x"9b5" => data <= x"7a";
when "01" & x"9b6" => data <= x"65";
when "01" & x"9b7" => data <= x"72";
when "01" & x"9b8" => data <= x"6f";
when "01" & x"9b9" => data <= x"00";
when "01" & x"9ba" => data <= x"00";
when "01" & x"9bb" => data <= x"00";
when "01" & x"9bc" => data <= x"03";
when "01" & x"9bd" => data <= x"27";
when "01" & x"9be" => data <= x"a8";
when "01" & x"9bf" => data <= x"20";
when "01" & x"9c0" => data <= x"f0";
when "01" & x"9c1" => data <= x"92";
when "01" & x"9c2" => data <= x"a5";
when "01" & x"9c3" => data <= x"2d";
when "01" & x"9c4" => data <= x"48";
when "01" & x"9c5" => data <= x"20";
when "01" & x"9c6" => data <= x"71";
when "01" & x"9c7" => data <= x"ad";
when "01" & x"9c8" => data <= x"20";
when "01" & x"9c9" => data <= x"1d";
when "01" & x"9ca" => data <= x"9e";
when "01" & x"9cb" => data <= x"86";
when "01" & x"9cc" => data <= x"27";
when "01" & x"9cd" => data <= x"a8";
when "01" & x"9ce" => data <= x"20";
when "01" & x"9cf" => data <= x"f0";
when "01" & x"9d0" => data <= x"92";
when "01" & x"9d1" => data <= x"68";
when "01" & x"9d2" => data <= x"85";
when "01" & x"9d3" => data <= x"38";
when "01" & x"9d4" => data <= x"45";
when "01" & x"9d5" => data <= x"2d";
when "01" & x"9d6" => data <= x"85";
when "01" & x"9d7" => data <= x"37";
when "01" & x"9d8" => data <= x"20";
when "01" & x"9d9" => data <= x"71";
when "01" & x"9da" => data <= x"ad";
when "01" & x"9db" => data <= x"a2";
when "01" & x"9dc" => data <= x"39";
when "01" & x"9dd" => data <= x"20";
when "01" & x"9de" => data <= x"0d";
when "01" & x"9df" => data <= x"be";
when "01" & x"9e0" => data <= x"84";
when "01" & x"9e1" => data <= x"3d";
when "01" & x"9e2" => data <= x"84";
when "01" & x"9e3" => data <= x"3e";
when "01" & x"9e4" => data <= x"84";
when "01" & x"9e5" => data <= x"3f";
when "01" & x"9e6" => data <= x"84";
when "01" & x"9e7" => data <= x"40";
when "01" & x"9e8" => data <= x"a5";
when "01" & x"9e9" => data <= x"2d";
when "01" & x"9ea" => data <= x"05";
when "01" & x"9eb" => data <= x"2a";
when "01" & x"9ec" => data <= x"05";
when "01" & x"9ed" => data <= x"2b";
when "01" & x"9ee" => data <= x"05";
when "01" & x"9ef" => data <= x"2c";
when "01" & x"9f0" => data <= x"f0";
when "01" & x"9f1" => data <= x"b5";
when "01" & x"9f2" => data <= x"a0";
when "01" & x"9f3" => data <= x"20";
when "01" & x"9f4" => data <= x"88";
when "01" & x"9f5" => data <= x"f0";
when "01" & x"9f6" => data <= x"41";
when "01" & x"9f7" => data <= x"06";
when "01" & x"9f8" => data <= x"39";
when "01" & x"9f9" => data <= x"26";
when "01" & x"9fa" => data <= x"3a";
when "01" & x"9fb" => data <= x"26";
when "01" & x"9fc" => data <= x"3b";
when "01" & x"9fd" => data <= x"26";
when "01" & x"9fe" => data <= x"3c";
when "01" & x"9ff" => data <= x"10";
when "01" & x"a00" => data <= x"f3";
when "01" & x"a01" => data <= x"26";
when "01" & x"a02" => data <= x"39";
when "01" & x"a03" => data <= x"26";
when "01" & x"a04" => data <= x"3a";
when "01" & x"a05" => data <= x"26";
when "01" & x"a06" => data <= x"3b";
when "01" & x"a07" => data <= x"26";
when "01" & x"a08" => data <= x"3c";
when "01" & x"a09" => data <= x"26";
when "01" & x"a0a" => data <= x"3d";
when "01" & x"a0b" => data <= x"26";
when "01" & x"a0c" => data <= x"3e";
when "01" & x"a0d" => data <= x"26";
when "01" & x"a0e" => data <= x"3f";
when "01" & x"a0f" => data <= x"26";
when "01" & x"a10" => data <= x"40";
when "01" & x"a11" => data <= x"38";
when "01" & x"a12" => data <= x"a5";
when "01" & x"a13" => data <= x"3d";
when "01" & x"a14" => data <= x"e5";
when "01" & x"a15" => data <= x"2a";
when "01" & x"a16" => data <= x"48";
when "01" & x"a17" => data <= x"a5";
when "01" & x"a18" => data <= x"3e";
when "01" & x"a19" => data <= x"e5";
when "01" & x"a1a" => data <= x"2b";
when "01" & x"a1b" => data <= x"48";
when "01" & x"a1c" => data <= x"a5";
when "01" & x"a1d" => data <= x"3f";
when "01" & x"a1e" => data <= x"e5";
when "01" & x"a1f" => data <= x"2c";
when "01" & x"a20" => data <= x"aa";
when "01" & x"a21" => data <= x"a5";
when "01" & x"a22" => data <= x"40";
when "01" & x"a23" => data <= x"e5";
when "01" & x"a24" => data <= x"2d";
when "01" & x"a25" => data <= x"90";
when "01" & x"a26" => data <= x"0c";
when "01" & x"a27" => data <= x"85";
when "01" & x"a28" => data <= x"40";
when "01" & x"a29" => data <= x"86";
when "01" & x"a2a" => data <= x"3f";
when "01" & x"a2b" => data <= x"68";
when "01" & x"a2c" => data <= x"85";
when "01" & x"a2d" => data <= x"3e";
when "01" & x"a2e" => data <= x"68";
when "01" & x"a2f" => data <= x"85";
when "01" & x"a30" => data <= x"3d";
when "01" & x"a31" => data <= x"b0";
when "01" & x"a32" => data <= x"02";
when "01" & x"a33" => data <= x"68";
when "01" & x"a34" => data <= x"68";
when "01" & x"a35" => data <= x"88";
when "01" & x"a36" => data <= x"d0";
when "01" & x"a37" => data <= x"c9";
when "01" & x"a38" => data <= x"60";
when "01" & x"a39" => data <= x"86";
when "01" & x"a3a" => data <= x"27";
when "01" & x"a3b" => data <= x"20";
when "01" & x"a3c" => data <= x"ea";
when "01" & x"a3d" => data <= x"bd";
when "01" & x"a3e" => data <= x"20";
when "01" & x"a3f" => data <= x"51";
when "01" & x"a40" => data <= x"bd";
when "01" & x"a41" => data <= x"20";
when "01" & x"a42" => data <= x"be";
when "01" & x"a43" => data <= x"a2";
when "01" & x"a44" => data <= x"20";
when "01" & x"a45" => data <= x"1e";
when "01" & x"a46" => data <= x"a2";
when "01" & x"a47" => data <= x"20";
when "01" & x"a48" => data <= x"7e";
when "01" & x"a49" => data <= x"bd";
when "01" & x"a4a" => data <= x"20";
when "01" & x"a4b" => data <= x"b5";
when "01" & x"a4c" => data <= x"a3";
when "01" & x"a4d" => data <= x"4c";
when "01" & x"a4e" => data <= x"62";
when "01" & x"a4f" => data <= x"9a";
when "01" & x"a50" => data <= x"20";
when "01" & x"a51" => data <= x"51";
when "01" & x"a52" => data <= x"bd";
when "01" & x"a53" => data <= x"20";
when "01" & x"a54" => data <= x"42";
when "01" & x"a55" => data <= x"9c";
when "01" & x"a56" => data <= x"86";
when "01" & x"a57" => data <= x"27";
when "01" & x"a58" => data <= x"a8";
when "01" & x"a59" => data <= x"20";
when "01" & x"a5a" => data <= x"fd";
when "01" & x"a5b" => data <= x"92";
when "01" & x"a5c" => data <= x"20";
when "01" & x"a5d" => data <= x"7e";
when "01" & x"a5e" => data <= x"bd";
when "01" & x"a5f" => data <= x"20";
when "01" & x"a60" => data <= x"4e";
when "01" & x"a61" => data <= x"a3";
when "01" & x"a62" => data <= x"a6";
when "01" & x"a63" => data <= x"27";
when "01" & x"a64" => data <= x"a0";
when "01" & x"a65" => data <= x"00";
when "01" & x"a66" => data <= x"a5";
when "01" & x"a67" => data <= x"3b";
when "01" & x"a68" => data <= x"29";
when "01" & x"a69" => data <= x"80";
when "01" & x"a6a" => data <= x"85";
when "01" & x"a6b" => data <= x"3b";
when "01" & x"a6c" => data <= x"a5";
when "01" & x"a6d" => data <= x"2e";
when "01" & x"a6e" => data <= x"29";
when "01" & x"a6f" => data <= x"80";
when "01" & x"a70" => data <= x"c5";
when "01" & x"a71" => data <= x"3b";
when "01" & x"a72" => data <= x"d0";
when "01" & x"a73" => data <= x"1e";
when "01" & x"a74" => data <= x"a5";
when "01" & x"a75" => data <= x"3d";
when "01" & x"a76" => data <= x"c5";
when "01" & x"a77" => data <= x"30";
when "01" & x"a78" => data <= x"d0";
when "01" & x"a79" => data <= x"19";
when "01" & x"a7a" => data <= x"a5";
when "01" & x"a7b" => data <= x"3e";
when "01" & x"a7c" => data <= x"c5";
when "01" & x"a7d" => data <= x"31";
when "01" & x"a7e" => data <= x"d0";
when "01" & x"a7f" => data <= x"13";
when "01" & x"a80" => data <= x"a5";
when "01" & x"a81" => data <= x"3f";
when "01" & x"a82" => data <= x"c5";
when "01" & x"a83" => data <= x"32";
when "01" & x"a84" => data <= x"d0";
when "01" & x"a85" => data <= x"0d";
when "01" & x"a86" => data <= x"a5";
when "01" & x"a87" => data <= x"40";
when "01" & x"a88" => data <= x"c5";
when "01" & x"a89" => data <= x"33";
when "01" & x"a8a" => data <= x"d0";
when "01" & x"a8b" => data <= x"07";
when "01" & x"a8c" => data <= x"a5";
when "01" & x"a8d" => data <= x"41";
when "01" & x"a8e" => data <= x"c5";
when "01" & x"a8f" => data <= x"34";
when "01" & x"a90" => data <= x"d0";
when "01" & x"a91" => data <= x"01";
when "01" & x"a92" => data <= x"60";
when "01" & x"a93" => data <= x"6a";
when "01" & x"a94" => data <= x"45";
when "01" & x"a95" => data <= x"3b";
when "01" & x"a96" => data <= x"2a";
when "01" & x"a97" => data <= x"a9";
when "01" & x"a98" => data <= x"01";
when "01" & x"a99" => data <= x"60";
when "01" & x"a9a" => data <= x"4c";
when "01" & x"a9b" => data <= x"0e";
when "01" & x"a9c" => data <= x"8c";
when "01" & x"a9d" => data <= x"8a";
when "01" & x"a9e" => data <= x"f0";
when "01" & x"a9f" => data <= x"47";
when "01" & x"aa0" => data <= x"30";
when "01" & x"aa1" => data <= x"ae";
when "01" & x"aa2" => data <= x"20";
when "01" & x"aa3" => data <= x"94";
when "01" & x"aa4" => data <= x"bd";
when "01" & x"aa5" => data <= x"20";
when "01" & x"aa6" => data <= x"42";
when "01" & x"aa7" => data <= x"9c";
when "01" & x"aa8" => data <= x"a8";
when "01" & x"aa9" => data <= x"f0";
when "01" & x"aaa" => data <= x"ef";
when "01" & x"aab" => data <= x"30";
when "01" & x"aac" => data <= x"8c";
when "01" & x"aad" => data <= x"a5";
when "01" & x"aae" => data <= x"2d";
when "01" & x"aaf" => data <= x"49";
when "01" & x"ab0" => data <= x"80";
when "01" & x"ab1" => data <= x"85";
when "01" & x"ab2" => data <= x"2d";
when "01" & x"ab3" => data <= x"38";
when "01" & x"ab4" => data <= x"a0";
when "01" & x"ab5" => data <= x"00";
when "01" & x"ab6" => data <= x"b1";
when "01" & x"ab7" => data <= x"04";
when "01" & x"ab8" => data <= x"e5";
when "01" & x"ab9" => data <= x"2a";
when "01" & x"aba" => data <= x"85";
when "01" & x"abb" => data <= x"2a";
when "01" & x"abc" => data <= x"c8";
when "01" & x"abd" => data <= x"b1";
when "01" & x"abe" => data <= x"04";
when "01" & x"abf" => data <= x"e5";
when "01" & x"ac0" => data <= x"2b";
when "01" & x"ac1" => data <= x"85";
when "01" & x"ac2" => data <= x"2b";
when "01" & x"ac3" => data <= x"c8";
when "01" & x"ac4" => data <= x"b1";
when "01" & x"ac5" => data <= x"04";
when "01" & x"ac6" => data <= x"e5";
when "01" & x"ac7" => data <= x"2c";
when "01" & x"ac8" => data <= x"85";
when "01" & x"ac9" => data <= x"2c";
when "01" & x"aca" => data <= x"c8";
when "01" & x"acb" => data <= x"b1";
when "01" & x"acc" => data <= x"04";
when "01" & x"acd" => data <= x"a0";
when "01" & x"ace" => data <= x"00";
when "01" & x"acf" => data <= x"49";
when "01" & x"ad0" => data <= x"80";
when "01" & x"ad1" => data <= x"e5";
when "01" & x"ad2" => data <= x"2d";
when "01" & x"ad3" => data <= x"05";
when "01" & x"ad4" => data <= x"2a";
when "01" & x"ad5" => data <= x"05";
when "01" & x"ad6" => data <= x"2b";
when "01" & x"ad7" => data <= x"05";
when "01" & x"ad8" => data <= x"2c";
when "01" & x"ad9" => data <= x"08";
when "01" & x"ada" => data <= x"18";
when "01" & x"adb" => data <= x"a9";
when "01" & x"adc" => data <= x"04";
when "01" & x"add" => data <= x"65";
when "01" & x"ade" => data <= x"04";
when "01" & x"adf" => data <= x"85";
when "01" & x"ae0" => data <= x"04";
when "01" & x"ae1" => data <= x"90";
when "01" & x"ae2" => data <= x"02";
when "01" & x"ae3" => data <= x"e6";
when "01" & x"ae4" => data <= x"05";
when "01" & x"ae5" => data <= x"28";
when "01" & x"ae6" => data <= x"60";
when "01" & x"ae7" => data <= x"20";
when "01" & x"ae8" => data <= x"b2";
when "01" & x"ae9" => data <= x"bd";
when "01" & x"aea" => data <= x"20";
when "01" & x"aeb" => data <= x"42";
when "01" & x"aec" => data <= x"9c";
when "01" & x"aed" => data <= x"a8";
when "01" & x"aee" => data <= x"d0";
when "01" & x"aef" => data <= x"aa";
when "01" & x"af0" => data <= x"86";
when "01" & x"af1" => data <= x"37";
when "01" & x"af2" => data <= x"a6";
when "01" & x"af3" => data <= x"36";
when "01" & x"af4" => data <= x"a0";
when "01" & x"af5" => data <= x"00";
when "01" & x"af6" => data <= x"b1";
when "01" & x"af7" => data <= x"04";
when "01" & x"af8" => data <= x"85";
when "01" & x"af9" => data <= x"39";
when "01" & x"afa" => data <= x"c5";
when "01" & x"afb" => data <= x"36";
when "01" & x"afc" => data <= x"b0";
when "01" & x"afd" => data <= x"01";
when "01" & x"afe" => data <= x"aa";
when "01" & x"aff" => data <= x"86";
when "01" & x"b00" => data <= x"3a";
when "01" & x"b01" => data <= x"a0";
when "01" & x"b02" => data <= x"00";
when "01" & x"b03" => data <= x"c4";
when "01" & x"b04" => data <= x"3a";
when "01" & x"b05" => data <= x"f0";
when "01" & x"b06" => data <= x"0a";
when "01" & x"b07" => data <= x"c8";
when "01" & x"b08" => data <= x"b1";
when "01" & x"b09" => data <= x"04";
when "01" & x"b0a" => data <= x"d9";
when "01" & x"b0b" => data <= x"ff";
when "01" & x"b0c" => data <= x"05";
when "01" & x"b0d" => data <= x"f0";
when "01" & x"b0e" => data <= x"f4";
when "01" & x"b0f" => data <= x"d0";
when "01" & x"b10" => data <= x"04";
when "01" & x"b11" => data <= x"a5";
when "01" & x"b12" => data <= x"39";
when "01" & x"b13" => data <= x"c5";
when "01" & x"b14" => data <= x"36";
when "01" & x"b15" => data <= x"08";
when "01" & x"b16" => data <= x"20";
when "01" & x"b17" => data <= x"dc";
when "01" & x"b18" => data <= x"bd";
when "01" & x"b19" => data <= x"a6";
when "01" & x"b1a" => data <= x"37";
when "01" & x"b1b" => data <= x"28";
when "01" & x"b1c" => data <= x"60";
when "01" & x"b1d" => data <= x"a5";
when "01" & x"b1e" => data <= x"0b";
when "01" & x"b1f" => data <= x"85";
when "01" & x"b20" => data <= x"19";
when "01" & x"b21" => data <= x"a5";
when "01" & x"b22" => data <= x"0c";
when "01" & x"b23" => data <= x"85";
when "01" & x"b24" => data <= x"1a";
when "01" & x"b25" => data <= x"a5";
when "01" & x"b26" => data <= x"0a";
when "01" & x"b27" => data <= x"85";
when "01" & x"b28" => data <= x"1b";
when "01" & x"b29" => data <= x"20";
when "01" & x"b2a" => data <= x"72";
when "01" & x"b2b" => data <= x"9b";
when "01" & x"b2c" => data <= x"e0";
when "01" & x"b2d" => data <= x"84";
when "01" & x"b2e" => data <= x"f0";
when "01" & x"b2f" => data <= x"0a";
when "01" & x"b30" => data <= x"e0";
when "01" & x"b31" => data <= x"82";
when "01" & x"b32" => data <= x"f0";
when "01" & x"b33" => data <= x"21";
when "01" & x"b34" => data <= x"c6";
when "01" & x"b35" => data <= x"1b";
when "01" & x"b36" => data <= x"a8";
when "01" & x"b37" => data <= x"85";
when "01" & x"b38" => data <= x"27";
when "01" & x"b39" => data <= x"60";
when "01" & x"b3a" => data <= x"20";
when "01" & x"b3b" => data <= x"6b";
when "01" & x"b3c" => data <= x"9b";
when "01" & x"b3d" => data <= x"a8";
when "01" & x"b3e" => data <= x"20";
when "01" & x"b3f" => data <= x"f0";
when "01" & x"b40" => data <= x"92";
when "01" & x"b41" => data <= x"a0";
when "01" & x"b42" => data <= x"03";
when "01" & x"b43" => data <= x"b1";
when "01" & x"b44" => data <= x"04";
when "01" & x"b45" => data <= x"19";
when "01" & x"b46" => data <= x"2a";
when "01" & x"b47" => data <= x"00";
when "01" & x"b48" => data <= x"99";
when "01" & x"b49" => data <= x"2a";
when "01" & x"b4a" => data <= x"00";
when "01" & x"b4b" => data <= x"88";
when "01" & x"b4c" => data <= x"10";
when "01" & x"b4d" => data <= x"f5";
when "01" & x"b4e" => data <= x"20";
when "01" & x"b4f" => data <= x"ff";
when "01" & x"b50" => data <= x"bd";
when "01" & x"b51" => data <= x"a9";
when "01" & x"b52" => data <= x"40";
when "01" & x"b53" => data <= x"d0";
when "01" & x"b54" => data <= x"d7";
when "01" & x"b55" => data <= x"20";
when "01" & x"b56" => data <= x"6b";
when "01" & x"b57" => data <= x"9b";
when "01" & x"b58" => data <= x"a8";
when "01" & x"b59" => data <= x"20";
when "01" & x"b5a" => data <= x"f0";
when "01" & x"b5b" => data <= x"92";
when "01" & x"b5c" => data <= x"a0";
when "01" & x"b5d" => data <= x"03";
when "01" & x"b5e" => data <= x"b1";
when "01" & x"b5f" => data <= x"04";
when "01" & x"b60" => data <= x"59";
when "01" & x"b61" => data <= x"2a";
when "01" & x"b62" => data <= x"00";
when "01" & x"b63" => data <= x"99";
when "01" & x"b64" => data <= x"2a";
when "01" & x"b65" => data <= x"00";
when "01" & x"b66" => data <= x"88";
when "01" & x"b67" => data <= x"10";
when "01" & x"b68" => data <= x"f5";
when "01" & x"b69" => data <= x"30";
when "01" & x"b6a" => data <= x"e3";
when "01" & x"b6b" => data <= x"a8";
when "01" & x"b6c" => data <= x"20";
when "01" & x"b6d" => data <= x"f0";
when "01" & x"b6e" => data <= x"92";
when "01" & x"b6f" => data <= x"20";
when "01" & x"b70" => data <= x"94";
when "01" & x"b71" => data <= x"bd";
when "01" & x"b72" => data <= x"20";
when "01" & x"b73" => data <= x"9c";
when "01" & x"b74" => data <= x"9b";
when "01" & x"b75" => data <= x"e0";
when "01" & x"b76" => data <= x"80";
when "01" & x"b77" => data <= x"f0";
when "01" & x"b78" => data <= x"01";
when "01" & x"b79" => data <= x"60";
when "01" & x"b7a" => data <= x"a8";
when "01" & x"b7b" => data <= x"20";
when "01" & x"b7c" => data <= x"f0";
when "01" & x"b7d" => data <= x"92";
when "01" & x"b7e" => data <= x"20";
when "01" & x"b7f" => data <= x"94";
when "01" & x"b80" => data <= x"bd";
when "01" & x"b81" => data <= x"20";
when "01" & x"b82" => data <= x"9c";
when "01" & x"b83" => data <= x"9b";
when "01" & x"b84" => data <= x"a8";
when "01" & x"b85" => data <= x"20";
when "01" & x"b86" => data <= x"f0";
when "01" & x"b87" => data <= x"92";
when "01" & x"b88" => data <= x"a0";
when "01" & x"b89" => data <= x"03";
when "01" & x"b8a" => data <= x"b1";
when "01" & x"b8b" => data <= x"04";
when "01" & x"b8c" => data <= x"39";
when "01" & x"b8d" => data <= x"2a";
when "01" & x"b8e" => data <= x"00";
when "01" & x"b8f" => data <= x"99";
when "01" & x"b90" => data <= x"2a";
when "01" & x"b91" => data <= x"00";
when "01" & x"b92" => data <= x"88";
when "01" & x"b93" => data <= x"10";
when "01" & x"b94" => data <= x"f5";
when "01" & x"b95" => data <= x"20";
when "01" & x"b96" => data <= x"ff";
when "01" & x"b97" => data <= x"bd";
when "01" & x"b98" => data <= x"a9";
when "01" & x"b99" => data <= x"40";
when "01" & x"b9a" => data <= x"d0";
when "01" & x"b9b" => data <= x"d9";
when "01" & x"b9c" => data <= x"20";
when "01" & x"b9d" => data <= x"42";
when "01" & x"b9e" => data <= x"9c";
when "01" & x"b9f" => data <= x"e0";
when "01" & x"ba0" => data <= x"3f";
when "01" & x"ba1" => data <= x"b0";
when "01" & x"ba2" => data <= x"04";
when "01" & x"ba3" => data <= x"e0";
when "01" & x"ba4" => data <= x"3c";
when "01" & x"ba5" => data <= x"b0";
when "01" & x"ba6" => data <= x"01";
when "01" & x"ba7" => data <= x"60";
when "01" & x"ba8" => data <= x"f0";
when "01" & x"ba9" => data <= x"16";
when "01" & x"baa" => data <= x"e0";
when "01" & x"bab" => data <= x"3e";
when "01" & x"bac" => data <= x"f0";
when "01" & x"bad" => data <= x"3a";
when "01" & x"bae" => data <= x"aa";
when "01" & x"baf" => data <= x"20";
when "01" & x"bb0" => data <= x"9e";
when "01" & x"bb1" => data <= x"9a";
when "01" & x"bb2" => data <= x"d0";
when "01" & x"bb3" => data <= x"01";
when "01" & x"bb4" => data <= x"88";
when "01" & x"bb5" => data <= x"84";
when "01" & x"bb6" => data <= x"2a";
when "01" & x"bb7" => data <= x"84";
when "01" & x"bb8" => data <= x"2b";
when "01" & x"bb9" => data <= x"84";
when "01" & x"bba" => data <= x"2c";
when "01" & x"bbb" => data <= x"84";
when "01" & x"bbc" => data <= x"2d";
when "01" & x"bbd" => data <= x"a9";
when "01" & x"bbe" => data <= x"40";
when "01" & x"bbf" => data <= x"60";
when "01" & x"bc0" => data <= x"aa";
when "01" & x"bc1" => data <= x"a4";
when "01" & x"bc2" => data <= x"1b";
when "01" & x"bc3" => data <= x"b1";
when "01" & x"bc4" => data <= x"19";
when "01" & x"bc5" => data <= x"c9";
when "01" & x"bc6" => data <= x"3d";
when "01" & x"bc7" => data <= x"f0";
when "01" & x"bc8" => data <= x"0b";
when "01" & x"bc9" => data <= x"c9";
when "01" & x"bca" => data <= x"3e";
when "01" & x"bcb" => data <= x"f0";
when "01" & x"bcc" => data <= x"12";
when "01" & x"bcd" => data <= x"20";
when "01" & x"bce" => data <= x"9d";
when "01" & x"bcf" => data <= x"9a";
when "01" & x"bd0" => data <= x"90";
when "01" & x"bd1" => data <= x"e2";
when "01" & x"bd2" => data <= x"b0";
when "01" & x"bd3" => data <= x"e1";
when "01" & x"bd4" => data <= x"e6";
when "01" & x"bd5" => data <= x"1b";
when "01" & x"bd6" => data <= x"20";
when "01" & x"bd7" => data <= x"9d";
when "01" & x"bd8" => data <= x"9a";
when "01" & x"bd9" => data <= x"f0";
when "01" & x"bda" => data <= x"d9";
when "01" & x"bdb" => data <= x"90";
when "01" & x"bdc" => data <= x"d7";
when "01" & x"bdd" => data <= x"b0";
when "01" & x"bde" => data <= x"d6";
when "01" & x"bdf" => data <= x"e6";
when "01" & x"be0" => data <= x"1b";
when "01" & x"be1" => data <= x"20";
when "01" & x"be2" => data <= x"9d";
when "01" & x"be3" => data <= x"9a";
when "01" & x"be4" => data <= x"d0";
when "01" & x"be5" => data <= x"ce";
when "01" & x"be6" => data <= x"f0";
when "01" & x"be7" => data <= x"cd";
when "01" & x"be8" => data <= x"aa";
when "01" & x"be9" => data <= x"a4";
when "01" & x"bea" => data <= x"1b";
when "01" & x"beb" => data <= x"b1";
when "01" & x"bec" => data <= x"19";
when "01" & x"bed" => data <= x"c9";
when "01" & x"bee" => data <= x"3d";
when "01" & x"bef" => data <= x"f0";
when "01" & x"bf0" => data <= x"09";
when "01" & x"bf1" => data <= x"20";
when "01" & x"bf2" => data <= x"9d";
when "01" & x"bf3" => data <= x"9a";
when "01" & x"bf4" => data <= x"f0";
when "01" & x"bf5" => data <= x"bf";
when "01" & x"bf6" => data <= x"b0";
when "01" & x"bf7" => data <= x"bc";
when "01" & x"bf8" => data <= x"90";
when "01" & x"bf9" => data <= x"bb";
when "01" & x"bfa" => data <= x"e6";
when "01" & x"bfb" => data <= x"1b";
when "01" & x"bfc" => data <= x"20";
when "01" & x"bfd" => data <= x"9d";
when "01" & x"bfe" => data <= x"9a";
when "01" & x"bff" => data <= x"b0";
when "01" & x"c00" => data <= x"b3";
when "01" & x"c01" => data <= x"90";
when "01" & x"c02" => data <= x"b2";
when "01" & x"c03" => data <= x"00";
when "01" & x"c04" => data <= x"13";
when "01" & x"c05" => data <= x"53";
when "01" & x"c06" => data <= x"74";
when "01" & x"c07" => data <= x"72";
when "01" & x"c08" => data <= x"69";
when "01" & x"c09" => data <= x"6e";
when "01" & x"c0a" => data <= x"67";
when "01" & x"c0b" => data <= x"20";
when "01" & x"c0c" => data <= x"74";
when "01" & x"c0d" => data <= x"6f";
when "01" & x"c0e" => data <= x"6f";
when "01" & x"c0f" => data <= x"20";
when "01" & x"c10" => data <= x"6c";
when "01" & x"c11" => data <= x"6f";
when "01" & x"c12" => data <= x"6e";
when "01" & x"c13" => data <= x"67";
when "01" & x"c14" => data <= x"00";
when "01" & x"c15" => data <= x"20";
when "01" & x"c16" => data <= x"b2";
when "01" & x"c17" => data <= x"bd";
when "01" & x"c18" => data <= x"20";
when "01" & x"c19" => data <= x"20";
when "01" & x"c1a" => data <= x"9e";
when "01" & x"c1b" => data <= x"a8";
when "01" & x"c1c" => data <= x"d0";
when "01" & x"c1d" => data <= x"6a";
when "01" & x"c1e" => data <= x"18";
when "01" & x"c1f" => data <= x"86";
when "01" & x"c20" => data <= x"37";
when "01" & x"c21" => data <= x"a0";
when "01" & x"c22" => data <= x"00";
when "01" & x"c23" => data <= x"b1";
when "01" & x"c24" => data <= x"04";
when "01" & x"c25" => data <= x"65";
when "01" & x"c26" => data <= x"36";
when "01" & x"c27" => data <= x"b0";
when "01" & x"c28" => data <= x"da";
when "01" & x"c29" => data <= x"aa";
when "01" & x"c2a" => data <= x"48";
when "01" & x"c2b" => data <= x"a4";
when "01" & x"c2c" => data <= x"36";
when "01" & x"c2d" => data <= x"b9";
when "01" & x"c2e" => data <= x"ff";
when "01" & x"c2f" => data <= x"05";
when "01" & x"c30" => data <= x"9d";
when "01" & x"c31" => data <= x"ff";
when "01" & x"c32" => data <= x"05";
when "01" & x"c33" => data <= x"ca";
when "01" & x"c34" => data <= x"88";
when "01" & x"c35" => data <= x"d0";
when "01" & x"c36" => data <= x"f6";
when "01" & x"c37" => data <= x"20";
when "01" & x"c38" => data <= x"cb";
when "01" & x"c39" => data <= x"bd";
when "01" & x"c3a" => data <= x"68";
when "01" & x"c3b" => data <= x"85";
when "01" & x"c3c" => data <= x"36";
when "01" & x"c3d" => data <= x"a6";
when "01" & x"c3e" => data <= x"37";
when "01" & x"c3f" => data <= x"98";
when "01" & x"c40" => data <= x"f0";
when "01" & x"c41" => data <= x"03";
when "01" & x"c42" => data <= x"20";
when "01" & x"c43" => data <= x"d1";
when "01" & x"c44" => data <= x"9d";
when "01" & x"c45" => data <= x"e0";
when "01" & x"c46" => data <= x"2b";
when "01" & x"c47" => data <= x"f0";
when "01" & x"c48" => data <= x"05";
when "01" & x"c49" => data <= x"e0";
when "01" & x"c4a" => data <= x"2d";
when "01" & x"c4b" => data <= x"f0";
when "01" & x"c4c" => data <= x"68";
when "01" & x"c4d" => data <= x"60";
when "01" & x"c4e" => data <= x"a8";
when "01" & x"c4f" => data <= x"f0";
when "01" & x"c50" => data <= x"c4";
when "01" & x"c51" => data <= x"30";
when "01" & x"c52" => data <= x"38";
when "01" & x"c53" => data <= x"20";
when "01" & x"c54" => data <= x"ce";
when "01" & x"c55" => data <= x"9d";
when "01" & x"c56" => data <= x"a8";
when "01" & x"c57" => data <= x"f0";
when "01" & x"c58" => data <= x"2f";
when "01" & x"c59" => data <= x"30";
when "01" & x"c5a" => data <= x"4c";
when "01" & x"c5b" => data <= x"a0";
when "01" & x"c5c" => data <= x"00";
when "01" & x"c5d" => data <= x"18";
when "01" & x"c5e" => data <= x"b1";
when "01" & x"c5f" => data <= x"04";
when "01" & x"c60" => data <= x"65";
when "01" & x"c61" => data <= x"2a";
when "01" & x"c62" => data <= x"85";
when "01" & x"c63" => data <= x"2a";
when "01" & x"c64" => data <= x"c8";
when "01" & x"c65" => data <= x"b1";
when "01" & x"c66" => data <= x"04";
when "01" & x"c67" => data <= x"65";
when "01" & x"c68" => data <= x"2b";
when "01" & x"c69" => data <= x"85";
when "01" & x"c6a" => data <= x"2b";
when "01" & x"c6b" => data <= x"c8";
when "01" & x"c6c" => data <= x"b1";
when "01" & x"c6d" => data <= x"04";
when "01" & x"c6e" => data <= x"65";
when "01" & x"c6f" => data <= x"2c";
when "01" & x"c70" => data <= x"85";
when "01" & x"c71" => data <= x"2c";
when "01" & x"c72" => data <= x"c8";
when "01" & x"c73" => data <= x"b1";
when "01" & x"c74" => data <= x"04";
when "01" & x"c75" => data <= x"65";
when "01" & x"c76" => data <= x"2d";
when "01" & x"c77" => data <= x"85";
when "01" & x"c78" => data <= x"2d";
when "01" & x"c79" => data <= x"18";
when "01" & x"c7a" => data <= x"a5";
when "01" & x"c7b" => data <= x"04";
when "01" & x"c7c" => data <= x"69";
when "01" & x"c7d" => data <= x"04";
when "01" & x"c7e" => data <= x"85";
when "01" & x"c7f" => data <= x"04";
when "01" & x"c80" => data <= x"a9";
when "01" & x"c81" => data <= x"40";
when "01" & x"c82" => data <= x"90";
when "01" & x"c83" => data <= x"c1";
when "01" & x"c84" => data <= x"e6";
when "01" & x"c85" => data <= x"05";
when "01" & x"c86" => data <= x"b0";
when "01" & x"c87" => data <= x"bd";
when "01" & x"c88" => data <= x"4c";
when "01" & x"c89" => data <= x"0e";
when "01" & x"c8a" => data <= x"8c";
when "01" & x"c8b" => data <= x"20";
when "01" & x"c8c" => data <= x"51";
when "01" & x"c8d" => data <= x"bd";
when "01" & x"c8e" => data <= x"20";
when "01" & x"c8f" => data <= x"d1";
when "01" & x"c90" => data <= x"9d";
when "01" & x"c91" => data <= x"a8";
when "01" & x"c92" => data <= x"f0";
when "01" & x"c93" => data <= x"f4";
when "01" & x"c94" => data <= x"86";
when "01" & x"c95" => data <= x"27";
when "01" & x"c96" => data <= x"30";
when "01" & x"c97" => data <= x"03";
when "01" & x"c98" => data <= x"20";
when "01" & x"c99" => data <= x"be";
when "01" & x"c9a" => data <= x"a2";
when "01" & x"c9b" => data <= x"20";
when "01" & x"c9c" => data <= x"7e";
when "01" & x"c9d" => data <= x"bd";
when "01" & x"c9e" => data <= x"20";
when "01" & x"c9f" => data <= x"00";
when "01" & x"ca0" => data <= x"a5";
when "01" & x"ca1" => data <= x"a6";
when "01" & x"ca2" => data <= x"27";
when "01" & x"ca3" => data <= x"a9";
when "01" & x"ca4" => data <= x"ff";
when "01" & x"ca5" => data <= x"d0";
when "01" & x"ca6" => data <= x"9e";
when "01" & x"ca7" => data <= x"86";
when "01" & x"ca8" => data <= x"27";
when "01" & x"ca9" => data <= x"20";
when "01" & x"caa" => data <= x"ea";
when "01" & x"cab" => data <= x"bd";
when "01" & x"cac" => data <= x"20";
when "01" & x"cad" => data <= x"51";
when "01" & x"cae" => data <= x"bd";
when "01" & x"caf" => data <= x"20";
when "01" & x"cb0" => data <= x"be";
when "01" & x"cb1" => data <= x"a2";
when "01" & x"cb2" => data <= x"4c";
when "01" & x"cb3" => data <= x"9b";
when "01" & x"cb4" => data <= x"9c";
when "01" & x"cb5" => data <= x"a8";
when "01" & x"cb6" => data <= x"f0";
when "01" & x"cb7" => data <= x"d0";
when "01" & x"cb8" => data <= x"30";
when "01" & x"cb9" => data <= x"27";
when "01" & x"cba" => data <= x"20";
when "01" & x"cbb" => data <= x"ce";
when "01" & x"cbc" => data <= x"9d";
when "01" & x"cbd" => data <= x"a8";
when "01" & x"cbe" => data <= x"f0";
when "01" & x"cbf" => data <= x"c8";
when "01" & x"cc0" => data <= x"30";
when "01" & x"cc1" => data <= x"38";
when "01" & x"cc2" => data <= x"38";
when "01" & x"cc3" => data <= x"a0";
when "01" & x"cc4" => data <= x"00";
when "01" & x"cc5" => data <= x"b1";
when "01" & x"cc6" => data <= x"04";
when "01" & x"cc7" => data <= x"e5";
when "01" & x"cc8" => data <= x"2a";
when "01" & x"cc9" => data <= x"85";
when "01" & x"cca" => data <= x"2a";
when "01" & x"ccb" => data <= x"c8";
when "01" & x"ccc" => data <= x"b1";
when "01" & x"ccd" => data <= x"04";
when "01" & x"cce" => data <= x"e5";
when "01" & x"ccf" => data <= x"2b";
when "01" & x"cd0" => data <= x"85";
when "01" & x"cd1" => data <= x"2b";
when "01" & x"cd2" => data <= x"c8";
when "01" & x"cd3" => data <= x"b1";
when "01" & x"cd4" => data <= x"04";
when "01" & x"cd5" => data <= x"e5";
when "01" & x"cd6" => data <= x"2c";
when "01" & x"cd7" => data <= x"85";
when "01" & x"cd8" => data <= x"2c";
when "01" & x"cd9" => data <= x"c8";
when "01" & x"cda" => data <= x"b1";
when "01" & x"cdb" => data <= x"04";
when "01" & x"cdc" => data <= x"e5";
when "01" & x"cdd" => data <= x"2d";
when "01" & x"cde" => data <= x"4c";
when "01" & x"cdf" => data <= x"77";
when "01" & x"ce0" => data <= x"9c";
when "01" & x"ce1" => data <= x"20";
when "01" & x"ce2" => data <= x"51";
when "01" & x"ce3" => data <= x"bd";
when "01" & x"ce4" => data <= x"20";
when "01" & x"ce5" => data <= x"d1";
when "01" & x"ce6" => data <= x"9d";
when "01" & x"ce7" => data <= x"a8";
when "01" & x"ce8" => data <= x"f0";
when "01" & x"ce9" => data <= x"9e";
when "01" & x"cea" => data <= x"86";
when "01" & x"ceb" => data <= x"27";
when "01" & x"cec" => data <= x"30";
when "01" & x"ced" => data <= x"03";
when "01" & x"cee" => data <= x"20";
when "01" & x"cef" => data <= x"be";
when "01" & x"cf0" => data <= x"a2";
when "01" & x"cf1" => data <= x"20";
when "01" & x"cf2" => data <= x"7e";
when "01" & x"cf3" => data <= x"bd";
when "01" & x"cf4" => data <= x"20";
when "01" & x"cf5" => data <= x"fd";
when "01" & x"cf6" => data <= x"a4";
when "01" & x"cf7" => data <= x"4c";
when "01" & x"cf8" => data <= x"a1";
when "01" & x"cf9" => data <= x"9c";
when "01" & x"cfa" => data <= x"86";
when "01" & x"cfb" => data <= x"27";
when "01" & x"cfc" => data <= x"20";
when "01" & x"cfd" => data <= x"ea";
when "01" & x"cfe" => data <= x"bd";
when "01" & x"cff" => data <= x"20";
when "01" & x"d00" => data <= x"51";
when "01" & x"d01" => data <= x"bd";
when "01" & x"d02" => data <= x"20";
when "01" & x"d03" => data <= x"be";
when "01" & x"d04" => data <= x"a2";
when "01" & x"d05" => data <= x"20";
when "01" & x"d06" => data <= x"7e";
when "01" & x"d07" => data <= x"bd";
when "01" & x"d08" => data <= x"20";
when "01" & x"d09" => data <= x"d0";
when "01" & x"d0a" => data <= x"a4";
when "01" & x"d0b" => data <= x"4c";
when "01" & x"d0c" => data <= x"a1";
when "01" & x"d0d" => data <= x"9c";
when "01" & x"d0e" => data <= x"20";
when "01" & x"d0f" => data <= x"be";
when "01" & x"d10" => data <= x"a2";
when "01" & x"d11" => data <= x"20";
when "01" & x"d12" => data <= x"ea";
when "01" & x"d13" => data <= x"bd";
when "01" & x"d14" => data <= x"20";
when "01" & x"d15" => data <= x"51";
when "01" & x"d16" => data <= x"bd";
when "01" & x"d17" => data <= x"20";
when "01" & x"d18" => data <= x"be";
when "01" & x"d19" => data <= x"a2";
when "01" & x"d1a" => data <= x"4c";
when "01" & x"d1b" => data <= x"2c";
when "01" & x"d1c" => data <= x"9d";
when "01" & x"d1d" => data <= x"20";
when "01" & x"d1e" => data <= x"be";
when "01" & x"d1f" => data <= x"a2";
when "01" & x"d20" => data <= x"20";
when "01" & x"d21" => data <= x"51";
when "01" & x"d22" => data <= x"bd";
when "01" & x"d23" => data <= x"20";
when "01" & x"d24" => data <= x"20";
when "01" & x"d25" => data <= x"9e";
when "01" & x"d26" => data <= x"86";
when "01" & x"d27" => data <= x"27";
when "01" & x"d28" => data <= x"a8";
when "01" & x"d29" => data <= x"20";
when "01" & x"d2a" => data <= x"fd";
when "01" & x"d2b" => data <= x"92";
when "01" & x"d2c" => data <= x"20";
when "01" & x"d2d" => data <= x"7e";
when "01" & x"d2e" => data <= x"bd";
when "01" & x"d2f" => data <= x"20";
when "01" & x"d30" => data <= x"56";
when "01" & x"d31" => data <= x"a6";
when "01" & x"d32" => data <= x"a9";
when "01" & x"d33" => data <= x"ff";
when "01" & x"d34" => data <= x"a6";
when "01" & x"d35" => data <= x"27";
when "01" & x"d36" => data <= x"4c";
when "01" & x"d37" => data <= x"d4";
when "01" & x"d38" => data <= x"9d";
when "01" & x"d39" => data <= x"4c";
when "01" & x"d3a" => data <= x"0e";
when "01" & x"d3b" => data <= x"8c";
when "01" & x"d3c" => data <= x"a8";
when "01" & x"d3d" => data <= x"f0";
when "01" & x"d3e" => data <= x"fa";
when "01" & x"d3f" => data <= x"30";
when "01" & x"d40" => data <= x"df";
when "01" & x"d41" => data <= x"a5";
when "01" & x"d42" => data <= x"2d";
when "01" & x"d43" => data <= x"c5";
when "01" & x"d44" => data <= x"2c";
when "01" & x"d45" => data <= x"d0";
when "01" & x"d46" => data <= x"d6";
when "01" & x"d47" => data <= x"a8";
when "01" & x"d48" => data <= x"f0";
when "01" & x"d49" => data <= x"04";
when "01" & x"d4a" => data <= x"c9";
when "01" & x"d4b" => data <= x"ff";
when "01" & x"d4c" => data <= x"d0";
when "01" & x"d4d" => data <= x"cf";
when "01" & x"d4e" => data <= x"45";
when "01" & x"d4f" => data <= x"2b";
when "01" & x"d50" => data <= x"30";
when "01" & x"d51" => data <= x"cb";
when "01" & x"d52" => data <= x"20";
when "01" & x"d53" => data <= x"1d";
when "01" & x"d54" => data <= x"9e";
when "01" & x"d55" => data <= x"86";
when "01" & x"d56" => data <= x"27";
when "01" & x"d57" => data <= x"a8";
when "01" & x"d58" => data <= x"f0";
when "01" & x"d59" => data <= x"df";
when "01" & x"d5a" => data <= x"30";
when "01" & x"d5b" => data <= x"b5";
when "01" & x"d5c" => data <= x"a5";
when "01" & x"d5d" => data <= x"2d";
when "01" & x"d5e" => data <= x"c5";
when "01" & x"d5f" => data <= x"2c";
when "01" & x"d60" => data <= x"d0";
when "01" & x"d61" => data <= x"ac";
when "01" & x"d62" => data <= x"a8";
when "01" & x"d63" => data <= x"f0";
when "01" & x"d64" => data <= x"04";
when "01" & x"d65" => data <= x"c9";
when "01" & x"d66" => data <= x"ff";
when "01" & x"d67" => data <= x"d0";
when "01" & x"d68" => data <= x"a5";
when "01" & x"d69" => data <= x"45";
when "01" & x"d6a" => data <= x"2b";
when "01" & x"d6b" => data <= x"30";
when "01" & x"d6c" => data <= x"a1";
when "01" & x"d6d" => data <= x"a5";
when "01" & x"d6e" => data <= x"2d";
when "01" & x"d6f" => data <= x"48";
when "01" & x"d70" => data <= x"20";
when "01" & x"d71" => data <= x"71";
when "01" & x"d72" => data <= x"ad";
when "01" & x"d73" => data <= x"a2";
when "01" & x"d74" => data <= x"39";
when "01" & x"d75" => data <= x"20";
when "01" & x"d76" => data <= x"44";
when "01" & x"d77" => data <= x"be";
when "01" & x"d78" => data <= x"20";
when "01" & x"d79" => data <= x"ea";
when "01" & x"d7a" => data <= x"bd";
when "01" & x"d7b" => data <= x"68";
when "01" & x"d7c" => data <= x"45";
when "01" & x"d7d" => data <= x"2d";
when "01" & x"d7e" => data <= x"85";
when "01" & x"d7f" => data <= x"37";
when "01" & x"d80" => data <= x"20";
when "01" & x"d81" => data <= x"71";
when "01" & x"d82" => data <= x"ad";
when "01" & x"d83" => data <= x"a0";
when "01" & x"d84" => data <= x"00";
when "01" & x"d85" => data <= x"a2";
when "01" & x"d86" => data <= x"00";
when "01" & x"d87" => data <= x"84";
when "01" & x"d88" => data <= x"3f";
when "01" & x"d89" => data <= x"84";
when "01" & x"d8a" => data <= x"40";
when "01" & x"d8b" => data <= x"46";
when "01" & x"d8c" => data <= x"3a";
when "01" & x"d8d" => data <= x"66";
when "01" & x"d8e" => data <= x"39";
when "01" & x"d8f" => data <= x"90";
when "01" & x"d90" => data <= x"15";
when "01" & x"d91" => data <= x"18";
when "01" & x"d92" => data <= x"98";
when "01" & x"d93" => data <= x"65";
when "01" & x"d94" => data <= x"2a";
when "01" & x"d95" => data <= x"a8";
when "01" & x"d96" => data <= x"8a";
when "01" & x"d97" => data <= x"65";
when "01" & x"d98" => data <= x"2b";
when "01" & x"d99" => data <= x"aa";
when "01" & x"d9a" => data <= x"a5";
when "01" & x"d9b" => data <= x"3f";
when "01" & x"d9c" => data <= x"65";
when "01" & x"d9d" => data <= x"2c";
when "01" & x"d9e" => data <= x"85";
when "01" & x"d9f" => data <= x"3f";
when "01" & x"da0" => data <= x"a5";
when "01" & x"da1" => data <= x"40";
when "01" & x"da2" => data <= x"65";
when "01" & x"da3" => data <= x"2d";
when "01" & x"da4" => data <= x"85";
when "01" & x"da5" => data <= x"40";
when "01" & x"da6" => data <= x"06";
when "01" & x"da7" => data <= x"2a";
when "01" & x"da8" => data <= x"26";
when "01" & x"da9" => data <= x"2b";
when "01" & x"daa" => data <= x"26";
when "01" & x"dab" => data <= x"2c";
when "01" & x"dac" => data <= x"26";
when "01" & x"dad" => data <= x"2d";
when "01" & x"dae" => data <= x"a5";
when "01" & x"daf" => data <= x"39";
when "01" & x"db0" => data <= x"05";
when "01" & x"db1" => data <= x"3a";
when "01" & x"db2" => data <= x"d0";
when "01" & x"db3" => data <= x"d7";
when "01" & x"db4" => data <= x"84";
when "01" & x"db5" => data <= x"3d";
when "01" & x"db6" => data <= x"86";
when "01" & x"db7" => data <= x"3e";
when "01" & x"db8" => data <= x"a5";
when "01" & x"db9" => data <= x"37";
when "01" & x"dba" => data <= x"08";
when "01" & x"dbb" => data <= x"a2";
when "01" & x"dbc" => data <= x"3d";
when "01" & x"dbd" => data <= x"20";
when "01" & x"dbe" => data <= x"56";
when "01" & x"dbf" => data <= x"af";
when "01" & x"dc0" => data <= x"28";
when "01" & x"dc1" => data <= x"10";
when "01" & x"dc2" => data <= x"03";
when "01" & x"dc3" => data <= x"20";
when "01" & x"dc4" => data <= x"93";
when "01" & x"dc5" => data <= x"ad";
when "01" & x"dc6" => data <= x"a6";
when "01" & x"dc7" => data <= x"27";
when "01" & x"dc8" => data <= x"4c";
when "01" & x"dc9" => data <= x"d4";
when "01" & x"dca" => data <= x"9d";
when "01" & x"dcb" => data <= x"4c";
when "01" & x"dcc" => data <= x"3c";
when "01" & x"dcd" => data <= x"9d";
when "01" & x"dce" => data <= x"20";
when "01" & x"dcf" => data <= x"94";
when "01" & x"dd0" => data <= x"bd";
when "01" & x"dd1" => data <= x"20";
when "01" & x"dd2" => data <= x"20";
when "01" & x"dd3" => data <= x"9e";
when "01" & x"dd4" => data <= x"e0";
when "01" & x"dd5" => data <= x"2a";
when "01" & x"dd6" => data <= x"f0";
when "01" & x"dd7" => data <= x"f3";
when "01" & x"dd8" => data <= x"e0";
when "01" & x"dd9" => data <= x"2f";
when "01" & x"dda" => data <= x"f0";
when "01" & x"ddb" => data <= x"09";
when "01" & x"ddc" => data <= x"e0";
when "01" & x"ddd" => data <= x"83";
when "01" & x"dde" => data <= x"f0";
when "01" & x"ddf" => data <= x"21";
when "01" & x"de0" => data <= x"e0";
when "01" & x"de1" => data <= x"81";
when "01" & x"de2" => data <= x"f0";
when "01" & x"de3" => data <= x"26";
when "01" & x"de4" => data <= x"60";
when "01" & x"de5" => data <= x"a8";
when "01" & x"de6" => data <= x"20";
when "01" & x"de7" => data <= x"fd";
when "01" & x"de8" => data <= x"92";
when "01" & x"de9" => data <= x"20";
when "01" & x"dea" => data <= x"51";
when "01" & x"deb" => data <= x"bd";
when "01" & x"dec" => data <= x"20";
when "01" & x"ded" => data <= x"20";
when "01" & x"dee" => data <= x"9e";
when "01" & x"def" => data <= x"86";
when "01" & x"df0" => data <= x"27";
when "01" & x"df1" => data <= x"a8";
when "01" & x"df2" => data <= x"20";
when "01" & x"df3" => data <= x"fd";
when "01" & x"df4" => data <= x"92";
when "01" & x"df5" => data <= x"20";
when "01" & x"df6" => data <= x"7e";
when "01" & x"df7" => data <= x"bd";
when "01" & x"df8" => data <= x"20";
when "01" & x"df9" => data <= x"ad";
when "01" & x"dfa" => data <= x"a6";
when "01" & x"dfb" => data <= x"a6";
when "01" & x"dfc" => data <= x"27";
when "01" & x"dfd" => data <= x"a9";
when "01" & x"dfe" => data <= x"ff";
when "01" & x"dff" => data <= x"d0";
when "01" & x"e00" => data <= x"d3";
when "01" & x"e01" => data <= x"20";
when "01" & x"e02" => data <= x"be";
when "01" & x"e03" => data <= x"99";
when "01" & x"e04" => data <= x"a5";
when "01" & x"e05" => data <= x"38";
when "01" & x"e06" => data <= x"08";
when "01" & x"e07" => data <= x"4c";
when "01" & x"e08" => data <= x"bb";
when "01" & x"e09" => data <= x"9d";
when "01" & x"e0a" => data <= x"20";
when "01" & x"e0b" => data <= x"be";
when "01" & x"e0c" => data <= x"99";
when "01" & x"e0d" => data <= x"26";
when "01" & x"e0e" => data <= x"39";
when "01" & x"e0f" => data <= x"26";
when "01" & x"e10" => data <= x"3a";
when "01" & x"e11" => data <= x"26";
when "01" & x"e12" => data <= x"3b";
when "01" & x"e13" => data <= x"26";
when "01" & x"e14" => data <= x"3c";
when "01" & x"e15" => data <= x"24";
when "01" & x"e16" => data <= x"37";
when "01" & x"e17" => data <= x"08";
when "01" & x"e18" => data <= x"a2";
when "01" & x"e19" => data <= x"39";
when "01" & x"e1a" => data <= x"4c";
when "01" & x"e1b" => data <= x"bd";
when "01" & x"e1c" => data <= x"9d";
when "01" & x"e1d" => data <= x"20";
when "01" & x"e1e" => data <= x"94";
when "01" & x"e1f" => data <= x"bd";
when "01" & x"e20" => data <= x"20";
when "01" & x"e21" => data <= x"ec";
when "01" & x"e22" => data <= x"ad";
when "01" & x"e23" => data <= x"48";
when "01" & x"e24" => data <= x"a4";
when "01" & x"e25" => data <= x"1b";
when "01" & x"e26" => data <= x"e6";
when "01" & x"e27" => data <= x"1b";
when "01" & x"e28" => data <= x"b1";
when "01" & x"e29" => data <= x"19";
when "01" & x"e2a" => data <= x"c9";
when "01" & x"e2b" => data <= x"20";
when "01" & x"e2c" => data <= x"f0";
when "01" & x"e2d" => data <= x"f6";
when "01" & x"e2e" => data <= x"aa";
when "01" & x"e2f" => data <= x"68";
when "01" & x"e30" => data <= x"e0";
when "01" & x"e31" => data <= x"5e";
when "01" & x"e32" => data <= x"f0";
when "01" & x"e33" => data <= x"01";
when "01" & x"e34" => data <= x"60";
when "01" & x"e35" => data <= x"a8";
when "01" & x"e36" => data <= x"20";
when "01" & x"e37" => data <= x"fd";
when "01" & x"e38" => data <= x"92";
when "01" & x"e39" => data <= x"20";
when "01" & x"e3a" => data <= x"51";
when "01" & x"e3b" => data <= x"bd";
when "01" & x"e3c" => data <= x"20";
when "01" & x"e3d" => data <= x"fa";
when "01" & x"e3e" => data <= x"92";
when "01" & x"e3f" => data <= x"a5";
when "01" & x"e40" => data <= x"30";
when "01" & x"e41" => data <= x"c9";
when "01" & x"e42" => data <= x"87";
when "01" & x"e43" => data <= x"b0";
when "01" & x"e44" => data <= x"43";
when "01" & x"e45" => data <= x"20";
when "01" & x"e46" => data <= x"86";
when "01" & x"e47" => data <= x"a4";
when "01" & x"e48" => data <= x"d0";
when "01" & x"e49" => data <= x"0f";
when "01" & x"e4a" => data <= x"20";
when "01" & x"e4b" => data <= x"7e";
when "01" & x"e4c" => data <= x"bd";
when "01" & x"e4d" => data <= x"20";
when "01" & x"e4e" => data <= x"b5";
when "01" & x"e4f" => data <= x"a3";
when "01" & x"e50" => data <= x"a5";
when "01" & x"e51" => data <= x"4a";
when "01" & x"e52" => data <= x"20";
when "01" & x"e53" => data <= x"12";
when "01" & x"e54" => data <= x"ab";
when "01" & x"e55" => data <= x"a9";
when "01" & x"e56" => data <= x"ff";
when "01" & x"e57" => data <= x"d0";
when "01" & x"e58" => data <= x"ca";
when "01" & x"e59" => data <= x"20";
when "01" & x"e5a" => data <= x"81";
when "01" & x"e5b" => data <= x"a3";
when "01" & x"e5c" => data <= x"a5";
when "01" & x"e5d" => data <= x"04";
when "01" & x"e5e" => data <= x"85";
when "01" & x"e5f" => data <= x"4b";
when "01" & x"e60" => data <= x"a5";
when "01" & x"e61" => data <= x"05";
when "01" & x"e62" => data <= x"85";
when "01" & x"e63" => data <= x"4c";
when "01" & x"e64" => data <= x"20";
when "01" & x"e65" => data <= x"b5";
when "01" & x"e66" => data <= x"a3";
when "01" & x"e67" => data <= x"a5";
when "01" & x"e68" => data <= x"4a";
when "01" & x"e69" => data <= x"20";
when "01" & x"e6a" => data <= x"12";
when "01" & x"e6b" => data <= x"ab";
when "01" & x"e6c" => data <= x"20";
when "01" & x"e6d" => data <= x"7d";
when "01" & x"e6e" => data <= x"a3";
when "01" & x"e6f" => data <= x"20";
when "01" & x"e70" => data <= x"7e";
when "01" & x"e71" => data <= x"bd";
when "01" & x"e72" => data <= x"20";
when "01" & x"e73" => data <= x"b5";
when "01" & x"e74" => data <= x"a3";
when "01" & x"e75" => data <= x"20";
when "01" & x"e76" => data <= x"01";
when "01" & x"e77" => data <= x"a8";
when "01" & x"e78" => data <= x"20";
when "01" & x"e79" => data <= x"d1";
when "01" & x"e7a" => data <= x"aa";
when "01" & x"e7b" => data <= x"20";
when "01" & x"e7c" => data <= x"94";
when "01" & x"e7d" => data <= x"aa";
when "01" & x"e7e" => data <= x"20";
when "01" & x"e7f" => data <= x"ed";
when "01" & x"e80" => data <= x"a7";
when "01" & x"e81" => data <= x"20";
when "01" & x"e82" => data <= x"56";
when "01" & x"e83" => data <= x"a6";
when "01" & x"e84" => data <= x"a9";
when "01" & x"e85" => data <= x"ff";
when "01" & x"e86" => data <= x"d0";
when "01" & x"e87" => data <= x"9b";
when "01" & x"e88" => data <= x"20";
when "01" & x"e89" => data <= x"81";
when "01" & x"e8a" => data <= x"a3";
when "01" & x"e8b" => data <= x"20";
when "01" & x"e8c" => data <= x"99";
when "01" & x"e8d" => data <= x"a6";
when "01" & x"e8e" => data <= x"d0";
when "01" & x"e8f" => data <= x"dc";
when "01" & x"e90" => data <= x"98";
when "01" & x"e91" => data <= x"10";
when "01" & x"e92" => data <= x"03";
when "01" & x"e93" => data <= x"20";
when "01" & x"e94" => data <= x"e4";
when "01" & x"e95" => data <= x"a3";
when "01" & x"e96" => data <= x"a2";
when "01" & x"e97" => data <= x"00";
when "01" & x"e98" => data <= x"a0";
when "01" & x"e99" => data <= x"00";
when "01" & x"e9a" => data <= x"b9";
when "01" & x"e9b" => data <= x"2a";
when "01" & x"e9c" => data <= x"00";
when "01" & x"e9d" => data <= x"48";
when "01" & x"e9e" => data <= x"29";
when "01" & x"e9f" => data <= x"0f";
when "01" & x"ea0" => data <= x"95";
when "01" & x"ea1" => data <= x"3f";
when "01" & x"ea2" => data <= x"68";
when "01" & x"ea3" => data <= x"4a";
when "01" & x"ea4" => data <= x"4a";
when "01" & x"ea5" => data <= x"4a";
when "01" & x"ea6" => data <= x"4a";
when "01" & x"ea7" => data <= x"e8";
when "01" & x"ea8" => data <= x"95";
when "01" & x"ea9" => data <= x"3f";
when "01" & x"eaa" => data <= x"e8";
when "01" & x"eab" => data <= x"c8";
when "01" & x"eac" => data <= x"c0";
when "01" & x"ead" => data <= x"04";
when "01" & x"eae" => data <= x"d0";
when "01" & x"eaf" => data <= x"ea";
when "01" & x"eb0" => data <= x"ca";
when "01" & x"eb1" => data <= x"f0";
when "01" & x"eb2" => data <= x"04";
when "01" & x"eb3" => data <= x"b5";
when "01" & x"eb4" => data <= x"3f";
when "01" & x"eb5" => data <= x"f0";
when "01" & x"eb6" => data <= x"f9";
when "01" & x"eb7" => data <= x"b5";
when "01" & x"eb8" => data <= x"3f";
when "01" & x"eb9" => data <= x"c9";
when "01" & x"eba" => data <= x"0a";
when "01" & x"ebb" => data <= x"90";
when "01" & x"ebc" => data <= x"02";
when "01" & x"ebd" => data <= x"69";
when "01" & x"ebe" => data <= x"06";
when "01" & x"ebf" => data <= x"69";
when "01" & x"ec0" => data <= x"30";
when "01" & x"ec1" => data <= x"20";
when "01" & x"ec2" => data <= x"66";
when "01" & x"ec3" => data <= x"a0";
when "01" & x"ec4" => data <= x"ca";
when "01" & x"ec5" => data <= x"10";
when "01" & x"ec6" => data <= x"f0";
when "01" & x"ec7" => data <= x"60";
when "01" & x"ec8" => data <= x"10";
when "01" & x"ec9" => data <= x"07";
when "01" & x"eca" => data <= x"a9";
when "01" & x"ecb" => data <= x"2d";
when "01" & x"ecc" => data <= x"85";
when "01" & x"ecd" => data <= x"2e";
when "01" & x"ece" => data <= x"20";
when "01" & x"ecf" => data <= x"66";
when "01" & x"ed0" => data <= x"a0";
when "01" & x"ed1" => data <= x"a5";
when "01" & x"ed2" => data <= x"30";
when "01" & x"ed3" => data <= x"c9";
when "01" & x"ed4" => data <= x"81";
when "01" & x"ed5" => data <= x"b0";
when "01" & x"ed6" => data <= x"4e";
when "01" & x"ed7" => data <= x"20";
when "01" & x"ed8" => data <= x"f4";
when "01" & x"ed9" => data <= x"a1";
when "01" & x"eda" => data <= x"c6";
when "01" & x"edb" => data <= x"49";
when "01" & x"edc" => data <= x"4c";
when "01" & x"edd" => data <= x"d1";
when "01" & x"ede" => data <= x"9e";
when "01" & x"edf" => data <= x"ae";
when "01" & x"ee0" => data <= x"02";
when "01" & x"ee1" => data <= x"04";
when "01" & x"ee2" => data <= x"e0";
when "01" & x"ee3" => data <= x"03";
when "01" & x"ee4" => data <= x"90";
when "01" & x"ee5" => data <= x"02";
when "01" & x"ee6" => data <= x"a2";
when "01" & x"ee7" => data <= x"00";
when "01" & x"ee8" => data <= x"86";
when "01" & x"ee9" => data <= x"37";
when "01" & x"eea" => data <= x"ad";
when "01" & x"eeb" => data <= x"01";
when "01" & x"eec" => data <= x"04";
when "01" & x"eed" => data <= x"f0";
when "01" & x"eee" => data <= x"06";
when "01" & x"eef" => data <= x"c9";
when "01" & x"ef0" => data <= x"0a";
when "01" & x"ef1" => data <= x"b0";
when "01" & x"ef2" => data <= x"06";
when "01" & x"ef3" => data <= x"90";
when "01" & x"ef4" => data <= x"06";
when "01" & x"ef5" => data <= x"e0";
when "01" & x"ef6" => data <= x"02";
when "01" & x"ef7" => data <= x"f0";
when "01" & x"ef8" => data <= x"02";
when "01" & x"ef9" => data <= x"a9";
when "01" & x"efa" => data <= x"0a";
when "01" & x"efb" => data <= x"85";
when "01" & x"efc" => data <= x"38";
when "01" & x"efd" => data <= x"85";
when "01" & x"efe" => data <= x"4e";
when "01" & x"eff" => data <= x"a9";
when "01" & x"f00" => data <= x"00";
when "01" & x"f01" => data <= x"85";
when "01" & x"f02" => data <= x"36";
when "01" & x"f03" => data <= x"85";
when "01" & x"f04" => data <= x"49";
when "01" & x"f05" => data <= x"24";
when "01" & x"f06" => data <= x"15";
when "01" & x"f07" => data <= x"30";
when "01" & x"f08" => data <= x"87";
when "01" & x"f09" => data <= x"98";
when "01" & x"f0a" => data <= x"30";
when "01" & x"f0b" => data <= x"03";
when "01" & x"f0c" => data <= x"20";
when "01" & x"f0d" => data <= x"be";
when "01" & x"f0e" => data <= x"a2";
when "01" & x"f0f" => data <= x"20";
when "01" & x"f10" => data <= x"da";
when "01" & x"f11" => data <= x"a1";
when "01" & x"f12" => data <= x"d0";
when "01" & x"f13" => data <= x"b4";
when "01" & x"f14" => data <= x"a5";
when "01" & x"f15" => data <= x"37";
when "01" & x"f16" => data <= x"d0";
when "01" & x"f17" => data <= x"05";
when "01" & x"f18" => data <= x"a9";
when "01" & x"f19" => data <= x"30";
when "01" & x"f1a" => data <= x"4c";
when "01" & x"f1b" => data <= x"66";
when "01" & x"f1c" => data <= x"a0";
when "01" & x"f1d" => data <= x"4c";
when "01" & x"f1e" => data <= x"9c";
when "01" & x"f1f" => data <= x"9f";
when "01" & x"f20" => data <= x"20";
when "01" & x"f21" => data <= x"99";
when "01" & x"f22" => data <= x"a6";
when "01" & x"f23" => data <= x"d0";
when "01" & x"f24" => data <= x"0f";
when "01" & x"f25" => data <= x"c9";
when "01" & x"f26" => data <= x"84";
when "01" & x"f27" => data <= x"90";
when "01" & x"f28" => data <= x"10";
when "01" & x"f29" => data <= x"d0";
when "01" & x"f2a" => data <= x"06";
when "01" & x"f2b" => data <= x"a5";
when "01" & x"f2c" => data <= x"31";
when "01" & x"f2d" => data <= x"c9";
when "01" & x"f2e" => data <= x"a0";
when "01" & x"f2f" => data <= x"90";
when "01" & x"f30" => data <= x"08";
when "01" & x"f31" => data <= x"20";
when "01" & x"f32" => data <= x"4d";
when "01" & x"f33" => data <= x"a2";
when "01" & x"f34" => data <= x"e6";
when "01" & x"f35" => data <= x"49";
when "01" & x"f36" => data <= x"4c";
when "01" & x"f37" => data <= x"d1";
when "01" & x"f38" => data <= x"9e";
when "01" & x"f39" => data <= x"a5";
when "01" & x"f3a" => data <= x"35";
when "01" & x"f3b" => data <= x"85";
when "01" & x"f3c" => data <= x"27";
when "01" & x"f3d" => data <= x"20";
when "01" & x"f3e" => data <= x"85";
when "01" & x"f3f" => data <= x"a3";
when "01" & x"f40" => data <= x"a5";
when "01" & x"f41" => data <= x"4e";
when "01" & x"f42" => data <= x"85";
when "01" & x"f43" => data <= x"38";
when "01" & x"f44" => data <= x"a6";
when "01" & x"f45" => data <= x"37";
when "01" & x"f46" => data <= x"e0";
when "01" & x"f47" => data <= x"02";
when "01" & x"f48" => data <= x"d0";
when "01" & x"f49" => data <= x"12";
when "01" & x"f4a" => data <= x"65";
when "01" & x"f4b" => data <= x"49";
when "01" & x"f4c" => data <= x"30";
when "01" & x"f4d" => data <= x"52";
when "01" & x"f4e" => data <= x"85";
when "01" & x"f4f" => data <= x"38";
when "01" & x"f50" => data <= x"c9";
when "01" & x"f51" => data <= x"0b";
when "01" & x"f52" => data <= x"90";
when "01" & x"f53" => data <= x"08";
when "01" & x"f54" => data <= x"a9";
when "01" & x"f55" => data <= x"0a";
when "01" & x"f56" => data <= x"85";
when "01" & x"f57" => data <= x"38";
when "01" & x"f58" => data <= x"a9";
when "01" & x"f59" => data <= x"00";
when "01" & x"f5a" => data <= x"85";
when "01" & x"f5b" => data <= x"37";
when "01" & x"f5c" => data <= x"20";
when "01" & x"f5d" => data <= x"86";
when "01" & x"f5e" => data <= x"a6";
when "01" & x"f5f" => data <= x"a9";
when "01" & x"f60" => data <= x"a0";
when "01" & x"f61" => data <= x"85";
when "01" & x"f62" => data <= x"31";
when "01" & x"f63" => data <= x"a9";
when "01" & x"f64" => data <= x"83";
when "01" & x"f65" => data <= x"85";
when "01" & x"f66" => data <= x"30";
when "01" & x"f67" => data <= x"a6";
when "01" & x"f68" => data <= x"38";
when "01" & x"f69" => data <= x"f0";
when "01" & x"f6a" => data <= x"06";
when "01" & x"f6b" => data <= x"20";
when "01" & x"f6c" => data <= x"4d";
when "01" & x"f6d" => data <= x"a2";
when "01" & x"f6e" => data <= x"ca";
when "01" & x"f6f" => data <= x"d0";
when "01" & x"f70" => data <= x"fa";
when "01" & x"f71" => data <= x"20";
when "01" & x"f72" => data <= x"f5";
when "01" & x"f73" => data <= x"a7";
when "01" & x"f74" => data <= x"20";
when "01" & x"f75" => data <= x"4e";
when "01" & x"f76" => data <= x"a3";
when "01" & x"f77" => data <= x"a5";
when "01" & x"f78" => data <= x"27";
when "01" & x"f79" => data <= x"85";
when "01" & x"f7a" => data <= x"42";
when "01" & x"f7b" => data <= x"20";
when "01" & x"f7c" => data <= x"0b";
when "01" & x"f7d" => data <= x"a5";
when "01" & x"f7e" => data <= x"a5";
when "01" & x"f7f" => data <= x"30";
when "01" & x"f80" => data <= x"c9";
when "01" & x"f81" => data <= x"84";
when "01" & x"f82" => data <= x"b0";
when "01" & x"f83" => data <= x"0e";
when "01" & x"f84" => data <= x"66";
when "01" & x"f85" => data <= x"31";
when "01" & x"f86" => data <= x"66";
when "01" & x"f87" => data <= x"32";
when "01" & x"f88" => data <= x"66";
when "01" & x"f89" => data <= x"33";
when "01" & x"f8a" => data <= x"66";
when "01" & x"f8b" => data <= x"34";
when "01" & x"f8c" => data <= x"66";
when "01" & x"f8d" => data <= x"35";
when "01" & x"f8e" => data <= x"e6";
when "01" & x"f8f" => data <= x"30";
when "01" & x"f90" => data <= x"d0";
when "01" & x"f91" => data <= x"ec";
when "01" & x"f92" => data <= x"a5";
when "01" & x"f93" => data <= x"31";
when "01" & x"f94" => data <= x"c9";
when "01" & x"f95" => data <= x"a0";
when "01" & x"f96" => data <= x"b0";
when "01" & x"f97" => data <= x"88";
when "01" & x"f98" => data <= x"a5";
when "01" & x"f99" => data <= x"38";
when "01" & x"f9a" => data <= x"d0";
when "01" & x"f9b" => data <= x"11";
when "01" & x"f9c" => data <= x"c9";
when "01" & x"f9d" => data <= x"01";
when "01" & x"f9e" => data <= x"f0";
when "01" & x"f9f" => data <= x"46";
when "01" & x"fa0" => data <= x"20";
when "01" & x"fa1" => data <= x"86";
when "01" & x"fa2" => data <= x"a6";
when "01" & x"fa3" => data <= x"a9";
when "01" & x"fa4" => data <= x"00";
when "01" & x"fa5" => data <= x"85";
when "01" & x"fa6" => data <= x"49";
when "01" & x"fa7" => data <= x"a5";
when "01" & x"fa8" => data <= x"4e";
when "01" & x"fa9" => data <= x"85";
when "01" & x"faa" => data <= x"38";
when "01" & x"fab" => data <= x"e6";
when "01" & x"fac" => data <= x"38";
when "01" & x"fad" => data <= x"a9";
when "01" & x"fae" => data <= x"01";
when "01" & x"faf" => data <= x"c5";
when "01" & x"fb0" => data <= x"37";
when "01" & x"fb1" => data <= x"f0";
when "01" & x"fb2" => data <= x"33";
when "01" & x"fb3" => data <= x"a4";
when "01" & x"fb4" => data <= x"49";
when "01" & x"fb5" => data <= x"30";
when "01" & x"fb6" => data <= x"0c";
when "01" & x"fb7" => data <= x"c4";
when "01" & x"fb8" => data <= x"38";
when "01" & x"fb9" => data <= x"b0";
when "01" & x"fba" => data <= x"2b";
when "01" & x"fbb" => data <= x"a9";
when "01" & x"fbc" => data <= x"00";
when "01" & x"fbd" => data <= x"85";
when "01" & x"fbe" => data <= x"49";
when "01" & x"fbf" => data <= x"c8";
when "01" & x"fc0" => data <= x"98";
when "01" & x"fc1" => data <= x"d0";
when "01" & x"fc2" => data <= x"23";
when "01" & x"fc3" => data <= x"a5";
when "01" & x"fc4" => data <= x"37";
when "01" & x"fc5" => data <= x"c9";
when "01" & x"fc6" => data <= x"02";
when "01" & x"fc7" => data <= x"f0";
when "01" & x"fc8" => data <= x"06";
when "01" & x"fc9" => data <= x"a9";
when "01" & x"fca" => data <= x"01";
when "01" & x"fcb" => data <= x"c0";
when "01" & x"fcc" => data <= x"ff";
when "01" & x"fcd" => data <= x"d0";
when "01" & x"fce" => data <= x"17";
when "01" & x"fcf" => data <= x"a9";
when "01" & x"fd0" => data <= x"30";
when "01" & x"fd1" => data <= x"20";
when "01" & x"fd2" => data <= x"66";
when "01" & x"fd3" => data <= x"a0";
when "01" & x"fd4" => data <= x"a9";
when "01" & x"fd5" => data <= x"2e";
when "01" & x"fd6" => data <= x"20";
when "01" & x"fd7" => data <= x"66";
when "01" & x"fd8" => data <= x"a0";
when "01" & x"fd9" => data <= x"a9";
when "01" & x"fda" => data <= x"30";
when "01" & x"fdb" => data <= x"e6";
when "01" & x"fdc" => data <= x"49";
when "01" & x"fdd" => data <= x"f0";
when "01" & x"fde" => data <= x"05";
when "01" & x"fdf" => data <= x"20";
when "01" & x"fe0" => data <= x"66";
when "01" & x"fe1" => data <= x"a0";
when "01" & x"fe2" => data <= x"d0";
when "01" & x"fe3" => data <= x"f7";
when "01" & x"fe4" => data <= x"a9";
when "01" & x"fe5" => data <= x"80";
when "01" & x"fe6" => data <= x"85";
when "01" & x"fe7" => data <= x"4e";
when "01" & x"fe8" => data <= x"20";
when "01" & x"fe9" => data <= x"40";
when "01" & x"fea" => data <= x"a0";
when "01" & x"feb" => data <= x"c6";
when "01" & x"fec" => data <= x"4e";
when "01" & x"fed" => data <= x"d0";
when "01" & x"fee" => data <= x"05";
when "01" & x"fef" => data <= x"a9";
when "01" & x"ff0" => data <= x"2e";
when "01" & x"ff1" => data <= x"20";
when "01" & x"ff2" => data <= x"66";
when "01" & x"ff3" => data <= x"a0";
when "01" & x"ff4" => data <= x"c6";
when "01" & x"ff5" => data <= x"38";
when "01" & x"ff6" => data <= x"d0";
when "01" & x"ff7" => data <= x"f0";
when "01" & x"ff8" => data <= x"a4";
when "01" & x"ff9" => data <= x"37";
when "01" & x"ffa" => data <= x"88";
when "01" & x"ffb" => data <= x"f0";
when "01" & x"ffc" => data <= x"18";
when "01" & x"ffd" => data <= x"88";
when "01" & x"ffe" => data <= x"f0";
when "01" & x"fff" => data <= x"11";
when "10" & x"000" => data <= x"a4";
when "10" & x"001" => data <= x"36";
when "10" & x"002" => data <= x"88";
when "10" & x"003" => data <= x"b9";
when "10" & x"004" => data <= x"00";
when "10" & x"005" => data <= x"06";
when "10" & x"006" => data <= x"c9";
when "10" & x"007" => data <= x"30";
when "10" & x"008" => data <= x"f0";
when "10" & x"009" => data <= x"f8";
when "10" & x"00a" => data <= x"c9";
when "10" & x"00b" => data <= x"2e";
when "10" & x"00c" => data <= x"f0";
when "10" & x"00d" => data <= x"01";
when "10" & x"00e" => data <= x"c8";
when "10" & x"00f" => data <= x"84";
when "10" & x"010" => data <= x"36";
when "10" & x"011" => data <= x"a5";
when "10" & x"012" => data <= x"49";
when "10" & x"013" => data <= x"f0";
when "10" & x"014" => data <= x"2a";
when "10" & x"015" => data <= x"a9";
when "10" & x"016" => data <= x"45";
when "10" & x"017" => data <= x"20";
when "10" & x"018" => data <= x"66";
when "10" & x"019" => data <= x"a0";
when "10" & x"01a" => data <= x"a5";
when "10" & x"01b" => data <= x"49";
when "10" & x"01c" => data <= x"10";
when "10" & x"01d" => data <= x"0a";
when "10" & x"01e" => data <= x"a9";
when "10" & x"01f" => data <= x"2d";
when "10" & x"020" => data <= x"20";
when "10" & x"021" => data <= x"66";
when "10" & x"022" => data <= x"a0";
when "10" & x"023" => data <= x"38";
when "10" & x"024" => data <= x"a9";
when "10" & x"025" => data <= x"00";
when "10" & x"026" => data <= x"e5";
when "10" & x"027" => data <= x"49";
when "10" & x"028" => data <= x"20";
when "10" & x"029" => data <= x"52";
when "10" & x"02a" => data <= x"a0";
when "10" & x"02b" => data <= x"a5";
when "10" & x"02c" => data <= x"37";
when "10" & x"02d" => data <= x"f0";
when "10" & x"02e" => data <= x"10";
when "10" & x"02f" => data <= x"a9";
when "10" & x"030" => data <= x"20";
when "10" & x"031" => data <= x"a4";
when "10" & x"032" => data <= x"49";
when "10" & x"033" => data <= x"30";
when "10" & x"034" => data <= x"03";
when "10" & x"035" => data <= x"20";
when "10" & x"036" => data <= x"66";
when "10" & x"037" => data <= x"a0";
when "10" & x"038" => data <= x"e0";
when "10" & x"039" => data <= x"00";
when "10" & x"03a" => data <= x"d0";
when "10" & x"03b" => data <= x"03";
when "10" & x"03c" => data <= x"4c";
when "10" & x"03d" => data <= x"66";
when "10" & x"03e" => data <= x"a0";
when "10" & x"03f" => data <= x"60";
when "10" & x"040" => data <= x"a5";
when "10" & x"041" => data <= x"31";
when "10" & x"042" => data <= x"4a";
when "10" & x"043" => data <= x"4a";
when "10" & x"044" => data <= x"4a";
when "10" & x"045" => data <= x"4a";
when "10" & x"046" => data <= x"20";
when "10" & x"047" => data <= x"64";
when "10" & x"048" => data <= x"a0";
when "10" & x"049" => data <= x"a5";
when "10" & x"04a" => data <= x"31";
when "10" & x"04b" => data <= x"29";
when "10" & x"04c" => data <= x"0f";
when "10" & x"04d" => data <= x"85";
when "10" & x"04e" => data <= x"31";
when "10" & x"04f" => data <= x"4c";
when "10" & x"050" => data <= x"97";
when "10" & x"051" => data <= x"a1";
when "10" & x"052" => data <= x"a2";
when "10" & x"053" => data <= x"ff";
when "10" & x"054" => data <= x"38";
when "10" & x"055" => data <= x"e8";
when "10" & x"056" => data <= x"e9";
when "10" & x"057" => data <= x"0a";
when "10" & x"058" => data <= x"b0";
when "10" & x"059" => data <= x"fb";
when "10" & x"05a" => data <= x"69";
when "10" & x"05b" => data <= x"0a";
when "10" & x"05c" => data <= x"48";
when "10" & x"05d" => data <= x"8a";
when "10" & x"05e" => data <= x"f0";
when "10" & x"05f" => data <= x"03";
when "10" & x"060" => data <= x"20";
when "10" & x"061" => data <= x"64";
when "10" & x"062" => data <= x"a0";
when "10" & x"063" => data <= x"68";
when "10" & x"064" => data <= x"09";
when "10" & x"065" => data <= x"30";
when "10" & x"066" => data <= x"86";
when "10" & x"067" => data <= x"3b";
when "10" & x"068" => data <= x"a6";
when "10" & x"069" => data <= x"36";
when "10" & x"06a" => data <= x"9d";
when "10" & x"06b" => data <= x"00";
when "10" & x"06c" => data <= x"06";
when "10" & x"06d" => data <= x"a6";
when "10" & x"06e" => data <= x"3b";
when "10" & x"06f" => data <= x"e6";
when "10" & x"070" => data <= x"36";
when "10" & x"071" => data <= x"60";
when "10" & x"072" => data <= x"18";
when "10" & x"073" => data <= x"86";
when "10" & x"074" => data <= x"35";
when "10" & x"075" => data <= x"20";
when "10" & x"076" => data <= x"da";
when "10" & x"077" => data <= x"a1";
when "10" & x"078" => data <= x"a9";
when "10" & x"079" => data <= x"ff";
when "10" & x"07a" => data <= x"60";
when "10" & x"07b" => data <= x"a2";
when "10" & x"07c" => data <= x"00";
when "10" & x"07d" => data <= x"86";
when "10" & x"07e" => data <= x"31";
when "10" & x"07f" => data <= x"86";
when "10" & x"080" => data <= x"32";
when "10" & x"081" => data <= x"86";
when "10" & x"082" => data <= x"33";
when "10" & x"083" => data <= x"86";
when "10" & x"084" => data <= x"34";
when "10" & x"085" => data <= x"86";
when "10" & x"086" => data <= x"35";
when "10" & x"087" => data <= x"86";
when "10" & x"088" => data <= x"48";
when "10" & x"089" => data <= x"86";
when "10" & x"08a" => data <= x"49";
when "10" & x"08b" => data <= x"c9";
when "10" & x"08c" => data <= x"2e";
when "10" & x"08d" => data <= x"f0";
when "10" & x"08e" => data <= x"11";
when "10" & x"08f" => data <= x"c9";
when "10" & x"090" => data <= x"3a";
when "10" & x"091" => data <= x"b0";
when "10" & x"092" => data <= x"df";
when "10" & x"093" => data <= x"e9";
when "10" & x"094" => data <= x"2f";
when "10" & x"095" => data <= x"30";
when "10" & x"096" => data <= x"db";
when "10" & x"097" => data <= x"85";
when "10" & x"098" => data <= x"35";
when "10" & x"099" => data <= x"c8";
when "10" & x"09a" => data <= x"b1";
when "10" & x"09b" => data <= x"19";
when "10" & x"09c" => data <= x"c9";
when "10" & x"09d" => data <= x"2e";
when "10" & x"09e" => data <= x"d0";
when "10" & x"09f" => data <= x"08";
when "10" & x"0a0" => data <= x"a5";
when "10" & x"0a1" => data <= x"48";
when "10" & x"0a2" => data <= x"d0";
when "10" & x"0a3" => data <= x"44";
when "10" & x"0a4" => data <= x"e6";
when "10" & x"0a5" => data <= x"48";
when "10" & x"0a6" => data <= x"d0";
when "10" & x"0a7" => data <= x"f1";
when "10" & x"0a8" => data <= x"c9";
when "10" & x"0a9" => data <= x"45";
when "10" & x"0aa" => data <= x"f0";
when "10" & x"0ab" => data <= x"35";
when "10" & x"0ac" => data <= x"c9";
when "10" & x"0ad" => data <= x"3a";
when "10" & x"0ae" => data <= x"b0";
when "10" & x"0af" => data <= x"38";
when "10" & x"0b0" => data <= x"e9";
when "10" & x"0b1" => data <= x"2f";
when "10" & x"0b2" => data <= x"90";
when "10" & x"0b3" => data <= x"34";
when "10" & x"0b4" => data <= x"a6";
when "10" & x"0b5" => data <= x"31";
when "10" & x"0b6" => data <= x"e0";
when "10" & x"0b7" => data <= x"18";
when "10" & x"0b8" => data <= x"90";
when "10" & x"0b9" => data <= x"08";
when "10" & x"0ba" => data <= x"a6";
when "10" & x"0bb" => data <= x"48";
when "10" & x"0bc" => data <= x"d0";
when "10" & x"0bd" => data <= x"db";
when "10" & x"0be" => data <= x"e6";
when "10" & x"0bf" => data <= x"49";
when "10" & x"0c0" => data <= x"b0";
when "10" & x"0c1" => data <= x"d7";
when "10" & x"0c2" => data <= x"a6";
when "10" & x"0c3" => data <= x"48";
when "10" & x"0c4" => data <= x"f0";
when "10" & x"0c5" => data <= x"02";
when "10" & x"0c6" => data <= x"c6";
when "10" & x"0c7" => data <= x"49";
when "10" & x"0c8" => data <= x"20";
when "10" & x"0c9" => data <= x"97";
when "10" & x"0ca" => data <= x"a1";
when "10" & x"0cb" => data <= x"65";
when "10" & x"0cc" => data <= x"35";
when "10" & x"0cd" => data <= x"85";
when "10" & x"0ce" => data <= x"35";
when "10" & x"0cf" => data <= x"90";
when "10" & x"0d0" => data <= x"c8";
when "10" & x"0d1" => data <= x"e6";
when "10" & x"0d2" => data <= x"34";
when "10" & x"0d3" => data <= x"d0";
when "10" & x"0d4" => data <= x"c4";
when "10" & x"0d5" => data <= x"e6";
when "10" & x"0d6" => data <= x"33";
when "10" & x"0d7" => data <= x"d0";
when "10" & x"0d8" => data <= x"c0";
when "10" & x"0d9" => data <= x"e6";
when "10" & x"0da" => data <= x"32";
when "10" & x"0db" => data <= x"d0";
when "10" & x"0dc" => data <= x"bc";
when "10" & x"0dd" => data <= x"e6";
when "10" & x"0de" => data <= x"31";
when "10" & x"0df" => data <= x"d0";
when "10" & x"0e0" => data <= x"b8";
when "10" & x"0e1" => data <= x"20";
when "10" & x"0e2" => data <= x"40";
when "10" & x"0e3" => data <= x"a1";
when "10" & x"0e4" => data <= x"65";
when "10" & x"0e5" => data <= x"49";
when "10" & x"0e6" => data <= x"85";
when "10" & x"0e7" => data <= x"49";
when "10" & x"0e8" => data <= x"84";
when "10" & x"0e9" => data <= x"1b";
when "10" & x"0ea" => data <= x"a5";
when "10" & x"0eb" => data <= x"49";
when "10" & x"0ec" => data <= x"05";
when "10" & x"0ed" => data <= x"48";
when "10" & x"0ee" => data <= x"f0";
when "10" & x"0ef" => data <= x"2f";
when "10" & x"0f0" => data <= x"20";
when "10" & x"0f1" => data <= x"da";
when "10" & x"0f2" => data <= x"a1";
when "10" & x"0f3" => data <= x"f0";
when "10" & x"0f4" => data <= x"26";
when "10" & x"0f5" => data <= x"a9";
when "10" & x"0f6" => data <= x"a8";
when "10" & x"0f7" => data <= x"85";
when "10" & x"0f8" => data <= x"30";
when "10" & x"0f9" => data <= x"a9";
when "10" & x"0fa" => data <= x"00";
when "10" & x"0fb" => data <= x"85";
when "10" & x"0fc" => data <= x"2f";
when "10" & x"0fd" => data <= x"85";
when "10" & x"0fe" => data <= x"2e";
when "10" & x"0ff" => data <= x"20";
when "10" & x"100" => data <= x"03";
when "10" & x"101" => data <= x"a3";
when "10" & x"102" => data <= x"a5";
when "10" & x"103" => data <= x"49";
when "10" & x"104" => data <= x"30";
when "10" & x"105" => data <= x"0b";
when "10" & x"106" => data <= x"f0";
when "10" & x"107" => data <= x"10";
when "10" & x"108" => data <= x"20";
when "10" & x"109" => data <= x"f4";
when "10" & x"10a" => data <= x"a1";
when "10" & x"10b" => data <= x"c6";
when "10" & x"10c" => data <= x"49";
when "10" & x"10d" => data <= x"d0";
when "10" & x"10e" => data <= x"f9";
when "10" & x"10f" => data <= x"f0";
when "10" & x"110" => data <= x"07";
when "10" & x"111" => data <= x"20";
when "10" & x"112" => data <= x"4d";
when "10" & x"113" => data <= x"a2";
when "10" & x"114" => data <= x"e6";
when "10" & x"115" => data <= x"49";
when "10" & x"116" => data <= x"d0";
when "10" & x"117" => data <= x"f9";
when "10" & x"118" => data <= x"20";
when "10" & x"119" => data <= x"5c";
when "10" & x"11a" => data <= x"a6";
when "10" & x"11b" => data <= x"38";
when "10" & x"11c" => data <= x"a9";
when "10" & x"11d" => data <= x"ff";
when "10" & x"11e" => data <= x"60";
when "10" & x"11f" => data <= x"a5";
when "10" & x"120" => data <= x"32";
when "10" & x"121" => data <= x"85";
when "10" & x"122" => data <= x"2d";
when "10" & x"123" => data <= x"29";
when "10" & x"124" => data <= x"80";
when "10" & x"125" => data <= x"05";
when "10" & x"126" => data <= x"31";
when "10" & x"127" => data <= x"d0";
when "10" & x"128" => data <= x"cc";
when "10" & x"129" => data <= x"a5";
when "10" & x"12a" => data <= x"35";
when "10" & x"12b" => data <= x"85";
when "10" & x"12c" => data <= x"2a";
when "10" & x"12d" => data <= x"a5";
when "10" & x"12e" => data <= x"34";
when "10" & x"12f" => data <= x"85";
when "10" & x"130" => data <= x"2b";
when "10" & x"131" => data <= x"a5";
when "10" & x"132" => data <= x"33";
when "10" & x"133" => data <= x"85";
when "10" & x"134" => data <= x"2c";
when "10" & x"135" => data <= x"a9";
when "10" & x"136" => data <= x"40";
when "10" & x"137" => data <= x"38";
when "10" & x"138" => data <= x"60";
when "10" & x"139" => data <= x"20";
when "10" & x"13a" => data <= x"4b";
when "10" & x"13b" => data <= x"a1";
when "10" & x"13c" => data <= x"49";
when "10" & x"13d" => data <= x"ff";
when "10" & x"13e" => data <= x"38";
when "10" & x"13f" => data <= x"60";
when "10" & x"140" => data <= x"c8";
when "10" & x"141" => data <= x"b1";
when "10" & x"142" => data <= x"19";
when "10" & x"143" => data <= x"c9";
when "10" & x"144" => data <= x"2d";
when "10" & x"145" => data <= x"f0";
when "10" & x"146" => data <= x"f2";
when "10" & x"147" => data <= x"c9";
when "10" & x"148" => data <= x"2b";
when "10" & x"149" => data <= x"d0";
when "10" & x"14a" => data <= x"03";
when "10" & x"14b" => data <= x"c8";
when "10" & x"14c" => data <= x"b1";
when "10" & x"14d" => data <= x"19";
when "10" & x"14e" => data <= x"c9";
when "10" & x"14f" => data <= x"3a";
when "10" & x"150" => data <= x"b0";
when "10" & x"151" => data <= x"22";
when "10" & x"152" => data <= x"e9";
when "10" & x"153" => data <= x"2f";
when "10" & x"154" => data <= x"90";
when "10" & x"155" => data <= x"1e";
when "10" & x"156" => data <= x"85";
when "10" & x"157" => data <= x"4a";
when "10" & x"158" => data <= x"c8";
when "10" & x"159" => data <= x"b1";
when "10" & x"15a" => data <= x"19";
when "10" & x"15b" => data <= x"c9";
when "10" & x"15c" => data <= x"3a";
when "10" & x"15d" => data <= x"b0";
when "10" & x"15e" => data <= x"11";
when "10" & x"15f" => data <= x"e9";
when "10" & x"160" => data <= x"2f";
when "10" & x"161" => data <= x"90";
when "10" & x"162" => data <= x"0d";
when "10" & x"163" => data <= x"c8";
when "10" & x"164" => data <= x"85";
when "10" & x"165" => data <= x"43";
when "10" & x"166" => data <= x"a5";
when "10" & x"167" => data <= x"4a";
when "10" & x"168" => data <= x"0a";
when "10" & x"169" => data <= x"0a";
when "10" & x"16a" => data <= x"65";
when "10" & x"16b" => data <= x"4a";
when "10" & x"16c" => data <= x"0a";
when "10" & x"16d" => data <= x"65";
when "10" & x"16e" => data <= x"43";
when "10" & x"16f" => data <= x"60";
when "10" & x"170" => data <= x"a5";
when "10" & x"171" => data <= x"4a";
when "10" & x"172" => data <= x"18";
when "10" & x"173" => data <= x"60";
when "10" & x"174" => data <= x"a9";
when "10" & x"175" => data <= x"00";
when "10" & x"176" => data <= x"18";
when "10" & x"177" => data <= x"60";
when "10" & x"178" => data <= x"a5";
when "10" & x"179" => data <= x"35";
when "10" & x"17a" => data <= x"65";
when "10" & x"17b" => data <= x"42";
when "10" & x"17c" => data <= x"85";
when "10" & x"17d" => data <= x"35";
when "10" & x"17e" => data <= x"a5";
when "10" & x"17f" => data <= x"34";
when "10" & x"180" => data <= x"65";
when "10" & x"181" => data <= x"41";
when "10" & x"182" => data <= x"85";
when "10" & x"183" => data <= x"34";
when "10" & x"184" => data <= x"a5";
when "10" & x"185" => data <= x"33";
when "10" & x"186" => data <= x"65";
when "10" & x"187" => data <= x"40";
when "10" & x"188" => data <= x"85";
when "10" & x"189" => data <= x"33";
when "10" & x"18a" => data <= x"a5";
when "10" & x"18b" => data <= x"32";
when "10" & x"18c" => data <= x"65";
when "10" & x"18d" => data <= x"3f";
when "10" & x"18e" => data <= x"85";
when "10" & x"18f" => data <= x"32";
when "10" & x"190" => data <= x"a5";
when "10" & x"191" => data <= x"31";
when "10" & x"192" => data <= x"65";
when "10" & x"193" => data <= x"3e";
when "10" & x"194" => data <= x"85";
when "10" & x"195" => data <= x"31";
when "10" & x"196" => data <= x"60";
when "10" & x"197" => data <= x"48";
when "10" & x"198" => data <= x"a6";
when "10" & x"199" => data <= x"34";
when "10" & x"19a" => data <= x"a5";
when "10" & x"19b" => data <= x"31";
when "10" & x"19c" => data <= x"48";
when "10" & x"19d" => data <= x"a5";
when "10" & x"19e" => data <= x"32";
when "10" & x"19f" => data <= x"48";
when "10" & x"1a0" => data <= x"a5";
when "10" & x"1a1" => data <= x"33";
when "10" & x"1a2" => data <= x"48";
when "10" & x"1a3" => data <= x"a5";
when "10" & x"1a4" => data <= x"35";
when "10" & x"1a5" => data <= x"0a";
when "10" & x"1a6" => data <= x"26";
when "10" & x"1a7" => data <= x"34";
when "10" & x"1a8" => data <= x"26";
when "10" & x"1a9" => data <= x"33";
when "10" & x"1aa" => data <= x"26";
when "10" & x"1ab" => data <= x"32";
when "10" & x"1ac" => data <= x"26";
when "10" & x"1ad" => data <= x"31";
when "10" & x"1ae" => data <= x"0a";
when "10" & x"1af" => data <= x"26";
when "10" & x"1b0" => data <= x"34";
when "10" & x"1b1" => data <= x"26";
when "10" & x"1b2" => data <= x"33";
when "10" & x"1b3" => data <= x"26";
when "10" & x"1b4" => data <= x"32";
when "10" & x"1b5" => data <= x"26";
when "10" & x"1b6" => data <= x"31";
when "10" & x"1b7" => data <= x"65";
when "10" & x"1b8" => data <= x"35";
when "10" & x"1b9" => data <= x"85";
when "10" & x"1ba" => data <= x"35";
when "10" & x"1bb" => data <= x"8a";
when "10" & x"1bc" => data <= x"65";
when "10" & x"1bd" => data <= x"34";
when "10" & x"1be" => data <= x"85";
when "10" & x"1bf" => data <= x"34";
when "10" & x"1c0" => data <= x"68";
when "10" & x"1c1" => data <= x"65";
when "10" & x"1c2" => data <= x"33";
when "10" & x"1c3" => data <= x"85";
when "10" & x"1c4" => data <= x"33";
when "10" & x"1c5" => data <= x"68";
when "10" & x"1c6" => data <= x"65";
when "10" & x"1c7" => data <= x"32";
when "10" & x"1c8" => data <= x"85";
when "10" & x"1c9" => data <= x"32";
when "10" & x"1ca" => data <= x"68";
when "10" & x"1cb" => data <= x"65";
when "10" & x"1cc" => data <= x"31";
when "10" & x"1cd" => data <= x"06";
when "10" & x"1ce" => data <= x"35";
when "10" & x"1cf" => data <= x"26";
when "10" & x"1d0" => data <= x"34";
when "10" & x"1d1" => data <= x"26";
when "10" & x"1d2" => data <= x"33";
when "10" & x"1d3" => data <= x"26";
when "10" & x"1d4" => data <= x"32";
when "10" & x"1d5" => data <= x"2a";
when "10" & x"1d6" => data <= x"85";
when "10" & x"1d7" => data <= x"31";
when "10" & x"1d8" => data <= x"68";
when "10" & x"1d9" => data <= x"60";
when "10" & x"1da" => data <= x"a5";
when "10" & x"1db" => data <= x"31";
when "10" & x"1dc" => data <= x"05";
when "10" & x"1dd" => data <= x"32";
when "10" & x"1de" => data <= x"05";
when "10" & x"1df" => data <= x"33";
when "10" & x"1e0" => data <= x"05";
when "10" & x"1e1" => data <= x"34";
when "10" & x"1e2" => data <= x"05";
when "10" & x"1e3" => data <= x"35";
when "10" & x"1e4" => data <= x"f0";
when "10" & x"1e5" => data <= x"07";
when "10" & x"1e6" => data <= x"a5";
when "10" & x"1e7" => data <= x"2e";
when "10" & x"1e8" => data <= x"d0";
when "10" & x"1e9" => data <= x"09";
when "10" & x"1ea" => data <= x"a9";
when "10" & x"1eb" => data <= x"01";
when "10" & x"1ec" => data <= x"60";
when "10" & x"1ed" => data <= x"85";
when "10" & x"1ee" => data <= x"2e";
when "10" & x"1ef" => data <= x"85";
when "10" & x"1f0" => data <= x"30";
when "10" & x"1f1" => data <= x"85";
when "10" & x"1f2" => data <= x"2f";
when "10" & x"1f3" => data <= x"60";
when "10" & x"1f4" => data <= x"18";
when "10" & x"1f5" => data <= x"a5";
when "10" & x"1f6" => data <= x"30";
when "10" & x"1f7" => data <= x"69";
when "10" & x"1f8" => data <= x"03";
when "10" & x"1f9" => data <= x"85";
when "10" & x"1fa" => data <= x"30";
when "10" & x"1fb" => data <= x"90";
when "10" & x"1fc" => data <= x"02";
when "10" & x"1fd" => data <= x"e6";
when "10" & x"1fe" => data <= x"2f";
when "10" & x"1ff" => data <= x"20";
when "10" & x"200" => data <= x"1e";
when "10" & x"201" => data <= x"a2";
when "10" & x"202" => data <= x"20";
when "10" & x"203" => data <= x"42";
when "10" & x"204" => data <= x"a2";
when "10" & x"205" => data <= x"20";
when "10" & x"206" => data <= x"42";
when "10" & x"207" => data <= x"a2";
when "10" & x"208" => data <= x"20";
when "10" & x"209" => data <= x"78";
when "10" & x"20a" => data <= x"a1";
when "10" & x"20b" => data <= x"90";
when "10" & x"20c" => data <= x"10";
when "10" & x"20d" => data <= x"66";
when "10" & x"20e" => data <= x"31";
when "10" & x"20f" => data <= x"66";
when "10" & x"210" => data <= x"32";
when "10" & x"211" => data <= x"66";
when "10" & x"212" => data <= x"33";
when "10" & x"213" => data <= x"66";
when "10" & x"214" => data <= x"34";
when "10" & x"215" => data <= x"66";
when "10" & x"216" => data <= x"35";
when "10" & x"217" => data <= x"e6";
when "10" & x"218" => data <= x"30";
when "10" & x"219" => data <= x"d0";
when "10" & x"21a" => data <= x"02";
when "10" & x"21b" => data <= x"e6";
when "10" & x"21c" => data <= x"2f";
when "10" & x"21d" => data <= x"60";
when "10" & x"21e" => data <= x"a5";
when "10" & x"21f" => data <= x"2e";
when "10" & x"220" => data <= x"85";
when "10" & x"221" => data <= x"3b";
when "10" & x"222" => data <= x"a5";
when "10" & x"223" => data <= x"2f";
when "10" & x"224" => data <= x"85";
when "10" & x"225" => data <= x"3c";
when "10" & x"226" => data <= x"a5";
when "10" & x"227" => data <= x"30";
when "10" & x"228" => data <= x"85";
when "10" & x"229" => data <= x"3d";
when "10" & x"22a" => data <= x"a5";
when "10" & x"22b" => data <= x"31";
when "10" & x"22c" => data <= x"85";
when "10" & x"22d" => data <= x"3e";
when "10" & x"22e" => data <= x"a5";
when "10" & x"22f" => data <= x"32";
when "10" & x"230" => data <= x"85";
when "10" & x"231" => data <= x"3f";
when "10" & x"232" => data <= x"a5";
when "10" & x"233" => data <= x"33";
when "10" & x"234" => data <= x"85";
when "10" & x"235" => data <= x"40";
when "10" & x"236" => data <= x"a5";
when "10" & x"237" => data <= x"34";
when "10" & x"238" => data <= x"85";
when "10" & x"239" => data <= x"41";
when "10" & x"23a" => data <= x"a5";
when "10" & x"23b" => data <= x"35";
when "10" & x"23c" => data <= x"85";
when "10" & x"23d" => data <= x"42";
when "10" & x"23e" => data <= x"60";
when "10" & x"23f" => data <= x"20";
when "10" & x"240" => data <= x"1e";
when "10" & x"241" => data <= x"a2";
when "10" & x"242" => data <= x"46";
when "10" & x"243" => data <= x"3e";
when "10" & x"244" => data <= x"66";
when "10" & x"245" => data <= x"3f";
when "10" & x"246" => data <= x"66";
when "10" & x"247" => data <= x"40";
when "10" & x"248" => data <= x"66";
when "10" & x"249" => data <= x"41";
when "10" & x"24a" => data <= x"66";
when "10" & x"24b" => data <= x"42";
when "10" & x"24c" => data <= x"60";
when "10" & x"24d" => data <= x"38";
when "10" & x"24e" => data <= x"a5";
when "10" & x"24f" => data <= x"30";
when "10" & x"250" => data <= x"e9";
when "10" & x"251" => data <= x"04";
when "10" & x"252" => data <= x"85";
when "10" & x"253" => data <= x"30";
when "10" & x"254" => data <= x"b0";
when "10" & x"255" => data <= x"02";
when "10" & x"256" => data <= x"c6";
when "10" & x"257" => data <= x"2f";
when "10" & x"258" => data <= x"20";
when "10" & x"259" => data <= x"3f";
when "10" & x"25a" => data <= x"a2";
when "10" & x"25b" => data <= x"20";
when "10" & x"25c" => data <= x"08";
when "10" & x"25d" => data <= x"a2";
when "10" & x"25e" => data <= x"20";
when "10" & x"25f" => data <= x"3f";
when "10" & x"260" => data <= x"a2";
when "10" & x"261" => data <= x"20";
when "10" & x"262" => data <= x"42";
when "10" & x"263" => data <= x"a2";
when "10" & x"264" => data <= x"20";
when "10" & x"265" => data <= x"42";
when "10" & x"266" => data <= x"a2";
when "10" & x"267" => data <= x"20";
when "10" & x"268" => data <= x"42";
when "10" & x"269" => data <= x"a2";
when "10" & x"26a" => data <= x"20";
when "10" & x"26b" => data <= x"08";
when "10" & x"26c" => data <= x"a2";
when "10" & x"26d" => data <= x"a9";
when "10" & x"26e" => data <= x"00";
when "10" & x"26f" => data <= x"85";
when "10" & x"270" => data <= x"3e";
when "10" & x"271" => data <= x"a5";
when "10" & x"272" => data <= x"31";
when "10" & x"273" => data <= x"85";
when "10" & x"274" => data <= x"3f";
when "10" & x"275" => data <= x"a5";
when "10" & x"276" => data <= x"32";
when "10" & x"277" => data <= x"85";
when "10" & x"278" => data <= x"40";
when "10" & x"279" => data <= x"a5";
when "10" & x"27a" => data <= x"33";
when "10" & x"27b" => data <= x"85";
when "10" & x"27c" => data <= x"41";
when "10" & x"27d" => data <= x"a5";
when "10" & x"27e" => data <= x"34";
when "10" & x"27f" => data <= x"85";
when "10" & x"280" => data <= x"42";
when "10" & x"281" => data <= x"a5";
when "10" & x"282" => data <= x"35";
when "10" & x"283" => data <= x"2a";
when "10" & x"284" => data <= x"20";
when "10" & x"285" => data <= x"08";
when "10" & x"286" => data <= x"a2";
when "10" & x"287" => data <= x"a9";
when "10" & x"288" => data <= x"00";
when "10" & x"289" => data <= x"85";
when "10" & x"28a" => data <= x"3e";
when "10" & x"28b" => data <= x"85";
when "10" & x"28c" => data <= x"3f";
when "10" & x"28d" => data <= x"a5";
when "10" & x"28e" => data <= x"31";
when "10" & x"28f" => data <= x"85";
when "10" & x"290" => data <= x"40";
when "10" & x"291" => data <= x"a5";
when "10" & x"292" => data <= x"32";
when "10" & x"293" => data <= x"85";
when "10" & x"294" => data <= x"41";
when "10" & x"295" => data <= x"a5";
when "10" & x"296" => data <= x"33";
when "10" & x"297" => data <= x"85";
when "10" & x"298" => data <= x"42";
when "10" & x"299" => data <= x"a5";
when "10" & x"29a" => data <= x"34";
when "10" & x"29b" => data <= x"2a";
when "10" & x"29c" => data <= x"20";
when "10" & x"29d" => data <= x"08";
when "10" & x"29e" => data <= x"a2";
when "10" & x"29f" => data <= x"a5";
when "10" & x"2a0" => data <= x"32";
when "10" & x"2a1" => data <= x"2a";
when "10" & x"2a2" => data <= x"a5";
when "10" & x"2a3" => data <= x"31";
when "10" & x"2a4" => data <= x"65";
when "10" & x"2a5" => data <= x"35";
when "10" & x"2a6" => data <= x"85";
when "10" & x"2a7" => data <= x"35";
when "10" & x"2a8" => data <= x"90";
when "10" & x"2a9" => data <= x"13";
when "10" & x"2aa" => data <= x"e6";
when "10" & x"2ab" => data <= x"34";
when "10" & x"2ac" => data <= x"d0";
when "10" & x"2ad" => data <= x"0f";
when "10" & x"2ae" => data <= x"e6";
when "10" & x"2af" => data <= x"33";
when "10" & x"2b0" => data <= x"d0";
when "10" & x"2b1" => data <= x"0b";
when "10" & x"2b2" => data <= x"e6";
when "10" & x"2b3" => data <= x"32";
when "10" & x"2b4" => data <= x"d0";
when "10" & x"2b5" => data <= x"07";
when "10" & x"2b6" => data <= x"e6";
when "10" & x"2b7" => data <= x"31";
when "10" & x"2b8" => data <= x"d0";
when "10" & x"2b9" => data <= x"03";
when "10" & x"2ba" => data <= x"4c";
when "10" & x"2bb" => data <= x"0b";
when "10" & x"2bc" => data <= x"a2";
when "10" & x"2bd" => data <= x"60";
when "10" & x"2be" => data <= x"a2";
when "10" & x"2bf" => data <= x"00";
when "10" & x"2c0" => data <= x"86";
when "10" & x"2c1" => data <= x"35";
when "10" & x"2c2" => data <= x"86";
when "10" & x"2c3" => data <= x"2f";
when "10" & x"2c4" => data <= x"a5";
when "10" & x"2c5" => data <= x"2d";
when "10" & x"2c6" => data <= x"10";
when "10" & x"2c7" => data <= x"05";
when "10" & x"2c8" => data <= x"20";
when "10" & x"2c9" => data <= x"93";
when "10" & x"2ca" => data <= x"ad";
when "10" & x"2cb" => data <= x"a2";
when "10" & x"2cc" => data <= x"ff";
when "10" & x"2cd" => data <= x"86";
when "10" & x"2ce" => data <= x"2e";
when "10" & x"2cf" => data <= x"a5";
when "10" & x"2d0" => data <= x"2a";
when "10" & x"2d1" => data <= x"85";
when "10" & x"2d2" => data <= x"34";
when "10" & x"2d3" => data <= x"a5";
when "10" & x"2d4" => data <= x"2b";
when "10" & x"2d5" => data <= x"85";
when "10" & x"2d6" => data <= x"33";
when "10" & x"2d7" => data <= x"a5";
when "10" & x"2d8" => data <= x"2c";
when "10" & x"2d9" => data <= x"85";
when "10" & x"2da" => data <= x"32";
when "10" & x"2db" => data <= x"a5";
when "10" & x"2dc" => data <= x"2d";
when "10" & x"2dd" => data <= x"85";
when "10" & x"2de" => data <= x"31";
when "10" & x"2df" => data <= x"a9";
when "10" & x"2e0" => data <= x"a0";
when "10" & x"2e1" => data <= x"85";
when "10" & x"2e2" => data <= x"30";
when "10" & x"2e3" => data <= x"4c";
when "10" & x"2e4" => data <= x"03";
when "10" & x"2e5" => data <= x"a3";
when "10" & x"2e6" => data <= x"85";
when "10" & x"2e7" => data <= x"2e";
when "10" & x"2e8" => data <= x"85";
when "10" & x"2e9" => data <= x"30";
when "10" & x"2ea" => data <= x"85";
when "10" & x"2eb" => data <= x"2f";
when "10" & x"2ec" => data <= x"60";
when "10" & x"2ed" => data <= x"48";
when "10" & x"2ee" => data <= x"20";
when "10" & x"2ef" => data <= x"86";
when "10" & x"2f0" => data <= x"a6";
when "10" & x"2f1" => data <= x"68";
when "10" & x"2f2" => data <= x"f0";
when "10" & x"2f3" => data <= x"f8";
when "10" & x"2f4" => data <= x"10";
when "10" & x"2f5" => data <= x"07";
when "10" & x"2f6" => data <= x"85";
when "10" & x"2f7" => data <= x"2e";
when "10" & x"2f8" => data <= x"a9";
when "10" & x"2f9" => data <= x"00";
when "10" & x"2fa" => data <= x"38";
when "10" & x"2fb" => data <= x"e5";
when "10" & x"2fc" => data <= x"2e";
when "10" & x"2fd" => data <= x"85";
when "10" & x"2fe" => data <= x"31";
when "10" & x"2ff" => data <= x"a9";
when "10" & x"300" => data <= x"88";
when "10" & x"301" => data <= x"85";
when "10" & x"302" => data <= x"30";
when "10" & x"303" => data <= x"a5";
when "10" & x"304" => data <= x"31";
when "10" & x"305" => data <= x"30";
when "10" & x"306" => data <= x"e5";
when "10" & x"307" => data <= x"05";
when "10" & x"308" => data <= x"32";
when "10" & x"309" => data <= x"05";
when "10" & x"30a" => data <= x"33";
when "10" & x"30b" => data <= x"05";
when "10" & x"30c" => data <= x"34";
when "10" & x"30d" => data <= x"05";
when "10" & x"30e" => data <= x"35";
when "10" & x"30f" => data <= x"f0";
when "10" & x"310" => data <= x"d5";
when "10" & x"311" => data <= x"a5";
when "10" & x"312" => data <= x"30";
when "10" & x"313" => data <= x"a4";
when "10" & x"314" => data <= x"31";
when "10" & x"315" => data <= x"30";
when "10" & x"316" => data <= x"d5";
when "10" & x"317" => data <= x"d0";
when "10" & x"318" => data <= x"21";
when "10" & x"319" => data <= x"a6";
when "10" & x"31a" => data <= x"32";
when "10" & x"31b" => data <= x"86";
when "10" & x"31c" => data <= x"31";
when "10" & x"31d" => data <= x"a6";
when "10" & x"31e" => data <= x"33";
when "10" & x"31f" => data <= x"86";
when "10" & x"320" => data <= x"32";
when "10" & x"321" => data <= x"a6";
when "10" & x"322" => data <= x"34";
when "10" & x"323" => data <= x"86";
when "10" & x"324" => data <= x"33";
when "10" & x"325" => data <= x"a6";
when "10" & x"326" => data <= x"35";
when "10" & x"327" => data <= x"86";
when "10" & x"328" => data <= x"34";
when "10" & x"329" => data <= x"84";
when "10" & x"32a" => data <= x"35";
when "10" & x"32b" => data <= x"38";
when "10" & x"32c" => data <= x"e9";
when "10" & x"32d" => data <= x"08";
when "10" & x"32e" => data <= x"85";
when "10" & x"32f" => data <= x"30";
when "10" & x"330" => data <= x"b0";
when "10" & x"331" => data <= x"e1";
when "10" & x"332" => data <= x"c6";
when "10" & x"333" => data <= x"2f";
when "10" & x"334" => data <= x"90";
when "10" & x"335" => data <= x"dd";
when "10" & x"336" => data <= x"a4";
when "10" & x"337" => data <= x"31";
when "10" & x"338" => data <= x"30";
when "10" & x"339" => data <= x"b2";
when "10" & x"33a" => data <= x"06";
when "10" & x"33b" => data <= x"35";
when "10" & x"33c" => data <= x"26";
when "10" & x"33d" => data <= x"34";
when "10" & x"33e" => data <= x"26";
when "10" & x"33f" => data <= x"33";
when "10" & x"340" => data <= x"26";
when "10" & x"341" => data <= x"32";
when "10" & x"342" => data <= x"26";
when "10" & x"343" => data <= x"31";
when "10" & x"344" => data <= x"e9";
when "10" & x"345" => data <= x"00";
when "10" & x"346" => data <= x"85";
when "10" & x"347" => data <= x"30";
when "10" & x"348" => data <= x"b0";
when "10" & x"349" => data <= x"ec";
when "10" & x"34a" => data <= x"c6";
when "10" & x"34b" => data <= x"2f";
when "10" & x"34c" => data <= x"90";
when "10" & x"34d" => data <= x"e8";
when "10" & x"34e" => data <= x"a0";
when "10" & x"34f" => data <= x"04";
when "10" & x"350" => data <= x"b1";
when "10" & x"351" => data <= x"4b";
when "10" & x"352" => data <= x"85";
when "10" & x"353" => data <= x"41";
when "10" & x"354" => data <= x"88";
when "10" & x"355" => data <= x"b1";
when "10" & x"356" => data <= x"4b";
when "10" & x"357" => data <= x"85";
when "10" & x"358" => data <= x"40";
when "10" & x"359" => data <= x"88";
when "10" & x"35a" => data <= x"b1";
when "10" & x"35b" => data <= x"4b";
when "10" & x"35c" => data <= x"85";
when "10" & x"35d" => data <= x"3f";
when "10" & x"35e" => data <= x"88";
when "10" & x"35f" => data <= x"b1";
when "10" & x"360" => data <= x"4b";
when "10" & x"361" => data <= x"85";
when "10" & x"362" => data <= x"3b";
when "10" & x"363" => data <= x"88";
when "10" & x"364" => data <= x"84";
when "10" & x"365" => data <= x"42";
when "10" & x"366" => data <= x"84";
when "10" & x"367" => data <= x"3c";
when "10" & x"368" => data <= x"b1";
when "10" & x"369" => data <= x"4b";
when "10" & x"36a" => data <= x"85";
when "10" & x"36b" => data <= x"3d";
when "10" & x"36c" => data <= x"05";
when "10" & x"36d" => data <= x"3b";
when "10" & x"36e" => data <= x"05";
when "10" & x"36f" => data <= x"3f";
when "10" & x"370" => data <= x"05";
when "10" & x"371" => data <= x"40";
when "10" & x"372" => data <= x"05";
when "10" & x"373" => data <= x"41";
when "10" & x"374" => data <= x"f0";
when "10" & x"375" => data <= x"04";
when "10" & x"376" => data <= x"a5";
when "10" & x"377" => data <= x"3b";
when "10" & x"378" => data <= x"09";
when "10" & x"379" => data <= x"80";
when "10" & x"37a" => data <= x"85";
when "10" & x"37b" => data <= x"3e";
when "10" & x"37c" => data <= x"60";
when "10" & x"37d" => data <= x"a9";
when "10" & x"37e" => data <= x"71";
when "10" & x"37f" => data <= x"d0";
when "10" & x"380" => data <= x"06";
when "10" & x"381" => data <= x"a9";
when "10" & x"382" => data <= x"76";
when "10" & x"383" => data <= x"d0";
when "10" & x"384" => data <= x"02";
when "10" & x"385" => data <= x"a9";
when "10" & x"386" => data <= x"6c";
when "10" & x"387" => data <= x"85";
when "10" & x"388" => data <= x"4b";
when "10" & x"389" => data <= x"a9";
when "10" & x"38a" => data <= x"04";
when "10" & x"38b" => data <= x"85";
when "10" & x"38c" => data <= x"4c";
when "10" & x"38d" => data <= x"a0";
when "10" & x"38e" => data <= x"00";
when "10" & x"38f" => data <= x"a5";
when "10" & x"390" => data <= x"30";
when "10" & x"391" => data <= x"91";
when "10" & x"392" => data <= x"4b";
when "10" & x"393" => data <= x"c8";
when "10" & x"394" => data <= x"a5";
when "10" & x"395" => data <= x"2e";
when "10" & x"396" => data <= x"29";
when "10" & x"397" => data <= x"80";
when "10" & x"398" => data <= x"85";
when "10" & x"399" => data <= x"2e";
when "10" & x"39a" => data <= x"a5";
when "10" & x"39b" => data <= x"31";
when "10" & x"39c" => data <= x"29";
when "10" & x"39d" => data <= x"7f";
when "10" & x"39e" => data <= x"05";
when "10" & x"39f" => data <= x"2e";
when "10" & x"3a0" => data <= x"91";
when "10" & x"3a1" => data <= x"4b";
when "10" & x"3a2" => data <= x"a5";
when "10" & x"3a3" => data <= x"32";
when "10" & x"3a4" => data <= x"c8";
when "10" & x"3a5" => data <= x"91";
when "10" & x"3a6" => data <= x"4b";
when "10" & x"3a7" => data <= x"a5";
when "10" & x"3a8" => data <= x"33";
when "10" & x"3a9" => data <= x"c8";
when "10" & x"3aa" => data <= x"91";
when "10" & x"3ab" => data <= x"4b";
when "10" & x"3ac" => data <= x"a5";
when "10" & x"3ad" => data <= x"34";
when "10" & x"3ae" => data <= x"c8";
when "10" & x"3af" => data <= x"91";
when "10" & x"3b0" => data <= x"4b";
when "10" & x"3b1" => data <= x"60";
when "10" & x"3b2" => data <= x"20";
when "10" & x"3b3" => data <= x"f5";
when "10" & x"3b4" => data <= x"a7";
when "10" & x"3b5" => data <= x"a0";
when "10" & x"3b6" => data <= x"04";
when "10" & x"3b7" => data <= x"b1";
when "10" & x"3b8" => data <= x"4b";
when "10" & x"3b9" => data <= x"85";
when "10" & x"3ba" => data <= x"34";
when "10" & x"3bb" => data <= x"88";
when "10" & x"3bc" => data <= x"b1";
when "10" & x"3bd" => data <= x"4b";
when "10" & x"3be" => data <= x"85";
when "10" & x"3bf" => data <= x"33";
when "10" & x"3c0" => data <= x"88";
when "10" & x"3c1" => data <= x"b1";
when "10" & x"3c2" => data <= x"4b";
when "10" & x"3c3" => data <= x"85";
when "10" & x"3c4" => data <= x"32";
when "10" & x"3c5" => data <= x"88";
when "10" & x"3c6" => data <= x"b1";
when "10" & x"3c7" => data <= x"4b";
when "10" & x"3c8" => data <= x"85";
when "10" & x"3c9" => data <= x"2e";
when "10" & x"3ca" => data <= x"88";
when "10" & x"3cb" => data <= x"b1";
when "10" & x"3cc" => data <= x"4b";
when "10" & x"3cd" => data <= x"85";
when "10" & x"3ce" => data <= x"30";
when "10" & x"3cf" => data <= x"84";
when "10" & x"3d0" => data <= x"35";
when "10" & x"3d1" => data <= x"84";
when "10" & x"3d2" => data <= x"2f";
when "10" & x"3d3" => data <= x"05";
when "10" & x"3d4" => data <= x"2e";
when "10" & x"3d5" => data <= x"05";
when "10" & x"3d6" => data <= x"32";
when "10" & x"3d7" => data <= x"05";
when "10" & x"3d8" => data <= x"33";
when "10" & x"3d9" => data <= x"05";
when "10" & x"3da" => data <= x"34";
when "10" & x"3db" => data <= x"f0";
when "10" & x"3dc" => data <= x"04";
when "10" & x"3dd" => data <= x"a5";
when "10" & x"3de" => data <= x"2e";
when "10" & x"3df" => data <= x"09";
when "10" & x"3e0" => data <= x"80";
when "10" & x"3e1" => data <= x"85";
when "10" & x"3e2" => data <= x"31";
when "10" & x"3e3" => data <= x"60";
when "10" & x"3e4" => data <= x"20";
when "10" & x"3e5" => data <= x"fe";
when "10" & x"3e6" => data <= x"a3";
when "10" & x"3e7" => data <= x"a5";
when "10" & x"3e8" => data <= x"31";
when "10" & x"3e9" => data <= x"85";
when "10" & x"3ea" => data <= x"2d";
when "10" & x"3eb" => data <= x"a5";
when "10" & x"3ec" => data <= x"32";
when "10" & x"3ed" => data <= x"85";
when "10" & x"3ee" => data <= x"2c";
when "10" & x"3ef" => data <= x"a5";
when "10" & x"3f0" => data <= x"33";
when "10" & x"3f1" => data <= x"85";
when "10" & x"3f2" => data <= x"2b";
when "10" & x"3f3" => data <= x"a5";
when "10" & x"3f4" => data <= x"34";
when "10" & x"3f5" => data <= x"85";
when "10" & x"3f6" => data <= x"2a";
when "10" & x"3f7" => data <= x"60";
when "10" & x"3f8" => data <= x"20";
when "10" & x"3f9" => data <= x"1e";
when "10" & x"3fa" => data <= x"a2";
when "10" & x"3fb" => data <= x"4c";
when "10" & x"3fc" => data <= x"86";
when "10" & x"3fd" => data <= x"a6";
when "10" & x"3fe" => data <= x"a5";
when "10" & x"3ff" => data <= x"30";
when "10" & x"400" => data <= x"10";
when "10" & x"401" => data <= x"f6";
when "10" & x"402" => data <= x"20";
when "10" & x"403" => data <= x"53";
when "10" & x"404" => data <= x"a4";
when "10" & x"405" => data <= x"20";
when "10" & x"406" => data <= x"da";
when "10" & x"407" => data <= x"a1";
when "10" & x"408" => data <= x"d0";
when "10" & x"409" => data <= x"32";
when "10" & x"40a" => data <= x"f0";
when "10" & x"40b" => data <= x"5c";
when "10" & x"40c" => data <= x"a5";
when "10" & x"40d" => data <= x"30";
when "10" & x"40e" => data <= x"c9";
when "10" & x"40f" => data <= x"a0";
when "10" & x"410" => data <= x"b0";
when "10" & x"411" => data <= x"54";
when "10" & x"412" => data <= x"c9";
when "10" & x"413" => data <= x"99";
when "10" & x"414" => data <= x"b0";
when "10" & x"415" => data <= x"26";
when "10" & x"416" => data <= x"69";
when "10" & x"417" => data <= x"08";
when "10" & x"418" => data <= x"85";
when "10" & x"419" => data <= x"30";
when "10" & x"41a" => data <= x"a5";
when "10" & x"41b" => data <= x"40";
when "10" & x"41c" => data <= x"85";
when "10" & x"41d" => data <= x"41";
when "10" & x"41e" => data <= x"a5";
when "10" & x"41f" => data <= x"3f";
when "10" & x"420" => data <= x"85";
when "10" & x"421" => data <= x"40";
when "10" & x"422" => data <= x"a5";
when "10" & x"423" => data <= x"3e";
when "10" & x"424" => data <= x"85";
when "10" & x"425" => data <= x"3f";
when "10" & x"426" => data <= x"a5";
when "10" & x"427" => data <= x"34";
when "10" & x"428" => data <= x"85";
when "10" & x"429" => data <= x"3e";
when "10" & x"42a" => data <= x"a5";
when "10" & x"42b" => data <= x"33";
when "10" & x"42c" => data <= x"85";
when "10" & x"42d" => data <= x"34";
when "10" & x"42e" => data <= x"a5";
when "10" & x"42f" => data <= x"32";
when "10" & x"430" => data <= x"85";
when "10" & x"431" => data <= x"33";
when "10" & x"432" => data <= x"a5";
when "10" & x"433" => data <= x"31";
when "10" & x"434" => data <= x"85";
when "10" & x"435" => data <= x"32";
when "10" & x"436" => data <= x"a9";
when "10" & x"437" => data <= x"00";
when "10" & x"438" => data <= x"85";
when "10" & x"439" => data <= x"31";
when "10" & x"43a" => data <= x"f0";
when "10" & x"43b" => data <= x"d0";
when "10" & x"43c" => data <= x"46";
when "10" & x"43d" => data <= x"31";
when "10" & x"43e" => data <= x"66";
when "10" & x"43f" => data <= x"32";
when "10" & x"440" => data <= x"66";
when "10" & x"441" => data <= x"33";
when "10" & x"442" => data <= x"66";
when "10" & x"443" => data <= x"34";
when "10" & x"444" => data <= x"66";
when "10" & x"445" => data <= x"3e";
when "10" & x"446" => data <= x"66";
when "10" & x"447" => data <= x"3f";
when "10" & x"448" => data <= x"66";
when "10" & x"449" => data <= x"40";
when "10" & x"44a" => data <= x"66";
when "10" & x"44b" => data <= x"41";
when "10" & x"44c" => data <= x"e6";
when "10" & x"44d" => data <= x"30";
when "10" & x"44e" => data <= x"d0";
when "10" & x"44f" => data <= x"bc";
when "10" & x"450" => data <= x"4c";
when "10" & x"451" => data <= x"6c";
when "10" & x"452" => data <= x"a6";
when "10" & x"453" => data <= x"a9";
when "10" & x"454" => data <= x"00";
when "10" & x"455" => data <= x"85";
when "10" & x"456" => data <= x"3b";
when "10" & x"457" => data <= x"85";
when "10" & x"458" => data <= x"3c";
when "10" & x"459" => data <= x"85";
when "10" & x"45a" => data <= x"3d";
when "10" & x"45b" => data <= x"85";
when "10" & x"45c" => data <= x"3e";
when "10" & x"45d" => data <= x"85";
when "10" & x"45e" => data <= x"3f";
when "10" & x"45f" => data <= x"85";
when "10" & x"460" => data <= x"40";
when "10" & x"461" => data <= x"85";
when "10" & x"462" => data <= x"41";
when "10" & x"463" => data <= x"85";
when "10" & x"464" => data <= x"42";
when "10" & x"465" => data <= x"60";
when "10" & x"466" => data <= x"d0";
when "10" & x"467" => data <= x"e8";
when "10" & x"468" => data <= x"a5";
when "10" & x"469" => data <= x"2e";
when "10" & x"46a" => data <= x"10";
when "10" & x"46b" => data <= x"19";
when "10" & x"46c" => data <= x"38";
when "10" & x"46d" => data <= x"a9";
when "10" & x"46e" => data <= x"00";
when "10" & x"46f" => data <= x"e5";
when "10" & x"470" => data <= x"34";
when "10" & x"471" => data <= x"85";
when "10" & x"472" => data <= x"34";
when "10" & x"473" => data <= x"a9";
when "10" & x"474" => data <= x"00";
when "10" & x"475" => data <= x"e5";
when "10" & x"476" => data <= x"33";
when "10" & x"477" => data <= x"85";
when "10" & x"478" => data <= x"33";
when "10" & x"479" => data <= x"a9";
when "10" & x"47a" => data <= x"00";
when "10" & x"47b" => data <= x"e5";
when "10" & x"47c" => data <= x"32";
when "10" & x"47d" => data <= x"85";
when "10" & x"47e" => data <= x"32";
when "10" & x"47f" => data <= x"a9";
when "10" & x"480" => data <= x"00";
when "10" & x"481" => data <= x"e5";
when "10" & x"482" => data <= x"31";
when "10" & x"483" => data <= x"85";
when "10" & x"484" => data <= x"31";
when "10" & x"485" => data <= x"60";
when "10" & x"486" => data <= x"a5";
when "10" & x"487" => data <= x"30";
when "10" & x"488" => data <= x"30";
when "10" & x"489" => data <= x"07";
when "10" & x"48a" => data <= x"a9";
when "10" & x"48b" => data <= x"00";
when "10" & x"48c" => data <= x"85";
when "10" & x"48d" => data <= x"4a";
when "10" & x"48e" => data <= x"4c";
when "10" & x"48f" => data <= x"da";
when "10" & x"490" => data <= x"a1";
when "10" & x"491" => data <= x"20";
when "10" & x"492" => data <= x"fe";
when "10" & x"493" => data <= x"a3";
when "10" & x"494" => data <= x"a5";
when "10" & x"495" => data <= x"34";
when "10" & x"496" => data <= x"85";
when "10" & x"497" => data <= x"4a";
when "10" & x"498" => data <= x"20";
when "10" & x"499" => data <= x"e8";
when "10" & x"49a" => data <= x"a4";
when "10" & x"49b" => data <= x"a9";
when "10" & x"49c" => data <= x"80";
when "10" & x"49d" => data <= x"85";
when "10" & x"49e" => data <= x"30";
when "10" & x"49f" => data <= x"a6";
when "10" & x"4a0" => data <= x"31";
when "10" & x"4a1" => data <= x"10";
when "10" & x"4a2" => data <= x"10";
when "10" & x"4a3" => data <= x"45";
when "10" & x"4a4" => data <= x"2e";
when "10" & x"4a5" => data <= x"85";
when "10" & x"4a6" => data <= x"2e";
when "10" & x"4a7" => data <= x"10";
when "10" & x"4a8" => data <= x"05";
when "10" & x"4a9" => data <= x"e6";
when "10" & x"4aa" => data <= x"4a";
when "10" & x"4ab" => data <= x"4c";
when "10" & x"4ac" => data <= x"b0";
when "10" & x"4ad" => data <= x"a4";
when "10" & x"4ae" => data <= x"c6";
when "10" & x"4af" => data <= x"4a";
when "10" & x"4b0" => data <= x"20";
when "10" & x"4b1" => data <= x"6c";
when "10" & x"4b2" => data <= x"a4";
when "10" & x"4b3" => data <= x"4c";
when "10" & x"4b4" => data <= x"03";
when "10" & x"4b5" => data <= x"a3";
when "10" & x"4b6" => data <= x"e6";
when "10" & x"4b7" => data <= x"34";
when "10" & x"4b8" => data <= x"d0";
when "10" & x"4b9" => data <= x"0c";
when "10" & x"4ba" => data <= x"e6";
when "10" & x"4bb" => data <= x"33";
when "10" & x"4bc" => data <= x"d0";
when "10" & x"4bd" => data <= x"08";
when "10" & x"4be" => data <= x"e6";
when "10" & x"4bf" => data <= x"32";
when "10" & x"4c0" => data <= x"d0";
when "10" & x"4c1" => data <= x"04";
when "10" & x"4c2" => data <= x"e6";
when "10" & x"4c3" => data <= x"31";
when "10" & x"4c4" => data <= x"f0";
when "10" & x"4c5" => data <= x"8a";
when "10" & x"4c6" => data <= x"60";
when "10" & x"4c7" => data <= x"20";
when "10" & x"4c8" => data <= x"6c";
when "10" & x"4c9" => data <= x"a4";
when "10" & x"4ca" => data <= x"20";
when "10" & x"4cb" => data <= x"b6";
when "10" & x"4cc" => data <= x"a4";
when "10" & x"4cd" => data <= x"4c";
when "10" & x"4ce" => data <= x"6c";
when "10" & x"4cf" => data <= x"a4";
when "10" & x"4d0" => data <= x"20";
when "10" & x"4d1" => data <= x"fd";
when "10" & x"4d2" => data <= x"a4";
when "10" & x"4d3" => data <= x"4c";
when "10" & x"4d4" => data <= x"7e";
when "10" & x"4d5" => data <= x"ad";
when "10" & x"4d6" => data <= x"20";
when "10" & x"4d7" => data <= x"4e";
when "10" & x"4d8" => data <= x"a3";
when "10" & x"4d9" => data <= x"20";
when "10" & x"4da" => data <= x"8d";
when "10" & x"4db" => data <= x"a3";
when "10" & x"4dc" => data <= x"a5";
when "10" & x"4dd" => data <= x"3b";
when "10" & x"4de" => data <= x"85";
when "10" & x"4df" => data <= x"2e";
when "10" & x"4e0" => data <= x"a5";
when "10" & x"4e1" => data <= x"3c";
when "10" & x"4e2" => data <= x"85";
when "10" & x"4e3" => data <= x"2f";
when "10" & x"4e4" => data <= x"a5";
when "10" & x"4e5" => data <= x"3d";
when "10" & x"4e6" => data <= x"85";
when "10" & x"4e7" => data <= x"30";
when "10" & x"4e8" => data <= x"a5";
when "10" & x"4e9" => data <= x"3e";
when "10" & x"4ea" => data <= x"85";
when "10" & x"4eb" => data <= x"31";
when "10" & x"4ec" => data <= x"a5";
when "10" & x"4ed" => data <= x"3f";
when "10" & x"4ee" => data <= x"85";
when "10" & x"4ef" => data <= x"32";
when "10" & x"4f0" => data <= x"a5";
when "10" & x"4f1" => data <= x"40";
when "10" & x"4f2" => data <= x"85";
when "10" & x"4f3" => data <= x"33";
when "10" & x"4f4" => data <= x"a5";
when "10" & x"4f5" => data <= x"41";
when "10" & x"4f6" => data <= x"85";
when "10" & x"4f7" => data <= x"34";
when "10" & x"4f8" => data <= x"a5";
when "10" & x"4f9" => data <= x"42";
when "10" & x"4fa" => data <= x"85";
when "10" & x"4fb" => data <= x"35";
when "10" & x"4fc" => data <= x"60";
when "10" & x"4fd" => data <= x"20";
when "10" & x"4fe" => data <= x"7e";
when "10" & x"4ff" => data <= x"ad";
when "10" & x"500" => data <= x"20";
when "10" & x"501" => data <= x"4e";
when "10" & x"502" => data <= x"a3";
when "10" & x"503" => data <= x"f0";
when "10" & x"504" => data <= x"f7";
when "10" & x"505" => data <= x"20";
when "10" & x"506" => data <= x"0b";
when "10" & x"507" => data <= x"a5";
when "10" & x"508" => data <= x"4c";
when "10" & x"509" => data <= x"5c";
when "10" & x"50a" => data <= x"a6";
when "10" & x"50b" => data <= x"20";
when "10" & x"50c" => data <= x"da";
when "10" & x"50d" => data <= x"a1";
when "10" & x"50e" => data <= x"f0";
when "10" & x"50f" => data <= x"cc";
when "10" & x"510" => data <= x"a0";
when "10" & x"511" => data <= x"00";
when "10" & x"512" => data <= x"38";
when "10" & x"513" => data <= x"a5";
when "10" & x"514" => data <= x"30";
when "10" & x"515" => data <= x"e5";
when "10" & x"516" => data <= x"3d";
when "10" & x"517" => data <= x"f0";
when "10" & x"518" => data <= x"77";
when "10" & x"519" => data <= x"90";
when "10" & x"51a" => data <= x"37";
when "10" & x"51b" => data <= x"c9";
when "10" & x"51c" => data <= x"25";
when "10" & x"51d" => data <= x"b0";
when "10" & x"51e" => data <= x"dd";
when "10" & x"51f" => data <= x"48";
when "10" & x"520" => data <= x"29";
when "10" & x"521" => data <= x"38";
when "10" & x"522" => data <= x"f0";
when "10" & x"523" => data <= x"19";
when "10" & x"524" => data <= x"4a";
when "10" & x"525" => data <= x"4a";
when "10" & x"526" => data <= x"4a";
when "10" & x"527" => data <= x"aa";
when "10" & x"528" => data <= x"a5";
when "10" & x"529" => data <= x"41";
when "10" & x"52a" => data <= x"85";
when "10" & x"52b" => data <= x"42";
when "10" & x"52c" => data <= x"a5";
when "10" & x"52d" => data <= x"40";
when "10" & x"52e" => data <= x"85";
when "10" & x"52f" => data <= x"41";
when "10" & x"530" => data <= x"a5";
when "10" & x"531" => data <= x"3f";
when "10" & x"532" => data <= x"85";
when "10" & x"533" => data <= x"40";
when "10" & x"534" => data <= x"a5";
when "10" & x"535" => data <= x"3e";
when "10" & x"536" => data <= x"85";
when "10" & x"537" => data <= x"3f";
when "10" & x"538" => data <= x"84";
when "10" & x"539" => data <= x"3e";
when "10" & x"53a" => data <= x"ca";
when "10" & x"53b" => data <= x"d0";
when "10" & x"53c" => data <= x"eb";
when "10" & x"53d" => data <= x"68";
when "10" & x"53e" => data <= x"29";
when "10" & x"53f" => data <= x"07";
when "10" & x"540" => data <= x"f0";
when "10" & x"541" => data <= x"4e";
when "10" & x"542" => data <= x"aa";
when "10" & x"543" => data <= x"46";
when "10" & x"544" => data <= x"3e";
when "10" & x"545" => data <= x"66";
when "10" & x"546" => data <= x"3f";
when "10" & x"547" => data <= x"66";
when "10" & x"548" => data <= x"40";
when "10" & x"549" => data <= x"66";
when "10" & x"54a" => data <= x"41";
when "10" & x"54b" => data <= x"66";
when "10" & x"54c" => data <= x"42";
when "10" & x"54d" => data <= x"ca";
when "10" & x"54e" => data <= x"d0";
when "10" & x"54f" => data <= x"f3";
when "10" & x"550" => data <= x"f0";
when "10" & x"551" => data <= x"3e";
when "10" & x"552" => data <= x"38";
when "10" & x"553" => data <= x"a5";
when "10" & x"554" => data <= x"3d";
when "10" & x"555" => data <= x"e5";
when "10" & x"556" => data <= x"30";
when "10" & x"557" => data <= x"c9";
when "10" & x"558" => data <= x"25";
when "10" & x"559" => data <= x"b0";
when "10" & x"55a" => data <= x"81";
when "10" & x"55b" => data <= x"48";
when "10" & x"55c" => data <= x"29";
when "10" & x"55d" => data <= x"38";
when "10" & x"55e" => data <= x"f0";
when "10" & x"55f" => data <= x"19";
when "10" & x"560" => data <= x"4a";
when "10" & x"561" => data <= x"4a";
when "10" & x"562" => data <= x"4a";
when "10" & x"563" => data <= x"aa";
when "10" & x"564" => data <= x"a5";
when "10" & x"565" => data <= x"34";
when "10" & x"566" => data <= x"85";
when "10" & x"567" => data <= x"35";
when "10" & x"568" => data <= x"a5";
when "10" & x"569" => data <= x"33";
when "10" & x"56a" => data <= x"85";
when "10" & x"56b" => data <= x"34";
when "10" & x"56c" => data <= x"a5";
when "10" & x"56d" => data <= x"32";
when "10" & x"56e" => data <= x"85";
when "10" & x"56f" => data <= x"33";
when "10" & x"570" => data <= x"a5";
when "10" & x"571" => data <= x"31";
when "10" & x"572" => data <= x"85";
when "10" & x"573" => data <= x"32";
when "10" & x"574" => data <= x"84";
when "10" & x"575" => data <= x"31";
when "10" & x"576" => data <= x"ca";
when "10" & x"577" => data <= x"d0";
when "10" & x"578" => data <= x"eb";
when "10" & x"579" => data <= x"68";
when "10" & x"57a" => data <= x"29";
when "10" & x"57b" => data <= x"07";
when "10" & x"57c" => data <= x"f0";
when "10" & x"57d" => data <= x"0e";
when "10" & x"57e" => data <= x"aa";
when "10" & x"57f" => data <= x"46";
when "10" & x"580" => data <= x"31";
when "10" & x"581" => data <= x"66";
when "10" & x"582" => data <= x"32";
when "10" & x"583" => data <= x"66";
when "10" & x"584" => data <= x"33";
when "10" & x"585" => data <= x"66";
when "10" & x"586" => data <= x"34";
when "10" & x"587" => data <= x"66";
when "10" & x"588" => data <= x"35";
when "10" & x"589" => data <= x"ca";
when "10" & x"58a" => data <= x"d0";
when "10" & x"58b" => data <= x"f3";
when "10" & x"58c" => data <= x"a5";
when "10" & x"58d" => data <= x"3d";
when "10" & x"58e" => data <= x"85";
when "10" & x"58f" => data <= x"30";
when "10" & x"590" => data <= x"a5";
when "10" & x"591" => data <= x"2e";
when "10" & x"592" => data <= x"45";
when "10" & x"593" => data <= x"3b";
when "10" & x"594" => data <= x"10";
when "10" & x"595" => data <= x"49";
when "10" & x"596" => data <= x"a5";
when "10" & x"597" => data <= x"31";
when "10" & x"598" => data <= x"c5";
when "10" & x"599" => data <= x"3e";
when "10" & x"59a" => data <= x"d0";
when "10" & x"59b" => data <= x"1b";
when "10" & x"59c" => data <= x"a5";
when "10" & x"59d" => data <= x"32";
when "10" & x"59e" => data <= x"c5";
when "10" & x"59f" => data <= x"3f";
when "10" & x"5a0" => data <= x"d0";
when "10" & x"5a1" => data <= x"15";
when "10" & x"5a2" => data <= x"a5";
when "10" & x"5a3" => data <= x"33";
when "10" & x"5a4" => data <= x"c5";
when "10" & x"5a5" => data <= x"40";
when "10" & x"5a6" => data <= x"d0";
when "10" & x"5a7" => data <= x"0f";
when "10" & x"5a8" => data <= x"a5";
when "10" & x"5a9" => data <= x"34";
when "10" & x"5aa" => data <= x"c5";
when "10" & x"5ab" => data <= x"41";
when "10" & x"5ac" => data <= x"d0";
when "10" & x"5ad" => data <= x"09";
when "10" & x"5ae" => data <= x"a5";
when "10" & x"5af" => data <= x"35";
when "10" & x"5b0" => data <= x"c5";
when "10" & x"5b1" => data <= x"42";
when "10" & x"5b2" => data <= x"d0";
when "10" & x"5b3" => data <= x"03";
when "10" & x"5b4" => data <= x"4c";
when "10" & x"5b5" => data <= x"86";
when "10" & x"5b6" => data <= x"a6";
when "10" & x"5b7" => data <= x"b0";
when "10" & x"5b8" => data <= x"2a";
when "10" & x"5b9" => data <= x"38";
when "10" & x"5ba" => data <= x"a5";
when "10" & x"5bb" => data <= x"42";
when "10" & x"5bc" => data <= x"e5";
when "10" & x"5bd" => data <= x"35";
when "10" & x"5be" => data <= x"85";
when "10" & x"5bf" => data <= x"35";
when "10" & x"5c0" => data <= x"a5";
when "10" & x"5c1" => data <= x"41";
when "10" & x"5c2" => data <= x"e5";
when "10" & x"5c3" => data <= x"34";
when "10" & x"5c4" => data <= x"85";
when "10" & x"5c5" => data <= x"34";
when "10" & x"5c6" => data <= x"a5";
when "10" & x"5c7" => data <= x"40";
when "10" & x"5c8" => data <= x"e5";
when "10" & x"5c9" => data <= x"33";
when "10" & x"5ca" => data <= x"85";
when "10" & x"5cb" => data <= x"33";
when "10" & x"5cc" => data <= x"a5";
when "10" & x"5cd" => data <= x"3f";
when "10" & x"5ce" => data <= x"e5";
when "10" & x"5cf" => data <= x"32";
when "10" & x"5d0" => data <= x"85";
when "10" & x"5d1" => data <= x"32";
when "10" & x"5d2" => data <= x"a5";
when "10" & x"5d3" => data <= x"3e";
when "10" & x"5d4" => data <= x"e5";
when "10" & x"5d5" => data <= x"31";
when "10" & x"5d6" => data <= x"85";
when "10" & x"5d7" => data <= x"31";
when "10" & x"5d8" => data <= x"a5";
when "10" & x"5d9" => data <= x"3b";
when "10" & x"5da" => data <= x"85";
when "10" & x"5db" => data <= x"2e";
when "10" & x"5dc" => data <= x"4c";
when "10" & x"5dd" => data <= x"03";
when "10" & x"5de" => data <= x"a3";
when "10" & x"5df" => data <= x"18";
when "10" & x"5e0" => data <= x"4c";
when "10" & x"5e1" => data <= x"08";
when "10" & x"5e2" => data <= x"a2";
when "10" & x"5e3" => data <= x"38";
when "10" & x"5e4" => data <= x"a5";
when "10" & x"5e5" => data <= x"35";
when "10" & x"5e6" => data <= x"e5";
when "10" & x"5e7" => data <= x"42";
when "10" & x"5e8" => data <= x"85";
when "10" & x"5e9" => data <= x"35";
when "10" & x"5ea" => data <= x"a5";
when "10" & x"5eb" => data <= x"34";
when "10" & x"5ec" => data <= x"e5";
when "10" & x"5ed" => data <= x"41";
when "10" & x"5ee" => data <= x"85";
when "10" & x"5ef" => data <= x"34";
when "10" & x"5f0" => data <= x"a5";
when "10" & x"5f1" => data <= x"33";
when "10" & x"5f2" => data <= x"e5";
when "10" & x"5f3" => data <= x"40";
when "10" & x"5f4" => data <= x"85";
when "10" & x"5f5" => data <= x"33";
when "10" & x"5f6" => data <= x"a5";
when "10" & x"5f7" => data <= x"32";
when "10" & x"5f8" => data <= x"e5";
when "10" & x"5f9" => data <= x"3f";
when "10" & x"5fa" => data <= x"85";
when "10" & x"5fb" => data <= x"32";
when "10" & x"5fc" => data <= x"a5";
when "10" & x"5fd" => data <= x"31";
when "10" & x"5fe" => data <= x"e5";
when "10" & x"5ff" => data <= x"3e";
when "10" & x"600" => data <= x"85";
when "10" & x"601" => data <= x"31";
when "10" & x"602" => data <= x"4c";
when "10" & x"603" => data <= x"03";
when "10" & x"604" => data <= x"a3";
when "10" & x"605" => data <= x"60";
when "10" & x"606" => data <= x"20";
when "10" & x"607" => data <= x"da";
when "10" & x"608" => data <= x"a1";
when "10" & x"609" => data <= x"f0";
when "10" & x"60a" => data <= x"fa";
when "10" & x"60b" => data <= x"20";
when "10" & x"60c" => data <= x"4e";
when "10" & x"60d" => data <= x"a3";
when "10" & x"60e" => data <= x"d0";
when "10" & x"60f" => data <= x"03";
when "10" & x"610" => data <= x"4c";
when "10" & x"611" => data <= x"86";
when "10" & x"612" => data <= x"a6";
when "10" & x"613" => data <= x"18";
when "10" & x"614" => data <= x"a5";
when "10" & x"615" => data <= x"30";
when "10" & x"616" => data <= x"65";
when "10" & x"617" => data <= x"3d";
when "10" & x"618" => data <= x"90";
when "10" & x"619" => data <= x"03";
when "10" & x"61a" => data <= x"e6";
when "10" & x"61b" => data <= x"2f";
when "10" & x"61c" => data <= x"18";
when "10" & x"61d" => data <= x"e9";
when "10" & x"61e" => data <= x"7f";
when "10" & x"61f" => data <= x"85";
when "10" & x"620" => data <= x"30";
when "10" & x"621" => data <= x"b0";
when "10" & x"622" => data <= x"02";
when "10" & x"623" => data <= x"c6";
when "10" & x"624" => data <= x"2f";
when "10" & x"625" => data <= x"a2";
when "10" & x"626" => data <= x"05";
when "10" & x"627" => data <= x"a0";
when "10" & x"628" => data <= x"00";
when "10" & x"629" => data <= x"b5";
when "10" & x"62a" => data <= x"30";
when "10" & x"62b" => data <= x"95";
when "10" & x"62c" => data <= x"42";
when "10" & x"62d" => data <= x"94";
when "10" & x"62e" => data <= x"30";
when "10" & x"62f" => data <= x"ca";
when "10" & x"630" => data <= x"d0";
when "10" & x"631" => data <= x"f7";
when "10" & x"632" => data <= x"a5";
when "10" & x"633" => data <= x"2e";
when "10" & x"634" => data <= x"45";
when "10" & x"635" => data <= x"3b";
when "10" & x"636" => data <= x"85";
when "10" & x"637" => data <= x"2e";
when "10" & x"638" => data <= x"a0";
when "10" & x"639" => data <= x"20";
when "10" & x"63a" => data <= x"46";
when "10" & x"63b" => data <= x"3e";
when "10" & x"63c" => data <= x"66";
when "10" & x"63d" => data <= x"3f";
when "10" & x"63e" => data <= x"66";
when "10" & x"63f" => data <= x"40";
when "10" & x"640" => data <= x"66";
when "10" & x"641" => data <= x"41";
when "10" & x"642" => data <= x"66";
when "10" & x"643" => data <= x"42";
when "10" & x"644" => data <= x"06";
when "10" & x"645" => data <= x"46";
when "10" & x"646" => data <= x"26";
when "10" & x"647" => data <= x"45";
when "10" & x"648" => data <= x"26";
when "10" & x"649" => data <= x"44";
when "10" & x"64a" => data <= x"26";
when "10" & x"64b" => data <= x"43";
when "10" & x"64c" => data <= x"90";
when "10" & x"64d" => data <= x"04";
when "10" & x"64e" => data <= x"18";
when "10" & x"64f" => data <= x"20";
when "10" & x"650" => data <= x"78";
when "10" & x"651" => data <= x"a1";
when "10" & x"652" => data <= x"88";
when "10" & x"653" => data <= x"d0";
when "10" & x"654" => data <= x"e5";
when "10" & x"655" => data <= x"60";
when "10" & x"656" => data <= x"20";
when "10" & x"657" => data <= x"06";
when "10" & x"658" => data <= x"a6";
when "10" & x"659" => data <= x"20";
when "10" & x"65a" => data <= x"03";
when "10" & x"65b" => data <= x"a3";
when "10" & x"65c" => data <= x"a5";
when "10" & x"65d" => data <= x"35";
when "10" & x"65e" => data <= x"c9";
when "10" & x"65f" => data <= x"80";
when "10" & x"660" => data <= x"90";
when "10" & x"661" => data <= x"1a";
when "10" & x"662" => data <= x"f0";
when "10" & x"663" => data <= x"12";
when "10" & x"664" => data <= x"a9";
when "10" & x"665" => data <= x"ff";
when "10" & x"666" => data <= x"20";
when "10" & x"667" => data <= x"a4";
when "10" & x"668" => data <= x"a2";
when "10" & x"669" => data <= x"4c";
when "10" & x"66a" => data <= x"7c";
when "10" & x"66b" => data <= x"a6";
when "10" & x"66c" => data <= x"00";
when "10" & x"66d" => data <= x"14";
when "10" & x"66e" => data <= x"54";
when "10" & x"66f" => data <= x"6f";
when "10" & x"670" => data <= x"6f";
when "10" & x"671" => data <= x"20";
when "10" & x"672" => data <= x"62";
when "10" & x"673" => data <= x"69";
when "10" & x"674" => data <= x"67";
when "10" & x"675" => data <= x"00";
when "10" & x"676" => data <= x"a5";
when "10" & x"677" => data <= x"34";
when "10" & x"678" => data <= x"09";
when "10" & x"679" => data <= x"01";
when "10" & x"67a" => data <= x"85";
when "10" & x"67b" => data <= x"34";
when "10" & x"67c" => data <= x"a9";
when "10" & x"67d" => data <= x"00";
when "10" & x"67e" => data <= x"85";
when "10" & x"67f" => data <= x"35";
when "10" & x"680" => data <= x"a5";
when "10" & x"681" => data <= x"2f";
when "10" & x"682" => data <= x"f0";
when "10" & x"683" => data <= x"14";
when "10" & x"684" => data <= x"10";
when "10" & x"685" => data <= x"e6";
when "10" & x"686" => data <= x"a9";
when "10" & x"687" => data <= x"00";
when "10" & x"688" => data <= x"85";
when "10" & x"689" => data <= x"2e";
when "10" & x"68a" => data <= x"85";
when "10" & x"68b" => data <= x"2f";
when "10" & x"68c" => data <= x"85";
when "10" & x"68d" => data <= x"30";
when "10" & x"68e" => data <= x"85";
when "10" & x"68f" => data <= x"31";
when "10" & x"690" => data <= x"85";
when "10" & x"691" => data <= x"32";
when "10" & x"692" => data <= x"85";
when "10" & x"693" => data <= x"33";
when "10" & x"694" => data <= x"85";
when "10" & x"695" => data <= x"34";
when "10" & x"696" => data <= x"85";
when "10" & x"697" => data <= x"35";
when "10" & x"698" => data <= x"60";
when "10" & x"699" => data <= x"20";
when "10" & x"69a" => data <= x"86";
when "10" & x"69b" => data <= x"a6";
when "10" & x"69c" => data <= x"a0";
when "10" & x"69d" => data <= x"80";
when "10" & x"69e" => data <= x"84";
when "10" & x"69f" => data <= x"31";
when "10" & x"6a0" => data <= x"c8";
when "10" & x"6a1" => data <= x"84";
when "10" & x"6a2" => data <= x"30";
when "10" & x"6a3" => data <= x"98";
when "10" & x"6a4" => data <= x"60";
when "10" & x"6a5" => data <= x"20";
when "10" & x"6a6" => data <= x"85";
when "10" & x"6a7" => data <= x"a3";
when "10" & x"6a8" => data <= x"20";
when "10" & x"6a9" => data <= x"99";
when "10" & x"6aa" => data <= x"a6";
when "10" & x"6ab" => data <= x"d0";
when "10" & x"6ac" => data <= x"3a";
when "10" & x"6ad" => data <= x"20";
when "10" & x"6ae" => data <= x"da";
when "10" & x"6af" => data <= x"a1";
when "10" & x"6b0" => data <= x"f0";
when "10" & x"6b1" => data <= x"09";
when "10" & x"6b2" => data <= x"20";
when "10" & x"6b3" => data <= x"1e";
when "10" & x"6b4" => data <= x"a2";
when "10" & x"6b5" => data <= x"20";
when "10" & x"6b6" => data <= x"b5";
when "10" & x"6b7" => data <= x"a3";
when "10" & x"6b8" => data <= x"d0";
when "10" & x"6b9" => data <= x"37";
when "10" & x"6ba" => data <= x"60";
when "10" & x"6bb" => data <= x"4c";
when "10" & x"6bc" => data <= x"a7";
when "10" & x"6bd" => data <= x"99";
when "10" & x"6be" => data <= x"20";
when "10" & x"6bf" => data <= x"fa";
when "10" & x"6c0" => data <= x"92";
when "10" & x"6c1" => data <= x"20";
when "10" & x"6c2" => data <= x"d3";
when "10" & x"6c3" => data <= x"a9";
when "10" & x"6c4" => data <= x"a5";
when "10" & x"6c5" => data <= x"4a";
when "10" & x"6c6" => data <= x"48";
when "10" & x"6c7" => data <= x"20";
when "10" & x"6c8" => data <= x"e9";
when "10" & x"6c9" => data <= x"a7";
when "10" & x"6ca" => data <= x"20";
when "10" & x"6cb" => data <= x"8d";
when "10" & x"6cc" => data <= x"a3";
when "10" & x"6cd" => data <= x"e6";
when "10" & x"6ce" => data <= x"4a";
when "10" & x"6cf" => data <= x"20";
when "10" & x"6d0" => data <= x"9e";
when "10" & x"6d1" => data <= x"a9";
when "10" & x"6d2" => data <= x"20";
when "10" & x"6d3" => data <= x"e9";
when "10" & x"6d4" => data <= x"a7";
when "10" & x"6d5" => data <= x"20";
when "10" & x"6d6" => data <= x"d6";
when "10" & x"6d7" => data <= x"a4";
when "10" & x"6d8" => data <= x"68";
when "10" & x"6d9" => data <= x"85";
when "10" & x"6da" => data <= x"4a";
when "10" & x"6db" => data <= x"20";
when "10" & x"6dc" => data <= x"9e";
when "10" & x"6dd" => data <= x"a9";
when "10" & x"6de" => data <= x"20";
when "10" & x"6df" => data <= x"e9";
when "10" & x"6e0" => data <= x"a7";
when "10" & x"6e1" => data <= x"20";
when "10" & x"6e2" => data <= x"e7";
when "10" & x"6e3" => data <= x"a6";
when "10" & x"6e4" => data <= x"a9";
when "10" & x"6e5" => data <= x"ff";
when "10" & x"6e6" => data <= x"60";
when "10" & x"6e7" => data <= x"20";
when "10" & x"6e8" => data <= x"da";
when "10" & x"6e9" => data <= x"a1";
when "10" & x"6ea" => data <= x"f0";
when "10" & x"6eb" => data <= x"ac";
when "10" & x"6ec" => data <= x"20";
when "10" & x"6ed" => data <= x"4e";
when "10" & x"6ee" => data <= x"a3";
when "10" & x"6ef" => data <= x"f0";
when "10" & x"6f0" => data <= x"ca";
when "10" & x"6f1" => data <= x"a5";
when "10" & x"6f2" => data <= x"2e";
when "10" & x"6f3" => data <= x"45";
when "10" & x"6f4" => data <= x"3b";
when "10" & x"6f5" => data <= x"85";
when "10" & x"6f6" => data <= x"2e";
when "10" & x"6f7" => data <= x"38";
when "10" & x"6f8" => data <= x"a5";
when "10" & x"6f9" => data <= x"30";
when "10" & x"6fa" => data <= x"e5";
when "10" & x"6fb" => data <= x"3d";
when "10" & x"6fc" => data <= x"b0";
when "10" & x"6fd" => data <= x"03";
when "10" & x"6fe" => data <= x"c6";
when "10" & x"6ff" => data <= x"2f";
when "10" & x"700" => data <= x"38";
when "10" & x"701" => data <= x"69";
when "10" & x"702" => data <= x"80";
when "10" & x"703" => data <= x"85";
when "10" & x"704" => data <= x"30";
when "10" & x"705" => data <= x"90";
when "10" & x"706" => data <= x"03";
when "10" & x"707" => data <= x"e6";
when "10" & x"708" => data <= x"2f";
when "10" & x"709" => data <= x"18";
when "10" & x"70a" => data <= x"a2";
when "10" & x"70b" => data <= x"20";
when "10" & x"70c" => data <= x"b0";
when "10" & x"70d" => data <= x"18";
when "10" & x"70e" => data <= x"a5";
when "10" & x"70f" => data <= x"31";
when "10" & x"710" => data <= x"c5";
when "10" & x"711" => data <= x"3e";
when "10" & x"712" => data <= x"d0";
when "10" & x"713" => data <= x"10";
when "10" & x"714" => data <= x"a5";
when "10" & x"715" => data <= x"32";
when "10" & x"716" => data <= x"c5";
when "10" & x"717" => data <= x"3f";
when "10" & x"718" => data <= x"d0";
when "10" & x"719" => data <= x"0a";
when "10" & x"71a" => data <= x"a5";
when "10" & x"71b" => data <= x"33";
when "10" & x"71c" => data <= x"c5";
when "10" & x"71d" => data <= x"40";
when "10" & x"71e" => data <= x"d0";
when "10" & x"71f" => data <= x"04";
when "10" & x"720" => data <= x"a5";
when "10" & x"721" => data <= x"34";
when "10" & x"722" => data <= x"c5";
when "10" & x"723" => data <= x"41";
when "10" & x"724" => data <= x"90";
when "10" & x"725" => data <= x"19";
when "10" & x"726" => data <= x"a5";
when "10" & x"727" => data <= x"34";
when "10" & x"728" => data <= x"e5";
when "10" & x"729" => data <= x"41";
when "10" & x"72a" => data <= x"85";
when "10" & x"72b" => data <= x"34";
when "10" & x"72c" => data <= x"a5";
when "10" & x"72d" => data <= x"33";
when "10" & x"72e" => data <= x"e5";
when "10" & x"72f" => data <= x"40";
when "10" & x"730" => data <= x"85";
when "10" & x"731" => data <= x"33";
when "10" & x"732" => data <= x"a5";
when "10" & x"733" => data <= x"32";
when "10" & x"734" => data <= x"e5";
when "10" & x"735" => data <= x"3f";
when "10" & x"736" => data <= x"85";
when "10" & x"737" => data <= x"32";
when "10" & x"738" => data <= x"a5";
when "10" & x"739" => data <= x"31";
when "10" & x"73a" => data <= x"e5";
when "10" & x"73b" => data <= x"3e";
when "10" & x"73c" => data <= x"85";
when "10" & x"73d" => data <= x"31";
when "10" & x"73e" => data <= x"38";
when "10" & x"73f" => data <= x"26";
when "10" & x"740" => data <= x"46";
when "10" & x"741" => data <= x"26";
when "10" & x"742" => data <= x"45";
when "10" & x"743" => data <= x"26";
when "10" & x"744" => data <= x"44";
when "10" & x"745" => data <= x"26";
when "10" & x"746" => data <= x"43";
when "10" & x"747" => data <= x"06";
when "10" & x"748" => data <= x"34";
when "10" & x"749" => data <= x"26";
when "10" & x"74a" => data <= x"33";
when "10" & x"74b" => data <= x"26";
when "10" & x"74c" => data <= x"32";
when "10" & x"74d" => data <= x"26";
when "10" & x"74e" => data <= x"31";
when "10" & x"74f" => data <= x"ca";
when "10" & x"750" => data <= x"d0";
when "10" & x"751" => data <= x"ba";
when "10" & x"752" => data <= x"a2";
when "10" & x"753" => data <= x"07";
when "10" & x"754" => data <= x"b0";
when "10" & x"755" => data <= x"18";
when "10" & x"756" => data <= x"a5";
when "10" & x"757" => data <= x"31";
when "10" & x"758" => data <= x"c5";
when "10" & x"759" => data <= x"3e";
when "10" & x"75a" => data <= x"d0";
when "10" & x"75b" => data <= x"10";
when "10" & x"75c" => data <= x"a5";
when "10" & x"75d" => data <= x"32";
when "10" & x"75e" => data <= x"c5";
when "10" & x"75f" => data <= x"3f";
when "10" & x"760" => data <= x"d0";
when "10" & x"761" => data <= x"0a";
when "10" & x"762" => data <= x"a5";
when "10" & x"763" => data <= x"33";
when "10" & x"764" => data <= x"c5";
when "10" & x"765" => data <= x"40";
when "10" & x"766" => data <= x"d0";
when "10" & x"767" => data <= x"04";
when "10" & x"768" => data <= x"a5";
when "10" & x"769" => data <= x"34";
when "10" & x"76a" => data <= x"c5";
when "10" & x"76b" => data <= x"41";
when "10" & x"76c" => data <= x"90";
when "10" & x"76d" => data <= x"19";
when "10" & x"76e" => data <= x"a5";
when "10" & x"76f" => data <= x"34";
when "10" & x"770" => data <= x"e5";
when "10" & x"771" => data <= x"41";
when "10" & x"772" => data <= x"85";
when "10" & x"773" => data <= x"34";
when "10" & x"774" => data <= x"a5";
when "10" & x"775" => data <= x"33";
when "10" & x"776" => data <= x"e5";
when "10" & x"777" => data <= x"40";
when "10" & x"778" => data <= x"85";
when "10" & x"779" => data <= x"33";
when "10" & x"77a" => data <= x"a5";
when "10" & x"77b" => data <= x"32";
when "10" & x"77c" => data <= x"e5";
when "10" & x"77d" => data <= x"3f";
when "10" & x"77e" => data <= x"85";
when "10" & x"77f" => data <= x"32";
when "10" & x"780" => data <= x"a5";
when "10" & x"781" => data <= x"31";
when "10" & x"782" => data <= x"e5";
when "10" & x"783" => data <= x"3e";
when "10" & x"784" => data <= x"85";
when "10" & x"785" => data <= x"31";
when "10" & x"786" => data <= x"38";
when "10" & x"787" => data <= x"26";
when "10" & x"788" => data <= x"35";
when "10" & x"789" => data <= x"06";
when "10" & x"78a" => data <= x"34";
when "10" & x"78b" => data <= x"26";
when "10" & x"78c" => data <= x"33";
when "10" & x"78d" => data <= x"26";
when "10" & x"78e" => data <= x"32";
when "10" & x"78f" => data <= x"26";
when "10" & x"790" => data <= x"31";
when "10" & x"791" => data <= x"ca";
when "10" & x"792" => data <= x"d0";
when "10" & x"793" => data <= x"c0";
when "10" & x"794" => data <= x"06";
when "10" & x"795" => data <= x"35";
when "10" & x"796" => data <= x"a5";
when "10" & x"797" => data <= x"46";
when "10" & x"798" => data <= x"85";
when "10" & x"799" => data <= x"34";
when "10" & x"79a" => data <= x"a5";
when "10" & x"79b" => data <= x"45";
when "10" & x"79c" => data <= x"85";
when "10" & x"79d" => data <= x"33";
when "10" & x"79e" => data <= x"a5";
when "10" & x"79f" => data <= x"44";
when "10" & x"7a0" => data <= x"85";
when "10" & x"7a1" => data <= x"32";
when "10" & x"7a2" => data <= x"a5";
when "10" & x"7a3" => data <= x"43";
when "10" & x"7a4" => data <= x"85";
when "10" & x"7a5" => data <= x"31";
when "10" & x"7a6" => data <= x"4c";
when "10" & x"7a7" => data <= x"59";
when "10" & x"7a8" => data <= x"a6";
when "10" & x"7a9" => data <= x"00";
when "10" & x"7aa" => data <= x"15";
when "10" & x"7ab" => data <= x"2d";
when "10" & x"7ac" => data <= x"76";
when "10" & x"7ad" => data <= x"65";
when "10" & x"7ae" => data <= x"20";
when "10" & x"7af" => data <= x"72";
when "10" & x"7b0" => data <= x"6f";
when "10" & x"7b1" => data <= x"6f";
when "10" & x"7b2" => data <= x"74";
when "10" & x"7b3" => data <= x"00";
when "10" & x"7b4" => data <= x"20";
when "10" & x"7b5" => data <= x"fa";
when "10" & x"7b6" => data <= x"92";
when "10" & x"7b7" => data <= x"20";
when "10" & x"7b8" => data <= x"da";
when "10" & x"7b9" => data <= x"a1";
when "10" & x"7ba" => data <= x"f0";
when "10" & x"7bb" => data <= x"2a";
when "10" & x"7bc" => data <= x"30";
when "10" & x"7bd" => data <= x"eb";
when "10" & x"7be" => data <= x"20";
when "10" & x"7bf" => data <= x"85";
when "10" & x"7c0" => data <= x"a3";
when "10" & x"7c1" => data <= x"a5";
when "10" & x"7c2" => data <= x"30";
when "10" & x"7c3" => data <= x"4a";
when "10" & x"7c4" => data <= x"69";
when "10" & x"7c5" => data <= x"40";
when "10" & x"7c6" => data <= x"85";
when "10" & x"7c7" => data <= x"30";
when "10" & x"7c8" => data <= x"a9";
when "10" & x"7c9" => data <= x"05";
when "10" & x"7ca" => data <= x"85";
when "10" & x"7cb" => data <= x"4a";
when "10" & x"7cc" => data <= x"20";
when "10" & x"7cd" => data <= x"ed";
when "10" & x"7ce" => data <= x"a7";
when "10" & x"7cf" => data <= x"20";
when "10" & x"7d0" => data <= x"8d";
when "10" & x"7d1" => data <= x"a3";
when "10" & x"7d2" => data <= x"a9";
when "10" & x"7d3" => data <= x"6c";
when "10" & x"7d4" => data <= x"85";
when "10" & x"7d5" => data <= x"4b";
when "10" & x"7d6" => data <= x"20";
when "10" & x"7d7" => data <= x"ad";
when "10" & x"7d8" => data <= x"a6";
when "10" & x"7d9" => data <= x"a9";
when "10" & x"7da" => data <= x"71";
when "10" & x"7db" => data <= x"85";
when "10" & x"7dc" => data <= x"4b";
when "10" & x"7dd" => data <= x"20";
when "10" & x"7de" => data <= x"00";
when "10" & x"7df" => data <= x"a5";
when "10" & x"7e0" => data <= x"c6";
when "10" & x"7e1" => data <= x"30";
when "10" & x"7e2" => data <= x"c6";
when "10" & x"7e3" => data <= x"4a";
when "10" & x"7e4" => data <= x"d0";
when "10" & x"7e5" => data <= x"e9";
when "10" & x"7e6" => data <= x"a9";
when "10" & x"7e7" => data <= x"ff";
when "10" & x"7e8" => data <= x"60";
when "10" & x"7e9" => data <= x"a9";
when "10" & x"7ea" => data <= x"7b";
when "10" & x"7eb" => data <= x"d0";
when "10" & x"7ec" => data <= x"0a";
when "10" & x"7ed" => data <= x"a9";
when "10" & x"7ee" => data <= x"71";
when "10" & x"7ef" => data <= x"d0";
when "10" & x"7f0" => data <= x"06";
when "10" & x"7f1" => data <= x"a9";
when "10" & x"7f2" => data <= x"76";
when "10" & x"7f3" => data <= x"d0";
when "10" & x"7f4" => data <= x"02";
when "10" & x"7f5" => data <= x"a9";
when "10" & x"7f6" => data <= x"6c";
when "10" & x"7f7" => data <= x"85";
when "10" & x"7f8" => data <= x"4b";
when "10" & x"7f9" => data <= x"a9";
when "10" & x"7fa" => data <= x"04";
when "10" & x"7fb" => data <= x"85";
when "10" & x"7fc" => data <= x"4c";
when "10" & x"7fd" => data <= x"60";
when "10" & x"7fe" => data <= x"20";
when "10" & x"7ff" => data <= x"fa";
when "10" & x"800" => data <= x"92";
when "10" & x"801" => data <= x"20";
when "10" & x"802" => data <= x"da";
when "10" & x"803" => data <= x"a1";
when "10" & x"804" => data <= x"f0";
when "10" & x"805" => data <= x"02";
when "10" & x"806" => data <= x"10";
when "10" & x"807" => data <= x"0c";
when "10" & x"808" => data <= x"00";
when "10" & x"809" => data <= x"16";
when "10" & x"80a" => data <= x"4c";
when "10" & x"80b" => data <= x"6f";
when "10" & x"80c" => data <= x"67";
when "10" & x"80d" => data <= x"20";
when "10" & x"80e" => data <= x"72";
when "10" & x"80f" => data <= x"61";
when "10" & x"810" => data <= x"6e";
when "10" & x"811" => data <= x"67";
when "10" & x"812" => data <= x"65";
when "10" & x"813" => data <= x"00";
when "10" & x"814" => data <= x"20";
when "10" & x"815" => data <= x"53";
when "10" & x"816" => data <= x"a4";
when "10" & x"817" => data <= x"a0";
when "10" & x"818" => data <= x"80";
when "10" & x"819" => data <= x"84";
when "10" & x"81a" => data <= x"3b";
when "10" & x"81b" => data <= x"84";
when "10" & x"81c" => data <= x"3e";
when "10" & x"81d" => data <= x"c8";
when "10" & x"81e" => data <= x"84";
when "10" & x"81f" => data <= x"3d";
when "10" & x"820" => data <= x"a6";
when "10" & x"821" => data <= x"30";
when "10" & x"822" => data <= x"f0";
when "10" & x"823" => data <= x"06";
when "10" & x"824" => data <= x"a5";
when "10" & x"825" => data <= x"31";
when "10" & x"826" => data <= x"c9";
when "10" & x"827" => data <= x"b5";
when "10" & x"828" => data <= x"90";
when "10" & x"829" => data <= x"02";
when "10" & x"82a" => data <= x"e8";
when "10" & x"82b" => data <= x"88";
when "10" & x"82c" => data <= x"8a";
when "10" & x"82d" => data <= x"48";
when "10" & x"82e" => data <= x"84";
when "10" & x"82f" => data <= x"30";
when "10" & x"830" => data <= x"20";
when "10" & x"831" => data <= x"05";
when "10" & x"832" => data <= x"a5";
when "10" & x"833" => data <= x"a9";
when "10" & x"834" => data <= x"7b";
when "10" & x"835" => data <= x"20";
when "10" & x"836" => data <= x"87";
when "10" & x"837" => data <= x"a3";
when "10" & x"838" => data <= x"a9";
when "10" & x"839" => data <= x"73";
when "10" & x"83a" => data <= x"a0";
when "10" & x"83b" => data <= x"a8";
when "10" & x"83c" => data <= x"20";
when "10" & x"83d" => data <= x"97";
when "10" & x"83e" => data <= x"a8";
when "10" & x"83f" => data <= x"20";
when "10" & x"840" => data <= x"e9";
when "10" & x"841" => data <= x"a7";
when "10" & x"842" => data <= x"20";
when "10" & x"843" => data <= x"56";
when "10" & x"844" => data <= x"a6";
when "10" & x"845" => data <= x"20";
when "10" & x"846" => data <= x"56";
when "10" & x"847" => data <= x"a6";
when "10" & x"848" => data <= x"20";
when "10" & x"849" => data <= x"00";
when "10" & x"84a" => data <= x"a5";
when "10" & x"84b" => data <= x"20";
when "10" & x"84c" => data <= x"85";
when "10" & x"84d" => data <= x"a3";
when "10" & x"84e" => data <= x"68";
when "10" & x"84f" => data <= x"38";
when "10" & x"850" => data <= x"e9";
when "10" & x"851" => data <= x"81";
when "10" & x"852" => data <= x"20";
when "10" & x"853" => data <= x"ed";
when "10" & x"854" => data <= x"a2";
when "10" & x"855" => data <= x"a9";
when "10" & x"856" => data <= x"6e";
when "10" & x"857" => data <= x"85";
when "10" & x"858" => data <= x"4b";
when "10" & x"859" => data <= x"a9";
when "10" & x"85a" => data <= x"a8";
when "10" & x"85b" => data <= x"85";
when "10" & x"85c" => data <= x"4c";
when "10" & x"85d" => data <= x"20";
when "10" & x"85e" => data <= x"56";
when "10" & x"85f" => data <= x"a6";
when "10" & x"860" => data <= x"20";
when "10" & x"861" => data <= x"f5";
when "10" & x"862" => data <= x"a7";
when "10" & x"863" => data <= x"20";
when "10" & x"864" => data <= x"00";
when "10" & x"865" => data <= x"a5";
when "10" & x"866" => data <= x"a9";
when "10" & x"867" => data <= x"ff";
when "10" & x"868" => data <= x"60";
when "10" & x"869" => data <= x"7f";
when "10" & x"86a" => data <= x"5e";
when "10" & x"86b" => data <= x"5b";
when "10" & x"86c" => data <= x"d8";
when "10" & x"86d" => data <= x"aa";
when "10" & x"86e" => data <= x"80";
when "10" & x"86f" => data <= x"31";
when "10" & x"870" => data <= x"72";
when "10" & x"871" => data <= x"17";
when "10" & x"872" => data <= x"f8";
when "10" & x"873" => data <= x"06";
when "10" & x"874" => data <= x"7a";
when "10" & x"875" => data <= x"12";
when "10" & x"876" => data <= x"38";
when "10" & x"877" => data <= x"a5";
when "10" & x"878" => data <= x"0b";
when "10" & x"879" => data <= x"88";
when "10" & x"87a" => data <= x"79";
when "10" & x"87b" => data <= x"0e";
when "10" & x"87c" => data <= x"9f";
when "10" & x"87d" => data <= x"f3";
when "10" & x"87e" => data <= x"7c";
when "10" & x"87f" => data <= x"2a";
when "10" & x"880" => data <= x"ac";
when "10" & x"881" => data <= x"3f";
when "10" & x"882" => data <= x"b5";
when "10" & x"883" => data <= x"86";
when "10" & x"884" => data <= x"34";
when "10" & x"885" => data <= x"01";
when "10" & x"886" => data <= x"a2";
when "10" & x"887" => data <= x"7a";
when "10" & x"888" => data <= x"7f";
when "10" & x"889" => data <= x"63";
when "10" & x"88a" => data <= x"8e";
when "10" & x"88b" => data <= x"37";
when "10" & x"88c" => data <= x"ec";
when "10" & x"88d" => data <= x"82";
when "10" & x"88e" => data <= x"3f";
when "10" & x"88f" => data <= x"ff";
when "10" & x"890" => data <= x"ff";
when "10" & x"891" => data <= x"c1";
when "10" & x"892" => data <= x"7f";
when "10" & x"893" => data <= x"ff";
when "10" & x"894" => data <= x"ff";
when "10" & x"895" => data <= x"ff";
when "10" & x"896" => data <= x"ff";
when "10" & x"897" => data <= x"85";
when "10" & x"898" => data <= x"4d";
when "10" & x"899" => data <= x"84";
when "10" & x"89a" => data <= x"4e";
when "10" & x"89b" => data <= x"20";
when "10" & x"89c" => data <= x"85";
when "10" & x"89d" => data <= x"a3";
when "10" & x"89e" => data <= x"a0";
when "10" & x"89f" => data <= x"00";
when "10" & x"8a0" => data <= x"b1";
when "10" & x"8a1" => data <= x"4d";
when "10" & x"8a2" => data <= x"85";
when "10" & x"8a3" => data <= x"48";
when "10" & x"8a4" => data <= x"e6";
when "10" & x"8a5" => data <= x"4d";
when "10" & x"8a6" => data <= x"d0";
when "10" & x"8a7" => data <= x"02";
when "10" & x"8a8" => data <= x"e6";
when "10" & x"8a9" => data <= x"4e";
when "10" & x"8aa" => data <= x"a5";
when "10" & x"8ab" => data <= x"4d";
when "10" & x"8ac" => data <= x"85";
when "10" & x"8ad" => data <= x"4b";
when "10" & x"8ae" => data <= x"a5";
when "10" & x"8af" => data <= x"4e";
when "10" & x"8b0" => data <= x"85";
when "10" & x"8b1" => data <= x"4c";
when "10" & x"8b2" => data <= x"20";
when "10" & x"8b3" => data <= x"b5";
when "10" & x"8b4" => data <= x"a3";
when "10" & x"8b5" => data <= x"20";
when "10" & x"8b6" => data <= x"f5";
when "10" & x"8b7" => data <= x"a7";
when "10" & x"8b8" => data <= x"20";
when "10" & x"8b9" => data <= x"ad";
when "10" & x"8ba" => data <= x"a6";
when "10" & x"8bb" => data <= x"18";
when "10" & x"8bc" => data <= x"a5";
when "10" & x"8bd" => data <= x"4d";
when "10" & x"8be" => data <= x"69";
when "10" & x"8bf" => data <= x"05";
when "10" & x"8c0" => data <= x"85";
when "10" & x"8c1" => data <= x"4d";
when "10" & x"8c2" => data <= x"85";
when "10" & x"8c3" => data <= x"4b";
when "10" & x"8c4" => data <= x"a5";
when "10" & x"8c5" => data <= x"4e";
when "10" & x"8c6" => data <= x"69";
when "10" & x"8c7" => data <= x"00";
when "10" & x"8c8" => data <= x"85";
when "10" & x"8c9" => data <= x"4e";
when "10" & x"8ca" => data <= x"85";
when "10" & x"8cb" => data <= x"4c";
when "10" & x"8cc" => data <= x"20";
when "10" & x"8cd" => data <= x"00";
when "10" & x"8ce" => data <= x"a5";
when "10" & x"8cf" => data <= x"c6";
when "10" & x"8d0" => data <= x"48";
when "10" & x"8d1" => data <= x"d0";
when "10" & x"8d2" => data <= x"e2";
when "10" & x"8d3" => data <= x"60";
when "10" & x"8d4" => data <= x"20";
when "10" & x"8d5" => data <= x"da";
when "10" & x"8d6" => data <= x"a8";
when "10" & x"8d7" => data <= x"4c";
when "10" & x"8d8" => data <= x"27";
when "10" & x"8d9" => data <= x"a9";
when "10" & x"8da" => data <= x"20";
when "10" & x"8db" => data <= x"fa";
when "10" & x"8dc" => data <= x"92";
when "10" & x"8dd" => data <= x"20";
when "10" & x"8de" => data <= x"da";
when "10" & x"8df" => data <= x"a1";
when "10" & x"8e0" => data <= x"10";
when "10" & x"8e1" => data <= x"08";
when "10" & x"8e2" => data <= x"46";
when "10" & x"8e3" => data <= x"2e";
when "10" & x"8e4" => data <= x"20";
when "10" & x"8e5" => data <= x"ea";
when "10" & x"8e6" => data <= x"a8";
when "10" & x"8e7" => data <= x"4c";
when "10" & x"8e8" => data <= x"16";
when "10" & x"8e9" => data <= x"a9";
when "10" & x"8ea" => data <= x"20";
when "10" & x"8eb" => data <= x"81";
when "10" & x"8ec" => data <= x"a3";
when "10" & x"8ed" => data <= x"20";
when "10" & x"8ee" => data <= x"b1";
when "10" & x"8ef" => data <= x"a9";
when "10" & x"8f0" => data <= x"20";
when "10" & x"8f1" => data <= x"da";
when "10" & x"8f2" => data <= x"a1";
when "10" & x"8f3" => data <= x"f0";
when "10" & x"8f4" => data <= x"09";
when "10" & x"8f5" => data <= x"20";
when "10" & x"8f6" => data <= x"f1";
when "10" & x"8f7" => data <= x"a7";
when "10" & x"8f8" => data <= x"20";
when "10" & x"8f9" => data <= x"ad";
when "10" & x"8fa" => data <= x"a6";
when "10" & x"8fb" => data <= x"4c";
when "10" & x"8fc" => data <= x"0a";
when "10" & x"8fd" => data <= x"a9";
when "10" & x"8fe" => data <= x"20";
when "10" & x"8ff" => data <= x"55";
when "10" & x"900" => data <= x"aa";
when "10" & x"901" => data <= x"20";
when "10" & x"902" => data <= x"b5";
when "10" & x"903" => data <= x"a3";
when "10" & x"904" => data <= x"a9";
when "10" & x"905" => data <= x"ff";
when "10" & x"906" => data <= x"60";
when "10" & x"907" => data <= x"20";
when "10" & x"908" => data <= x"fa";
when "10" & x"909" => data <= x"92";
when "10" & x"90a" => data <= x"20";
when "10" & x"90b" => data <= x"da";
when "10" & x"90c" => data <= x"a1";
when "10" & x"90d" => data <= x"f0";
when "10" & x"90e" => data <= x"f5";
when "10" & x"90f" => data <= x"10";
when "10" & x"910" => data <= x"0a";
when "10" & x"911" => data <= x"46";
when "10" & x"912" => data <= x"2e";
when "10" & x"913" => data <= x"20";
when "10" & x"914" => data <= x"1b";
when "10" & x"915" => data <= x"a9";
when "10" & x"916" => data <= x"a9";
when "10" & x"917" => data <= x"80";
when "10" & x"918" => data <= x"85";
when "10" & x"919" => data <= x"2e";
when "10" & x"91a" => data <= x"60";
when "10" & x"91b" => data <= x"a5";
when "10" & x"91c" => data <= x"30";
when "10" & x"91d" => data <= x"c9";
when "10" & x"91e" => data <= x"81";
when "10" & x"91f" => data <= x"90";
when "10" & x"920" => data <= x"15";
when "10" & x"921" => data <= x"20";
when "10" & x"922" => data <= x"a5";
when "10" & x"923" => data <= x"a6";
when "10" & x"924" => data <= x"20";
when "10" & x"925" => data <= x"36";
when "10" & x"926" => data <= x"a9";
when "10" & x"927" => data <= x"20";
when "10" & x"928" => data <= x"48";
when "10" & x"929" => data <= x"aa";
when "10" & x"92a" => data <= x"20";
when "10" & x"92b" => data <= x"00";
when "10" & x"92c" => data <= x"a5";
when "10" & x"92d" => data <= x"20";
when "10" & x"92e" => data <= x"4c";
when "10" & x"92f" => data <= x"aa";
when "10" & x"930" => data <= x"20";
when "10" & x"931" => data <= x"00";
when "10" & x"932" => data <= x"a5";
when "10" & x"933" => data <= x"4c";
when "10" & x"934" => data <= x"7e";
when "10" & x"935" => data <= x"ad";
when "10" & x"936" => data <= x"a5";
when "10" & x"937" => data <= x"30";
when "10" & x"938" => data <= x"c9";
when "10" & x"939" => data <= x"73";
when "10" & x"93a" => data <= x"90";
when "10" & x"93b" => data <= x"c8";
when "10" & x"93c" => data <= x"20";
when "10" & x"93d" => data <= x"81";
when "10" & x"93e" => data <= x"a3";
when "10" & x"93f" => data <= x"20";
when "10" & x"940" => data <= x"53";
when "10" & x"941" => data <= x"a4";
when "10" & x"942" => data <= x"a9";
when "10" & x"943" => data <= x"80";
when "10" & x"944" => data <= x"85";
when "10" & x"945" => data <= x"3d";
when "10" & x"946" => data <= x"85";
when "10" & x"947" => data <= x"3e";
when "10" & x"948" => data <= x"85";
when "10" & x"949" => data <= x"3b";
when "10" & x"94a" => data <= x"20";
when "10" & x"94b" => data <= x"05";
when "10" & x"94c" => data <= x"a5";
when "10" & x"94d" => data <= x"a9";
when "10" & x"94e" => data <= x"5a";
when "10" & x"94f" => data <= x"a0";
when "10" & x"950" => data <= x"a9";
when "10" & x"951" => data <= x"20";
when "10" & x"952" => data <= x"97";
when "10" & x"953" => data <= x"a8";
when "10" & x"954" => data <= x"20";
when "10" & x"955" => data <= x"d1";
when "10" & x"956" => data <= x"aa";
when "10" & x"957" => data <= x"a9";
when "10" & x"958" => data <= x"ff";
when "10" & x"959" => data <= x"60";
when "10" & x"95a" => data <= x"09";
when "10" & x"95b" => data <= x"85";
when "10" & x"95c" => data <= x"a3";
when "10" & x"95d" => data <= x"59";
when "10" & x"95e" => data <= x"e8";
when "10" & x"95f" => data <= x"67";
when "10" & x"960" => data <= x"80";
when "10" & x"961" => data <= x"1c";
when "10" & x"962" => data <= x"9d";
when "10" & x"963" => data <= x"07";
when "10" & x"964" => data <= x"36";
when "10" & x"965" => data <= x"80";
when "10" & x"966" => data <= x"57";
when "10" & x"967" => data <= x"bb";
when "10" & x"968" => data <= x"78";
when "10" & x"969" => data <= x"df";
when "10" & x"96a" => data <= x"80";
when "10" & x"96b" => data <= x"ca";
when "10" & x"96c" => data <= x"9a";
when "10" & x"96d" => data <= x"0e";
when "10" & x"96e" => data <= x"83";
when "10" & x"96f" => data <= x"84";
when "10" & x"970" => data <= x"8c";
when "10" & x"971" => data <= x"bb";
when "10" & x"972" => data <= x"ca";
when "10" & x"973" => data <= x"6e";
when "10" & x"974" => data <= x"81";
when "10" & x"975" => data <= x"95";
when "10" & x"976" => data <= x"96";
when "10" & x"977" => data <= x"06";
when "10" & x"978" => data <= x"de";
when "10" & x"979" => data <= x"81";
when "10" & x"97a" => data <= x"0a";
when "10" & x"97b" => data <= x"c7";
when "10" & x"97c" => data <= x"6c";
when "10" & x"97d" => data <= x"52";
when "10" & x"97e" => data <= x"7f";
when "10" & x"97f" => data <= x"7d";
when "10" & x"980" => data <= x"ad";
when "10" & x"981" => data <= x"90";
when "10" & x"982" => data <= x"a1";
when "10" & x"983" => data <= x"82";
when "10" & x"984" => data <= x"fb";
when "10" & x"985" => data <= x"62";
when "10" & x"986" => data <= x"57";
when "10" & x"987" => data <= x"2f";
when "10" & x"988" => data <= x"80";
when "10" & x"989" => data <= x"6d";
when "10" & x"98a" => data <= x"63";
when "10" & x"98b" => data <= x"38";
when "10" & x"98c" => data <= x"2c";
when "10" & x"98d" => data <= x"20";
when "10" & x"98e" => data <= x"fa";
when "10" & x"98f" => data <= x"92";
when "10" & x"990" => data <= x"20";
when "10" & x"991" => data <= x"d3";
when "10" & x"992" => data <= x"a9";
when "10" & x"993" => data <= x"e6";
when "10" & x"994" => data <= x"4a";
when "10" & x"995" => data <= x"4c";
when "10" & x"996" => data <= x"9e";
when "10" & x"997" => data <= x"a9";
when "10" & x"998" => data <= x"20";
when "10" & x"999" => data <= x"fa";
when "10" & x"99a" => data <= x"92";
when "10" & x"99b" => data <= x"20";
when "10" & x"99c" => data <= x"d3";
when "10" & x"99d" => data <= x"a9";
when "10" & x"99e" => data <= x"a5";
when "10" & x"99f" => data <= x"4a";
when "10" & x"9a0" => data <= x"29";
when "10" & x"9a1" => data <= x"02";
when "10" & x"9a2" => data <= x"f0";
when "10" & x"9a3" => data <= x"06";
when "10" & x"9a4" => data <= x"20";
when "10" & x"9a5" => data <= x"aa";
when "10" & x"9a6" => data <= x"a9";
when "10" & x"9a7" => data <= x"4c";
when "10" & x"9a8" => data <= x"7e";
when "10" & x"9a9" => data <= x"ad";
when "10" & x"9aa" => data <= x"46";
when "10" & x"9ab" => data <= x"4a";
when "10" & x"9ac" => data <= x"90";
when "10" & x"9ad" => data <= x"15";
when "10" & x"9ae" => data <= x"20";
when "10" & x"9af" => data <= x"c3";
when "10" & x"9b0" => data <= x"a9";
when "10" & x"9b1" => data <= x"20";
when "10" & x"9b2" => data <= x"85";
when "10" & x"9b3" => data <= x"a3";
when "10" & x"9b4" => data <= x"20";
when "10" & x"9b5" => data <= x"56";
when "10" & x"9b6" => data <= x"a6";
when "10" & x"9b7" => data <= x"20";
when "10" & x"9b8" => data <= x"8d";
when "10" & x"9b9" => data <= x"a3";
when "10" & x"9ba" => data <= x"20";
when "10" & x"9bb" => data <= x"99";
when "10" & x"9bc" => data <= x"a6";
when "10" & x"9bd" => data <= x"20";
when "10" & x"9be" => data <= x"d0";
when "10" & x"9bf" => data <= x"a4";
when "10" & x"9c0" => data <= x"4c";
when "10" & x"9c1" => data <= x"b7";
when "10" & x"9c2" => data <= x"a7";
when "10" & x"9c3" => data <= x"20";
when "10" & x"9c4" => data <= x"81";
when "10" & x"9c5" => data <= x"a3";
when "10" & x"9c6" => data <= x"20";
when "10" & x"9c7" => data <= x"56";
when "10" & x"9c8" => data <= x"a6";
when "10" & x"9c9" => data <= x"a9";
when "10" & x"9ca" => data <= x"72";
when "10" & x"9cb" => data <= x"a0";
when "10" & x"9cc" => data <= x"aa";
when "10" & x"9cd" => data <= x"20";
when "10" & x"9ce" => data <= x"97";
when "10" & x"9cf" => data <= x"a8";
when "10" & x"9d0" => data <= x"4c";
when "10" & x"9d1" => data <= x"d1";
when "10" & x"9d2" => data <= x"aa";
when "10" & x"9d3" => data <= x"a5";
when "10" & x"9d4" => data <= x"30";
when "10" & x"9d5" => data <= x"c9";
when "10" & x"9d6" => data <= x"98";
when "10" & x"9d7" => data <= x"b0";
when "10" & x"9d8" => data <= x"5f";
when "10" & x"9d9" => data <= x"20";
when "10" & x"9da" => data <= x"85";
when "10" & x"9db" => data <= x"a3";
when "10" & x"9dc" => data <= x"20";
when "10" & x"9dd" => data <= x"55";
when "10" & x"9de" => data <= x"aa";
when "10" & x"9df" => data <= x"20";
when "10" & x"9e0" => data <= x"4e";
when "10" & x"9e1" => data <= x"a3";
when "10" & x"9e2" => data <= x"a5";
when "10" & x"9e3" => data <= x"2e";
when "10" & x"9e4" => data <= x"85";
when "10" & x"9e5" => data <= x"3b";
when "10" & x"9e6" => data <= x"c6";
when "10" & x"9e7" => data <= x"3d";
when "10" & x"9e8" => data <= x"20";
when "10" & x"9e9" => data <= x"05";
when "10" & x"9ea" => data <= x"a5";
when "10" & x"9eb" => data <= x"20";
when "10" & x"9ec" => data <= x"e7";
when "10" & x"9ed" => data <= x"a6";
when "10" & x"9ee" => data <= x"20";
when "10" & x"9ef" => data <= x"fe";
when "10" & x"9f0" => data <= x"a3";
when "10" & x"9f1" => data <= x"a5";
when "10" & x"9f2" => data <= x"34";
when "10" & x"9f3" => data <= x"85";
when "10" & x"9f4" => data <= x"4a";
when "10" & x"9f5" => data <= x"05";
when "10" & x"9f6" => data <= x"33";
when "10" & x"9f7" => data <= x"05";
when "10" & x"9f8" => data <= x"32";
when "10" & x"9f9" => data <= x"05";
when "10" & x"9fa" => data <= x"31";
when "10" & x"9fb" => data <= x"f0";
when "10" & x"9fc" => data <= x"38";
when "10" & x"9fd" => data <= x"a9";
when "10" & x"9fe" => data <= x"a0";
when "10" & x"9ff" => data <= x"85";
when "10" & x"a00" => data <= x"30";
when "10" & x"a01" => data <= x"a0";
when "10" & x"a02" => data <= x"00";
when "10" & x"a03" => data <= x"84";
when "10" & x"a04" => data <= x"35";
when "10" & x"a05" => data <= x"a5";
when "10" & x"a06" => data <= x"31";
when "10" & x"a07" => data <= x"85";
when "10" & x"a08" => data <= x"2e";
when "10" & x"a09" => data <= x"10";
when "10" & x"a0a" => data <= x"03";
when "10" & x"a0b" => data <= x"20";
when "10" & x"a0c" => data <= x"6c";
when "10" & x"a0d" => data <= x"a4";
when "10" & x"a0e" => data <= x"20";
when "10" & x"a0f" => data <= x"03";
when "10" & x"a10" => data <= x"a3";
when "10" & x"a11" => data <= x"20";
when "10" & x"a12" => data <= x"7d";
when "10" & x"a13" => data <= x"a3";
when "10" & x"a14" => data <= x"20";
when "10" & x"a15" => data <= x"48";
when "10" & x"a16" => data <= x"aa";
when "10" & x"a17" => data <= x"20";
when "10" & x"a18" => data <= x"56";
when "10" & x"a19" => data <= x"a6";
when "10" & x"a1a" => data <= x"20";
when "10" & x"a1b" => data <= x"f5";
when "10" & x"a1c" => data <= x"a7";
when "10" & x"a1d" => data <= x"20";
when "10" & x"a1e" => data <= x"00";
when "10" & x"a1f" => data <= x"a5";
when "10" & x"a20" => data <= x"20";
when "10" & x"a21" => data <= x"8d";
when "10" & x"a22" => data <= x"a3";
when "10" & x"a23" => data <= x"20";
when "10" & x"a24" => data <= x"ed";
when "10" & x"a25" => data <= x"a7";
when "10" & x"a26" => data <= x"20";
when "10" & x"a27" => data <= x"b5";
when "10" & x"a28" => data <= x"a3";
when "10" & x"a29" => data <= x"20";
when "10" & x"a2a" => data <= x"4c";
when "10" & x"a2b" => data <= x"aa";
when "10" & x"a2c" => data <= x"20";
when "10" & x"a2d" => data <= x"56";
when "10" & x"a2e" => data <= x"a6";
when "10" & x"a2f" => data <= x"20";
when "10" & x"a30" => data <= x"f5";
when "10" & x"a31" => data <= x"a7";
when "10" & x"a32" => data <= x"4c";
when "10" & x"a33" => data <= x"00";
when "10" & x"a34" => data <= x"a5";
when "10" & x"a35" => data <= x"4c";
when "10" & x"a36" => data <= x"b2";
when "10" & x"a37" => data <= x"a3";
when "10" & x"a38" => data <= x"00";
when "10" & x"a39" => data <= x"17";
when "10" & x"a3a" => data <= x"41";
when "10" & x"a3b" => data <= x"63";
when "10" & x"a3c" => data <= x"63";
when "10" & x"a3d" => data <= x"75";
when "10" & x"a3e" => data <= x"72";
when "10" & x"a3f" => data <= x"61";
when "10" & x"a40" => data <= x"63";
when "10" & x"a41" => data <= x"79";
when "10" & x"a42" => data <= x"20";
when "10" & x"a43" => data <= x"6c";
when "10" & x"a44" => data <= x"6f";
when "10" & x"a45" => data <= x"73";
when "10" & x"a46" => data <= x"74";
when "10" & x"a47" => data <= x"00";
when "10" & x"a48" => data <= x"a9";
when "10" & x"a49" => data <= x"59";
when "10" & x"a4a" => data <= x"d0";
when "10" & x"a4b" => data <= x"02";
when "10" & x"a4c" => data <= x"a9";
when "10" & x"a4d" => data <= x"5e";
when "10" & x"a4e" => data <= x"85";
when "10" & x"a4f" => data <= x"4b";
when "10" & x"a50" => data <= x"a9";
when "10" & x"a51" => data <= x"aa";
when "10" & x"a52" => data <= x"85";
when "10" & x"a53" => data <= x"4c";
when "10" & x"a54" => data <= x"60";
when "10" & x"a55" => data <= x"a9";
when "10" & x"a56" => data <= x"63";
when "10" & x"a57" => data <= x"d0";
when "10" & x"a58" => data <= x"f5";
when "10" & x"a59" => data <= x"81";
when "10" & x"a5a" => data <= x"c9";
when "10" & x"a5b" => data <= x"10";
when "10" & x"a5c" => data <= x"00";
when "10" & x"a5d" => data <= x"00";
when "10" & x"a5e" => data <= x"6f";
when "10" & x"a5f" => data <= x"15";
when "10" & x"a60" => data <= x"77";
when "10" & x"a61" => data <= x"7a";
when "10" & x"a62" => data <= x"61";
when "10" & x"a63" => data <= x"81";
when "10" & x"a64" => data <= x"49";
when "10" & x"a65" => data <= x"0f";
when "10" & x"a66" => data <= x"da";
when "10" & x"a67" => data <= x"a2";
when "10" & x"a68" => data <= x"7b";
when "10" & x"a69" => data <= x"0e";
when "10" & x"a6a" => data <= x"fa";
when "10" & x"a6b" => data <= x"35";
when "10" & x"a6c" => data <= x"12";
when "10" & x"a6d" => data <= x"86";
when "10" & x"a6e" => data <= x"65";
when "10" & x"a6f" => data <= x"2e";
when "10" & x"a70" => data <= x"e0";
when "10" & x"a71" => data <= x"d3";
when "10" & x"a72" => data <= x"05";
when "10" & x"a73" => data <= x"84";
when "10" & x"a74" => data <= x"8a";
when "10" & x"a75" => data <= x"ea";
when "10" & x"a76" => data <= x"0c";
when "10" & x"a77" => data <= x"1b";
when "10" & x"a78" => data <= x"84";
when "10" & x"a79" => data <= x"1a";
when "10" & x"a7a" => data <= x"be";
when "10" & x"a7b" => data <= x"bb";
when "10" & x"a7c" => data <= x"2b";
when "10" & x"a7d" => data <= x"84";
when "10" & x"a7e" => data <= x"37";
when "10" & x"a7f" => data <= x"45";
when "10" & x"a80" => data <= x"55";
when "10" & x"a81" => data <= x"ab";
when "10" & x"a82" => data <= x"82";
when "10" & x"a83" => data <= x"d5";
when "10" & x"a84" => data <= x"55";
when "10" & x"a85" => data <= x"57";
when "10" & x"a86" => data <= x"7c";
when "10" & x"a87" => data <= x"83";
when "10" & x"a88" => data <= x"c0";
when "10" & x"a89" => data <= x"00";
when "10" & x"a8a" => data <= x"00";
when "10" & x"a8b" => data <= x"05";
when "10" & x"a8c" => data <= x"81";
when "10" & x"a8d" => data <= x"00";
when "10" & x"a8e" => data <= x"00";
when "10" & x"a8f" => data <= x"00";
when "10" & x"a90" => data <= x"00";
when "10" & x"a91" => data <= x"20";
when "10" & x"a92" => data <= x"fa";
when "10" & x"a93" => data <= x"92";
when "10" & x"a94" => data <= x"a5";
when "10" & x"a95" => data <= x"30";
when "10" & x"a96" => data <= x"c9";
when "10" & x"a97" => data <= x"87";
when "10" & x"a98" => data <= x"90";
when "10" & x"a99" => data <= x"1e";
when "10" & x"a9a" => data <= x"d0";
when "10" & x"a9b" => data <= x"06";
when "10" & x"a9c" => data <= x"a4";
when "10" & x"a9d" => data <= x"31";
when "10" & x"a9e" => data <= x"c0";
when "10" & x"a9f" => data <= x"b3";
when "10" & x"aa0" => data <= x"90";
when "10" & x"aa1" => data <= x"16";
when "10" & x"aa2" => data <= x"a5";
when "10" & x"aa3" => data <= x"2e";
when "10" & x"aa4" => data <= x"10";
when "10" & x"aa5" => data <= x"06";
when "10" & x"aa6" => data <= x"20";
when "10" & x"aa7" => data <= x"86";
when "10" & x"aa8" => data <= x"a6";
when "10" & x"aa9" => data <= x"a9";
when "10" & x"aaa" => data <= x"ff";
when "10" & x"aab" => data <= x"60";
when "10" & x"aac" => data <= x"00";
when "10" & x"aad" => data <= x"18";
when "10" & x"aae" => data <= x"45";
when "10" & x"aaf" => data <= x"78";
when "10" & x"ab0" => data <= x"70";
when "10" & x"ab1" => data <= x"20";
when "10" & x"ab2" => data <= x"72";
when "10" & x"ab3" => data <= x"61";
when "10" & x"ab4" => data <= x"6e";
when "10" & x"ab5" => data <= x"67";
when "10" & x"ab6" => data <= x"65";
when "10" & x"ab7" => data <= x"00";
when "10" & x"ab8" => data <= x"20";
when "10" & x"ab9" => data <= x"86";
when "10" & x"aba" => data <= x"a4";
when "10" & x"abb" => data <= x"20";
when "10" & x"abc" => data <= x"da";
when "10" & x"abd" => data <= x"aa";
when "10" & x"abe" => data <= x"20";
when "10" & x"abf" => data <= x"81";
when "10" & x"ac0" => data <= x"a3";
when "10" & x"ac1" => data <= x"a9";
when "10" & x"ac2" => data <= x"e4";
when "10" & x"ac3" => data <= x"85";
when "10" & x"ac4" => data <= x"4b";
when "10" & x"ac5" => data <= x"a9";
when "10" & x"ac6" => data <= x"aa";
when "10" & x"ac7" => data <= x"85";
when "10" & x"ac8" => data <= x"4c";
when "10" & x"ac9" => data <= x"20";
when "10" & x"aca" => data <= x"b5";
when "10" & x"acb" => data <= x"a3";
when "10" & x"acc" => data <= x"a5";
when "10" & x"acd" => data <= x"4a";
when "10" & x"ace" => data <= x"20";
when "10" & x"acf" => data <= x"12";
when "10" & x"ad0" => data <= x"ab";
when "10" & x"ad1" => data <= x"20";
when "10" & x"ad2" => data <= x"f1";
when "10" & x"ad3" => data <= x"a7";
when "10" & x"ad4" => data <= x"20";
when "10" & x"ad5" => data <= x"56";
when "10" & x"ad6" => data <= x"a6";
when "10" & x"ad7" => data <= x"a9";
when "10" & x"ad8" => data <= x"ff";
when "10" & x"ad9" => data <= x"60";
when "10" & x"ada" => data <= x"a9";
when "10" & x"adb" => data <= x"e9";
when "10" & x"adc" => data <= x"a0";
when "10" & x"add" => data <= x"aa";
when "10" & x"ade" => data <= x"20";
when "10" & x"adf" => data <= x"97";
when "10" & x"ae0" => data <= x"a8";
when "10" & x"ae1" => data <= x"a9";
when "10" & x"ae2" => data <= x"ff";
when "10" & x"ae3" => data <= x"60";
when "10" & x"ae4" => data <= x"82";
when "10" & x"ae5" => data <= x"2d";
when "10" & x"ae6" => data <= x"f8";
when "10" & x"ae7" => data <= x"54";
when "10" & x"ae8" => data <= x"58";
when "10" & x"ae9" => data <= x"07";
when "10" & x"aea" => data <= x"83";
when "10" & x"aeb" => data <= x"e0";
when "10" & x"aec" => data <= x"20";
when "10" & x"aed" => data <= x"86";
when "10" & x"aee" => data <= x"5b";
when "10" & x"aef" => data <= x"82";
when "10" & x"af0" => data <= x"80";
when "10" & x"af1" => data <= x"53";
when "10" & x"af2" => data <= x"93";
when "10" & x"af3" => data <= x"b8";
when "10" & x"af4" => data <= x"83";
when "10" & x"af5" => data <= x"20";
when "10" & x"af6" => data <= x"00";
when "10" & x"af7" => data <= x"06";
when "10" & x"af8" => data <= x"a1";
when "10" & x"af9" => data <= x"82";
when "10" & x"afa" => data <= x"00";
when "10" & x"afb" => data <= x"00";
when "10" & x"afc" => data <= x"21";
when "10" & x"afd" => data <= x"63";
when "10" & x"afe" => data <= x"82";
when "10" & x"aff" => data <= x"c0";
when "10" & x"b00" => data <= x"00";
when "10" & x"b01" => data <= x"00";
when "10" & x"b02" => data <= x"02";
when "10" & x"b03" => data <= x"82";
when "10" & x"b04" => data <= x"80";
when "10" & x"b05" => data <= x"00";
when "10" & x"b06" => data <= x"00";
when "10" & x"b07" => data <= x"0c";
when "10" & x"b08" => data <= x"81";
when "10" & x"b09" => data <= x"00";
when "10" & x"b0a" => data <= x"00";
when "10" & x"b0b" => data <= x"00";
when "10" & x"b0c" => data <= x"00";
when "10" & x"b0d" => data <= x"81";
when "10" & x"b0e" => data <= x"00";
when "10" & x"b0f" => data <= x"00";
when "10" & x"b10" => data <= x"00";
when "10" & x"b11" => data <= x"00";
when "10" & x"b12" => data <= x"aa";
when "10" & x"b13" => data <= x"10";
when "10" & x"b14" => data <= x"09";
when "10" & x"b15" => data <= x"ca";
when "10" & x"b16" => data <= x"8a";
when "10" & x"b17" => data <= x"49";
when "10" & x"b18" => data <= x"ff";
when "10" & x"b19" => data <= x"48";
when "10" & x"b1a" => data <= x"20";
when "10" & x"b1b" => data <= x"a5";
when "10" & x"b1c" => data <= x"a6";
when "10" & x"b1d" => data <= x"68";
when "10" & x"b1e" => data <= x"48";
when "10" & x"b1f" => data <= x"20";
when "10" & x"b20" => data <= x"85";
when "10" & x"b21" => data <= x"a3";
when "10" & x"b22" => data <= x"20";
when "10" & x"b23" => data <= x"99";
when "10" & x"b24" => data <= x"a6";
when "10" & x"b25" => data <= x"68";
when "10" & x"b26" => data <= x"f0";
when "10" & x"b27" => data <= x"0a";
when "10" & x"b28" => data <= x"38";
when "10" & x"b29" => data <= x"e9";
when "10" & x"b2a" => data <= x"01";
when "10" & x"b2b" => data <= x"48";
when "10" & x"b2c" => data <= x"20";
when "10" & x"b2d" => data <= x"56";
when "10" & x"b2e" => data <= x"a6";
when "10" & x"b2f" => data <= x"4c";
when "10" & x"b30" => data <= x"25";
when "10" & x"b31" => data <= x"ab";
when "10" & x"b32" => data <= x"60";
when "10" & x"b33" => data <= x"20";
when "10" & x"b34" => data <= x"e3";
when "10" & x"b35" => data <= x"92";
when "10" & x"b36" => data <= x"a6";
when "10" & x"b37" => data <= x"2a";
when "10" & x"b38" => data <= x"a9";
when "10" & x"b39" => data <= x"80";
when "10" & x"b3a" => data <= x"20";
when "10" & x"b3b" => data <= x"f4";
when "10" & x"b3c" => data <= x"ff";
when "10" & x"b3d" => data <= x"8a";
when "10" & x"b3e" => data <= x"4c";
when "10" & x"b3f" => data <= x"ea";
when "10" & x"b40" => data <= x"ae";
when "10" & x"b41" => data <= x"20";
when "10" & x"b42" => data <= x"dd";
when "10" & x"b43" => data <= x"92";
when "10" & x"b44" => data <= x"20";
when "10" & x"b45" => data <= x"94";
when "10" & x"b46" => data <= x"bd";
when "10" & x"b47" => data <= x"20";
when "10" & x"b48" => data <= x"ae";
when "10" & x"b49" => data <= x"8a";
when "10" & x"b4a" => data <= x"20";
when "10" & x"b4b" => data <= x"56";
when "10" & x"b4c" => data <= x"ae";
when "10" & x"b4d" => data <= x"20";
when "10" & x"b4e" => data <= x"f0";
when "10" & x"b4f" => data <= x"92";
when "10" & x"b50" => data <= x"a5";
when "10" & x"b51" => data <= x"2a";
when "10" & x"b52" => data <= x"48";
when "10" & x"b53" => data <= x"a5";
when "10" & x"b54" => data <= x"2b";
when "10" & x"b55" => data <= x"48";
when "10" & x"b56" => data <= x"20";
when "10" & x"b57" => data <= x"ea";
when "10" & x"b58" => data <= x"bd";
when "10" & x"b59" => data <= x"68";
when "10" & x"b5a" => data <= x"85";
when "10" & x"b5b" => data <= x"2d";
when "10" & x"b5c" => data <= x"68";
when "10" & x"b5d" => data <= x"85";
when "10" & x"b5e" => data <= x"2c";
when "10" & x"b5f" => data <= x"a2";
when "10" & x"b60" => data <= x"2a";
when "10" & x"b61" => data <= x"a9";
when "10" & x"b62" => data <= x"09";
when "10" & x"b63" => data <= x"20";
when "10" & x"b64" => data <= x"f1";
when "10" & x"b65" => data <= x"ff";
when "10" & x"b66" => data <= x"a5";
when "10" & x"b67" => data <= x"2e";
when "10" & x"b68" => data <= x"30";
when "10" & x"b69" => data <= x"33";
when "10" & x"b6a" => data <= x"4c";
when "10" & x"b6b" => data <= x"d8";
when "10" & x"b6c" => data <= x"ae";
when "10" & x"b6d" => data <= x"a9";
when "10" & x"b6e" => data <= x"86";
when "10" & x"b6f" => data <= x"20";
when "10" & x"b70" => data <= x"f4";
when "10" & x"b71" => data <= x"ff";
when "10" & x"b72" => data <= x"8a";
when "10" & x"b73" => data <= x"4c";
when "10" & x"b74" => data <= x"d8";
when "10" & x"b75" => data <= x"ae";
when "10" & x"b76" => data <= x"a9";
when "10" & x"b77" => data <= x"86";
when "10" & x"b78" => data <= x"20";
when "10" & x"b79" => data <= x"f4";
when "10" & x"b7a" => data <= x"ff";
when "10" & x"b7b" => data <= x"98";
when "10" & x"b7c" => data <= x"4c";
when "10" & x"b7d" => data <= x"d8";
when "10" & x"b7e" => data <= x"ae";
when "10" & x"b7f" => data <= x"20";
when "10" & x"b80" => data <= x"da";
when "10" & x"b81" => data <= x"a1";
when "10" & x"b82" => data <= x"f0";
when "10" & x"b83" => data <= x"1e";
when "10" & x"b84" => data <= x"10";
when "10" & x"b85" => data <= x"1a";
when "10" & x"b86" => data <= x"30";
when "10" & x"b87" => data <= x"15";
when "10" & x"b88" => data <= x"20";
when "10" & x"b89" => data <= x"ec";
when "10" & x"b8a" => data <= x"ad";
when "10" & x"b8b" => data <= x"f0";
when "10" & x"b8c" => data <= x"59";
when "10" & x"b8d" => data <= x"30";
when "10" & x"b8e" => data <= x"f0";
when "10" & x"b8f" => data <= x"a5";
when "10" & x"b90" => data <= x"2d";
when "10" & x"b91" => data <= x"05";
when "10" & x"b92" => data <= x"2c";
when "10" & x"b93" => data <= x"05";
when "10" & x"b94" => data <= x"2b";
when "10" & x"b95" => data <= x"05";
when "10" & x"b96" => data <= x"2a";
when "10" & x"b97" => data <= x"f0";
when "10" & x"b98" => data <= x"0c";
when "10" & x"b99" => data <= x"a5";
when "10" & x"b9a" => data <= x"2d";
when "10" & x"b9b" => data <= x"10";
when "10" & x"b9c" => data <= x"03";
when "10" & x"b9d" => data <= x"4c";
when "10" & x"b9e" => data <= x"c4";
when "10" & x"b9f" => data <= x"ac";
when "10" & x"ba0" => data <= x"a9";
when "10" & x"ba1" => data <= x"01";
when "10" & x"ba2" => data <= x"4c";
when "10" & x"ba3" => data <= x"d8";
when "10" & x"ba4" => data <= x"ae";
when "10" & x"ba5" => data <= x"a9";
when "10" & x"ba6" => data <= x"40";
when "10" & x"ba7" => data <= x"60";
when "10" & x"ba8" => data <= x"20";
when "10" & x"ba9" => data <= x"fe";
when "10" & x"baa" => data <= x"a7";
when "10" & x"bab" => data <= x"a0";
when "10" & x"bac" => data <= x"69";
when "10" & x"bad" => data <= x"a9";
when "10" & x"bae" => data <= x"a8";
when "10" & x"baf" => data <= x"d0";
when "10" & x"bb0" => data <= x"07";
when "10" & x"bb1" => data <= x"20";
when "10" & x"bb2" => data <= x"fa";
when "10" & x"bb3" => data <= x"92";
when "10" & x"bb4" => data <= x"a0";
when "10" & x"bb5" => data <= x"68";
when "10" & x"bb6" => data <= x"a9";
when "10" & x"bb7" => data <= x"aa";
when "10" & x"bb8" => data <= x"84";
when "10" & x"bb9" => data <= x"4b";
when "10" & x"bba" => data <= x"85";
when "10" & x"bbb" => data <= x"4c";
when "10" & x"bbc" => data <= x"20";
when "10" & x"bbd" => data <= x"56";
when "10" & x"bbe" => data <= x"a6";
when "10" & x"bbf" => data <= x"a9";
when "10" & x"bc0" => data <= x"ff";
when "10" & x"bc1" => data <= x"60";
when "10" & x"bc2" => data <= x"20";
when "10" & x"bc3" => data <= x"fa";
when "10" & x"bc4" => data <= x"92";
when "10" & x"bc5" => data <= x"a0";
when "10" & x"bc6" => data <= x"6d";
when "10" & x"bc7" => data <= x"a9";
when "10" & x"bc8" => data <= x"aa";
when "10" & x"bc9" => data <= x"d0";
when "10" & x"bca" => data <= x"ed";
when "10" & x"bcb" => data <= x"20";
when "10" & x"bcc" => data <= x"fe";
when "10" & x"bcd" => data <= x"a8";
when "10" & x"bce" => data <= x"e6";
when "10" & x"bcf" => data <= x"30";
when "10" & x"bd0" => data <= x"a8";
when "10" & x"bd1" => data <= x"60";
when "10" & x"bd2" => data <= x"20";
when "10" & x"bd3" => data <= x"e3";
when "10" & x"bd4" => data <= x"92";
when "10" & x"bd5" => data <= x"20";
when "10" & x"bd6" => data <= x"1e";
when "10" & x"bd7" => data <= x"8f";
when "10" & x"bd8" => data <= x"85";
when "10" & x"bd9" => data <= x"2a";
when "10" & x"bda" => data <= x"86";
when "10" & x"bdb" => data <= x"2b";
when "10" & x"bdc" => data <= x"84";
when "10" & x"bdd" => data <= x"2c";
when "10" & x"bde" => data <= x"08";
when "10" & x"bdf" => data <= x"68";
when "10" & x"be0" => data <= x"85";
when "10" & x"be1" => data <= x"2d";
when "10" & x"be2" => data <= x"d8";
when "10" & x"be3" => data <= x"a9";
when "10" & x"be4" => data <= x"40";
when "10" & x"be5" => data <= x"60";
when "10" & x"be6" => data <= x"4c";
when "10" & x"be7" => data <= x"0e";
when "10" & x"be8" => data <= x"8c";
when "10" & x"be9" => data <= x"20";
when "10" & x"bea" => data <= x"ec";
when "10" & x"beb" => data <= x"ad";
when "10" & x"bec" => data <= x"d0";
when "10" & x"bed" => data <= x"f8";
when "10" & x"bee" => data <= x"e6";
when "10" & x"bef" => data <= x"36";
when "10" & x"bf0" => data <= x"a4";
when "10" & x"bf1" => data <= x"36";
when "10" & x"bf2" => data <= x"a9";
when "10" & x"bf3" => data <= x"0d";
when "10" & x"bf4" => data <= x"99";
when "10" & x"bf5" => data <= x"ff";
when "10" & x"bf6" => data <= x"05";
when "10" & x"bf7" => data <= x"20";
when "10" & x"bf8" => data <= x"b2";
when "10" & x"bf9" => data <= x"bd";
when "10" & x"bfa" => data <= x"a5";
when "10" & x"bfb" => data <= x"19";
when "10" & x"bfc" => data <= x"48";
when "10" & x"bfd" => data <= x"a5";
when "10" & x"bfe" => data <= x"1a";
when "10" & x"bff" => data <= x"48";
when "10" & x"c00" => data <= x"a5";
when "10" & x"c01" => data <= x"1b";
when "10" & x"c02" => data <= x"48";
when "10" & x"c03" => data <= x"a4";
when "10" & x"c04" => data <= x"04";
when "10" & x"c05" => data <= x"a6";
when "10" & x"c06" => data <= x"05";
when "10" & x"c07" => data <= x"c8";
when "10" & x"c08" => data <= x"84";
when "10" & x"c09" => data <= x"19";
when "10" & x"c0a" => data <= x"84";
when "10" & x"c0b" => data <= x"37";
when "10" & x"c0c" => data <= x"d0";
when "10" & x"c0d" => data <= x"01";
when "10" & x"c0e" => data <= x"e8";
when "10" & x"c0f" => data <= x"86";
when "10" & x"c10" => data <= x"1a";
when "10" & x"c11" => data <= x"86";
when "10" & x"c12" => data <= x"38";
when "10" & x"c13" => data <= x"a0";
when "10" & x"c14" => data <= x"ff";
when "10" & x"c15" => data <= x"84";
when "10" & x"c16" => data <= x"3b";
when "10" & x"c17" => data <= x"c8";
when "10" & x"c18" => data <= x"84";
when "10" & x"c19" => data <= x"1b";
when "10" & x"c1a" => data <= x"20";
when "10" & x"c1b" => data <= x"55";
when "10" & x"c1c" => data <= x"89";
when "10" & x"c1d" => data <= x"20";
when "10" & x"c1e" => data <= x"29";
when "10" & x"c1f" => data <= x"9b";
when "10" & x"c20" => data <= x"20";
when "10" & x"c21" => data <= x"dc";
when "10" & x"c22" => data <= x"bd";
when "10" & x"c23" => data <= x"68";
when "10" & x"c24" => data <= x"85";
when "10" & x"c25" => data <= x"1b";
when "10" & x"c26" => data <= x"68";
when "10" & x"c27" => data <= x"85";
when "10" & x"c28" => data <= x"1a";
when "10" & x"c29" => data <= x"68";
when "10" & x"c2a" => data <= x"85";
when "10" & x"c2b" => data <= x"19";
when "10" & x"c2c" => data <= x"a5";
when "10" & x"c2d" => data <= x"27";
when "10" & x"c2e" => data <= x"60";
when "10" & x"c2f" => data <= x"20";
when "10" & x"c30" => data <= x"ec";
when "10" & x"c31" => data <= x"ad";
when "10" & x"c32" => data <= x"d0";
when "10" & x"c33" => data <= x"67";
when "10" & x"c34" => data <= x"a4";
when "10" & x"c35" => data <= x"36";
when "10" & x"c36" => data <= x"a9";
when "10" & x"c37" => data <= x"00";
when "10" & x"c38" => data <= x"99";
when "10" & x"c39" => data <= x"00";
when "10" & x"c3a" => data <= x"06";
when "10" & x"c3b" => data <= x"a5";
when "10" & x"c3c" => data <= x"19";
when "10" & x"c3d" => data <= x"48";
when "10" & x"c3e" => data <= x"a5";
when "10" & x"c3f" => data <= x"1a";
when "10" & x"c40" => data <= x"48";
when "10" & x"c41" => data <= x"a5";
when "10" & x"c42" => data <= x"1b";
when "10" & x"c43" => data <= x"48";
when "10" & x"c44" => data <= x"a9";
when "10" & x"c45" => data <= x"00";
when "10" & x"c46" => data <= x"85";
when "10" & x"c47" => data <= x"1b";
when "10" & x"c48" => data <= x"a9";
when "10" & x"c49" => data <= x"00";
when "10" & x"c4a" => data <= x"85";
when "10" & x"c4b" => data <= x"19";
when "10" & x"c4c" => data <= x"a9";
when "10" & x"c4d" => data <= x"06";
when "10" & x"c4e" => data <= x"85";
when "10" & x"c4f" => data <= x"1a";
when "10" & x"c50" => data <= x"20";
when "10" & x"c51" => data <= x"8c";
when "10" & x"c52" => data <= x"8a";
when "10" & x"c53" => data <= x"c9";
when "10" & x"c54" => data <= x"2d";
when "10" & x"c55" => data <= x"f0";
when "10" & x"c56" => data <= x"0f";
when "10" & x"c57" => data <= x"c9";
when "10" & x"c58" => data <= x"2b";
when "10" & x"c59" => data <= x"d0";
when "10" & x"c5a" => data <= x"03";
when "10" & x"c5b" => data <= x"20";
when "10" & x"c5c" => data <= x"8c";
when "10" & x"c5d" => data <= x"8a";
when "10" & x"c5e" => data <= x"c6";
when "10" & x"c5f" => data <= x"1b";
when "10" & x"c60" => data <= x"20";
when "10" & x"c61" => data <= x"7b";
when "10" & x"c62" => data <= x"a0";
when "10" & x"c63" => data <= x"4c";
when "10" & x"c64" => data <= x"73";
when "10" & x"c65" => data <= x"ac";
when "10" & x"c66" => data <= x"20";
when "10" & x"c67" => data <= x"8c";
when "10" & x"c68" => data <= x"8a";
when "10" & x"c69" => data <= x"c6";
when "10" & x"c6a" => data <= x"1b";
when "10" & x"c6b" => data <= x"20";
when "10" & x"c6c" => data <= x"7b";
when "10" & x"c6d" => data <= x"a0";
when "10" & x"c6e" => data <= x"90";
when "10" & x"c6f" => data <= x"03";
when "10" & x"c70" => data <= x"20";
when "10" & x"c71" => data <= x"8f";
when "10" & x"c72" => data <= x"ad";
when "10" & x"c73" => data <= x"85";
when "10" & x"c74" => data <= x"27";
when "10" & x"c75" => data <= x"4c";
when "10" & x"c76" => data <= x"23";
when "10" & x"c77" => data <= x"ac";
when "10" & x"c78" => data <= x"20";
when "10" & x"c79" => data <= x"ec";
when "10" & x"c7a" => data <= x"ad";
when "10" & x"c7b" => data <= x"f0";
when "10" & x"c7c" => data <= x"1e";
when "10" & x"c7d" => data <= x"10";
when "10" & x"c7e" => data <= x"1b";
when "10" & x"c7f" => data <= x"a5";
when "10" & x"c80" => data <= x"2e";
when "10" & x"c81" => data <= x"08";
when "10" & x"c82" => data <= x"20";
when "10" & x"c83" => data <= x"fe";
when "10" & x"c84" => data <= x"a3";
when "10" & x"c85" => data <= x"28";
when "10" & x"c86" => data <= x"10";
when "10" & x"c87" => data <= x"0d";
when "10" & x"c88" => data <= x"a5";
when "10" & x"c89" => data <= x"3e";
when "10" & x"c8a" => data <= x"05";
when "10" & x"c8b" => data <= x"3f";
when "10" & x"c8c" => data <= x"05";
when "10" & x"c8d" => data <= x"40";
when "10" & x"c8e" => data <= x"05";
when "10" & x"c8f" => data <= x"41";
when "10" & x"c90" => data <= x"f0";
when "10" & x"c91" => data <= x"03";
when "10" & x"c92" => data <= x"20";
when "10" & x"c93" => data <= x"c7";
when "10" & x"c94" => data <= x"a4";
when "10" & x"c95" => data <= x"20";
when "10" & x"c96" => data <= x"e7";
when "10" & x"c97" => data <= x"a3";
when "10" & x"c98" => data <= x"a9";
when "10" & x"c99" => data <= x"40";
when "10" & x"c9a" => data <= x"60";
when "10" & x"c9b" => data <= x"4c";
when "10" & x"c9c" => data <= x"0e";
when "10" & x"c9d" => data <= x"8c";
when "10" & x"c9e" => data <= x"20";
when "10" & x"c9f" => data <= x"ec";
when "10" & x"ca0" => data <= x"ad";
when "10" & x"ca1" => data <= x"d0";
when "10" & x"ca2" => data <= x"f8";
when "10" & x"ca3" => data <= x"a5";
when "10" & x"ca4" => data <= x"36";
when "10" & x"ca5" => data <= x"f0";
when "10" & x"ca6" => data <= x"1d";
when "10" & x"ca7" => data <= x"ad";
when "10" & x"ca8" => data <= x"00";
when "10" & x"ca9" => data <= x"06";
when "10" & x"caa" => data <= x"4c";
when "10" & x"cab" => data <= x"d8";
when "10" & x"cac" => data <= x"ae";
when "10" & x"cad" => data <= x"20";
when "10" & x"cae" => data <= x"ad";
when "10" & x"caf" => data <= x"af";
when "10" & x"cb0" => data <= x"c0";
when "10" & x"cb1" => data <= x"00";
when "10" & x"cb2" => data <= x"d0";
when "10" & x"cb3" => data <= x"10";
when "10" & x"cb4" => data <= x"8a";
when "10" & x"cb5" => data <= x"4c";
when "10" & x"cb6" => data <= x"ea";
when "10" & x"cb7" => data <= x"ae";
when "10" & x"cb8" => data <= x"20";
when "10" & x"cb9" => data <= x"b5";
when "10" & x"cba" => data <= x"bf";
when "10" & x"cbb" => data <= x"aa";
when "10" & x"cbc" => data <= x"a9";
when "10" & x"cbd" => data <= x"7f";
when "10" & x"cbe" => data <= x"20";
when "10" & x"cbf" => data <= x"f4";
when "10" & x"cc0" => data <= x"ff";
when "10" & x"cc1" => data <= x"8a";
when "10" & x"cc2" => data <= x"f0";
when "10" & x"cc3" => data <= x"e6";
when "10" & x"cc4" => data <= x"a9";
when "10" & x"cc5" => data <= x"ff";
when "10" & x"cc6" => data <= x"85";
when "10" & x"cc7" => data <= x"2a";
when "10" & x"cc8" => data <= x"85";
when "10" & x"cc9" => data <= x"2b";
when "10" & x"cca" => data <= x"85";
when "10" & x"ccb" => data <= x"2c";
when "10" & x"ccc" => data <= x"85";
when "10" & x"ccd" => data <= x"2d";
when "10" & x"cce" => data <= x"a9";
when "10" & x"ccf" => data <= x"40";
when "10" & x"cd0" => data <= x"60";
when "10" & x"cd1" => data <= x"20";
when "10" & x"cd2" => data <= x"e3";
when "10" & x"cd3" => data <= x"92";
when "10" & x"cd4" => data <= x"a2";
when "10" & x"cd5" => data <= x"03";
when "10" & x"cd6" => data <= x"b5";
when "10" & x"cd7" => data <= x"2a";
when "10" & x"cd8" => data <= x"49";
when "10" & x"cd9" => data <= x"ff";
when "10" & x"cda" => data <= x"95";
when "10" & x"cdb" => data <= x"2a";
when "10" & x"cdc" => data <= x"ca";
when "10" & x"cdd" => data <= x"10";
when "10" & x"cde" => data <= x"f7";
when "10" & x"cdf" => data <= x"a9";
when "10" & x"ce0" => data <= x"40";
when "10" & x"ce1" => data <= x"60";
when "10" & x"ce2" => data <= x"20";
when "10" & x"ce3" => data <= x"29";
when "10" & x"ce4" => data <= x"9b";
when "10" & x"ce5" => data <= x"d0";
when "10" & x"ce6" => data <= x"b4";
when "10" & x"ce7" => data <= x"e0";
when "10" & x"ce8" => data <= x"2c";
when "10" & x"ce9" => data <= x"d0";
when "10" & x"cea" => data <= x"18";
when "10" & x"ceb" => data <= x"e6";
when "10" & x"cec" => data <= x"1b";
when "10" & x"ced" => data <= x"20";
when "10" & x"cee" => data <= x"b2";
when "10" & x"cef" => data <= x"bd";
when "10" & x"cf0" => data <= x"20";
when "10" & x"cf1" => data <= x"29";
when "10" & x"cf2" => data <= x"9b";
when "10" & x"cf3" => data <= x"d0";
when "10" & x"cf4" => data <= x"a6";
when "10" & x"cf5" => data <= x"a9";
when "10" & x"cf6" => data <= x"01";
when "10" & x"cf7" => data <= x"85";
when "10" & x"cf8" => data <= x"2a";
when "10" & x"cf9" => data <= x"e6";
when "10" & x"cfa" => data <= x"1b";
when "10" & x"cfb" => data <= x"e0";
when "10" & x"cfc" => data <= x"29";
when "10" & x"cfd" => data <= x"f0";
when "10" & x"cfe" => data <= x"13";
when "10" & x"cff" => data <= x"e0";
when "10" & x"d00" => data <= x"2c";
when "10" & x"d01" => data <= x"f0";
when "10" & x"d02" => data <= x"03";
when "10" & x"d03" => data <= x"4c";
when "10" & x"d04" => data <= x"a2";
when "10" & x"d05" => data <= x"8a";
when "10" & x"d06" => data <= x"20";
when "10" & x"d07" => data <= x"b2";
when "10" & x"d08" => data <= x"bd";
when "10" & x"d09" => data <= x"20";
when "10" & x"d0a" => data <= x"56";
when "10" & x"d0b" => data <= x"ae";
when "10" & x"d0c" => data <= x"20";
when "10" & x"d0d" => data <= x"f0";
when "10" & x"d0e" => data <= x"92";
when "10" & x"d0f" => data <= x"20";
when "10" & x"d10" => data <= x"cb";
when "10" & x"d11" => data <= x"bd";
when "10" & x"d12" => data <= x"a0";
when "10" & x"d13" => data <= x"00";
when "10" & x"d14" => data <= x"a6";
when "10" & x"d15" => data <= x"2a";
when "10" & x"d16" => data <= x"d0";
when "10" & x"d17" => data <= x"02";
when "10" & x"d18" => data <= x"a2";
when "10" & x"d19" => data <= x"01";
when "10" & x"d1a" => data <= x"86";
when "10" & x"d1b" => data <= x"2a";
when "10" & x"d1c" => data <= x"8a";
when "10" & x"d1d" => data <= x"ca";
when "10" & x"d1e" => data <= x"86";
when "10" & x"d1f" => data <= x"2d";
when "10" & x"d20" => data <= x"18";
when "10" & x"d21" => data <= x"65";
when "10" & x"d22" => data <= x"04";
when "10" & x"d23" => data <= x"85";
when "10" & x"d24" => data <= x"37";
when "10" & x"d25" => data <= x"98";
when "10" & x"d26" => data <= x"65";
when "10" & x"d27" => data <= x"05";
when "10" & x"d28" => data <= x"85";
when "10" & x"d29" => data <= x"38";
when "10" & x"d2a" => data <= x"b1";
when "10" & x"d2b" => data <= x"04";
when "10" & x"d2c" => data <= x"38";
when "10" & x"d2d" => data <= x"e5";
when "10" & x"d2e" => data <= x"2d";
when "10" & x"d2f" => data <= x"90";
when "10" & x"d30" => data <= x"21";
when "10" & x"d31" => data <= x"e5";
when "10" & x"d32" => data <= x"36";
when "10" & x"d33" => data <= x"90";
when "10" & x"d34" => data <= x"1d";
when "10" & x"d35" => data <= x"69";
when "10" & x"d36" => data <= x"00";
when "10" & x"d37" => data <= x"85";
when "10" & x"d38" => data <= x"2b";
when "10" & x"d39" => data <= x"20";
when "10" & x"d3a" => data <= x"dc";
when "10" & x"d3b" => data <= x"bd";
when "10" & x"d3c" => data <= x"a0";
when "10" & x"d3d" => data <= x"00";
when "10" & x"d3e" => data <= x"a6";
when "10" & x"d3f" => data <= x"36";
when "10" & x"d40" => data <= x"f0";
when "10" & x"d41" => data <= x"0b";
when "10" & x"d42" => data <= x"b1";
when "10" & x"d43" => data <= x"37";
when "10" & x"d44" => data <= x"d9";
when "10" & x"d45" => data <= x"00";
when "10" & x"d46" => data <= x"06";
when "10" & x"d47" => data <= x"d0";
when "10" & x"d48" => data <= x"10";
when "10" & x"d49" => data <= x"c8";
when "10" & x"d4a" => data <= x"ca";
when "10" & x"d4b" => data <= x"d0";
when "10" & x"d4c" => data <= x"f5";
when "10" & x"d4d" => data <= x"a5";
when "10" & x"d4e" => data <= x"2a";
when "10" & x"d4f" => data <= x"4c";
when "10" & x"d50" => data <= x"d8";
when "10" & x"d51" => data <= x"ae";
when "10" & x"d52" => data <= x"20";
when "10" & x"d53" => data <= x"dc";
when "10" & x"d54" => data <= x"bd";
when "10" & x"d55" => data <= x"a9";
when "10" & x"d56" => data <= x"00";
when "10" & x"d57" => data <= x"f0";
when "10" & x"d58" => data <= x"f6";
when "10" & x"d59" => data <= x"e6";
when "10" & x"d5a" => data <= x"2a";
when "10" & x"d5b" => data <= x"c6";
when "10" & x"d5c" => data <= x"2b";
when "10" & x"d5d" => data <= x"f0";
when "10" & x"d5e" => data <= x"f6";
when "10" & x"d5f" => data <= x"e6";
when "10" & x"d60" => data <= x"37";
when "10" & x"d61" => data <= x"d0";
when "10" & x"d62" => data <= x"d9";
when "10" & x"d63" => data <= x"e6";
when "10" & x"d64" => data <= x"38";
when "10" & x"d65" => data <= x"d0";
when "10" & x"d66" => data <= x"d5";
when "10" & x"d67" => data <= x"4c";
when "10" & x"d68" => data <= x"0e";
when "10" & x"d69" => data <= x"8c";
when "10" & x"d6a" => data <= x"20";
when "10" & x"d6b" => data <= x"ec";
when "10" & x"d6c" => data <= x"ad";
when "10" & x"d6d" => data <= x"f0";
when "10" & x"d6e" => data <= x"f8";
when "10" & x"d6f" => data <= x"30";
when "10" & x"d70" => data <= x"06";
when "10" & x"d71" => data <= x"24";
when "10" & x"d72" => data <= x"2d";
when "10" & x"d73" => data <= x"30";
when "10" & x"d74" => data <= x"1e";
when "10" & x"d75" => data <= x"10";
when "10" & x"d76" => data <= x"33";
when "10" & x"d77" => data <= x"20";
when "10" & x"d78" => data <= x"da";
when "10" & x"d79" => data <= x"a1";
when "10" & x"d7a" => data <= x"10";
when "10" & x"d7b" => data <= x"0d";
when "10" & x"d7c" => data <= x"30";
when "10" & x"d7d" => data <= x"05";
when "10" & x"d7e" => data <= x"20";
when "10" & x"d7f" => data <= x"da";
when "10" & x"d80" => data <= x"a1";
when "10" & x"d81" => data <= x"f0";
when "10" & x"d82" => data <= x"06";
when "10" & x"d83" => data <= x"a5";
when "10" & x"d84" => data <= x"2e";
when "10" & x"d85" => data <= x"49";
when "10" & x"d86" => data <= x"80";
when "10" & x"d87" => data <= x"85";
when "10" & x"d88" => data <= x"2e";
when "10" & x"d89" => data <= x"a9";
when "10" & x"d8a" => data <= x"ff";
when "10" & x"d8b" => data <= x"60";
when "10" & x"d8c" => data <= x"20";
when "10" & x"d8d" => data <= x"02";
when "10" & x"d8e" => data <= x"ae";
when "10" & x"d8f" => data <= x"f0";
when "10" & x"d90" => data <= x"d6";
when "10" & x"d91" => data <= x"30";
when "10" & x"d92" => data <= x"eb";
when "10" & x"d93" => data <= x"38";
when "10" & x"d94" => data <= x"a9";
when "10" & x"d95" => data <= x"00";
when "10" & x"d96" => data <= x"a8";
when "10" & x"d97" => data <= x"e5";
when "10" & x"d98" => data <= x"2a";
when "10" & x"d99" => data <= x"85";
when "10" & x"d9a" => data <= x"2a";
when "10" & x"d9b" => data <= x"98";
when "10" & x"d9c" => data <= x"e5";
when "10" & x"d9d" => data <= x"2b";
when "10" & x"d9e" => data <= x"85";
when "10" & x"d9f" => data <= x"2b";
when "10" & x"da0" => data <= x"98";
when "10" & x"da1" => data <= x"e5";
when "10" & x"da2" => data <= x"2c";
when "10" & x"da3" => data <= x"85";
when "10" & x"da4" => data <= x"2c";
when "10" & x"da5" => data <= x"98";
when "10" & x"da6" => data <= x"e5";
when "10" & x"da7" => data <= x"2d";
when "10" & x"da8" => data <= x"85";
when "10" & x"da9" => data <= x"2d";
when "10" & x"daa" => data <= x"a9";
when "10" & x"dab" => data <= x"40";
when "10" & x"dac" => data <= x"60";
when "10" & x"dad" => data <= x"20";
when "10" & x"dae" => data <= x"8c";
when "10" & x"daf" => data <= x"8a";
when "10" & x"db0" => data <= x"c9";
when "10" & x"db1" => data <= x"22";
when "10" & x"db2" => data <= x"f0";
when "10" & x"db3" => data <= x"15";
when "10" & x"db4" => data <= x"a2";
when "10" & x"db5" => data <= x"00";
when "10" & x"db6" => data <= x"b1";
when "10" & x"db7" => data <= x"19";
when "10" & x"db8" => data <= x"9d";
when "10" & x"db9" => data <= x"00";
when "10" & x"dba" => data <= x"06";
when "10" & x"dbb" => data <= x"c8";
when "10" & x"dbc" => data <= x"e8";
when "10" & x"dbd" => data <= x"c9";
when "10" & x"dbe" => data <= x"0d";
when "10" & x"dbf" => data <= x"f0";
when "10" & x"dc0" => data <= x"04";
when "10" & x"dc1" => data <= x"c9";
when "10" & x"dc2" => data <= x"2c";
when "10" & x"dc3" => data <= x"d0";
when "10" & x"dc4" => data <= x"f1";
when "10" & x"dc5" => data <= x"88";
when "10" & x"dc6" => data <= x"4c";
when "10" & x"dc7" => data <= x"e1";
when "10" & x"dc8" => data <= x"ad";
when "10" & x"dc9" => data <= x"a2";
when "10" & x"dca" => data <= x"00";
when "10" & x"dcb" => data <= x"c8";
when "10" & x"dcc" => data <= x"b1";
when "10" & x"dcd" => data <= x"19";
when "10" & x"dce" => data <= x"c9";
when "10" & x"dcf" => data <= x"0d";
when "10" & x"dd0" => data <= x"f0";
when "10" & x"dd1" => data <= x"17";
when "10" & x"dd2" => data <= x"c8";
when "10" & x"dd3" => data <= x"9d";
when "10" & x"dd4" => data <= x"00";
when "10" & x"dd5" => data <= x"06";
when "10" & x"dd6" => data <= x"e8";
when "10" & x"dd7" => data <= x"c9";
when "10" & x"dd8" => data <= x"22";
when "10" & x"dd9" => data <= x"d0";
when "10" & x"dda" => data <= x"f1";
when "10" & x"ddb" => data <= x"b1";
when "10" & x"ddc" => data <= x"19";
when "10" & x"ddd" => data <= x"c9";
when "10" & x"dde" => data <= x"22";
when "10" & x"ddf" => data <= x"f0";
when "10" & x"de0" => data <= x"ea";
when "10" & x"de1" => data <= x"ca";
when "10" & x"de2" => data <= x"86";
when "10" & x"de3" => data <= x"36";
when "10" & x"de4" => data <= x"84";
when "10" & x"de5" => data <= x"1b";
when "10" & x"de6" => data <= x"a9";
when "10" & x"de7" => data <= x"00";
when "10" & x"de8" => data <= x"60";
when "10" & x"de9" => data <= x"4c";
when "10" & x"dea" => data <= x"98";
when "10" & x"deb" => data <= x"8e";
when "10" & x"dec" => data <= x"a4";
when "10" & x"ded" => data <= x"1b";
when "10" & x"dee" => data <= x"e6";
when "10" & x"def" => data <= x"1b";
when "10" & x"df0" => data <= x"b1";
when "10" & x"df1" => data <= x"19";
when "10" & x"df2" => data <= x"c9";
when "10" & x"df3" => data <= x"20";
when "10" & x"df4" => data <= x"f0";
when "10" & x"df5" => data <= x"f6";
when "10" & x"df6" => data <= x"c9";
when "10" & x"df7" => data <= x"2d";
when "10" & x"df8" => data <= x"f0";
when "10" & x"df9" => data <= x"92";
when "10" & x"dfa" => data <= x"c9";
when "10" & x"dfb" => data <= x"22";
when "10" & x"dfc" => data <= x"f0";
when "10" & x"dfd" => data <= x"cb";
when "10" & x"dfe" => data <= x"c9";
when "10" & x"dff" => data <= x"2b";
when "10" & x"e00" => data <= x"d0";
when "10" & x"e01" => data <= x"03";
when "10" & x"e02" => data <= x"20";
when "10" & x"e03" => data <= x"8c";
when "10" & x"e04" => data <= x"8a";
when "10" & x"e05" => data <= x"c9";
when "10" & x"e06" => data <= x"8e";
when "10" & x"e07" => data <= x"90";
when "10" & x"e08" => data <= x"07";
when "10" & x"e09" => data <= x"c9";
when "10" & x"e0a" => data <= x"c6";
when "10" & x"e0b" => data <= x"b0";
when "10" & x"e0c" => data <= x"36";
when "10" & x"e0d" => data <= x"4c";
when "10" & x"e0e" => data <= x"b1";
when "10" & x"e0f" => data <= x"8b";
when "10" & x"e10" => data <= x"c9";
when "10" & x"e11" => data <= x"3f";
when "10" & x"e12" => data <= x"b0";
when "10" & x"e13" => data <= x"0c";
when "10" & x"e14" => data <= x"c9";
when "10" & x"e15" => data <= x"2e";
when "10" & x"e16" => data <= x"b0";
when "10" & x"e17" => data <= x"12";
when "10" & x"e18" => data <= x"c9";
when "10" & x"e19" => data <= x"26";
when "10" & x"e1a" => data <= x"f0";
when "10" & x"e1b" => data <= x"51";
when "10" & x"e1c" => data <= x"c9";
when "10" & x"e1d" => data <= x"28";
when "10" & x"e1e" => data <= x"f0";
when "10" & x"e1f" => data <= x"36";
when "10" & x"e20" => data <= x"c6";
when "10" & x"e21" => data <= x"1b";
when "10" & x"e22" => data <= x"20";
when "10" & x"e23" => data <= x"dd";
when "10" & x"e24" => data <= x"95";
when "10" & x"e25" => data <= x"f0";
when "10" & x"e26" => data <= x"09";
when "10" & x"e27" => data <= x"4c";
when "10" & x"e28" => data <= x"2c";
when "10" & x"e29" => data <= x"b3";
when "10" & x"e2a" => data <= x"20";
when "10" & x"e2b" => data <= x"7b";
when "10" & x"e2c" => data <= x"a0";
when "10" & x"e2d" => data <= x"90";
when "10" & x"e2e" => data <= x"14";
when "10" & x"e2f" => data <= x"60";
when "10" & x"e30" => data <= x"a5";
when "10" & x"e31" => data <= x"28";
when "10" & x"e32" => data <= x"29";
when "10" & x"e33" => data <= x"02";
when "10" & x"e34" => data <= x"d0";
when "10" & x"e35" => data <= x"0d";
when "10" & x"e36" => data <= x"b0";
when "10" & x"e37" => data <= x"0b";
when "10" & x"e38" => data <= x"86";
when "10" & x"e39" => data <= x"1b";
when "10" & x"e3a" => data <= x"ad";
when "10" & x"e3b" => data <= x"40";
when "10" & x"e3c" => data <= x"04";
when "10" & x"e3d" => data <= x"ac";
when "10" & x"e3e" => data <= x"41";
when "10" & x"e3f" => data <= x"04";
when "10" & x"e40" => data <= x"4c";
when "10" & x"e41" => data <= x"ea";
when "10" & x"e42" => data <= x"ae";
when "10" & x"e43" => data <= x"00";
when "10" & x"e44" => data <= x"1a";
when "10" & x"e45" => data <= x"4e";
when "10" & x"e46" => data <= x"6f";
when "10" & x"e47" => data <= x"20";
when "10" & x"e48" => data <= x"73";
when "10" & x"e49" => data <= x"75";
when "10" & x"e4a" => data <= x"63";
when "10" & x"e4b" => data <= x"68";
when "10" & x"e4c" => data <= x"20";
when "10" & x"e4d" => data <= x"76";
when "10" & x"e4e" => data <= x"61";
when "10" & x"e4f" => data <= x"72";
when "10" & x"e50" => data <= x"69";
when "10" & x"e51" => data <= x"61";
when "10" & x"e52" => data <= x"62";
when "10" & x"e53" => data <= x"6c";
when "10" & x"e54" => data <= x"65";
when "10" & x"e55" => data <= x"00";
when "10" & x"e56" => data <= x"20";
when "10" & x"e57" => data <= x"29";
when "10" & x"e58" => data <= x"9b";
when "10" & x"e59" => data <= x"e6";
when "10" & x"e5a" => data <= x"1b";
when "10" & x"e5b" => data <= x"e0";
when "10" & x"e5c" => data <= x"29";
when "10" & x"e5d" => data <= x"d0";
when "10" & x"e5e" => data <= x"02";
when "10" & x"e5f" => data <= x"a8";
when "10" & x"e60" => data <= x"60";
when "10" & x"e61" => data <= x"00";
when "10" & x"e62" => data <= x"1b";
when "10" & x"e63" => data <= x"4d";
when "10" & x"e64" => data <= x"69";
when "10" & x"e65" => data <= x"73";
when "10" & x"e66" => data <= x"73";
when "10" & x"e67" => data <= x"69";
when "10" & x"e68" => data <= x"6e";
when "10" & x"e69" => data <= x"67";
when "10" & x"e6a" => data <= x"20";
when "10" & x"e6b" => data <= x"29";
when "10" & x"e6c" => data <= x"00";
when "10" & x"e6d" => data <= x"a2";
when "10" & x"e6e" => data <= x"00";
when "10" & x"e6f" => data <= x"86";
when "10" & x"e70" => data <= x"2a";
when "10" & x"e71" => data <= x"86";
when "10" & x"e72" => data <= x"2b";
when "10" & x"e73" => data <= x"86";
when "10" & x"e74" => data <= x"2c";
when "10" & x"e75" => data <= x"86";
when "10" & x"e76" => data <= x"2d";
when "10" & x"e77" => data <= x"a4";
when "10" & x"e78" => data <= x"1b";
when "10" & x"e79" => data <= x"b1";
when "10" & x"e7a" => data <= x"19";
when "10" & x"e7b" => data <= x"c9";
when "10" & x"e7c" => data <= x"30";
when "10" & x"e7d" => data <= x"90";
when "10" & x"e7e" => data <= x"23";
when "10" & x"e7f" => data <= x"c9";
when "10" & x"e80" => data <= x"3a";
when "10" & x"e81" => data <= x"90";
when "10" & x"e82" => data <= x"0a";
when "10" & x"e83" => data <= x"e9";
when "10" & x"e84" => data <= x"37";
when "10" & x"e85" => data <= x"c9";
when "10" & x"e86" => data <= x"0a";
when "10" & x"e87" => data <= x"90";
when "10" & x"e88" => data <= x"19";
when "10" & x"e89" => data <= x"c9";
when "10" & x"e8a" => data <= x"10";
when "10" & x"e8b" => data <= x"b0";
when "10" & x"e8c" => data <= x"15";
when "10" & x"e8d" => data <= x"0a";
when "10" & x"e8e" => data <= x"0a";
when "10" & x"e8f" => data <= x"0a";
when "10" & x"e90" => data <= x"0a";
when "10" & x"e91" => data <= x"a2";
when "10" & x"e92" => data <= x"03";
when "10" & x"e93" => data <= x"0a";
when "10" & x"e94" => data <= x"26";
when "10" & x"e95" => data <= x"2a";
when "10" & x"e96" => data <= x"26";
when "10" & x"e97" => data <= x"2b";
when "10" & x"e98" => data <= x"26";
when "10" & x"e99" => data <= x"2c";
when "10" & x"e9a" => data <= x"26";
when "10" & x"e9b" => data <= x"2d";
when "10" & x"e9c" => data <= x"ca";
when "10" & x"e9d" => data <= x"10";
when "10" & x"e9e" => data <= x"f4";
when "10" & x"e9f" => data <= x"c8";
when "10" & x"ea0" => data <= x"d0";
when "10" & x"ea1" => data <= x"d7";
when "10" & x"ea2" => data <= x"8a";
when "10" & x"ea3" => data <= x"10";
when "10" & x"ea4" => data <= x"05";
when "10" & x"ea5" => data <= x"84";
when "10" & x"ea6" => data <= x"1b";
when "10" & x"ea7" => data <= x"a9";
when "10" & x"ea8" => data <= x"40";
when "10" & x"ea9" => data <= x"60";
when "10" & x"eaa" => data <= x"00";
when "10" & x"eab" => data <= x"1c";
when "10" & x"eac" => data <= x"42";
when "10" & x"ead" => data <= x"61";
when "10" & x"eae" => data <= x"64";
when "10" & x"eaf" => data <= x"20";
when "10" & x"eb0" => data <= x"48";
when "10" & x"eb1" => data <= x"45";
when "10" & x"eb2" => data <= x"58";
when "10" & x"eb3" => data <= x"00";
when "10" & x"eb4" => data <= x"a2";
when "10" & x"eb5" => data <= x"2a";
when "10" & x"eb6" => data <= x"a0";
when "10" & x"eb7" => data <= x"00";
when "10" & x"eb8" => data <= x"a9";
when "10" & x"eb9" => data <= x"01";
when "10" & x"eba" => data <= x"20";
when "10" & x"ebb" => data <= x"f1";
when "10" & x"ebc" => data <= x"ff";
when "10" & x"ebd" => data <= x"a9";
when "10" & x"ebe" => data <= x"40";
when "10" & x"ebf" => data <= x"60";
when "10" & x"ec0" => data <= x"a9";
when "10" & x"ec1" => data <= x"00";
when "10" & x"ec2" => data <= x"a4";
when "10" & x"ec3" => data <= x"18";
when "10" & x"ec4" => data <= x"4c";
when "10" & x"ec5" => data <= x"ea";
when "10" & x"ec6" => data <= x"ae";
when "10" & x"ec7" => data <= x"4c";
when "10" & x"ec8" => data <= x"43";
when "10" & x"ec9" => data <= x"ae";
when "10" & x"eca" => data <= x"a9";
when "10" & x"ecb" => data <= x"00";
when "10" & x"ecc" => data <= x"f0";
when "10" & x"ecd" => data <= x"0a";
when "10" & x"ece" => data <= x"4c";
when "10" & x"ecf" => data <= x"0e";
when "10" & x"ed0" => data <= x"8c";
when "10" & x"ed1" => data <= x"20";
when "10" & x"ed2" => data <= x"ec";
when "10" & x"ed3" => data <= x"ad";
when "10" & x"ed4" => data <= x"d0";
when "10" & x"ed5" => data <= x"f8";
when "10" & x"ed6" => data <= x"a5";
when "10" & x"ed7" => data <= x"36";
when "10" & x"ed8" => data <= x"a0";
when "10" & x"ed9" => data <= x"00";
when "10" & x"eda" => data <= x"f0";
when "10" & x"edb" => data <= x"0e";
when "10" & x"edc" => data <= x"a4";
when "10" & x"edd" => data <= x"1b";
when "10" & x"ede" => data <= x"b1";
when "10" & x"edf" => data <= x"19";
when "10" & x"ee0" => data <= x"c9";
when "10" & x"ee1" => data <= x"50";
when "10" & x"ee2" => data <= x"d0";
when "10" & x"ee3" => data <= x"e3";
when "10" & x"ee4" => data <= x"e6";
when "10" & x"ee5" => data <= x"1b";
when "10" & x"ee6" => data <= x"a5";
when "10" & x"ee7" => data <= x"12";
when "10" & x"ee8" => data <= x"a4";
when "10" & x"ee9" => data <= x"13";
when "10" & x"eea" => data <= x"85";
when "10" & x"eeb" => data <= x"2a";
when "10" & x"eec" => data <= x"84";
when "10" & x"eed" => data <= x"2b";
when "10" & x"eee" => data <= x"a9";
when "10" & x"eef" => data <= x"00";
when "10" & x"ef0" => data <= x"85";
when "10" & x"ef1" => data <= x"2c";
when "10" & x"ef2" => data <= x"85";
when "10" & x"ef3" => data <= x"2d";
when "10" & x"ef4" => data <= x"a9";
when "10" & x"ef5" => data <= x"40";
when "10" & x"ef6" => data <= x"60";
when "10" & x"ef7" => data <= x"a5";
when "10" & x"ef8" => data <= x"1e";
when "10" & x"ef9" => data <= x"4c";
when "10" & x"efa" => data <= x"d8";
when "10" & x"efb" => data <= x"ae";
when "10" & x"efc" => data <= x"a5";
when "10" & x"efd" => data <= x"00";
when "10" & x"efe" => data <= x"a4";
when "10" & x"eff" => data <= x"01";
when "10" & x"f00" => data <= x"4c";
when "10" & x"f01" => data <= x"ea";
when "10" & x"f02" => data <= x"ae";
when "10" & x"f03" => data <= x"a5";
when "10" & x"f04" => data <= x"06";
when "10" & x"f05" => data <= x"a4";
when "10" & x"f06" => data <= x"07";
when "10" & x"f07" => data <= x"4c";
when "10" & x"f08" => data <= x"ea";
when "10" & x"f09" => data <= x"ae";
when "10" & x"f0a" => data <= x"e6";
when "10" & x"f0b" => data <= x"1b";
when "10" & x"f0c" => data <= x"20";
when "10" & x"f0d" => data <= x"56";
when "10" & x"f0e" => data <= x"ae";
when "10" & x"f0f" => data <= x"20";
when "10" & x"f10" => data <= x"f0";
when "10" & x"f11" => data <= x"92";
when "10" & x"f12" => data <= x"a5";
when "10" & x"f13" => data <= x"2d";
when "10" & x"f14" => data <= x"30";
when "10" & x"f15" => data <= x"29";
when "10" & x"f16" => data <= x"05";
when "10" & x"f17" => data <= x"2c";
when "10" & x"f18" => data <= x"05";
when "10" & x"f19" => data <= x"2b";
when "10" & x"f1a" => data <= x"d0";
when "10" & x"f1b" => data <= x"08";
when "10" & x"f1c" => data <= x"a5";
when "10" & x"f1d" => data <= x"2a";
when "10" & x"f1e" => data <= x"f0";
when "10" & x"f1f" => data <= x"4c";
when "10" & x"f20" => data <= x"c9";
when "10" & x"f21" => data <= x"01";
when "10" & x"f22" => data <= x"f0";
when "10" & x"f23" => data <= x"45";
when "10" & x"f24" => data <= x"20";
when "10" & x"f25" => data <= x"be";
when "10" & x"f26" => data <= x"a2";
when "10" & x"f27" => data <= x"20";
when "10" & x"f28" => data <= x"51";
when "10" & x"f29" => data <= x"bd";
when "10" & x"f2a" => data <= x"20";
when "10" & x"f2b" => data <= x"69";
when "10" & x"f2c" => data <= x"af";
when "10" & x"f2d" => data <= x"20";
when "10" & x"f2e" => data <= x"7e";
when "10" & x"f2f" => data <= x"bd";
when "10" & x"f30" => data <= x"20";
when "10" & x"f31" => data <= x"06";
when "10" & x"f32" => data <= x"a6";
when "10" & x"f33" => data <= x"20";
when "10" & x"f34" => data <= x"03";
when "10" & x"f35" => data <= x"a3";
when "10" & x"f36" => data <= x"20";
when "10" & x"f37" => data <= x"e4";
when "10" & x"f38" => data <= x"a3";
when "10" & x"f39" => data <= x"20";
when "10" & x"f3a" => data <= x"22";
when "10" & x"f3b" => data <= x"92";
when "10" & x"f3c" => data <= x"a9";
when "10" & x"f3d" => data <= x"40";
when "10" & x"f3e" => data <= x"60";
when "10" & x"f3f" => data <= x"a2";
when "10" & x"f40" => data <= x"0d";
when "10" & x"f41" => data <= x"20";
when "10" & x"f42" => data <= x"44";
when "10" & x"f43" => data <= x"be";
when "10" & x"f44" => data <= x"a9";
when "10" & x"f45" => data <= x"40";
when "10" & x"f46" => data <= x"85";
when "10" & x"f47" => data <= x"11";
when "10" & x"f48" => data <= x"60";
when "10" & x"f49" => data <= x"a4";
when "10" & x"f4a" => data <= x"1b";
when "10" & x"f4b" => data <= x"b1";
when "10" & x"f4c" => data <= x"19";
when "10" & x"f4d" => data <= x"c9";
when "10" & x"f4e" => data <= x"28";
when "10" & x"f4f" => data <= x"f0";
when "10" & x"f50" => data <= x"b9";
when "10" & x"f51" => data <= x"20";
when "10" & x"f52" => data <= x"87";
when "10" & x"f53" => data <= x"af";
when "10" & x"f54" => data <= x"a2";
when "10" & x"f55" => data <= x"0d";
when "10" & x"f56" => data <= x"b5";
when "10" & x"f57" => data <= x"00";
when "10" & x"f58" => data <= x"85";
when "10" & x"f59" => data <= x"2a";
when "10" & x"f5a" => data <= x"b5";
when "10" & x"f5b" => data <= x"01";
when "10" & x"f5c" => data <= x"85";
when "10" & x"f5d" => data <= x"2b";
when "10" & x"f5e" => data <= x"b5";
when "10" & x"f5f" => data <= x"02";
when "10" & x"f60" => data <= x"85";
when "10" & x"f61" => data <= x"2c";
when "10" & x"f62" => data <= x"b5";
when "10" & x"f63" => data <= x"03";
when "10" & x"f64" => data <= x"85";
when "10" & x"f65" => data <= x"2d";
when "10" & x"f66" => data <= x"a9";
when "10" & x"f67" => data <= x"40";
when "10" & x"f68" => data <= x"60";
when "10" & x"f69" => data <= x"20";
when "10" & x"f6a" => data <= x"87";
when "10" & x"f6b" => data <= x"af";
when "10" & x"f6c" => data <= x"a2";
when "10" & x"f6d" => data <= x"00";
when "10" & x"f6e" => data <= x"86";
when "10" & x"f6f" => data <= x"2e";
when "10" & x"f70" => data <= x"86";
when "10" & x"f71" => data <= x"2f";
when "10" & x"f72" => data <= x"86";
when "10" & x"f73" => data <= x"35";
when "10" & x"f74" => data <= x"a9";
when "10" & x"f75" => data <= x"80";
when "10" & x"f76" => data <= x"85";
when "10" & x"f77" => data <= x"30";
when "10" & x"f78" => data <= x"b5";
when "10" & x"f79" => data <= x"0d";
when "10" & x"f7a" => data <= x"95";
when "10" & x"f7b" => data <= x"31";
when "10" & x"f7c" => data <= x"e8";
when "10" & x"f7d" => data <= x"e0";
when "10" & x"f7e" => data <= x"04";
when "10" & x"f7f" => data <= x"d0";
when "10" & x"f80" => data <= x"f7";
when "10" & x"f81" => data <= x"20";
when "10" & x"f82" => data <= x"59";
when "10" & x"f83" => data <= x"a6";
when "10" & x"f84" => data <= x"a9";
when "10" & x"f85" => data <= x"ff";
when "10" & x"f86" => data <= x"60";
when "10" & x"f87" => data <= x"a0";
when "10" & x"f88" => data <= x"20";
when "10" & x"f89" => data <= x"a5";
when "10" & x"f8a" => data <= x"0f";
when "10" & x"f8b" => data <= x"4a";
when "10" & x"f8c" => data <= x"4a";
when "10" & x"f8d" => data <= x"4a";
when "10" & x"f8e" => data <= x"45";
when "10" & x"f8f" => data <= x"11";
when "10" & x"f90" => data <= x"6a";
when "10" & x"f91" => data <= x"26";
when "10" & x"f92" => data <= x"0d";
when "10" & x"f93" => data <= x"26";
when "10" & x"f94" => data <= x"0e";
when "10" & x"f95" => data <= x"26";
when "10" & x"f96" => data <= x"0f";
when "10" & x"f97" => data <= x"26";
when "10" & x"f98" => data <= x"10";
when "10" & x"f99" => data <= x"26";
when "10" & x"f9a" => data <= x"11";
when "10" & x"f9b" => data <= x"88";
when "10" & x"f9c" => data <= x"d0";
when "10" & x"f9d" => data <= x"eb";
when "10" & x"f9e" => data <= x"60";
when "10" & x"f9f" => data <= x"a4";
when "10" & x"fa0" => data <= x"09";
when "10" & x"fa1" => data <= x"a5";
when "10" & x"fa2" => data <= x"08";
when "10" & x"fa3" => data <= x"4c";
when "10" & x"fa4" => data <= x"ea";
when "10" & x"fa5" => data <= x"ae";
when "10" & x"fa6" => data <= x"a0";
when "10" & x"fa7" => data <= x"00";
when "10" & x"fa8" => data <= x"b1";
when "10" & x"fa9" => data <= x"fd";
when "10" & x"faa" => data <= x"4c";
when "10" & x"fab" => data <= x"ea";
when "10" & x"fac" => data <= x"ae";
when "10" & x"fad" => data <= x"20";
when "10" & x"fae" => data <= x"e3";
when "10" & x"faf" => data <= x"92";
when "10" & x"fb0" => data <= x"a9";
when "10" & x"fb1" => data <= x"81";
when "10" & x"fb2" => data <= x"a6";
when "10" & x"fb3" => data <= x"2a";
when "10" & x"fb4" => data <= x"a4";
when "10" & x"fb5" => data <= x"2b";
when "10" & x"fb6" => data <= x"4c";
when "10" & x"fb7" => data <= x"f4";
when "10" & x"fb8" => data <= x"ff";
when "10" & x"fb9" => data <= x"20";
when "10" & x"fba" => data <= x"e0";
when "10" & x"fbb" => data <= x"ff";
when "10" & x"fbc" => data <= x"4c";
when "10" & x"fbd" => data <= x"d8";
when "10" & x"fbe" => data <= x"ae";
when "10" & x"fbf" => data <= x"20";
when "10" & x"fc0" => data <= x"e0";
when "10" & x"fc1" => data <= x"ff";
when "10" & x"fc2" => data <= x"8d";
when "10" & x"fc3" => data <= x"00";
when "10" & x"fc4" => data <= x"06";
when "10" & x"fc5" => data <= x"a9";
when "10" & x"fc6" => data <= x"01";
when "10" & x"fc7" => data <= x"85";
when "10" & x"fc8" => data <= x"36";
when "10" & x"fc9" => data <= x"a9";
when "10" & x"fca" => data <= x"00";
when "10" & x"fcb" => data <= x"60";
when "10" & x"fcc" => data <= x"20";
when "10" & x"fcd" => data <= x"29";
when "10" & x"fce" => data <= x"9b";
when "10" & x"fcf" => data <= x"d0";
when "10" & x"fd0" => data <= x"62";
when "10" & x"fd1" => data <= x"e0";
when "10" & x"fd2" => data <= x"2c";
when "10" & x"fd3" => data <= x"d0";
when "10" & x"fd4" => data <= x"61";
when "10" & x"fd5" => data <= x"e6";
when "10" & x"fd6" => data <= x"1b";
when "10" & x"fd7" => data <= x"20";
when "10" & x"fd8" => data <= x"b2";
when "10" & x"fd9" => data <= x"bd";
when "10" & x"fda" => data <= x"20";
when "10" & x"fdb" => data <= x"56";
when "10" & x"fdc" => data <= x"ae";
when "10" & x"fdd" => data <= x"20";
when "10" & x"fde" => data <= x"f0";
when "10" & x"fdf" => data <= x"92";
when "10" & x"fe0" => data <= x"20";
when "10" & x"fe1" => data <= x"cb";
when "10" & x"fe2" => data <= x"bd";
when "10" & x"fe3" => data <= x"a5";
when "10" & x"fe4" => data <= x"2a";
when "10" & x"fe5" => data <= x"c5";
when "10" & x"fe6" => data <= x"36";
when "10" & x"fe7" => data <= x"b0";
when "10" & x"fe8" => data <= x"02";
when "10" & x"fe9" => data <= x"85";
when "10" & x"fea" => data <= x"36";
when "10" & x"feb" => data <= x"a9";
when "10" & x"fec" => data <= x"00";
when "10" & x"fed" => data <= x"60";
when "10" & x"fee" => data <= x"20";
when "10" & x"fef" => data <= x"29";
when "10" & x"ff0" => data <= x"9b";
when "10" & x"ff1" => data <= x"d0";
when "10" & x"ff2" => data <= x"40";
when "10" & x"ff3" => data <= x"e0";
when "10" & x"ff4" => data <= x"2c";
when "10" & x"ff5" => data <= x"d0";
when "10" & x"ff6" => data <= x"3f";
when "10" & x"ff7" => data <= x"e6";
when "10" & x"ff8" => data <= x"1b";
when "10" & x"ff9" => data <= x"20";
when "10" & x"ffa" => data <= x"b2";
when "10" & x"ffb" => data <= x"bd";
when "10" & x"ffc" => data <= x"20";
when "10" & x"ffd" => data <= x"56";
when "10" & x"ffe" => data <= x"ae";
when "10" & x"fff" => data <= x"20";
when "11" & x"000" => data <= x"f0";
when "11" & x"001" => data <= x"92";
when "11" & x"002" => data <= x"20";
when "11" & x"003" => data <= x"cb";
when "11" & x"004" => data <= x"bd";
when "11" & x"005" => data <= x"a5";
when "11" & x"006" => data <= x"36";
when "11" & x"007" => data <= x"38";
when "11" & x"008" => data <= x"e5";
when "11" & x"009" => data <= x"2a";
when "11" & x"00a" => data <= x"90";
when "11" & x"00b" => data <= x"17";
when "11" & x"00c" => data <= x"f0";
when "11" & x"00d" => data <= x"17";
when "11" & x"00e" => data <= x"aa";
when "11" & x"00f" => data <= x"a5";
when "11" & x"010" => data <= x"2a";
when "11" & x"011" => data <= x"85";
when "11" & x"012" => data <= x"36";
when "11" & x"013" => data <= x"f0";
when "11" & x"014" => data <= x"10";
when "11" & x"015" => data <= x"a0";
when "11" & x"016" => data <= x"00";
when "11" & x"017" => data <= x"bd";
when "11" & x"018" => data <= x"00";
when "11" & x"019" => data <= x"06";
when "11" & x"01a" => data <= x"99";
when "11" & x"01b" => data <= x"00";
when "11" & x"01c" => data <= x"06";
when "11" & x"01d" => data <= x"e8";
when "11" & x"01e" => data <= x"c8";
when "11" & x"01f" => data <= x"c6";
when "11" & x"020" => data <= x"2a";
when "11" & x"021" => data <= x"d0";
when "11" & x"022" => data <= x"f4";
when "11" & x"023" => data <= x"a9";
when "11" & x"024" => data <= x"00";
when "11" & x"025" => data <= x"60";
when "11" & x"026" => data <= x"20";
when "11" & x"027" => data <= x"ad";
when "11" & x"028" => data <= x"af";
when "11" & x"029" => data <= x"8a";
when "11" & x"02a" => data <= x"c0";
when "11" & x"02b" => data <= x"00";
when "11" & x"02c" => data <= x"f0";
when "11" & x"02d" => data <= x"94";
when "11" & x"02e" => data <= x"a9";
when "11" & x"02f" => data <= x"00";
when "11" & x"030" => data <= x"85";
when "11" & x"031" => data <= x"36";
when "11" & x"032" => data <= x"60";
when "11" & x"033" => data <= x"4c";
when "11" & x"034" => data <= x"0e";
when "11" & x"035" => data <= x"8c";
when "11" & x"036" => data <= x"4c";
when "11" & x"037" => data <= x"a2";
when "11" & x"038" => data <= x"8a";
when "11" & x"039" => data <= x"20";
when "11" & x"03a" => data <= x"29";
when "11" & x"03b" => data <= x"9b";
when "11" & x"03c" => data <= x"d0";
when "11" & x"03d" => data <= x"f5";
when "11" & x"03e" => data <= x"e0";
when "11" & x"03f" => data <= x"2c";
when "11" & x"040" => data <= x"d0";
when "11" & x"041" => data <= x"f4";
when "11" & x"042" => data <= x"20";
when "11" & x"043" => data <= x"b2";
when "11" & x"044" => data <= x"bd";
when "11" & x"045" => data <= x"e6";
when "11" & x"046" => data <= x"1b";
when "11" & x"047" => data <= x"20";
when "11" & x"048" => data <= x"dd";
when "11" & x"049" => data <= x"92";
when "11" & x"04a" => data <= x"a5";
when "11" & x"04b" => data <= x"2a";
when "11" & x"04c" => data <= x"48";
when "11" & x"04d" => data <= x"a9";
when "11" & x"04e" => data <= x"ff";
when "11" & x"04f" => data <= x"85";
when "11" & x"050" => data <= x"2a";
when "11" & x"051" => data <= x"e6";
when "11" & x"052" => data <= x"1b";
when "11" & x"053" => data <= x"e0";
when "11" & x"054" => data <= x"29";
when "11" & x"055" => data <= x"f0";
when "11" & x"056" => data <= x"0a";
when "11" & x"057" => data <= x"e0";
when "11" & x"058" => data <= x"2c";
when "11" & x"059" => data <= x"d0";
when "11" & x"05a" => data <= x"db";
when "11" & x"05b" => data <= x"20";
when "11" & x"05c" => data <= x"56";
when "11" & x"05d" => data <= x"ae";
when "11" & x"05e" => data <= x"20";
when "11" & x"05f" => data <= x"f0";
when "11" & x"060" => data <= x"92";
when "11" & x"061" => data <= x"20";
when "11" & x"062" => data <= x"cb";
when "11" & x"063" => data <= x"bd";
when "11" & x"064" => data <= x"68";
when "11" & x"065" => data <= x"a8";
when "11" & x"066" => data <= x"18";
when "11" & x"067" => data <= x"f0";
when "11" & x"068" => data <= x"06";
when "11" & x"069" => data <= x"e5";
when "11" & x"06a" => data <= x"36";
when "11" & x"06b" => data <= x"b0";
when "11" & x"06c" => data <= x"c1";
when "11" & x"06d" => data <= x"88";
when "11" & x"06e" => data <= x"98";
when "11" & x"06f" => data <= x"85";
when "11" & x"070" => data <= x"2c";
when "11" & x"071" => data <= x"aa";
when "11" & x"072" => data <= x"a0";
when "11" & x"073" => data <= x"00";
when "11" & x"074" => data <= x"a5";
when "11" & x"075" => data <= x"36";
when "11" & x"076" => data <= x"38";
when "11" & x"077" => data <= x"e5";
when "11" & x"078" => data <= x"2c";
when "11" & x"079" => data <= x"c5";
when "11" & x"07a" => data <= x"2a";
when "11" & x"07b" => data <= x"b0";
when "11" & x"07c" => data <= x"02";
when "11" & x"07d" => data <= x"85";
when "11" & x"07e" => data <= x"2a";
when "11" & x"07f" => data <= x"a5";
when "11" & x"080" => data <= x"2a";
when "11" & x"081" => data <= x"f0";
when "11" & x"082" => data <= x"ab";
when "11" & x"083" => data <= x"bd";
when "11" & x"084" => data <= x"00";
when "11" & x"085" => data <= x"06";
when "11" & x"086" => data <= x"99";
when "11" & x"087" => data <= x"00";
when "11" & x"088" => data <= x"06";
when "11" & x"089" => data <= x"c8";
when "11" & x"08a" => data <= x"e8";
when "11" & x"08b" => data <= x"c4";
when "11" & x"08c" => data <= x"2a";
when "11" & x"08d" => data <= x"d0";
when "11" & x"08e" => data <= x"f4";
when "11" & x"08f" => data <= x"84";
when "11" & x"090" => data <= x"36";
when "11" & x"091" => data <= x"a9";
when "11" & x"092" => data <= x"00";
when "11" & x"093" => data <= x"60";
when "11" & x"094" => data <= x"20";
when "11" & x"095" => data <= x"8c";
when "11" & x"096" => data <= x"8a";
when "11" & x"097" => data <= x"a0";
when "11" & x"098" => data <= x"ff";
when "11" & x"099" => data <= x"c9";
when "11" & x"09a" => data <= x"7e";
when "11" & x"09b" => data <= x"f0";
when "11" & x"09c" => data <= x"04";
when "11" & x"09d" => data <= x"a0";
when "11" & x"09e" => data <= x"00";
when "11" & x"09f" => data <= x"c6";
when "11" & x"0a0" => data <= x"1b";
when "11" & x"0a1" => data <= x"98";
when "11" & x"0a2" => data <= x"48";
when "11" & x"0a3" => data <= x"20";
when "11" & x"0a4" => data <= x"ec";
when "11" & x"0a5" => data <= x"ad";
when "11" & x"0a6" => data <= x"f0";
when "11" & x"0a7" => data <= x"17";
when "11" & x"0a8" => data <= x"a8";
when "11" & x"0a9" => data <= x"68";
when "11" & x"0aa" => data <= x"85";
when "11" & x"0ab" => data <= x"15";
when "11" & x"0ac" => data <= x"ad";
when "11" & x"0ad" => data <= x"03";
when "11" & x"0ae" => data <= x"04";
when "11" & x"0af" => data <= x"d0";
when "11" & x"0b0" => data <= x"08";
when "11" & x"0b1" => data <= x"85";
when "11" & x"0b2" => data <= x"37";
when "11" & x"0b3" => data <= x"20";
when "11" & x"0b4" => data <= x"f9";
when "11" & x"0b5" => data <= x"9e";
when "11" & x"0b6" => data <= x"a9";
when "11" & x"0b7" => data <= x"00";
when "11" & x"0b8" => data <= x"60";
when "11" & x"0b9" => data <= x"20";
when "11" & x"0ba" => data <= x"df";
when "11" & x"0bb" => data <= x"9e";
when "11" & x"0bc" => data <= x"a9";
when "11" & x"0bd" => data <= x"00";
when "11" & x"0be" => data <= x"60";
when "11" & x"0bf" => data <= x"4c";
when "11" & x"0c0" => data <= x"0e";
when "11" & x"0c1" => data <= x"8c";
when "11" & x"0c2" => data <= x"20";
when "11" & x"0c3" => data <= x"dd";
when "11" & x"0c4" => data <= x"92";
when "11" & x"0c5" => data <= x"20";
when "11" & x"0c6" => data <= x"94";
when "11" & x"0c7" => data <= x"bd";
when "11" & x"0c8" => data <= x"20";
when "11" & x"0c9" => data <= x"ae";
when "11" & x"0ca" => data <= x"8a";
when "11" & x"0cb" => data <= x"20";
when "11" & x"0cc" => data <= x"56";
when "11" & x"0cd" => data <= x"ae";
when "11" & x"0ce" => data <= x"d0";
when "11" & x"0cf" => data <= x"ef";
when "11" & x"0d0" => data <= x"20";
when "11" & x"0d1" => data <= x"ea";
when "11" & x"0d2" => data <= x"bd";
when "11" & x"0d3" => data <= x"a4";
when "11" & x"0d4" => data <= x"36";
when "11" & x"0d5" => data <= x"f0";
when "11" & x"0d6" => data <= x"1e";
when "11" & x"0d7" => data <= x"a5";
when "11" & x"0d8" => data <= x"2a";
when "11" & x"0d9" => data <= x"f0";
when "11" & x"0da" => data <= x"1d";
when "11" & x"0db" => data <= x"c6";
when "11" & x"0dc" => data <= x"2a";
when "11" & x"0dd" => data <= x"f0";
when "11" & x"0de" => data <= x"16";
when "11" & x"0df" => data <= x"a2";
when "11" & x"0e0" => data <= x"00";
when "11" & x"0e1" => data <= x"bd";
when "11" & x"0e2" => data <= x"00";
when "11" & x"0e3" => data <= x"06";
when "11" & x"0e4" => data <= x"99";
when "11" & x"0e5" => data <= x"00";
when "11" & x"0e6" => data <= x"06";
when "11" & x"0e7" => data <= x"e8";
when "11" & x"0e8" => data <= x"c8";
when "11" & x"0e9" => data <= x"f0";
when "11" & x"0ea" => data <= x"10";
when "11" & x"0eb" => data <= x"e4";
when "11" & x"0ec" => data <= x"36";
when "11" & x"0ed" => data <= x"90";
when "11" & x"0ee" => data <= x"f2";
when "11" & x"0ef" => data <= x"c6";
when "11" & x"0f0" => data <= x"2a";
when "11" & x"0f1" => data <= x"d0";
when "11" & x"0f2" => data <= x"ec";
when "11" & x"0f3" => data <= x"84";
when "11" & x"0f4" => data <= x"36";
when "11" & x"0f5" => data <= x"a9";
when "11" & x"0f6" => data <= x"00";
when "11" & x"0f7" => data <= x"60";
when "11" & x"0f8" => data <= x"85";
when "11" & x"0f9" => data <= x"36";
when "11" & x"0fa" => data <= x"60";
when "11" & x"0fb" => data <= x"4c";
when "11" & x"0fc" => data <= x"03";
when "11" & x"0fd" => data <= x"9c";
when "11" & x"0fe" => data <= x"68";
when "11" & x"0ff" => data <= x"85";
when "11" & x"100" => data <= x"0c";
when "11" & x"101" => data <= x"68";
when "11" & x"102" => data <= x"85";
when "11" & x"103" => data <= x"0b";
when "11" & x"104" => data <= x"00";
when "11" & x"105" => data <= x"1d";
when "11" & x"106" => data <= x"4e";
when "11" & x"107" => data <= x"6f";
when "11" & x"108" => data <= x"20";
when "11" & x"109" => data <= x"73";
when "11" & x"10a" => data <= x"75";
when "11" & x"10b" => data <= x"63";
when "11" & x"10c" => data <= x"68";
when "11" & x"10d" => data <= x"20";
when "11" & x"10e" => data <= x"a4";
when "11" & x"10f" => data <= x"2f";
when "11" & x"110" => data <= x"f2";
when "11" & x"111" => data <= x"00";
when "11" & x"112" => data <= x"a5";
when "11" & x"113" => data <= x"18";
when "11" & x"114" => data <= x"85";
when "11" & x"115" => data <= x"0c";
when "11" & x"116" => data <= x"a9";
when "11" & x"117" => data <= x"00";
when "11" & x"118" => data <= x"85";
when "11" & x"119" => data <= x"0b";
when "11" & x"11a" => data <= x"a0";
when "11" & x"11b" => data <= x"01";
when "11" & x"11c" => data <= x"b1";
when "11" & x"11d" => data <= x"0b";
when "11" & x"11e" => data <= x"30";
when "11" & x"11f" => data <= x"de";
when "11" & x"120" => data <= x"a0";
when "11" & x"121" => data <= x"03";
when "11" & x"122" => data <= x"c8";
when "11" & x"123" => data <= x"b1";
when "11" & x"124" => data <= x"0b";
when "11" & x"125" => data <= x"c9";
when "11" & x"126" => data <= x"20";
when "11" & x"127" => data <= x"f0";
when "11" & x"128" => data <= x"f9";
when "11" & x"129" => data <= x"c9";
when "11" & x"12a" => data <= x"dd";
when "11" & x"12b" => data <= x"f0";
when "11" & x"12c" => data <= x"0f";
when "11" & x"12d" => data <= x"a0";
when "11" & x"12e" => data <= x"03";
when "11" & x"12f" => data <= x"b1";
when "11" & x"130" => data <= x"0b";
when "11" & x"131" => data <= x"18";
when "11" & x"132" => data <= x"65";
when "11" & x"133" => data <= x"0b";
when "11" & x"134" => data <= x"85";
when "11" & x"135" => data <= x"0b";
when "11" & x"136" => data <= x"90";
when "11" & x"137" => data <= x"e2";
when "11" & x"138" => data <= x"e6";
when "11" & x"139" => data <= x"0c";
when "11" & x"13a" => data <= x"b0";
when "11" & x"13b" => data <= x"de";
when "11" & x"13c" => data <= x"c8";
when "11" & x"13d" => data <= x"84";
when "11" & x"13e" => data <= x"0a";
when "11" & x"13f" => data <= x"20";
when "11" & x"140" => data <= x"97";
when "11" & x"141" => data <= x"8a";
when "11" & x"142" => data <= x"98";
when "11" & x"143" => data <= x"aa";
when "11" & x"144" => data <= x"18";
when "11" & x"145" => data <= x"65";
when "11" & x"146" => data <= x"0b";
when "11" & x"147" => data <= x"a4";
when "11" & x"148" => data <= x"0c";
when "11" & x"149" => data <= x"90";
when "11" & x"14a" => data <= x"02";
when "11" & x"14b" => data <= x"c8";
when "11" & x"14c" => data <= x"18";
when "11" & x"14d" => data <= x"e9";
when "11" & x"14e" => data <= x"00";
when "11" & x"14f" => data <= x"85";
when "11" & x"150" => data <= x"3c";
when "11" & x"151" => data <= x"98";
when "11" & x"152" => data <= x"e9";
when "11" & x"153" => data <= x"00";
when "11" & x"154" => data <= x"85";
when "11" & x"155" => data <= x"3d";
when "11" & x"156" => data <= x"a0";
when "11" & x"157" => data <= x"00";
when "11" & x"158" => data <= x"c8";
when "11" & x"159" => data <= x"e8";
when "11" & x"15a" => data <= x"b1";
when "11" & x"15b" => data <= x"3c";
when "11" & x"15c" => data <= x"d1";
when "11" & x"15d" => data <= x"37";
when "11" & x"15e" => data <= x"d0";
when "11" & x"15f" => data <= x"cd";
when "11" & x"160" => data <= x"c4";
when "11" & x"161" => data <= x"39";
when "11" & x"162" => data <= x"d0";
when "11" & x"163" => data <= x"f4";
when "11" & x"164" => data <= x"c8";
when "11" & x"165" => data <= x"b1";
when "11" & x"166" => data <= x"3c";
when "11" & x"167" => data <= x"20";
when "11" & x"168" => data <= x"26";
when "11" & x"169" => data <= x"89";
when "11" & x"16a" => data <= x"b0";
when "11" & x"16b" => data <= x"c1";
when "11" & x"16c" => data <= x"8a";
when "11" & x"16d" => data <= x"a8";
when "11" & x"16e" => data <= x"20";
when "11" & x"16f" => data <= x"6d";
when "11" & x"170" => data <= x"98";
when "11" & x"171" => data <= x"20";
when "11" & x"172" => data <= x"ed";
when "11" & x"173" => data <= x"94";
when "11" & x"174" => data <= x"a2";
when "11" & x"175" => data <= x"01";
when "11" & x"176" => data <= x"20";
when "11" & x"177" => data <= x"31";
when "11" & x"178" => data <= x"95";
when "11" & x"179" => data <= x"a0";
when "11" & x"17a" => data <= x"00";
when "11" & x"17b" => data <= x"a5";
when "11" & x"17c" => data <= x"0b";
when "11" & x"17d" => data <= x"91";
when "11" & x"17e" => data <= x"02";
when "11" & x"17f" => data <= x"c8";
when "11" & x"180" => data <= x"a5";
when "11" & x"181" => data <= x"0c";
when "11" & x"182" => data <= x"91";
when "11" & x"183" => data <= x"02";
when "11" & x"184" => data <= x"20";
when "11" & x"185" => data <= x"39";
when "11" & x"186" => data <= x"95";
when "11" & x"187" => data <= x"4c";
when "11" & x"188" => data <= x"f4";
when "11" & x"189" => data <= x"b1";
when "11" & x"18a" => data <= x"00";
when "11" & x"18b" => data <= x"1e";
when "11" & x"18c" => data <= x"42";
when "11" & x"18d" => data <= x"61";
when "11" & x"18e" => data <= x"64";
when "11" & x"18f" => data <= x"20";
when "11" & x"190" => data <= x"63";
when "11" & x"191" => data <= x"61";
when "11" & x"192" => data <= x"6c";
when "11" & x"193" => data <= x"6c";
when "11" & x"194" => data <= x"00";
when "11" & x"195" => data <= x"a9";
when "11" & x"196" => data <= x"a4";
when "11" & x"197" => data <= x"85";
when "11" & x"198" => data <= x"27";
when "11" & x"199" => data <= x"ba";
when "11" & x"19a" => data <= x"8a";
when "11" & x"19b" => data <= x"18";
when "11" & x"19c" => data <= x"65";
when "11" & x"19d" => data <= x"04";
when "11" & x"19e" => data <= x"20";
when "11" & x"19f" => data <= x"2e";
when "11" & x"1a0" => data <= x"be";
when "11" & x"1a1" => data <= x"a0";
when "11" & x"1a2" => data <= x"00";
when "11" & x"1a3" => data <= x"8a";
when "11" & x"1a4" => data <= x"91";
when "11" & x"1a5" => data <= x"04";
when "11" & x"1a6" => data <= x"e8";
when "11" & x"1a7" => data <= x"c8";
when "11" & x"1a8" => data <= x"bd";
when "11" & x"1a9" => data <= x"00";
when "11" & x"1aa" => data <= x"01";
when "11" & x"1ab" => data <= x"91";
when "11" & x"1ac" => data <= x"04";
when "11" & x"1ad" => data <= x"e0";
when "11" & x"1ae" => data <= x"ff";
when "11" & x"1af" => data <= x"d0";
when "11" & x"1b0" => data <= x"f5";
when "11" & x"1b1" => data <= x"9a";
when "11" & x"1b2" => data <= x"a5";
when "11" & x"1b3" => data <= x"27";
when "11" & x"1b4" => data <= x"48";
when "11" & x"1b5" => data <= x"a5";
when "11" & x"1b6" => data <= x"0a";
when "11" & x"1b7" => data <= x"48";
when "11" & x"1b8" => data <= x"a5";
when "11" & x"1b9" => data <= x"0b";
when "11" & x"1ba" => data <= x"48";
when "11" & x"1bb" => data <= x"a5";
when "11" & x"1bc" => data <= x"0c";
when "11" & x"1bd" => data <= x"48";
when "11" & x"1be" => data <= x"a5";
when "11" & x"1bf" => data <= x"1b";
when "11" & x"1c0" => data <= x"aa";
when "11" & x"1c1" => data <= x"18";
when "11" & x"1c2" => data <= x"65";
when "11" & x"1c3" => data <= x"19";
when "11" & x"1c4" => data <= x"a4";
when "11" & x"1c5" => data <= x"1a";
when "11" & x"1c6" => data <= x"90";
when "11" & x"1c7" => data <= x"02";
when "11" & x"1c8" => data <= x"c8";
when "11" & x"1c9" => data <= x"18";
when "11" & x"1ca" => data <= x"e9";
when "11" & x"1cb" => data <= x"01";
when "11" & x"1cc" => data <= x"85";
when "11" & x"1cd" => data <= x"37";
when "11" & x"1ce" => data <= x"98";
when "11" & x"1cf" => data <= x"e9";
when "11" & x"1d0" => data <= x"00";
when "11" & x"1d1" => data <= x"85";
when "11" & x"1d2" => data <= x"38";
when "11" & x"1d3" => data <= x"a0";
when "11" & x"1d4" => data <= x"02";
when "11" & x"1d5" => data <= x"20";
when "11" & x"1d6" => data <= x"5b";
when "11" & x"1d7" => data <= x"95";
when "11" & x"1d8" => data <= x"c0";
when "11" & x"1d9" => data <= x"02";
when "11" & x"1da" => data <= x"f0";
when "11" & x"1db" => data <= x"ae";
when "11" & x"1dc" => data <= x"86";
when "11" & x"1dd" => data <= x"1b";
when "11" & x"1de" => data <= x"88";
when "11" & x"1df" => data <= x"84";
when "11" & x"1e0" => data <= x"39";
when "11" & x"1e1" => data <= x"20";
when "11" & x"1e2" => data <= x"5b";
when "11" & x"1e3" => data <= x"94";
when "11" & x"1e4" => data <= x"d0";
when "11" & x"1e5" => data <= x"03";
when "11" & x"1e6" => data <= x"4c";
when "11" & x"1e7" => data <= x"12";
when "11" & x"1e8" => data <= x"b1";
when "11" & x"1e9" => data <= x"a0";
when "11" & x"1ea" => data <= x"00";
when "11" & x"1eb" => data <= x"b1";
when "11" & x"1ec" => data <= x"2a";
when "11" & x"1ed" => data <= x"85";
when "11" & x"1ee" => data <= x"0b";
when "11" & x"1ef" => data <= x"c8";
when "11" & x"1f0" => data <= x"b1";
when "11" & x"1f1" => data <= x"2a";
when "11" & x"1f2" => data <= x"85";
when "11" & x"1f3" => data <= x"0c";
when "11" & x"1f4" => data <= x"a9";
when "11" & x"1f5" => data <= x"00";
when "11" & x"1f6" => data <= x"48";
when "11" & x"1f7" => data <= x"85";
when "11" & x"1f8" => data <= x"0a";
when "11" & x"1f9" => data <= x"20";
when "11" & x"1fa" => data <= x"97";
when "11" & x"1fb" => data <= x"8a";
when "11" & x"1fc" => data <= x"c9";
when "11" & x"1fd" => data <= x"28";
when "11" & x"1fe" => data <= x"f0";
when "11" & x"1ff" => data <= x"4d";
when "11" & x"200" => data <= x"c6";
when "11" & x"201" => data <= x"0a";
when "11" & x"202" => data <= x"a5";
when "11" & x"203" => data <= x"1b";
when "11" & x"204" => data <= x"48";
when "11" & x"205" => data <= x"a5";
when "11" & x"206" => data <= x"19";
when "11" & x"207" => data <= x"48";
when "11" & x"208" => data <= x"a5";
when "11" & x"209" => data <= x"1a";
when "11" & x"20a" => data <= x"48";
when "11" & x"20b" => data <= x"20";
when "11" & x"20c" => data <= x"a3";
when "11" & x"20d" => data <= x"8b";
when "11" & x"20e" => data <= x"68";
when "11" & x"20f" => data <= x"85";
when "11" & x"210" => data <= x"1a";
when "11" & x"211" => data <= x"68";
when "11" & x"212" => data <= x"85";
when "11" & x"213" => data <= x"19";
when "11" & x"214" => data <= x"68";
when "11" & x"215" => data <= x"85";
when "11" & x"216" => data <= x"1b";
when "11" & x"217" => data <= x"68";
when "11" & x"218" => data <= x"f0";
when "11" & x"219" => data <= x"0c";
when "11" & x"21a" => data <= x"85";
when "11" & x"21b" => data <= x"3f";
when "11" & x"21c" => data <= x"20";
when "11" & x"21d" => data <= x"0b";
when "11" & x"21e" => data <= x"be";
when "11" & x"21f" => data <= x"20";
when "11" & x"220" => data <= x"c1";
when "11" & x"221" => data <= x"8c";
when "11" & x"222" => data <= x"c6";
when "11" & x"223" => data <= x"3f";
when "11" & x"224" => data <= x"d0";
when "11" & x"225" => data <= x"f6";
when "11" & x"226" => data <= x"68";
when "11" & x"227" => data <= x"85";
when "11" & x"228" => data <= x"0c";
when "11" & x"229" => data <= x"68";
when "11" & x"22a" => data <= x"85";
when "11" & x"22b" => data <= x"0b";
when "11" & x"22c" => data <= x"68";
when "11" & x"22d" => data <= x"85";
when "11" & x"22e" => data <= x"0a";
when "11" & x"22f" => data <= x"68";
when "11" & x"230" => data <= x"a0";
when "11" & x"231" => data <= x"00";
when "11" & x"232" => data <= x"b1";
when "11" & x"233" => data <= x"04";
when "11" & x"234" => data <= x"aa";
when "11" & x"235" => data <= x"9a";
when "11" & x"236" => data <= x"c8";
when "11" & x"237" => data <= x"e8";
when "11" & x"238" => data <= x"b1";
when "11" & x"239" => data <= x"04";
when "11" & x"23a" => data <= x"9d";
when "11" & x"23b" => data <= x"00";
when "11" & x"23c" => data <= x"01";
when "11" & x"23d" => data <= x"e0";
when "11" & x"23e" => data <= x"ff";
when "11" & x"23f" => data <= x"d0";
when "11" & x"240" => data <= x"f5";
when "11" & x"241" => data <= x"98";
when "11" & x"242" => data <= x"65";
when "11" & x"243" => data <= x"04";
when "11" & x"244" => data <= x"85";
when "11" & x"245" => data <= x"04";
when "11" & x"246" => data <= x"90";
when "11" & x"247" => data <= x"02";
when "11" & x"248" => data <= x"e6";
when "11" & x"249" => data <= x"05";
when "11" & x"24a" => data <= x"a5";
when "11" & x"24b" => data <= x"27";
when "11" & x"24c" => data <= x"60";
when "11" & x"24d" => data <= x"a5";
when "11" & x"24e" => data <= x"1b";
when "11" & x"24f" => data <= x"48";
when "11" & x"250" => data <= x"a5";
when "11" & x"251" => data <= x"19";
when "11" & x"252" => data <= x"48";
when "11" & x"253" => data <= x"a5";
when "11" & x"254" => data <= x"1a";
when "11" & x"255" => data <= x"48";
when "11" & x"256" => data <= x"20";
when "11" & x"257" => data <= x"82";
when "11" & x"258" => data <= x"95";
when "11" & x"259" => data <= x"f0";
when "11" & x"25a" => data <= x"5a";
when "11" & x"25b" => data <= x"a5";
when "11" & x"25c" => data <= x"1b";
when "11" & x"25d" => data <= x"85";
when "11" & x"25e" => data <= x"0a";
when "11" & x"25f" => data <= x"68";
when "11" & x"260" => data <= x"85";
when "11" & x"261" => data <= x"1a";
when "11" & x"262" => data <= x"68";
when "11" & x"263" => data <= x"85";
when "11" & x"264" => data <= x"19";
when "11" & x"265" => data <= x"68";
when "11" & x"266" => data <= x"85";
when "11" & x"267" => data <= x"1b";
when "11" & x"268" => data <= x"68";
when "11" & x"269" => data <= x"aa";
when "11" & x"26a" => data <= x"a5";
when "11" & x"26b" => data <= x"2c";
when "11" & x"26c" => data <= x"48";
when "11" & x"26d" => data <= x"a5";
when "11" & x"26e" => data <= x"2b";
when "11" & x"26f" => data <= x"48";
when "11" & x"270" => data <= x"a5";
when "11" & x"271" => data <= x"2a";
when "11" & x"272" => data <= x"48";
when "11" & x"273" => data <= x"e8";
when "11" & x"274" => data <= x"8a";
when "11" & x"275" => data <= x"48";
when "11" & x"276" => data <= x"20";
when "11" & x"277" => data <= x"0d";
when "11" & x"278" => data <= x"b3";
when "11" & x"279" => data <= x"20";
when "11" & x"27a" => data <= x"97";
when "11" & x"27b" => data <= x"8a";
when "11" & x"27c" => data <= x"c9";
when "11" & x"27d" => data <= x"2c";
when "11" & x"27e" => data <= x"f0";
when "11" & x"27f" => data <= x"cd";
when "11" & x"280" => data <= x"c9";
when "11" & x"281" => data <= x"29";
when "11" & x"282" => data <= x"d0";
when "11" & x"283" => data <= x"31";
when "11" & x"284" => data <= x"a9";
when "11" & x"285" => data <= x"00";
when "11" & x"286" => data <= x"48";
when "11" & x"287" => data <= x"20";
when "11" & x"288" => data <= x"8c";
when "11" & x"289" => data <= x"8a";
when "11" & x"28a" => data <= x"c9";
when "11" & x"28b" => data <= x"28";
when "11" & x"28c" => data <= x"d0";
when "11" & x"28d" => data <= x"27";
when "11" & x"28e" => data <= x"20";
when "11" & x"28f" => data <= x"29";
when "11" & x"290" => data <= x"9b";
when "11" & x"291" => data <= x"20";
when "11" & x"292" => data <= x"90";
when "11" & x"293" => data <= x"bd";
when "11" & x"294" => data <= x"a5";
when "11" & x"295" => data <= x"27";
when "11" & x"296" => data <= x"85";
when "11" & x"297" => data <= x"2d";
when "11" & x"298" => data <= x"20";
when "11" & x"299" => data <= x"94";
when "11" & x"29a" => data <= x"bd";
when "11" & x"29b" => data <= x"68";
when "11" & x"29c" => data <= x"aa";
when "11" & x"29d" => data <= x"e8";
when "11" & x"29e" => data <= x"8a";
when "11" & x"29f" => data <= x"48";
when "11" & x"2a0" => data <= x"20";
when "11" & x"2a1" => data <= x"8c";
when "11" & x"2a2" => data <= x"8a";
when "11" & x"2a3" => data <= x"c9";
when "11" & x"2a4" => data <= x"2c";
when "11" & x"2a5" => data <= x"f0";
when "11" & x"2a6" => data <= x"e7";
when "11" & x"2a7" => data <= x"c9";
when "11" & x"2a8" => data <= x"29";
when "11" & x"2a9" => data <= x"d0";
when "11" & x"2aa" => data <= x"0a";
when "11" & x"2ab" => data <= x"68";
when "11" & x"2ac" => data <= x"68";
when "11" & x"2ad" => data <= x"85";
when "11" & x"2ae" => data <= x"4d";
when "11" & x"2af" => data <= x"85";
when "11" & x"2b0" => data <= x"4e";
when "11" & x"2b1" => data <= x"e4";
when "11" & x"2b2" => data <= x"4d";
when "11" & x"2b3" => data <= x"f0";
when "11" & x"2b4" => data <= x"15";
when "11" & x"2b5" => data <= x"a2";
when "11" & x"2b6" => data <= x"fb";
when "11" & x"2b7" => data <= x"9a";
when "11" & x"2b8" => data <= x"68";
when "11" & x"2b9" => data <= x"85";
when "11" & x"2ba" => data <= x"0c";
when "11" & x"2bb" => data <= x"68";
when "11" & x"2bc" => data <= x"85";
when "11" & x"2bd" => data <= x"0b";
when "11" & x"2be" => data <= x"00";
when "11" & x"2bf" => data <= x"1f";
when "11" & x"2c0" => data <= x"41";
when "11" & x"2c1" => data <= x"72";
when "11" & x"2c2" => data <= x"67";
when "11" & x"2c3" => data <= x"75";
when "11" & x"2c4" => data <= x"6d";
when "11" & x"2c5" => data <= x"65";
when "11" & x"2c6" => data <= x"6e";
when "11" & x"2c7" => data <= x"74";
when "11" & x"2c8" => data <= x"73";
when "11" & x"2c9" => data <= x"00";
when "11" & x"2ca" => data <= x"20";
when "11" & x"2cb" => data <= x"ea";
when "11" & x"2cc" => data <= x"bd";
when "11" & x"2cd" => data <= x"68";
when "11" & x"2ce" => data <= x"85";
when "11" & x"2cf" => data <= x"2a";
when "11" & x"2d0" => data <= x"68";
when "11" & x"2d1" => data <= x"85";
when "11" & x"2d2" => data <= x"2b";
when "11" & x"2d3" => data <= x"68";
when "11" & x"2d4" => data <= x"85";
when "11" & x"2d5" => data <= x"2c";
when "11" & x"2d6" => data <= x"30";
when "11" & x"2d7" => data <= x"21";
when "11" & x"2d8" => data <= x"a5";
when "11" & x"2d9" => data <= x"2d";
when "11" & x"2da" => data <= x"f0";
when "11" & x"2db" => data <= x"d9";
when "11" & x"2dc" => data <= x"85";
when "11" & x"2dd" => data <= x"27";
when "11" & x"2de" => data <= x"a2";
when "11" & x"2df" => data <= x"37";
when "11" & x"2e0" => data <= x"20";
when "11" & x"2e1" => data <= x"44";
when "11" & x"2e2" => data <= x"be";
when "11" & x"2e3" => data <= x"a5";
when "11" & x"2e4" => data <= x"27";
when "11" & x"2e5" => data <= x"10";
when "11" & x"2e6" => data <= x"09";
when "11" & x"2e7" => data <= x"20";
when "11" & x"2e8" => data <= x"7e";
when "11" & x"2e9" => data <= x"bd";
when "11" & x"2ea" => data <= x"20";
when "11" & x"2eb" => data <= x"b5";
when "11" & x"2ec" => data <= x"a3";
when "11" & x"2ed" => data <= x"4c";
when "11" & x"2ee" => data <= x"f3";
when "11" & x"2ef" => data <= x"b2";
when "11" & x"2f0" => data <= x"20";
when "11" & x"2f1" => data <= x"ea";
when "11" & x"2f2" => data <= x"bd";
when "11" & x"2f3" => data <= x"20";
when "11" & x"2f4" => data <= x"b7";
when "11" & x"2f5" => data <= x"b4";
when "11" & x"2f6" => data <= x"4c";
when "11" & x"2f7" => data <= x"03";
when "11" & x"2f8" => data <= x"b3";
when "11" & x"2f9" => data <= x"a5";
when "11" & x"2fa" => data <= x"2d";
when "11" & x"2fb" => data <= x"d0";
when "11" & x"2fc" => data <= x"b8";
when "11" & x"2fd" => data <= x"20";
when "11" & x"2fe" => data <= x"cb";
when "11" & x"2ff" => data <= x"bd";
when "11" & x"300" => data <= x"20";
when "11" & x"301" => data <= x"21";
when "11" & x"302" => data <= x"8c";
when "11" & x"303" => data <= x"c6";
when "11" & x"304" => data <= x"4d";
when "11" & x"305" => data <= x"d0";
when "11" & x"306" => data <= x"c3";
when "11" & x"307" => data <= x"a5";
when "11" & x"308" => data <= x"4e";
when "11" & x"309" => data <= x"48";
when "11" & x"30a" => data <= x"4c";
when "11" & x"30b" => data <= x"02";
when "11" & x"30c" => data <= x"b2";
when "11" & x"30d" => data <= x"a4";
when "11" & x"30e" => data <= x"2c";
when "11" & x"30f" => data <= x"c0";
when "11" & x"310" => data <= x"04";
when "11" & x"311" => data <= x"d0";
when "11" & x"312" => data <= x"05";
when "11" & x"313" => data <= x"a2";
when "11" & x"314" => data <= x"37";
when "11" & x"315" => data <= x"20";
when "11" & x"316" => data <= x"44";
when "11" & x"317" => data <= x"be";
when "11" & x"318" => data <= x"20";
when "11" & x"319" => data <= x"2c";
when "11" & x"31a" => data <= x"b3";
when "11" & x"31b" => data <= x"08";
when "11" & x"31c" => data <= x"20";
when "11" & x"31d" => data <= x"90";
when "11" & x"31e" => data <= x"bd";
when "11" & x"31f" => data <= x"28";
when "11" & x"320" => data <= x"f0";
when "11" & x"321" => data <= x"07";
when "11" & x"322" => data <= x"30";
when "11" & x"323" => data <= x"05";
when "11" & x"324" => data <= x"a2";
when "11" & x"325" => data <= x"37";
when "11" & x"326" => data <= x"20";
when "11" & x"327" => data <= x"56";
when "11" & x"328" => data <= x"af";
when "11" & x"329" => data <= x"4c";
when "11" & x"32a" => data <= x"94";
when "11" & x"32b" => data <= x"bd";
when "11" & x"32c" => data <= x"a4";
when "11" & x"32d" => data <= x"2c";
when "11" & x"32e" => data <= x"30";
when "11" & x"32f" => data <= x"54";
when "11" & x"330" => data <= x"f0";
when "11" & x"331" => data <= x"1d";
when "11" & x"332" => data <= x"c0";
when "11" & x"333" => data <= x"05";
when "11" & x"334" => data <= x"f0";
when "11" & x"335" => data <= x"1e";
when "11" & x"336" => data <= x"a0";
when "11" & x"337" => data <= x"03";
when "11" & x"338" => data <= x"b1";
when "11" & x"339" => data <= x"2a";
when "11" & x"33a" => data <= x"85";
when "11" & x"33b" => data <= x"2d";
when "11" & x"33c" => data <= x"88";
when "11" & x"33d" => data <= x"b1";
when "11" & x"33e" => data <= x"2a";
when "11" & x"33f" => data <= x"85";
when "11" & x"340" => data <= x"2c";
when "11" & x"341" => data <= x"88";
when "11" & x"342" => data <= x"b1";
when "11" & x"343" => data <= x"2a";
when "11" & x"344" => data <= x"aa";
when "11" & x"345" => data <= x"88";
when "11" & x"346" => data <= x"b1";
when "11" & x"347" => data <= x"2a";
when "11" & x"348" => data <= x"85";
when "11" & x"349" => data <= x"2a";
when "11" & x"34a" => data <= x"86";
when "11" & x"34b" => data <= x"2b";
when "11" & x"34c" => data <= x"a9";
when "11" & x"34d" => data <= x"40";
when "11" & x"34e" => data <= x"60";
when "11" & x"34f" => data <= x"b1";
when "11" & x"350" => data <= x"2a";
when "11" & x"351" => data <= x"4c";
when "11" & x"352" => data <= x"ea";
when "11" & x"353" => data <= x"ae";
when "11" & x"354" => data <= x"88";
when "11" & x"355" => data <= x"b1";
when "11" & x"356" => data <= x"2a";
when "11" & x"357" => data <= x"85";
when "11" & x"358" => data <= x"34";
when "11" & x"359" => data <= x"88";
when "11" & x"35a" => data <= x"b1";
when "11" & x"35b" => data <= x"2a";
when "11" & x"35c" => data <= x"85";
when "11" & x"35d" => data <= x"33";
when "11" & x"35e" => data <= x"88";
when "11" & x"35f" => data <= x"b1";
when "11" & x"360" => data <= x"2a";
when "11" & x"361" => data <= x"85";
when "11" & x"362" => data <= x"32";
when "11" & x"363" => data <= x"88";
when "11" & x"364" => data <= x"b1";
when "11" & x"365" => data <= x"2a";
when "11" & x"366" => data <= x"85";
when "11" & x"367" => data <= x"2e";
when "11" & x"368" => data <= x"88";
when "11" & x"369" => data <= x"b1";
when "11" & x"36a" => data <= x"2a";
when "11" & x"36b" => data <= x"85";
when "11" & x"36c" => data <= x"30";
when "11" & x"36d" => data <= x"84";
when "11" & x"36e" => data <= x"35";
when "11" & x"36f" => data <= x"84";
when "11" & x"370" => data <= x"2f";
when "11" & x"371" => data <= x"05";
when "11" & x"372" => data <= x"2e";
when "11" & x"373" => data <= x"05";
when "11" & x"374" => data <= x"32";
when "11" & x"375" => data <= x"05";
when "11" & x"376" => data <= x"33";
when "11" & x"377" => data <= x"05";
when "11" & x"378" => data <= x"34";
when "11" & x"379" => data <= x"f0";
when "11" & x"37a" => data <= x"04";
when "11" & x"37b" => data <= x"a5";
when "11" & x"37c" => data <= x"2e";
when "11" & x"37d" => data <= x"09";
when "11" & x"37e" => data <= x"80";
when "11" & x"37f" => data <= x"85";
when "11" & x"380" => data <= x"31";
when "11" & x"381" => data <= x"a9";
when "11" & x"382" => data <= x"ff";
when "11" & x"383" => data <= x"60";
when "11" & x"384" => data <= x"c0";
when "11" & x"385" => data <= x"80";
when "11" & x"386" => data <= x"f0";
when "11" & x"387" => data <= x"1f";
when "11" & x"388" => data <= x"a0";
when "11" & x"389" => data <= x"03";
when "11" & x"38a" => data <= x"b1";
when "11" & x"38b" => data <= x"2a";
when "11" & x"38c" => data <= x"85";
when "11" & x"38d" => data <= x"36";
when "11" & x"38e" => data <= x"f0";
when "11" & x"38f" => data <= x"16";
when "11" & x"390" => data <= x"a0";
when "11" & x"391" => data <= x"01";
when "11" & x"392" => data <= x"b1";
when "11" & x"393" => data <= x"2a";
when "11" & x"394" => data <= x"85";
when "11" & x"395" => data <= x"38";
when "11" & x"396" => data <= x"88";
when "11" & x"397" => data <= x"b1";
when "11" & x"398" => data <= x"2a";
when "11" & x"399" => data <= x"85";
when "11" & x"39a" => data <= x"37";
when "11" & x"39b" => data <= x"a4";
when "11" & x"39c" => data <= x"36";
when "11" & x"39d" => data <= x"88";
when "11" & x"39e" => data <= x"b1";
when "11" & x"39f" => data <= x"37";
when "11" & x"3a0" => data <= x"99";
when "11" & x"3a1" => data <= x"00";
when "11" & x"3a2" => data <= x"06";
when "11" & x"3a3" => data <= x"98";
when "11" & x"3a4" => data <= x"d0";
when "11" & x"3a5" => data <= x"f7";
when "11" & x"3a6" => data <= x"60";
when "11" & x"3a7" => data <= x"a5";
when "11" & x"3a8" => data <= x"2b";
when "11" & x"3a9" => data <= x"f0";
when "11" & x"3aa" => data <= x"15";
when "11" & x"3ab" => data <= x"a0";
when "11" & x"3ac" => data <= x"00";
when "11" & x"3ad" => data <= x"b1";
when "11" & x"3ae" => data <= x"2a";
when "11" & x"3af" => data <= x"99";
when "11" & x"3b0" => data <= x"00";
when "11" & x"3b1" => data <= x"06";
when "11" & x"3b2" => data <= x"49";
when "11" & x"3b3" => data <= x"0d";
when "11" & x"3b4" => data <= x"f0";
when "11" & x"3b5" => data <= x"04";
when "11" & x"3b6" => data <= x"c8";
when "11" & x"3b7" => data <= x"d0";
when "11" & x"3b8" => data <= x"f4";
when "11" & x"3b9" => data <= x"98";
when "11" & x"3ba" => data <= x"84";
when "11" & x"3bb" => data <= x"36";
when "11" & x"3bc" => data <= x"60";
when "11" & x"3bd" => data <= x"20";
when "11" & x"3be" => data <= x"e3";
when "11" & x"3bf" => data <= x"92";
when "11" & x"3c0" => data <= x"a5";
when "11" & x"3c1" => data <= x"2a";
when "11" & x"3c2" => data <= x"4c";
when "11" & x"3c3" => data <= x"c2";
when "11" & x"3c4" => data <= x"af";
when "11" & x"3c5" => data <= x"a0";
when "11" & x"3c6" => data <= x"00";
when "11" & x"3c7" => data <= x"84";
when "11" & x"3c8" => data <= x"08";
when "11" & x"3c9" => data <= x"84";
when "11" & x"3ca" => data <= x"09";
when "11" & x"3cb" => data <= x"a6";
when "11" & x"3cc" => data <= x"18";
when "11" & x"3cd" => data <= x"86";
when "11" & x"3ce" => data <= x"38";
when "11" & x"3cf" => data <= x"84";
when "11" & x"3d0" => data <= x"37";
when "11" & x"3d1" => data <= x"a6";
when "11" & x"3d2" => data <= x"0c";
when "11" & x"3d3" => data <= x"e0";
when "11" & x"3d4" => data <= x"07";
when "11" & x"3d5" => data <= x"f0";
when "11" & x"3d6" => data <= x"2a";
when "11" & x"3d7" => data <= x"a6";
when "11" & x"3d8" => data <= x"0b";
when "11" & x"3d9" => data <= x"20";
when "11" & x"3da" => data <= x"42";
when "11" & x"3db" => data <= x"89";
when "11" & x"3dc" => data <= x"c9";
when "11" & x"3dd" => data <= x"0d";
when "11" & x"3de" => data <= x"d0";
when "11" & x"3df" => data <= x"19";
when "11" & x"3e0" => data <= x"e4";
when "11" & x"3e1" => data <= x"37";
when "11" & x"3e2" => data <= x"a5";
when "11" & x"3e3" => data <= x"0c";
when "11" & x"3e4" => data <= x"e5";
when "11" & x"3e5" => data <= x"38";
when "11" & x"3e6" => data <= x"90";
when "11" & x"3e7" => data <= x"19";
when "11" & x"3e8" => data <= x"20";
when "11" & x"3e9" => data <= x"42";
when "11" & x"3ea" => data <= x"89";
when "11" & x"3eb" => data <= x"09";
when "11" & x"3ec" => data <= x"00";
when "11" & x"3ed" => data <= x"30";
when "11" & x"3ee" => data <= x"12";
when "11" & x"3ef" => data <= x"85";
when "11" & x"3f0" => data <= x"09";
when "11" & x"3f1" => data <= x"20";
when "11" & x"3f2" => data <= x"42";
when "11" & x"3f3" => data <= x"89";
when "11" & x"3f4" => data <= x"85";
when "11" & x"3f5" => data <= x"08";
when "11" & x"3f6" => data <= x"20";
when "11" & x"3f7" => data <= x"42";
when "11" & x"3f8" => data <= x"89";
when "11" & x"3f9" => data <= x"e4";
when "11" & x"3fa" => data <= x"37";
when "11" & x"3fb" => data <= x"a5";
when "11" & x"3fc" => data <= x"0c";
when "11" & x"3fd" => data <= x"e5";
when "11" & x"3fe" => data <= x"38";
when "11" & x"3ff" => data <= x"b0";
when "11" & x"400" => data <= x"d8";
when "11" & x"401" => data <= x"60";
when "11" & x"402" => data <= x"20";
when "11" & x"403" => data <= x"c5";
when "11" & x"404" => data <= x"b3";
when "11" & x"405" => data <= x"84";
when "11" & x"406" => data <= x"20";
when "11" & x"407" => data <= x"b1";
when "11" & x"408" => data <= x"fd";
when "11" & x"409" => data <= x"d0";
when "11" & x"40a" => data <= x"08";
when "11" & x"40b" => data <= x"a9";
when "11" & x"40c" => data <= x"33";
when "11" & x"40d" => data <= x"85";
when "11" & x"40e" => data <= x"16";
when "11" & x"40f" => data <= x"a9";
when "11" & x"410" => data <= x"b4";
when "11" & x"411" => data <= x"85";
when "11" & x"412" => data <= x"17";
when "11" & x"413" => data <= x"a5";
when "11" & x"414" => data <= x"16";
when "11" & x"415" => data <= x"85";
when "11" & x"416" => data <= x"0b";
when "11" & x"417" => data <= x"a5";
when "11" & x"418" => data <= x"17";
when "11" & x"419" => data <= x"85";
when "11" & x"41a" => data <= x"0c";
when "11" & x"41b" => data <= x"20";
when "11" & x"41c" => data <= x"3a";
when "11" & x"41d" => data <= x"bd";
when "11" & x"41e" => data <= x"aa";
when "11" & x"41f" => data <= x"86";
when "11" & x"420" => data <= x"0a";
when "11" & x"421" => data <= x"a9";
when "11" & x"422" => data <= x"da";
when "11" & x"423" => data <= x"20";
when "11" & x"424" => data <= x"f4";
when "11" & x"425" => data <= x"ff";
when "11" & x"426" => data <= x"a9";
when "11" & x"427" => data <= x"7e";
when "11" & x"428" => data <= x"20";
when "11" & x"429" => data <= x"f4";
when "11" & x"42a" => data <= x"ff";
when "11" & x"42b" => data <= x"a2";
when "11" & x"42c" => data <= x"ff";
when "11" & x"42d" => data <= x"86";
when "11" & x"42e" => data <= x"28";
when "11" & x"42f" => data <= x"9a";
when "11" & x"430" => data <= x"4c";
when "11" & x"431" => data <= x"a3";
when "11" & x"432" => data <= x"8b";
when "11" & x"433" => data <= x"f6";
when "11" & x"434" => data <= x"3a";
when "11" & x"435" => data <= x"e7";
when "11" & x"436" => data <= x"9e";
when "11" & x"437" => data <= x"f1";
when "11" & x"438" => data <= x"22";
when "11" & x"439" => data <= x"20";
when "11" & x"43a" => data <= x"61";
when "11" & x"43b" => data <= x"74";
when "11" & x"43c" => data <= x"20";
when "11" & x"43d" => data <= x"6c";
when "11" & x"43e" => data <= x"69";
when "11" & x"43f" => data <= x"6e";
when "11" & x"440" => data <= x"65";
when "11" & x"441" => data <= x"20";
when "11" & x"442" => data <= x"22";
when "11" & x"443" => data <= x"3b";
when "11" & x"444" => data <= x"9e";
when "11" & x"445" => data <= x"3a";
when "11" & x"446" => data <= x"e0";
when "11" & x"447" => data <= x"8b";
when "11" & x"448" => data <= x"f1";
when "11" & x"449" => data <= x"3a";
when "11" & x"44a" => data <= x"e0";
when "11" & x"44b" => data <= x"0d";
when "11" & x"44c" => data <= x"20";
when "11" & x"44d" => data <= x"21";
when "11" & x"44e" => data <= x"88";
when "11" & x"44f" => data <= x"a2";
when "11" & x"450" => data <= x"03";
when "11" & x"451" => data <= x"a5";
when "11" & x"452" => data <= x"2a";
when "11" & x"453" => data <= x"48";
when "11" & x"454" => data <= x"a5";
when "11" & x"455" => data <= x"2b";
when "11" & x"456" => data <= x"48";
when "11" & x"457" => data <= x"8a";
when "11" & x"458" => data <= x"48";
when "11" & x"459" => data <= x"20";
when "11" & x"45a" => data <= x"da";
when "11" & x"45b" => data <= x"92";
when "11" & x"45c" => data <= x"68";
when "11" & x"45d" => data <= x"aa";
when "11" & x"45e" => data <= x"ca";
when "11" & x"45f" => data <= x"d0";
when "11" & x"460" => data <= x"f0";
when "11" & x"461" => data <= x"20";
when "11" & x"462" => data <= x"52";
when "11" & x"463" => data <= x"98";
when "11" & x"464" => data <= x"a5";
when "11" & x"465" => data <= x"2a";
when "11" & x"466" => data <= x"85";
when "11" & x"467" => data <= x"3d";
when "11" & x"468" => data <= x"a5";
when "11" & x"469" => data <= x"2b";
when "11" & x"46a" => data <= x"85";
when "11" & x"46b" => data <= x"3e";
when "11" & x"46c" => data <= x"a0";
when "11" & x"46d" => data <= x"07";
when "11" & x"46e" => data <= x"a2";
when "11" & x"46f" => data <= x"05";
when "11" & x"470" => data <= x"d0";
when "11" & x"471" => data <= x"1d";
when "11" & x"472" => data <= x"20";
when "11" & x"473" => data <= x"21";
when "11" & x"474" => data <= x"88";
when "11" & x"475" => data <= x"a2";
when "11" & x"476" => data <= x"0d";
when "11" & x"477" => data <= x"a5";
when "11" & x"478" => data <= x"2a";
when "11" & x"479" => data <= x"48";
when "11" & x"47a" => data <= x"8a";
when "11" & x"47b" => data <= x"48";
when "11" & x"47c" => data <= x"20";
when "11" & x"47d" => data <= x"da";
when "11" & x"47e" => data <= x"92";
when "11" & x"47f" => data <= x"68";
when "11" & x"480" => data <= x"aa";
when "11" & x"481" => data <= x"ca";
when "11" & x"482" => data <= x"d0";
when "11" & x"483" => data <= x"f3";
when "11" & x"484" => data <= x"20";
when "11" & x"485" => data <= x"52";
when "11" & x"486" => data <= x"98";
when "11" & x"487" => data <= x"a5";
when "11" & x"488" => data <= x"2a";
when "11" & x"489" => data <= x"85";
when "11" & x"48a" => data <= x"44";
when "11" & x"48b" => data <= x"a2";
when "11" & x"48c" => data <= x"0c";
when "11" & x"48d" => data <= x"a0";
when "11" & x"48e" => data <= x"08";
when "11" & x"48f" => data <= x"68";
when "11" & x"490" => data <= x"95";
when "11" & x"491" => data <= x"37";
when "11" & x"492" => data <= x"ca";
when "11" & x"493" => data <= x"10";
when "11" & x"494" => data <= x"fa";
when "11" & x"495" => data <= x"98";
when "11" & x"496" => data <= x"a2";
when "11" & x"497" => data <= x"37";
when "11" & x"498" => data <= x"a0";
when "11" & x"499" => data <= x"00";
when "11" & x"49a" => data <= x"20";
when "11" & x"49b" => data <= x"f1";
when "11" & x"49c" => data <= x"ff";
when "11" & x"49d" => data <= x"4c";
when "11" & x"49e" => data <= x"9b";
when "11" & x"49f" => data <= x"8b";
when "11" & x"4a0" => data <= x"20";
when "11" & x"4a1" => data <= x"21";
when "11" & x"4a2" => data <= x"88";
when "11" & x"4a3" => data <= x"20";
when "11" & x"4a4" => data <= x"52";
when "11" & x"4a5" => data <= x"98";
when "11" & x"4a6" => data <= x"a4";
when "11" & x"4a7" => data <= x"2a";
when "11" & x"4a8" => data <= x"88";
when "11" & x"4a9" => data <= x"84";
when "11" & x"4aa" => data <= x"23";
when "11" & x"4ab" => data <= x"4c";
when "11" & x"4ac" => data <= x"9b";
when "11" & x"4ad" => data <= x"8b";
when "11" & x"4ae" => data <= x"4c";
when "11" & x"4af" => data <= x"0e";
when "11" & x"4b0" => data <= x"8c";
when "11" & x"4b1" => data <= x"20";
when "11" & x"4b2" => data <= x"29";
when "11" & x"4b3" => data <= x"9b";
when "11" & x"4b4" => data <= x"20";
when "11" & x"4b5" => data <= x"0b";
when "11" & x"4b6" => data <= x"be";
when "11" & x"4b7" => data <= x"a5";
when "11" & x"4b8" => data <= x"39";
when "11" & x"4b9" => data <= x"c9";
when "11" & x"4ba" => data <= x"05";
when "11" & x"4bb" => data <= x"f0";
when "11" & x"4bc" => data <= x"23";
when "11" & x"4bd" => data <= x"a5";
when "11" & x"4be" => data <= x"27";
when "11" & x"4bf" => data <= x"f0";
when "11" & x"4c0" => data <= x"ed";
when "11" & x"4c1" => data <= x"10";
when "11" & x"4c2" => data <= x"03";
when "11" & x"4c3" => data <= x"20";
when "11" & x"4c4" => data <= x"e4";
when "11" & x"4c5" => data <= x"a3";
when "11" & x"4c6" => data <= x"a0";
when "11" & x"4c7" => data <= x"00";
when "11" & x"4c8" => data <= x"a5";
when "11" & x"4c9" => data <= x"2a";
when "11" & x"4ca" => data <= x"91";
when "11" & x"4cb" => data <= x"37";
when "11" & x"4cc" => data <= x"a5";
when "11" & x"4cd" => data <= x"39";
when "11" & x"4ce" => data <= x"f0";
when "11" & x"4cf" => data <= x"0f";
when "11" & x"4d0" => data <= x"a5";
when "11" & x"4d1" => data <= x"2b";
when "11" & x"4d2" => data <= x"c8";
when "11" & x"4d3" => data <= x"91";
when "11" & x"4d4" => data <= x"37";
when "11" & x"4d5" => data <= x"a5";
when "11" & x"4d6" => data <= x"2c";
when "11" & x"4d7" => data <= x"c8";
when "11" & x"4d8" => data <= x"91";
when "11" & x"4d9" => data <= x"37";
when "11" & x"4da" => data <= x"a5";
when "11" & x"4db" => data <= x"2d";
when "11" & x"4dc" => data <= x"c8";
when "11" & x"4dd" => data <= x"91";
when "11" & x"4de" => data <= x"37";
when "11" & x"4df" => data <= x"60";
when "11" & x"4e0" => data <= x"a5";
when "11" & x"4e1" => data <= x"27";
when "11" & x"4e2" => data <= x"f0";
when "11" & x"4e3" => data <= x"ca";
when "11" & x"4e4" => data <= x"30";
when "11" & x"4e5" => data <= x"03";
when "11" & x"4e6" => data <= x"20";
when "11" & x"4e7" => data <= x"be";
when "11" & x"4e8" => data <= x"a2";
when "11" & x"4e9" => data <= x"a0";
when "11" & x"4ea" => data <= x"00";
when "11" & x"4eb" => data <= x"a5";
when "11" & x"4ec" => data <= x"30";
when "11" & x"4ed" => data <= x"91";
when "11" & x"4ee" => data <= x"37";
when "11" & x"4ef" => data <= x"c8";
when "11" & x"4f0" => data <= x"a5";
when "11" & x"4f1" => data <= x"2e";
when "11" & x"4f2" => data <= x"29";
when "11" & x"4f3" => data <= x"80";
when "11" & x"4f4" => data <= x"85";
when "11" & x"4f5" => data <= x"2e";
when "11" & x"4f6" => data <= x"a5";
when "11" & x"4f7" => data <= x"31";
when "11" & x"4f8" => data <= x"29";
when "11" & x"4f9" => data <= x"7f";
when "11" & x"4fa" => data <= x"05";
when "11" & x"4fb" => data <= x"2e";
when "11" & x"4fc" => data <= x"91";
when "11" & x"4fd" => data <= x"37";
when "11" & x"4fe" => data <= x"c8";
when "11" & x"4ff" => data <= x"a5";
when "11" & x"500" => data <= x"32";
when "11" & x"501" => data <= x"91";
when "11" & x"502" => data <= x"37";
when "11" & x"503" => data <= x"c8";
when "11" & x"504" => data <= x"a5";
when "11" & x"505" => data <= x"33";
when "11" & x"506" => data <= x"91";
when "11" & x"507" => data <= x"37";
when "11" & x"508" => data <= x"c8";
when "11" & x"509" => data <= x"a5";
when "11" & x"50a" => data <= x"34";
when "11" & x"50b" => data <= x"91";
when "11" & x"50c" => data <= x"37";
when "11" & x"50d" => data <= x"60";
when "11" & x"50e" => data <= x"85";
when "11" & x"50f" => data <= x"37";
when "11" & x"510" => data <= x"c9";
when "11" & x"511" => data <= x"80";
when "11" & x"512" => data <= x"90";
when "11" & x"513" => data <= x"44";
when "11" & x"514" => data <= x"a9";
when "11" & x"515" => data <= x"71";
when "11" & x"516" => data <= x"85";
when "11" & x"517" => data <= x"38";
when "11" & x"518" => data <= x"a9";
when "11" & x"519" => data <= x"80";
when "11" & x"51a" => data <= x"85";
when "11" & x"51b" => data <= x"39";
when "11" & x"51c" => data <= x"84";
when "11" & x"51d" => data <= x"3a";
when "11" & x"51e" => data <= x"a0";
when "11" & x"51f" => data <= x"00";
when "11" & x"520" => data <= x"c8";
when "11" & x"521" => data <= x"b1";
when "11" & x"522" => data <= x"38";
when "11" & x"523" => data <= x"10";
when "11" & x"524" => data <= x"fb";
when "11" & x"525" => data <= x"c5";
when "11" & x"526" => data <= x"37";
when "11" & x"527" => data <= x"f0";
when "11" & x"528" => data <= x"0d";
when "11" & x"529" => data <= x"c8";
when "11" & x"52a" => data <= x"98";
when "11" & x"52b" => data <= x"38";
when "11" & x"52c" => data <= x"65";
when "11" & x"52d" => data <= x"38";
when "11" & x"52e" => data <= x"85";
when "11" & x"52f" => data <= x"38";
when "11" & x"530" => data <= x"90";
when "11" & x"531" => data <= x"ec";
when "11" & x"532" => data <= x"e6";
when "11" & x"533" => data <= x"39";
when "11" & x"534" => data <= x"b0";
when "11" & x"535" => data <= x"e8";
when "11" & x"536" => data <= x"a0";
when "11" & x"537" => data <= x"00";
when "11" & x"538" => data <= x"b1";
when "11" & x"539" => data <= x"38";
when "11" & x"53a" => data <= x"30";
when "11" & x"53b" => data <= x"06";
when "11" & x"53c" => data <= x"20";
when "11" & x"53d" => data <= x"58";
when "11" & x"53e" => data <= x"b5";
when "11" & x"53f" => data <= x"c8";
when "11" & x"540" => data <= x"d0";
when "11" & x"541" => data <= x"f6";
when "11" & x"542" => data <= x"a4";
when "11" & x"543" => data <= x"3a";
when "11" & x"544" => data <= x"60";
when "11" & x"545" => data <= x"48";
when "11" & x"546" => data <= x"4a";
when "11" & x"547" => data <= x"4a";
when "11" & x"548" => data <= x"4a";
when "11" & x"549" => data <= x"4a";
when "11" & x"54a" => data <= x"20";
when "11" & x"54b" => data <= x"50";
when "11" & x"54c" => data <= x"b5";
when "11" & x"54d" => data <= x"68";
when "11" & x"54e" => data <= x"29";
when "11" & x"54f" => data <= x"0f";
when "11" & x"550" => data <= x"c9";
when "11" & x"551" => data <= x"0a";
when "11" & x"552" => data <= x"90";
when "11" & x"553" => data <= x"02";
when "11" & x"554" => data <= x"69";
when "11" & x"555" => data <= x"06";
when "11" & x"556" => data <= x"69";
when "11" & x"557" => data <= x"30";
when "11" & x"558" => data <= x"c9";
when "11" & x"559" => data <= x"0d";
when "11" & x"55a" => data <= x"d0";
when "11" & x"55b" => data <= x"0b";
when "11" & x"55c" => data <= x"20";
when "11" & x"55d" => data <= x"ee";
when "11" & x"55e" => data <= x"ff";
when "11" & x"55f" => data <= x"4c";
when "11" & x"560" => data <= x"28";
when "11" & x"561" => data <= x"bc";
when "11" & x"562" => data <= x"20";
when "11" & x"563" => data <= x"45";
when "11" & x"564" => data <= x"b5";
when "11" & x"565" => data <= x"a9";
when "11" & x"566" => data <= x"20";
when "11" & x"567" => data <= x"48";
when "11" & x"568" => data <= x"a5";
when "11" & x"569" => data <= x"23";
when "11" & x"56a" => data <= x"c5";
when "11" & x"56b" => data <= x"1e";
when "11" & x"56c" => data <= x"b0";
when "11" & x"56d" => data <= x"03";
when "11" & x"56e" => data <= x"20";
when "11" & x"56f" => data <= x"25";
when "11" & x"570" => data <= x"bc";
when "11" & x"571" => data <= x"68";
when "11" & x"572" => data <= x"e6";
when "11" & x"573" => data <= x"1e";
when "11" & x"574" => data <= x"6c";
when "11" & x"575" => data <= x"0e";
when "11" & x"576" => data <= x"02";
when "11" & x"577" => data <= x"25";
when "11" & x"578" => data <= x"1f";
when "11" & x"579" => data <= x"f0";
when "11" & x"57a" => data <= x"0e";
when "11" & x"57b" => data <= x"8a";
when "11" & x"57c" => data <= x"f0";
when "11" & x"57d" => data <= x"0b";
when "11" & x"57e" => data <= x"30";
when "11" & x"57f" => data <= x"e5";
when "11" & x"580" => data <= x"20";
when "11" & x"581" => data <= x"65";
when "11" & x"582" => data <= x"b5";
when "11" & x"583" => data <= x"20";
when "11" & x"584" => data <= x"58";
when "11" & x"585" => data <= x"b5";
when "11" & x"586" => data <= x"ca";
when "11" & x"587" => data <= x"d0";
when "11" & x"588" => data <= x"f7";
when "11" & x"589" => data <= x"60";
when "11" & x"58a" => data <= x"e6";
when "11" & x"58b" => data <= x"0a";
when "11" & x"58c" => data <= x"20";
when "11" & x"58d" => data <= x"1d";
when "11" & x"58e" => data <= x"9b";
when "11" & x"58f" => data <= x"20";
when "11" & x"590" => data <= x"4c";
when "11" & x"591" => data <= x"98";
when "11" & x"592" => data <= x"20";
when "11" & x"593" => data <= x"ee";
when "11" & x"594" => data <= x"92";
when "11" & x"595" => data <= x"a5";
when "11" & x"596" => data <= x"2a";
when "11" & x"597" => data <= x"85";
when "11" & x"598" => data <= x"1f";
when "11" & x"599" => data <= x"4c";
when "11" & x"59a" => data <= x"f6";
when "11" & x"59b" => data <= x"8a";
when "11" & x"59c" => data <= x"c8";
when "11" & x"59d" => data <= x"b1";
when "11" & x"59e" => data <= x"0b";
when "11" & x"59f" => data <= x"c9";
when "11" & x"5a0" => data <= x"4f";
when "11" & x"5a1" => data <= x"f0";
when "11" & x"5a2" => data <= x"e7";
when "11" & x"5a3" => data <= x"a9";
when "11" & x"5a4" => data <= x"00";
when "11" & x"5a5" => data <= x"85";
when "11" & x"5a6" => data <= x"3b";
when "11" & x"5a7" => data <= x"85";
when "11" & x"5a8" => data <= x"3c";
when "11" & x"5a9" => data <= x"20";
when "11" & x"5aa" => data <= x"d8";
when "11" & x"5ab" => data <= x"ae";
when "11" & x"5ac" => data <= x"20";
when "11" & x"5ad" => data <= x"df";
when "11" & x"5ae" => data <= x"97";
when "11" & x"5af" => data <= x"08";
when "11" & x"5b0" => data <= x"20";
when "11" & x"5b1" => data <= x"94";
when "11" & x"5b2" => data <= x"bd";
when "11" & x"5b3" => data <= x"a9";
when "11" & x"5b4" => data <= x"ff";
when "11" & x"5b5" => data <= x"85";
when "11" & x"5b6" => data <= x"2a";
when "11" & x"5b7" => data <= x"a9";
when "11" & x"5b8" => data <= x"7f";
when "11" & x"5b9" => data <= x"85";
when "11" & x"5ba" => data <= x"2b";
when "11" & x"5bb" => data <= x"28";
when "11" & x"5bc" => data <= x"90";
when "11" & x"5bd" => data <= x"11";
when "11" & x"5be" => data <= x"20";
when "11" & x"5bf" => data <= x"97";
when "11" & x"5c0" => data <= x"8a";
when "11" & x"5c1" => data <= x"c9";
when "11" & x"5c2" => data <= x"2c";
when "11" & x"5c3" => data <= x"f0";
when "11" & x"5c4" => data <= x"13";
when "11" & x"5c5" => data <= x"20";
when "11" & x"5c6" => data <= x"ea";
when "11" & x"5c7" => data <= x"bd";
when "11" & x"5c8" => data <= x"20";
when "11" & x"5c9" => data <= x"94";
when "11" & x"5ca" => data <= x"bd";
when "11" & x"5cb" => data <= x"c6";
when "11" & x"5cc" => data <= x"0a";
when "11" & x"5cd" => data <= x"10";
when "11" & x"5ce" => data <= x"0c";
when "11" & x"5cf" => data <= x"20";
when "11" & x"5d0" => data <= x"97";
when "11" & x"5d1" => data <= x"8a";
when "11" & x"5d2" => data <= x"c9";
when "11" & x"5d3" => data <= x"2c";
when "11" & x"5d4" => data <= x"f0";
when "11" & x"5d5" => data <= x"02";
when "11" & x"5d6" => data <= x"c6";
when "11" & x"5d7" => data <= x"0a";
when "11" & x"5d8" => data <= x"20";
when "11" & x"5d9" => data <= x"df";
when "11" & x"5da" => data <= x"97";
when "11" & x"5db" => data <= x"a5";
when "11" & x"5dc" => data <= x"2a";
when "11" & x"5dd" => data <= x"85";
when "11" & x"5de" => data <= x"31";
when "11" & x"5df" => data <= x"a5";
when "11" & x"5e0" => data <= x"2b";
when "11" & x"5e1" => data <= x"85";
when "11" & x"5e2" => data <= x"32";
when "11" & x"5e3" => data <= x"20";
when "11" & x"5e4" => data <= x"57";
when "11" & x"5e5" => data <= x"98";
when "11" & x"5e6" => data <= x"20";
when "11" & x"5e7" => data <= x"6f";
when "11" & x"5e8" => data <= x"be";
when "11" & x"5e9" => data <= x"20";
when "11" & x"5ea" => data <= x"ea";
when "11" & x"5eb" => data <= x"bd";
when "11" & x"5ec" => data <= x"20";
when "11" & x"5ed" => data <= x"70";
when "11" & x"5ee" => data <= x"99";
when "11" & x"5ef" => data <= x"a5";
when "11" & x"5f0" => data <= x"3d";
when "11" & x"5f1" => data <= x"85";
when "11" & x"5f2" => data <= x"0b";
when "11" & x"5f3" => data <= x"a5";
when "11" & x"5f4" => data <= x"3e";
when "11" & x"5f5" => data <= x"85";
when "11" & x"5f6" => data <= x"0c";
when "11" & x"5f7" => data <= x"90";
when "11" & x"5f8" => data <= x"16";
when "11" & x"5f9" => data <= x"88";
when "11" & x"5fa" => data <= x"b0";
when "11" & x"5fb" => data <= x"06";
when "11" & x"5fc" => data <= x"20";
when "11" & x"5fd" => data <= x"25";
when "11" & x"5fe" => data <= x"bc";
when "11" & x"5ff" => data <= x"20";
when "11" & x"600" => data <= x"6d";
when "11" & x"601" => data <= x"98";
when "11" & x"602" => data <= x"b1";
when "11" & x"603" => data <= x"0b";
when "11" & x"604" => data <= x"85";
when "11" & x"605" => data <= x"2b";
when "11" & x"606" => data <= x"c8";
when "11" & x"607" => data <= x"b1";
when "11" & x"608" => data <= x"0b";
when "11" & x"609" => data <= x"85";
when "11" & x"60a" => data <= x"2a";
when "11" & x"60b" => data <= x"c8";
when "11" & x"60c" => data <= x"c8";
when "11" & x"60d" => data <= x"84";
when "11" & x"60e" => data <= x"0a";
when "11" & x"60f" => data <= x"a5";
when "11" & x"610" => data <= x"2a";
when "11" & x"611" => data <= x"18";
when "11" & x"612" => data <= x"e5";
when "11" & x"613" => data <= x"31";
when "11" & x"614" => data <= x"a5";
when "11" & x"615" => data <= x"2b";
when "11" & x"616" => data <= x"e5";
when "11" & x"617" => data <= x"32";
when "11" & x"618" => data <= x"90";
when "11" & x"619" => data <= x"03";
when "11" & x"61a" => data <= x"4c";
when "11" & x"61b" => data <= x"f6";
when "11" & x"61c" => data <= x"8a";
when "11" & x"61d" => data <= x"20";
when "11" & x"61e" => data <= x"23";
when "11" & x"61f" => data <= x"99";
when "11" & x"620" => data <= x"a2";
when "11" & x"621" => data <= x"ff";
when "11" & x"622" => data <= x"86";
when "11" & x"623" => data <= x"4d";
when "11" & x"624" => data <= x"a9";
when "11" & x"625" => data <= x"01";
when "11" & x"626" => data <= x"20";
when "11" & x"627" => data <= x"77";
when "11" & x"628" => data <= x"b5";
when "11" & x"629" => data <= x"a6";
when "11" & x"62a" => data <= x"3b";
when "11" & x"62b" => data <= x"a9";
when "11" & x"62c" => data <= x"02";
when "11" & x"62d" => data <= x"20";
when "11" & x"62e" => data <= x"77";
when "11" & x"62f" => data <= x"b5";
when "11" & x"630" => data <= x"a6";
when "11" & x"631" => data <= x"3c";
when "11" & x"632" => data <= x"a9";
when "11" & x"633" => data <= x"04";
when "11" & x"634" => data <= x"20";
when "11" & x"635" => data <= x"77";
when "11" & x"636" => data <= x"b5";
when "11" & x"637" => data <= x"a4";
when "11" & x"638" => data <= x"0a";
when "11" & x"639" => data <= x"b1";
when "11" & x"63a" => data <= x"0b";
when "11" & x"63b" => data <= x"c9";
when "11" & x"63c" => data <= x"0d";
when "11" & x"63d" => data <= x"f0";
when "11" & x"63e" => data <= x"bd";
when "11" & x"63f" => data <= x"c9";
when "11" & x"640" => data <= x"22";
when "11" & x"641" => data <= x"d0";
when "11" & x"642" => data <= x"0e";
when "11" & x"643" => data <= x"a9";
when "11" & x"644" => data <= x"ff";
when "11" & x"645" => data <= x"45";
when "11" & x"646" => data <= x"4d";
when "11" & x"647" => data <= x"85";
when "11" & x"648" => data <= x"4d";
when "11" & x"649" => data <= x"a9";
when "11" & x"64a" => data <= x"22";
when "11" & x"64b" => data <= x"20";
when "11" & x"64c" => data <= x"58";
when "11" & x"64d" => data <= x"b5";
when "11" & x"64e" => data <= x"c8";
when "11" & x"64f" => data <= x"d0";
when "11" & x"650" => data <= x"e8";
when "11" & x"651" => data <= x"24";
when "11" & x"652" => data <= x"4d";
when "11" & x"653" => data <= x"10";
when "11" & x"654" => data <= x"f6";
when "11" & x"655" => data <= x"c9";
when "11" & x"656" => data <= x"8d";
when "11" & x"657" => data <= x"d0";
when "11" & x"658" => data <= x"0f";
when "11" & x"659" => data <= x"20";
when "11" & x"65a" => data <= x"eb";
when "11" & x"65b" => data <= x"97";
when "11" & x"65c" => data <= x"84";
when "11" & x"65d" => data <= x"0a";
when "11" & x"65e" => data <= x"a9";
when "11" & x"65f" => data <= x"00";
when "11" & x"660" => data <= x"85";
when "11" & x"661" => data <= x"14";
when "11" & x"662" => data <= x"20";
when "11" & x"663" => data <= x"1f";
when "11" & x"664" => data <= x"99";
when "11" & x"665" => data <= x"4c";
when "11" & x"666" => data <= x"37";
when "11" & x"667" => data <= x"b6";
when "11" & x"668" => data <= x"c9";
when "11" & x"669" => data <= x"e3";
when "11" & x"66a" => data <= x"d0";
when "11" & x"66b" => data <= x"02";
when "11" & x"66c" => data <= x"e6";
when "11" & x"66d" => data <= x"3b";
when "11" & x"66e" => data <= x"c9";
when "11" & x"66f" => data <= x"ed";
when "11" & x"670" => data <= x"d0";
when "11" & x"671" => data <= x"06";
when "11" & x"672" => data <= x"a6";
when "11" & x"673" => data <= x"3b";
when "11" & x"674" => data <= x"f0";
when "11" & x"675" => data <= x"02";
when "11" & x"676" => data <= x"c6";
when "11" & x"677" => data <= x"3b";
when "11" & x"678" => data <= x"c9";
when "11" & x"679" => data <= x"f5";
when "11" & x"67a" => data <= x"d0";
when "11" & x"67b" => data <= x"02";
when "11" & x"67c" => data <= x"e6";
when "11" & x"67d" => data <= x"3c";
when "11" & x"67e" => data <= x"c9";
when "11" & x"67f" => data <= x"fd";
when "11" & x"680" => data <= x"d0";
when "11" & x"681" => data <= x"06";
when "11" & x"682" => data <= x"a6";
when "11" & x"683" => data <= x"3c";
when "11" & x"684" => data <= x"f0";
when "11" & x"685" => data <= x"02";
when "11" & x"686" => data <= x"c6";
when "11" & x"687" => data <= x"3c";
when "11" & x"688" => data <= x"20";
when "11" & x"689" => data <= x"0e";
when "11" & x"68a" => data <= x"b5";
when "11" & x"68b" => data <= x"c8";
when "11" & x"68c" => data <= x"d0";
when "11" & x"68d" => data <= x"ab";
when "11" & x"68e" => data <= x"00";
when "11" & x"68f" => data <= x"20";
when "11" & x"690" => data <= x"4e";
when "11" & x"691" => data <= x"6f";
when "11" & x"692" => data <= x"20";
when "11" & x"693" => data <= x"e3";
when "11" & x"694" => data <= x"00";
when "11" & x"695" => data <= x"20";
when "11" & x"696" => data <= x"c9";
when "11" & x"697" => data <= x"95";
when "11" & x"698" => data <= x"d0";
when "11" & x"699" => data <= x"09";
when "11" & x"69a" => data <= x"a6";
when "11" & x"69b" => data <= x"26";
when "11" & x"69c" => data <= x"f0";
when "11" & x"69d" => data <= x"f0";
when "11" & x"69e" => data <= x"b0";
when "11" & x"69f" => data <= x"37";
when "11" & x"6a0" => data <= x"4c";
when "11" & x"6a1" => data <= x"2a";
when "11" & x"6a2" => data <= x"98";
when "11" & x"6a3" => data <= x"b0";
when "11" & x"6a4" => data <= x"fb";
when "11" & x"6a5" => data <= x"a6";
when "11" & x"6a6" => data <= x"26";
when "11" & x"6a7" => data <= x"f0";
when "11" & x"6a8" => data <= x"e5";
when "11" & x"6a9" => data <= x"a5";
when "11" & x"6aa" => data <= x"2a";
when "11" & x"6ab" => data <= x"dd";
when "11" & x"6ac" => data <= x"f1";
when "11" & x"6ad" => data <= x"04";
when "11" & x"6ae" => data <= x"d0";
when "11" & x"6af" => data <= x"0e";
when "11" & x"6b0" => data <= x"a5";
when "11" & x"6b1" => data <= x"2b";
when "11" & x"6b2" => data <= x"dd";
when "11" & x"6b3" => data <= x"f2";
when "11" & x"6b4" => data <= x"04";
when "11" & x"6b5" => data <= x"d0";
when "11" & x"6b6" => data <= x"07";
when "11" & x"6b7" => data <= x"a5";
when "11" & x"6b8" => data <= x"2c";
when "11" & x"6b9" => data <= x"dd";
when "11" & x"6ba" => data <= x"f3";
when "11" & x"6bb" => data <= x"04";
when "11" & x"6bc" => data <= x"f0";
when "11" & x"6bd" => data <= x"19";
when "11" & x"6be" => data <= x"8a";
when "11" & x"6bf" => data <= x"38";
when "11" & x"6c0" => data <= x"e9";
when "11" & x"6c1" => data <= x"0f";
when "11" & x"6c2" => data <= x"aa";
when "11" & x"6c3" => data <= x"86";
when "11" & x"6c4" => data <= x"26";
when "11" & x"6c5" => data <= x"d0";
when "11" & x"6c6" => data <= x"e2";
when "11" & x"6c7" => data <= x"00";
when "11" & x"6c8" => data <= x"21";
when "11" & x"6c9" => data <= x"43";
when "11" & x"6ca" => data <= x"61";
when "11" & x"6cb" => data <= x"6e";
when "11" & x"6cc" => data <= x"27";
when "11" & x"6cd" => data <= x"74";
when "11" & x"6ce" => data <= x"20";
when "11" & x"6cf" => data <= x"4d";
when "11" & x"6d0" => data <= x"61";
when "11" & x"6d1" => data <= x"74";
when "11" & x"6d2" => data <= x"63";
when "11" & x"6d3" => data <= x"68";
when "11" & x"6d4" => data <= x"20";
when "11" & x"6d5" => data <= x"e3";
when "11" & x"6d6" => data <= x"00";
when "11" & x"6d7" => data <= x"bd";
when "11" & x"6d8" => data <= x"f1";
when "11" & x"6d9" => data <= x"04";
when "11" & x"6da" => data <= x"85";
when "11" & x"6db" => data <= x"2a";
when "11" & x"6dc" => data <= x"bd";
when "11" & x"6dd" => data <= x"f2";
when "11" & x"6de" => data <= x"04";
when "11" & x"6df" => data <= x"85";
when "11" & x"6e0" => data <= x"2b";
when "11" & x"6e1" => data <= x"bc";
when "11" & x"6e2" => data <= x"f3";
when "11" & x"6e3" => data <= x"04";
when "11" & x"6e4" => data <= x"c0";
when "11" & x"6e5" => data <= x"05";
when "11" & x"6e6" => data <= x"f0";
when "11" & x"6e7" => data <= x"7e";
when "11" & x"6e8" => data <= x"a0";
when "11" & x"6e9" => data <= x"00";
when "11" & x"6ea" => data <= x"b1";
when "11" & x"6eb" => data <= x"2a";
when "11" & x"6ec" => data <= x"7d";
when "11" & x"6ed" => data <= x"f4";
when "11" & x"6ee" => data <= x"04";
when "11" & x"6ef" => data <= x"91";
when "11" & x"6f0" => data <= x"2a";
when "11" & x"6f1" => data <= x"85";
when "11" & x"6f2" => data <= x"37";
when "11" & x"6f3" => data <= x"c8";
when "11" & x"6f4" => data <= x"b1";
when "11" & x"6f5" => data <= x"2a";
when "11" & x"6f6" => data <= x"7d";
when "11" & x"6f7" => data <= x"f5";
when "11" & x"6f8" => data <= x"04";
when "11" & x"6f9" => data <= x"91";
when "11" & x"6fa" => data <= x"2a";
when "11" & x"6fb" => data <= x"85";
when "11" & x"6fc" => data <= x"38";
when "11" & x"6fd" => data <= x"c8";
when "11" & x"6fe" => data <= x"b1";
when "11" & x"6ff" => data <= x"2a";
when "11" & x"700" => data <= x"7d";
when "11" & x"701" => data <= x"f6";
when "11" & x"702" => data <= x"04";
when "11" & x"703" => data <= x"91";
when "11" & x"704" => data <= x"2a";
when "11" & x"705" => data <= x"85";
when "11" & x"706" => data <= x"39";
when "11" & x"707" => data <= x"c8";
when "11" & x"708" => data <= x"b1";
when "11" & x"709" => data <= x"2a";
when "11" & x"70a" => data <= x"7d";
when "11" & x"70b" => data <= x"f7";
when "11" & x"70c" => data <= x"04";
when "11" & x"70d" => data <= x"91";
when "11" & x"70e" => data <= x"2a";
when "11" & x"70f" => data <= x"a8";
when "11" & x"710" => data <= x"a5";
when "11" & x"711" => data <= x"37";
when "11" & x"712" => data <= x"38";
when "11" & x"713" => data <= x"fd";
when "11" & x"714" => data <= x"f9";
when "11" & x"715" => data <= x"04";
when "11" & x"716" => data <= x"85";
when "11" & x"717" => data <= x"37";
when "11" & x"718" => data <= x"a5";
when "11" & x"719" => data <= x"38";
when "11" & x"71a" => data <= x"fd";
when "11" & x"71b" => data <= x"fa";
when "11" & x"71c" => data <= x"04";
when "11" & x"71d" => data <= x"85";
when "11" & x"71e" => data <= x"38";
when "11" & x"71f" => data <= x"a5";
when "11" & x"720" => data <= x"39";
when "11" & x"721" => data <= x"fd";
when "11" & x"722" => data <= x"fb";
when "11" & x"723" => data <= x"04";
when "11" & x"724" => data <= x"85";
when "11" & x"725" => data <= x"39";
when "11" & x"726" => data <= x"98";
when "11" & x"727" => data <= x"fd";
when "11" & x"728" => data <= x"fc";
when "11" & x"729" => data <= x"04";
when "11" & x"72a" => data <= x"05";
when "11" & x"72b" => data <= x"37";
when "11" & x"72c" => data <= x"05";
when "11" & x"72d" => data <= x"38";
when "11" & x"72e" => data <= x"05";
when "11" & x"72f" => data <= x"39";
when "11" & x"730" => data <= x"f0";
when "11" & x"731" => data <= x"0f";
when "11" & x"732" => data <= x"98";
when "11" & x"733" => data <= x"5d";
when "11" & x"734" => data <= x"f7";
when "11" & x"735" => data <= x"04";
when "11" & x"736" => data <= x"5d";
when "11" & x"737" => data <= x"fc";
when "11" & x"738" => data <= x"04";
when "11" & x"739" => data <= x"10";
when "11" & x"73a" => data <= x"04";
when "11" & x"73b" => data <= x"b0";
when "11" & x"73c" => data <= x"04";
when "11" & x"73d" => data <= x"90";
when "11" & x"73e" => data <= x"12";
when "11" & x"73f" => data <= x"b0";
when "11" & x"740" => data <= x"10";
when "11" & x"741" => data <= x"bc";
when "11" & x"742" => data <= x"fe";
when "11" & x"743" => data <= x"04";
when "11" & x"744" => data <= x"bd";
when "11" & x"745" => data <= x"ff";
when "11" & x"746" => data <= x"04";
when "11" & x"747" => data <= x"84";
when "11" & x"748" => data <= x"0b";
when "11" & x"749" => data <= x"85";
when "11" & x"74a" => data <= x"0c";
when "11" & x"74b" => data <= x"20";
when "11" & x"74c" => data <= x"77";
when "11" & x"74d" => data <= x"98";
when "11" & x"74e" => data <= x"4c";
when "11" & x"74f" => data <= x"a3";
when "11" & x"750" => data <= x"8b";
when "11" & x"751" => data <= x"a5";
when "11" & x"752" => data <= x"26";
when "11" & x"753" => data <= x"38";
when "11" & x"754" => data <= x"e9";
when "11" & x"755" => data <= x"0f";
when "11" & x"756" => data <= x"85";
when "11" & x"757" => data <= x"26";
when "11" & x"758" => data <= x"a4";
when "11" & x"759" => data <= x"1b";
when "11" & x"75a" => data <= x"84";
when "11" & x"75b" => data <= x"0a";
when "11" & x"75c" => data <= x"20";
when "11" & x"75d" => data <= x"97";
when "11" & x"75e" => data <= x"8a";
when "11" & x"75f" => data <= x"c9";
when "11" & x"760" => data <= x"2c";
when "11" & x"761" => data <= x"d0";
when "11" & x"762" => data <= x"3e";
when "11" & x"763" => data <= x"4c";
when "11" & x"764" => data <= x"95";
when "11" & x"765" => data <= x"b6";
when "11" & x"766" => data <= x"20";
when "11" & x"767" => data <= x"54";
when "11" & x"768" => data <= x"b3";
when "11" & x"769" => data <= x"a5";
when "11" & x"76a" => data <= x"26";
when "11" & x"76b" => data <= x"18";
when "11" & x"76c" => data <= x"69";
when "11" & x"76d" => data <= x"f4";
when "11" & x"76e" => data <= x"85";
when "11" & x"76f" => data <= x"4b";
when "11" & x"770" => data <= x"a9";
when "11" & x"771" => data <= x"05";
when "11" & x"772" => data <= x"85";
when "11" & x"773" => data <= x"4c";
when "11" & x"774" => data <= x"20";
when "11" & x"775" => data <= x"00";
when "11" & x"776" => data <= x"a5";
when "11" & x"777" => data <= x"a5";
when "11" & x"778" => data <= x"2a";
when "11" & x"779" => data <= x"85";
when "11" & x"77a" => data <= x"37";
when "11" & x"77b" => data <= x"a5";
when "11" & x"77c" => data <= x"2b";
when "11" & x"77d" => data <= x"85";
when "11" & x"77e" => data <= x"38";
when "11" & x"77f" => data <= x"20";
when "11" & x"780" => data <= x"e9";
when "11" & x"781" => data <= x"b4";
when "11" & x"782" => data <= x"a5";
when "11" & x"783" => data <= x"26";
when "11" & x"784" => data <= x"85";
when "11" & x"785" => data <= x"27";
when "11" & x"786" => data <= x"18";
when "11" & x"787" => data <= x"69";
when "11" & x"788" => data <= x"f9";
when "11" & x"789" => data <= x"85";
when "11" & x"78a" => data <= x"4b";
when "11" & x"78b" => data <= x"a9";
when "11" & x"78c" => data <= x"05";
when "11" & x"78d" => data <= x"85";
when "11" & x"78e" => data <= x"4c";
when "11" & x"78f" => data <= x"20";
when "11" & x"790" => data <= x"5f";
when "11" & x"791" => data <= x"9a";
when "11" & x"792" => data <= x"f0";
when "11" & x"793" => data <= x"ad";
when "11" & x"794" => data <= x"bd";
when "11" & x"795" => data <= x"f5";
when "11" & x"796" => data <= x"04";
when "11" & x"797" => data <= x"30";
when "11" & x"798" => data <= x"04";
when "11" & x"799" => data <= x"b0";
when "11" & x"79a" => data <= x"a6";
when "11" & x"79b" => data <= x"90";
when "11" & x"79c" => data <= x"b4";
when "11" & x"79d" => data <= x"90";
when "11" & x"79e" => data <= x"a2";
when "11" & x"79f" => data <= x"b0";
when "11" & x"7a0" => data <= x"b0";
when "11" & x"7a1" => data <= x"4c";
when "11" & x"7a2" => data <= x"96";
when "11" & x"7a3" => data <= x"8b";
when "11" & x"7a4" => data <= x"00";
when "11" & x"7a5" => data <= x"22";
when "11" & x"7a6" => data <= x"e3";
when "11" & x"7a7" => data <= x"20";
when "11" & x"7a8" => data <= x"76";
when "11" & x"7a9" => data <= x"61";
when "11" & x"7aa" => data <= x"72";
when "11" & x"7ab" => data <= x"69";
when "11" & x"7ac" => data <= x"61";
when "11" & x"7ad" => data <= x"62";
when "11" & x"7ae" => data <= x"6c";
when "11" & x"7af" => data <= x"65";
when "11" & x"7b0" => data <= x"00";
when "11" & x"7b1" => data <= x"23";
when "11" & x"7b2" => data <= x"54";
when "11" & x"7b3" => data <= x"6f";
when "11" & x"7b4" => data <= x"6f";
when "11" & x"7b5" => data <= x"20";
when "11" & x"7b6" => data <= x"6d";
when "11" & x"7b7" => data <= x"61";
when "11" & x"7b8" => data <= x"6e";
when "11" & x"7b9" => data <= x"79";
when "11" & x"7ba" => data <= x"20";
when "11" & x"7bb" => data <= x"e3";
when "11" & x"7bc" => data <= x"73";
when "11" & x"7bd" => data <= x"00";
when "11" & x"7be" => data <= x"24";
when "11" & x"7bf" => data <= x"4e";
when "11" & x"7c0" => data <= x"6f";
when "11" & x"7c1" => data <= x"20";
when "11" & x"7c2" => data <= x"b8";
when "11" & x"7c3" => data <= x"00";
when "11" & x"7c4" => data <= x"20";
when "11" & x"7c5" => data <= x"82";
when "11" & x"7c6" => data <= x"95";
when "11" & x"7c7" => data <= x"f0";
when "11" & x"7c8" => data <= x"db";
when "11" & x"7c9" => data <= x"b0";
when "11" & x"7ca" => data <= x"d9";
when "11" & x"7cb" => data <= x"20";
when "11" & x"7cc" => data <= x"94";
when "11" & x"7cd" => data <= x"bd";
when "11" & x"7ce" => data <= x"20";
when "11" & x"7cf" => data <= x"41";
when "11" & x"7d0" => data <= x"98";
when "11" & x"7d1" => data <= x"20";
when "11" & x"7d2" => data <= x"b1";
when "11" & x"7d3" => data <= x"b4";
when "11" & x"7d4" => data <= x"a4";
when "11" & x"7d5" => data <= x"26";
when "11" & x"7d6" => data <= x"c0";
when "11" & x"7d7" => data <= x"96";
when "11" & x"7d8" => data <= x"b0";
when "11" & x"7d9" => data <= x"d6";
when "11" & x"7da" => data <= x"a5";
when "11" & x"7db" => data <= x"37";
when "11" & x"7dc" => data <= x"99";
when "11" & x"7dd" => data <= x"00";
when "11" & x"7de" => data <= x"05";
when "11" & x"7df" => data <= x"a5";
when "11" & x"7e0" => data <= x"38";
when "11" & x"7e1" => data <= x"99";
when "11" & x"7e2" => data <= x"01";
when "11" & x"7e3" => data <= x"05";
when "11" & x"7e4" => data <= x"a5";
when "11" & x"7e5" => data <= x"39";
when "11" & x"7e6" => data <= x"99";
when "11" & x"7e7" => data <= x"02";
when "11" & x"7e8" => data <= x"05";
when "11" & x"7e9" => data <= x"aa";
when "11" & x"7ea" => data <= x"20";
when "11" & x"7eb" => data <= x"8c";
when "11" & x"7ec" => data <= x"8a";
when "11" & x"7ed" => data <= x"c9";
when "11" & x"7ee" => data <= x"b8";
when "11" & x"7ef" => data <= x"d0";
when "11" & x"7f0" => data <= x"cc";
when "11" & x"7f1" => data <= x"e0";
when "11" & x"7f2" => data <= x"05";
when "11" & x"7f3" => data <= x"f0";
when "11" & x"7f4" => data <= x"5a";
when "11" & x"7f5" => data <= x"20";
when "11" & x"7f6" => data <= x"dd";
when "11" & x"7f7" => data <= x"92";
when "11" & x"7f8" => data <= x"a4";
when "11" & x"7f9" => data <= x"26";
when "11" & x"7fa" => data <= x"a5";
when "11" & x"7fb" => data <= x"2a";
when "11" & x"7fc" => data <= x"99";
when "11" & x"7fd" => data <= x"08";
when "11" & x"7fe" => data <= x"05";
when "11" & x"7ff" => data <= x"a5";
when "11" & x"800" => data <= x"2b";
when "11" & x"801" => data <= x"99";
when "11" & x"802" => data <= x"09";
when "11" & x"803" => data <= x"05";
when "11" & x"804" => data <= x"a5";
when "11" & x"805" => data <= x"2c";
when "11" & x"806" => data <= x"99";
when "11" & x"807" => data <= x"0a";
when "11" & x"808" => data <= x"05";
when "11" & x"809" => data <= x"a5";
when "11" & x"80a" => data <= x"2d";
when "11" & x"80b" => data <= x"99";
when "11" & x"80c" => data <= x"0b";
when "11" & x"80d" => data <= x"05";
when "11" & x"80e" => data <= x"a9";
when "11" & x"80f" => data <= x"01";
when "11" & x"810" => data <= x"20";
when "11" & x"811" => data <= x"d8";
when "11" & x"812" => data <= x"ae";
when "11" & x"813" => data <= x"20";
when "11" & x"814" => data <= x"8c";
when "11" & x"815" => data <= x"8a";
when "11" & x"816" => data <= x"c9";
when "11" & x"817" => data <= x"88";
when "11" & x"818" => data <= x"d0";
when "11" & x"819" => data <= x"05";
when "11" & x"81a" => data <= x"20";
when "11" & x"81b" => data <= x"dd";
when "11" & x"81c" => data <= x"92";
when "11" & x"81d" => data <= x"a4";
when "11" & x"81e" => data <= x"1b";
when "11" & x"81f" => data <= x"84";
when "11" & x"820" => data <= x"0a";
when "11" & x"821" => data <= x"a4";
when "11" & x"822" => data <= x"26";
when "11" & x"823" => data <= x"a5";
when "11" & x"824" => data <= x"2a";
when "11" & x"825" => data <= x"99";
when "11" & x"826" => data <= x"03";
when "11" & x"827" => data <= x"05";
when "11" & x"828" => data <= x"a5";
when "11" & x"829" => data <= x"2b";
when "11" & x"82a" => data <= x"99";
when "11" & x"82b" => data <= x"04";
when "11" & x"82c" => data <= x"05";
when "11" & x"82d" => data <= x"a5";
when "11" & x"82e" => data <= x"2c";
when "11" & x"82f" => data <= x"99";
when "11" & x"830" => data <= x"05";
when "11" & x"831" => data <= x"05";
when "11" & x"832" => data <= x"a5";
when "11" & x"833" => data <= x"2d";
when "11" & x"834" => data <= x"99";
when "11" & x"835" => data <= x"06";
when "11" & x"836" => data <= x"05";
when "11" & x"837" => data <= x"20";
when "11" & x"838" => data <= x"80";
when "11" & x"839" => data <= x"98";
when "11" & x"83a" => data <= x"a4";
when "11" & x"83b" => data <= x"26";
when "11" & x"83c" => data <= x"a5";
when "11" & x"83d" => data <= x"0b";
when "11" & x"83e" => data <= x"99";
when "11" & x"83f" => data <= x"0d";
when "11" & x"840" => data <= x"05";
when "11" & x"841" => data <= x"a5";
when "11" & x"842" => data <= x"0c";
when "11" & x"843" => data <= x"99";
when "11" & x"844" => data <= x"0e";
when "11" & x"845" => data <= x"05";
when "11" & x"846" => data <= x"18";
when "11" & x"847" => data <= x"98";
when "11" & x"848" => data <= x"69";
when "11" & x"849" => data <= x"0f";
when "11" & x"84a" => data <= x"85";
when "11" & x"84b" => data <= x"26";
when "11" & x"84c" => data <= x"4c";
when "11" & x"84d" => data <= x"a3";
when "11" & x"84e" => data <= x"8b";
when "11" & x"84f" => data <= x"20";
when "11" & x"850" => data <= x"29";
when "11" & x"851" => data <= x"9b";
when "11" & x"852" => data <= x"20";
when "11" & x"853" => data <= x"fd";
when "11" & x"854" => data <= x"92";
when "11" & x"855" => data <= x"a5";
when "11" & x"856" => data <= x"26";
when "11" & x"857" => data <= x"18";
when "11" & x"858" => data <= x"69";
when "11" & x"859" => data <= x"08";
when "11" & x"85a" => data <= x"85";
when "11" & x"85b" => data <= x"4b";
when "11" & x"85c" => data <= x"a9";
when "11" & x"85d" => data <= x"05";
when "11" & x"85e" => data <= x"85";
when "11" & x"85f" => data <= x"4c";
when "11" & x"860" => data <= x"20";
when "11" & x"861" => data <= x"8d";
when "11" & x"862" => data <= x"a3";
when "11" & x"863" => data <= x"20";
when "11" & x"864" => data <= x"99";
when "11" & x"865" => data <= x"a6";
when "11" & x"866" => data <= x"20";
when "11" & x"867" => data <= x"8c";
when "11" & x"868" => data <= x"8a";
when "11" & x"869" => data <= x"c9";
when "11" & x"86a" => data <= x"88";
when "11" & x"86b" => data <= x"d0";
when "11" & x"86c" => data <= x"08";
when "11" & x"86d" => data <= x"20";
when "11" & x"86e" => data <= x"29";
when "11" & x"86f" => data <= x"9b";
when "11" & x"870" => data <= x"20";
when "11" & x"871" => data <= x"fd";
when "11" & x"872" => data <= x"92";
when "11" & x"873" => data <= x"a4";
when "11" & x"874" => data <= x"1b";
when "11" & x"875" => data <= x"84";
when "11" & x"876" => data <= x"0a";
when "11" & x"877" => data <= x"a5";
when "11" & x"878" => data <= x"26";
when "11" & x"879" => data <= x"18";
when "11" & x"87a" => data <= x"69";
when "11" & x"87b" => data <= x"03";
when "11" & x"87c" => data <= x"85";
when "11" & x"87d" => data <= x"4b";
when "11" & x"87e" => data <= x"a9";
when "11" & x"87f" => data <= x"05";
when "11" & x"880" => data <= x"85";
when "11" & x"881" => data <= x"4c";
when "11" & x"882" => data <= x"20";
when "11" & x"883" => data <= x"8d";
when "11" & x"884" => data <= x"a3";
when "11" & x"885" => data <= x"4c";
when "11" & x"886" => data <= x"37";
when "11" & x"887" => data <= x"b8";
when "11" & x"888" => data <= x"20";
when "11" & x"889" => data <= x"9a";
when "11" & x"88a" => data <= x"b9";
when "11" & x"88b" => data <= x"20";
when "11" & x"88c" => data <= x"57";
when "11" & x"88d" => data <= x"98";
when "11" & x"88e" => data <= x"a4";
when "11" & x"88f" => data <= x"25";
when "11" & x"890" => data <= x"c0";
when "11" & x"891" => data <= x"1a";
when "11" & x"892" => data <= x"b0";
when "11" & x"893" => data <= x"0e";
when "11" & x"894" => data <= x"a5";
when "11" & x"895" => data <= x"0b";
when "11" & x"896" => data <= x"99";
when "11" & x"897" => data <= x"cc";
when "11" & x"898" => data <= x"05";
when "11" & x"899" => data <= x"a5";
when "11" & x"89a" => data <= x"0c";
when "11" & x"89b" => data <= x"99";
when "11" & x"89c" => data <= x"e6";
when "11" & x"89d" => data <= x"05";
when "11" & x"89e" => data <= x"e6";
when "11" & x"89f" => data <= x"25";
when "11" & x"8a0" => data <= x"90";
when "11" & x"8a1" => data <= x"30";
when "11" & x"8a2" => data <= x"00";
when "11" & x"8a3" => data <= x"25";
when "11" & x"8a4" => data <= x"54";
when "11" & x"8a5" => data <= x"6f";
when "11" & x"8a6" => data <= x"6f";
when "11" & x"8a7" => data <= x"20";
when "11" & x"8a8" => data <= x"6d";
when "11" & x"8a9" => data <= x"61";
when "11" & x"8aa" => data <= x"6e";
when "11" & x"8ab" => data <= x"79";
when "11" & x"8ac" => data <= x"20";
when "11" & x"8ad" => data <= x"e4";
when "11" & x"8ae" => data <= x"73";
when "11" & x"8af" => data <= x"00";
when "11" & x"8b0" => data <= x"26";
when "11" & x"8b1" => data <= x"4e";
when "11" & x"8b2" => data <= x"6f";
when "11" & x"8b3" => data <= x"20";
when "11" & x"8b4" => data <= x"e4";
when "11" & x"8b5" => data <= x"00";
when "11" & x"8b6" => data <= x"20";
when "11" & x"8b7" => data <= x"57";
when "11" & x"8b8" => data <= x"98";
when "11" & x"8b9" => data <= x"a6";
when "11" & x"8ba" => data <= x"25";
when "11" & x"8bb" => data <= x"f0";
when "11" & x"8bc" => data <= x"f2";
when "11" & x"8bd" => data <= x"c6";
when "11" & x"8be" => data <= x"25";
when "11" & x"8bf" => data <= x"bc";
when "11" & x"8c0" => data <= x"cb";
when "11" & x"8c1" => data <= x"05";
when "11" & x"8c2" => data <= x"bd";
when "11" & x"8c3" => data <= x"e5";
when "11" & x"8c4" => data <= x"05";
when "11" & x"8c5" => data <= x"84";
when "11" & x"8c6" => data <= x"0b";
when "11" & x"8c7" => data <= x"85";
when "11" & x"8c8" => data <= x"0c";
when "11" & x"8c9" => data <= x"4c";
when "11" & x"8ca" => data <= x"9b";
when "11" & x"8cb" => data <= x"8b";
when "11" & x"8cc" => data <= x"20";
when "11" & x"8cd" => data <= x"9a";
when "11" & x"8ce" => data <= x"b9";
when "11" & x"8cf" => data <= x"20";
when "11" & x"8d0" => data <= x"57";
when "11" & x"8d1" => data <= x"98";
when "11" & x"8d2" => data <= x"a5";
when "11" & x"8d3" => data <= x"20";
when "11" & x"8d4" => data <= x"f0";
when "11" & x"8d5" => data <= x"03";
when "11" & x"8d6" => data <= x"20";
when "11" & x"8d7" => data <= x"05";
when "11" & x"8d8" => data <= x"99";
when "11" & x"8d9" => data <= x"a4";
when "11" & x"8da" => data <= x"3d";
when "11" & x"8db" => data <= x"a5";
when "11" & x"8dc" => data <= x"3e";
when "11" & x"8dd" => data <= x"84";
when "11" & x"8de" => data <= x"0b";
when "11" & x"8df" => data <= x"85";
when "11" & x"8e0" => data <= x"0c";
when "11" & x"8e1" => data <= x"4c";
when "11" & x"8e2" => data <= x"a3";
when "11" & x"8e3" => data <= x"8b";
when "11" & x"8e4" => data <= x"20";
when "11" & x"8e5" => data <= x"57";
when "11" & x"8e6" => data <= x"98";
when "11" & x"8e7" => data <= x"a9";
when "11" & x"8e8" => data <= x"33";
when "11" & x"8e9" => data <= x"85";
when "11" & x"8ea" => data <= x"16";
when "11" & x"8eb" => data <= x"a9";
when "11" & x"8ec" => data <= x"b4";
when "11" & x"8ed" => data <= x"85";
when "11" & x"8ee" => data <= x"17";
when "11" & x"8ef" => data <= x"4c";
when "11" & x"8f0" => data <= x"9b";
when "11" & x"8f1" => data <= x"8b";
when "11" & x"8f2" => data <= x"20";
when "11" & x"8f3" => data <= x"97";
when "11" & x"8f4" => data <= x"8a";
when "11" & x"8f5" => data <= x"c9";
when "11" & x"8f6" => data <= x"87";
when "11" & x"8f7" => data <= x"f0";
when "11" & x"8f8" => data <= x"eb";
when "11" & x"8f9" => data <= x"a4";
when "11" & x"8fa" => data <= x"0a";
when "11" & x"8fb" => data <= x"88";
when "11" & x"8fc" => data <= x"20";
when "11" & x"8fd" => data <= x"6d";
when "11" & x"8fe" => data <= x"98";
when "11" & x"8ff" => data <= x"a5";
when "11" & x"900" => data <= x"0b";
when "11" & x"901" => data <= x"85";
when "11" & x"902" => data <= x"16";
when "11" & x"903" => data <= x"a5";
when "11" & x"904" => data <= x"0c";
when "11" & x"905" => data <= x"85";
when "11" & x"906" => data <= x"17";
when "11" & x"907" => data <= x"4c";
when "11" & x"908" => data <= x"7d";
when "11" & x"909" => data <= x"8b";
when "11" & x"90a" => data <= x"00";
when "11" & x"90b" => data <= x"27";
when "11" & x"90c" => data <= x"ee";
when "11" & x"90d" => data <= x"20";
when "11" & x"90e" => data <= x"73";
when "11" & x"90f" => data <= x"79";
when "11" & x"910" => data <= x"6e";
when "11" & x"911" => data <= x"74";
when "11" & x"912" => data <= x"61";
when "11" & x"913" => data <= x"78";
when "11" & x"914" => data <= x"00";
when "11" & x"915" => data <= x"20";
when "11" & x"916" => data <= x"97";
when "11" & x"917" => data <= x"8a";
when "11" & x"918" => data <= x"c9";
when "11" & x"919" => data <= x"85";
when "11" & x"91a" => data <= x"f0";
when "11" & x"91b" => data <= x"d6";
when "11" & x"91c" => data <= x"c6";
when "11" & x"91d" => data <= x"0a";
when "11" & x"91e" => data <= x"20";
when "11" & x"91f" => data <= x"1d";
when "11" & x"920" => data <= x"9b";
when "11" & x"921" => data <= x"20";
when "11" & x"922" => data <= x"f0";
when "11" & x"923" => data <= x"92";
when "11" & x"924" => data <= x"a4";
when "11" & x"925" => data <= x"1b";
when "11" & x"926" => data <= x"c8";
when "11" & x"927" => data <= x"84";
when "11" & x"928" => data <= x"0a";
when "11" & x"929" => data <= x"e0";
when "11" & x"92a" => data <= x"e5";
when "11" & x"92b" => data <= x"f0";
when "11" & x"92c" => data <= x"04";
when "11" & x"92d" => data <= x"e0";
when "11" & x"92e" => data <= x"e4";
when "11" & x"92f" => data <= x"d0";
when "11" & x"930" => data <= x"d9";
when "11" & x"931" => data <= x"8a";
when "11" & x"932" => data <= x"48";
when "11" & x"933" => data <= x"a5";
when "11" & x"934" => data <= x"2b";
when "11" & x"935" => data <= x"05";
when "11" & x"936" => data <= x"2c";
when "11" & x"937" => data <= x"05";
when "11" & x"938" => data <= x"2d";
when "11" & x"939" => data <= x"d0";
when "11" & x"93a" => data <= x"42";
when "11" & x"93b" => data <= x"a6";
when "11" & x"93c" => data <= x"2a";
when "11" & x"93d" => data <= x"f0";
when "11" & x"93e" => data <= x"3e";
when "11" & x"93f" => data <= x"ca";
when "11" & x"940" => data <= x"f0";
when "11" & x"941" => data <= x"1a";
when "11" & x"942" => data <= x"a4";
when "11" & x"943" => data <= x"0a";
when "11" & x"944" => data <= x"b1";
when "11" & x"945" => data <= x"0b";
when "11" & x"946" => data <= x"c8";
when "11" & x"947" => data <= x"c9";
when "11" & x"948" => data <= x"0d";
when "11" & x"949" => data <= x"f0";
when "11" & x"94a" => data <= x"32";
when "11" & x"94b" => data <= x"c9";
when "11" & x"94c" => data <= x"3a";
when "11" & x"94d" => data <= x"f0";
when "11" & x"94e" => data <= x"2e";
when "11" & x"94f" => data <= x"c9";
when "11" & x"950" => data <= x"8b";
when "11" & x"951" => data <= x"f0";
when "11" & x"952" => data <= x"2a";
when "11" & x"953" => data <= x"c9";
when "11" & x"954" => data <= x"2c";
when "11" & x"955" => data <= x"d0";
when "11" & x"956" => data <= x"ed";
when "11" & x"957" => data <= x"ca";
when "11" & x"958" => data <= x"d0";
when "11" & x"959" => data <= x"ea";
when "11" & x"95a" => data <= x"84";
when "11" & x"95b" => data <= x"0a";
when "11" & x"95c" => data <= x"20";
when "11" & x"95d" => data <= x"9a";
when "11" & x"95e" => data <= x"b9";
when "11" & x"95f" => data <= x"68";
when "11" & x"960" => data <= x"c9";
when "11" & x"961" => data <= x"e4";
when "11" & x"962" => data <= x"f0";
when "11" & x"963" => data <= x"06";
when "11" & x"964" => data <= x"20";
when "11" & x"965" => data <= x"77";
when "11" & x"966" => data <= x"98";
when "11" & x"967" => data <= x"4c";
when "11" & x"968" => data <= x"d2";
when "11" & x"969" => data <= x"b8";
when "11" & x"96a" => data <= x"a4";
when "11" & x"96b" => data <= x"0a";
when "11" & x"96c" => data <= x"b1";
when "11" & x"96d" => data <= x"0b";
when "11" & x"96e" => data <= x"c8";
when "11" & x"96f" => data <= x"c9";
when "11" & x"970" => data <= x"0d";
when "11" & x"971" => data <= x"f0";
when "11" & x"972" => data <= x"04";
when "11" & x"973" => data <= x"c9";
when "11" & x"974" => data <= x"3a";
when "11" & x"975" => data <= x"d0";
when "11" & x"976" => data <= x"f5";
when "11" & x"977" => data <= x"88";
when "11" & x"978" => data <= x"84";
when "11" & x"979" => data <= x"0a";
when "11" & x"97a" => data <= x"4c";
when "11" & x"97b" => data <= x"8b";
when "11" & x"97c" => data <= x"b8";
when "11" & x"97d" => data <= x"a4";
when "11" & x"97e" => data <= x"0a";
when "11" & x"97f" => data <= x"68";
when "11" & x"980" => data <= x"b1";
when "11" & x"981" => data <= x"0b";
when "11" & x"982" => data <= x"c8";
when "11" & x"983" => data <= x"c9";
when "11" & x"984" => data <= x"8b";
when "11" & x"985" => data <= x"f0";
when "11" & x"986" => data <= x"0e";
when "11" & x"987" => data <= x"c9";
when "11" & x"988" => data <= x"0d";
when "11" & x"989" => data <= x"d0";
when "11" & x"98a" => data <= x"f5";
when "11" & x"98b" => data <= x"00";
when "11" & x"98c" => data <= x"28";
when "11" & x"98d" => data <= x"ee";
when "11" & x"98e" => data <= x"20";
when "11" & x"98f" => data <= x"72";
when "11" & x"990" => data <= x"61";
when "11" & x"991" => data <= x"6e";
when "11" & x"992" => data <= x"67";
when "11" & x"993" => data <= x"65";
when "11" & x"994" => data <= x"00";
when "11" & x"995" => data <= x"84";
when "11" & x"996" => data <= x"0a";
when "11" & x"997" => data <= x"4c";
when "11" & x"998" => data <= x"e3";
when "11" & x"999" => data <= x"98";
when "11" & x"99a" => data <= x"20";
when "11" & x"99b" => data <= x"df";
when "11" & x"99c" => data <= x"97";
when "11" & x"99d" => data <= x"b0";
when "11" & x"99e" => data <= x"10";
when "11" & x"99f" => data <= x"20";
when "11" & x"9a0" => data <= x"1d";
when "11" & x"9a1" => data <= x"9b";
when "11" & x"9a2" => data <= x"20";
when "11" & x"9a3" => data <= x"f0";
when "11" & x"9a4" => data <= x"92";
when "11" & x"9a5" => data <= x"a5";
when "11" & x"9a6" => data <= x"1b";
when "11" & x"9a7" => data <= x"85";
when "11" & x"9a8" => data <= x"0a";
when "11" & x"9a9" => data <= x"a5";
when "11" & x"9aa" => data <= x"2b";
when "11" & x"9ab" => data <= x"29";
when "11" & x"9ac" => data <= x"7f";
when "11" & x"9ad" => data <= x"85";
when "11" & x"9ae" => data <= x"2b";
when "11" & x"9af" => data <= x"20";
when "11" & x"9b0" => data <= x"70";
when "11" & x"9b1" => data <= x"99";
when "11" & x"9b2" => data <= x"b0";
when "11" & x"9b3" => data <= x"01";
when "11" & x"9b4" => data <= x"60";
when "11" & x"9b5" => data <= x"00";
when "11" & x"9b6" => data <= x"29";
when "11" & x"9b7" => data <= x"4e";
when "11" & x"9b8" => data <= x"6f";
when "11" & x"9b9" => data <= x"20";
when "11" & x"9ba" => data <= x"73";
when "11" & x"9bb" => data <= x"75";
when "11" & x"9bc" => data <= x"63";
when "11" & x"9bd" => data <= x"68";
when "11" & x"9be" => data <= x"20";
when "11" & x"9bf" => data <= x"6c";
when "11" & x"9c0" => data <= x"69";
when "11" & x"9c1" => data <= x"6e";
when "11" & x"9c2" => data <= x"65";
when "11" & x"9c3" => data <= x"00";
when "11" & x"9c4" => data <= x"4c";
when "11" & x"9c5" => data <= x"0e";
when "11" & x"9c6" => data <= x"8c";
when "11" & x"9c7" => data <= x"4c";
when "11" & x"9c8" => data <= x"2a";
when "11" & x"9c9" => data <= x"98";
when "11" & x"9ca" => data <= x"84";
when "11" & x"9cb" => data <= x"0a";
when "11" & x"9cc" => data <= x"4c";
when "11" & x"9cd" => data <= x"98";
when "11" & x"9ce" => data <= x"8b";
when "11" & x"9cf" => data <= x"c6";
when "11" & x"9d0" => data <= x"0a";
when "11" & x"9d1" => data <= x"20";
when "11" & x"9d2" => data <= x"a9";
when "11" & x"9d3" => data <= x"bf";
when "11" & x"9d4" => data <= x"a5";
when "11" & x"9d5" => data <= x"1b";
when "11" & x"9d6" => data <= x"85";
when "11" & x"9d7" => data <= x"0a";
when "11" & x"9d8" => data <= x"84";
when "11" & x"9d9" => data <= x"4d";
when "11" & x"9da" => data <= x"20";
when "11" & x"9db" => data <= x"97";
when "11" & x"9dc" => data <= x"8a";
when "11" & x"9dd" => data <= x"c9";
when "11" & x"9de" => data <= x"2c";
when "11" & x"9df" => data <= x"d0";
when "11" & x"9e0" => data <= x"e9";
when "11" & x"9e1" => data <= x"a5";
when "11" & x"9e2" => data <= x"4d";
when "11" & x"9e3" => data <= x"48";
when "11" & x"9e4" => data <= x"20";
when "11" & x"9e5" => data <= x"82";
when "11" & x"9e6" => data <= x"95";
when "11" & x"9e7" => data <= x"f0";
when "11" & x"9e8" => data <= x"de";
when "11" & x"9e9" => data <= x"a5";
when "11" & x"9ea" => data <= x"1b";
when "11" & x"9eb" => data <= x"85";
when "11" & x"9ec" => data <= x"0a";
when "11" & x"9ed" => data <= x"68";
when "11" & x"9ee" => data <= x"85";
when "11" & x"9ef" => data <= x"4d";
when "11" & x"9f0" => data <= x"08";
when "11" & x"9f1" => data <= x"20";
when "11" & x"9f2" => data <= x"94";
when "11" & x"9f3" => data <= x"bd";
when "11" & x"9f4" => data <= x"a4";
when "11" & x"9f5" => data <= x"4d";
when "11" & x"9f6" => data <= x"20";
when "11" & x"9f7" => data <= x"d7";
when "11" & x"9f8" => data <= x"ff";
when "11" & x"9f9" => data <= x"85";
when "11" & x"9fa" => data <= x"27";
when "11" & x"9fb" => data <= x"28";
when "11" & x"9fc" => data <= x"90";
when "11" & x"9fd" => data <= x"1b";
when "11" & x"9fe" => data <= x"a5";
when "11" & x"9ff" => data <= x"27";
when "11" & x"a00" => data <= x"d0";
when "11" & x"a01" => data <= x"c2";
when "11" & x"a02" => data <= x"20";
when "11" & x"a03" => data <= x"d7";
when "11" & x"a04" => data <= x"ff";
when "11" & x"a05" => data <= x"85";
when "11" & x"a06" => data <= x"36";
when "11" & x"a07" => data <= x"aa";
when "11" & x"a08" => data <= x"f0";
when "11" & x"a09" => data <= x"09";
when "11" & x"a0a" => data <= x"20";
when "11" & x"a0b" => data <= x"d7";
when "11" & x"a0c" => data <= x"ff";
when "11" & x"a0d" => data <= x"9d";
when "11" & x"a0e" => data <= x"ff";
when "11" & x"a0f" => data <= x"05";
when "11" & x"a10" => data <= x"ca";
when "11" & x"a11" => data <= x"d0";
when "11" & x"a12" => data <= x"f7";
when "11" & x"a13" => data <= x"20";
when "11" & x"a14" => data <= x"1e";
when "11" & x"a15" => data <= x"8c";
when "11" & x"a16" => data <= x"4c";
when "11" & x"a17" => data <= x"da";
when "11" & x"a18" => data <= x"b9";
when "11" & x"a19" => data <= x"a5";
when "11" & x"a1a" => data <= x"27";
when "11" & x"a1b" => data <= x"f0";
when "11" & x"a1c" => data <= x"a7";
when "11" & x"a1d" => data <= x"30";
when "11" & x"a1e" => data <= x"0c";
when "11" & x"a1f" => data <= x"a2";
when "11" & x"a20" => data <= x"03";
when "11" & x"a21" => data <= x"20";
when "11" & x"a22" => data <= x"d7";
when "11" & x"a23" => data <= x"ff";
when "11" & x"a24" => data <= x"95";
when "11" & x"a25" => data <= x"2a";
when "11" & x"a26" => data <= x"ca";
when "11" & x"a27" => data <= x"10";
when "11" & x"a28" => data <= x"f8";
when "11" & x"a29" => data <= x"30";
when "11" & x"a2a" => data <= x"0e";
when "11" & x"a2b" => data <= x"a2";
when "11" & x"a2c" => data <= x"04";
when "11" & x"a2d" => data <= x"20";
when "11" & x"a2e" => data <= x"d7";
when "11" & x"a2f" => data <= x"ff";
when "11" & x"a30" => data <= x"9d";
when "11" & x"a31" => data <= x"6c";
when "11" & x"a32" => data <= x"04";
when "11" & x"a33" => data <= x"ca";
when "11" & x"a34" => data <= x"10";
when "11" & x"a35" => data <= x"f7";
when "11" & x"a36" => data <= x"20";
when "11" & x"a37" => data <= x"b2";
when "11" & x"a38" => data <= x"a3";
when "11" & x"a39" => data <= x"20";
when "11" & x"a3a" => data <= x"b4";
when "11" & x"a3b" => data <= x"b4";
when "11" & x"a3c" => data <= x"4c";
when "11" & x"a3d" => data <= x"da";
when "11" & x"a3e" => data <= x"b9";
when "11" & x"a3f" => data <= x"68";
when "11" & x"a40" => data <= x"68";
when "11" & x"a41" => data <= x"4c";
when "11" & x"a42" => data <= x"98";
when "11" & x"a43" => data <= x"8b";
when "11" & x"a44" => data <= x"20";
when "11" & x"a45" => data <= x"97";
when "11" & x"a46" => data <= x"8a";
when "11" & x"a47" => data <= x"c9";
when "11" & x"a48" => data <= x"23";
when "11" & x"a49" => data <= x"f0";
when "11" & x"a4a" => data <= x"84";
when "11" & x"a4b" => data <= x"c9";
when "11" & x"a4c" => data <= x"86";
when "11" & x"a4d" => data <= x"f0";
when "11" & x"a4e" => data <= x"03";
when "11" & x"a4f" => data <= x"c6";
when "11" & x"a50" => data <= x"0a";
when "11" & x"a51" => data <= x"18";
when "11" & x"a52" => data <= x"66";
when "11" & x"a53" => data <= x"4d";
when "11" & x"a54" => data <= x"46";
when "11" & x"a55" => data <= x"4d";
when "11" & x"a56" => data <= x"a9";
when "11" & x"a57" => data <= x"ff";
when "11" & x"a58" => data <= x"85";
when "11" & x"a59" => data <= x"4e";
when "11" & x"a5a" => data <= x"20";
when "11" & x"a5b" => data <= x"8a";
when "11" & x"a5c" => data <= x"8e";
when "11" & x"a5d" => data <= x"b0";
when "11" & x"a5e" => data <= x"0a";
when "11" & x"a5f" => data <= x"20";
when "11" & x"a60" => data <= x"8a";
when "11" & x"a61" => data <= x"8e";
when "11" & x"a62" => data <= x"90";
when "11" & x"a63" => data <= x"fb";
when "11" & x"a64" => data <= x"a2";
when "11" & x"a65" => data <= x"ff";
when "11" & x"a66" => data <= x"86";
when "11" & x"a67" => data <= x"4e";
when "11" & x"a68" => data <= x"18";
when "11" & x"a69" => data <= x"08";
when "11" & x"a6a" => data <= x"06";
when "11" & x"a6b" => data <= x"4d";
when "11" & x"a6c" => data <= x"28";
when "11" & x"a6d" => data <= x"66";
when "11" & x"a6e" => data <= x"4d";
when "11" & x"a6f" => data <= x"c9";
when "11" & x"a70" => data <= x"2c";
when "11" & x"a71" => data <= x"f0";
when "11" & x"a72" => data <= x"e7";
when "11" & x"a73" => data <= x"c9";
when "11" & x"a74" => data <= x"3b";
when "11" & x"a75" => data <= x"f0";
when "11" & x"a76" => data <= x"e3";
when "11" & x"a77" => data <= x"c6";
when "11" & x"a78" => data <= x"0a";
when "11" & x"a79" => data <= x"a5";
when "11" & x"a7a" => data <= x"4d";
when "11" & x"a7b" => data <= x"48";
when "11" & x"a7c" => data <= x"a5";
when "11" & x"a7d" => data <= x"4e";
when "11" & x"a7e" => data <= x"48";
when "11" & x"a7f" => data <= x"20";
when "11" & x"a80" => data <= x"82";
when "11" & x"a81" => data <= x"95";
when "11" & x"a82" => data <= x"f0";
when "11" & x"a83" => data <= x"bb";
when "11" & x"a84" => data <= x"68";
when "11" & x"a85" => data <= x"85";
when "11" & x"a86" => data <= x"4e";
when "11" & x"a87" => data <= x"68";
when "11" & x"a88" => data <= x"85";
when "11" & x"a89" => data <= x"4d";
when "11" & x"a8a" => data <= x"a5";
when "11" & x"a8b" => data <= x"1b";
when "11" & x"a8c" => data <= x"85";
when "11" & x"a8d" => data <= x"0a";
when "11" & x"a8e" => data <= x"08";
when "11" & x"a8f" => data <= x"24";
when "11" & x"a90" => data <= x"4d";
when "11" & x"a91" => data <= x"70";
when "11" & x"a92" => data <= x"06";
when "11" & x"a93" => data <= x"a5";
when "11" & x"a94" => data <= x"4e";
when "11" & x"a95" => data <= x"c9";
when "11" & x"a96" => data <= x"ff";
when "11" & x"a97" => data <= x"d0";
when "11" & x"a98" => data <= x"17";
when "11" & x"a99" => data <= x"24";
when "11" & x"a9a" => data <= x"4d";
when "11" & x"a9b" => data <= x"10";
when "11" & x"a9c" => data <= x"05";
when "11" & x"a9d" => data <= x"a9";
when "11" & x"a9e" => data <= x"3f";
when "11" & x"a9f" => data <= x"20";
when "11" & x"aa0" => data <= x"58";
when "11" & x"aa1" => data <= x"b5";
when "11" & x"aa2" => data <= x"20";
when "11" & x"aa3" => data <= x"fc";
when "11" & x"aa4" => data <= x"bb";
when "11" & x"aa5" => data <= x"84";
when "11" & x"aa6" => data <= x"36";
when "11" & x"aa7" => data <= x"06";
when "11" & x"aa8" => data <= x"4d";
when "11" & x"aa9" => data <= x"18";
when "11" & x"aaa" => data <= x"66";
when "11" & x"aab" => data <= x"4d";
when "11" & x"aac" => data <= x"24";
when "11" & x"aad" => data <= x"4d";
when "11" & x"aae" => data <= x"70";
when "11" & x"aaf" => data <= x"1d";
when "11" & x"ab0" => data <= x"85";
when "11" & x"ab1" => data <= x"1b";
when "11" & x"ab2" => data <= x"a9";
when "11" & x"ab3" => data <= x"00";
when "11" & x"ab4" => data <= x"85";
when "11" & x"ab5" => data <= x"19";
when "11" & x"ab6" => data <= x"a9";
when "11" & x"ab7" => data <= x"06";
when "11" & x"ab8" => data <= x"85";
when "11" & x"ab9" => data <= x"1a";
when "11" & x"aba" => data <= x"20";
when "11" & x"abb" => data <= x"ad";
when "11" & x"abc" => data <= x"ad";
when "11" & x"abd" => data <= x"20";
when "11" & x"abe" => data <= x"8c";
when "11" & x"abf" => data <= x"8a";
when "11" & x"ac0" => data <= x"c9";
when "11" & x"ac1" => data <= x"2c";
when "11" & x"ac2" => data <= x"f0";
when "11" & x"ac3" => data <= x"06";
when "11" & x"ac4" => data <= x"c9";
when "11" & x"ac5" => data <= x"0d";
when "11" & x"ac6" => data <= x"d0";
when "11" & x"ac7" => data <= x"f5";
when "11" & x"ac8" => data <= x"a0";
when "11" & x"ac9" => data <= x"fe";
when "11" & x"aca" => data <= x"c8";
when "11" & x"acb" => data <= x"84";
when "11" & x"acc" => data <= x"4e";
when "11" & x"acd" => data <= x"28";
when "11" & x"ace" => data <= x"b0";
when "11" & x"acf" => data <= x"0c";
when "11" & x"ad0" => data <= x"20";
when "11" & x"ad1" => data <= x"94";
when "11" & x"ad2" => data <= x"bd";
when "11" & x"ad3" => data <= x"20";
when "11" & x"ad4" => data <= x"34";
when "11" & x"ad5" => data <= x"ac";
when "11" & x"ad6" => data <= x"20";
when "11" & x"ad7" => data <= x"b4";
when "11" & x"ad8" => data <= x"b4";
when "11" & x"ad9" => data <= x"4c";
when "11" & x"ada" => data <= x"5a";
when "11" & x"adb" => data <= x"ba";
when "11" & x"adc" => data <= x"a9";
when "11" & x"add" => data <= x"00";
when "11" & x"ade" => data <= x"85";
when "11" & x"adf" => data <= x"27";
when "11" & x"ae0" => data <= x"20";
when "11" & x"ae1" => data <= x"21";
when "11" & x"ae2" => data <= x"8c";
when "11" & x"ae3" => data <= x"4c";
when "11" & x"ae4" => data <= x"5a";
when "11" & x"ae5" => data <= x"ba";
when "11" & x"ae6" => data <= x"a0";
when "11" & x"ae7" => data <= x"00";
when "11" & x"ae8" => data <= x"84";
when "11" & x"ae9" => data <= x"3d";
when "11" & x"aea" => data <= x"a4";
when "11" & x"aeb" => data <= x"18";
when "11" & x"aec" => data <= x"84";
when "11" & x"aed" => data <= x"3e";
when "11" & x"aee" => data <= x"20";
when "11" & x"aef" => data <= x"97";
when "11" & x"af0" => data <= x"8a";
when "11" & x"af1" => data <= x"c6";
when "11" & x"af2" => data <= x"0a";
when "11" & x"af3" => data <= x"c9";
when "11" & x"af4" => data <= x"3a";
when "11" & x"af5" => data <= x"f0";
when "11" & x"af6" => data <= x"10";
when "11" & x"af7" => data <= x"c9";
when "11" & x"af8" => data <= x"0d";
when "11" & x"af9" => data <= x"f0";
when "11" & x"afa" => data <= x"0c";
when "11" & x"afb" => data <= x"c9";
when "11" & x"afc" => data <= x"8b";
when "11" & x"afd" => data <= x"f0";
when "11" & x"afe" => data <= x"08";
when "11" & x"aff" => data <= x"20";
when "11" & x"b00" => data <= x"9a";
when "11" & x"b01" => data <= x"b9";
when "11" & x"b02" => data <= x"a0";
when "11" & x"b03" => data <= x"01";
when "11" & x"b04" => data <= x"20";
when "11" & x"b05" => data <= x"55";
when "11" & x"b06" => data <= x"be";
when "11" & x"b07" => data <= x"20";
when "11" & x"b08" => data <= x"57";
when "11" & x"b09" => data <= x"98";
when "11" & x"b0a" => data <= x"a5";
when "11" & x"b0b" => data <= x"3d";
when "11" & x"b0c" => data <= x"85";
when "11" & x"b0d" => data <= x"1c";
when "11" & x"b0e" => data <= x"a5";
when "11" & x"b0f" => data <= x"3e";
when "11" & x"b10" => data <= x"85";
when "11" & x"b11" => data <= x"1d";
when "11" & x"b12" => data <= x"4c";
when "11" & x"b13" => data <= x"9b";
when "11" & x"b14" => data <= x"8b";
when "11" & x"b15" => data <= x"20";
when "11" & x"b16" => data <= x"97";
when "11" & x"b17" => data <= x"8a";
when "11" & x"b18" => data <= x"c9";
when "11" & x"b19" => data <= x"2c";
when "11" & x"b1a" => data <= x"f0";
when "11" & x"b1b" => data <= x"03";
when "11" & x"b1c" => data <= x"4c";
when "11" & x"b1d" => data <= x"96";
when "11" & x"b1e" => data <= x"8b";
when "11" & x"b1f" => data <= x"20";
when "11" & x"b20" => data <= x"82";
when "11" & x"b21" => data <= x"95";
when "11" & x"b22" => data <= x"f0";
when "11" & x"b23" => data <= x"f1";
when "11" & x"b24" => data <= x"b0";
when "11" & x"b25" => data <= x"0c";
when "11" & x"b26" => data <= x"20";
when "11" & x"b27" => data <= x"50";
when "11" & x"b28" => data <= x"bb";
when "11" & x"b29" => data <= x"20";
when "11" & x"b2a" => data <= x"94";
when "11" & x"b2b" => data <= x"bd";
when "11" & x"b2c" => data <= x"20";
when "11" & x"b2d" => data <= x"b1";
when "11" & x"b2e" => data <= x"b4";
when "11" & x"b2f" => data <= x"4c";
when "11" & x"b30" => data <= x"40";
when "11" & x"b31" => data <= x"bb";
when "11" & x"b32" => data <= x"20";
when "11" & x"b33" => data <= x"50";
when "11" & x"b34" => data <= x"bb";
when "11" & x"b35" => data <= x"20";
when "11" & x"b36" => data <= x"94";
when "11" & x"b37" => data <= x"bd";
when "11" & x"b38" => data <= x"20";
when "11" & x"b39" => data <= x"ad";
when "11" & x"b3a" => data <= x"ad";
when "11" & x"b3b" => data <= x"85";
when "11" & x"b3c" => data <= x"27";
when "11" & x"b3d" => data <= x"20";
when "11" & x"b3e" => data <= x"1e";
when "11" & x"b3f" => data <= x"8c";
when "11" & x"b40" => data <= x"18";
when "11" & x"b41" => data <= x"a5";
when "11" & x"b42" => data <= x"1b";
when "11" & x"b43" => data <= x"65";
when "11" & x"b44" => data <= x"19";
when "11" & x"b45" => data <= x"85";
when "11" & x"b46" => data <= x"1c";
when "11" & x"b47" => data <= x"a5";
when "11" & x"b48" => data <= x"1a";
when "11" & x"b49" => data <= x"69";
when "11" & x"b4a" => data <= x"00";
when "11" & x"b4b" => data <= x"85";
when "11" & x"b4c" => data <= x"1d";
when "11" & x"b4d" => data <= x"4c";
when "11" & x"b4e" => data <= x"15";
when "11" & x"b4f" => data <= x"bb";
when "11" & x"b50" => data <= x"a5";
when "11" & x"b51" => data <= x"1b";
when "11" & x"b52" => data <= x"85";
when "11" & x"b53" => data <= x"0a";
when "11" & x"b54" => data <= x"a5";
when "11" & x"b55" => data <= x"1c";
when "11" & x"b56" => data <= x"85";
when "11" & x"b57" => data <= x"19";
when "11" & x"b58" => data <= x"a5";
when "11" & x"b59" => data <= x"1d";
when "11" & x"b5a" => data <= x"85";
when "11" & x"b5b" => data <= x"1a";
when "11" & x"b5c" => data <= x"a0";
when "11" & x"b5d" => data <= x"00";
when "11" & x"b5e" => data <= x"84";
when "11" & x"b5f" => data <= x"1b";
when "11" & x"b60" => data <= x"20";
when "11" & x"b61" => data <= x"8c";
when "11" & x"b62" => data <= x"8a";
when "11" & x"b63" => data <= x"c9";
when "11" & x"b64" => data <= x"2c";
when "11" & x"b65" => data <= x"f0";
when "11" & x"b66" => data <= x"49";
when "11" & x"b67" => data <= x"c9";
when "11" & x"b68" => data <= x"dc";
when "11" & x"b69" => data <= x"f0";
when "11" & x"b6a" => data <= x"45";
when "11" & x"b6b" => data <= x"c9";
when "11" & x"b6c" => data <= x"0d";
when "11" & x"b6d" => data <= x"f0";
when "11" & x"b6e" => data <= x"0b";
when "11" & x"b6f" => data <= x"20";
when "11" & x"b70" => data <= x"8c";
when "11" & x"b71" => data <= x"8a";
when "11" & x"b72" => data <= x"c9";
when "11" & x"b73" => data <= x"2c";
when "11" & x"b74" => data <= x"f0";
when "11" & x"b75" => data <= x"3a";
when "11" & x"b76" => data <= x"c9";
when "11" & x"b77" => data <= x"0d";
when "11" & x"b78" => data <= x"d0";
when "11" & x"b79" => data <= x"f5";
when "11" & x"b7a" => data <= x"a4";
when "11" & x"b7b" => data <= x"1b";
when "11" & x"b7c" => data <= x"b1";
when "11" & x"b7d" => data <= x"19";
when "11" & x"b7e" => data <= x"30";
when "11" & x"b7f" => data <= x"1c";
when "11" & x"b80" => data <= x"c8";
when "11" & x"b81" => data <= x"c8";
when "11" & x"b82" => data <= x"b1";
when "11" & x"b83" => data <= x"19";
when "11" & x"b84" => data <= x"aa";
when "11" & x"b85" => data <= x"c8";
when "11" & x"b86" => data <= x"b1";
when "11" & x"b87" => data <= x"19";
when "11" & x"b88" => data <= x"c9";
when "11" & x"b89" => data <= x"20";
when "11" & x"b8a" => data <= x"f0";
when "11" & x"b8b" => data <= x"f9";
when "11" & x"b8c" => data <= x"c9";
when "11" & x"b8d" => data <= x"dc";
when "11" & x"b8e" => data <= x"f0";
when "11" & x"b8f" => data <= x"1d";
when "11" & x"b90" => data <= x"8a";
when "11" & x"b91" => data <= x"18";
when "11" & x"b92" => data <= x"65";
when "11" & x"b93" => data <= x"19";
when "11" & x"b94" => data <= x"85";
when "11" & x"b95" => data <= x"19";
when "11" & x"b96" => data <= x"90";
when "11" & x"b97" => data <= x"e2";
when "11" & x"b98" => data <= x"e6";
when "11" & x"b99" => data <= x"1a";
when "11" & x"b9a" => data <= x"b0";
when "11" & x"b9b" => data <= x"de";
when "11" & x"b9c" => data <= x"00";
when "11" & x"b9d" => data <= x"2a";
when "11" & x"b9e" => data <= x"4f";
when "11" & x"b9f" => data <= x"75";
when "11" & x"ba0" => data <= x"74";
when "11" & x"ba1" => data <= x"20";
when "11" & x"ba2" => data <= x"6f";
when "11" & x"ba3" => data <= x"66";
when "11" & x"ba4" => data <= x"20";
when "11" & x"ba5" => data <= x"dc";
when "11" & x"ba6" => data <= x"00";
when "11" & x"ba7" => data <= x"2b";
when "11" & x"ba8" => data <= x"4e";
when "11" & x"ba9" => data <= x"6f";
when "11" & x"baa" => data <= x"20";
when "11" & x"bab" => data <= x"f5";
when "11" & x"bac" => data <= x"00";
when "11" & x"bad" => data <= x"c8";
when "11" & x"bae" => data <= x"84";
when "11" & x"baf" => data <= x"1b";
when "11" & x"bb0" => data <= x"60";
when "11" & x"bb1" => data <= x"20";
when "11" & x"bb2" => data <= x"1d";
when "11" & x"bb3" => data <= x"9b";
when "11" & x"bb4" => data <= x"20";
when "11" & x"bb5" => data <= x"4c";
when "11" & x"bb6" => data <= x"98";
when "11" & x"bb7" => data <= x"20";
when "11" & x"bb8" => data <= x"ee";
when "11" & x"bb9" => data <= x"92";
when "11" & x"bba" => data <= x"a6";
when "11" & x"bbb" => data <= x"24";
when "11" & x"bbc" => data <= x"f0";
when "11" & x"bbd" => data <= x"e8";
when "11" & x"bbe" => data <= x"a5";
when "11" & x"bbf" => data <= x"2a";
when "11" & x"bc0" => data <= x"05";
when "11" & x"bc1" => data <= x"2b";
when "11" & x"bc2" => data <= x"05";
when "11" & x"bc3" => data <= x"2c";
when "11" & x"bc4" => data <= x"05";
when "11" & x"bc5" => data <= x"2d";
when "11" & x"bc6" => data <= x"f0";
when "11" & x"bc7" => data <= x"05";
when "11" & x"bc8" => data <= x"c6";
when "11" & x"bc9" => data <= x"24";
when "11" & x"bca" => data <= x"4c";
when "11" & x"bcb" => data <= x"9b";
when "11" & x"bcc" => data <= x"8b";
when "11" & x"bcd" => data <= x"bc";
when "11" & x"bce" => data <= x"a3";
when "11" & x"bcf" => data <= x"05";
when "11" & x"bd0" => data <= x"bd";
when "11" & x"bd1" => data <= x"b7";
when "11" & x"bd2" => data <= x"05";
when "11" & x"bd3" => data <= x"4c";
when "11" & x"bd4" => data <= x"dd";
when "11" & x"bd5" => data <= x"b8";
when "11" & x"bd6" => data <= x"00";
when "11" & x"bd7" => data <= x"2c";
when "11" & x"bd8" => data <= x"54";
when "11" & x"bd9" => data <= x"6f";
when "11" & x"bda" => data <= x"6f";
when "11" & x"bdb" => data <= x"20";
when "11" & x"bdc" => data <= x"6d";
when "11" & x"bdd" => data <= x"61";
when "11" & x"bde" => data <= x"6e";
when "11" & x"bdf" => data <= x"79";
when "11" & x"be0" => data <= x"20";
when "11" & x"be1" => data <= x"f5";
when "11" & x"be2" => data <= x"73";
when "11" & x"be3" => data <= x"00";
when "11" & x"be4" => data <= x"a6";
when "11" & x"be5" => data <= x"24";
when "11" & x"be6" => data <= x"e0";
when "11" & x"be7" => data <= x"14";
when "11" & x"be8" => data <= x"b0";
when "11" & x"be9" => data <= x"ec";
when "11" & x"bea" => data <= x"20";
when "11" & x"beb" => data <= x"6d";
when "11" & x"bec" => data <= x"98";
when "11" & x"bed" => data <= x"a5";
when "11" & x"bee" => data <= x"0b";
when "11" & x"bef" => data <= x"9d";
when "11" & x"bf0" => data <= x"a4";
when "11" & x"bf1" => data <= x"05";
when "11" & x"bf2" => data <= x"a5";
when "11" & x"bf3" => data <= x"0c";
when "11" & x"bf4" => data <= x"9d";
when "11" & x"bf5" => data <= x"b8";
when "11" & x"bf6" => data <= x"05";
when "11" & x"bf7" => data <= x"e6";
when "11" & x"bf8" => data <= x"24";
when "11" & x"bf9" => data <= x"4c";
when "11" & x"bfa" => data <= x"a3";
when "11" & x"bfb" => data <= x"8b";
when "11" & x"bfc" => data <= x"a0";
when "11" & x"bfd" => data <= x"00";
when "11" & x"bfe" => data <= x"a9";
when "11" & x"bff" => data <= x"06";
when "11" & x"c00" => data <= x"d0";
when "11" & x"c01" => data <= x"07";
when "11" & x"c02" => data <= x"20";
when "11" & x"c03" => data <= x"58";
when "11" & x"c04" => data <= x"b5";
when "11" & x"c05" => data <= x"a0";
when "11" & x"c06" => data <= x"00";
when "11" & x"c07" => data <= x"a9";
when "11" & x"c08" => data <= x"07";
when "11" & x"c09" => data <= x"84";
when "11" & x"c0a" => data <= x"37";
when "11" & x"c0b" => data <= x"85";
when "11" & x"c0c" => data <= x"38";
when "11" & x"c0d" => data <= x"a9";
when "11" & x"c0e" => data <= x"ee";
when "11" & x"c0f" => data <= x"85";
when "11" & x"c10" => data <= x"39";
when "11" & x"c11" => data <= x"a9";
when "11" & x"c12" => data <= x"20";
when "11" & x"c13" => data <= x"85";
when "11" & x"c14" => data <= x"3a";
when "11" & x"c15" => data <= x"a0";
when "11" & x"c16" => data <= x"ff";
when "11" & x"c17" => data <= x"84";
when "11" & x"c18" => data <= x"3b";
when "11" & x"c19" => data <= x"c8";
when "11" & x"c1a" => data <= x"a2";
when "11" & x"c1b" => data <= x"37";
when "11" & x"c1c" => data <= x"98";
when "11" & x"c1d" => data <= x"20";
when "11" & x"c1e" => data <= x"f1";
when "11" & x"c1f" => data <= x"ff";
when "11" & x"c20" => data <= x"90";
when "11" & x"c21" => data <= x"06";
when "11" & x"c22" => data <= x"4c";
when "11" & x"c23" => data <= x"38";
when "11" & x"c24" => data <= x"98";
when "11" & x"c25" => data <= x"20";
when "11" & x"c26" => data <= x"e7";
when "11" & x"c27" => data <= x"ff";
when "11" & x"c28" => data <= x"a9";
when "11" & x"c29" => data <= x"00";
when "11" & x"c2a" => data <= x"85";
when "11" & x"c2b" => data <= x"1e";
when "11" & x"c2c" => data <= x"60";
when "11" & x"c2d" => data <= x"20";
when "11" & x"c2e" => data <= x"70";
when "11" & x"c2f" => data <= x"99";
when "11" & x"c30" => data <= x"b0";
when "11" & x"c31" => data <= x"4e";
when "11" & x"c32" => data <= x"a5";
when "11" & x"c33" => data <= x"3d";
when "11" & x"c34" => data <= x"e9";
when "11" & x"c35" => data <= x"02";
when "11" & x"c36" => data <= x"85";
when "11" & x"c37" => data <= x"37";
when "11" & x"c38" => data <= x"85";
when "11" & x"c39" => data <= x"3d";
when "11" & x"c3a" => data <= x"85";
when "11" & x"c3b" => data <= x"12";
when "11" & x"c3c" => data <= x"a5";
when "11" & x"c3d" => data <= x"3e";
when "11" & x"c3e" => data <= x"e9";
when "11" & x"c3f" => data <= x"00";
when "11" & x"c40" => data <= x"85";
when "11" & x"c41" => data <= x"38";
when "11" & x"c42" => data <= x"85";
when "11" & x"c43" => data <= x"13";
when "11" & x"c44" => data <= x"85";
when "11" & x"c45" => data <= x"3e";
when "11" & x"c46" => data <= x"a0";
when "11" & x"c47" => data <= x"03";
when "11" & x"c48" => data <= x"b1";
when "11" & x"c49" => data <= x"37";
when "11" & x"c4a" => data <= x"18";
when "11" & x"c4b" => data <= x"65";
when "11" & x"c4c" => data <= x"37";
when "11" & x"c4d" => data <= x"85";
when "11" & x"c4e" => data <= x"37";
when "11" & x"c4f" => data <= x"90";
when "11" & x"c50" => data <= x"02";
when "11" & x"c51" => data <= x"e6";
when "11" & x"c52" => data <= x"38";
when "11" & x"c53" => data <= x"a0";
when "11" & x"c54" => data <= x"00";
when "11" & x"c55" => data <= x"b1";
when "11" & x"c56" => data <= x"37";
when "11" & x"c57" => data <= x"91";
when "11" & x"c58" => data <= x"12";
when "11" & x"c59" => data <= x"c9";
when "11" & x"c5a" => data <= x"0d";
when "11" & x"c5b" => data <= x"f0";
when "11" & x"c5c" => data <= x"09";
when "11" & x"c5d" => data <= x"c8";
when "11" & x"c5e" => data <= x"d0";
when "11" & x"c5f" => data <= x"f5";
when "11" & x"c60" => data <= x"e6";
when "11" & x"c61" => data <= x"38";
when "11" & x"c62" => data <= x"e6";
when "11" & x"c63" => data <= x"13";
when "11" & x"c64" => data <= x"d0";
when "11" & x"c65" => data <= x"ef";
when "11" & x"c66" => data <= x"c8";
when "11" & x"c67" => data <= x"d0";
when "11" & x"c68" => data <= x"04";
when "11" & x"c69" => data <= x"e6";
when "11" & x"c6a" => data <= x"38";
when "11" & x"c6b" => data <= x"e6";
when "11" & x"c6c" => data <= x"13";
when "11" & x"c6d" => data <= x"b1";
when "11" & x"c6e" => data <= x"37";
when "11" & x"c6f" => data <= x"91";
when "11" & x"c70" => data <= x"12";
when "11" & x"c71" => data <= x"30";
when "11" & x"c72" => data <= x"09";
when "11" & x"c73" => data <= x"20";
when "11" & x"c74" => data <= x"81";
when "11" & x"c75" => data <= x"bc";
when "11" & x"c76" => data <= x"20";
when "11" & x"c77" => data <= x"81";
when "11" & x"c78" => data <= x"bc";
when "11" & x"c79" => data <= x"4c";
when "11" & x"c7a" => data <= x"5d";
when "11" & x"c7b" => data <= x"bc";
when "11" & x"c7c" => data <= x"20";
when "11" & x"c7d" => data <= x"92";
when "11" & x"c7e" => data <= x"be";
when "11" & x"c7f" => data <= x"18";
when "11" & x"c80" => data <= x"60";
when "11" & x"c81" => data <= x"c8";
when "11" & x"c82" => data <= x"d0";
when "11" & x"c83" => data <= x"04";
when "11" & x"c84" => data <= x"e6";
when "11" & x"c85" => data <= x"13";
when "11" & x"c86" => data <= x"e6";
when "11" & x"c87" => data <= x"38";
when "11" & x"c88" => data <= x"b1";
when "11" & x"c89" => data <= x"37";
when "11" & x"c8a" => data <= x"91";
when "11" & x"c8b" => data <= x"12";
when "11" & x"c8c" => data <= x"60";
when "11" & x"c8d" => data <= x"84";
when "11" & x"c8e" => data <= x"3b";
when "11" & x"c8f" => data <= x"20";
when "11" & x"c90" => data <= x"2d";
when "11" & x"c91" => data <= x"bc";
when "11" & x"c92" => data <= x"a0";
when "11" & x"c93" => data <= x"07";
when "11" & x"c94" => data <= x"84";
when "11" & x"c95" => data <= x"3c";
when "11" & x"c96" => data <= x"a0";
when "11" & x"c97" => data <= x"00";
when "11" & x"c98" => data <= x"a9";
when "11" & x"c99" => data <= x"0d";
when "11" & x"c9a" => data <= x"d1";
when "11" & x"c9b" => data <= x"3b";
when "11" & x"c9c" => data <= x"f0";
when "11" & x"c9d" => data <= x"72";
when "11" & x"c9e" => data <= x"c8";
when "11" & x"c9f" => data <= x"d1";
when "11" & x"ca0" => data <= x"3b";
when "11" & x"ca1" => data <= x"d0";
when "11" & x"ca2" => data <= x"fb";
when "11" & x"ca3" => data <= x"c8";
when "11" & x"ca4" => data <= x"c8";
when "11" & x"ca5" => data <= x"c8";
when "11" & x"ca6" => data <= x"84";
when "11" & x"ca7" => data <= x"3f";
when "11" & x"ca8" => data <= x"e6";
when "11" & x"ca9" => data <= x"3f";
when "11" & x"caa" => data <= x"a5";
when "11" & x"cab" => data <= x"12";
when "11" & x"cac" => data <= x"85";
when "11" & x"cad" => data <= x"39";
when "11" & x"cae" => data <= x"a5";
when "11" & x"caf" => data <= x"13";
when "11" & x"cb0" => data <= x"85";
when "11" & x"cb1" => data <= x"3a";
when "11" & x"cb2" => data <= x"20";
when "11" & x"cb3" => data <= x"92";
when "11" & x"cb4" => data <= x"be";
when "11" & x"cb5" => data <= x"85";
when "11" & x"cb6" => data <= x"37";
when "11" & x"cb7" => data <= x"a5";
when "11" & x"cb8" => data <= x"13";
when "11" & x"cb9" => data <= x"85";
when "11" & x"cba" => data <= x"38";
when "11" & x"cbb" => data <= x"88";
when "11" & x"cbc" => data <= x"a5";
when "11" & x"cbd" => data <= x"06";
when "11" & x"cbe" => data <= x"c5";
when "11" & x"cbf" => data <= x"12";
when "11" & x"cc0" => data <= x"a5";
when "11" & x"cc1" => data <= x"07";
when "11" & x"cc2" => data <= x"e5";
when "11" & x"cc3" => data <= x"13";
when "11" & x"cc4" => data <= x"b0";
when "11" & x"cc5" => data <= x"10";
when "11" & x"cc6" => data <= x"20";
when "11" & x"cc7" => data <= x"6f";
when "11" & x"cc8" => data <= x"be";
when "11" & x"cc9" => data <= x"20";
when "11" & x"cca" => data <= x"20";
when "11" & x"ccb" => data <= x"bd";
when "11" & x"ccc" => data <= x"00";
when "11" & x"ccd" => data <= x"00";
when "11" & x"cce" => data <= x"86";
when "11" & x"ccf" => data <= x"20";
when "11" & x"cd0" => data <= x"73";
when "11" & x"cd1" => data <= x"70";
when "11" & x"cd2" => data <= x"61";
when "11" & x"cd3" => data <= x"63";
when "11" & x"cd4" => data <= x"65";
when "11" & x"cd5" => data <= x"00";
when "11" & x"cd6" => data <= x"b1";
when "11" & x"cd7" => data <= x"39";
when "11" & x"cd8" => data <= x"91";
when "11" & x"cd9" => data <= x"37";
when "11" & x"cda" => data <= x"98";
when "11" & x"cdb" => data <= x"d0";
when "11" & x"cdc" => data <= x"04";
when "11" & x"cdd" => data <= x"c6";
when "11" & x"cde" => data <= x"3a";
when "11" & x"cdf" => data <= x"c6";
when "11" & x"ce0" => data <= x"38";
when "11" & x"ce1" => data <= x"88";
when "11" & x"ce2" => data <= x"98";
when "11" & x"ce3" => data <= x"65";
when "11" & x"ce4" => data <= x"39";
when "11" & x"ce5" => data <= x"a6";
when "11" & x"ce6" => data <= x"3a";
when "11" & x"ce7" => data <= x"90";
when "11" & x"ce8" => data <= x"01";
when "11" & x"ce9" => data <= x"e8";
when "11" & x"cea" => data <= x"c5";
when "11" & x"ceb" => data <= x"3d";
when "11" & x"cec" => data <= x"8a";
when "11" & x"ced" => data <= x"e5";
when "11" & x"cee" => data <= x"3e";
when "11" & x"cef" => data <= x"b0";
when "11" & x"cf0" => data <= x"e5";
when "11" & x"cf1" => data <= x"38";
when "11" & x"cf2" => data <= x"a0";
when "11" & x"cf3" => data <= x"01";
when "11" & x"cf4" => data <= x"a5";
when "11" & x"cf5" => data <= x"2b";
when "11" & x"cf6" => data <= x"91";
when "11" & x"cf7" => data <= x"3d";
when "11" & x"cf8" => data <= x"c8";
when "11" & x"cf9" => data <= x"a5";
when "11" & x"cfa" => data <= x"2a";
when "11" & x"cfb" => data <= x"91";
when "11" & x"cfc" => data <= x"3d";
when "11" & x"cfd" => data <= x"c8";
when "11" & x"cfe" => data <= x"a5";
when "11" & x"cff" => data <= x"3f";
when "11" & x"d00" => data <= x"91";
when "11" & x"d01" => data <= x"3d";
when "11" & x"d02" => data <= x"20";
when "11" & x"d03" => data <= x"56";
when "11" & x"d04" => data <= x"be";
when "11" & x"d05" => data <= x"a0";
when "11" & x"d06" => data <= x"ff";
when "11" & x"d07" => data <= x"c8";
when "11" & x"d08" => data <= x"b1";
when "11" & x"d09" => data <= x"3b";
when "11" & x"d0a" => data <= x"91";
when "11" & x"d0b" => data <= x"3d";
when "11" & x"d0c" => data <= x"c9";
when "11" & x"d0d" => data <= x"0d";
when "11" & x"d0e" => data <= x"d0";
when "11" & x"d0f" => data <= x"f7";
when "11" & x"d10" => data <= x"60";
when "11" & x"d11" => data <= x"20";
when "11" & x"d12" => data <= x"57";
when "11" & x"d13" => data <= x"98";
when "11" & x"d14" => data <= x"20";
when "11" & x"d15" => data <= x"20";
when "11" & x"d16" => data <= x"bd";
when "11" & x"d17" => data <= x"a5";
when "11" & x"d18" => data <= x"18";
when "11" & x"d19" => data <= x"85";
when "11" & x"d1a" => data <= x"0c";
when "11" & x"d1b" => data <= x"86";
when "11" & x"d1c" => data <= x"0b";
when "11" & x"d1d" => data <= x"4c";
when "11" & x"d1e" => data <= x"0b";
when "11" & x"d1f" => data <= x"8b";
when "11" & x"d20" => data <= x"a5";
when "11" & x"d21" => data <= x"12";
when "11" & x"d22" => data <= x"85";
when "11" & x"d23" => data <= x"00";
when "11" & x"d24" => data <= x"85";
when "11" & x"d25" => data <= x"02";
when "11" & x"d26" => data <= x"a5";
when "11" & x"d27" => data <= x"13";
when "11" & x"d28" => data <= x"85";
when "11" & x"d29" => data <= x"01";
when "11" & x"d2a" => data <= x"85";
when "11" & x"d2b" => data <= x"03";
when "11" & x"d2c" => data <= x"20";
when "11" & x"d2d" => data <= x"3a";
when "11" & x"d2e" => data <= x"bd";
when "11" & x"d2f" => data <= x"a2";
when "11" & x"d30" => data <= x"80";
when "11" & x"d31" => data <= x"a9";
when "11" & x"d32" => data <= x"00";
when "11" & x"d33" => data <= x"9d";
when "11" & x"d34" => data <= x"7f";
when "11" & x"d35" => data <= x"04";
when "11" & x"d36" => data <= x"ca";
when "11" & x"d37" => data <= x"d0";
when "11" & x"d38" => data <= x"fa";
when "11" & x"d39" => data <= x"60";
when "11" & x"d3a" => data <= x"a5";
when "11" & x"d3b" => data <= x"18";
when "11" & x"d3c" => data <= x"85";
when "11" & x"d3d" => data <= x"1d";
when "11" & x"d3e" => data <= x"a5";
when "11" & x"d3f" => data <= x"06";
when "11" & x"d40" => data <= x"85";
when "11" & x"d41" => data <= x"04";
when "11" & x"d42" => data <= x"a5";
when "11" & x"d43" => data <= x"07";
when "11" & x"d44" => data <= x"85";
when "11" & x"d45" => data <= x"05";
when "11" & x"d46" => data <= x"a9";
when "11" & x"d47" => data <= x"00";
when "11" & x"d48" => data <= x"85";
when "11" & x"d49" => data <= x"24";
when "11" & x"d4a" => data <= x"85";
when "11" & x"d4b" => data <= x"26";
when "11" & x"d4c" => data <= x"85";
when "11" & x"d4d" => data <= x"25";
when "11" & x"d4e" => data <= x"85";
when "11" & x"d4f" => data <= x"1c";
when "11" & x"d50" => data <= x"60";
when "11" & x"d51" => data <= x"a5";
when "11" & x"d52" => data <= x"04";
when "11" & x"d53" => data <= x"38";
when "11" & x"d54" => data <= x"e9";
when "11" & x"d55" => data <= x"05";
when "11" & x"d56" => data <= x"20";
when "11" & x"d57" => data <= x"2e";
when "11" & x"d58" => data <= x"be";
when "11" & x"d59" => data <= x"a0";
when "11" & x"d5a" => data <= x"00";
when "11" & x"d5b" => data <= x"a5";
when "11" & x"d5c" => data <= x"30";
when "11" & x"d5d" => data <= x"91";
when "11" & x"d5e" => data <= x"04";
when "11" & x"d5f" => data <= x"c8";
when "11" & x"d60" => data <= x"a5";
when "11" & x"d61" => data <= x"2e";
when "11" & x"d62" => data <= x"29";
when "11" & x"d63" => data <= x"80";
when "11" & x"d64" => data <= x"85";
when "11" & x"d65" => data <= x"2e";
when "11" & x"d66" => data <= x"a5";
when "11" & x"d67" => data <= x"31";
when "11" & x"d68" => data <= x"29";
when "11" & x"d69" => data <= x"7f";
when "11" & x"d6a" => data <= x"05";
when "11" & x"d6b" => data <= x"2e";
when "11" & x"d6c" => data <= x"91";
when "11" & x"d6d" => data <= x"04";
when "11" & x"d6e" => data <= x"c8";
when "11" & x"d6f" => data <= x"a5";
when "11" & x"d70" => data <= x"32";
when "11" & x"d71" => data <= x"91";
when "11" & x"d72" => data <= x"04";
when "11" & x"d73" => data <= x"c8";
when "11" & x"d74" => data <= x"a5";
when "11" & x"d75" => data <= x"33";
when "11" & x"d76" => data <= x"91";
when "11" & x"d77" => data <= x"04";
when "11" & x"d78" => data <= x"c8";
when "11" & x"d79" => data <= x"a5";
when "11" & x"d7a" => data <= x"34";
when "11" & x"d7b" => data <= x"91";
when "11" & x"d7c" => data <= x"04";
when "11" & x"d7d" => data <= x"60";
when "11" & x"d7e" => data <= x"a5";
when "11" & x"d7f" => data <= x"04";
when "11" & x"d80" => data <= x"18";
when "11" & x"d81" => data <= x"85";
when "11" & x"d82" => data <= x"4b";
when "11" & x"d83" => data <= x"69";
when "11" & x"d84" => data <= x"05";
when "11" & x"d85" => data <= x"85";
when "11" & x"d86" => data <= x"04";
when "11" & x"d87" => data <= x"a5";
when "11" & x"d88" => data <= x"05";
when "11" & x"d89" => data <= x"85";
when "11" & x"d8a" => data <= x"4c";
when "11" & x"d8b" => data <= x"69";
when "11" & x"d8c" => data <= x"00";
when "11" & x"d8d" => data <= x"85";
when "11" & x"d8e" => data <= x"05";
when "11" & x"d8f" => data <= x"60";
when "11" & x"d90" => data <= x"f0";
when "11" & x"d91" => data <= x"20";
when "11" & x"d92" => data <= x"30";
when "11" & x"d93" => data <= x"bd";
when "11" & x"d94" => data <= x"a5";
when "11" & x"d95" => data <= x"04";
when "11" & x"d96" => data <= x"38";
when "11" & x"d97" => data <= x"e9";
when "11" & x"d98" => data <= x"04";
when "11" & x"d99" => data <= x"20";
when "11" & x"d9a" => data <= x"2e";
when "11" & x"d9b" => data <= x"be";
when "11" & x"d9c" => data <= x"a0";
when "11" & x"d9d" => data <= x"03";
when "11" & x"d9e" => data <= x"a5";
when "11" & x"d9f" => data <= x"2d";
when "11" & x"da0" => data <= x"91";
when "11" & x"da1" => data <= x"04";
when "11" & x"da2" => data <= x"88";
when "11" & x"da3" => data <= x"a5";
when "11" & x"da4" => data <= x"2c";
when "11" & x"da5" => data <= x"91";
when "11" & x"da6" => data <= x"04";
when "11" & x"da7" => data <= x"88";
when "11" & x"da8" => data <= x"a5";
when "11" & x"da9" => data <= x"2b";
when "11" & x"daa" => data <= x"91";
when "11" & x"dab" => data <= x"04";
when "11" & x"dac" => data <= x"88";
when "11" & x"dad" => data <= x"a5";
when "11" & x"dae" => data <= x"2a";
when "11" & x"daf" => data <= x"91";
when "11" & x"db0" => data <= x"04";
when "11" & x"db1" => data <= x"60";
when "11" & x"db2" => data <= x"18";
when "11" & x"db3" => data <= x"a5";
when "11" & x"db4" => data <= x"04";
when "11" & x"db5" => data <= x"e5";
when "11" & x"db6" => data <= x"36";
when "11" & x"db7" => data <= x"20";
when "11" & x"db8" => data <= x"2e";
when "11" & x"db9" => data <= x"be";
when "11" & x"dba" => data <= x"a4";
when "11" & x"dbb" => data <= x"36";
when "11" & x"dbc" => data <= x"f0";
when "11" & x"dbd" => data <= x"08";
when "11" & x"dbe" => data <= x"b9";
when "11" & x"dbf" => data <= x"ff";
when "11" & x"dc0" => data <= x"05";
when "11" & x"dc1" => data <= x"91";
when "11" & x"dc2" => data <= x"04";
when "11" & x"dc3" => data <= x"88";
when "11" & x"dc4" => data <= x"d0";
when "11" & x"dc5" => data <= x"f8";
when "11" & x"dc6" => data <= x"a5";
when "11" & x"dc7" => data <= x"36";
when "11" & x"dc8" => data <= x"91";
when "11" & x"dc9" => data <= x"04";
when "11" & x"dca" => data <= x"60";
when "11" & x"dcb" => data <= x"a0";
when "11" & x"dcc" => data <= x"00";
when "11" & x"dcd" => data <= x"b1";
when "11" & x"dce" => data <= x"04";
when "11" & x"dcf" => data <= x"85";
when "11" & x"dd0" => data <= x"36";
when "11" & x"dd1" => data <= x"f0";
when "11" & x"dd2" => data <= x"09";
when "11" & x"dd3" => data <= x"a8";
when "11" & x"dd4" => data <= x"b1";
when "11" & x"dd5" => data <= x"04";
when "11" & x"dd6" => data <= x"99";
when "11" & x"dd7" => data <= x"ff";
when "11" & x"dd8" => data <= x"05";
when "11" & x"dd9" => data <= x"88";
when "11" & x"dda" => data <= x"d0";
when "11" & x"ddb" => data <= x"f8";
when "11" & x"ddc" => data <= x"a0";
when "11" & x"ddd" => data <= x"00";
when "11" & x"dde" => data <= x"b1";
when "11" & x"ddf" => data <= x"04";
when "11" & x"de0" => data <= x"38";
when "11" & x"de1" => data <= x"65";
when "11" & x"de2" => data <= x"04";
when "11" & x"de3" => data <= x"85";
when "11" & x"de4" => data <= x"04";
when "11" & x"de5" => data <= x"90";
when "11" & x"de6" => data <= x"23";
when "11" & x"de7" => data <= x"e6";
when "11" & x"de8" => data <= x"05";
when "11" & x"de9" => data <= x"60";
when "11" & x"dea" => data <= x"a0";
when "11" & x"deb" => data <= x"03";
when "11" & x"dec" => data <= x"b1";
when "11" & x"ded" => data <= x"04";
when "11" & x"dee" => data <= x"85";
when "11" & x"def" => data <= x"2d";
when "11" & x"df0" => data <= x"88";
when "11" & x"df1" => data <= x"b1";
when "11" & x"df2" => data <= x"04";
when "11" & x"df3" => data <= x"85";
when "11" & x"df4" => data <= x"2c";
when "11" & x"df5" => data <= x"88";
when "11" & x"df6" => data <= x"b1";
when "11" & x"df7" => data <= x"04";
when "11" & x"df8" => data <= x"85";
when "11" & x"df9" => data <= x"2b";
when "11" & x"dfa" => data <= x"88";
when "11" & x"dfb" => data <= x"b1";
when "11" & x"dfc" => data <= x"04";
when "11" & x"dfd" => data <= x"85";
when "11" & x"dfe" => data <= x"2a";
when "11" & x"dff" => data <= x"18";
when "11" & x"e00" => data <= x"a5";
when "11" & x"e01" => data <= x"04";
when "11" & x"e02" => data <= x"69";
when "11" & x"e03" => data <= x"04";
when "11" & x"e04" => data <= x"85";
when "11" & x"e05" => data <= x"04";
when "11" & x"e06" => data <= x"90";
when "11" & x"e07" => data <= x"02";
when "11" & x"e08" => data <= x"e6";
when "11" & x"e09" => data <= x"05";
when "11" & x"e0a" => data <= x"60";
when "11" & x"e0b" => data <= x"a2";
when "11" & x"e0c" => data <= x"37";
when "11" & x"e0d" => data <= x"a0";
when "11" & x"e0e" => data <= x"03";
when "11" & x"e0f" => data <= x"b1";
when "11" & x"e10" => data <= x"04";
when "11" & x"e11" => data <= x"95";
when "11" & x"e12" => data <= x"03";
when "11" & x"e13" => data <= x"88";
when "11" & x"e14" => data <= x"b1";
when "11" & x"e15" => data <= x"04";
when "11" & x"e16" => data <= x"95";
when "11" & x"e17" => data <= x"02";
when "11" & x"e18" => data <= x"88";
when "11" & x"e19" => data <= x"b1";
when "11" & x"e1a" => data <= x"04";
when "11" & x"e1b" => data <= x"95";
when "11" & x"e1c" => data <= x"01";
when "11" & x"e1d" => data <= x"88";
when "11" & x"e1e" => data <= x"b1";
when "11" & x"e1f" => data <= x"04";
when "11" & x"e20" => data <= x"95";
when "11" & x"e21" => data <= x"00";
when "11" & x"e22" => data <= x"18";
when "11" & x"e23" => data <= x"a5";
when "11" & x"e24" => data <= x"04";
when "11" & x"e25" => data <= x"69";
when "11" & x"e26" => data <= x"04";
when "11" & x"e27" => data <= x"85";
when "11" & x"e28" => data <= x"04";
when "11" & x"e29" => data <= x"90";
when "11" & x"e2a" => data <= x"df";
when "11" & x"e2b" => data <= x"e6";
when "11" & x"e2c" => data <= x"05";
when "11" & x"e2d" => data <= x"60";
when "11" & x"e2e" => data <= x"85";
when "11" & x"e2f" => data <= x"04";
when "11" & x"e30" => data <= x"b0";
when "11" & x"e31" => data <= x"02";
when "11" & x"e32" => data <= x"c6";
when "11" & x"e33" => data <= x"05";
when "11" & x"e34" => data <= x"a4";
when "11" & x"e35" => data <= x"05";
when "11" & x"e36" => data <= x"c4";
when "11" & x"e37" => data <= x"03";
when "11" & x"e38" => data <= x"90";
when "11" & x"e39" => data <= x"07";
when "11" & x"e3a" => data <= x"d0";
when "11" & x"e3b" => data <= x"04";
when "11" & x"e3c" => data <= x"c5";
when "11" & x"e3d" => data <= x"02";
when "11" & x"e3e" => data <= x"90";
when "11" & x"e3f" => data <= x"01";
when "11" & x"e40" => data <= x"60";
when "11" & x"e41" => data <= x"4c";
when "11" & x"e42" => data <= x"b7";
when "11" & x"e43" => data <= x"8c";
when "11" & x"e44" => data <= x"a5";
when "11" & x"e45" => data <= x"2a";
when "11" & x"e46" => data <= x"95";
when "11" & x"e47" => data <= x"00";
when "11" & x"e48" => data <= x"a5";
when "11" & x"e49" => data <= x"2b";
when "11" & x"e4a" => data <= x"95";
when "11" & x"e4b" => data <= x"01";
when "11" & x"e4c" => data <= x"a5";
when "11" & x"e4d" => data <= x"2c";
when "11" & x"e4e" => data <= x"95";
when "11" & x"e4f" => data <= x"02";
when "11" & x"e50" => data <= x"a5";
when "11" & x"e51" => data <= x"2d";
when "11" & x"e52" => data <= x"95";
when "11" & x"e53" => data <= x"03";
when "11" & x"e54" => data <= x"60";
when "11" & x"e55" => data <= x"18";
when "11" & x"e56" => data <= x"98";
when "11" & x"e57" => data <= x"65";
when "11" & x"e58" => data <= x"3d";
when "11" & x"e59" => data <= x"85";
when "11" & x"e5a" => data <= x"3d";
when "11" & x"e5b" => data <= x"90";
when "11" & x"e5c" => data <= x"02";
when "11" & x"e5d" => data <= x"e6";
when "11" & x"e5e" => data <= x"3e";
when "11" & x"e5f" => data <= x"a0";
when "11" & x"e60" => data <= x"01";
when "11" & x"e61" => data <= x"60";
when "11" & x"e62" => data <= x"20";
when "11" & x"e63" => data <= x"dd";
when "11" & x"e64" => data <= x"be";
when "11" & x"e65" => data <= x"a8";
when "11" & x"e66" => data <= x"a9";
when "11" & x"e67" => data <= x"ff";
when "11" & x"e68" => data <= x"84";
when "11" & x"e69" => data <= x"3d";
when "11" & x"e6a" => data <= x"a2";
when "11" & x"e6b" => data <= x"37";
when "11" & x"e6c" => data <= x"20";
when "11" & x"e6d" => data <= x"dd";
when "11" & x"e6e" => data <= x"ff";
when "11" & x"e6f" => data <= x"a5";
when "11" & x"e70" => data <= x"18";
when "11" & x"e71" => data <= x"85";
when "11" & x"e72" => data <= x"13";
when "11" & x"e73" => data <= x"a0";
when "11" & x"e74" => data <= x"00";
when "11" & x"e75" => data <= x"84";
when "11" & x"e76" => data <= x"12";
when "11" & x"e77" => data <= x"c8";
when "11" & x"e78" => data <= x"88";
when "11" & x"e79" => data <= x"b1";
when "11" & x"e7a" => data <= x"12";
when "11" & x"e7b" => data <= x"c9";
when "11" & x"e7c" => data <= x"0d";
when "11" & x"e7d" => data <= x"d0";
when "11" & x"e7e" => data <= x"1f";
when "11" & x"e7f" => data <= x"c8";
when "11" & x"e80" => data <= x"b1";
when "11" & x"e81" => data <= x"12";
when "11" & x"e82" => data <= x"30";
when "11" & x"e83" => data <= x"0c";
when "11" & x"e84" => data <= x"a0";
when "11" & x"e85" => data <= x"03";
when "11" & x"e86" => data <= x"b1";
when "11" & x"e87" => data <= x"12";
when "11" & x"e88" => data <= x"f0";
when "11" & x"e89" => data <= x"14";
when "11" & x"e8a" => data <= x"18";
when "11" & x"e8b" => data <= x"20";
when "11" & x"e8c" => data <= x"93";
when "11" & x"e8d" => data <= x"be";
when "11" & x"e8e" => data <= x"d0";
when "11" & x"e8f" => data <= x"e8";
when "11" & x"e90" => data <= x"c8";
when "11" & x"e91" => data <= x"18";
when "11" & x"e92" => data <= x"98";
when "11" & x"e93" => data <= x"65";
when "11" & x"e94" => data <= x"12";
when "11" & x"e95" => data <= x"85";
when "11" & x"e96" => data <= x"12";
when "11" & x"e97" => data <= x"90";
when "11" & x"e98" => data <= x"02";
when "11" & x"e99" => data <= x"e6";
when "11" & x"e9a" => data <= x"13";
when "11" & x"e9b" => data <= x"a0";
when "11" & x"e9c" => data <= x"01";
when "11" & x"e9d" => data <= x"60";
when "11" & x"e9e" => data <= x"20";
when "11" & x"e9f" => data <= x"cf";
when "11" & x"ea0" => data <= x"bf";
when "11" & x"ea1" => data <= x"0d";
when "11" & x"ea2" => data <= x"42";
when "11" & x"ea3" => data <= x"61";
when "11" & x"ea4" => data <= x"64";
when "11" & x"ea5" => data <= x"20";
when "11" & x"ea6" => data <= x"70";
when "11" & x"ea7" => data <= x"72";
when "11" & x"ea8" => data <= x"6f";
when "11" & x"ea9" => data <= x"67";
when "11" & x"eaa" => data <= x"72";
when "11" & x"eab" => data <= x"61";
when "11" & x"eac" => data <= x"6d";
when "11" & x"ead" => data <= x"0d";
when "11" & x"eae" => data <= x"ea";
when "11" & x"eaf" => data <= x"4c";
when "11" & x"eb0" => data <= x"f6";
when "11" & x"eb1" => data <= x"8a";
when "11" & x"eb2" => data <= x"a9";
when "11" & x"eb3" => data <= x"00";
when "11" & x"eb4" => data <= x"85";
when "11" & x"eb5" => data <= x"37";
when "11" & x"eb6" => data <= x"a9";
when "11" & x"eb7" => data <= x"06";
when "11" & x"eb8" => data <= x"85";
when "11" & x"eb9" => data <= x"38";
when "11" & x"eba" => data <= x"a4";
when "11" & x"ebb" => data <= x"36";
when "11" & x"ebc" => data <= x"a9";
when "11" & x"ebd" => data <= x"0d";
when "11" & x"ebe" => data <= x"99";
when "11" & x"ebf" => data <= x"00";
when "11" & x"ec0" => data <= x"06";
when "11" & x"ec1" => data <= x"60";
when "11" & x"ec2" => data <= x"20";
when "11" & x"ec3" => data <= x"d2";
when "11" & x"ec4" => data <= x"be";
when "11" & x"ec5" => data <= x"a2";
when "11" & x"ec6" => data <= x"00";
when "11" & x"ec7" => data <= x"a0";
when "11" & x"ec8" => data <= x"06";
when "11" & x"ec9" => data <= x"20";
when "11" & x"eca" => data <= x"f7";
when "11" & x"ecb" => data <= x"ff";
when "11" & x"ecc" => data <= x"4c";
when "11" & x"ecd" => data <= x"9b";
when "11" & x"ece" => data <= x"8b";
when "11" & x"ecf" => data <= x"4c";
when "11" & x"ed0" => data <= x"0e";
when "11" & x"ed1" => data <= x"8c";
when "11" & x"ed2" => data <= x"20";
when "11" & x"ed3" => data <= x"1d";
when "11" & x"ed4" => data <= x"9b";
when "11" & x"ed5" => data <= x"d0";
when "11" & x"ed6" => data <= x"f8";
when "11" & x"ed7" => data <= x"20";
when "11" & x"ed8" => data <= x"b2";
when "11" & x"ed9" => data <= x"be";
when "11" & x"eda" => data <= x"4c";
when "11" & x"edb" => data <= x"4c";
when "11" & x"edc" => data <= x"98";
when "11" & x"edd" => data <= x"20";
when "11" & x"ede" => data <= x"d2";
when "11" & x"edf" => data <= x"be";
when "11" & x"ee0" => data <= x"88";
when "11" & x"ee1" => data <= x"84";
when "11" & x"ee2" => data <= x"39";
when "11" & x"ee3" => data <= x"a5";
when "11" & x"ee4" => data <= x"18";
when "11" & x"ee5" => data <= x"85";
when "11" & x"ee6" => data <= x"3a";
when "11" & x"ee7" => data <= x"a9";
when "11" & x"ee8" => data <= x"82";
when "11" & x"ee9" => data <= x"20";
when "11" & x"eea" => data <= x"f4";
when "11" & x"eeb" => data <= x"ff";
when "11" & x"eec" => data <= x"86";
when "11" & x"eed" => data <= x"3b";
when "11" & x"eee" => data <= x"84";
when "11" & x"eef" => data <= x"3c";
when "11" & x"ef0" => data <= x"a9";
when "11" & x"ef1" => data <= x"00";
when "11" & x"ef2" => data <= x"60";
when "11" & x"ef3" => data <= x"20";
when "11" & x"ef4" => data <= x"6f";
when "11" & x"ef5" => data <= x"be";
when "11" & x"ef6" => data <= x"a5";
when "11" & x"ef7" => data <= x"12";
when "11" & x"ef8" => data <= x"85";
when "11" & x"ef9" => data <= x"45";
when "11" & x"efa" => data <= x"a5";
when "11" & x"efb" => data <= x"13";
when "11" & x"efc" => data <= x"85";
when "11" & x"efd" => data <= x"46";
when "11" & x"efe" => data <= x"a9";
when "11" & x"eff" => data <= x"23";
when "11" & x"f00" => data <= x"85";
when "11" & x"f01" => data <= x"3d";
when "11" & x"f02" => data <= x"a9";
when "11" & x"f03" => data <= x"80";
when "11" & x"f04" => data <= x"85";
when "11" & x"f05" => data <= x"3e";
when "11" & x"f06" => data <= x"a5";
when "11" & x"f07" => data <= x"18";
when "11" & x"f08" => data <= x"85";
when "11" & x"f09" => data <= x"42";
when "11" & x"f0a" => data <= x"20";
when "11" & x"f0b" => data <= x"dd";
when "11" & x"f0c" => data <= x"be";
when "11" & x"f0d" => data <= x"86";
when "11" & x"f0e" => data <= x"3f";
when "11" & x"f0f" => data <= x"84";
when "11" & x"f10" => data <= x"40";
when "11" & x"f11" => data <= x"86";
when "11" & x"f12" => data <= x"43";
when "11" & x"f13" => data <= x"84";
when "11" & x"f14" => data <= x"44";
when "11" & x"f15" => data <= x"86";
when "11" & x"f16" => data <= x"47";
when "11" & x"f17" => data <= x"84";
when "11" & x"f18" => data <= x"48";
when "11" & x"f19" => data <= x"85";
when "11" & x"f1a" => data <= x"41";
when "11" & x"f1b" => data <= x"a8";
when "11" & x"f1c" => data <= x"a2";
when "11" & x"f1d" => data <= x"37";
when "11" & x"f1e" => data <= x"20";
when "11" & x"f1f" => data <= x"dd";
when "11" & x"f20" => data <= x"ff";
when "11" & x"f21" => data <= x"4c";
when "11" & x"f22" => data <= x"9b";
when "11" & x"f23" => data <= x"8b";
when "11" & x"f24" => data <= x"20";
when "11" & x"f25" => data <= x"62";
when "11" & x"f26" => data <= x"be";
when "11" & x"f27" => data <= x"4c";
when "11" & x"f28" => data <= x"f3";
when "11" & x"f29" => data <= x"8a";
when "11" & x"f2a" => data <= x"20";
when "11" & x"f2b" => data <= x"62";
when "11" & x"f2c" => data <= x"be";
when "11" & x"f2d" => data <= x"4c";
when "11" & x"f2e" => data <= x"14";
when "11" & x"f2f" => data <= x"bd";
when "11" & x"f30" => data <= x"20";
when "11" & x"f31" => data <= x"a9";
when "11" & x"f32" => data <= x"bf";
when "11" & x"f33" => data <= x"48";
when "11" & x"f34" => data <= x"20";
when "11" & x"f35" => data <= x"13";
when "11" & x"f36" => data <= x"98";
when "11" & x"f37" => data <= x"20";
when "11" & x"f38" => data <= x"ee";
when "11" & x"f39" => data <= x"92";
when "11" & x"f3a" => data <= x"68";
when "11" & x"f3b" => data <= x"a8";
when "11" & x"f3c" => data <= x"a2";
when "11" & x"f3d" => data <= x"2a";
when "11" & x"f3e" => data <= x"a9";
when "11" & x"f3f" => data <= x"01";
when "11" & x"f40" => data <= x"20";
when "11" & x"f41" => data <= x"da";
when "11" & x"f42" => data <= x"ff";
when "11" & x"f43" => data <= x"4c";
when "11" & x"f44" => data <= x"9b";
when "11" & x"f45" => data <= x"8b";
when "11" & x"f46" => data <= x"38";
when "11" & x"f47" => data <= x"a9";
when "11" & x"f48" => data <= x"00";
when "11" & x"f49" => data <= x"2a";
when "11" & x"f4a" => data <= x"2a";
when "11" & x"f4b" => data <= x"48";
when "11" & x"f4c" => data <= x"20";
when "11" & x"f4d" => data <= x"b5";
when "11" & x"f4e" => data <= x"bf";
when "11" & x"f4f" => data <= x"a2";
when "11" & x"f50" => data <= x"2a";
when "11" & x"f51" => data <= x"68";
when "11" & x"f52" => data <= x"20";
when "11" & x"f53" => data <= x"da";
when "11" & x"f54" => data <= x"ff";
when "11" & x"f55" => data <= x"a9";
when "11" & x"f56" => data <= x"40";
when "11" & x"f57" => data <= x"60";
when "11" & x"f58" => data <= x"20";
when "11" & x"f59" => data <= x"a9";
when "11" & x"f5a" => data <= x"bf";
when "11" & x"f5b" => data <= x"48";
when "11" & x"f5c" => data <= x"20";
when "11" & x"f5d" => data <= x"ae";
when "11" & x"f5e" => data <= x"8a";
when "11" & x"f5f" => data <= x"20";
when "11" & x"f60" => data <= x"49";
when "11" & x"f61" => data <= x"98";
when "11" & x"f62" => data <= x"20";
when "11" & x"f63" => data <= x"ee";
when "11" & x"f64" => data <= x"92";
when "11" & x"f65" => data <= x"68";
when "11" & x"f66" => data <= x"a8";
when "11" & x"f67" => data <= x"a5";
when "11" & x"f68" => data <= x"2a";
when "11" & x"f69" => data <= x"20";
when "11" & x"f6a" => data <= x"d4";
when "11" & x"f6b" => data <= x"ff";
when "11" & x"f6c" => data <= x"4c";
when "11" & x"f6d" => data <= x"9b";
when "11" & x"f6e" => data <= x"8b";
when "11" & x"f6f" => data <= x"20";
when "11" & x"f70" => data <= x"b5";
when "11" & x"f71" => data <= x"bf";
when "11" & x"f72" => data <= x"20";
when "11" & x"f73" => data <= x"d7";
when "11" & x"f74" => data <= x"ff";
when "11" & x"f75" => data <= x"4c";
when "11" & x"f76" => data <= x"d8";
when "11" & x"f77" => data <= x"ae";
when "11" & x"f78" => data <= x"a9";
when "11" & x"f79" => data <= x"40";
when "11" & x"f7a" => data <= x"d0";
when "11" & x"f7b" => data <= x"06";
when "11" & x"f7c" => data <= x"a9";
when "11" & x"f7d" => data <= x"80";
when "11" & x"f7e" => data <= x"d0";
when "11" & x"f7f" => data <= x"02";
when "11" & x"f80" => data <= x"a9";
when "11" & x"f81" => data <= x"c0";
when "11" & x"f82" => data <= x"48";
when "11" & x"f83" => data <= x"20";
when "11" & x"f84" => data <= x"ec";
when "11" & x"f85" => data <= x"ad";
when "11" & x"f86" => data <= x"d0";
when "11" & x"f87" => data <= x"0e";
when "11" & x"f88" => data <= x"20";
when "11" & x"f89" => data <= x"ba";
when "11" & x"f8a" => data <= x"be";
when "11" & x"f8b" => data <= x"a2";
when "11" & x"f8c" => data <= x"00";
when "11" & x"f8d" => data <= x"a0";
when "11" & x"f8e" => data <= x"06";
when "11" & x"f8f" => data <= x"68";
when "11" & x"f90" => data <= x"20";
when "11" & x"f91" => data <= x"ce";
when "11" & x"f92" => data <= x"ff";
when "11" & x"f93" => data <= x"4c";
when "11" & x"f94" => data <= x"d8";
when "11" & x"f95" => data <= x"ae";
when "11" & x"f96" => data <= x"4c";
when "11" & x"f97" => data <= x"0e";
when "11" & x"f98" => data <= x"8c";
when "11" & x"f99" => data <= x"20";
when "11" & x"f9a" => data <= x"a9";
when "11" & x"f9b" => data <= x"bf";
when "11" & x"f9c" => data <= x"20";
when "11" & x"f9d" => data <= x"52";
when "11" & x"f9e" => data <= x"98";
when "11" & x"f9f" => data <= x"a4";
when "11" & x"fa0" => data <= x"2a";
when "11" & x"fa1" => data <= x"a9";
when "11" & x"fa2" => data <= x"00";
when "11" & x"fa3" => data <= x"20";
when "11" & x"fa4" => data <= x"ce";
when "11" & x"fa5" => data <= x"ff";
when "11" & x"fa6" => data <= x"4c";
when "11" & x"fa7" => data <= x"9b";
when "11" & x"fa8" => data <= x"8b";
when "11" & x"fa9" => data <= x"a5";
when "11" & x"faa" => data <= x"0a";
when "11" & x"fab" => data <= x"85";
when "11" & x"fac" => data <= x"1b";
when "11" & x"fad" => data <= x"a5";
when "11" & x"fae" => data <= x"0b";
when "11" & x"faf" => data <= x"85";
when "11" & x"fb0" => data <= x"19";
when "11" & x"fb1" => data <= x"a5";
when "11" & x"fb2" => data <= x"0c";
when "11" & x"fb3" => data <= x"85";
when "11" & x"fb4" => data <= x"1a";
when "11" & x"fb5" => data <= x"20";
when "11" & x"fb6" => data <= x"8c";
when "11" & x"fb7" => data <= x"8a";
when "11" & x"fb8" => data <= x"c9";
when "11" & x"fb9" => data <= x"23";
when "11" & x"fba" => data <= x"d0";
when "11" & x"fbb" => data <= x"07";
when "11" & x"fbc" => data <= x"20";
when "11" & x"fbd" => data <= x"e3";
when "11" & x"fbe" => data <= x"92";
when "11" & x"fbf" => data <= x"a4";
when "11" & x"fc0" => data <= x"2a";
when "11" & x"fc1" => data <= x"98";
when "11" & x"fc2" => data <= x"60";
when "11" & x"fc3" => data <= x"00";
when "11" & x"fc4" => data <= x"2d";
when "11" & x"fc5" => data <= x"4d";
when "11" & x"fc6" => data <= x"69";
when "11" & x"fc7" => data <= x"73";
when "11" & x"fc8" => data <= x"73";
when "11" & x"fc9" => data <= x"69";
when "11" & x"fca" => data <= x"6e";
when "11" & x"fcb" => data <= x"67";
when "11" & x"fcc" => data <= x"20";
when "11" & x"fcd" => data <= x"23";
when "11" & x"fce" => data <= x"00";
when "11" & x"fcf" => data <= x"68";
when "11" & x"fd0" => data <= x"85";
when "11" & x"fd1" => data <= x"37";
when "11" & x"fd2" => data <= x"68";
when "11" & x"fd3" => data <= x"85";
when "11" & x"fd4" => data <= x"38";
when "11" & x"fd5" => data <= x"a0";
when "11" & x"fd6" => data <= x"00";
when "11" & x"fd7" => data <= x"f0";
when "11" & x"fd8" => data <= x"03";
when "11" & x"fd9" => data <= x"20";
when "11" & x"fda" => data <= x"e3";
when "11" & x"fdb" => data <= x"ff";
when "11" & x"fdc" => data <= x"20";
when "11" & x"fdd" => data <= x"4b";
when "11" & x"fde" => data <= x"89";
when "11" & x"fdf" => data <= x"10";
when "11" & x"fe0" => data <= x"f8";
when "11" & x"fe1" => data <= x"6c";
when "11" & x"fe2" => data <= x"37";
when "11" & x"fe3" => data <= x"00";
when "11" & x"fe4" => data <= x"20";
when "11" & x"fe5" => data <= x"57";
when "11" & x"fe6" => data <= x"98";
when "11" & x"fe7" => data <= x"20";
when "11" & x"fe8" => data <= x"25";
when "11" & x"fe9" => data <= x"bc";
when "11" & x"fea" => data <= x"a0";
when "11" & x"feb" => data <= x"01";
when "11" & x"fec" => data <= x"b1";
when "11" & x"fed" => data <= x"fd";
when "11" & x"fee" => data <= x"f0";
when "11" & x"fef" => data <= x"06";
when "11" & x"ff0" => data <= x"20";
when "11" & x"ff1" => data <= x"0e";
when "11" & x"ff2" => data <= x"b5";
when "11" & x"ff3" => data <= x"c8";
when "11" & x"ff4" => data <= x"d0";
when "11" & x"ff5" => data <= x"f6";
when "11" & x"ff6" => data <= x"4c";
when "11" & x"ff7" => data <= x"9b";
when "11" & x"ff8" => data <= x"8b";
when "11" & x"ff9" => data <= x"00";
when "11" & x"ffa" => data <= x"52";
when "11" & x"ffb" => data <= x"6f";
when "11" & x"ffc" => data <= x"67";
when "11" & x"ffd" => data <= x"65";
when "11" & x"ffe" => data <= x"72";
when "11" & x"fff" => data <= x"00";
when others => data <= (others => '0');
end case;
end process;
end RTL;
| gpl-3.0 | 4586fb785971c0f8d000489ea1245a39 | 0.347135 | 2.665261 | false | false | false | false |
hoglet67/ElectronFpga | src/common/mist_scandoubler.vhd | 1 | 6,416 | --
-- scandoubler.vhd
--
-- Copyright (c) 2015 Till Harbaum <[email protected]>
--
-- Migrated to VHDL by David Banks
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org/licenses/>.
-- TODO: Delay vsync one line
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity mist_scandoubler is
port (
-- system interface
clk : in std_logic; -- 32MHz
clk_16 : in std_logic; -- from shifter
clk_16_en : in std_logic;
scanlines : in std_logic;
-- shifter video interface
hs_in : in std_logic;
vs_in : in std_logic;
r_in : in std_logic;
g_in : in std_logic;
b_in : in std_logic;
-- output interface
hs_out : out std_logic;
vs_out : out std_logic;
r_out : out std_logic_vector(1 downto 0);
g_out : out std_logic_vector(1 downto 0);
b_out : out std_logic_vector(1 downto 0);
is15k : out std_logic
);
end entity;
architecture rtl of mist_scandoubler is
-- scan doubler output register
signal sd_out : std_logic_vector(2 downto 0);
-- --------------------- create output signals -----------------
-- latch everything once more to make it glitch free and apply scanline effect
signal scanline : std_logic;
-- 2 lines of 1024 pixels 3*4 bit RGB
type ram_type is array (2047 downto 0) of std_logic_vector (2 downto 0);
signal sd_buffer : ram_type;
-- use alternating sd_buffers when storing/reading data
signal vsD : std_logic;
signal line_toggle : std_logic;
-- total hsync time (in 16MHz cycles), hs_total reaches 1024
signal hs_max : std_logic_vector(9 downto 0);
signal hs_rise : std_logic_vector(9 downto 0);
signal hcnt : std_logic_vector(9 downto 0);
signal hsD : std_logic;
signal sd_hcnt : std_logic_vector(9 downto 0);
signal hs_sd : std_logic;
signal vs : std_logic;
signal hs : std_logic;
begin
hs_out <= hs;
vs_out <= vs;
process(clk)
begin
if rising_edge(clk) then
hs <= hs_sd;
vs <= vs_in;
-- reset scanlines at every new screen
if vs /= vs_in then
scanline <= '0';
end if;
-- toggle scanlines at begin of every hsync
if hs = '1' and hs_sd = '0' then
scanline <= not scanline;
end if;
-- if no scanlines or not a scanline
if scanlines = '0' or scanline = '0' then
r_out <= sd_out(2) & sd_out(2);
g_out <= sd_out(1) & sd_out(1);
b_out <= sd_out(0) & sd_out(0);
else
r_out <= '0' & sd_out(2);
g_out <= '0' & sd_out(1);
b_out <= '0' & sd_out(0);
end if;
end if;
end process;
-- ==================================================================
-- ======================== the line buffers ========================
-- ==================================================================
process(clk_16)
begin
if falling_edge(clk_16) then
if clk_16_en = '1' then
vsD <= vs_in;
if vsD /= vs_in then
line_toggle <= '0';
end if;
-- begin of incoming hsync
if hsD = '1' and hs_in = '0' then
line_toggle <= not line_toggle;
end if;
end if;
end if;
end process;
process(clk_16)
begin
if falling_edge(clk_16) then
if clk_16_en = '1' then
sd_buffer(conv_integer(line_toggle & hcnt)) <= r_in & g_in & b_in;
end if;
end if;
end process;
-- ==================================================================
-- =================== horizontal timing analysis ===================
-- ==================================================================
-- signal detection of 15khz if hsync frequency is less than 20KHz
is15k <= '1' when hs_max > (16000000/20000) else '0';
process(clk_16)
begin
if falling_edge(clk_16) then
if clk_16_en = '1' then
hsD <= hs_in;
-- falling edge of hsync indicates start of line
if hsD = '1' and hs_in = '0' then
hs_max <= hcnt;
hcnt <= (others => '0');
else
hcnt <= hcnt + 1;
end if;
-- save position of rising edge
if hsD = '0' and hs_in = '1' then
hs_rise <= hcnt;
end if;
end if;
end if;
end process;
-- ==================================================================
-- ==================== output timing generation ====================
-- ==================================================================
-- timing generation runs 32 MHz (twice the input signal analysis speed)
process(clk)
begin
if rising_edge(clk) then
-- output counter synchronous to input and at twice the rate
sd_hcnt <= sd_hcnt + 1;
if hsD = '1' and hs_in = '0' then
sd_hcnt <= hs_max;
end if;
if sd_hcnt = hs_max then
sd_hcnt <= (others => '0');
end if;
-- replicate horizontal sync at twice the speed
if sd_hcnt = hs_max then
hs_sd <= '0';
end if;
if sd_hcnt = hs_rise then
hs_sd <= '1';
end if;
-- read data from line sd_buffer
sd_out <= sd_buffer(conv_integer((not line_toggle) & sd_hcnt));
end if;
end process;
end architecture;
| gpl-3.0 | db9940a911498091d74c6148317358a2 | 0.483167 | 4.012508 | false | false | false | false |
DreamIP/GPStudio | support/toolchain/caph/hdl/caph_lib/port_in.vhd | 1 | 3,883 | -----------------------------------------------------------------------------------------
-- --
-- This file is part of the CAPH Compiler distribution --
-- http://caph.univ-bpclermont.fr --
-- --
-- Jocelyn SEROT --
-- [email protected] --
-- --
-- Copyright 2011-2015 Jocelyn SEROT. All rights reserved. --
-- This file is distributed under the terms of the GNU Library General Public License --
-- with the special exception on linking described in file ../LICENSE. --
-- --
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity port_in is
generic ( filename: string := ""; size: integer := 10; ival: bit_vector; max_events: integer := 16);
port ( full : in std_logic;
dout : out std_logic_vector(size-1 downto 0);
wr : out std_logic; -- write (push) signal, active 1 on clk^
clk : in std_logic;
rst : in std_logic
);
end port_in;
architecture beh of port_in is
begin
process
-- Note 2014-11-22, JS
-- Types and fns for reading event files.
-- This should really be in a separate package,
-- but this requires generic packages, which are not always supported :(
type port_event is record
date: natural;
value : bit_vector(size-1 downto 0);
end record;
type event_array is array (0 to max_events-1) of port_event;
type port_events is record
length: natural;
data: event_array;
end record;
file f: text;
variable l,log: line;
variable i: integer;
variable r: port_events;
variable current_value: bit_vector(size-1 downto 0);
variable current_time: integer; -- in ns
variable next_index: integer;
variable next_change: integer;
begin
wr <= '0';
i := 0; -- Reading the event file
if ( filename /= "" ) then
file_open(f,filename,READ_MODE);
while not endfile(f) loop
readline (f,l);
read(l,r.data(i).date);
readline (f,l);
read(l,r.data(i).value);
i := i+1;
end loop;
file_close(f);
r.length := i;
report "port_in.vhd: read " & integer'image(r.length) & " event(s) from file " & filename;
for j in 0 to r.length-1 loop
write(log,r.data(j).value);
write(log,string'(" @ "));
write(log,r.data(j).date);
writeline(output,log);
end loop;
next_change := r.data(0).date;
else
r.length := 0;
next_change := -1;
end if;
current_value := ival;
next_index := 0;
while true loop
wait until rising_edge(clk);
current_time := time'pos(now) / 1000000; -- now() returns time in fs
if ( next_index < r.length and current_time >= next_change ) then
report "port_in.vhd: changing value at t= " & integer'image(current_time);
current_value := r.data(next_index).value;
next_change := r.data(next_index).date;
next_index := next_index+1;
end if;
assert (full='0')
report "port_in: cannot write: downstream fifo is full !"
severity warning;
dout <= to_stdlogicvector(current_value);
wr <= '1';
wait until rising_edge(clk);
wr <= '0';
end loop;
wait;
end process;
end;
| gpl-3.0 | 2bb88ef871cfddf8fafd645fe134c707 | 0.481071 | 4.179763 | false | false | false | false |
DreamIP/GPStudio | support/process/roi/hdl/roi_slave.vhd | 1 | 7,878 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity roi_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
status_reg_bypass_bit : out std_logic;
in_size_reg_in_w_reg : out std_logic_vector(11 downto 0);
in_size_reg_in_h_reg : out std_logic_vector(11 downto 0);
out_size_reg_out_w_reg : out std_logic_vector(11 downto 0);
out_size_reg_out_h_reg : out std_logic_vector(11 downto 0);
out_offset_reg_out_x_reg : out std_logic_vector(11 downto 0);
out_offset_reg_out_y_reg : out std_logic_vector(11 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end roi_slave;
architecture rtl of roi_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant IN_SIZE_REG_REG_ADDR : natural := 1;
constant OUT_SIZE_REG_REG_ADDR : natural := 2;
constant OUT_OFFSET_REG_REG_ADDR : natural := 3;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal status_reg_bypass_bit_reg : std_logic;
signal in_size_reg_in_w_reg_reg : std_logic_vector (11 downto 0);
signal in_size_reg_in_h_reg_reg : std_logic_vector (11 downto 0);
signal out_size_reg_out_w_reg_reg : std_logic_vector (11 downto 0);
signal out_size_reg_out_h_reg_reg : std_logic_vector (11 downto 0);
signal out_offset_reg_out_x_reg_reg : std_logic_vector (11 downto 0);
signal out_offset_reg_out_y_reg_reg : std_logic_vector (11 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
status_reg_bypass_bit_reg <= '0';
in_size_reg_in_w_reg_reg <= "000000000000";
in_size_reg_in_h_reg_reg <= "000000000000";
out_size_reg_out_w_reg_reg <= "000000000000";
out_size_reg_out_h_reg_reg <= "000000000000";
out_offset_reg_out_x_reg_reg <= "000000000000";
out_offset_reg_out_y_reg_reg <= "000000000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 2))=>
status_reg_enable_bit_reg <= datawr_i(0);
status_reg_bypass_bit_reg <= datawr_i(1);
when std_logic_vector(to_unsigned(IN_SIZE_REG_REG_ADDR, 2))=>
in_size_reg_in_w_reg_reg <= datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
in_size_reg_in_h_reg_reg <= datawr_i(27) & datawr_i(26) & datawr_i(25) & datawr_i(24) & datawr_i(23) & datawr_i(22) & datawr_i(21) & datawr_i(20) & datawr_i(19) & datawr_i(18) & datawr_i(17) & datawr_i(16);
when std_logic_vector(to_unsigned(OUT_SIZE_REG_REG_ADDR, 2))=>
out_size_reg_out_w_reg_reg <= datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
out_size_reg_out_h_reg_reg <= datawr_i(27) & datawr_i(26) & datawr_i(25) & datawr_i(24) & datawr_i(23) & datawr_i(22) & datawr_i(21) & datawr_i(20) & datawr_i(19) & datawr_i(18) & datawr_i(17) & datawr_i(16);
when std_logic_vector(to_unsigned(OUT_OFFSET_REG_REG_ADDR, 2))=>
out_offset_reg_out_x_reg_reg <= datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
out_offset_reg_out_y_reg_reg <= datawr_i(27) & datawr_i(26) & datawr_i(25) & datawr_i(24) & datawr_i(23) & datawr_i(22) & datawr_i(21) & datawr_i(20) & datawr_i(19) & datawr_i(18) & datawr_i(17) & datawr_i(16);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 2))=>
datard_o <= "000000000000000000000000000000" & status_reg_bypass_bit_reg & status_reg_enable_bit_reg;
when std_logic_vector(to_unsigned(IN_SIZE_REG_REG_ADDR, 2))=>
datard_o <= "0000" & in_size_reg_in_h_reg_reg(11) & in_size_reg_in_h_reg_reg(10) & in_size_reg_in_h_reg_reg(9) & in_size_reg_in_h_reg_reg(8) & in_size_reg_in_h_reg_reg(7) & in_size_reg_in_h_reg_reg(6) & in_size_reg_in_h_reg_reg(5) & in_size_reg_in_h_reg_reg(4) & in_size_reg_in_h_reg_reg(3) & in_size_reg_in_h_reg_reg(2) & in_size_reg_in_h_reg_reg(1) & in_size_reg_in_h_reg_reg(0) & "0000" & in_size_reg_in_w_reg_reg(11) & in_size_reg_in_w_reg_reg(10) & in_size_reg_in_w_reg_reg(9) & in_size_reg_in_w_reg_reg(8) & in_size_reg_in_w_reg_reg(7) & in_size_reg_in_w_reg_reg(6) & in_size_reg_in_w_reg_reg(5) & in_size_reg_in_w_reg_reg(4) & in_size_reg_in_w_reg_reg(3) & in_size_reg_in_w_reg_reg(2) & in_size_reg_in_w_reg_reg(1) & in_size_reg_in_w_reg_reg(0);
when std_logic_vector(to_unsigned(OUT_SIZE_REG_REG_ADDR, 2))=>
datard_o <= "0000" & out_size_reg_out_h_reg_reg(11) & out_size_reg_out_h_reg_reg(10) & out_size_reg_out_h_reg_reg(9) & out_size_reg_out_h_reg_reg(8) & out_size_reg_out_h_reg_reg(7) & out_size_reg_out_h_reg_reg(6) & out_size_reg_out_h_reg_reg(5) & out_size_reg_out_h_reg_reg(4) & out_size_reg_out_h_reg_reg(3) & out_size_reg_out_h_reg_reg(2) & out_size_reg_out_h_reg_reg(1) & out_size_reg_out_h_reg_reg(0) & "0000" & out_size_reg_out_w_reg_reg(11) & out_size_reg_out_w_reg_reg(10) & out_size_reg_out_w_reg_reg(9) & out_size_reg_out_w_reg_reg(8) & out_size_reg_out_w_reg_reg(7) & out_size_reg_out_w_reg_reg(6) & out_size_reg_out_w_reg_reg(5) & out_size_reg_out_w_reg_reg(4) & out_size_reg_out_w_reg_reg(3) & out_size_reg_out_w_reg_reg(2) & out_size_reg_out_w_reg_reg(1) & out_size_reg_out_w_reg_reg(0);
when std_logic_vector(to_unsigned(OUT_OFFSET_REG_REG_ADDR, 2))=>
datard_o <= "0000" & out_offset_reg_out_y_reg_reg(11) & out_offset_reg_out_y_reg_reg(10) & out_offset_reg_out_y_reg_reg(9) & out_offset_reg_out_y_reg_reg(8) & out_offset_reg_out_y_reg_reg(7) & out_offset_reg_out_y_reg_reg(6) & out_offset_reg_out_y_reg_reg(5) & out_offset_reg_out_y_reg_reg(4) & out_offset_reg_out_y_reg_reg(3) & out_offset_reg_out_y_reg_reg(2) & out_offset_reg_out_y_reg_reg(1) & out_offset_reg_out_y_reg_reg(0) & "0000" & out_offset_reg_out_x_reg_reg(11) & out_offset_reg_out_x_reg_reg(10) & out_offset_reg_out_x_reg_reg(9) & out_offset_reg_out_x_reg_reg(8) & out_offset_reg_out_x_reg_reg(7) & out_offset_reg_out_x_reg_reg(6) & out_offset_reg_out_x_reg_reg(5) & out_offset_reg_out_x_reg_reg(4) & out_offset_reg_out_x_reg_reg(3) & out_offset_reg_out_x_reg_reg(2) & out_offset_reg_out_x_reg_reg(1) & out_offset_reg_out_x_reg_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
status_reg_bypass_bit <= status_reg_bypass_bit_reg;
in_size_reg_in_w_reg <= in_size_reg_in_w_reg_reg;
in_size_reg_in_h_reg <= in_size_reg_in_h_reg_reg;
out_size_reg_out_w_reg <= out_size_reg_out_w_reg_reg;
out_size_reg_out_h_reg <= out_size_reg_out_h_reg_reg;
out_offset_reg_out_x_reg <= out_offset_reg_out_x_reg_reg;
out_offset_reg_out_y_reg <= out_offset_reg_out_y_reg_reg;
end rtl;
| gpl-3.0 | dd2018bb8969d9dad91073d812eea7fd | 0.613354 | 2.343945 | false | false | false | false |
DreamIP/GPStudio | support/io/com/hdl/hal/eth_marvell_88e1111/hdl/encapsulation/eth_tx_pad.vhd | 1 | 1,968 | -- This entity add '0' to the packet when it is too short.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity eth_tx_pad is Port(
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
IN_ETH_STREAM : in STD_LOGIC_VECTOR(9 downto 0);
OUT_ETH_STREAM : out STD_LOGIC_VECTOR(9 downto 0));
end eth_tx_pad;
architecture Behavioral of eth_tx_pad is
signal state : unsigned(6 downto 0) := "0000000";
signal next_state : unsigned(6 downto 0) := "0000000";
constant min_packet : unsigned(6 downto 0) := "1001000";
begin
process(CLK,RESET)
begin
if RESET = '0' then
state <= "0000000";
OUT_ETH_STREAM <= "00" & x"00";
elsif CLK'event and CLK = '1' then
if IN_ETH_STREAM(9) = '1' then
state <= next_state;
OUT_ETH_STREAM(9) <= '1';
if next_state = "0000000" then
OUT_ETH_STREAM(8) <= '0';
else
OUT_ETH_STREAM(8) <= '1';--extend frame signal, if need be
end if;
if IN_ETH_STREAM(8) = '1' then--route data out normally
OUT_ETH_STREAM(7 downto 0) <= IN_ETH_STREAM(7 downto 0);
else--replace data with 0 when padding packet
OUT_ETH_STREAM(7 downto 0) <= x"00";
end if;
else
state <= state;
OUT_ETH_STREAM(9) <= '0';
end if;
end if;
end process;
process(state, IN_ETH_STREAM(8))
begin
case state is
when "0000000" =>
if IN_ETH_STREAM(8) = '1' then--when frame signal turns high,
next_state <= "0000001";--begin looking at the new packet
else
next_state <= "0000000";
end if;
when min_packet =>--60 bytes have been seen
if IN_ETH_STREAM(8) = '0' then--wait until packet finished
next_state <= min_packet + "0000001";--to append extra 4 bytes
else
next_state <= min_packet;
end if;
when "1001100" =>
next_state <= "0000000";
when others =>
next_state <= state + "0000001";
end case;
end process;
end Behavioral;
| gpl-3.0 | 16b0c985881c59f132b6a1e3dac67f29 | 0.598069 | 3.032357 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_jtag_uart_0.vhd | 1 | 45,281 | --Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity tracking_camera_system_jtag_uart_0_log_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal strobe : IN STD_LOGIC;
signal valid : IN STD_LOGIC
);
end entity tracking_camera_system_jtag_uart_0_log_module;
architecture europa of tracking_camera_system_jtag_uart_0_log_module is
file text_handle : TEXT ;
begin
--synthesis translate_off
-- purpose: simulate verilog initial function to open file in write mode
-- type : combinational
-- inputs : initial
-- outputs: <none>
process is
variable initial : boolean := true; -- not initialized yet
variable status : file_open_status; -- status for fopen
begin -- process
if initial = true then
file_open (status, text_handle, "tracking_camera_system_jtag_uart_0_output_stream.dat", WRITE_MODE);
initial := false; -- done!
end if;
wait; -- wait forever
end process;
process (clk)
variable data_string : LINE; -- for line buffer to file
variable status : file_open_status; -- status for fopen
begin -- process clk
if clk'event and clk = '1' then -- sync ' chars for hilighting txt editors
if (valid and strobe) = '1' then
write (data_string,To_bitvector(data)); -- every char flushes line
writeline (text_handle,data_string);
file_close (text_handle); -- flush buffer
file_open (status, text_handle, "tracking_camera_system_jtag_uart_0_output_stream.dat", APPEND_MODE);
end if;
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tracking_camera_system_jtag_uart_0_sim_scfifo_w is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_wdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_wr : IN STD_LOGIC;
-- outputs:
signal fifo_FF : OUT STD_LOGIC;
signal r_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal wfifo_empty : OUT STD_LOGIC;
signal wfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end entity tracking_camera_system_jtag_uart_0_sim_scfifo_w;
architecture europa of tracking_camera_system_jtag_uart_0_sim_scfifo_w is
--synthesis translate_off
component tracking_camera_system_jtag_uart_0_log_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal strobe : IN STD_LOGIC;
signal valid : IN STD_LOGIC
);
end component tracking_camera_system_jtag_uart_0_log_module;
--synthesis translate_on
begin
--synthesis translate_off
--tracking_camera_system_jtag_uart_0_log, which is an e_log
tracking_camera_system_jtag_uart_0_log : tracking_camera_system_jtag_uart_0_log_module
port map(
clk => clk,
data => fifo_wdata,
strobe => fifo_wr,
valid => fifo_wr
);
wfifo_used <= A_REP(std_logic'('0'), 6);
r_dat <= A_REP(std_logic'('0'), 8);
fifo_FF <= std_logic'('0');
wfifo_empty <= std_logic'('1');
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.all;
entity tracking_camera_system_jtag_uart_0_scfifo_w is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_clear : IN STD_LOGIC;
signal fifo_wdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_wr : IN STD_LOGIC;
signal rd_wfifo : IN STD_LOGIC;
-- outputs:
signal fifo_FF : OUT STD_LOGIC;
signal r_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal wfifo_empty : OUT STD_LOGIC;
signal wfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end entity tracking_camera_system_jtag_uart_0_scfifo_w;
architecture europa of tracking_camera_system_jtag_uart_0_scfifo_w is
--synthesis translate_off
component tracking_camera_system_jtag_uart_0_sim_scfifo_w is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_wdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_wr : IN STD_LOGIC;
-- outputs:
signal fifo_FF : OUT STD_LOGIC;
signal r_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal wfifo_empty : OUT STD_LOGIC;
signal wfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end component tracking_camera_system_jtag_uart_0_sim_scfifo_w;
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- component scfifo is
--GENERIC (
-- lpm_hint : STRING;
-- lpm_numwords : NATURAL;
-- lpm_showahead : STRING;
-- lpm_type : STRING;
-- lpm_width : NATURAL;
-- lpm_widthu : NATURAL;
-- overflow_checking : STRING;
-- underflow_checking : STRING;
-- use_eab : STRING
-- );
-- PORT (
-- signal full : OUT STD_LOGIC;
-- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
-- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
-- signal empty : OUT STD_LOGIC;
-- signal rdreq : IN STD_LOGIC;
-- signal aclr : IN STD_LOGIC;
-- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- signal clock : IN STD_LOGIC;
-- signal wrreq : IN STD_LOGIC
-- );
-- end component scfifo;
--synthesis read_comments_as_HDL off
signal internal_fifo_FF : STD_LOGIC;
signal internal_r_dat : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal internal_wfifo_empty : STD_LOGIC;
signal internal_wfifo_used : STD_LOGIC_VECTOR (5 DOWNTO 0);
begin
--vhdl renameroo for output signals
fifo_FF <= internal_fifo_FF;
--vhdl renameroo for output signals
r_dat <= internal_r_dat;
--vhdl renameroo for output signals
wfifo_empty <= internal_wfifo_empty;
--vhdl renameroo for output signals
wfifo_used <= internal_wfifo_used;
--synthesis translate_off
--the_tracking_camera_system_jtag_uart_0_sim_scfifo_w, which is an e_instance
the_tracking_camera_system_jtag_uart_0_sim_scfifo_w : tracking_camera_system_jtag_uart_0_sim_scfifo_w
port map(
fifo_FF => internal_fifo_FF,
r_dat => internal_r_dat,
wfifo_empty => internal_wfifo_empty,
wfifo_used => internal_wfifo_used,
clk => clk,
fifo_wdata => fifo_wdata,
fifo_wr => fifo_wr
);
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- wfifo : scfifo
-- generic map(
-- lpm_hint => "RAM_BLOCK_TYPE=AUTO",
-- lpm_numwords => 64,
-- lpm_showahead => "OFF",
-- lpm_type => "scfifo",
-- lpm_width => 8,
-- lpm_widthu => 6,
-- overflow_checking => "OFF",
-- underflow_checking => "OFF",
-- use_eab => "ON"
-- )
-- port map(
-- aclr => fifo_clear,
-- clock => clk,
-- data => fifo_wdata,
-- empty => internal_wfifo_empty,
-- full => internal_fifo_FF,
-- q => internal_r_dat,
-- rdreq => rd_wfifo,
-- usedw => internal_wfifo_used,
-- wrreq => fifo_wr
-- );
--
--synthesis read_comments_as_HDL off
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity tracking_camera_system_jtag_uart_0_drom_module is
generic (
POLL_RATE : integer := 100
);
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal incr_addr : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal new_rom : OUT STD_LOGIC;
signal num_bytes : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal safe : OUT STD_LOGIC
);
end entity tracking_camera_system_jtag_uart_0_drom_module;
architecture europa of tracking_camera_system_jtag_uart_0_drom_module is
signal address : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal d1_pre : STD_LOGIC;
signal d2_pre : STD_LOGIC;
signal d3_pre : STD_LOGIC;
signal d4_pre : STD_LOGIC;
signal d5_pre : STD_LOGIC;
signal d6_pre : STD_LOGIC;
signal d7_pre : STD_LOGIC;
signal d8_pre : STD_LOGIC;
signal d9_pre : STD_LOGIC;
TYPE mem_type is ARRAY( 2047 DOWNTO 0) of STD_LOGIC_VECTOR(7 DOWNTO 0);
signal mem_array : mem_type;
TYPE mem_type1 is ARRAY( 1 DOWNTO 0) of STD_LOGIC_VECTOR(31 DOWNTO 0);
signal mutex : mem_type1;
signal pre : STD_LOGIC;
signal safe_wire : STD_LOGIC; -- deal with bogus VHDL type casting
signal safe_delay : STD_LOGIC;
FILE mutex_handle : TEXT ; -- open this for read and write manually.
-- stream can be opened simply for read...
FILE stream_handle : TEXT open READ_MODE is "tracking_camera_system_jtag_uart_0_input_stream.dat";
-- synthesis translate_off
-- convert functions deadlifted from e_rom.pm
FUNCTION convert_string_to_number(string_to_convert : STRING;
final_char_index : NATURAL := 0)
RETURN NATURAL IS
VARIABLE result: NATURAL := 0;
VARIABLE current_index : NATURAL := 1;
VARIABLE the_char : CHARACTER;
BEGIN
IF final_char_index = 0 THEN
result := 0;
ELSE
WHILE current_index <= final_char_index LOOP
the_char := string_to_convert(current_index);
IF '0' <= the_char AND the_char <= '9' THEN
result := result * 16 + character'pos(the_char) - character'pos('0');
ELSIF 'A' <= the_char AND the_char <= 'F' THEN
result := result * 16 + character'pos(the_char) - character'pos('A') + 10;
ELSIF 'a' <= the_char AND the_char <= 'f' THEN
result := result * 16 + character'pos(the_char) - character'pos('a') + 10;
ELSE
report "convert_string_to_number: Ack, a formatting error!";
END IF;
current_index := current_index + 1;
END LOOP;
END IF;
RETURN result;
END convert_string_to_number;
FUNCTION convert_string_to_std_logic(value : STRING; num_chars : INTEGER; mem_width_chars : INTEGER)
RETURN STD_LOGIC_VECTOR is
VARIABLE num_bits: integer := mem_width_chars * 4;
VARIABLE result: std_logic_vector(num_bits-1 downto 0);
VARIABLE curr_char : integer;
VARIABLE min_width : integer := mem_width_chars;
VARIABLE num_nibbles : integer := 0;
BEGIN
result := (others => '0');
num_nibbles := mem_width_chars;
IF (mem_width_chars > num_chars) THEN
num_nibbles := num_chars;
END IF;
FOR I IN 1 TO num_nibbles LOOP
curr_char := num_nibbles - (I-1);
CASE value(I) IS
WHEN '0' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0000";
WHEN '1' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0001";
WHEN '2' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0010";
WHEN '3' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0011";
WHEN '4' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0100";
WHEN '5' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0101";
WHEN '6' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0110";
WHEN '7' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0111";
WHEN '8' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1000";
WHEN '9' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1001";
WHEN 'A' | 'a' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1010";
WHEN 'B' | 'b' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1011";
WHEN 'C' | 'c' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1100";
WHEN 'D' | 'd' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1101";
WHEN 'E' | 'e' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1110";
WHEN 'F' | 'f' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1111";
WHEN ' ' => EXIT;
WHEN HT => exit;
WHEN others =>
ASSERT False
REPORT "function From_Hex: string """ & value & """ contains non-hex character"
severity Error;
EXIT;
END case;
END loop;
RETURN result;
END convert_string_to_std_logic;
-- purpose: open mutex/discard @address/convert value to std_logic_vector
function get_mutex_val (file_name : string)
return STD_LOGIC_VECTOR is
VARIABLE result : STD_LOGIC_VECTOR (31 downto 0) := X"00000000";
FILE handle : TEXT ;
VARIABLE status : file_open_status; -- status for fopen
VARIABLE data_line : LINE;
VARIABLE the_character_from_data_line : CHARACTER;
VARIABLE converted_number : NATURAL := 0;
VARIABLE found_string_array : STRING(1 TO 128);
VARIABLE string_index : NATURAL := 0;
VARIABLE line_length : NATURAL := 0;
begin -- get_mutex_val
file_open (status, handle, file_name, READ_MODE);
IF (status=OPEN_OK) THEN
WHILE NOT(endfile(handle)) LOOP
readline(handle, data_line);
line_length := data_line'LENGTH; -- match ' for emacs font-lock
WHILE line_length > 0 LOOP
read(data_line, the_character_from_data_line);
-- check for the @ character indicating a new address wad
-- if found, ignore the line! This is just protection
IF '@' = the_character_from_data_line THEN
exit; -- bail out of this line
end if;
-- process the hex address, character by character ...
IF NOT(' ' = the_character_from_data_line) THEN
string_index := string_index + 1;
found_string_array(string_index) := the_character_from_data_line;
END IF;
line_length := line_length - 1;
end loop; -- read characters
end loop; -- read lines
END IF;
file_close (handle);
if string_index /= 0 then
result := convert_string_to_std_logic(found_string_array, string_index, 8);
end if;
return result;
end get_mutex_val;
-- purpose: emulate verilogs readmemh function (mostly)
-- in verilog you say: $readmemh ("file", array);
-- in VHDL, we say: array <= readmemh("file"); -- which makes more sense.
function readmemh (file_name : string)
return mem_type is
VARIABLE result : mem_type;
FILE handle : TEXT ;
VARIABLE status : file_open_status; -- status for fopen
VARIABLE data_line : LINE;
VARIABLE b_address : BOOLEAN := FALSE; -- distinguish between addrs and data
VARIABLE the_character_from_data_line : CHARACTER;
VARIABLE converted_number : NATURAL := 0;
VARIABLE found_string_array : STRING(1 TO 128);
VARIABLE string_index : NATURAL := 0;
VARIABLE line_length : NATURAL := 0;
VARIABLE load_address : NATURAL := 0;
VARIABLE mem_index : NATURAL := 0;
begin -- readmemh
file_open (status, handle, file_name, READ_MODE);
WHILE NOT(endfile(handle)) LOOP
readline(handle, data_line);
line_length := data_line'LENGTH; -- match ' for emacs font-lock
b_address := false;
WHILE line_length > 0 LOOP
read(data_line, the_character_from_data_line);
-- check for the @ character indicating a new address wad
-- if found, ignore the line! This is just protection
IF '@' = the_character_from_data_line and not b_address then -- is addr
b_address := true;
end if;
-- process the hex address, character by character ...
IF NOT((' ' = the_character_from_data_line) or
('@' = the_character_from_data_line) or
(lf = the_character_from_data_line) or
(cr = the_character_from_data_line)) THEN
string_index := string_index + 1;
found_string_array(string_index) := the_character_from_data_line;
END IF;
line_length := line_length - 1;
end loop; -- read characters
if b_address then
mem_index := convert_string_to_number(found_string_array, string_index);
b_address := FALSE;
else
result(mem_index) := convert_string_to_std_logic(found_string_array, string_index, 2);
end if;
string_index := 0;
end loop; -- read lines
file_close (handle);
return result;
end readmemh;
-- purpose: emulate verilogs readmemb function (mostly)
-- in verilog you say: $readmemb ("file", array);
-- in VHDL, we say: array <= readmemb("file"); -- which makes more sense.
function readmemb (file_name : string)
return mem_type is
VARIABLE result : mem_type;
FILE handle : TEXT ;
VARIABLE status : file_open_status; -- status for fopen
VARIABLE data_line : LINE;
VARIABLE the_character_from_data_line : BIT_VECTOR(7 DOWNTO 0); -- '0' & '1's
VARIABLE line_length : NATURAL := 0;
VARIABLE mem_index : NATURAL := 0;
begin -- readmemb
file_open (status, handle, file_name, READ_MODE);
WHILE NOT(endfile(handle)) LOOP
readline(handle, data_line);
line_length := data_line'LENGTH; -- match ' for emacs font-lock
WHILE line_length > 7 LOOP
read(data_line, the_character_from_data_line);
-- No @ characters allowed in binary/bit_vector mode
result(mem_index) := To_stdlogicvector(the_character_from_data_line);
mem_index := mem_index + 1;
line_length := line_length - 8;
end loop; -- read characters
end loop; -- read lines
file_close (handle);
return result;
end readmemb;
-- synthesis translate_on
begin
--synthesis translate_off
q <= mem_array(CONV_INTEGER(UNSIGNED((address))));
process (clk, reset_n)
begin
if reset_n = '0' then
d1_pre <= std_logic'('0');
d2_pre <= std_logic'('0');
d3_pre <= std_logic'('0');
d4_pre <= std_logic'('0');
d5_pre <= std_logic'('0');
d6_pre <= std_logic'('0');
d7_pre <= std_logic'('0');
d8_pre <= std_logic'('0');
d9_pre <= std_logic'('0');
new_rom <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_pre <= pre;
d2_pre <= d1_pre;
d3_pre <= d2_pre;
d4_pre <= d3_pre;
d5_pre <= d4_pre;
d6_pre <= d5_pre;
d7_pre <= d6_pre;
d8_pre <= d7_pre;
d9_pre <= d8_pre;
new_rom <= d9_pre;
end if;
end process;
num_bytes <= mutex(1);
safe <= safe_wire;
safe_wire <= to_std_logic( address < mutex(1) );
process (clk, reset_n)
begin
if reset_n = '0' then
safe_delay <= '0';
elsif clk'event and clk = '1' then -- balance ' for emacs quoting
safe_delay <= safe_wire;
end if;
end process;
process (clk, reset_n)
variable poll_count : integer := POLL_RATE; -- STD_LOGIC_VECTOR (31:0);
variable status : file_open_status; -- status for fopen
variable mutex_string : LINE; -- temp space for read/write data
variable stream_string : LINE; -- temp space for read data
variable init_done : BOOLEAN; -- only used if non-interactive
variable interactive : BOOLEAN := TRUE;
begin
if reset_n /= '1' then
address <= "000000000000";
mem_array(0) <= X"00";
mutex(0) <= X"00000000";
mutex(1) <= X"00000000";
pre <= '0';
init_done := FALSE;
elsif clk'event and clk = '1' then -- balance ' for emacs quoting
pre <= '0';
if incr_addr = '1' and safe_wire = '1' then
address <= address + "000000000001";
end if;
-- blast mutex via textio after falling edge of safe
if mutex(0) /= X"00000000" and safe_wire = '0' and safe_delay = '1' then
if interactive then -- bash mutex
file_open (status, mutex_handle, "tracking_camera_system_jtag_uart_0_input_mutex.dat", WRITE_MODE);
write (mutex_string, string'("0")); -- balance ' for emacs quoting
writeline (mutex_handle, mutex_string);
file_close (mutex_handle);
mutex(0) <= X"00000000";
else -- non-nteractive does not bash mutex: it stops poll counter
init_done := TRUE;
end if;
end if;
if poll_count < POLL_RATE then -- wait
if not init_done then -- stop counting if init_done is TRUE
poll_count := poll_count + 1;
end if;
else -- do the real work
poll_count := 0;
-- get mutex via textio ...
mutex(0) <= get_mutex_val ("tracking_camera_system_jtag_uart_0_input_mutex.dat");
if mutex(0) /= X"00000000" and safe_wire = '0' then
-- read stream into array after previous stream is complete
mutex (1) <= mutex (0); -- save mutex value for address compare
-- get mem_array via textio ...
mem_array <= readmemb("tracking_camera_system_jtag_uart_0_input_stream.dat");
-- prep address and pre-pulse to alert world to new contents
address <= "000000000000";
pre <= '1';
end if; -- poll_count
end if; -- clock
end if; -- reset
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tracking_camera_system_jtag_uart_0_sim_scfifo_r is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_rd : IN STD_LOGIC;
signal rst_n : IN STD_LOGIC;
-- outputs:
signal fifo_EF : OUT STD_LOGIC;
signal fifo_rdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rfifo_full : OUT STD_LOGIC;
signal rfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end entity tracking_camera_system_jtag_uart_0_sim_scfifo_r;
architecture europa of tracking_camera_system_jtag_uart_0_sim_scfifo_r is
--synthesis translate_off
component tracking_camera_system_jtag_uart_0_drom_module is
generic (
POLL_RATE : integer := 100
);
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal incr_addr : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal new_rom : OUT STD_LOGIC;
signal num_bytes : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal safe : OUT STD_LOGIC
);
end component tracking_camera_system_jtag_uart_0_drom_module;
--synthesis translate_on
signal bytes_left : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_rd_d : STD_LOGIC;
signal internal_fifo_rdata1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal internal_rfifo_full1 : STD_LOGIC;
signal new_rom : STD_LOGIC;
signal num_bytes : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rfifo_entries : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal safe : STD_LOGIC;
begin
--vhdl renameroo for output signals
fifo_rdata <= internal_fifo_rdata1;
--vhdl renameroo for output signals
rfifo_full <= internal_rfifo_full1;
--synthesis translate_off
--tracking_camera_system_jtag_uart_0_drom, which is an e_drom
tracking_camera_system_jtag_uart_0_drom : tracking_camera_system_jtag_uart_0_drom_module
port map(
new_rom => new_rom,
num_bytes => num_bytes,
q => internal_fifo_rdata1,
safe => safe,
clk => clk,
incr_addr => fifo_rd_d,
reset_n => rst_n
);
-- Generate rfifo_entries for simulation
process (clk, rst_n)
begin
if rst_n = '0' then
bytes_left <= std_logic_vector'("00000000000000000000000000000000");
fifo_rd_d <= std_logic'('0');
elsif clk'event and clk = '1' then
fifo_rd_d <= fifo_rd;
-- decrement on read
if std_logic'(fifo_rd_d) = '1' then
bytes_left <= A_EXT (((std_logic_vector'("0") & (bytes_left)) - (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 32);
end if;
-- catch new contents
if std_logic'(new_rom) = '1' then
bytes_left <= num_bytes;
end if;
end if;
end process;
fifo_EF <= to_std_logic((bytes_left = std_logic_vector'("00000000000000000000000000000000")));
internal_rfifo_full1 <= to_std_logic((bytes_left>std_logic_vector'("00000000000000000000000001000000")));
rfifo_entries <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_rfifo_full1)) = '1'), std_logic_vector'("00000000000000000000000001000000"), bytes_left), 7);
rfifo_used <= rfifo_entries(5 DOWNTO 0);
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.all;
entity tracking_camera_system_jtag_uart_0_scfifo_r is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_clear : IN STD_LOGIC;
signal fifo_rd : IN STD_LOGIC;
signal rst_n : IN STD_LOGIC;
signal t_dat : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal wr_rfifo : IN STD_LOGIC;
-- outputs:
signal fifo_EF : OUT STD_LOGIC;
signal fifo_rdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rfifo_full : OUT STD_LOGIC;
signal rfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end entity tracking_camera_system_jtag_uart_0_scfifo_r;
architecture europa of tracking_camera_system_jtag_uart_0_scfifo_r is
--synthesis translate_off
component tracking_camera_system_jtag_uart_0_sim_scfifo_r is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_rd : IN STD_LOGIC;
signal rst_n : IN STD_LOGIC;
-- outputs:
signal fifo_EF : OUT STD_LOGIC;
signal fifo_rdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rfifo_full : OUT STD_LOGIC;
signal rfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end component tracking_camera_system_jtag_uart_0_sim_scfifo_r;
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- component scfifo is
--GENERIC (
-- lpm_hint : STRING;
-- lpm_numwords : NATURAL;
-- lpm_showahead : STRING;
-- lpm_type : STRING;
-- lpm_width : NATURAL;
-- lpm_widthu : NATURAL;
-- overflow_checking : STRING;
-- underflow_checking : STRING;
-- use_eab : STRING
-- );
-- PORT (
-- signal full : OUT STD_LOGIC;
-- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
-- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
-- signal empty : OUT STD_LOGIC;
-- signal rdreq : IN STD_LOGIC;
-- signal aclr : IN STD_LOGIC;
-- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- signal clock : IN STD_LOGIC;
-- signal wrreq : IN STD_LOGIC
-- );
-- end component scfifo;
--synthesis read_comments_as_HDL off
signal internal_fifo_EF : STD_LOGIC;
signal internal_fifo_rdata : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal internal_rfifo_full : STD_LOGIC;
signal internal_rfifo_used : STD_LOGIC_VECTOR (5 DOWNTO 0);
begin
--vhdl renameroo for output signals
fifo_EF <= internal_fifo_EF;
--vhdl renameroo for output signals
fifo_rdata <= internal_fifo_rdata;
--vhdl renameroo for output signals
rfifo_full <= internal_rfifo_full;
--vhdl renameroo for output signals
rfifo_used <= internal_rfifo_used;
--synthesis translate_off
--the_tracking_camera_system_jtag_uart_0_sim_scfifo_r, which is an e_instance
the_tracking_camera_system_jtag_uart_0_sim_scfifo_r : tracking_camera_system_jtag_uart_0_sim_scfifo_r
port map(
fifo_EF => internal_fifo_EF,
fifo_rdata => internal_fifo_rdata,
rfifo_full => internal_rfifo_full,
rfifo_used => internal_rfifo_used,
clk => clk,
fifo_rd => fifo_rd,
rst_n => rst_n
);
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- rfifo : scfifo
-- generic map(
-- lpm_hint => "RAM_BLOCK_TYPE=AUTO",
-- lpm_numwords => 64,
-- lpm_showahead => "OFF",
-- lpm_type => "scfifo",
-- lpm_width => 8,
-- lpm_widthu => 6,
-- overflow_checking => "OFF",
-- underflow_checking => "OFF",
-- use_eab => "ON"
-- )
-- port map(
-- aclr => fifo_clear,
-- clock => clk,
-- data => t_dat,
-- empty => internal_fifo_EF,
-- full => internal_rfifo_full,
-- q => internal_fifo_rdata,
-- rdreq => fifo_rd,
-- usedw => internal_rfifo_used,
-- wrreq => wr_rfifo
-- );
--
--synthesis read_comments_as_HDL off
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.all;
entity tracking_camera_system_jtag_uart_0 is
port (
-- inputs:
signal av_address : IN STD_LOGIC;
signal av_chipselect : IN STD_LOGIC;
signal av_read_n : IN STD_LOGIC;
signal av_write_n : IN STD_LOGIC;
signal av_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal rst_n : IN STD_LOGIC;
-- outputs:
signal av_irq : OUT STD_LOGIC;
signal av_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal av_waitrequest : OUT STD_LOGIC;
signal dataavailable : OUT STD_LOGIC;
signal readyfordata : OUT STD_LOGIC
);
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of tracking_camera_system_jtag_uart_0 : entity is "SUPPRESS_DA_RULE_INTERNAL=""R101,C106,D101,D103""";
end entity tracking_camera_system_jtag_uart_0;
architecture europa of tracking_camera_system_jtag_uart_0 is
component tracking_camera_system_jtag_uart_0_scfifo_w is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_clear : IN STD_LOGIC;
signal fifo_wdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_wr : IN STD_LOGIC;
signal rd_wfifo : IN STD_LOGIC;
-- outputs:
signal fifo_FF : OUT STD_LOGIC;
signal r_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal wfifo_empty : OUT STD_LOGIC;
signal wfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end component tracking_camera_system_jtag_uart_0_scfifo_w;
component tracking_camera_system_jtag_uart_0_scfifo_r is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_clear : IN STD_LOGIC;
signal fifo_rd : IN STD_LOGIC;
signal rst_n : IN STD_LOGIC;
signal t_dat : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal wr_rfifo : IN STD_LOGIC;
-- outputs:
signal fifo_EF : OUT STD_LOGIC;
signal fifo_rdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rfifo_full : OUT STD_LOGIC;
signal rfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end component tracking_camera_system_jtag_uart_0_scfifo_r;
--synthesis read_comments_as_HDL on
-- component alt_jtag_atlantic is
--GENERIC (
-- INSTANCE_ID : NATURAL;
-- LOG2_RXFIFO_DEPTH : NATURAL;
-- LOG2_TXFIFO_DEPTH : NATURAL;
-- SLD_AUTO_INSTANCE_INDEX : STRING
-- );
-- PORT (
-- signal t_pause : OUT STD_LOGIC;
-- signal r_ena : OUT STD_LOGIC;
-- signal t_ena : OUT STD_LOGIC;
-- signal t_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
-- signal t_dav : IN STD_LOGIC;
-- signal rst_n : IN STD_LOGIC;
-- signal r_dat : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- signal r_val : IN STD_LOGIC;
-- signal clk : IN STD_LOGIC
-- );
-- end component alt_jtag_atlantic;
--synthesis read_comments_as_HDL off
signal ac : STD_LOGIC;
signal activity : STD_LOGIC;
signal fifo_AE : STD_LOGIC;
signal fifo_AF : STD_LOGIC;
signal fifo_EF : STD_LOGIC;
signal fifo_FF : STD_LOGIC;
signal fifo_clear : STD_LOGIC;
signal fifo_rd : STD_LOGIC;
signal fifo_rdata : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_wdata : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_wr : STD_LOGIC;
signal ien_AE : STD_LOGIC;
signal ien_AF : STD_LOGIC;
signal internal_av_waitrequest : STD_LOGIC;
signal ipen_AE : STD_LOGIC;
signal ipen_AF : STD_LOGIC;
signal pause_irq : STD_LOGIC;
signal r_dat : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal r_ena : STD_LOGIC;
signal r_val : STD_LOGIC;
signal rd_wfifo : STD_LOGIC;
signal read_0 : STD_LOGIC;
signal rfifo_full : STD_LOGIC;
signal rfifo_used : STD_LOGIC_VECTOR (5 DOWNTO 0);
signal rvalid : STD_LOGIC;
signal sim_r_ena : STD_LOGIC;
signal sim_t_dat : STD_LOGIC;
signal sim_t_ena : STD_LOGIC;
signal sim_t_pause : STD_LOGIC;
signal t_dat : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal t_dav : STD_LOGIC;
signal t_ena : STD_LOGIC;
signal t_pause : STD_LOGIC;
signal wfifo_empty : STD_LOGIC;
signal wfifo_used : STD_LOGIC_VECTOR (5 DOWNTO 0);
signal woverflow : STD_LOGIC;
signal wr_rfifo : STD_LOGIC;
begin
--avalon_jtag_slave, which is an e_avalon_slave
rd_wfifo <= r_ena AND NOT wfifo_empty;
wr_rfifo <= t_ena AND NOT rfifo_full;
fifo_clear <= NOT rst_n;
--the_tracking_camera_system_jtag_uart_0_scfifo_w, which is an e_instance
the_tracking_camera_system_jtag_uart_0_scfifo_w : tracking_camera_system_jtag_uart_0_scfifo_w
port map(
fifo_FF => fifo_FF,
r_dat => r_dat,
wfifo_empty => wfifo_empty,
wfifo_used => wfifo_used,
clk => clk,
fifo_clear => fifo_clear,
fifo_wdata => fifo_wdata,
fifo_wr => fifo_wr,
rd_wfifo => rd_wfifo
);
--the_tracking_camera_system_jtag_uart_0_scfifo_r, which is an e_instance
the_tracking_camera_system_jtag_uart_0_scfifo_r : tracking_camera_system_jtag_uart_0_scfifo_r
port map(
fifo_EF => fifo_EF,
fifo_rdata => fifo_rdata,
rfifo_full => rfifo_full,
rfifo_used => rfifo_used,
clk => clk,
fifo_clear => fifo_clear,
fifo_rd => fifo_rd,
rst_n => rst_n,
t_dat => t_dat,
wr_rfifo => wr_rfifo
);
ipen_AE <= ien_AE AND fifo_AE;
ipen_AF <= ien_AF AND ((pause_irq OR fifo_AF));
av_irq <= ipen_AE OR ipen_AF;
activity <= t_pause OR t_ena;
process (clk, rst_n)
begin
if rst_n = '0' then
pause_irq <= std_logic'('0');
elsif clk'event and clk = '1' then
-- only if fifo is not empty...
if std_logic'((t_pause AND NOT fifo_EF)) = '1' then
pause_irq <= std_logic'('1');
elsif std_logic'(read_0) = '1' then
pause_irq <= std_logic'('0');
end if;
end if;
end process;
process (clk, rst_n)
begin
if rst_n = '0' then
r_val <= std_logic'('0');
t_dav <= std_logic'('1');
elsif clk'event and clk = '1' then
r_val <= r_ena AND NOT wfifo_empty;
t_dav <= NOT rfifo_full;
end if;
end process;
process (clk, rst_n)
begin
if rst_n = '0' then
fifo_AE <= std_logic'('0');
fifo_AF <= std_logic'('0');
fifo_wr <= std_logic'('0');
rvalid <= std_logic'('0');
read_0 <= std_logic'('0');
ien_AE <= std_logic'('0');
ien_AF <= std_logic'('0');
ac <= std_logic'('0');
woverflow <= std_logic'('0');
internal_av_waitrequest <= std_logic'('1');
elsif clk'event and clk = '1' then
fifo_AE <= to_std_logic(((std_logic_vector'("0000000000000000000000000") & (Std_Logic_Vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used)))<=std_logic_vector'("00000000000000000000000000001000")));
fifo_AF <= to_std_logic(((std_logic_vector'("000000000000000000000000") & (((std_logic_vector'("01000000") - (std_logic_vector'("0") & (Std_Logic_Vector'(A_ToStdLogicVector(rfifo_full) & rfifo_used)))))))<=std_logic_vector'("00000000000000000000000000001000")));
fifo_wr <= std_logic'('0');
read_0 <= std_logic'('0');
internal_av_waitrequest <= NOT (((av_chipselect AND ((NOT av_write_n OR NOT av_read_n))) AND internal_av_waitrequest));
if std_logic'(activity) = '1' then
ac <= std_logic'('1');
end if;
-- write
if std_logic'(((av_chipselect AND NOT av_write_n) AND internal_av_waitrequest)) = '1' then
-- addr 1 is control; addr 0 is data
if std_logic'(av_address) = '1' then
ien_AF <= av_writedata(0);
ien_AE <= av_writedata(1);
if std_logic'((av_writedata(10) AND NOT activity)) = '1' then
ac <= std_logic'('0');
end if;
else
fifo_wr <= NOT fifo_FF;
woverflow <= fifo_FF;
end if;
end if;
-- read
if std_logic'(((av_chipselect AND NOT av_read_n) AND internal_av_waitrequest)) = '1' then
-- addr 1 is interrupt; addr 0 is data
if std_logic'(NOT av_address) = '1' then
rvalid <= NOT fifo_EF;
end if;
read_0 <= NOT av_address;
end if;
end if;
end process;
fifo_wdata <= av_writedata(7 DOWNTO 0);
fifo_rd <= A_WE_StdLogic((std_logic'(((((av_chipselect AND NOT av_read_n) AND internal_av_waitrequest) AND NOT av_address))) = '1'), NOT fifo_EF, std_logic'('0'));
av_readdata <= A_EXT (A_WE_StdLogicVector((std_logic'(read_0) = '1'), (std_logic_vector'("0") & ((A_REP(std_logic'('0'), 9) & A_ToStdLogicVector(rfifo_full) & rfifo_used & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(NOT fifo_FF) & A_ToStdLogicVector(NOT fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & fifo_rdata))), (A_REP(std_logic'('0'), 9) & ((std_logic_vector'("01000000") - (std_logic_vector'("0") & (Std_Logic_Vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used))))) & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(NOT fifo_FF) & A_ToStdLogicVector(NOT fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & A_REP(std_logic'('0'), 6) & A_ToStdLogicVector(ien_AE) & A_ToStdLogicVector(ien_AF))), 32);
process (clk, rst_n)
begin
if rst_n = '0' then
readyfordata <= std_logic'('0');
elsif clk'event and clk = '1' then
readyfordata <= NOT fifo_FF;
end if;
end process;
--vhdl renameroo for output signals
av_waitrequest <= internal_av_waitrequest;
--synthesis translate_off
-- Tie off Atlantic Interface signals not used for simulation
process (clk)
begin
if clk'event and clk = '1' then
sim_t_pause <= std_logic'('0');
sim_t_ena <= std_logic'('0');
sim_t_dat <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(t_dav) = '1'), r_dat, A_REP(r_val, 8)));
sim_r_ena <= std_logic'('0');
end if;
end process;
r_ena <= sim_r_ena;
t_ena <= sim_t_ena;
t_dat <= std_logic_vector'("0000000") & (A_TOSTDLOGICVECTOR(sim_t_dat));
t_pause <= sim_t_pause;
process (fifo_EF)
begin
dataavailable <= NOT fifo_EF;
end process;
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- tracking_camera_system_jtag_uart_0_alt_jtag_atlantic : alt_jtag_atlantic
-- generic map(
-- INSTANCE_ID => 0,
-- LOG2_RXFIFO_DEPTH => 6,
-- LOG2_TXFIFO_DEPTH => 6,
-- SLD_AUTO_INSTANCE_INDEX => "YES"
-- )
-- port map(
-- clk => clk,
-- r_dat => r_dat,
-- r_ena => r_ena,
-- r_val => r_val,
-- rst_n => rst_n,
-- t_dat => t_dat,
-- t_dav => t_dav,
-- t_ena => t_ena,
-- t_pause => t_pause
-- );
--
-- process (clk, rst_n)
-- begin
-- if rst_n = '0' then
-- dataavailable <= std_logic'('0');
-- elsif clk'event and clk = '1' then
-- dataavailable <= NOT fifo_EF;
-- end if;
--
-- end process;
--
--synthesis read_comments_as_HDL off
end europa;
| gpl-2.0 | 4f81704c66972eaaaaa7f208099ceda3 | 0.574678 | 3.667963 | false | false | false | false |
SonicFrog/ArchOrd | sipo.vhdl | 1 | 1,236 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity SIPO is
port (
Reset : in std_logic;
Start : in std_logic;
DataIn : in std_logic;
DataOut : out std_logic(7 downto 0)
Valid : out std_logic
);
end SIPO;
architecture synth of sipo is
signal content : std_logic_vector(7 downto 0);
signal counter : std_logic(2 downto 0);
signal counting : std_logic;
begin
-- This signal is at 1 when we are receiving bits
counting <= Start or not(counter = "000");
-- This signal is at 1 when we finished receiving bits
Valid <= counter = "000" and not Start;
-- This contains the final parralel out when it is available
-- otherwise it is zeros
DataOut <= content when counter = "000"
else (others => '0');
-- This process does the counting
count : process(clk)
begin
if rising_edge(clk) then
if counting = '1' then
counter <= counter + 1;
end if;
end if;
end process;
-- This process puts the data in the correct place
fetch : process(clk, counting)
begin
if rising_edge(clk) then
if counting = '1' then
content <= DataIn & content(6 downto 0);
end if;
end if;
end process;
end architecture ; -- synth | gpl-2.0 | a3e052a80a49494ba208dd31fe2e8f12 | 0.67233 | 2.971154 | false | false | false | false |
ou-cse-378/vhdl-tetris | TetrisIO.vhd | 1 | 10,052 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: tetrisIO.vhd
-- // Date: 12/9/2004
-- // Description: Main Tetris Program
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TetrisIO is
port ( NESData : in std_logic;
mclk : in std_logic;
NESClock : out std_logic;
NESLatch: out std_logic;
RGB : out std_logic_vector(2 downto 0);
VSync : out std_logic;
HSync : out std_logic;
LDG : out std_logic;
LED : out std_logic;
LD : out std_logic_vector(1 to 8);
bn : in std_logic;
BTN4 : in std_logic;
SW : in std_logic_vector(7 downto 0);
A : out std_logic_vector(1 to 4);
AtoG : out std_logic_vector(6 downto 0));
end TetrisIO;
architecture Behavioral of TetrisIO is
signal clr : std_logic;
signal tClk190hz, tClk25mhz, tClk48khz : std_logic;
signal Buttons : std_logic_vector(7 downto 0);
signal tGPUBlockAddr : std_logic_vector(4 downto 0); --Holds static blocks
signal tGPUBlockData : std_logic_vector(15 downto 0);
signal tDiag : std_logic;
-- // intermediate signals connecting into the x position register
signal t_xpos_in : std_logic_vector(3 downto 0) := "0000";
signal t_xpos_out : std_logic_vector(3 downto 0) := "0000";
signal t_xpos_load : std_logic := '0';
-- // intermediate signals connecting into the y position register
signal t_ypos_in : std_logic_vector(4 downto 0) := "00000";
signal t_ypos_out : std_logic_vector(4 downto 0) := "00000";
signal t_ypos_load : std_logic := '0';
-- // intermediate signals connecting into the block shape register
signal t_block_in : std_logic_vector(15 downto 0) := X"0000";
signal t_block_out : std_logic_vector(15 downto 0) := X"0000";
signal t_block_load : std_logic := '0';
Signal tT : std_logic_vector(15 downto 0);
signal tDigLoad : std_logic;
Signal tAddr : std_logic_vector(15 downto 0);
Signal tM : std_logic_vector(15 downto 0);
Signal tLinesDestroyed : std_logic_vector(2 downto 0);
signal tClearLines : std_logic := '0';
Signal tClr : std_logic := '0';
signal clrflag : std_logic := '0';
-- // '1' denotes "PAUSED" status
signal t_paused : std_logic := '0';
-- // Intermediate signals for tetris_control
Signal t_row_no : std_logic_vector(4 downto 0);
Signal t_row_val : std_logic_vector(15 downto 0);
Signal t_row_val2 : std_logic_vector(15 downto 0);
Signal t_row_load : std_logic;
signal tRandom : std_logic_vector(2 downto 0) := "000";
component tetris_control is
port(
clk: in STD_LOGIC;
clr: in STD_LOGIC;
i_buttons: in STD_LOGIC_VECTOR(7 downto 0); -- controller buttons vector
i_block_code: in STD_LOGIC_VECTOR(2 downto 0); -- 0..8, chooses next block
o_load_xpos: out STD_LOGIC; -- '1' when xreg should be loaded with xpos
o_xpos_val: out STD_LOGIC_VECTOR(3 downto 0); -- 0..9 < 16
o_load_ypos: out STD_LOGIC; -- '1' when yreg should be loaded with ypos
o_ypos_val: out STD_LOGIC_VECTOR(4 downto 0); -- 0..19 < 32
o_load_block: out STD_LOGIC; -- '1' when blockreg should be loaded with shape
o_block_val: out STD_LOGIC_VECTOR(15 downto 0); -- 4x4 block, '1' = SOLID
o_paused: out STD_LOGIC; -- '1' when the game is paused
-- // for fetching rows into and out of tetris_control / ramtable
i_row_val: in STD_LOGIC_VECTOR(15 downto 0);
o_row_fetch: out STD_LOGIC; -- '1' when i_row_val should be loaded for i_row_no
o_row_load: out STD_LOGIC; -- '1' when o_row_val should br put for o_row_no
o_row_no: out STD_LOGIC_VECTOR(4 downto 0); -- 0..19 < 32
o_row_val: out STD_LOGIC_VECTOR(15 downto 0);
o_Lines_Destroyed : out std_logic_vector(2 downto 0);
i_clear_Lines : in std_logic
);
end component;
component reg is
generic(width: positive);
port
(
d: in STD_LOGIC_VECTOR (width-1 downto 0);
load: in STD_LOGIC;
clr: in STD_LOGIC;
clk: in STD_LOGIC;
q: out STD_LOGIC_VECTOR (width-1 downto 0)
);
end component;
component dpram32x16 IS
port
(
A: IN std_logic_VECTOR(4 downto 0);
CLK: IN std_logic;
D: IN std_logic_VECTOR(15 downto 0);
WE: IN std_logic;
DPRA: IN std_logic_VECTOR(4 downto 0);
DPO: OUT std_logic_VECTOR(15 downto 0);
SPO: OUT std_logic_VECTOR(15 downto 0)
);
end component;
component NES is
Port ( DataI : in std_logic;
clkO : out std_logic;
clkI : in std_logic; --50 mhz
waitCLKI : std_logic; --97.6 Khz
clr : in std_logic;
latchO : out std_logic;
Buttons : out std_logic_vector(7 downto 0));
end component;
component ClockDiv is
Port ( iMclk : in std_logic;
oClk190Hz : out std_logic;
oClk48Khz : out std_logic;
oClk25Mhz : out std_logic);
end component;
component GPU is
port(
iClk25MHZ : in std_logic;
iPaused : in std_logic;
iScore : std_logic_vector(15 downto 0);
oBlockAddr : out std_logic_vector(4 downto 0); --Holds static blocks
iBlockData : in std_logic_vector(15 downto 0); --Holds each row
iBlockY : in std_logic_vector(4 downto 0); --top edge of moving block
iBlockX : in std_logic_vector(3 downto 0); --left edge of moving block
iBlockReg : in std_logic_vector(15 downto 0); --encoded dynamic block memory
iClr : in std_logic;
iDiag : in std_logic;
oRGB : out std_logic_vector(2 downto 0);
oVSync : out std_logic;
oHSync : out std_logic);
end component;
component whypcore is
port (
p : out STD_LOGIC_VECTOR(15 downto 0);
destro : in STD_LOGIC_VECTOR(2 downto 0);
m : in STD_LOGIC_VECTOR(15 downto 0);
SW : in std_logic_vector(7 downto 0);
BTN4 : in std_logic;
clk : in STD_LOGIC;
clr : in STD_LOGIC;
digload : out STD_LOGIC;
ldload: out STD_LOGIC;
t : out STD_LOGIC_VECTOR(15 downto 0);
o_Clear_Lines : out std_logic
);
end component;
component Promscore is
port (
addr : in STD_LOGIC_VECTOR (15 downto 0);
M : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
component dig7seg is
Port ( T: in std_logic_vector(15 downto 0);
digload: in std_logic;
clr : in std_logic;
clk : in std_logic; --25 Mhz
cclk : in std_logic; --190 Hz
AtoG : out std_logic_vector(6 downto 0);
A : out std_logic_vector(1 to 4));
end component;
component IBUFG
port (
I : in STD_LOGIC;
O : out std_logic
);
end component;
component random is
Port ( iClk : in std_logic;
iClr : in std_logic;
iM : in std_logic_vector(15 downto 0);
iP : in std_logic_vector(15 downto 0);
oRandom : out std_logic_vector(2 downto 0);
iT : in std_logic_vector(15 downto 0);
iX : in std_logic_vector(3 downto 0);
iY : in std_logic_vector(4 downto 0));
end component;
begin
RND00 : random port map(
iClk => tclk25Mhz,
iClr => clr,
iP => tAddr,
iM => tM,
oRandom => tRandom,
iX => t_xpos_in,
iY => t_ypos_in,
iT => tT);
GPU00 : GPU port map(
iClk25Mhz => tclk25Mhz,
iPaused => t_paused,
iScore => X"0000",
oBlockAddr => tGPUBlockAddr,
iBlockData => tGPUBlockData,
iBlockX => t_xpos_out,
iBlockY => t_ypos_out,
iBlockReg => t_block_out,
iClr => clr,
iDiag => tDiag,
oRGB => RGB,
oVSync => VSync,
oHSync => HSync);
CLK00 : ClockDiv port map(iMclk => mclk, oClk190Hz => tClk190hz, oClk48khz => tClk48khz, oClk25mhz => tClk25mhz);
NES00 : NES port map(DataI => NESData, clkO => NESClock, clkI => tclk25Mhz, WaitclkI => tClk48Khz, clr => clr, latchO => NESLatch, buttons => Buttons);
DEB00 : IBUFG port map(I => BN, O => tClr);
RegXPos : Reg generic map(width => 4) port map(clk => tclk25Mhz, clr => clr, d => t_xpos_in, q => t_xpos_out, load => t_xpos_load);
RegYPos : Reg generic map(width => 16) port map(clk => tclk25Mhz, clr => clr, d => t_block_in, q => t_block_out, load => t_block_load);
RegBlk: Reg generic map(width => 5) port map(clk => tclk25Mhz, clr => clr, d => t_ypos_in, q => t_ypos_out, load => t_ypos_load);
BlockRAM : dpram32x16 port map(A => t_row_no, clk => tclk25Mhz, d => t_row_val, we => t_row_load, DPRA=> tGPUBlockAddr, SPO => t_row_val2, DPO => tGPUBlockData);
tc_00: tetris_control port map(
clk => tclk25Mhz,
clr => clr,
i_buttons => Buttons,
i_block_code => tRandom,
o_load_xpos => t_xpos_load,
o_xpos_val => t_xpos_in,
o_load_ypos => t_ypos_load,
o_ypos_val => t_ypos_in,
o_load_block => t_block_load,
o_block_val => t_block_in,
o_paused => t_paused,
i_row_val => t_row_val2,
--o_row_fetch
o_row_load => t_row_load,
o_row_no => t_row_no,
o_row_val => t_row_val,
o_Lines_Destroyed => tLinesDestroyed,
i_clear_Lines => tClearLines);
d7s00: dig7seg port map(
T => tT,
digload => tDigLoad,
clr => clr,
clk => tclk25Mhz,
cclk => tclk190hz,
AtoG => AtoG,
A => A);
PRM00: Promscore port map(
addr => tAddr,
M => tM);
WPC00 : whypcore port map(
p => tAddr,
M => tM,
digload => tDigLoad,
T => tT,
clk => tclk25Mhz,
clr => clr,
Destro => tLinesDestroyed,
BTN4 => BTN4,
SW => SW,
o_Clear_Lines => tClearLines);
Reset : process(tClk190hz, tClr, clr, Buttons)
begin
if tClk190hz'event and tClk190hz = '1' then
if (((Buttons(7) and Buttons(6) and Buttons(5) and Buttons(4)) or tClr) and (not clrflag)) = '1' then
clr <= '1';
clrflag <= '1';
else
clr <= '0';
clrflag <= '0';
end if;
end if;
end process;
tDiag <= SW(7);
LD <= Buttons;
LED <= clr;
LDG <= '1';
end Behavioral; | mit | fead7e98b1dec4a0880e2aa4717ffd01 | 0.611918 | 2.887676 | false | false | false | false |
DreamIP/GPStudio | support/component/gp_dcfifo/gp_dcfifo.vhd | 1 | 2,465 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.math_real.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY gp_dcfifo IS
GENERIC(FIFO_DEPTH : positive;
DATA_WIDTH : positive);
PORT
(
aclr : IN STD_LOGIC;
--- writer
data : IN STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
wrfull : OUT STD_LOGIC;
--- reader
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
rdempty : OUT STD_LOGIC
);
END gp_dcfifo;
ARCHITECTURE SYN OF gp_dcfifo IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
COMPONENT dcfifo
GENERIC (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
rdclk : IN STD_LOGIC ;
wrfull : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
rdreq : IN STD_LOGIC
);
END COMPONENT;
BEGIN
wrfull <= sub_wire0;
q <= sub_wire1(DATA_WIDTH-1 DOWNTO 0);
rdempty <= sub_wire2;
dcfifo_component : dcfifo
GENERIC MAP (
intended_device_family => "Cyclone III",
lpm_numwords => FIFO_DEPTH,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => DATA_WIDTH,
lpm_widthu => integer(ceil(log2(real(FIFO_DEPTH)))),
overflow_checking => "ON",
rdsync_delaypipe => 4,
read_aclr_synch => "OFF",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 4
)
PORT MAP (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data,
rdreq => rdreq,
wrfull => sub_wire0,
q => sub_wire1,
rdempty => sub_wire2
);
END SYN; | gpl-3.0 | c7a84594b8a038a34a3a4373f3f392ba | 0.554158 | 3.088972 | false | false | false | false |
zatslogic/UDI_example | core_project/core_project.srcs/sources_1/ip/mult_16_x_16_res_32/mult_gen_v11_2/simulation/mult_gen_pkg_v11_2.vhd | 1 | 170,669 | -- $Id: mult_gen_pkg_v11_2.vhd,v 1.5 2011/03/17 13:01:31 gordono Exp $
--------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Master package for Multiplier core
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library xilinxcorelib;
use xilinxcorelib.bip_utils_pkg_v2_0.all;
package mult_gen_pkg_v11_2 is
-----------------------------------------------------------------------------
-- Constants and functions for use all over the core
-----------------------------------------------------------------------------
-- enable/disable debug output from functions
constant debug : boolean := false;
-- enable assert statements to debug progress through function hierarchy
constant fn_debug : boolean := false;
-- enable debug output for CCM functions
constant ccm_debug : boolean := false;
-- enumerated constants for c_mult_type
constant LUT : integer := 0;
constant EMBEDDED_MULT : integer := 1;
constant FIXED_CCM : integer := 2;
-- enumerated constants for c_optimize_goal
constant EMB_MULT_RESOURCES : integer := 0;
constant CORE_SPEED : integer := 1;
-- enumerated constants for the on/off pins e.g. CE, SCLR
constant MG_NO : integer := 0;
constant MG_YES : integer := 1;
-- enumerated constants for c_ccm_imp
constant DIST_MEM : integer := 0;
constant BRAM : integer := 1;
constant MULTS : integer := 2;
constant CSD : integer := 3;
constant PIPELINE_CFG_BREAKPT : integer := 1000000000;
constant MAX_PIPE_STAGES : integer := 30;
constant MAX_PRODUCT_WIDTH : integer := 128;
-- constants for the 3 possible hybrid configurations
constant BASE_MULT : integer := 0; -- no fabric required - just use the base DSP48 or Mult18x18 multiplier
constant ONE_MULT : integer := 1; -- fabric multiplier only needed on one side of the partial-product array
constant TWO_MULT : integer := 2; -- 2 fabric multipliers and a fabric adder needed around the embedded mult array
-- default generics for all core components etc.
constant DEF_C_VERBOSITY : integer := 0;
constant DEF_C_MODEL_TYPE : integer := 1;
constant DEF_C_XDEVICEFAMILY : string := "no_family";
constant DEF_C_A_WIDTH : integer := 18;
constant DEF_C_A_TYPE : integer := 0;
constant DEF_C_B_WIDTH : integer := 18;
constant DEF_C_B_TYPE : integer := 0;
constant DEF_C_OUT_HIGH : integer := 35;
constant DEF_C_OUT_LOW : integer := 0;
constant DEF_C_MULT_TYPE : integer := EMBEDDED_MULT;
constant DEF_C_OPTIMIZE_GOAL : integer := CORE_SPEED;
constant DEF_C_HAS_CE : integer := MG_NO;
constant DEF_C_HAS_SCLR : integer := MG_NO;
constant DEF_C_CE_OVERRIDES_SCLR : integer := MG_NO;
constant DEF_C_LATENCY : integer := 1;
constant DEF_C_CCM_IMP : integer := DIST_MEM;
constant DEF_C_B_VALUE : string := "111111111111111111";
constant DEF_C_HAS_ZERO_DETECT : integer := MG_NO;
constant DEF_C_ROUND_OUTPUT : integer := MG_NO;
constant DEF_C_ROUND_PT : integer := 0;
constant DSP_P_WIDTH : integer := 48;
-----------------------------------------------------------------------------
-- TYPES AND RECORDS
-----------------------------------------------------------------------------
-- record to define the widths of all the ports that may be required when building a block-based multiplier
type PORT_ASPECTS is record
a : integer; -- size of port A
b : integer; -- size of port B
m : integer; -- size of M register after mult
c : integer; -- size of port C
p : integer; -- size of port P
end record PORT_ASPECTS;
-- a record to store the width of the a and b operands and if they should be
-- swapped internally for the best mapping/resource use
type WIDTH_REC is record
a : integer;
b : integer;
a_type : integer;
b_type : integer;
swap : boolean;
end record WIDTH_REC;
type BLOCK_MULT_REC is record
a_width : integer; -- width of A operand on block mult
a_type : integer; -- datatype of A operand on block mult
b_width : integer; -- width of B operand on block mult
b_type : integer; -- datatype of B operand on block mult
end record BLOCK_MULT_REC;
type ONE_MULT_REC is record
a : integer; -- width of A input to fabric mult
b : integer; -- width of B input to fabric mult
a_type : integer; -- type of A input to fabric mult
b_type : integer; -- type of B input to fabric mult
out_width : integer; -- output width of fabric mult
bypass : integer; -- number of bypass bits
a_offset : integer; -- the offset on the A operand due to the mult configuration and # bypass bits
b_offset : integer; -- the offset on the B operand due to the mult configuration and # bypass bits
end record ONE_MULT_REC;
type TWO_MULT_REC is record
a_top : integer; -- width of A operand on top fabric mult
b_top : integer; -- width of B operand on top fabric mult
a_type_top : integer; -- type of A operand on top fabric mult
b_type_top : integer; -- type of B operand on top fabric mult
out_width_top : integer; -- output width of top fabric mult
a_side : integer; -- width of A operand on side fabric mult
b_side : integer; -- width of B operand on side fabric mult
a_type_side : integer; -- type of A operand on side fabric mult
b_type_side : integer; -- type of B operand on side fabric mult
out_width_side : integer; -- output width of side fabric mult
mult_bypass : integer; -- number of bypass bits from top fabric mult
add_bypass : integer; -- number of bypass bits from fabric adder
a_offset : integer; -- offset for A operand into block multiplier
b_offset : integer; -- offset for B operand into block multiplier
end record TWO_MULT_REC;
-- Record holding the resolved generics with any user misconfiguration or
-- invalid settings removed
type T_RESOLVED_GENERICS is record
R_A_WIDTH : integer;
R_A_TYPE : integer;
R_B_WIDTH : integer;
R_B_TYPE : integer;
R_OUT_HIGH : integer;
R_OUT_LOW : integer;
R_MULT_TYPE : integer;
R_OPT_GOAL : integer;
R_HAS_CE : integer;
R_HAS_SCLR : integer;
R_CE_OVERRIDES_SCLR : integer;
R_LATENCY : integer;
R_CCM_IMP : integer;
R_B_VALUE : string(1 to 64);
R_HAS_ZERO_DETECT : integer;
R_ROUND_OUTPUT : integer;
R_ROUND_PT : integer;
end record T_RESOLVED_GENERICS;
-- record to hold details of the DSP48 partial products so they can all be passed
-- back from a single function
type R_DSP_PP is record
a_pp : integer;
b_pp : integer;
extra_b_pp : integer;
end record R_DSP_PP;
-- record to hold the resource counts for use by the core's GUI
type R_MULT_RESOURCES is record
LUTs : integer;
DSPs : integer;
MULT18X18s : integer;
BRAMS : integer;
end record R_MULT_RESOURCES;
-----------------------------------------------------------------------------
-- FUNCTIONS
-----------------------------------------------------------------------------
-- purpose: validates the generics for the whole core, traps any bad combinations
function check_generics(c_xdevicefamily : string;
a_width, a_type, b_width, b_type : integer;
out_high, out_low : integer;
mult_type, opt_goal : integer;
has_ce, has_sclr, ce_overrides_sclr : integer;
latency, ccm_imp : integer;
b_value : string;
has_zero_detect, round_output, round_pt : integer) return T_RESOLVED_GENERICS;
-- purpose: catches the case where the xdevicefamily is Spartan-3E, 3A or 3ADSP and modifies the family info accordingly
-- There aren't any shared functions to do this, but the only piece of IP where this really matters is the multiplier
-- function modify_family(family_str : string) return string;
-- converts a std_logic bit to an integer representation
function sl_to_int(sl : std_logic) return integer;
-- reports the 'logarithm' (base 2) of an INTEGER
function mult_gen_log2(x : integer) return integer;
-- reports the 'logarithm' (base 2) of an INTEGER
-- the value it returns is constrained to the integer value
-- e.g. log(4) = 2, log(6) = 2, log(8) = 3, log(10) = 3
function mult_gen_log2d(x : integer) return integer;
-- purpose: calculates the a_pp and b_pp partial product configurations for
-- DSP48 multipliers, and deals with irregular structures used for some optimisations
function calc_dsp48_pps (family : string; op_width : WIDTH_REC) return R_DSP_PP;
-- purpose: calculates term number for LUT6 mult
function func_term_number(an : integer; bn : integer; s : integer) return integer;
-- purpose: calculates number of adder layers for LUT6 mult
function adder_layer_number_calc(width : integer) return integer;
-- purpose: works out for the multiplier specification provided what the fully-pipelined latency will be
-- This is the public interface to the core's latency function
function mult_gen_v11_2_calc_fully_pipelined_latency (family : string; a_width, a_type, b_width, b_type, mult_type, opt_goal, ccm_imp : integer; b_value : string) return integer;
-- purpose: works out for the multiplier specification provided what the fully-pipelined latency will be
-- Used when calling the multiplier from inside another core
function mult_gen_v11_2_calc_fully_pipelined_latency_internal (family : string; a_width, a_type, b_width, b_type, mult_type, opt_goal, ccm_imp : integer; b_value : string; standalone : integer := 1) return integer;
-- purpose: works out if the operands need to be swapped around and generates the correct widths for them
-- these values can then be used to control the wire swapping in the hardware generation
function get_true_widths(family : string; c_a_width, c_b_width, c_a_type, c_b_type : integer; port_size : PORT_ASPECTS) return WIDTH_REC;
-- purpose: works out how many partial products are required for the A operand (number of DSPs/MULT18X18s)
function calc_a_pp(family : string; op_width : WIDTH_REC) return integer;
-- purpose: works out how many partial products are required for the B operand (number of DSPs/MULT18X18s)
-- note that there is no family restriction here because MULT18X18, DSP48 and DSP48E
-- both have 18-bit B ports on the multiplier
function calc_b_pp(op_width : WIDTH_REC) return integer;
-- purpose: works out how many partial products are required for the A operand (number of DSPs/MULT18X18s)
function hybrid_calc_a_pp(family : string; op_width : WIDTH_REC) return integer;
-- purpose: works out how many partial products are required for the B operand (number of DSPs/MULT18X18s)
-- note that there is no family restriction here because MULT18X18, DSP48 and DSP48E
-- both have 18-bit B ports on the multiplier
function hybrid_calc_b_pp(family : string; op_width : WIDTH_REC) return integer;
-- purpose: works out which configuration of hybrid is required based on the input operand widths
-- and types and the multiplier primitive being used
function get_hybrid_configuration(family : string;
a_pp, b_pp : integer;
op_width : WIDTH_REC;
port_size : PORT_ASPECTS)return integer;
-- purpose: works out the operand widths and types for the block multiplier subcomponent
function get_block_mult_cfg (family : string;
a_pp, b_pp : integer;
op_width : WIDTH_REC;
hybrid_cfg : integer;
port_size : PORT_ASPECTS) return BLOCK_MULT_REC;
function get_one_mult_cfg(width : WIDTH_REC;
block_a_width, block_a_type, block_b_width, block_b_type : integer;
hybrid_cfg : integer;
port_size : PORT_ASPECTS) return ONE_MULT_REC;
-- purpose: works out the required operand widths of the fabric multiplier for the 'two mult' case
function get_two_mult_cfg(op_width : WIDTH_REC;
a_width, a_type, b_width, b_type : integer;
hybrid_cfg : integer) return TWO_MULT_REC;
-- purpose: works out fully-pipelined latency of a LUT multiplier
function fab_mult_full_pipe_lat(a_width, b_width : integer) return integer;
-- purpose: works out how many pipeline stages a particular configuration of DSPs or MULT18s needs
-- for max performance
function get_emb_mult_max_pipe_stages (family : string; a_pp, b_pp : integer) return integer;
-- purpose: works out the depth of the adder tree on the LUT multiplier(s)
-- to see what the maximum fully-pipelined latency will be
function get_LUT_max_pipe_stages (one_mult_cfg : ONE_MULT_REC; two_mult_cfg : TWO_MULT_REC; hybrid_configuration : integer) return integer;
-- purpose: checks to see if the constant has any zeros at the MSB (left) side of the string and
-- returns an integer to say how many consecutive zeros there are
-- These zeros don't need to go through the multiplier, so we could save some
-- logic in a few cases
-- If the constant is of signed type, we need to keep one of the leading zeros
-- If the constant is signed though, we can also check for leading ones and
-- trim them, stopping when we find "10" when searching from the left-hand side
function get_trimmed_leading_bits (b_value : string; b_type : integer; mult_type : integer) return integer;
-- purpose: counts the number of LSB zeros in the supplied constant STRING
-- If the bits are zero, we don't need to pass these bits into the multiplier
-- and we can just right-shift the output by these number of bits
function get_output_scaling (b_value : string; b_type : integer; mult_type : integer) return integer;
-- purpose: checks if the constant is all-zeros, in which case there is no point in creating logic!
function check_b_value_all_zeros (b_value : string; b_value_length : integer) return boolean;
-- -- purpose: returns the c_family equivalent of a string value
-- function t_device_family_to_c_family (family : string) return string;
-- -- purpose: returns the c_xdevicefamily equivalent of a string value
-- function t_device_family_to_c_xdevicefamily (family : string) return string;
-- purpose: checks if the constant string represents a power of two
function check_const_power_of_two (b_value : string; b_type, mult_type : integer) return boolean;
-------------------------------------------------------------------------------
-- Functions, constants, types imported from ccm_pkg.vhd
-------------------------------------------------------------------------------
constant C_DISTRIBUTED : integer := 0;
constant C_SP_BLOCK : integer := 1;
constant C_DP_BLOCK : integer := 2;
constant NEW_LINE : string(1 to 1) := (1 => LF); -- FOR ASSERTION REPORTS
constant A_MAX_WIDTH : integer := 64;
-- a_max_width is the only thing that needs to be modified in order to
-- support wider input busses
-- max number of partial products - add 2 as contingency for a_signed
constant MAX_NUM_PPS : integer := (A_MAX_WIDTH+2)/4;
function calc_reqd_b_value(b_value : string;
b_width : integer;
b_type : integer;
reqd_b_width : integer) return string;
function bitstorep_string(a_value : string;
a_type : integer) return integer;--natural;
function calc_shift_bits(b_value : string;
b_constant : integer) return integer;
function get_rom_addr_width(family : string; mem_type : integer) return integer;
function calc_a_input_width(operand_width, has_a_signed, rom_addr_width, b_constant : integer) return integer;
function calc_num_pps(a_width, rom_addr_width : integer) return integer;
-- TYPE for storing information about symmetric adders
type adder_info_type is record
a_input : integer;
b_input : integer;
a_width : integer;
b_width : integer;
b_type : integer;
b_pipe_regs : integer;
scale_by : integer;
drop_lsbs : integer;
out_width : integer;
pipe_stages : integer; -- new in V9.0!
row : integer; -- redundant
col : integer; -- redundant
height_limit : integer; -- redundant
height : integer; -- redundant
has_o : boolean; -- redundant
has_q : boolean; -- redundant
place_above_mem : boolean; -- redundant
end record;
function calc_adder_level(adder_num, max_add_levels : integer) return integer;
function calc_last_pp_input_width(operand_width, has_a_signed,
rom_addr_width, b_constant : integer) return integer;
function calc_pp_width(b_width : integer;
b_type : integer;
b_value : string;
b_constant : integer;
a_width : integer;
a_type : integer;
has_a_signed : integer;
last_pp : boolean;
full_prod : boolean) return integer;
function calc_last_pp_adder(num_pps : integer;
max_add_levels : integer;
num_adders : integer;
num_extra_adders : integer) return integer;
function calc_last_rom_contents(b_width : integer;
a_width : integer;
a_type : integer;
b_type : integer;
has_a_signed : integer;
rom_addr_width : integer;
rom_depth : integer;
rom_width : integer;
start_bit : integer;
b_value : string;
b_constant : integer;
num_rom_bits : integer;
number_of_pps : integer;
a_signed_extension : boolean) return bit_vector;
function calc_rom_contents(b_width : integer;
b_type : integer;
rom_addr_width : integer;
rom_depth : integer;
rom_width : integer;
start_bit : integer;
b_value : string;
num_rom_bits : integer) return bit_vector;
function calc_rom_start_bit(b_width : integer;
b_value : string;
b_constant : integer;
pp_width : integer;
a_type : integer;
rom_has_a_signed : integer;
mem_type : integer;
mem_addr_width : integer;
pipeline : integer;
num_adders : integer;
has_q : integer;
last_mem : boolean) return integer;
function calc_num_extra_adders(num_pps, max_num_pps : integer) return integer;
function get_mem_type(family : string;
mem_type : integer;
bram_addr_width : integer;
has_swapb : integer;
a_width : integer;
a_type : integer;
has_a_signed : integer;
b_constant : integer;
has_o : integer) return integer;
function bitsneededtorepresent(a_value : integer) return integer;--(a_value : natural) return natural;
function bitstorep_bv(a_value : bit_vector;
a_type : integer;
a_positive : boolean) return integer;--natural;
function mult_gen_max_of(i0, i1 : integer) return integer;
function multiply_bv(a, b : bit_vector; a_signed, b_signed : boolean) return bit_vector;
function natural_to_bit_vector(in_val : in integer; length : in integer) return bit_vector; --(in_val : in natural; length : in natural) return bit_vector;
function mult_gen_select_string(i0 : string; i1 : string; sel : boolean) return string;
function select_val(i0 : integer; i1 : integer; sel : boolean) return integer;
function select_val_int(i0 : integer; i1 : integer; sel : integer) return integer;
function mult_gen_str_to_bv(bitsin : string; nbits : integer) return bit_vector;
function mult_gen_bv_to_str(bitsin : bit_vector; nbits : integer) return string;
function slv_to_str(bitsin : std_logic_vector; nbits : integer) return string;
-----------------------------------------------------------------------------
-- Functions, types, constants from ccm_mem_utils
-----------------------------------------------------------------------------
-- Cannot have a dist mem > 'deepest_dist_mem' - have to use block mem
constant deepest_dist_mem : integer := 256;--natural := 256;
constant c_automatic : integer := -1;
function calc_depth(reqd_depth : integer; mem_type : integer) return integer;
-----------------------------------------------------------------------------
-- Functions to be translated by VTFC for use only in the GUI
-----------------------------------------------------------------------------
function calc_lut_mult_resources (c_a_width, c_b_width : integer) return integer;
function calc_hybrid_emb_mults (family : string; op_width : WIDTH_REC) return integer;
function calc_hybrid_luts (family : string; op_width : WIDTH_REC) return integer;
function calc_emb_mults (family : string; op_width : WIDTH_REC) return integer;
function calc_reqd_b_width (c_b_value : string; c_b_width, c_b_type : integer; reloadable : boolean) return integer;
function mult_gen_v11_2_luts (
family : string;
c_a_width : integer;
c_a_type : integer;
c_b_width : integer;
c_b_type : integer;
c_mult_type : integer;
c_optimize_goal : integer;
c_latency : integer;
c_ccm_imp : integer;
c_b_value : string)
return integer;
function mult_gen_v11_2_mults (
family : string;
c_a_width : integer;
c_a_type : integer;
c_b_width : integer;
c_b_type : integer;
c_mult_type : integer;
c_optimize_goal : integer;
c_latency : integer;
c_ccm_imp : integer;
c_b_value : string)
return integer;
function mult_gen_v11_2_brams (
family : string;
c_a_width : integer;
c_a_type : integer;
c_b_width : integer;
c_b_type : integer;
c_mult_type : integer;
c_optimize_goal : integer;
c_latency : integer;
c_ccm_imp : integer;
c_b_value : string)
return integer;
function mult_gen_v11_2_gui_resources (
family : string;
c_a_width : integer;
c_a_type : integer;
c_b_width : integer;
c_b_type : integer;
c_mult_type : integer;
c_optimize_goal : integer;
c_latency : integer;
c_ccm_imp : integer;
c_b_value : string)
return R_MULT_RESOURCES;
function get_port_sizes (family : string) return PORT_ASPECTS;
end package mult_gen_pkg_v11_2;
package body mult_gen_pkg_v11_2 is
-- purpose: validates the generics for the whole core, traps any bad combinations
function check_generics(c_xdevicefamily : string;
a_width, a_type, b_width, b_type : integer;
out_high, out_low : integer;
mult_type, opt_goal : integer;
has_ce, has_sclr, ce_overrides_sclr : integer;
latency, ccm_imp : integer;
b_value : string;
has_zero_detect, round_output, round_pt : integer) return T_RESOLVED_GENERICS is
variable r_generics : T_RESOLVED_GENERICS;
begin -- FUNCTION check_generics
-- Assign the incoming generics to the record elements
-- We will update them as required when the checks are performed
-- before the record is returned
r_generics.R_A_WIDTH := a_width;
r_generics.R_A_TYPE := a_type;
r_generics.R_B_WIDTH := b_width;
r_generics.R_B_TYPE := b_type;
r_generics.R_OUT_HIGH := out_high;
r_generics.R_OUT_LOW := out_low;
r_generics.R_MULT_TYPE := mult_type;
r_generics.R_OPT_GOAL := opt_goal;
r_generics.R_HAS_CE := has_ce;
r_generics.R_HAS_SCLR := has_sclr;
r_generics.R_CE_OVERRIDES_SCLR := ce_overrides_sclr;
r_generics.R_LATENCY := latency;
r_generics.R_CCM_IMP := ccm_imp;
-- This syntax ensures that the string for the constant
-- will be represented as (1 to N) throughout the core
-- This is necessary for VTFC support
r_generics.R_B_VALUE(1 to b_value'length) := b_value;
r_generics.R_HAS_ZERO_DETECT := has_zero_detect;
r_generics.R_ROUND_OUTPUT := round_output;
r_generics.R_ROUND_PT := round_pt;
-- check that the A and B types are valid
assert r_generics.R_A_TYPE = C_SIGNED or r_generics.R_A_TYPE = C_UNSIGNED report "ERROR: mult_gen: c_a_type should be 0 (signed) or 1 (unsigned)" severity failure;
assert r_generics.R_B_TYPE = C_SIGNED or r_generics.R_B_TYPE = C_UNSIGNED report "ERROR: mult_gen: c_b_type should be 0 (signed) or 1 (unsigned)" severity failure;
-- check that the port widths are valid, based on the operand types and the multiplier type
-- assert r_generics.R_A_WIDTH+r_generics.R_A_TYPE >= 2 and r_generics.R_A_WIDTH < 65 report "ERROR: mult_gen: c_a_width must be in the range 2->64 for signed data and 1->64 for unsigned data" severity failure;
-- assert r_generics.R_B_WIDTH+r_generics.R_B_TYPE >= 2 and r_generics.R_B_WIDTH < 65 report "ERROR: mult_gen: c_b_width must be in the range 2->64 for signed data and 1->64 for unsigned data" severity failure;
-- check that MULT_TYPE is valid
assert r_generics.R_MULT_TYPE = LUT or r_generics.R_MULT_TYPE = EMBEDDED_MULT or r_generics.R_MULT_TYPE = FIXED_CCM report "ERROR: mult_gen: c_mult_type must be 0, 1 or 2" severity failure;
-- check that opt_goal is valid
if r_generics.R_MULT_TYPE = EMBEDDED_MULT then
if r_generics.R_OPT_GOAL /= EMB_MULT_RESOURCES and r_generics.R_OPT_GOAL /= CORE_SPEED then
report "WARNING: mult_gen: c_optimize_goal must be 0 (optimize for embedded mult resources) or 1 (optimize for core speed). Optimizing for speed..." severity warning;
r_generics.R_OPT_GOAL := CORE_SPEED;
end if;
else
-- don't care - generic doesn't apply to CCM or LUT mult
null;
end if;
-- check has_ce, has_sclr, ce_overrides_sclr
assert r_generics.R_HAS_CE = MG_NO or r_generics.R_HAS_CE = MG_YES report "ERROR: mult_gen: c_has_ce must be 0 or 1" severity failure;
if r_generics.R_HAS_CE /= 0 and r_generics.R_LATENCY = 0 then
report "WARNING: mult_gen: c_has_ce is set to 1, but no clock enable is required as the core latency is zero. Setting c_has_ce to 0 internally" severity warning;
r_generics.R_HAS_CE := 0;
end if;
assert r_generics.R_HAS_SCLR = MG_NO or r_generics.R_HAS_SCLR = MG_YES report "ERROR: mult_gen: c_has_sclr must be 0 or 1" severity failure;
if r_generics.R_HAS_SCLR /= 0 and r_generics.R_LATENCY = 0 then
report "WARNING: mult_gen: c_has_sclr is set to 1, but no synchronous clear is required as the core latency is zero. Setting c_has_sclr to 0 internally" severity warning;
r_generics.R_HAS_SCLR := 0;
end if;
if r_generics.R_HAS_SCLR = MG_YES and r_generics.R_HAS_ZERO_DETECT = MG_YES then
report "ERROR: mult_gen: c_has_sclr must be set to 0 if c_has_zero_detect is to be used" severity failure;
end if;
assert r_generics.R_CE_OVERRIDES_SCLR = MG_NO or r_generics.R_CE_OVERRIDES_SCLR = MG_YES report "ERROR: mult_gen: c_ce_overrides_sclr must be 0 or 1" severity failure;
-- check latency is valid, and account for auto-pipelining
if r_generics.R_LATENCY = -1 then
-- let the core decide on the optimum number of pipeline stages
r_generics.R_LATENCY := mult_gen_v11_2_calc_fully_pipelined_latency(C_XDEVICEFAMILY, r_generics.R_A_WIDTH, r_generics.R_A_TYPE, r_generics.R_B_WIDTH, r_generics.R_B_TYPE, r_generics.R_MULT_TYPE, r_generics.R_OPT_GOAL, r_generics.R_CCM_IMP, r_generics.R_B_VALUE);
assert not(debug) report "INFO: mult_gen: The core calculated that " & integer'image(r_generics.R_LATENCY) & " pipeline stages are required for this multiplier" severity note;
else
-- just check that the supplied latency value is in the supported range(s)
assert (r_generics.R_LATENCY >= 0 and r_generics.R_LATENCY <= MAX_PIPE_STAGES) or r_generics.R_LATENCY >= PIPELINE_CFG_BREAKPT report "ERROR: mult_gen: C_LATENCY must be > 0 and < " & integer'image(MAX_PIPE_STAGES) & " (or >= " & integer'image(PIPELINE_CFG_BREAKPT) & " for bit pattern mode)" severity failure;
end if;
-- check ccm_imp is valid - depends on MULT_TYPE
if r_generics.R_MULT_TYPE = FIXED_CCM then
assert r_generics.R_CCM_IMP = DIST_MEM or r_generics.R_CCM_IMP = BRAM or r_generics.R_CCM_IMP = MULTS report "ERROR: mult_gen: c_ccm_imp must be 0, 1 or 2" severity failure;
else
-- we don't care - it's a parallel multiplier - set it to zero
r_generics.R_CCM_IMP := 0;
null;
end if;
-- check b_value is not a null string if it's a CCM
if r_generics.R_MULT_TYPE = FIXED_CCM then
assert r_generics.R_B_VALUE'length /= 0 report "ERROR: mult_gen: c_b_value string length is zero" severity failure;
else
-- we don't care, as b_value's not used
r_generics.R_B_VALUE(1 to 64) := (others => 'Z');
null;
end if;
if r_generics.R_MULT_TYPE = LUT or r_generics.R_MULT_TYPE = EMBEDDED_MULT then
assert r_generics.R_HAS_ZERO_DETECT = MG_NO or r_generics.R_HAS_ZERO_DETECT = MG_YES report "ERROR: mult_gen: c_has_zero_detect must be 0 or 1" severity failure;
else
assert r_generics.R_HAS_ZERO_DETECT = MG_NO report "WARNING: mult_gen: Zero Detection is only supported for parallel multipliers" severity warning;
r_generics.R_HAS_ZERO_DETECT := 0;
end if;
if r_generics.R_MULT_TYPE = EMBEDDED_MULT and (supports_dsp48(C_XDEVICEFAMILY) = 1 or supports_dsp48e(C_XDEVICEFAMILY) > 0) then
assert r_generics.R_ROUND_OUTPUT = MG_NO or r_generics.R_ROUND_OUTPUT = MG_YES report "ERROR: mult_gen: c_round_output must be 0 or 1" severity failure;
if supports_dsp48(C_XDEVICEFAMILY) = 1 and r_generics.R_ROUND_OUTPUT = MG_YES then
assert r_generics.R_A_WIDTH+r_generics.R_A_TYPE <= 18 and r_generics.R_B_WIDTH+r_generics.R_B_TYPE <= 18 report "ERROR: mult_gen: Symmetric rounding is only supported for a single DSP48 in Virtex-4" severity failure;
elsif supports_dsp48e(C_XDEVICEFAMILY) > 0 and r_generics.R_ROUND_OUTPUT = MG_YES then
assert r_generics.R_A_WIDTH+r_generics.R_A_TYPE <= 25 and r_generics.R_B_WIDTH+r_generics.R_B_TYPE <= 18 report "ERROR: mult_gen: Symmetric rounding is only supported for a single DSP48E in Virtex-5" severity failure;
end if;
else
-- don't allow rounding for other multipliers - expensive
assert r_generics.R_ROUND_OUTPUT = MG_NO report "WARNING: mult_gen: Rounding is only supported for Virtex-4 and Virtex-5 DSP48(E)-based multipliers" severity warning;
r_generics.R_ROUND_OUTPUT := 0;
end if;
return r_generics;
end function check_generics;
function sl_to_int(sl : std_logic) return integer is
begin -- FUNCTION sl_to_int
if sl = '1' then
return 1;
else
return 0;
end if;
end function sl_to_int;
function mult_gen_log2(x : integer) return integer is
variable y : integer;
variable two_to_the_y : integer;
begin
y := 0;
two_to_the_y := 1;
while (two_to_the_y < x) loop
y := y+1;
two_to_the_y := two_to_the_y * 2;
end loop;
return y;
end mult_gen_log2;
function mult_gen_log2d(x : integer) return integer is
variable y : integer;
variable two_to_the_y : integer;
begin
y := 0;
two_to_the_y := 1;
while (two_to_the_y < x) loop
y := y+1;
two_to_the_y := two_to_the_y * 2;
end loop;
if two_to_the_y > x then
y := y - 1;
end if;
return y;
end mult_gen_log2d;
-- purpose: figures out the number of PPs in each dimension of the multiplier array
-- may require an extra PP for optimised DSP48E-based implementations
function calc_dsp48_pps (family : string; op_width : WIDTH_REC) return R_DSP_PP is
variable pps : R_DSP_PP := (a_pp => 0, b_pp => 0, extra_b_pp => 0);
begin -- function calc_pps
if supports_dsp48e(family) = 0 then
-- no asymmetric multiplier...
pps.a_pp := calc_a_pp(family, op_width);
pps.b_pp := calc_b_pp(op_width);
pps.extra_b_pp := 0;
else
-- scope for some optimisations to reduce DSP count
pps.a_pp := calc_a_pp(family, op_width);
if (op_width.a > 42 and op_width.a <= 59 and op_width.b > 52 and op_width.b <= 59)
or (op_width.a > 25 and op_width.a <= 42 and op_width.b > 35 and op_width.b <= 42)
or (op_width.a > 25 and op_width.a <= 42 and op_width.b > 52 and op_width.b <= 59) then
-- can perform this multiply in only 10 DSPs, rather than 12.
-- subtract one row from B, and one to the extra_b_pp element
-- this should yield a_pp = 3, b_pp = 3, extra_b_pp = 1
pps.b_pp := calc_b_pp(op_width) - 1;
pps.extra_b_pp := 1;
else
pps.b_pp := calc_b_pp(op_width);
pps.extra_b_pp := 0;
end if;
end if;
return pps;
end function calc_dsp48_pps;
function func_term_number(an : integer; bn : integer; s : integer) return integer is
variable mn : integer;
begin
mn := bn;
if (an = bn) then
return 2*mn+s-1;
else
return 2*mn+s;
end if;
end function func_term_number;
function adder_layer_number_calc(width : integer) return integer is
variable layer_counter : integer := 0;
variable adder_counter : integer;
variable input_counter : integer;
begin
input_counter := width;
while input_counter > 1 loop
layer_counter := layer_counter + 1;
adder_counter := input_counter/3;
if adder_counter = 0 and input_counter = 2 then -- Final two-input counter
adder_counter := 1;
input_counter := 1;
else
input_counter := input_counter - adder_counter*3; -- count the unused inputs
input_counter := input_counter + adder_counter; -- add the outputs from the adders
end if;
-- report "ADDER TREE: Adder number is " & integer'image(adder_counter) &", output = "&integer'image(input_counter) &" in layer "& integer'image(layer_counter);
end loop;
-- report "Layer number is " & integer'image(layer_counter) severity note;
return layer_counter;
end function adder_layer_number_calc;
function mult_gen_v11_2_calc_fully_pipelined_latency (family : string;
a_width, a_type, b_width, b_type, mult_type, opt_goal, ccm_imp : integer;
b_value : string) return integer is
begin
return mult_gen_v11_2_calc_fully_pipelined_latency_internal(family, a_width, a_type, b_width, b_type, mult_type, opt_goal, ccm_imp, b_value, 1);
end function mult_gen_v11_2_calc_fully_pipelined_latency;
-- If 'standalone' is set to 1, the latency of a Spartan-6 multiplier will be
-- 2 cycles. If 'standalone' = 0, we assume that the adder will be used, so
-- the latency will be 3 cycles
function mult_gen_v11_2_calc_fully_pipelined_latency_internal (family : string;
a_width, a_type, b_width, b_type, mult_type, opt_goal, ccm_imp : integer;
b_value : string;
standalone : integer := 1) return integer is
-- General use variables
variable latency : integer := 0;
variable a_pp : integer := 0;
variable b_pp : integer := 0;
variable num_pp : integer := 0;
variable dsp_pps : R_DSP_PP := (a_pp => 0, b_pp => 0, extra_b_pp => 0);
variable op_width : WIDTH_REC;
variable port_size : PORT_ASPECTS := get_port_sizes(family);
-- variables for the CCM calculations
variable rom_latency : integer := 0;
variable rom_addr_width : integer := 0;
variable a_input_width : integer := 0;
variable num_pps : integer := 0;
variable const_power_of_two : boolean := false;
variable const_is_zero : boolean := false;
-- variables for the hybrid configurations
variable widths : WIDTH_REC;
variable block_mult_pipeline : integer;
variable block_mult_output_pipeline : integer;
variable hybrid_cfg : integer;
variable block_mult_cfg : BLOCK_MULT_REC;
variable one_mult_cfg : ONE_MULT_REC;
variable two_mult_cfg : TWO_MULT_REC;
variable top_mult_a_width : integer := 0;
variable top_mult_b_width : integer := 0;
variable side_mult_a_width : integer := 0;
variable side_mult_b_width : integer := 0;
variable deepest_lut_mult_tree : integer := 0;
variable deepest_pipeline : integer := 0;
variable adder_latency : integer := 0;
variable fab_prereg : integer := 0;
variable Creg : integer := 0;
-- variables for the embedded mult CCM
variable reqd_b_value : string(1 to calc_reqd_b_width(b_value,b_width, b_type, false));
variable trimmed_msbs : integer := 0;
variable trimmed_lsbs : integer := 0;
-- variables for LUT6 mult (area optimised)
variable sign_correction : integer := 0;
variable a_digit_number, b_digit_number : integer := 0;
begin -- FUNCTION mult_gen_v11_2_calc_fully_pipelined_latency_internal
if mult_type = FIXED_CCM then
-- check to see if the constant is exactly a (positive) power of 2
-- use this to set up the latency of the fixed CCM later on
trimmed_msbs := get_trimmed_leading_bits(b_value, b_type, mult_type);
trimmed_lsbs := calc_shift_bits(b_value, 1);
const_power_of_two := check_const_power_of_two(b_value, b_type, mult_type);
-- b_width should represent the length of the b_value string - required
-- for VTFC support, as 'length cannot be used
const_is_zero := check_b_value_all_zeros(b_value, b_width);
end if;
-- swap the operands around to get the best operand size for each PORT
-- Any invalid families will be caught in this routine
op_width := get_true_widths(family, a_width, b_width, a_type, b_type, port_size);
case mult_type is
when LUT =>
if opt_goal = CORE_SPEED then
if get_min(a_width, b_width) = 1 then
latency := 1;
else
latency := mult_gen_log2(get_min(a_width, b_width));
end if;
else
if a_type = 1 and b_type = 1 then
-- unsigned
sign_correction := 0;
else
sign_correction := 1;
end if;
a_digit_number := (mult_gen_max_of(a_width, b_width)+2)/3;
b_digit_number := (get_min(a_width, b_width)+2)/3;
latency := adder_layer_number_calc(func_term_number(a_digit_number, b_digit_number, sign_correction)) + 1;
end if;
when EMBEDDED_MULT =>
case opt_goal is
when CORE_SPEED =>
-- To account for possible extra DSP in V5 optimised cases
dsp_pps := calc_dsp48_pps(family, op_width);
num_pp := (dsp_pps.a_pp * dsp_pps.b_pp) + dsp_pps.extra_b_pp;
a_pp := dsp_pps.a_pp;
b_pp := dsp_pps.b_pp;
if supports_dsp48(family) = 1 or supports_dsp48e(family) > 0 then
-- latency is determined by # DSP48(E)s used - call a_pp and b_pp calculation functions
latency := num_pp + 2; -- A/Breg + Mreg in first DSP + Pregs in all DSPs above it in the column
elsif supports_dsp48a(family) > 0 then
-- There's no simple formula to work out what the latency will
-- be based on the number of DSPs. It depends how many wireshifts we need in
-- the fabric (i.e. how many times the C port needs to be used)
if a_pp = 1 and b_pp = 1 then
if supports_dsp48a1(family) > 0 and standalone = 1 then
-- 2-cycle mult in Spartan-6
latency := 2;
else
latency := 3;
end if;
elsif a_pp = 2 and b_pp = 1 then
latency := 5;
elsif a_pp = 3 and b_pp = 1 then
latency := 7;
elsif a_pp = 4 and b_pp = 1 then
latency := 9;
elsif a_pp = 2 and b_pp = 2 then
latency := 8;
elsif a_pp = 3 and b_pp = 2 then
latency := 11;
elsif a_pp = 3 and b_pp = 3 then
latency := 15;
elsif a_pp = 4 and b_pp = 2 then
latency := 14;
elsif a_pp = 4 and b_pp = 3 then
latency := 19;
elsif a_pp = 4 and b_pp = 4 then
latency := 24;
end if;
elsif supports_mult18x18s(family) = 1 or supports_mult18x18sio(family) = 1 then
-- latency is determined by depth of adder tree required, which is determined by the number of Mult18x18s required
-- Add two for the register stage and fabric register in V2 and S3 multipliers, add 3 for the
-- Mult18x18SIO in S3E - 2 for the multiplier and 1 for the post-output fabric
latency := mult_gen_log2(num_pp) + 2 + (boolean'pos(supports_mult18x18sio(family) = 1));
else
report "ERROR: invalid family caught in EMB_MULT/CORE_SPEED in mult_gen_v11_2_calc_fully_pipelined_latency"
severity failure;
end if;
when EMB_MULT_RESOURCES =>
-- fully-pipelined latency depends on if the fabric portion or the
-- embedded mult portion is deeper in terms of registers
-- Account for operand swapping
if a_width > b_width then
widths.a := a_width;
widths.a_type := a_type;
widths.b := b_width;
widths.b_type := b_type;
op_width.a := a_width;
op_width.a_type := a_type;
op_width.b := b_width;
op_width.b_type := b_type;
else
widths.a := b_width;
widths.a_type := b_type;
widths.b := a_width;
widths.b_type := a_type;
op_width.a := b_width;
op_width.a_type := b_type;
op_width.b := a_width;
op_width.b_type := a_type;
end if;
assert not(debug) report "widths.a " & integer'image(widths.a) severity note;
assert not(debug) report "widths.a_type " & integer'image(widths.a_type) severity note;
assert not(debug) report "widths.b " & integer'image(widths.b) severity note;
assert not(debug) report "widths.b_type " & integer'image(widths.b_type) severity note;
if supports_dsp48(family) = 1 or supports_dsp48e(family) > 0 or supports_dsp48a(family) > 0 then
-- New approach
-- Consider paths to the adder in the DSP48x
-- Areg/Breg + Mreg gives 2 cycles of latency
block_mult_pipeline := 2;
-- The pipeline after the DSP48x adder is defined by the number
-- of DSPs used (number of registers in the P cascade)
a_pp := hybrid_calc_a_pp(family, op_width);
b_pp := hybrid_calc_b_pp(family, op_width);
block_mult_output_pipeline := a_pp * b_pp;
assert not(debug) report "a_pp " & integer'image(a_pp) severity note;
assert not(debug) report "b_pp " & integer'image(b_pp) severity note;
assert not(debug) report "block_mult_output_pipeline " & integer'image(block_mult_output_pipeline) severity note;
assert not(debug) report "block_mult_output_pipeline is " & integer'image(block_mult_output_pipeline) severity note;
hybrid_cfg := get_hybrid_configuration(family, a_pp, b_pp, widths, port_size);
block_mult_cfg := get_block_mult_cfg (family, a_pp, b_pp, widths, hybrid_cfg, port_size);
assert not(debug) report "hybrid_cfg is " & integer'image(hybrid_cfg) severity note;
assert not(debug) report "block_mult_cfg.a_width " & integer'image(block_mult_cfg.a_width) severity note;
assert not(debug) report "block_mult_cfg.a_type " & integer'image(block_mult_cfg.a_type) severity note;
assert not(debug) report "block_mult_cfg.b_width " & integer'image(block_mult_cfg.b_width) severity note;
assert not(debug) report "block_mult_cfg.b_type " & integer'image(block_mult_cfg.b_type) severity note;
if hybrid_cfg = ONE_MULT then
one_mult_cfg := get_one_mult_cfg(widths,
block_mult_cfg.a_width, block_mult_cfg.a_type, block_mult_cfg.b_width, block_mult_cfg.b_type,
hybrid_cfg, port_size);
top_mult_a_width := one_mult_cfg.a;
top_mult_b_width := one_mult_cfg.b;
side_mult_a_width := 0;
side_mult_b_width := 0;
assert not(debug) report "top_mult_a_width = " & integer'image(top_mult_a_width) severity note;
assert not(debug) report "top_mult_b_width = " & integer'image(top_mult_b_width) severity note;
assert not(debug) report "side_mult_a_width = " & integer'image(side_mult_a_width) severity note;
assert not(debug) report "side_mult_b_width = " & integer'image(side_mult_b_width) severity note;
deepest_lut_mult_tree := fab_mult_full_pipe_lat(top_mult_a_width, top_mult_b_width);
elsif hybrid_cfg = TWO_MULT then
two_mult_cfg := get_two_mult_cfg(widths, block_mult_cfg.a_width, block_mult_cfg.a_type, block_mult_cfg.b_width, block_mult_cfg.b_type, hybrid_cfg);
top_mult_a_width := two_mult_cfg.a_top;
top_mult_b_width := two_mult_cfg.b_top;
side_mult_a_width := two_mult_cfg.a_side;
side_mult_b_width := two_mult_cfg.b_side;
assert not(debug) report "top_mult_a_width = " & integer'image(top_mult_a_width) severity note;
assert not(debug) report "top_mult_b_width = " & integer'image(top_mult_b_width) severity note;
assert not(debug) report "side_mult_a_width = " & integer'image(side_mult_a_width) severity note;
assert not(debug) report "side_mult_b_width = " & integer'image(side_mult_b_width) severity note;
deepest_lut_mult_tree := mult_gen_max_of(fab_mult_full_pipe_lat(top_mult_a_width, top_mult_b_width), fab_mult_full_pipe_lat(side_mult_a_width, side_mult_b_width));
end if;
if hybrid_cfg = BASE_MULT then
adder_latency := 0;
Creg := 0;
elsif hybrid_cfg = ONE_MULT then
adder_latency := 0;
Creg := 1;
elsif hybrid_cfg = TWO_MULT then
adder_latency := 1;
Creg := 1;
end if;
assert not(debug) report "deepest_lut_mult_tree is " & integer'image(deepest_lut_mult_tree) severity note;
-- Work out the deepest path to the adder in the LS DSP48
deepest_pipeline := mult_gen_max_of(block_mult_pipeline, (deepest_lut_mult_tree + adder_latency + Creg));
-- Don't actually need the pre-register for best performance...
fab_prereg := 0;
latency := fab_prereg + deepest_pipeline + block_mult_output_pipeline;
elsif supports_mult18x18s(family) = 1 or supports_mult18x18sio(family) = 1 then
-- calc number of emb mults
-- calc_tree_latency via mult_gen_log2 routine
-- if V2 or S3, add 2 to tree lat
-- if S3E, add 3 to tree lat
-- get configuration of hybrid
-- get widths of lut mults
-- get max depth of the lut mults, if they are required
-- work out max depth from lut mults and the embedded mult
-- add in any adder latency to this final value
a_pp := hybrid_calc_a_pp(family, op_width);
b_pp := hybrid_calc_b_pp(family, op_width);
num_pp := a_pp * b_pp;
-- work out the latency of the adder tree based on the number
-- on embedded multipliers used, and then add the latency of
-- the embedded multipliers themselves for best performance
if supports_mult18x18s(family) = 1 then
block_mult_pipeline := mult_gen_log2(num_pp) + 2;
elsif supports_mult18x18sio(family) = 1 then
block_mult_pipeline := mult_gen_log2(num_pp) + 3;
end if;
hybrid_cfg := get_hybrid_configuration(family, a_pp, b_pp, widths, port_size);
block_mult_cfg := get_block_mult_cfg (family, a_pp, b_pp, widths, hybrid_cfg, port_size);
if hybrid_cfg = ONE_MULT then
one_mult_cfg := get_one_mult_cfg(widths,
block_mult_cfg.a_width, block_mult_cfg.a_type, block_mult_cfg.b_width, block_mult_cfg.b_type,
hybrid_cfg, port_size);
top_mult_a_width := one_mult_cfg.a;
top_mult_b_width := one_mult_cfg.b;
side_mult_a_width := 0;
side_mult_b_width := 0;
deepest_lut_mult_tree := fab_mult_full_pipe_lat(top_mult_a_width, top_mult_b_width);
elsif hybrid_cfg = TWO_MULT then
two_mult_cfg := get_two_mult_cfg(widths, block_mult_cfg.a_width, block_mult_cfg.a_type, block_mult_cfg.b_width, block_mult_cfg.b_type, hybrid_cfg);
top_mult_a_width := two_mult_cfg.a_top;
top_mult_b_width := two_mult_cfg.b_top;
side_mult_a_width := two_mult_cfg.a_side;
side_mult_b_width := two_mult_cfg.b_side;
deepest_lut_mult_tree := mult_gen_max_of(fab_mult_full_pipe_lat(top_mult_a_width, top_mult_b_width), fab_mult_full_pipe_lat(side_mult_a_width, side_mult_b_width));
end if;
if hybrid_cfg = BASE_MULT then
adder_latency := 0;
elsif hybrid_cfg = ONE_MULT then
adder_latency := 0;
elsif hybrid_cfg = TWO_MULT then
adder_latency := 1;
end if;
deepest_pipeline := mult_gen_max_of(block_mult_pipeline, (deepest_lut_mult_tree + adder_latency));
-- Add one cycle of latency for the register on the final adder
-- which sums all the partial products together
latency := deepest_pipeline + 1;
else
report "ERROR: invalid family caught in EMB_MULT/EMB_MULT_RESOURCES in mult_gen_v11_2_calc_fully_pipelined_latency"
severity failure;
end if;
when others => null;
end case;
when FIXED_CCM =>
if const_power_of_two or const_is_zero then
-- can perform the multiply just by bit-shifting - no logic required
-- or just generate constant zeros at the output
latency := 0;
else
case ccm_imp is
when DIST_MEM =>
rom_latency := 1;
if supports_lut6(family) = 1 then
rom_addr_width := 6;
else
rom_addr_width := 4;
end if;
a_input_width := calc_a_input_width(a_width, 0, rom_addr_width, 0);
num_pps := calc_num_pps(a_input_width, rom_addr_width);
-- log2 function will return 0 if 0 is input, which works for this application
latency := mult_gen_log2((num_pps * boolean'pos(num_pps > 1))) + rom_latency;
when BRAM =>
if supports_ramb18(family) > 0 or supports_ramb16bwer(family) > 0 or supports_ramb16(family) = 1 then
-- add 1 cycle for speed-up register
rom_latency := 3;
else
rom_latency := 2;
end if;
-- Fixed width for all supported families (18K BRAM)
rom_addr_width := 9;
a_input_width := calc_a_input_width(a_width, 0, rom_addr_width, 0);
num_pps := calc_num_pps(a_input_width, rom_addr_width);
-- log2 function will return 0 if 0 is input, which works for this application
latency := mult_gen_log2((num_pps * boolean'pos(num_pps > 1))) + rom_latency;
when MULTS =>
reqd_b_value := calc_reqd_b_value(b_value, b_width, b_type, calc_reqd_b_width(b_value,b_width, b_type, false));
-- modify op_width.b to reflect the number of bits from the
-- constant value that actually need to go through the multiplier
trimmed_lsbs := get_output_scaling(b_value, b_type, mult_type);
trimmed_msbs := get_trimmed_leading_bits(b_value, b_type, mult_type);
-- Completely reset the op_width record contents
op_width := get_true_widths(family, a_width, (reqd_b_value'length - (trimmed_lsbs + trimmed_msbs)), a_type, b_type, port_size);
-- calc_dsp48_pps will work for mult18x18-based families too!
dsp_pps := calc_dsp48_pps(family, op_width);
num_pp := (dsp_pps.a_pp * dsp_pps.b_pp) + dsp_pps.extra_b_pp;
a_pp := dsp_pps.a_pp;
b_pp := dsp_pps.b_pp;
if supports_dsp48(family) = 1 or supports_dsp48e(family) > 0 then
-- latency is determined by # DSP48(E)s used - call a_pp and b_pp calculation functions
latency := num_pp + 2; -- A/Breg + Mreg in first DSP + Pregs in all DSPs above it in the column
elsif supports_dsp48a(family) > 0 then
-- There's no simple formula to work out what the latency will
-- be based on the number of DSPs. It depends how many wireshifts we need in
-- the fabric (i.e. how many times the C port needs to be used)
if a_pp = 1 and b_pp = 1 then
if supports_dsp48a1(family) > 0 and standalone = 1 then
-- 2-cycle mult in Spartan-6
latency := 2;
else
latency := 3;
end if;
elsif a_pp = 2 and b_pp = 1 then
latency := 5;
elsif a_pp = 3 and b_pp = 1 then
latency := 7;
elsif a_pp = 4 and b_pp = 1 then
latency := 9;
elsif a_pp = 2 and b_pp = 2 then
latency := 8;
elsif a_pp = 3 and b_pp = 2 then
latency := 11;
elsif a_pp = 3 and b_pp = 3 then
latency := 15;
elsif a_pp = 4 and b_pp = 2 then
latency := 14;
elsif a_pp = 4 and b_pp = 3 then
latency := 19;
elsif a_pp = 4 and b_pp = 4 then
latency := 24;
end if;
elsif supports_mult18x18s(family) = 1 or supports_mult18x18sio(family) = 1 then
-- latency is determined by depth of adder tree required, which is determined by the number of Mult18x18s required
-- Add one for the register stage in V2 and S3 multipliers, add 3 for the Mult18x18SIO in S3E - 2 for the multiplier and 1 for the post-output fabric
latency := mult_gen_log2(num_pp) + 2 + (boolean'pos(supports_mult18x18sio(family) = 1));
else
report "ERROR: invalid family caught in FIXED_CCM/MULTS in mult_gen_v11_2_calc_fully_pipelined_latency"
severity failure;
end if;
when CSD =>
report "WARNING: The core cannot calculate the fully-pipelined latency - check XST log (if available)" severity warning;
latency := 0;
when others =>
report "ERROR: invalid c_ccm_imp caught in mult_gen_v11_2_calc_fully_pipelined_latency" severity failure;
end case;
end if;
when others =>
report "ERROR: invalid mult_type caught in mult_gen_v11_2_calc_fully_pipelined_latency" severity failure;
end case;
return latency;
end function mult_gen_v11_2_calc_fully_pipelined_latency_internal;
-- purpose: works out if the operands need to be swapped around and generates the correct widths for them
-- these values can then be used to control the wire swapping in the hardware generation
function get_true_widths(family : string;
c_a_width, c_b_width, c_a_type, c_b_type : integer;
port_size : PORT_ASPECTS) return WIDTH_REC is
variable ret : WIDTH_REC := (a => 0, b => 0, a_type => 0, b_type => 0, swap => false);
constant full_a_width : integer := c_a_width+c_a_type;
constant full_b_width : integer := c_b_width+c_b_type;
variable a_pp_1, a_pp_2 : integer := 0;
variable b_pp_1, b_pp_2 : integer := 0;
variable res_1, res_2 : integer := 0;
variable widths : WIDTH_REC := (a => 0, b => 0, a_type => 0, b_type => 0, swap => false);
begin -- FUNCTION get_true_widths
assert not(fn_debug) report "entered get_true_widths" severity note;
if supports_dsp48(family) = 1 or supports_mult18x18s(family) = 1 or supports_mult18x18sio(family) = 1 or supports_dsp48a(family) > 0 then
-- All the families with 18x18 multipliers, be they mult18s or DSP primitives
if full_a_width >= full_b_width then
-- no swapping required
ret.swap := false;
if c_a_type = C_SIGNED then
ret.a := c_a_width;
elsif c_a_type = C_UNSIGNED then
ret.a := c_a_width+1;
end if;
if c_b_type = C_SIGNED then
ret.b := c_b_width;
elsif c_b_type = C_UNSIGNED then
ret.b := c_b_width+1;
end if;
ret.a_type := c_a_type;
ret.b_type := c_b_type;
else
-- need to swap the operands around
ret.swap := true;
if c_b_type = 0 then
ret.a := c_b_width;
elsif c_b_type = 1 then
ret.a := c_b_width+1;
end if;
if c_a_type = C_SIGNED then
ret.b := c_a_width;
elsif c_a_type = C_UNSIGNED then
ret.b := c_a_width+1;
end if;
ret.a_type := c_b_type;
ret.b_type := c_a_type;
end if;
elsif supports_dsp48e(family) > 0 then
-- Harder to work out when we need to swap the operands over here
-- because of the asymmetric multiplier - more efficient for some widths not to swap the operands!
-- Check to see if the operand sizes as they are supplied to the core
-- fit one of the optimal array configurations - if not, we want to
-- swap A and B over since that will fit one of the patterns
-- i.e. 42x64 and 64x42 will both be implemented on an a_pp=2, b_pp=4
-- array rather than using the (much larger) a_pp=4, b_pp=3 array
-- don't swap operands over - the last argument doesn't matter here!
widths := (a => c_a_width, b => c_b_width, a_type => c_a_type, b_type => c_b_type, swap => false);
a_pp_1 := calc_a_pp(family, widths);
b_pp_1 := calc_b_pp(widths);
-- swap the operands over - the last argument doesn't matter here!
widths := (a => c_b_width, b => c_a_width, a_type => c_b_type, b_type => c_a_type, swap => false);
a_pp_2 := calc_a_pp(family, widths);
b_pp_2 := calc_b_pp(widths);
-- compare the two results - pick the smallest one!
res_1 := a_pp_1 * b_pp_1;
res_2 := a_pp_2 * b_pp_2;
assert not(debug) report "res_1 (a_pp_1 * b_pp_1) is " & integer'image(res_1);
assert not(debug) report "res_2 (a_pp_2 * b_pp_2) is " & integer'image(res_2);
if res_1 <= res_2 then
-- leave as is - don't swap the operands
ret.swap := false;
if c_a_type = C_SIGNED then
ret.a := c_a_width;
elsif c_a_type = C_UNSIGNED then
ret.a := c_a_width+1;
end if;
if c_b_type = C_SIGNED then
ret.b := c_b_width;
elsif c_b_type = C_UNSIGNED then
ret.b := c_b_width+1;
end if;
ret.a_type := c_a_type;
ret.b_type := c_b_type;
else
-- operand sizes don't fit one of the optimal patterns,
-- so swap them around so that they will fit one of the patterns
ret.swap := true;
assert not(debug) report "swapping operands internally" severity note;
if c_b_type = 0 then
ret.a := c_b_width;
elsif c_b_type = 1 then
ret.a := c_b_width+1;
end if;
if c_a_type = C_SIGNED then
ret.b := c_a_width;
elsif c_a_type = C_UNSIGNED then
ret.b := c_a_width+1;
end if;
ret.a_type := c_b_type;
ret.b_type := c_a_type;
end if;
else
report "ERROR: mult_pkg.vhd: invalid family " & family & " caught in dsp.vhd/get_true_widths()"
severity error;
end if;
-- if an operand is smaller than the port width for a DSP,
-- round it up so it uses the full port width - this helps when the
-- multiplier is to be inferred
if ret.a < port_size.a then
ret.a := port_size.a;
end if;
if ret.b < port_size.b then
ret.b := port_size.b;
end if;
assert not(fn_debug) report "leaving get_true_widths" severity note;
return ret;
end function get_true_widths;
-- purpose: works out how many partial products are required for the A operand (number of DSPs)
function calc_a_pp(family : string; op_width : WIDTH_REC) return integer is
variable a_pp : integer := 0;
constant width_minus_18 : integer := op_width.a - 18;
constant width_minus_25 : integer := op_width.a - 25;
constant width_gt_18 : boolean := (op_width.a > 18);
constant width_gt_25 : boolean := (op_width.a > 25);
constant arg1 : integer := (width_minus_18/17)*boolean'pos(width_gt_18);
constant arg2 : integer := boolean'pos(width_minus_18 mod 17 /= 0 and width_gt_18);
constant arg11 : integer := (width_minus_25/17)*boolean'pos(width_gt_25);
constant arg21 : integer := boolean'pos(width_minus_25 mod 17 /= 0 and width_gt_25);
constant supports_25bit_mult : boolean := (supports_dsp48e(family) > 0);
begin -- FUNCTION calc_a_pp
assert not(fn_debug) report "entered calc_a_pp" severity note;
assert not(debug) report "op_width.a is " & integer'image(op_width.a) severity note;
if supports_25bit_mult then
a_pp := 1 + arg11 + arg21;
else
a_pp := 1 + arg1 + arg2;
end if;
assert not(debug) report "a_pp count: " & integer'image(a_pp) severity note;
assert not(fn_debug) report "leaving calc_a_pp" severity note;
return a_pp;
end function calc_a_pp;
-- purpose: works out how many partial products are required for the B operand (number of DSPs)
-- note that there is no family restriction here because DSP48 and DSP48E
-- both have 18-bit B ports on the multiplier
function calc_b_pp(op_width : WIDTH_REC) return integer is
variable b_pp : integer := 0;
constant width_minus_18 : integer := op_width.b - 18;
constant width_gt_18 : boolean := (op_width.b > 18);
constant arg1 : integer := (width_minus_18/17)*boolean'pos(width_gt_18);
constant arg2 : integer := boolean'pos(width_minus_18 mod 17 /= 0 and width_gt_18);
begin -- FUNCTION calc_b_pp
assert not(fn_debug) report "entered calc_b_pp" severity note;
assert not(debug) report "op_width.b is " & integer'image(op_width.b) severity note;
b_pp := 1 + arg1 + arg2;
assert not(debug) report "b_pp count: " & integer'image(b_pp) severity note;
assert not(fn_debug) report "leaving calc_b_pp" severity note;
return b_pp;
end function calc_b_pp;
-- purpose: works out how many partial products are required for the A operand (number of DSPs/MULT18X18s)
function hybrid_calc_a_pp(family : string; op_width : WIDTH_REC) return integer is
variable a_pp : integer := 0;
constant port_size_a : integer := 18+(7*boolean'pos(supports_dsp48e(family) > 0));
variable found_match : boolean := false;
constant a : integer := op_width.a+op_width.a_type;
constant b : integer := op_width.b+op_width.b_type;
begin -- FUNCTION hybrid_calc_a_pp
if supports_dsp48e(family) > 0 then
-- pick out the particular configurations that are supported
-- widths will be swapped so that the largest is on the A operand
-- perform the PP allocation in reverse order so that we don't need to trap as many cases
if op_width.a+op_width.a_type >= 42 and op_width.b+op_width.b_type >= 35 then
-- 2x2 configuration
a_pp := 2;
assert not(debug) report "DSP48E 2x2 configuration - a_pp" severity note;
elsif op_width.a+op_width.a_type >= 35 then
-- could implement a 2x1 or 1x2 array here - depends on the operand
-- widths to get best logic utilisation
if a >= 35 and a < 42 and b >= 25 then
-- 1x2 - shorter carry chain
a_pp := 1;
elsif a >= 42 and b >= 25 then
-- 2x1 - no choice
a_pp := 2;
elsif a >= 35 and a < 42 and b < 25 then
-- 1x2
a_pp := 1;
elsif a >= 42 and b < 25 then
a_pp := 2;
elsif a >= 42 and b >= 25 then
a_pp := 2;
end if;
elsif (op_width.a+op_width.a_type >= 25 and op_width.b+op_width.b_type >= 18)
or (op_width.a+op_width.a_type <= 25 and op_width.b+op_width.b_type >= 18)
or (op_width.a+op_width.a_type >= 25 and op_width.b+op_width.b_type <= 18) then
-- 1x1 CONFIGURATION
a_pp := 1;
assert not(debug) report "DSP48E 1x1 configuration - a_pp" severity note;
elsif op_width.a+op_width.a_type <= 25 and op_width.b+op_width.b_type <= 18 then
-- base mult - no fabric
a_pp := 1;
assert not(debug) report "DSP48E base mult configuration - a_pp" severity note;
end if;
else
a_pp := calc_a_pp(family, op_width);
if (op_width.a-(port_size_a)) mod 17 /= 0 and op_width.a > port_size_a then
a_pp := a_pp-1;
end if;
end if;
assert not(debug) report "hybrid a_pp count: " & integer'image(a_pp) severity note;
return a_pp;
end function hybrid_calc_a_pp;
-- purpose: works out how many partial products are required for the B operand (number of DSPs/MULT18X18s)
-- note that there is no family restriction here because MULT18X18, DSP48 and DSP48E
-- both have 18-bit B ports on the multiplier
function hybrid_calc_b_pp(family : string; op_width : WIDTH_REC) return integer is
variable b_pp : integer := 0;
variable int_width : integer := op_width.b;
constant port_size_b : integer := 18;
variable found_match : boolean := false;
constant a : integer := op_width.a+op_width.a_type;
constant b : integer := op_width.b+op_width.b_type;
begin -- FUNCTION hybrid_calc_b_pp
if supports_dsp48e(family) > 0 then
-- widths will be swapped so that the largest is on the A operand
-- perform the PP allocation in reverse order so that we don't need to trap as many cases
if op_width.a+op_width.a_type >= 42 and op_width.b+op_width.b_type >= 35 then
-- 2x2 configuration
b_pp := 2;
assert not(debug) report "DSP48E 2x2 configuration - b_pp" severity note;
elsif op_width.a+op_width.a_type >= 35 then
-- could implement a 2x1 or 1x2 array here - depends on the operand
-- widths to get best logic utilisation
if a >= 35 and a < 42 and b >= 25 then
-- 1x2 - shorter carry chain
b_pp := 2;
elsif a >= 42 and b >= 25 then
-- 2x1 - no choice
b_pp := 1;
elsif a >= 35 and a < 42 and b < 25 then
-- 1x2
b_pp := 2;
elsif a >= 42 and b < 25 then
b_pp := 1;
elsif a >= 42 and b >= 25 then
b_pp := 1;
end if;
elsif (op_width.a+op_width.a_type >= 25 and op_width.b+op_width.b_type >= 18)
or (op_width.a+op_width.a_type <= 25 and op_width.b+op_width.b_type >= 18)
or (op_width.a+op_width.a_type >= 25 and op_width.b+op_width.b_type <= 18) then
-- 1x1 CONFIGURATION
b_pp := 1;
assert not(debug) report "DSP48E 1x1 configuration - b_pp" severity note;
elsif op_width.a+op_width.a_type <= 25 and op_width.b+op_width.b_type <= 18 then
-- base mult - no fabric
b_pp := 1;
assert not(debug) report "DSP48E base mult configuration - b_pp" severity note;
end if;
else
b_pp := calc_b_pp(op_width);
if (op_width.b-(port_size_b)) mod 17 /= 0 and op_width.b > port_size_b then
b_pp := b_pp-1;
end if;
end if;
assert not(debug) report "hybrid b_pp count: " & integer'image(b_pp) severity note;
return b_pp;
end function hybrid_calc_b_pp;
-- purpose: works out which configuration of hybrid is required based on the input operand widths
-- and types and the multiplier primitive being used
function get_hybrid_configuration(family : string;
a_pp, b_pp : integer;
op_width : WIDTH_REC;
port_size : PORT_ASPECTS)return integer is
variable full_a_width : integer := 0;
variable full_b_width : integer := 0;
variable ret : integer := 99; -- error code - should always be assigned later
constant right_shift : integer := 17;
begin -- FUNCTION get_hybrid_configuration
full_a_width := op_width.a+op_width.a_type;
full_b_width := op_width.b+op_width.b_type;
assert not(debug) report "full_a_width is " & integer'image(full_a_width) severity note;
assert not(debug) report "full_b_width is " & integer'image(full_b_width) severity note;
if a_pp = 1 and b_pp = 1 then
if full_a_width <= port_size.a and full_b_width <= port_size.b then
ret := BASE_MULT;
assert not(debug) report "1x1 base mult" severity note;
elsif (full_a_width > port_size.a and full_b_width <= port_size.b) or (full_a_width <= port_size.a and full_b_width > port_size.b) then
ret := ONE_MULT;
assert not(debug) report "1x1 one fabric mult" severity note;
elsif full_a_width > port_size.a and full_b_width > port_size.b then
ret := TWO_MULT;
assert not(debug) report "1x1 two fabric mults" severity note;
end if;
elsif (a_pp = 2 and b_pp = 1) then
if full_a_width <= port_size.a+right_shift and full_b_width <= port_size.b then
ret := BASE_MULT;
assert not(debug) report "2x1 base mult" severity note;
elsif (full_a_width > port_size.a+right_shift and full_b_width <= port_size.b) or (full_a_width <= port_size.a+right_shift and full_b_width >= port_size.b) then
ret := ONE_MULT;
assert not(debug) report "2x1 one fabric mult" severity note;
elsif full_a_width > port_size.a+right_shift and full_b_width >= port_size.b then
ret := TWO_MULT;
assert not(debug) report "2x1 two fabric mults" severity note;
end if;
elsif a_pp = 1 and b_pp = 2 then
if (full_b_width <= port_size.a and full_a_width <= port_size.b+right_shift) then
ret := BASE_MULT;
assert not(debug) report "1x2 base mult" severity note;
elsif (full_b_width <= port_size.a and full_a_width >= port_size.b+right_shift) or (full_b_width >= port_size.a and full_a_width <= port_size.b+right_shift) then
ret := ONE_MULT;
assert not(debug) report "1x2 one fabric mult" severity note;
elsif (full_b_width > port_size.a and full_a_width > port_size.b+right_shift) then
ret := TWO_MULT;
assert not(debug) report "1x2 two fabric mults" severity note;
end if;
elsif a_pp = 2 and b_pp = 2 then
if full_a_width <= port_size.a+right_shift and full_b_width <= port_size.b+right_shift then
ret := BASE_MULT;
assert not(debug) report "2x2 base mult" severity note;
elsif (full_a_width > port_size.a+right_shift and full_b_width <= port_size.b+right_shift) or (full_a_width <= port_size.a+right_shift and full_b_width > port_size.b+right_shift) then
ret := ONE_MULT;
assert not(debug) report "2x2 one fabric mult" severity note;
elsif full_a_width > port_size.a+right_shift and full_b_width > port_size.b+right_shift then
ret := TWO_MULT;
assert not(debug) report "2x2 two fabric mults" severity note;
end if;
end if;
assert not(debug) report "hybrid_configuration is " & integer'image(ret) severity note;
assert ret /= 99 report "no valid configuration found" severity failure;
return ret;
end function get_hybrid_configuration;
-- purpose: works out the operand widths and types for the block multiplier subcomponent
function get_block_mult_cfg (family : string;
a_pp, b_pp : integer;
op_width : WIDTH_REC;
hybrid_cfg : integer;
port_size : PORT_ASPECTS) return BLOCK_MULT_REC is
variable ret : BLOCK_MULT_REC;
constant wire_shift : integer := 17;
variable mult_blocks : integer := 0;
constant a_width : integer := op_width.a;
constant a_type : integer := op_width.a_type;
constant b_width : integer := op_width.b;
constant b_type : integer := op_width.b_type;
variable a_port_size : integer := 0;
variable b_port_size : integer := 0;
begin -- FUNCTION get_block_mult_cfg
if a_width < port_size.a then
a_port_size := a_width;
else
a_port_size := port_size.a;
end if;
if b_width < port_size.b then
b_port_size := b_width;
else
b_port_size := port_size.b;
end if;
if a_pp = 1 and b_pp = 1 then
ret.a_width := a_port_size - boolean'pos(a_type = C_UNSIGNED and a_width >= port_size.a);
ret.b_width := b_port_size - boolean'pos(b_type = C_UNSIGNED and b_width >= port_size.b);
ret.a_type := a_type;
ret.b_type := b_type;
mult_blocks := 1;
elsif a_pp = 2 and b_pp = 1 then
ret.a_width := port_size.a+wire_shift - boolean'pos(a_type = C_UNSIGNED and a_width >= port_size.a);
ret.b_width := b_port_size - boolean'pos(b_type = C_UNSIGNED and b_width >= port_size.b);
ret.a_type := a_type;
ret.b_type := b_type;
mult_blocks := 2;
elsif a_pp = 1 and b_pp = 2 then
-- the operands will be swapped around so that the A operand is the largest
-- this means that we need to swap the a_type and b_type values over so
-- that they remain correct w.r.t. the operand widths
ret.a_width := port_size.b+wire_shift - boolean'pos(a_type = C_UNSIGNED);
ret.b_width := a_port_size - boolean'pos(b_type = C_UNSIGNED);
ret.a_type := a_type;
ret.b_type := b_type;
mult_blocks := 2;
elsif a_pp = 2 and b_pp = 2 then
ret.a_width := port_size.a+wire_shift - boolean'pos(a_type = C_UNSIGNED);
ret.b_width := port_size.b+wire_shift - boolean'pos(b_type = C_UNSIGNED);
ret.a_type := a_type;
ret.b_type := b_type;
mult_blocks := 4;
end if;
assert not(debug) report "Building hybrid around a " & integer'image(ret.a_width) & "x" & integer'image(ret.b_width) & " multiplier using " & integer'image(mult_blocks) & " block multipliers" severity note;
assert not(debug) report CR & "block_mult_cfg is: " &
CR & "a_width: " & integer'image(ret.a_width) &
CR & "b_width: " & integer'image(ret.b_width) &
CR & "a_type: " & integer'image(ret.a_type) &
CR & "b_type: " & integer'image(ret.b_type) & CR severity note;
return ret;
end function get_block_mult_cfg;
-- purpose: works out the required operand widths of the fabric multiplier for the 'one mult' case
function get_one_mult_cfg(width : WIDTH_REC;
block_a_width, block_a_type, block_b_width, block_b_type : integer;
hybrid_cfg : integer;
port_size : PORT_ASPECTS) return ONE_MULT_REC is
constant x_width : integer := block_a_width;
constant y_width : integer := block_b_width;
variable ret : ONE_MULT_REC;
variable print_debug : boolean := false;
begin -- FUNCTION get_one_mult_cfg
-- set defaults to avoid MTI disappearing...
ret.a := 0;
ret.b := 0;
ret.a_type := 0;
ret.b_type := 0;
ret.out_width := 0;
ret.bypass := 0;
ret.a_offset := 0;
ret.b_offset := 0;
assert not(debug) report "-------------------------------------------------------"
& CR & "get_one_mult_cfg width.a: " & integer'image(width.a) &
CR & "get_one_mult_cfg width.a_type: " & integer'image(width.a_type) &
CR & "get_one_mult_cfg width.b: " & integer'image(width.b) &
CR & "get_one_mult_cfg width.b_type: " & integer'image(width.b_type) &
CR & "get_one_mult_cfg hybrid_cfg " & integer'image(hybrid_cfg) &
CR & "get_one_mult_cfg x_width " &integer'image(x_width) &
CR & "get_one_mult_cfg y_width " & integer'image(y_width) &
CR & "-------------------------------------------------------" severity note;
if (width.a > x_width and (width.b <= y_width or y_width < port_size.b)) and hybrid_cfg = ONE_MULT then
assert not(debug) report "a_width > x_width and b_width <= y_width" severity note;
ret.a := width.a-x_width;
ret.b := width.b;
ret.a_type := C_UNSIGNED;
ret.b_type := width.b_type;
ret.bypass := ret.a;
ret.b_offset := 0;
ret.a_offset := ret.a;
print_debug := true;
end if;
-- this one doesn't work - do we even need this clause since the operands
-- are always swapped to make A the largest? What about the 1x2 V5 case?
if (width.a <= x_width and (width.b > y_width or y_width < port_size.b)) and hybrid_cfg = ONE_MULT then
assert not(debug) report "a_width <= x_width and b_width > y_width" severity note;
ret.a := width.a;
ret.b := width.b-y_width;
ret.a_type := width.a_type;
ret.b_type := C_UNSIGNED;
ret.bypass := ret.b;
ret.b_offset := ret.b;
ret.a_offset := 0;
print_debug := true;
end if;
ret.out_width := ret.a+ret.b;
assert not(debug) report CR & "one_mult_cfg is: " &
CR & "a: " & integer'image(ret.a) &
CR & "b: " & integer'image(ret.b) &
CR & "a_type: " & integer'image(ret.a_type) &
CR & "b_type: " & integer'image(ret.b_type) &
CR & "bypass: " & integer'image(ret.bypass) &
CR & "a_offset: " & integer'image(ret.a_offset) &
CR & "b_offset: " & integer'image(ret.b_offset) & CR severity note;
return ret;
end function get_one_mult_cfg;
-- purpose: works out the required operand widths of the fabric multiplier for the 'two mult' case
function get_two_mult_cfg(op_width : WIDTH_REC;
a_width, a_type, b_width, b_type : integer;
hybrid_cfg : integer) return TWO_MULT_REC is
constant x_width : integer := a_width;
constant y_width : integer := b_width;
variable ret : TWO_MULT_REC;
variable print_debug : boolean := false;
constant full_width_a : integer := op_width.a; --+op_width.a_type;
constant full_width_b : integer := op_width.b; --+op_width.b_type;
begin -- FUNCTION get_two_mult_cfg
-- set defaults to avoid MTI disappearing...
ret.a_top := 0;
ret.b_top := 0;
ret.a_type_top := 0;
ret.b_type_top := 0;
ret.out_width_top := 0;
ret.a_side := 0;
ret.b_side := 0;
ret.a_type_side := 0;
ret.b_type_side := 0;
ret.out_width_side := 0;
ret.mult_bypass := 0;
ret.add_bypass := 0;
ret.a_offset := 0;
ret.b_offset := 0;
assert not(debug) report "get_two_mult_cfg x_width is " & integer'image(x_width) severity note;
assert not(debug) report "get_two_mult_cfg y_width is " & integer'image(y_width) severity note;
assert not(debug) report "get_two_mult_cfg full_width_a is " & integer'image(full_width_a) severity note;
assert not(debug) report "get_two_mult_cfg full_width_b is " & integer'image(full_width_b) severity note;
if (full_width_a >= x_width and full_width_b >= y_width) and hybrid_cfg = TWO_MULT then -- condition for this configuration to be valid
-- The code above will automatically swap the operands so that the largest is
-- on the A bus. Because we only make 2 cuts in the partial product
-- array, this means that we want to make the A operand shorter than the B
-- operand to balance out the carry chain lengths for e.g. 22x20 multipliers
-- top fabric mult
ret.a_top := x_width;
ret.b_top := full_width_b - y_width;
ret.a_type_top := a_type;
ret.b_type_top := C_UNSIGNED;
ret.out_width_top := ret.a_top + ret.b_top;
-- side fabric mult
ret.a_side := full_width_a - x_width;
ret.b_side := full_width_b;
ret.a_type_side := C_UNSIGNED;
ret.b_type_side := b_type;
ret.out_width_side := ret.a_side + ret.b_side;
-- bypass vectors
ret.mult_bypass := ret.a_side;
ret.add_bypass := ret.b_top;
-- offsets for the block mult array inputs
ret.a_offset := ret.a_side;
ret.b_offset := ret.b_top;
print_debug := true;
elsif (full_width_b >= x_width and full_width_a >= y_width) and hybrid_cfg = TWO_MULT then
-- top fabric mult
ret.a_top := y_width;
ret.b_top := full_width_b - x_width;
ret.a_type_top := a_type;
ret.b_type_top := C_UNSIGNED;
ret.out_width_top := ret.a_top + ret.b_top;
-- side fabric mult
ret.a_side := full_width_a - y_width;
ret.b_side := full_width_b;
ret.a_type_side := C_UNSIGNED;
ret.b_type_side := b_type;
ret.out_width_side := ret.a_side + ret.b_side;
-- bypass vectors
ret.mult_bypass := ret.a_side;
ret.add_bypass := ret.b_top;
-- offsets for the block mult array inputs
ret.a_offset := ret.a_side;
ret.b_offset := ret.b_top;
print_debug := true;
end if;
assert not(debug) report CR & "two_mult_cfg is: " &
CR & "a_top: " & integer'image(ret.a_top) &
CR & "b_top: " & integer'image(ret.b_top) &
CR & "a_type_top: " & integer'image(ret.a_type_top) &
CR & "b_type_top: " & integer'image(ret.b_type_top) &
CR & "out_width_top: " & integer'image(ret.out_width_top) &
CR & "a_side: " & integer'image(ret.a_side) &
CR & "b_side: " & integer'image(ret.b_side) &
CR & "a_type_side: " & integer'image(ret.a_type_side) &
CR & "b_type_side: " & integer'image(ret.b_type_side) &
CR & "out_width_side: " & integer'image(ret.out_width_side) &
CR & "mult_bypass: " & integer'image(ret.mult_bypass) &
CR & "add_bypass: " & integer'image(ret.add_bypass) &
CR & "a_offset: " & integer'image(ret.a_offset) &
CR & "b_offset: " & integer'image(ret.b_offset) & CR severity note;
return ret;
end function get_two_mult_cfg;
-- purpose: works out the fully-pipelined latency of a LUT multiplier
function fab_mult_full_pipe_lat(a_width, b_width : integer) return integer is
variable b : integer := 0;
begin -- FUNCTION fab_mult_full_pipe_lat
b := get_min(a_width, b_width);
if b = 1 then
-- Need to trap this, otherwise a 35x1 multiplier would have a
-- fully-pipelined latency of zero!
return 1;
else
return mult_gen_log2(b);
end if;
end function fab_mult_full_pipe_lat;
-- purpose: works out how many pipeline stages a particular configuration of DSP blocks needs
function get_emb_mult_max_pipe_stages (family : string; a_pp, b_pp : integer) return integer is
variable ret : integer := 0;
begin -- FUNCTION get_DSP_max_pipe_stages
if supports_dsp48(family) = 1 or supports_dsp48e(family) > 0 then
if a_pp = 1 and b_pp = 1 then
ret := 3;
elsif a_pp = 2 and b_pp = 1 then
ret := 4;
elsif a_pp = 1 and b_pp = 2 then
ret := 4;
elsif a_pp = 2 and b_pp = 2 then
ret := 6;
else
ret := 99; -- unsupported configuration
report "ERROR: caught unsupported hybrid configuration in get_DSP_max_pipe_stages in mult_pkg"
severity failure;
end if;
elsif supports_dsp48a(family) > 0 then
-- There's no simple formula to work out what the latency will
-- be based on the number of DSPs. It depends how many wireshifts we need in
-- the fabric (i.e. how many times the C port needs to be used)
if a_pp = 1 and b_pp = 1 then
ret := 3;
elsif a_pp = 2 and b_pp = 1 then
ret := 5;
elsif a_pp = 2 and b_pp = 2 then
ret := 8;
else
ret := 99; -- unsupported configuration
report "ERROR: caught unsupported hybrid configuration in get_DSP_max_pipe_stages in mult_pkg"
severity failure;
end if;
elsif supports_mult18x18s(family) = 1 or supports_mult18x18sio(family) = 1 then
-- number of pipeline stages dictated by number of partial products
-- which determines the depth of the adder tree + registers in and
-- after the multiplier block
ret := mult_gen_log2(a_pp * b_pp) + 2;
if supports_mult18x18sio(family) = 1 then
-- add another register for after the multiplier blocks
ret := ret + 1;
end if;
else
report "ERROR: caught invalid family in get_emb_mult_max_pipe_stages"
severity failure;
end if;
return ret;
end function get_emb_mult_max_pipe_stages;
-- purpose: works out the depth of the adder tree on the LUT multiplier(s)
-- to see what the maximum fully-pipelined latency will be
function get_LUT_max_pipe_stages (one_mult_cfg : ONE_MULT_REC; two_mult_cfg : TWO_MULT_REC; hybrid_configuration : integer) return integer is
variable true_b_width_side : integer := 0;
variable true_b_width_top : integer := 0;
variable ret : integer := 0;
begin -- FUNCTION get_LUT_max_pipe_stages
if hybrid_configuration = 0 then
ret := 0;
elsif hybrid_configuration = 1 then
-- only one fabric multiplier - use one_mult_cfg
ret := fab_mult_full_pipe_lat(one_mult_cfg.a, one_mult_cfg.b);
elsif hybrid_configuration = 2 then
-- two fabric multipliers - work out which is the largest aka deepest
true_b_width_top := get_min(two_mult_cfg.a_top, two_mult_cfg.b_top);
true_b_width_side := get_min(two_mult_cfg.a_side, two_mult_cfg.b_side);
if true_b_width_top > true_b_width_side then
ret := mult_gen_log2(true_b_width_top);
else
ret := mult_gen_log2(true_b_width_side);
end if;
else
report "ERROR: invalid hybrid configuration value caught in get_LUT_max_pipe_stages in mult_pkg"
severity failure;
ret := 99;
end if;
return ret;
end function get_LUT_max_pipe_stages;
-- purpose: counts the number of LSB zeros in the supplied constant STRING
-- If the bits are zero, we don't need to pass these bits into the multiplier
-- and we can just right-shift the output by these number of bits
function get_output_scaling (b_value : string; b_type : integer; mult_type : integer)return integer is
variable shift : integer := 0;
variable can_trim : boolean := true;
variable all_ones : string(1 to b_value'length-1);
begin -- FUNCTION get_output_scaling
-- VTFC doesn't support (others => '1') assignment to a string
-- so we have to initialise the variable this way instead
for i in 1 to all_ones'length loop
all_ones(i) := '1';
end loop; -- i
if mult_type = FIXED_CCM then
-- first check if the constant is a negative power of 2
-- if it is, we can't trim the LS zeros
-- Assume that the input string will always be (1 to N) ranged
-- for support by VTFC
if b_value(b_value'high) = '0' and b_value(b_value'low to b_value'high-1) = all_ones then
can_trim := false;
end if;
if can_trim then
-- start at the LSB and work our way left gaining bit significance
for i in b_value'high downto b_value'low loop
if b_value(i) = '1' then
exit;
else
shift := shift + 1;
end if;
end loop; -- i
end if;
-- OLD CODE - COVERS ALL POSSIBLE STRING ORIENTATIONS
-- if b_value'ascending then
-- if b_value(b_value'right) = '0' and b_value(b_value'left to b_value'right-1) = all_ones then
-- can_trim := false;
-- end if;
-- else
-- if b_value(b_value'right) = '0' and b_value(b_value'left downto b_value'right+1) = all_ones then
-- can_trim := false;
-- end if;
-- end if;
-- if can_trim then
-- -- start at the LSB and work our way left gaining bit significance
-- -- Account for the strings being TO or DOWNTO
-- if b_value'ascending then
-- for i in b_value'right downto b_value'left loop
-- if b_value(i) = '1' then
-- exit;
-- else
-- shift := shift + 1;
-- end if;
-- end loop; -- i
-- else -- b_value'descending
-- for i in b_value'right to b_value'left loop
-- if b_value(i) = '1' then
-- exit;
-- else
-- shift := shift + 1;
-- end if;
-- end loop; -- i
-- end if;
-- end if;
assert not(debug) report "shift value is " & integer'image(shift) severity note;
end if;
return shift;
end function get_output_scaling;
-- purpose: checks to see if the constant has any zeros at the MSB (left) side of the string and
-- returns an integer to say how many consecutive zeros there are
-- These zeros don't need to go through the multiplier, so we could save some
-- logic in a few cases
-- If the constant is of signed type, we need to keep one of the leading zeros
-- If the constant is signed though, we can also check for leading ones and
-- trim them, stopping when we find "10" when searching from the left-hand side
function get_trimmed_leading_bits (b_value : string; b_type : integer; mult_type : integer) return integer is
variable zeros_to_trim : integer := 0;
variable ones_to_trim : integer := 0;
variable bits_to_trim : integer := 0;
begin -- FUNCTION get_trimmed_leading_bits
-- To make this function compatible with VTFC (for the GUI), we need to do
-- away with the 'ascending, 'left, 'right attributes and use only 'length,
-- 'low and 'high. This is based on the assumption that only strings with
-- (1 to N) ranges will be passed into this function
if mult_type = FIXED_CCM then
for i in b_value'low to b_value'high loop
if b_value(i) = '1' then
exit;
else
zeros_to_trim := zeros_to_trim + 1;
end if;
end loop; -- i
-- New loop for V10.0 that avoids the array indexing error for -1
if b_type = C_SIGNED and zeros_to_trim = 0 then
for i in b_value'low to b_value'high loop
if b_value(i) = '1' then
if i+1 <= b_value'high then
if b_value(i+1) = '0' then
exit;
end if;
else
null;
end if;
else
ones_to_trim := ones_to_trim + 1;
end if;
end loop; -- i
end if;
-- OLD CODE - COVERS THE ASCENDING AND DESCENDING STRING CASES
-- BUT DOESN'T SUPPORT VTFC
-- if mult_type = FIXED_CCM then
-- -- Account for the strings being TO or DOWNTO
-- if b_value'ascending then
-- for i in b_value'left to b_value'right loop
-- if b_value(i) = '1' then
-- exit;
-- else
-- zeros_to_trim := zeros_to_trim + 1;
-- end if;
-- end loop; -- i
-- else -- b_value'descending
-- for i in b_value'left downto b_value'right loop
-- if b_value(i) = '1' then
-- exit;
-- else
-- zeros_to_trim := zeros_to_trim + 1;
-- end if;
-- end loop; -- i
-- end if;
-- -- New loop for V10.0 that avoids the array indexing error for -1
-- if b_type = C_SIGNED and zeros_to_trim = 0 then
-- -- Account for the strings being TO or DOWNTO
-- if b_value'ascending then
-- for i in b_value'left to b_value'right loop
-- if b_value(i) = '1' then
-- if i+1 <= b_value'right then
-- if b_value(i+1) = '0' then
-- exit;
-- end if;
-- else
-- null;
-- end if;
-- else
-- ones_to_trim := ones_to_trim + 1;
-- end if;
-- end loop; -- i
-- else -- b_value'descending
-- for i in b_value'left downto b_value'right loop
-- if b_value(i) = '1' then
-- if i-1 >= b_value'right then
-- if b_value(i-1) = '0' then
-- exit;
-- end if;
-- else
-- null;
-- end if;
-- else
-- ones_to_trim := ones_to_trim + 1;
-- end if;
-- end loop; -- i
-- end if;
-- end if;
-- need to keep the MSB zero in the signed case to allow for correct
-- operand extension in the subcores
if b_type = C_SIGNED and zeros_to_trim > 0 then
zeros_to_trim := zeros_to_trim - 1;
end if;
bits_to_trim := ones_to_trim + zeros_to_trim; -- only one of these will be non-zero
assert not(debug) report "trimming " & integer'image(bits_to_trim) & " leading ones or zeros" severity note;
end if;
return bits_to_trim;
end function get_trimmed_leading_bits;
-- purpose: checks if the constant is all-zeros, in which case there is no point in creating logic!
function check_b_value_all_zeros (b_value : string; b_value_length : integer) return boolean is
variable ret : boolean := false;
begin -- FUNCTION check_b_value_all_zeros
for i in 1 to b_value_length loop
if b_value(i) = '1' then
ret := false;
exit;
end if;
ret := true;
end loop; -- i
assert ret = false report "b_value constant is exactly zero - no logic will be created" severity warning;
return ret;
end function check_b_value_all_zeros;
function check_const_power_of_two (b_value : string; b_type, mult_type : integer) return boolean is
variable trimmed_msbs : integer := get_trimmed_leading_bits(b_value, b_type, mult_type);
variable trimmed_lsbs : integer := calc_shift_bits(b_value, boolean'pos(mult_type = FIXED_CCM));
variable ret : boolean := false;
begin
-- Assume that the input string has a range of (1 to N) for VTFC support
if b_value(b_value'low) = '1' and b_type = C_SIGNED then
-- signed constant - can't represent by shifting alone
ret := false;
else
ret := (b_value'length - (trimmed_lsbs + trimmed_msbs) = 1);
end if;
-- OLD CODE - COVERS ALL POSSIBLE STRINGS
-- if b_value'ascending then
-- if b_value(b_value'low) = '1' and b_type = C_SIGNED then
-- -- signed constant - can't represent by shifting alone
-- ret := false;
-- else
-- ret := (b_value'length - (trimmed_lsbs + trimmed_msbs) = 1);
-- end if;
-- else -- b_value'descending
-- if b_value(b_value'high) = '1' and b_type = C_SIGNED then
-- -- signed constant - can't represent by shifting alone
-- ret := false;
-- else
-- ret := (b_value'length - (trimmed_lsbs + trimmed_msbs) = 1);
-- end if;
-- end if;
return ret;
end function check_const_power_of_two;
-------------------------------------------------------------------------------
-- Functions imported from ccm_pkg.vhd
-------------------------------------------------------------------------------
function calc_reqd_b_value(b_value : string;
b_width : integer;
b_type : integer;
reqd_b_width : integer) return string is
constant b_lsb : integer := b_value'high;
variable b_bit : integer;
variable reqd_b_value : string(1 to reqd_b_width);
begin
for bit in 1 to reqd_b_width loop
b_bit := bit + b_lsb - reqd_b_width;
if b_bit > 0 then
reqd_b_value(bit) := b_value(b_bit);
else
if b_type = C_SIGNED then
reqd_b_value(bit) := b_value(1);
else
reqd_b_value(bit) := '0';
end if; -- b_type
end if; -- b_bit
end loop;
assert not(ccm_debug) report "calc_reqd_b_value returning " & reqd_b_value severity note;
return reqd_b_value;
end calc_reqd_b_value;
function bitstorep_string(a_value : string;
a_type : integer) return integer is
variable return_value : integer;
begin
return_value := a_value'length;
if a_type = C_UNSIGNED then
-- a_value represents an unsigned number
-- FOR i IN a_value'RANGE LOOP -- Doesn't work with XCC
for i in a_value'low to a_value'high loop
if a_value(i) = '1' then
exit; -- EXIT when the msb is found
elsif a_value(i) = '0' then
return_value := return_value - 1;
else
null;
end if;
end loop;
else
-- a_value represents a signed number
-- Look for ms '1' followed by a '0'
-- FOR i IN a_value'RANGE LOOP -- Doesn't work with XCC
for i in a_value'low to a_value'high loop
if a_value(i) = '1' then
if i < a_value'high then
if a_value(i+1) = '0' then
exit; -- EXIT when the msb is found
else
return_value := return_value - 1;
end if;
else
exit; -- EXIT when end of STRING reached
end if;
elsif a_value(i) = '0' then
return_value := return_value - 1;
else
null;
end if;
end loop;
end if;
if return_value <= 0 then
return 1;
else
return return_value;
end if;
end bitstorep_string;
function calc_shift_bits(b_value : string;
b_constant : integer) return integer is
variable bit : integer;
variable shift_bits : integer;
begin
shift_bits := 0;
assert not(ccm_debug) report "calc_shift_bits params: " & b_value & " " & integer'image(b_constant) severity note;
if b_constant /= 0 then
bit := b_value'high;
while (bit >= b_value'low) loop
if b_value(bit) = '0' then
shift_bits := shift_bits + 1;
else
exit;
end if;
bit := bit - 1;
end loop;
end if;
if shift_bits >= b_value'high then
shift_bits := 0; -- All zeroes value
end if;
assert not(ccm_debug) report "calc_shift_bits returning " & integer'image(shift_bits) severity note;
return shift_bits;
end calc_shift_bits;
function get_rom_addr_width(family : string; mem_type : integer) return integer is
begin
if mem_type = C_DISTRIBUTED then
if supports_lut6(family) = 1 then
assert not(debug) report "distributed ram address width is 6 - 64x1 RAM (LUT6)" severity note;
return 6;
else
assert not(debug) report "distributed ram address width is 4 - 16x1 RAM (LUT4)" severity note;
return 4;
end if;
else
-- use a 9-bit address width
-- use the 18K BRAM for V5 as well
return 9;
end if;
end get_rom_addr_width;
function calc_a_input_width(operand_width, has_a_signed, rom_addr_width, b_constant : integer) return integer is
variable effective_op_width : integer;
begin
if has_a_signed = 0 or b_constant = 0 then
effective_op_width := operand_width;
else
-- Allow extra input for 'a_signed'
effective_op_width := operand_width + 1;
end if;
if (effective_op_width mod rom_addr_width = 0) then
return effective_op_width;
else
return effective_op_width + rom_addr_width - (effective_op_width mod rom_addr_width);
end if;
end calc_a_input_width;
function calc_num_pps(a_width, rom_addr_width : integer) return integer is
begin
if (a_width mod rom_addr_width /= 0) then
return (a_width / rom_addr_width) + 1;
else
return (a_width / rom_addr_width);
end if;
end calc_num_pps;
------------------------------------------------------------------------------
-- Returns the number of input bits required by the last partial product ROM.
-- Does not include a_signed bit.
------------------------------------------------------------------------------
function calc_last_pp_input_width(operand_width, has_a_signed,
rom_addr_width, b_constant : integer) return integer is
begin
if (operand_width mod rom_addr_width /= 0) then
return operand_width mod rom_addr_width;
else
-- There is an extra pp in this case due to the msb and 'a_signed' having
-- to have a separate LUT
if has_a_signed /= 0 and b_constant /= 0 then
return 1;
else
return rom_addr_width;
end if;
end if;
end calc_last_pp_input_width;
------------------------------------------------------------------------------
-- Calculate amount to delay signal which drives addsub add input.
------------------------------------------------------------------------------
function calc_add_lastpp_delay(reg_a_b_inputs : integer;
pipeline : integer;
num_pipe_stages : integer) return integer is
variable delay : integer;
begin
if reg_a_b_inputs = 0 then
delay := 0;
else
delay := 1;
end if;
if pipeline /= 0 then
delay := num_pipe_stages + 1; -- Add 1 for RAM output register
end if;
return delay;
end calc_add_lastpp_delay;
------------------------------------------------------------------------------
-- Only the product bits from 'start_bit' upwards are stored in the ROMs
-- because the bits below 'start_bit' are one of the address bits.
--
-- e.g. ROM output(0) = I0 if b(0)='1'
-- ROM output(1) = I1 if b(1:0)='01'
-- ROM output(2) = I2 if b(2:0)='001'
-- .. ..
-- ROM output(n) = In if b(n:0)='0...01'
------------------------------------------------------------------------------
function calc_rom_start_bit(b_width : integer;
b_value : string;
b_constant : integer;
pp_width : integer;
a_type : integer;
rom_has_a_signed : integer;
mem_type : integer;
mem_addr_width : integer;
pipeline : integer;
num_adders : integer;
has_q : integer;
last_mem : boolean) return integer is
variable b_bit : integer;
variable start_bit : integer;
begin
start_bit := 0;
b_bit := b_value'high; -- STRINGs go from 1 to N (lsb = N)
if b_bit > 1 and b_constant /= 0 and mem_type = C_DISTRIBUTED and rom_has_a_signed = 0
and ((num_adders > 0 and pipeline = 0) or (num_adders = 0 and has_q = 0)) then
if b_value(b_bit) = '1' then
start_bit := 1;
while start_bit < pp_width loop
-- Increment start_bit if 1st bit = '1' and next ms bit = '0'
if b_bit > b_value'low then
b_bit := b_bit - 1;
if b_value(b_bit) = '0' then
start_bit := start_bit + 1;
else
exit;
end if;
else
start_bit := start_bit + 1;
end if; -- b_bit > b_value'LOW
end loop; -- WHILE ...
end if; -- b_value(b_value'HIGH) = '1'
end if; -- b_constant /= 0
-- Do not allow start_bit to exceed mem_addr_width if last mem and
-- a is signed
if last_mem and a_type = C_SIGNED and start_bit > mem_addr_width then
start_bit := mem_addr_width;
end if;
return start_bit;
end calc_rom_start_bit;
-- andreww restructured calc_rom_contents to work better with XST
-- previously the call the multiply_bv was made within the nested FOR loops,
-- which could result in extra memory overhead. Moving this outside to an independent
-- FOR loop and assembling a constant array is much easier on XST
-- 16 November 2005
function calc_rom_contents(b_width : integer;
b_type : integer;
rom_addr_width : integer;
rom_depth : integer;
rom_width : integer;
start_bit : integer;
b_value : string;
num_rom_bits : integer) return bit_vector is
variable b_value_bv : bit_vector(b_width-1 downto 0);
variable prod : bit_vector(rom_addr_width+b_width-1 downto 0);
variable rom_contents : bit_vector(num_rom_bits-1 downto 0);
-- new things
type T_PROD is array (0 to rom_depth-1) of bit_vector(rom_addr_width+b_width-1 downto 0);
variable prod_array : T_PROD;
variable prod_el : bit_vector(rom_addr_width+b_width-1 downto 0);
begin
b_value_bv := mult_gen_str_to_bv(b_value, b_width);
for rom_addr in 0 to rom_depth-1 loop
prod_array(rom_addr) := multiply_bv(natural_to_bit_vector(rom_addr, rom_addr_width), b_value_bv, false, (b_type = C_SIGNED));
end loop; -- rom_addr
for rom_addr in 0 to rom_depth-1 loop
-- Multiply rom_addr by c_b_value
-- get the bit vector out of the array
prod_el := prod_array(rom_addr);
rom_contents((rom_addr*rom_width + rom_width-1) downto (rom_addr*rom_width + 0)) := prod_el((rom_width-1 + start_bit) downto (0 + start_bit));
end loop;
return rom_contents;
end calc_rom_contents;
------------------------------------------------------------------------------
--
-- Last ROM contents differ because 'a' may not occupy the full address bus
-- and the MSB of 'a' may be a sign bit.
--
-- c_has_a_signed=0 (a=3 bits) c_has_a_signed/=0 (a=2 bits)
-- Location Contents Location Contents
-- 0 0 * B 0 0 * B
-- 1 1 * B 1 1 * B
-- 2 2 * B 2 2 * B
-- 3 3 * B 3 3 * B
-- 4 4 * B <-- 2**(a_width-1) 4 0 * B <-- 2**(a_width-1)
-- 5 3 * B 5 -1 * B
-- 6 2 * B 6 -2 * B
-- 7 1 * B 7 -1 * B
-- 8 Don't care 8 Don't care
-- etc etc
--
-- If b is not constant then last ROM is just the same as all the others.
------------------------------------------------------------------------------
function calc_last_rom_contents(b_width : integer;
a_width : integer; -- not incl a_signed
a_type : integer;
b_type : integer;
has_a_signed : integer;
rom_addr_width : integer;
rom_depth : integer;
rom_width : integer;
start_bit : integer;
b_value : string;
b_constant : integer;
num_rom_bits : integer;
number_of_pps : integer;
a_signed_extension : boolean) return bit_vector is
constant a_signed : boolean := ((a_type = C_SIGNED) or (has_a_signed /= 0));
constant max_val : integer := 2**(a_width-1);
constant prod_width : integer := a_width + b_width;
variable b_value_bv : bit_vector(b_width-1 downto 0);
variable prod : bit_vector(prod_width-1 downto 0);
variable rom_contents : bit_vector(num_rom_bits-1 downto 0);
variable debug_string : string(1 to prod_width);
begin
if (has_a_signed = 0 and a_type = C_UNSIGNED) or (b_constant = 0) then
return calc_rom_contents(b_width, b_type, a_width, rom_depth, rom_width, start_bit, b_value, num_rom_bits);
else
b_value_bv := mult_gen_str_to_bv(b_value, b_width);
for rom_addr in 0 to rom_depth-1 loop
-- Multiply rom_addr by c_b_value
prod := multiply_bv(natural_to_bit_vector(rom_addr, a_width), b_value_bv, a_signed, (b_type = C_SIGNED));
rom_contents((rom_addr*rom_width + rom_width-1) downto (rom_addr*rom_width + 0)) := prod((rom_width-1 + start_bit) downto (0 + start_bit));
end loop;
return rom_contents;
end if;
end calc_last_rom_contents;
------------------------------------------------------------------------------
-- Return adder level within the symmetric tree for a given adder number.
-- Adder numbers start from 0. Level 1 is the level nearest the pprods.
------------------------------------------------------------------------------
function calc_adder_level(adder_num, max_add_levels : integer) return integer is
type num_al_type is array(1 to max_add_levels) of integer;
variable add_level : integer;
variable num_al : num_al_type;
begin
for i in 1 to max_add_levels loop
num_al(i) := 0;
end loop;
add_level := 1;
for i in 0 to (adder_num-1) loop
num_al(add_level) := num_al(add_level) + 1;
if (num_al(add_level) = 2) then
num_al(add_level) := 0;
add_level := add_level + 1;
else
add_level := 1;
end if;
end loop;
return add_level;
end calc_adder_level;
------------------------------------------------------------------------------
-- Return the adder number of the adder whose b input is the last partial
-- product. Adders are numbered 0 to n.
------------------------------------------------------------------------------
function calc_last_pp_adder(num_pps : integer;
max_add_levels : integer;
num_adders : integer;
num_extra_adders : integer) return integer is
variable add_num : integer;
begin
if num_extra_adders > 0 and (num_pps mod 2 /= 0) then
-- First extra adder is the last pp adder
return num_adders-num_extra_adders;
else
add_num := 0;
for p in 0 to num_pps-2 loop
for l in 1 to max_add_levels loop
if ((p+1) mod 2**l = 0) then
add_num := add_num + 1;
end if;
end loop; -- l
end loop; -- p
return add_num;
end if; -- num_extra_adders > 0 ...
end calc_last_pp_adder;
------------------------------------------------------------------------------
--
-- Calculate number of extra add stages to place at the right.
-- Input parameter is total number of partial products.
--
-- Algorithm is (for max_num_pps = 8 example)
-- add_count := 0
-- pps=8? Yes --> Done
-- pps>8? Yes --> Subtract 8, increment add_count, (pps=4?) Yes --> Done
-- pps>4? Yes --> Subtract 4, increment add_count, (pps=2?) Yes --> Done
-- pps>2? Yes --> Subtract 2, increment add_count, Done
-- Done
------------------------------------------------------------------------------
function calc_num_extra_adders(num_pps, max_num_pps : integer)
return integer is
variable adder_count : integer;
variable pps_group : integer;
variable pps_remaining : integer;
begin
pps_remaining := num_pps;
pps_group := max_num_pps;
adder_count := 0;
while ((pps_group > 1) and (pps_group /= pps_remaining)) loop
if (pps_remaining > pps_group) then
adder_count := adder_count + 1;
pps_remaining := pps_remaining - pps_group;
end if;
pps_group := pps_group / 2;
end loop;
return adder_count;
end calc_num_extra_adders;
------------------------------------------------------------------------------
-- Return width of partial or full product
-- Set full_prod to TRUE if width of total final product is to be returned.
------------------------------------------------------------------------------
function calc_pp_width(b_width : integer;
b_type : integer;
b_value : string;
b_constant : integer;
a_width : integer;
a_type : integer;
has_a_signed : integer;
last_pp : boolean;
full_prod : boolean) return integer is
variable a_all_1s : bit_vector(a_width-1 downto 0);
variable b_all_1s : bit_vector(b_width-1 downto 0);
-- a_type is always unsigned for partial products if b is not constant
constant act_a_type : integer :=
select_val(a_type, C_UNSIGNED, b_constant = 0 and not(full_prod));
constant act_a_sgnd : integer :=
select_val(has_a_signed, 0, b_constant = 0 and not(full_prod));
variable min_a : bit_vector(a_width-1 downto 0);
variable a_value_bv : bit_vector(a_width-1 downto 0);
variable b_value_bv : bit_vector(b_width-1 downto 0);
variable pp_width : integer;
variable pp_width_a_negative : integer;
begin
assert not(ccm_debug) report "calc_pp_width args "
& integer'image(b_width)
& " " & integer'image(b_type)
& " " & b_value
& " " & integer'image(b_constant)
& " " & integer'image(a_width)
& " " & integer'image(a_type)
& " " & integer'image(has_a_signed)
& " " & boolean'image(last_pp)
& " " & boolean'image(full_prod) severity note;
-- Workaround for VTFC not handling bit_vector type correctly
for i in a_width-1 downto 0 loop
a_all_1s(i) := '1';
end loop; -- i
for i in b_width-1 downto 0 loop
b_all_1s(i) := '1';
end loop; -- i
assert not(ccm_debug) report "0: pp_width is " & integer'image(pp_width) severity note;
if b_width = 1 and b_type = C_UNSIGNED then
if b_value(b_value'high) = '0' and b_constant /= 0 then
pp_width := 1; -- Special case for multiplying by 0
else
pp_width := a_width;
-- a_signed is not part of pp input if b_constant/=0
if last_pp and act_a_sgnd /= 0 then
pp_width := pp_width + 1;
end if;
end if; -- b_value
else
-- Return minimum number of bits to represent maximum possible pp value
if b_constant = 0 then
if b_type = C_UNSIGNED then
-- Must assume max possible B value
b_value_bv := b_all_1s;
else
if b_width > 1 then
-- Use loop assignment for VTFC support
for i in b_width-2 downto 0 loop
b_value_bv(i) := '0';
end loop; -- i
end if;
b_value_bv(b_width-1) := '1';
end if; -- b_type = C_UNSIGNED
else
b_value_bv := mult_gen_str_to_bv(b_value, b_width);
end if;
-- A input always treated as unsigned except for last pp
if not(last_pp) or act_a_type = C_UNSIGNED then
if a_width = 1 and b_value_bv = b_all_1s and b_type /= C_UNSIGNED and b_constant /= 0 then
pp_width := 1; -- -1 * (0 or 1) only needs 1 bit
else
pp_width := bitstorep_bv(multiply_bv(a_all_1s, b_value_bv, false, (b_type = C_SIGNED)), b_type, (b_type /= C_SIGNED));
end if; -- a_width = 1 AND ...
-- a_signed input has effect on last PP
elsif act_a_sgnd /= 0 then -- 1 is added later
pp_width := bitstorep_bv(multiply_bv(a_all_1s, b_value_bv, false, (b_type = C_SIGNED)), b_type, (b_type /= C_SIGNED));
-- Add 1 to last pp width if extra bit has to be added due to
-- c_has_a_signed as above result always +ve if b_type unsigned
if b_type = C_UNSIGNED then
pp_width := pp_width + 1;
else
-- Get minimum possible A value
if a_width > 1 then
-- Use loop assignment for VTFC support
for i in a_width-1 downto 0 loop
a_value_bv(i) := '0';
end loop; -- i
end if;
a_value_bv(a_width-1) := '1';
-- Min A * Min B to get max +ve output
pp_width_a_negative := bitstorep_bv(multiply_bv(a_value_bv, b_value_bv, true, true), C_UNSIGNED, true); -- -ve (A) * -ve (B) = +ve
if pp_width_a_negative >= pp_width then
pp_width := pp_width + 1;
end if;
end if;
else -- last_pp and a_type=C_SIGNED and c_has_a_signed=0
if a_width = 1 then -- Worst case = -1
pp_width := bitstorep_bv(multiply_bv("11", b_value_bv, true, (b_type = C_SIGNED)), C_SIGNED, (b_type = C_SIGNED));
else
-- Lowest possible A value
-- Use loop assignment for VTFC support
for i in a_width-1 downto 0 loop
min_a(i) := '0';
end loop; -- i
min_a(a_width-1) := '1';
-- Determine type of widest possible PP
-- -ve * -ve = +ve, -ve * +ve = -ve
pp_width := bitstorep_bv(multiply_bv(min_a, b_value_bv, true, (b_type = C_SIGNED)), C_SIGNED, (b_type = C_SIGNED));
end if;
end if; -- NOT(last_pp) OR ...
end if;
assert not(ccm_debug) report "INFO: pp_width calculated as " & integer'image(pp_width) severity note;
return pp_width;
end calc_pp_width;
------------------------------------------------------------------------------
-- Sometimes specified c_mem_type parameter is illegal. Check and change to a
-- legal value if necessary.
------------------------------------------------------------------------------
function get_mem_type(family : string;
mem_type : integer;
bram_addr_width : integer;
has_swapb : integer;
a_width : integer;
a_type : integer;
has_a_signed : integer;
b_constant : integer;
has_o : integer) return integer is
constant rom_addr_width : integer := get_rom_addr_width(family, mem_type);
constant a_input_width : integer := calc_a_input_width(a_width, has_a_signed, rom_addr_width, b_constant);
constant number_of_pps : integer := calc_num_pps(a_input_width, rom_addr_width);
constant need_addsub : boolean := b_constant = 0 and (a_type /= C_UNSIGNED or has_a_signed /= 0);
-- Single PP but need an addsub to negate result
constant need_0_minus_pp : boolean := need_addsub and number_of_pps <= 1;
constant number_of_adders : integer := select_val(number_of_pps-1, 1, need_0_minus_pp);
variable mem_type_i : integer;
begin
if mem_type /= C_DISTRIBUTED and has_swapb = 0 and has_o /= 0 and number_of_adders < 1 then
mem_type_i := C_DISTRIBUTED;
report "ERROR: CCM - the O output is not available with block memory " &
"and this parameter combination." & new_line &
" Select distributed memory if the O " &
"output is required in this case." & new_line
severity failure;
else
mem_type_i := mem_type;
end if;
return mem_type_i;
end get_mem_type;
-----------------------------------------------------------------------------
-- FUNCTIONS FROM CCM_UTILS_V9_0
-----------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Return number of bits required to represent the supplied parameter
--------------------------------------------------------------------------------
function bitsneededtorepresent(a_value : integer) return integer is--(a_value : natural) return natural is
variable return_value : integer := 1;
begin
for i in 30 downto 0 loop
if a_value >= 2**i then
return_value := i+1;
exit;
end if;
end loop;
return return_value;
end bitsneededtorepresent;
-------------------------------------------------------------------------------
-- bitstorep_bv updated by andreww 19th May 06 - Worked correctly with MTI 6.1e,
-- but not with XST I.31 - simplified code to ease debug
-- Assumes that the bit_vector a_value is a DOWNTO vector
-------------------------------------------------------------------------------
function bitstorep_bv(a_value : bit_vector;
a_type : integer;
a_positive : boolean) return integer is
variable str_rep : string(1 to a_value'length);
variable return_value : integer := a_value'length;
begin
-- assert not(ccm_debug) report "bitstorep_bv args " & slv_to_str(bv_to_slv(a_value)) & " " & integer'image(a_type) & " " & boolean'image(a_positive) severity note;
-- For VTFC support, we need to convert to a string before analysing the
-- vector. Only 'length, 'low and 'high are supported by VTFC at present.
-- Assumes that the bit_vector is DOWNTO and has LSB at index zero
for i in str_rep'low-1 to str_rep'high-1 loop
if a_value(i) = '1' then
str_rep(i+1) := '1';
elsif a_value(i) = '0' then
str_rep(i+1) := '0';
else
report "ERROR: mult_gen: non-binary value caught in bitstorep_bv"
severity failure;
end if;
end loop; -- i
if a_type = C_UNSIGNED then
-- str_rep represents an unsigned number
for i in str_rep'high downto str_rep'low loop
if str_rep(i) = '1' then
exit; -- EXIT when the msb is found
elsif str_rep(i) = '0' then
return_value := return_value - 1;
end if;
end loop;
else
-- str_rep represents a signed number
if a_positive then
-- Look for ms '1' then add 1 for a leading 0
for i in str_rep'high downto str_rep'low loop
if i-1 > 0 then
if str_rep(i) = '0' and str_rep(i-1) = '1' then
exit;
else
return_value := return_value - 1;
end if;
else
exit;
end if;
end loop; -- i
else
-- Look for ms '1' followed by a '0'
for i in str_rep'high downto str_rep'low loop
if i-1 > 0 then
if str_rep(i) = '1' and str_rep(i-1) = '0' then
exit;
else
return_value := return_value - 1;
end if;
else
exit;
end if;
end loop; -- i
end if; -- a_positive
end if;
if return_value <= 0 then
return 1;
elsif a_type /= c_unsigned and return_value <= 2 then
return 2; -- always need at least 2 bits to represent signed numbers
else
return return_value;
end if;
end bitstorep_bv;
--------------------------------------------------------------------------------
-- Convert STD_LOGIC_VECTOR to STRING
-- Assumes STRING is of type (n TO n+length-1) with MSB in 'n' position.
-- Returns STD_LOGIC_VECTOR of type (nbits-1 DOWNTO 0) with LSB in 0 position.
--------------------------------------------------------------------------------
function slv_to_str(bitsin : std_logic_vector; nbits : integer) return string is
variable ret : string(1 to nbits);
variable bit_num : integer;
begin
ret := (others => '0');
bit_num := 1;
for i in bitsin'range loop
if bitsin(i) = '1' then
ret(bit_num) := '1';
elsif bitsin(i) = '0' then
ret(bit_num) := '0';
elsif (bitsin(i) = 'L') then
ret(bit_num) := 'L';
elsif (bitsin(i) = 'H') then
ret(bit_num) := 'H';
elsif (bitsin(i) = 'Z') then
ret(bit_num) := 'Z';
elsif (bitsin(i) = 'W') then
ret(bit_num) := 'W';
elsif (bitsin(i) = 'U') then
ret(bit_num) := 'U';
elsif (bitsin(i) = 'X') then
ret(bit_num) := 'X';
elsif (bitsin(i) = '-') then
ret(bit_num) := '-';
else
report "ERROR: invalid character passed to slv_to_str function." &
new_line
severity failure;
end if;
bit_num := bit_num + 1;
if bit_num > nbits then
exit; -- Ignore ms bits in SLV if SLV is longer than STRING
end if;
end loop;
return ret;
end slv_to_str;
--------------------------------------------------------------------------------
-- Return i0 if sel = 0, i1 if sel = 1
--------------------------------------------------------------------------------
function mult_gen_max_of(i0, i1 : integer) return integer is
begin
if (i0 > i1) then
return i0;
else
return i1;
end if;
end mult_gen_max_of;
-------------------------------------------------------------------------------
-- function modified by andreww 13th May 06 - need to account for signed and
-- unsigned products
-------------------------------------------------------------------------------
use ieee.std_logic_signed.all;
function multiply_bv(a, b : bit_vector; a_signed, b_signed : boolean) return bit_vector is
constant a_slv : std_logic_vector(a'range) := to_stdlogicvector(a);
constant b_slv : std_logic_vector(b'range) := to_stdlogicvector(b);
variable ai : std_logic_vector(a'high+1 downto a'low);
variable bi : std_logic_vector(b'high+1 downto b'low);
variable prod : std_logic_vector(ai'length+bi'length-1 downto 0);
-- create an intermediate variable to assign the bit_vector into
-- if we don't do this and return directly from the to_bitvector function,
-- XST assumes that the returned bit_vector is (0 TO N-1) rather than the
-- (N-1 downto 0) that we require (and all other functions assume...)
variable prod_slv : std_logic_vector(a'length+b'length-1 downto 0);
variable prod_bv : bit_vector(a'length+b'length-1 downto 0);
begin
-- assert not(ccm_debug) report "multiply_bv args " & slv_to_str(bv_to_slv(a)) & " " & slv_to_str(bv_to_slv(b)) & " " & boolean'image(a_signed) & " " & boolean'image(b_signed) severity note;
-- -- Original code in v11.0 - this doesn't work with modelsim 6.4a/b (at least)
-- if a_signed then
-- ai := std_logic_vector(resize(signed(to_Stdlogicvector(a)), ai'length));
-- else
-- ai := std_logic_vector(resize(unsigned(to_Stdlogicvector(a)), ai'length));
-- end if;
-- if b_signed then
-- bi := std_logic_vector(resize(signed(to_Stdlogicvector(b)), bi'length));
-- else
-- bi := std_logic_vector(resize(unsigned(to_Stdlogicvector(b)), bi'length));
-- end if;
if a_signed then
ai := std_logic_vector(resize(signed(a_slv), ai'length));
else
ai := std_logic_vector(resize(unsigned(a_slv), ai'length));
end if;
if b_signed then
bi := std_logic_vector(resize(signed(b_slv), bi'length));
else
bi := std_logic_vector(resize(unsigned(b_slv), bi'length));
end if;
-- since we've manually sign- (or zero-) extended, we can perform a signed multiplication
prod := ieee.std_logic_signed."*"(ai, bi);
-- return only the necessary width - don't use the resize() function here as it can give the wrong results
prod_bv := to_bitvector(prod(a'length+b'length-1 downto 0)); -- this line doesn't work with VTFC - no arguments passed to to_bitvector
return prod_bv;
end multiply_bv;
--------------------------------------------------------------------------------
-- Convert NATURAL to BIT_VECTOR
-- The ls length bits of in_val are returned.
--------------------------------------------------------------------------------
function natural_to_bit_vector(in_val : in integer; length : in integer)
return bit_vector is
variable temp : integer := in_val;
variable result : bit_vector(length-1 downto 0) := (others => '0');
begin
result := to_bitvector(std_logic_vector(resize(to_unsigned(in_val, 32), length)));
return result;
end natural_to_bit_vector;
--------------------------------------------------------------------------------
-- Return i0 if sel = FALSE, i1 if sel = TRUE
--------------------------------------------------------------------------------
function mult_gen_select_string(i0 : string; i1 : string; sel : boolean)
return string is
begin
if sel then
return i1;
else
return i0;
end if; -- sel
end mult_gen_select_string;
--------------------------------------------------------------------------------
-- Return i0 if sel = FALSE, i1 if sel = TRUE
--------------------------------------------------------------------------------
function select_val(i0 : integer; i1 : integer; sel : boolean) return integer is
begin
if sel then
return i1;
else
return i0;
end if; -- sel
end select_val;
function select_val_int(i0 : integer; i1 : integer; sel : integer) return integer is
begin
if sel = 1 then
return i1;
else
return i0;
end if; -- sel
end select_val_int;
--------------------------------------------------------------------------------
-- Convert STRING to BIT_VECTOR
-- Assumes STRING is of type (n TO n+length-1) with MSB in 'n' position.
-- Returns BIT_VECTOR of type (nbits-1 DOWNTO 0) with LSB in 0 position.
--------------------------------------------------------------------------------
function mult_gen_str_to_bv(bitsin : string; nbits : integer) return bit_vector is
variable ret : bit_vector(nbits-1 downto 0);
variable bit_num : integer;
begin
ret := (others => '0');
if (bitsin'length = 0) then -- Make all '0's
return ret;
end if;
bit_num := 0;
-- FOR i IN bitsin'REVERSE_RANGE LOOP -- doesn't work with XCC
for i in bitsin'high downto bitsin'low loop
if bitsin(i) = '1' then
ret(bit_num) := '1';
elsif bitsin(i) = '0' then
ret(bit_num) := '0';
else
report "ERROR: non 0 or 1 character passed to mult_gen_str_to_bv function. String passed in was: " & bitsin
severity failure;
end if;
bit_num := bit_num + 1;
if bit_num >= nbits then
exit; -- Ignore ms characters in STRING if STRING is longer than BV
end if;
end loop;
return ret;
end mult_gen_str_to_bv;
function mult_gen_bv_to_str(bitsin : bit_vector; nbits : integer) return string is
variable ret : string(1 to bitsin'length);
variable bit_num : integer;
begin
ret := (others => '0');
if (bitsin'length = 0) then -- Make all '0's
return ret;
end if;
bit_num := 0;
for i in bitsin'high downto bitsin'low loop
if bitsin(i) = '1' then
ret(bit_num) := '1';
elsif bitsin(i) = '0' then
ret(bit_num) := '0';
else
report "ERROR: non 0 or 1 character passed to mult_gen_bv_to_str function"
severity failure;
end if;
bit_num := bit_num + 1;
if bit_num >= nbits then
exit; -- Ignore ms characters in bit_vector if bit_vector is longer than string
end if;
end loop;
return ret;
end mult_gen_bv_to_str;
-----------------------------------------------------------------------------
-- functions imported from ccm_mem_utils_v9.0.vhd
function calc_depth(reqd_depth : integer; mem_type : integer) return integer is
variable extra : integer := 0;
variable addr_width : integer := bitsneededtorepresent(reqd_depth-1);
begin
if mem_type = c_distributed then
extra := reqd_depth mod 2**addr_width; --16;
if (extra = 0) then
return reqd_depth;
else
return (reqd_depth + (2**addr_width) - extra); --16 - extra);
end if;
else
-- Must be block mem. Block mems must be 16, 32, 64, 128, 256 or n * 256 deep
if reqd_depth <= 16 then
return 16;
elsif reqd_depth <= 256 then
return 2**(bitsneededtorepresent(reqd_depth-1));
else
return 256 + (256 * ((reqd_depth-1)/256));
end if; -- reqd_depth
end if; -- mem_type
end calc_depth;
-----------------------------------------------------------------------------
-- Resource estimation functions to be converted by VTFC
-----------------------------------------------------------------------------
-- purpose: this routine works out the LUT count for the LUT multiplier in a
-- LUT4 binary adder structure and is accurate to +/- 1-% of characterisation data
function calc_lut_mult_resources (c_a_width, c_b_width : integer) return integer is
-- calculation variables
variable opa : integer := 0;
variable opb : integer := 0;
variable PPs : integer := 0;
variable carrychainlength : integer := 0;
variable treestages : integer := 0;
variable stage1adders, stage2adders, stage3adders, stage4adders, stage5adders : integer := 0;
-- the final return value
variable lutcount : integer := 0;
begin -- function calc_lut_mult_resources
opa := mult_gen_max_of(c_a_width, c_b_width);
opb := get_min(c_a_width, c_b_width);
assert not(debug) report " opa is " & integer'image(opa);
assert not(debug) report " opb is " & integer'image(opb);
-- work out how many PP generators there are
if (opb mod 2) /= 0 then
PPs := (opb+1)/2;
else
PPs := opb / 2;
end if;
carrychainlength := opa + 2;
-- Set the lut count for the PP generators to be rounded down if PPs is odd
-- - the LUTs will be sucked into the adder tree
if opb > 1 then
lutcount := (opb / 2) * carrychainlength;
else
lutcount := opa;
end if;
if (opb mod 2) /= 0 and PPs > 1 then
lutcount := lutcount + opb;
end if;
case PPs is
when 1 => treestages := 0;
when 2 => treestages := 1;
when 3 to 4 => treestages := 2;
when 5 to 8 => treestages := 3;
when 9 to 16 => treestages := 4;
when 17 to 32 => treestages := 5;
when others => null;
end case;
case PPs is
when 1 =>
stage1adders := 0;
stage2adders := 0;
stage3adders := 0;
stage4adders := 0;
stage5adders := 0;
when 2 =>
stage1adders := 1;
stage2adders := 0;
stage3adders := 0;
stage4adders := 0;
stage5adders := 0;
when 3 =>
stage1adders := 1;
stage2adders := 1;
stage3adders := 0;
stage4adders := 0;
stage5adders := 0;
when 4 =>
stage1adders := 2;
stage2adders := 1;
stage3adders := 0;
stage4adders := 0;
stage5adders := 0;
when 5 =>
stage1adders := 2;
stage2adders := 1;
stage3adders := 1;
stage4adders := 0;
stage5adders := 0;
when 6 =>
stage1adders := 3;
stage2adders := 1;
stage3adders := 1;
stage4adders := 0;
stage5adders := 0;
when 7 =>
stage1adders := 3;
stage2adders := 2;
stage3adders := 1;
stage4adders := 0;
stage5adders := 0;
when 8 =>
stage1adders := 4;
stage2adders := 2;
stage3adders := 1;
stage4adders := 0;
stage5adders := 0;
when 9 =>
stage1adders := 4;
stage2adders := 2;
stage3adders := 1;
stage4adders := 1;
stage5adders := 0;
when 10 =>
stage1adders := 5;
stage2adders := 2;
stage3adders := 1;
stage4adders := 1;
stage5adders := 0;
when 11 =>
stage1adders := 5;
stage2adders := 2;
stage3adders := 2;
stage4adders := 1;
stage5adders := 0;
when 12 =>
stage1adders := 6;
stage2adders := 3;
stage3adders := 2;
stage4adders := 1;
stage5adders := 0;
when 13 =>
stage1adders := 6;
stage2adders := 3;
stage3adders := 2;
stage4adders := 1;
stage5adders := 0;
when 14 =>
stage1adders := 7;
stage2adders := 2;
stage3adders := 2;
stage4adders := 1;
stage5adders := 0;
when 15 =>
stage1adders := 7;
stage2adders := 3;
stage3adders := 2;
stage4adders := 1;
stage5adders := 0;
when 16 =>
stage1adders := 8;
stage2adders := 4;
stage3adders := 2;
stage4adders := 1;
stage5adders := 0;
when 17 =>
stage1adders := 8;
stage2adders := 4;
stage3adders := 2;
stage4adders := 1;
stage5adders := 1;
when 18 =>
stage1adders := 9;
stage2adders := 4;
stage3adders := 2;
stage4adders := 1;
stage5adders := 1;
when 19 =>
stage1adders := 9;
stage2adders := 5;
stage3adders := 2;
stage4adders := 1;
stage5adders := 1;
when 20 =>
stage1adders := 10;
stage2adders := 5;
stage3adders := 2;
stage4adders := 1;
stage5adders := 1;
when 21 =>
stage1adders := 10;
stage2adders := 5;
stage3adders := 3;
stage4adders := 1;
stage5adders := 1;
when 22 =>
stage1adders := 11;
stage2adders := 6;
stage3adders := 3;
stage4adders := 1;
stage5adders := 1;
when 23 =>
stage1adders := 11;
stage2adders := 6;
stage3adders := 3;
stage4adders := 2;
stage5adders := 1;
when 24 =>
stage1adders := 12;
stage2adders := 6;
stage3adders := 3;
stage4adders := 1;
stage5adders := 1;
when 25 =>
stage1adders := 12;
stage2adders := 7;
stage3adders := 3;
stage4adders := 1;
stage5adders := 1;
when 26 =>
stage1adders := 13;
stage2adders := 7;
stage3adders := 3;
stage4adders := 1;
stage5adders := 1;
when 27 =>
stage1adders := 13;
stage2adders := 7;
stage3adders := 3;
stage4adders := 2;
stage5adders := 1;
when 28 =>
stage1adders := 14;
stage2adders := 7;
stage3adders := 3;
stage4adders := 2;
stage5adders := 1;
when 29 =>
stage1adders := 14;
stage2adders := 7;
stage3adders := 4;
stage4adders := 2;
stage5adders := 1;
when 30 =>
stage1adders := 15;
stage2adders := 7;
stage3adders := 4;
stage4adders := 2;
stage5adders := 1;
when 31 =>
stage1adders := 15;
stage2adders := 8;
stage3adders := 4;
stage4adders := 2;
stage5adders := 1;
when 32 =>
stage1adders := 16;
stage2adders := 8;
stage3adders := 4;
stage4adders := 2;
stage5adders := 1;
when others => null;
end case;
lutcount := lutcount + (stage1adders * carrychainlength);
lutcount := lutcount + (stage2adders * (carrychainlength+2));
lutcount := lutcount + (stage3adders * (carrychainlength+2+4));
lutcount := lutcount + (stage4adders * (carrychainlength+2+4+8));
lutcount := lutcount + (stage5adders * (carrychainlength+2+4+8+16));
return lutcount;
end function calc_lut_mult_resources;
-- purpose: Calculates number of embedded multipliers used to build a
-- hybrid multiplier
function calc_hybrid_emb_mults (
family : string;
op_width : WIDTH_REC) return integer is
variable a_pp : integer := hybrid_calc_a_pp(family, op_width);
variable b_pp : integer := hybrid_calc_b_pp(family, op_width);
variable mults : integer := 0;
begin -- function calc_hybrid_emb_mults
mults := a_pp * b_pp;
return mults;
end function calc_hybrid_emb_mults;
-- purpose: calculates roughly how many LUTs are used in building a given
-- hybrid multiplier
function calc_hybrid_luts (
family : string;
op_width : WIDTH_REC) return integer is
-- calculation variables and constants
constant BASE_MULT : integer := 0;
constant ONE_MULT : integer := 1;
constant TWO_MULT : integer := 2;
constant wire_shift : integer := 17;
-- set up the port sizes for all families
constant port_size : PORT_ASPECTS := (a => 18+(7*boolean'pos(supports_dsp48e(family) > 0)), b => 18, m => 36+(7*boolean'pos(supports_dsp48e(family) > 0)), c => 48, p => 48);
variable hybrid_cfg : integer := 0;
variable a_pp : integer := 0;
variable b_pp : integer := 0;
variable top_mult_a_width : integer := 0;
variable top_mult_b_width : integer := 0;
variable side_mult_a_width : integer := 0;
variable side_mult_b_width : integer := 0;
variable block_a_width : integer := 0;
variable block_b_width : integer := 0;
variable a_port_size : integer := 0;
variable b_port_size : integer := 0;
variable x_width : integer := 0;
variable y_width : integer := 0;
variable block_a_type : integer := 0;
variable block_b_type : integer := 0;
variable largest_output : integer := 0;
-- final return value
variable lutcount : integer := 0;
begin -- function calc_hybrid_luts
---------------------------------------------------------------------------
-- This code was translated from the Tcl's calc_hybrid_lut_mult_dimensions()
---------------------------------------------------------------------------
a_pp := hybrid_calc_a_pp(family, op_width);
b_pp := hybrid_calc_b_pp(family, op_width);
a_port_size := mult_gen_max_of(op_width.a, port_size.a);
b_port_size := mult_gen_max_of(op_width.b, port_size.b);
if a_pp = 1 and b_pp = 1 then
-- one mult block
block_a_width := a_port_size;
if op_width.a_type = C_UNSIGNED and op_width.a >= port_size.a then
block_a_width := block_a_width - 1;
end if;
block_b_width := port_size.b;
if op_width.b_type = C_UNSIGNED and op_width.b >= port_size.b then
block_b_width := block_b_width - 1;
end if;
block_a_type := op_width.a_type;
block_b_type := op_width.b_type;
elsif a_pp = 2 and b_pp = 1 then
-- two mult blocks
block_a_width := port_size.a+wire_shift;
if op_width.a_type = C_UNSIGNED and op_width.a >= port_size.a then
block_a_width := block_a_width - 1;
end if;
block_b_width := port_size.b;
if op_width.b_type = C_UNSIGNED and op_width.b >= port_size.b then
block_b_width := block_b_width - 1;
end if;
block_a_type := op_width.a_type;
block_b_type := op_width.b_type;
elsif a_pp = 1 and b_pp = 2 then
-- two mult blocks
-- The operands will be swapped arund so that the A operand is the
-- largest. This means that we need to swap the a_type and b_type values over
-- so that they remain correct w.r.t. the operand widths
block_a_width := port_size.b+wire_shift;
if op_width.a_type = C_UNSIGNED then
block_a_width := block_a_width - 1;
end if;
block_b_width := port_size.a;
if op_width.b_type = C_UNSIGNED then
block_b_width := block_b_width - 1;
end if;
-- REVISIT: andreww: is there a bug here? should these values be swapped?
block_a_type := op_width.a_type;
block_b_type := op_width.b_type;
elsif a_pp = 2 and b_pp = 2 then
-- four mult blocks
block_a_width := port_size.a+wire_shift;
if op_width.a_type = C_UNSIGNED then
block_a_width := block_a_width - 1;
end if;
block_b_width := port_size.b+wire_shift;
if op_width.b_type = C_UNSIGNED then
block_b_width := block_b_width - 1;
end if;
block_a_type := op_width.a_type;
block_b_type := op_width.b_type;
end if;
hybrid_cfg := get_hybrid_configuration(family, a_pp, b_pp, op_width, port_size);
x_width := block_a_width;
y_width := block_b_width;
if (op_width.a > x_width and (op_width.b <= y_width or y_width < port_size.b)) and hybrid_cfg = ONE_MULT then
top_mult_a_width := op_width.a - x_width;
top_mult_b_width := op_width.b;
end if;
if (op_width.a <= x_width and (op_width.b > y_width or y_width < port_size.b)) and hybrid_cfg = ONE_MULT then
top_mult_a_width := op_width.a;
top_mult_b_width := op_width.b - y_width;
end if;
-- set up cfg for two LUT mults
-- this is the code from get_two_mult_cfg in the HDL
-- Also need to account for the fabric adder here
if op_width.a >= x_width and op_width.b >= y_width and hybrid_cfg = TWO_MULT then
-- The code above will automatically swap the operands so that the largest is
-- on the A bus. Because we only make 2 cuts in the partial product
-- array, this means that we want to make the A operand shorter than the B
-- operand to balance out the carry chain lengths for e.g. 22x20 multipliers
-- top fabric mult
top_mult_a_width := x_width;
top_mult_b_width := op_width.b - y_width;
-- side fabric mult
side_mult_a_width := op_width.a - x_width;
side_mult_b_width := op_width.b;
elsif op_width.b >= x_width and op_width.a >= y_width and hybrid_cfg = TWO_MULT then
-- top fabric mult
top_mult_a_width := y_width;
top_mult_b_width := op_width.b - x_width;
-- side fabric mult
side_mult_a_width := op_width.a - x_width;
side_mult_b_width := op_width.b;
end if;
---------------------------------------------------------------------------
-- End code translated from the Tcl's calc_hybrid_lut_mult_dimensions()
---------------------------------------------------------------------------
if hybrid_cfg = ONE_MULT then
lutcount := calc_lut_mult_resources(top_mult_a_width, top_mult_b_width);
elsif hybrid_cfg = TWO_MULT then
lutcount := (calc_lut_mult_resources(top_mult_a_width, top_mult_b_width)) + (calc_lut_mult_resources(side_mult_a_width, side_mult_b_width));
end if;
if hybrid_cfg = TWO_MULT then
if supports_dsp48e(family) > 0 or supports_dsp48(family) = 1 or supports_dsp48a(family) > 0 then
-- Use the LS adder - no extra logic unless it's a TWO_MULT case
largest_output := mult_gen_max_of(top_mult_a_width+top_mult_b_width, side_mult_a_width+side_mult_b_width);
-- add in the LUTs (roughly) for the adder bringing together the two fabric PPs
lutcount := lutcount + largest_output + 1;
else
-- Virtex-2, Spartan-3 etc. - always require at least 1 extra adder, two if it's a TWO_MULT configuration
largest_output := mult_gen_max_of(top_mult_a_width+top_mult_b_width, side_mult_a_width+side_mult_b_width);
-- add in the LUTs (roughly) fo rthe adder bringing together the two fabric PPs
lutcount := lutcount + largest_output + 1;
-- now add in the LUTs for the adder which brings together the output
-- of the large mult - this shoudl be 1 bit more than the output width of the
-- embedded mult part
lutcount := lutcount + block_a_width + block_b_width;
end if;
end if;
return lutcount;
end function calc_hybrid_luts;
-- purpose: works out how many embedded multipliers (DSPs or 18x18s) will be
-- used for a particular configuration
function calc_emb_mults (
family : string;
op_width : WIDTH_REC) return integer is
variable dsp_pps : R_DSP_PP;
variable a_pp, b_pp : integer := 0;
variable mults : integer := 0;
begin -- function calc_emb_mults
assert not(fn_debug) report "entered calc_emb_mults" severity note;
if has_dsp(family) then
assert not(fn_debug) report "calling calc_dsp48_pps for DSPs" severity note;
dsp_pps := calc_dsp48_pps(family, op_width);
mults := (dsp_pps.a_pp * dsp_pps.b_pp) + dsp_pps.extra_b_pp;
else
a_pp := calc_a_pp(family, op_width);
b_pp := calc_b_pp(op_width);
mults := a_pp * b_pp;
end if;
assert not(fn_debug) report "leaving calc_emb_mults" severity note;
return mults;
end function calc_emb_mults;
function calc_reqd_b_width (c_b_value : string; c_b_width, c_b_type : integer; reloadable : boolean) return integer is
begin
return select_val (c_b_width, bitstorep_string(c_b_value, c_b_type), not(reloadable));
end function calc_reqd_b_width;
function mult_gen_v11_2_luts (
family : string;
c_a_width : integer;
c_a_type : integer;
c_b_width : integer;
c_b_type : integer;
c_mult_type : integer;
c_optimize_goal : integer;
c_latency : integer;
c_ccm_imp : integer;
c_b_value : string)
return integer is
constant rec : R_MULT_RESOURCES := mult_gen_v11_2_gui_resources(family, c_a_width, c_a_type, c_b_width, c_b_type, c_mult_type, c_optimize_goal, c_latency, c_ccm_imp, c_b_value);
constant luts : integer := rec.LUTs;
begin
return luts;
end function mult_gen_v11_2_luts;
function mult_gen_v11_2_mults (
family : string;
c_a_width : integer;
c_a_type : integer;
c_b_width : integer;
c_b_type : integer;
c_mult_type : integer;
c_optimize_goal : integer;
c_latency : integer;
c_ccm_imp : integer;
c_b_value : string)
return integer is
constant rec : R_MULT_RESOURCES := mult_gen_v11_2_gui_resources(family, c_a_width, c_a_type, c_b_width, c_b_type, c_mult_type, c_optimize_goal, c_latency, c_ccm_imp, c_b_value);
constant mults : integer := rec.MULT18X18s + rec.DSPs; -- only one of these values will be non-zero
begin
return mults;
end function mult_gen_v11_2_mults;
function mult_gen_v11_2_brams (
family : string;
c_a_width : integer;
c_a_type : integer;
c_b_width : integer;
c_b_type : integer;
c_mult_type : integer;
c_optimize_goal : integer;
c_latency : integer;
c_ccm_imp : integer;
c_b_value : string)
return integer is
constant rec : R_MULT_RESOURCES := mult_gen_v11_2_gui_resources(family, c_a_width, c_a_type, c_b_width, c_b_type, c_mult_type, c_optimize_goal, c_latency, c_ccm_imp, c_b_value);
constant brams : integer := rec.BRAMs;
begin
return brams;
end function mult_gen_v11_2_brams;
-- purpose: calculates the FPGA resources for all supported multiplier configurations
-- For use with VTFC to provide resource counts in the mult_gen CoreGen GUI
function mult_gen_v11_2_gui_resources (
family : string;
c_a_width : integer;
c_a_type : integer;
c_b_width : integer;
c_b_type : integer;
c_mult_type : integer;
c_optimize_goal : integer;
c_latency : integer;
c_ccm_imp : integer;
c_b_value : string)
return R_MULT_RESOURCES is
-- The values we will eventually return
variable mult_resources : R_MULT_RESOURCES := (LUTs => 0, DSPs => 0, MULT18X18s => 0, BRAMs => 0);
-- Intermediate variables and constants
constant port_size : PORT_ASPECTS := get_port_sizes(family);
constant op_width : WIDTH_REC := get_true_widths(family, c_a_width, c_b_width, c_a_type, c_b_type, port_size);
constant reloadable : boolean := false;
variable number_of_pps : integer := 0;
variable pp_width : integer := 0;
variable last_pp_width : integer := 0;
variable need_addsub : boolean := false;
variable need_0_minus_pp : boolean := false;
variable trimmed_msbs : integer := 0;
variable trimmed_lsbs : integer := 0;
variable num_brams : integer := 0;
variable adder_luts : integer := 0;
variable b_length : integer := 0;
variable new_b_width : integer := 0;
variable largest_pp : integer := 0;
variable reqd_b_value : string(1 to calc_reqd_b_width(c_b_value, c_b_width, c_b_type, false));
variable number_of_adders : integer := 0;
begin -- function mult_gen_v11_2_gui_resources
assert not(fn_debug) report "entered mult_gen_v11_2_gui_resources" severity note;
case c_mult_type is
when LUT =>
mult_resources.LUTs := calc_lut_mult_resources(c_a_width, c_b_width);
mult_resources.DSPs := 0;
mult_resources.MULT18X18s := 0;
mult_resources.BRAMs := 0;
when EMBEDDED_MULT =>
if supports_dsp48e(family) > 0 or supports_dsp48(family) = 1 or supports_dsp48a(family) > 0 then
-- DSP-based implementations
case c_optimize_goal is
when EMB_MULT_RESOURCES =>
assert false report "WARNING: The LUT results (maybe also the DSP result) will be wrong because the widths need to swapped so A is largest" severity warning;
mult_resources.DSPs := calc_hybrid_emb_mults(family, op_width);
mult_resources.LUTs := calc_hybrid_luts(family, op_width);
mult_resources.MULT18X18s := 0;
mult_resources.BRAMs := 0;
when CORE_SPEED =>
assert not(fn_debug) report "calling calc_emb_mults" severity note;
mult_resources.DSPs := calc_emb_mults(family, op_width);
mult_resources.LUTs := 0;
mult_resources.MULT18X18s := 0;
mult_resources.BRAMs := 0;
when others =>
null;
end case;
else
case c_optimize_goal is
-- Mult18x18-based implementations
when EMB_MULT_RESOURCES =>
assert false report "WARNING: The LUT results (maybe also the DSP result) will be wrong because the widths need to swapped so A is largest" severity warning;
mult_resources.DSPs := 0;
mult_resources.LUTs := calc_hybrid_luts(family, op_width);
mult_resources.MULT18X18s := calc_hybrid_emb_mults(family, op_width);
mult_resources.BRAMs := 0;
when CORE_SPEED =>
mult_resources.DSPs := 0;
mult_resources.LUTs := 0;
mult_resources.MULT18X18s := calc_emb_mults(family, op_width);
mult_resources.BRAMs := 0;
when others =>
null;
end case;
end if;
when FIXED_CCM =>
if check_const_power_of_two(c_b_value, c_b_type, c_mult_type) then
-- constant is a power of two
mult_resources.DSPs := 0;
mult_resources.LUTs := 0;
mult_resources.MULT18X18s := 0;
mult_resources.BRAMS := 0;
else
case c_ccm_imp is
when DIST_MEM =>
mult_resources.DSPs := 0;
mult_resources.MULT18X18s := 0;
mult_resources.BRAMs := 0;
number_of_pps := calc_num_pps(calc_a_input_width(c_b_width, 0, get_rom_addr_width(family, c_ccm_imp), 1), get_rom_addr_width(family, c_ccm_imp));
pp_width := calc_pp_width(c_b_width, c_b_type, c_b_value, 1, c_a_width, c_a_type, 0, false, false);
last_pp_width := calc_pp_width(c_b_width, c_b_type, c_b_value, 1, c_a_width, c_a_type, 0, true, false);
need_addsub := false;
need_0_minus_pp := false;
number_of_adders := select_val(number_of_pps-1, 1, need_0_minus_pp);
adder_luts := (number_of_adders * mult_gen_max_of(pp_width, last_pp_width));
mult_resources.LUTs := ((number_of_pps-1)*pp_width) + last_pp_width + adder_luts;
when BRAM =>
mult_resources.DSPs := 0;
mult_resources.MULT18X18s := 0;
number_of_pps := calc_num_pps(calc_a_input_width(c_b_width, 0, get_rom_addr_width(family, c_ccm_imp), 1), get_rom_addr_width(family, c_ccm_imp));
pp_width := calc_pp_width(c_b_width, c_b_type, c_b_value, 1, c_a_width, c_a_type, 0, false, false);
last_pp_width := calc_pp_width(c_b_width, c_b_type, c_b_value, 1, c_a_width, c_a_type, 0, true, false);
need_addsub := false;
need_0_minus_pp := false;
number_of_adders := select_val(number_of_pps-1, 1, need_0_minus_pp);
num_brams := (number_of_pps + 1) / 2;
if num_brams > 1 then
largest_pp := mult_gen_max_of(pp_width, last_pp_width);
adder_luts := (number_of_adders * largest_pp) - (largest_pp / 2);
else
adder_luts := 0;
end if;
mult_resources.LUTs := adder_luts;
if supports_dsp48e(family) > 0 then
-- we can pack 2x 18K BRAMs into a 36K BRAM, so need further division here to give
-- true number of BRAM blocks - need to round up to account for odd # BRAMs
-- This will indicate that a whole 36K is used, even though only half may actually be
if num_brams > 1 then
mult_resources.BRAMs := (num_brams + 1) / 2;
end if;
else
mult_resources.BRAMs := num_brams;
end if;
when MULTS =>
reqd_b_value := calc_reqd_b_value(c_b_value, c_b_width, c_b_type, calc_reqd_b_width(c_b_value, c_b_width, c_b_type, false));
b_length := reqd_b_value'length;
trimmed_msbs := get_trimmed_leading_bits(c_b_value, c_b_type, c_mult_type);
trimmed_lsbs := calc_shift_bits(reqd_b_value, 1);
new_b_width := b_length - (trimmed_msbs + trimmed_lsbs);
mult_resources.BRAMS := 0;
if supports_dsp48e(family) > 0 or supports_dsp48(family) = 1 or supports_dsp48a(family) > 0 then
mult_resources.DSPs := calc_emb_mults(family, op_width);
mult_resources.MULT18X18s := 0;
mult_resources.LUTs := 0;
else
mult_resources.DSPs := 0;
mult_resources.MULT18X18s := calc_emb_mults(family, op_width);
mult_resources.LUTs := 0;
end if;
when others =>
null;
end case;
end if;
when others =>
null;
end case;
return mult_resources;
end function mult_gen_v11_2_gui_resources;
function get_port_sizes (family : string) return PORT_ASPECTS is
variable port_size : PORT_ASPECTS;
begin
-- set up the port sizes for all families
port_size.a := 18+(7*boolean'pos(supports_dsp48e(family) > 0));
port_size.b := 18;
port_size.m := 36+(7*boolean'pos(supports_dsp48e(family) > 0));
port_size.c := 48;
port_size.p := 48;
return port_size;
end function get_port_sizes;
end package body mult_gen_pkg_v11_2;
| gpl-3.0 | 1b39da26d64ffe8af673142b418fec2a | 0.545869 | 3.716255 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_Onchip_Memory.vhd | 1 | 5,784 | --Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.all;
entity Video_System_Onchip_Memory is
generic (
INIT_FILE : STRING := "../Video_System_Onchip_Memory.hex"
);
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal chipselect : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal clken : IN STD_LOGIC;
signal reset : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity Video_System_Onchip_Memory;
architecture europa of Video_System_Onchip_Memory is
--synthesis translate_off
component altsyncram is
GENERIC (
byte_size : NATURAL;
init_file : STRING;
lpm_type : STRING;
maximum_depth : NATURAL;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_reg_a : STRING;
ram_block_type : STRING;
read_during_write_mode_mixed_ports : STRING;
width_a : NATURAL;
width_byteena_a : NATURAL;
widthad_a : NATURAL
);
PORT (
signal q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal wren_a : IN STD_LOGIC;
signal byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal clock0 : IN STD_LOGIC;
signal address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal clocken0 : IN STD_LOGIC;
signal data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component altsyncram;
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- component altsyncram is
--GENERIC (
-- byte_size : NATURAL;
-- init_file : STRING;
-- lpm_type : STRING;
-- maximum_depth : NATURAL;
-- numwords_a : NATURAL;
-- operation_mode : STRING;
-- outdata_reg_a : STRING;
-- ram_block_type : STRING;
-- read_during_write_mode_mixed_ports : STRING;
-- width_a : NATURAL;
-- width_byteena_a : NATURAL;
-- widthad_a : NATURAL
-- );
-- PORT (
-- signal q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
-- signal wren_a : IN STD_LOGIC;
-- signal byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
-- signal clock0 : IN STD_LOGIC;
-- signal address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- signal clocken0 : IN STD_LOGIC;
-- signal data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
-- );
-- end component altsyncram;
--synthesis read_comments_as_HDL off
signal internal_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal wren : STD_LOGIC;
begin
wren <= chipselect AND write;
--s1, which is an e_avalon_slave
--s2, which is an e_avalon_slave
--vhdl renameroo for output signals
readdata <= internal_readdata;
--synthesis translate_off
the_altsyncram : altsyncram
generic map(
byte_size => 8,
init_file => INIT_FILE,
lpm_type => "altsyncram",
maximum_depth => 4096,
numwords_a => 4096,
operation_mode => "SINGLE_PORT",
outdata_reg_a => "UNREGISTERED",
ram_block_type => "AUTO",
read_during_write_mode_mixed_ports => "DONT_CARE",
width_a => 32,
width_byteena_a => 4,
widthad_a => 12
)
port map(
address_a => address,
byteena_a => byteenable,
clock0 => clk,
clocken0 => clken,
data_a => writedata,
q_a => internal_readdata,
wren_a => wren
);
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- the_altsyncram : altsyncram
-- generic map(
-- byte_size => 8,
-- init_file => "Video_System_Onchip_Memory.hex",
-- lpm_type => "altsyncram",
-- maximum_depth => 4096,
-- numwords_a => 4096,
-- operation_mode => "SINGLE_PORT",
-- outdata_reg_a => "UNREGISTERED",
-- ram_block_type => "AUTO",
-- read_during_write_mode_mixed_ports => "DONT_CARE",
-- width_a => 32,
-- width_byteena_a => 4,
-- widthad_a => 12
-- )
-- port map(
-- address_a => address,
-- byteena_a => byteenable,
-- clock0 => clk,
-- clocken0 => clken,
-- data_a => writedata,
-- q_a => internal_readdata,
-- wren_a => wren
-- );
--
--synthesis read_comments_as_HDL off
end europa;
| gpl-2.0 | e5ff5240223bdd89c512c914487d9646 | 0.58316 | 3.916046 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_Clock_Signals.vhd | 1 | 11,277 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
USE ieee.numeric_std.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module generates the clocks needed for the I/O devices on *
-- * Altera's DE-series boards. *
-- * *
-- ******************************************************************************
ENTITY Video_System_Clock_Signals IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
CLOCK_50 :IN STD_LOGIC;
reset :IN STD_LOGIC;
-- Bidirectionals
-- Outputs
VGA_CLK :BUFFER STD_LOGIC;
sys_clk :BUFFER STD_LOGIC;
sys_reset_n :BUFFER STD_LOGIC
);
END Video_System_Clock_Signals;
ARCHITECTURE Behaviour OF Video_System_Clock_Signals IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
CONSTANT SYS_CLK_MULT :INTEGER := 1;
CONSTANT SYS_CLK_DIV :INTEGER := 1;
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
SIGNAL sys_mem_clks :STD_LOGIC_VECTOR( 2 DOWNTO 0);
SIGNAL clk_locked :STD_LOGIC;
SIGNAL video_in_clk :STD_LOGIC;
SIGNAL SDRAM_CLK :STD_LOGIC;
-- Internal Registers
-- State Machine Registers
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
COMPONENT altpll
GENERIC (
clk0_divide_by :INTEGER;
clk0_duty_cycle :INTEGER;
clk0_multiply_by :INTEGER;
clk0_phase_shift :STRING;
clk1_divide_by :INTEGER;
clk1_duty_cycle :INTEGER;
clk1_multiply_by :INTEGER;
clk1_phase_shift :STRING;
clk2_divide_by :INTEGER;
clk2_duty_cycle :INTEGER;
clk2_multiply_by :INTEGER;
clk2_phase_shift :STRING;
compensate_clock :STRING;
gate_lock_signal :STRING;
inclk0_input_frequency :INTEGER;
intended_device_family :STRING;
invalid_lock_multiplier :INTEGER;
lpm_type :STRING;
operation_mode :STRING;
pll_type :STRING;
port_activeclock :STRING;
port_areset :STRING;
port_clkbad0 :STRING;
port_clkbad1 :STRING;
port_clkloss :STRING;
port_clkswitch :STRING;
port_fbin :STRING;
port_inclk0 :STRING;
port_inclk1 :STRING;
port_locked :STRING;
port_pfdena :STRING;
port_pllena :STRING;
port_scanaclr :STRING;
port_scanclk :STRING;
port_scandata :STRING;
port_scandataout :STRING;
port_scandone :STRING;
port_scanread :STRING;
port_scanwrite :STRING;
port_clk0 :STRING;
port_clk1 :STRING;
port_clk2 :STRING;
port_clk3 :STRING;
port_clk4 :STRING;
port_clk5 :STRING;
port_clkena0 :STRING;
port_clkena1 :STRING;
port_clkena2 :STRING;
port_clkena3 :STRING;
port_clkena4 :STRING;
port_clkena5 :STRING;
port_enable0 :STRING;
port_enable1 :STRING;
port_extclk0 :STRING;
port_extclk1 :STRING;
port_extclk2 :STRING;
port_extclk3 :STRING;
port_extclkena0 :STRING;
port_extclkena1 :STRING;
port_extclkena2 :STRING;
port_extclkena3 :STRING;
port_sclkout0 :STRING;
port_sclkout1 :STRING;
valid_lock_multiplier :INTEGER
);
PORT (
-- Inputs
inclk :IN STD_LOGIC_VECTOR( 1 DOWNTO 0);
-- Outputs
clk :BUFFER STD_LOGIC_VECTOR( 2 DOWNTO 0);
locked :BUFFER STD_LOGIC
);
END COMPONENT;
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
-- Output Registers
-- Internal Registers
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
sys_reset_n <= clk_locked;
sys_clk <= sys_mem_clks(0);
SDRAM_CLK <= sys_mem_clks(1);
VGA_CLK <= sys_mem_clks(2);
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
DE_Clock_Generator_System : altpll
GENERIC MAP (
clk0_divide_by => SYS_CLK_DIV,
clk0_duty_cycle => 50,
clk0_multiply_by => SYS_CLK_MULT,
clk0_phase_shift => "0",
clk1_divide_by => SYS_CLK_DIV,
clk1_duty_cycle => 50,
clk1_multiply_by => SYS_CLK_MULT,
clk1_phase_shift => "-3000",
clk2_divide_by => 2,
clk2_duty_cycle => 50,
clk2_multiply_by => 1,
clk2_phase_shift => "20000",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "FAST",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_enable0 => "PORT_UNUSED",
port_enable1 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
port_extclkena0 => "PORT_UNUSED",
port_extclkena1 => "PORT_UNUSED",
port_extclkena2 => "PORT_UNUSED",
port_extclkena3 => "PORT_UNUSED",
port_sclkout0 => "PORT_UNUSED",
port_sclkout1 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
-- Inputs
inclk => '0' & CLOCK_50,
-- Outputs
clk => sys_mem_clks,
locked => clk_locked
);
END Behaviour;
| gpl-2.0 | b63e16d1dac221ae9ca7c78720b177f0 | 0.470515 | 3.914266 | false | false | false | false |
DreamIP/GPStudio | support/toolchain/caph/hdl/caph_toplevel/src/bus2caph.vhd | 1 | 3,416 | -- **************************************************************************
-- bus2caph
-- **************************************************************************
-- 03/12/2014
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-- entity "uses" the package
--use work.ComFlow_pkg.all;
use work.caph_flow_pkg.caph_ports_t;
entity bus2caph is
generic (
NB_PORTS:positive := 0
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- quartus declaration
addr_i : in std_logic_vector(3 DOWNTO 0);
wr_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
enable_o : out std_logic;
-- port_o : out std_logic_vector(31 downto 0);
ports: out caph_ports_t;
imwidth_o : out std_logic_vector(31 downto 0);
imheight_o : out std_logic_vector(31 downto 0)
);
end bus2caph;
architecture rtl of bus2caph is
constant ENABLE_0_REG_ADDR : std_logic_vector(3 downto 0) := X"0";
constant IMWIDTH_REG_ADDR : std_logic_vector(3 downto 0) := X"1";
constant IMHEIGHT_REG_ADDR : std_logic_vector(3 downto 0) := X"2";
-- Listes des ports utilisées dans caph
constant PORT_k0_REG_ADDR : std_logic_vector(3 downto 0) := X"3";
constant PORT_k1_REG_ADDR : std_logic_vector(3 downto 0) := X"4";
constant PORT_k2_REG_ADDR : std_logic_vector(3 downto 0) := X"5";
constant PORT_k3_REG_ADDR : std_logic_vector(3 downto 0) := X"6";
constant PORT_k4_REG_ADDR : std_logic_vector(3 downto 0) := X"7";
constant PORT_k5_REG_ADDR : std_logic_vector(3 downto 0) := X"8";
constant PORT_k6_REG_ADDR : std_logic_vector(3 downto 0) := X"9";
constant PORT_k7_REG_ADDR : std_logic_vector(3 downto 0) := X"A";
constant PORT_k8_REG_ADDR : std_logic_vector(3 downto 0) := X"B";
constant PORT_N_REG_ADDR : std_logic_vector(3 downto 0) := X"C";
begin
REG:process (clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
enable_o <= '0';
-- port_o <= (others=>'0');
imwidth_o <= X"00000140";
imheight_o <= X"000000F0";
for i in 0 to NB_PORTS-1 loop
ports(i).wr <='0';
end loop;
elsif rising_edge(clk_i) then
if(wr_i = '1') then
case addr_i is
when ENABLE_0_REG_ADDR =>
enable_o <= datawr_i(0);
when IMWIDTH_REG_ADDR =>
imwidth_o <= datawr_i;
when IMHEIGHT_REG_ADDR =>
imheight_o <= datawr_i;
when PORT_k0_REG_ADDR =>
ports(0).wr <= '1';
ports(0).data <= datawr_i;
when PORT_k1_REG_ADDR =>
ports(1).wr <= '1';
ports(1).data <= datawr_i;
when PORT_k2_REG_ADDR =>
ports(2).wr <= '1';
ports(2).data <= datawr_i;
when PORT_k3_REG_ADDR =>
ports(3).wr <= '1';
ports(3).data <= datawr_i;
when PORT_k4_REG_ADDR =>
ports(4).wr <= '1';
ports(4).data <= datawr_i;
when PORT_k5_REG_ADDR =>
ports(5).wr <= '1';
ports(5).data <= datawr_i;
when PORT_k6_REG_ADDR =>
ports(6).wr <= '1';
ports(6).data <= datawr_i;
when PORT_k7_REG_ADDR =>
ports(7).wr <= '1';
ports(7).data <= datawr_i;
when PORT_k8_REG_ADDR =>
ports(8).wr <= '1';
ports(8).data <= datawr_i;
when PORT_N_REG_ADDR =>
ports(9).wr <= '1';
ports(9).data <= datawr_i;
when others =>
end case;
else
for i in 0 to NB_PORTS-1 loop
ports(i).wr <='0';
end loop;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | 5ede89d797a915f98e3d4f999d6466a2 | 0.557247 | 2.649341 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_nios2_qsys_0_test_bench.vhd | 1 | 62,380 | --Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity tracking_camera_system_nios2_qsys_0_test_bench is
port (
-- inputs:
signal A_bstatus_reg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal A_cmp_result : IN STD_LOGIC;
signal A_ctrl_exception : IN STD_LOGIC;
signal A_ctrl_ld_non_bypass : IN STD_LOGIC;
signal A_dst_regnum : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal A_en : IN STD_LOGIC;
signal A_estatus_reg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal A_ienable_reg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal A_ipending_reg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal A_iw : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal A_mem_byte_en : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal A_op_hbreak : IN STD_LOGIC;
signal A_op_intr : IN STD_LOGIC;
signal A_pcb : IN STD_LOGIC_VECTOR (24 DOWNTO 0);
signal A_st_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal A_status_reg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal A_valid : IN STD_LOGIC;
signal A_wr_data_unfiltered : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal A_wr_dst_reg : IN STD_LOGIC;
signal E_add_br_to_taken_history_unfiltered : IN STD_LOGIC;
signal E_logic_result : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_valid : IN STD_LOGIC;
signal M_bht_ptr_unfiltered : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal M_bht_wr_data_unfiltered : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal M_bht_wr_en_unfiltered : IN STD_LOGIC;
signal M_mem_baddr : IN STD_LOGIC_VECTOR (24 DOWNTO 0);
signal M_target_pcb : IN STD_LOGIC_VECTOR (24 DOWNTO 0);
signal M_valid : IN STD_LOGIC;
signal W_dst_regnum : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal W_iw : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_iw_op : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
signal W_iw_opx : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
signal W_pcb : IN STD_LOGIC_VECTOR (24 DOWNTO 0);
signal W_valid : IN STD_LOGIC;
signal W_vinst : IN STD_LOGIC_VECTOR (55 DOWNTO 0);
signal W_wr_dst_reg : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal d_address : IN STD_LOGIC_VECTOR (24 DOWNTO 0);
signal d_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal d_read : IN STD_LOGIC;
signal d_write : IN STD_LOGIC;
signal i_address : IN STD_LOGIC_VECTOR (24 DOWNTO 0);
signal i_read : IN STD_LOGIC;
signal i_readdatavalid : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal A_wr_data_filtered : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_add_br_to_taken_history_filtered : OUT STD_LOGIC;
signal E_src1_eq_src2 : OUT STD_LOGIC;
signal M_bht_ptr_filtered : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal M_bht_wr_data_filtered : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal M_bht_wr_en_filtered : OUT STD_LOGIC;
signal test_has_ended : OUT STD_LOGIC
);
end entity tracking_camera_system_nios2_qsys_0_test_bench;
architecture europa of tracking_camera_system_nios2_qsys_0_test_bench is
signal A_mem_baddr : STD_LOGIC_VECTOR (24 DOWNTO 0);
signal A_target_pcb : STD_LOGIC_VECTOR (24 DOWNTO 0);
signal A_wr_data_unfiltered_0_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_10_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_11_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_12_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_13_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_14_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_15_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_16_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_17_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_18_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_19_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_1_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_20_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_21_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_22_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_23_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_24_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_25_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_26_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_27_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_28_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_29_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_2_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_30_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_31_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_3_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_4_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_5_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_6_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_7_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_8_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_9_is_x : STD_LOGIC;
signal W_op_add : STD_LOGIC;
signal W_op_addi : STD_LOGIC;
signal W_op_and : STD_LOGIC;
signal W_op_andhi : STD_LOGIC;
signal W_op_andi : STD_LOGIC;
signal W_op_beq : STD_LOGIC;
signal W_op_bge : STD_LOGIC;
signal W_op_bgeu : STD_LOGIC;
signal W_op_blt : STD_LOGIC;
signal W_op_bltu : STD_LOGIC;
signal W_op_bne : STD_LOGIC;
signal W_op_br : STD_LOGIC;
signal W_op_break : STD_LOGIC;
signal W_op_bret : STD_LOGIC;
signal W_op_call : STD_LOGIC;
signal W_op_callr : STD_LOGIC;
signal W_op_cmpeq : STD_LOGIC;
signal W_op_cmpeqi : STD_LOGIC;
signal W_op_cmpge : STD_LOGIC;
signal W_op_cmpgei : STD_LOGIC;
signal W_op_cmpgeu : STD_LOGIC;
signal W_op_cmpgeui : STD_LOGIC;
signal W_op_cmplt : STD_LOGIC;
signal W_op_cmplti : STD_LOGIC;
signal W_op_cmpltu : STD_LOGIC;
signal W_op_cmpltui : STD_LOGIC;
signal W_op_cmpne : STD_LOGIC;
signal W_op_cmpnei : STD_LOGIC;
signal W_op_crst : STD_LOGIC;
signal W_op_custom : STD_LOGIC;
signal W_op_div : STD_LOGIC;
signal W_op_divu : STD_LOGIC;
signal W_op_eret : STD_LOGIC;
signal W_op_flushd : STD_LOGIC;
signal W_op_flushda : STD_LOGIC;
signal W_op_flushi : STD_LOGIC;
signal W_op_flushp : STD_LOGIC;
signal W_op_hbreak : STD_LOGIC;
signal W_op_initd : STD_LOGIC;
signal W_op_initda : STD_LOGIC;
signal W_op_initi : STD_LOGIC;
signal W_op_intr : STD_LOGIC;
signal W_op_jmp : STD_LOGIC;
signal W_op_jmpi : STD_LOGIC;
signal W_op_ldb : STD_LOGIC;
signal W_op_ldbio : STD_LOGIC;
signal W_op_ldbu : STD_LOGIC;
signal W_op_ldbuio : STD_LOGIC;
signal W_op_ldh : STD_LOGIC;
signal W_op_ldhio : STD_LOGIC;
signal W_op_ldhu : STD_LOGIC;
signal W_op_ldhuio : STD_LOGIC;
signal W_op_ldl : STD_LOGIC;
signal W_op_ldw : STD_LOGIC;
signal W_op_ldwio : STD_LOGIC;
signal W_op_mul : STD_LOGIC;
signal W_op_muli : STD_LOGIC;
signal W_op_mulxss : STD_LOGIC;
signal W_op_mulxsu : STD_LOGIC;
signal W_op_mulxuu : STD_LOGIC;
signal W_op_nextpc : STD_LOGIC;
signal W_op_nor : STD_LOGIC;
signal W_op_opx : STD_LOGIC;
signal W_op_or : STD_LOGIC;
signal W_op_orhi : STD_LOGIC;
signal W_op_ori : STD_LOGIC;
signal W_op_rdctl : STD_LOGIC;
signal W_op_rdprs : STD_LOGIC;
signal W_op_ret : STD_LOGIC;
signal W_op_rol : STD_LOGIC;
signal W_op_roli : STD_LOGIC;
signal W_op_ror : STD_LOGIC;
signal W_op_rsv02 : STD_LOGIC;
signal W_op_rsv09 : STD_LOGIC;
signal W_op_rsv10 : STD_LOGIC;
signal W_op_rsv17 : STD_LOGIC;
signal W_op_rsv18 : STD_LOGIC;
signal W_op_rsv25 : STD_LOGIC;
signal W_op_rsv26 : STD_LOGIC;
signal W_op_rsv33 : STD_LOGIC;
signal W_op_rsv34 : STD_LOGIC;
signal W_op_rsv41 : STD_LOGIC;
signal W_op_rsv42 : STD_LOGIC;
signal W_op_rsv49 : STD_LOGIC;
signal W_op_rsv57 : STD_LOGIC;
signal W_op_rsv61 : STD_LOGIC;
signal W_op_rsv62 : STD_LOGIC;
signal W_op_rsv63 : STD_LOGIC;
signal W_op_rsvx00 : STD_LOGIC;
signal W_op_rsvx10 : STD_LOGIC;
signal W_op_rsvx15 : STD_LOGIC;
signal W_op_rsvx17 : STD_LOGIC;
signal W_op_rsvx21 : STD_LOGIC;
signal W_op_rsvx25 : STD_LOGIC;
signal W_op_rsvx33 : STD_LOGIC;
signal W_op_rsvx34 : STD_LOGIC;
signal W_op_rsvx35 : STD_LOGIC;
signal W_op_rsvx42 : STD_LOGIC;
signal W_op_rsvx43 : STD_LOGIC;
signal W_op_rsvx44 : STD_LOGIC;
signal W_op_rsvx47 : STD_LOGIC;
signal W_op_rsvx50 : STD_LOGIC;
signal W_op_rsvx51 : STD_LOGIC;
signal W_op_rsvx55 : STD_LOGIC;
signal W_op_rsvx56 : STD_LOGIC;
signal W_op_rsvx60 : STD_LOGIC;
signal W_op_rsvx63 : STD_LOGIC;
signal W_op_sll : STD_LOGIC;
signal W_op_slli : STD_LOGIC;
signal W_op_sra : STD_LOGIC;
signal W_op_srai : STD_LOGIC;
signal W_op_srl : STD_LOGIC;
signal W_op_srli : STD_LOGIC;
signal W_op_stb : STD_LOGIC;
signal W_op_stbio : STD_LOGIC;
signal W_op_stc : STD_LOGIC;
signal W_op_sth : STD_LOGIC;
signal W_op_sthio : STD_LOGIC;
signal W_op_stw : STD_LOGIC;
signal W_op_stwio : STD_LOGIC;
signal W_op_sub : STD_LOGIC;
signal W_op_sync : STD_LOGIC;
signal W_op_trap : STD_LOGIC;
signal W_op_wrctl : STD_LOGIC;
signal W_op_wrprs : STD_LOGIC;
signal W_op_xor : STD_LOGIC;
signal W_op_xorhi : STD_LOGIC;
signal W_op_xori : STD_LOGIC;
signal internal_A_wr_data_filtered : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_test_has_ended : STD_LOGIC;
file trace_handle : TEXT ;
begin
W_op_call <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000000000")));
W_op_jmpi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000000001")));
W_op_ldbu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000000011")));
W_op_addi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000000100")));
W_op_stb <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000000101")));
W_op_br <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000000110")));
W_op_ldb <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000000111")));
W_op_cmpgei <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000001000")));
W_op_ldhu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000001011")));
W_op_andi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000001100")));
W_op_sth <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000001101")));
W_op_bge <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000001110")));
W_op_ldh <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000001111")));
W_op_cmplti <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000010000")));
W_op_initda <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000010011")));
W_op_ori <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000010100")));
W_op_stw <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000010101")));
W_op_blt <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000010110")));
W_op_ldw <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000010111")));
W_op_cmpnei <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000011000")));
W_op_flushda <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000011011")));
W_op_xori <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000011100")));
W_op_stc <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000011101")));
W_op_bne <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000011110")));
W_op_ldl <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000011111")));
W_op_cmpeqi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000100000")));
W_op_ldbuio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000100011")));
W_op_muli <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000100100")));
W_op_stbio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000100101")));
W_op_beq <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000100110")));
W_op_ldbio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000100111")));
W_op_cmpgeui <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000101000")));
W_op_ldhuio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000101011")));
W_op_andhi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000101100")));
W_op_sthio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000101101")));
W_op_bgeu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000101110")));
W_op_ldhio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000101111")));
W_op_cmpltui <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000110000")));
W_op_initd <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000110011")));
W_op_orhi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000110100")));
W_op_stwio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000110101")));
W_op_bltu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000110110")));
W_op_ldwio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000110111")));
W_op_rdprs <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000111000")));
W_op_flushd <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000111011")));
W_op_xorhi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000111100")));
W_op_rsv02 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000000010")));
W_op_rsv09 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000001001")));
W_op_rsv10 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000001010")));
W_op_rsv17 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000010001")));
W_op_rsv18 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000010010")));
W_op_rsv25 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000011001")));
W_op_rsv26 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000011010")));
W_op_rsv33 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000100001")));
W_op_rsv34 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000100010")));
W_op_rsv41 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000101001")));
W_op_rsv42 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000101010")));
W_op_rsv49 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000110001")));
W_op_rsv57 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000111001")));
W_op_rsv61 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000111101")));
W_op_rsv62 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000111110")));
W_op_rsv63 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000111111")));
W_op_eret <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000000001"))));
W_op_roli <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000000010"))));
W_op_rol <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000000011"))));
W_op_flushp <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000000100"))));
W_op_ret <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000000101"))));
W_op_nor <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000000110"))));
W_op_mulxuu <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000000111"))));
W_op_cmpge <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000001000"))));
W_op_bret <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000001001"))));
W_op_ror <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000001011"))));
W_op_flushi <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000001100"))));
W_op_jmp <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000001101"))));
W_op_and <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000001110"))));
W_op_cmplt <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000010000"))));
W_op_slli <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000010010"))));
W_op_sll <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000010011"))));
W_op_wrprs <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000010100"))));
W_op_or <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000010110"))));
W_op_mulxsu <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000010111"))));
W_op_cmpne <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000011000"))));
W_op_srli <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000011010"))));
W_op_srl <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000011011"))));
W_op_nextpc <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000011100"))));
W_op_callr <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000011101"))));
W_op_xor <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000011110"))));
W_op_mulxss <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000011111"))));
W_op_cmpeq <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000100000"))));
W_op_divu <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000100100"))));
W_op_div <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000100101"))));
W_op_rdctl <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000100110"))));
W_op_mul <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000100111"))));
W_op_cmpgeu <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000101000"))));
W_op_initi <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000101001"))));
W_op_trap <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000101101"))));
W_op_wrctl <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000101110"))));
W_op_cmpltu <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000110000"))));
W_op_add <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000110001"))));
W_op_break <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000110100"))));
W_op_hbreak <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000110101"))));
W_op_sync <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000110110"))));
W_op_sub <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000111001"))));
W_op_srai <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000111010"))));
W_op_sra <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000111011"))));
W_op_intr <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000111101"))));
W_op_crst <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000111110"))));
W_op_rsvx00 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000000000"))));
W_op_rsvx10 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000001010"))));
W_op_rsvx15 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000001111"))));
W_op_rsvx17 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000010001"))));
W_op_rsvx21 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000010101"))));
W_op_rsvx25 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000011001"))));
W_op_rsvx33 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000100001"))));
W_op_rsvx34 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000100010"))));
W_op_rsvx35 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000100011"))));
W_op_rsvx42 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000101010"))));
W_op_rsvx43 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000101011"))));
W_op_rsvx44 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000101100"))));
W_op_rsvx47 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000101111"))));
W_op_rsvx50 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000110010"))));
W_op_rsvx51 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000110011"))));
W_op_rsvx55 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000110111"))));
W_op_rsvx56 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000111000"))));
W_op_rsvx60 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000111100"))));
W_op_rsvx63 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000111111"))));
W_op_opx <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000111010")));
W_op_custom <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000110010")));
process (clk, reset_n)
begin
if reset_n = '0' then
A_target_pcb <= std_logic_vector'("0000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(A_en) = '1' then
A_target_pcb <= M_target_pcb;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
A_mem_baddr <= std_logic_vector'("0000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(A_en) = '1' then
A_mem_baddr <= M_mem_baddr;
end if;
end if;
end process;
E_src1_eq_src2 <= to_std_logic((E_logic_result = std_logic_vector'("00000000000000000000000000000000")));
--Propagating 'X' data bits
E_add_br_to_taken_history_filtered <= E_add_br_to_taken_history_unfiltered;
--Propagating 'X' data bits
M_bht_wr_en_filtered <= M_bht_wr_en_unfiltered;
--Propagating 'X' data bits
M_bht_wr_data_filtered <= M_bht_wr_data_unfiltered;
--Propagating 'X' data bits
M_bht_ptr_filtered <= M_bht_ptr_unfiltered;
internal_test_has_ended <= std_logic'('0');
--vhdl renameroo for output signals
A_wr_data_filtered <= internal_A_wr_data_filtered;
--vhdl renameroo for output signals
test_has_ended <= internal_test_has_ended;
--synthesis translate_off
--Clearing 'X' data bits
A_wr_data_unfiltered_0_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(0))), '1','0');
internal_A_wr_data_filtered(0) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_0_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(0));
A_wr_data_unfiltered_1_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(1))), '1','0');
internal_A_wr_data_filtered(1) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_1_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(1));
A_wr_data_unfiltered_2_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(2))), '1','0');
internal_A_wr_data_filtered(2) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_2_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(2));
A_wr_data_unfiltered_3_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(3))), '1','0');
internal_A_wr_data_filtered(3) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_3_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(3));
A_wr_data_unfiltered_4_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(4))), '1','0');
internal_A_wr_data_filtered(4) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_4_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(4));
A_wr_data_unfiltered_5_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(5))), '1','0');
internal_A_wr_data_filtered(5) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_5_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(5));
A_wr_data_unfiltered_6_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(6))), '1','0');
internal_A_wr_data_filtered(6) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_6_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(6));
A_wr_data_unfiltered_7_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(7))), '1','0');
internal_A_wr_data_filtered(7) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_7_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(7));
A_wr_data_unfiltered_8_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(8))), '1','0');
internal_A_wr_data_filtered(8) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_8_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(8));
A_wr_data_unfiltered_9_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(9))), '1','0');
internal_A_wr_data_filtered(9) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_9_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(9));
A_wr_data_unfiltered_10_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(10))), '1','0');
internal_A_wr_data_filtered(10) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_10_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(10));
A_wr_data_unfiltered_11_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(11))), '1','0');
internal_A_wr_data_filtered(11) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_11_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(11));
A_wr_data_unfiltered_12_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(12))), '1','0');
internal_A_wr_data_filtered(12) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_12_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(12));
A_wr_data_unfiltered_13_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(13))), '1','0');
internal_A_wr_data_filtered(13) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_13_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(13));
A_wr_data_unfiltered_14_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(14))), '1','0');
internal_A_wr_data_filtered(14) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_14_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(14));
A_wr_data_unfiltered_15_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(15))), '1','0');
internal_A_wr_data_filtered(15) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_15_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(15));
A_wr_data_unfiltered_16_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(16))), '1','0');
internal_A_wr_data_filtered(16) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_16_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(16));
A_wr_data_unfiltered_17_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(17))), '1','0');
internal_A_wr_data_filtered(17) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_17_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(17));
A_wr_data_unfiltered_18_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(18))), '1','0');
internal_A_wr_data_filtered(18) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_18_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(18));
A_wr_data_unfiltered_19_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(19))), '1','0');
internal_A_wr_data_filtered(19) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_19_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(19));
A_wr_data_unfiltered_20_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(20))), '1','0');
internal_A_wr_data_filtered(20) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_20_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(20));
A_wr_data_unfiltered_21_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(21))), '1','0');
internal_A_wr_data_filtered(21) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_21_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(21));
A_wr_data_unfiltered_22_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(22))), '1','0');
internal_A_wr_data_filtered(22) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_22_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(22));
A_wr_data_unfiltered_23_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(23))), '1','0');
internal_A_wr_data_filtered(23) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_23_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(23));
A_wr_data_unfiltered_24_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(24))), '1','0');
internal_A_wr_data_filtered(24) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_24_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(24));
A_wr_data_unfiltered_25_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(25))), '1','0');
internal_A_wr_data_filtered(25) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_25_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(25));
A_wr_data_unfiltered_26_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(26))), '1','0');
internal_A_wr_data_filtered(26) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_26_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(26));
A_wr_data_unfiltered_27_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(27))), '1','0');
internal_A_wr_data_filtered(27) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_27_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(27));
A_wr_data_unfiltered_28_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(28))), '1','0');
internal_A_wr_data_filtered(28) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_28_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(28));
A_wr_data_unfiltered_29_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(29))), '1','0');
internal_A_wr_data_filtered(29) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_29_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(29));
A_wr_data_unfiltered_30_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(30))), '1','0');
internal_A_wr_data_filtered(30) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_30_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(30));
A_wr_data_unfiltered_31_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(31))), '1','0');
internal_A_wr_data_filtered(31) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_31_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(31));
process (clk)
VARIABLE write_line : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(W_wr_dst_reg)) then
write(write_line, now);
write(write_line, string'(": "));
write(write_line, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/W_wr_dst_reg is 'x'"));
write(output, write_line.all & CR);
deallocate (write_line);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line1 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'(W_wr_dst_reg) = '1' then
if is_x(W_dst_regnum) then
write(write_line1, now);
write(write_line1, string'(": "));
write(write_line1, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/W_dst_regnum is 'x'"));
write(output, write_line1.all & CR);
deallocate (write_line1);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line2 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(W_valid)) then
write(write_line2, now);
write(write_line2, string'(": "));
write(write_line2, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/W_valid is 'x'"));
write(output, write_line2.all & CR);
deallocate (write_line2);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line3 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'(W_valid) = '1' then
if is_x(W_pcb) then
write(write_line3, now);
write(write_line3, string'(": "));
write(write_line3, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/W_pcb is 'x'"));
write(output, write_line3.all & CR);
deallocate (write_line3);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line4 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'(W_valid) = '1' then
if is_x(W_iw) then
write(write_line4, now);
write(write_line4, string'(": "));
write(write_line4, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/W_iw is 'x'"));
write(output, write_line4.all & CR);
deallocate (write_line4);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line5 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(A_en)) then
write(write_line5, now);
write(write_line5, string'(": "));
write(write_line5, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/A_en is 'x'"));
write(output, write_line5.all & CR);
deallocate (write_line5);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line6 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(E_valid)) then
write(write_line6, now);
write(write_line6, string'(": "));
write(write_line6, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/E_valid is 'x'"));
write(output, write_line6.all & CR);
deallocate (write_line6);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line7 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(M_valid)) then
write(write_line7, now);
write(write_line7, string'(": "));
write(write_line7, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/M_valid is 'x'"));
write(output, write_line7.all & CR);
deallocate (write_line7);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line8 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(A_valid)) then
write(write_line8, now);
write(write_line8, string'(": "));
write(write_line8, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/A_valid is 'x'"));
write(output, write_line8.all & CR);
deallocate (write_line8);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line9 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'(((A_valid AND A_en) AND A_wr_dst_reg)) = '1' then
if is_x(A_wr_data_unfiltered) then
write(write_line9, now);
write(write_line9, string'(": "));
write(write_line9, string'("WARNING: tracking_camera_system_nios2_qsys_0_test_bench/A_wr_data_unfiltered is 'x'"));
write(output, write_line9.all & CR);
deallocate (write_line9);
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line10 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(A_status_reg) then
write(write_line10, now);
write(write_line10, string'(": "));
write(write_line10, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/A_status_reg is 'x'"));
write(output, write_line10.all & CR);
deallocate (write_line10);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line11 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(A_estatus_reg) then
write(write_line11, now);
write(write_line11, string'(": "));
write(write_line11, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/A_estatus_reg is 'x'"));
write(output, write_line11.all & CR);
deallocate (write_line11);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line12 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(A_bstatus_reg) then
write(write_line12, now);
write(write_line12, string'(": "));
write(write_line12, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/A_bstatus_reg is 'x'"));
write(output, write_line12.all & CR);
deallocate (write_line12);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line13 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(i_read)) then
write(write_line13, now);
write(write_line13, string'(": "));
write(write_line13, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/i_read is 'x'"));
write(output, write_line13.all & CR);
deallocate (write_line13);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line14 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'(i_read) = '1' then
if is_x(i_address) then
write(write_line14, now);
write(write_line14, string'(": "));
write(write_line14, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/i_address is 'x'"));
write(output, write_line14.all & CR);
deallocate (write_line14);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line15 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(i_readdatavalid)) then
write(write_line15, now);
write(write_line15, string'(": "));
write(write_line15, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/i_readdatavalid is 'x'"));
write(output, write_line15.all & CR);
deallocate (write_line15);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line16 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(d_write)) then
write(write_line16, now);
write(write_line16, string'(": "));
write(write_line16, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/d_write is 'x'"));
write(output, write_line16.all & CR);
deallocate (write_line16);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line17 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'(d_write) = '1' then
if is_x(d_byteenable) then
write(write_line17, now);
write(write_line17, string'(": "));
write(write_line17, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/d_byteenable is 'x'"));
write(output, write_line17.all & CR);
deallocate (write_line17);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line18 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'((d_write OR d_read)) = '1' then
if is_x(d_address) then
write(write_line18, now);
write(write_line18, string'(": "));
write(write_line18, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/d_address is 'x'"));
write(output, write_line18.all & CR);
deallocate (write_line18);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line19 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(d_read)) then
write(write_line19, now);
write(write_line19, string'(": "));
write(write_line19, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/d_read is 'x'"));
write(output, write_line19.all & CR);
deallocate (write_line19);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process is
variable status : file_open_status; -- status for fopen
VARIABLE write_line20 : line;
VARIABLE write_line21 : line;
begin -- process
file_open(status, trace_handle, "tracking_camera_system_nios2_qsys_0.tr", WRITE_MODE);
write(write_line20, string'("version 3"));
write(trace_handle, write_line20.all & LF);
deallocate (write_line20);
write(write_line21, string'("numThreads 1"));
write(trace_handle, write_line21.all & LF);
deallocate (write_line21);
wait; -- wait forever
end process;
process (clk)
VARIABLE write_line22 : line;
begin
if clk'event and clk = '1' then
if std_logic'((((NOT reset_n OR ((A_valid AND A_en)))) AND NOT internal_test_has_ended)) = '1' then
write(write_line22, now);
write(write_line22, string'(": "));
write(write_line22, to_hex_string(NOT reset_n, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_pcb, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_op_intr, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_op_hbreak, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_iw, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(NOT ((A_op_intr OR A_op_hbreak)), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_wr_dst_reg, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_dst_regnum, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(internal_A_wr_data_filtered, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_mem_baddr, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_st_data, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_mem_byte_en, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_cmp_result, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_target_pcb, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_status_reg, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_estatus_reg, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_bstatus_reg, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_ienable_reg, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_ipending_reg, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_WE_StdLogicVector((std_logic'(A_ctrl_exception) = '1'), std_logic_vector'("00000000000000000000000000000001"), std_logic_vector'("00000000000000000000000000000000")), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(""));
write(trace_handle, write_line22.all & LF);
deallocate (write_line22);
end if;
end if;
end process;
--synthesis translate_on
--synthesis read_comments_as_HDL on
--
-- internal_A_wr_data_filtered <= A_wr_data_unfiltered;
--synthesis read_comments_as_HDL off
end europa;
| gpl-2.0 | 27588f50e1153e25be8752969d74b12c | 0.61898 | 3.442415 | false | false | false | false |
DreamIP/GPStudio | support/process/laplacian/hdl/laplacian.vhd | 1 | 6,302 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity laplacian is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end laplacian;
architecture rtl of laplacian is
component laplacian_process
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_width : in std_logic_vector(15 downto 0);
w00_reg_m00 : in std_logic_vector(7 downto 0);
w01_reg_m01 : in std_logic_vector(7 downto 0);
w02_reg_m02 : in std_logic_vector(7 downto 0);
w10_reg_m10 : in std_logic_vector(7 downto 0);
w11_reg_m11 : in std_logic_vector(7 downto 0);
w12_reg_m12 : in std_logic_vector(7 downto 0);
w20_reg_m20 : in std_logic_vector(7 downto 0);
w21_reg_m21 : in std_logic_vector(7 downto 0);
w22_reg_m22 : in std_logic_vector(7 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component laplacian_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
w00_reg_m00 : out std_logic_vector(7 downto 0);
w01_reg_m01 : out std_logic_vector(7 downto 0);
w02_reg_m02 : out std_logic_vector(7 downto 0);
w10_reg_m10 : out std_logic_vector(7 downto 0);
w11_reg_m11 : out std_logic_vector(7 downto 0);
w12_reg_m12 : out std_logic_vector(7 downto 0);
w20_reg_m20 : out std_logic_vector(7 downto 0);
w21_reg_m21 : out std_logic_vector(7 downto 0);
w22_reg_m22 : out std_logic_vector(7 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal widthimg_reg_width : std_logic_vector (15 downto 0);
signal w00_reg_m00 : std_logic_vector (7 downto 0);
signal w01_reg_m01 : std_logic_vector (7 downto 0);
signal w02_reg_m02 : std_logic_vector (7 downto 0);
signal w10_reg_m10 : std_logic_vector (7 downto 0);
signal w11_reg_m11 : std_logic_vector (7 downto 0);
signal w12_reg_m12 : std_logic_vector (7 downto 0);
signal w20_reg_m20 : std_logic_vector (7 downto 0);
signal w21_reg_m21 : std_logic_vector (7 downto 0);
signal w22_reg_m22 : std_logic_vector (7 downto 0);
begin
laplacian_process_inst : laplacian_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_width => widthimg_reg_width,
w00_reg_m00 => w00_reg_m00,
w01_reg_m01 => w01_reg_m01,
w02_reg_m02 => w02_reg_m02,
w10_reg_m10 => w10_reg_m10,
w11_reg_m11 => w11_reg_m11,
w12_reg_m12 => w12_reg_m12,
w20_reg_m20 => w20_reg_m20,
w21_reg_m21 => w21_reg_m21,
w22_reg_m22 => w22_reg_m22,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
laplacian_slave_inst : laplacian_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_width => widthimg_reg_width,
w00_reg_m00 => w00_reg_m00,
w01_reg_m01 => w01_reg_m01,
w02_reg_m02 => w02_reg_m02,
w10_reg_m10 => w10_reg_m10,
w11_reg_m11 => w11_reg_m11,
w12_reg_m12 => w12_reg_m12,
w20_reg_m20 => w20_reg_m20,
w21_reg_m21 => w21_reg_m21,
w22_reg_m22 => w22_reg_m22,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
| gpl-3.0 | 9cf27424ea5713b9d7ff88a66ff59a6d | 0.48683 | 3.008115 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/sync/debounce.vhdl | 1 | 955 | --
-- Debounce
--
-- Author(s):
-- * Francisco Salomón
--
-- Copyright (c) 2012 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
entity Debounce is
generic(
FREQUENCY : positive:=50e6; -- Clock frequency [Hz]
DEB_TIME : real:=50.0e-3 -- Debounce time [s]
);
port(
clk_i : in std_logic;
deb_i : in std_logic;
deb_o : out std_logic
);
end entity Debounce;
architecture RTL of Debounce is
begin
do_debounce:
process (clk_i)
variable cnt : natural:=0;
begin
if rising_edge(clk_i) then
if deb_i='1' then
if cnt=natural(real(FREQUENCY)*DEB_TIME) then
deb_o <= '1';
cnt:=0;
else
cnt:=cnt+1;
end if;
else
deb_o <= '0';
cnt:=0;
end if;
end if;
end process do_debounce;
end architecture RTL;
| bsd-3-clause | ceaf1979aed9fc259450053b74a23dad | 0.535639 | 3.431655 | false | false | false | false |
hoglet67/ElectronFpga | src/altera/WatchEvents.vhd | 1 | 5,498 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY WatchEvents IS
PORT
(
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END WatchEvents;
ARCHITECTURE SYN OF watchevents IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (71 DOWNTO 0);
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
rdreq : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (71 DOWNTO 0);
wrreq : IN STD_LOGIC
);
END COMPONENT;
BEGIN
empty <= sub_wire0;
full <= sub_wire1;
dout <= sub_wire2(71 DOWNTO 0);
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
intended_device_family => "Cyclone II",
lpm_numwords => 256,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => 72,
lpm_widthu => 8,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
clock => clk,
data => din,
rdreq => rd_en,
sclr => srst,
wrreq => wr_en,
empty => sub_wire0,
full => sub_wire1,
q => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "512"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "0"
-- Retrieval info: PRIVATE: Width NUMERIC "72"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "72"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "72"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data 0 0 72 0 INPUT NODEFVAL "data[71..0]"
-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
-- Retrieval info: USED_PORT: q 0 0 72 0 OUTPUT NODEFVAL "q[71..0]"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 72 0 data 0 0 72 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 72 0 @q 0 0 72 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL WatchEvents.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WatchEvents.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WatchEvents.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WatchEvents.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WatchEvents_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | db32c3c64d1d262a49b2e9ba35444062 | 0.67861 | 3.381304 | false | false | false | false |
DreamIP/GPStudio | support/process/fast/hdl/components/fastElement.vhd | 1 | 20,122 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fast_types.all;
entity fastElement is
generic(
KERNEL_SIZE : integer;
PIXEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in pixel_array (0 to KERNEL_SIZE * KERNEL_SIZE - 1);
in_dv : in std_logic;
in_fv : in std_logic;
in_kernel : in pixel_array (0 to KERNEL_SIZE * KERNEL_SIZE - 1);
--in_norm : in std_logic_vector(PIXEL_SIZE-1 downto 0);
out_data : out std_logic_vector(PIXEL_SIZE-1 downto 0);
out_dv : out std_logic;
out_fv : out std_logic
);
end fastElement;
architecture bhv of fastElement is
-- Signals
type pixel_array_s1 is array (0 to KERNEL_SIZE * KERNEL_SIZE - 1) of signed ((PIXEL_SIZE) downto 0);
signal px : pixel_array_s1 ;
signal kernel_s : pixel_array_s1 ;
signal res : signed (PIXEL_SIZE downto 0);
signal all_valid : std_logic;
signal ev_c1b : std_logic;
signal ev_c2b : std_logic;
signal ev_c3b : std_logic;
signal ev_c4b : std_logic;
signal ev_c5b : std_logic;
signal ev_c6b : std_logic;
signal ev_c7b : std_logic;
signal ev_c8b : std_logic;
signal ev_c9b : std_logic;
signal ev_c10b : std_logic;
signal ev_c11b : std_logic;
signal ev_c12b : std_logic;
signal ev_c13b : std_logic;
signal ev_c14b : std_logic;
signal ev_c15b : std_logic;
signal ev_c16b : std_logic;
signal ev_c1h : std_logic;
signal ev_c2h : std_logic;
signal ev_c3h : std_logic;
signal ev_c4h : std_logic;
signal ev_c5h : std_logic;
signal ev_c6h : std_logic;
signal ev_c7h : std_logic;
signal ev_c8h : std_logic;
signal ev_c9h : std_logic;
signal ev_c10h : std_logic;
signal ev_c11h : std_logic;
signal ev_c12h : std_logic;
signal ev_c13h : std_logic;
signal ev_c14h : std_logic;
signal ev_c15h : std_logic;
signal ev_c16h : std_logic;
signal tmp : signed(pixel_size downto 0);
begin
-- All valid : Logic and
all_valid <= in_dv and in_fv and enable;
SIGNED_CAST : for i in 0 to ( KERNEL_SIZE * KERNEL_SIZE - 1 ) generate
px(i) <= signed('0' & in_data(i));
end generate;
process(clk)
variable threshold : signed(6 downto 0) := "0001111"; -- threshold value
------------- Variables Bresenham circle points -------------------------
variable p1b : std_logic; -- pixel-1-bas if the pixel 1 of the Bresenham circle is smaller
-- than the center pixel minus the threshold value
variable p2b : std_logic;
variable p3b : std_logic;
variable p4b : std_logic;
variable p5b : std_logic;
variable p6b : std_logic;
variable p7b : std_logic;
variable p8b : std_logic;
variable p9b : std_logic;
variable p10b : std_logic;
variable p11b : std_logic;
variable p12b : std_logic;
variable p13b : std_logic;
variable p14b : std_logic;
variable p15b : std_logic;
variable p16b : std_logic;
variable p1h : std_logic; -- pixel-1-haut if the pixel 1 of the Bresenham circle is bigger
-- than the center pixel plus the threshold value
variable p2h : std_logic;
variable p3h : std_logic;
variable p4h : std_logic;
variable p5h : std_logic;
variable p6h : std_logic;
variable p7h : std_logic;
variable p8h : std_logic;
variable p9h : std_logic;
variable p10h : std_logic;
variable p11h : std_logic;
variable p12h : std_logic;
variable p13h : std_logic;
variable p14h : std_logic;
variable p15h : std_logic;
variable p16h : std_logic;
begin
----------------- Bresenham Circle pixels -------------------------
if (px(3) <= px(24)-threshold) then
p1b := '1';
p1h := '0';
elsif (px(3) >= px(24)+threshold) then
p1b := '0';
p1h := '1';
else
p1b := '0';
p1h := '0';
end if;
if (px(4) <= px(24)-threshold) then
p2b := '1';
p2h := '0';
elsif (px(4) >= px(24)+threshold) then
p2b := '0';
p2h := '1';
else
p2b := '0';
p2h := '0';
end if;
if (px(12) <= px(24)-threshold) then
p3b := '1';
p3h := '0';
elsif (px(12) >= px(24)+threshold) then
p3b := '0';
p3h := '1';
else
p3b := '0';
p3h := '0';
end if;
if (px(20) <= px(24)-threshold) then
p4b := '1';
p4h := '0';
elsif (px(20) >= px(24)+threshold) then
p4b := '0';
p4h := '1';
else
p4b := '0';
p4h := '0';
end if;
if (px(27) <= px(24)-threshold) then
p5b := '1';
p5h := '0';
elsif (px(27) >= px(24)+threshold) then
p5b := '0';
p5h := '1';
else
p5b := '0';
p5h := '0';
end if;
if (px(34) <= px(24)-threshold) then
p6b := '1';
p6h := '0';
elsif (px(34) >= px(24)+threshold) then
p6b := '0';
p6h := '1';
else
p6b := '0';
p6h := '0';
end if;
if (px(40) <= px(24)-threshold) then
p7b := '1';
p7h := '0';
elsif (px(40) >= px(24)+threshold) then
p7b := '0';
p7h := '1';
else
p7b := '0';
p7h := '0';
end if;
if (px(46) <= px(24)-threshold) then
p8b := '1';
p8h := '0';
elsif (px(46) >= px(24)+threshold) then
p8b := '0';
p8h := '1';
else
p8b := '0';
p8h := '0';
end if;
if (px(45) <= px(24)-threshold) then
p9b := '1';
p9h := '0';
elsif (px(45) >= px(24)+threshold) then
p9b := '0';
p9h := '1';
else
p9b := '0';
p9h := '0';
end if;
if (px(44) <= px(24)-threshold) then
p10b := '1';
p10h := '0';
elsif (px(44) >= px(24)+threshold) then
p10b := '0';
p10h := '1';
else
p10b := '0';
p10h := '0';
end if;
if (px(36) <= px(24)-threshold) then
p11b := '1';
p11h := '0';
elsif (px(36) >= px(24)+threshold) then
p11b := '0';
p11h := '1';
else
p11b := '0';
p11h := '0';
end if;
if (px(28) <= px(24)-threshold) then
p12b := '1';
p12h := '0';
elsif (px(28) >= px(24)+threshold) then
p12b := '0';
p12h := '1';
else
p12b := '0';
p12h := '0';
end if;
if (px(21) <= px(24)-threshold) then
p13b := '1';
p13h := '0';
elsif (px(21) >= px(24)+threshold) then
p13b := '0';
p13h := '1';
else
p13b := '0';
p13h := '0';
end if;
if (px(14) <= px(24)-threshold) then
p14b := '1';
p14h := '0';
elsif (px(14) >= px(24)+threshold) then
p14b := '0';
p14h := '1';
else
p14b := '0';
p14h := '0';
end if;
if (px(8) <= px(24)-threshold) then
p15b := '1';
p15h := '0';
elsif (px(8) >= px(24)+threshold) then
p15b := '0';
p15h := '1';
else
p15b := '0';
p15h := '0';
end if;
if (px(2) <= px(24)-threshold) then
p16b := '1';
p16h := '0';
elsif (px(2) >= px(24)+threshold) then
p16b := '0';
p16h := '1';
else
p16b := '0';
p16h := '0';
end if;
----------------- Bresenham Circle pixels -------------------------
if (all_valid='1') then
-- 1 ---------------------------- High-speed test FAST -------------------------------------------------
-- First pixel 1 and 9 are tested, if they are too brighter or darker. If so, then checks 5 and 13. If the central pixel is a corner, then at least of these
-- must all be brighter then the central pixel brightness plus the threshold value or darker than the central pixel brightness
-- minus the threshold value
if ((px(3) <= px(24)-threshold or px(3) >= px(24)+threshold) and (px(45) <= px(24)-threshold or px(45) >= px(24)+threshold)) then
-- 2 ---------------------------------------------------------------------------------------------------
if ((px(27) <= px(24)-threshold or px(27) >= px(24)+threshold) and (px(21) <= px(24)-threshold or px(21) >= px(24)+threshold)) then
-- 3 ---------------------------------------------------------------------------------------------------
if ((p1b ='1' and p5b='1' and p9b='1') or
(p5b ='1' and p9b='1' and p13b='1') or
(p9b ='1' and p13b='1' and p1b='1') or
(p13b ='1' and p1b='1' and p5b='1') or
(p1h ='1' and p5h='1' and p9h='1') or
(p5h ='1' and p9h='1' and p13h='1') or
(p9h ='1' and p13h='1' and p1h='1') or
(p13h ='1' and p1h='1' and p5h='1') or
(p13h ='1' and p1h='1' and p5h='1' and p9h='1') or
(p13b ='1' and p1b='1' and p5b='1' and p9b='1')) then
-- 4 ---------------------------------------------------------------------------------------------------
-- Set of 12 contiguous pixels in the Bresenham circle which are ALL brighter than the central pixel brightness
-- plus the threshold value or ALL darker than the central pixel brightness minus the threshold value.
if (p1b ='1' and p2b='1' and p3b='1' and p4b='1' and p5b='1' and p6b='1' and p7b='1' and p8b='1' and p9b='1' and p10b='1' and p11b='1' and p12b='1') then
ev_c1b <= '1';
ev_c1h <= '0';
elsif (p1h ='1' and p2h='1' and p3h='1' and p4h='1' and p5h='1' and p6h='1' and p7h='1' and p8h='1' and p9h='1' and p10h='1' and p11h='1' and p12h='1') then
ev_c1b <= '0';
ev_c1h <= '1';
else
ev_c1b <= '0';
ev_c1h <= '0';
end if;
if (p13b ='1' and p2b='1' and p3b='1' and p4b='1' and p5b='1' and p6b='1' and p7b='1' and p8b='1' and p9b='1' and p10b='1' and p11b='1' and p12b='1') then
ev_c2b <= '1';
ev_c2h <= '0';
elsif (p13h ='1' and p2h='1' and p3h='1' and p4h='1' and p5h='1' and p6h='1' and p7h='1' and p8h='1' and p9h='1' and p10h='1' and p11h='1' and p12h='1') then
ev_c2b <= '0';
ev_c2h <= '1';
else
ev_c2b <= '0';
ev_c2h <= '0';
end if;
if (p13b ='1' and p14b='1' and p3b='1' and p4b='1' and p5b='1' and p6b='1' and p7b='1' and p8b='1' and p9b='1' and p10b='1' and p11b='1' and p12b='1') then
ev_c3b <= '1';
ev_c3h <= '0';
elsif (p13h ='1' and p14h='1' and p3h='1' and p4h='1' and p5h='1' and p6h='1' and p7h='1' and p8h='1' and p9h='1' and p10h='1' and p11h='1' and p12h='1') then
ev_c3b <= '0';
ev_c3h <= '1';
else
ev_c3b <= '0';
ev_c3h <= '0';
end if;
if (p13b ='1' and p14b='1' and p15b='1' and p4b='1' and p5b='1' and p6b='1' and p7b='1' and p8b='1' and p9b='1' and p10b='1' and p11b='1' and p12b='1') then
ev_c4b <= '1';
ev_c4h <= '0';
elsif (p13h ='1' and p14h='1' and p15h='1' and p4h='1' and p5h='1' and p6h='1' and p7h='1' and p8h='1' and p9h='1' and p10h='1' and p11h='1' and p12h='1') then
ev_c4b <= '0';
ev_c4h <= '1';
else
ev_c4b <= '0';
ev_c4h <= '0';
end if;
if (p13b ='1' and p14b='1' and p15b='1' and p16b='1' and p5b='1' and p6b='1' and p7b='1' and p8b='1' and p9b='1' and p10b='1' and p11b='1' and p12b='1') then
ev_c5b <= '1';
ev_c5h <= '0';
elsif (p13h ='1' and p14h='1' and p15h='1' and p16h='1' and p5h='1' and p6h='1' and p7h='1' and p8h='1' and p9h='1' and p10h='1' and p11h='1' and p12h='1') then
ev_c5b <= '0';
ev_c5h <= '1';
else
ev_c5b <= '0';
ev_c5h <= '0';
end if;
if (p13b ='1' and p14b='1' and p15b='1' and p16b='1' and p1b='1' and p6b='1' and p7b='1' and p8b='1' and p9b='1' and p10b='1' and p11b='1' and p12b='1') then
ev_c6b <= '1';
ev_c6h <= '0';
elsif (p13h ='1' and p14h='1' and p15h='1' and p16h='1' and p1h='1' and p6h='1' and p7h='1' and p8h='1' and p9h='1' and p10h='1' and p11h='1' and p12h='1') then
ev_c6b <= '0';
ev_c6h <= '1';
else
ev_c6b <= '0';
ev_c6h <= '0';
end if;
if (p13b ='1' and p14b='1' and p15b='1' and p16b='1' and p1b='1' and p2b='1' and p7b='1' and p8b='1' and p9b='1' and p10b='1' and p11b='1' and p12b='1') then
ev_c7b <= '1';
ev_c7h <= '0';
elsif (p13h ='1' and p14h='1' and p15h='1' and p16h='1' and p1h='1' and p2h='1' and p7h='1' and p8h='1' and p9h='1' and p10h='1' and p11h='1' and p12h='1') then
ev_c7b <= '0';
ev_c7h <= '1';
else
ev_c7b <= '0';
ev_c7h <= '0';
end if;
if (p13b ='1' and p14b='1' and p15b='1' and p16b='1' and p1b='1' and p2b='1' and p3b='1' and p8b='1' and p9b='1' and p10b='1' and p11b='1' and p12b='1') then
ev_c8b <= '1';
ev_c8h <= '0';
elsif (p13h ='1' and p14h='1' and p15h='1' and p16h='1' and p1h='1' and p2h='1' and p3h='1' and p8h='1' and p9h='1' and p10h='1' and p11h='1' and p12h='1') then
ev_c8b <= '0';
ev_c8h <= '1';
else
ev_c8b <= '0';
ev_c8h <= '0';
end if;
if (p13b ='1' and p14b='1' and p15b='1' and p16b='1' and p1b='1' and p2b='1' and p3b='1' and p4b='1' and p9b='1' and p10b='1' and p11b='1' and p12b='1') then
ev_c9b <= '1';
ev_c9h <= '0';
elsif (p13h ='1' and p14h='1' and p15h='1' and p16h='1' and p1h='1' and p2h='1' and p3h='1' and p4h='1' and p9h='1' and p10h='1' and p11h='1' and p12h='1') then
ev_c9b <= '0';
ev_c9h <= '1';
else
ev_c9b <= '0';
ev_c9h <= '0';
end if;
if (p13b ='1' and p14b='1' and p15b='1' and p16b='1' and p1b='1' and p2b='1' and p3b='1' and p4b='1' and p5b='1' and p10b='1' and p11b='1' and p12b='1') then
ev_c10b <= '1';
ev_c10h <= '0';
elsif (p13h ='1' and p14h='1' and p15h='1' and p16h='1' and p1h='1' and p2h='1' and p3h='1' and p4h='1' and p5h='1' and p10h='1' and p11h='1' and p12h='1') then
ev_c10b <= '0';
ev_c10h <= '1';
else
ev_c10b <= '0';
ev_c10h <= '0';
end if;
if (p13b ='1' and p14b='1' and p15b='1' and p16b='1' and p1b='1' and p2b='1' and p3b='1' and p4b='1' and p5b='1' and p6b='1' and p11b='1' and p12b='1') then
ev_c11b <= '1';
ev_c11h <= '0';
elsif (p13h ='1' and p14h='1' and p15h='1' and p16h='1' and p1h='1' and p2h='1' and p3h='1' and p4h='1' and p5h='1' and p6h='1' and p11h='1' and p12h='1') then
ev_c11b <= '0';
ev_c11h <= '1';
else
ev_c11b <= '0';
ev_c11h <= '0';
end if;
if (p13b ='1' and p14b='1' and p15b='1' and p16b='1' and p1b='1' and p2b='1' and p3b='1' and p4b='1' and p5b='1' and p6b='1' and p7b='1' and p12b='1') then
ev_c12b <= '1';
ev_c12h <= '0';
elsif (p13h ='1' and p14h='1' and p15h='1' and p16h='1' and p1h='1' and p2h='1' and p3h='1' and p4h='1' and p5h='1' and p6h='1' and p7h='1' and p12h='1') then
ev_c12b <= '0';
ev_c12h <= '1';
else
ev_c12b <= '0';
ev_c12h <= '0';
end if;
if (p13b ='1' and p14b='1' and p15b='1' and p16b='1' and p1b='1' and p2b='1' and p3b='1' and p4b='1' and p5b='1' and p6b='1' and p7b='1' and p8b='1') then
ev_c13b <= '1';
ev_c13h <= '0';
elsif (p13h ='1' and p14h='1' and p15h='1' and p16h='1' and p1h='1' and p2h='1' and p3h='1' and p4h='1' and p5h='1' and p6h='1' and p7h='1' and p8h='1') then
ev_c13b <= '0';
ev_c13h <= '1';
else
ev_c13b <= '0';
ev_c13h <= '0';
end if;
if (p9b ='1' and p14b='1' and p15b='1' and p16b='1' and p1b='1' and p2b='1' and p3b='1' and p4b='1' and p5b='1' and p6b='1' and p7b='1' and p8b='1') then
ev_c14b <= '1';
ev_c14h <= '0';
elsif (p9h ='1' and p14h='1' and p15h='1' and p16h='1' and p1h='1' and p2h='1' and p3h='1' and p4h='1' and p5h='1' and p6h='1' and p7h='1' and p8h='1') then
ev_c14b <= '0';
ev_c14h <= '1';
else
ev_c14b <= '0';
ev_c14h <= '0';
end if;
if (p9b ='1' and p10b='1' and p15b='1' and p16b='1' and p1b='1' and p2b='1' and p3b='1' and p4b='1' and p5b='1' and p6b='1' and p7b='1' and p8b='1') then
ev_c15b <= '1';
ev_c15h <= '0';
elsif (p9h ='1' and p10h='1' and p15h='1' and p16h='1' and p1h='1' and p2h='1' and p3h='1' and p4h='1' and p5h='1' and p6h='1' and p7h='1' and p8h='1') then
ev_c15b <= '0';
ev_c15h <= '1';
else
ev_c15b <= '0';
ev_c15h <= '0';
end if;
if (p9b ='1' and p10b='1' and p11b='1' and p16b='1' and p1b='1' and p2b='1' and p3b='1' and p4b='1' and p5b='1' and p6b='1' and p7b='1' and p8b='1') then
ev_c16b <= '1';
ev_c16h <= '0';
elsif (p9h ='1' and p10h='1' and p11h='1' and p16h='1' and p1h='1' and p2h='1' and p3h='1' and p4h='1' and p5h='1' and p6h='1' and p7h='1' and p8h='1') then
ev_c16b <= '0';
ev_c16h <= '1';
else
ev_c16b <= '0';
ev_c16h <= '0';
end if;
-- 4 ---------------------------------------------------------------------------------------------------
-- 5 ---------------------------------------------------------------------------------------------------
if (ev_c1b ='1' or ev_c2b='1' or ev_c3b='1' or ev_c4b='1' or ev_c5b='1' or ev_c6b='1' or ev_c7b='1' or ev_c8b='1' or ev_c9b='1' or ev_c10b='1' or ev_c11b='1' or ev_c12b='1' or ev_c13b='1' or ev_c14b='1' or ev_c15b='1' or ev_c16b='1'
or ev_c1h ='1' or ev_c2h='1' or ev_c3h='1' or ev_c4h='1' or ev_c5h='1' or ev_c6h='1' or ev_c7h='1' or ev_c8h='1' or ev_c9h='1' or ev_c10h='1' or ev_c11h='1' or ev_c12h='1' or ev_c13h='1' or ev_c14h='1' or ev_c15h='1' or ev_c16h='1'
) then
-- Corner candidate
tmp <= px(23);
tmp(0) <= '1';
out_data <= std_logic_vector (tmp(PIXEL_SIZE-1 downto 0));
else
tmp <= px(23);
tmp(0) <= '0';
out_data <= std_logic_vector (tmp(PIXEL_SIZE-1 downto 0));
end if;
-- 5 ---------------------------------------------------------------------------------------------------
else
tmp <= px(23);
tmp(0) <= '0';
out_data <= std_logic_vector (tmp(PIXEL_SIZE-1 downto 0));
end if;
-- -- 3 ---------------------------------------------------------------------------------------------------
else
tmp <= px(23);
tmp(0) <= '0';
out_data <= std_logic_vector (tmp(PIXEL_SIZE-1 downto 0));
end if;
-- 2 ---------------------------------------------------------------------------------------------------
else
tmp <= px(23);
tmp(0) <= '0';
out_data <= std_logic_vector (tmp(PIXEL_SIZE-1 downto 0));
end if;
-- 1 ---------------------------------------------------------------------------------------------------
end if;
end process;
out_dv <= in_dv;
out_fv <= in_fv;
end bhv;
| gpl-3.0 | ef26babf1701ae44526fe86220a1bba8 | 0.443992 | 2.456899 | false | false | false | false |
buserror/xc3sprog | bscan_spi/bscan_xc5_spi.vhd | 5 | 4,932 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
port (
MOSI_ext : out std_logic;
CSB_ext : out std_logic
);
end top;
architecture Behavioral of top is
signal CAPTURE: std_logic;
signal UPDATE: std_logic;
signal DRCK1: std_logic;
signal TDI: std_logic;
signal TDO1: std_logic;
signal CSB: std_logic := '1';
signal header: std_logic_vector(47 downto 0);
signal len: std_logic_vector(15 downto 0);
signal have_header : std_logic := '0';
signal MISO: std_logic;
signal MOSI: std_logic;
signal SEL1: std_logic;
signal SHIFT: std_logic;
signal RESET: std_logic;
signal CS_GO: std_logic := '0';
signal CS_GO_PREP: std_logic := '0';
signal CS_STOP: std_logic := '0';
signal CS_STOP_PREP: std_logic := '0';
signal RAM_RADDR: std_logic_vector(13 downto 0);
signal RAM_WADDR: std_logic_vector(13 downto 0);
signal DRCK1_INV : std_logic;
signal RAM_DO: std_logic_vector(0 downto 0);
signal RAM_DI: std_logic_vector(0 downto 0);
signal RAM_WE: std_logic := '0';
begin
MOSI_ext <= MOSI;
CSB_ext <= CSB;
DRCK1_INV <= not DRCK1;
RAMB16_S1_S1_inst : RAMB16_S1_S1
port map (
DOA => RAM_DO, -- Port A 1-bit Data Output
DOB => open, -- Port B 1-bit Data Output
ADDRA => RAM_RADDR, -- Port A 14-bit Address Input
ADDRB => RAM_WADDR, -- Port B 14-bit Address Input
CLKA => DRCK1_inv, -- Port A Clock
CLKB => DRCK1, -- Port B Clock
DIA => "0", -- Port A 1-bit Data Input
DIB => RAM_DI, -- Port B 1-bit Data Input
ENA => '1', -- Port A RAM Enable Input
ENB => '1', -- PortB RAM Enable Input
SSRA => '0', -- Port A Synchronous Set/Reset Input
SSRB => '0', -- Port B Synchronous Set/Reset Input
WEA => '0', -- Port A Write Enable Input
WEB => RAM_WE -- Port B Write Enable Input
);
BSCAN_VIRTEX5_inst : BSCAN_VIRTEX5
generic map (
JTAG_CHAIN => 1 -- Value for USER command. Possible values: (1,2,3 or 4)
)
port map (
CAPTURE => CAPTURE, -- CAPTURE output from TAP controller
DRCK => DRCK1, -- Data register output for USER functions
RESET => RESET, -- Reset output from TAP controller
SEL => SEL1, -- USER active output
SHIFT => SHIFT, -- SHIFT output from TAP controller
TDI => TDI, -- TDI output from TAP controller
UPDATE => UPDATE, -- UPDATE output from TAP controller
TDO => TDO1 -- Data input for USER function
);
-- see XAPP1020
STARTUP_VIRTEX5_inst : STARTUP_VIRTEX5
port map (
CFGCLK => open, -- Config logic clock 1-bit output
CFGMCLK => open, -- Config internal osc clock 1-bit output
DINSPI => MISO, -- DIN SPI PROM access 1-bit output
EOS => open, -- End of Startup 1-bit output
TCKSPI => open, -- TCK SPI PROM access 1-bit output
CLK => open, -- Clock input for start-up sequence
GSR => '0', -- Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- Global 3-state input (GTS cannot be used for the port name)
USRCCLKO => DRCK1, -- User CCLK 1-bit input
USRCCLKTS => '0', -- User CCLK 3-state, 1-bit input
USRDONEO => open, -- User Done 1-bit input
USRDONETS => open -- User Done 3-state, 1-bit input
);
MOSI <= TDI;
CSB <= '0' when CS_GO = '1' and CS_STOP = '0' else '1';
RAM_DI <= MISO & "";
TDO1 <= RAM_DO(0);
-- falling edges
process(DRCK1, CAPTURE, RESET, UPDATE, SEL1)
begin
if CAPTURE = '1' or RESET='1' or UPDATE='1' or SEL1='0' then
have_header <= '0';
-- disable CSB
CS_GO_PREP <= '0';
CS_STOP <= '0';
elsif falling_edge(DRCK1) then
-- disable CSB?
CS_STOP <= CS_STOP_PREP;
-- waiting for header?
if have_header='0' then
-- got magic + len
if header(46 downto 15) = x"59a659a6" then
len <= header(14 downto 0) & "0";
have_header <= '1';
-- enable CSB on rising edge (if len > 0?)
if (header(14 downto 0) & "0") /= x"0000" then
CS_GO_PREP <= '1';
end if;
end if;
elsif len /= x"0000" then
len <= len - 1;
end if;
end if;
end process;
-- rising edges
process(DRCK1, CAPTURE, RESET, UPDATE, SEL1)
begin
if CAPTURE = '1' or RESET='1' or UPDATE='1' or SEL1='0' then
-- disable CSB
CS_GO <= '0';
CS_STOP_PREP <= '0';
RAM_WADDR <= (others => '0');
RAM_RADDR <= (others => '0');
RAM_WE <= '0';
elsif rising_edge(DRCK1) then
RAM_RADDR <= RAM_RADDR + 1;
RAM_WE <= not CSB;
if RAM_WE='1' then
RAM_WADDR <= RAM_WADDR + 1;
end if;
header <= header(46 downto 0) & TDI;
-- enable CSB?
CS_GO <= CS_GO_PREP;
-- disable CSB on falling edge
if CS_GO = '1' and len = x"0000" then
CS_STOP_PREP <= '1';
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 6be84afe1da49c3df27f9e5b146f90b0 | 0.592863 | 2.942721 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/ARP/arp_RX.vhd | 1 | 13,224 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp_rx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle receipt of arp pkt
-- ignores other types of pkt
--
-- When it receives an ARP pkt that is either addressed to our IP or is a global request,
-- it outputs for a single clock cycle either recv_who_has or recv_I_have along
-- with associated mac or arp entry data.
--
-- Note that if recv who_has and we have it, then we also assert I_have so that we can cache the rev lookup
-- on the expectation that we will want to reply to this host.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created - refactored from arp v0.02 module
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.arp_types.all;
entity arp_rx is
port (
-- MAC layer RX signals
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- ARP output signals
recv_who_has : out std_logic; -- pulse will be latched
arp_entry_for_who_has : out arp_entry_t; -- target for who_has msg (Iie, who to reply to)
recv_I_have : out std_logic; -- pulse will be latched
arp_entry_for_I_have : out arp_entry_t; -- arp target for I_have msg
-- control and status signals
req_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
-- system signals
our_ip_address : in std_logic_vector (31 downto 0);
rx_clk : in std_logic;
reset : in std_logic
);
end arp_rx;
architecture Behavioral of arp_rx is
type rx_state_t is (IDLE, PARSE, PROCESS_ARP, WAIT_END);
type rx_event_t is (NO_EVENT, DATA);
type count_mode_t is (RST, INCR, HOLD);
type arp_oper_t is (NOP, REQUEST, REPLY);
type tx_state_type is (IDLE, WAIT_MAC, SEND);
-- state variables
signal send_request_needed : std_logic;
signal tx_mac_chn_reqd : std_logic;
signal rx_state : rx_state_t;
signal rx_count : unsigned (7 downto 0);
signal arp_operation : arp_oper_t;
signal arp_req_count : unsigned (7 downto 0);
signal new_arp_entry : arp_entry_t;
-- FIXME - remove these debug state signals
signal arp_err_data : std_logic_vector (7 downto 0);
signal set_err_data : std_logic;
attribute keep : string;
attribute keep of arp_err_data : signal is "true";
-- rx control signals
signal next_rx_state : rx_state_t;
signal set_rx_state : std_logic;
signal rx_event : rx_event_t;
signal rx_count_mode : count_mode_t;
signal set_arp_oper : std_logic;
signal arp_oper_set_val : arp_oper_t;
signal dataval : std_logic_vector (7 downto 0);
signal count_arp_rcvd : std_logic;
signal set_mac5 : std_logic;
signal set_mac4 : std_logic;
signal set_mac3 : std_logic;
signal set_mac2 : std_logic;
signal set_mac1 : std_logic;
signal set_mac0 : std_logic;
signal set_ip3 : std_logic;
signal set_ip2 : std_logic;
signal set_ip1 : std_logic;
signal set_ip0 : std_logic;
-- function to determine whether the rx pkt is an arp pkt and whether we want to process it
-- Returns 1 if we should discard
-- The following will make us ignore the frame (all values hexadecimal):
-- PDU type /= 0806
-- Protocol Type /= 0800
-- Hardware Type /= 1
-- Hardware Length /= 6
-- Protocol Length /= 4
-- Operation /= 1 or 2
-- Target IP /= our IP (i.er. message is not meant for us)
--
function not_our_arp(data : std_logic_vector; count : unsigned; our_ip : std_logic_vector) return std_logic is
begin
if
(count = 12 and data /= x"08") or -- PDU type 0806 : ARP
(count = 13 and data /= x"06") or
(count = 14 and data /= x"00") or -- HW type 1 : eth
(count = 15 and data /= x"01") or
(count = 16 and data /= x"08") or -- Protocol 0800 : IP
(count = 17 and data /= x"00") or
(count = 18 and data /= x"06") or -- HW Length 6
(count = 19 and data /= x"04") or -- protocol length 4
(count = 20 and data /= x"00") or -- operation 1 or 2 (req or reply)
(count = 21 and data /= x"01" and data /= x"02") or
(count = 38 and data /= our_ip(31 downto 24)) or -- target IP is ours
(count = 39 and data /= our_ip(23 downto 16)) or
(count = 40 and data /= our_ip(15 downto 8)) or
(count = 41 and data /= our_ip(7 downto 0))
then
return '1';
else
return '0';
end if;
end function not_our_arp;
begin
rx_combinatorial : process (
-- input signals
data_in, data_in_valid, data_in_last, our_ip_address,
-- state variables
rx_state, rx_count, arp_operation, arp_req_count, arp_err_data, new_arp_entry,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode, set_arp_oper, arp_oper_set_val,
dataval, set_mac5, set_mac4, set_mac3, set_mac2, set_mac1, set_mac0, set_ip3, set_ip2, set_ip1, set_ip0, set_err_data,
count_arp_rcvd
)
begin
-- set output followers
req_count <= std_logic_vector(arp_req_count);
-- set defaults for combinatorial outputs
recv_who_has <= '0';
arp_entry_for_who_has.ip <= (others => '0');
arp_entry_for_who_has.mac <= (others => '0');
recv_I_have <= '0';
arp_entry_for_I_have.ip <= (others => '0');
arp_entry_for_I_have.mac <= (others => '0');
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= HOLD;
set_arp_oper <= '0';
arp_oper_set_val <= NOP;
dataval <= (others => '0');
set_mac5 <= '0';
set_mac4 <= '0';
set_mac3 <= '0';
set_mac2 <= '0';
set_mac1 <= '0';
set_mac0 <= '0';
set_ip3 <= '0';
set_ip2 <= '0';
set_ip1 <= '0';
set_ip0 <= '0';
count_arp_rcvd <= '0';
set_err_data <= '0';
-- determine event (if any)
if data_in_valid = '1' then
rx_event <= DATA;
end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
next_rx_state <= PARSE;
set_rx_state <= '1';
rx_count_mode <= INCR;
end case;
when PARSE =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
rx_count_mode <= INCR;
-- handle early frame termination
if data_in_last = '1' then
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
--else
end if;
-- check for end of frame. Also, detect and discard if not our frame
if not_our_arp(data_in, rx_count, our_ip_address) = '1' then
dataval <= data_in;
set_err_data <= '1';
next_rx_state <= WAIT_END;
set_rx_state <= '1';
else
case (to_integer(rx_count)) is
when 41 =>
next_rx_state <= PROCESS_ARP;
set_rx_state <= '1';
when 21 => -- capture ARP operation
case (data_in) is
when x"01" =>
arp_oper_set_val <= REQUEST;
set_arp_oper <= '1';
when x"02" =>
arp_oper_set_val <= REPLY;
set_arp_oper <= '1';
when others => -- ignore other values
end case;
-- capture source mac addr
when 22 =>
set_mac5 <= '1';
dataval <= data_in;
when 23 =>
set_mac4 <= '1';
dataval <= data_in;
when 24 =>
set_mac3 <= '1';
dataval <= data_in;
when 25 =>
set_mac2 <= '1';
dataval <= data_in;
when 26 =>
set_mac1 <= '1';
dataval <= data_in;
when 27 =>
set_mac0 <= '1';
dataval <= data_in;
when 28 => -- capture source ip addr
set_ip3 <= '1';
dataval <= data_in;
when 29 =>
set_ip2 <= '1';
dataval <= data_in;
when 30 =>
set_ip1 <= '1';
dataval <= data_in;
when 31 =>
set_ip0 <= '1';
dataval <= data_in;
when others => -- do nothing
end case;
end if;
-- end if;
end case;
when PROCESS_ARP =>
next_rx_state <= WAIT_END;
set_rx_state <= '1';
arp_oper_set_val <= NOP;
set_arp_oper <= '1';
case arp_operation is
when NOP => -- (nothing to do)
when REQUEST =>
count_arp_rcvd <= '1';
recv_who_has <= '1';
arp_entry_for_who_has <= new_arp_entry;
-- setting I_Have as well allows us to cache the remote node's entry immediately
recv_I_have <= '1';
arp_entry_for_I_have <= new_arp_entry;
when REPLY =>
count_arp_rcvd <= '1';
recv_I_have <= '1';
arp_entry_for_I_have <= new_arp_entry;
end case;
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if data_in_last = '1' then
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
end if;
end case;
end case;
end process;
rx_sequential : process (rx_clk)
begin
if rising_edge(rx_clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"00";
arp_operation <= NOP;
arp_req_count <= x"00";
arp_err_data <= (others => '0');
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
-- rx_count processing
case rx_count_mode is
when RST =>
rx_count <= x"00";
when INCR =>
rx_count <= rx_count + 1;
when HOLD =>
rx_count <= rx_count;
end case;
-- err data
if set_err_data = '1' then
arp_err_data <= data_in;
else
arp_err_data <= arp_err_data;
end if;
-- arp operation processing
if set_arp_oper = '1' then
arp_operation <= arp_oper_set_val;
else
arp_operation <= arp_operation;
end if;
-- source mac capture
if (set_mac5 = '1') then new_arp_entry.mac(47 downto 40) <= dataval; end if;
if (set_mac4 = '1') then new_arp_entry.mac(39 downto 32) <= dataval; end if;
if (set_mac3 = '1') then new_arp_entry.mac(31 downto 24) <= dataval; end if;
if (set_mac2 = '1') then new_arp_entry.mac(23 downto 16) <= dataval; end if;
if (set_mac1 = '1') then new_arp_entry.mac(15 downto 8) <= dataval; end if;
if (set_mac0 = '1') then new_arp_entry.mac(7 downto 0) <= dataval; end if;
-- source ip capture
if (set_ip3 = '1') then new_arp_entry.ip(31 downto 24) <= dataval; end if;
if (set_ip2 = '1') then new_arp_entry.ip(23 downto 16) <= dataval; end if;
if (set_ip1 = '1') then new_arp_entry.ip(15 downto 8) <= dataval; end if;
if (set_ip0 = '1') then new_arp_entry.ip(7 downto 0) <= dataval; end if;
-- set arp entry request
if count_arp_rcvd = '1' then
-- count another ARP pkt received
arp_req_count <= arp_req_count + 1;
else
arp_req_count <= arp_req_count;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | de88288c1fe126be4bb33a3271362ecf | 0.486388 | 3.68254 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/openmacPkg-p.vhd | 3 | 14,052 | -------------------------------------------------------------------------------
--! @file openmacPkg-p.vhd
--
--! @brief OpenMAC package
--
--! @details This is the openMAC package providing common types.
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
package openmacPkg is
---------------------------------------------------------------------------
-- Configuration
---------------------------------------------------------------------------
--! Packet buffer is internal (e.g. memory blocks)
constant cPktBufLocal : natural := 1;
--! Packet buffer is external
constant cPktBufExtern : natural := 2;
--! Phy port(s) are Rmii
constant cPhyPortRmii : natural := 1;
--! Phy port(s) are Mii
constant cPhyPortMii : natural := 2;
---------------------------------------------------------------------------
-- (R)MII types and constants
---------------------------------------------------------------------------
--! RMII data width
constant cRmiiDataWidth : natural := 2;
--! MII data width
constant cMiiDataWidth : natural := 4;
--! RMII path
type tRmiiPath is record
enable : std_logic;
data : std_logic_vector(cRmiiDataWidth-1 downto 0);
end record;
--! MII path
type tMiiPath is record
enable : std_logic;
data : std_logic_vector(cMiiDataWidth-1 downto 0);
end record;
--! RMII path array
type tRmiiPathArray is array (natural range <>) of tRmiiPath;
--! MII path array
type tMiiPathArray is array (natural range <>) of tMiiPath;
--! RMII link
type tRmii is record
rx : tRmiiPath;
tx : tRmiiPath;
end record;
--! MII link
type tMii is record
rx : tMiiPath;
tx : tMiiPath;
end record;
--! RMII link array
type tRmiiArray is array (natural range <>) of tRmii;
--! MII link array
type tMiiArray is array (natural range <>) of tMii;
--! RMII path initialization
constant cRmiiPathInit : tRmiiPath := (
enable => cInactivated,
data => (others => cInactivated)
);
--! MII path initialization
constant cMiiPathInit : tMiiPath := (
enable => cInactivated,
data => (others => cInactivated)
);
--! RMII link initialization
constant cRmiiInit : tRmii := (
rx => cRmiiPathInit,
tx => cRmiiPathInit
);
--! MII link initialization
constant cMiiInit : tMii := (
rx => cMiiPathInit,
tx => cMiiPathInit
);
--! Functio to get tRmiiPathArray enables.
function rmiiGetEnable ( iArray : tRmiiPathArray ) return std_logic_vector;
--! Procedure to convert tRmiiPathArray to std_logic_vector.
procedure rmiiPathArrayToStdLogicVector (
signal iVector : in tRmiiPathArray;
signal oEnable : out std_logic_vector;
signal oData : out std_logic_vector
);
--! Procedure to convert std_logic_vector to tRmiiPathArray
procedure stdLogicVectorToRmiiPathArray (
signal iEnable : in std_logic_vector;
signal iData : in std_logic_vector;
signal oVector : out tRmiiPathArray
);
--! Procedure to convert tMiiPathArray to std_logic_vector.
procedure miiPathArrayToStdLogicVector (
signal iVector : in tMiiPathArray;
signal oEnable : out std_logic_vector;
signal oData : out std_logic_vector
);
--! Procedure to convert std_logic_vector to tMiiPathArray
procedure stdLogicVectorToMiiPathArray (
signal iEnable : in std_logic_vector;
signal iData : in std_logic_vector;
signal oVector : out tMiiPathArray
);
---------------------------------------------------------------------------
-- Memory mapping
---------------------------------------------------------------------------
--! Memory range type
type tMemRange is record
base : natural;
high : natural;
end record;
--! openMAC memory mapping type
type tMemMap is array (natural range <>) of tMemRange;
--! openMAC memory map count
constant cMemMapCount : natural := 6;
--! openMAC memory map index for DMA Error
constant cMemMapIndex_dmaError : natural := 5;
--! openMAC memory map index for IRQ Table
constant cMemMapIndex_irqTable : natural := 4;
--! openMAC memory map index for SMI
constant cMemMapIndex_smi : natural := 3;
--! openMAC memory map index for MAC RAM
constant cMemMapIndex_macRam : natural := 2;
--! openMAC memory map index for MAC Filter
constant cMemMapIndex_macFilter : natural := 1;
--! openMAC memory map index for MAC Content
constant cMemMapIndex_macCont : natural := 0;
--! openMAC memory mapping table
constant cMemMapTable : tMemMap(cMemMapCount-1 downto 0) := (
(base => 16#1020#, high => 16#102F#), -- DMA error
(base => 16#1010#, high => 16#101F#), -- IRQ table
(base => 16#1000#, high => 16#100F#), -- SMI
(base => 16#0800#, high => 16#0FFF#), -- MAC ram
(base => 16#0800#, high => 16#0BFF#), -- MAC filter
(base => 16#0000#, high => 16#03FF#) -- MAC content
);
---------------------------------------------------------------------------
-- Access delay
---------------------------------------------------------------------------
--! Access delay type
type tMemAccessDelay is record
write : natural;
read : natural;
end record;
--! Access delay type
type tMemAccessDelayArray is array (natural range <>) of tMemAccessDelay;
--! Access delay count
constant cMemAccessDelayCount : natural := 3;
--! Access delay index for PKT BUFFER
constant cMemAccessDelayIndex_pktBuf : natural := 2;
--! Access delay index for MAC TIMER
constant cMemAccessDelayIndex_macTimer : natural := 1;
--! Access delay index for MAC REG
constant cMemAccessDelayIndex_macReg : natural := 0;
--! Access delay table
constant cMemAccessDelayTable : tMemAccessDelayArray(cMemAccessDelayCount-1 downto 0) := (
(write => 0, read => 1), -- PKT BUFFER
(write => 0, read => 1), -- MAC TIMER
(write => 0, read => 1) -- MAC REG
);
--! Access acknowlegde type
type tMemAccessAck is record
write : std_logic;
read : std_logic;
end record;
--! Access acknowledge array type
type tMemAccessAckArray is array (natural range <>) of tMemAccessAck;
---------------------------------------------------------------------------
-- Constants for openmac
---------------------------------------------------------------------------
--! MAC REGISTER address width
constant cMacRegAddrWidth : natural := 13;
--! MAC REGISTER data width
constant cMacRegDataWidth : natural := 16;
--! MAC TIMER address width
constant cMacTimerAddrWidth : natural := 5;
--! MAC TIMER data width
constant cMacTimerDataWidth : natural := 32;
--! MAC PACKET BUFFER data width
constant cPktBufDataWidth : natural := 32;
--! MAC TIME width
constant cMacTimeWidth : natural := 32;
---------------------------------------------------------------------------
-- Constants for activity blinking
---------------------------------------------------------------------------
--! The activity blink frequency [Hz]
constant cActivityFreq : natural := 6;
--! Clock frequency of iClk [Hz]
constant cClkFreq : natural := 50e6;
---------------------------------------------------------------------------
-- Constants for openhub
---------------------------------------------------------------------------
--! Internal port number
constant cHubIntPort : natural := 1;
---------------------------------------------------------------------------
-- Interrupt table
---------------------------------------------------------------------------
--! Interrupt table subtype
subtype tMacRegIrqTable is std_logic_vector(cMacRegDataWidth-1 downto 0);
--! MAC Tx interrupt offset
constant cMacRegIrqTable_macTx : natural := 0;
--! MAC Rx interrupt offset
constant cMacRegIrqTable_macRx : natural := 1;
---------------------------------------------------------------------------
-- DMA Error table
---------------------------------------------------------------------------
--! DMA error table subtype
subtype tMacDmaErrorTable is std_logic_vector(cMacRegDataWidth-1 downto 0);
--! DMA error write (Rx packet transfer)
constant cMacDmaErrorTable_write : natural := 0;
--! DMA error read (Tx packet transfer)
constant cMacDmaErrorTable_read : natural := 8;
end package openmacPkg;
package body openmacPkg is
--! Functio to get tRmiiPathArray enables.
function rmiiGetEnable ( iArray : tRmiiPathArray ) return std_logic_vector is
variable vRes_tmp : std_logic_vector(iArray'range);
begin
vRes_tmp := (others => cInactivated);
for i in iArray'range loop
vRes_tmp(i) := iArray(i).enable;
end loop;
return vRes_tmp;
end function;
--! Procedure to convert tRmiiPathArray to std_logic_vector.
procedure rmiiPathArrayToStdLogicVector (
signal iVector : in tRmiiPathArray;
signal oEnable : out std_logic_vector;
signal oData : out std_logic_vector
) is
variable vVector_tmp : tRmiiPathArray(iVector'length-1 downto 0);
begin
vVector_tmp := iVector;
for i in vVector_tmp'range loop
oEnable(i) <= vVector_tmp(i).enable;
for j in cRmiiDataWidth-1 downto 0 loop
oData(i*cRmiiDataWidth+j) <= vVector_tmp(i).data(j);
end loop;
end loop;
end procedure;
--! Procedure to convert std_logic_vector to tRmiiPathArray
procedure stdLogicVectorToRmiiPathArray (
signal iEnable : in std_logic_vector;
signal iData : in std_logic_vector;
signal oVector : out tRmiiPathArray
) is
variable vVector_tmp : tRmiiPathArray(iEnable'length-1 downto 0);
begin
for i in vVector_tmp'range loop
vVector_tmp(i).enable := iEnable(i);
for j in cRmiiDataWidth-1 downto 0 loop
vVector_tmp(i).data(j) := iData(i*cRmiiDataWidth+j);
end loop;
end loop;
oVector <= vVector_tmp;
end procedure;
--! Procedure to convert tMiiPathArray to std_logic_vector.
procedure miiPathArrayToStdLogicVector (
signal iVector : in tMiiPathArray;
signal oEnable : out std_logic_vector;
signal oData : out std_logic_vector
) is
variable vVector_tmp : tMiiPathArray(iVector'length-1 downto 0);
begin
vVector_tmp := iVector;
for i in vVector_tmp'range loop
oEnable(i) <= vVector_tmp(i).enable;
for j in cMiiDataWidth-1 downto 0 loop
oData(i*cMiiDataWidth+j) <= vVector_tmp(i).data(j);
end loop;
end loop;
end procedure;
--! Procedure to convert std_logic_vector to tMiiPathArray
procedure stdLogicVectorToMiiPathArray (
signal iEnable : in std_logic_vector;
signal iData : in std_logic_vector;
signal oVector : out tMiiPathArray
) is
variable vVector_tmp : tMiiPathArray(iEnable'length-1 downto 0);
begin
for i in vVector_tmp'range loop
vVector_tmp(i).enable := iEnable(i);
for j in cMiiDataWidth-1 downto 0 loop
vVector_tmp(i).data(j) := iData(i*cMiiDataWidth+j);
end loop;
end loop;
oVector <= vVector_tmp;
end procedure;
end package body openmacPkg;
| gpl-2.0 | f2a4b15cd878b38e37d38a5dbf904dea | 0.554868 | 5.034755 | false | false | false | false |
hoglet67/ElectronFpga | src/altera/i2c_loader.vhd | 2 | 9,178 | -- ZX Spectrum for Altera DE1
--
-- Copyright (c) 2009-2011 Mike Stirling
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- * Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- * Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written agreement from the author.
--
-- * License is granted for non-commercial use only. A fee may not be charged
-- for redistributions as source code or in synthesized/hardware form without
-- specific prior written agreement from the author.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_MISC.ALL; -- for AND_REDUCE
use IEEE.NUMERIC_STD.ALL;
entity i2c_loader is
generic (
-- Address of slave to be loaded
device_address : integer := 16#1a#;
-- Number of retries to allow before stopping
num_retries : integer := 0;
-- Length of clock divider in bits. Resulting bus frequency is
-- CLK/2^(log2_divider + 2)
log2_divider : integer := 6
);
port (
CLK : in std_logic;
nRESET : in std_logic;
I2C_SCL : inout std_logic;
I2C_SDA : inout std_logic;
IS_DONE : out std_logic;
IS_ERROR : out std_logic
);
end i2c_loader;
architecture i2c_loader_arch of i2c_loader is
type regs is array(0 to 19) of std_logic_vector(7 downto 0);
constant init_regs : regs := (
-- Left line in, 0dB, unmute
X"00", X"17",
-- Right line in, 0dB, unmute
X"02", X"17",
-- Left headphone out, 0dB
X"04", X"79",
-- Right headphone out, 0dB
X"06", X"79",
-- Audio path, DAC enabled, Line in, Bypass off, mic unmuted
X"08", X"10",
-- Digital path, Unmute, HP filter enabled
X"0A", X"00",
-- Power down mic, clkout and xtal osc
X"0C", X"62",
-- Format 16-bit I2S, no bit inversion or phase changes
X"0E", X"02",
-- -- Sampling control, 8 kHz USB mode (MCLK = 250fs * 6)
-- X"10", X"0D",
-- -- Sampling control, 48 kHz USB mode (MCLK = 250fs)
-- X"10", X"01",
-- -- Sampling control, 48 kHz Normal (MCLK = 256fs) = 62.5KHz when fed with 16MHz
-- X"10", X"00",
-- Sampling control, 96 kHz Normal (MCLK = 128fs) = 125KHz when fed with 16MHz
X"10", X"1C",
-- Activate
X"12", X"01"
);
-- Number of bursts (i.e. total number of registers)
constant burst_length : positive := 2;
-- Number of bytes to transfer per burst
constant num_bursts : positive := (init_regs'length / burst_length);
type state_t is (Idle, Start, Data, Ack, Stop, Pause, Done);
signal state : state_t;
signal phase : std_logic_vector(1 downto 0);
subtype nbit_t is integer range 0 to 7;
signal nbit : nbit_t;
subtype nbyte_t is integer range 0 to burst_length; -- +1 for address byte
signal nbyte : nbyte_t;
subtype thisbyte_t is integer range 0 to init_regs'length; -- +1 for "done"
signal thisbyte : thisbyte_t;
subtype retries_t is integer range 0 to num_retries;
signal retries : retries_t;
signal clken : std_logic;
signal divider : std_logic_vector(log2_divider-1 downto 0);
signal shiftreg : std_logic_vector(7 downto 0);
signal scl_out : std_logic;
signal sda_out : std_logic;
signal nak : std_logic;
begin
-- Create open-drain outputs for I2C bus
I2C_SCL <= '0' when scl_out = '0' else 'Z';
I2C_SDA <= '0' when sda_out = '0' else 'Z';
-- Status outputs are driven both ways
IS_DONE <= '1' when state = Done else '0';
IS_ERROR <= nak;
-- Generate clock enable for desired bus speed
clken <= AND_REDUCE(divider);
process(nRESET,CLK)
begin
if nRESET = '0' then
divider <= (others => '0');
elsif falling_edge(CLK) then
divider <= divider + '1';
end if;
end process;
-- The I2C loader process
process(nRESET,CLK)
begin
if nRESET = '0' then
scl_out <= '1';
sda_out <= '1';
state <= Idle;
phase <= "00";
nbit <= 0;
nbyte <= 0;
thisbyte <= 0;
shiftreg <= (others => '0');
nak <= '0'; -- No error
retries <= num_retries;
elsif rising_edge(CLK) then
if clken = '1' then
-- Next phase by default
phase <= phase + 1;
-- STATE: IDLE
if state = Idle then
-- Start loading the device registers straight away
-- A 'GO' bit could be polled here if required
state <= Start;
phase <= "00";
scl_out <= '1';
sda_out <= '1';
-- STATE: START
elsif state = Start then
-- Generate START condition
case phase is
when "00" =>
-- Drop SDA first
sda_out <= '0';
when "10" =>
-- Then drop SCL
scl_out <= '0';
when "11" =>
-- Advance to next state
-- Shift register loaded with device slave address
state <= Data;
nbit <= 7;
shiftreg <= std_logic_vector(to_unsigned(device_address,7)) & '0'; -- writing
nbyte <= burst_length;
when others =>
null;
end case;
-- STATE: DATA
elsif state = Data then
-- Generate data
case phase is
when "00" =>
-- Drop SCL
scl_out <= '0';
when "01" =>
-- Output data and shift (MSb first)
sda_out <= shiftreg(7);
shiftreg <= shiftreg(6 downto 0) & '0';
when "10" =>
-- Raise SCL
scl_out <= '1';
when "11" =>
-- Next bit or advance to next state when done
if nbit = 0 then
state <= Ack;
else
nbit <= nbit - 1;
end if;
when others =>
null;
end case;
-- STATE: ACK
elsif state = Ack then
-- Generate ACK clock and check for error condition
case phase is
when "00" =>
-- Drop SCL
scl_out <= '0';
when "01" =>
-- Float data
sda_out <= '1';
when "10" =>
-- Sample ack bit
nak <= I2C_SDA;
if I2C_SDA = '1' then
-- Error
nbyte <= 0; -- Close this burst and skip remaining registers
thisbyte <= init_regs'length;
else
-- Hold ACK to avoid spurious stops - this seems to fix a
-- problem with the Wolfson codec which releases the ACK
-- right on the falling edge of the clock pulse. It looks like
-- the device interprets this is a STOP condition and then fails
-- to acknowledge the next byte. We can avoid this by holding the
-- ACK condition for a little longer.
sda_out <= '0';
end if;
-- Raise SCL
scl_out <= '1';
when "11" =>
-- Advance to next state
if nbyte = 0 then
-- No more bytes in this burst - generate a STOP
state <= Stop;
else
-- Generate next byte
state <= Data;
nbit <= 7;
shiftreg <= init_regs(thisbyte);
nbyte <= nbyte - 1;
thisbyte <= thisbyte + 1;
end if;
when others =>
null;
end case;
-- STATE: STOP
elsif state = Stop then
-- Generate STOP condition
case phase is
when "00" =>
-- Drop SCL first
scl_out <= '0';
when "01" =>
-- Drop SDA
sda_out <= '0';
when "10" =>
-- Raise SCL
scl_out <= '1';
when "11" =>
if thisbyte = init_regs'length then
-- All registers done, advance to finished state. This will
-- bring SDA high while SCL is still high, completing the STOP
-- condition
state <= Done;
else
-- Load the next register after a short delay
state <= Pause;
end if;
when others =>
null;
end case;
-- STATE: PAUSE
elsif state = Pause then
-- Delay for one cycle of 'phase' then start the next burst
scl_out <= '1';
sda_out <= '1';
if phase = "11" then
state <= Start;
end if;
-- STATE: DONE
else
-- Finished
scl_out <= '1';
sda_out <= '1';
if nak = '1' and retries > 0 then
-- We can retry in the event of a NAK in case the
-- slave got out of sync for some reason
retries <= retries - 1;
state <= Idle;
end if;
end if;
end if;
end if;
end process;
end i2c_loader_arch;
| gpl-3.0 | acb5e35b2746b0d7e2800460caf4819b | 0.618871 | 3.328981 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_Pixel_Buffer_DMA.vhd | 1 | 16,995 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
USE ieee.numeric_std.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module constantly performs a DMA transfer from a memory device *
-- * containing pixel data to the VGA Controller IP Core. *
-- * *
-- ******************************************************************************
ENTITY Video_System_Pixel_Buffer_DMA IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
GENERIC (
-- Parameters
DEFAULT_BUFFER_ADDRESS :STD_LOGIC_VECTOR(31 DOWNTO 0) := B"00000000000000000000000000000000";
DEFAULT_BACK_BUF_ADDRESS :STD_LOGIC_VECTOR(31 DOWNTO 0) := B"00000000000000000000000000000000";
WW :INTEGER := 8; -- Image width's address width
HW :INTEGER := 7; -- Image height's address width
MW :INTEGER := 15; -- Avalon master's data width
DW :INTEGER := 15; -- Image pixel width
EW :INTEGER := 0; -- Streaming empty signel width
PIXELS :INTEGER := 320; -- Image width - number of pixels
LINES :INTEGER := 240 -- Image height
);
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
slave_address :IN STD_LOGIC_VECTOR( 1 DOWNTO 0);
slave_byteenable :IN STD_LOGIC_VECTOR( 3 DOWNTO 0);
slave_read :IN STD_LOGIC;
slave_write :IN STD_LOGIC;
slave_writedata :IN STD_LOGIC_VECTOR(31 DOWNTO 0);
master_readdata :IN STD_LOGIC_VECTOR(MW DOWNTO 0);
master_readdatavalid :IN STD_LOGIC;
master_waitrequest :IN STD_LOGIC;
stream_ready :IN STD_LOGIC;
-- Bi-Directional
-- Outputs
slave_readdata :BUFFER STD_LOGIC_VECTOR(31 DOWNTO 0);
master_address :BUFFER STD_LOGIC_VECTOR(31 DOWNTO 0);
master_arbiterlock :BUFFER STD_LOGIC;
master_read :BUFFER STD_LOGIC;
stream_data :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_startofpacket :BUFFER STD_LOGIC;
stream_endofpacket :BUFFER STD_LOGIC;
stream_empty :BUFFER STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_valid :BUFFER STD_LOGIC
);
END Video_System_Pixel_Buffer_DMA;
ARCHITECTURE Behaviour OF Video_System_Pixel_Buffer_DMA IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
-- states
TYPE State_Type IS ( STATE_0_IDLE,
STATE_1_WAIT_FOR_LAST_PIXEL,
STATE_2_READ_BUFFER,
STATE_3_MAX_PENDING_READS_STALL
);
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
-- Data fifo signals
SIGNAL fifo_data_in :STD_LOGIC_VECTOR((DW+2) DOWNTO 0);
SIGNAL fifo_read :STD_LOGIC;
SIGNAL fifo_write :STD_LOGIC;
SIGNAL fifo_data_out :STD_LOGIC_VECTOR((DW+2) DOWNTO 0);
SIGNAL fifo_empty :STD_LOGIC;
SIGNAL fifo_full :STD_LOGIC;
SIGNAL fifo_almost_empty :STD_LOGIC;
SIGNAL fifo_almost_full :STD_LOGIC;
-- Internal Registers
SIGNAL buffer_start_address :STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL back_buf_start_address :STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL buffer_swap :STD_LOGIC;
SIGNAL pending_reads :STD_LOGIC_VECTOR( 3 DOWNTO 0);
SIGNAL reading_first_pixel_in_image :STD_LOGIC;
SIGNAL pixel_address :STD_LOGIC_VECTOR(WW DOWNTO 0);
SIGNAL line_address :STD_LOGIC_VECTOR(HW DOWNTO 0);
-- State Machine Registers
SIGNAL s_pixel_buffer :State_Type;
SIGNAL ns_pixel_buffer :State_Type;
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
COMPONENT scfifo
GENERIC (
add_ram_output_register :STRING;
almost_empty_value :INTEGER;
almost_full_value :INTEGER;
intended_device_family :STRING;
lpm_numwords :INTEGER;
lpm_showahead :STRING;
lpm_type :STRING;
lpm_width :INTEGER;
lpm_widthu :INTEGER;
overflow_checking :STRING;
underflow_checking :STRING;
use_eab :STRING
);
PORT (
-- Inputs
clock :IN STD_LOGIC;
sclr :IN STD_LOGIC;
data :IN STD_LOGIC_VECTOR((DW+2) DOWNTO 0);
wrreq :IN STD_LOGIC;
rdreq :IN STD_LOGIC;
-- Outputs
q :BUFFER STD_LOGIC_VECTOR((DW+2) DOWNTO 0);
empty :BUFFER STD_LOGIC;
full :BUFFER STD_LOGIC;
almost_empty :BUFFER STD_LOGIC;
almost_full :BUFFER STD_LOGIC
-- synopsys translate_off
-- synopsys translate_on
);
END COMPONENT;
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
s_pixel_buffer <= STATE_0_IDLE;
ELSE
s_pixel_buffer <= ns_pixel_buffer;
END IF;
END IF;
END PROCESS;
PROCESS (s_pixel_buffer, fifo_almost_empty, ns_pixel_buffer, pending_reads,
master_waitrequest, pixel_address,
line_address,
fifo_almost_full)
BEGIN
CASE (s_pixel_buffer) IS
WHEN STATE_0_IDLE =>
IF (fifo_almost_empty = '1') THEN
ns_pixel_buffer <= STATE_2_READ_BUFFER;
ELSE
ns_pixel_buffer <= STATE_0_IDLE;
END IF;
WHEN STATE_1_WAIT_FOR_LAST_PIXEL =>
IF (pending_reads = B"0000") THEN
ns_pixel_buffer <= STATE_0_IDLE;
ELSE
ns_pixel_buffer <= STATE_1_WAIT_FOR_LAST_PIXEL;
END IF;
WHEN STATE_2_READ_BUFFER =>
IF (master_waitrequest = '0') THEN
IF ((pixel_address = (PIXELS - 1)) AND
(line_address = (LINES - 1))) THEN
ns_pixel_buffer <= STATE_1_WAIT_FOR_LAST_PIXEL;
ELSIF (fifo_almost_full = '1') THEN
ns_pixel_buffer <= STATE_0_IDLE;
ELSIF (pending_reads >= B"1100") THEN
ns_pixel_buffer <= STATE_3_MAX_PENDING_READS_STALL;
ELSE
ns_pixel_buffer <= STATE_2_READ_BUFFER;
END IF;
ELSE
ns_pixel_buffer <= STATE_2_READ_BUFFER;
END IF;
WHEN STATE_3_MAX_PENDING_READS_STALL =>
IF (pending_reads <= B"0111") THEN
ns_pixel_buffer <= STATE_2_READ_BUFFER;
ELSE
ns_pixel_buffer <= STATE_3_MAX_PENDING_READS_STALL;
END IF;
WHEN OTHERS =>
ns_pixel_buffer <= STATE_0_IDLE;
END CASE;
END PROCESS;
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
-- Output Registers
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
slave_readdata <= B"00000000000000000000000000000000";
ELSIF ((slave_read = '1') AND (slave_address = B"00")) THEN
slave_readdata <= buffer_start_address;
ELSIF ((slave_read = '1') AND (slave_address = B"01")) THEN
slave_readdata <= back_buf_start_address;
ELSIF ((slave_read = '1') AND (slave_address = B"10")) THEN
slave_readdata(31 DOWNTO 16) <= STD_LOGIC_VECTOR(TO_UNSIGNED(LINES, 16));
slave_readdata(15 DOWNTO 0) <= STD_LOGIC_VECTOR(TO_UNSIGNED(PIXELS, 16));
ELSIF (slave_read = '1') THEN
slave_readdata(31 DOWNTO 24) <= HW + B"00000001";
slave_readdata(23 DOWNTO 16) <= WW + B"00000001";
slave_readdata(15 DOWNTO 8) <= B"00000000";
slave_readdata( 7 DOWNTO 4) <= B"0010";
slave_readdata( 3 DOWNTO 2) <= B"00";
slave_readdata( 1) <= '0';
slave_readdata( 0) <= buffer_swap;
END IF;
END IF;
END PROCESS;
-- Internal Registers
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
buffer_start_address <= DEFAULT_BUFFER_ADDRESS;
back_buf_start_address <= DEFAULT_BACK_BUF_ADDRESS;
ELSIF ((slave_write = '1') AND (slave_address = B"01")) THEN
IF (slave_byteenable(0) = '1') THEN
back_buf_start_address( 7 DOWNTO 0) <= slave_writedata( 7 DOWNTO 0);
END IF;
IF (slave_byteenable(1) = '1') THEN
back_buf_start_address(15 DOWNTO 8) <= slave_writedata(15 DOWNTO 8);
END IF;
IF (slave_byteenable(2) = '1') THEN
back_buf_start_address(23 DOWNTO 16) <= slave_writedata(23 DOWNTO 16);
END IF;
IF (slave_byteenable(3) = '1') THEN
back_buf_start_address(31 DOWNTO 24) <= slave_writedata(31 DOWNTO 24);
END IF;
ELSIF ((buffer_swap = '1') AND (master_read = '1') AND
(master_waitrequest = '0') AND
((pixel_address = (PIXELS - 1)) AND
(line_address = (LINES - 1)))) THEN
buffer_start_address <= back_buf_start_address;
back_buf_start_address <= buffer_start_address;
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
buffer_swap <= '0';
ELSIF ((slave_write = '1') AND (slave_address = B"00")) THEN
buffer_swap <= '1';
ELSIF ((pixel_address = 0) AND (line_address = 0)) THEN
buffer_swap <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
pending_reads <= B"0000";
ELSIF ((master_read = '1') AND (master_waitrequest = '0')) THEN
IF (master_readdatavalid = '0') THEN
pending_reads <= pending_reads + '1';
END IF;
ELSIF ((master_readdatavalid = '1') AND (pending_reads /= B"0000")) THEN
pending_reads <= pending_reads - '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
reading_first_pixel_in_image <= '0';
ELSIF ((s_pixel_buffer = STATE_0_IDLE) AND
((pixel_address = 0) AND (line_address = 0))) THEN
reading_first_pixel_in_image <= '1';
ELSIF (master_readdatavalid = '1') THEN
reading_first_pixel_in_image <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
pixel_address <= (OTHERS => '0');
ELSIF ((master_read = '1') AND (master_waitrequest = '0')) THEN
IF (pixel_address = (PIXELS - 1)) THEN
pixel_address <= (OTHERS => '0');
ELSE
pixel_address <= pixel_address + 1;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
line_address <= (OTHERS => '0');
ELSIF (((master_read = '1') AND (master_waitrequest = '0')) AND (pixel_address = (PIXELS - 1))) THEN
IF (line_address = (LINES - 1)) THEN
line_address <= (OTHERS => '0');
ELSE
line_address <= line_address + 1;
END IF;
END IF;
END IF;
END PROCESS;
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
-- Output Assignments
master_address <= buffer_start_address +
(line_address & pixel_address & '0');
master_arbiterlock <= '0' WHEN ((s_pixel_buffer = STATE_2_READ_BUFFER) OR
(s_pixel_buffer = STATE_3_MAX_PENDING_READS_STALL)) ELSE
'1';
master_read <= '1' WHEN (s_pixel_buffer = STATE_2_READ_BUFFER) ELSE
'0';
stream_data <= fifo_data_out(DW DOWNTO 0);
stream_startofpacket <= fifo_data_out(DW+1);
stream_endofpacket <= fifo_data_out(DW+2);
stream_empty <= (OTHERS => '0');
stream_valid <= NOT fifo_empty;
-- Internal Assignments
fifo_data_in(DW DOWNTO 0) <= master_readdata(DW DOWNTO 0);
fifo_data_in(DW+1) <= reading_first_pixel_in_image;
fifo_data_in(DW+2) <= '1' WHEN (s_pixel_buffer = STATE_1_WAIT_FOR_LAST_PIXEL) AND
(pending_reads = B"0001") ELSE
'0';
fifo_write <= master_readdatavalid AND NOT fifo_full;
fifo_read <= stream_ready AND stream_valid;
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
Image_Buffer : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
almost_empty_value => 32,
almost_full_value => 96,
intended_device_family => "Cyclone II",
lpm_numwords => 128,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => DW + 3,
lpm_widthu => 7,
overflow_checking => "OFF",
underflow_checking => "OFF",
use_eab => "ON"
)
PORT MAP (
-- Inputs
clock => clk,
sclr => reset,
data => fifo_data_in,
wrreq => fifo_write,
rdreq => fifo_read,
-- Outputs
q => fifo_data_out,
empty => fifo_empty,
full => fifo_full,
almost_empty => fifo_almost_empty,
almost_full => fifo_almost_full
-- synopsys translate_off
-- synopsys translate_on
);
END Behaviour;
| gpl-2.0 | 99d210a1572f3a5604ae999a9c43097c | 0.523272 | 3.639186 | false | false | false | false |
DreamIP/GPStudio | support/component/gp_com/com_to_master_pi/params_flow_decoder.vhd | 1 | 3,968 | -- **************************************************************************
--
-- **************************************************************************
-- 28/11/2014 - creation
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
--Mode burst flag ...
use work.ComFlow_pkg.BURSTMODE;
entity params_flow_decoder is
generic (
MASTER_ADDR_WIDTH : INTEGER := 10
);
port (
clk : in std_logic;
rst_n : in std_logic;
data_i : in std_logic_vector(15 downto 0);
flow_rdy_i : in std_logic;
f_empty_i : in std_logic;
flag_i : in std_logic_vector(7 downto 0);
read_data_o : out std_logic;
-- signaux pour wishbone
-- Addr must be < 16^2
param_addr_o : buffer std_logic_vector(MASTER_ADDR_WIDTH-1 DOWNTO 0);
param_data_o : out std_logic_vector(31 downto 0);
param_wr_o : out std_logic;
update_port_o : out std_logic
);
end params_flow_decoder;
architecture rtl of params_flow_decoder is
---------------------------------------------------------
-- SIGNALS
---------------------------------------------------------
signal param_addr_s : std_logic_vector(31 DOWNTO 0);
-------------
-- FSM Signal
-------------
type fsm_state_t is (Idle, Waiting_one_cycle, DecodeFlag, ReadAddrMSB, ReadAddrLSB, ReadDataMSB, ReadDataLSB);
signal fsm_state : fsm_state_t := Idle;
signal f_empty_r : std_logic := '0';
signal flow_rdy_r : std_logic := '0';
begin
FSM:process (clk, rst_n)
begin
if (rst_n = '0') then
fsm_state <= Idle;
read_data_o <= '0';
flow_rdy_r <= '0';
param_wr_o <= '0';
param_addr_o <= (others=>'0');
param_data_o <= (others=>'0');
update_port_o <= '0';
elsif rising_edge(clk) then
f_empty_r <= f_empty_i; -- reg pour detecter rising/falling edge du signal
flow_rdy_r <= flow_rdy_i;
case fsm_state is
when Idle =>
read_data_o <= '0';
param_wr_o <= '0';
update_port_o<='0';
if (flow_rdy_r='0' and flow_rdy_i='1') then -- si le flow est rdy
fsm_state <= DecodeFlag;
end if;
--Flag pour mode burst ?
when DecodeFlag =>
read_data_o <= '1';
fsm_state <= Waiting_one_cycle;
-- one cycle delay between read_data request and data presence as input
when Waiting_one_cycle =>
fsm_state <= ReadAddrMSB;
when ReadAddrMSB =>
param_addr_s(31 downto 16) <= data_i;
param_wr_o <= '0';
-- escape if case of bad trame
if (f_empty_i='1' ) then
read_data_o <='0';
fsm_state <= Idle;
update_port_o<='1';
else
fsm_state <= ReadAddrLSB;
end if;
when ReadAddrLSB =>
param_addr_s(15 downto 0) <= data_i;
param_wr_o <= '0';
-- escape if case of bad trame
if (f_empty_i='1' ) then
read_data_o <='0';
fsm_state <= Idle;
update_port_o<='1';
else
fsm_state <= ReadDataMSB;
end if;
when ReadDataMSB =>
param_data_o(31 downto 16) <= data_i;
param_wr_o <= '0';
param_addr_o <= param_addr_s(MASTER_ADDR_WIDTH-1 downto 0);
if (f_empty_i='1' ) then
read_data_o <='0';
fsm_state <= Idle;
update_port_o<='1';
else
fsm_state <= ReadDataLSB;
end if;
when ReadDataLSB =>
param_data_o(15 downto 0) <= data_i;
param_wr_o <= '1';
if (f_empty_i='1' ) then
read_data_o <='0';
fsm_state <= Idle;
update_port_o<='1';
elsif (flag_i = BURSTMODE) then
fsm_state <= ReadDataMSB;
param_addr_o <= std_logic_vector( unsigned(param_addr_o) + "1");
else
fsm_state <= ReadAddrMSB;
end if;
end case;
end if;
end process;
end rtl;
| gpl-3.0 | f16239c848e3c4e10645051e47413580 | 0.491431 | 3.233904 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/hostinterface/src/irqGenRtl.vhd | 3 | 7,281 | -------------------------------------------------------------------------------
--! @file irqGenRtl.vhd
--
--! @brief irq generator with sync latch feature
--
--! @details The irq generator is similar to a ordinary interrupt controller,
--! however, it is extended with a "sync-latch" feature. This enables to
--! throttle the interrupt requests and assert the general irq with the sync
--! input signal. Hence, any irq source is deferred to the sync assertion.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use host interface package for specific types
use work.hostInterfacePkg.all;
entity irqGen is
generic (
--! number of interrupt sources
gIrqSourceCount : natural := 3
);
port (
-- Global
--! component wide clock signal
iClk : in std_logic;
--! component wide reset signal
iRst : in std_logic;
-- Irq
--! sync source
iSync : in std_logic;
--! interrupt source vector (pulse)
iIrqSource : in std_logic_vector(gIrqSourceCount downto 1);
--! interrupt signal
oIrq : out std_logic;
-- Control
--! master enable
iIrqMasterEnable : in std_logic;
--! interrupt source enable vector ('right is sync)
iIrqSourceEnable : in std_logic_vector(gIrqSourceCount downto 0);
--! interrupt acknowledge (pulse, 'right is sync)
iIrqAcknowledge : in std_logic_vector(gIrqSourceCount downto 0);
--! interrupt source pending
oIrgPending : out std_logic_vector(gIrqSourceCount downto 0)
);
end irqGen;
architecture Rtl of irqGen is
--! sync rising edge
signal syncRising : std_logic;
--! interrupt register latch
signal irqRegLatch, irqRegLatch_next : std_logic_vector(gIrqSourceCount downto 0);
--! interrupt source store
signal irqSourceStore, irqSourceStore_next : std_logic_vector(gIrqSourceCount downto 1);
--! unregistered irq out signal
signal unregIrq, irq_reg : std_logic;
begin
--! generate pulse for rising edge of sync
syncEdgeDet : entity libcommon.edgedetector
port map (
iArst => iRst,
iClk => iClk,
iEnable => cActivated,
iData => iSync,
oRising => syncRising,
oFalling => open,
oAny => open
);
--! irq registers
clkdReg : process(iClk)
begin
if rising_edge(iClk) then
if iRst = cActivated then
irqRegLatch <= (others => cInactivated);
irqSourceStore <= (others => cInactivated);
irq_reg <= cInactivated;
else
irqRegLatch <= irqRegLatch_next;
irqSourceStore <= irqSourceStore_next;
irq_reg <= unregIrq;
end if;
end if;
end process;
oIrq <= irq_reg;
--! irq register control
combIrqRegCont : process (
iIrqSource,
iIrqAcknowledge,
irqRegLatch,
irqSourceStore,
syncRising,
iIrqSourceEnable(iIrqSourceEnable'right)
)
begin
--default
irqRegLatch_next <= irqRegLatch;
irqSourceStore_next <= irqSourceStore;
-- do acknowledge with latched and source register
for i in gIrqSourceCount downto 1 loop
if iIrqAcknowledge(i) = cActivated then
irqRegLatch_next(i) <= cInactivated;
irqSourceStore_next(i) <= cInactivated;
end if;
end loop;
if iIrqAcknowledge(irqRegLatch'right) = cActivated then
irqRegLatch_next(irqRegLatch'right) <= cInactivated;
end if;
for i in gIrqSourceCount downto 1 loop
if iIrqSource(i) = cActivated then
irqSourceStore_next(i) <= cActivated;
end if;
end loop;
-- trigger irq with sync
if syncRising = cActivated then
-- loop through all irq sources
for i in gIrqSourceCount downto 1 loop
irqRegLatch_next(i) <= irqSourceStore(i);
end loop;
-- activate sync irq if it is enabled
-- (sync irqs in the past are not of interest!)
irqRegLatch_next(irqRegLatch'right) <= iIrqSourceEnable(iIrqSourceEnable'right);
end if;
end process;
--! output irq register
oIrgPending <= irqRegLatch;
--! irq signal generation
combIrqGen : process (
irqRegLatch,
iIrqMasterEnable,
iIrqSourceEnable
)
variable vTmp : std_logic;
begin
--default
unregIrq <= cInactivated;
-- the master enable overrules everything
if iIrqMasterEnable = cActivated then
-- check individual irqs
vTmp := cInactivated;
for i in gIrqSourceCount downto 0 loop
vTmp := vTmp or (iIrqSourceEnable(i) and irqRegLatch(i));
end loop;
-- variable holds irq state
unregIrq <= vTmp;
end if;
end process;
end Rtl;
| gpl-2.0 | 7de1ad5c4d3d1a427a12c404d08e819d | 0.592638 | 5.014463 | false | false | false | false |
makestuff/get-me-started-with | modelsim-altera-gtkwave/dpram_tb.vhdl | 1 | 3,862 | --
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
entity dpram_tb is
--port(
-- dispClk_out : out std_logic
--);
end entity;
architecture behavioural of dpram_tb is
-- Clocks
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
signal fooClk : std_logic; -- display version of sysClk, which transitions 4ns before it
-- Write port
signal writeAddr : std_logic_vector(9 downto 0);
signal writeData : std_logic_vector(3 downto 0);
signal writeEnable : std_logic;
-- Read port
signal readAddr : std_logic_vector(9 downto 0);
signal readData : std_logic_vector(3 downto 0);
begin
--dispClk_out <= dispClk;
-- Instantiate the memory controller for testing
uut: entity work.dpram
port map(
-- Write port
wrclock => sysClk,
wraddress => writeAddr,
data => writeData,
wren => writeEnable,
-- Read port
rdclock => sysClk,
rdaddress => readAddr,
q => readData
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 20 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 3 ns;
fooClk <= sysClk;
wait for 3 ns;
end loop;
end process;
-- Drive the unit under test. Read stimulus from stimulus.sim and write results to results.sim
process
variable inLine : line;
variable outLine : line;
file inFile : text open read_mode is "stimulus.sim";
file outFile : text open write_mode is "results.sim";
begin
writeAddr <= (others => '0');
writeData <= (others => '0');
writeEnable <= '0';
readAddr <= (others => '1');
while ( not endfile(inFile) ) loop
readline(inFile, inLine);
while ( inLine.all'length = 0 or inLine.all(1) = '#' or inLine.all(1) = ht or inLine.all(1) = ' ' ) loop
readline(inFile, inLine);
end loop;
wait until rising_edge(sysClk);
writeAddr <= to_2(inLine.all(1)) & to_4(inLine.all(2)) & to_4(inLine.all(3));
writeData <= to_4(inLine.all(5));
writeEnable <= to_1(inLine.all(7));
readAddr <= to_2(inLine.all(9)) & to_4(inLine.all(10)) & to_4(inLine.all(11));
write(outLine, from_4("00" & writeAddr(9 downto 8)) & from_4(writeAddr(7 downto 4)) & from_4(writeAddr(3 downto 0)));
write(outLine, ' ');
write(outLine, from_4(writeData));
write(outLine, ' ');
write(outLine, writeEnable);
write(outLine, ' ');
write(outLine, '|');
write(outLine, ' ');
write(outLine, from_4("00" & readAddr(9 downto 8)) & from_4(readAddr(7 downto 4)) & from_4(readAddr(3 downto 0)));
write(outLine, ' ');
write(outLine, from_4(readData));
writeline(outFile, outLine);
end loop;
writeAddr <= (others => '0');
writeData <= (others => '0');
writeEnable <= '0';
readAddr <= (others => '1');
wait;
end process;
end architecture;
| gpl-3.0 | 149f0cb2e7a35312cc2b33f4b54f060d | 0.662351 | 3.326443 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/boards/terasic-de2-115/cn-dual-hostif-gpio/quartus/toplevel.vhd | 3 | 18,369 | -------------------------------------------------------------------------------
--! @file toplevel.vhd
--
--! @brief Toplevel of dual Nios CN design
--
--! @details This is the toplevel of the dual Nios CN FPGA design for the
--! INK DE2-115 Evaluation Board.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2015
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library libcommon;
use libcommon.global.all;
entity toplevel is
port (
-- 50 MHZ CLK IN
EXT_CLK : in std_logic;
-- PHY Interfaces
PHY_GXCLK : out std_logic_vector(1 downto 0);
PHY_LINK_n : in std_logic_vector(1 downto 0);
PHY_RXCLK : in std_logic_vector(1 downto 0);
PHY_RXER : in std_logic_vector(1 downto 0);
PHY_RXDV : in std_logic_vector(1 downto 0);
PHY_RXD : in std_logic_vector(7 downto 0);
PHY_TXCLK : in std_logic_vector(1 downto 0);
PHY_TXER : out std_logic_vector(1 downto 0);
PHY_TXEN : out std_logic_vector(1 downto 0);
PHY_TXD : out std_logic_vector(7 downto 0);
PHY_MDIO : inout std_logic_vector(1 downto 0);
PHY_MDC : out std_logic_vector(1 downto 0);
PHY_RESET_n : out std_logic_vector(1 downto 0);
-- EPCS
EPCS_DCLK : out std_logic;
EPCS_SCE : out std_logic;
EPCS_SDO : out std_logic;
EPCS_DATA0 : in std_logic;
-- 2 MB SRAM
SRAM_CE_n : out std_logic;
SRAM_OE_n : out std_logic;
SRAM_WE_n : out std_logic;
SRAM_ADDR : out std_logic_vector(20 downto 1);
SRAM_BE_n : out std_logic_vector(1 downto 0);
SRAM_DQ : inout std_logic_vector(15 downto 0);
-- 64 MBx2 SDRAM
SDRAM_CLK : out std_logic;
SDRAM_CAS_n : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CS_n : out std_logic;
SDRAM_RAS_n : out std_logic;
SDRAM_WE_n : out std_logic;
SDRAM_ADDR : out std_logic_vector(12 downto 0);
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_DQM : out std_logic_vector(3 downto 0);
SDRAM_DQ : inout std_logic_vector(31 downto 0);
-- FLASH 8Mx8
CFI_FLASH_ADDR : out std_logic_vector(22 downto 0);
CFI_FLASH_DATA : inout std_logic_vector(7 downto 0);
CFI_FLASH_WE_n : out std_logic;
CFI_FLASH_CE_n : out std_logic;
CFI_FLASH_OE_n : out std_logic;
CFI_FLASH_RESET_n : out std_logic;
CFI_FLASH_WP_n : out std_logic;
CFI_FLASH_RY : in std_logic;
-- NODE_SWITCH
NODE_SWITCH : in std_logic_vector(7 downto 0);
-- LED
LEDG : out std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(15 downto 0);
-- KEY
KEY_n : in std_logic_vector(3 downto 0);
-- HEX LED
HEX0 : out std_logic_vector(6 downto 0);
HEX1 : out std_logic_vector(6 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
-- LCD
LCD_ON : out std_logic;
LCD_BLON : out std_logic;
LCD_DQ : inout std_logic_vector(7 downto 0);
LCD_E : out std_logic;
LCD_RS : out std_logic;
LCD_RW : out std_logic;
-- BENCHMARK
BENCHMARK : out std_logic_vector(7 downto 0);
-- BENCHMARK_AP
BENCHMARK_AP : out std_logic_vector(7 downto 0)
);
end toplevel;
architecture rtl of toplevel is
component cnDualHostifGpio is
port (
clk25_clk : in std_logic;
clk50_clk : in std_logic := 'X';
clk100_clk : in std_logic;
reset_reset_n : in std_logic := 'X';
tri_state_sram_0_tcm_address_out : out std_logic_vector(20 downto 0);
tri_state_sram_0_tcm_byteenable_n_out : out std_logic_vector(1 downto 0);
tri_state_sram_0_tcm_read_n_out : out std_logic;
tri_state_sram_0_tcm_write_n_out : out std_logic;
tri_state_sram_0_tcm_data_out : inout std_logic_vector(15 downto 0) := (others => 'X');
tri_state_sram_0_tcm_chipselect_n_out : out std_logic;
pcp_0_benchmark_pio_export : out std_logic_vector(7 downto 0);
-- OPENMAC
openmac_0_mii_txEnable : out std_logic_vector(1 downto 0);
openmac_0_mii_txData : out std_logic_vector(7 downto 0);
openmac_0_mii_txClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxError : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxDataValid : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxData : in std_logic_vector(7 downto 0) := (others => 'X');
openmac_0_mii_rxClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_smi_nPhyRst : out std_logic_vector(1 downto 0);
openmac_0_smi_clk : out std_logic_vector(1 downto 0);
openmac_0_smi_dio : inout std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_pktactivity_export : out std_logic;
powerlink_led_export : out std_logic_vector(1 downto 0);
host_0_benchmark_pio_export : out std_logic_vector(7 downto 0);
node_switch_pio_export : in std_logic_vector(7 downto 0) := (others => 'X');
epcs_flash_dclk : out std_logic;
epcs_flash_sce : out std_logic;
epcs_flash_sdo : out std_logic;
epcs_flash_data0 : in std_logic := 'X';
sdram_0_addr : out std_logic_vector(12 downto 0);
sdram_0_ba : out std_logic_vector(1 downto 0);
sdram_0_cas_n : out std_logic;
sdram_0_cke : out std_logic;
sdram_0_cs_n : out std_logic;
sdram_0_dq : inout std_logic_vector(31 downto 0) := (others => 'X');
sdram_0_dqm : out std_logic_vector(3 downto 0);
sdram_0_ras_n : out std_logic;
sdram_0_we_n : out std_logic;
lcd_data : inout std_logic_vector(7 downto 0) := (others => 'X');
lcd_E : out std_logic;
lcd_RS : out std_logic;
lcd_RW : out std_logic;
-- CPU RESET REQUEST
pcp_0_cpu_resetrequest_resetrequest : in std_logic := 'X';
pcp_0_cpu_resetrequest_resettaken : out std_logic;
-- CFI FLASH FOR HOST
tristate_cfi_flash_0_tcm_address_out : out std_logic_vector(22 downto 0);
tristate_cfi_flash_0_tcm_read_n_out : out std_logic;
tristate_cfi_flash_0_tcm_write_n_out : out std_logic;
tristate_cfi_flash_0_tcm_data_out : inout std_logic_vector(7 downto 0) := (others => 'X');
tristate_cfi_flash_0_tcm_chipselect_n_out : out std_logic;
-- Application ports
app_pio_in_port : in std_logic_vector(31 downto 0) := (others => 'X');
app_pio_out_port : out std_logic_vector(31 downto 0)
);
end component cnDualHostifGpio;
-- PLL component
component pll
port (
inclk0 : in std_logic;
c0 : out std_logic;
c1 : out std_logic;
c2 : out std_logic;
c3 : out std_logic;
locked : out std_logic
);
end component;
signal clk25 : std_logic;
signal clk50 : std_logic;
signal clk100 : std_logic;
signal clk100_p : std_logic;
signal pllLocked : std_logic;
signal sramAddr : std_logic_vector(SRAM_ADDR'high downto 0);
signal plk_status_error : std_logic_vector(1 downto 0);
signal openmac_activity : std_logic;
type tSevenSegArray is array (natural range <>) of std_logic_vector(6 downto 0);
constant cNumberOfHex : natural := 8;
signal hex : std_logic_vector(cNumberOfHex*4-1 downto 0);
signal sevenSegArray : tSevenSegArray(cNumberOfHex-1 downto 0);
signal app_input : std_logic_vector(31 downto 0);
signal app_output : std_logic_vector(31 downto 0);
begin
SRAM_ADDR <= sramAddr(SRAM_ADDR'range);
PHY_GXCLK <= (others => '0');
PHY_TXER <= (others => '0');
LCD_ON <= '1';
LCD_BLON <= '1';
SDRAM_CLK <= clk100_p;
CFI_FLASH_RESET_n <= cnInactivated;
CFI_FLASH_WP_n <= cnInactivated;
---------------------------------------------------------------------------
-- Green LED assignments
LEDG <= plk_status_error(0) & -- POWERLINK Status LED
"000" & -- Reserved
(openmac_activity and not PHY_LINK_n(0)) & -- Gated activity
not PHY_LINK_n(0) & -- Link
(openmac_activity and not PHY_LINK_n(1)) & -- Gated activity
not PHY_LINK_n(1); -- Link
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Red LED assignments
LEDR <= x"000" & -- Reserved
"000" & -- Reserved
plk_status_error(1); -- POWERLINK Error LED
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Application Input and Output assignments
-- Input: Map KEY nibble to Application Input
app_input <= x"0000000" & not KEY_n;
-- Output: Map Application Output to HEX LEDs
hex <= app_output;
---------------------------------------------------------------------------
inst : component cnDualHostifGpio
port map (
clk25_clk => clk25,
clk50_clk => clk50,
clk100_clk => clk100,
reset_reset_n => pllLocked,
pcp_0_cpu_resetrequest_resetrequest => '0',
pcp_0_cpu_resetrequest_resettaken => open,
openmac_0_mii_txEnable => PHY_TXEN,
openmac_0_mii_txData => PHY_TXD,
openmac_0_mii_txClk => PHY_TXCLK,
openmac_0_mii_rxError => PHY_RXER,
openmac_0_mii_rxDataValid => PHY_RXDV,
openmac_0_mii_rxData => PHY_RXD,
openmac_0_mii_rxClk => PHY_RXCLK,
openmac_0_smi_nPhyRst => PHY_RESET_n,
openmac_0_smi_clk => PHY_MDC,
openmac_0_smi_dio => PHY_MDIO,
openmac_0_pktactivity_export => openmac_activity,
tri_state_sram_0_tcm_address_out => sramAddr,
tri_state_sram_0_tcm_read_n_out => SRAM_OE_n,
tri_state_sram_0_tcm_byteenable_n_out => SRAM_BE_n,
tri_state_sram_0_tcm_write_n_out => SRAM_WE_n,
tri_state_sram_0_tcm_data_out => SRAM_DQ,
tri_state_sram_0_tcm_chipselect_n_out => SRAM_CE_n,
pcp_0_benchmark_pio_export => BENCHMARK,
node_switch_pio_export => NODE_SWITCH,
powerlink_led_export => plk_status_error,
host_0_benchmark_pio_export => BENCHMARK_AP,
epcs_flash_dclk => EPCS_DCLK,
epcs_flash_sce => EPCS_SCE,
epcs_flash_sdo => EPCS_SDO,
epcs_flash_data0 => EPCS_DATA0,
sdram_0_addr => SDRAM_ADDR,
sdram_0_ba => SDRAM_BA,
sdram_0_cas_n => SDRAM_CAS_n,
sdram_0_cke => SDRAM_CKE,
sdram_0_cs_n => SDRAM_CS_n,
sdram_0_dq => SDRAM_DQ,
sdram_0_dqm => SDRAM_DQM,
sdram_0_ras_n => SDRAM_RAS_n,
sdram_0_we_n => SDRAM_WE_n,
lcd_data => LCD_DQ,
lcd_E => LCD_E,
lcd_RS => LCD_RS,
lcd_RW => LCD_RW,
tristate_cfi_flash_0_tcm_address_out => CFI_FLASH_ADDR,
tristate_cfi_flash_0_tcm_read_n_out => CFI_FLASH_OE_n,
tristate_cfi_flash_0_tcm_write_n_out => CFI_FLASH_WE_n,
tristate_cfi_flash_0_tcm_data_out => CFI_FLASH_DATA,
tristate_cfi_flash_0_tcm_chipselect_n_out => CFI_FLASH_CE_n,
app_pio_in_port => app_input,
app_pio_out_port => app_output
);
-- Pll Instance
pllInst : pll
port map (
inclk0 => EXT_CLK,
c0 => clk50,
c1 => clk100,
c2 => clk25,
c3 => clk100_p,
locked => pllLocked
);
-- bcd to 7 segment
genBcdTo7Seg : for i in cNumberOfHex-1 downto 0 generate
signal tmpHex : std_logic_vector(3 downto 0);
signal tmpSev : std_logic_vector(6 downto 0);
begin
tmpHex <= hex((i+1)*4-1 downto i*4);
sevenSegArray(i) <= tmpSev;
bcdTo7Seg0 : entity libcommon.bcd2led
port map (
iBcdVal => tmpHex,
oLed => open,
onLed => tmpSev
);
end generate genBcdTo7Seg;
-- assign outports to array
HEX0 <= sevenSegArray(0);
HEX1 <= sevenSegArray(1);
HEX2 <= sevenSegArray(2);
HEX3 <= sevenSegArray(3);
HEX4 <= sevenSegArray(4);
HEX5 <= sevenSegArray(5);
HEX6 <= sevenSegArray(6);
HEX7 <= sevenSegArray(7);
end rtl;
| gpl-2.0 | a691b2300b738859abaa5d2d596886f1 | 0.446241 | 4.235416 | false | false | false | false |
DreamIP/GPStudio | support/component/gp_com/flow_to_com/flowto16.vhd | 1 | 5,562 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- N TO 16 BITS Adaptateur
-- valeurs possibles entrée 8,16,32
-- tester avec 1, 2, 4 avec le code en 8to16, devrait fonctionner ou presque ...
-- ALtera libray used for 32 to 16 bits scfifo component
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
use ieee.math_real.all;
entity flowto16 is
generic (
INPUT_SIZE : integer;
FIFO_DEPTH : integer := 32
);
port (
rst_n : in std_logic;
clk : in std_logic;
in_data : in std_logic_vector(INPUT_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_data : out std_logic_vector(15 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end flowto16;
architecture rtl of flowto16 is
-- signaux pour inf a 16bits
constant CPT_MAX : integer := 16/INPUT_SIZE;
type state_t is (Initial, WaitSd);
signal state : state_t := Initial;
signal tmp8bits : std_logic_vector(7 downto 0) := (others=>'0');
-- signaux pour fonctionnement 32 to 16
type state_32t is (Initial, SendLSB, DumpLastMSB, DumpLastLSB, SyncSignal);
signal state_32b : state_32t := Initial;
signal tmp16bits : std_logic_vector(15 downto 0) := (others=>'0');
signal fifo_empty_s : std_logic := '0';
signal databuf : std_logic_vector(31 downto 0) := (others=>'0');
signal aclr_s : std_logic := '0';
signal rdreq_s : std_logic := '0';
signal usedw_s : std_logic_vector(integer(ceil(log2(real(FIFO_DEPTH))))-1 downto 0) := (others=>'0');
signal fifo_empty_r : std_logic :='0';
begin
label_16bits : if (INPUT_SIZE=16) generate
out_fv <= in_fv;
out_dv <= in_dv;
out_data <= in_data;
end generate label_16bits;
label_32bits : if (INPUT_SIZE=32) generate
aclr_s <= not(rst_n);
with state_32b select
rdreq_s <= not(fifo_empty_s) when Initial,
'0' when SendLSB ,
'0' when others;
FIFO : component scfifo
generic map(
intended_device_family => "Cyclone III",
lpm_numwords => FIFO_DEPTH,
lpm_showahead => "OFF",
lpm_type => "scfifo",
lpm_width => 32,
lpm_widthu => integer(ceil(log2(real(FIFO_DEPTH)))),
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
port map
(
data => in_data,
rdreq => rdreq_s,
clock => clk,
wrreq => in_dv,
aclr => aclr_s ,
q => databuf,
empty => fifo_empty_s,
usedw => usedw_s,
full => open
);
process(clk, rst_n)
begin
if (rst_n = '0') then
state_32b <= Initial;
out_fv <= '0';
out_dv <='0';
out_data <= (others=>'0');
tmp16bits <= (others=>'0');
fifo_empty_r <= '1';
-- rdreq_s <= '0';
elsif rising_edge(clk) then
-- out_fv <= in_fv;
out_dv <='0';
fifo_empty_r <= fifo_empty_s;
case state_32b is
when Initial =>
if (in_fv = '1') then
out_fv <='1';
end if;
if( fifo_empty_r = '0' ) then
out_data <= databuf(31 downto 16);
out_dv <='1';
tmp16bits <= databuf(15 downto 0);
state_32b <= SendLSB;
end if;
when SendLSB =>
out_data <= tmp16bits ;
out_dv <='1';
state_32b <= Initial;
-- Dernière donnée : cas particulier
if(fifo_empty_s = '1') then
state_32b <= DumpLastMSB;
end if;
when DumpLastMSB =>
out_dv <='1';
out_data <= databuf(31 downto 16);
state_32b <= DumpLastLSB;
when DumpLastLSB =>
out_dv <='1';
out_data <= databuf(15 downto 0);
state_32b <= SyncSignal;
when SyncSignal =>
if (in_fv = '0') then
out_fv <='0';
out_dv <='0';
end if;
state_32b <= Initial;
end case;
end if;
end process;
end generate label_32bits;
-- Fonctionnement 8 TO 16bits
label_8bits : if INPUT_SIZE = 8 generate
process(clk,rst_n)
begin
if (rst_n = '0') then
state <= Initial;
out_fv <= '0';
out_dv <='0';
out_data <= (others=>'0');
tmp8bits <= (others=>'0');
elsif rising_edge(clk) then
out_fv <= in_fv;
out_dv <='0';
case state is
when Initial =>
if (in_dv ='1' and in_fv='1') then
out_dv <='0';
tmp8bits <= in_data;
state <= WaitSd;
end if;
when WaitSd =>
if (in_dv ='1' and in_fv='1') then
out_data <= tmp8bits & in_data;
out_dv <='1';
state <= Initial;
end if;
end case;
end if;
end process;
end generate label_8bits;
-- Fonctionnement non verifie pour INPUT_SIZE < 8
-- label_inf8bits : if INPUT_SIZE < 8 generate
-- process(clk,rst_n)
-- variable cpt : integer range 0 to CPT_MAX := 0;
-- begin
-- if (rst_n = '0') then
-- state <= Initial;
-- out_fv <= '0';
-- out_dv <='0';
-- out_data <= (others=>'0');
-- tmp <= (others=>'0');
-- cpt = 0;
-- elsif rising_edge(clk) then
-- out_fv <= in_fv;
-- out_dv <='0';
-- case state is
-- when Initial =>
-- if in_dv ='1' then
-- tmp (INPUT_SIZE-1 downto 0) <= in_data;
-- tmp sll INPUT_SIZE;
-- cpt = cpt + 1;
-- if (cpt = CPT_MAX) then
-- state <= WaitSd;
-- cpt = 0;
-- end if;
-- end if;
-- when WaitSd =>
-- if in_dv ='1' then
-- out_data <= tmp ;
-- out_dv <='1';
-- state <= Initial;
-- end if;
-- end case;
-- end if;
-- end process;
-- end generate label_inf8bits;
end rtl;
| gpl-3.0 | a2b86143b82de21cea985b37cc5f9c59 | 0.538835 | 2.837755 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_character_lcd_0.vhd | 1 | 13,643 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module controls 16x2 character LCD on the Altera DE2 Board. *
-- * *
-- ******************************************************************************
ENTITY tracking_camera_system_character_lcd_0 IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
GENERIC (
CURSOR_ON :STD_LOGIC := '1';
BLINKING_ON :STD_LOGIC := '0'
);
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
address :IN STD_LOGIC;
chipselect :IN STD_LOGIC;
read :IN STD_LOGIC;
write :IN STD_LOGIC;
writedata :IN STD_LOGIC_VECTOR( 7 DOWNTO 0);
-- Bidirectionals
LCD_DATA :INOUT STD_LOGIC_VECTOR( 7 DOWNTO 0); -- LCD Data bus 8 bits
-- Outputs
LCD_ON :BUFFER STD_LOGIC; -- LCD Power ON/OFF
LCD_BLON :BUFFER STD_LOGIC; -- LCD Back Light ON/OFF
LCD_EN :BUFFER STD_LOGIC; -- LCD Enable
LCD_RS :BUFFER STD_LOGIC; -- LCD 0-Command/1-Data Select
LCD_RW :BUFFER STD_LOGIC; -- LCD 1-Read/0-Write Select
readdata :BUFFER STD_LOGIC_VECTOR( 7 DOWNTO 0);
waitrequest :BUFFER STD_LOGIC
);
END tracking_camera_system_character_lcd_0;
ARCHITECTURE Behaviour OF tracking_camera_system_character_lcd_0 IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
-- states
TYPE State_Type IS ( LCD_STATE_0_IDLE,
LCD_STATE_1_INITIALIZE,
LCD_STATE_2_START_CHECK_BUSY,
LCD_STATE_3_CHECK_BUSY,
LCD_STATE_4_BEGIN_TRANSFER,
LCD_STATE_5_TRANSFER,
LCD_STATE_6_COMPLETE
);
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
SIGNAL transfer_complete :STD_LOGIC;
SIGNAL done_initialization :STD_LOGIC;
SIGNAL init_send_command :STD_LOGIC;
SIGNAL init_command :STD_LOGIC_VECTOR( 8 DOWNTO 0);
SIGNAL send_data :STD_LOGIC;
SIGNAL data_received :STD_LOGIC_VECTOR( 7 DOWNTO 0);
-- Internal Registers
SIGNAL initialize_lcd_display :STD_LOGIC;
SIGNAL data_to_send :STD_LOGIC_VECTOR( 7 DOWNTO 0);
SIGNAL rs :STD_LOGIC;
SIGNAL rw :STD_LOGIC;
-- State Machine Registers
SIGNAL ns_lcd_controller :State_Type;
SIGNAL s_lcd_controller :State_Type;
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
COMPONENT altera_up_character_lcd_communication
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
data_in :IN STD_LOGIC_VECTOR( 7 DOWNTO 0);
enable :IN STD_LOGIC;
rs :IN STD_LOGIC;
rw :IN STD_LOGIC;
display_on :IN STD_LOGIC;
back_light_on :IN STD_LOGIC;
-- Bidirectionals
LCD_DATA :INOUT STD_LOGIC_VECTOR( 7 DOWNTO 0);
-- Outputs
LCD_ON :BUFFER STD_LOGIC;
LCD_BLON :BUFFER STD_LOGIC;
LCD_EN :BUFFER STD_LOGIC;
LCD_RS :BUFFER STD_LOGIC;
LCD_RW :BUFFER STD_LOGIC;
data_out :BUFFER STD_LOGIC_VECTOR( 7 DOWNTO 0);
transfer_complete :BUFFER STD_LOGIC
);
END COMPONENT;
COMPONENT altera_up_character_lcd_initialization
GENERIC (
CURSOR_ON :STD_LOGIC;
BLINKING_ON :STD_LOGIC
);
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
initialize_LCD_display :IN STD_LOGIC;
command_was_sent :IN STD_LOGIC;
-- Bidirectionals
-- Outputs
done_initialization :BUFFER STD_LOGIC;
send_command :BUFFER STD_LOGIC;
the_command :BUFFER STD_LOGIC_VECTOR( 8 DOWNTO 0)
);
END COMPONENT;
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
s_lcd_controller <= LCD_STATE_0_IDLE;
ELSE
s_lcd_controller <= ns_lcd_controller;
END IF;
END IF;
END PROCESS;
PROCESS (ns_lcd_controller, s_lcd_controller, initialize_lcd_display,
chipselect, done_initialization, transfer_complete, data_received)
BEGIN
-- Defaults
ns_lcd_controller <= LCD_STATE_0_IDLE;
CASE (s_lcd_controller) IS
WHEN LCD_STATE_0_IDLE =>
IF (initialize_lcd_display = '1') THEN
ns_lcd_controller <= LCD_STATE_1_INITIALIZE;
ELSIF (chipselect = '1') THEN
ns_lcd_controller <= LCD_STATE_2_START_CHECK_BUSY;
ELSE
ns_lcd_controller <= LCD_STATE_0_IDLE;
END IF;
WHEN LCD_STATE_1_INITIALIZE =>
IF (done_initialization = '1') THEN
ns_lcd_controller <= LCD_STATE_6_COMPLETE;
ELSE
ns_lcd_controller <= LCD_STATE_1_INITIALIZE;
END IF;
WHEN LCD_STATE_2_START_CHECK_BUSY =>
IF (transfer_complete = '0') THEN
ns_lcd_controller <= LCD_STATE_3_CHECK_BUSY;
ELSE
ns_lcd_controller <= LCD_STATE_2_START_CHECK_BUSY;
END IF;
WHEN LCD_STATE_3_CHECK_BUSY =>
IF ((transfer_complete = '1') AND (data_received(7) = '1')) THEN
ns_lcd_controller <= LCD_STATE_2_START_CHECK_BUSY;
ELSIF ((transfer_complete = '1') AND (data_received(7) = '0')) THEN
ns_lcd_controller <= LCD_STATE_4_BEGIN_TRANSFER;
ELSE
ns_lcd_controller <= LCD_STATE_3_CHECK_BUSY;
END IF;
WHEN LCD_STATE_4_BEGIN_TRANSFER =>
IF (transfer_complete = '0') THEN
ns_lcd_controller <= LCD_STATE_5_TRANSFER;
ELSE
ns_lcd_controller <= LCD_STATE_4_BEGIN_TRANSFER;
END IF;
WHEN LCD_STATE_5_TRANSFER =>
IF (transfer_complete = '1') THEN
ns_lcd_controller <= LCD_STATE_6_COMPLETE;
ELSE
ns_lcd_controller <= LCD_STATE_5_TRANSFER;
END IF;
WHEN LCD_STATE_6_COMPLETE =>
ns_lcd_controller <= LCD_STATE_0_IDLE;
WHEN OTHERS =>
ns_lcd_controller <= LCD_STATE_0_IDLE;
END CASE;
END PROCESS;
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
initialize_lcd_display <= '1';
ELSIF (done_initialization = '1') THEN
initialize_lcd_display <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
data_to_send <= B"00000000";
ELSIF (s_lcd_controller = LCD_STATE_1_INITIALIZE) THEN
data_to_send <= init_command(7 DOWNTO 0);
ELSIF (s_lcd_controller = LCD_STATE_4_BEGIN_TRANSFER) THEN
data_to_send <= writedata(7 DOWNTO 0);
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
rs <= '0';
ELSIF (s_lcd_controller = LCD_STATE_1_INITIALIZE) THEN
rs <= init_command(8);
ELSIF (s_lcd_controller = LCD_STATE_2_START_CHECK_BUSY) THEN
rs <= '0';
ELSIF (s_lcd_controller = LCD_STATE_4_BEGIN_TRANSFER) THEN
rs <= address;
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
rw <= '0';
ELSIF (s_lcd_controller = LCD_STATE_1_INITIALIZE) THEN
rw <= '0';
ELSIF (s_lcd_controller = LCD_STATE_2_START_CHECK_BUSY) THEN
rw <= '1';
ELSIF (s_lcd_controller = LCD_STATE_4_BEGIN_TRANSFER) THEN
rw <= NOT write;
END IF;
END IF;
END PROCESS;
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
-- Output Assignments
readdata <= data_received;
waitrequest <=
'1' WHEN ((chipselect = '1') AND (s_lcd_controller /= LCD_STATE_6_COMPLETE))
ELSE '0';
-- Internal Assignments
send_data <=
init_send_command WHEN (s_lcd_controller = LCD_STATE_1_INITIALIZE) ELSE
'1' WHEN (s_lcd_controller = LCD_STATE_3_CHECK_BUSY) ELSE
'1' WHEN (s_lcd_controller = LCD_STATE_5_TRANSFER) ELSE
'0';
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
Char_LCD_Comm : altera_up_character_lcd_communication
PORT MAP (
-- Inputs
clk => clk,
reset => reset,
data_in => data_to_send,
enable => send_data,
rs => rs,
rw => rw,
display_on => '1',
back_light_on => '1',
-- Bidirectionals
LCD_DATA => LCD_DATA,
-- Outputs
LCD_ON => LCD_ON,
LCD_BLON => LCD_BLON,
LCD_EN => LCD_EN,
LCD_RS => LCD_RS,
LCD_RW => LCD_RW,
data_out => data_received,
transfer_complete => transfer_complete
);
Char_LCD_Init : altera_up_character_lcd_initialization
GENERIC MAP (
CURSOR_ON => CURSOR_ON,
BLINKING_ON => BLINKING_ON
)
PORT MAP (
-- Inputs
clk => clk,
reset => reset,
initialize_LCD_display => initialize_lcd_display,
command_was_sent => transfer_complete,
-- Bidirectionals
-- Outputs
done_initialization => done_initialization,
send_command => init_send_command,
the_command => init_command
);
END Behaviour;
| gpl-2.0 | 0ab4d0ec7f2bdd410f7e937abef9ea9f | 0.505387 | 3.72556 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_nios2_qsys_0_mult_cell.vhd | 1 | 6,672 | --Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.all;
entity tracking_camera_system_nios2_qsys_0_mult_cell is
port (
-- inputs:
signal A_mul_src1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal A_mul_src2 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal A_mul_cell_result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity tracking_camera_system_nios2_qsys_0_mult_cell;
architecture europa of tracking_camera_system_nios2_qsys_0_mult_cell is
component altmult_add
GENERIC (
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_register : STRING;
port_addnsub1 : STRING;
port_addnsub3 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
clock0 : IN STD_LOGIC;
result : OUT STD_LOGIC_VECTOR (width_result-1 DOWNTO 0);
ena0 : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
aclr0 : IN STD_LOGIC
);
end component altmult_add;
signal A_mul_cell_result_part_1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal A_mul_cell_result_part_2 : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal mul_clr : STD_LOGIC;
begin
mul_clr <= NOT reset_n;
the_altmult_add_part_1 : altmult_add
generic map(
addnsub_multiplier_pipeline_aclr1 => "ACLR0",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "UNREGISTERED",
dedicated_multiplier_circuitry => "YES",
input_register_a0 => "UNREGISTERED",
input_register_b0 => "UNREGISTERED",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "CYCLONEII",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR0",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_register => "UNREGISTERED",
port_addnsub1 => "PORT_UNUSED",
port_addnsub3 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_pipeline_aclr_a => "ACLR0",
signed_pipeline_aclr_b => "ACLR0",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "UNREGISTERED",
signed_register_b => "UNREGISTERED",
width_a => 16,
width_b => 16,
width_result => 32
)
port map(
aclr0 => mul_clr,
clock0 => clk,
dataa => A_mul_src1(15 DOWNTO 0),
datab => A_mul_src2(15 DOWNTO 0),
ena0 => std_logic'('1'),
result => A_mul_cell_result_part_1
);
the_altmult_add_part_2 : altmult_add
generic map(
addnsub_multiplier_pipeline_aclr1 => "ACLR0",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "UNREGISTERED",
dedicated_multiplier_circuitry => "YES",
input_register_a0 => "UNREGISTERED",
input_register_b0 => "UNREGISTERED",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "CYCLONEII",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR0",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_register => "UNREGISTERED",
port_addnsub1 => "PORT_UNUSED",
port_addnsub3 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_pipeline_aclr_a => "ACLR0",
signed_pipeline_aclr_b => "ACLR0",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "UNREGISTERED",
signed_register_b => "UNREGISTERED",
width_a => 16,
width_b => 16,
width_result => 16
)
port map(
aclr0 => mul_clr,
clock0 => clk,
dataa => A_mul_src1(31 DOWNTO 16),
datab => A_mul_src2(15 DOWNTO 0),
ena0 => std_logic'('1'),
result => A_mul_cell_result_part_2
);
A_mul_cell_result <= A_EXT (Std_Logic_Vector'(((std_logic_vector'("0") & (A_mul_cell_result_part_1(31 DOWNTO 16))) + (std_logic_vector'("0") & (A_mul_cell_result_part_2))) & A_mul_cell_result_part_1(15 DOWNTO 0)), 32);
end europa;
| gpl-2.0 | 1e9c6f3f991a05a70a4c83f52107a897 | 0.616007 | 3.795222 | false | false | false | false |
ou-cse-378/vhdl-tetris | acode.vhd | 1 | 1,116 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: acode.vhd
-- // Date: 12/9/2004
-- // Description: Display component
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity Acode is
port (
Aen : in STD_LOGIC_VECTOR (3 downto 0);
Asel : in STD_LOGIC_VECTOR (1 downto 0);
A : out STD_LOGIC_VECTOR (3 downto 0)
);
end Acode;
architecture Acode_arch of Acode is
begin
process(Aen, Asel)
begin
A <= "0000";
case Asel is
when "00" =>
if Aen(0) = '1' then
A <= "1000";
end if;
when "01" =>
if Aen(1) = '1' then
A <= "0100";
end if;
when "10" =>
if Aen(2) = '1' then
A <= "0010";
end if;
when others =>
if Aen(3) = '1' then
A <= "0001";
end if;
end case;
end process;
end Acode_arch;
| mit | c0930837bdadbc0a82b5ef7697f6e417 | 0.40233 | 3.695364 | false | false | false | false |
DreamIP/GPStudio | support/process/threshold/hdl/threshold_process.vhd | 1 | 1,337 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity threshold_process is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
threshold_reg : in std_logic_vector(31 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end threshold_process;
architecture rtl of threshold_process is
begin
data_process : process (clk_proc, reset_n)
begin
if(reset_n='0') then
out_data <= (others => '0');
out_dv <= '0';
out_fv <= '0';
elsif(rising_edge(clk_proc)) then
out_dv <= in_dv;
out_fv <= in_fv;
if(in_dv='1' and in_fv='1') then
if(in_data >= threshold_reg(IN_SIZE-1 downto 0)) then
out_data <= (others => '1');
else
out_data <= (others => '0');
end if;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | 711203ebe6db529eb7110febaea771e5 | 0.509349 | 3.073563 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_nios2_qsys_0_jtag_debug_module_wrapper.vhd | 1 | 15,177 | --Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tracking_camera_system_nios2_qsys_0_jtag_debug_module_wrapper is
port (
-- inputs:
signal MonDReg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal break_readreg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal dbrk_hit0_latch : IN STD_LOGIC;
signal dbrk_hit1_latch : IN STD_LOGIC;
signal dbrk_hit2_latch : IN STD_LOGIC;
signal dbrk_hit3_latch : IN STD_LOGIC;
signal debugack : IN STD_LOGIC;
signal monitor_error : IN STD_LOGIC;
signal monitor_ready : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal resetlatch : IN STD_LOGIC;
signal tracemem_on : IN STD_LOGIC;
signal tracemem_trcdata : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tracemem_tw : IN STD_LOGIC;
signal trc_im_addr : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal trc_on : IN STD_LOGIC;
signal trc_wrap : IN STD_LOGIC;
signal trigbrktype : IN STD_LOGIC;
signal trigger_state_1 : IN STD_LOGIC;
-- outputs:
signal jdo : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : OUT STD_LOGIC;
signal st_ready_test_idle : OUT STD_LOGIC;
signal take_action_break_a : OUT STD_LOGIC;
signal take_action_break_b : OUT STD_LOGIC;
signal take_action_break_c : OUT STD_LOGIC;
signal take_action_ocimem_a : OUT STD_LOGIC;
signal take_action_ocimem_b : OUT STD_LOGIC;
signal take_action_tracectrl : OUT STD_LOGIC;
signal take_action_tracemem_a : OUT STD_LOGIC;
signal take_action_tracemem_b : OUT STD_LOGIC;
signal take_no_action_break_a : OUT STD_LOGIC;
signal take_no_action_break_b : OUT STD_LOGIC;
signal take_no_action_break_c : OUT STD_LOGIC;
signal take_no_action_ocimem_a : OUT STD_LOGIC;
signal take_no_action_tracemem_a : OUT STD_LOGIC
);
end entity tracking_camera_system_nios2_qsys_0_jtag_debug_module_wrapper;
architecture europa of tracking_camera_system_nios2_qsys_0_jtag_debug_module_wrapper is
component tracking_camera_system_nios2_qsys_0_jtag_debug_module_tck is
port (
-- inputs:
signal MonDReg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal break_readreg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dbrk_hit0_latch : IN STD_LOGIC;
signal dbrk_hit1_latch : IN STD_LOGIC;
signal dbrk_hit2_latch : IN STD_LOGIC;
signal dbrk_hit3_latch : IN STD_LOGIC;
signal debugack : IN STD_LOGIC;
signal ir_in : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal jtag_state_rti : IN STD_LOGIC;
signal monitor_error : IN STD_LOGIC;
signal monitor_ready : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal resetlatch : IN STD_LOGIC;
signal tck : IN STD_LOGIC;
signal tdi : IN STD_LOGIC;
signal tracemem_on : IN STD_LOGIC;
signal tracemem_trcdata : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tracemem_tw : IN STD_LOGIC;
signal trc_im_addr : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal trc_on : IN STD_LOGIC;
signal trc_wrap : IN STD_LOGIC;
signal trigbrktype : IN STD_LOGIC;
signal trigger_state_1 : IN STD_LOGIC;
signal vs_cdr : IN STD_LOGIC;
signal vs_sdr : IN STD_LOGIC;
signal vs_uir : IN STD_LOGIC;
-- outputs:
signal ir_out : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal jrst_n : OUT STD_LOGIC;
signal sr : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
signal st_ready_test_idle : OUT STD_LOGIC;
signal tdo : OUT STD_LOGIC
);
end component tracking_camera_system_nios2_qsys_0_jtag_debug_module_tck;
component tracking_camera_system_nios2_qsys_0_jtag_debug_module_sysclk is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal ir_in : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal sr : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal vs_udr : IN STD_LOGIC;
signal vs_uir : IN STD_LOGIC;
-- outputs:
signal jdo : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
signal take_action_break_a : OUT STD_LOGIC;
signal take_action_break_b : OUT STD_LOGIC;
signal take_action_break_c : OUT STD_LOGIC;
signal take_action_ocimem_a : OUT STD_LOGIC;
signal take_action_ocimem_b : OUT STD_LOGIC;
signal take_action_tracectrl : OUT STD_LOGIC;
signal take_action_tracemem_a : OUT STD_LOGIC;
signal take_action_tracemem_b : OUT STD_LOGIC;
signal take_no_action_break_a : OUT STD_LOGIC;
signal take_no_action_break_b : OUT STD_LOGIC;
signal take_no_action_break_c : OUT STD_LOGIC;
signal take_no_action_ocimem_a : OUT STD_LOGIC;
signal take_no_action_tracemem_a : OUT STD_LOGIC
);
end component tracking_camera_system_nios2_qsys_0_jtag_debug_module_sysclk;
--synthesis read_comments_as_HDL on
-- component sld_virtual_jtag_basic is
--GENERIC (
-- sld_auto_instance_index : STRING;
-- sld_instance_index : NATURAL;
-- sld_ir_width : NATURAL;
-- sld_mfg_id : NATURAL;
-- sld_sim_action : STRING;
-- sld_sim_n_scan : NATURAL;
-- sld_sim_total_length : NATURAL;
-- sld_type_id : NATURAL;
-- sld_version : NATURAL
-- );
-- PORT (
-- signal virtual_state_udr : OUT STD_LOGIC;
-- signal ir_in : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal tdi : OUT STD_LOGIC;
-- signal virtual_state_sdr : OUT STD_LOGIC;
-- signal jtag_state_rti : OUT STD_LOGIC;
-- signal tck : OUT STD_LOGIC;
-- signal virtual_state_cdr : OUT STD_LOGIC;
-- signal virtual_state_uir : OUT STD_LOGIC;
-- signal ir_out : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal tdo : IN STD_LOGIC
-- );
-- end component sld_virtual_jtag_basic;
--synthesis read_comments_as_HDL off
signal internal_jdo : STD_LOGIC_VECTOR (37 DOWNTO 0);
signal internal_jrst_n : STD_LOGIC;
signal internal_st_ready_test_idle : STD_LOGIC;
signal internal_take_action_break_a : STD_LOGIC;
signal internal_take_action_break_b : STD_LOGIC;
signal internal_take_action_break_c : STD_LOGIC;
signal internal_take_action_ocimem_a : STD_LOGIC;
signal internal_take_action_ocimem_b : STD_LOGIC;
signal internal_take_action_tracectrl : STD_LOGIC;
signal internal_take_action_tracemem_a : STD_LOGIC;
signal internal_take_action_tracemem_b : STD_LOGIC;
signal internal_take_no_action_break_a : STD_LOGIC;
signal internal_take_no_action_break_b : STD_LOGIC;
signal internal_take_no_action_break_c : STD_LOGIC;
signal internal_take_no_action_ocimem_a : STD_LOGIC;
signal internal_take_no_action_tracemem_a : STD_LOGIC;
signal sr : STD_LOGIC_VECTOR (37 DOWNTO 0);
signal vji_cdr : STD_LOGIC;
signal vji_ir_in : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal vji_ir_out : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal vji_rti : STD_LOGIC;
signal vji_sdr : STD_LOGIC;
signal vji_tck : STD_LOGIC;
signal vji_tdi : STD_LOGIC;
signal vji_tdo : STD_LOGIC;
signal vji_udr : STD_LOGIC;
signal vji_uir : STD_LOGIC;
begin
--Change the sld_virtual_jtag_basic's defparams to
--switch between a regular Nios II or an internally embedded Nios II.
--For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
--For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
--the_tracking_camera_system_nios2_qsys_0_jtag_debug_module_tck, which is an e_instance
the_tracking_camera_system_nios2_qsys_0_jtag_debug_module_tck : tracking_camera_system_nios2_qsys_0_jtag_debug_module_tck
port map(
ir_out => vji_ir_out,
jrst_n => internal_jrst_n,
sr => sr,
st_ready_test_idle => internal_st_ready_test_idle,
tdo => vji_tdo,
MonDReg => MonDReg,
break_readreg => break_readreg,
dbrk_hit0_latch => dbrk_hit0_latch,
dbrk_hit1_latch => dbrk_hit1_latch,
dbrk_hit2_latch => dbrk_hit2_latch,
dbrk_hit3_latch => dbrk_hit3_latch,
debugack => debugack,
ir_in => vji_ir_in,
jtag_state_rti => vji_rti,
monitor_error => monitor_error,
monitor_ready => monitor_ready,
reset_n => reset_n,
resetlatch => resetlatch,
tck => vji_tck,
tdi => vji_tdi,
tracemem_on => tracemem_on,
tracemem_trcdata => tracemem_trcdata,
tracemem_tw => tracemem_tw,
trc_im_addr => trc_im_addr,
trc_on => trc_on,
trc_wrap => trc_wrap,
trigbrktype => trigbrktype,
trigger_state_1 => trigger_state_1,
vs_cdr => vji_cdr,
vs_sdr => vji_sdr,
vs_uir => vji_uir
);
--the_tracking_camera_system_nios2_qsys_0_jtag_debug_module_sysclk, which is an e_instance
the_tracking_camera_system_nios2_qsys_0_jtag_debug_module_sysclk : tracking_camera_system_nios2_qsys_0_jtag_debug_module_sysclk
port map(
jdo => internal_jdo,
take_action_break_a => internal_take_action_break_a,
take_action_break_b => internal_take_action_break_b,
take_action_break_c => internal_take_action_break_c,
take_action_ocimem_a => internal_take_action_ocimem_a,
take_action_ocimem_b => internal_take_action_ocimem_b,
take_action_tracectrl => internal_take_action_tracectrl,
take_action_tracemem_a => internal_take_action_tracemem_a,
take_action_tracemem_b => internal_take_action_tracemem_b,
take_no_action_break_a => internal_take_no_action_break_a,
take_no_action_break_b => internal_take_no_action_break_b,
take_no_action_break_c => internal_take_no_action_break_c,
take_no_action_ocimem_a => internal_take_no_action_ocimem_a,
take_no_action_tracemem_a => internal_take_no_action_tracemem_a,
clk => clk,
ir_in => vji_ir_in,
sr => sr,
vs_udr => vji_udr,
vs_uir => vji_uir
);
--vhdl renameroo for output signals
jdo <= internal_jdo;
--vhdl renameroo for output signals
jrst_n <= internal_jrst_n;
--vhdl renameroo for output signals
st_ready_test_idle <= internal_st_ready_test_idle;
--vhdl renameroo for output signals
take_action_break_a <= internal_take_action_break_a;
--vhdl renameroo for output signals
take_action_break_b <= internal_take_action_break_b;
--vhdl renameroo for output signals
take_action_break_c <= internal_take_action_break_c;
--vhdl renameroo for output signals
take_action_ocimem_a <= internal_take_action_ocimem_a;
--vhdl renameroo for output signals
take_action_ocimem_b <= internal_take_action_ocimem_b;
--vhdl renameroo for output signals
take_action_tracectrl <= internal_take_action_tracectrl;
--vhdl renameroo for output signals
take_action_tracemem_a <= internal_take_action_tracemem_a;
--vhdl renameroo for output signals
take_action_tracemem_b <= internal_take_action_tracemem_b;
--vhdl renameroo for output signals
take_no_action_break_a <= internal_take_no_action_break_a;
--vhdl renameroo for output signals
take_no_action_break_b <= internal_take_no_action_break_b;
--vhdl renameroo for output signals
take_no_action_break_c <= internal_take_no_action_break_c;
--vhdl renameroo for output signals
take_no_action_ocimem_a <= internal_take_no_action_ocimem_a;
--vhdl renameroo for output signals
take_no_action_tracemem_a <= internal_take_no_action_tracemem_a;
--synthesis translate_off
vji_tck <= std_logic'('0');
vji_tdi <= std_logic'('0');
vji_sdr <= std_logic'('0');
vji_cdr <= std_logic'('0');
vji_rti <= std_logic'('0');
vji_uir <= std_logic'('0');
vji_udr <= std_logic'('0');
vji_ir_in <= std_logic_vector'("00");
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- tracking_camera_system_nios2_qsys_0_jtag_debug_module_phy : sld_virtual_jtag_basic
-- generic map(
-- sld_auto_instance_index => "YES",
-- sld_instance_index => 0,
-- sld_ir_width => 2,
-- sld_mfg_id => 70,
-- sld_sim_action => "",
-- sld_sim_n_scan => 0,
-- sld_sim_total_length => 0,
-- sld_type_id => 34,
-- sld_version => 3
-- )
-- port map(
-- ir_in => vji_ir_in,
-- ir_out => vji_ir_out,
-- jtag_state_rti => vji_rti,
-- tck => vji_tck,
-- tdi => vji_tdi,
-- tdo => vji_tdo,
-- virtual_state_cdr => vji_cdr,
-- virtual_state_sdr => vji_sdr,
-- virtual_state_udr => vji_udr,
-- virtual_state_uir => vji_uir
-- );
--
--synthesis read_comments_as_HDL off
end europa;
| gpl-2.0 | ca7a791fb44fad701fc21b5a665e6704 | 0.585952 | 3.770683 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/types/eth_pkg.vhd | 1 | 3,800 | -------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : eth_pkg.vhd
-- Author : liyi <[email protected]>
-- Company : OE@HUST
-- Created : 2012-11-04
-- Last update: 2012-12-03
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-11-04 1.0 root Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
PACKAGE eth_pkg IS
CONSTANT ETH_TYPE_IPv4 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0800";
CONSTANT ETH_TYPE_ARP : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0806";
CONSTANT ETH_TYPE_RARP : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"8035";
CONSTANT ETH_TYPE_8021Q : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"8100";
CONSTANT ETH_TYPE_CTRL : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"8808";
CONSTANT ETH_TYPE_JUMBO : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"8870";
CONSTANT IPv4_PROTOCOL_ICMP : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"01";
CONSTANT IPv4_PROTOCOL_TCP : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"06";
CONSTANT IPv4_PROTOCOL_UDP : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"11";
-- multicast address for control frame
CONSTANT MAC_ADDR_CTRL : STD_LOGIC_VECTOR(47 DOWNTO 0) := X"0180C2000001";
CONSTANT TCP_OPT_EOL : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"00"; --end of list
CONSTANT TCP_OPT_NOP : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"01";
CONSTANT TCP_OPT_MSS : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"02";
CONSTANT TCP_OPT_WS : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"03"; --window scale
-----------------------------------------------------------------------------
-- registers address
-----------------------------------------------------------------------------
CONSTANT REG_ADDR_WIDTH : INTEGER := 5;
CONSTANT MDIO_MODER_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(0, REG_ADDR_WIDTH);
CONSTANT MDIO_CMD_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(1, REG_ADDR_WIDTH);
CONSTANT MDIO_ADDR_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(2, REG_ADDR_WIDTH);
CONSTANT MDIO_TxD_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(3, REG_ADDR_WIDTH);
CONSTANT MDIO_RxD_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(4, REG_ADDR_WIDTH);
CONSTANT RGMII_STATUS_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(5, REG_ADDR_WIDTH);
CONSTANT MAC_ADDR0L_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(6, REG_ADDR_WIDTH);
CONSTANT MAC_ADDR0H_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(7, REG_ADDR_WIDTH);
CONSTANT MAC_ADDR1L_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(8, REG_ADDR_WIDTH);
CONSTANT MAC_ADDR1H_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(9, REG_ADDR_WIDTH);
CONSTANT IP_ADDR0_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(10, REG_ADDR_WIDTH);
CONSTANT IP_ADDR1_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(11, REG_ADDR_WIDTH);
CONSTANT LISTEN_PORT_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(12, REG_ADDR_WIDTH);
END PACKAGE eth_pkg;
-------------------------------------------------------------------------------
PACKAGE BODY eth_pkg IS
END PACKAGE BODY eth_pkg;
| gpl-3.0 | 2a72746de7ce2f8dc16e085e96542e87 | 0.529474 | 3.678606 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/numeric/numeric_pkg.vhdl | 1 | 5,525 | --
-- Numeric Package
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2015-2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--! Related with numerical/mathematical operations
--! Mainly composed by functions to convert between types integers and std_logic_vectors, not covered in the packages std_logic_1164 and numeric_std. It also contains functions to calculate log, min and max of integers, mainly useful to work with generics, counters and function to convert between Binary Natural and Gray codes.
package Numeric is
--! Converts a std_logic into an integer
function to_integer(arg: std_logic) return integer;
--! Converts a std_logic_vector into an integer
function to_integer(arg: std_logic_vector) return integer;
--! Converts a std_logic_vector into a natural
function to_natural(arg: std_logic_vector) return natural;
--! Converts an integer into a std_logic
function to_logic(arg: integer) return std_logic;
--! Converts an integer into a std_logic_vector
function to_vector(arg: integer; size: positive; sign: boolean:=FALSE) return std_logic_vector;
--! Bin to Gray conversion between unsigned types
function bin2gray(arg: unsigned) return unsigned;
--! Bin to Gray conversion between std_logic_vectorpes
function bin2gray(arg: std_logic_vector) return std_logic_vector;
--! Gray to Bin conversion between unsigned types
function gray2bin(arg: unsigned) return unsigned;
--! Gray to Bin conversion between std_logic_vector types
function gray2bin(arg: std_logic_vector) return std_logic_vector;
--! Calculation of the minimum between two integers
function minimum(left, right: in integer) return integer;
--! Calculation of the maximum between two integers
function maximum(left, right: in integer) return integer;
--! Calculation of the ceiling of the logarithm to the base 2 of a integer
function clog2(arg: natural) return natural;
component Counter is
generic (
DEPTH : positive:=8
);
port (
clk_i : in std_logic; -- Clock
rst_i : in std_logic; -- Reset
ena_i : in std_logic; -- Input Enable
count_o : out std_logic_vector(clog2(DEPTH)-1 downto 0); -- Counter value
last_o : out std_logic -- Last value
);
end component Counter;
end package Numeric;
package body Numeric is
----------------------------------------------------------------------------
-- Conversions to integer
----------------------------------------------------------------------------
function to_integer(arg: std_logic) return integer is
begin
if arg='1' then
return 1;
end if;
return 0;
end to_integer;
function to_integer(arg: std_logic_vector) return integer is
begin
return to_integer(signed(arg));
end to_integer;
function to_natural(arg: std_logic_vector) return natural is
begin
return to_integer(unsigned(arg));
end to_natural;
----------------------------------------------------------------------------
-- Conversions to standard logic
----------------------------------------------------------------------------
function to_logic(arg: integer) return std_logic is
begin
if arg=1 then
return '1';
end if;
return '0';
end to_logic;
function to_vector(arg: integer; size: positive; sign: boolean:=FALSE) return std_logic_vector is
begin
if not(sign) then
return std_logic_vector(to_unsigned(arg,size));
end if;
return std_logic_vector(to_signed(arg,size));
end function to_vector;
----------------------------------------------------------------------------
-- Conversions betwenn Binary and Gray codes
----------------------------------------------------------------------------
function bin2gray(arg: unsigned) return unsigned is
begin
return shift_right(arg, 1) xor arg;
end bin2gray;
function bin2gray(arg: std_logic_vector) return std_logic_vector is
begin
return std_logic_vector(bin2gray(unsigned(arg)));
end bin2gray;
function gray2bin(arg: unsigned) return unsigned is
variable gray, bin : unsigned(arg'high downto 0);
begin
gray := arg;
bin(bin'high):=gray(gray'high);
for i in gray'high-1 downto 0 loop
bin(i):=bin(i+1) xor gray(i);
end loop;
return bin;
end gray2bin;
function gray2bin(arg: std_logic_vector) return std_logic_vector is
begin
return std_logic_vector(gray2bin(unsigned(arg)));
end gray2bin;
----------------------------------------------------------------------------
-- Math Functions
----------------------------------------------------------------------------
function minimum (left, right: in integer) return integer is
begin
if left < right then return left;
else return right;
end if;
end function minimum;
function maximum (left, right: in integer) return integer is
begin
if left > right then return left;
else return right;
end if;
end function maximum;
function clog2 (arg : natural) return natural is
begin
for i in 0 to 31 loop
if arg <= 2**i then
return i;
end if;
end loop;
return 32;
end function clog2;
----------------------------------------------------------------------------
end package body Numeric;
| bsd-3-clause | 77cc099292858a1388d2a71887879ece | 0.588054 | 4.473684 | false | false | false | false |
hoglet67/ElectronFpga | src/altera/i2s_intf.vhd | 2 | 7,214 | -- ZX Spectrum for Altera DE1
--
-- Copyright (c) 2009-2011 Mike Stirling
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- * Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- * Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written agreement from the author.
--
-- * License is granted for non-commercial use only. A fee may not be charged
-- for redistributions as source code or in synthesized/hardware form without
-- specific prior written agreement from the author.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity i2s_intf is
generic(
-- CLK is now the 32Mhz clock
inclk_rate : positive := 32000000;
-- The DAC is fed with a 16MHz clock, and configured to FS=MCLK/125, giving FS=125KHz
sample_rate : positive := 125000;
preamble : positive := 1; -- I2S
word_length : positive := 16
);
port (
-- 2x MCLK in (e.g. 24 MHz for WM8731 USB mode)
CLK : in std_logic;
nRESET : in std_logic;
-- Parallel IO
PCM_INL : out std_logic_vector(word_length - 1 downto 0);
PCM_INR : out std_logic_vector(word_length - 1 downto 0);
PCM_OUTL : in std_logic_vector(word_length - 1 downto 0);
PCM_OUTR : in std_logic_vector(word_length - 1 downto 0);
-- Codec interface (right justified mode)
-- MCLK is generated at half of the CLK input
I2S_MCLK : out std_logic;
-- LRCLK is equal to the sample rate and is synchronous to
-- MCLK. It must be related to MCLK by the oversampling ratio
-- given in the codec datasheet.
I2S_LRCLK : out std_logic;
-- Data is shifted out on the falling edge of BCLK, sampled
-- on the rising edge. The bit rate is determined such that
-- it is fast enough to fit preamble + word_length bits into
-- each LRCLK half cycle. The last cycle of each word may be
-- stretched to fit to LRCLK. This is OK at least for the
-- WM8731 codec.
-- The first falling edge of each timeslot is always synchronised
-- with the LRCLK edge.
I2S_BCLK : out std_logic;
-- Output bitstream
I2S_DOUT : out std_logic;
-- Input bitstream
I2S_DIN : in std_logic
);
end i2s_intf;
architecture i2s_intf_arch of i2s_intf is
-- this works out at 256
constant ratio_inclk_fs : positive := (inclk_rate / sample_rate);
-- this work out at 127
constant lrdivider_top : positive := (ratio_inclk_fs / 2) - 1;
-- this works out as 1; erring on the small side is fine
constant bdivider_top : positive := (ratio_inclk_fs / 8 / (preamble + word_length) * 2) - 1;
-- this works out as 17
constant nbits : positive := preamble + word_length;
subtype lrdivider_t is integer range 0 to lrdivider_top;
subtype bdivider_t is integer range 0 to bdivider_top;
subtype bitcount_t is integer range 0 to nbits;
signal lrdivider : lrdivider_t := lrdivider_top;
signal bdivider : bdivider_t := bdivider_top;
signal bitcount : bitcount_t := nbits;
signal mclk_r : std_logic := '0';
signal lrclk_r : std_logic := '0';
signal bclk_r : std_logic := '0';
-- Shift register is long enough for the number of data bits
-- plus the preamble, plus an extra bit on the right to register
-- the incoming data
signal shiftreg : std_logic_vector(nbits downto 0);
begin
I2S_MCLK <= mclk_r;
I2S_LRCLK <= lrclk_r;
I2S_BCLK <= bclk_r;
I2S_DOUT <= shiftreg(nbits); -- data goes out MSb first
process(nRESET,CLK)
begin
if nRESET = '0' then
PCM_INL <= (others => '0');
PCM_INR <= (others => '0');
-- Preload down-counters for clock generation
lrdivider <= lrdivider_top;
bdivider <= bdivider_top;
bitcount <= nbits;
mclk_r <= '0';
lrclk_r <= '0';
bclk_r <= '0';
shiftreg <= (others => '0');
elsif rising_edge(CLK) then
-- Generate MCLK at half input clock rate
mclk_r <= not mclk_r;
-- Generate LRCLK at rate specified by codec configuration
if lrdivider = 0 then
-- LRCLK divider has reached 0 - start again from the top
lrdivider <= lrdivider_top;
-- Generate LRCLK edge and sync the BCLK counter
lrclk_r <= not lrclk_r;
bclk_r <= '0';
bitcount <= nbits; -- 1 extra required for setup
bdivider <= bdivider_top;
-- Load shift register with output data padding preamble
-- with 0s. Load output buses with input word from the
-- previous timeslot.
shiftreg(nbits downto nbits - preamble + 1) <= (others => '0');
if lrclk_r = '0' then
-- Previous channel input is LEFT. This is available in the
-- shift register at the end of a cycle, right justified
PCM_INL <= shiftreg(word_length - 1 downto 0);
-- Next channel to output is RIGHT. Load this into the
-- shift register at the start of a cycle, left justified
shiftreg(word_length downto 1) <= PCM_OUTR;
else
-- Previous channel input is RIGHT
PCM_INR <= shiftreg(word_length - 1 downto 0);
-- Next channel is LEFT
shiftreg(word_length downto 1) <= PCM_OUTL;
end if;
else
-- Decrement the LRCLK counter
lrdivider <= lrdivider - 1;
-- Generate BCLK at a suitable rate to fit the required number
-- of bits into each timeslot. Data is changed on the falling edge,
-- sampled on the rising edge
if bdivider = 0 then
-- If all bits have been output for this phase then
-- stop and wait to sync back up with LRCLK
if bitcount > 0 then
-- Reset
bdivider <= bdivider_top;
-- Toggle BCLK
bclk_r <= not bclk_r;
if bclk_r = '0' then
-- Rising edge - shift in current bit and decrement bit counter
bitcount <= bitcount - 1;
shiftreg(0) <= I2S_DIN;
else
-- Falling edge - shift out next bit
shiftreg(nbits downto 1) <= shiftreg(nbits - 1 downto 0);
end if;
end if;
else
-- Decrement the BCLK counter
bdivider <= bdivider - 1;
end if;
end if;
end if;
end process;
end i2s_intf_arch;
| gpl-3.0 | fdf7c0e53532a8a84290d636d391b597 | 0.685334 | 3.56952 | false | false | false | false |
DreamIP/GPStudio | support/process/prewitt/hdl/prewitt.vhd | 1 | 3,881 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity prewitt is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end prewitt;
architecture rtl of prewitt is
component prewitt_process
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_width : in std_logic_vector(15 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component prewitt_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal widthimg_reg_width : std_logic_vector (15 downto 0);
begin
prewitt_process_inst : prewitt_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_width => widthimg_reg_width,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
prewitt_slave_inst : prewitt_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_width => widthimg_reg_width,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
| gpl-3.0 | cfc3834b908282992a9b97b052f99f3d | 0.461221 | 3.348576 | false | false | false | false |
DreamIP/GPStudio | support/io/com/hdl/com_master.vhd | 1 | 2,495 | -- This entity receives packets that are send on MASTER_PORT then extracts parameters values
-- and address before sending them on the Parameter Interconnect.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.com_package.all;
entity com_master is
generic (
pi_size_addr : integer:=2
);
port (
clk : in STD_LOGIC;
reset_n : in STD_LOGIC;
flow_in : in flow_t;
master_addr_o : out std_logic_vector(pi_size_addr downto 0);
master_wr_o : out std_logic;
master_rd_o : out std_logic;
master_datawr_o : out std_logic_vector(31 downto 0);
master_datard_i : in std_logic_vector(31 downto 0)
);
end com_master;
architecture RTL of com_master is
type master_fsm is (idle, get_data, write_param);
signal state : master_fsm;
signal count : unsigned(3 downto 0);
signal rx_dv_dl : std_logic;
signal master_datawr_o_s : std_logic_vector(31 downto 0);
begin
master_rd_o <= '0';
master_datawr_o <= master_datawr_o_s;
process(clk, reset_n)
begin
if RESET_n='0' then
master_wr_o <= '0';
state <= idle;
master_datawr_o_s <= (others => '0');
master_addr_o <= (others => '0');
elsif clk'event and clk='1' then
rx_dv_dl <= flow_in.dv;
case (state) is
when idle =>
master_wr_o <= '0';
if flow_in.dv='1' and rx_dv_dl='0' then
state <= get_data;
master_datawr_o_s(7 downto 0) <= flow_in.data;
count <= x"0";
end if;
when get_data =>
count <= count + 1;
if count < x"3" then
master_datawr_o_s <= master_datawr_o_s(23 downto 0) & flow_in.data;
elsif count = x"3" then
master_addr_o <= flow_in.data(pi_size_addr downto 0);
else
state <= write_param;
end if;
when write_param =>
master_wr_o <= '1';
state <= idle;
when others =>
state <= idle;
end case;
end if;
end process;
end RTL;
| gpl-3.0 | 9f24b4474524581c5bcfa099d4bf1db8 | 0.46493 | 3.814985 | false | false | false | false |
DreamIP/GPStudio | support/component/gp_com/gp_com.vhd | 1 | 13,856 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ComFlow_pkg.all;
-- Top level du driver USB
-- 4 output flows max
-- 2 input flow max
-- TODO
-- PASSER LES Identifiants de FLOW en générique du driver:
-- ca permettrait de specifier les valeurs des identifiants des trames par GPStudio
-- Header trame USB
-- TRAME USB 16 bits : permier mot header: FLOW ID/FLAG (8b/8b)
-- : second mot header : Packet number (16b)
entity gp_com is
generic (
IN0_SIZE : INTEGER := 8;
IN1_SIZE : INTEGER := 8;
IN2_SIZE : INTEGER := 8;
IN3_SIZE : INTEGER := 8;
OUT0_SIZE : INTEGER := 8;
OUT1_SIZE : INTEGER := 8;
IN0_NBWORDS : INTEGER := 1280;
IN1_NBWORDS : INTEGER := 1280;
IN2_NBWORDS : INTEGER := 1280;
IN3_NBWORDS : INTEGER := 1280;
OUT0_NBWORDS : INTEGER := 2000;
OUT1_NBWORDS : INTEGER := 2000;
CLK_PROC_FREQ : INTEGER;
CLK_HAL_FREQ : INTEGER;
DATA_HAL_SIZE : INTEGER;
PACKET_HAL_SIZE : INTEGER;
MASTER_ADDR_WIDTH : INTEGER
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------ hal connections ------
clk_hal : in std_logic;
from_hal_data : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
from_hal_wr : in std_logic;
from_hal_full : out std_logic;
from_hal_pktend : in std_logic;
to_hal_data : out std_logic_vector(DATA_HAL_SIZE-1 downto 0);
to_hal_rd : in std_logic;
to_hal_empty : out std_logic;
to_hal_rdy : out std_logic;
to_hal_size_packet : out std_logic_vector(15 downto 0);
-------- slave -------
status_enable : in std_logic;
flow_in0_enable : in std_logic;
flow_in1_enable : in std_logic;
flow_in2_enable : in std_logic;
flow_in3_enable : in std_logic;
------ in0 flow ------
in0_data : in std_logic_vector(IN0_SIZE-1 downto 0);
in0_fv : in std_logic;
in0_dv : in std_logic;
------ in1 flow ------
in1_data : in std_logic_vector(IN1_SIZE-1 downto 0);
in1_fv : in std_logic;
in1_dv : in std_logic;
------ in2 flow ------
in2_data : in std_logic_vector(IN2_SIZE-1 downto 0);
in2_fv : in std_logic;
in2_dv : in std_logic;
------ in3 flow ------
in3_data : in std_logic_vector(IN3_SIZE-1 downto 0);
in3_fv : in std_logic;
in3_dv : in std_logic;
------ out0 flow ------
out0_data : out std_logic_vector(OUT0_SIZE-1 downto 0);
out0_fv : out std_logic;
out0_dv : out std_logic;
------ out1 flow ------
out1_data : out std_logic_vector(OUT1_SIZE-1 downto 0);
out1_fv : out std_logic;
out1_dv : out std_logic;
---- ===== Masters =====
------ bus_master ------
master_addr_o : out std_logic_vector(MASTER_ADDR_WIDTH-1 downto 0);
master_wr_o : out std_logic;
master_rd_o : out std_logic;
master_datawr_o : out std_logic_vector(31 downto 0);
master_datard_i : in std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of gp_com is
-- flow signals
signal flow_out_data_0_s : std_logic_vector(DATA_HAL_SIZE-1 downto 0) := (others => '0');
signal flow_out_empty_0_s : std_logic := '0';
signal flow_out_rd_0_s : std_logic := '0';
signal flow_out_rdy_0_s : std_logic := '0';
signal flow_out_size_0_packet_s : std_logic_vector(15 downto 0) := (others => '0');
signal flow_out_data_1_s : std_logic_vector(DATA_HAL_SIZE-1 downto 0) := (others => '0');
signal flow_out_empty_1_s : std_logic := '0';
signal flow_out_rd_1_s : std_logic := '0';
signal flow_out_rdy_1_s : std_logic := '0';
signal flow_out_size_1_packet_s : std_logic_vector(15 downto 0) := (others => '0');
signal flow_out_data_2_s : std_logic_vector(DATA_HAL_SIZE-1 downto 0) := (others => '0');
signal flow_out_empty_2_s : std_logic := '0';
signal flow_out_rd_2_s : std_logic := '0';
signal flow_out_rdy_2_s : std_logic := '0';
signal flow_out_size_2_packet_s : std_logic_vector(15 downto 0) := (others => '0');
signal flow_out_data_3_s : std_logic_vector(DATA_HAL_SIZE-1 downto 0) := (others => '0');
signal flow_out_empty_3_s : std_logic := '0';
signal flow_out_rd_3_s : std_logic := '0';
signal flow_out_rdy_3_s : std_logic := '0';
signal flow_out_size_3_packet_s : std_logic_vector(15 downto 0) := (others => '0');
-- FLOW_PARAMS
signal update_port_s : std_logic := '0';
begin
--FLOW_OUT out0
FO0_disabled : if OUT0_NBWORDS = 0 generate
out0_data <= (others => '0');
out0_fv <= '0';
out0_dv <= '0';
end generate FO0_disabled;
FO0_enabled : if OUT0_NBWORDS > 0 generate
FLOW_OUT0: component com_to_flow
generic map (
FIFO_DEPTH => OUT0_NBWORDS,
FLOW_ID => 1,
FLAGS_CODES => InitFlagCodes,
FLOW_SIZE => OUT0_SIZE,
DATA_HAL_SIZE => DATA_HAL_SIZE
)
port map (
clk_hal => clk_hal,
clk_proc => clk_proc,
rst_n => reset_n,
data_wr_i => from_hal_wr,
data_i => from_hal_data,
pktend_i => from_hal_pktend,
enable_i => status_enable,
data_o => out0_data,
fv_o => out0_fv,
dv_o => out0_dv,
flow_full_o => open
);
end generate FO0_enabled;
--FLOW_OUT out1
FO1_disabled : if OUT1_NBWORDS = 0 generate
out1_data <= (others => '0');
out1_fv <= '0';
out1_dv <= '0';
end generate FO1_disabled;
FO1_enabled : if OUT1_NBWORDS > 0 generate
FLOW_OUT1: component com_to_flow
generic map (
FIFO_DEPTH => OUT1_NBWORDS,
FLOW_ID => 2,
FLAGS_CODES => InitFlagCodes,
FLOW_SIZE => OUT1_SIZE,
DATA_HAL_SIZE => DATA_HAL_SIZE
)
port map (
clk_hal => clk_hal,
clk_proc => clk_proc,
rst_n => reset_n,
data_wr_i => from_hal_wr,
data_i => from_hal_data,
pktend_i => from_hal_pktend,
enable_i => status_enable,
data_o => out1_data,
fv_o => out1_fv,
dv_o => out1_dv,
flow_full_o => open
);
end generate FO1_enabled;
------------------------------------------------------------
--FLOW IN in0
--Disable flow if not used
FI0_disabled : if IN0_NBWORDS = 0 generate
flow_out_rdy_0_s <= '0';
flow_out_empty_0_s <= '0';
flow_out_data_0_s <= (others => '0');
end generate FI0_disabled;
FI0_enabled : if IN0_NBWORDS > 0 generate
FLOW_IN0: component flow_to_com
generic map (
FLOW_SIZE => IN0_SIZE,
FIFO_DEPTH => IN0_NBWORDS,
FLOW_ID => 128,
PACKET_SIZE => PACKET_HAL_SIZE, -- header inclus
FLAGS_CODES => InitFlagCodes,
DATA_HAL_SIZE => DATA_HAL_SIZE
)
port map (
clk_proc => clk_proc,
clk_hal => clk_hal,
rst_n => reset_n,
in_data => in0_data,
in_fv => in0_fv,
in_dv => in0_dv,
enable_flow_i => flow_in0_enable,
enable_global_i => status_enable,
-- to arbitrer
rdreq_i => flow_out_rd_0_s,
data_o => flow_out_data_0_s,
flow_rdy_o => flow_out_rdy_0_s,
f_empty_o => flow_out_empty_0_s,
size_packet_o => flow_out_size_0_packet_s
);
end generate FI0_enabled;
------------------------------------------------------------
------------------------------------------------------------
--FLOW IN in1
FI1_disabled : if IN1_NBWORDS = 0 generate
flow_out_rdy_1_s <= '0';
flow_out_empty_1_s <= '0';
flow_out_data_1_s <= (others => '0');
end generate FI1_disabled;
FI1_enabled : if IN1_NBWORDS > 0 generate
FLOW_IN1: component flow_to_com
generic map (
FLOW_SIZE => IN1_SIZE,
FIFO_DEPTH => IN1_NBWORDS,
FLOW_ID => 129,
PACKET_SIZE => PACKET_HAL_SIZE, -- header inclus
FLAGS_CODES => InitFlagCodes,
DATA_HAL_SIZE => DATA_HAL_SIZE
)
port map (
clk_proc => clk_proc,
clk_hal => clk_hal,
rst_n => reset_n,
in_data => in1_data,
in_fv => in1_fv,
in_dv => in1_dv,
enable_flow_i => flow_in1_enable,
enable_global_i => status_enable,
-- to arbitrer
rdreq_i => flow_out_rd_1_s,
data_o => flow_out_data_1_s,
flow_rdy_o => flow_out_rdy_1_s,
f_empty_o => flow_out_empty_1_s,
size_packet_o => flow_out_size_1_packet_s
);
end generate FI1_enabled;
------------------------------------------------------------
------------------------------------------------------------
--FLOW IN in2
FI2_disabled : if IN2_NBWORDS = 0 generate
flow_out_rdy_2_s <= '0';
flow_out_empty_2_s <= '0';
flow_out_data_2_s <= (others => '0');
end generate FI2_disabled;
FI2_enabled : if IN2_NBWORDS > 0 generate
FLOW_IN2: component flow_to_com
generic map (
FLOW_SIZE => IN2_SIZE,
FIFO_DEPTH => IN2_NBWORDS,
FLOW_ID => 130,
PACKET_SIZE => PACKET_HAL_SIZE, -- header inclus
FLAGS_CODES => InitFlagCodes,
DATA_HAL_SIZE => DATA_HAL_SIZE
)
port map (
clk_proc => clk_proc,
clk_hal => clk_hal,
rst_n => reset_n,
in_data => in2_data,
in_fv => in2_fv,
in_dv => in2_dv,
enable_flow_i => flow_in2_enable,
enable_global_i => status_enable,
-- to arbitrer
rdreq_i => flow_out_rd_2_s,
data_o => flow_out_data_2_s,
flow_rdy_o => flow_out_rdy_2_s,
f_empty_o => flow_out_empty_2_s,
size_packet_o => flow_out_size_2_packet_s
);
end generate FI2_enabled;
------------------------------------------------------------
------------------------------------------------------------
--FLOW IN in3
FI3_disabled : if IN3_NBWORDS = 0 generate
flow_out_rdy_3_s <= '0';
flow_out_empty_3_s <= '0';
flow_out_data_3_s <= (others => '0');
end generate FI3_disabled;
FI3_enabled : if IN3_NBWORDS > 0 generate
FLOW_IN3: component flow_to_com
generic map (
FLOW_SIZE => IN3_SIZE,
FIFO_DEPTH => IN3_NBWORDS,
FLOW_ID => 131,
PACKET_SIZE => PACKET_HAL_SIZE, -- header inclus
FLAGS_CODES => InitFlagCodes,
DATA_HAL_SIZE => DATA_HAL_SIZE
)
port map (
clk_proc => clk_proc,
clk_hal => clk_hal,
rst_n => reset_n,
in_data => in3_data,
in_fv => in3_fv,
in_dv => in3_dv,
enable_flow_i => flow_in3_enable,
enable_global_i => status_enable,
-- to arbitrer
rdreq_i => flow_out_rd_3_s,
data_o => flow_out_data_3_s,
flow_rdy_o => flow_out_rdy_3_s,
f_empty_o => flow_out_empty_3_s,
size_packet_o => flow_out_size_3_packet_s
);
end generate FI3_enabled;
------------------------------------------------------------
-- component flow_to_com_arb4
FLOW_ARB : component flow_to_com_arb4
generic map (
DATA_HAL_SIZE => DATA_HAL_SIZE
)
port map (
clk => clk_hal,
rst_n => reset_n,
-- fv 0 signals
rdreq_0_o => flow_out_rd_0_s,
data_0_i => flow_out_data_0_s,
flow_rdy_0_i => flow_out_rdy_0_s,
f_empty_0_i => flow_out_empty_0_s,
size_packet_0_i => flow_out_size_0_packet_s,
-- fv 1 signals
rdreq_1_o => flow_out_rd_1_s,
data_1_i => flow_out_data_1_s,
flow_rdy_1_i => flow_out_rdy_1_s,
f_empty_1_i => flow_out_empty_1_s,
size_packet_1_i => flow_out_size_1_packet_s,
-- fv 2 signals
rdreq_2_o => flow_out_rd_2_s,
data_2_i => flow_out_data_2_s,
flow_rdy_2_i => flow_out_rdy_2_s,
f_empty_2_i => flow_out_empty_2_s,
size_packet_2_i => flow_out_size_2_packet_s,
-- fv 3 signals
rdreq_3_o => flow_out_rd_3_s,
data_3_i => flow_out_data_3_s,
flow_rdy_3_i => flow_out_rdy_3_s,
f_empty_3_i => flow_out_empty_3_s,
size_packet_3_i => flow_out_size_3_packet_s,
-- fv usb signals
rdreq_usb_i => to_hal_rd,
data_usb_o => to_hal_data,
flow_rdy_usb_o => to_hal_rdy,
f_empty_usb_o => to_hal_empty,
size_packet_o => to_hal_size_packet
);
-- FLOW_PARAMS module --> Parameter Interconnect Master
FLOW_PARAMS : component com_to_master_pi
generic map (
FIFO_DEPTH => 64,
FLOW_ID_SET => 15,
MASTER_ADDR_WIDTH => MASTER_ADDR_WIDTH,
DATA_HAL_SIZE => DATA_HAL_SIZE
)
port map (
clk_hal => clk_hal,
clk_proc => clk_proc,
rst_n => reset_n,
data_wr_i => from_hal_wr,
data_i => from_hal_data,
pktend_i => from_hal_pktend,
fifo_full_o => from_hal_full,
param_addr_o => master_addr_o,
param_data_o => master_datawr_o,
param_wr_o => master_wr_o
-- rajouter fin d'ecriture dans la memoire...
--~ tmp_update_port_o => update_port_s
);
end rtl;
| gpl-3.0 | 3f0d4345bcd26720ea1977c201b0b4b5 | 0.493865 | 3.0013 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/RGMII_MAC/rgmii1000_pll.vhd | 1 | 16,291 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: rgmii1000_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY rgmii1000_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC
);
END rgmii1000_pll;
ARCHITECTURE SYN OF rgmii1000_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 8000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=rgmii1000_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire4,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "250.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "125.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "250.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "rgmii1000_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii1000_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii1000_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii1000_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii1000_pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii1000_pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii1000_pll_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-3.0 | e8a7c0a516e91d11091dc1f72777500f | 0.701307 | 3.332856 | false | false | false | false |
DreamIP/GPStudio | support/io/mpu/hdl/mpu_fifo.vhd | 1 | 8,163 | -- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo
-- ============================================================
-- File Name: mpu_fifo.vhd
-- Megafunction Name(s):
-- dcfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY mpu_fifo IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
wrfull : OUT STD_LOGIC
);
END mpu_fifo;
ARCHITECTURE SYN OF mpu_fifo IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT dcfifo
GENERIC (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
rdclk : IN STD_LOGIC ;
wrfull : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
wrfull <= sub_wire0;
q <= sub_wire1(7 DOWNTO 0);
rdempty <= sub_wire2;
rdusedw <= sub_wire3(5 DOWNTO 0);
dcfifo_component : dcfifo
GENERIC MAP (
intended_device_family => "Cyclone III",
lpm_numwords => 64,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => 8,
lpm_widthu => 6,
overflow_checking => "ON",
rdsync_delaypipe => 4,
read_aclr_synch => "ON",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "ON",
wrsync_delaypipe => 4
)
PORT MAP (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data,
rdreq => rdreq,
wrfull => sub_wire0,
q => sub_wire1,
rdempty => sub_wire2,
rdusedw => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "64"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "8"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "8"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
-- Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: rdusedw 0 0 6 0 OUTPUT NODEFVAL "rdusedw[5..0]"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-- Retrieval info: CONNECT: rdusedw 0 0 6 0 @rdusedw 0 0 6 0
-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo_imu.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo_imu.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo_imu.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo_imu.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo_imu_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo_imu_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo_imu_wave*.jpg FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mpu_fifo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mpu_fifo.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mpu_fifo.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mpu_fifo.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mpu_fifo_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | 2487acb25f62d1c4b20b63bd51caec60 | 0.670097 | 3.482509 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/atomicmodify/src/atomicmodifyRtl.vhd | 3 | 6,975 | -------------------------------------------------------------------------------
--! @file atomicmodifyRtl.vhd
--
--! @brief Atomic modify
--
--! @details This component is used to modify memory atomically.
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2015
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity atomicmodify is
generic (
--! Address bus width
gAddrWidth : natural := 16
);
port (
--! Clock
iClk : in std_logic;
--! Reset
iRst : in std_logic;
-- Memory Mapped master
--! MM master address
oMst_address : out std_logic_vector(gAddrWidth-1 downto 0);
--! MM master byteenable
oMst_byteenable : out std_logic_vector(3 downto 0);
--! MM master read
oMst_read : out std_logic;
--! MM master readdata
iMst_readdata : in std_logic_vector(31 downto 0);
--! MM master write
oMst_write : out std_logic;
--! MM master writedata
oMst_writedata : out std_logic_vector(31 downto 0);
--! MM master waitrequest
iMst_waitrequest : in std_logic;
--! MM master lock
oMst_lock : out std_logic;
-- Memory mapped slave
--! Address
iSlv_address : in std_logic_vector(gAddrWidth-1 downto 2);
--! Byteenable
iSlv_byteenable : in std_logic_vector(3 downto 0);
--! Read strobe
iSlv_read : in std_logic;
--! Readdata
oSlv_readdata : out std_logic_vector(31 downto 0);
--! Write strobe
iSlv_write : in std_logic;
--! Writedata
iSlv_writedata : in std_logic_vector(31 downto 0);
--! Waitrequest
oSlv_waitrequest : out std_logic
);
end atomicmodify;
architecture rtl of atomicmodify is
-- fsm
type tFsm is (
sIdle,
sRead,
sWrite
);
-- register set
type tReg is record
address : std_logic_vector(oMst_address'range);
byteenable : std_logic_vector(oMst_byteenable'range);
writedata : std_logic_vector(oMst_writedata'range);
readdata : std_logic_vector(iMst_readdata'range);
fsm : tFsm;
ack : std_logic;
end record;
constant cRegInit : tReg := (
address => (others => cInactivated),
byteenable => (others => cInactivated),
writedata => (others => cInactivated),
readdata => (others => cInactivated),
fsm => sIdle,
ack => cInactivated
);
-- register set signals
signal reg : tReg;
signal reg_next : tReg;
begin
--! The process describes the register set.
regClk : process(iClk)
begin
if rising_edge(iClk) then
if iRst = cActivated then
reg <= cRegInit;
else
reg <= reg_next;
end if;
end if;
end process;
--! The process describes the combinational circuit for the register set.
regComb : process (
reg,
iSlv_address, iSlv_byteenable, iSlv_read, iSlv_write, iSlv_writedata,
iMst_waitrequest, iMst_readdata
)
begin
-- default
reg_next <= reg;
reg_next.ack <= cInactivated;
-- Master access state machine
case reg.fsm is
when sIdle =>
if iSlv_write = cActivated and reg.ack = cInactivated then
reg_next.fsm <= sRead;
reg_next.address <= iSlv_address & "00";
reg_next.byteenable <= iSlv_byteenable;
reg_next.writedata <= iSlv_writedata;
elsif iSlv_read = cActivated and reg.ack = cInactivated then
reg_next.fsm <= sIdle;
reg_next.ack <= cActivated;
end if;
when sRead =>
if iMst_waitrequest = cInactivated then
reg_next.fsm <= sWrite;
reg_next.readdata <= iMst_readdata;
end if;
when sWrite =>
if iMst_waitrequest = cInactivated then
reg_next.fsm <= sIdle;
reg_next.ack <= cActivated;
end if;
end case;
end process;
-- Assign ports to register set
oSlv_waitrequest <= not reg.ack;
oSlv_readdata <= reg.readdata;
oMst_address <= reg.address;
oMst_byteenable <= reg.byteenable;
oMst_writedata <= reg.writedata;
oMst_read <= cActivated when reg.fsm = sRead else cInactivated;
oMst_write <= cActivated when reg.fsm = sWrite else cInactivated;
oMst_lock <= cActivated when reg.fsm = sRead else cInactivated;
end rtl;
| gpl-2.0 | 31dd46d9d7dbbc2518e62bae7618128e | 0.551685 | 4.681208 | false | false | false | false |
DreamIP/GPStudio | support/process/fastfilter/hdl/components/taps2.vhd | 1 | 1,121 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fastfilter_types.all;
entity taps2 is
generic (
PIXEL_SIZE : integer;
TAPS_WIDTH : integer;
KERNEL_SIZE : integer
);
port (
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE-1 downto 0);
taps_data : out pixel_array (0 to KERNEL_SIZE -1 );
out_data : out std_logic_vector (PIXEL_SIZE-1 downto 0)
);
end taps2;
architecture bhv of taps2 is
signal cell : pixel_array (0 to TAPS_WIDTH-1);
begin
process(clk)
variable i : integer := 0;
begin
if ( reset_n = '0' ) then
cell <= (others =>(others => '0'));
out_data <= (others => '0');
taps_data <= (others =>(others => '0'));
elsif (rising_edge(clk)) then
if (enable='1') then
cell(0) <= in_data;
for i in 1 to (TAPS_WIDTH-1) loop
cell(i) <= cell(i-1);
end loop;
taps_data <= cell(0 to KERNEL_SIZE-1);
out_data <= cell(TAPS_WIDTH-1);
end if;
end if;
end process;
end bhv;
| gpl-3.0 | 8ba8c724135ea8140a207222e8f5aeeb | 0.578947 | 2.54195 | false | false | false | false |
DreamIP/GPStudio | support/io/usb3_ft600x/hdl/usb3_ft600x.vhd | 1 | 2,942 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity usb3_ft600x is
generic (
CLK_PROC_FREQ : integer;
OUT0_SIZE : integer;
OUT1_SIZE : integer;
IN0_SIZE : integer;
IN1_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
--------------------- external ports --------------------
ftreset_n : out std_logic;
ftclk : in std_logic;
be : inout std_logic_vector(1 downto 0);
data : inout std_logic_vector(15 downto 0);
txe_n : in std_logic;
rxf_n : in std_logic;
siwu_n : out std_logic;
wr_n : out std_logic;
rd_n : out std_logic;
oe_n : out std_logic;
------------------------ out0 flow ----------------------
out0_data : out std_logic_vector(OUT0_SIZE-1 downto 0);
out0_fv : out std_logic;
out0_dv : out std_logic;
------------------------ out1 flow ----------------------
out1_data : out std_logic_vector(OUT1_SIZE-1 downto 0);
out1_fv : out std_logic;
out1_dv : out std_logic;
------------------------ in0 flow -----------------------
in0_data : in std_logic_vector(IN0_SIZE-1 downto 0);
in0_fv : in std_logic;
in0_dv : in std_logic;
------------------------ in1 flow -----------------------
in1_data : in std_logic_vector(IN1_SIZE-1 downto 0);
in1_fv : in std_logic;
in1_dv : in std_logic
);
end usb3_ft600x;
architecture rtl of usb3_ft600x is
type read_sm is (w_wait, w_start_read, w_start_read2, w_start_read3, w_read);
signal read_sm_state : read_sm := w_wait;
begin
ftreset_n <= reset_n;
process (ftclk, reset_n)
begin
if(reset_n = '0') then
wr_n <= '1';
rd_n <= '1';
oe_n <= '1';
data <= "ZZZZZZZZZZZZZZZZ";
be <= "ZZ";
read_sm_state <= w_wait;
elsif(rising_edge(ftclk)) then
case read_sm_state is
when w_wait =>
wr_n <= '1';
rd_n <= '1';
oe_n <= '1';
if(rxf_n = '0') then
read_sm_state <= w_start_read;
end if;
when w_start_read =>
read_sm_state <= w_start_read2;
data <= "ZZZZZZZZZZZZZZZZ";
be <= "ZZ";
when w_start_read2 =>
read_sm_state <= w_start_read3;
oe_n <= '0';
when w_start_read3 =>
read_sm_state <= w_read;
rd_n <= '0';
when w_read =>
out0_data <= data(7 downto 0);
if(rxf_n = '1') then
read_sm_state <= w_wait;
end if;
when others =>
end case;
end if;
end process;
end rtl;
| gpl-3.0 | b011ed630e8dccb15a9f0c742bfe655c | 0.433719 | 3.298206 | false | false | false | false |
DreamIP/GPStudio | support/io/com/hdl/hal/eth_marvell_88e1111/hdl/interface_management/rgmii2gmii_fifo.vhd | 1 | 3,157 | -- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo_mixed_widths
-- ============================================================
-- File Name: rgmi2gmii_fifo.vhd
-- Megafunction Name(s):
-- dcfifo_mixed_widths
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY rgmii2gmii_fifo IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC
);
END rgmii2gmii_fifo;
ARCHITECTURE SYN OF rgmii2gmii_fifo IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
COMPONENT dcfifo_mixed_widths
GENERIC (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
lpm_widthu_r : NATURAL;
lpm_width_r : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
underflow_checking : STRING;
use_eab : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
rdempty <= sub_wire1;
dcfifo_mixed_widths_component : dcfifo_mixed_widths
GENERIC MAP (
intended_device_family => "Cyclone III",
lpm_numwords => 32,
lpm_showahead => "OFF",
lpm_type => "dcfifo_mixed_widths",
lpm_width => 4,
lpm_widthu => 5,
lpm_widthu_r => 4,
lpm_width_r => 8,
overflow_checking => "ON",
rdsync_delaypipe => 4,
underflow_checking => "ON",
use_eab => "ON",
wrsync_delaypipe => 4
)
PORT MAP (
data => data,
rdclk => rdclk,
rdreq => rdreq,
wrclk => wrclk,
wrreq => wrreq,
q => sub_wire0,
rdempty => sub_wire1
);
END SYN;
| gpl-3.0 | b4bd012b7e041e6dfe4ba1f5571cac22 | 0.627494 | 3.333685 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/nShiftRegRtl.vhd | 3 | 5,408 | -------------------------------------------------------------------------------
--! @file nShiftRegRtl.vhd
--
--! @brief Shift register with n-bit-width
--
--! @details This shift register implementation provides a configurable width.
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity nShiftReg is
generic (
--! Data width
gWidth : natural := 8;
--! Number of tabs
gTabs : natural := 4;
--! Shift direction ("left" or "right")
gShiftDir : string := "left"
);
port (
--! Asynchronous reset
iArst : in std_logic;
--! Clock
iClk : in std_logic;
--! Parallel Load
iLoad : in std_logic;
--! Shift Enable
iShift : in std_logic;
--! Load Data (gTabs x gWidth)
iLoadData : in std_logic_vector(gWidth*gTabs-1 downto 0);
--! Parallel Output Data
oParData : out std_logic_vector(gWidth*gTabs-1 downto 0);
--! Input Shift Data
iData : in std_logic_vector(gWidth-1 downto 0);
--! Ouptut Shift Data
oData : out std_logic_vector(gWidth-1 downto 0)
);
end nShiftReg;
architecture rtl of nShiftReg is
--! Shift register type
type tShiftReg is
array (gTabs-1 downto 0) of std_logic_vector(gWidth-1 downto 0);
--! Function to convert std_logic_vector into tShiftReg
function convStdLogicToShiftReg (din : std_logic_vector)
return tShiftReg is
variable vTmp : tShiftReg;
begin
--default
vTmp := (others => (others => cInactivated));
--loop tab-wise
for i in gTabs-1 downto 0 loop
vTmp(i) := din((i+1)*gWidth-1 downto i*gWidth);
end loop;
return vTmp;
end function;
--! Function to convert tShiftReg into std_logic_vector
function convShiftRegToStdLogic (din : tShiftReg)
return std_logic_vector is
variable vTmp : std_logic_vector(gWidth*gTabs-1 downto 0);
begin
--default
vTmp := (others => cInactivated);
--loop tab-wise
for i in gTabs-1 downto 0 loop
vTmp((i+1)*gWidth-1 downto i*gWidth) := din(i);
end loop;
return vTmp;
end function;
--! Shift register
signal reg, reg_next : tShiftReg;
begin
assert (gShiftDir = "left" or gShiftDir = "right") report
"Set either left or right for shift direction!" severity failure;
--serial output
oData <= reg(reg'right) when gShiftDir = "right" else
reg(reg'left);
--parallel output
oParData <= convShiftRegToStdLogic(reg);
--! Process doing loading and shifting
comb : process (
reg,
iLoad, iShift,
iLoadData, iData
)
begin
--default
reg_next <= reg;
if iLoad = cActivated then
reg_next <= convStdLogicToShiftReg(iLoadData);
elsif iShift = cActivated then
if gShiftDir = "right" then
reg_next <= iData & reg(reg'left downto 1);
else
reg_next <= reg(reg'left-1 downto 0) & iData;
end if;
end if;
end process;
--! Register process
regClk : process(iArst, iClk)
begin
if iArst = cActivated then
reg <= (others => (others => cInactivated));
elsif rising_edge(iClk) then
reg <= reg_next;
end if;
end process;
end rtl;
| gpl-2.0 | 41d8cbc94804fd46bd501d213b548fba | 0.601701 | 4.407498 | false | false | false | false |
DreamIP/GPStudio | support/io/mpu/hdl/mpu_offset_correction.vhd | 1 | 3,823 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.mpu_pkg.all;
entity offset_correction is
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
rd_fifo_count : in std_logic;
parameters : in param;
wr_en_flag : in std_logic;
wr_fifo : out std_logic;
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0)
);
end offset_correction;
architecture RTL of offset_correction is
signal count : unsigned(1 downto 0);
signal raw_data : std_logic_vector(15 downto 0);
signal data_cor : std_logic_vector(15 downto 0);
signal count_value : unsigned(3 downto 0);
signal offset, offset_default : std_logic_vector(15 downto 0);
signal sign : std_logic;
type state_off is (idle,correction);
signal state : state_off;
begin
--------This process correct data values by subtracting the corresponding offset to the raw value.
process(clk,reset)
begin
if reset='0' then
count <= "00";
wr_fifo <= '0';
count_value <= x"0";
elsif clk'event and clk='1' then
if enable ='1' then
case(state) is
when idle =>
if wr_en_flag='1' then
count <= count +1;
raw_data <= raw_data(7 downto 0) & data_i;
elsif count="10" then
count <= "00";
state <= correction;
if rd_fifo_count='0' then
if count_value=x"9" then
count_value <= x"0";
else
count_value <= count_value+1;
end if;
if count_value<x"7" then
data_cor <= raw_data-offset;
else
data_cor <= raw_data;
end if;
else
data_cor <= raw_data;
end if;
end if;
when correction =>
if count="10" then
count <= "00";
state <= idle;
wr_fifo <= '0';
else
count <= count+1;
wr_fifo <= '1';
data_o <= data_cor(15 downto 8);
data_cor <= data_cor(7 downto 0) & data_cor(15 downto 8);
end if;
end case;
else
count <= "00";
wr_fifo <= '0';
count_value <= x"0";
state <= idle;
end if;
end if;
end process;
--------This process determine each offset to subtract depending on the actual configuration and its value (whether it is negative or positive)
process(clk,reset)
begin
if reset='0' then
offset <= x"0000";
elsif clk'event and clk='1' then
if enable = '1' then
if count_value<3 then
if parameters(0)(20 downto 19)="01" then
offset <= sign & offset_default(15 downto 1);
elsif parameters(0)(20 downto 19)="10" then
offset <= sign&sign& offset_default(15 downto 2);
elsif parameters(0)(20 downto 19)="11" then
offset <= sign&sign&sign& offset_default(15 downto 3);
else
offset <= offset_default;
end if;
else
if parameters(0)(22 downto 21)="01" then
offset <= sign & offset_default(15 downto 1);
elsif parameters(0)(22 downto 21)="10" then
offset <= sign&sign& offset_default(15 downto 2);
elsif parameters(0)(22 downto 21)="11" then
offset <= sign&sign&sign& offset_default(15 downto 3);
else
offset <= offset_default;
end if;
end if;
end if;
end if;
end process;
sign <= offset_default(15);
offset_default <= parameters(1)(15 downto 0) when count_value = x"0" else --offset accel X
parameters(2)(15 downto 0) when count_value = x"1" else --offset accel Y
parameters(3)(15 downto 0) when count_value = x"2" else --offset accel Z
parameters(1)(31 downto 16) when count_value = x"4" else --offset gyro X
parameters(2)(31 downto 16) when count_value = x"5" else --offset gyro Y
parameters(3)(31 downto 16) when count_value = x"6" else --offset gyro Z
x"0000";
end RTL;
| gpl-3.0 | f78b275016acfc93a27bd596661bb48b | 0.602668 | 3.055955 | false | false | false | false |
DreamIP/GPStudio | support/io/com/hdl/hal/eth_marvell_88e1111/hdl/encapsulation/eth_tx_encap.vhd | 1 | 1,401 | -- This file regroup the entities that add padding and CRC to the packets.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity eth_tx_encap is
port(
GE_TXEN : out STD_LOGIC;
GE_TXD : out STD_LOGIC_VECTOR(7 downto 0);
CLK125 : in STD_LOGIC;
reset_n : in STD_LOGIC;
ETH_TX_STREAM : in STD_LOGIC_VECTOR(8 downto 0)
);
end eth_tx_encap;
architecture Behavioral of eth_tx_encap is
signal send_cke : STD_LOGIC;
signal mid_tx_stream : STD_LOGIC_VECTOR(9 downto 0);
signal mid_tx_stream2 : STD_LOGIC_VECTOR(9 downto 0);
begin
trans : entity work.eth_tx_stream port map(
CLK125 => CLK125,
RESET => reset_n,
TXD => GE_TXD,
TXCTRL => GE_TXEN,
ETH_TX_STREAM => mid_tx_stream2
);
transmit_crc : entity work.eth_tx_crc port map(
CLK => CLK125,
RESET => reset_n,
IN_ETH_STREAM => mid_tx_stream,
OUT_ETH_STREAM => mid_tx_stream2
);
pad_packet : entity work.eth_tx_pad port map(
CLK => CLK125,
RESET => reset_n,
IN_ETH_STREAM(9) => send_cke,
IN_ETH_STREAM(8 downto 0) => ETH_TX_STREAM,
OUT_ETH_STREAM => mid_tx_stream
);
send_cke <= '1';
end Behavioral;
| gpl-3.0 | 945969d5e76cb51f81d3f7572b07d115 | 0.534618 | 3.134228 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/eth_marvell_88e1111_hal.vhd | 1 | 9,832 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
use work.ComFlow_pkg.all;
entity eth_marvell_88e1111_hal is
port (
clk_proc : in std_logic;
clk_hal : out std_logic;
reset_n : in std_logic;
---------------------- external ports --------------------
gtx_clk : out std_logic;
tx_en : out std_logic;
tx_data : out std_logic_vector(3 downto 0);
rx_clk : in std_logic;
rx_dv : in std_logic;
rx_data : in std_logic_vector(3 downto 0);
phy_reset_l : out std_logic;
phy_mdc : out std_logic;
phy_mdio : inout std_logic;
---------------------- hal com --------------------------
out_data_o : out std_logic_vector(7 downto 0);
out_data_wr_o : out std_logic;
out_data_full_i : in std_logic;
out_data_end_o : out std_logic;
in_data_i : in std_logic_vector(7 downto 0);
in_data_rd_o : out std_logic;
in_data_empty_i : in std_logic;
in_data_rdy_i : in std_logic;
in_data_size_packet : in std_logic_vector(15 downto 0)
);
end eth_marvell_88e1111_hal;
architecture rtl of eth_marvell_88e1111_hal is
component UDP_MAC_GE
port (
---------------------------------------------------------------------------
-- RGMII Interface
---------------------------------------------------------------------------
gtx_clk : out std_logic;
tx_en : out std_logic;
tx_data : out std_logic_vector(3 downto 0);
rx_clk : in std_logic;
rx_dv : in std_logic;
rx_data : in std_logic_vector(3 downto 0);
--phy
phy_reset_l : out std_logic;
phy_mdc : out std_logic;
phy_mdio : inout std_logic;
---------------------------------------------------------------------------
-- user Interface
---------------------------------------------------------------------------
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
udp_tx_data_out_ready : out std_logic; -- indicates udp_tx is ready to take data
-- UDP RX signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
CLK_OUT : OUT STD_LOGIC
);
end component;
-- udp
signal udp_tx_start : std_logic;
signal udp_txi : udp_tx_type;
signal udp_tx_result : std_logic_vector (1 downto 0);
signal udp_tx_data_out_ready : std_logic;
signal udp_rx_start : std_logic;
signal udp_rxo : udp_rx_type;
signal udp_header_valid_prev : std_logic;
signal out_data_end_s : std_logic;
signal CLK_OUT : std_logic;
constant IP_DEST : std_logic_vector(31 downto 0) := x"AC1B014A";
constant PORT_DEST : std_logic_vector(15 downto 0) := x"079B";
constant PORT_SRC : std_logic_vector(15 downto 0) := x"079B";
-- fsm read
type fsm_read_state_t is (Read_Idle, Read_Receive);
signal fsm_read_state : fsm_read_state_t := Read_Idle;
-- fsm write
type fsm_write_state_t is (Write_Idle, Wait_udp_tx_ready, wait_one_cycle_to_read_ff, transmit_tx);
signal fsm_write_state : fsm_write_state_t := Write_Idle;
begin
udp_mac_ge_inst : UDP_MAC_GE
port map (
---------------------------------------------------------------------------
-- RGMII Interface
---------------------------------------------------------------------------
gtx_clk => gtx_clk,
tx_en => tx_en,
tx_data => tx_data,
rx_clk => rx_clk,
rx_dv => rx_dv,
rx_data => rx_data,
--phy
phy_reset_l => phy_reset_l,
phy_mdc => phy_mdc,
phy_mdio => phy_mdio,
---------------------------------------------------------------------------
-- user Interface
---------------------------------------------------------------------------
udp_tx_start => udp_tx_start,
udp_txi => udp_txi,
udp_tx_result => open,
udp_tx_data_out_ready => udp_tx_data_out_ready,
-- UDP RX signals
udp_rx_start => udp_rx_start,
udp_rxo => udp_rxo,
CLK_OUT => CLK_OUT
);
clk_hal <= CLK_OUT;
--------------------------------------------
-----------------READ SIDE------------------
read_proc : process (CLK_OUT, reset_n)
begin
if(reset_n='0') then
fsm_read_state <= Read_Idle;
udp_header_valid_prev <= '0';
elsif(rising_edge(CLK_OUT)) then
udp_header_valid_prev <= udp_rxo.hdr.is_valid;
out_data_end_o <= out_data_end_s;
case fsm_read_state is
when Read_Idle =>
if(udp_header_valid_prev = '0'
and udp_rxo.hdr.is_valid = '1'
and udp_rxo.hdr.src_ip_addr = IP_DEST
and udp_rxo.hdr.src_port = PORT_DEST) then
fsm_read_state <= Read_Receive;
end if;
out_data_wr_o <= '0';
out_data_end_s <= '0';
when Read_Receive =>
if(udp_rxo.data.data_in_valid = '1') then
out_data_o <= udp_rxo.data.data_in;
out_data_wr_o <= '1';
if(udp_rxo.data.data_in_last = '1') then
out_data_end_s <= '1';
fsm_read_state <= Read_Idle;
else
out_data_end_s <= '0';
fsm_read_state <= Read_Receive;
end if;
end if;
when others =>
end case;
end if;
end process;
--------------------------------------------
-----------------WRITE SIDE------------------
udp_txi.hdr.dst_ip_addr <= IP_DEST;
udp_txi.hdr.dst_port <= PORT_DEST;
udp_txi.hdr.src_port <= PORT_SRC;
--udp_txi.hdr.data_length <= in_data_size_packet;
udp_txi.hdr.checksum <= (others => '0');
write_proc : process(CLK_OUT, reset_n)
begin
if(reset_n='0') then
in_data_rd_o <= '0';
udp_tx_start <= '0';
udp_txi.hdr.data_length <= (others => '0');
udp_txi.data.data_out_valid <= '0';
udp_txi.data.data_out_last <= '0';
udp_txi.data.data_out <= (others => '0');
fsm_write_state <= Write_Idle;
elsif rising_edge(CLK_OUT) then
case fsm_write_state is
------
when Write_Idle =>
if in_data_rdy_i = '1' and in_data_empty_i = '0' then
in_data_rd_o <= '0';
udp_tx_start <= '1';--
udp_txi.hdr.data_length <= in_data_size_packet;
fsm_write_state <= Wait_udp_tx_ready;
else
in_data_rd_o <= '0';
udp_tx_start <= '0';
udp_txi.hdr.data_length <= (others => '0');
fsm_write_state <= Write_Idle;
end if;
udp_txi.data.data_out_valid <= '0';
udp_txi.data.data_out_last <= '0';
udp_txi.data.data_out <= (others => '0');
------
when Wait_udp_tx_ready =>
if udp_tx_data_out_ready = '1' then
in_data_rd_o <= '1';--
udp_tx_start <= '0';--
fsm_write_state <= wait_one_cycle_to_read_ff;
else
in_data_rd_o <= '0';
udp_tx_start <= '1';--
fsm_write_state <= Wait_udp_tx_ready;
end if;
udp_txi.hdr.data_length <= udp_txi.hdr.data_length;
udp_txi.data.data_out_valid <= '0';
udp_txi.data.data_out_last <= '0';
udp_txi.data.data_out <= (others => '0');
------
when wait_one_cycle_to_read_ff =>
in_data_rd_o <= '1';
udp_tx_start <= '0';
udp_txi.hdr.data_length <= udp_txi.hdr.data_length;
udp_txi.data.data_out_valid <= '0';
udp_txi.data.data_out_last <= '0';
udp_txi.data.data_out <= (others => '0');
fsm_write_state <= transmit_tx;
------
when transmit_tx =>
if in_data_rdy_i = '0' then --stop reading ff
in_data_rd_o <= '0';--stop
udp_txi.data.data_out_last <= '1';
fsm_write_state <= Write_Idle;
else
in_data_rd_o <= '1';--hold on
udp_txi.data.data_out_last <= '0';
fsm_write_state <= transmit_tx;
end if;
udp_tx_start <= '0';
udp_txi.hdr.data_length <= udp_txi.hdr.data_length;
udp_txi.data.data_out_valid <= '1';
udp_txi.data.data_out <= in_data_i;
when others =>
in_data_rd_o <= '0';
udp_tx_start <= '0';
udp_txi.hdr.data_length <= (others => '0');
udp_txi.data.data_out_valid <= '0';
udp_txi.data.data_out_last <= '0';
udp_txi.data.data_out <= (others => '0');
fsm_write_state <= Write_Idle;
end case;
end if;
end process;
end rtl;
| gpl-3.0 | 3d2b6df790e6b0990f79a49c24b42d27 | 0.429923 | 3.424591 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_VGA_Controller.vhd | 1 | 12,633 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module controls VGA output for Altera's DE1 and DE2 Boards. *
-- * *
-- ******************************************************************************
ENTITY Video_System_VGA_Controller IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
GENERIC (
CW :INTEGER := 9;
DW :INTEGER := 29;
R_UI :INTEGER := 29;
R_LI :INTEGER := 20;
G_UI :INTEGER := 19;
G_LI :INTEGER := 10;
B_UI :INTEGER := 9;
B_LI :INTEGER := 0;
-- Number of pixels
H_ACTIVE :INTEGER := 640;
H_FRONT_PORCH :INTEGER := 16;
H_SYNC :INTEGER := 96;
H_BACK_PORCH :INTEGER := 48;
H_TOTAL :INTEGER := 800;
-- Number of lines
V_ACTIVE :INTEGER := 480;
V_FRONT_PORCH :INTEGER := 10;
V_SYNC :INTEGER := 2;
V_BACK_PORCH :INTEGER := 33;
V_TOTAL :INTEGER := 525;
LW :INTEGER := 10;
LINE_COUNTER_INCREMENT :STD_LOGIC_VECTOR( 9 DOWNTO 0) := B"0000000001";
PW :INTEGER := 10;
PIXEL_COUNTER_INCREMENT :STD_LOGIC_VECTOR( 9 DOWNTO 0) := B"0000000001"
);
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
data :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
startofpacket :IN STD_LOGIC;
endofpacket :IN STD_LOGIC;
empty :IN STD_LOGIC_VECTOR( 1 DOWNTO 0);
valid :IN STD_LOGIC;
-- Bidirectionals
-- Outputs
ready :BUFFER STD_LOGIC;
VGA_CLK :BUFFER STD_LOGIC;
VGA_BLANK :BUFFER STD_LOGIC;
VGA_SYNC :BUFFER STD_LOGIC;
VGA_HS :BUFFER STD_LOGIC;
VGA_VS :BUFFER STD_LOGIC;
VGA_R :BUFFER STD_LOGIC_VECTOR(CW DOWNTO 0);
VGA_G :BUFFER STD_LOGIC_VECTOR(CW DOWNTO 0);
VGA_B :BUFFER STD_LOGIC_VECTOR(CW DOWNTO 0)
);
END Video_System_VGA_Controller;
ARCHITECTURE Behaviour OF Video_System_VGA_Controller IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
-- States
TYPE State_Type IS ( STATE_0_SYNC_FRAME,
STATE_1_DISPLAY
);
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
SIGNAL read_enable :STD_LOGIC;
SIGNAL end_of_active_frame :STD_LOGIC;
SIGNAL vga_blank_sync :STD_LOGIC;
SIGNAL vga_c_sync :STD_LOGIC;
SIGNAL vga_h_sync :STD_LOGIC;
SIGNAL vga_v_sync :STD_LOGIC;
SIGNAL vga_data_enable :STD_LOGIC;
SIGNAL vga_red :STD_LOGIC_VECTOR(CW DOWNTO 0);
SIGNAL vga_green :STD_LOGIC_VECTOR(CW DOWNTO 0);
SIGNAL vga_blue :STD_LOGIC_VECTOR(CW DOWNTO 0);
SIGNAL vga_color_data :STD_LOGIC_VECTOR(CW DOWNTO 0);
-- Internal Registers
SIGNAL color_select :STD_LOGIC_VECTOR( 3 DOWNTO 0); -- Use for the TRDB_LCM
-- State Machine Registers
SIGNAL ns_mode :State_Type;
SIGNAL s_mode :State_Type;
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
COMPONENT altera_up_avalon_video_vga_timing
GENERIC (
CW :INTEGER;
H_ACTIVE :INTEGER;
H_FRONT_PORCH :INTEGER;
H_SYNC :INTEGER;
H_BACK_PORCH :INTEGER;
H_TOTAL :INTEGER;
V_ACTIVE :INTEGER;
V_FRONT_PORCH :INTEGER;
V_SYNC :INTEGER;
V_BACK_PORCH :INTEGER;
V_TOTAL :INTEGER;
LW :INTEGER;
LINE_COUNTER_INCREMENT :STD_LOGIC_VECTOR( 9 DOWNTO 0);
PW :INTEGER;
PIXEL_COUNTER_INCREMENT :STD_LOGIC_VECTOR( 9 DOWNTO 0)
);
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
red_to_vga_display :IN STD_LOGIC_VECTOR((R_UI - R_LI) DOWNTO 0);
green_to_vga_display :IN STD_LOGIC_VECTOR((G_UI - G_LI) DOWNTO 0);
blue_to_vga_display :IN STD_LOGIC_VECTOR((B_UI - B_LI) DOWNTO 0);
color_select :IN STD_LOGIC_VECTOR( 3 DOWNTO 0);
-- Bidirectionals
-- Outputs
read_enable :BUFFER STD_LOGIC;
end_of_active_frame :BUFFER STD_LOGIC;
-- dac pins
vga_blank :BUFFER STD_LOGIC;
vga_c_sync :BUFFER STD_LOGIC;
vga_h_sync :BUFFER STD_LOGIC;
vga_v_sync :BUFFER STD_LOGIC;
vga_data_enable :BUFFER STD_LOGIC;
vga_red :BUFFER STD_LOGIC_VECTOR(CW DOWNTO 0);
vga_green :BUFFER STD_LOGIC_VECTOR(CW DOWNTO 0);
vga_blue :BUFFER STD_LOGIC_VECTOR(CW DOWNTO 0);
vga_color_data :BUFFER STD_LOGIC_VECTOR(CW DOWNTO 0)
);
END COMPONENT;
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
PROCESS (clk) -- sync reset
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
s_mode <= STATE_0_SYNC_FRAME;
ELSE
s_mode <= ns_mode;
END IF;
END IF;
END PROCESS;
PROCESS (ns_mode, s_mode, valid, startofpacket, end_of_active_frame)
BEGIN
-- Defaults
ns_mode <= STATE_0_SYNC_FRAME;
CASE (s_mode) IS
WHEN STATE_0_SYNC_FRAME =>
IF ((valid = '1') AND (startofpacket = '1')) THEN
ns_mode <= STATE_1_DISPLAY;
ELSE
ns_mode <= STATE_0_SYNC_FRAME;
END IF;
WHEN STATE_1_DISPLAY =>
IF (end_of_active_frame = '1') THEN
ns_mode <= STATE_0_SYNC_FRAME;
ELSE
ns_mode <= STATE_1_DISPLAY;
END IF;
WHEN OTHERS =>
ns_mode <= STATE_0_SYNC_FRAME;
END CASE;
END PROCESS;
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
-- Output Registers
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
VGA_BLANK <= vga_blank_sync;
VGA_SYNC <= '0';
VGA_HS <= vga_h_sync;
VGA_VS <= vga_v_sync;
VGA_R <= vga_red;
VGA_G <= vga_green;
VGA_B <= vga_blue;
END IF;
END PROCESS;
-- Internal Registers
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
color_select <= B"0001";
ELSIF (s_mode = STATE_0_SYNC_FRAME) THEN
color_select <= B"0001";
ELSIF (read_enable = '0') THEN
color_select <= (color_select(2 DOWNTO 0) & color_select(3));
END IF;
END IF;
END PROCESS;
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
-- Output Assignments
ready <=
valid AND NOT startofpacket WHEN (s_mode = STATE_0_SYNC_FRAME) ELSE
read_enable;
VGA_CLK <= NOT clk;
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
VGA_Timing : altera_up_avalon_video_vga_timing
GENERIC MAP (
CW => CW,
H_ACTIVE => H_ACTIVE,
H_FRONT_PORCH => H_FRONT_PORCH,
H_SYNC => H_SYNC,
H_BACK_PORCH => H_BACK_PORCH,
H_TOTAL => H_TOTAL,
V_ACTIVE => V_ACTIVE,
V_FRONT_PORCH => V_FRONT_PORCH,
V_SYNC => V_SYNC,
V_BACK_PORCH => V_BACK_PORCH,
V_TOTAL => V_TOTAL,
LW => LW,
LINE_COUNTER_INCREMENT => LINE_COUNTER_INCREMENT,
PW => PW,
PIXEL_COUNTER_INCREMENT => PIXEL_COUNTER_INCREMENT
)
PORT MAP (
-- Inputs
clk => clk,
reset => reset,
red_to_vga_display => data(R_UI DOWNTO R_LI),
green_to_vga_display => data(G_UI DOWNTO G_LI),
blue_to_vga_display => data(B_UI DOWNTO B_LI),
color_select => color_select,
-- Bidirectionals
-- Outputs
read_enable => read_enable,
end_of_active_frame => end_of_active_frame, -- end_of_frame,
-- dac pins
vga_blank => vga_blank_sync,
vga_c_sync => vga_c_sync,
vga_h_sync => vga_h_sync,
vga_v_sync => vga_v_sync,
vga_data_enable => vga_data_enable,
vga_red => vga_red,
vga_green => vga_green,
vga_blue => vga_blue,
vga_color_data => vga_color_data
);
END Behaviour;
| gpl-2.0 | d188c4d32033459f8f2bcaa982a7aef4 | 0.471068 | 3.69494 | false | false | false | false |
DreamIP/GPStudio | support/toolchain/caph/hdl/caph_lib/caph.vhd | 1 | 13,658 | -----------------------------------------------------------------------------------------
-- --
-- This file is part of the CAPH Compiler distribution --
-- http://caph.univ-bpclermont.fr --
-- --
-- Jocelyn SEROT --
-- [email protected] --
-- --
-- Copyright 2011-2015 Jocelyn SEROT. All rights reserved. --
-- This file is distributed under the terms of the GNU Library General Public License --
-- with the special exception on linking described in file ../LICENSE. --
-- --
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package core is
function cond(e1: boolean; e2: signed; e3: signed) return signed;
function cond(e1: boolean; e2: unsigned; e3: unsigned) return unsigned;
function cond(e1: boolean; e2: std_logic_vector; e3: std_logic_vector) return std_logic_vector;
function eq(e1: signed; e2: signed) return unsigned;
function eq(e1: unsigned; e2: unsigned) return unsigned;
function mul(e1: signed; e2: signed) return signed;
function mul(e1: unsigned; e2: unsigned) return unsigned;
function to_std_logic_vector(e: unsigned; s: natural) return std_logic_vector;
function to_std_logic_vector(e: signed; s: natural) return std_logic_vector;
function to_std_logic_vector(e: boolean; s: natural) return std_logic_vector;
function from_std_logic_vector(e: std_logic_vector; s: natural) return unsigned;
function from_std_logic_vector(e: std_logic_vector; s: natural) return signed;
function from_std_logic_vector(e: std_logic_vector; s: natural) return boolean;
function from_std_logic_vector(e: std_logic_vector; s: natural) return std_logic_vector;
function to_bool(e: unsigned) return boolean;
function to_bool(e: signed) return boolean;
function to_bool(e: std_logic_vector) return boolean;
function conv_unsigned(e: unsigned; s: natural) return unsigned;
function conv_unsigned(e: signed; s: natural) return unsigned;
function conv_unsigned(e: boolean; s: natural) return unsigned;
function conv_unsigned(e: integer; s: natural) return unsigned;
function conv_signed(e: signed; s: natural) return signed;
function conv_signed(e: unsigned; s: natural) return signed;
function conv_signed(e: boolean; s: natural) return signed;
function conv_signed(e: integer; s: natural) return signed;
function to_integer(e: integer) return integer;
function to_string(v : std_logic_vector) return string; -- for debug only
procedure dump_slv(name: string; v: std_logic_vector); -- for debug only
component stream_in is
generic ( filename: string := "input.bin"; size: integer := 10; period: integer := 2; blanking: boolean := false );
port ( full : in std_logic;
dout : out std_logic_vector(size-1 downto 0);
wr : out std_logic; -- write (push) signal, active 1 on clk^
clk : in std_logic;
rst : in std_logic
);
end component;
component stream_out is
generic ( filename: string := "vhdl_result.dat"; size: integer := 10);
port ( empty : in std_logic;
din : in std_logic_vector(size-1 downto 0);
rd : out std_logic; -- read (pop) signal
clk : in std_logic;
rst : in std_logic
);
end component;
component port_in is
generic ( filename: string := ""; size: integer := 10; ival: bit_vector);
port ( full : in std_logic;
dout : out std_logic_vector(size-1 downto 0);
wr : out std_logic; -- write (push) signal, active 1 on clk^
clk : in std_logic;
rst : in std_logic
);
end component;
component port_out is
generic ( filename: string := "result.bin"; size: integer := 10 );
port ( empty : in std_logic;
din : in std_logic_vector(size-1 downto 0);
rd : out std_logic; -- read (pop) signal, active 1 on clk^
clk : in std_logic;
rst : in std_logic
);
end component;
--~
--~ component split2 is
--~ generic ( size: integer := 10);
--~ port (
--~ d_f: out std_logic;
--~ d : in std_logic_vector (size-1 downto 0);
--~ d_wr : in std_logic;
--~ d1_f : in std_logic;
--~ d1 : out std_logic_vector(size-1 downto 0);
--~ d1_wr : out std_logic;
--~ d2_f : in std_logic;
--~ d2 : out std_logic_vector(size-1 downto 0);
--~ d2_wr : out std_logic
--~ );
--~ end component;
--~
--~ component split3 is
--~ generic ( size: integer := 10);
--~ port (
--~ d_f: out std_logic;
--~ d : in std_logic_vector (size-1 downto 0);
--~ d_wr : in std_logic;
--~ d1_f : in std_logic;
--~ d1 : out std_logic_vector(size-1 downto 0);
--~ d1_wr : out std_logic;
--~ d2_f : in std_logic;
--~ d2 : out std_logic_vector(size-1 downto 0);
--~ d2_wr : out std_logic;
--~ d3_f : in std_logic;
--~ d3 : out std_logic_vector(size-1 downto 0);
--~ d3_wr : out std_logic
--~ );
--~ end component;
--~
--~ component split4 is
--~ generic ( size: integer := 10);
--~ port (
--~ d_f: out std_logic;
--~ d : in std_logic_vector (size-1 downto 0);
--~ d_wr : in std_logic;
--~ d1_f : in std_logic;
--~ d1 : out std_logic_vector(size-1 downto 0);
--~ d1_wr : out std_logic;
--~ d2_f : in std_logic;
--~ d2 : out std_logic_vector(size-1 downto 0);
--~ d2_wr : out std_logic;
--~ d3_f : in std_logic;
--~ d3 : out std_logic_vector(size-1 downto 0);
--~ d3_wr : out std_logic;
--~ d4_f : in std_logic;
--~ d4 : out std_logic_vector(size-1 downto 0);
--~ d4_wr : out std_logic
--~ );
--~ end component;
--~
--~ component split5 is
--~ generic ( size: integer := 10);
--~ port (
--~ d_f: out std_logic;
--~ d : in std_logic_vector (size-1 downto 0);
--~ d_wr : in std_logic;
--~ d1_f : in std_logic;
--~ d1 : out std_logic_vector(size-1 downto 0);
--~ d1_wr : out std_logic;
--~ d2_f : in std_logic;
--~ d2 : out std_logic_vector(size-1 downto 0);
--~ d2_wr : out std_logic;
--~ d3_f : in std_logic;
--~ d3 : out std_logic_vector(size-1 downto 0);
--~ d3_wr : out std_logic;
--~ d4_f : in std_logic;
--~ d4 : out std_logic_vector(size-1 downto 0);
--~ d4_wr : out std_logic;
--~ d5_f : in std_logic;
--~ d5 : out std_logic_vector(size-1 downto 0);
--~ d5_wr : out std_logic
--~ );
--~ end component;
--~
--~ component split6 is
--~ generic ( size: integer := 10);
--~ port (
--~ d_f: out std_logic;
--~ d : in std_logic_vector (size-1 downto 0);
--~ d_wr : in std_logic;
--~ d1_f : in std_logic;
--~ d1 : out std_logic_vector(size-1 downto 0);
--~ d1_wr : out std_logic;
--~ d2_f : in std_logic;
--~ d2 : out std_logic_vector(size-1 downto 0);
--~ d2_wr : out std_logic;
--~ d3_f : in std_logic;
--~ d3 : out std_logic_vector(size-1 downto 0);
--~ d3_wr : out std_logic;
--~ d4_f : in std_logic;
--~ d4 : out std_logic_vector(size-1 downto 0);
--~ d4_wr : out std_logic;
--~ d5_f : in std_logic;
--~ d5 : out std_logic_vector(size-1 downto 0);
--~ d5_wr : out std_logic;
--~ d6_f : in std_logic;
--~ d6 : out std_logic_vector(size-1 downto 0);
--~ d6_wr : out std_logic
--~ );
--~ end component;
--component decoder is
-- generic ( size: integer := 8 )
-- port (
-- sel: in integer;
-- outp: std_logic_vector ( size-1 downto 0)
-- );
--end component;
end core;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- use STD.textio.all; -- FOR DEBUG ONLY
package body core is
function cond(e1: boolean; e2: signed; e3: signed) return signed is
begin
if e1 then return e2; else return e3; end if;
end;
function cond(e1: boolean; e2: unsigned; e3: unsigned) return unsigned is
begin
if e1 then return e2; else return e3; end if;
end;
function cond(e1: boolean; e2: std_logic_vector; e3: std_logic_vector) return std_logic_vector is
begin
if e1 then return e2; else return e3; end if;
end;
function eq(e1: signed; e2: signed) return unsigned is
begin
if ( e1 = e2 ) then
return "1";
else
return "0";
end if;
end;
function eq(e1: unsigned; e2: unsigned) return unsigned is
begin
if ( e1 = e2 ) then
return "1";
else
return "0";
end if;
end;
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function mul (e1: signed; e2: signed) return signed is
constant length: INTEGER := maximum(e1'length, e2'length);
begin
return resize(e1*e2, length);
end;
function mul (e1: unsigned; e2: unsigned) return unsigned is
constant length: INTEGER := maximum(e1'length, e2'length);
begin
return resize(e1*e2, length);
end;
function to_std_logic_vector(e: unsigned; s:natural) return std_logic_vector is
begin
return STD_LOGIC_VECTOR(resize(e,s));
end;
function to_std_logic_vector(e: signed; s:natural) return std_logic_vector is
begin
return STD_LOGIC_VECTOR(resize(e,s));
end;
function to_std_logic_vector(e: boolean; s:natural) return std_logic_vector is
begin
if e then
return STD_LOGIC_VECTOR(TO_UNSIGNED(0,s-1)) & "1";
else
return STD_LOGIC_VECTOR(TO_UNSIGNED(0,s-1)) & "0";
end if;
end;
function from_std_logic_vector(e: std_logic_vector; s:natural) return unsigned is
begin
-- return UNSIGNED(e(s-1 downto 0));
-- return UNSIGNED(e(e'high downto e'high-s+1));
return UNSIGNED(e(s-1 downto 0)); -- Changed in v2.6.2: in variants, fields are RIGHT justified
end;
function from_std_logic_vector(e: std_logic_vector; s:natural) return signed is
begin
-- return SIGNED(e(s-1 downto 0));
-- return SIGNED(e(e'high downto e'high-s+1));
return SIGNED(e(s-1 downto 0)); -- Changed in v2.6.2: in variants, fields are RIGHT justified
end;
function from_std_logic_vector(e: std_logic_vector; s:natural) return boolean is
begin
-- if e(e'high downto e'high) = "1" then
if e(0 downto 0) = "1" then -- Changed in v2.6.2: in variants, fields are RIGHT justified
return true;
else
return false;
end if;
end;
function from_std_logic_vector(e: std_logic_vector; s:natural) return std_logic_vector is
begin
return (e(s-1 downto 0)); -- Changed in v2.6.2: in variants, fields are RIGHT justified
-- return e(e'high downto e'high-s+1);
end;
function to_bool(e: unsigned) return boolean is
begin
if e = (e'range=>'0') then return false; else return true; end if;
end;
function to_bool(e: signed) return boolean is
begin
if e = (e'range=>'0') then return false; else return true; end if;
end;
function to_bool(e: std_logic_vector) return boolean is
begin
if e = (e'range=>'0') then return false; else return true; end if;
end;
function conv_unsigned(e: unsigned; s: natural) return unsigned is
begin
return resize(e, s);
end;
function conv_unsigned(e: signed; s: natural) return unsigned is
begin
return resize(unsigned(e), s);
end;
function conv_unsigned(e: boolean; s: natural) return unsigned is
begin
if ( e ) then return to_unsigned(1,s); else return to_unsigned(0,s); end if;
end;
function conv_unsigned(e: integer; s: natural) return unsigned is
begin
return to_unsigned(e,s);
end;
function conv_signed(e: signed; s: natural) return signed is
begin
return resize(e, s);
end;
function conv_signed(e: unsigned; s: natural) return signed is
begin
return resize(signed('0' & e), s);
end;
function conv_signed(e: boolean; s: natural) return signed is
begin
if ( e ) then return to_signed(1,s); else return to_signed(0,s); end if;
end;
function conv_signed(e: integer; s: natural) return signed is
begin
return to_signed(e,s);
end;
function to_integer(e: integer) return integer is
begin
return e;
end;
-- Debug aux fns
function to_string(v : std_logic_vector) return string is
variable s : string(1 to v'length) := (others => 'x');
variable c : string(1 to 3);
variable j : integer := 1;
begin
for i in v'high downto v'low loop
c := std_logic'image(v(i));
s(j to j) := c(2 to 2); -- c is a 3 character string (with quotes) !
j := j+1;
end loop;
return s;
end to_string;
procedure dump_slv(name: string; v: std_logic_vector) is
begin
report name & "[" & integer'image(v'high) & ":" & integer'image(v'low) & "]=" & to_string(v);
end;
end package body core;
| gpl-3.0 | ac883c4128c2dd6c1e451da4a39d15b1 | 0.564578 | 3.393292 | false | false | false | false |
DreamIP/GPStudio | support/io/mt9/hdl/mt9_config_slave.vhd | 1 | 9,823 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity mt9_config_slave is
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(4 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0);
-- connections to video sampler
enable_o : out std_logic;
flowlength_o : out std_logic_vector(31 downto 0);
-- connections to mt9_config_i2c
xstart_o : out std_logic_vector(15 downto 0);
ystart_o : out std_logic_vector(15 downto 0);
xend_o : out std_logic_vector(15 downto 0);
yend_o : out std_logic_vector(15 downto 0);
autoexp_o : out std_logic;
autoexptarget_o : out std_logic_vector(15 downto 0);
autoexpvmin_o : out std_logic_vector(15 downto 0);
autoexpvmax_o : out std_logic_vector(15 downto 0);
autoexpstepmin_o : out std_logic_vector(15 downto 0);
autoexpstepmax_o : out std_logic_vector(15 downto 0);
autoexpdampofset_o : out std_logic_vector(15 downto 0);
autoexpdampgain_o : out std_logic_vector(15 downto 0);
autoexpdampmax_o : out std_logic_vector(15 downto 0);
flipvert_o : out std_logic;
mirrorx_o : out std_logic;
binning_o : out std_logic;
integtime_o : out std_logic_vector(15 downto 0);
linelenght_o : out std_logic_vector(15 downto 0);
need_to_reconf_o : out std_logic
);
end mt9_config_slave;
architecture rtl of mt9_config_slave is
constant ENABLE_REG_ADDR : natural := 0;
constant FLOWLENGHT_REG_ADDR : natural := 1;
constant XSTART_REG_ADDR : natural := 2;
constant YSTART_REG_ADDR : natural := 3;
constant XEND_REG_ADDR : natural := 4;
constant YEND_REG_ADDR : natural := 5;
constant MODE_REG_ADDR : natural := 6;
constant INTEGTIME_REG_ADDR : natural := 7;
constant LINE_LENGHT_REG_ADDR : natural := 8;
constant AUTOEXPTARGET_REG_ADDR : natural := 9;
constant AUTOEXPVMIN_REG_ADDR : natural := 10;
constant AUTOEXPVMAX_REG_ADDR : natural := 11;
constant AUTOEXPMINSTEP_REG_ADDR : natural := 12;
constant AUTOEXPMAXSTEP_REG_ADDR : natural := 13;
constant AUTOEXPDAMPOFSET_REG_ADDR : natural := 14;
constant AUTOEXPDAMPGAIN_REG_ADDR : natural := 15;
constant AUTOEXPDAMPMAX_REG_ADDR : natural := 16;
signal data_out : std_logic_vector(31 downto 0);
signal enable_reg : std_logic;
signal flowlength_reg : std_logic_vector(31 downto 0);
signal xstart_reg : std_logic_vector(15 downto 0);
signal ystart_reg : std_logic_vector(15 downto 0);
signal xend_reg : std_logic_vector(15 downto 0);
signal yend_reg : std_logic_vector(15 downto 0);
signal autoexp_reg : std_logic;
signal autoexptarget_reg : std_logic_vector(15 downto 0);
signal autoexpvmin_reg : std_logic_vector(15 downto 0);
signal autoexpvmax_reg : std_logic_vector(15 downto 0);
signal autoexpstepmin_reg : std_logic_vector(15 downto 0);
signal autoexpstepmax_reg : std_logic_vector(15 downto 0);
signal autoexpdampofset_reg : std_logic_vector(15 downto 0);
signal autoexpdampgain_reg : std_logic_vector(15 downto 0);
signal autoexpdampmax_reg : std_logic_vector(15 downto 0);
signal flipvert_reg : std_logic;
signal mirrorx_reg : std_logic;
signal binning_reg : std_logic;
signal integtime_reg : std_logic_vector(15 downto 0);
signal linelenght_reg : std_logic_vector(15 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
enable_reg <= '0';
flowlength_reg <= std_logic_vector(to_unsigned(320*240, 32));
xstart_reg <= std_logic_vector(to_unsigned(0, 16));
ystart_reg <= std_logic_vector(to_unsigned(0, 16));
xend_reg <= std_logic_vector(to_unsigned(320, 16));
yend_reg <= std_logic_vector(to_unsigned(240, 16));
autoexp_reg <= '0';
autoexptarget_reg <= x"002C";
autoexpvmin_reg <= x"0001";
autoexpvmax_reg <= x"02A0";
autoexpstepmin_reg <= x"0070";
autoexpstepmax_reg <= x"0008";
autoexpdampofset_reg <= x"0200";
autoexpdampgain_reg <= x"0200";
autoexpdampmax_reg <= x"0140";
flipvert_reg <= '0';
mirrorx_reg <= '0';
binning_reg <= '0';
integtime_reg <= x"00E6";
linelenght_reg <= std_logic_vector(to_unsigned(1650, 16));
need_to_reconf_o <= '1';
elsif(rising_edge(clk_proc)) then
need_to_reconf_o <= '0';
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(ENABLE_REG_ADDR, 5))=>
enable_reg <= datawr_i(0);
when std_logic_vector(to_unsigned(FLOWLENGHT_REG_ADDR, 5))=>
flowlength_reg <= datawr_i;
when std_logic_vector(to_unsigned(XSTART_REG_ADDR, 5))=>
xstart_reg <= datawr_i(15 downto 0);
need_to_reconf_o <= '1';
when std_logic_vector(to_unsigned(YSTART_REG_ADDR, 5))=>
ystart_reg <= datawr_i(15 downto 0);
need_to_reconf_o <= '1';
when std_logic_vector(to_unsigned(XEND_REG_ADDR, 5))=>
xend_reg <= datawr_i(15 downto 0);
need_to_reconf_o <= '1';
when std_logic_vector(to_unsigned(YEND_REG_ADDR, 5))=>
yend_reg <= datawr_i(15 downto 0);
need_to_reconf_o <= '1';
when std_logic_vector(to_unsigned(MODE_REG_ADDR, 5))=>
autoexp_reg <= datawr_i(0);
flipvert_reg <= datawr_i(1);
mirrorx_reg <= datawr_i(2);
binning_reg <= datawr_i(3);
need_to_reconf_o <= '1';
when std_logic_vector(to_unsigned(INTEGTIME_REG_ADDR, 5))=>
integtime_reg <= datawr_i(15 downto 0);
need_to_reconf_o <= '1';
when std_logic_vector(to_unsigned(LINE_LENGHT_REG_ADDR, 5))=>
linelenght_reg <= datawr_i(15 downto 0);
need_to_reconf_o <= '1';
when std_logic_vector(to_unsigned(AUTOEXPTARGET_REG_ADDR, 5))=>
autoexptarget_reg <= datawr_i(15 downto 0);
need_to_reconf_o <= '1';
when std_logic_vector(to_unsigned(AUTOEXPVMIN_REG_ADDR, 5))=>
autoexpvmin_reg <= datawr_i(15 downto 0);
need_to_reconf_o <= '1';
when std_logic_vector(to_unsigned(AUTOEXPVMAX_REG_ADDR, 5))=>
autoexpvmax_reg <= datawr_i(15 downto 0);
need_to_reconf_o <= '1';
when std_logic_vector(to_unsigned(AUTOEXPMINSTEP_REG_ADDR, 5))=>
autoexpstepmin_reg <= datawr_i(15 downto 0);
need_to_reconf_o <= '1';
when std_logic_vector(to_unsigned(AUTOEXPMAXSTEP_REG_ADDR, 5))=>
autoexpstepmax_reg <= datawr_i(15 downto 0);
need_to_reconf_o <= '1';
when std_logic_vector(to_unsigned(AUTOEXPDAMPOFSET_REG_ADDR, 5))=>
autoexpdampofset_reg <= datawr_i(15 downto 0);
need_to_reconf_o <= '1';
when std_logic_vector(to_unsigned(AUTOEXPDAMPGAIN_REG_ADDR, 5))=>
autoexpdampgain_reg <= datawr_i(15 downto 0);
need_to_reconf_o <= '1';
when std_logic_vector(to_unsigned(AUTOEXPDAMPMAX_REG_ADDR, 5))=>
autoexpdampmax_reg <= datawr_i(15 downto 0);
need_to_reconf_o <= '1';
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
data_out <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(ENABLE_REG_ADDR, 5))=>
data_out <= x"0000000" & "000" & enable_reg;
when std_logic_vector(to_unsigned(FLOWLENGHT_REG_ADDR, 5))=>
data_out <= flowlength_reg;
when std_logic_vector(to_unsigned(XSTART_REG_ADDR, 5))=>
data_out <= x"0000" & xstart_reg;
when std_logic_vector(to_unsigned(YSTART_REG_ADDR, 5))=>
data_out <= x"0000" & ystart_reg;
when std_logic_vector(to_unsigned(XEND_REG_ADDR, 5))=>
data_out <= x"0000" & xend_reg;
when std_logic_vector(to_unsigned(YEND_REG_ADDR, 5))=>
data_out <= x"0000" & yend_reg;
when std_logic_vector(to_unsigned(MODE_REG_ADDR, 5))=>
data_out <= x"0000000" & binning_reg & mirrorx_reg & flipvert_reg & autoexp_reg;
when std_logic_vector(to_unsigned(INTEGTIME_REG_ADDR, 5))=>
data_out <= x"0000" & integtime_reg;
when std_logic_vector(to_unsigned(LINE_LENGHT_REG_ADDR, 5))=>
data_out <= x"0000" & linelenght_reg;
when std_logic_vector(to_unsigned(AUTOEXPTARGET_REG_ADDR, 5))=>
data_out <= x"0000" & autoexptarget_reg;
when std_logic_vector(to_unsigned(AUTOEXPVMIN_REG_ADDR, 5))=>
data_out <= x"0000" & autoexpvmin_reg;
when std_logic_vector(to_unsigned(AUTOEXPVMAX_REG_ADDR, 5))=>
data_out <= x"0000" & autoexpvmax_reg;
when std_logic_vector(to_unsigned(AUTOEXPMINSTEP_REG_ADDR, 5))=>
data_out <= x"0000" & autoexpstepmin_reg;
when std_logic_vector(to_unsigned(AUTOEXPMAXSTEP_REG_ADDR, 5))=>
data_out <= x"0000" & autoexpstepmax_reg;
when std_logic_vector(to_unsigned(AUTOEXPDAMPOFSET_REG_ADDR, 5))=>
data_out <= x"0000" & autoexpdampofset_reg;
when std_logic_vector(to_unsigned(AUTOEXPDAMPGAIN_REG_ADDR, 5))=>
data_out <= x"0000" & autoexpdampgain_reg;
when std_logic_vector(to_unsigned(AUTOEXPDAMPMAX_REG_ADDR, 5))=>
data_out <= x"0000" & autoexpdampmax_reg;
when others=>
end case;
end if;
end if;
end process;
datard_o <= data_out;
enable_o <= enable_reg;
flowlength_o <= flowlength_reg;
xstart_o <= xstart_reg;
ystart_o <= ystart_reg;
xend_o <= xend_reg;
yend_o <= yend_reg;
autoexp_o <= autoexp_reg;
flipvert_o <= flipvert_reg;
mirrorx_o <= mirrorx_reg;
binning_o <= binning_reg;
integtime_o <= integtime_reg;
linelenght_o <= linelenght_reg;
autoexptarget_o <= autoexptarget_reg;
autoexpvmin_o <= autoexpvmin_reg;
autoexpvmax_o <= autoexpvmax_reg;
autoexpstepmin_o <= autoexpstepmin_reg;
autoexpstepmax_o <= autoexpstepmax_reg;
autoexpdampofset_o <= autoexpdampofset_reg;
autoexpdampgain_o <= autoexpdampgain_reg;
autoexpdampmax_o <= autoexpdampmax_reg;
end rtl;
| gpl-3.0 | 58fce9934a53e3861b2dbfcbf396d20c | 0.652754 | 2.670745 | false | false | false | false |
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