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DreamIP/GPStudio | support/process/sconv/hdl/sconv_process.vhd | 1 | 4,604 | -- Author : K. Abdelouahab
-- Company : DREAM - Institut Pascal - Unviersite Clermont Auvergne
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_process is
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer
);
port(
clk_proc : in std_logic;
reset_n : in std_logic;
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
w11,w12,w13 : in std_logic_vector ((PIX_WIDTH-1) downto 0);
w21,w22,w23 : in std_logic_vector ((PIX_WIDTH-1) downto 0);
w31,w32,w33 : in std_logic_vector ((PIX_WIDTH-1) downto 0);
norm : in std_logic_vector ((PIX_WIDTH-1) downto 0);
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0);
out_data : out std_logic_vector (PIX_WIDTH-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end conv_process;
architecture DataFlow of conv_process is
signal i00, i01, i02 : std_logic_vector (PIX_WIDTH-1 downto 0);
signal i10, i11, i12 : std_logic_vector (PIX_WIDTH-1 downto 0);
signal i20, i21, i22 : std_logic_vector (PIX_WIDTH-1 downto 0);
signal out_dvp : std_logic;
signal out_fvp : std_logic;
component kernel_3x3
generic(
PIX_WIDTH : integer
);
port (
reset_n : in std_logic;
clk_proc : in std_logic;
in_dv : in std_logic;
in_fv : in std_logic;
enable_i : in std_logic;
p11,p12,p13 : in std_logic_vector(PIX_WIDTH-1 downto 0);
p21,p22,p23 : in std_logic_vector(PIX_WIDTH-1 downto 0);
p31,p32,p33 : in std_logic_vector(PIX_WIDTH-1 downto 0);
ker11,ker12,ker13 : in std_logic_vector(PIX_WIDTH-1 downto 0);
ker21,ker22,ker23 : in std_logic_vector(PIX_WIDTH-1 downto 0);
ker31,ker32,ker33 : in std_logic_vector(PIX_WIDTH-1 downto 0);
norm : in std_logic_vector(PIX_WIDTH-1 downto 0);
out_data : out std_logic_vector(PIX_WIDTH-1 downto 0);
out_dv : out std_logic;
out_fv : out std_logic
);
end component;
component pipliner_3x3
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0);
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_fv : out std_logic;
out_dv : out std_logic;
p00, p01, p02 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p10, p11, p12 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p20, p21, p22 : out std_logic_vector((PIX_WIDTH-1) downto 0)
);
end component;
------------------------------------------------------------------------------
begin
inst_pipliner : pipliner_3x3
generic map(
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
PIX_WIDTH => PIX_WIDTH
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_fv => out_fvp,
out_dv => out_dvp,
enable_i => enable_i ,
widthimg_i => widthimg_i,
p00 => i00, p01 => i01, p02 => i02,
p10 => i10, p11 => i11, p12 => i12,
p20 => i20, p21 => i21, p22 => i22
);
inst_ker : kernel_3x3
generic map(
PIX_WIDTH => PIX_WIDTH
)
port map(
clk_proc => clk_proc,
reset_n => reset_n,
in_fv => out_fvp,
in_dv => out_dvp,
enable_i => enable_i,
norm => norm,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv,
p11 => i00, p12 => i01, p13 => i02,
p21 => i10, p22 => i11, p23 => i12,
p31 => i20, p32 => i21, p33 => i22,
ker11 => w11, ker12 => w12, ker13 => w13,
ker21 => w21, ker22 => w22, ker23 => w23,
ker31 => w31, ker32 => w32, ker33 => w33
);
end DataFlow;
| gpl-3.0 | 0eda4c6cf8224995f055e0b67541af7f | 0.481755 | 3.140518 | false | false | false | false |
ou-cse-378/vhdl-tetris | returnstack.vhd | 1 | 2,342 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: returnstack.vhd
-- // Date: 12/9/2004
-- // Description: Return stack Module
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ReturnStack is
Port ( Rin : in std_logic_vector(15 downto 0);
rsel : in std_logic;
rload : in std_logic;
rdec : in std_logic;
clr : in std_logic;
clk : in std_logic;
rpush : in std_logic;
rpop : in std_logic;
R : out std_logic_vector(15 downto 0));
end ReturnStack;
architecture Behavioral of ReturnStack is
component mux2g
generic(width:positive);
Port (
a : in std_logic_vector(width-1 downto 0);
b : in std_logic_vector(width-1 downto 0);
sel : in std_logic;
y : out std_logic_vector(width-1 downto 0)
);
end component;
component reg2
generic(width: positive);
port (
d : in STD_LOGIC_VECTOR (width-1 downto 0);
load : in STD_LOGIC;
dec : in STD_LOGIC;
clr : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (width-1 downto 0)
);
end component;
component stack32x16
port (
d : in STD_LOGIC_VECTOR(15 downto 0);
clk : in STD_LOGIC;
clr : in STD_LOGIC;
push : in STD_LOGIC;
pop : in STD_LOGIC;
full : out STD_LOGIC;
empty : out STD_LOGIC;
q : out STD_LOGIC_VECTOR(15 downto 0)
);
end component;
constant bus_width: positive := 16;
signal R_IN: std_logic_vector (15 downto 0);
signal RS: std_logic_vector (15 downto 0);
signal R1: std_logic_vector (15 downto 0);
signal FULL: std_logic;
signal EMPTY: std_logic;
begin
R <= RS;
SWmux2g : mux2g generic map (width => bus_width) port map
( a => Rin, b => R1, sel => rsel, y => R_IN );
SWr : reg2 generic map (width => bus_width) port map
( d => R_IN, load => rload, dec => rdec, clr => clr, clk => clk, q => RS );
SWstack32x16: stack32x16 port map
( d => RS, clk => clk, clr => clr, push => rpush, pop => rpop, full => FULL, empty => EMPTY, q => R1 );
end Behavioral;
| mit | ce942788086165a5b58b5bc71a03f19c | 0.553373 | 3.345714 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/addrDecodeRtl.vhd | 3 | 4,113 | -------------------------------------------------------------------------------
--! @file addrDecodeRtl.vhd
--
--! @brief Address Decoder for generating select signal
--
--! @details This address decoder generates a select signal depending on the
--! provided base- and high-addresses by using smaller/greater logic.
--! Additionally a strob is generated if the base or high address is selected.
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity addrDecode is
generic (
--! Address bus width
gAddrWidth : natural := 32;
--! Decode space base address
gBaseAddr : natural := 16#1000#;
--! Decode space high address
gHighAddr : natural := 16#1FFF#
);
port (
--! Enable decoding
iEnable : in std_logic;
--! Address bus
iAddress : in std_logic_vector(gAddrWidth-1 downto 0);
--! Select output
oSelect : out std_logic
);
end addrDecode;
architecture rtl of addrDecode is
--! Address to be decoded
signal address : unsigned(gAddrWidth-1 downto 0);
--! Address is in range
signal addressInRange : std_logic;
--! Base address used for comparison
constant cBase : unsigned(gAddrWidth-1 downto 0) :=
to_unsigned(gBaseAddr, gAddrWidth);
--! High address used for comparison
constant cHigh : unsigned(gAddrWidth-1 downto 0) :=
to_unsigned(gHighAddr, gAddrWidth);
begin
-- check generics
assert (gBaseAddr < gHighAddr)
report "Base address should be smaller than High address!" severity failure;
-- connect ports to signals
oSelect <= addressInRange;
address <= unsigned(iAddress);
--! Decode input address logic
combAddrDec : process (
iEnable,
address
)
begin
--default assignments of process outputs
addressInRange <= cInactivated;
if iEnable = cActivated then
if (cBase <= address) and (address <= cHigh) then
addressInRange <= cActivated;
end if;
end if;
end process;
end rtl;
| gpl-2.0 | ed6818e681b867e98da7380b16e1c1e8 | 0.631656 | 4.884798 | false | false | false | false |
marzoul/PoC | src/common/strings.vhdl | 1 | 30,077 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: String related functions and types
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
--use PoC.FileIO.all;
package strings is
-- default fill and string termination character for fixed size strings
-- ===========================================================================
constant C_POC_NUL : CHARACTER := ite((SYNTHESIS_TOOL /= SYNTHESIS_TOOL_ALTERA_QUARTUS2), NUL, '`');
-- character 0 causes Quartus to crash, if uses to pad STRINGs
-- characters < 32 (control characters) are not supported in Quartus
-- characters > 127 are not supported in VHDL files (strict ASCII files)
-- character 255 craches ISE log window (created by 'CHARACTER'val(255)')
-- Type declarations
-- ===========================================================================
subtype T_RAWCHAR is STD_LOGIC_VECTOR(7 downto 0);
type T_RAWSTRING is array (NATURAL range <>) of T_RAWCHAR;
-- testing area:
-- ===========================================================================
function to_IPStyle(str : STRING) return T_IPSTYLE;
-- to_char
function to_char(value : STD_LOGIC) return CHARACTER;
function to_char(value : NATURAL) return CHARACTER;
function to_char(rawchar : T_RAWCHAR) return CHARACTER;
-- chr_is* function
function chr_isDigit(chr : character) return boolean;
function chr_isLowerHexDigit(chr : character) return boolean;
function chr_isUpperHexDigit(chr : character) return boolean;
function chr_isHexDigit(chr : character) return boolean;
function chr_isLower(chr : character) return boolean;
function chr_isLowerAlpha(chr : character) return boolean;
function chr_isUpper(chr : character) return boolean;
function chr_isUpperAlpha(chr : character) return boolean;
function chr_isAlpha(chr : character) return boolean;
-- raw_format_* functions
function raw_format_bool_bin(value : BOOLEAN) return STRING;
function raw_format_bool_chr(value : BOOLEAN) return STRING;
function raw_format_bool_str(value : BOOLEAN) return STRING;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_nat_bin(value : NATURAL) return STRING;
function raw_format_nat_oct(value : NATURAL) return STRING;
function raw_format_nat_dec(value : NATURAL) return STRING;
function raw_format_nat_hex(value : NATURAL) return STRING;
-- str_format_* functions
function str_format(value : REAL; precision : NATURAL := 3) return STRING;
-- to_string
function to_string(value : BOOLEAN) return STRING;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING;
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING;
function to_string(rawstring : T_RAWSTRING) return STRING;
-- to_slv
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR;
-- to_digit*
function to_digit_bin(chr : character) return integer;
function to_digit_oct(chr : character) return integer;
function to_digit_dec(chr : character) return integer;
function to_digit_hex(chr : character) return integer;
function to_digit(chr : character; base : character := 'd') return integer;
-- to_natural*
function to_natural_bin(str : STRING) return INTEGER;
function to_natural_oct(str : STRING) return INTEGER;
function to_natural_dec(str : STRING) return INTEGER;
function to_natural_hex(str : STRING) return INTEGER;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER;
-- to_raw*
function to_RawChar(char : character) return T_RAWCHAR;
function to_RawString(str : string) return T_RAWSTRING;
-- resize
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING;
-- function resize(rawstr : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING;
-- Character functions
function chr_toLower(chr : character) return character;
function chr_toUpper(chr : character) return character;
-- String functions
function str_length(str : STRING) return NATURAL;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_find(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_find(str : STRING; pattern : STRING) return BOOLEAN;
function str_ifind(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_ifind(str : STRING; pattern : STRING) return BOOLEAN;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING;
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_trim(str : STRING) return STRING;
function str_toLower(str : STRING) return STRING;
function str_toUpper(str : STRING) return STRING;
end package;
package body strings is
--
function to_IPStyle(str : STRING) return T_IPSTYLE is
begin
for i in T_IPSTYLE'pos(T_IPSTYLE'low) to T_IPSTYLE'pos(T_IPSTYLE'high) loop
if str_imatch(str, T_IPSTYLE'image(T_IPSTYLE'val(I))) then
return T_IPSTYLE'val(i);
end if;
end loop;
report "Unknown IPStyle: '" & str & "'" severity FAILURE;
end function;
-- to_char
-- ===========================================================================
function to_char(value : STD_LOGIC) return CHARACTER is
begin
case value IS
when 'U' => return 'U';
when 'X' => return 'X';
when '0' => return '0';
when '1' => return '1';
when 'Z' => return 'Z';
when 'W' => return 'W';
when 'L' => return 'L';
when 'H' => return 'H';
when '-' => return '-';
when others => return 'X';
end case;
end function;
-- TODO: rename to to_HexDigit(..) ?
function to_char(value : natural) return character is
constant HEX : string := "0123456789ABCDEF";
begin
return ite(value < 16, HEX(value+1), 'X');
end function;
function to_char(rawchar : T_RAWCHAR) return CHARACTER is
begin
return CHARACTER'val(to_integer(unsigned(rawchar)));
end function;
-- chr_is* function
function chr_isDigit(chr : character) return boolean is
begin
return (character'pos('0') <= character'pos(chr)) and (character'pos(chr) <= character'pos('9'));
end function;
function chr_isLowerHexDigit(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('f'));
end function;
function chr_isUpperHexDigit(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('F'));
end function;
function chr_isHexDigit(chr : character) return boolean is
begin
return chr_isDigit(chr) or chr_isLowerHexDigit(chr) or chr_isUpperHexDigit(chr);
end function;
function chr_isLower(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr);
end function;
function chr_isLowerAlpha(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('z'));
end function;
function chr_isUpper(chr : character) return boolean is
begin
return chr_isUpperAlpha(chr);
end function;
function chr_isUpperAlpha(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('Z'));
end function;
function chr_isAlpha(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr) or chr_isUpperAlpha(chr);
end function;
-- raw_format_* functions
-- ===========================================================================
function raw_format_bool_bin(value : BOOLEAN) return STRING is
begin
return ite(value, "1", "0");
end function;
function raw_format_bool_chr(value : BOOLEAN) return STRING is
begin
return ite(value, "T", "F");
end function;
function raw_format_bool_str(value : BOOLEAN) return STRING is
begin
return str_toUpper(boolean'image(value));
end function;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to slv'length);
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector and normalize range to slv'low = 0
Value := movez(ite(slv'ascending, descend(slv), slv));
-- convert each bit to a character
J := 0;
for i in Result'reverse_range loop
Result(i) := to_char(Value(j));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(2 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector; normalize range to slv'low = 0 and resize it to a multiple of 3
Value := resize(movez(ite(slv'ascending, descend(slv), slv)), (Result'length * 3));
-- convert 3 bit to a character
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 3) + 2 downto (j * 3));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
subtype TT_BCD is INTEGER range 0 to 31;
type TT_BCD_VECTOR is array(natural range <>) of TT_BCD;
variable Temp : TT_BCD_VECTOR(div_ceil(slv'length, 3) - 1 downto 0);
variable Carry : T_UINT_8;
variable Pos : NATURAL;
begin
Temp := (others => 0);
Pos := 0;
-- convert input slv to a downto ranged vector
Value := ite(slv'ascending, descend(slv), slv);
for i in Value'range loop
Carry := to_int(Value(i));
for j in Temp'reverse_range loop
Temp(j) := Temp(j) * 2 + Carry;
Carry := to_int(Temp(j) > 9);
Temp(j) := Temp(j) - to_int((Temp(j) > 9), 0, 10);
end loop;
end loop;
for i in Result'range loop
Result(i) := to_char(Temp(Temp'high - i + 1));
if ((Result(i) /= '0') and (Pos = 0)) then
Pos := i;
end if;
end loop;
-- trim leading zeros, except the last
return Result(imin(Pos, Result'high) to Result'high);
end function;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(4*div_ceil(slv'length, 4) - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(3 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 4));
variable j : NATURAL;
begin
Value := resize(slv, Value'length);
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 4) + 3 downto (j * 4));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_nat_bin(value : NATURAL) return STRING is
begin
return raw_format_slv_bin(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_oct(value : NATURAL) return STRING is
begin
return raw_format_slv_oct(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_dec(value : NATURAL) return STRING is
begin
return INTEGER'image(value);
end function;
function raw_format_nat_hex(value : NATURAL) return STRING is
begin
return raw_format_slv_hex(to_slv(value, log2ceilnz(value+1)));
end function;
-- str_format_* functions
-- ===========================================================================
function str_format(value : REAL; precision : NATURAL := 3) return STRING is
constant s : REAL := sign(value);
constant val : REAL := value * s;
constant int : INTEGER := integer(floor(val));
constant frac : INTEGER := integer(round((val - real(int)) * 10.0**precision));
constant frac_str : STRING := INTEGER'image(frac);
constant res : STRING := INTEGER'image(int) & "." & (2 to (precision - frac_str'length + 1) => '0') & frac_str;
begin
return ite ((s < 0.0), "-" & res, res);
end function;
-- to_string
-- ===========================================================================
function to_string(value : boolean) return string is
begin
return raw_format_bool_str(value);
end function;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING is
constant absValue : NATURAL := abs(value);
constant len : POSITIVE := log10ceilnz(absValue);
variable power : POSITIVE;
variable Result : STRING(1 TO len);
begin
power := 1;
if (base = 10) then
return INTEGER'image(value);
else
for i in len downto 1 loop
Result(i) := to_char(absValue / power MOD base);
power := power * base;
end loop;
if (value < 0) then
return '-' & Result;
else
return Result;
end if;
end if;
end function;
-- TODO: rename to slv_format(..) ?
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING is
constant int : INTEGER := ite((slv'length <= 31), to_integer(unsigned(resize(slv, 31))), 0);
constant str : STRING := INTEGER'image(int);
constant bin_len : POSITIVE := slv'length;
constant dec_len : POSITIVE := str'length;--log10ceilnz(int);
constant hex_len : POSITIVE := ite(((bin_len MOD 4) = 0), (bin_len / 4), (bin_len / 4) + 1);
constant len : NATURAL := ite((format = 'b'), bin_len,
ite((format = 'd'), dec_len,
ite((format = 'h'), hex_len, 0)));
variable j : NATURAL;
variable Result : STRING(1 to ite((length = 0), len, imax(len, length)));
begin
j := 0;
Result := (others => fill);
if (format = 'b') then
for i in Result'reverse_range loop
Result(i) := to_char(slv(j));
j := j + 1;
end loop;
elsif (format = 'd') then
-- if (slv'length < 32) then
-- return INTEGER'image(int);
-- else
-- return raw_format_slv_dec(slv);
-- end if;
Result(Result'length - str'length + 1 to Result'high) := str;
elsif (format = 'h') then
for i in Result'reverse_range loop
Result(i) := to_char(to_integer(unsigned(slv((j * 4) + 3 downto (j * 4)))));
j := j + 1;
end loop;
else
report "unknown format" severity FAILURE;
end if;
return Result;
end function;
function to_string(rawstring : T_RAWSTRING) return STRING is
variable str : STRING(1 to rawstring'length);
begin
for i in rawstring'low to rawstring'high loop
str(I - rawstring'low + 1) := to_char(rawstring(I));
end loop;
return str;
end function;
-- to_slv
-- ===========================================================================
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR((rawstring'length * 8) - 1 downto 0);
begin
for i in rawstring'range loop
result(((i - rawstring'low) * 8) + 7 downto (i - rawstring'low) * 8) := rawstring(i);
end loop;
return result;
end function;
-- to_*
-- ===========================================================================
function to_digit_bin(chr : character) return integer is
begin
case chr is
when '0' => return 0;
when '1' => return 1;
when others => return -1;
end case;
end function;
function to_digit_oct(chr : character) return integer is
variable dec : integer;
begin
dec := to_digit_dec(chr);
return ite((dec < 8), dec, -1);
end function;
function to_digit_dec(chr : character) return integer is
begin
if chr_isDigit(chr) then
return character'pos(chr) - character'pos('0');
else
return -1;
end if;
end function;
function to_digit_hex(chr : character) return integer is
begin
if chr_isDigit(chr) then return character'pos(chr) - character'pos('0');
elsif chr_isLowerHexDigit(chr) then return character'pos(chr) - character'pos('a') + 10;
elsif chr_isUpperHexDigit(chr) then return character'pos(chr) - character'pos('A') + 10;
else return -1;
end if;
end function;
function to_digit(chr : character; base : character := 'd') return integer is
begin
case base is
when 'b' => return to_digit_bin(chr);
when 'o' => return to_digit_oct(chr);
when 'd' => return to_digit_dec(chr);
when 'h' => return to_digit_hex(chr);
when others => report "Unknown base character: " & base & "." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function to_natural_bin(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_bin(str(I));
if (Digit /= -1) then
Result := Result * 2 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_oct(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_oct(str(I));
if (Digit /= -1) then
Result := Result * 8 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_dec(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_dec(str(I));
if (Digit /= -1) then
Result := Result * 10 + Digit;
else
return -1;
end if;
end loop;
return Result;
-- return INTEGER'value(str); -- 'value(...) is not supported by Vivado Synth 2014.1
end function;
function to_natural_hex(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_hex(str(I));
if (Digit /= -1) then
Result := Result * 16 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER is
begin
case base is
when 'b' => return to_natural_bin(str);
when 'o' => return to_natural_oct(str);
when 'd' => return to_natural_dec(str);
when 'h' => return to_natural_hex(str);
when others => report "unknown base" severity ERROR;
end case;
end function;
-- to_raw*
-- ===========================================================================
function to_RawChar(char : character) return t_rawchar is
begin
return std_logic_vector(to_unsigned(character'pos(char), t_rawchar'length));
end function;
function to_RawString(str : STRING) return T_RAWSTRING is
variable rawstr : T_RAWSTRING(0 to str'length - 1);
begin
for i in str'low to str'high loop
rawstr(i - str'low) := to_RawChar(str(i));
end loop;
return rawstr;
end function;
-- resize
-- ===========================================================================
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING is
constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
variable Result : STRING(1 to size);
begin
Result := (others => FillChar);
if (str'length > 0) then
Result(1 to imin(size, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
end if;
return Result;
end function;
-- function resize(str : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING is
-- constant ConstNUL : T_RAWSTRING(1 to 1) := (others => x"00");
-- variable Result : T_RAWSTRING(1 to size);
-- function ifthenelse(cond : BOOLEAN; value1 : T_RAWSTRING; value2 : T_RAWSTRING) return T_RAWSTRING is
-- begin
-- if cond then
-- return value1;
-- else
-- return value2;
-- end if;
-- end function;
-- begin
-- Result := (others => FillChar);
-- if (str'length > 0) then
-- Result(1 to imin(size, imax(1, str'length))) := ifthenelse((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
-- end if;
-- return Result;
-- end function;
-- Character functions
-- ===========================================================================
function chr_toLower(chr : character) return character is
begin
if chr_isUpperAlpha(chr) then
return character'val(character'pos(chr) - character'pos('A') + character'pos('a'));
else
return chr;
end if;
end function;
function chr_toUpper(chr : character) return character is
begin
if chr_isLowerAlpha(chr) then
return character'val(character'pos(chr) - character'pos('a') + character'pos('A'));
else
return chr;
end if;
end function;
-- String functions
-- ===========================================================================
function str_length(str : STRING) return NATURAL is
begin
for i in str'range loop
if (str(i) = C_POC_NUL) then
return i - str'low;
end if;
end loop;
return str'length;
end function;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
if str1'length /= str2'length then
return FALSE;
else
return (str1 = str2);
end if;
end function;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN is
constant len : NATURAL := imin(str1'length, str2'length);
begin
-- if both strings are empty
if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if;
-- compare char by char
for i in str1'low to str1'low + len - 1 loop
if (str1(i) /= str2(str2'low + (i - str1'low))) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) xor (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) and (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return TRUE;
end if;
end loop;
-- check special cases,
return (((str1'length = len) and (str2'length = len)) or -- both strings are fully consumed and equal
((str1'length > len) and (str1(str1'low + len) = C_POC_NUL)) or -- str1 is longer, but str_length equals len
((str2'length > len) and (str2(str2'low + len) = C_POC_NUL))); -- str2 is longer, but str_length equals len
end function;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
return str_match(str_toLower(str1), str_toLower(str2));
end function;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to str'high loop
exit when (str(i) = C_POC_NUL);
if (str(i) = chr) then
return i;
end if;
end loop;
return -1;
end function;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to (str'high - pattern'length + 1) loop
exit when (str(i) = C_POC_NUL);
if (str(i to i + pattern'length - 1) = pattern) then
return i;
end if;
end loop;
return -1;
end function;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), chr_toLower(chr));
end function;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), str_toLower(pattern));
end function;
-- function str_pos(str1 : STRING; str2 : STRING) return INTEGER is
-- variable PrefixTable : T_INTVEC(0 to str2'length);
-- variable j : INTEGER;
-- begin
-- -- construct prefix table for KMP algorithm
-- j := -1;
-- PrefixTable(0) := -1;
-- for i in str2'range loop
-- while ((j >= 0) and str2(j + 1) /= str2(i)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- PrefixTable(i - 1) := j + 1;
-- end loop;
--
-- -- search pattern str2 in text str1
-- j := 0;
-- for i in str1'range loop
-- while ((j >= 0) and str1(i) /= str2(j + 1)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- if ((j + 1) = str2'high) then
-- return i - str2'length + 1;
-- end if;
-- end loop;
--
-- return -1;
-- end function;
function str_find(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_pos(str, chr) > 0);
end function;
function str_find(str : STRING; pattern : STRING) return boolean is
begin
return (str_pos(str, pattern) > 0);
end function;
function str_ifind(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_ipos(str, chr) > 0);
end function;
function str_ifind(str : STRING; pattern : STRING) return boolean is
begin
return (str_ipos(str, pattern) > 0);
end function;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING is
variable pos : INTEGER;
begin
pos := str_pos(str, pattern);
if (pos > 0) then
if (pos = 1) then
return replace & str(pattern'length + 1 to str'length);
elsif (pos = str'length - pattern'length + 1) then
return str(1 to str'length - pattern'length) & replace;
else
return str(1 to pos - 1) & replace & str(pos + pattern'length to str'length);
end if;
else
return str;
end if;
end function;
-- examples:
-- 123456789ABC
-- input string: "Hello World."
-- low=1; high=12; length=12
--
-- str_substr("Hello World.", 0, 0) => "Hello World." - copy all
-- str_substr("Hello World.", 7, 0) => "World." - copy from pos 7 to end of string
-- str_substr("Hello World.", 7, 5) => "World" - copy from pos 7 for 5 characters
-- str_substr("Hello World.", 0, -7) => "Hello World." - copy all until character 8 from right boundary
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING is
variable StartOfString : positive;
variable EndOfString : positive;
begin
if (start < 0) then -- start is negative -> start substring at right string boundary
StartOfString := str'high + start + 1;
elsif (start = 0) then -- start is zero -> start substring at left string boundary
StartOfString := str'low;
else -- start is positive -> start substring at left string boundary + offset
StartOfString := start;
end if;
if (length < 0) then -- length is negative -> end substring at length'th character before right string boundary
EndOfString := str'high + length;
elsif (length = 0) then -- length is zero -> end substring at right string boundary
EndOfString := str'high;
else -- length is positive -> end substring at StartOfString + length
EndOfString := StartOfString + length - 1;
end if;
if (StartOfString < str'low) then report "StartOfString is out of str's range. (str=" & str & ")" severity error; end if;
if (EndOfString < str'high) then report "EndOfString is out of str's range. (str=" & str & ")" severity error; end if;
return str(StartOfString to EndOfString);
end function;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'range loop
if (str(i) /= char) then
return str(i to str'high);
end if;
end loop;
return "";
end function;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'reverse_range loop
if (str(i) /= char) then
return str(str'low to i);
end if;
end loop;
return "";
end function;
function str_trim(str : STRING) return STRING is
begin
return str(str'low to str'low + str_length(str) - 1);
end function;
function str_toLower(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toLower(str(I));
end loop;
return temp;
end function;
function str_toUpper(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toUpper(str(I));
end loop;
return temp;
end function;
end package body;
| apache-2.0 | 40a4de46bc86e8164807d9f6d2992ffe | 0.631579 | 3.223687 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/sync/gray_sync.vhdl | 1 | 925 | --
-- Gray Synchronizer
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library FPGALIB;
use FPGALIB.Numeric.all;
use FPGALIB.Sync.all;
entity Gray_Sync is
generic(
WIDTH : positive:=8;
DEPTH : positive:=2
);
port(
clk_i : in std_logic;
data_i : in unsigned(WIDTH-1 downto 0);
data_o : out unsigned(WIDTH-1 downto 0)
);
end entity Gray_Sync;
architecture Structural of Gray_Sync is
signal grayi, grayo : std_logic_vector(WIDTH-1 downto 0);
begin
grayi <= std_logic_vector(bin2gray(data_i));
i_sync: FFchain
generic map(WIDTH => WIDTH, DEPTH => DEPTH)
port map(clk_i => clk_i, rst_i => '0', ena_i => '1', data_i => grayi, data_o => grayo);
data_o <= unsigned(gray2bin(grayo));
end architecture Structural;
| bsd-3-clause | e69462932cd73724d108356acf7535b0 | 0.646486 | 3.104027 | false | false | false | false |
hoglet67/ElectronFpga | src/common/ROM/RomSmelk3006.vhd | 1 | 803,561 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity RomSmelk3006 is
port (
clk : in std_logic;
addr : in std_logic_vector(13 downto 0);
data : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of RomSmelk3006 is
signal rom_addr : std_logic_vector(13 downto 0);
begin
p_addr : process(addr)
begin
rom_addr <= (others => '0');
rom_addr(13 downto 0) <= addr;
end process;
p_rom : process
begin
wait until rising_edge(clk);
data <= (others => '0');
case rom_addr is
when "00" & x"000" => data <= x"00";
when "00" & x"001" => data <= x"00";
when "00" & x"002" => data <= x"00";
when "00" & x"003" => data <= x"4c";
when "00" & x"004" => data <= x"55";
when "00" & x"005" => data <= x"94";
when "00" & x"006" => data <= x"82";
when "00" & x"007" => data <= x"11";
when "00" & x"008" => data <= x"5a";
when "00" & x"009" => data <= x"53";
when "00" & x"00a" => data <= x"50";
when "00" & x"00b" => data <= x"49";
when "00" & x"00c" => data <= x"00";
when "00" & x"00d" => data <= x"30";
when "00" & x"00e" => data <= x"2e";
when "00" & x"00f" => data <= x"39";
when "00" & x"010" => data <= x"30";
when "00" & x"011" => data <= x"00";
when "00" & x"012" => data <= x"28";
when "00" & x"013" => data <= x"43";
when "00" & x"014" => data <= x"29";
when "00" & x"015" => data <= x"6c";
when "00" & x"016" => data <= x"1e";
when "00" & x"017" => data <= x"02";
when "00" & x"018" => data <= x"20";
when "00" & x"019" => data <= x"5b";
when "00" & x"01a" => data <= x"80";
when "00" & x"01b" => data <= x"44";
when "00" & x"01c" => data <= x"69";
when "00" & x"01d" => data <= x"73";
when "00" & x"01e" => data <= x"6b";
when "00" & x"01f" => data <= x"20";
when "00" & x"020" => data <= x"90";
when "00" & x"021" => data <= x"11";
when "00" & x"022" => data <= x"20";
when "00" & x"023" => data <= x"5b";
when "00" & x"024" => data <= x"80";
when "00" & x"025" => data <= x"42";
when "00" & x"026" => data <= x"61";
when "00" & x"027" => data <= x"64";
when "00" & x"028" => data <= x"20";
when "00" & x"029" => data <= x"90";
when "00" & x"02a" => data <= x"08";
when "00" & x"02b" => data <= x"20";
when "00" & x"02c" => data <= x"5b";
when "00" & x"02d" => data <= x"80";
when "00" & x"02e" => data <= x"46";
when "00" & x"02f" => data <= x"69";
when "00" & x"030" => data <= x"6c";
when "00" & x"031" => data <= x"65";
when "00" & x"032" => data <= x"20";
when "00" & x"033" => data <= x"85";
when "00" & x"034" => data <= x"b3";
when "00" & x"035" => data <= x"68";
when "00" & x"036" => data <= x"85";
when "00" & x"037" => data <= x"ae";
when "00" & x"038" => data <= x"68";
when "00" & x"039" => data <= x"85";
when "00" & x"03a" => data <= x"af";
when "00" & x"03b" => data <= x"a5";
when "00" & x"03c" => data <= x"b3";
when "00" & x"03d" => data <= x"48";
when "00" & x"03e" => data <= x"98";
when "00" & x"03f" => data <= x"48";
when "00" & x"040" => data <= x"a0";
when "00" & x"041" => data <= x"00";
when "00" & x"042" => data <= x"20";
when "00" & x"043" => data <= x"da";
when "00" & x"044" => data <= x"83";
when "00" & x"045" => data <= x"b1";
when "00" & x"046" => data <= x"ae";
when "00" & x"047" => data <= x"8d";
when "00" & x"048" => data <= x"01";
when "00" & x"049" => data <= x"01";
when "00" & x"04a" => data <= x"2c";
when "00" & x"04b" => data <= x"de";
when "00" & x"04c" => data <= x"10";
when "00" & x"04d" => data <= x"10";
when "00" & x"04e" => data <= x"25";
when "00" & x"04f" => data <= x"a9";
when "00" & x"050" => data <= x"02";
when "00" & x"051" => data <= x"8d";
when "00" & x"052" => data <= x"de";
when "00" & x"053" => data <= x"10";
when "00" & x"054" => data <= x"a9";
when "00" & x"055" => data <= x"00";
when "00" & x"056" => data <= x"8d";
when "00" & x"057" => data <= x"00";
when "00" & x"058" => data <= x"01";
when "00" & x"059" => data <= x"f0";
when "00" & x"05a" => data <= x"19";
when "00" & x"05b" => data <= x"a9";
when "00" & x"05c" => data <= x"02";
when "00" & x"05d" => data <= x"8d";
when "00" & x"05e" => data <= x"de";
when "00" & x"05f" => data <= x"10";
when "00" & x"060" => data <= x"a9";
when "00" & x"061" => data <= x"00";
when "00" & x"062" => data <= x"8d";
when "00" & x"063" => data <= x"00";
when "00" & x"064" => data <= x"01";
when "00" & x"065" => data <= x"85";
when "00" & x"066" => data <= x"b3";
when "00" & x"067" => data <= x"68";
when "00" & x"068" => data <= x"85";
when "00" & x"069" => data <= x"ae";
when "00" & x"06a" => data <= x"68";
when "00" & x"06b" => data <= x"85";
when "00" & x"06c" => data <= x"af";
when "00" & x"06d" => data <= x"a5";
when "00" & x"06e" => data <= x"b3";
when "00" & x"06f" => data <= x"48";
when "00" & x"070" => data <= x"98";
when "00" & x"071" => data <= x"48";
when "00" & x"072" => data <= x"a0";
when "00" & x"073" => data <= x"00";
when "00" & x"074" => data <= x"20";
when "00" & x"075" => data <= x"da";
when "00" & x"076" => data <= x"83";
when "00" & x"077" => data <= x"b1";
when "00" & x"078" => data <= x"ae";
when "00" & x"079" => data <= x"30";
when "00" & x"07a" => data <= x"08";
when "00" & x"07b" => data <= x"f0";
when "00" & x"07c" => data <= x"0d";
when "00" & x"07d" => data <= x"20";
when "00" & x"07e" => data <= x"9c";
when "00" & x"07f" => data <= x"80";
when "00" & x"080" => data <= x"4c";
when "00" & x"081" => data <= x"74";
when "00" & x"082" => data <= x"80";
when "00" & x"083" => data <= x"68";
when "00" & x"084" => data <= x"a8";
when "00" & x"085" => data <= x"68";
when "00" & x"086" => data <= x"18";
when "00" & x"087" => data <= x"6c";
when "00" & x"088" => data <= x"ae";
when "00" & x"089" => data <= x"00";
when "00" & x"08a" => data <= x"a9";
when "00" & x"08b" => data <= x"00";
when "00" & x"08c" => data <= x"ae";
when "00" & x"08d" => data <= x"de";
when "00" & x"08e" => data <= x"10";
when "00" & x"08f" => data <= x"9d";
when "00" & x"090" => data <= x"00";
when "00" & x"091" => data <= x"01";
when "00" & x"092" => data <= x"a9";
when "00" & x"093" => data <= x"ff";
when "00" & x"094" => data <= x"8d";
when "00" & x"095" => data <= x"de";
when "00" & x"096" => data <= x"10";
when "00" & x"097" => data <= x"4c";
when "00" & x"098" => data <= x"00";
when "00" & x"099" => data <= x"01";
when "00" & x"09a" => data <= x"a9";
when "00" & x"09b" => data <= x"2e";
when "00" & x"09c" => data <= x"20";
when "00" & x"09d" => data <= x"e1";
when "00" & x"09e" => data <= x"83";
when "00" & x"09f" => data <= x"2c";
when "00" & x"0a0" => data <= x"de";
when "00" & x"0a1" => data <= x"10";
when "00" & x"0a2" => data <= x"10";
when "00" & x"0a3" => data <= x"14";
when "00" & x"0a4" => data <= x"48";
when "00" & x"0a5" => data <= x"20";
when "00" & x"0a6" => data <= x"1c";
when "00" & x"0a7" => data <= x"99";
when "00" & x"0a8" => data <= x"8a";
when "00" & x"0a9" => data <= x"48";
when "00" & x"0aa" => data <= x"09";
when "00" & x"0ab" => data <= x"10";
when "00" & x"0ac" => data <= x"20";
when "00" & x"0ad" => data <= x"17";
when "00" & x"0ae" => data <= x"99";
when "00" & x"0af" => data <= x"68";
when "00" & x"0b0" => data <= x"aa";
when "00" & x"0b1" => data <= x"68";
when "00" & x"0b2" => data <= x"20";
when "00" & x"0b3" => data <= x"e3";
when "00" & x"0b4" => data <= x"ff";
when "00" & x"0b5" => data <= x"4c";
when "00" & x"0b6" => data <= x"18";
when "00" & x"0b7" => data <= x"99";
when "00" & x"0b8" => data <= x"ae";
when "00" & x"0b9" => data <= x"de";
when "00" & x"0ba" => data <= x"10";
when "00" & x"0bb" => data <= x"9d";
when "00" & x"0bc" => data <= x"00";
when "00" & x"0bd" => data <= x"01";
when "00" & x"0be" => data <= x"ee";
when "00" & x"0bf" => data <= x"de";
when "00" & x"0c0" => data <= x"10";
when "00" & x"0c1" => data <= x"60";
when "00" & x"0c2" => data <= x"48";
when "00" & x"0c3" => data <= x"20";
when "00" & x"0c4" => data <= x"05";
when "00" & x"0c5" => data <= x"82";
when "00" & x"0c6" => data <= x"20";
when "00" & x"0c7" => data <= x"ca";
when "00" & x"0c8" => data <= x"80";
when "00" & x"0c9" => data <= x"68";
when "00" & x"0ca" => data <= x"48";
when "00" & x"0cb" => data <= x"29";
when "00" & x"0cc" => data <= x"0f";
when "00" & x"0cd" => data <= x"c9";
when "00" & x"0ce" => data <= x"0a";
when "00" & x"0cf" => data <= x"90";
when "00" & x"0d0" => data <= x"02";
when "00" & x"0d1" => data <= x"69";
when "00" & x"0d2" => data <= x"06";
when "00" & x"0d3" => data <= x"69";
when "00" & x"0d4" => data <= x"30";
when "00" & x"0d5" => data <= x"20";
when "00" & x"0d6" => data <= x"9c";
when "00" & x"0d7" => data <= x"80";
when "00" & x"0d8" => data <= x"68";
when "00" & x"0d9" => data <= x"60";
when "00" & x"0da" => data <= x"20";
when "00" & x"0db" => data <= x"ea";
when "00" & x"0dc" => data <= x"80";
when "00" & x"0dd" => data <= x"ca";
when "00" & x"0de" => data <= x"ca";
when "00" & x"0df" => data <= x"20";
when "00" & x"0e0" => data <= x"e2";
when "00" & x"0e1" => data <= x"80";
when "00" & x"0e2" => data <= x"b1";
when "00" & x"0e3" => data <= x"b0";
when "00" & x"0e4" => data <= x"9d";
when "00" & x"0e5" => data <= x"72";
when "00" & x"0e6" => data <= x"10";
when "00" & x"0e7" => data <= x"e8";
when "00" & x"0e8" => data <= x"c8";
when "00" & x"0e9" => data <= x"60";
when "00" & x"0ea" => data <= x"20";
when "00" & x"0eb" => data <= x"ed";
when "00" & x"0ec" => data <= x"80";
when "00" & x"0ed" => data <= x"b1";
when "00" & x"0ee" => data <= x"b0";
when "00" & x"0ef" => data <= x"95";
when "00" & x"0f0" => data <= x"bc";
when "00" & x"0f1" => data <= x"e8";
when "00" & x"0f2" => data <= x"c8";
when "00" & x"0f3" => data <= x"60";
when "00" & x"0f4" => data <= x"a9";
when "00" & x"0f5" => data <= x"20";
when "00" & x"0f6" => data <= x"a2";
when "00" & x"0f7" => data <= x"06";
when "00" & x"0f8" => data <= x"95";
when "00" & x"0f9" => data <= x"c7";
when "00" & x"0fa" => data <= x"ca";
when "00" & x"0fb" => data <= x"10";
when "00" & x"0fc" => data <= x"fb";
when "00" & x"0fd" => data <= x"60";
when "00" & x"0fe" => data <= x"20";
when "00" & x"0ff" => data <= x"4d";
when "00" & x"100" => data <= x"83";
when "00" & x"101" => data <= x"20";
when "00" & x"102" => data <= x"f4";
when "00" & x"103" => data <= x"80";
when "00" & x"104" => data <= x"30";
when "00" & x"105" => data <= x"13";
when "00" & x"106" => data <= x"20";
when "00" & x"107" => data <= x"4d";
when "00" & x"108" => data <= x"83";
when "00" & x"109" => data <= x"20";
when "00" & x"10a" => data <= x"f4";
when "00" & x"10b" => data <= x"80";
when "00" & x"10c" => data <= x"a5";
when "00" & x"10d" => data <= x"bc";
when "00" & x"10e" => data <= x"85";
when "00" & x"10f" => data <= x"f2";
when "00" & x"110" => data <= x"a5";
when "00" & x"111" => data <= x"bd";
when "00" & x"112" => data <= x"85";
when "00" & x"113" => data <= x"f3";
when "00" & x"114" => data <= x"a0";
when "00" & x"115" => data <= x"00";
when "00" & x"116" => data <= x"20";
when "00" & x"117" => data <= x"bf";
when "00" & x"118" => data <= x"86";
when "00" & x"119" => data <= x"a2";
when "00" & x"11a" => data <= x"01";
when "00" & x"11b" => data <= x"20";
when "00" & x"11c" => data <= x"c5";
when "00" & x"11d" => data <= x"ff";
when "00" & x"11e" => data <= x"b0";
when "00" & x"11f" => data <= x"dd";
when "00" & x"120" => data <= x"85";
when "00" & x"121" => data <= x"c7";
when "00" & x"122" => data <= x"c9";
when "00" & x"123" => data <= x"2e";
when "00" & x"124" => data <= x"d0";
when "00" & x"125" => data <= x"04";
when "00" & x"126" => data <= x"a9";
when "00" & x"127" => data <= x"20";
when "00" & x"128" => data <= x"d0";
when "00" & x"129" => data <= x"4d";
when "00" & x"12a" => data <= x"c9";
when "00" & x"12b" => data <= x"3a";
when "00" & x"12c" => data <= x"d0";
when "00" & x"12d" => data <= x"21";
when "00" & x"12e" => data <= x"20";
when "00" & x"12f" => data <= x"c5";
when "00" & x"130" => data <= x"ff";
when "00" & x"131" => data <= x"b0";
when "00" & x"132" => data <= x"15";
when "00" & x"133" => data <= x"38";
when "00" & x"134" => data <= x"e9";
when "00" & x"135" => data <= x"30";
when "00" & x"136" => data <= x"90";
when "00" & x"137" => data <= x"10";
when "00" & x"138" => data <= x"c9";
when "00" & x"139" => data <= x"04";
when "00" & x"13a" => data <= x"b0";
when "00" & x"13b" => data <= x"0c";
when "00" & x"13c" => data <= x"20";
when "00" & x"13d" => data <= x"7e";
when "00" & x"13e" => data <= x"87";
when "00" & x"13f" => data <= x"20";
when "00" & x"140" => data <= x"c5";
when "00" & x"141" => data <= x"ff";
when "00" & x"142" => data <= x"b0";
when "00" & x"143" => data <= x"5c";
when "00" & x"144" => data <= x"c9";
when "00" & x"145" => data <= x"2e";
when "00" & x"146" => data <= x"f0";
when "00" & x"147" => data <= x"03";
when "00" & x"148" => data <= x"4c";
when "00" & x"149" => data <= x"74";
when "00" & x"14a" => data <= x"83";
when "00" & x"14b" => data <= x"a9";
when "00" & x"14c" => data <= x"24";
when "00" & x"14d" => data <= x"d0";
when "00" & x"14e" => data <= x"28";
when "00" & x"14f" => data <= x"c9";
when "00" & x"150" => data <= x"2a";
when "00" & x"151" => data <= x"d0";
when "00" & x"152" => data <= x"19";
when "00" & x"153" => data <= x"20";
when "00" & x"154" => data <= x"c5";
when "00" & x"155" => data <= x"ff";
when "00" & x"156" => data <= x"b0";
when "00" & x"157" => data <= x"08";
when "00" & x"158" => data <= x"c9";
when "00" & x"159" => data <= x"2e";
when "00" & x"15a" => data <= x"d0";
when "00" & x"15b" => data <= x"32";
when "00" & x"15c" => data <= x"a9";
when "00" & x"15d" => data <= x"23";
when "00" & x"15e" => data <= x"d0";
when "00" & x"15f" => data <= x"17";
when "00" & x"160" => data <= x"a2";
when "00" & x"161" => data <= x"00";
when "00" & x"162" => data <= x"a9";
when "00" & x"163" => data <= x"23";
when "00" & x"164" => data <= x"95";
when "00" & x"165" => data <= x"c7";
when "00" & x"166" => data <= x"e8";
when "00" & x"167" => data <= x"e0";
when "00" & x"168" => data <= x"07";
when "00" & x"169" => data <= x"d0";
when "00" & x"16a" => data <= x"f9";
when "00" & x"16b" => data <= x"60";
when "00" & x"16c" => data <= x"20";
when "00" & x"16d" => data <= x"c5";
when "00" & x"16e" => data <= x"ff";
when "00" & x"16f" => data <= x"b0";
when "00" & x"170" => data <= x"2f";
when "00" & x"171" => data <= x"c9";
when "00" & x"172" => data <= x"2e";
when "00" & x"173" => data <= x"d0";
when "00" & x"174" => data <= x"10";
when "00" & x"175" => data <= x"a5";
when "00" & x"176" => data <= x"c7";
when "00" & x"177" => data <= x"85";
when "00" & x"178" => data <= x"ce";
when "00" & x"179" => data <= x"4c";
when "00" & x"17a" => data <= x"1b";
when "00" & x"17b" => data <= x"81";
when "00" & x"17c" => data <= x"20";
when "00" & x"17d" => data <= x"c5";
when "00" & x"17e" => data <= x"ff";
when "00" & x"17f" => data <= x"b0";
when "00" & x"180" => data <= x"1f";
when "00" & x"181" => data <= x"e0";
when "00" & x"182" => data <= x"07";
when "00" & x"183" => data <= x"f0";
when "00" & x"184" => data <= x"09";
when "00" & x"185" => data <= x"c9";
when "00" & x"186" => data <= x"2a";
when "00" & x"187" => data <= x"d0";
when "00" & x"188" => data <= x"12";
when "00" & x"189" => data <= x"20";
when "00" & x"18a" => data <= x"c5";
when "00" & x"18b" => data <= x"ff";
when "00" & x"18c" => data <= x"b0";
when "00" & x"18d" => data <= x"d4";
when "00" & x"18e" => data <= x"20";
when "00" & x"18f" => data <= x"22";
when "00" & x"190" => data <= x"80";
when "00" & x"191" => data <= x"cc";
when "00" & x"192" => data <= x"66";
when "00" & x"193" => data <= x"69";
when "00" & x"194" => data <= x"6c";
when "00" & x"195" => data <= x"65";
when "00" & x"196" => data <= x"6e";
when "00" & x"197" => data <= x"61";
when "00" & x"198" => data <= x"6d";
when "00" & x"199" => data <= x"65";
when "00" & x"19a" => data <= x"00";
when "00" & x"19b" => data <= x"95";
when "00" & x"19c" => data <= x"c7";
when "00" & x"19d" => data <= x"e8";
when "00" & x"19e" => data <= x"d0";
when "00" & x"19f" => data <= x"dc";
when "00" & x"1a0" => data <= x"60";
when "00" & x"1a1" => data <= x"20";
when "00" & x"1a2" => data <= x"e1";
when "00" & x"1a3" => data <= x"83";
when "00" & x"1a4" => data <= x"ad";
when "00" & x"1a5" => data <= x"04";
when "00" & x"1a6" => data <= x"0f";
when "00" & x"1a7" => data <= x"20";
when "00" & x"1a8" => data <= x"47";
when "00" & x"1a9" => data <= x"83";
when "00" & x"1aa" => data <= x"cd";
when "00" & x"1ab" => data <= x"04";
when "00" & x"1ac" => data <= x"0f";
when "00" & x"1ad" => data <= x"f0";
when "00" & x"1ae" => data <= x"f1";
when "00" & x"1af" => data <= x"20";
when "00" & x"1b0" => data <= x"33";
when "00" & x"1b1" => data <= x"80";
when "00" & x"1b2" => data <= x"c8";
when "00" & x"1b3" => data <= x"44";
when "00" & x"1b4" => data <= x"69";
when "00" & x"1b5" => data <= x"73";
when "00" & x"1b6" => data <= x"6b";
when "00" & x"1b7" => data <= x"20";
when "00" & x"1b8" => data <= x"63";
when "00" & x"1b9" => data <= x"68";
when "00" & x"1ba" => data <= x"61";
when "00" & x"1bb" => data <= x"6e";
when "00" & x"1bc" => data <= x"67";
when "00" & x"1bd" => data <= x"65";
when "00" & x"1be" => data <= x"64";
when "00" & x"1bf" => data <= x"00";
when "00" & x"1c0" => data <= x"20";
when "00" & x"1c1" => data <= x"e1";
when "00" & x"1c2" => data <= x"83";
when "00" & x"1c3" => data <= x"b9";
when "00" & x"1c4" => data <= x"0f";
when "00" & x"1c5" => data <= x"0e";
when "00" & x"1c6" => data <= x"08";
when "00" & x"1c7" => data <= x"29";
when "00" & x"1c8" => data <= x"7f";
when "00" & x"1c9" => data <= x"d0";
when "00" & x"1ca" => data <= x"05";
when "00" & x"1cb" => data <= x"20";
when "00" & x"1cc" => data <= x"cb";
when "00" & x"1cd" => data <= x"9f";
when "00" & x"1ce" => data <= x"f0";
when "00" & x"1cf" => data <= x"06";
when "00" & x"1d0" => data <= x"20";
when "00" & x"1d1" => data <= x"9c";
when "00" & x"1d2" => data <= x"80";
when "00" & x"1d3" => data <= x"20";
when "00" & x"1d4" => data <= x"9a";
when "00" & x"1d5" => data <= x"80";
when "00" & x"1d6" => data <= x"a2";
when "00" & x"1d7" => data <= x"06";
when "00" & x"1d8" => data <= x"b9";
when "00" & x"1d9" => data <= x"08";
when "00" & x"1da" => data <= x"0e";
when "00" & x"1db" => data <= x"29";
when "00" & x"1dc" => data <= x"7f";
when "00" & x"1dd" => data <= x"20";
when "00" & x"1de" => data <= x"9c";
when "00" & x"1df" => data <= x"80";
when "00" & x"1e0" => data <= x"c8";
when "00" & x"1e1" => data <= x"ca";
when "00" & x"1e2" => data <= x"10";
when "00" & x"1e3" => data <= x"f4";
when "00" & x"1e4" => data <= x"20";
when "00" & x"1e5" => data <= x"cb";
when "00" & x"1e6" => data <= x"9f";
when "00" & x"1e7" => data <= x"a9";
when "00" & x"1e8" => data <= x"20";
when "00" & x"1e9" => data <= x"28";
when "00" & x"1ea" => data <= x"10";
when "00" & x"1eb" => data <= x"02";
when "00" & x"1ec" => data <= x"a9";
when "00" & x"1ed" => data <= x"4c";
when "00" & x"1ee" => data <= x"20";
when "00" & x"1ef" => data <= x"9c";
when "00" & x"1f0" => data <= x"80";
when "00" & x"1f1" => data <= x"4c";
when "00" & x"1f2" => data <= x"ce";
when "00" & x"1f3" => data <= x"9f";
when "00" & x"1f4" => data <= x"20";
when "00" & x"1f5" => data <= x"ce";
when "00" & x"1f6" => data <= x"9f";
when "00" & x"1f7" => data <= x"88";
when "00" & x"1f8" => data <= x"d0";
when "00" & x"1f9" => data <= x"fa";
when "00" & x"1fa" => data <= x"60";
when "00" & x"1fb" => data <= x"4a";
when "00" & x"1fc" => data <= x"4a";
when "00" & x"1fd" => data <= x"4a";
when "00" & x"1fe" => data <= x"4a";
when "00" & x"1ff" => data <= x"4a";
when "00" & x"200" => data <= x"4a";
when "00" & x"201" => data <= x"29";
when "00" & x"202" => data <= x"03";
when "00" & x"203" => data <= x"60";
when "00" & x"204" => data <= x"4a";
when "00" & x"205" => data <= x"4a";
when "00" & x"206" => data <= x"4a";
when "00" & x"207" => data <= x"4a";
when "00" & x"208" => data <= x"4a";
when "00" & x"209" => data <= x"60";
when "00" & x"20a" => data <= x"0a";
when "00" & x"20b" => data <= x"0a";
when "00" & x"20c" => data <= x"0a";
when "00" & x"20d" => data <= x"0a";
when "00" & x"20e" => data <= x"0a";
when "00" & x"20f" => data <= x"60";
when "00" & x"210" => data <= x"c8";
when "00" & x"211" => data <= x"c8";
when "00" & x"212" => data <= x"c8";
when "00" & x"213" => data <= x"c8";
when "00" & x"214" => data <= x"c8";
when "00" & x"215" => data <= x"c8";
when "00" & x"216" => data <= x"c8";
when "00" & x"217" => data <= x"c8";
when "00" & x"218" => data <= x"60";
when "00" & x"219" => data <= x"88";
when "00" & x"21a" => data <= x"88";
when "00" & x"21b" => data <= x"88";
when "00" & x"21c" => data <= x"88";
when "00" & x"21d" => data <= x"88";
when "00" & x"21e" => data <= x"88";
when "00" & x"21f" => data <= x"88";
when "00" & x"220" => data <= x"88";
when "00" & x"221" => data <= x"60";
when "00" & x"222" => data <= x"00";
when "00" & x"223" => data <= x"00";
when "00" & x"224" => data <= x"00";
when "00" & x"225" => data <= x"00";
when "00" & x"226" => data <= x"00";
when "00" & x"227" => data <= x"00";
when "00" & x"228" => data <= x"00";
when "00" & x"229" => data <= x"00";
when "00" & x"22a" => data <= x"00";
when "00" & x"22b" => data <= x"00";
when "00" & x"22c" => data <= x"00";
when "00" & x"22d" => data <= x"00";
when "00" & x"22e" => data <= x"00";
when "00" & x"22f" => data <= x"00";
when "00" & x"230" => data <= x"00";
when "00" & x"231" => data <= x"00";
when "00" & x"232" => data <= x"00";
when "00" & x"233" => data <= x"00";
when "00" & x"234" => data <= x"00";
when "00" & x"235" => data <= x"00";
when "00" & x"236" => data <= x"00";
when "00" & x"237" => data <= x"00";
when "00" & x"238" => data <= x"00";
when "00" & x"239" => data <= x"00";
when "00" & x"23a" => data <= x"00";
when "00" & x"23b" => data <= x"00";
when "00" & x"23c" => data <= x"00";
when "00" & x"23d" => data <= x"00";
when "00" & x"23e" => data <= x"00";
when "00" & x"23f" => data <= x"00";
when "00" & x"240" => data <= x"00";
when "00" & x"241" => data <= x"00";
when "00" & x"242" => data <= x"00";
when "00" & x"243" => data <= x"00";
when "00" & x"244" => data <= x"00";
when "00" & x"245" => data <= x"00";
when "00" & x"246" => data <= x"00";
when "00" & x"247" => data <= x"00";
when "00" & x"248" => data <= x"00";
when "00" & x"249" => data <= x"00";
when "00" & x"24a" => data <= x"00";
when "00" & x"24b" => data <= x"00";
when "00" & x"24c" => data <= x"00";
when "00" & x"24d" => data <= x"00";
when "00" & x"24e" => data <= x"00";
when "00" & x"24f" => data <= x"00";
when "00" & x"250" => data <= x"00";
when "00" & x"251" => data <= x"00";
when "00" & x"252" => data <= x"00";
when "00" & x"253" => data <= x"00";
when "00" & x"254" => data <= x"00";
when "00" & x"255" => data <= x"00";
when "00" & x"256" => data <= x"00";
when "00" & x"257" => data <= x"00";
when "00" & x"258" => data <= x"00";
when "00" & x"259" => data <= x"00";
when "00" & x"25a" => data <= x"00";
when "00" & x"25b" => data <= x"00";
when "00" & x"25c" => data <= x"00";
when "00" & x"25d" => data <= x"60";
when "00" & x"25e" => data <= x"a9";
when "00" & x"25f" => data <= x"23";
when "00" & x"260" => data <= x"d0";
when "00" & x"261" => data <= x"02";
when "00" & x"262" => data <= x"a9";
when "00" & x"263" => data <= x"ff";
when "00" & x"264" => data <= x"8d";
when "00" & x"265" => data <= x"cf";
when "00" & x"266" => data <= x"10";
when "00" & x"267" => data <= x"60";
when "00" & x"268" => data <= x"20";
when "00" & x"269" => data <= x"fe";
when "00" & x"26a" => data <= x"80";
when "00" & x"26b" => data <= x"4c";
when "00" & x"26c" => data <= x"71";
when "00" & x"26d" => data <= x"82";
when "00" & x"26e" => data <= x"20";
when "00" & x"26f" => data <= x"06";
when "00" & x"270" => data <= x"81";
when "00" & x"271" => data <= x"20";
when "00" & x"272" => data <= x"96";
when "00" & x"273" => data <= x"82";
when "00" & x"274" => data <= x"b0";
when "00" & x"275" => data <= x"e7";
when "00" & x"276" => data <= x"20";
when "00" & x"277" => data <= x"2b";
when "00" & x"278" => data <= x"80";
when "00" & x"279" => data <= x"d6";
when "00" & x"27a" => data <= x"6e";
when "00" & x"27b" => data <= x"6f";
when "00" & x"27c" => data <= x"74";
when "00" & x"27d" => data <= x"20";
when "00" & x"27e" => data <= x"66";
when "00" & x"27f" => data <= x"6f";
when "00" & x"280" => data <= x"75";
when "00" & x"281" => data <= x"6e";
when "00" & x"282" => data <= x"64";
when "00" & x"283" => data <= x"00";
when "00" & x"284" => data <= x"20";
when "00" & x"285" => data <= x"5e";
when "00" & x"286" => data <= x"82";
when "00" & x"287" => data <= x"20";
when "00" & x"288" => data <= x"01";
when "00" & x"289" => data <= x"9a";
when "00" & x"28a" => data <= x"20";
when "00" & x"28b" => data <= x"68";
when "00" & x"28c" => data <= x"82";
when "00" & x"28d" => data <= x"20";
when "00" & x"28e" => data <= x"01";
when "00" & x"28f" => data <= x"83";
when "00" & x"290" => data <= x"20";
when "00" & x"291" => data <= x"9d";
when "00" & x"292" => data <= x"82";
when "00" & x"293" => data <= x"b0";
when "00" & x"294" => data <= x"f8";
when "00" & x"295" => data <= x"60";
when "00" & x"296" => data <= x"20";
when "00" & x"297" => data <= x"41";
when "00" & x"298" => data <= x"af";
when "00" & x"299" => data <= x"a0";
when "00" & x"29a" => data <= x"f8";
when "00" & x"29b" => data <= x"d0";
when "00" & x"29c" => data <= x"03";
when "00" & x"29d" => data <= x"ac";
when "00" & x"29e" => data <= x"ce";
when "00" & x"29f" => data <= x"10";
when "00" & x"2a0" => data <= x"20";
when "00" & x"2a1" => data <= x"10";
when "00" & x"2a2" => data <= x"82";
when "00" & x"2a3" => data <= x"cc";
when "00" & x"2a4" => data <= x"05";
when "00" & x"2a5" => data <= x"0f";
when "00" & x"2a6" => data <= x"b0";
when "00" & x"2a7" => data <= x"44";
when "00" & x"2a8" => data <= x"20";
when "00" & x"2a9" => data <= x"10";
when "00" & x"2aa" => data <= x"82";
when "00" & x"2ab" => data <= x"a2";
when "00" & x"2ac" => data <= x"07";
when "00" & x"2ad" => data <= x"b5";
when "00" & x"2ae" => data <= x"c7";
when "00" & x"2af" => data <= x"cd";
when "00" & x"2b0" => data <= x"cf";
when "00" & x"2b1" => data <= x"10";
when "00" & x"2b2" => data <= x"f0";
when "00" & x"2b3" => data <= x"0e";
when "00" & x"2b4" => data <= x"20";
when "00" & x"2b5" => data <= x"ee";
when "00" & x"2b6" => data <= x"82";
when "00" & x"2b7" => data <= x"59";
when "00" & x"2b8" => data <= x"07";
when "00" & x"2b9" => data <= x"0e";
when "00" & x"2ba" => data <= x"b0";
when "00" & x"2bb" => data <= x"02";
when "00" & x"2bc" => data <= x"29";
when "00" & x"2bd" => data <= x"df";
when "00" & x"2be" => data <= x"29";
when "00" & x"2bf" => data <= x"7f";
when "00" & x"2c0" => data <= x"d0";
when "00" & x"2c1" => data <= x"09";
when "00" & x"2c2" => data <= x"88";
when "00" & x"2c3" => data <= x"ca";
when "00" & x"2c4" => data <= x"10";
when "00" & x"2c5" => data <= x"e7";
when "00" & x"2c6" => data <= x"8c";
when "00" & x"2c7" => data <= x"ce";
when "00" & x"2c8" => data <= x"10";
when "00" & x"2c9" => data <= x"38";
when "00" & x"2ca" => data <= x"60";
when "00" & x"2cb" => data <= x"88";
when "00" & x"2cc" => data <= x"ca";
when "00" & x"2cd" => data <= x"10";
when "00" & x"2ce" => data <= x"fc";
when "00" & x"2cf" => data <= x"30";
when "00" & x"2d0" => data <= x"cf";
when "00" & x"2d1" => data <= x"20";
when "00" & x"2d2" => data <= x"4c";
when "00" & x"2d3" => data <= x"98";
when "00" & x"2d4" => data <= x"b9";
when "00" & x"2d5" => data <= x"10";
when "00" & x"2d6" => data <= x"0e";
when "00" & x"2d7" => data <= x"99";
when "00" & x"2d8" => data <= x"08";
when "00" & x"2d9" => data <= x"0e";
when "00" & x"2da" => data <= x"b9";
when "00" & x"2db" => data <= x"10";
when "00" & x"2dc" => data <= x"0f";
when "00" & x"2dd" => data <= x"99";
when "00" & x"2de" => data <= x"08";
when "00" & x"2df" => data <= x"0f";
when "00" & x"2e0" => data <= x"c8";
when "00" & x"2e1" => data <= x"cc";
when "00" & x"2e2" => data <= x"05";
when "00" & x"2e3" => data <= x"0f";
when "00" & x"2e4" => data <= x"90";
when "00" & x"2e5" => data <= x"ee";
when "00" & x"2e6" => data <= x"98";
when "00" & x"2e7" => data <= x"e9";
when "00" & x"2e8" => data <= x"08";
when "00" & x"2e9" => data <= x"8d";
when "00" & x"2ea" => data <= x"05";
when "00" & x"2eb" => data <= x"0f";
when "00" & x"2ec" => data <= x"18";
when "00" & x"2ed" => data <= x"60";
when "00" & x"2ee" => data <= x"48";
when "00" & x"2ef" => data <= x"29";
when "00" & x"2f0" => data <= x"df";
when "00" & x"2f1" => data <= x"c9";
when "00" & x"2f2" => data <= x"41";
when "00" & x"2f3" => data <= x"90";
when "00" & x"2f4" => data <= x"04";
when "00" & x"2f5" => data <= x"c9";
when "00" & x"2f6" => data <= x"5b";
when "00" & x"2f7" => data <= x"90";
when "00" & x"2f8" => data <= x"01";
when "00" & x"2f9" => data <= x"38";
when "00" & x"2fa" => data <= x"68";
when "00" & x"2fb" => data <= x"60";
when "00" & x"2fc" => data <= x"2c";
when "00" & x"2fd" => data <= x"c7";
when "00" & x"2fe" => data <= x"10";
when "00" & x"2ff" => data <= x"30";
when "00" & x"300" => data <= x"ec";
when "00" & x"301" => data <= x"20";
when "00" & x"302" => data <= x"e1";
when "00" & x"303" => data <= x"83";
when "00" & x"304" => data <= x"20";
when "00" & x"305" => data <= x"c0";
when "00" & x"306" => data <= x"81";
when "00" & x"307" => data <= x"98";
when "00" & x"308" => data <= x"48";
when "00" & x"309" => data <= x"a9";
when "00" & x"30a" => data <= x"60";
when "00" & x"30b" => data <= x"85";
when "00" & x"30c" => data <= x"b0";
when "00" & x"30d" => data <= x"a9";
when "00" & x"30e" => data <= x"10";
when "00" & x"30f" => data <= x"85";
when "00" & x"310" => data <= x"b1";
when "00" & x"311" => data <= x"20";
when "00" & x"312" => data <= x"7e";
when "00" & x"313" => data <= x"83";
when "00" & x"314" => data <= x"a0";
when "00" & x"315" => data <= x"02";
when "00" & x"316" => data <= x"20";
when "00" & x"317" => data <= x"ce";
when "00" & x"318" => data <= x"9f";
when "00" & x"319" => data <= x"20";
when "00" & x"31a" => data <= x"35";
when "00" & x"31b" => data <= x"83";
when "00" & x"31c" => data <= x"20";
when "00" & x"31d" => data <= x"35";
when "00" & x"31e" => data <= x"83";
when "00" & x"31f" => data <= x"20";
when "00" & x"320" => data <= x"35";
when "00" & x"321" => data <= x"83";
when "00" & x"322" => data <= x"68";
when "00" & x"323" => data <= x"a8";
when "00" & x"324" => data <= x"b9";
when "00" & x"325" => data <= x"0e";
when "00" & x"326" => data <= x"0f";
when "00" & x"327" => data <= x"29";
when "00" & x"328" => data <= x"03";
when "00" & x"329" => data <= x"20";
when "00" & x"32a" => data <= x"ca";
when "00" & x"32b" => data <= x"80";
when "00" & x"32c" => data <= x"b9";
when "00" & x"32d" => data <= x"0f";
when "00" & x"32e" => data <= x"0f";
when "00" & x"32f" => data <= x"20";
when "00" & x"330" => data <= x"c2";
when "00" & x"331" => data <= x"80";
when "00" & x"332" => data <= x"4c";
when "00" & x"333" => data <= x"9a";
when "00" & x"334" => data <= x"9f";
when "00" & x"335" => data <= x"a2";
when "00" & x"336" => data <= x"03";
when "00" & x"337" => data <= x"b9";
when "00" & x"338" => data <= x"62";
when "00" & x"339" => data <= x"10";
when "00" & x"33a" => data <= x"20";
when "00" & x"33b" => data <= x"c2";
when "00" & x"33c" => data <= x"80";
when "00" & x"33d" => data <= x"88";
when "00" & x"33e" => data <= x"ca";
when "00" & x"33f" => data <= x"d0";
when "00" & x"340" => data <= x"f6";
when "00" & x"341" => data <= x"20";
when "00" & x"342" => data <= x"11";
when "00" & x"343" => data <= x"82";
when "00" & x"344" => data <= x"4c";
when "00" & x"345" => data <= x"ce";
when "00" & x"346" => data <= x"9f";
when "00" & x"347" => data <= x"20";
when "00" & x"348" => data <= x"e1";
when "00" & x"349" => data <= x"83";
when "00" & x"34a" => data <= x"4c";
when "00" & x"34b" => data <= x"41";
when "00" & x"34c" => data <= x"af";
when "00" & x"34d" => data <= x"ad";
when "00" & x"34e" => data <= x"ca";
when "00" & x"34f" => data <= x"10";
when "00" & x"350" => data <= x"85";
when "00" & x"351" => data <= x"ce";
when "00" & x"352" => data <= x"ad";
when "00" & x"353" => data <= x"cb";
when "00" & x"354" => data <= x"10";
when "00" & x"355" => data <= x"4c";
when "00" & x"356" => data <= x"7e";
when "00" & x"357" => data <= x"87";
when "00" & x"358" => data <= x"20";
when "00" & x"359" => data <= x"bf";
when "00" & x"35a" => data <= x"86";
when "00" & x"35b" => data <= x"f0";
when "00" & x"35c" => data <= x"f5";
when "00" & x"35d" => data <= x"20";
when "00" & x"35e" => data <= x"c5";
when "00" & x"35f" => data <= x"ff";
when "00" & x"360" => data <= x"b0";
when "00" & x"361" => data <= x"12";
when "00" & x"362" => data <= x"c9";
when "00" & x"363" => data <= x"3a";
when "00" & x"364" => data <= x"f0";
when "00" & x"365" => data <= x"f7";
when "00" & x"366" => data <= x"38";
when "00" & x"367" => data <= x"e9";
when "00" & x"368" => data <= x"30";
when "00" & x"369" => data <= x"90";
when "00" & x"36a" => data <= x"09";
when "00" & x"36b" => data <= x"c9";
when "00" & x"36c" => data <= x"04";
when "00" & x"36d" => data <= x"b0";
when "00" & x"36e" => data <= x"05";
when "00" & x"36f" => data <= x"20";
when "00" & x"370" => data <= x"7e";
when "00" & x"371" => data <= x"87";
when "00" & x"372" => data <= x"18";
when "00" & x"373" => data <= x"60";
when "00" & x"374" => data <= x"20";
when "00" & x"375" => data <= x"22";
when "00" & x"376" => data <= x"80";
when "00" & x"377" => data <= x"cd";
when "00" & x"378" => data <= x"64";
when "00" & x"379" => data <= x"72";
when "00" & x"37a" => data <= x"69";
when "00" & x"37b" => data <= x"76";
when "00" & x"37c" => data <= x"65";
when "00" & x"37d" => data <= x"00";
when "00" & x"37e" => data <= x"20";
when "00" & x"37f" => data <= x"e1";
when "00" & x"380" => data <= x"83";
when "00" & x"381" => data <= x"98";
when "00" & x"382" => data <= x"48";
when "00" & x"383" => data <= x"aa";
when "00" & x"384" => data <= x"a0";
when "00" & x"385" => data <= x"02";
when "00" & x"386" => data <= x"a9";
when "00" & x"387" => data <= x"00";
when "00" & x"388" => data <= x"91";
when "00" & x"389" => data <= x"b0";
when "00" & x"38a" => data <= x"c8";
when "00" & x"38b" => data <= x"c0";
when "00" & x"38c" => data <= x"12";
when "00" & x"38d" => data <= x"d0";
when "00" & x"38e" => data <= x"f9";
when "00" & x"38f" => data <= x"a0";
when "00" & x"390" => data <= x"02";
when "00" & x"391" => data <= x"20";
when "00" & x"392" => data <= x"cf";
when "00" & x"393" => data <= x"83";
when "00" & x"394" => data <= x"c8";
when "00" & x"395" => data <= x"c8";
when "00" & x"396" => data <= x"c0";
when "00" & x"397" => data <= x"0e";
when "00" & x"398" => data <= x"d0";
when "00" & x"399" => data <= x"f7";
when "00" & x"39a" => data <= x"68";
when "00" & x"39b" => data <= x"aa";
when "00" & x"39c" => data <= x"bd";
when "00" & x"39d" => data <= x"0f";
when "00" & x"39e" => data <= x"0e";
when "00" & x"39f" => data <= x"10";
when "00" & x"3a0" => data <= x"06";
when "00" & x"3a1" => data <= x"a9";
when "00" & x"3a2" => data <= x"0a";
when "00" & x"3a3" => data <= x"a0";
when "00" & x"3a4" => data <= x"0e";
when "00" & x"3a5" => data <= x"91";
when "00" & x"3a6" => data <= x"b0";
when "00" & x"3a7" => data <= x"bd";
when "00" & x"3a8" => data <= x"0e";
when "00" & x"3a9" => data <= x"0f";
when "00" & x"3aa" => data <= x"a0";
when "00" & x"3ab" => data <= x"04";
when "00" & x"3ac" => data <= x"20";
when "00" & x"3ad" => data <= x"bb";
when "00" & x"3ae" => data <= x"83";
when "00" & x"3af" => data <= x"a0";
when "00" & x"3b0" => data <= x"0c";
when "00" & x"3b1" => data <= x"4a";
when "00" & x"3b2" => data <= x"4a";
when "00" & x"3b3" => data <= x"48";
when "00" & x"3b4" => data <= x"29";
when "00" & x"3b5" => data <= x"03";
when "00" & x"3b6" => data <= x"91";
when "00" & x"3b7" => data <= x"b0";
when "00" & x"3b8" => data <= x"68";
when "00" & x"3b9" => data <= x"a0";
when "00" & x"3ba" => data <= x"08";
when "00" & x"3bb" => data <= x"4a";
when "00" & x"3bc" => data <= x"4a";
when "00" & x"3bd" => data <= x"48";
when "00" & x"3be" => data <= x"29";
when "00" & x"3bf" => data <= x"03";
when "00" & x"3c0" => data <= x"91";
when "00" & x"3c1" => data <= x"b0";
when "00" & x"3c2" => data <= x"c9";
when "00" & x"3c3" => data <= x"03";
when "00" & x"3c4" => data <= x"d0";
when "00" & x"3c5" => data <= x"07";
when "00" & x"3c6" => data <= x"a9";
when "00" & x"3c7" => data <= x"ff";
when "00" & x"3c8" => data <= x"91";
when "00" & x"3c9" => data <= x"b0";
when "00" & x"3ca" => data <= x"c8";
when "00" & x"3cb" => data <= x"91";
when "00" & x"3cc" => data <= x"b0";
when "00" & x"3cd" => data <= x"68";
when "00" & x"3ce" => data <= x"60";
when "00" & x"3cf" => data <= x"20";
when "00" & x"3d0" => data <= x"d2";
when "00" & x"3d1" => data <= x"83";
when "00" & x"3d2" => data <= x"bd";
when "00" & x"3d3" => data <= x"08";
when "00" & x"3d4" => data <= x"0f";
when "00" & x"3d5" => data <= x"91";
when "00" & x"3d6" => data <= x"b0";
when "00" & x"3d7" => data <= x"e8";
when "00" & x"3d8" => data <= x"c8";
when "00" & x"3d9" => data <= x"60";
when "00" & x"3da" => data <= x"e6";
when "00" & x"3db" => data <= x"ae";
when "00" & x"3dc" => data <= x"d0";
when "00" & x"3dd" => data <= x"02";
when "00" & x"3de" => data <= x"e6";
when "00" & x"3df" => data <= x"af";
when "00" & x"3e0" => data <= x"60";
when "00" & x"3e1" => data <= x"48";
when "00" & x"3e2" => data <= x"8a";
when "00" & x"3e3" => data <= x"48";
when "00" & x"3e4" => data <= x"98";
when "00" & x"3e5" => data <= x"48";
when "00" & x"3e6" => data <= x"a9";
when "00" & x"3e7" => data <= x"84";
when "00" & x"3e8" => data <= x"48";
when "00" & x"3e9" => data <= x"a9";
when "00" & x"3ea" => data <= x"03";
when "00" & x"3eb" => data <= x"48";
when "00" & x"3ec" => data <= x"a0";
when "00" & x"3ed" => data <= x"05";
when "00" & x"3ee" => data <= x"ba";
when "00" & x"3ef" => data <= x"bd";
when "00" & x"3f0" => data <= x"07";
when "00" & x"3f1" => data <= x"01";
when "00" & x"3f2" => data <= x"48";
when "00" & x"3f3" => data <= x"88";
when "00" & x"3f4" => data <= x"d0";
when "00" & x"3f5" => data <= x"f8";
when "00" & x"3f6" => data <= x"a0";
when "00" & x"3f7" => data <= x"0a";
when "00" & x"3f8" => data <= x"bd";
when "00" & x"3f9" => data <= x"09";
when "00" & x"3fa" => data <= x"01";
when "00" & x"3fb" => data <= x"9d";
when "00" & x"3fc" => data <= x"0b";
when "00" & x"3fd" => data <= x"01";
when "00" & x"3fe" => data <= x"ca";
when "00" & x"3ff" => data <= x"88";
when "00" & x"400" => data <= x"d0";
when "00" & x"401" => data <= x"f6";
when "00" & x"402" => data <= x"68";
when "00" & x"403" => data <= x"68";
when "00" & x"404" => data <= x"68";
when "00" & x"405" => data <= x"a8";
when "00" & x"406" => data <= x"68";
when "00" & x"407" => data <= x"aa";
when "00" & x"408" => data <= x"68";
when "00" & x"409" => data <= x"60";
when "00" & x"40a" => data <= x"ba";
when "00" & x"40b" => data <= x"9d";
when "00" & x"40c" => data <= x"03";
when "00" & x"40d" => data <= x"01";
when "00" & x"40e" => data <= x"4c";
when "00" & x"40f" => data <= x"04";
when "00" & x"410" => data <= x"84";
when "00" & x"411" => data <= x"48";
when "00" & x"412" => data <= x"8a";
when "00" & x"413" => data <= x"48";
when "00" & x"414" => data <= x"98";
when "00" & x"415" => data <= x"48";
when "00" & x"416" => data <= x"a9";
when "00" & x"417" => data <= x"84";
when "00" & x"418" => data <= x"48";
when "00" & x"419" => data <= x"a9";
when "00" & x"41a" => data <= x"09";
when "00" & x"41b" => data <= x"48";
when "00" & x"41c" => data <= x"d0";
when "00" & x"41d" => data <= x"ce";
when "00" & x"41e" => data <= x"20";
when "00" & x"41f" => data <= x"b8";
when "00" & x"420" => data <= x"86";
when "00" & x"421" => data <= x"20";
when "00" & x"422" => data <= x"3b";
when "00" & x"423" => data <= x"af";
when "00" & x"424" => data <= x"a0";
when "00" & x"425" => data <= x"ff";
when "00" & x"426" => data <= x"84";
when "00" & x"427" => data <= x"a8";
when "00" & x"428" => data <= x"c8";
when "00" & x"429" => data <= x"84";
when "00" & x"42a" => data <= x"aa";
when "00" & x"42b" => data <= x"b9";
when "00" & x"42c" => data <= x"00";
when "00" & x"42d" => data <= x"0e";
when "00" & x"42e" => data <= x"c0";
when "00" & x"42f" => data <= x"08";
when "00" & x"430" => data <= x"90";
when "00" & x"431" => data <= x"03";
when "00" & x"432" => data <= x"b9";
when "00" & x"433" => data <= x"f8";
when "00" & x"434" => data <= x"0e";
when "00" & x"435" => data <= x"20";
when "00" & x"436" => data <= x"9c";
when "00" & x"437" => data <= x"80";
when "00" & x"438" => data <= x"c8";
when "00" & x"439" => data <= x"c0";
when "00" & x"43a" => data <= x"0c";
when "00" & x"43b" => data <= x"d0";
when "00" & x"43c" => data <= x"ee";
when "00" & x"43d" => data <= x"20";
when "00" & x"43e" => data <= x"65";
when "00" & x"43f" => data <= x"80";
when "00" & x"440" => data <= x"20";
when "00" & x"441" => data <= x"28";
when "00" & x"442" => data <= x"ad";
when "00" & x"443" => data <= x"04";
when "00" & x"444" => data <= x"0f";
when "00" & x"445" => data <= x"20";
when "00" & x"446" => data <= x"c2";
when "00" & x"447" => data <= x"80";
when "00" & x"448" => data <= x"20";
when "00" & x"449" => data <= x"65";
when "00" & x"44a" => data <= x"80";
when "00" & x"44b" => data <= x"29";
when "00" & x"44c" => data <= x"0d";
when "00" & x"44d" => data <= x"44";
when "00" & x"44e" => data <= x"72";
when "00" & x"44f" => data <= x"69";
when "00" & x"450" => data <= x"76";
when "00" & x"451" => data <= x"65";
when "00" & x"452" => data <= x"20";
when "00" & x"453" => data <= x"a5";
when "00" & x"454" => data <= x"cf";
when "00" & x"455" => data <= x"20";
when "00" & x"456" => data <= x"ca";
when "00" & x"457" => data <= x"80";
when "00" & x"458" => data <= x"a0";
when "00" & x"459" => data <= x"0d";
when "00" & x"45a" => data <= x"20";
when "00" & x"45b" => data <= x"f4";
when "00" & x"45c" => data <= x"81";
when "00" & x"45d" => data <= x"20";
when "00" & x"45e" => data <= x"65";
when "00" & x"45f" => data <= x"80";
when "00" & x"460" => data <= x"4f";
when "00" & x"461" => data <= x"70";
when "00" & x"462" => data <= x"74";
when "00" & x"463" => data <= x"69";
when "00" & x"464" => data <= x"6f";
when "00" & x"465" => data <= x"6e";
when "00" & x"466" => data <= x"20";
when "00" & x"467" => data <= x"ad";
when "00" & x"468" => data <= x"06";
when "00" & x"469" => data <= x"0f";
when "00" & x"46a" => data <= x"20";
when "00" & x"46b" => data <= x"05";
when "00" & x"46c" => data <= x"82";
when "00" & x"46d" => data <= x"20";
when "00" & x"46e" => data <= x"ca";
when "00" & x"46f" => data <= x"80";
when "00" & x"470" => data <= x"20";
when "00" & x"471" => data <= x"65";
when "00" & x"472" => data <= x"80";
when "00" & x"473" => data <= x"20";
when "00" & x"474" => data <= x"28";
when "00" & x"475" => data <= x"a0";
when "00" & x"476" => data <= x"03";
when "00" & x"477" => data <= x"0a";
when "00" & x"478" => data <= x"0a";
when "00" & x"479" => data <= x"aa";
when "00" & x"47a" => data <= x"bd";
when "00" & x"47b" => data <= x"6f";
when "00" & x"47c" => data <= x"85";
when "00" & x"47d" => data <= x"20";
when "00" & x"47e" => data <= x"9c";
when "00" & x"47f" => data <= x"80";
when "00" & x"480" => data <= x"e8";
when "00" & x"481" => data <= x"88";
when "00" & x"482" => data <= x"10";
when "00" & x"483" => data <= x"f6";
when "00" & x"484" => data <= x"20";
when "00" & x"485" => data <= x"65";
when "00" & x"486" => data <= x"80";
when "00" & x"487" => data <= x"29";
when "00" & x"488" => data <= x"0d";
when "00" & x"489" => data <= x"44";
when "00" & x"48a" => data <= x"69";
when "00" & x"48b" => data <= x"72";
when "00" & x"48c" => data <= x"65";
when "00" & x"48d" => data <= x"63";
when "00" & x"48e" => data <= x"74";
when "00" & x"48f" => data <= x"6f";
when "00" & x"490" => data <= x"72";
when "00" & x"491" => data <= x"79";
when "00" & x"492" => data <= x"20";
when "00" & x"493" => data <= x"3a";
when "00" & x"494" => data <= x"ad";
when "00" & x"495" => data <= x"cb";
when "00" & x"496" => data <= x"10";
when "00" & x"497" => data <= x"20";
when "00" & x"498" => data <= x"ca";
when "00" & x"499" => data <= x"80";
when "00" & x"49a" => data <= x"20";
when "00" & x"49b" => data <= x"9a";
when "00" & x"49c" => data <= x"80";
when "00" & x"49d" => data <= x"ad";
when "00" & x"49e" => data <= x"ca";
when "00" & x"49f" => data <= x"10";
when "00" & x"4a0" => data <= x"20";
when "00" & x"4a1" => data <= x"9c";
when "00" & x"4a2" => data <= x"80";
when "00" & x"4a3" => data <= x"a0";
when "00" & x"4a4" => data <= x"06";
when "00" & x"4a5" => data <= x"20";
when "00" & x"4a6" => data <= x"f4";
when "00" & x"4a7" => data <= x"81";
when "00" & x"4a8" => data <= x"20";
when "00" & x"4a9" => data <= x"65";
when "00" & x"4aa" => data <= x"80";
when "00" & x"4ab" => data <= x"4c";
when "00" & x"4ac" => data <= x"69";
when "00" & x"4ad" => data <= x"62";
when "00" & x"4ae" => data <= x"72";
when "00" & x"4af" => data <= x"61";
when "00" & x"4b0" => data <= x"72";
when "00" & x"4b1" => data <= x"79";
when "00" & x"4b2" => data <= x"20";
when "00" & x"4b3" => data <= x"3a";
when "00" & x"4b4" => data <= x"ad";
when "00" & x"4b5" => data <= x"cd";
when "00" & x"4b6" => data <= x"10";
when "00" & x"4b7" => data <= x"20";
when "00" & x"4b8" => data <= x"ca";
when "00" & x"4b9" => data <= x"80";
when "00" & x"4ba" => data <= x"20";
when "00" & x"4bb" => data <= x"9a";
when "00" & x"4bc" => data <= x"80";
when "00" & x"4bd" => data <= x"ad";
when "00" & x"4be" => data <= x"cc";
when "00" & x"4bf" => data <= x"10";
when "00" & x"4c0" => data <= x"20";
when "00" & x"4c1" => data <= x"9c";
when "00" & x"4c2" => data <= x"80";
when "00" & x"4c3" => data <= x"20";
when "00" & x"4c4" => data <= x"9a";
when "00" & x"4c5" => data <= x"9f";
when "00" & x"4c6" => data <= x"a0";
when "00" & x"4c7" => data <= x"00";
when "00" & x"4c8" => data <= x"cc";
when "00" & x"4c9" => data <= x"05";
when "00" & x"4ca" => data <= x"0f";
when "00" & x"4cb" => data <= x"b0";
when "00" & x"4cc" => data <= x"17";
when "00" & x"4cd" => data <= x"b9";
when "00" & x"4ce" => data <= x"0f";
when "00" & x"4cf" => data <= x"0e";
when "00" & x"4d0" => data <= x"4d";
when "00" & x"4d1" => data <= x"ca";
when "00" & x"4d2" => data <= x"10";
when "00" & x"4d3" => data <= x"29";
when "00" & x"4d4" => data <= x"7f";
when "00" & x"4d5" => data <= x"d0";
when "00" & x"4d6" => data <= x"08";
when "00" & x"4d7" => data <= x"b9";
when "00" & x"4d8" => data <= x"0f";
when "00" & x"4d9" => data <= x"0e";
when "00" & x"4da" => data <= x"29";
when "00" & x"4db" => data <= x"80";
when "00" & x"4dc" => data <= x"99";
when "00" & x"4dd" => data <= x"0f";
when "00" & x"4de" => data <= x"0e";
when "00" & x"4df" => data <= x"20";
when "00" & x"4e0" => data <= x"10";
when "00" & x"4e1" => data <= x"82";
when "00" & x"4e2" => data <= x"90";
when "00" & x"4e3" => data <= x"e4";
when "00" & x"4e4" => data <= x"a0";
when "00" & x"4e5" => data <= x"00";
when "00" & x"4e6" => data <= x"20";
when "00" & x"4e7" => data <= x"f6";
when "00" & x"4e8" => data <= x"84";
when "00" & x"4e9" => data <= x"90";
when "00" & x"4ea" => data <= x"16";
when "00" & x"4eb" => data <= x"a9";
when "00" & x"4ec" => data <= x"ff";
when "00" & x"4ed" => data <= x"8d";
when "00" & x"4ee" => data <= x"82";
when "00" & x"4ef" => data <= x"10";
when "00" & x"4f0" => data <= x"4c";
when "00" & x"4f1" => data <= x"9a";
when "00" & x"4f2" => data <= x"9f";
when "00" & x"4f3" => data <= x"20";
when "00" & x"4f4" => data <= x"10";
when "00" & x"4f5" => data <= x"82";
when "00" & x"4f6" => data <= x"cc";
when "00" & x"4f7" => data <= x"05";
when "00" & x"4f8" => data <= x"0f";
when "00" & x"4f9" => data <= x"b0";
when "00" & x"4fa" => data <= x"05";
when "00" & x"4fb" => data <= x"b9";
when "00" & x"4fc" => data <= x"08";
when "00" & x"4fd" => data <= x"0e";
when "00" & x"4fe" => data <= x"30";
when "00" & x"4ff" => data <= x"f3";
when "00" & x"500" => data <= x"60";
when "00" & x"501" => data <= x"84";
when "00" & x"502" => data <= x"ab";
when "00" & x"503" => data <= x"a2";
when "00" & x"504" => data <= x"00";
when "00" & x"505" => data <= x"b9";
when "00" & x"506" => data <= x"08";
when "00" & x"507" => data <= x"0e";
when "00" & x"508" => data <= x"29";
when "00" & x"509" => data <= x"7f";
when "00" & x"50a" => data <= x"9d";
when "00" & x"50b" => data <= x"60";
when "00" & x"50c" => data <= x"10";
when "00" & x"50d" => data <= x"c8";
when "00" & x"50e" => data <= x"e8";
when "00" & x"50f" => data <= x"e0";
when "00" & x"510" => data <= x"08";
when "00" & x"511" => data <= x"d0";
when "00" & x"512" => data <= x"f2";
when "00" & x"513" => data <= x"20";
when "00" & x"514" => data <= x"f6";
when "00" & x"515" => data <= x"84";
when "00" & x"516" => data <= x"b0";
when "00" & x"517" => data <= x"1f";
when "00" & x"518" => data <= x"38";
when "00" & x"519" => data <= x"a2";
when "00" & x"51a" => data <= x"06";
when "00" & x"51b" => data <= x"b9";
when "00" & x"51c" => data <= x"0e";
when "00" & x"51d" => data <= x"0e";
when "00" & x"51e" => data <= x"fd";
when "00" & x"51f" => data <= x"60";
when "00" & x"520" => data <= x"10";
when "00" & x"521" => data <= x"88";
when "00" & x"522" => data <= x"ca";
when "00" & x"523" => data <= x"10";
when "00" & x"524" => data <= x"f6";
when "00" & x"525" => data <= x"20";
when "00" & x"526" => data <= x"11";
when "00" & x"527" => data <= x"82";
when "00" & x"528" => data <= x"b9";
when "00" & x"529" => data <= x"0f";
when "00" & x"52a" => data <= x"0e";
when "00" & x"52b" => data <= x"29";
when "00" & x"52c" => data <= x"7f";
when "00" & x"52d" => data <= x"ed";
when "00" & x"52e" => data <= x"67";
when "00" & x"52f" => data <= x"10";
when "00" & x"530" => data <= x"90";
when "00" & x"531" => data <= x"cf";
when "00" & x"532" => data <= x"20";
when "00" & x"533" => data <= x"10";
when "00" & x"534" => data <= x"82";
when "00" & x"535" => data <= x"b0";
when "00" & x"536" => data <= x"dc";
when "00" & x"537" => data <= x"a4";
when "00" & x"538" => data <= x"ab";
when "00" & x"539" => data <= x"b9";
when "00" & x"53a" => data <= x"08";
when "00" & x"53b" => data <= x"0e";
when "00" & x"53c" => data <= x"09";
when "00" & x"53d" => data <= x"80";
when "00" & x"53e" => data <= x"99";
when "00" & x"53f" => data <= x"08";
when "00" & x"540" => data <= x"0e";
when "00" & x"541" => data <= x"ad";
when "00" & x"542" => data <= x"67";
when "00" & x"543" => data <= x"10";
when "00" & x"544" => data <= x"c5";
when "00" & x"545" => data <= x"aa";
when "00" & x"546" => data <= x"f0";
when "00" & x"547" => data <= x"10";
when "00" & x"548" => data <= x"a6";
when "00" & x"549" => data <= x"aa";
when "00" & x"54a" => data <= x"85";
when "00" & x"54b" => data <= x"aa";
when "00" & x"54c" => data <= x"d0";
when "00" & x"54d" => data <= x"0a";
when "00" & x"54e" => data <= x"20";
when "00" & x"54f" => data <= x"9a";
when "00" & x"550" => data <= x"9f";
when "00" & x"551" => data <= x"20";
when "00" & x"552" => data <= x"9a";
when "00" & x"553" => data <= x"9f";
when "00" & x"554" => data <= x"a0";
when "00" & x"555" => data <= x"ff";
when "00" & x"556" => data <= x"d0";
when "00" & x"557" => data <= x"09";
when "00" & x"558" => data <= x"a4";
when "00" & x"559" => data <= x"a8";
when "00" & x"55a" => data <= x"d0";
when "00" & x"55b" => data <= x"f5";
when "00" & x"55c" => data <= x"a0";
when "00" & x"55d" => data <= x"05";
when "00" & x"55e" => data <= x"20";
when "00" & x"55f" => data <= x"f4";
when "00" & x"560" => data <= x"81";
when "00" & x"561" => data <= x"c8";
when "00" & x"562" => data <= x"84";
when "00" & x"563" => data <= x"a8";
when "00" & x"564" => data <= x"a4";
when "00" & x"565" => data <= x"ab";
when "00" & x"566" => data <= x"20";
when "00" & x"567" => data <= x"cb";
when "00" & x"568" => data <= x"9f";
when "00" & x"569" => data <= x"20";
when "00" & x"56a" => data <= x"c0";
when "00" & x"56b" => data <= x"81";
when "00" & x"56c" => data <= x"4c";
when "00" & x"56d" => data <= x"e4";
when "00" & x"56e" => data <= x"84";
when "00" & x"56f" => data <= x"6f";
when "00" & x"570" => data <= x"66";
when "00" & x"571" => data <= x"66";
when "00" & x"572" => data <= x"00";
when "00" & x"573" => data <= x"4c";
when "00" & x"574" => data <= x"4f";
when "00" & x"575" => data <= x"41";
when "00" & x"576" => data <= x"44";
when "00" & x"577" => data <= x"52";
when "00" & x"578" => data <= x"55";
when "00" & x"579" => data <= x"4e";
when "00" & x"57a" => data <= x"00";
when "00" & x"57b" => data <= x"45";
when "00" & x"57c" => data <= x"58";
when "00" & x"57d" => data <= x"45";
when "00" & x"57e" => data <= x"43";
when "00" & x"57f" => data <= x"b9";
when "00" & x"580" => data <= x"0e";
when "00" & x"581" => data <= x"0f";
when "00" & x"582" => data <= x"20";
when "00" & x"583" => data <= x"fd";
when "00" & x"584" => data <= x"81";
when "00" & x"585" => data <= x"85";
when "00" & x"586" => data <= x"c4";
when "00" & x"587" => data <= x"18";
when "00" & x"588" => data <= x"a9";
when "00" & x"589" => data <= x"ff";
when "00" & x"58a" => data <= x"79";
when "00" & x"58b" => data <= x"0c";
when "00" & x"58c" => data <= x"0f";
when "00" & x"58d" => data <= x"b9";
when "00" & x"58e" => data <= x"0f";
when "00" & x"58f" => data <= x"0f";
when "00" & x"590" => data <= x"79";
when "00" & x"591" => data <= x"0d";
when "00" & x"592" => data <= x"0f";
when "00" & x"593" => data <= x"85";
when "00" & x"594" => data <= x"c5";
when "00" & x"595" => data <= x"b9";
when "00" & x"596" => data <= x"0e";
when "00" & x"597" => data <= x"0f";
when "00" & x"598" => data <= x"29";
when "00" & x"599" => data <= x"03";
when "00" & x"59a" => data <= x"65";
when "00" & x"59b" => data <= x"c4";
when "00" & x"59c" => data <= x"85";
when "00" & x"59d" => data <= x"c4";
when "00" & x"59e" => data <= x"38";
when "00" & x"59f" => data <= x"b9";
when "00" & x"5a0" => data <= x"07";
when "00" & x"5a1" => data <= x"0f";
when "00" & x"5a2" => data <= x"e5";
when "00" & x"5a3" => data <= x"c5";
when "00" & x"5a4" => data <= x"48";
when "00" & x"5a5" => data <= x"b9";
when "00" & x"5a6" => data <= x"06";
when "00" & x"5a7" => data <= x"0f";
when "00" & x"5a8" => data <= x"29";
when "00" & x"5a9" => data <= x"03";
when "00" & x"5aa" => data <= x"e5";
when "00" & x"5ab" => data <= x"c4";
when "00" & x"5ac" => data <= x"aa";
when "00" & x"5ad" => data <= x"a9";
when "00" & x"5ae" => data <= x"00";
when "00" & x"5af" => data <= x"c5";
when "00" & x"5b0" => data <= x"c2";
when "00" & x"5b1" => data <= x"68";
when "00" & x"5b2" => data <= x"e5";
when "00" & x"5b3" => data <= x"c3";
when "00" & x"5b4" => data <= x"8a";
when "00" & x"5b5" => data <= x"e5";
when "00" & x"5b6" => data <= x"c6";
when "00" & x"5b7" => data <= x"60";
when "00" & x"5b8" => data <= x"41";
when "00" & x"5b9" => data <= x"43";
when "00" & x"5ba" => data <= x"43";
when "00" & x"5bb" => data <= x"45";
when "00" & x"5bc" => data <= x"53";
when "00" & x"5bd" => data <= x"53";
when "00" & x"5be" => data <= x"88";
when "00" & x"5bf" => data <= x"d1";
when "00" & x"5c0" => data <= x"32";
when "00" & x"5c1" => data <= x"42";
when "00" & x"5c2" => data <= x"41";
when "00" & x"5c3" => data <= x"43";
when "00" & x"5c4" => data <= x"4b";
when "00" & x"5c5" => data <= x"55";
when "00" & x"5c6" => data <= x"50";
when "00" & x"5c7" => data <= x"9c";
when "00" & x"5c8" => data <= x"ba";
when "00" & x"5c9" => data <= x"54";
when "00" & x"5ca" => data <= x"43";
when "00" & x"5cb" => data <= x"4f";
when "00" & x"5cc" => data <= x"4d";
when "00" & x"5cd" => data <= x"50";
when "00" & x"5ce" => data <= x"41";
when "00" & x"5cf" => data <= x"43";
when "00" & x"5d0" => data <= x"54";
when "00" & x"5d1" => data <= x"9a";
when "00" & x"5d2" => data <= x"bf";
when "00" & x"5d3" => data <= x"0a";
when "00" & x"5d4" => data <= x"43";
when "00" & x"5d5" => data <= x"4f";
when "00" & x"5d6" => data <= x"50";
when "00" & x"5d7" => data <= x"59";
when "00" & x"5d8" => data <= x"9d";
when "00" & x"5d9" => data <= x"26";
when "00" & x"5da" => data <= x"64";
when "00" & x"5db" => data <= x"44";
when "00" & x"5dc" => data <= x"45";
when "00" & x"5dd" => data <= x"4c";
when "00" & x"5de" => data <= x"45";
when "00" & x"5df" => data <= x"54";
when "00" & x"5e0" => data <= x"45";
when "00" & x"5e1" => data <= x"86";
when "00" & x"5e2" => data <= x"fd";
when "00" & x"5e3" => data <= x"01";
when "00" & x"5e4" => data <= x"44";
when "00" & x"5e5" => data <= x"45";
when "00" & x"5e6" => data <= x"53";
when "00" & x"5e7" => data <= x"54";
when "00" & x"5e8" => data <= x"52";
when "00" & x"5e9" => data <= x"4f";
when "00" & x"5ea" => data <= x"59";
when "00" & x"5eb" => data <= x"87";
when "00" & x"5ec" => data <= x"0f";
when "00" & x"5ed" => data <= x"02";
when "00" & x"5ee" => data <= x"44";
when "00" & x"5ef" => data <= x"49";
when "00" & x"5f0" => data <= x"52";
when "00" & x"5f1" => data <= x"88";
when "00" & x"5f2" => data <= x"4d";
when "00" & x"5f3" => data <= x"09";
when "00" & x"5f4" => data <= x"44";
when "00" & x"5f5" => data <= x"52";
when "00" & x"5f6" => data <= x"49";
when "00" & x"5f7" => data <= x"56";
when "00" & x"5f8" => data <= x"45";
when "00" & x"5f9" => data <= x"87";
when "00" & x"5fa" => data <= x"74";
when "00" & x"5fb" => data <= x"0a";
when "00" & x"5fc" => data <= x"45";
when "00" & x"5fd" => data <= x"4e";
when "00" & x"5fe" => data <= x"41";
when "00" & x"5ff" => data <= x"42";
when "00" & x"600" => data <= x"4c";
when "00" & x"601" => data <= x"45";
when "00" & x"602" => data <= x"8a";
when "00" & x"603" => data <= x"38";
when "00" & x"604" => data <= x"00";
when "00" & x"605" => data <= x"49";
when "00" & x"606" => data <= x"4e";
when "00" & x"607" => data <= x"46";
when "00" & x"608" => data <= x"4f";
when "00" & x"609" => data <= x"82";
when "00" & x"60a" => data <= x"83";
when "00" & x"60b" => data <= x"02";
when "00" & x"60c" => data <= x"4c";
when "00" & x"60d" => data <= x"49";
when "00" & x"60e" => data <= x"42";
when "00" & x"60f" => data <= x"88";
when "00" & x"610" => data <= x"51";
when "00" & x"611" => data <= x"09";
when "00" & x"612" => data <= x"52";
when "00" & x"613" => data <= x"45";
when "00" & x"614" => data <= x"4e";
when "00" & x"615" => data <= x"41";
when "00" & x"616" => data <= x"4d";
when "00" & x"617" => data <= x"45";
when "00" & x"618" => data <= x"8a";
when "00" & x"619" => data <= x"6c";
when "00" & x"61a" => data <= x"87";
when "00" & x"61b" => data <= x"54";
when "00" & x"61c" => data <= x"49";
when "00" & x"61d" => data <= x"54";
when "00" & x"61e" => data <= x"4c";
when "00" & x"61f" => data <= x"45";
when "00" & x"620" => data <= x"88";
when "00" & x"621" => data <= x"a2";
when "00" & x"622" => data <= x"0b";
when "00" & x"623" => data <= x"57";
when "00" & x"624" => data <= x"49";
when "00" & x"625" => data <= x"50";
when "00" & x"626" => data <= x"45";
when "00" & x"627" => data <= x"86";
when "00" & x"628" => data <= x"c2";
when "00" & x"629" => data <= x"02";
when "00" & x"62a" => data <= x"b4";
when "00" & x"62b" => data <= x"6b";
when "00" & x"62c" => data <= x"00";
when "00" & x"62d" => data <= x"42";
when "00" & x"62e" => data <= x"55";
when "00" & x"62f" => data <= x"49";
when "00" & x"630" => data <= x"4c";
when "00" & x"631" => data <= x"44";
when "00" & x"632" => data <= x"9f";
when "00" & x"633" => data <= x"47";
when "00" & x"634" => data <= x"01";
when "00" & x"635" => data <= x"43";
when "00" & x"636" => data <= x"41";
when "00" & x"637" => data <= x"52";
when "00" & x"638" => data <= x"44";
when "00" & x"639" => data <= x"93";
when "00" & x"63a" => data <= x"37";
when "00" & x"63b" => data <= x"00";
when "00" & x"63c" => data <= x"44";
when "00" & x"63d" => data <= x"55";
when "00" & x"63e" => data <= x"4d";
when "00" & x"63f" => data <= x"50";
when "00" & x"640" => data <= x"9e";
when "00" & x"641" => data <= x"cf";
when "00" & x"642" => data <= x"01";
when "00" & x"643" => data <= x"4c";
when "00" & x"644" => data <= x"49";
when "00" & x"645" => data <= x"53";
when "00" & x"646" => data <= x"54";
when "00" & x"647" => data <= x"9e";
when "00" & x"648" => data <= x"8d";
when "00" & x"649" => data <= x"01";
when "00" & x"64a" => data <= x"54";
when "00" & x"64b" => data <= x"59";
when "00" & x"64c" => data <= x"50";
when "00" & x"64d" => data <= x"45";
when "00" & x"64e" => data <= x"9e";
when "00" & x"64f" => data <= x"86";
when "00" & x"650" => data <= x"01";
when "00" & x"651" => data <= x"44";
when "00" & x"652" => data <= x"4d";
when "00" & x"653" => data <= x"4d";
when "00" & x"654" => data <= x"43";
when "00" & x"655" => data <= x"93";
when "00" & x"656" => data <= x"37";
when "00" & x"657" => data <= x"00";
when "00" & x"658" => data <= x"85";
when "00" & x"659" => data <= x"b6";
when "00" & x"65a" => data <= x"00";
when "00" & x"65b" => data <= x"44";
when "00" & x"65c" => data <= x"46";
when "00" & x"65d" => data <= x"53";
when "00" & x"65e" => data <= x"99";
when "00" & x"65f" => data <= x"c5";
when "00" & x"660" => data <= x"00";
when "00" & x"661" => data <= x"55";
when "00" & x"662" => data <= x"54";
when "00" & x"663" => data <= x"49";
when "00" & x"664" => data <= x"4c";
when "00" & x"665" => data <= x"53";
when "00" & x"666" => data <= x"99";
when "00" & x"667" => data <= x"ed";
when "00" & x"668" => data <= x"00";
when "00" & x"669" => data <= x"99";
when "00" & x"66a" => data <= x"f4";
when "00" & x"66b" => data <= x"00";
when "00" & x"66c" => data <= x"20";
when "00" & x"66d" => data <= x"b8";
when "00" & x"66e" => data <= x"86";
when "00" & x"66f" => data <= x"a2";
when "00" & x"670" => data <= x"fd";
when "00" & x"671" => data <= x"8a";
when "00" & x"672" => data <= x"ba";
when "00" & x"673" => data <= x"86";
when "00" & x"674" => data <= x"b6";
when "00" & x"675" => data <= x"aa";
when "00" & x"676" => data <= x"98";
when "00" & x"677" => data <= x"48";
when "00" & x"678" => data <= x"e8";
when "00" & x"679" => data <= x"e8";
when "00" & x"67a" => data <= x"68";
when "00" & x"67b" => data <= x"48";
when "00" & x"67c" => data <= x"a8";
when "00" & x"67d" => data <= x"20";
when "00" & x"67e" => data <= x"bf";
when "00" & x"67f" => data <= x"86";
when "00" & x"680" => data <= x"e8";
when "00" & x"681" => data <= x"bd";
when "00" & x"682" => data <= x"b8";
when "00" & x"683" => data <= x"85";
when "00" & x"684" => data <= x"30";
when "00" & x"685" => data <= x"28";
when "00" & x"686" => data <= x"ca";
when "00" & x"687" => data <= x"88";
when "00" & x"688" => data <= x"86";
when "00" & x"689" => data <= x"b8";
when "00" & x"68a" => data <= x"e8";
when "00" & x"68b" => data <= x"c8";
when "00" & x"68c" => data <= x"bd";
when "00" & x"68d" => data <= x"b8";
when "00" & x"68e" => data <= x"85";
when "00" & x"68f" => data <= x"30";
when "00" & x"690" => data <= x"16";
when "00" & x"691" => data <= x"51";
when "00" & x"692" => data <= x"f2";
when "00" & x"693" => data <= x"29";
when "00" & x"694" => data <= x"5f";
when "00" & x"695" => data <= x"f0";
when "00" & x"696" => data <= x"f3";
when "00" & x"697" => data <= x"ca";
when "00" & x"698" => data <= x"e8";
when "00" & x"699" => data <= x"bd";
when "00" & x"69a" => data <= x"b8";
when "00" & x"69b" => data <= x"85";
when "00" & x"69c" => data <= x"10";
when "00" & x"69d" => data <= x"fa";
when "00" & x"69e" => data <= x"b1";
when "00" & x"69f" => data <= x"f2";
when "00" & x"6a0" => data <= x"c9";
when "00" & x"6a1" => data <= x"2e";
when "00" & x"6a2" => data <= x"d0";
when "00" & x"6a3" => data <= x"d4";
when "00" & x"6a4" => data <= x"c8";
when "00" & x"6a5" => data <= x"b0";
when "00" & x"6a6" => data <= x"07";
when "00" & x"6a7" => data <= x"b1";
when "00" & x"6a8" => data <= x"f2";
when "00" & x"6a9" => data <= x"20";
when "00" & x"6aa" => data <= x"ee";
when "00" & x"6ab" => data <= x"82";
when "00" & x"6ac" => data <= x"90";
when "00" & x"6ad" => data <= x"ca";
when "00" & x"6ae" => data <= x"68";
when "00" & x"6af" => data <= x"bd";
when "00" & x"6b0" => data <= x"b8";
when "00" & x"6b1" => data <= x"85";
when "00" & x"6b2" => data <= x"48";
when "00" & x"6b3" => data <= x"bd";
when "00" & x"6b4" => data <= x"b9";
when "00" & x"6b5" => data <= x"85";
when "00" & x"6b6" => data <= x"48";
when "00" & x"6b7" => data <= x"60";
when "00" & x"6b8" => data <= x"86";
when "00" & x"6b9" => data <= x"f2";
when "00" & x"6ba" => data <= x"84";
when "00" & x"6bb" => data <= x"f3";
when "00" & x"6bc" => data <= x"a0";
when "00" & x"6bd" => data <= x"00";
when "00" & x"6be" => data <= x"60";
when "00" & x"6bf" => data <= x"18";
when "00" & x"6c0" => data <= x"4c";
when "00" & x"6c1" => data <= x"c2";
when "00" & x"6c2" => data <= x"ff";
when "00" & x"6c3" => data <= x"20";
when "00" & x"6c4" => data <= x"5e";
when "00" & x"6c5" => data <= x"82";
when "00" & x"6c6" => data <= x"20";
when "00" & x"6c7" => data <= x"01";
when "00" & x"6c8" => data <= x"9a";
when "00" & x"6c9" => data <= x"20";
when "00" & x"6ca" => data <= x"68";
when "00" & x"6cb" => data <= x"82";
when "00" & x"6cc" => data <= x"b9";
when "00" & x"6cd" => data <= x"0f";
when "00" & x"6ce" => data <= x"0e";
when "00" & x"6cf" => data <= x"30";
when "00" & x"6d0" => data <= x"12";
when "00" & x"6d1" => data <= x"20";
when "00" & x"6d2" => data <= x"c0";
when "00" & x"6d3" => data <= x"81";
when "00" & x"6d4" => data <= x"20";
when "00" & x"6d5" => data <= x"65";
when "00" & x"6d6" => data <= x"80";
when "00" & x"6d7" => data <= x"20";
when "00" & x"6d8" => data <= x"3a";
when "00" & x"6d9" => data <= x"20";
when "00" & x"6da" => data <= x"ea";
when "00" & x"6db" => data <= x"20";
when "00" & x"6dc" => data <= x"9e";
when "00" & x"6dd" => data <= x"9c";
when "00" & x"6de" => data <= x"f0";
when "00" & x"6df" => data <= x"09";
when "00" & x"6e0" => data <= x"20";
when "00" & x"6e1" => data <= x"9a";
when "00" & x"6e2" => data <= x"9f";
when "00" & x"6e3" => data <= x"20";
when "00" & x"6e4" => data <= x"9d";
when "00" & x"6e5" => data <= x"82";
when "00" & x"6e6" => data <= x"b0";
when "00" & x"6e7" => data <= x"e4";
when "00" & x"6e8" => data <= x"60";
when "00" & x"6e9" => data <= x"20";
when "00" & x"6ea" => data <= x"a1";
when "00" & x"6eb" => data <= x"81";
when "00" & x"6ec" => data <= x"20";
when "00" & x"6ed" => data <= x"d1";
when "00" & x"6ee" => data <= x"82";
when "00" & x"6ef" => data <= x"20";
when "00" & x"6f0" => data <= x"b4";
when "00" & x"6f1" => data <= x"8a";
when "00" & x"6f2" => data <= x"ac";
when "00" & x"6f3" => data <= x"ce";
when "00" & x"6f4" => data <= x"10";
when "00" & x"6f5" => data <= x"20";
when "00" & x"6f6" => data <= x"19";
when "00" & x"6f7" => data <= x"82";
when "00" & x"6f8" => data <= x"8c";
when "00" & x"6f9" => data <= x"ce";
when "00" & x"6fa" => data <= x"10";
when "00" & x"6fb" => data <= x"4c";
when "00" & x"6fc" => data <= x"e0";
when "00" & x"6fd" => data <= x"86";
when "00" & x"6fe" => data <= x"20";
when "00" & x"6ff" => data <= x"62";
when "00" & x"700" => data <= x"82";
when "00" & x"701" => data <= x"20";
when "00" & x"702" => data <= x"01";
when "00" & x"703" => data <= x"9a";
when "00" & x"704" => data <= x"20";
when "00" & x"705" => data <= x"68";
when "00" & x"706" => data <= x"82";
when "00" & x"707" => data <= x"20";
when "00" & x"708" => data <= x"fc";
when "00" & x"709" => data <= x"82";
when "00" & x"70a" => data <= x"20";
when "00" & x"70b" => data <= x"d1";
when "00" & x"70c" => data <= x"82";
when "00" & x"70d" => data <= x"4c";
when "00" & x"70e" => data <= x"b4";
when "00" & x"70f" => data <= x"8a";
when "00" & x"710" => data <= x"20";
when "00" & x"711" => data <= x"bd";
when "00" & x"712" => data <= x"9b";
when "00" & x"713" => data <= x"20";
when "00" & x"714" => data <= x"5e";
when "00" & x"715" => data <= x"82";
when "00" & x"716" => data <= x"20";
when "00" & x"717" => data <= x"01";
when "00" & x"718" => data <= x"9a";
when "00" & x"719" => data <= x"20";
when "00" & x"71a" => data <= x"68";
when "00" & x"71b" => data <= x"82";
when "00" & x"71c" => data <= x"b9";
when "00" & x"71d" => data <= x"0f";
when "00" & x"71e" => data <= x"0e";
when "00" & x"71f" => data <= x"30";
when "00" & x"720" => data <= x"06";
when "00" & x"721" => data <= x"20";
when "00" & x"722" => data <= x"c0";
when "00" & x"723" => data <= x"81";
when "00" & x"724" => data <= x"20";
when "00" & x"725" => data <= x"9a";
when "00" & x"726" => data <= x"9f";
when "00" & x"727" => data <= x"20";
when "00" & x"728" => data <= x"9d";
when "00" & x"729" => data <= x"82";
when "00" & x"72a" => data <= x"b0";
when "00" & x"72b" => data <= x"f0";
when "00" & x"72c" => data <= x"20";
when "00" & x"72d" => data <= x"65";
when "00" & x"72e" => data <= x"80";
when "00" & x"72f" => data <= x"0d";
when "00" & x"730" => data <= x"44";
when "00" & x"731" => data <= x"65";
when "00" & x"732" => data <= x"6c";
when "00" & x"733" => data <= x"65";
when "00" & x"734" => data <= x"74";
when "00" & x"735" => data <= x"65";
when "00" & x"736" => data <= x"20";
when "00" & x"737" => data <= x"28";
when "00" & x"738" => data <= x"59";
when "00" & x"739" => data <= x"2f";
when "00" & x"73a" => data <= x"4e";
when "00" & x"73b" => data <= x"29";
when "00" & x"73c" => data <= x"20";
when "00" & x"73d" => data <= x"3f";
when "00" & x"73e" => data <= x"20";
when "00" & x"73f" => data <= x"ea";
when "00" & x"740" => data <= x"20";
when "00" & x"741" => data <= x"9e";
when "00" & x"742" => data <= x"9c";
when "00" & x"743" => data <= x"f0";
when "00" & x"744" => data <= x"03";
when "00" & x"745" => data <= x"4c";
when "00" & x"746" => data <= x"9a";
when "00" & x"747" => data <= x"9f";
when "00" & x"748" => data <= x"20";
when "00" & x"749" => data <= x"a1";
when "00" & x"74a" => data <= x"81";
when "00" & x"74b" => data <= x"20";
when "00" & x"74c" => data <= x"96";
when "00" & x"74d" => data <= x"82";
when "00" & x"74e" => data <= x"b9";
when "00" & x"74f" => data <= x"0f";
when "00" & x"750" => data <= x"0e";
when "00" & x"751" => data <= x"30";
when "00" & x"752" => data <= x"0c";
when "00" & x"753" => data <= x"20";
when "00" & x"754" => data <= x"d1";
when "00" & x"755" => data <= x"82";
when "00" & x"756" => data <= x"ac";
when "00" & x"757" => data <= x"ce";
when "00" & x"758" => data <= x"10";
when "00" & x"759" => data <= x"20";
when "00" & x"75a" => data <= x"19";
when "00" & x"75b" => data <= x"82";
when "00" & x"75c" => data <= x"8c";
when "00" & x"75d" => data <= x"ce";
when "00" & x"75e" => data <= x"10";
when "00" & x"75f" => data <= x"20";
when "00" & x"760" => data <= x"9d";
when "00" & x"761" => data <= x"82";
when "00" & x"762" => data <= x"b0";
when "00" & x"763" => data <= x"ea";
when "00" & x"764" => data <= x"20";
when "00" & x"765" => data <= x"b4";
when "00" & x"766" => data <= x"8a";
when "00" & x"767" => data <= x"20";
when "00" & x"768" => data <= x"65";
when "00" & x"769" => data <= x"80";
when "00" & x"76a" => data <= x"0d";
when "00" & x"76b" => data <= x"44";
when "00" & x"76c" => data <= x"65";
when "00" & x"76d" => data <= x"6c";
when "00" & x"76e" => data <= x"65";
when "00" & x"76f" => data <= x"74";
when "00" & x"770" => data <= x"65";
when "00" & x"771" => data <= x"64";
when "00" & x"772" => data <= x"0d";
when "00" & x"773" => data <= x"ea";
when "00" & x"774" => data <= x"60";
when "00" & x"775" => data <= x"20";
when "00" & x"776" => data <= x"01";
when "00" & x"777" => data <= x"9a";
when "00" & x"778" => data <= x"20";
when "00" & x"779" => data <= x"5d";
when "00" & x"77a" => data <= x"83";
when "00" & x"77b" => data <= x"8d";
when "00" & x"77c" => data <= x"cb";
when "00" & x"77d" => data <= x"10";
when "00" & x"77e" => data <= x"ea";
when "00" & x"77f" => data <= x"ea";
when "00" & x"780" => data <= x"ea";
when "00" & x"781" => data <= x"29";
when "00" & x"782" => data <= x"03";
when "00" & x"783" => data <= x"85";
when "00" & x"784" => data <= x"cf";
when "00" & x"785" => data <= x"60";
when "00" & x"786" => data <= x"20";
when "00" & x"787" => data <= x"61";
when "00" & x"788" => data <= x"89";
when "00" & x"789" => data <= x"20";
when "00" & x"78a" => data <= x"6e";
when "00" & x"78b" => data <= x"98";
when "00" & x"78c" => data <= x"20";
when "00" & x"78d" => data <= x"7e";
when "00" & x"78e" => data <= x"83";
when "00" & x"78f" => data <= x"4c";
when "00" & x"790" => data <= x"99";
when "00" & x"791" => data <= x"af";
when "00" & x"792" => data <= x"ea";
when "00" & x"793" => data <= x"ea";
when "00" & x"794" => data <= x"20";
when "00" & x"795" => data <= x"6e";
when "00" & x"796" => data <= x"82";
when "00" & x"797" => data <= x"20";
when "00" & x"798" => data <= x"6e";
when "00" & x"799" => data <= x"98";
when "00" & x"79a" => data <= x"20";
when "00" & x"79b" => data <= x"7e";
when "00" & x"79c" => data <= x"83";
when "00" & x"79d" => data <= x"84";
when "00" & x"79e" => data <= x"bc";
when "00" & x"79f" => data <= x"a2";
when "00" & x"7a0" => data <= x"00";
when "00" & x"7a1" => data <= x"a5";
when "00" & x"7a2" => data <= x"c0";
when "00" & x"7a3" => data <= x"d0";
when "00" & x"7a4" => data <= x"06";
when "00" & x"7a5" => data <= x"c8";
when "00" & x"7a6" => data <= x"c8";
when "00" & x"7a7" => data <= x"a2";
when "00" & x"7a8" => data <= x"02";
when "00" & x"7a9" => data <= x"d0";
when "00" & x"7aa" => data <= x"08";
when "00" & x"7ab" => data <= x"b9";
when "00" & x"7ac" => data <= x"0e";
when "00" & x"7ad" => data <= x"0f";
when "00" & x"7ae" => data <= x"85";
when "00" & x"7af" => data <= x"c4";
when "00" & x"7b0" => data <= x"20";
when "00" & x"7b1" => data <= x"3f";
when "00" & x"7b2" => data <= x"8a";
when "00" & x"7b3" => data <= x"b9";
when "00" & x"7b4" => data <= x"08";
when "00" & x"7b5" => data <= x"0f";
when "00" & x"7b6" => data <= x"95";
when "00" & x"7b7" => data <= x"be";
when "00" & x"7b8" => data <= x"c8";
when "00" & x"7b9" => data <= x"e8";
when "00" & x"7ba" => data <= x"e0";
when "00" & x"7bb" => data <= x"08";
when "00" & x"7bc" => data <= x"d0";
when "00" & x"7bd" => data <= x"f5";
when "00" & x"7be" => data <= x"20";
when "00" & x"7bf" => data <= x"56";
when "00" & x"7c0" => data <= x"8a";
when "00" & x"7c1" => data <= x"a4";
when "00" & x"7c2" => data <= x"bc";
when "00" & x"7c3" => data <= x"20";
when "00" & x"7c4" => data <= x"fc";
when "00" & x"7c5" => data <= x"82";
when "00" & x"7c6" => data <= x"4c";
when "00" & x"7c7" => data <= x"8a";
when "00" & x"7c8" => data <= x"af";
when "00" & x"7c9" => data <= x"00";
when "00" & x"7ca" => data <= x"00";
when "00" & x"7cb" => data <= x"00";
when "00" & x"7cc" => data <= x"00";
when "00" & x"7cd" => data <= x"00";
when "00" & x"7ce" => data <= x"00";
when "00" & x"7cf" => data <= x"00";
when "00" & x"7d0" => data <= x"00";
when "00" & x"7d1" => data <= x"00";
when "00" & x"7d2" => data <= x"00";
when "00" & x"7d3" => data <= x"00";
when "00" & x"7d4" => data <= x"20";
when "00" & x"7d5" => data <= x"b8";
when "00" & x"7d6" => data <= x"86";
when "00" & x"7d7" => data <= x"20";
when "00" & x"7d8" => data <= x"41";
when "00" & x"7d9" => data <= x"88";
when "00" & x"7da" => data <= x"8c";
when "00" & x"7db" => data <= x"db";
when "00" & x"7dc" => data <= x"10";
when "00" & x"7dd" => data <= x"20";
when "00" & x"7de" => data <= x"06";
when "00" & x"7df" => data <= x"81";
when "00" & x"7e0" => data <= x"8c";
when "00" & x"7e1" => data <= x"da";
when "00" & x"7e2" => data <= x"10";
when "00" & x"7e3" => data <= x"20";
when "00" & x"7e4" => data <= x"96";
when "00" & x"7e5" => data <= x"82";
when "00" & x"7e6" => data <= x"b0";
when "00" & x"7e7" => data <= x"22";
when "00" & x"7e8" => data <= x"ac";
when "00" & x"7e9" => data <= x"db";
when "00" & x"7ea" => data <= x"10";
when "00" & x"7eb" => data <= x"ad";
when "00" & x"7ec" => data <= x"cc";
when "00" & x"7ed" => data <= x"10";
when "00" & x"7ee" => data <= x"85";
when "00" & x"7ef" => data <= x"ce";
when "00" & x"7f0" => data <= x"ad";
when "00" & x"7f1" => data <= x"cd";
when "00" & x"7f2" => data <= x"10";
when "00" & x"7f3" => data <= x"20";
when "00" & x"7f4" => data <= x"7e";
when "00" & x"7f5" => data <= x"87";
when "00" & x"7f6" => data <= x"20";
when "00" & x"7f7" => data <= x"09";
when "00" & x"7f8" => data <= x"81";
when "00" & x"7f9" => data <= x"20";
when "00" & x"7fa" => data <= x"96";
when "00" & x"7fb" => data <= x"82";
when "00" & x"7fc" => data <= x"b0";
when "00" & x"7fd" => data <= x"0c";
when "00" & x"7fe" => data <= x"20";
when "00" & x"7ff" => data <= x"22";
when "00" & x"800" => data <= x"80";
when "00" & x"801" => data <= x"fe";
when "00" & x"802" => data <= x"63";
when "00" & x"803" => data <= x"6f";
when "00" & x"804" => data <= x"6d";
when "00" & x"805" => data <= x"6d";
when "00" & x"806" => data <= x"61";
when "00" & x"807" => data <= x"6e";
when "00" & x"808" => data <= x"64";
when "00" & x"809" => data <= x"00";
when "00" & x"80a" => data <= x"20";
when "00" & x"80b" => data <= x"9d";
when "00" & x"80c" => data <= x"87";
when "00" & x"80d" => data <= x"18";
when "00" & x"80e" => data <= x"ad";
when "00" & x"80f" => data <= x"da";
when "00" & x"810" => data <= x"10";
when "00" & x"811" => data <= x"a8";
when "00" & x"812" => data <= x"65";
when "00" & x"813" => data <= x"f2";
when "00" & x"814" => data <= x"8d";
when "00" & x"815" => data <= x"da";
when "00" & x"816" => data <= x"10";
when "00" & x"817" => data <= x"a5";
when "00" & x"818" => data <= x"f3";
when "00" & x"819" => data <= x"69";
when "00" & x"81a" => data <= x"00";
when "00" & x"81b" => data <= x"8d";
when "00" & x"81c" => data <= x"db";
when "00" & x"81d" => data <= x"10";
when "00" & x"81e" => data <= x"ad";
when "00" & x"81f" => data <= x"76";
when "00" & x"820" => data <= x"10";
when "00" & x"821" => data <= x"2d";
when "00" & x"822" => data <= x"77";
when "00" & x"823" => data <= x"10";
when "00" & x"824" => data <= x"0d";
when "00" & x"825" => data <= x"d7";
when "00" & x"826" => data <= x"10";
when "00" & x"827" => data <= x"c9";
when "00" & x"828" => data <= x"ff";
when "00" & x"829" => data <= x"f0";
when "00" & x"82a" => data <= x"13";
when "00" & x"82b" => data <= x"a5";
when "00" & x"82c" => data <= x"c0";
when "00" & x"82d" => data <= x"8d";
when "00" & x"82e" => data <= x"74";
when "00" & x"82f" => data <= x"10";
when "00" & x"830" => data <= x"a5";
when "00" & x"831" => data <= x"c1";
when "00" & x"832" => data <= x"8d";
when "00" & x"833" => data <= x"75";
when "00" & x"834" => data <= x"10";
when "00" & x"835" => data <= x"a2";
when "00" & x"836" => data <= x"74";
when "00" & x"837" => data <= x"a0";
when "00" & x"838" => data <= x"10";
when "00" & x"839" => data <= x"a9";
when "00" & x"83a" => data <= x"04";
when "00" & x"83b" => data <= x"4c";
when "00" & x"83c" => data <= x"06";
when "00" & x"83d" => data <= x"04";
when "00" & x"83e" => data <= x"6c";
when "00" & x"83f" => data <= x"c0";
when "00" & x"840" => data <= x"00";
when "00" & x"841" => data <= x"a9";
when "00" & x"842" => data <= x"ff";
when "00" & x"843" => data <= x"85";
when "00" & x"844" => data <= x"c0";
when "00" & x"845" => data <= x"a5";
when "00" & x"846" => data <= x"f2";
when "00" & x"847" => data <= x"85";
when "00" & x"848" => data <= x"bc";
when "00" & x"849" => data <= x"a5";
when "00" & x"84a" => data <= x"f3";
when "00" & x"84b" => data <= x"85";
when "00" & x"84c" => data <= x"bd";
when "00" & x"84d" => data <= x"60";
when "00" & x"84e" => data <= x"a2";
when "00" & x"84f" => data <= x"00";
when "00" & x"850" => data <= x"f0";
when "00" & x"851" => data <= x"02";
when "00" & x"852" => data <= x"a2";
when "00" & x"853" => data <= x"02";
when "00" & x"854" => data <= x"20";
when "00" & x"855" => data <= x"60";
when "00" & x"856" => data <= x"88";
when "00" & x"857" => data <= x"9d";
when "00" & x"858" => data <= x"cb";
when "00" & x"859" => data <= x"10";
when "00" & x"85a" => data <= x"a5";
when "00" & x"85b" => data <= x"ce";
when "00" & x"85c" => data <= x"9d";
when "00" & x"85d" => data <= x"ca";
when "00" & x"85e" => data <= x"10";
when "00" & x"85f" => data <= x"60";
when "00" & x"860" => data <= x"a9";
when "00" & x"861" => data <= x"24";
when "00" & x"862" => data <= x"85";
when "00" & x"863" => data <= x"ce";
when "00" & x"864" => data <= x"20";
when "00" & x"865" => data <= x"bf";
when "00" & x"866" => data <= x"86";
when "00" & x"867" => data <= x"d0";
when "00" & x"868" => data <= x"07";
when "00" & x"869" => data <= x"a9";
when "00" & x"86a" => data <= x"00";
when "00" & x"86b" => data <= x"20";
when "00" & x"86c" => data <= x"7e";
when "00" & x"86d" => data <= x"87";
when "00" & x"86e" => data <= x"f0";
when "00" & x"86f" => data <= x"30";
when "00" & x"870" => data <= x"ad";
when "00" & x"871" => data <= x"cb";
when "00" & x"872" => data <= x"10";
when "00" & x"873" => data <= x"20";
when "00" & x"874" => data <= x"7e";
when "00" & x"875" => data <= x"87";
when "00" & x"876" => data <= x"20";
when "00" & x"877" => data <= x"c5";
when "00" & x"878" => data <= x"ff";
when "00" & x"879" => data <= x"b0";
when "00" & x"87a" => data <= x"10";
when "00" & x"87b" => data <= x"c9";
when "00" & x"87c" => data <= x"3a";
when "00" & x"87d" => data <= x"d0";
when "00" & x"87e" => data <= x"1a";
when "00" & x"87f" => data <= x"20";
when "00" & x"880" => data <= x"5d";
when "00" & x"881" => data <= x"83";
when "00" & x"882" => data <= x"20";
when "00" & x"883" => data <= x"c5";
when "00" & x"884" => data <= x"ff";
when "00" & x"885" => data <= x"b0";
when "00" & x"886" => data <= x"19";
when "00" & x"887" => data <= x"c9";
when "00" & x"888" => data <= x"2e";
when "00" & x"889" => data <= x"f0";
when "00" & x"88a" => data <= x"eb";
when "00" & x"88b" => data <= x"20";
when "00" & x"88c" => data <= x"22";
when "00" & x"88d" => data <= x"80";
when "00" & x"88e" => data <= x"ce";
when "00" & x"88f" => data <= x"64";
when "00" & x"890" => data <= x"69";
when "00" & x"891" => data <= x"72";
when "00" & x"892" => data <= x"65";
when "00" & x"893" => data <= x"63";
when "00" & x"894" => data <= x"74";
when "00" & x"895" => data <= x"6f";
when "00" & x"896" => data <= x"72";
when "00" & x"897" => data <= x"79";
when "00" & x"898" => data <= x"00";
when "00" & x"899" => data <= x"85";
when "00" & x"89a" => data <= x"ce";
when "00" & x"89b" => data <= x"20";
when "00" & x"89c" => data <= x"c5";
when "00" & x"89d" => data <= x"ff";
when "00" & x"89e" => data <= x"90";
when "00" & x"89f" => data <= x"eb";
when "00" & x"8a0" => data <= x"a5";
when "00" & x"8a1" => data <= x"cf";
when "00" & x"8a2" => data <= x"60";
when "00" & x"8a3" => data <= x"20";
when "00" & x"8a4" => data <= x"01";
when "00" & x"8a5" => data <= x"9a";
when "00" & x"8a6" => data <= x"20";
when "00" & x"8a7" => data <= x"4d";
when "00" & x"8a8" => data <= x"83";
when "00" & x"8a9" => data <= x"20";
when "00" & x"8aa" => data <= x"47";
when "00" & x"8ab" => data <= x"83";
when "00" & x"8ac" => data <= x"4c";
when "00" & x"8ad" => data <= x"ce";
when "00" & x"8ae" => data <= x"b2";
when "00" & x"8af" => data <= x"00";
when "00" & x"8b0" => data <= x"20";
when "00" & x"8b1" => data <= x"c6";
when "00" & x"8b2" => data <= x"88";
when "00" & x"8b3" => data <= x"ca";
when "00" & x"8b4" => data <= x"10";
when "00" & x"8b5" => data <= x"fa";
when "00" & x"8b6" => data <= x"e8";
when "00" & x"8b7" => data <= x"20";
when "00" & x"8b8" => data <= x"c5";
when "00" & x"8b9" => data <= x"ff";
when "00" & x"8ba" => data <= x"b0";
when "00" & x"8bb" => data <= x"07";
when "00" & x"8bc" => data <= x"20";
when "00" & x"8bd" => data <= x"c6";
when "00" & x"8be" => data <= x"88";
when "00" & x"8bf" => data <= x"e0";
when "00" & x"8c0" => data <= x"0b";
when "00" & x"8c1" => data <= x"90";
when "00" & x"8c2" => data <= x"f3";
when "00" & x"8c3" => data <= x"4c";
when "00" & x"8c4" => data <= x"b4";
when "00" & x"8c5" => data <= x"8a";
when "00" & x"8c6" => data <= x"e0";
when "00" & x"8c7" => data <= x"08";
when "00" & x"8c8" => data <= x"90";
when "00" & x"8c9" => data <= x"04";
when "00" & x"8ca" => data <= x"9d";
when "00" & x"8cb" => data <= x"f8";
when "00" & x"8cc" => data <= x"0e";
when "00" & x"8cd" => data <= x"60";
when "00" & x"8ce" => data <= x"9d";
when "00" & x"8cf" => data <= x"00";
when "00" & x"8d0" => data <= x"0e";
when "00" & x"8d1" => data <= x"60";
when "00" & x"8d2" => data <= x"20";
when "00" & x"8d3" => data <= x"5e";
when "00" & x"8d4" => data <= x"82";
when "00" & x"8d5" => data <= x"20";
when "00" & x"8d6" => data <= x"01";
when "00" & x"8d7" => data <= x"9a";
when "00" & x"8d8" => data <= x"20";
when "00" & x"8d9" => data <= x"fe";
when "00" & x"8da" => data <= x"80";
when "00" & x"8db" => data <= x"a2";
when "00" & x"8dc" => data <= x"00";
when "00" & x"8dd" => data <= x"20";
when "00" & x"8de" => data <= x"bf";
when "00" & x"8df" => data <= x"86";
when "00" & x"8e0" => data <= x"d0";
when "00" & x"8e1" => data <= x"23";
when "00" & x"8e2" => data <= x"86";
when "00" & x"8e3" => data <= x"aa";
when "00" & x"8e4" => data <= x"20";
when "00" & x"8e5" => data <= x"96";
when "00" & x"8e6" => data <= x"82";
when "00" & x"8e7" => data <= x"b0";
when "00" & x"8e8" => data <= x"03";
when "00" & x"8e9" => data <= x"4c";
when "00" & x"8ea" => data <= x"76";
when "00" & x"8eb" => data <= x"82";
when "00" & x"8ec" => data <= x"20";
when "00" & x"8ed" => data <= x"4f";
when "00" & x"8ee" => data <= x"98";
when "00" & x"8ef" => data <= x"b9";
when "00" & x"8f0" => data <= x"0f";
when "00" & x"8f1" => data <= x"0e";
when "00" & x"8f2" => data <= x"29";
when "00" & x"8f3" => data <= x"7f";
when "00" & x"8f4" => data <= x"05";
when "00" & x"8f5" => data <= x"aa";
when "00" & x"8f6" => data <= x"99";
when "00" & x"8f7" => data <= x"0f";
when "00" & x"8f8" => data <= x"0e";
when "00" & x"8f9" => data <= x"20";
when "00" & x"8fa" => data <= x"fc";
when "00" & x"8fb" => data <= x"82";
when "00" & x"8fc" => data <= x"20";
when "00" & x"8fd" => data <= x"9d";
when "00" & x"8fe" => data <= x"82";
when "00" & x"8ff" => data <= x"b0";
when "00" & x"900" => data <= x"eb";
when "00" & x"901" => data <= x"90";
when "00" & x"902" => data <= x"c0";
when "00" & x"903" => data <= x"a2";
when "00" & x"904" => data <= x"80";
when "00" & x"905" => data <= x"20";
when "00" & x"906" => data <= x"c5";
when "00" & x"907" => data <= x"ff";
when "00" & x"908" => data <= x"b0";
when "00" & x"909" => data <= x"d8";
when "00" & x"90a" => data <= x"c9";
when "00" & x"90b" => data <= x"4c";
when "00" & x"90c" => data <= x"f0";
when "00" & x"90d" => data <= x"f5";
when "00" & x"90e" => data <= x"20";
when "00" & x"90f" => data <= x"22";
when "00" & x"910" => data <= x"80";
when "00" & x"911" => data <= x"cf";
when "00" & x"912" => data <= x"61";
when "00" & x"913" => data <= x"74";
when "00" & x"914" => data <= x"74";
when "00" & x"915" => data <= x"72";
when "00" & x"916" => data <= x"69";
when "00" & x"917" => data <= x"62";
when "00" & x"918" => data <= x"75";
when "00" & x"919" => data <= x"74";
when "00" & x"91a" => data <= x"65";
when "00" & x"91b" => data <= x"00";
when "00" & x"91c" => data <= x"20";
when "00" & x"91d" => data <= x"e1";
when "00" & x"91e" => data <= x"83";
when "00" & x"91f" => data <= x"8a";
when "00" & x"920" => data <= x"c9";
when "00" & x"921" => data <= x"04";
when "00" & x"922" => data <= x"f0";
when "00" & x"923" => data <= x"1a";
when "00" & x"924" => data <= x"c9";
when "00" & x"925" => data <= x"02";
when "00" & x"926" => data <= x"90";
when "00" & x"927" => data <= x"0b";
when "00" & x"928" => data <= x"20";
when "00" & x"929" => data <= x"22";
when "00" & x"92a" => data <= x"80";
when "00" & x"92b" => data <= x"cb";
when "00" & x"92c" => data <= x"6f";
when "00" & x"92d" => data <= x"70";
when "00" & x"92e" => data <= x"74";
when "00" & x"92f" => data <= x"69";
when "00" & x"930" => data <= x"6f";
when "00" & x"931" => data <= x"6e";
when "00" & x"932" => data <= x"00";
when "00" & x"933" => data <= x"a2";
when "00" & x"934" => data <= x"ff";
when "00" & x"935" => data <= x"98";
when "00" & x"936" => data <= x"f0";
when "00" & x"937" => data <= x"02";
when "00" & x"938" => data <= x"a2";
when "00" & x"939" => data <= x"00";
when "00" & x"93a" => data <= x"8e";
when "00" & x"93b" => data <= x"c7";
when "00" & x"93c" => data <= x"10";
when "00" & x"93d" => data <= x"60";
when "00" & x"93e" => data <= x"98";
when "00" & x"93f" => data <= x"48";
when "00" & x"940" => data <= x"20";
when "00" & x"941" => data <= x"4d";
when "00" & x"942" => data <= x"83";
when "00" & x"943" => data <= x"20";
when "00" & x"944" => data <= x"41";
when "00" & x"945" => data <= x"af";
when "00" & x"946" => data <= x"68";
when "00" & x"947" => data <= x"20";
when "00" & x"948" => data <= x"0b";
when "00" & x"949" => data <= x"82";
when "00" & x"94a" => data <= x"4d";
when "00" & x"94b" => data <= x"06";
when "00" & x"94c" => data <= x"0f";
when "00" & x"94d" => data <= x"29";
when "00" & x"94e" => data <= x"30";
when "00" & x"94f" => data <= x"4d";
when "00" & x"950" => data <= x"06";
when "00" & x"951" => data <= x"0f";
when "00" & x"952" => data <= x"8d";
when "00" & x"953" => data <= x"06";
when "00" & x"954" => data <= x"0f";
when "00" & x"955" => data <= x"4c";
when "00" & x"956" => data <= x"b4";
when "00" & x"957" => data <= x"8a";
when "00" & x"958" => data <= x"20";
when "00" & x"959" => data <= x"18";
when "00" & x"95a" => data <= x"80";
when "00" & x"95b" => data <= x"c6";
when "00" & x"95c" => data <= x"66";
when "00" & x"95d" => data <= x"75";
when "00" & x"95e" => data <= x"6c";
when "00" & x"95f" => data <= x"6c";
when "00" & x"960" => data <= x"00";
when "00" & x"961" => data <= x"20";
when "00" & x"962" => data <= x"06";
when "00" & x"963" => data <= x"81";
when "00" & x"964" => data <= x"20";
when "00" & x"965" => data <= x"96";
when "00" & x"966" => data <= x"82";
when "00" & x"967" => data <= x"90";
when "00" & x"968" => data <= x"03";
when "00" & x"969" => data <= x"20";
when "00" & x"96a" => data <= x"d1";
when "00" & x"96b" => data <= x"82";
when "00" & x"96c" => data <= x"a5";
when "00" & x"96d" => data <= x"c2";
when "00" & x"96e" => data <= x"48";
when "00" & x"96f" => data <= x"a5";
when "00" & x"970" => data <= x"c3";
when "00" & x"971" => data <= x"48";
when "00" & x"972" => data <= x"38";
when "00" & x"973" => data <= x"a5";
when "00" & x"974" => data <= x"c4";
when "00" & x"975" => data <= x"e5";
when "00" & x"976" => data <= x"c2";
when "00" & x"977" => data <= x"85";
when "00" & x"978" => data <= x"c2";
when "00" & x"979" => data <= x"a5";
when "00" & x"97a" => data <= x"c5";
when "00" & x"97b" => data <= x"e5";
when "00" & x"97c" => data <= x"c3";
when "00" & x"97d" => data <= x"85";
when "00" & x"97e" => data <= x"c3";
when "00" & x"97f" => data <= x"ad";
when "00" & x"980" => data <= x"7a";
when "00" & x"981" => data <= x"10";
when "00" & x"982" => data <= x"ed";
when "00" & x"983" => data <= x"78";
when "00" & x"984" => data <= x"10";
when "00" & x"985" => data <= x"85";
when "00" & x"986" => data <= x"c6";
when "00" & x"987" => data <= x"20";
when "00" & x"988" => data <= x"9d";
when "00" & x"989" => data <= x"89";
when "00" & x"98a" => data <= x"ad";
when "00" & x"98b" => data <= x"79";
when "00" & x"98c" => data <= x"10";
when "00" & x"98d" => data <= x"8d";
when "00" & x"98e" => data <= x"75";
when "00" & x"98f" => data <= x"10";
when "00" & x"990" => data <= x"ad";
when "00" & x"991" => data <= x"78";
when "00" & x"992" => data <= x"10";
when "00" & x"993" => data <= x"8d";
when "00" & x"994" => data <= x"74";
when "00" & x"995" => data <= x"10";
when "00" & x"996" => data <= x"68";
when "00" & x"997" => data <= x"85";
when "00" & x"998" => data <= x"bf";
when "00" & x"999" => data <= x"68";
when "00" & x"99a" => data <= x"85";
when "00" & x"99b" => data <= x"be";
when "00" & x"99c" => data <= x"60";
when "00" & x"99d" => data <= x"a9";
when "00" & x"99e" => data <= x"00";
when "00" & x"99f" => data <= x"85";
when "00" & x"9a0" => data <= x"c4";
when "00" & x"9a1" => data <= x"a9";
when "00" & x"9a2" => data <= x"02";
when "00" & x"9a3" => data <= x"85";
when "00" & x"9a4" => data <= x"c5";
when "00" & x"9a5" => data <= x"ac";
when "00" & x"9a6" => data <= x"05";
when "00" & x"9a7" => data <= x"0f";
when "00" & x"9a8" => data <= x"f0";
when "00" & x"9a9" => data <= x"2d";
when "00" & x"9aa" => data <= x"c0";
when "00" & x"9ab" => data <= x"f8";
when "00" & x"9ac" => data <= x"b0";
when "00" & x"9ad" => data <= x"56";
when "00" & x"9ae" => data <= x"20";
when "00" & x"9af" => data <= x"9e";
when "00" & x"9b0" => data <= x"85";
when "00" & x"9b1" => data <= x"4c";
when "00" & x"9b2" => data <= x"bc";
when "00" & x"9b3" => data <= x"89";
when "00" & x"9b4" => data <= x"f0";
when "00" & x"9b5" => data <= x"a2";
when "00" & x"9b6" => data <= x"20";
when "00" & x"9b7" => data <= x"19";
when "00" & x"9b8" => data <= x"82";
when "00" & x"9b9" => data <= x"20";
when "00" & x"9ba" => data <= x"7f";
when "00" & x"9bb" => data <= x"85";
when "00" & x"9bc" => data <= x"98";
when "00" & x"9bd" => data <= x"90";
when "00" & x"9be" => data <= x"f5";
when "00" & x"9bf" => data <= x"84";
when "00" & x"9c0" => data <= x"b0";
when "00" & x"9c1" => data <= x"ac";
when "00" & x"9c2" => data <= x"05";
when "00" & x"9c3" => data <= x"0f";
when "00" & x"9c4" => data <= x"c4";
when "00" & x"9c5" => data <= x"b0";
when "00" & x"9c6" => data <= x"f0";
when "00" & x"9c7" => data <= x"0f";
when "00" & x"9c8" => data <= x"b9";
when "00" & x"9c9" => data <= x"07";
when "00" & x"9ca" => data <= x"0e";
when "00" & x"9cb" => data <= x"99";
when "00" & x"9cc" => data <= x"0f";
when "00" & x"9cd" => data <= x"0e";
when "00" & x"9ce" => data <= x"b9";
when "00" & x"9cf" => data <= x"07";
when "00" & x"9d0" => data <= x"0f";
when "00" & x"9d1" => data <= x"99";
when "00" & x"9d2" => data <= x"0f";
when "00" & x"9d3" => data <= x"0f";
when "00" & x"9d4" => data <= x"88";
when "00" & x"9d5" => data <= x"b0";
when "00" & x"9d6" => data <= x"ed";
when "00" & x"9d7" => data <= x"a2";
when "00" & x"9d8" => data <= x"00";
when "00" & x"9d9" => data <= x"20";
when "00" & x"9da" => data <= x"17";
when "00" & x"9db" => data <= x"8a";
when "00" & x"9dc" => data <= x"b5";
when "00" & x"9dd" => data <= x"c7";
when "00" & x"9de" => data <= x"99";
when "00" & x"9df" => data <= x"08";
when "00" & x"9e0" => data <= x"0e";
when "00" & x"9e1" => data <= x"c8";
when "00" & x"9e2" => data <= x"e8";
when "00" & x"9e3" => data <= x"e0";
when "00" & x"9e4" => data <= x"08";
when "00" & x"9e5" => data <= x"d0";
when "00" & x"9e6" => data <= x"f5";
when "00" & x"9e7" => data <= x"b5";
when "00" & x"9e8" => data <= x"bd";
when "00" & x"9e9" => data <= x"88";
when "00" & x"9ea" => data <= x"99";
when "00" & x"9eb" => data <= x"08";
when "00" & x"9ec" => data <= x"0f";
when "00" & x"9ed" => data <= x"ca";
when "00" & x"9ee" => data <= x"d0";
when "00" & x"9ef" => data <= x"f7";
when "00" & x"9f0" => data <= x"20";
when "00" & x"9f1" => data <= x"fc";
when "00" & x"9f2" => data <= x"82";
when "00" & x"9f3" => data <= x"98";
when "00" & x"9f4" => data <= x"48";
when "00" & x"9f5" => data <= x"ac";
when "00" & x"9f6" => data <= x"05";
when "00" & x"9f7" => data <= x"0f";
when "00" & x"9f8" => data <= x"20";
when "00" & x"9f9" => data <= x"10";
when "00" & x"9fa" => data <= x"82";
when "00" & x"9fb" => data <= x"8c";
when "00" & x"9fc" => data <= x"05";
when "00" & x"9fd" => data <= x"0f";
when "00" & x"9fe" => data <= x"20";
when "00" & x"9ff" => data <= x"b4";
when "00" & x"a00" => data <= x"8a";
when "00" & x"a01" => data <= x"68";
when "00" & x"a02" => data <= x"a8";
when "00" & x"a03" => data <= x"60";
when "00" & x"a04" => data <= x"20";
when "00" & x"a05" => data <= x"33";
when "00" & x"a06" => data <= x"80";
when "00" & x"a07" => data <= x"be";
when "00" & x"a08" => data <= x"43";
when "00" & x"a09" => data <= x"61";
when "00" & x"a0a" => data <= x"74";
when "00" & x"a0b" => data <= x"61";
when "00" & x"a0c" => data <= x"6c";
when "00" & x"a0d" => data <= x"6f";
when "00" & x"a0e" => data <= x"67";
when "00" & x"a0f" => data <= x"75";
when "00" & x"a10" => data <= x"65";
when "00" & x"a11" => data <= x"20";
when "00" & x"a12" => data <= x"66";
when "00" & x"a13" => data <= x"75";
when "00" & x"a14" => data <= x"6c";
when "00" & x"a15" => data <= x"6c";
when "00" & x"a16" => data <= x"00";
when "00" & x"a17" => data <= x"ad";
when "00" & x"a18" => data <= x"76";
when "00" & x"a19" => data <= x"10";
when "00" & x"a1a" => data <= x"29";
when "00" & x"a1b" => data <= x"03";
when "00" & x"a1c" => data <= x"0a";
when "00" & x"a1d" => data <= x"0a";
when "00" & x"a1e" => data <= x"45";
when "00" & x"a1f" => data <= x"c6";
when "00" & x"a20" => data <= x"29";
when "00" & x"a21" => data <= x"fc";
when "00" & x"a22" => data <= x"45";
when "00" & x"a23" => data <= x"c6";
when "00" & x"a24" => data <= x"0a";
when "00" & x"a25" => data <= x"0a";
when "00" & x"a26" => data <= x"4d";
when "00" & x"a27" => data <= x"74";
when "00" & x"a28" => data <= x"10";
when "00" & x"a29" => data <= x"29";
when "00" & x"a2a" => data <= x"fc";
when "00" & x"a2b" => data <= x"4d";
when "00" & x"a2c" => data <= x"74";
when "00" & x"a2d" => data <= x"10";
when "00" & x"a2e" => data <= x"0a";
when "00" & x"a2f" => data <= x"0a";
when "00" & x"a30" => data <= x"45";
when "00" & x"a31" => data <= x"c4";
when "00" & x"a32" => data <= x"29";
when "00" & x"a33" => data <= x"fc";
when "00" & x"a34" => data <= x"45";
when "00" & x"a35" => data <= x"c4";
when "00" & x"a36" => data <= x"85";
when "00" & x"a37" => data <= x"c4";
when "00" & x"a38" => data <= x"60";
when "00" & x"a39" => data <= x"a9";
when "00" & x"a3a" => data <= x"01";
when "00" & x"a3b" => data <= x"8d";
when "00" & x"a3c" => data <= x"c8";
when "00" & x"a3d" => data <= x"10";
when "00" & x"a3e" => data <= x"60";
when "00" & x"a3f" => data <= x"a9";
when "00" & x"a40" => data <= x"00";
when "00" & x"a41" => data <= x"8d";
when "00" & x"a42" => data <= x"75";
when "00" & x"a43" => data <= x"10";
when "00" & x"a44" => data <= x"a5";
when "00" & x"a45" => data <= x"c4";
when "00" & x"a46" => data <= x"20";
when "00" & x"a47" => data <= x"ff";
when "00" & x"a48" => data <= x"81";
when "00" & x"a49" => data <= x"c9";
when "00" & x"a4a" => data <= x"03";
when "00" & x"a4b" => data <= x"d0";
when "00" & x"a4c" => data <= x"05";
when "00" & x"a4d" => data <= x"a9";
when "00" & x"a4e" => data <= x"ff";
when "00" & x"a4f" => data <= x"8d";
when "00" & x"a50" => data <= x"75";
when "00" & x"a51" => data <= x"10";
when "00" & x"a52" => data <= x"8d";
when "00" & x"a53" => data <= x"74";
when "00" & x"a54" => data <= x"10";
when "00" & x"a55" => data <= x"60";
when "00" & x"a56" => data <= x"a9";
when "00" & x"a57" => data <= x"00";
when "00" & x"a58" => data <= x"8d";
when "00" & x"a59" => data <= x"77";
when "00" & x"a5a" => data <= x"10";
when "00" & x"a5b" => data <= x"a5";
when "00" & x"a5c" => data <= x"c4";
when "00" & x"a5d" => data <= x"20";
when "00" & x"a5e" => data <= x"fb";
when "00" & x"a5f" => data <= x"81";
when "00" & x"a60" => data <= x"c9";
when "00" & x"a61" => data <= x"03";
when "00" & x"a62" => data <= x"d0";
when "00" & x"a63" => data <= x"05";
when "00" & x"a64" => data <= x"a9";
when "00" & x"a65" => data <= x"ff";
when "00" & x"a66" => data <= x"8d";
when "00" & x"a67" => data <= x"77";
when "00" & x"a68" => data <= x"10";
when "00" & x"a69" => data <= x"8d";
when "00" & x"a6a" => data <= x"76";
when "00" & x"a6b" => data <= x"10";
when "00" & x"a6c" => data <= x"60";
when "00" & x"a6d" => data <= x"20";
when "00" & x"a6e" => data <= x"62";
when "00" & x"a6f" => data <= x"82";
when "00" & x"a70" => data <= x"20";
when "00" & x"a71" => data <= x"bf";
when "00" & x"a72" => data <= x"86";
when "00" & x"a73" => data <= x"d0";
when "00" & x"a74" => data <= x"03";
when "00" & x"a75" => data <= x"4c";
when "00" & x"a76" => data <= x"06";
when "00" & x"a77" => data <= x"9a";
when "00" & x"a78" => data <= x"20";
when "00" & x"a79" => data <= x"fe";
when "00" & x"a7a" => data <= x"80";
when "00" & x"a7b" => data <= x"98";
when "00" & x"a7c" => data <= x"48";
when "00" & x"a7d" => data <= x"20";
when "00" & x"a7e" => data <= x"96";
when "00" & x"a7f" => data <= x"82";
when "00" & x"a80" => data <= x"b0";
when "00" & x"a81" => data <= x"03";
when "00" & x"a82" => data <= x"4c";
when "00" & x"a83" => data <= x"76";
when "00" & x"a84" => data <= x"82";
when "00" & x"a85" => data <= x"20";
when "00" & x"a86" => data <= x"4c";
when "00" & x"a87" => data <= x"98";
when "00" & x"a88" => data <= x"84";
when "00" & x"a89" => data <= x"b3";
when "00" & x"a8a" => data <= x"68";
when "00" & x"a8b" => data <= x"a8";
when "00" & x"a8c" => data <= x"20";
when "00" & x"a8d" => data <= x"bf";
when "00" & x"a8e" => data <= x"86";
when "00" & x"a8f" => data <= x"f0";
when "00" & x"a90" => data <= x"e4";
when "00" & x"a91" => data <= x"20";
when "00" & x"a92" => data <= x"fe";
when "00" & x"a93" => data <= x"80";
when "00" & x"a94" => data <= x"20";
when "00" & x"a95" => data <= x"96";
when "00" & x"a96" => data <= x"82";
when "00" & x"a97" => data <= x"90";
when "00" & x"a98" => data <= x"0b";
when "00" & x"a99" => data <= x"20";
when "00" & x"a9a" => data <= x"2b";
when "00" & x"a9b" => data <= x"80";
when "00" & x"a9c" => data <= x"c4";
when "00" & x"a9d" => data <= x"65";
when "00" & x"a9e" => data <= x"78";
when "00" & x"a9f" => data <= x"69";
when "00" & x"aa0" => data <= x"73";
when "00" & x"aa1" => data <= x"74";
when "00" & x"aa2" => data <= x"73";
when "00" & x"aa3" => data <= x"00";
when "00" & x"aa4" => data <= x"a4";
when "00" & x"aa5" => data <= x"b3";
when "00" & x"aa6" => data <= x"20";
when "00" & x"aa7" => data <= x"10";
when "00" & x"aa8" => data <= x"82";
when "00" & x"aa9" => data <= x"a2";
when "00" & x"aaa" => data <= x"07";
when "00" & x"aab" => data <= x"b5";
when "00" & x"aac" => data <= x"c7";
when "00" & x"aad" => data <= x"99";
when "00" & x"aae" => data <= x"07";
when "00" & x"aaf" => data <= x"0e";
when "00" & x"ab0" => data <= x"88";
when "00" & x"ab1" => data <= x"ca";
when "00" & x"ab2" => data <= x"10";
when "00" & x"ab3" => data <= x"f7";
when "00" & x"ab4" => data <= x"18";
when "00" & x"ab5" => data <= x"f8";
when "00" & x"ab6" => data <= x"ad";
when "00" & x"ab7" => data <= x"04";
when "00" & x"ab8" => data <= x"0f";
when "00" & x"ab9" => data <= x"69";
when "00" & x"aba" => data <= x"01";
when "00" & x"abb" => data <= x"d8";
when "00" & x"abc" => data <= x"8d";
when "00" & x"abd" => data <= x"04";
when "00" & x"abe" => data <= x"0f";
when "00" & x"abf" => data <= x"4c";
when "00" & x"ac0" => data <= x"55";
when "00" & x"ac1" => data <= x"af";
when "00" & x"ac2" => data <= x"a9";
when "00" & x"ac3" => data <= x"ff";
when "00" & x"ac4" => data <= x"20";
when "00" & x"ac5" => data <= x"9e";
when "00" & x"ac6" => data <= x"06";
when "00" & x"ac7" => data <= x"ad";
when "00" & x"ac8" => data <= x"e3";
when "00" & x"ac9" => data <= x"fe";
when "00" & x"aca" => data <= x"a9";
when "00" & x"acb" => data <= x"00";
when "00" & x"acc" => data <= x"20";
when "00" & x"acd" => data <= x"95";
when "00" & x"ace" => data <= x"06";
when "00" & x"acf" => data <= x"a8";
when "00" & x"ad0" => data <= x"b1";
when "00" & x"ad1" => data <= x"fd";
when "00" & x"ad2" => data <= x"20";
when "00" & x"ad3" => data <= x"95";
when "00" & x"ad4" => data <= x"06";
when "00" & x"ad5" => data <= x"c8";
when "00" & x"ad6" => data <= x"b1";
when "00" & x"ad7" => data <= x"fd";
when "00" & x"ad8" => data <= x"20";
when "00" & x"ad9" => data <= x"95";
when "00" & x"ada" => data <= x"06";
when "00" & x"adb" => data <= x"aa";
when "00" & x"adc" => data <= x"d0";
when "00" & x"add" => data <= x"f7";
when "00" & x"ade" => data <= x"a2";
when "00" & x"adf" => data <= x"ff";
when "00" & x"ae0" => data <= x"9a";
when "00" & x"ae1" => data <= x"58";
when "00" & x"ae2" => data <= x"2c";
when "00" & x"ae3" => data <= x"e0";
when "00" & x"ae4" => data <= x"fe";
when "00" & x"ae5" => data <= x"10";
when "00" & x"ae6" => data <= x"06";
when "00" & x"ae7" => data <= x"ad";
when "00" & x"ae8" => data <= x"e1";
when "00" & x"ae9" => data <= x"fe";
when "00" & x"aea" => data <= x"20";
when "00" & x"aeb" => data <= x"ee";
when "00" & x"aec" => data <= x"ff";
when "00" & x"aed" => data <= x"2c";
when "00" & x"aee" => data <= x"e2";
when "00" & x"aef" => data <= x"fe";
when "00" & x"af0" => data <= x"10";
when "00" & x"af1" => data <= x"f0";
when "00" & x"af2" => data <= x"2c";
when "00" & x"af3" => data <= x"e0";
when "00" & x"af4" => data <= x"fe";
when "00" & x"af5" => data <= x"30";
when "00" & x"af6" => data <= x"f0";
when "00" & x"af7" => data <= x"ae";
when "00" & x"af8" => data <= x"e3";
when "00" & x"af9" => data <= x"fe";
when "00" & x"afa" => data <= x"86";
when "00" & x"afb" => data <= x"51";
when "00" & x"afc" => data <= x"6c";
when "00" & x"afd" => data <= x"00";
when "00" & x"afe" => data <= x"05";
when "00" & x"aff" => data <= x"00";
when "00" & x"b00" => data <= x"80";
when "00" & x"b01" => data <= x"00";
when "00" & x"b02" => data <= x"00";
when "00" & x"b03" => data <= x"4c";
when "00" & x"b04" => data <= x"84";
when "00" & x"b05" => data <= x"04";
when "00" & x"b06" => data <= x"4c";
when "00" & x"b07" => data <= x"a7";
when "00" & x"b08" => data <= x"06";
when "00" & x"b09" => data <= x"c9";
when "00" & x"b0a" => data <= x"80";
when "00" & x"b0b" => data <= x"90";
when "00" & x"b0c" => data <= x"2b";
when "00" & x"b0d" => data <= x"c9";
when "00" & x"b0e" => data <= x"c0";
when "00" & x"b0f" => data <= x"b0";
when "00" & x"b10" => data <= x"1a";
when "00" & x"b11" => data <= x"09";
when "00" & x"b12" => data <= x"40";
when "00" & x"b13" => data <= x"c5";
when "00" & x"b14" => data <= x"15";
when "00" & x"b15" => data <= x"d0";
when "00" & x"b16" => data <= x"20";
when "00" & x"b17" => data <= x"08";
when "00" & x"b18" => data <= x"78";
when "00" & x"b19" => data <= x"a9";
when "00" & x"b1a" => data <= x"05";
when "00" & x"b1b" => data <= x"20";
when "00" & x"b1c" => data <= x"9e";
when "00" & x"b1d" => data <= x"06";
when "00" & x"b1e" => data <= x"a5";
when "00" & x"b1f" => data <= x"15";
when "00" & x"b20" => data <= x"20";
when "00" & x"b21" => data <= x"9e";
when "00" & x"b22" => data <= x"06";
when "00" & x"b23" => data <= x"28";
when "00" & x"b24" => data <= x"a9";
when "00" & x"b25" => data <= x"80";
when "00" & x"b26" => data <= x"85";
when "00" & x"b27" => data <= x"15";
when "00" & x"b28" => data <= x"85";
when "00" & x"b29" => data <= x"14";
when "00" & x"b2a" => data <= x"60";
when "00" & x"b2b" => data <= x"06";
when "00" & x"b2c" => data <= x"14";
when "00" & x"b2d" => data <= x"b0";
when "00" & x"b2e" => data <= x"06";
when "00" & x"b2f" => data <= x"c5";
when "00" & x"b30" => data <= x"15";
when "00" & x"b31" => data <= x"f0";
when "00" & x"b32" => data <= x"04";
when "00" & x"b33" => data <= x"18";
when "00" & x"b34" => data <= x"60";
when "00" & x"b35" => data <= x"85";
when "00" & x"b36" => data <= x"15";
when "00" & x"b37" => data <= x"60";
when "00" & x"b38" => data <= x"08";
when "00" & x"b39" => data <= x"78";
when "00" & x"b3a" => data <= x"84";
when "00" & x"b3b" => data <= x"13";
when "00" & x"b3c" => data <= x"86";
when "00" & x"b3d" => data <= x"12";
when "00" & x"b3e" => data <= x"20";
when "00" & x"b3f" => data <= x"9e";
when "00" & x"b40" => data <= x"06";
when "00" & x"b41" => data <= x"aa";
when "00" & x"b42" => data <= x"a0";
when "00" & x"b43" => data <= x"03";
when "00" & x"b44" => data <= x"a5";
when "00" & x"b45" => data <= x"15";
when "00" & x"b46" => data <= x"20";
when "00" & x"b47" => data <= x"9e";
when "00" & x"b48" => data <= x"06";
when "00" & x"b49" => data <= x"b1";
when "00" & x"b4a" => data <= x"12";
when "00" & x"b4b" => data <= x"20";
when "00" & x"b4c" => data <= x"9e";
when "00" & x"b4d" => data <= x"06";
when "00" & x"b4e" => data <= x"88";
when "00" & x"b4f" => data <= x"10";
when "00" & x"b50" => data <= x"f8";
when "00" & x"b51" => data <= x"a0";
when "00" & x"b52" => data <= x"18";
when "00" & x"b53" => data <= x"8c";
when "00" & x"b54" => data <= x"e0";
when "00" & x"b55" => data <= x"fe";
when "00" & x"b56" => data <= x"bd";
when "00" & x"b57" => data <= x"18";
when "00" & x"b58" => data <= x"05";
when "00" & x"b59" => data <= x"8d";
when "00" & x"b5a" => data <= x"e0";
when "00" & x"b5b" => data <= x"fe";
when "00" & x"b5c" => data <= x"4a";
when "00" & x"b5d" => data <= x"4a";
when "00" & x"b5e" => data <= x"90";
when "00" & x"b5f" => data <= x"06";
when "00" & x"b60" => data <= x"2c";
when "00" & x"b61" => data <= x"e5";
when "00" & x"b62" => data <= x"fe";
when "00" & x"b63" => data <= x"2c";
when "00" & x"b64" => data <= x"e5";
when "00" & x"b65" => data <= x"fe";
when "00" & x"b66" => data <= x"20";
when "00" & x"b67" => data <= x"9e";
when "00" & x"b68" => data <= x"06";
when "00" & x"b69" => data <= x"2c";
when "00" & x"b6a" => data <= x"e6";
when "00" & x"b6b" => data <= x"fe";
when "00" & x"b6c" => data <= x"50";
when "00" & x"b6d" => data <= x"fb";
when "00" & x"b6e" => data <= x"b0";
when "00" & x"b6f" => data <= x"0d";
when "00" & x"b70" => data <= x"e0";
when "00" & x"b71" => data <= x"04";
when "00" & x"b72" => data <= x"d0";
when "00" & x"b73" => data <= x"11";
when "00" & x"b74" => data <= x"20";
when "00" & x"b75" => data <= x"14";
when "00" & x"b76" => data <= x"04";
when "00" & x"b77" => data <= x"20";
when "00" & x"b78" => data <= x"95";
when "00" & x"b79" => data <= x"06";
when "00" & x"b7a" => data <= x"4c";
when "00" & x"b7b" => data <= x"32";
when "00" & x"b7c" => data <= x"00";
when "00" & x"b7d" => data <= x"4a";
when "00" & x"b7e" => data <= x"90";
when "00" & x"b7f" => data <= x"05";
when "00" & x"b80" => data <= x"a0";
when "00" & x"b81" => data <= x"88";
when "00" & x"b82" => data <= x"8c";
when "00" & x"b83" => data <= x"e0";
when "00" & x"b84" => data <= x"fe";
when "00" & x"b85" => data <= x"28";
when "00" & x"b86" => data <= x"60";
when "00" & x"b87" => data <= x"58";
when "00" & x"b88" => data <= x"b0";
when "00" & x"b89" => data <= x"11";
when "00" & x"b8a" => data <= x"d0";
when "00" & x"b8b" => data <= x"03";
when "00" & x"b8c" => data <= x"4c";
when "00" & x"b8d" => data <= x"9c";
when "00" & x"b8e" => data <= x"05";
when "00" & x"b8f" => data <= x"a2";
when "00" & x"b90" => data <= x"00";
when "00" & x"b91" => data <= x"a0";
when "00" & x"b92" => data <= x"ff";
when "00" & x"b93" => data <= x"a9";
when "00" & x"b94" => data <= x"fd";
when "00" & x"b95" => data <= x"20";
when "00" & x"b96" => data <= x"f4";
when "00" & x"b97" => data <= x"ff";
when "00" & x"b98" => data <= x"8a";
when "00" & x"b99" => data <= x"f0";
when "00" & x"b9a" => data <= x"d9";
when "00" & x"b9b" => data <= x"a9";
when "00" & x"b9c" => data <= x"ff";
when "00" & x"b9d" => data <= x"20";
when "00" & x"b9e" => data <= x"06";
when "00" & x"b9f" => data <= x"04";
when "00" & x"ba0" => data <= x"90";
when "00" & x"ba1" => data <= x"f9";
when "00" & x"ba2" => data <= x"20";
when "00" & x"ba3" => data <= x"d2";
when "00" & x"ba4" => data <= x"04";
when "00" & x"ba5" => data <= x"a9";
when "00" & x"ba6" => data <= x"07";
when "00" & x"ba7" => data <= x"20";
when "00" & x"ba8" => data <= x"cb";
when "00" & x"ba9" => data <= x"04";
when "00" & x"baa" => data <= x"a0";
when "00" & x"bab" => data <= x"00";
when "00" & x"bac" => data <= x"84";
when "00" & x"bad" => data <= x"00";
when "00" & x"bae" => data <= x"b1";
when "00" & x"baf" => data <= x"00";
when "00" & x"bb0" => data <= x"8d";
when "00" & x"bb1" => data <= x"e5";
when "00" & x"bb2" => data <= x"fe";
when "00" & x"bb3" => data <= x"ea";
when "00" & x"bb4" => data <= x"ea";
when "00" & x"bb5" => data <= x"ea";
when "00" & x"bb6" => data <= x"c8";
when "00" & x"bb7" => data <= x"d0";
when "00" & x"bb8" => data <= x"f5";
when "00" & x"bb9" => data <= x"e6";
when "00" & x"bba" => data <= x"54";
when "00" & x"bbb" => data <= x"d0";
when "00" & x"bbc" => data <= x"06";
when "00" & x"bbd" => data <= x"e6";
when "00" & x"bbe" => data <= x"55";
when "00" & x"bbf" => data <= x"d0";
when "00" & x"bc0" => data <= x"02";
when "00" & x"bc1" => data <= x"e6";
when "00" & x"bc2" => data <= x"56";
when "00" & x"bc3" => data <= x"e6";
when "00" & x"bc4" => data <= x"01";
when "00" & x"bc5" => data <= x"24";
when "00" & x"bc6" => data <= x"01";
when "00" & x"bc7" => data <= x"50";
when "00" & x"bc8" => data <= x"dc";
when "00" & x"bc9" => data <= x"20";
when "00" & x"bca" => data <= x"d2";
when "00" & x"bcb" => data <= x"04";
when "00" & x"bcc" => data <= x"a9";
when "00" & x"bcd" => data <= x"04";
when "00" & x"bce" => data <= x"a0";
when "00" & x"bcf" => data <= x"00";
when "00" & x"bd0" => data <= x"a2";
when "00" & x"bd1" => data <= x"53";
when "00" & x"bd2" => data <= x"4c";
when "00" & x"bd3" => data <= x"06";
when "00" & x"bd4" => data <= x"04";
when "00" & x"bd5" => data <= x"a9";
when "00" & x"bd6" => data <= x"80";
when "00" & x"bd7" => data <= x"85";
when "00" & x"bd8" => data <= x"54";
when "00" & x"bd9" => data <= x"85";
when "00" & x"bda" => data <= x"01";
when "00" & x"bdb" => data <= x"a9";
when "00" & x"bdc" => data <= x"20";
when "00" & x"bdd" => data <= x"2d";
when "00" & x"bde" => data <= x"06";
when "00" & x"bdf" => data <= x"80";
when "00" & x"be0" => data <= x"a8";
when "00" & x"be1" => data <= x"84";
when "00" & x"be2" => data <= x"53";
when "00" & x"be3" => data <= x"f0";
when "00" & x"be4" => data <= x"19";
when "00" & x"be5" => data <= x"ae";
when "00" & x"be6" => data <= x"07";
when "00" & x"be7" => data <= x"80";
when "00" & x"be8" => data <= x"e8";
when "00" & x"be9" => data <= x"bd";
when "00" & x"bea" => data <= x"00";
when "00" & x"beb" => data <= x"80";
when "00" & x"bec" => data <= x"d0";
when "00" & x"bed" => data <= x"fa";
when "00" & x"bee" => data <= x"bd";
when "00" & x"bef" => data <= x"01";
when "00" & x"bf0" => data <= x"80";
when "00" & x"bf1" => data <= x"85";
when "00" & x"bf2" => data <= x"53";
when "00" & x"bf3" => data <= x"bd";
when "00" & x"bf4" => data <= x"02";
when "00" & x"bf5" => data <= x"80";
when "00" & x"bf6" => data <= x"85";
when "00" & x"bf7" => data <= x"54";
when "00" & x"bf8" => data <= x"bc";
when "00" & x"bf9" => data <= x"03";
when "00" & x"bfa" => data <= x"80";
when "00" & x"bfb" => data <= x"bd";
when "00" & x"bfc" => data <= x"04";
when "00" & x"bfd" => data <= x"80";
when "00" & x"bfe" => data <= x"85";
when "00" & x"bff" => data <= x"56";
when "00" & x"c00" => data <= x"84";
when "00" & x"c01" => data <= x"55";
when "00" & x"c02" => data <= x"60";
when "00" & x"c03" => data <= x"37";
when "00" & x"c04" => data <= x"05";
when "00" & x"c05" => data <= x"96";
when "00" & x"c06" => data <= x"05";
when "00" & x"c07" => data <= x"f2";
when "00" & x"c08" => data <= x"05";
when "00" & x"c09" => data <= x"07";
when "00" & x"c0a" => data <= x"06";
when "00" & x"c0b" => data <= x"27";
when "00" & x"c0c" => data <= x"06";
when "00" & x"c0d" => data <= x"68";
when "00" & x"c0e" => data <= x"06";
when "00" & x"c0f" => data <= x"5e";
when "00" & x"c10" => data <= x"05";
when "00" & x"c11" => data <= x"2d";
when "00" & x"c12" => data <= x"05";
when "00" & x"c13" => data <= x"20";
when "00" & x"c14" => data <= x"05";
when "00" & x"c15" => data <= x"42";
when "00" & x"c16" => data <= x"05";
when "00" & x"c17" => data <= x"a9";
when "00" & x"c18" => data <= x"05";
when "00" & x"c19" => data <= x"d1";
when "00" & x"c1a" => data <= x"05";
when "00" & x"c1b" => data <= x"86";
when "00" & x"c1c" => data <= x"88";
when "00" & x"c1d" => data <= x"96";
when "00" & x"c1e" => data <= x"98";
when "00" & x"c1f" => data <= x"18";
when "00" & x"c20" => data <= x"18";
when "00" & x"c21" => data <= x"82";
when "00" & x"c22" => data <= x"18";
when "00" & x"c23" => data <= x"20";
when "00" & x"c24" => data <= x"c5";
when "00" & x"c25" => data <= x"06";
when "00" & x"c26" => data <= x"a8";
when "00" & x"c27" => data <= x"20";
when "00" & x"c28" => data <= x"c5";
when "00" & x"c29" => data <= x"06";
when "00" & x"c2a" => data <= x"20";
when "00" & x"c2b" => data <= x"d4";
when "00" & x"c2c" => data <= x"ff";
when "00" & x"c2d" => data <= x"4c";
when "00" & x"c2e" => data <= x"9c";
when "00" & x"c2f" => data <= x"05";
when "00" & x"c30" => data <= x"20";
when "00" & x"c31" => data <= x"c5";
when "00" & x"c32" => data <= x"06";
when "00" & x"c33" => data <= x"a8";
when "00" & x"c34" => data <= x"20";
when "00" & x"c35" => data <= x"d7";
when "00" & x"c36" => data <= x"ff";
when "00" & x"c37" => data <= x"4c";
when "00" & x"c38" => data <= x"3a";
when "00" & x"c39" => data <= x"05";
when "00" & x"c3a" => data <= x"20";
when "00" & x"c3b" => data <= x"e0";
when "00" & x"c3c" => data <= x"ff";
when "00" & x"c3d" => data <= x"6a";
when "00" & x"c3e" => data <= x"20";
when "00" & x"c3f" => data <= x"95";
when "00" & x"c40" => data <= x"06";
when "00" & x"c41" => data <= x"2a";
when "00" & x"c42" => data <= x"4c";
when "00" & x"c43" => data <= x"9e";
when "00" & x"c44" => data <= x"05";
when "00" & x"c45" => data <= x"20";
when "00" & x"c46" => data <= x"c5";
when "00" & x"c47" => data <= x"06";
when "00" & x"c48" => data <= x"f0";
when "00" & x"c49" => data <= x"0b";
when "00" & x"c4a" => data <= x"48";
when "00" & x"c4b" => data <= x"20";
when "00" & x"c4c" => data <= x"82";
when "00" & x"c4d" => data <= x"05";
when "00" & x"c4e" => data <= x"68";
when "00" & x"c4f" => data <= x"20";
when "00" & x"c50" => data <= x"ce";
when "00" & x"c51" => data <= x"ff";
when "00" & x"c52" => data <= x"4c";
when "00" & x"c53" => data <= x"9e";
when "00" & x"c54" => data <= x"05";
when "00" & x"c55" => data <= x"20";
when "00" & x"c56" => data <= x"c5";
when "00" & x"c57" => data <= x"06";
when "00" & x"c58" => data <= x"a8";
when "00" & x"c59" => data <= x"a9";
when "00" & x"c5a" => data <= x"00";
when "00" & x"c5b" => data <= x"20";
when "00" & x"c5c" => data <= x"ce";
when "00" & x"c5d" => data <= x"ff";
when "00" & x"c5e" => data <= x"4c";
when "00" & x"c5f" => data <= x"9c";
when "00" & x"c60" => data <= x"05";
when "00" & x"c61" => data <= x"20";
when "00" & x"c62" => data <= x"c5";
when "00" & x"c63" => data <= x"06";
when "00" & x"c64" => data <= x"a8";
when "00" & x"c65" => data <= x"a2";
when "00" & x"c66" => data <= x"04";
when "00" & x"c67" => data <= x"20";
when "00" & x"c68" => data <= x"c5";
when "00" & x"c69" => data <= x"06";
when "00" & x"c6a" => data <= x"95";
when "00" & x"c6b" => data <= x"ff";
when "00" & x"c6c" => data <= x"ca";
when "00" & x"c6d" => data <= x"d0";
when "00" & x"c6e" => data <= x"f8";
when "00" & x"c6f" => data <= x"20";
when "00" & x"c70" => data <= x"c5";
when "00" & x"c71" => data <= x"06";
when "00" & x"c72" => data <= x"20";
when "00" & x"c73" => data <= x"da";
when "00" & x"c74" => data <= x"ff";
when "00" & x"c75" => data <= x"20";
when "00" & x"c76" => data <= x"95";
when "00" & x"c77" => data <= x"06";
when "00" & x"c78" => data <= x"a2";
when "00" & x"c79" => data <= x"03";
when "00" & x"c7a" => data <= x"b5";
when "00" & x"c7b" => data <= x"00";
when "00" & x"c7c" => data <= x"20";
when "00" & x"c7d" => data <= x"95";
when "00" & x"c7e" => data <= x"06";
when "00" & x"c7f" => data <= x"ca";
when "00" & x"c80" => data <= x"10";
when "00" & x"c81" => data <= x"f8";
when "00" & x"c82" => data <= x"4c";
when "00" & x"c83" => data <= x"36";
when "00" & x"c84" => data <= x"00";
when "00" & x"c85" => data <= x"a2";
when "00" & x"c86" => data <= x"00";
when "00" & x"c87" => data <= x"a0";
when "00" & x"c88" => data <= x"00";
when "00" & x"c89" => data <= x"20";
when "00" & x"c8a" => data <= x"c5";
when "00" & x"c8b" => data <= x"06";
when "00" & x"c8c" => data <= x"99";
when "00" & x"c8d" => data <= x"00";
when "00" & x"c8e" => data <= x"07";
when "00" & x"c8f" => data <= x"c8";
when "00" & x"c90" => data <= x"f0";
when "00" & x"c91" => data <= x"04";
when "00" & x"c92" => data <= x"c9";
when "00" & x"c93" => data <= x"0d";
when "00" & x"c94" => data <= x"d0";
when "00" & x"c95" => data <= x"f3";
when "00" & x"c96" => data <= x"a0";
when "00" & x"c97" => data <= x"07";
when "00" & x"c98" => data <= x"60";
when "00" & x"c99" => data <= x"20";
when "00" & x"c9a" => data <= x"82";
when "00" & x"c9b" => data <= x"05";
when "00" & x"c9c" => data <= x"20";
when "00" & x"c9d" => data <= x"f7";
when "00" & x"c9e" => data <= x"ff";
when "00" & x"c9f" => data <= x"a9";
when "00" & x"ca0" => data <= x"7f";
when "00" & x"ca1" => data <= x"2c";
when "00" & x"ca2" => data <= x"e2";
when "00" & x"ca3" => data <= x"fe";
when "00" & x"ca4" => data <= x"50";
when "00" & x"ca5" => data <= x"fb";
when "00" & x"ca6" => data <= x"8d";
when "00" & x"ca7" => data <= x"e3";
when "00" & x"ca8" => data <= x"fe";
when "00" & x"ca9" => data <= x"4c";
when "00" & x"caa" => data <= x"36";
when "00" & x"cab" => data <= x"00";
when "00" & x"cac" => data <= x"a2";
when "00" & x"cad" => data <= x"10";
when "00" & x"cae" => data <= x"20";
when "00" & x"caf" => data <= x"c5";
when "00" & x"cb0" => data <= x"06";
when "00" & x"cb1" => data <= x"95";
when "00" & x"cb2" => data <= x"01";
when "00" & x"cb3" => data <= x"ca";
when "00" & x"cb4" => data <= x"d0";
when "00" & x"cb5" => data <= x"f8";
when "00" & x"cb6" => data <= x"20";
when "00" & x"cb7" => data <= x"82";
when "00" & x"cb8" => data <= x"05";
when "00" & x"cb9" => data <= x"86";
when "00" & x"cba" => data <= x"00";
when "00" & x"cbb" => data <= x"84";
when "00" & x"cbc" => data <= x"01";
when "00" & x"cbd" => data <= x"a0";
when "00" & x"cbe" => data <= x"00";
when "00" & x"cbf" => data <= x"20";
when "00" & x"cc0" => data <= x"c5";
when "00" & x"cc1" => data <= x"06";
when "00" & x"cc2" => data <= x"20";
when "00" & x"cc3" => data <= x"dd";
when "00" & x"cc4" => data <= x"ff";
when "00" & x"cc5" => data <= x"20";
when "00" & x"cc6" => data <= x"95";
when "00" & x"cc7" => data <= x"06";
when "00" & x"cc8" => data <= x"a2";
when "00" & x"cc9" => data <= x"10";
when "00" & x"cca" => data <= x"b5";
when "00" & x"ccb" => data <= x"01";
when "00" & x"ccc" => data <= x"20";
when "00" & x"ccd" => data <= x"95";
when "00" & x"cce" => data <= x"06";
when "00" & x"ccf" => data <= x"ca";
when "00" & x"cd0" => data <= x"d0";
when "00" & x"cd1" => data <= x"f8";
when "00" & x"cd2" => data <= x"f0";
when "00" & x"cd3" => data <= x"d5";
when "00" & x"cd4" => data <= x"a2";
when "00" & x"cd5" => data <= x"0d";
when "00" & x"cd6" => data <= x"20";
when "00" & x"cd7" => data <= x"c5";
when "00" & x"cd8" => data <= x"06";
when "00" & x"cd9" => data <= x"95";
when "00" & x"cda" => data <= x"ff";
when "00" & x"cdb" => data <= x"ca";
when "00" & x"cdc" => data <= x"d0";
when "00" & x"cdd" => data <= x"f8";
when "00" & x"cde" => data <= x"20";
when "00" & x"cdf" => data <= x"c5";
when "00" & x"ce0" => data <= x"06";
when "00" & x"ce1" => data <= x"a0";
when "00" & x"ce2" => data <= x"00";
when "00" & x"ce3" => data <= x"20";
when "00" & x"ce4" => data <= x"d1";
when "00" & x"ce5" => data <= x"ff";
when "00" & x"ce6" => data <= x"48";
when "00" & x"ce7" => data <= x"a2";
when "00" & x"ce8" => data <= x"0c";
when "00" & x"ce9" => data <= x"b5";
when "00" & x"cea" => data <= x"00";
when "00" & x"ceb" => data <= x"20";
when "00" & x"cec" => data <= x"95";
when "00" & x"ced" => data <= x"06";
when "00" & x"cee" => data <= x"ca";
when "00" & x"cef" => data <= x"10";
when "00" & x"cf0" => data <= x"f8";
when "00" & x"cf1" => data <= x"68";
when "00" & x"cf2" => data <= x"4c";
when "00" & x"cf3" => data <= x"3a";
when "00" & x"cf4" => data <= x"05";
when "00" & x"cf5" => data <= x"20";
when "00" & x"cf6" => data <= x"c5";
when "00" & x"cf7" => data <= x"06";
when "00" & x"cf8" => data <= x"aa";
when "00" & x"cf9" => data <= x"20";
when "00" & x"cfa" => data <= x"c5";
when "00" & x"cfb" => data <= x"06";
when "00" & x"cfc" => data <= x"20";
when "00" & x"cfd" => data <= x"f4";
when "00" & x"cfe" => data <= x"ff";
when "00" & x"cff" => data <= x"2c";
when "00" & x"d00" => data <= x"e2";
when "00" & x"d01" => data <= x"fe";
when "00" & x"d02" => data <= x"50";
when "00" & x"d03" => data <= x"fb";
when "00" & x"d04" => data <= x"8e";
when "00" & x"d05" => data <= x"e3";
when "00" & x"d06" => data <= x"fe";
when "00" & x"d07" => data <= x"4c";
when "00" & x"d08" => data <= x"36";
when "00" & x"d09" => data <= x"00";
when "00" & x"d0a" => data <= x"20";
when "00" & x"d0b" => data <= x"c5";
when "00" & x"d0c" => data <= x"06";
when "00" & x"d0d" => data <= x"aa";
when "00" & x"d0e" => data <= x"20";
when "00" & x"d0f" => data <= x"c5";
when "00" & x"d10" => data <= x"06";
when "00" & x"d11" => data <= x"a8";
when "00" & x"d12" => data <= x"20";
when "00" & x"d13" => data <= x"c5";
when "00" & x"d14" => data <= x"06";
when "00" & x"d15" => data <= x"20";
when "00" & x"d16" => data <= x"f4";
when "00" & x"d17" => data <= x"ff";
when "00" & x"d18" => data <= x"49";
when "00" & x"d19" => data <= x"9d";
when "00" & x"d1a" => data <= x"f0";
when "00" & x"d1b" => data <= x"eb";
when "00" & x"d1c" => data <= x"6a";
when "00" & x"d1d" => data <= x"20";
when "00" & x"d1e" => data <= x"95";
when "00" & x"d1f" => data <= x"06";
when "00" & x"d20" => data <= x"2c";
when "00" & x"d21" => data <= x"e2";
when "00" & x"d22" => data <= x"fe";
when "00" & x"d23" => data <= x"50";
when "00" & x"d24" => data <= x"fb";
when "00" & x"d25" => data <= x"8c";
when "00" & x"d26" => data <= x"e3";
when "00" & x"d27" => data <= x"fe";
when "00" & x"d28" => data <= x"70";
when "00" & x"d29" => data <= x"d5";
when "00" & x"d2a" => data <= x"20";
when "00" & x"d2b" => data <= x"c5";
when "00" & x"d2c" => data <= x"06";
when "00" & x"d2d" => data <= x"a8";
when "00" & x"d2e" => data <= x"2c";
when "00" & x"d2f" => data <= x"e2";
when "00" & x"d30" => data <= x"fe";
when "00" & x"d31" => data <= x"10";
when "00" & x"d32" => data <= x"fb";
when "00" & x"d33" => data <= x"ae";
when "00" & x"d34" => data <= x"e3";
when "00" & x"d35" => data <= x"fe";
when "00" & x"d36" => data <= x"ca";
when "00" & x"d37" => data <= x"30";
when "00" & x"d38" => data <= x"0f";
when "00" & x"d39" => data <= x"2c";
when "00" & x"d3a" => data <= x"e2";
when "00" & x"d3b" => data <= x"fe";
when "00" & x"d3c" => data <= x"10";
when "00" & x"d3d" => data <= x"fb";
when "00" & x"d3e" => data <= x"ad";
when "00" & x"d3f" => data <= x"e3";
when "00" & x"d40" => data <= x"fe";
when "00" & x"d41" => data <= x"9d";
when "00" & x"d42" => data <= x"28";
when "00" & x"d43" => data <= x"01";
when "00" & x"d44" => data <= x"ca";
when "00" & x"d45" => data <= x"10";
when "00" & x"d46" => data <= x"f2";
when "00" & x"d47" => data <= x"98";
when "00" & x"d48" => data <= x"a2";
when "00" & x"d49" => data <= x"28";
when "00" & x"d4a" => data <= x"a0";
when "00" & x"d4b" => data <= x"01";
when "00" & x"d4c" => data <= x"20";
when "00" & x"d4d" => data <= x"f1";
when "00" & x"d4e" => data <= x"ff";
when "00" & x"d4f" => data <= x"2c";
when "00" & x"d50" => data <= x"e2";
when "00" & x"d51" => data <= x"fe";
when "00" & x"d52" => data <= x"10";
when "00" & x"d53" => data <= x"fb";
when "00" & x"d54" => data <= x"ae";
when "00" & x"d55" => data <= x"e3";
when "00" & x"d56" => data <= x"fe";
when "00" & x"d57" => data <= x"ca";
when "00" & x"d58" => data <= x"30";
when "00" & x"d59" => data <= x"0e";
when "00" & x"d5a" => data <= x"bc";
when "00" & x"d5b" => data <= x"28";
when "00" & x"d5c" => data <= x"01";
when "00" & x"d5d" => data <= x"2c";
when "00" & x"d5e" => data <= x"e2";
when "00" & x"d5f" => data <= x"fe";
when "00" & x"d60" => data <= x"50";
when "00" & x"d61" => data <= x"fb";
when "00" & x"d62" => data <= x"8c";
when "00" & x"d63" => data <= x"e3";
when "00" & x"d64" => data <= x"fe";
when "00" & x"d65" => data <= x"ca";
when "00" & x"d66" => data <= x"10";
when "00" & x"d67" => data <= x"f2";
when "00" & x"d68" => data <= x"4c";
when "00" & x"d69" => data <= x"36";
when "00" & x"d6a" => data <= x"00";
when "00" & x"d6b" => data <= x"a2";
when "00" & x"d6c" => data <= x"04";
when "00" & x"d6d" => data <= x"20";
when "00" & x"d6e" => data <= x"c5";
when "00" & x"d6f" => data <= x"06";
when "00" & x"d70" => data <= x"95";
when "00" & x"d71" => data <= x"00";
when "00" & x"d72" => data <= x"ca";
when "00" & x"d73" => data <= x"10";
when "00" & x"d74" => data <= x"f8";
when "00" & x"d75" => data <= x"e8";
when "00" & x"d76" => data <= x"a0";
when "00" & x"d77" => data <= x"00";
when "00" & x"d78" => data <= x"8a";
when "00" & x"d79" => data <= x"20";
when "00" & x"d7a" => data <= x"f1";
when "00" & x"d7b" => data <= x"ff";
when "00" & x"d7c" => data <= x"90";
when "00" & x"d7d" => data <= x"05";
when "00" & x"d7e" => data <= x"a9";
when "00" & x"d7f" => data <= x"ff";
when "00" & x"d80" => data <= x"4c";
when "00" & x"d81" => data <= x"9e";
when "00" & x"d82" => data <= x"05";
when "00" & x"d83" => data <= x"a2";
when "00" & x"d84" => data <= x"00";
when "00" & x"d85" => data <= x"a9";
when "00" & x"d86" => data <= x"7f";
when "00" & x"d87" => data <= x"20";
when "00" & x"d88" => data <= x"95";
when "00" & x"d89" => data <= x"06";
when "00" & x"d8a" => data <= x"bd";
when "00" & x"d8b" => data <= x"00";
when "00" & x"d8c" => data <= x"07";
when "00" & x"d8d" => data <= x"20";
when "00" & x"d8e" => data <= x"95";
when "00" & x"d8f" => data <= x"06";
when "00" & x"d90" => data <= x"e8";
when "00" & x"d91" => data <= x"c9";
when "00" & x"d92" => data <= x"0d";
when "00" & x"d93" => data <= x"d0";
when "00" & x"d94" => data <= x"f5";
when "00" & x"d95" => data <= x"4c";
when "00" & x"d96" => data <= x"36";
when "00" & x"d97" => data <= x"00";
when "00" & x"d98" => data <= x"2c";
when "00" & x"d99" => data <= x"e2";
when "00" & x"d9a" => data <= x"fe";
when "00" & x"d9b" => data <= x"50";
when "00" & x"d9c" => data <= x"fb";
when "00" & x"d9d" => data <= x"8d";
when "00" & x"d9e" => data <= x"e3";
when "00" & x"d9f" => data <= x"fe";
when "00" & x"da0" => data <= x"60";
when "00" & x"da1" => data <= x"2c";
when "00" & x"da2" => data <= x"e6";
when "00" & x"da3" => data <= x"fe";
when "00" & x"da4" => data <= x"50";
when "00" & x"da5" => data <= x"fb";
when "00" & x"da6" => data <= x"8d";
when "00" & x"da7" => data <= x"e7";
when "00" & x"da8" => data <= x"fe";
when "00" & x"da9" => data <= x"60";
when "00" & x"daa" => data <= x"a5";
when "00" & x"dab" => data <= x"ff";
when "00" & x"dac" => data <= x"38";
when "00" & x"dad" => data <= x"6a";
when "00" & x"dae" => data <= x"30";
when "00" & x"daf" => data <= x"0f";
when "00" & x"db0" => data <= x"48";
when "00" & x"db1" => data <= x"a9";
when "00" & x"db2" => data <= x"00";
when "00" & x"db3" => data <= x"20";
when "00" & x"db4" => data <= x"bc";
when "00" & x"db5" => data <= x"06";
when "00" & x"db6" => data <= x"98";
when "00" & x"db7" => data <= x"20";
when "00" & x"db8" => data <= x"bc";
when "00" & x"db9" => data <= x"06";
when "00" & x"dba" => data <= x"8a";
when "00" & x"dbb" => data <= x"20";
when "00" & x"dbc" => data <= x"bc";
when "00" & x"dbd" => data <= x"06";
when "00" & x"dbe" => data <= x"68";
when "00" & x"dbf" => data <= x"2c";
when "00" & x"dc0" => data <= x"e0";
when "00" & x"dc1" => data <= x"fe";
when "00" & x"dc2" => data <= x"50";
when "00" & x"dc3" => data <= x"fb";
when "00" & x"dc4" => data <= x"8d";
when "00" & x"dc5" => data <= x"e1";
when "00" & x"dc6" => data <= x"fe";
when "00" & x"dc7" => data <= x"60";
when "00" & x"dc8" => data <= x"2c";
when "00" & x"dc9" => data <= x"e2";
when "00" & x"dca" => data <= x"fe";
when "00" & x"dcb" => data <= x"10";
when "00" & x"dcc" => data <= x"fb";
when "00" & x"dcd" => data <= x"ad";
when "00" & x"dce" => data <= x"e3";
when "00" & x"dcf" => data <= x"fe";
when "00" & x"dd0" => data <= x"60";
when "00" & x"dd1" => data <= x"00";
when "00" & x"dd2" => data <= x"00";
when "00" & x"dd3" => data <= x"00";
when "00" & x"dd4" => data <= x"00";
when "00" & x"dd5" => data <= x"00";
when "00" & x"dd6" => data <= x"00";
when "00" & x"dd7" => data <= x"00";
when "00" & x"dd8" => data <= x"00";
when "00" & x"dd9" => data <= x"00";
when "00" & x"dda" => data <= x"00";
when "00" & x"ddb" => data <= x"00";
when "00" & x"ddc" => data <= x"00";
when "00" & x"ddd" => data <= x"a2";
when "00" & x"dde" => data <= x"11";
when "00" & x"ddf" => data <= x"a0";
when "00" & x"de0" => data <= x"13";
when "00" & x"de1" => data <= x"60";
when "00" & x"de2" => data <= x"20";
when "00" & x"de3" => data <= x"e1";
when "00" & x"de4" => data <= x"83";
when "00" & x"de5" => data <= x"a9";
when "00" & x"de6" => data <= x"77";
when "00" & x"de7" => data <= x"4c";
when "00" & x"de8" => data <= x"f4";
when "00" & x"de9" => data <= x"ff";
when "00" & x"dea" => data <= x"20";
when "00" & x"deb" => data <= x"e2";
when "00" & x"dec" => data <= x"8d";
when "00" & x"ded" => data <= x"a9";
when "00" & x"dee" => data <= x"00";
when "00" & x"def" => data <= x"18";
when "00" & x"df0" => data <= x"69";
when "00" & x"df1" => data <= x"20";
when "00" & x"df2" => data <= x"f0";
when "00" & x"df3" => data <= x"ed";
when "00" & x"df4" => data <= x"a8";
when "00" & x"df5" => data <= x"20";
when "00" & x"df6" => data <= x"05";
when "00" & x"df7" => data <= x"8e";
when "00" & x"df8" => data <= x"d0";
when "00" & x"df9" => data <= x"f5";
when "00" & x"dfa" => data <= x"98";
when "00" & x"dfb" => data <= x"f0";
when "00" & x"dfc" => data <= x"ed";
when "00" & x"dfd" => data <= x"20";
when "00" & x"dfe" => data <= x"7b";
when "00" & x"dff" => data <= x"90";
when "00" & x"e00" => data <= x"90";
when "00" & x"e01" => data <= x"03";
when "00" & x"e02" => data <= x"4c";
when "00" & x"e03" => data <= x"ad";
when "00" & x"e04" => data <= x"90";
when "00" & x"e05" => data <= x"48";
when "00" & x"e06" => data <= x"20";
when "00" & x"e07" => data <= x"51";
when "00" & x"e08" => data <= x"90";
when "00" & x"e09" => data <= x"b0";
when "00" & x"e0a" => data <= x"45";
when "00" & x"e0b" => data <= x"b9";
when "00" & x"e0c" => data <= x"1b";
when "00" & x"e0d" => data <= x"11";
when "00" & x"e0e" => data <= x"49";
when "00" & x"e0f" => data <= x"ff";
when "00" & x"e10" => data <= x"2d";
when "00" & x"e11" => data <= x"c0";
when "00" & x"e12" => data <= x"10";
when "00" & x"e13" => data <= x"8d";
when "00" & x"e14" => data <= x"c0";
when "00" & x"e15" => data <= x"10";
when "00" & x"e16" => data <= x"b9";
when "00" & x"e17" => data <= x"17";
when "00" & x"e18" => data <= x"11";
when "00" & x"e19" => data <= x"29";
when "00" & x"e1a" => data <= x"60";
when "00" & x"e1b" => data <= x"f0";
when "00" & x"e1c" => data <= x"33";
when "00" & x"e1d" => data <= x"20";
when "00" & x"e1e" => data <= x"55";
when "00" & x"e1f" => data <= x"8e";
when "00" & x"e20" => data <= x"b9";
when "00" & x"e21" => data <= x"17";
when "00" & x"e22" => data <= x"11";
when "00" & x"e23" => data <= x"29";
when "00" & x"e24" => data <= x"20";
when "00" & x"e25" => data <= x"f0";
when "00" & x"e26" => data <= x"26";
when "00" & x"e27" => data <= x"ae";
when "00" & x"e28" => data <= x"c4";
when "00" & x"e29" => data <= x"10";
when "00" & x"e2a" => data <= x"b9";
when "00" & x"e2b" => data <= x"14";
when "00" & x"e2c" => data <= x"11";
when "00" & x"e2d" => data <= x"9d";
when "00" & x"e2e" => data <= x"0c";
when "00" & x"e2f" => data <= x"0f";
when "00" & x"e30" => data <= x"b9";
when "00" & x"e31" => data <= x"15";
when "00" & x"e32" => data <= x"11";
when "00" & x"e33" => data <= x"9d";
when "00" & x"e34" => data <= x"0d";
when "00" & x"e35" => data <= x"0f";
when "00" & x"e36" => data <= x"b9";
when "00" & x"e37" => data <= x"16";
when "00" & x"e38" => data <= x"11";
when "00" & x"e39" => data <= x"20";
when "00" & x"e3a" => data <= x"0b";
when "00" & x"e3b" => data <= x"82";
when "00" & x"e3c" => data <= x"5d";
when "00" & x"e3d" => data <= x"0e";
when "00" & x"e3e" => data <= x"0f";
when "00" & x"e3f" => data <= x"29";
when "00" & x"e40" => data <= x"30";
when "00" & x"e41" => data <= x"5d";
when "00" & x"e42" => data <= x"0e";
when "00" & x"e43" => data <= x"0f";
when "00" & x"e44" => data <= x"9d";
when "00" & x"e45" => data <= x"0e";
when "00" & x"e46" => data <= x"0f";
when "00" & x"e47" => data <= x"20";
when "00" & x"e48" => data <= x"b4";
when "00" & x"e49" => data <= x"8a";
when "00" & x"e4a" => data <= x"ac";
when "00" & x"e4b" => data <= x"c2";
when "00" & x"e4c" => data <= x"10";
when "00" & x"e4d" => data <= x"20";
when "00" & x"e4e" => data <= x"4b";
when "00" & x"e4f" => data <= x"91";
when "00" & x"e50" => data <= x"ae";
when "00" & x"e51" => data <= x"c6";
when "00" & x"e52" => data <= x"10";
when "00" & x"e53" => data <= x"68";
when "00" & x"e54" => data <= x"60";
when "00" & x"e55" => data <= x"20";
when "00" & x"e56" => data <= x"83";
when "00" & x"e57" => data <= x"8e";
when "00" & x"e58" => data <= x"a2";
when "00" & x"e59" => data <= x"07";
when "00" & x"e5a" => data <= x"b9";
when "00" & x"e5b" => data <= x"0c";
when "00" & x"e5c" => data <= x"11";
when "00" & x"e5d" => data <= x"95";
when "00" & x"e5e" => data <= x"c6";
when "00" & x"e5f" => data <= x"88";
when "00" & x"e60" => data <= x"88";
when "00" & x"e61" => data <= x"ca";
when "00" & x"e62" => data <= x"d0";
when "00" & x"e63" => data <= x"f6";
when "00" & x"e64" => data <= x"20";
when "00" & x"e65" => data <= x"96";
when "00" & x"e66" => data <= x"82";
when "00" & x"e67" => data <= x"90";
when "00" & x"e68" => data <= x"27";
when "00" & x"e69" => data <= x"8c";
when "00" & x"e6a" => data <= x"c4";
when "00" & x"e6b" => data <= x"10";
when "00" & x"e6c" => data <= x"b9";
when "00" & x"e6d" => data <= x"0e";
when "00" & x"e6e" => data <= x"0f";
when "00" & x"e6f" => data <= x"be";
when "00" & x"e70" => data <= x"0f";
when "00" & x"e71" => data <= x"0f";
when "00" & x"e72" => data <= x"ac";
when "00" & x"e73" => data <= x"c2";
when "00" & x"e74" => data <= x"10";
when "00" & x"e75" => data <= x"59";
when "00" & x"e76" => data <= x"0d";
when "00" & x"e77" => data <= x"11";
when "00" & x"e78" => data <= x"29";
when "00" & x"e79" => data <= x"03";
when "00" & x"e7a" => data <= x"d0";
when "00" & x"e7b" => data <= x"14";
when "00" & x"e7c" => data <= x"8a";
when "00" & x"e7d" => data <= x"d9";
when "00" & x"e7e" => data <= x"0f";
when "00" & x"e7f" => data <= x"11";
when "00" & x"e80" => data <= x"d0";
when "00" & x"e81" => data <= x"0e";
when "00" & x"e82" => data <= x"60";
when "00" & x"e83" => data <= x"b9";
when "00" & x"e84" => data <= x"0e";
when "00" & x"e85" => data <= x"11";
when "00" & x"e86" => data <= x"29";
when "00" & x"e87" => data <= x"7f";
when "00" & x"e88" => data <= x"85";
when "00" & x"e89" => data <= x"ce";
when "00" & x"e8a" => data <= x"b9";
when "00" & x"e8b" => data <= x"17";
when "00" & x"e8c" => data <= x"11";
when "00" & x"e8d" => data <= x"4c";
when "00" & x"e8e" => data <= x"7e";
when "00" & x"e8f" => data <= x"87";
when "00" & x"e90" => data <= x"4c";
when "00" & x"e91" => data <= x"af";
when "00" & x"e92" => data <= x"81";
when "00" & x"e93" => data <= x"c9";
when "00" & x"e94" => data <= x"00";
when "00" & x"e95" => data <= x"d0";
when "00" & x"e96" => data <= x"06";
when "00" & x"e97" => data <= x"20";
when "00" & x"e98" => data <= x"e1";
when "00" & x"e99" => data <= x"83";
when "00" & x"e9a" => data <= x"4c";
when "00" & x"e9b" => data <= x"fa";
when "00" & x"e9c" => data <= x"8d";
when "00" & x"e9d" => data <= x"20";
when "00" & x"e9e" => data <= x"11";
when "00" & x"e9f" => data <= x"84";
when "00" & x"ea0" => data <= x"86";
when "00" & x"ea1" => data <= x"bc";
when "00" & x"ea2" => data <= x"84";
when "00" & x"ea3" => data <= x"bd";
when "00" & x"ea4" => data <= x"85";
when "00" & x"ea5" => data <= x"b4";
when "00" & x"ea6" => data <= x"24";
when "00" & x"ea7" => data <= x"b4";
when "00" & x"ea8" => data <= x"08";
when "00" & x"ea9" => data <= x"20";
when "00" & x"eaa" => data <= x"06";
when "00" & x"eab" => data <= x"81";
when "00" & x"eac" => data <= x"20";
when "00" & x"ead" => data <= x"96";
when "00" & x"eae" => data <= x"82";
when "00" & x"eaf" => data <= x"b0";
when "00" & x"eb0" => data <= x"1a";
when "00" & x"eb1" => data <= x"28";
when "00" & x"eb2" => data <= x"50";
when "00" & x"eb3" => data <= x"03";
when "00" & x"eb4" => data <= x"a9";
when "00" & x"eb5" => data <= x"00";
when "00" & x"eb6" => data <= x"60";
when "00" & x"eb7" => data <= x"08";
when "00" & x"eb8" => data <= x"a9";
when "00" & x"eb9" => data <= x"00";
when "00" & x"eba" => data <= x"a2";
when "00" & x"ebb" => data <= x"07";
when "00" & x"ebc" => data <= x"95";
when "00" & x"ebd" => data <= x"be";
when "00" & x"ebe" => data <= x"9d";
when "00" & x"ebf" => data <= x"74";
when "00" & x"ec0" => data <= x"10";
when "00" & x"ec1" => data <= x"ca";
when "00" & x"ec2" => data <= x"10";
when "00" & x"ec3" => data <= x"f8";
when "00" & x"ec4" => data <= x"a9";
when "00" & x"ec5" => data <= x"40";
when "00" & x"ec6" => data <= x"85";
when "00" & x"ec7" => data <= x"c5";
when "00" & x"ec8" => data <= x"20";
when "00" & x"ec9" => data <= x"61";
when "00" & x"eca" => data <= x"89";
when "00" & x"ecb" => data <= x"28";
when "00" & x"ecc" => data <= x"08";
when "00" & x"ecd" => data <= x"70";
when "00" & x"ece" => data <= x"03";
when "00" & x"ecf" => data <= x"20";
when "00" & x"ed0" => data <= x"3c";
when "00" & x"ed1" => data <= x"98";
when "00" & x"ed2" => data <= x"20";
when "00" & x"ed3" => data <= x"9e";
when "00" & x"ed4" => data <= x"8f";
when "00" & x"ed5" => data <= x"90";
when "00" & x"ed6" => data <= x"0e";
when "00" & x"ed7" => data <= x"b9";
when "00" & x"ed8" => data <= x"0c";
when "00" & x"ed9" => data <= x"11";
when "00" & x"eda" => data <= x"10";
when "00" & x"edb" => data <= x"26";
when "00" & x"edc" => data <= x"24";
when "00" & x"edd" => data <= x"b4";
when "00" & x"ede" => data <= x"30";
when "00" & x"edf" => data <= x"22";
when "00" & x"ee0" => data <= x"20";
when "00" & x"ee1" => data <= x"99";
when "00" & x"ee2" => data <= x"8f";
when "00" & x"ee3" => data <= x"b0";
when "00" & x"ee4" => data <= x"f2";
when "00" & x"ee5" => data <= x"ac";
when "00" & x"ee6" => data <= x"c2";
when "00" & x"ee7" => data <= x"10";
when "00" & x"ee8" => data <= x"d0";
when "00" & x"ee9" => data <= x"21";
when "00" & x"eea" => data <= x"20";
when "00" & x"eeb" => data <= x"33";
when "00" & x"eec" => data <= x"80";
when "00" & x"eed" => data <= x"c0";
when "00" & x"eee" => data <= x"54";
when "00" & x"eef" => data <= x"6f";
when "00" & x"ef0" => data <= x"6f";
when "00" & x"ef1" => data <= x"20";
when "00" & x"ef2" => data <= x"6d";
when "00" & x"ef3" => data <= x"61";
when "00" & x"ef4" => data <= x"6e";
when "00" & x"ef5" => data <= x"79";
when "00" & x"ef6" => data <= x"20";
when "00" & x"ef7" => data <= x"66";
when "00" & x"ef8" => data <= x"69";
when "00" & x"ef9" => data <= x"6c";
when "00" & x"efa" => data <= x"65";
when "00" & x"efb" => data <= x"73";
when "00" & x"efc" => data <= x"20";
when "00" & x"efd" => data <= x"6f";
when "00" & x"efe" => data <= x"70";
when "00" & x"eff" => data <= x"65";
when "00" & x"f00" => data <= x"6e";
when "00" & x"f01" => data <= x"00";
when "00" & x"f02" => data <= x"20";
when "00" & x"f03" => data <= x"2b";
when "00" & x"f04" => data <= x"80";
when "00" & x"f05" => data <= x"c2";
when "00" & x"f06" => data <= x"6f";
when "00" & x"f07" => data <= x"70";
when "00" & x"f08" => data <= x"65";
when "00" & x"f09" => data <= x"6e";
when "00" & x"f0a" => data <= x"00";
when "00" & x"f0b" => data <= x"a9";
when "00" & x"f0c" => data <= x"08";
when "00" & x"f0d" => data <= x"8d";
when "00" & x"f0e" => data <= x"c5";
when "00" & x"f0f" => data <= x"10";
when "00" & x"f10" => data <= x"bd";
when "00" & x"f11" => data <= x"08";
when "00" & x"f12" => data <= x"0e";
when "00" & x"f13" => data <= x"99";
when "00" & x"f14" => data <= x"00";
when "00" & x"f15" => data <= x"11";
when "00" & x"f16" => data <= x"c8";
when "00" & x"f17" => data <= x"bd";
when "00" & x"f18" => data <= x"08";
when "00" & x"f19" => data <= x"0f";
when "00" & x"f1a" => data <= x"99";
when "00" & x"f1b" => data <= x"00";
when "00" & x"f1c" => data <= x"11";
when "00" & x"f1d" => data <= x"c8";
when "00" & x"f1e" => data <= x"e8";
when "00" & x"f1f" => data <= x"ce";
when "00" & x"f20" => data <= x"c5";
when "00" & x"f21" => data <= x"10";
when "00" & x"f22" => data <= x"d0";
when "00" & x"f23" => data <= x"ec";
when "00" & x"f24" => data <= x"a2";
when "00" & x"f25" => data <= x"10";
when "00" & x"f26" => data <= x"a9";
when "00" & x"f27" => data <= x"00";
when "00" & x"f28" => data <= x"99";
when "00" & x"f29" => data <= x"00";
when "00" & x"f2a" => data <= x"11";
when "00" & x"f2b" => data <= x"c8";
when "00" & x"f2c" => data <= x"ca";
when "00" & x"f2d" => data <= x"d0";
when "00" & x"f2e" => data <= x"f9";
when "00" & x"f2f" => data <= x"ad";
when "00" & x"f30" => data <= x"c2";
when "00" & x"f31" => data <= x"10";
when "00" & x"f32" => data <= x"a8";
when "00" & x"f33" => data <= x"20";
when "00" & x"f34" => data <= x"04";
when "00" & x"f35" => data <= x"82";
when "00" & x"f36" => data <= x"69";
when "00" & x"f37" => data <= x"11";
when "00" & x"f38" => data <= x"99";
when "00" & x"f39" => data <= x"13";
when "00" & x"f3a" => data <= x"11";
when "00" & x"f3b" => data <= x"ad";
when "00" & x"f3c" => data <= x"c1";
when "00" & x"f3d" => data <= x"10";
when "00" & x"f3e" => data <= x"99";
when "00" & x"f3f" => data <= x"1b";
when "00" & x"f40" => data <= x"11";
when "00" & x"f41" => data <= x"0d";
when "00" & x"f42" => data <= x"c0";
when "00" & x"f43" => data <= x"10";
when "00" & x"f44" => data <= x"8d";
when "00" & x"f45" => data <= x"c0";
when "00" & x"f46" => data <= x"10";
when "00" & x"f47" => data <= x"b9";
when "00" & x"f48" => data <= x"09";
when "00" & x"f49" => data <= x"11";
when "00" & x"f4a" => data <= x"69";
when "00" & x"f4b" => data <= x"ff";
when "00" & x"f4c" => data <= x"b9";
when "00" & x"f4d" => data <= x"0b";
when "00" & x"f4e" => data <= x"11";
when "00" & x"f4f" => data <= x"69";
when "00" & x"f50" => data <= x"00";
when "00" & x"f51" => data <= x"99";
when "00" & x"f52" => data <= x"19";
when "00" & x"f53" => data <= x"11";
when "00" & x"f54" => data <= x"b9";
when "00" & x"f55" => data <= x"0d";
when "00" & x"f56" => data <= x"11";
when "00" & x"f57" => data <= x"09";
when "00" & x"f58" => data <= x"0f";
when "00" & x"f59" => data <= x"69";
when "00" & x"f5a" => data <= x"00";
when "00" & x"f5b" => data <= x"20";
when "00" & x"f5c" => data <= x"fd";
when "00" & x"f5d" => data <= x"81";
when "00" & x"f5e" => data <= x"99";
when "00" & x"f5f" => data <= x"1a";
when "00" & x"f60" => data <= x"11";
when "00" & x"f61" => data <= x"28";
when "00" & x"f62" => data <= x"50";
when "00" & x"f63" => data <= x"2e";
when "00" & x"f64" => data <= x"30";
when "00" & x"f65" => data <= x"08";
when "00" & x"f66" => data <= x"a9";
when "00" & x"f67" => data <= x"80";
when "00" & x"f68" => data <= x"19";
when "00" & x"f69" => data <= x"0c";
when "00" & x"f6a" => data <= x"11";
when "00" & x"f6b" => data <= x"99";
when "00" & x"f6c" => data <= x"0c";
when "00" & x"f6d" => data <= x"11";
when "00" & x"f6e" => data <= x"b9";
when "00" & x"f6f" => data <= x"09";
when "00" & x"f70" => data <= x"11";
when "00" & x"f71" => data <= x"99";
when "00" & x"f72" => data <= x"14";
when "00" & x"f73" => data <= x"11";
when "00" & x"f74" => data <= x"b9";
when "00" & x"f75" => data <= x"0b";
when "00" & x"f76" => data <= x"11";
when "00" & x"f77" => data <= x"99";
when "00" & x"f78" => data <= x"15";
when "00" & x"f79" => data <= x"11";
when "00" & x"f7a" => data <= x"b9";
when "00" & x"f7b" => data <= x"0d";
when "00" & x"f7c" => data <= x"11";
when "00" & x"f7d" => data <= x"20";
when "00" & x"f7e" => data <= x"fd";
when "00" & x"f7f" => data <= x"81";
when "00" & x"f80" => data <= x"99";
when "00" & x"f81" => data <= x"16";
when "00" & x"f82" => data <= x"11";
when "00" & x"f83" => data <= x"a5";
when "00" & x"f84" => data <= x"cf";
when "00" & x"f85" => data <= x"19";
when "00" & x"f86" => data <= x"17";
when "00" & x"f87" => data <= x"11";
when "00" & x"f88" => data <= x"99";
when "00" & x"f89" => data <= x"17";
when "00" & x"f8a" => data <= x"11";
when "00" & x"f8b" => data <= x"98";
when "00" & x"f8c" => data <= x"20";
when "00" & x"f8d" => data <= x"04";
when "00" & x"f8e" => data <= x"82";
when "00" & x"f8f" => data <= x"09";
when "00" & x"f90" => data <= x"10";
when "00" & x"f91" => data <= x"60";
when "00" & x"f92" => data <= x"a9";
when "00" & x"f93" => data <= x"20";
when "00" & x"f94" => data <= x"99";
when "00" & x"f95" => data <= x"17";
when "00" & x"f96" => data <= x"11";
when "00" & x"f97" => data <= x"d0";
when "00" & x"f98" => data <= x"ea";
when "00" & x"f99" => data <= x"8a";
when "00" & x"f9a" => data <= x"48";
when "00" & x"f9b" => data <= x"4c";
when "00" & x"f9c" => data <= x"dd";
when "00" & x"f9d" => data <= x"8f";
when "00" & x"f9e" => data <= x"a9";
when "00" & x"f9f" => data <= x"00";
when "00" & x"fa0" => data <= x"8d";
when "00" & x"fa1" => data <= x"c2";
when "00" & x"fa2" => data <= x"10";
when "00" & x"fa3" => data <= x"a9";
when "00" & x"fa4" => data <= x"08";
when "00" & x"fa5" => data <= x"85";
when "00" & x"fa6" => data <= x"b5";
when "00" & x"fa7" => data <= x"98";
when "00" & x"fa8" => data <= x"aa";
when "00" & x"fa9" => data <= x"a0";
when "00" & x"faa" => data <= x"a0";
when "00" & x"fab" => data <= x"84";
when "00" & x"fac" => data <= x"b3";
when "00" & x"fad" => data <= x"8a";
when "00" & x"fae" => data <= x"48";
when "00" & x"faf" => data <= x"a9";
when "00" & x"fb0" => data <= x"08";
when "00" & x"fb1" => data <= x"85";
when "00" & x"fb2" => data <= x"b2";
when "00" & x"fb3" => data <= x"a5";
when "00" & x"fb4" => data <= x"b5";
when "00" & x"fb5" => data <= x"2c";
when "00" & x"fb6" => data <= x"c0";
when "00" & x"fb7" => data <= x"10";
when "00" & x"fb8" => data <= x"f0";
when "00" & x"fb9" => data <= x"1d";
when "00" & x"fba" => data <= x"b9";
when "00" & x"fbb" => data <= x"17";
when "00" & x"fbc" => data <= x"11";
when "00" & x"fbd" => data <= x"45";
when "00" & x"fbe" => data <= x"cf";
when "00" & x"fbf" => data <= x"29";
when "00" & x"fc0" => data <= x"03";
when "00" & x"fc1" => data <= x"d0";
when "00" & x"fc2" => data <= x"1a";
when "00" & x"fc3" => data <= x"bd";
when "00" & x"fc4" => data <= x"08";
when "00" & x"fc5" => data <= x"0e";
when "00" & x"fc6" => data <= x"59";
when "00" & x"fc7" => data <= x"00";
when "00" & x"fc8" => data <= x"11";
when "00" & x"fc9" => data <= x"29";
when "00" & x"fca" => data <= x"7f";
when "00" & x"fcb" => data <= x"d0";
when "00" & x"fcc" => data <= x"10";
when "00" & x"fcd" => data <= x"e8";
when "00" & x"fce" => data <= x"c8";
when "00" & x"fcf" => data <= x"c8";
when "00" & x"fd0" => data <= x"c6";
when "00" & x"fd1" => data <= x"b2";
when "00" & x"fd2" => data <= x"d0";
when "00" & x"fd3" => data <= x"ef";
when "00" & x"fd4" => data <= x"38";
when "00" & x"fd5" => data <= x"b0";
when "00" & x"fd6" => data <= x"10";
when "00" & x"fd7" => data <= x"8c";
when "00" & x"fd8" => data <= x"c2";
when "00" & x"fd9" => data <= x"10";
when "00" & x"fda" => data <= x"8d";
when "00" & x"fdb" => data <= x"c1";
when "00" & x"fdc" => data <= x"10";
when "00" & x"fdd" => data <= x"38";
when "00" & x"fde" => data <= x"a5";
when "00" & x"fdf" => data <= x"b3";
when "00" & x"fe0" => data <= x"e9";
when "00" & x"fe1" => data <= x"20";
when "00" & x"fe2" => data <= x"85";
when "00" & x"fe3" => data <= x"b3";
when "00" & x"fe4" => data <= x"06";
when "00" & x"fe5" => data <= x"b5";
when "00" & x"fe6" => data <= x"18";
when "00" & x"fe7" => data <= x"68";
when "00" & x"fe8" => data <= x"aa";
when "00" & x"fe9" => data <= x"a4";
when "00" & x"fea" => data <= x"b3";
when "00" & x"feb" => data <= x"a5";
when "00" & x"fec" => data <= x"b5";
when "00" & x"fed" => data <= x"b0";
when "00" & x"fee" => data <= x"02";
when "00" & x"fef" => data <= x"d0";
when "00" & x"ff0" => data <= x"ba";
when "00" & x"ff1" => data <= x"60";
when "00" & x"ff2" => data <= x"ad";
when "00" & x"ff3" => data <= x"c0";
when "00" & x"ff4" => data <= x"10";
when "00" & x"ff5" => data <= x"48";
when "00" & x"ff6" => data <= x"20";
when "00" & x"ff7" => data <= x"ed";
when "00" & x"ff8" => data <= x"8d";
when "00" & x"ff9" => data <= x"f0";
when "00" & x"ffa" => data <= x"07";
when "00" & x"ffb" => data <= x"ad";
when "00" & x"ffc" => data <= x"c0";
when "00" & x"ffd" => data <= x"10";
when "00" & x"ffe" => data <= x"48";
when "00" & x"fff" => data <= x"20";
when "01" & x"000" => data <= x"fa";
when "01" & x"001" => data <= x"8d";
when "01" & x"002" => data <= x"68";
when "01" & x"003" => data <= x"8d";
when "01" & x"004" => data <= x"c0";
when "01" & x"005" => data <= x"10";
when "01" & x"006" => data <= x"60";
when "01" & x"007" => data <= x"c0";
when "01" & x"008" => data <= x"00";
when "01" & x"009" => data <= x"f0";
when "01" & x"00a" => data <= x"11";
when "01" & x"00b" => data <= x"20";
when "01" & x"00c" => data <= x"e1";
when "01" & x"00d" => data <= x"83";
when "01" & x"00e" => data <= x"c9";
when "01" & x"00f" => data <= x"ff";
when "01" & x"010" => data <= x"f0";
when "01" & x"011" => data <= x"e9";
when "01" & x"012" => data <= x"c9";
when "01" & x"013" => data <= x"03";
when "01" & x"014" => data <= x"b0";
when "01" & x"015" => data <= x"17";
when "01" & x"016" => data <= x"4a";
when "01" & x"017" => data <= x"90";
when "01" & x"018" => data <= x"15";
when "01" & x"019" => data <= x"4c";
when "01" & x"01a" => data <= x"a7";
when "01" & x"01b" => data <= x"92";
when "01" & x"01c" => data <= x"20";
when "01" & x"01d" => data <= x"11";
when "01" & x"01e" => data <= x"84";
when "01" & x"01f" => data <= x"a8";
when "01" & x"020" => data <= x"c8";
when "01" & x"021" => data <= x"c0";
when "01" & x"022" => data <= x"03";
when "01" & x"023" => data <= x"b0";
when "01" & x"024" => data <= x"08";
when "01" & x"025" => data <= x"b9";
when "01" & x"026" => data <= x"81";
when "01" & x"027" => data <= x"99";
when "01" & x"028" => data <= x"48";
when "01" & x"029" => data <= x"b9";
when "01" & x"02a" => data <= x"7e";
when "01" & x"02b" => data <= x"99";
when "01" & x"02c" => data <= x"48";
when "01" & x"02d" => data <= x"60";
when "01" & x"02e" => data <= x"20";
when "01" & x"02f" => data <= x"e1";
when "01" & x"030" => data <= x"83";
when "01" & x"031" => data <= x"20";
when "01" & x"032" => data <= x"a5";
when "01" & x"033" => data <= x"90";
when "01" & x"034" => data <= x"8c";
when "01" & x"035" => data <= x"c2";
when "01" & x"036" => data <= x"10";
when "01" & x"037" => data <= x"0a";
when "01" & x"038" => data <= x"0a";
when "01" & x"039" => data <= x"6d";
when "01" & x"03a" => data <= x"c2";
when "01" & x"03b" => data <= x"10";
when "01" & x"03c" => data <= x"a8";
when "01" & x"03d" => data <= x"b9";
when "01" & x"03e" => data <= x"10";
when "01" & x"03f" => data <= x"11";
when "01" & x"040" => data <= x"95";
when "01" & x"041" => data <= x"00";
when "01" & x"042" => data <= x"b9";
when "01" & x"043" => data <= x"11";
when "01" & x"044" => data <= x"11";
when "01" & x"045" => data <= x"95";
when "01" & x"046" => data <= x"01";
when "01" & x"047" => data <= x"b9";
when "01" & x"048" => data <= x"12";
when "01" & x"049" => data <= x"11";
when "01" & x"04a" => data <= x"95";
when "01" & x"04b" => data <= x"02";
when "01" & x"04c" => data <= x"a9";
when "01" & x"04d" => data <= x"00";
when "01" & x"04e" => data <= x"95";
when "01" & x"04f" => data <= x"03";
when "01" & x"050" => data <= x"60";
when "01" & x"051" => data <= x"48";
when "01" & x"052" => data <= x"8e";
when "01" & x"053" => data <= x"c6";
when "01" & x"054" => data <= x"10";
when "01" & x"055" => data <= x"98";
when "01" & x"056" => data <= x"29";
when "01" & x"057" => data <= x"e0";
when "01" & x"058" => data <= x"8d";
when "01" & x"059" => data <= x"c2";
when "01" & x"05a" => data <= x"10";
when "01" & x"05b" => data <= x"f0";
when "01" & x"05c" => data <= x"13";
when "01" & x"05d" => data <= x"20";
when "01" & x"05e" => data <= x"04";
when "01" & x"05f" => data <= x"82";
when "01" & x"060" => data <= x"a8";
when "01" & x"061" => data <= x"a9";
when "01" & x"062" => data <= x"00";
when "01" & x"063" => data <= x"38";
when "01" & x"064" => data <= x"6a";
when "01" & x"065" => data <= x"88";
when "01" & x"066" => data <= x"d0";
when "01" & x"067" => data <= x"fc";
when "01" & x"068" => data <= x"ac";
when "01" & x"069" => data <= x"c2";
when "01" & x"06a" => data <= x"10";
when "01" & x"06b" => data <= x"2c";
when "01" & x"06c" => data <= x"c0";
when "01" & x"06d" => data <= x"10";
when "01" & x"06e" => data <= x"d0";
when "01" & x"06f" => data <= x"03";
when "01" & x"070" => data <= x"68";
when "01" & x"071" => data <= x"38";
when "01" & x"072" => data <= x"60";
when "01" & x"073" => data <= x"68";
when "01" & x"074" => data <= x"18";
when "01" & x"075" => data <= x"60";
when "01" & x"076" => data <= x"48";
when "01" & x"077" => data <= x"8a";
when "01" & x"078" => data <= x"4c";
when "01" & x"079" => data <= x"7d";
when "01" & x"07a" => data <= x"90";
when "01" & x"07b" => data <= x"48";
when "01" & x"07c" => data <= x"98";
when "01" & x"07d" => data <= x"c9";
when "01" & x"07e" => data <= x"10";
when "01" & x"07f" => data <= x"90";
when "01" & x"080" => data <= x"04";
when "01" & x"081" => data <= x"c9";
when "01" & x"082" => data <= x"18";
when "01" & x"083" => data <= x"90";
when "01" & x"084" => data <= x"02";
when "01" & x"085" => data <= x"a9";
when "01" & x"086" => data <= x"08";
when "01" & x"087" => data <= x"20";
when "01" & x"088" => data <= x"0a";
when "01" & x"089" => data <= x"82";
when "01" & x"08a" => data <= x"a8";
when "01" & x"08b" => data <= x"68";
when "01" & x"08c" => data <= x"60";
when "01" & x"08d" => data <= x"48";
when "01" & x"08e" => data <= x"98";
when "01" & x"08f" => data <= x"48";
when "01" & x"090" => data <= x"8a";
when "01" & x"091" => data <= x"a8";
when "01" & x"092" => data <= x"20";
when "01" & x"093" => data <= x"a5";
when "01" & x"094" => data <= x"90";
when "01" & x"095" => data <= x"98";
when "01" & x"096" => data <= x"20";
when "01" & x"097" => data <= x"f8";
when "01" & x"098" => data <= x"92";
when "01" & x"099" => data <= x"d0";
when "01" & x"09a" => data <= x"04";
when "01" & x"09b" => data <= x"a2";
when "01" & x"09c" => data <= x"ff";
when "01" & x"09d" => data <= x"d0";
when "01" & x"09e" => data <= x"02";
when "01" & x"09f" => data <= x"a2";
when "01" & x"0a0" => data <= x"00";
when "01" & x"0a1" => data <= x"68";
when "01" & x"0a2" => data <= x"a8";
when "01" & x"0a3" => data <= x"68";
when "01" & x"0a4" => data <= x"60";
when "01" & x"0a5" => data <= x"20";
when "01" & x"0a6" => data <= x"7b";
when "01" & x"0a7" => data <= x"90";
when "01" & x"0a8" => data <= x"20";
when "01" & x"0a9" => data <= x"51";
when "01" & x"0aa" => data <= x"90";
when "01" & x"0ab" => data <= x"90";
when "01" & x"0ac" => data <= x"f7";
when "01" & x"0ad" => data <= x"20";
when "01" & x"0ae" => data <= x"33";
when "01" & x"0af" => data <= x"80";
when "01" & x"0b0" => data <= x"de";
when "01" & x"0b1" => data <= x"43";
when "01" & x"0b2" => data <= x"68";
when "01" & x"0b3" => data <= x"61";
when "01" & x"0b4" => data <= x"6e";
when "01" & x"0b5" => data <= x"6e";
when "01" & x"0b6" => data <= x"65";
when "01" & x"0b7" => data <= x"6c";
when "01" & x"0b8" => data <= x"00";
when "01" & x"0b9" => data <= x"20";
when "01" & x"0ba" => data <= x"33";
when "01" & x"0bb" => data <= x"80";
when "01" & x"0bc" => data <= x"df";
when "01" & x"0bd" => data <= x"45";
when "01" & x"0be" => data <= x"4f";
when "01" & x"0bf" => data <= x"46";
when "01" & x"0c0" => data <= x"00";
when "01" & x"0c1" => data <= x"20";
when "01" & x"0c2" => data <= x"11";
when "01" & x"0c3" => data <= x"84";
when "01" & x"0c4" => data <= x"20";
when "01" & x"0c5" => data <= x"a5";
when "01" & x"0c6" => data <= x"90";
when "01" & x"0c7" => data <= x"98";
when "01" & x"0c8" => data <= x"20";
when "01" & x"0c9" => data <= x"f8";
when "01" & x"0ca" => data <= x"92";
when "01" & x"0cb" => data <= x"d0";
when "01" & x"0cc" => data <= x"13";
when "01" & x"0cd" => data <= x"b9";
when "01" & x"0ce" => data <= x"17";
when "01" & x"0cf" => data <= x"11";
when "01" & x"0d0" => data <= x"29";
when "01" & x"0d1" => data <= x"10";
when "01" & x"0d2" => data <= x"d0";
when "01" & x"0d3" => data <= x"e5";
when "01" & x"0d4" => data <= x"a9";
when "01" & x"0d5" => data <= x"10";
when "01" & x"0d6" => data <= x"20";
when "01" & x"0d7" => data <= x"3c";
when "01" & x"0d8" => data <= x"91";
when "01" & x"0d9" => data <= x"ae";
when "01" & x"0da" => data <= x"c6";
when "01" & x"0db" => data <= x"10";
when "01" & x"0dc" => data <= x"a9";
when "01" & x"0dd" => data <= x"fe";
when "01" & x"0de" => data <= x"38";
when "01" & x"0df" => data <= x"60";
when "01" & x"0e0" => data <= x"b9";
when "01" & x"0e1" => data <= x"17";
when "01" & x"0e2" => data <= x"11";
when "01" & x"0e3" => data <= x"30";
when "01" & x"0e4" => data <= x"0a";
when "01" & x"0e5" => data <= x"20";
when "01" & x"0e6" => data <= x"83";
when "01" & x"0e7" => data <= x"8e";
when "01" & x"0e8" => data <= x"20";
when "01" & x"0e9" => data <= x"4b";
when "01" & x"0ea" => data <= x"91";
when "01" & x"0eb" => data <= x"38";
when "01" & x"0ec" => data <= x"20";
when "01" & x"0ed" => data <= x"53";
when "01" & x"0ee" => data <= x"91";
when "01" & x"0ef" => data <= x"b9";
when "01" & x"0f0" => data <= x"10";
when "01" & x"0f1" => data <= x"11";
when "01" & x"0f2" => data <= x"85";
when "01" & x"0f3" => data <= x"bc";
when "01" & x"0f4" => data <= x"b9";
when "01" & x"0f5" => data <= x"13";
when "01" & x"0f6" => data <= x"11";
when "01" & x"0f7" => data <= x"85";
when "01" & x"0f8" => data <= x"bd";
when "01" & x"0f9" => data <= x"a0";
when "01" & x"0fa" => data <= x"00";
when "01" & x"0fb" => data <= x"b1";
when "01" & x"0fc" => data <= x"bc";
when "01" & x"0fd" => data <= x"48";
when "01" & x"0fe" => data <= x"ac";
when "01" & x"0ff" => data <= x"c2";
when "01" & x"100" => data <= x"10";
when "01" & x"101" => data <= x"a6";
when "01" & x"102" => data <= x"bc";
when "01" & x"103" => data <= x"e8";
when "01" & x"104" => data <= x"8a";
when "01" & x"105" => data <= x"99";
when "01" & x"106" => data <= x"10";
when "01" & x"107" => data <= x"11";
when "01" & x"108" => data <= x"d0";
when "01" & x"109" => data <= x"14";
when "01" & x"10a" => data <= x"18";
when "01" & x"10b" => data <= x"b9";
when "01" & x"10c" => data <= x"11";
when "01" & x"10d" => data <= x"11";
when "01" & x"10e" => data <= x"69";
when "01" & x"10f" => data <= x"01";
when "01" & x"110" => data <= x"99";
when "01" & x"111" => data <= x"11";
when "01" & x"112" => data <= x"11";
when "01" & x"113" => data <= x"b9";
when "01" & x"114" => data <= x"12";
when "01" & x"115" => data <= x"11";
when "01" & x"116" => data <= x"69";
when "01" & x"117" => data <= x"00";
when "01" & x"118" => data <= x"99";
when "01" & x"119" => data <= x"12";
when "01" & x"11a" => data <= x"11";
when "01" & x"11b" => data <= x"20";
when "01" & x"11c" => data <= x"41";
when "01" & x"11d" => data <= x"91";
when "01" & x"11e" => data <= x"18";
when "01" & x"11f" => data <= x"68";
when "01" & x"120" => data <= x"60";
when "01" & x"121" => data <= x"18";
when "01" & x"122" => data <= x"b9";
when "01" & x"123" => data <= x"0f";
when "01" & x"124" => data <= x"11";
when "01" & x"125" => data <= x"79";
when "01" & x"126" => data <= x"11";
when "01" & x"127" => data <= x"11";
when "01" & x"128" => data <= x"85";
when "01" & x"129" => data <= x"c5";
when "01" & x"12a" => data <= x"99";
when "01" & x"12b" => data <= x"1c";
when "01" & x"12c" => data <= x"11";
when "01" & x"12d" => data <= x"b9";
when "01" & x"12e" => data <= x"0d";
when "01" & x"12f" => data <= x"11";
when "01" & x"130" => data <= x"29";
when "01" & x"131" => data <= x"03";
when "01" & x"132" => data <= x"79";
when "01" & x"133" => data <= x"12";
when "01" & x"134" => data <= x"11";
when "01" & x"135" => data <= x"85";
when "01" & x"136" => data <= x"c4";
when "01" & x"137" => data <= x"99";
when "01" & x"138" => data <= x"1d";
when "01" & x"139" => data <= x"11";
when "01" & x"13a" => data <= x"a9";
when "01" & x"13b" => data <= x"80";
when "01" & x"13c" => data <= x"19";
when "01" & x"13d" => data <= x"17";
when "01" & x"13e" => data <= x"11";
when "01" & x"13f" => data <= x"d0";
when "01" & x"140" => data <= x"05";
when "01" & x"141" => data <= x"a9";
when "01" & x"142" => data <= x"7f";
when "01" & x"143" => data <= x"39";
when "01" & x"144" => data <= x"17";
when "01" & x"145" => data <= x"11";
when "01" & x"146" => data <= x"99";
when "01" & x"147" => data <= x"17";
when "01" & x"148" => data <= x"11";
when "01" & x"149" => data <= x"18";
when "01" & x"14a" => data <= x"60";
when "01" & x"14b" => data <= x"b9";
when "01" & x"14c" => data <= x"17";
when "01" & x"14d" => data <= x"11";
when "01" & x"14e" => data <= x"29";
when "01" & x"14f" => data <= x"40";
when "01" & x"150" => data <= x"f0";
when "01" & x"151" => data <= x"3d";
when "01" & x"152" => data <= x"18";
when "01" & x"153" => data <= x"08";
when "01" & x"154" => data <= x"20";
when "01" & x"155" => data <= x"3e";
when "01" & x"156" => data <= x"be";
when "01" & x"157" => data <= x"ac";
when "01" & x"158" => data <= x"c2";
when "01" & x"159" => data <= x"10";
when "01" & x"15a" => data <= x"b9";
when "01" & x"15b" => data <= x"13";
when "01" & x"15c" => data <= x"11";
when "01" & x"15d" => data <= x"85";
when "01" & x"15e" => data <= x"bf";
when "01" & x"15f" => data <= x"20";
when "01" & x"160" => data <= x"8d";
when "01" & x"161" => data <= x"a0";
when "01" & x"162" => data <= x"a9";
when "01" & x"163" => data <= x"00";
when "01" & x"164" => data <= x"85";
when "01" & x"165" => data <= x"be";
when "01" & x"166" => data <= x"85";
when "01" & x"167" => data <= x"c2";
when "01" & x"168" => data <= x"a9";
when "01" & x"169" => data <= x"01";
when "01" & x"16a" => data <= x"85";
when "01" & x"16b" => data <= x"c3";
when "01" & x"16c" => data <= x"28";
when "01" & x"16d" => data <= x"b0";
when "01" & x"16e" => data <= x"17";
when "01" & x"16f" => data <= x"b9";
when "01" & x"170" => data <= x"1c";
when "01" & x"171" => data <= x"11";
when "01" & x"172" => data <= x"85";
when "01" & x"173" => data <= x"c5";
when "01" & x"174" => data <= x"b9";
when "01" & x"175" => data <= x"1d";
when "01" & x"176" => data <= x"11";
when "01" & x"177" => data <= x"85";
when "01" & x"178" => data <= x"c4";
when "01" & x"179" => data <= x"20";
when "01" & x"17a" => data <= x"8f";
when "01" & x"17b" => data <= x"87";
when "01" & x"17c" => data <= x"ac";
when "01" & x"17d" => data <= x"c2";
when "01" & x"17e" => data <= x"10";
when "01" & x"17f" => data <= x"a9";
when "01" & x"180" => data <= x"bf";
when "01" & x"181" => data <= x"20";
when "01" & x"182" => data <= x"43";
when "01" & x"183" => data <= x"91";
when "01" & x"184" => data <= x"90";
when "01" & x"185" => data <= x"06";
when "01" & x"186" => data <= x"20";
when "01" & x"187" => data <= x"21";
when "01" & x"188" => data <= x"91";
when "01" & x"189" => data <= x"20";
when "01" & x"18a" => data <= x"c6";
when "01" & x"18b" => data <= x"87";
when "01" & x"18c" => data <= x"ac";
when "01" & x"18d" => data <= x"c2";
when "01" & x"18e" => data <= x"10";
when "01" & x"18f" => data <= x"60";
when "01" & x"190" => data <= x"4c";
when "01" & x"191" => data <= x"ad";
when "01" & x"192" => data <= x"90";
when "01" & x"193" => data <= x"4c";
when "01" & x"194" => data <= x"41";
when "01" & x"195" => data <= x"98";
when "01" & x"196" => data <= x"20";
when "01" & x"197" => data <= x"2b";
when "01" & x"198" => data <= x"80";
when "01" & x"199" => data <= x"c1";
when "01" & x"19a" => data <= x"72";
when "01" & x"19b" => data <= x"65";
when "01" & x"19c" => data <= x"61";
when "01" & x"19d" => data <= x"64";
when "01" & x"19e" => data <= x"20";
when "01" & x"19f" => data <= x"6f";
when "01" & x"1a0" => data <= x"6e";
when "01" & x"1a1" => data <= x"6c";
when "01" & x"1a2" => data <= x"79";
when "01" & x"1a3" => data <= x"00";
when "01" & x"1a4" => data <= x"20";
when "01" & x"1a5" => data <= x"e1";
when "01" & x"1a6" => data <= x"83";
when "01" & x"1a7" => data <= x"4c";
when "01" & x"1a8" => data <= x"b0";
when "01" & x"1a9" => data <= x"91";
when "01" & x"1aa" => data <= x"20";
when "01" & x"1ab" => data <= x"e1";
when "01" & x"1ac" => data <= x"83";
when "01" & x"1ad" => data <= x"20";
when "01" & x"1ae" => data <= x"a5";
when "01" & x"1af" => data <= x"90";
when "01" & x"1b0" => data <= x"48";
when "01" & x"1b1" => data <= x"b9";
when "01" & x"1b2" => data <= x"0c";
when "01" & x"1b3" => data <= x"11";
when "01" & x"1b4" => data <= x"30";
when "01" & x"1b5" => data <= x"e0";
when "01" & x"1b6" => data <= x"b9";
when "01" & x"1b7" => data <= x"0e";
when "01" & x"1b8" => data <= x"11";
when "01" & x"1b9" => data <= x"30";
when "01" & x"1ba" => data <= x"d8";
when "01" & x"1bb" => data <= x"20";
when "01" & x"1bc" => data <= x"83";
when "01" & x"1bd" => data <= x"8e";
when "01" & x"1be" => data <= x"98";
when "01" & x"1bf" => data <= x"18";
when "01" & x"1c0" => data <= x"69";
when "01" & x"1c1" => data <= x"04";
when "01" & x"1c2" => data <= x"20";
when "01" & x"1c3" => data <= x"f8";
when "01" & x"1c4" => data <= x"92";
when "01" & x"1c5" => data <= x"d0";
when "01" & x"1c6" => data <= x"76";
when "01" & x"1c7" => data <= x"20";
when "01" & x"1c8" => data <= x"58";
when "01" & x"1c9" => data <= x"8e";
when "01" & x"1ca" => data <= x"ae";
when "01" & x"1cb" => data <= x"c4";
when "01" & x"1cc" => data <= x"10";
when "01" & x"1cd" => data <= x"38";
when "01" & x"1ce" => data <= x"bd";
when "01" & x"1cf" => data <= x"07";
when "01" & x"1d0" => data <= x"0f";
when "01" & x"1d1" => data <= x"fd";
when "01" & x"1d2" => data <= x"0f";
when "01" & x"1d3" => data <= x"0f";
when "01" & x"1d4" => data <= x"48";
when "01" & x"1d5" => data <= x"bd";
when "01" & x"1d6" => data <= x"06";
when "01" & x"1d7" => data <= x"0f";
when "01" & x"1d8" => data <= x"fd";
when "01" & x"1d9" => data <= x"0e";
when "01" & x"1da" => data <= x"0f";
when "01" & x"1db" => data <= x"29";
when "01" & x"1dc" => data <= x"03";
when "01" & x"1dd" => data <= x"8d";
when "01" & x"1de" => data <= x"c3";
when "01" & x"1df" => data <= x"10";
when "01" & x"1e0" => data <= x"0a";
when "01" & x"1e1" => data <= x"0a";
when "01" & x"1e2" => data <= x"0a";
when "01" & x"1e3" => data <= x"0a";
when "01" & x"1e4" => data <= x"5d";
when "01" & x"1e5" => data <= x"0e";
when "01" & x"1e6" => data <= x"0f";
when "01" & x"1e7" => data <= x"29";
when "01" & x"1e8" => data <= x"30";
when "01" & x"1e9" => data <= x"5d";
when "01" & x"1ea" => data <= x"0e";
when "01" & x"1eb" => data <= x"0f";
when "01" & x"1ec" => data <= x"9d";
when "01" & x"1ed" => data <= x"0e";
when "01" & x"1ee" => data <= x"0f";
when "01" & x"1ef" => data <= x"ad";
when "01" & x"1f0" => data <= x"c3";
when "01" & x"1f1" => data <= x"10";
when "01" & x"1f2" => data <= x"d9";
when "01" & x"1f3" => data <= x"1a";
when "01" & x"1f4" => data <= x"11";
when "01" & x"1f5" => data <= x"d0";
when "01" & x"1f6" => data <= x"2b";
when "01" & x"1f7" => data <= x"68";
when "01" & x"1f8" => data <= x"d9";
when "01" & x"1f9" => data <= x"19";
when "01" & x"1fa" => data <= x"11";
when "01" & x"1fb" => data <= x"d0";
when "01" & x"1fc" => data <= x"26";
when "01" & x"1fd" => data <= x"84";
when "01" & x"1fe" => data <= x"b4";
when "01" & x"1ff" => data <= x"20";
when "01" & x"200" => data <= x"20";
when "01" & x"201" => data <= x"99";
when "01" & x"202" => data <= x"20";
when "01" & x"203" => data <= x"76";
when "01" & x"204" => data <= x"90";
when "01" & x"205" => data <= x"c4";
when "01" & x"206" => data <= x"b4";
when "01" & x"207" => data <= x"d0";
when "01" & x"208" => data <= x"03";
when "01" & x"209" => data <= x"20";
when "01" & x"20a" => data <= x"11";
when "01" & x"20b" => data <= x"99";
when "01" & x"20c" => data <= x"a4";
when "01" & x"20d" => data <= x"b4";
when "01" & x"20e" => data <= x"20";
when "01" & x"20f" => data <= x"05";
when "01" & x"210" => data <= x"8e";
when "01" & x"211" => data <= x"20";
when "01" & x"212" => data <= x"33";
when "01" & x"213" => data <= x"80";
when "01" & x"214" => data <= x"bf";
when "01" & x"215" => data <= x"43";
when "01" & x"216" => data <= x"61";
when "01" & x"217" => data <= x"6e";
when "01" & x"218" => data <= x"27";
when "01" & x"219" => data <= x"74";
when "01" & x"21a" => data <= x"20";
when "01" & x"21b" => data <= x"65";
when "01" & x"21c" => data <= x"78";
when "01" & x"21d" => data <= x"74";
when "01" & x"21e" => data <= x"65";
when "01" & x"21f" => data <= x"6e";
when "01" & x"220" => data <= x"64";
when "01" & x"221" => data <= x"00";
when "01" & x"222" => data <= x"68";
when "01" & x"223" => data <= x"9d";
when "01" & x"224" => data <= x"0d";
when "01" & x"225" => data <= x"0f";
when "01" & x"226" => data <= x"99";
when "01" & x"227" => data <= x"19";
when "01" & x"228" => data <= x"11";
when "01" & x"229" => data <= x"ad";
when "01" & x"22a" => data <= x"c3";
when "01" & x"22b" => data <= x"10";
when "01" & x"22c" => data <= x"99";
when "01" & x"22d" => data <= x"1a";
when "01" & x"22e" => data <= x"11";
when "01" & x"22f" => data <= x"a9";
when "01" & x"230" => data <= x"00";
when "01" & x"231" => data <= x"9d";
when "01" & x"232" => data <= x"0c";
when "01" & x"233" => data <= x"0f";
when "01" & x"234" => data <= x"20";
when "01" & x"235" => data <= x"b4";
when "01" & x"236" => data <= x"8a";
when "01" & x"237" => data <= x"ea";
when "01" & x"238" => data <= x"ea";
when "01" & x"239" => data <= x"ea";
when "01" & x"23a" => data <= x"ac";
when "01" & x"23b" => data <= x"c2";
when "01" & x"23c" => data <= x"10";
when "01" & x"23d" => data <= x"b9";
when "01" & x"23e" => data <= x"17";
when "01" & x"23f" => data <= x"11";
when "01" & x"240" => data <= x"30";
when "01" & x"241" => data <= x"17";
when "01" & x"242" => data <= x"20";
when "01" & x"243" => data <= x"4b";
when "01" & x"244" => data <= x"91";
when "01" & x"245" => data <= x"b9";
when "01" & x"246" => data <= x"14";
when "01" & x"247" => data <= x"11";
when "01" & x"248" => data <= x"d0";
when "01" & x"249" => data <= x"0b";
when "01" & x"24a" => data <= x"98";
when "01" & x"24b" => data <= x"20";
when "01" & x"24c" => data <= x"f8";
when "01" & x"24d" => data <= x"92";
when "01" & x"24e" => data <= x"d0";
when "01" & x"24f" => data <= x"05";
when "01" & x"250" => data <= x"20";
when "01" & x"251" => data <= x"21";
when "01" & x"252" => data <= x"91";
when "01" & x"253" => data <= x"d0";
when "01" & x"254" => data <= x"04";
when "01" & x"255" => data <= x"38";
when "01" & x"256" => data <= x"20";
when "01" & x"257" => data <= x"53";
when "01" & x"258" => data <= x"91";
when "01" & x"259" => data <= x"b9";
when "01" & x"25a" => data <= x"10";
when "01" & x"25b" => data <= x"11";
when "01" & x"25c" => data <= x"85";
when "01" & x"25d" => data <= x"bc";
when "01" & x"25e" => data <= x"b9";
when "01" & x"25f" => data <= x"13";
when "01" & x"260" => data <= x"11";
when "01" & x"261" => data <= x"85";
when "01" & x"262" => data <= x"bd";
when "01" & x"263" => data <= x"68";
when "01" & x"264" => data <= x"a0";
when "01" & x"265" => data <= x"00";
when "01" & x"266" => data <= x"91";
when "01" & x"267" => data <= x"bc";
when "01" & x"268" => data <= x"ac";
when "01" & x"269" => data <= x"c2";
when "01" & x"26a" => data <= x"10";
when "01" & x"26b" => data <= x"a9";
when "01" & x"26c" => data <= x"40";
when "01" & x"26d" => data <= x"20";
when "01" & x"26e" => data <= x"3c";
when "01" & x"26f" => data <= x"91";
when "01" & x"270" => data <= x"e6";
when "01" & x"271" => data <= x"bc";
when "01" & x"272" => data <= x"a5";
when "01" & x"273" => data <= x"bc";
when "01" & x"274" => data <= x"99";
when "01" & x"275" => data <= x"10";
when "01" & x"276" => data <= x"11";
when "01" & x"277" => data <= x"d0";
when "01" & x"278" => data <= x"13";
when "01" & x"279" => data <= x"20";
when "01" & x"27a" => data <= x"41";
when "01" & x"27b" => data <= x"91";
when "01" & x"27c" => data <= x"b9";
when "01" & x"27d" => data <= x"11";
when "01" & x"27e" => data <= x"11";
when "01" & x"27f" => data <= x"69";
when "01" & x"280" => data <= x"01";
when "01" & x"281" => data <= x"99";
when "01" & x"282" => data <= x"11";
when "01" & x"283" => data <= x"11";
when "01" & x"284" => data <= x"b9";
when "01" & x"285" => data <= x"12";
when "01" & x"286" => data <= x"11";
when "01" & x"287" => data <= x"69";
when "01" & x"288" => data <= x"00";
when "01" & x"289" => data <= x"99";
when "01" & x"28a" => data <= x"12";
when "01" & x"28b" => data <= x"11";
when "01" & x"28c" => data <= x"98";
when "01" & x"28d" => data <= x"20";
when "01" & x"28e" => data <= x"f8";
when "01" & x"28f" => data <= x"92";
when "01" & x"290" => data <= x"90";
when "01" & x"291" => data <= x"14";
when "01" & x"292" => data <= x"a9";
when "01" & x"293" => data <= x"20";
when "01" & x"294" => data <= x"20";
when "01" & x"295" => data <= x"3c";
when "01" & x"296" => data <= x"91";
when "01" & x"297" => data <= x"a2";
when "01" & x"298" => data <= x"02";
when "01" & x"299" => data <= x"b9";
when "01" & x"29a" => data <= x"10";
when "01" & x"29b" => data <= x"11";
when "01" & x"29c" => data <= x"99";
when "01" & x"29d" => data <= x"14";
when "01" & x"29e" => data <= x"11";
when "01" & x"29f" => data <= x"c8";
when "01" & x"2a0" => data <= x"ca";
when "01" & x"2a1" => data <= x"10";
when "01" & x"2a2" => data <= x"f6";
when "01" & x"2a3" => data <= x"88";
when "01" & x"2a4" => data <= x"88";
when "01" & x"2a5" => data <= x"88";
when "01" & x"2a6" => data <= x"60";
when "01" & x"2a7" => data <= x"20";
when "01" & x"2a8" => data <= x"e1";
when "01" & x"2a9" => data <= x"83";
when "01" & x"2aa" => data <= x"20";
when "01" & x"2ab" => data <= x"a5";
when "01" & x"2ac" => data <= x"90";
when "01" & x"2ad" => data <= x"20";
when "01" & x"2ae" => data <= x"63";
when "01" & x"2af" => data <= x"a1";
when "01" & x"2b0" => data <= x"ea";
when "01" & x"2b1" => data <= x"ea";
when "01" & x"2b2" => data <= x"ea";
when "01" & x"2b3" => data <= x"ea";
when "01" & x"2b4" => data <= x"ea";
when "01" & x"2b5" => data <= x"ea";
when "01" & x"2b6" => data <= x"20";
when "01" & x"2b7" => data <= x"10";
when "01" & x"2b8" => data <= x"93";
when "01" & x"2b9" => data <= x"b0";
when "01" & x"2ba" => data <= x"08";
when "01" & x"2bb" => data <= x"a9";
when "01" & x"2bc" => data <= x"00";
when "01" & x"2bd" => data <= x"20";
when "01" & x"2be" => data <= x"a4";
when "01" & x"2bf" => data <= x"91";
when "01" & x"2c0" => data <= x"4c";
when "01" & x"2c1" => data <= x"b6";
when "01" & x"2c2" => data <= x"92";
when "01" & x"2c3" => data <= x"b5";
when "01" & x"2c4" => data <= x"00";
when "01" & x"2c5" => data <= x"99";
when "01" & x"2c6" => data <= x"10";
when "01" & x"2c7" => data <= x"11";
when "01" & x"2c8" => data <= x"b5";
when "01" & x"2c9" => data <= x"01";
when "01" & x"2ca" => data <= x"99";
when "01" & x"2cb" => data <= x"11";
when "01" & x"2cc" => data <= x"11";
when "01" & x"2cd" => data <= x"b5";
when "01" & x"2ce" => data <= x"02";
when "01" & x"2cf" => data <= x"99";
when "01" & x"2d0" => data <= x"12";
when "01" & x"2d1" => data <= x"11";
when "01" & x"2d2" => data <= x"a9";
when "01" & x"2d3" => data <= x"6f";
when "01" & x"2d4" => data <= x"20";
when "01" & x"2d5" => data <= x"43";
when "01" & x"2d6" => data <= x"91";
when "01" & x"2d7" => data <= x"b9";
when "01" & x"2d8" => data <= x"0f";
when "01" & x"2d9" => data <= x"11";
when "01" & x"2da" => data <= x"79";
when "01" & x"2db" => data <= x"11";
when "01" & x"2dc" => data <= x"11";
when "01" & x"2dd" => data <= x"8d";
when "01" & x"2de" => data <= x"c5";
when "01" & x"2df" => data <= x"10";
when "01" & x"2e0" => data <= x"b9";
when "01" & x"2e1" => data <= x"0d";
when "01" & x"2e2" => data <= x"11";
when "01" & x"2e3" => data <= x"29";
when "01" & x"2e4" => data <= x"03";
when "01" & x"2e5" => data <= x"79";
when "01" & x"2e6" => data <= x"12";
when "01" & x"2e7" => data <= x"11";
when "01" & x"2e8" => data <= x"d9";
when "01" & x"2e9" => data <= x"1d";
when "01" & x"2ea" => data <= x"11";
when "01" & x"2eb" => data <= x"d0";
when "01" & x"2ec" => data <= x"b9";
when "01" & x"2ed" => data <= x"ad";
when "01" & x"2ee" => data <= x"c5";
when "01" & x"2ef" => data <= x"10";
when "01" & x"2f0" => data <= x"d9";
when "01" & x"2f1" => data <= x"1c";
when "01" & x"2f2" => data <= x"11";
when "01" & x"2f3" => data <= x"d0";
when "01" & x"2f4" => data <= x"b1";
when "01" & x"2f5" => data <= x"4c";
when "01" & x"2f6" => data <= x"3a";
when "01" & x"2f7" => data <= x"91";
when "01" & x"2f8" => data <= x"aa";
when "01" & x"2f9" => data <= x"b9";
when "01" & x"2fa" => data <= x"12";
when "01" & x"2fb" => data <= x"11";
when "01" & x"2fc" => data <= x"dd";
when "01" & x"2fd" => data <= x"16";
when "01" & x"2fe" => data <= x"11";
when "01" & x"2ff" => data <= x"d0";
when "01" & x"300" => data <= x"0e";
when "01" & x"301" => data <= x"b9";
when "01" & x"302" => data <= x"11";
when "01" & x"303" => data <= x"11";
when "01" & x"304" => data <= x"dd";
when "01" & x"305" => data <= x"15";
when "01" & x"306" => data <= x"11";
when "01" & x"307" => data <= x"d0";
when "01" & x"308" => data <= x"06";
when "01" & x"309" => data <= x"b9";
when "01" & x"30a" => data <= x"10";
when "01" & x"30b" => data <= x"11";
when "01" & x"30c" => data <= x"dd";
when "01" & x"30d" => data <= x"14";
when "01" & x"30e" => data <= x"11";
when "01" & x"30f" => data <= x"60";
when "01" & x"310" => data <= x"b9";
when "01" & x"311" => data <= x"14";
when "01" & x"312" => data <= x"11";
when "01" & x"313" => data <= x"d5";
when "01" & x"314" => data <= x"00";
when "01" & x"315" => data <= x"b9";
when "01" & x"316" => data <= x"15";
when "01" & x"317" => data <= x"11";
when "01" & x"318" => data <= x"f5";
when "01" & x"319" => data <= x"01";
when "01" & x"31a" => data <= x"b9";
when "01" & x"31b" => data <= x"16";
when "01" & x"31c" => data <= x"11";
when "01" & x"31d" => data <= x"f5";
when "01" & x"31e" => data <= x"02";
when "01" & x"31f" => data <= x"60";
when "01" & x"320" => data <= x"a5";
when "01" & x"321" => data <= x"b3";
when "01" & x"322" => data <= x"48";
when "01" & x"323" => data <= x"a9";
when "01" & x"324" => data <= x"ff";
when "01" & x"325" => data <= x"8d";
when "01" & x"326" => data <= x"de";
when "01" & x"327" => data <= x"10";
when "01" & x"328" => data <= x"20";
when "01" & x"329" => data <= x"65";
when "01" & x"32a" => data <= x"80";
when "01" & x"32b" => data <= x"53";
when "01" & x"32c" => data <= x"6d";
when "01" & x"32d" => data <= x"61";
when "01" & x"32e" => data <= x"72";
when "01" & x"32f" => data <= x"74";
when "01" & x"330" => data <= x"20";
when "01" & x"331" => data <= x"53";
when "01" & x"332" => data <= x"50";
when "01" & x"333" => data <= x"49";
when "01" & x"334" => data <= x"0d";
when "01" & x"335" => data <= x"0d";
when "01" & x"336" => data <= x"90";
when "01" & x"337" => data <= x"03";
when "01" & x"338" => data <= x"4c";
when "01" & x"339" => data <= x"28";
when "01" & x"33a" => data <= x"b1";
when "01" & x"33b" => data <= x"a9";
when "01" & x"33c" => data <= x"00";
when "01" & x"33d" => data <= x"ba";
when "01" & x"33e" => data <= x"9d";
when "01" & x"33f" => data <= x"06";
when "01" & x"340" => data <= x"01";
when "01" & x"341" => data <= x"a9";
when "01" & x"342" => data <= x"06";
when "01" & x"343" => data <= x"20";
when "01" & x"344" => data <= x"15";
when "01" & x"345" => data <= x"80";
when "01" & x"346" => data <= x"a2";
when "01" & x"347" => data <= x"0d";
when "01" & x"348" => data <= x"bd";
when "01" & x"349" => data <= x"49";
when "01" & x"34a" => data <= x"99";
when "01" & x"34b" => data <= x"9d";
when "01" & x"34c" => data <= x"12";
when "01" & x"34d" => data <= x"02";
when "01" & x"34e" => data <= x"ca";
when "01" & x"34f" => data <= x"10";
when "01" & x"350" => data <= x"f7";
when "01" & x"351" => data <= x"20";
when "01" & x"352" => data <= x"28";
when "01" & x"353" => data <= x"99";
when "01" & x"354" => data <= x"84";
when "01" & x"355" => data <= x"b1";
when "01" & x"356" => data <= x"86";
when "01" & x"357" => data <= x"b0";
when "01" & x"358" => data <= x"a2";
when "01" & x"359" => data <= x"07";
when "01" & x"35a" => data <= x"a0";
when "01" & x"35b" => data <= x"1b";
when "01" & x"35c" => data <= x"b9";
when "01" & x"35d" => data <= x"3c";
when "01" & x"35e" => data <= x"99";
when "01" & x"35f" => data <= x"91";
when "01" & x"360" => data <= x"b0";
when "01" & x"361" => data <= x"c8";
when "01" & x"362" => data <= x"b9";
when "01" & x"363" => data <= x"3c";
when "01" & x"364" => data <= x"99";
when "01" & x"365" => data <= x"91";
when "01" & x"366" => data <= x"b0";
when "01" & x"367" => data <= x"c8";
when "01" & x"368" => data <= x"a5";
when "01" & x"369" => data <= x"f4";
when "01" & x"36a" => data <= x"91";
when "01" & x"36b" => data <= x"b0";
when "01" & x"36c" => data <= x"c8";
when "01" & x"36d" => data <= x"ca";
when "01" & x"36e" => data <= x"d0";
when "01" & x"36f" => data <= x"ec";
when "01" & x"370" => data <= x"86";
when "01" & x"371" => data <= x"cf";
when "01" & x"372" => data <= x"8c";
when "01" & x"373" => data <= x"82";
when "01" & x"374" => data <= x"10";
when "01" & x"375" => data <= x"a2";
when "01" & x"376" => data <= x"0f";
when "01" & x"377" => data <= x"20";
when "01" & x"378" => data <= x"2c";
when "01" & x"379" => data <= x"99";
when "01" & x"37a" => data <= x"20";
when "01" & x"37b" => data <= x"9e";
when "01" & x"37c" => data <= x"98";
when "01" & x"37d" => data <= x"a0";
when "01" & x"37e" => data <= x"d4";
when "01" & x"37f" => data <= x"b1";
when "01" & x"380" => data <= x"b0";
when "01" & x"381" => data <= x"10";
when "01" & x"382" => data <= x"2f";
when "01" & x"383" => data <= x"a0";
when "01" & x"384" => data <= x"d5";
when "01" & x"385" => data <= x"b1";
when "01" & x"386" => data <= x"b0";
when "01" & x"387" => data <= x"30";
when "01" & x"388" => data <= x"27";
when "01" & x"389" => data <= x"20";
when "01" & x"38a" => data <= x"8f";
when "01" & x"38b" => data <= x"98";
when "01" & x"38c" => data <= x"a0";
when "01" & x"38d" => data <= x"00";
when "01" & x"38e" => data <= x"b1";
when "01" & x"38f" => data <= x"b0";
when "01" & x"390" => data <= x"c0";
when "01" & x"391" => data <= x"c0";
when "01" & x"392" => data <= x"90";
when "01" & x"393" => data <= x"05";
when "01" & x"394" => data <= x"99";
when "01" & x"395" => data <= x"00";
when "01" & x"396" => data <= x"10";
when "01" & x"397" => data <= x"b0";
when "01" & x"398" => data <= x"03";
when "01" & x"399" => data <= x"99";
when "01" & x"39a" => data <= x"00";
when "01" & x"39b" => data <= x"11";
when "01" & x"39c" => data <= x"88";
when "01" & x"39d" => data <= x"d0";
when "01" & x"39e" => data <= x"ef";
when "01" & x"39f" => data <= x"a9";
when "01" & x"3a0" => data <= x"a0";
when "01" & x"3a1" => data <= x"a8";
when "01" & x"3a2" => data <= x"48";
when "01" & x"3a3" => data <= x"a9";
when "01" & x"3a4" => data <= x"3f";
when "01" & x"3a5" => data <= x"20";
when "01" & x"3a6" => data <= x"43";
when "01" & x"3a7" => data <= x"91";
when "01" & x"3a8" => data <= x"68";
when "01" & x"3a9" => data <= x"99";
when "01" & x"3aa" => data <= x"1d";
when "01" & x"3ab" => data <= x"11";
when "01" & x"3ac" => data <= x"e9";
when "01" & x"3ad" => data <= x"1f";
when "01" & x"3ae" => data <= x"d0";
when "01" & x"3af" => data <= x"f1";
when "01" & x"3b0" => data <= x"68";
when "01" & x"3b1" => data <= x"60";
when "01" & x"3b2" => data <= x"a9";
when "01" & x"3b3" => data <= x"ff";
when "01" & x"3b4" => data <= x"91";
when "01" & x"3b5" => data <= x"b0";
when "01" & x"3b6" => data <= x"8d";
when "01" & x"3b7" => data <= x"d4";
when "01" & x"3b8" => data <= x"10";
when "01" & x"3b9" => data <= x"20";
when "01" & x"3ba" => data <= x"8f";
when "01" & x"3bb" => data <= x"98";
when "01" & x"3bc" => data <= x"20";
when "01" & x"3bd" => data <= x"24";
when "01" & x"3be" => data <= x"99";
when "01" & x"3bf" => data <= x"8a";
when "01" & x"3c0" => data <= x"49";
when "01" & x"3c1" => data <= x"ff";
when "01" & x"3c2" => data <= x"8d";
when "01" & x"3c3" => data <= x"d7";
when "01" & x"3c4" => data <= x"10";
when "01" & x"3c5" => data <= x"a9";
when "01" & x"3c6" => data <= x"24";
when "01" & x"3c7" => data <= x"8d";
when "01" & x"3c8" => data <= x"ca";
when "01" & x"3c9" => data <= x"10";
when "01" & x"3ca" => data <= x"8d";
when "01" & x"3cb" => data <= x"cc";
when "01" & x"3cc" => data <= x"10";
when "01" & x"3cd" => data <= x"a0";
when "01" & x"3ce" => data <= x"00";
when "01" & x"3cf" => data <= x"8c";
when "01" & x"3d0" => data <= x"cb";
when "01" & x"3d1" => data <= x"10";
when "01" & x"3d2" => data <= x"8c";
when "01" & x"3d3" => data <= x"cd";
when "01" & x"3d4" => data <= x"10";
when "01" & x"3d5" => data <= x"a0";
when "01" & x"3d6" => data <= x"00";
when "01" & x"3d7" => data <= x"8c";
when "01" & x"3d8" => data <= x"c0";
when "01" & x"3d9" => data <= x"10";
when "01" & x"3da" => data <= x"8c";
when "01" & x"3db" => data <= x"c9";
when "01" & x"3dc" => data <= x"10";
when "01" & x"3dd" => data <= x"88";
when "01" & x"3de" => data <= x"8c";
when "01" & x"3df" => data <= x"c8";
when "01" & x"3e0" => data <= x"10";
when "01" & x"3e1" => data <= x"8c";
when "01" & x"3e2" => data <= x"c7";
when "01" & x"3e3" => data <= x"10";
when "01" & x"3e4" => data <= x"8c";
when "01" & x"3e5" => data <= x"de";
when "01" & x"3e6" => data <= x"10";
when "01" & x"3e7" => data <= x"20";
when "01" & x"3e8" => data <= x"37";
when "01" & x"3e9" => data <= x"b1";
when "01" & x"3ea" => data <= x"4c";
when "01" & x"3eb" => data <= x"04";
when "01" & x"3ec" => data <= x"94";
when "01" & x"3ed" => data <= x"00";
when "01" & x"3ee" => data <= x"00";
when "01" & x"3ef" => data <= x"00";
when "01" & x"3f0" => data <= x"00";
when "01" & x"3f1" => data <= x"00";
when "01" & x"3f2" => data <= x"00";
when "01" & x"3f3" => data <= x"00";
when "01" & x"3f4" => data <= x"00";
when "01" & x"3f5" => data <= x"00";
when "01" & x"3f6" => data <= x"00";
when "01" & x"3f7" => data <= x"00";
when "01" & x"3f8" => data <= x"00";
when "01" & x"3f9" => data <= x"00";
when "01" & x"3fa" => data <= x"00";
when "01" & x"3fb" => data <= x"00";
when "01" & x"3fc" => data <= x"00";
when "01" & x"3fd" => data <= x"00";
when "01" & x"3fe" => data <= x"00";
when "01" & x"3ff" => data <= x"00";
when "01" & x"400" => data <= x"00";
when "01" & x"401" => data <= x"00";
when "01" & x"402" => data <= x"00";
when "01" & x"403" => data <= x"00";
when "01" & x"404" => data <= x"68";
when "01" & x"405" => data <= x"d0";
when "01" & x"406" => data <= x"34";
when "01" & x"407" => data <= x"20";
when "01" & x"408" => data <= x"41";
when "01" & x"409" => data <= x"af";
when "01" & x"40a" => data <= x"a0";
when "01" & x"40b" => data <= x"00";
when "01" & x"40c" => data <= x"a2";
when "01" & x"40d" => data <= x"00";
when "01" & x"40e" => data <= x"ad";
when "01" & x"40f" => data <= x"06";
when "01" & x"410" => data <= x"0f";
when "01" & x"411" => data <= x"20";
when "01" & x"412" => data <= x"05";
when "01" & x"413" => data <= x"82";
when "01" & x"414" => data <= x"f0";
when "01" & x"415" => data <= x"25";
when "01" & x"416" => data <= x"48";
when "01" & x"417" => data <= x"a2";
when "01" & x"418" => data <= x"43";
when "01" & x"419" => data <= x"a0";
when "01" & x"41a" => data <= x"99";
when "01" & x"41b" => data <= x"20";
when "01" & x"41c" => data <= x"b8";
when "01" & x"41d" => data <= x"86";
when "01" & x"41e" => data <= x"20";
when "01" & x"41f" => data <= x"fe";
when "01" & x"420" => data <= x"80";
when "01" & x"421" => data <= x"20";
when "01" & x"422" => data <= x"96";
when "01" & x"423" => data <= x"82";
when "01" & x"424" => data <= x"68";
when "01" & x"425" => data <= x"b0";
when "01" & x"426" => data <= x"15";
when "01" & x"427" => data <= x"20";
when "01" & x"428" => data <= x"65";
when "01" & x"429" => data <= x"80";
when "01" & x"42a" => data <= x"46";
when "01" & x"42b" => data <= x"69";
when "01" & x"42c" => data <= x"6c";
when "01" & x"42d" => data <= x"65";
when "01" & x"42e" => data <= x"20";
when "01" & x"42f" => data <= x"6e";
when "01" & x"430" => data <= x"6f";
when "01" & x"431" => data <= x"74";
when "01" & x"432" => data <= x"20";
when "01" & x"433" => data <= x"66";
when "01" & x"434" => data <= x"6f";
when "01" & x"435" => data <= x"75";
when "01" & x"436" => data <= x"6e";
when "01" & x"437" => data <= x"64";
when "01" & x"438" => data <= x"0d";
when "01" & x"439" => data <= x"0d";
when "01" & x"43a" => data <= x"ea";
when "01" & x"43b" => data <= x"60";
when "01" & x"43c" => data <= x"c9";
when "01" & x"43d" => data <= x"02";
when "01" & x"43e" => data <= x"90";
when "01" & x"43f" => data <= x"0e";
when "01" & x"440" => data <= x"f0";
when "01" & x"441" => data <= x"06";
when "01" & x"442" => data <= x"a2";
when "01" & x"443" => data <= x"41";
when "01" & x"444" => data <= x"a0";
when "01" & x"445" => data <= x"99";
when "01" & x"446" => data <= x"d0";
when "01" & x"447" => data <= x"0a";
when "01" & x"448" => data <= x"a2";
when "01" & x"449" => data <= x"43";
when "01" & x"44a" => data <= x"a0";
when "01" & x"44b" => data <= x"99";
when "01" & x"44c" => data <= x"d0";
when "01" & x"44d" => data <= x"04";
when "01" & x"44e" => data <= x"a2";
when "01" & x"44f" => data <= x"39";
when "01" & x"450" => data <= x"a0";
when "01" & x"451" => data <= x"99";
when "01" & x"452" => data <= x"4c";
when "01" & x"453" => data <= x"f7";
when "01" & x"454" => data <= x"ff";
when "01" & x"455" => data <= x"c9";
when "01" & x"456" => data <= x"01";
when "01" & x"457" => data <= x"d0";
when "01" & x"458" => data <= x"07";
when "01" & x"459" => data <= x"c0";
when "01" & x"45a" => data <= x"17";
when "01" & x"45b" => data <= x"b0";
when "01" & x"45c" => data <= x"02";
when "01" & x"45d" => data <= x"a0";
when "01" & x"45e" => data <= x"17";
when "01" & x"45f" => data <= x"60";
when "01" & x"460" => data <= x"c9";
when "01" & x"461" => data <= x"02";
when "01" & x"462" => data <= x"d0";
when "01" & x"463" => data <= x"1a";
when "01" & x"464" => data <= x"48";
when "01" & x"465" => data <= x"69";
when "01" & x"466" => data <= x"12";
when "01" & x"467" => data <= x"85";
when "01" & x"468" => data <= x"b1";
when "01" & x"469" => data <= x"9d";
when "01" & x"46a" => data <= x"f0";
when "01" & x"46b" => data <= x"0d";
when "01" & x"46c" => data <= x"98";
when "01" & x"46d" => data <= x"ea";
when "01" & x"46e" => data <= x"48";
when "01" & x"46f" => data <= x"a9";
when "01" & x"470" => data <= x"00";
when "01" & x"471" => data <= x"85";
when "01" & x"472" => data <= x"b0";
when "01" & x"473" => data <= x"a0";
when "01" & x"474" => data <= x"d4";
when "01" & x"475" => data <= x"91";
when "01" & x"476" => data <= x"b0";
when "01" & x"477" => data <= x"c8";
when "01" & x"478" => data <= x"91";
when "01" & x"479" => data <= x"b0";
when "01" & x"47a" => data <= x"68";
when "01" & x"47b" => data <= x"a8";
when "01" & x"47c" => data <= x"68";
when "01" & x"47d" => data <= x"60";
when "01" & x"47e" => data <= x"c9";
when "01" & x"47f" => data <= x"03";
when "01" & x"480" => data <= x"d0";
when "01" & x"481" => data <= x"19";
when "01" & x"482" => data <= x"84";
when "01" & x"483" => data <= x"b3";
when "01" & x"484" => data <= x"20";
when "01" & x"485" => data <= x"e1";
when "01" & x"486" => data <= x"83";
when "01" & x"487" => data <= x"4c";
when "01" & x"488" => data <= x"8f";
when "01" & x"489" => data <= x"a9";
when "01" & x"48a" => data <= x"f4";
when "01" & x"48b" => data <= x"ff";
when "01" & x"48c" => data <= x"8a";
when "01" & x"48d" => data <= x"30";
when "01" & x"48e" => data <= x"09";
when "01" & x"48f" => data <= x"c9";
when "01" & x"490" => data <= x"32";
when "01" & x"491" => data <= x"d0";
when "01" & x"492" => data <= x"ea";
when "01" & x"493" => data <= x"a9";
when "01" & x"494" => data <= x"78";
when "01" & x"495" => data <= x"20";
when "01" & x"496" => data <= x"f4";
when "01" & x"497" => data <= x"ff";
when "01" & x"498" => data <= x"4c";
when "01" & x"499" => data <= x"20";
when "01" & x"49a" => data <= x"93";
when "01" & x"49b" => data <= x"c9";
when "01" & x"49c" => data <= x"04";
when "01" & x"49d" => data <= x"d0";
when "01" & x"49e" => data <= x"08";
when "01" & x"49f" => data <= x"20";
when "01" & x"4a0" => data <= x"e1";
when "01" & x"4a1" => data <= x"83";
when "01" & x"4a2" => data <= x"a2";
when "01" & x"4a3" => data <= x"72";
when "01" & x"4a4" => data <= x"4c";
when "01" & x"4a5" => data <= x"71";
when "01" & x"4a6" => data <= x"86";
when "01" & x"4a7" => data <= x"c9";
when "01" & x"4a8" => data <= x"09";
when "01" & x"4a9" => data <= x"d0";
when "01" & x"4aa" => data <= x"12";
when "01" & x"4ab" => data <= x"20";
when "01" & x"4ac" => data <= x"e1";
when "01" & x"4ad" => data <= x"83";
when "01" & x"4ae" => data <= x"4c";
when "01" & x"4af" => data <= x"cc";
when "01" & x"4b0" => data <= x"b3";
when "01" & x"4b1" => data <= x"a0";
when "01" & x"4b2" => data <= x"c9";
when "01" & x"4b3" => data <= x"0d";
when "01" & x"4b4" => data <= x"d0";
when "01" & x"4b5" => data <= x"ee";
when "01" & x"4b6" => data <= x"98";
when "01" & x"4b7" => data <= x"e8";
when "01" & x"4b8" => data <= x"a0";
when "01" & x"4b9" => data <= x"02";
when "01" & x"4ba" => data <= x"4c";
when "01" & x"4bb" => data <= x"cb";
when "01" & x"4bc" => data <= x"99";
when "01" & x"4bd" => data <= x"c9";
when "01" & x"4be" => data <= x"0a";
when "01" & x"4bf" => data <= x"d0";
when "01" & x"4c0" => data <= x"29";
when "01" & x"4c1" => data <= x"20";
when "01" & x"4c2" => data <= x"e1";
when "01" & x"4c3" => data <= x"83";
when "01" & x"4c4" => data <= x"20";
when "01" & x"4c5" => data <= x"9e";
when "01" & x"4c6" => data <= x"98";
when "01" & x"4c7" => data <= x"a0";
when "01" & x"4c8" => data <= x"d5";
when "01" & x"4c9" => data <= x"b1";
when "01" & x"4ca" => data <= x"b0";
when "01" & x"4cb" => data <= x"10";
when "01" & x"4cc" => data <= x"1c";
when "01" & x"4cd" => data <= x"a0";
when "01" & x"4ce" => data <= x"00";
when "01" & x"4cf" => data <= x"c0";
when "01" & x"4d0" => data <= x"c0";
when "01" & x"4d1" => data <= x"90";
when "01" & x"4d2" => data <= x"05";
when "01" & x"4d3" => data <= x"b9";
when "01" & x"4d4" => data <= x"00";
when "01" & x"4d5" => data <= x"10";
when "01" & x"4d6" => data <= x"b0";
when "01" & x"4d7" => data <= x"03";
when "01" & x"4d8" => data <= x"b9";
when "01" & x"4d9" => data <= x"00";
when "01" & x"4da" => data <= x"11";
when "01" & x"4db" => data <= x"91";
when "01" & x"4dc" => data <= x"b0";
when "01" & x"4dd" => data <= x"88";
when "01" & x"4de" => data <= x"d0";
when "01" & x"4df" => data <= x"ef";
when "01" & x"4e0" => data <= x"20";
when "01" & x"4e1" => data <= x"f2";
when "01" & x"4e2" => data <= x"8f";
when "01" & x"4e3" => data <= x"a0";
when "01" & x"4e4" => data <= x"d5";
when "01" & x"4e5" => data <= x"a9";
when "01" & x"4e6" => data <= x"00";
when "01" & x"4e7" => data <= x"91";
when "01" & x"4e8" => data <= x"b0";
when "01" & x"4e9" => data <= x"60";
when "01" & x"4ea" => data <= x"c9";
when "01" & x"4eb" => data <= x"08";
when "01" & x"4ec" => data <= x"d0";
when "01" & x"4ed" => data <= x"15";
when "01" & x"4ee" => data <= x"20";
when "01" & x"4ef" => data <= x"11";
when "01" & x"4f0" => data <= x"84";
when "01" & x"4f1" => data <= x"a4";
when "01" & x"4f2" => data <= x"f0";
when "01" & x"4f3" => data <= x"84";
when "01" & x"4f4" => data <= x"b0";
when "01" & x"4f5" => data <= x"a4";
when "01" & x"4f6" => data <= x"f1";
when "01" & x"4f7" => data <= x"84";
when "01" & x"4f8" => data <= x"b1";
when "01" & x"4f9" => data <= x"a4";
when "01" & x"4fa" => data <= x"ef";
when "01" & x"4fb" => data <= x"c0";
when "01" & x"4fc" => data <= x"7f";
when "01" & x"4fd" => data <= x"d0";
when "01" & x"4fe" => data <= x"4c";
when "01" & x"4ff" => data <= x"4c";
when "01" & x"500" => data <= x"46";
when "01" & x"501" => data <= x"be";
when "01" & x"502" => data <= x"00";
when "01" & x"503" => data <= x"4c";
when "01" & x"504" => data <= x"f6";
when "01" & x"505" => data <= x"a0";
when "01" & x"506" => data <= x"00";
when "01" & x"507" => data <= x"00";
when "01" & x"508" => data <= x"00";
when "01" & x"509" => data <= x"00";
when "01" & x"50a" => data <= x"00";
when "01" & x"50b" => data <= x"00";
when "01" & x"50c" => data <= x"00";
when "01" & x"50d" => data <= x"00";
when "01" & x"50e" => data <= x"00";
when "01" & x"50f" => data <= x"00";
when "01" & x"510" => data <= x"00";
when "01" & x"511" => data <= x"00";
when "01" & x"512" => data <= x"00";
when "01" & x"513" => data <= x"00";
when "01" & x"514" => data <= x"00";
when "01" & x"515" => data <= x"00";
when "01" & x"516" => data <= x"00";
when "01" & x"517" => data <= x"00";
when "01" & x"518" => data <= x"00";
when "01" & x"519" => data <= x"00";
when "01" & x"51a" => data <= x"00";
when "01" & x"51b" => data <= x"00";
when "01" & x"51c" => data <= x"00";
when "01" & x"51d" => data <= x"00";
when "01" & x"51e" => data <= x"00";
when "01" & x"51f" => data <= x"00";
when "01" & x"520" => data <= x"00";
when "01" & x"521" => data <= x"00";
when "01" & x"522" => data <= x"00";
when "01" & x"523" => data <= x"00";
when "01" & x"524" => data <= x"00";
when "01" & x"525" => data <= x"00";
when "01" & x"526" => data <= x"00";
when "01" & x"527" => data <= x"00";
when "01" & x"528" => data <= x"00";
when "01" & x"529" => data <= x"00";
when "01" & x"52a" => data <= x"00";
when "01" & x"52b" => data <= x"00";
when "01" & x"52c" => data <= x"00";
when "01" & x"52d" => data <= x"00";
when "01" & x"52e" => data <= x"00";
when "01" & x"52f" => data <= x"00";
when "01" & x"530" => data <= x"00";
when "01" & x"531" => data <= x"00";
when "01" & x"532" => data <= x"00";
when "01" & x"533" => data <= x"00";
when "01" & x"534" => data <= x"00";
when "01" & x"535" => data <= x"00";
when "01" & x"536" => data <= x"00";
when "01" & x"537" => data <= x"00";
when "01" & x"538" => data <= x"00";
when "01" & x"539" => data <= x"00";
when "01" & x"53a" => data <= x"00";
when "01" & x"53b" => data <= x"00";
when "01" & x"53c" => data <= x"00";
when "01" & x"53d" => data <= x"00";
when "01" & x"53e" => data <= x"00";
when "01" & x"53f" => data <= x"00";
when "01" & x"540" => data <= x"00";
when "01" & x"541" => data <= x"00";
when "01" & x"542" => data <= x"00";
when "01" & x"543" => data <= x"00";
when "01" & x"544" => data <= x"00";
when "01" & x"545" => data <= x"00";
when "01" & x"546" => data <= x"00";
when "01" & x"547" => data <= x"00";
when "01" & x"548" => data <= x"00";
when "01" & x"549" => data <= x"00";
when "01" & x"54a" => data <= x"00";
when "01" & x"54b" => data <= x"c0";
when "01" & x"54c" => data <= x"7d";
when "01" & x"54d" => data <= x"90";
when "01" & x"54e" => data <= x"2b";
when "01" & x"54f" => data <= x"20";
when "01" & x"550" => data <= x"4d";
when "01" & x"551" => data <= x"83";
when "01" & x"552" => data <= x"20";
when "01" & x"553" => data <= x"47";
when "01" & x"554" => data <= x"83";
when "01" & x"555" => data <= x"c0";
when "01" & x"556" => data <= x"7e";
when "01" & x"557" => data <= x"f0";
when "01" & x"558" => data <= x"09";
when "01" & x"559" => data <= x"a0";
when "01" & x"55a" => data <= x"00";
when "01" & x"55b" => data <= x"ad";
when "01" & x"55c" => data <= x"04";
when "01" & x"55d" => data <= x"0f";
when "01" & x"55e" => data <= x"91";
when "01" & x"55f" => data <= x"b0";
when "01" & x"560" => data <= x"98";
when "01" & x"561" => data <= x"60";
when "01" & x"562" => data <= x"a9";
when "01" & x"563" => data <= x"00";
when "01" & x"564" => data <= x"a8";
when "01" & x"565" => data <= x"91";
when "01" & x"566" => data <= x"b0";
when "01" & x"567" => data <= x"c8";
when "01" & x"568" => data <= x"ad";
when "01" & x"569" => data <= x"07";
when "01" & x"56a" => data <= x"0f";
when "01" & x"56b" => data <= x"91";
when "01" & x"56c" => data <= x"b0";
when "01" & x"56d" => data <= x"c8";
when "01" & x"56e" => data <= x"ad";
when "01" & x"56f" => data <= x"06";
when "01" & x"570" => data <= x"0f";
when "01" & x"571" => data <= x"29";
when "01" & x"572" => data <= x"03";
when "01" & x"573" => data <= x"91";
when "01" & x"574" => data <= x"b0";
when "01" & x"575" => data <= x"c8";
when "01" & x"576" => data <= x"a9";
when "01" & x"577" => data <= x"00";
when "01" & x"578" => data <= x"91";
when "01" & x"579" => data <= x"b0";
when "01" & x"57a" => data <= x"60";
when "01" & x"57b" => data <= x"20";
when "01" & x"57c" => data <= x"11";
when "01" & x"57d" => data <= x"84";
when "01" & x"57e" => data <= x"48";
when "01" & x"57f" => data <= x"20";
when "01" & x"580" => data <= x"62";
when "01" & x"581" => data <= x"82";
when "01" & x"582" => data <= x"86";
when "01" & x"583" => data <= x"b0";
when "01" & x"584" => data <= x"8e";
when "01" & x"585" => data <= x"dc";
when "01" & x"586" => data <= x"10";
when "01" & x"587" => data <= x"84";
when "01" & x"588" => data <= x"b1";
when "01" & x"589" => data <= x"8c";
when "01" & x"58a" => data <= x"dd";
when "01" & x"58b" => data <= x"10";
when "01" & x"58c" => data <= x"a2";
when "01" & x"58d" => data <= x"00";
when "01" & x"58e" => data <= x"a0";
when "01" & x"58f" => data <= x"00";
when "01" & x"590" => data <= x"20";
when "01" & x"591" => data <= x"ea";
when "01" & x"592" => data <= x"80";
when "01" & x"593" => data <= x"20";
when "01" & x"594" => data <= x"da";
when "01" & x"595" => data <= x"80";
when "01" & x"596" => data <= x"c0";
when "01" & x"597" => data <= x"12";
when "01" & x"598" => data <= x"d0";
when "01" & x"599" => data <= x"f9";
when "01" & x"59a" => data <= x"68";
when "01" & x"59b" => data <= x"aa";
when "01" & x"59c" => data <= x"e8";
when "01" & x"59d" => data <= x"e0";
when "01" & x"59e" => data <= x"08";
when "01" & x"59f" => data <= x"b0";
when "01" & x"5a0" => data <= x"08";
when "01" & x"5a1" => data <= x"bd";
when "01" & x"5a2" => data <= x"8c";
when "01" & x"5a3" => data <= x"99";
when "01" & x"5a4" => data <= x"48";
when "01" & x"5a5" => data <= x"bd";
when "01" & x"5a6" => data <= x"84";
when "01" & x"5a7" => data <= x"99";
when "01" & x"5a8" => data <= x"48";
when "01" & x"5a9" => data <= x"60";
when "01" & x"5aa" => data <= x"c9";
when "01" & x"5ab" => data <= x"09";
when "01" & x"5ac" => data <= x"b0";
when "01" & x"5ad" => data <= x"fb";
when "01" & x"5ae" => data <= x"86";
when "01" & x"5af" => data <= x"b5";
when "01" & x"5b0" => data <= x"aa";
when "01" & x"5b1" => data <= x"bd";
when "01" & x"5b2" => data <= x"75";
when "01" & x"5b3" => data <= x"99";
when "01" & x"5b4" => data <= x"48";
when "01" & x"5b5" => data <= x"bd";
when "01" & x"5b6" => data <= x"6c";
when "01" & x"5b7" => data <= x"99";
when "01" & x"5b8" => data <= x"48";
when "01" & x"5b9" => data <= x"8a";
when "01" & x"5ba" => data <= x"a6";
when "01" & x"5bb" => data <= x"b5";
when "01" & x"5bc" => data <= x"60";
when "01" & x"5bd" => data <= x"a9";
when "01" & x"5be" => data <= x"ff";
when "01" & x"5bf" => data <= x"95";
when "01" & x"5c0" => data <= x"02";
when "01" & x"5c1" => data <= x"95";
when "01" & x"5c2" => data <= x"03";
when "01" & x"5c3" => data <= x"ad";
when "01" & x"5c4" => data <= x"da";
when "01" & x"5c5" => data <= x"10";
when "01" & x"5c6" => data <= x"95";
when "01" & x"5c7" => data <= x"00";
when "01" & x"5c8" => data <= x"ad";
when "01" & x"5c9" => data <= x"db";
when "01" & x"5ca" => data <= x"10";
when "01" & x"5cb" => data <= x"95";
when "01" & x"5cc" => data <= x"01";
when "01" & x"5cd" => data <= x"a9";
when "01" & x"5ce" => data <= x"00";
when "01" & x"5cf" => data <= x"60";
when "01" & x"5d0" => data <= x"c9";
when "01" & x"5d1" => data <= x"09";
when "01" & x"5d2" => data <= x"b0";
when "01" & x"5d3" => data <= x"fb";
when "01" & x"5d4" => data <= x"20";
when "01" & x"5d5" => data <= x"e1";
when "01" & x"5d6" => data <= x"83";
when "01" & x"5d7" => data <= x"8e";
when "01" & x"5d8" => data <= x"7d";
when "01" & x"5d9" => data <= x"10";
when "01" & x"5da" => data <= x"8c";
when "01" & x"5db" => data <= x"7e";
when "01" & x"5dc" => data <= x"10";
when "01" & x"5dd" => data <= x"a8";
when "01" & x"5de" => data <= x"ba";
when "01" & x"5df" => data <= x"a9";
when "01" & x"5e0" => data <= x"00";
when "01" & x"5e1" => data <= x"4c";
when "01" & x"5e2" => data <= x"d8";
when "01" & x"5e3" => data <= x"a0";
when "01" & x"5e4" => data <= x"b9";
when "01" & x"5e5" => data <= x"ab";
when "01" & x"5e6" => data <= x"99";
when "01" & x"5e7" => data <= x"8d";
when "01" & x"5e8" => data <= x"d8";
when "01" & x"5e9" => data <= x"10";
when "01" & x"5ea" => data <= x"b9";
when "01" & x"5eb" => data <= x"b4";
when "01" & x"5ec" => data <= x"99";
when "01" & x"5ed" => data <= x"8d";
when "01" & x"5ee" => data <= x"d9";
when "01" & x"5ef" => data <= x"10";
when "01" & x"5f0" => data <= x"b9";
when "01" & x"5f1" => data <= x"bd";
when "01" & x"5f2" => data <= x"99";
when "01" & x"5f3" => data <= x"4a";
when "01" & x"5f4" => data <= x"08";
when "01" & x"5f5" => data <= x"4a";
when "01" & x"5f6" => data <= x"08";
when "01" & x"5f7" => data <= x"8d";
when "01" & x"5f8" => data <= x"7f";
when "01" & x"5f9" => data <= x"10";
when "01" & x"5fa" => data <= x"20";
when "01" & x"5fb" => data <= x"56";
when "01" & x"5fc" => data <= x"97";
when "01" & x"5fd" => data <= x"a0";
when "01" & x"5fe" => data <= x"0c";
when "01" & x"5ff" => data <= x"b1";
when "01" & x"600" => data <= x"b4";
when "01" & x"601" => data <= x"99";
when "01" & x"602" => data <= x"60";
when "01" & x"603" => data <= x"10";
when "01" & x"604" => data <= x"88";
when "01" & x"605" => data <= x"10";
when "01" & x"606" => data <= x"f8";
when "01" & x"607" => data <= x"ad";
when "01" & x"608" => data <= x"63";
when "01" & x"609" => data <= x"10";
when "01" & x"60a" => data <= x"2d";
when "01" & x"60b" => data <= x"64";
when "01" & x"60c" => data <= x"10";
when "01" & x"60d" => data <= x"0d";
when "01" & x"60e" => data <= x"d7";
when "01" & x"60f" => data <= x"10";
when "01" & x"610" => data <= x"18";
when "01" & x"611" => data <= x"69";
when "01" & x"612" => data <= x"01";
when "01" & x"613" => data <= x"4c";
when "01" & x"614" => data <= x"eb";
when "01" & x"615" => data <= x"a0";
when "01" & x"616" => data <= x"ea";
when "01" & x"617" => data <= x"8d";
when "01" & x"618" => data <= x"81";
when "01" & x"619" => data <= x"10";
when "01" & x"61a" => data <= x"ad";
when "01" & x"61b" => data <= x"7f";
when "01" & x"61c" => data <= x"10";
when "01" & x"61d" => data <= x"b0";
when "01" & x"61e" => data <= x"07";
when "01" & x"61f" => data <= x"a2";
when "01" & x"620" => data <= x"61";
when "01" & x"621" => data <= x"a0";
when "01" & x"622" => data <= x"10";
when "01" & x"623" => data <= x"20";
when "01" & x"624" => data <= x"06";
when "01" & x"625" => data <= x"04";
when "01" & x"626" => data <= x"28";
when "01" & x"627" => data <= x"b0";
when "01" & x"628" => data <= x"04";
when "01" & x"629" => data <= x"28";
when "01" & x"62a" => data <= x"6c";
when "01" & x"62b" => data <= x"d8";
when "01" & x"62c" => data <= x"10";
when "01" & x"62d" => data <= x"a2";
when "01" & x"62e" => data <= x"03";
when "01" & x"62f" => data <= x"bd";
when "01" & x"630" => data <= x"69";
when "01" & x"631" => data <= x"10";
when "01" & x"632" => data <= x"95";
when "01" & x"633" => data <= x"b6";
when "01" & x"634" => data <= x"ca";
when "01" & x"635" => data <= x"10";
when "01" & x"636" => data <= x"f8";
when "01" & x"637" => data <= x"a2";
when "01" & x"638" => data <= x"b6";
when "01" & x"639" => data <= x"ac";
when "01" & x"63a" => data <= x"60";
when "01" & x"63b" => data <= x"10";
when "01" & x"63c" => data <= x"a9";
when "01" & x"63d" => data <= x"00";
when "01" & x"63e" => data <= x"28";
when "01" & x"63f" => data <= x"b0";
when "01" & x"640" => data <= x"03";
when "01" & x"641" => data <= x"20";
when "01" & x"642" => data <= x"a7";
when "01" & x"643" => data <= x"92";
when "01" & x"644" => data <= x"20";
when "01" & x"645" => data <= x"2e";
when "01" & x"646" => data <= x"90";
when "01" & x"647" => data <= x"a2";
when "01" & x"648" => data <= x"03";
when "01" & x"649" => data <= x"b5";
when "01" & x"64a" => data <= x"b6";
when "01" & x"64b" => data <= x"9d";
when "01" & x"64c" => data <= x"69";
when "01" & x"64d" => data <= x"10";
when "01" & x"64e" => data <= x"ca";
when "01" & x"64f" => data <= x"10";
when "01" & x"650" => data <= x"f8";
when "01" & x"651" => data <= x"20";
when "01" & x"652" => data <= x"48";
when "01" & x"653" => data <= x"97";
when "01" & x"654" => data <= x"30";
when "01" & x"655" => data <= x"0d";
when "01" & x"656" => data <= x"ac";
when "01" & x"657" => data <= x"60";
when "01" & x"658" => data <= x"10";
when "01" & x"659" => data <= x"20";
when "01" & x"65a" => data <= x"2a";
when "01" & x"65b" => data <= x"96";
when "01" & x"65c" => data <= x"b0";
when "01" & x"65d" => data <= x"0d";
when "01" & x"65e" => data <= x"a2";
when "01" & x"65f" => data <= x"09";
when "01" & x"660" => data <= x"20";
when "01" & x"661" => data <= x"3c";
when "01" & x"662" => data <= x"97";
when "01" & x"663" => data <= x"a2";
when "01" & x"664" => data <= x"05";
when "01" & x"665" => data <= x"20";
when "01" & x"666" => data <= x"3c";
when "01" & x"667" => data <= x"97";
when "01" & x"668" => data <= x"d0";
when "01" & x"669" => data <= x"ec";
when "01" & x"66a" => data <= x"18";
when "01" & x"66b" => data <= x"08";
when "01" & x"66c" => data <= x"20";
when "01" & x"66d" => data <= x"48";
when "01" & x"66e" => data <= x"97";
when "01" & x"66f" => data <= x"a2";
when "01" & x"670" => data <= x"05";
when "01" & x"671" => data <= x"20";
when "01" & x"672" => data <= x"3c";
when "01" & x"673" => data <= x"97";
when "01" & x"674" => data <= x"a0";
when "01" & x"675" => data <= x"0c";
when "01" & x"676" => data <= x"20";
when "01" & x"677" => data <= x"56";
when "01" & x"678" => data <= x"97";
when "01" & x"679" => data <= x"b9";
when "01" & x"67a" => data <= x"60";
when "01" & x"67b" => data <= x"10";
when "01" & x"67c" => data <= x"91";
when "01" & x"67d" => data <= x"b4";
when "01" & x"67e" => data <= x"88";
when "01" & x"67f" => data <= x"10";
when "01" & x"680" => data <= x"f8";
when "01" & x"681" => data <= x"28";
when "01" & x"682" => data <= x"60";
when "01" & x"683" => data <= x"20";
when "01" & x"684" => data <= x"4d";
when "01" & x"685" => data <= x"83";
when "01" & x"686" => data <= x"20";
when "01" & x"687" => data <= x"41";
when "01" & x"688" => data <= x"af";
when "01" & x"689" => data <= x"a9";
when "01" & x"68a" => data <= x"95";
when "01" & x"68b" => data <= x"8d";
when "01" & x"68c" => data <= x"d8";
when "01" & x"68d" => data <= x"10";
when "01" & x"68e" => data <= x"a9";
when "01" & x"68f" => data <= x"96";
when "01" & x"690" => data <= x"8d";
when "01" & x"691" => data <= x"d9";
when "01" & x"692" => data <= x"10";
when "01" & x"693" => data <= x"d0";
when "01" & x"694" => data <= x"bc";
when "01" & x"695" => data <= x"ac";
when "01" & x"696" => data <= x"69";
when "01" & x"697" => data <= x"10";
when "01" & x"698" => data <= x"cc";
when "01" & x"699" => data <= x"05";
when "01" & x"69a" => data <= x"0f";
when "01" & x"69b" => data <= x"b0";
when "01" & x"69c" => data <= x"28";
when "01" & x"69d" => data <= x"b9";
when "01" & x"69e" => data <= x"0f";
when "01" & x"69f" => data <= x"0e";
when "01" & x"6a0" => data <= x"20";
when "01" & x"6a1" => data <= x"ee";
when "01" & x"6a2" => data <= x"82";
when "01" & x"6a3" => data <= x"45";
when "01" & x"6a4" => data <= x"ce";
when "01" & x"6a5" => data <= x"b0";
when "01" & x"6a6" => data <= x"02";
when "01" & x"6a7" => data <= x"29";
when "01" & x"6a8" => data <= x"df";
when "01" & x"6a9" => data <= x"29";
when "01" & x"6aa" => data <= x"7f";
when "01" & x"6ab" => data <= x"f0";
when "01" & x"6ac" => data <= x"05";
when "01" & x"6ad" => data <= x"20";
when "01" & x"6ae" => data <= x"10";
when "01" & x"6af" => data <= x"82";
when "01" & x"6b0" => data <= x"d0";
when "01" & x"6b1" => data <= x"e6";
when "01" & x"6b2" => data <= x"a9";
when "01" & x"6b3" => data <= x"07";
when "01" & x"6b4" => data <= x"20";
when "01" & x"6b5" => data <= x"6a";
when "01" & x"6b6" => data <= x"97";
when "01" & x"6b7" => data <= x"85";
when "01" & x"6b8" => data <= x"b0";
when "01" & x"6b9" => data <= x"b9";
when "01" & x"6ba" => data <= x"08";
when "01" & x"6bb" => data <= x"0e";
when "01" & x"6bc" => data <= x"20";
when "01" & x"6bd" => data <= x"6a";
when "01" & x"6be" => data <= x"97";
when "01" & x"6bf" => data <= x"c8";
when "01" & x"6c0" => data <= x"c6";
when "01" & x"6c1" => data <= x"b0";
when "01" & x"6c2" => data <= x"d0";
when "01" & x"6c3" => data <= x"f5";
when "01" & x"6c4" => data <= x"18";
when "01" & x"6c5" => data <= x"8c";
when "01" & x"6c6" => data <= x"69";
when "01" & x"6c7" => data <= x"10";
when "01" & x"6c8" => data <= x"ad";
when "01" & x"6c9" => data <= x"04";
when "01" & x"6ca" => data <= x"0f";
when "01" & x"6cb" => data <= x"8d";
when "01" & x"6cc" => data <= x"60";
when "01" & x"6cd" => data <= x"10";
when "01" & x"6ce" => data <= x"60";
when "01" & x"6cf" => data <= x"20";
when "01" & x"6d0" => data <= x"4d";
when "01" & x"6d1" => data <= x"83";
when "01" & x"6d2" => data <= x"20";
when "01" & x"6d3" => data <= x"41";
when "01" & x"6d4" => data <= x"af";
when "01" & x"6d5" => data <= x"a9";
when "01" & x"6d6" => data <= x"0c";
when "01" & x"6d7" => data <= x"20";
when "01" & x"6d8" => data <= x"6a";
when "01" & x"6d9" => data <= x"97";
when "01" & x"6da" => data <= x"a0";
when "01" & x"6db" => data <= x"00";
when "01" & x"6dc" => data <= x"b9";
when "01" & x"6dd" => data <= x"00";
when "01" & x"6de" => data <= x"0e";
when "01" & x"6df" => data <= x"20";
when "01" & x"6e0" => data <= x"6a";
when "01" & x"6e1" => data <= x"97";
when "01" & x"6e2" => data <= x"c8";
when "01" & x"6e3" => data <= x"c0";
when "01" & x"6e4" => data <= x"08";
when "01" & x"6e5" => data <= x"d0";
when "01" & x"6e6" => data <= x"f5";
when "01" & x"6e7" => data <= x"b9";
when "01" & x"6e8" => data <= x"f8";
when "01" & x"6e9" => data <= x"0e";
when "01" & x"6ea" => data <= x"20";
when "01" & x"6eb" => data <= x"6a";
when "01" & x"6ec" => data <= x"97";
when "01" & x"6ed" => data <= x"c8";
when "01" & x"6ee" => data <= x"c0";
when "01" & x"6ef" => data <= x"0c";
when "01" & x"6f0" => data <= x"d0";
when "01" & x"6f1" => data <= x"f5";
when "01" & x"6f2" => data <= x"ad";
when "01" & x"6f3" => data <= x"06";
when "01" & x"6f4" => data <= x"0f";
when "01" & x"6f5" => data <= x"20";
when "01" & x"6f6" => data <= x"05";
when "01" & x"6f7" => data <= x"82";
when "01" & x"6f8" => data <= x"20";
when "01" & x"6f9" => data <= x"6a";
when "01" & x"6fa" => data <= x"97";
when "01" & x"6fb" => data <= x"a5";
when "01" & x"6fc" => data <= x"cf";
when "01" & x"6fd" => data <= x"4c";
when "01" & x"6fe" => data <= x"6a";
when "01" & x"6ff" => data <= x"97";
when "01" & x"700" => data <= x"20";
when "01" & x"701" => data <= x"61";
when "01" & x"702" => data <= x"97";
when "01" & x"703" => data <= x"ad";
when "01" & x"704" => data <= x"cb";
when "01" & x"705" => data <= x"10";
when "01" & x"706" => data <= x"09";
when "01" & x"707" => data <= x"30";
when "01" & x"708" => data <= x"20";
when "01" & x"709" => data <= x"6a";
when "01" & x"70a" => data <= x"97";
when "01" & x"70b" => data <= x"20";
when "01" & x"70c" => data <= x"61";
when "01" & x"70d" => data <= x"97";
when "01" & x"70e" => data <= x"ad";
when "01" & x"70f" => data <= x"ca";
when "01" & x"710" => data <= x"10";
when "01" & x"711" => data <= x"4c";
when "01" & x"712" => data <= x"6a";
when "01" & x"713" => data <= x"97";
when "01" & x"714" => data <= x"20";
when "01" & x"715" => data <= x"61";
when "01" & x"716" => data <= x"97";
when "01" & x"717" => data <= x"ad";
when "01" & x"718" => data <= x"cd";
when "01" & x"719" => data <= x"10";
when "01" & x"71a" => data <= x"09";
when "01" & x"71b" => data <= x"30";
when "01" & x"71c" => data <= x"20";
when "01" & x"71d" => data <= x"6a";
when "01" & x"71e" => data <= x"97";
when "01" & x"71f" => data <= x"20";
when "01" & x"720" => data <= x"61";
when "01" & x"721" => data <= x"97";
when "01" & x"722" => data <= x"ad";
when "01" & x"723" => data <= x"cc";
when "01" & x"724" => data <= x"10";
when "01" & x"725" => data <= x"4c";
when "01" & x"726" => data <= x"6a";
when "01" & x"727" => data <= x"97";
when "01" & x"728" => data <= x"48";
when "01" & x"729" => data <= x"ad";
when "01" & x"72a" => data <= x"61";
when "01" & x"72b" => data <= x"10";
when "01" & x"72c" => data <= x"85";
when "01" & x"72d" => data <= x"b8";
when "01" & x"72e" => data <= x"ad";
when "01" & x"72f" => data <= x"62";
when "01" & x"730" => data <= x"10";
when "01" & x"731" => data <= x"85";
when "01" & x"732" => data <= x"b9";
when "01" & x"733" => data <= x"a2";
when "01" & x"734" => data <= x"00";
when "01" & x"735" => data <= x"68";
when "01" & x"736" => data <= x"60";
when "01" & x"737" => data <= x"20";
when "01" & x"738" => data <= x"e1";
when "01" & x"739" => data <= x"83";
when "01" & x"73a" => data <= x"a2";
when "01" & x"73b" => data <= x"01";
when "01" & x"73c" => data <= x"a0";
when "01" & x"73d" => data <= x"04";
when "01" & x"73e" => data <= x"fe";
when "01" & x"73f" => data <= x"60";
when "01" & x"740" => data <= x"10";
when "01" & x"741" => data <= x"d0";
when "01" & x"742" => data <= x"04";
when "01" & x"743" => data <= x"e8";
when "01" & x"744" => data <= x"88";
when "01" & x"745" => data <= x"d0";
when "01" & x"746" => data <= x"f7";
when "01" & x"747" => data <= x"60";
when "01" & x"748" => data <= x"a2";
when "01" & x"749" => data <= x"03";
when "01" & x"74a" => data <= x"a9";
when "01" & x"74b" => data <= x"ff";
when "01" & x"74c" => data <= x"5d";
when "01" & x"74d" => data <= x"65";
when "01" & x"74e" => data <= x"10";
when "01" & x"74f" => data <= x"9d";
when "01" & x"750" => data <= x"65";
when "01" & x"751" => data <= x"10";
when "01" & x"752" => data <= x"ca";
when "01" & x"753" => data <= x"10";
when "01" & x"754" => data <= x"f5";
when "01" & x"755" => data <= x"60";
when "01" & x"756" => data <= x"ad";
when "01" & x"757" => data <= x"7d";
when "01" & x"758" => data <= x"10";
when "01" & x"759" => data <= x"85";
when "01" & x"75a" => data <= x"b4";
when "01" & x"75b" => data <= x"ad";
when "01" & x"75c" => data <= x"7e";
when "01" & x"75d" => data <= x"10";
when "01" & x"75e" => data <= x"85";
when "01" & x"75f" => data <= x"b5";
when "01" & x"760" => data <= x"60";
when "01" & x"761" => data <= x"a9";
when "01" & x"762" => data <= x"01";
when "01" & x"763" => data <= x"d0";
when "01" & x"764" => data <= x"05";
when "01" & x"765" => data <= x"20";
when "01" & x"766" => data <= x"c1";
when "01" & x"767" => data <= x"90";
when "01" & x"768" => data <= x"b0";
when "01" & x"769" => data <= x"f6";
when "01" & x"76a" => data <= x"2c";
when "01" & x"76b" => data <= x"81";
when "01" & x"76c" => data <= x"10";
when "01" & x"76d" => data <= x"10";
when "01" & x"76e" => data <= x"06";
when "01" & x"76f" => data <= x"8d";
when "01" & x"770" => data <= x"e5";
when "01" & x"771" => data <= x"fe";
when "01" & x"772" => data <= x"4c";
when "01" & x"773" => data <= x"37";
when "01" & x"774" => data <= x"97";
when "01" & x"775" => data <= x"20";
when "01" & x"776" => data <= x"28";
when "01" & x"777" => data <= x"97";
when "01" & x"778" => data <= x"81";
when "01" & x"779" => data <= x"b8";
when "01" & x"77a" => data <= x"4c";
when "01" & x"77b" => data <= x"37";
when "01" & x"77c" => data <= x"97";
when "01" & x"77d" => data <= x"20";
when "01" & x"77e" => data <= x"85";
when "01" & x"77f" => data <= x"97";
when "01" & x"780" => data <= x"20";
when "01" & x"781" => data <= x"aa";
when "01" & x"782" => data <= x"91";
when "01" & x"783" => data <= x"18";
when "01" & x"784" => data <= x"60";
when "01" & x"785" => data <= x"2c";
when "01" & x"786" => data <= x"81";
when "01" & x"787" => data <= x"10";
when "01" & x"788" => data <= x"10";
when "01" & x"789" => data <= x"06";
when "01" & x"78a" => data <= x"ad";
when "01" & x"78b" => data <= x"e5";
when "01" & x"78c" => data <= x"fe";
when "01" & x"78d" => data <= x"4c";
when "01" & x"78e" => data <= x"37";
when "01" & x"78f" => data <= x"97";
when "01" & x"790" => data <= x"20";
when "01" & x"791" => data <= x"28";
when "01" & x"792" => data <= x"97";
when "01" & x"793" => data <= x"a1";
when "01" & x"794" => data <= x"b8";
when "01" & x"795" => data <= x"4c";
when "01" & x"796" => data <= x"37";
when "01" & x"797" => data <= x"97";
when "01" & x"798" => data <= x"2c";
when "01" & x"799" => data <= x"c8";
when "01" & x"79a" => data <= x"10";
when "01" & x"79b" => data <= x"30";
when "01" & x"79c" => data <= x"03";
when "01" & x"79d" => data <= x"ce";
when "01" & x"79e" => data <= x"c8";
when "01" & x"79f" => data <= x"10";
when "01" & x"7a0" => data <= x"60";
when "01" & x"7a1" => data <= x"20";
when "01" & x"7a2" => data <= x"5a";
when "01" & x"7a3" => data <= x"98";
when "01" & x"7a4" => data <= x"20";
when "01" & x"7a5" => data <= x"7e";
when "01" & x"7a6" => data <= x"83";
when "01" & x"7a7" => data <= x"a9";
when "01" & x"7a8" => data <= x"01";
when "01" & x"7a9" => data <= x"60";
when "01" & x"7aa" => data <= x"20";
when "01" & x"7ab" => data <= x"37";
when "01" & x"7ac" => data <= x"98";
when "01" & x"7ad" => data <= x"20";
when "01" & x"7ae" => data <= x"7e";
when "01" & x"7af" => data <= x"83";
when "01" & x"7b0" => data <= x"20";
when "01" & x"7b1" => data <= x"d1";
when "01" & x"7b2" => data <= x"82";
when "01" & x"7b3" => data <= x"90";
when "01" & x"7b4" => data <= x"24";
when "01" & x"7b5" => data <= x"20";
when "01" & x"7b6" => data <= x"37";
when "01" & x"7b7" => data <= x"98";
when "01" & x"7b8" => data <= x"20";
when "01" & x"7b9" => data <= x"df";
when "01" & x"7ba" => data <= x"97";
when "01" & x"7bb" => data <= x"20";
when "01" & x"7bc" => data <= x"fb";
when "01" & x"7bd" => data <= x"97";
when "01" & x"7be" => data <= x"50";
when "01" & x"7bf" => data <= x"16";
when "01" & x"7c0" => data <= x"20";
when "01" & x"7c1" => data <= x"37";
when "01" & x"7c2" => data <= x"98";
when "01" & x"7c3" => data <= x"20";
when "01" & x"7c4" => data <= x"df";
when "01" & x"7c5" => data <= x"97";
when "01" & x"7c6" => data <= x"50";
when "01" & x"7c7" => data <= x"11";
when "01" & x"7c8" => data <= x"20";
when "01" & x"7c9" => data <= x"37";
when "01" & x"7ca" => data <= x"98";
when "01" & x"7cb" => data <= x"20";
when "01" & x"7cc" => data <= x"fb";
when "01" & x"7cd" => data <= x"97";
when "01" & x"7ce" => data <= x"50";
when "01" & x"7cf" => data <= x"09";
when "01" & x"7d0" => data <= x"20";
when "01" & x"7d1" => data <= x"5a";
when "01" & x"7d2" => data <= x"98";
when "01" & x"7d3" => data <= x"20";
when "01" & x"7d4" => data <= x"4f";
when "01" & x"7d5" => data <= x"98";
when "01" & x"7d6" => data <= x"20";
when "01" & x"7d7" => data <= x"1e";
when "01" & x"7d8" => data <= x"98";
when "01" & x"7d9" => data <= x"20";
when "01" & x"7da" => data <= x"c3";
when "01" & x"7db" => data <= x"88";
when "01" & x"7dc" => data <= x"a9";
when "01" & x"7dd" => data <= x"01";
when "01" & x"7de" => data <= x"60";
when "01" & x"7df" => data <= x"20";
when "01" & x"7e0" => data <= x"e1";
when "01" & x"7e1" => data <= x"83";
when "01" & x"7e2" => data <= x"a0";
when "01" & x"7e3" => data <= x"02";
when "01" & x"7e4" => data <= x"b1";
when "01" & x"7e5" => data <= x"b0";
when "01" & x"7e6" => data <= x"9d";
when "01" & x"7e7" => data <= x"08";
when "01" & x"7e8" => data <= x"0f";
when "01" & x"7e9" => data <= x"c8";
when "01" & x"7ea" => data <= x"b1";
when "01" & x"7eb" => data <= x"b0";
when "01" & x"7ec" => data <= x"9d";
when "01" & x"7ed" => data <= x"09";
when "01" & x"7ee" => data <= x"0f";
when "01" & x"7ef" => data <= x"c8";
when "01" & x"7f0" => data <= x"b1";
when "01" & x"7f1" => data <= x"b0";
when "01" & x"7f2" => data <= x"0a";
when "01" & x"7f3" => data <= x"0a";
when "01" & x"7f4" => data <= x"5d";
when "01" & x"7f5" => data <= x"0e";
when "01" & x"7f6" => data <= x"0f";
when "01" & x"7f7" => data <= x"29";
when "01" & x"7f8" => data <= x"0c";
when "01" & x"7f9" => data <= x"10";
when "01" & x"7fa" => data <= x"1b";
when "01" & x"7fb" => data <= x"20";
when "01" & x"7fc" => data <= x"e1";
when "01" & x"7fd" => data <= x"83";
when "01" & x"7fe" => data <= x"a0";
when "01" & x"7ff" => data <= x"06";
when "01" & x"800" => data <= x"b1";
when "01" & x"801" => data <= x"b0";
when "01" & x"802" => data <= x"9d";
when "01" & x"803" => data <= x"0a";
when "01" & x"804" => data <= x"0f";
when "01" & x"805" => data <= x"c8";
when "01" & x"806" => data <= x"b1";
when "01" & x"807" => data <= x"b0";
when "01" & x"808" => data <= x"9d";
when "01" & x"809" => data <= x"0b";
when "01" & x"80a" => data <= x"0f";
when "01" & x"80b" => data <= x"c8";
when "01" & x"80c" => data <= x"b1";
when "01" & x"80d" => data <= x"b0";
when "01" & x"80e" => data <= x"6a";
when "01" & x"80f" => data <= x"6a";
when "01" & x"810" => data <= x"6a";
when "01" & x"811" => data <= x"5d";
when "01" & x"812" => data <= x"0e";
when "01" & x"813" => data <= x"0f";
when "01" & x"814" => data <= x"29";
when "01" & x"815" => data <= x"c0";
when "01" & x"816" => data <= x"5d";
when "01" & x"817" => data <= x"0e";
when "01" & x"818" => data <= x"0f";
when "01" & x"819" => data <= x"9d";
when "01" & x"81a" => data <= x"0e";
when "01" & x"81b" => data <= x"0f";
when "01" & x"81c" => data <= x"b8";
when "01" & x"81d" => data <= x"60";
when "01" & x"81e" => data <= x"20";
when "01" & x"81f" => data <= x"e1";
when "01" & x"820" => data <= x"83";
when "01" & x"821" => data <= x"a0";
when "01" & x"822" => data <= x"0e";
when "01" & x"823" => data <= x"b1";
when "01" & x"824" => data <= x"b0";
when "01" & x"825" => data <= x"29";
when "01" & x"826" => data <= x"0a";
when "01" & x"827" => data <= x"f0";
when "01" & x"828" => data <= x"02";
when "01" & x"829" => data <= x"a9";
when "01" & x"82a" => data <= x"80";
when "01" & x"82b" => data <= x"5d";
when "01" & x"82c" => data <= x"0f";
when "01" & x"82d" => data <= x"0e";
when "01" & x"82e" => data <= x"29";
when "01" & x"82f" => data <= x"80";
when "01" & x"830" => data <= x"5d";
when "01" & x"831" => data <= x"0f";
when "01" & x"832" => data <= x"0e";
when "01" & x"833" => data <= x"9d";
when "01" & x"834" => data <= x"0f";
when "01" & x"835" => data <= x"0e";
when "01" & x"836" => data <= x"60";
when "01" & x"837" => data <= x"20";
when "01" & x"838" => data <= x"64";
when "01" & x"839" => data <= x"98";
when "01" & x"83a" => data <= x"90";
when "01" & x"83b" => data <= x"23";
when "01" & x"83c" => data <= x"b9";
when "01" & x"83d" => data <= x"0f";
when "01" & x"83e" => data <= x"0e";
when "01" & x"83f" => data <= x"10";
when "01" & x"840" => data <= x"22";
when "01" & x"841" => data <= x"20";
when "01" & x"842" => data <= x"2b";
when "01" & x"843" => data <= x"80";
when "01" & x"844" => data <= x"c3";
when "01" & x"845" => data <= x"6c";
when "01" & x"846" => data <= x"6f";
when "01" & x"847" => data <= x"63";
when "01" & x"848" => data <= x"6b";
when "01" & x"849" => data <= x"65";
when "01" & x"84a" => data <= x"64";
when "01" & x"84b" => data <= x"00";
when "01" & x"84c" => data <= x"20";
when "01" & x"84d" => data <= x"3c";
when "01" & x"84e" => data <= x"98";
when "01" & x"84f" => data <= x"20";
when "01" & x"850" => data <= x"e1";
when "01" & x"851" => data <= x"83";
when "01" & x"852" => data <= x"20";
when "01" & x"853" => data <= x"9e";
when "01" & x"854" => data <= x"8f";
when "01" & x"855" => data <= x"90";
when "01" & x"856" => data <= x"21";
when "01" & x"857" => data <= x"4c";
when "01" & x"858" => data <= x"02";
when "01" & x"859" => data <= x"8f";
when "01" & x"85a" => data <= x"20";
when "01" & x"85b" => data <= x"64";
when "01" & x"85c" => data <= x"98";
when "01" & x"85d" => data <= x"b0";
when "01" & x"85e" => data <= x"19";
when "01" & x"85f" => data <= x"68";
when "01" & x"860" => data <= x"68";
when "01" & x"861" => data <= x"a9";
when "01" & x"862" => data <= x"00";
when "01" & x"863" => data <= x"60";
when "01" & x"864" => data <= x"20";
when "01" & x"865" => data <= x"06";
when "01" & x"866" => data <= x"81";
when "01" & x"867" => data <= x"20";
when "01" & x"868" => data <= x"96";
when "01" & x"869" => data <= x"82";
when "01" & x"86a" => data <= x"90";
when "01" & x"86b" => data <= x"0c";
when "01" & x"86c" => data <= x"98";
when "01" & x"86d" => data <= x"aa";
when "01" & x"86e" => data <= x"ad";
when "01" & x"86f" => data <= x"dc";
when "01" & x"870" => data <= x"10";
when "01" & x"871" => data <= x"85";
when "01" & x"872" => data <= x"b0";
when "01" & x"873" => data <= x"ad";
when "01" & x"874" => data <= x"dd";
when "01" & x"875" => data <= x"10";
when "01" & x"876" => data <= x"85";
when "01" & x"877" => data <= x"b1";
when "01" & x"878" => data <= x"60";
when "01" & x"879" => data <= x"a9";
when "01" & x"87a" => data <= x"83";
when "01" & x"87b" => data <= x"20";
when "01" & x"87c" => data <= x"f4";
when "01" & x"87d" => data <= x"ff";
when "01" & x"87e" => data <= x"8c";
when "01" & x"87f" => data <= x"d0";
when "01" & x"880" => data <= x"10";
when "01" & x"881" => data <= x"a9";
when "01" & x"882" => data <= x"84";
when "01" & x"883" => data <= x"20";
when "01" & x"884" => data <= x"f4";
when "01" & x"885" => data <= x"ff";
when "01" & x"886" => data <= x"98";
when "01" & x"887" => data <= x"38";
when "01" & x"888" => data <= x"ed";
when "01" & x"889" => data <= x"d0";
when "01" & x"88a" => data <= x"10";
when "01" & x"88b" => data <= x"8d";
when "01" & x"88c" => data <= x"d1";
when "01" & x"88d" => data <= x"10";
when "01" & x"88e" => data <= x"60";
when "01" & x"88f" => data <= x"a2";
when "01" & x"890" => data <= x"0a";
when "01" & x"891" => data <= x"20";
when "01" & x"892" => data <= x"2c";
when "01" & x"893" => data <= x"99";
when "01" & x"894" => data <= x"20";
when "01" & x"895" => data <= x"9e";
when "01" & x"896" => data <= x"98";
when "01" & x"897" => data <= x"a0";
when "01" & x"898" => data <= x"d5";
when "01" & x"899" => data <= x"a9";
when "01" & x"89a" => data <= x"ff";
when "01" & x"89b" => data <= x"91";
when "01" & x"89c" => data <= x"b0";
when "01" & x"89d" => data <= x"60";
when "01" & x"89e" => data <= x"48";
when "01" & x"89f" => data <= x"a6";
when "01" & x"8a0" => data <= x"f4";
when "01" & x"8a1" => data <= x"a9";
when "01" & x"8a2" => data <= x"00";
when "01" & x"8a3" => data <= x"85";
when "01" & x"8a4" => data <= x"b0";
when "01" & x"8a5" => data <= x"bd";
when "01" & x"8a6" => data <= x"f0";
when "01" & x"8a7" => data <= x"0d";
when "01" & x"8a8" => data <= x"85";
when "01" & x"8a9" => data <= x"b1";
when "01" & x"8aa" => data <= x"68";
when "01" & x"8ab" => data <= x"60";
when "01" & x"8ac" => data <= x"00";
when "01" & x"8ad" => data <= x"00";
when "01" & x"8ae" => data <= x"00";
when "01" & x"8af" => data <= x"00";
when "01" & x"8b0" => data <= x"00";
when "01" & x"8b1" => data <= x"00";
when "01" & x"8b2" => data <= x"00";
when "01" & x"8b3" => data <= x"00";
when "01" & x"8b4" => data <= x"00";
when "01" & x"8b5" => data <= x"00";
when "01" & x"8b6" => data <= x"00";
when "01" & x"8b7" => data <= x"00";
when "01" & x"8b8" => data <= x"00";
when "01" & x"8b9" => data <= x"00";
when "01" & x"8ba" => data <= x"00";
when "01" & x"8bb" => data <= x"00";
when "01" & x"8bc" => data <= x"00";
when "01" & x"8bd" => data <= x"00";
when "01" & x"8be" => data <= x"00";
when "01" & x"8bf" => data <= x"00";
when "01" & x"8c0" => data <= x"00";
when "01" & x"8c1" => data <= x"00";
when "01" & x"8c2" => data <= x"00";
when "01" & x"8c3" => data <= x"00";
when "01" & x"8c4" => data <= x"00";
when "01" & x"8c5" => data <= x"00";
when "01" & x"8c6" => data <= x"00";
when "01" & x"8c7" => data <= x"00";
when "01" & x"8c8" => data <= x"00";
when "01" & x"8c9" => data <= x"00";
when "01" & x"8ca" => data <= x"00";
when "01" & x"8cb" => data <= x"00";
when "01" & x"8cc" => data <= x"00";
when "01" & x"8cd" => data <= x"00";
when "01" & x"8ce" => data <= x"00";
when "01" & x"8cf" => data <= x"00";
when "01" & x"8d0" => data <= x"00";
when "01" & x"8d1" => data <= x"00";
when "01" & x"8d2" => data <= x"00";
when "01" & x"8d3" => data <= x"00";
when "01" & x"8d4" => data <= x"00";
when "01" & x"8d5" => data <= x"00";
when "01" & x"8d6" => data <= x"00";
when "01" & x"8d7" => data <= x"00";
when "01" & x"8d8" => data <= x"00";
when "01" & x"8d9" => data <= x"00";
when "01" & x"8da" => data <= x"00";
when "01" & x"8db" => data <= x"00";
when "01" & x"8dc" => data <= x"00";
when "01" & x"8dd" => data <= x"00";
when "01" & x"8de" => data <= x"00";
when "01" & x"8df" => data <= x"00";
when "01" & x"8e0" => data <= x"00";
when "01" & x"8e1" => data <= x"00";
when "01" & x"8e2" => data <= x"00";
when "01" & x"8e3" => data <= x"00";
when "01" & x"8e4" => data <= x"00";
when "01" & x"8e5" => data <= x"00";
when "01" & x"8e6" => data <= x"00";
when "01" & x"8e7" => data <= x"00";
when "01" & x"8e8" => data <= x"00";
when "01" & x"8e9" => data <= x"00";
when "01" & x"8ea" => data <= x"00";
when "01" & x"8eb" => data <= x"00";
when "01" & x"8ec" => data <= x"00";
when "01" & x"8ed" => data <= x"00";
when "01" & x"8ee" => data <= x"00";
when "01" & x"8ef" => data <= x"00";
when "01" & x"8f0" => data <= x"00";
when "01" & x"8f1" => data <= x"00";
when "01" & x"8f2" => data <= x"00";
when "01" & x"8f3" => data <= x"00";
when "01" & x"8f4" => data <= x"00";
when "01" & x"8f5" => data <= x"00";
when "01" & x"8f6" => data <= x"00";
when "01" & x"8f7" => data <= x"00";
when "01" & x"8f8" => data <= x"00";
when "01" & x"8f9" => data <= x"00";
when "01" & x"8fa" => data <= x"00";
when "01" & x"8fb" => data <= x"00";
when "01" & x"8fc" => data <= x"00";
when "01" & x"8fd" => data <= x"00";
when "01" & x"8fe" => data <= x"00";
when "01" & x"8ff" => data <= x"00";
when "01" & x"900" => data <= x"00";
when "01" & x"901" => data <= x"00";
when "01" & x"902" => data <= x"00";
when "01" & x"903" => data <= x"00";
when "01" & x"904" => data <= x"00";
when "01" & x"905" => data <= x"60";
when "01" & x"906" => data <= x"20";
when "01" & x"907" => data <= x"e1";
when "01" & x"908" => data <= x"83";
when "01" & x"909" => data <= x"a9";
when "01" & x"90a" => data <= x"0f";
when "01" & x"90b" => data <= x"a2";
when "01" & x"90c" => data <= x"01";
when "01" & x"90d" => data <= x"a0";
when "01" & x"90e" => data <= x"00";
when "01" & x"90f" => data <= x"f0";
when "01" & x"910" => data <= x"25";
when "01" & x"911" => data <= x"a9";
when "01" & x"912" => data <= x"c7";
when "01" & x"913" => data <= x"a2";
when "01" & x"914" => data <= x"00";
when "01" & x"915" => data <= x"f0";
when "01" & x"916" => data <= x"f6";
when "01" & x"917" => data <= x"aa";
when "01" & x"918" => data <= x"a9";
when "01" & x"919" => data <= x"03";
when "01" & x"91a" => data <= x"d0";
when "01" & x"91b" => data <= x"1a";
when "01" & x"91c" => data <= x"a9";
when "01" & x"91d" => data <= x"ec";
when "01" & x"91e" => data <= x"d0";
when "01" & x"91f" => data <= x"12";
when "01" & x"920" => data <= x"a9";
when "01" & x"921" => data <= x"c7";
when "01" & x"922" => data <= x"d0";
when "01" & x"923" => data <= x"0e";
when "01" & x"924" => data <= x"a9";
when "01" & x"925" => data <= x"ea";
when "01" & x"926" => data <= x"d0";
when "01" & x"927" => data <= x"0a";
when "01" & x"928" => data <= x"a9";
when "01" & x"929" => data <= x"a8";
when "01" & x"92a" => data <= x"d0";
when "01" & x"92b" => data <= x"06";
when "01" & x"92c" => data <= x"a9";
when "01" & x"92d" => data <= x"8f";
when "01" & x"92e" => data <= x"d0";
when "01" & x"92f" => data <= x"06";
when "01" & x"930" => data <= x"a9";
when "01" & x"931" => data <= x"ff";
when "01" & x"932" => data <= x"a2";
when "01" & x"933" => data <= x"00";
when "01" & x"934" => data <= x"a0";
when "01" & x"935" => data <= x"ff";
when "01" & x"936" => data <= x"4c";
when "01" & x"937" => data <= x"f4";
when "01" & x"938" => data <= x"ff";
when "01" & x"939" => data <= x"4c";
when "01" & x"93a" => data <= x"2e";
when "01" & x"93b" => data <= x"21";
when "01" & x"93c" => data <= x"42";
when "01" & x"93d" => data <= x"4f";
when "01" & x"93e" => data <= x"4f";
when "01" & x"93f" => data <= x"54";
when "01" & x"940" => data <= x"0d";
when "01" & x"941" => data <= x"45";
when "01" & x"942" => data <= x"2e";
when "01" & x"943" => data <= x"21";
when "01" & x"944" => data <= x"42";
when "01" & x"945" => data <= x"4f";
when "01" & x"946" => data <= x"4f";
when "01" & x"947" => data <= x"54";
when "01" & x"948" => data <= x"0d";
when "01" & x"949" => data <= x"1b";
when "01" & x"94a" => data <= x"ff";
when "01" & x"94b" => data <= x"1e";
when "01" & x"94c" => data <= x"ff";
when "01" & x"94d" => data <= x"21";
when "01" & x"94e" => data <= x"ff";
when "01" & x"94f" => data <= x"24";
when "01" & x"950" => data <= x"ff";
when "01" & x"951" => data <= x"27";
when "01" & x"952" => data <= x"ff";
when "01" & x"953" => data <= x"2a";
when "01" & x"954" => data <= x"ff";
when "01" & x"955" => data <= x"2d";
when "01" & x"956" => data <= x"ff";
when "01" & x"957" => data <= x"7b";
when "01" & x"958" => data <= x"95";
when "01" & x"959" => data <= x"00";
when "01" & x"95a" => data <= x"07";
when "01" & x"95b" => data <= x"90";
when "01" & x"95c" => data <= x"00";
when "01" & x"95d" => data <= x"c1";
when "01" & x"95e" => data <= x"90";
when "01" & x"95f" => data <= x"00";
when "01" & x"960" => data <= x"aa";
when "01" & x"961" => data <= x"91";
when "01" & x"962" => data <= x"00";
when "01" & x"963" => data <= x"d0";
when "01" & x"964" => data <= x"95";
when "01" & x"965" => data <= x"00";
when "01" & x"966" => data <= x"93";
when "01" & x"967" => data <= x"8e";
when "01" & x"968" => data <= x"00";
when "01" & x"969" => data <= x"aa";
when "01" & x"96a" => data <= x"95";
when "01" & x"96b" => data <= x"00";
when "01" & x"96c" => data <= x"1b";
when "01" & x"96d" => data <= x"8c";
when "01" & x"96e" => data <= x"d3";
when "01" & x"96f" => data <= x"6b";
when "01" & x"970" => data <= x"d3";
when "01" & x"971" => data <= x"1d";
when "01" & x"972" => data <= x"e1";
when "01" & x"973" => data <= x"dc";
when "01" & x"974" => data <= x"97";
when "01" & x"975" => data <= x"89";
when "01" & x"976" => data <= x"90";
when "01" & x"977" => data <= x"87";
when "01" & x"978" => data <= x"86";
when "01" & x"979" => data <= x"87";
when "01" & x"97a" => data <= x"84";
when "01" & x"97b" => data <= x"8d";
when "01" & x"97c" => data <= x"8d";
when "01" & x"97d" => data <= x"97";
when "01" & x"97e" => data <= x"f1";
when "01" & x"97f" => data <= x"3c";
when "01" & x"980" => data <= x"bc";
when "01" & x"981" => data <= x"8f";
when "01" & x"982" => data <= x"9b";
when "01" & x"983" => data <= x"95";
when "01" & x"984" => data <= x"93";
when "01" & x"985" => data <= x"85";
when "01" & x"986" => data <= x"b4";
when "01" & x"987" => data <= x"bf";
when "01" & x"988" => data <= x"c7";
when "01" & x"989" => data <= x"cf";
when "01" & x"98a" => data <= x"a0";
when "01" & x"98b" => data <= x"a9";
when "01" & x"98c" => data <= x"87";
when "01" & x"98d" => data <= x"87";
when "01" & x"98e" => data <= x"97";
when "01" & x"98f" => data <= x"97";
when "01" & x"990" => data <= x"97";
when "01" & x"991" => data <= x"97";
when "01" & x"992" => data <= x"97";
when "01" & x"993" => data <= x"97";
when "01" & x"994" => data <= x"12";
when "01" & x"995" => data <= x"32";
when "01" & x"996" => data <= x"5d";
when "01" & x"997" => data <= x"cd";
when "01" & x"998" => data <= x"a2";
when "01" & x"999" => data <= x"bd";
when "01" & x"99a" => data <= x"87";
when "01" & x"99b" => data <= x"8d";
when "01" & x"99c" => data <= x"8d";
when "01" & x"99d" => data <= x"8d";
when "01" & x"99e" => data <= x"8d";
when "01" & x"99f" => data <= x"8d";
when "01" & x"9a0" => data <= x"8d";
when "01" & x"9a1" => data <= x"8d";
when "01" & x"9a2" => data <= x"74";
when "01" & x"9a3" => data <= x"54";
when "01" & x"9a4" => data <= x"00";
when "01" & x"9a5" => data <= x"0f";
when "01" & x"9a6" => data <= x"1a";
when "01" & x"9a7" => data <= x"0f";
when "01" & x"9a8" => data <= x"1a";
when "01" & x"9a9" => data <= x"63";
when "01" & x"9aa" => data <= x"43";
when "01" & x"9ab" => data <= x"b7";
when "01" & x"9ac" => data <= x"7d";
when "01" & x"9ad" => data <= x"7d";
when "01" & x"9ae" => data <= x"65";
when "01" & x"9af" => data <= x"65";
when "01" & x"9b0" => data <= x"cf";
when "01" & x"9b1" => data <= x"00";
when "01" & x"9b2" => data <= x"14";
when "01" & x"9b3" => data <= x"83";
when "01" & x"9b4" => data <= x"85";
when "01" & x"9b5" => data <= x"97";
when "01" & x"9b6" => data <= x"97";
when "01" & x"9b7" => data <= x"97";
when "01" & x"9b8" => data <= x"97";
when "01" & x"9b9" => data <= x"96";
when "01" & x"9ba" => data <= x"97";
when "01" & x"9bb" => data <= x"97";
when "01" & x"9bc" => data <= x"96";
when "01" & x"9bd" => data <= x"04";
when "01" & x"9be" => data <= x"02";
when "01" & x"9bf" => data <= x"03";
when "01" & x"9c0" => data <= x"06";
when "01" & x"9c1" => data <= x"07";
when "01" & x"9c2" => data <= x"04";
when "01" & x"9c3" => data <= x"04";
when "01" & x"9c4" => data <= x"04";
when "01" & x"9c5" => data <= x"04";
when "01" & x"9c6" => data <= x"98";
when "01" & x"9c7" => data <= x"a2";
when "01" & x"9c8" => data <= x"ff";
when "01" & x"9c9" => data <= x"a0";
when "01" & x"9ca" => data <= x"0e";
when "01" & x"9cb" => data <= x"48";
when "01" & x"9cc" => data <= x"20";
when "01" & x"9cd" => data <= x"65";
when "01" & x"9ce" => data <= x"80";
when "01" & x"9cf" => data <= x"0d";
when "01" & x"9d0" => data <= x"44";
when "01" & x"9d1" => data <= x"46";
when "01" & x"9d2" => data <= x"53";
when "01" & x"9d3" => data <= x"20";
when "01" & x"9d4" => data <= x"30";
when "01" & x"9d5" => data <= x"2e";
when "01" & x"9d6" => data <= x"39";
when "01" & x"9d7" => data <= x"30";
when "01" & x"9d8" => data <= x"0d";
when "01" & x"9d9" => data <= x"86";
when "01" & x"9da" => data <= x"b8";
when "01" & x"9db" => data <= x"20";
when "01" & x"9dc" => data <= x"cb";
when "01" & x"9dd" => data <= x"9f";
when "01" & x"9de" => data <= x"20";
when "01" & x"9df" => data <= x"19";
when "01" & x"9e0" => data <= x"9a";
when "01" & x"9e1" => data <= x"20";
when "01" & x"9e2" => data <= x"9a";
when "01" & x"9e3" => data <= x"9f";
when "01" & x"9e4" => data <= x"88";
when "01" & x"9e5" => data <= x"d0";
when "01" & x"9e6" => data <= x"f4";
when "01" & x"9e7" => data <= x"68";
when "01" & x"9e8" => data <= x"a8";
when "01" & x"9e9" => data <= x"a2";
when "01" & x"9ea" => data <= x"a0";
when "01" & x"9eb" => data <= x"4c";
when "01" & x"9ec" => data <= x"71";
when "01" & x"9ed" => data <= x"86";
when "01" & x"9ee" => data <= x"98";
when "01" & x"9ef" => data <= x"a2";
when "01" & x"9f0" => data <= x"74";
when "01" & x"9f1" => data <= x"a0";
when "01" & x"9f2" => data <= x"05";
when "01" & x"9f3" => data <= x"d0";
when "01" & x"9f4" => data <= x"d6";
when "01" & x"9f5" => data <= x"20";
when "01" & x"9f6" => data <= x"bf";
when "01" & x"9f7" => data <= x"86";
when "01" & x"9f8" => data <= x"f0";
when "01" & x"9f9" => data <= x"60";
when "01" & x"9fa" => data <= x"20";
when "01" & x"9fb" => data <= x"c5";
when "01" & x"9fc" => data <= x"ff";
when "01" & x"9fd" => data <= x"90";
when "01" & x"9fe" => data <= x"fb";
when "01" & x"9ff" => data <= x"b0";
when "01" & x"a00" => data <= x"e8";
when "01" & x"a01" => data <= x"20";
when "01" & x"a02" => data <= x"bf";
when "01" & x"a03" => data <= x"86";
when "01" & x"a04" => data <= x"d0";
when "01" & x"a05" => data <= x"54";
when "01" & x"a06" => data <= x"20";
when "01" & x"a07" => data <= x"33";
when "01" & x"a08" => data <= x"80";
when "01" & x"a09" => data <= x"dc";
when "01" & x"a0a" => data <= x"53";
when "01" & x"a0b" => data <= x"79";
when "01" & x"a0c" => data <= x"6e";
when "01" & x"a0d" => data <= x"74";
when "01" & x"a0e" => data <= x"61";
when "01" & x"a0f" => data <= x"78";
when "01" & x"a10" => data <= x"3a";
when "01" & x"a11" => data <= x"20";
when "01" & x"a12" => data <= x"ea";
when "01" & x"a13" => data <= x"20";
when "01" & x"a14" => data <= x"19";
when "01" & x"a15" => data <= x"9a";
when "01" & x"a16" => data <= x"4c";
when "01" & x"a17" => data <= x"8a";
when "01" & x"a18" => data <= x"80";
when "01" & x"a19" => data <= x"a6";
when "01" & x"a1a" => data <= x"b8";
when "01" & x"a1b" => data <= x"e8";
when "01" & x"a1c" => data <= x"bd";
when "01" & x"a1d" => data <= x"b8";
when "01" & x"a1e" => data <= x"85";
when "01" & x"a1f" => data <= x"30";
when "01" & x"a20" => data <= x"06";
when "01" & x"a21" => data <= x"20";
when "01" & x"a22" => data <= x"9c";
when "01" & x"a23" => data <= x"80";
when "01" & x"a24" => data <= x"4c";
when "01" & x"a25" => data <= x"1b";
when "01" & x"a26" => data <= x"9a";
when "01" & x"a27" => data <= x"e8";
when "01" & x"a28" => data <= x"e8";
when "01" & x"a29" => data <= x"86";
when "01" & x"a2a" => data <= x"b8";
when "01" & x"a2b" => data <= x"bd";
when "01" & x"a2c" => data <= x"b8";
when "01" & x"a2d" => data <= x"85";
when "01" & x"a2e" => data <= x"20";
when "01" & x"a2f" => data <= x"34";
when "01" & x"a30" => data <= x"9a";
when "01" & x"a31" => data <= x"20";
when "01" & x"a32" => data <= x"05";
when "01" & x"a33" => data <= x"82";
when "01" & x"a34" => data <= x"20";
when "01" & x"a35" => data <= x"e1";
when "01" & x"a36" => data <= x"83";
when "01" & x"a37" => data <= x"29";
when "01" & x"a38" => data <= x"0f";
when "01" & x"a39" => data <= x"f0";
when "01" & x"a3a" => data <= x"1f";
when "01" & x"a3b" => data <= x"a8";
when "01" & x"a3c" => data <= x"a9";
when "01" & x"a3d" => data <= x"20";
when "01" & x"a3e" => data <= x"20";
when "01" & x"a3f" => data <= x"9c";
when "01" & x"a40" => data <= x"80";
when "01" & x"a41" => data <= x"a2";
when "01" & x"a42" => data <= x"00";
when "01" & x"a43" => data <= x"bd";
when "01" & x"a44" => data <= x"5b";
when "01" & x"a45" => data <= x"9a";
when "01" & x"a46" => data <= x"f0";
when "01" & x"a47" => data <= x"03";
when "01" & x"a48" => data <= x"e8";
when "01" & x"a49" => data <= x"d0";
when "01" & x"a4a" => data <= x"f8";
when "01" & x"a4b" => data <= x"88";
when "01" & x"a4c" => data <= x"d0";
when "01" & x"a4d" => data <= x"fa";
when "01" & x"a4e" => data <= x"e8";
when "01" & x"a4f" => data <= x"bd";
when "01" & x"a50" => data <= x"5b";
when "01" & x"a51" => data <= x"9a";
when "01" & x"a52" => data <= x"f0";
when "01" & x"a53" => data <= x"06";
when "01" & x"a54" => data <= x"20";
when "01" & x"a55" => data <= x"9c";
when "01" & x"a56" => data <= x"80";
when "01" & x"a57" => data <= x"4c";
when "01" & x"a58" => data <= x"4e";
when "01" & x"a59" => data <= x"9a";
when "01" & x"a5a" => data <= x"60";
when "01" & x"a5b" => data <= x"00";
when "01" & x"a5c" => data <= x"3c";
when "01" & x"a5d" => data <= x"66";
when "01" & x"a5e" => data <= x"73";
when "01" & x"a5f" => data <= x"70";
when "01" & x"a60" => data <= x"3e";
when "01" & x"a61" => data <= x"00";
when "01" & x"a62" => data <= x"3c";
when "01" & x"a63" => data <= x"61";
when "01" & x"a64" => data <= x"66";
when "01" & x"a65" => data <= x"73";
when "01" & x"a66" => data <= x"70";
when "01" & x"a67" => data <= x"3e";
when "01" & x"a68" => data <= x"00";
when "01" & x"a69" => data <= x"28";
when "01" & x"a6a" => data <= x"4c";
when "01" & x"a6b" => data <= x"29";
when "01" & x"a6c" => data <= x"00";
when "01" & x"a6d" => data <= x"3c";
when "01" & x"a6e" => data <= x"73";
when "01" & x"a6f" => data <= x"72";
when "01" & x"a70" => data <= x"63";
when "01" & x"a71" => data <= x"20";
when "01" & x"a72" => data <= x"64";
when "01" & x"a73" => data <= x"72";
when "01" & x"a74" => data <= x"76";
when "01" & x"a75" => data <= x"3e";
when "01" & x"a76" => data <= x"00";
when "01" & x"a77" => data <= x"3c";
when "01" & x"a78" => data <= x"64";
when "01" & x"a79" => data <= x"65";
when "01" & x"a7a" => data <= x"73";
when "01" & x"a7b" => data <= x"74";
when "01" & x"a7c" => data <= x"20";
when "01" & x"a7d" => data <= x"64";
when "01" & x"a7e" => data <= x"72";
when "01" & x"a7f" => data <= x"76";
when "01" & x"a80" => data <= x"3e";
when "01" & x"a81" => data <= x"00";
when "01" & x"a82" => data <= x"3c";
when "01" & x"a83" => data <= x"64";
when "01" & x"a84" => data <= x"65";
when "01" & x"a85" => data <= x"73";
when "01" & x"a86" => data <= x"74";
when "01" & x"a87" => data <= x"20";
when "01" & x"a88" => data <= x"64";
when "01" & x"a89" => data <= x"72";
when "01" & x"a8a" => data <= x"76";
when "01" & x"a8b" => data <= x"3e";
when "01" & x"a8c" => data <= x"20";
when "01" & x"a8d" => data <= x"3c";
when "01" & x"a8e" => data <= x"61";
when "01" & x"a8f" => data <= x"66";
when "01" & x"a90" => data <= x"73";
when "01" & x"a91" => data <= x"70";
when "01" & x"a92" => data <= x"3e";
when "01" & x"a93" => data <= x"00";
when "01" & x"a94" => data <= x"3c";
when "01" & x"a95" => data <= x"6f";
when "01" & x"a96" => data <= x"6c";
when "01" & x"a97" => data <= x"64";
when "01" & x"a98" => data <= x"20";
when "01" & x"a99" => data <= x"66";
when "01" & x"a9a" => data <= x"73";
when "01" & x"a9b" => data <= x"70";
when "01" & x"a9c" => data <= x"3e";
when "01" & x"a9d" => data <= x"00";
when "01" & x"a9e" => data <= x"3c";
when "01" & x"a9f" => data <= x"6e";
when "01" & x"aa0" => data <= x"65";
when "01" & x"aa1" => data <= x"77";
when "01" & x"aa2" => data <= x"20";
when "01" & x"aa3" => data <= x"66";
when "01" & x"aa4" => data <= x"73";
when "01" & x"aa5" => data <= x"70";
when "01" & x"aa6" => data <= x"3e";
when "01" & x"aa7" => data <= x"00";
when "01" & x"aa8" => data <= x"28";
when "01" & x"aa9" => data <= x"3c";
when "01" & x"aaa" => data <= x"64";
when "01" & x"aab" => data <= x"69";
when "01" & x"aac" => data <= x"72";
when "01" & x"aad" => data <= x"3e";
when "01" & x"aae" => data <= x"29";
when "01" & x"aaf" => data <= x"00";
when "01" & x"ab0" => data <= x"28";
when "01" & x"ab1" => data <= x"3c";
when "01" & x"ab2" => data <= x"64";
when "01" & x"ab3" => data <= x"72";
when "01" & x"ab4" => data <= x"76";
when "01" & x"ab5" => data <= x"3e";
when "01" & x"ab6" => data <= x"29";
when "01" & x"ab7" => data <= x"00";
when "01" & x"ab8" => data <= x"3c";
when "01" & x"ab9" => data <= x"74";
when "01" & x"aba" => data <= x"69";
when "01" & x"abb" => data <= x"74";
when "01" & x"abc" => data <= x"6c";
when "01" & x"abd" => data <= x"65";
when "01" & x"abe" => data <= x"3e";
when "01" & x"abf" => data <= x"00";
when "01" & x"ac0" => data <= x"20";
when "01" & x"ac1" => data <= x"58";
when "01" & x"ac2" => data <= x"83";
when "01" & x"ac3" => data <= x"20";
when "01" & x"ac4" => data <= x"65";
when "01" & x"ac5" => data <= x"80";
when "01" & x"ac6" => data <= x"43";
when "01" & x"ac7" => data <= x"6f";
when "01" & x"ac8" => data <= x"6d";
when "01" & x"ac9" => data <= x"70";
when "01" & x"aca" => data <= x"61";
when "01" & x"acb" => data <= x"63";
when "01" & x"acc" => data <= x"74";
when "01" & x"acd" => data <= x"69";
when "01" & x"ace" => data <= x"6e";
when "01" & x"acf" => data <= x"67";
when "01" & x"ad0" => data <= x"20";
when "01" & x"ad1" => data <= x"64";
when "01" & x"ad2" => data <= x"72";
when "01" & x"ad3" => data <= x"69";
when "01" & x"ad4" => data <= x"76";
when "01" & x"ad5" => data <= x"65";
when "01" & x"ad6" => data <= x"20";
when "01" & x"ad7" => data <= x"8d";
when "01" & x"ad8" => data <= x"d2";
when "01" & x"ad9" => data <= x"10";
when "01" & x"ada" => data <= x"8d";
when "01" & x"adb" => data <= x"d3";
when "01" & x"adc" => data <= x"10";
when "01" & x"add" => data <= x"20";
when "01" & x"ade" => data <= x"ca";
when "01" & x"adf" => data <= x"80";
when "01" & x"ae0" => data <= x"20";
when "01" & x"ae1" => data <= x"9a";
when "01" & x"ae2" => data <= x"9f";
when "01" & x"ae3" => data <= x"a0";
when "01" & x"ae4" => data <= x"00";
when "01" & x"ae5" => data <= x"20";
when "01" & x"ae6" => data <= x"05";
when "01" & x"ae7" => data <= x"8e";
when "01" & x"ae8" => data <= x"20";
when "01" & x"ae9" => data <= x"79";
when "01" & x"aea" => data <= x"98";
when "01" & x"aeb" => data <= x"20";
when "01" & x"aec" => data <= x"47";
when "01" & x"aed" => data <= x"83";
when "01" & x"aee" => data <= x"ac";
when "01" & x"aef" => data <= x"05";
when "01" & x"af0" => data <= x"0f";
when "01" & x"af1" => data <= x"84";
when "01" & x"af2" => data <= x"cc";
when "01" & x"af3" => data <= x"a9";
when "01" & x"af4" => data <= x"02";
when "01" & x"af5" => data <= x"85";
when "01" & x"af6" => data <= x"ca";
when "01" & x"af7" => data <= x"a9";
when "01" & x"af8" => data <= x"00";
when "01" & x"af9" => data <= x"85";
when "01" & x"afa" => data <= x"cb";
when "01" & x"afb" => data <= x"a4";
when "01" & x"afc" => data <= x"cc";
when "01" & x"afd" => data <= x"20";
when "01" & x"afe" => data <= x"19";
when "01" & x"aff" => data <= x"82";
when "01" & x"b00" => data <= x"c0";
when "01" & x"b01" => data <= x"f8";
when "01" & x"b02" => data <= x"d0";
when "01" & x"b03" => data <= x"3c";
when "01" & x"b04" => data <= x"20";
when "01" & x"b05" => data <= x"65";
when "01" & x"b06" => data <= x"80";
when "01" & x"b07" => data <= x"44";
when "01" & x"b08" => data <= x"69";
when "01" & x"b09" => data <= x"73";
when "01" & x"b0a" => data <= x"6b";
when "01" & x"b0b" => data <= x"20";
when "01" & x"b0c" => data <= x"63";
when "01" & x"b0d" => data <= x"6f";
when "01" & x"b0e" => data <= x"6d";
when "01" & x"b0f" => data <= x"70";
when "01" & x"b10" => data <= x"61";
when "01" & x"b11" => data <= x"63";
when "01" & x"b12" => data <= x"74";
when "01" & x"b13" => data <= x"65";
when "01" & x"b14" => data <= x"64";
when "01" & x"b15" => data <= x"20";
when "01" & x"b16" => data <= x"ea";
when "01" & x"b17" => data <= x"38";
when "01" & x"b18" => data <= x"ad";
when "01" & x"b19" => data <= x"07";
when "01" & x"b1a" => data <= x"0f";
when "01" & x"b1b" => data <= x"e5";
when "01" & x"b1c" => data <= x"ca";
when "01" & x"b1d" => data <= x"48";
when "01" & x"b1e" => data <= x"ad";
when "01" & x"b1f" => data <= x"06";
when "01" & x"b20" => data <= x"0f";
when "01" & x"b21" => data <= x"29";
when "01" & x"b22" => data <= x"03";
when "01" & x"b23" => data <= x"e5";
when "01" & x"b24" => data <= x"cb";
when "01" & x"b25" => data <= x"20";
when "01" & x"b26" => data <= x"ca";
when "01" & x"b27" => data <= x"80";
when "01" & x"b28" => data <= x"68";
when "01" & x"b29" => data <= x"20";
when "01" & x"b2a" => data <= x"c2";
when "01" & x"b2b" => data <= x"80";
when "01" & x"b2c" => data <= x"20";
when "01" & x"b2d" => data <= x"65";
when "01" & x"b2e" => data <= x"80";
when "01" & x"b2f" => data <= x"20";
when "01" & x"b30" => data <= x"66";
when "01" & x"b31" => data <= x"72";
when "01" & x"b32" => data <= x"65";
when "01" & x"b33" => data <= x"65";
when "01" & x"b34" => data <= x"20";
when "01" & x"b35" => data <= x"73";
when "01" & x"b36" => data <= x"65";
when "01" & x"b37" => data <= x"63";
when "01" & x"b38" => data <= x"74";
when "01" & x"b39" => data <= x"6f";
when "01" & x"b3a" => data <= x"72";
when "01" & x"b3b" => data <= x"73";
when "01" & x"b3c" => data <= x"0d";
when "01" & x"b3d" => data <= x"a9";
when "01" & x"b3e" => data <= x"04";
when "01" & x"b3f" => data <= x"60";
when "01" & x"b40" => data <= x"84";
when "01" & x"b41" => data <= x"cc";
when "01" & x"b42" => data <= x"20";
when "01" & x"b43" => data <= x"fc";
when "01" & x"b44" => data <= x"82";
when "01" & x"b45" => data <= x"a4";
when "01" & x"b46" => data <= x"cc";
when "01" & x"b47" => data <= x"b9";
when "01" & x"b48" => data <= x"0e";
when "01" & x"b49" => data <= x"0f";
when "01" & x"b4a" => data <= x"29";
when "01" & x"b4b" => data <= x"30";
when "01" & x"b4c" => data <= x"19";
when "01" & x"b4d" => data <= x"0d";
when "01" & x"b4e" => data <= x"0f";
when "01" & x"b4f" => data <= x"19";
when "01" & x"b50" => data <= x"0c";
when "01" & x"b51" => data <= x"0f";
when "01" & x"b52" => data <= x"f0";
when "01" & x"b53" => data <= x"61";
when "01" & x"b54" => data <= x"a9";
when "01" & x"b55" => data <= x"00";
when "01" & x"b56" => data <= x"85";
when "01" & x"b57" => data <= x"be";
when "01" & x"b58" => data <= x"85";
when "01" & x"b59" => data <= x"c2";
when "01" & x"b5a" => data <= x"a9";
when "01" & x"b5b" => data <= x"ff";
when "01" & x"b5c" => data <= x"18";
when "01" & x"b5d" => data <= x"79";
when "01" & x"b5e" => data <= x"0c";
when "01" & x"b5f" => data <= x"0f";
when "01" & x"b60" => data <= x"a9";
when "01" & x"b61" => data <= x"00";
when "01" & x"b62" => data <= x"79";
when "01" & x"b63" => data <= x"0d";
when "01" & x"b64" => data <= x"0f";
when "01" & x"b65" => data <= x"85";
when "01" & x"b66" => data <= x"c6";
when "01" & x"b67" => data <= x"b9";
when "01" & x"b68" => data <= x"0e";
when "01" & x"b69" => data <= x"0f";
when "01" & x"b6a" => data <= x"08";
when "01" & x"b6b" => data <= x"20";
when "01" & x"b6c" => data <= x"fd";
when "01" & x"b6d" => data <= x"81";
when "01" & x"b6e" => data <= x"28";
when "01" & x"b6f" => data <= x"69";
when "01" & x"b70" => data <= x"00";
when "01" & x"b71" => data <= x"85";
when "01" & x"b72" => data <= x"c7";
when "01" & x"b73" => data <= x"b9";
when "01" & x"b74" => data <= x"0f";
when "01" & x"b75" => data <= x"0f";
when "01" & x"b76" => data <= x"85";
when "01" & x"b77" => data <= x"c8";
when "01" & x"b78" => data <= x"b9";
when "01" & x"b79" => data <= x"0e";
when "01" & x"b7a" => data <= x"0f";
when "01" & x"b7b" => data <= x"29";
when "01" & x"b7c" => data <= x"03";
when "01" & x"b7d" => data <= x"85";
when "01" & x"b7e" => data <= x"c9";
when "01" & x"b7f" => data <= x"c5";
when "01" & x"b80" => data <= x"cb";
when "01" & x"b81" => data <= x"d0";
when "01" & x"b82" => data <= x"14";
when "01" & x"b83" => data <= x"a5";
when "01" & x"b84" => data <= x"c8";
when "01" & x"b85" => data <= x"c5";
when "01" & x"b86" => data <= x"ca";
when "01" & x"b87" => data <= x"d0";
when "01" & x"b88" => data <= x"0e";
when "01" & x"b89" => data <= x"18";
when "01" & x"b8a" => data <= x"65";
when "01" & x"b8b" => data <= x"c6";
when "01" & x"b8c" => data <= x"85";
when "01" & x"b8d" => data <= x"ca";
when "01" & x"b8e" => data <= x"a5";
when "01" & x"b8f" => data <= x"cb";
when "01" & x"b90" => data <= x"65";
when "01" & x"b91" => data <= x"c7";
when "01" & x"b92" => data <= x"85";
when "01" & x"b93" => data <= x"cb";
when "01" & x"b94" => data <= x"4c";
when "01" & x"b95" => data <= x"b5";
when "01" & x"b96" => data <= x"9b";
when "01" & x"b97" => data <= x"a5";
when "01" & x"b98" => data <= x"ca";
when "01" & x"b99" => data <= x"99";
when "01" & x"b9a" => data <= x"0f";
when "01" & x"b9b" => data <= x"0f";
when "01" & x"b9c" => data <= x"b9";
when "01" & x"b9d" => data <= x"0e";
when "01" & x"b9e" => data <= x"0f";
when "01" & x"b9f" => data <= x"29";
when "01" & x"ba0" => data <= x"fc";
when "01" & x"ba1" => data <= x"05";
when "01" & x"ba2" => data <= x"cb";
when "01" & x"ba3" => data <= x"99";
when "01" & x"ba4" => data <= x"0e";
when "01" & x"ba5" => data <= x"0f";
when "01" & x"ba6" => data <= x"a9";
when "01" & x"ba7" => data <= x"00";
when "01" & x"ba8" => data <= x"85";
when "01" & x"ba9" => data <= x"a8";
when "01" & x"baa" => data <= x"85";
when "01" & x"bab" => data <= x"a9";
when "01" & x"bac" => data <= x"20";
when "01" & x"bad" => data <= x"b4";
when "01" & x"bae" => data <= x"8a";
when "01" & x"baf" => data <= x"20";
when "01" & x"bb0" => data <= x"06";
when "01" & x"bb1" => data <= x"9e";
when "01" & x"bb2" => data <= x"20";
when "01" & x"bb3" => data <= x"47";
when "01" & x"bb4" => data <= x"83";
when "01" & x"bb5" => data <= x"a4";
when "01" & x"bb6" => data <= x"cc";
when "01" & x"bb7" => data <= x"20";
when "01" & x"bb8" => data <= x"01";
when "01" & x"bb9" => data <= x"83";
when "01" & x"bba" => data <= x"4c";
when "01" & x"bbb" => data <= x"fb";
when "01" & x"bbc" => data <= x"9a";
when "01" & x"bbd" => data <= x"2c";
when "01" & x"bbe" => data <= x"c8";
when "01" & x"bbf" => data <= x"10";
when "01" & x"bc0" => data <= x"10";
when "01" & x"bc1" => data <= x"75";
when "01" & x"bc2" => data <= x"20";
when "01" & x"bc3" => data <= x"33";
when "01" & x"bc4" => data <= x"80";
when "01" & x"bc5" => data <= x"bd";
when "01" & x"bc6" => data <= x"4e";
when "01" & x"bc7" => data <= x"6f";
when "01" & x"bc8" => data <= x"74";
when "01" & x"bc9" => data <= x"20";
when "01" & x"bca" => data <= x"65";
when "01" & x"bcb" => data <= x"6e";
when "01" & x"bcc" => data <= x"61";
when "01" & x"bcd" => data <= x"62";
when "01" & x"bce" => data <= x"6c";
when "01" & x"bcf" => data <= x"65";
when "01" & x"bd0" => data <= x"64";
when "01" & x"bd1" => data <= x"00";
when "01" & x"bd2" => data <= x"20";
when "01" & x"bd3" => data <= x"bf";
when "01" & x"bd4" => data <= x"86";
when "01" & x"bd5" => data <= x"d0";
when "01" & x"bd6" => data <= x"03";
when "01" & x"bd7" => data <= x"4c";
when "01" & x"bd8" => data <= x"06";
when "01" & x"bd9" => data <= x"9a";
when "01" & x"bda" => data <= x"20";
when "01" & x"bdb" => data <= x"5d";
when "01" & x"bdc" => data <= x"83";
when "01" & x"bdd" => data <= x"8d";
when "01" & x"bde" => data <= x"d2";
when "01" & x"bdf" => data <= x"10";
when "01" & x"be0" => data <= x"20";
when "01" & x"be1" => data <= x"bf";
when "01" & x"be2" => data <= x"86";
when "01" & x"be3" => data <= x"f0";
when "01" & x"be4" => data <= x"f2";
when "01" & x"be5" => data <= x"20";
when "01" & x"be6" => data <= x"5d";
when "01" & x"be7" => data <= x"83";
when "01" & x"be8" => data <= x"8d";
when "01" & x"be9" => data <= x"d3";
when "01" & x"bea" => data <= x"10";
when "01" & x"beb" => data <= x"98";
when "01" & x"bec" => data <= x"48";
when "01" & x"bed" => data <= x"a9";
when "01" & x"bee" => data <= x"00";
when "01" & x"bef" => data <= x"85";
when "01" & x"bf0" => data <= x"a9";
when "01" & x"bf1" => data <= x"ad";
when "01" & x"bf2" => data <= x"d3";
when "01" & x"bf3" => data <= x"10";
when "01" & x"bf4" => data <= x"cd";
when "01" & x"bf5" => data <= x"d2";
when "01" & x"bf6" => data <= x"10";
when "01" & x"bf7" => data <= x"d0";
when "01" & x"bf8" => data <= x"06";
when "01" & x"bf9" => data <= x"a9";
when "01" & x"bfa" => data <= x"ff";
when "01" & x"bfb" => data <= x"85";
when "01" & x"bfc" => data <= x"a9";
when "01" & x"bfd" => data <= x"85";
when "01" & x"bfe" => data <= x"aa";
when "01" & x"bff" => data <= x"20";
when "01" & x"c00" => data <= x"79";
when "01" & x"c01" => data <= x"98";
when "01" & x"c02" => data <= x"20";
when "01" & x"c03" => data <= x"65";
when "01" & x"c04" => data <= x"80";
when "01" & x"c05" => data <= x"43";
when "01" & x"c06" => data <= x"6f";
when "01" & x"c07" => data <= x"70";
when "01" & x"c08" => data <= x"79";
when "01" & x"c09" => data <= x"69";
when "01" & x"c0a" => data <= x"6e";
when "01" & x"c0b" => data <= x"67";
when "01" & x"c0c" => data <= x"20";
when "01" & x"c0d" => data <= x"66";
when "01" & x"c0e" => data <= x"72";
when "01" & x"c0f" => data <= x"6f";
when "01" & x"c10" => data <= x"6d";
when "01" & x"c11" => data <= x"20";
when "01" & x"c12" => data <= x"64";
when "01" & x"c13" => data <= x"72";
when "01" & x"c14" => data <= x"69";
when "01" & x"c15" => data <= x"76";
when "01" & x"c16" => data <= x"65";
when "01" & x"c17" => data <= x"20";
when "01" & x"c18" => data <= x"ad";
when "01" & x"c19" => data <= x"d2";
when "01" & x"c1a" => data <= x"10";
when "01" & x"c1b" => data <= x"20";
when "01" & x"c1c" => data <= x"ca";
when "01" & x"c1d" => data <= x"80";
when "01" & x"c1e" => data <= x"20";
when "01" & x"c1f" => data <= x"65";
when "01" & x"c20" => data <= x"80";
when "01" & x"c21" => data <= x"20";
when "01" & x"c22" => data <= x"74";
when "01" & x"c23" => data <= x"6f";
when "01" & x"c24" => data <= x"20";
when "01" & x"c25" => data <= x"64";
when "01" & x"c26" => data <= x"72";
when "01" & x"c27" => data <= x"69";
when "01" & x"c28" => data <= x"76";
when "01" & x"c29" => data <= x"65";
when "01" & x"c2a" => data <= x"20";
when "01" & x"c2b" => data <= x"ad";
when "01" & x"c2c" => data <= x"d3";
when "01" & x"c2d" => data <= x"10";
when "01" & x"c2e" => data <= x"20";
when "01" & x"c2f" => data <= x"ca";
when "01" & x"c30" => data <= x"80";
when "01" & x"c31" => data <= x"20";
when "01" & x"c32" => data <= x"9a";
when "01" & x"c33" => data <= x"9f";
when "01" & x"c34" => data <= x"68";
when "01" & x"c35" => data <= x"a8";
when "01" & x"c36" => data <= x"18";
when "01" & x"c37" => data <= x"60";
when "01" & x"c38" => data <= x"20";
when "01" & x"c39" => data <= x"e1";
when "01" & x"c3a" => data <= x"83";
when "01" & x"c3b" => data <= x"24";
when "01" & x"c3c" => data <= x"a9";
when "01" & x"c3d" => data <= x"10";
when "01" & x"c3e" => data <= x"0b";
when "01" & x"c3f" => data <= x"a9";
when "01" & x"c40" => data <= x"00";
when "01" & x"c41" => data <= x"f0";
when "01" & x"c42" => data <= x"0a";
when "01" & x"c43" => data <= x"20";
when "01" & x"c44" => data <= x"e1";
when "01" & x"c45" => data <= x"83";
when "01" & x"c46" => data <= x"24";
when "01" & x"c47" => data <= x"a9";
when "01" & x"c48" => data <= x"30";
when "01" & x"c49" => data <= x"01";
when "01" & x"c4a" => data <= x"60";
when "01" & x"c4b" => data <= x"a9";
when "01" & x"c4c" => data <= x"80";
when "01" & x"c4d" => data <= x"c5";
when "01" & x"c4e" => data <= x"aa";
when "01" & x"c4f" => data <= x"f0";
when "01" & x"c50" => data <= x"f9";
when "01" & x"c51" => data <= x"85";
when "01" & x"c52" => data <= x"aa";
when "01" & x"c53" => data <= x"20";
when "01" & x"c54" => data <= x"65";
when "01" & x"c55" => data <= x"80";
when "01" & x"c56" => data <= x"49";
when "01" & x"c57" => data <= x"6e";
when "01" & x"c58" => data <= x"73";
when "01" & x"c59" => data <= x"65";
when "01" & x"c5a" => data <= x"72";
when "01" & x"c5b" => data <= x"74";
when "01" & x"c5c" => data <= x"20";
when "01" & x"c5d" => data <= x"ea";
when "01" & x"c5e" => data <= x"24";
when "01" & x"c5f" => data <= x"aa";
when "01" & x"c60" => data <= x"30";
when "01" & x"c61" => data <= x"0b";
when "01" & x"c62" => data <= x"20";
when "01" & x"c63" => data <= x"65";
when "01" & x"c64" => data <= x"80";
when "01" & x"c65" => data <= x"73";
when "01" & x"c66" => data <= x"6f";
when "01" & x"c67" => data <= x"75";
when "01" & x"c68" => data <= x"72";
when "01" & x"c69" => data <= x"63";
when "01" & x"c6a" => data <= x"65";
when "01" & x"c6b" => data <= x"90";
when "01" & x"c6c" => data <= x"0f";
when "01" & x"c6d" => data <= x"20";
when "01" & x"c6e" => data <= x"65";
when "01" & x"c6f" => data <= x"80";
when "01" & x"c70" => data <= x"64";
when "01" & x"c71" => data <= x"65";
when "01" & x"c72" => data <= x"73";
when "01" & x"c73" => data <= x"74";
when "01" & x"c74" => data <= x"69";
when "01" & x"c75" => data <= x"6e";
when "01" & x"c76" => data <= x"61";
when "01" & x"c77" => data <= x"74";
when "01" & x"c78" => data <= x"69";
when "01" & x"c79" => data <= x"6f";
when "01" & x"c7a" => data <= x"6e";
when "01" & x"c7b" => data <= x"ea";
when "01" & x"c7c" => data <= x"20";
when "01" & x"c7d" => data <= x"65";
when "01" & x"c7e" => data <= x"80";
when "01" & x"c7f" => data <= x"20";
when "01" & x"c80" => data <= x"64";
when "01" & x"c81" => data <= x"69";
when "01" & x"c82" => data <= x"73";
when "01" & x"c83" => data <= x"6b";
when "01" & x"c84" => data <= x"20";
when "01" & x"c85" => data <= x"61";
when "01" & x"c86" => data <= x"6e";
when "01" & x"c87" => data <= x"64";
when "01" & x"c88" => data <= x"20";
when "01" & x"c89" => data <= x"68";
when "01" & x"c8a" => data <= x"69";
when "01" & x"c8b" => data <= x"74";
when "01" & x"c8c" => data <= x"20";
when "01" & x"c8d" => data <= x"61";
when "01" & x"c8e" => data <= x"20";
when "01" & x"c8f" => data <= x"6b";
when "01" & x"c90" => data <= x"65";
when "01" & x"c91" => data <= x"79";
when "01" & x"c92" => data <= x"ea";
when "01" & x"c93" => data <= x"20";
when "01" & x"c94" => data <= x"06";
when "01" & x"c95" => data <= x"99";
when "01" & x"c96" => data <= x"20";
when "01" & x"c97" => data <= x"e0";
when "01" & x"c98" => data <= x"ff";
when "01" & x"c99" => data <= x"b0";
when "01" & x"c9a" => data <= x"19";
when "01" & x"c9b" => data <= x"4c";
when "01" & x"c9c" => data <= x"9a";
when "01" & x"c9d" => data <= x"9f";
when "01" & x"c9e" => data <= x"20";
when "01" & x"c9f" => data <= x"06";
when "01" & x"ca0" => data <= x"99";
when "01" & x"ca1" => data <= x"20";
when "01" & x"ca2" => data <= x"e0";
when "01" & x"ca3" => data <= x"ff";
when "01" & x"ca4" => data <= x"b0";
when "01" & x"ca5" => data <= x"0e";
when "01" & x"ca6" => data <= x"29";
when "01" & x"ca7" => data <= x"5f";
when "01" & x"ca8" => data <= x"c9";
when "01" & x"ca9" => data <= x"59";
when "01" & x"caa" => data <= x"08";
when "01" & x"cab" => data <= x"f0";
when "01" & x"cac" => data <= x"02";
when "01" & x"cad" => data <= x"a9";
when "01" & x"cae" => data <= x"4e";
when "01" & x"caf" => data <= x"20";
when "01" & x"cb0" => data <= x"9c";
when "01" & x"cb1" => data <= x"80";
when "01" & x"cb2" => data <= x"28";
when "01" & x"cb3" => data <= x"60";
when "01" & x"cb4" => data <= x"a6";
when "01" & x"cb5" => data <= x"b6";
when "01" & x"cb6" => data <= x"9a";
when "01" & x"cb7" => data <= x"60";
when "01" & x"cb8" => data <= x"4c";
when "01" & x"cb9" => data <= x"58";
when "01" & x"cba" => data <= x"89";
when "01" & x"cbb" => data <= x"20";
when "01" & x"cbc" => data <= x"bd";
when "01" & x"cbd" => data <= x"9b";
when "01" & x"cbe" => data <= x"20";
when "01" & x"cbf" => data <= x"d2";
when "01" & x"cc0" => data <= x"9b";
when "01" & x"cc1" => data <= x"a9";
when "01" & x"cc2" => data <= x"00";
when "01" & x"cc3" => data <= x"85";
when "01" & x"cc4" => data <= x"c9";
when "01" & x"cc5" => data <= x"85";
when "01" & x"cc6" => data <= x"cb";
when "01" & x"cc7" => data <= x"85";
when "01" & x"cc8" => data <= x"ca";
when "01" & x"cc9" => data <= x"85";
when "01" & x"cca" => data <= x"c8";
when "01" & x"ccb" => data <= x"85";
when "01" & x"ccc" => data <= x"a8";
when "01" & x"ccd" => data <= x"20";
when "01" & x"cce" => data <= x"38";
when "01" & x"ccf" => data <= x"9c";
when "01" & x"cd0" => data <= x"ad";
when "01" & x"cd1" => data <= x"d2";
when "01" & x"cd2" => data <= x"10";
when "01" & x"cd3" => data <= x"85";
when "01" & x"cd4" => data <= x"cf";
when "01" & x"cd5" => data <= x"20";
when "01" & x"cd6" => data <= x"41";
when "01" & x"cd7" => data <= x"af";
when "01" & x"cd8" => data <= x"ad";
when "01" & x"cd9" => data <= x"07";
when "01" & x"cda" => data <= x"0f";
when "01" & x"cdb" => data <= x"85";
when "01" & x"cdc" => data <= x"c6";
when "01" & x"cdd" => data <= x"ad";
when "01" & x"cde" => data <= x"06";
when "01" & x"cdf" => data <= x"0f";
when "01" & x"ce0" => data <= x"29";
when "01" & x"ce1" => data <= x"03";
when "01" & x"ce2" => data <= x"85";
when "01" & x"ce3" => data <= x"c7";
when "01" & x"ce4" => data <= x"ad";
when "01" & x"ce5" => data <= x"06";
when "01" & x"ce6" => data <= x"0f";
when "01" & x"ce7" => data <= x"29";
when "01" & x"ce8" => data <= x"f0";
when "01" & x"ce9" => data <= x"8d";
when "01" & x"cea" => data <= x"d8";
when "01" & x"ceb" => data <= x"10";
when "01" & x"cec" => data <= x"20";
when "01" & x"ced" => data <= x"43";
when "01" & x"cee" => data <= x"9c";
when "01" & x"cef" => data <= x"ad";
when "01" & x"cf0" => data <= x"d3";
when "01" & x"cf1" => data <= x"10";
when "01" & x"cf2" => data <= x"85";
when "01" & x"cf3" => data <= x"cf";
when "01" & x"cf4" => data <= x"20";
when "01" & x"cf5" => data <= x"41";
when "01" & x"cf6" => data <= x"af";
when "01" & x"cf7" => data <= x"ad";
when "01" & x"cf8" => data <= x"06";
when "01" & x"cf9" => data <= x"0f";
when "01" & x"cfa" => data <= x"29";
when "01" & x"cfb" => data <= x"03";
when "01" & x"cfc" => data <= x"c5";
when "01" & x"cfd" => data <= x"c7";
when "01" & x"cfe" => data <= x"90";
when "01" & x"cff" => data <= x"b8";
when "01" & x"d00" => data <= x"d0";
when "01" & x"d01" => data <= x"07";
when "01" & x"d02" => data <= x"ad";
when "01" & x"d03" => data <= x"07";
when "01" & x"d04" => data <= x"0f";
when "01" & x"d05" => data <= x"c5";
when "01" & x"d06" => data <= x"c6";
when "01" & x"d07" => data <= x"90";
when "01" & x"d08" => data <= x"af";
when "01" & x"d09" => data <= x"20";
when "01" & x"d0a" => data <= x"06";
when "01" & x"d0b" => data <= x"9e";
when "01" & x"d0c" => data <= x"ad";
when "01" & x"d0d" => data <= x"06";
when "01" & x"d0e" => data <= x"0f";
when "01" & x"d0f" => data <= x"48";
when "01" & x"d10" => data <= x"ad";
when "01" & x"d11" => data <= x"07";
when "01" & x"d12" => data <= x"0f";
when "01" & x"d13" => data <= x"48";
when "01" & x"d14" => data <= x"20";
when "01" & x"d15" => data <= x"41";
when "01" & x"d16" => data <= x"af";
when "01" & x"d17" => data <= x"68";
when "01" & x"d18" => data <= x"8d";
when "01" & x"d19" => data <= x"07";
when "01" & x"d1a" => data <= x"0f";
when "01" & x"d1b" => data <= x"68";
when "01" & x"d1c" => data <= x"29";
when "01" & x"d1d" => data <= x"0f";
when "01" & x"d1e" => data <= x"0d";
when "01" & x"d1f" => data <= x"d8";
when "01" & x"d20" => data <= x"10";
when "01" & x"d21" => data <= x"8d";
when "01" & x"d22" => data <= x"06";
when "01" & x"d23" => data <= x"0f";
when "01" & x"d24" => data <= x"4c";
when "01" & x"d25" => data <= x"b4";
when "01" & x"d26" => data <= x"8a";
when "01" & x"d27" => data <= x"20";
when "01" & x"d28" => data <= x"5e";
when "01" & x"d29" => data <= x"82";
when "01" & x"d2a" => data <= x"20";
when "01" & x"d2b" => data <= x"d2";
when "01" & x"d2c" => data <= x"9b";
when "01" & x"d2d" => data <= x"20";
when "01" & x"d2e" => data <= x"bf";
when "01" & x"d2f" => data <= x"86";
when "01" & x"d30" => data <= x"d0";
when "01" & x"d31" => data <= x"03";
when "01" & x"d32" => data <= x"4c";
when "01" & x"d33" => data <= x"06";
when "01" & x"d34" => data <= x"9a";
when "01" & x"d35" => data <= x"20";
when "01" & x"d36" => data <= x"fe";
when "01" & x"d37" => data <= x"80";
when "01" & x"d38" => data <= x"20";
when "01" & x"d39" => data <= x"38";
when "01" & x"d3a" => data <= x"9c";
when "01" & x"d3b" => data <= x"ad";
when "01" & x"d3c" => data <= x"d2";
when "01" & x"d3d" => data <= x"10";
when "01" & x"d3e" => data <= x"20";
when "01" & x"d3f" => data <= x"7e";
when "01" & x"d40" => data <= x"87";
when "01" & x"d41" => data <= x"20";
when "01" & x"d42" => data <= x"96";
when "01" & x"d43" => data <= x"82";
when "01" & x"d44" => data <= x"b0";
when "01" & x"d45" => data <= x"03";
when "01" & x"d46" => data <= x"4c";
when "01" & x"d47" => data <= x"76";
when "01" & x"d48" => data <= x"82";
when "01" & x"d49" => data <= x"84";
when "01" & x"d4a" => data <= x"ab";
when "01" & x"d4b" => data <= x"20";
when "01" & x"d4c" => data <= x"01";
when "01" & x"d4d" => data <= x"83";
when "01" & x"d4e" => data <= x"a2";
when "01" & x"d4f" => data <= x"00";
when "01" & x"d50" => data <= x"b5";
when "01" & x"d51" => data <= x"c7";
when "01" & x"d52" => data <= x"9d";
when "01" & x"d53" => data <= x"58";
when "01" & x"d54" => data <= x"10";
when "01" & x"d55" => data <= x"b9";
when "01" & x"d56" => data <= x"08";
when "01" & x"d57" => data <= x"0e";
when "01" & x"d58" => data <= x"95";
when "01" & x"d59" => data <= x"c7";
when "01" & x"d5a" => data <= x"9d";
when "01" & x"d5b" => data <= x"50";
when "01" & x"d5c" => data <= x"10";
when "01" & x"d5d" => data <= x"b9";
when "01" & x"d5e" => data <= x"08";
when "01" & x"d5f" => data <= x"0f";
when "01" & x"d60" => data <= x"95";
when "01" & x"d61" => data <= x"bd";
when "01" & x"d62" => data <= x"9d";
when "01" & x"d63" => data <= x"47";
when "01" & x"d64" => data <= x"10";
when "01" & x"d65" => data <= x"e8";
when "01" & x"d66" => data <= x"c8";
when "01" & x"d67" => data <= x"e0";
when "01" & x"d68" => data <= x"08";
when "01" & x"d69" => data <= x"d0";
when "01" & x"d6a" => data <= x"e5";
when "01" & x"d6b" => data <= x"a5";
when "01" & x"d6c" => data <= x"c3";
when "01" & x"d6d" => data <= x"20";
when "01" & x"d6e" => data <= x"fd";
when "01" & x"d6f" => data <= x"81";
when "01" & x"d70" => data <= x"85";
when "01" & x"d71" => data <= x"c5";
when "01" & x"d72" => data <= x"a5";
when "01" & x"d73" => data <= x"c1";
when "01" & x"d74" => data <= x"18";
when "01" & x"d75" => data <= x"69";
when "01" & x"d76" => data <= x"ff";
when "01" & x"d77" => data <= x"a5";
when "01" & x"d78" => data <= x"c2";
when "01" & x"d79" => data <= x"69";
when "01" & x"d7a" => data <= x"00";
when "01" & x"d7b" => data <= x"85";
when "01" & x"d7c" => data <= x"c6";
when "01" & x"d7d" => data <= x"a5";
when "01" & x"d7e" => data <= x"c5";
when "01" & x"d7f" => data <= x"69";
when "01" & x"d80" => data <= x"00";
when "01" & x"d81" => data <= x"85";
when "01" & x"d82" => data <= x"c7";
when "01" & x"d83" => data <= x"ad";
when "01" & x"d84" => data <= x"4e";
when "01" & x"d85" => data <= x"10";
when "01" & x"d86" => data <= x"85";
when "01" & x"d87" => data <= x"c8";
when "01" & x"d88" => data <= x"ad";
when "01" & x"d89" => data <= x"4d";
when "01" & x"d8a" => data <= x"10";
when "01" & x"d8b" => data <= x"29";
when "01" & x"d8c" => data <= x"03";
when "01" & x"d8d" => data <= x"85";
when "01" & x"d8e" => data <= x"c9";
when "01" & x"d8f" => data <= x"a9";
when "01" & x"d90" => data <= x"ff";
when "01" & x"d91" => data <= x"85";
when "01" & x"d92" => data <= x"a8";
when "01" & x"d93" => data <= x"20";
when "01" & x"d94" => data <= x"06";
when "01" & x"d95" => data <= x"9e";
when "01" & x"d96" => data <= x"20";
when "01" & x"d97" => data <= x"38";
when "01" & x"d98" => data <= x"9c";
when "01" & x"d99" => data <= x"ad";
when "01" & x"d9a" => data <= x"d2";
when "01" & x"d9b" => data <= x"10";
when "01" & x"d9c" => data <= x"20";
when "01" & x"d9d" => data <= x"7e";
when "01" & x"d9e" => data <= x"87";
when "01" & x"d9f" => data <= x"20";
when "01" & x"da0" => data <= x"47";
when "01" & x"da1" => data <= x"83";
when "01" & x"da2" => data <= x"a2";
when "01" & x"da3" => data <= x"07";
when "01" & x"da4" => data <= x"bd";
when "01" & x"da5" => data <= x"58";
when "01" & x"da6" => data <= x"10";
when "01" & x"da7" => data <= x"95";
when "01" & x"da8" => data <= x"c7";
when "01" & x"da9" => data <= x"ca";
when "01" & x"daa" => data <= x"10";
when "01" & x"dab" => data <= x"f8";
when "01" & x"dac" => data <= x"a4";
when "01" & x"dad" => data <= x"ab";
when "01" & x"dae" => data <= x"8c";
when "01" & x"daf" => data <= x"ce";
when "01" & x"db0" => data <= x"10";
when "01" & x"db1" => data <= x"20";
when "01" & x"db2" => data <= x"9d";
when "01" & x"db3" => data <= x"82";
when "01" & x"db4" => data <= x"b0";
when "01" & x"db5" => data <= x"93";
when "01" & x"db6" => data <= x"60";
when "01" & x"db7" => data <= x"20";
when "01" & x"db8" => data <= x"f5";
when "01" & x"db9" => data <= x"9d";
when "01" & x"dba" => data <= x"20";
when "01" & x"dbb" => data <= x"43";
when "01" & x"dbc" => data <= x"9c";
when "01" & x"dbd" => data <= x"ad";
when "01" & x"dbe" => data <= x"d3";
when "01" & x"dbf" => data <= x"10";
when "01" & x"dc0" => data <= x"85";
when "01" & x"dc1" => data <= x"cf";
when "01" & x"dc2" => data <= x"a5";
when "01" & x"dc3" => data <= x"ce";
when "01" & x"dc4" => data <= x"48";
when "01" & x"dc5" => data <= x"20";
when "01" & x"dc6" => data <= x"47";
when "01" & x"dc7" => data <= x"83";
when "01" & x"dc8" => data <= x"20";
when "01" & x"dc9" => data <= x"96";
when "01" & x"dca" => data <= x"82";
when "01" & x"dcb" => data <= x"90";
when "01" & x"dcc" => data <= x"03";
when "01" & x"dcd" => data <= x"20";
when "01" & x"dce" => data <= x"d1";
when "01" & x"dcf" => data <= x"82";
when "01" & x"dd0" => data <= x"68";
when "01" & x"dd1" => data <= x"85";
when "01" & x"dd2" => data <= x"ce";
when "01" & x"dd3" => data <= x"20";
when "01" & x"dd4" => data <= x"3f";
when "01" & x"dd5" => data <= x"8a";
when "01" & x"dd6" => data <= x"20";
when "01" & x"dd7" => data <= x"56";
when "01" & x"dd8" => data <= x"8a";
when "01" & x"dd9" => data <= x"a5";
when "01" & x"dda" => data <= x"c4";
when "01" & x"ddb" => data <= x"20";
when "01" & x"ddc" => data <= x"fd";
when "01" & x"ddd" => data <= x"81";
when "01" & x"dde" => data <= x"85";
when "01" & x"ddf" => data <= x"c6";
when "01" & x"de0" => data <= x"20";
when "01" & x"de1" => data <= x"9d";
when "01" & x"de2" => data <= x"89";
when "01" & x"de3" => data <= x"a5";
when "01" & x"de4" => data <= x"c4";
when "01" & x"de5" => data <= x"29";
when "01" & x"de6" => data <= x"03";
when "01" & x"de7" => data <= x"48";
when "01" & x"de8" => data <= x"a5";
when "01" & x"de9" => data <= x"c5";
when "01" & x"dea" => data <= x"48";
when "01" & x"deb" => data <= x"20";
when "01" & x"dec" => data <= x"f5";
when "01" & x"ded" => data <= x"9d";
when "01" & x"dee" => data <= x"68";
when "01" & x"def" => data <= x"85";
when "01" & x"df0" => data <= x"ca";
when "01" & x"df1" => data <= x"68";
when "01" & x"df2" => data <= x"85";
when "01" & x"df3" => data <= x"cb";
when "01" & x"df4" => data <= x"60";
when "01" & x"df5" => data <= x"a2";
when "01" & x"df6" => data <= x"11";
when "01" & x"df7" => data <= x"bd";
when "01" & x"df8" => data <= x"45";
when "01" & x"df9" => data <= x"10";
when "01" & x"dfa" => data <= x"b4";
when "01" & x"dfb" => data <= x"bc";
when "01" & x"dfc" => data <= x"95";
when "01" & x"dfd" => data <= x"bc";
when "01" & x"dfe" => data <= x"98";
when "01" & x"dff" => data <= x"9d";
when "01" & x"e00" => data <= x"45";
when "01" & x"e01" => data <= x"10";
when "01" & x"e02" => data <= x"ca";
when "01" & x"e03" => data <= x"10";
when "01" & x"e04" => data <= x"f2";
when "01" & x"e05" => data <= x"60";
when "01" & x"e06" => data <= x"20";
when "01" & x"e07" => data <= x"8d";
when "01" & x"e08" => data <= x"a0";
when "01" & x"e09" => data <= x"a9";
when "01" & x"e0a" => data <= x"00";
when "01" & x"e0b" => data <= x"85";
when "01" & x"e0c" => data <= x"be";
when "01" & x"e0d" => data <= x"85";
when "01" & x"e0e" => data <= x"c2";
when "01" & x"e0f" => data <= x"a5";
when "01" & x"e10" => data <= x"c6";
when "01" & x"e11" => data <= x"a8";
when "01" & x"e12" => data <= x"cd";
when "01" & x"e13" => data <= x"d1";
when "01" & x"e14" => data <= x"10";
when "01" & x"e15" => data <= x"a5";
when "01" & x"e16" => data <= x"c7";
when "01" & x"e17" => data <= x"e9";
when "01" & x"e18" => data <= x"00";
when "01" & x"e19" => data <= x"90";
when "01" & x"e1a" => data <= x"03";
when "01" & x"e1b" => data <= x"ac";
when "01" & x"e1c" => data <= x"d1";
when "01" & x"e1d" => data <= x"10";
when "01" & x"e1e" => data <= x"84";
when "01" & x"e1f" => data <= x"c3";
when "01" & x"e20" => data <= x"a5";
when "01" & x"e21" => data <= x"c8";
when "01" & x"e22" => data <= x"85";
when "01" & x"e23" => data <= x"c5";
when "01" & x"e24" => data <= x"a5";
when "01" & x"e25" => data <= x"c9";
when "01" & x"e26" => data <= x"85";
when "01" & x"e27" => data <= x"c4";
when "01" & x"e28" => data <= x"ad";
when "01" & x"e29" => data <= x"d0";
when "01" & x"e2a" => data <= x"10";
when "01" & x"e2b" => data <= x"85";
when "01" & x"e2c" => data <= x"bf";
when "01" & x"e2d" => data <= x"ad";
when "01" & x"e2e" => data <= x"d2";
when "01" & x"e2f" => data <= x"10";
when "01" & x"e30" => data <= x"85";
when "01" & x"e31" => data <= x"cf";
when "01" & x"e32" => data <= x"20";
when "01" & x"e33" => data <= x"38";
when "01" & x"e34" => data <= x"9c";
when "01" & x"e35" => data <= x"20";
when "01" & x"e36" => data <= x"3e";
when "01" & x"e37" => data <= x"be";
when "01" & x"e38" => data <= x"20";
when "01" & x"e39" => data <= x"c6";
when "01" & x"e3a" => data <= x"87";
when "01" & x"e3b" => data <= x"ad";
when "01" & x"e3c" => data <= x"d3";
when "01" & x"e3d" => data <= x"10";
when "01" & x"e3e" => data <= x"85";
when "01" & x"e3f" => data <= x"cf";
when "01" & x"e40" => data <= x"24";
when "01" & x"e41" => data <= x"a8";
when "01" & x"e42" => data <= x"10";
when "01" & x"e43" => data <= x"07";
when "01" & x"e44" => data <= x"20";
when "01" & x"e45" => data <= x"b7";
when "01" & x"e46" => data <= x"9d";
when "01" & x"e47" => data <= x"a9";
when "01" & x"e48" => data <= x"00";
when "01" & x"e49" => data <= x"85";
when "01" & x"e4a" => data <= x"a8";
when "01" & x"e4b" => data <= x"a5";
when "01" & x"e4c" => data <= x"ca";
when "01" & x"e4d" => data <= x"85";
when "01" & x"e4e" => data <= x"c5";
when "01" & x"e4f" => data <= x"a5";
when "01" & x"e50" => data <= x"cb";
when "01" & x"e51" => data <= x"85";
when "01" & x"e52" => data <= x"c4";
when "01" & x"e53" => data <= x"ad";
when "01" & x"e54" => data <= x"d0";
when "01" & x"e55" => data <= x"10";
when "01" & x"e56" => data <= x"85";
when "01" & x"e57" => data <= x"bf";
when "01" & x"e58" => data <= x"20";
when "01" & x"e59" => data <= x"43";
when "01" & x"e5a" => data <= x"9c";
when "01" & x"e5b" => data <= x"20";
when "01" & x"e5c" => data <= x"3e";
when "01" & x"e5d" => data <= x"be";
when "01" & x"e5e" => data <= x"20";
when "01" & x"e5f" => data <= x"8f";
when "01" & x"e60" => data <= x"87";
when "01" & x"e61" => data <= x"a5";
when "01" & x"e62" => data <= x"c3";
when "01" & x"e63" => data <= x"18";
when "01" & x"e64" => data <= x"65";
when "01" & x"e65" => data <= x"ca";
when "01" & x"e66" => data <= x"85";
when "01" & x"e67" => data <= x"ca";
when "01" & x"e68" => data <= x"90";
when "01" & x"e69" => data <= x"02";
when "01" & x"e6a" => data <= x"e6";
when "01" & x"e6b" => data <= x"cb";
when "01" & x"e6c" => data <= x"a5";
when "01" & x"e6d" => data <= x"c3";
when "01" & x"e6e" => data <= x"18";
when "01" & x"e6f" => data <= x"65";
when "01" & x"e70" => data <= x"c8";
when "01" & x"e71" => data <= x"85";
when "01" & x"e72" => data <= x"c8";
when "01" & x"e73" => data <= x"90";
when "01" & x"e74" => data <= x"02";
when "01" & x"e75" => data <= x"e6";
when "01" & x"e76" => data <= x"c9";
when "01" & x"e77" => data <= x"38";
when "01" & x"e78" => data <= x"a5";
when "01" & x"e79" => data <= x"c6";
when "01" & x"e7a" => data <= x"e5";
when "01" & x"e7b" => data <= x"c3";
when "01" & x"e7c" => data <= x"85";
when "01" & x"e7d" => data <= x"c6";
when "01" & x"e7e" => data <= x"b0";
when "01" & x"e7f" => data <= x"02";
when "01" & x"e80" => data <= x"c6";
when "01" & x"e81" => data <= x"c7";
when "01" & x"e82" => data <= x"05";
when "01" & x"e83" => data <= x"c7";
when "01" & x"e84" => data <= x"d0";
when "01" & x"e85" => data <= x"89";
when "01" & x"e86" => data <= x"60";
when "01" & x"e87" => data <= x"20";
when "01" & x"e88" => data <= x"d7";
when "01" & x"e89" => data <= x"9f";
when "01" & x"e8a" => data <= x"a9";
when "01" & x"e8b" => data <= x"00";
when "01" & x"e8c" => data <= x"f0";
when "01" & x"e8d" => data <= x"05";
when "01" & x"e8e" => data <= x"20";
when "01" & x"e8f" => data <= x"d7";
when "01" & x"e90" => data <= x"9f";
when "01" & x"e91" => data <= x"a9";
when "01" & x"e92" => data <= x"ff";
when "01" & x"e93" => data <= x"85";
when "01" & x"e94" => data <= x"ab";
when "01" & x"e95" => data <= x"a9";
when "01" & x"e96" => data <= x"c0";
when "01" & x"e97" => data <= x"20";
when "01" & x"e98" => data <= x"ce";
when "01" & x"e99" => data <= x"ff";
when "01" & x"e9a" => data <= x"a8";
when "01" & x"e9b" => data <= x"a9";
when "01" & x"e9c" => data <= x"0d";
when "01" & x"e9d" => data <= x"c0";
when "01" & x"e9e" => data <= x"00";
when "01" & x"e9f" => data <= x"d0";
when "01" & x"ea0" => data <= x"1e";
when "01" & x"ea1" => data <= x"4c";
when "01" & x"ea2" => data <= x"76";
when "01" & x"ea3" => data <= x"82";
when "01" & x"ea4" => data <= x"20";
when "01" & x"ea5" => data <= x"d7";
when "01" & x"ea6" => data <= x"ff";
when "01" & x"ea7" => data <= x"b0";
when "01" & x"ea8" => data <= x"1e";
when "01" & x"ea9" => data <= x"c9";
when "01" & x"eaa" => data <= x"0a";
when "01" & x"eab" => data <= x"f0";
when "01" & x"eac" => data <= x"f7";
when "01" & x"ead" => data <= x"28";
when "01" & x"eae" => data <= x"d0";
when "01" & x"eaf" => data <= x"08";
when "01" & x"eb0" => data <= x"48";
when "01" & x"eb1" => data <= x"20";
when "01" & x"eb2" => data <= x"a2";
when "01" & x"eb3" => data <= x"9f";
when "01" & x"eb4" => data <= x"20";
when "01" & x"eb5" => data <= x"ce";
when "01" & x"eb6" => data <= x"9f";
when "01" & x"eb7" => data <= x"68";
when "01" & x"eb8" => data <= x"20";
when "01" & x"eb9" => data <= x"e3";
when "01" & x"eba" => data <= x"ff";
when "01" & x"ebb" => data <= x"24";
when "01" & x"ebc" => data <= x"ff";
when "01" & x"ebd" => data <= x"30";
when "01" & x"ebe" => data <= x"09";
when "01" & x"ebf" => data <= x"25";
when "01" & x"ec0" => data <= x"ab";
when "01" & x"ec1" => data <= x"c9";
when "01" & x"ec2" => data <= x"0d";
when "01" & x"ec3" => data <= x"08";
when "01" & x"ec4" => data <= x"4c";
when "01" & x"ec5" => data <= x"a4";
when "01" & x"ec6" => data <= x"9e";
when "01" & x"ec7" => data <= x"28";
when "01" & x"ec8" => data <= x"20";
when "01" & x"ec9" => data <= x"9a";
when "01" & x"eca" => data <= x"9f";
when "01" & x"ecb" => data <= x"a9";
when "01" & x"ecc" => data <= x"00";
when "01" & x"ecd" => data <= x"4c";
when "01" & x"ece" => data <= x"ce";
when "01" & x"ecf" => data <= x"ff";
when "01" & x"ed0" => data <= x"20";
when "01" & x"ed1" => data <= x"d7";
when "01" & x"ed2" => data <= x"9f";
when "01" & x"ed3" => data <= x"a9";
when "01" & x"ed4" => data <= x"c0";
when "01" & x"ed5" => data <= x"20";
when "01" & x"ed6" => data <= x"ce";
when "01" & x"ed7" => data <= x"ff";
when "01" & x"ed8" => data <= x"a8";
when "01" & x"ed9" => data <= x"f0";
when "01" & x"eda" => data <= x"c6";
when "01" & x"edb" => data <= x"a6";
when "01" & x"edc" => data <= x"f4";
when "01" & x"edd" => data <= x"bd";
when "01" & x"ede" => data <= x"f0";
when "01" & x"edf" => data <= x"0d";
when "01" & x"ee0" => data <= x"85";
when "01" & x"ee1" => data <= x"ad";
when "01" & x"ee2" => data <= x"e6";
when "01" & x"ee3" => data <= x"ad";
when "01" & x"ee4" => data <= x"24";
when "01" & x"ee5" => data <= x"ff";
when "01" & x"ee6" => data <= x"30";
when "01" & x"ee7" => data <= x"e3";
when "01" & x"ee8" => data <= x"a5";
when "01" & x"ee9" => data <= x"a9";
when "01" & x"eea" => data <= x"20";
when "01" & x"eeb" => data <= x"c2";
when "01" & x"eec" => data <= x"80";
when "01" & x"eed" => data <= x"a5";
when "01" & x"eee" => data <= x"a8";
when "01" & x"eef" => data <= x"20";
when "01" & x"ef0" => data <= x"c2";
when "01" & x"ef1" => data <= x"80";
when "01" & x"ef2" => data <= x"20";
when "01" & x"ef3" => data <= x"ce";
when "01" & x"ef4" => data <= x"9f";
when "01" & x"ef5" => data <= x"a9";
when "01" & x"ef6" => data <= x"07";
when "01" & x"ef7" => data <= x"85";
when "01" & x"ef8" => data <= x"ac";
when "01" & x"ef9" => data <= x"a2";
when "01" & x"efa" => data <= x"00";
when "01" & x"efb" => data <= x"20";
when "01" & x"efc" => data <= x"d7";
when "01" & x"efd" => data <= x"ff";
when "01" & x"efe" => data <= x"b0";
when "01" & x"eff" => data <= x"0d";
when "01" & x"f00" => data <= x"81";
when "01" & x"f01" => data <= x"ac";
when "01" & x"f02" => data <= x"20";
when "01" & x"f03" => data <= x"c2";
when "01" & x"f04" => data <= x"80";
when "01" & x"f05" => data <= x"20";
when "01" & x"f06" => data <= x"ce";
when "01" & x"f07" => data <= x"9f";
when "01" & x"f08" => data <= x"c6";
when "01" & x"f09" => data <= x"ac";
when "01" & x"f0a" => data <= x"10";
when "01" & x"f0b" => data <= x"ef";
when "01" & x"f0c" => data <= x"18";
when "01" & x"f0d" => data <= x"08";
when "01" & x"f0e" => data <= x"90";
when "01" & x"f0f" => data <= x"0e";
when "01" & x"f10" => data <= x"20";
when "01" & x"f11" => data <= x"65";
when "01" & x"f12" => data <= x"80";
when "01" & x"f13" => data <= x"2a";
when "01" & x"f14" => data <= x"2a";
when "01" & x"f15" => data <= x"20";
when "01" & x"f16" => data <= x"a9";
when "01" & x"f17" => data <= x"00";
when "01" & x"f18" => data <= x"81";
when "01" & x"f19" => data <= x"ac";
when "01" & x"f1a" => data <= x"c6";
when "01" & x"f1b" => data <= x"ac";
when "01" & x"f1c" => data <= x"10";
when "01" & x"f1d" => data <= x"f2";
when "01" & x"f1e" => data <= x"a9";
when "01" & x"f1f" => data <= x"07";
when "01" & x"f20" => data <= x"85";
when "01" & x"f21" => data <= x"ac";
when "01" & x"f22" => data <= x"a1";
when "01" & x"f23" => data <= x"ac";
when "01" & x"f24" => data <= x"c9";
when "01" & x"f25" => data <= x"7f";
when "01" & x"f26" => data <= x"b0";
when "01" & x"f27" => data <= x"04";
when "01" & x"f28" => data <= x"c9";
when "01" & x"f29" => data <= x"20";
when "01" & x"f2a" => data <= x"b0";
when "01" & x"f2b" => data <= x"02";
when "01" & x"f2c" => data <= x"a9";
when "01" & x"f2d" => data <= x"2e";
when "01" & x"f2e" => data <= x"20";
when "01" & x"f2f" => data <= x"e3";
when "01" & x"f30" => data <= x"ff";
when "01" & x"f31" => data <= x"c6";
when "01" & x"f32" => data <= x"ac";
when "01" & x"f33" => data <= x"10";
when "01" & x"f34" => data <= x"ed";
when "01" & x"f35" => data <= x"20";
when "01" & x"f36" => data <= x"9a";
when "01" & x"f37" => data <= x"9f";
when "01" & x"f38" => data <= x"a9";
when "01" & x"f39" => data <= x"08";
when "01" & x"f3a" => data <= x"18";
when "01" & x"f3b" => data <= x"65";
when "01" & x"f3c" => data <= x"a8";
when "01" & x"f3d" => data <= x"85";
when "01" & x"f3e" => data <= x"a8";
when "01" & x"f3f" => data <= x"90";
when "01" & x"f40" => data <= x"02";
when "01" & x"f41" => data <= x"e6";
when "01" & x"f42" => data <= x"a9";
when "01" & x"f43" => data <= x"28";
when "01" & x"f44" => data <= x"90";
when "01" & x"f45" => data <= x"9e";
when "01" & x"f46" => data <= x"b0";
when "01" & x"f47" => data <= x"83";
when "01" & x"f48" => data <= x"20";
when "01" & x"f49" => data <= x"d7";
when "01" & x"f4a" => data <= x"9f";
when "01" & x"f4b" => data <= x"a9";
when "01" & x"f4c" => data <= x"80";
when "01" & x"f4d" => data <= x"20";
when "01" & x"f4e" => data <= x"ce";
when "01" & x"f4f" => data <= x"ff";
when "01" & x"f50" => data <= x"85";
when "01" & x"f51" => data <= x"ab";
when "01" & x"f52" => data <= x"20";
when "01" & x"f53" => data <= x"a2";
when "01" & x"f54" => data <= x"9f";
when "01" & x"f55" => data <= x"20";
when "01" & x"f56" => data <= x"ce";
when "01" & x"f57" => data <= x"9f";
when "01" & x"f58" => data <= x"a6";
when "01" & x"f59" => data <= x"f4";
when "01" & x"f5a" => data <= x"bc";
when "01" & x"f5b" => data <= x"f0";
when "01" & x"f5c" => data <= x"0d";
when "01" & x"f5d" => data <= x"c8";
when "01" & x"f5e" => data <= x"84";
when "01" & x"f5f" => data <= x"ad";
when "01" & x"f60" => data <= x"a2";
when "01" & x"f61" => data <= x"ac";
when "01" & x"f62" => data <= x"a0";
when "01" & x"f63" => data <= x"ff";
when "01" & x"f64" => data <= x"84";
when "01" & x"f65" => data <= x"ae";
when "01" & x"f66" => data <= x"84";
when "01" & x"f67" => data <= x"b0";
when "01" & x"f68" => data <= x"c8";
when "01" & x"f69" => data <= x"84";
when "01" & x"f6a" => data <= x"ac";
when "01" & x"f6b" => data <= x"84";
when "01" & x"f6c" => data <= x"af";
when "01" & x"f6d" => data <= x"98";
when "01" & x"f6e" => data <= x"20";
when "01" & x"f6f" => data <= x"f1";
when "01" & x"f70" => data <= x"ff";
when "01" & x"f71" => data <= x"08";
when "01" & x"f72" => data <= x"84";
when "01" & x"f73" => data <= x"aa";
when "01" & x"f74" => data <= x"a4";
when "01" & x"f75" => data <= x"ab";
when "01" & x"f76" => data <= x"a2";
when "01" & x"f77" => data <= x"00";
when "01" & x"f78" => data <= x"f0";
when "01" & x"f79" => data <= x"07";
when "01" & x"f7a" => data <= x"a1";
when "01" & x"f7b" => data <= x"ac";
when "01" & x"f7c" => data <= x"20";
when "01" & x"f7d" => data <= x"d4";
when "01" & x"f7e" => data <= x"ff";
when "01" & x"f7f" => data <= x"e6";
when "01" & x"f80" => data <= x"ac";
when "01" & x"f81" => data <= x"a5";
when "01" & x"f82" => data <= x"ac";
when "01" & x"f83" => data <= x"c5";
when "01" & x"f84" => data <= x"aa";
when "01" & x"f85" => data <= x"d0";
when "01" & x"f86" => data <= x"f3";
when "01" & x"f87" => data <= x"28";
when "01" & x"f88" => data <= x"b0";
when "01" & x"f89" => data <= x"08";
when "01" & x"f8a" => data <= x"a9";
when "01" & x"f8b" => data <= x"0d";
when "01" & x"f8c" => data <= x"20";
when "01" & x"f8d" => data <= x"d4";
when "01" & x"f8e" => data <= x"ff";
when "01" & x"f8f" => data <= x"4c";
when "01" & x"f90" => data <= x"52";
when "01" & x"f91" => data <= x"9f";
when "01" & x"f92" => data <= x"a9";
when "01" & x"f93" => data <= x"7e";
when "01" & x"f94" => data <= x"20";
when "01" & x"f95" => data <= x"f4";
when "01" & x"f96" => data <= x"ff";
when "01" & x"f97" => data <= x"20";
when "01" & x"f98" => data <= x"cb";
when "01" & x"f99" => data <= x"9e";
when "01" & x"f9a" => data <= x"48";
when "01" & x"f9b" => data <= x"a9";
when "01" & x"f9c" => data <= x"0d";
when "01" & x"f9d" => data <= x"20";
when "01" & x"f9e" => data <= x"9c";
when "01" & x"f9f" => data <= x"80";
when "01" & x"fa0" => data <= x"68";
when "01" & x"fa1" => data <= x"60";
when "01" & x"fa2" => data <= x"f8";
when "01" & x"fa3" => data <= x"18";
when "01" & x"fa4" => data <= x"a5";
when "01" & x"fa5" => data <= x"a8";
when "01" & x"fa6" => data <= x"69";
when "01" & x"fa7" => data <= x"01";
when "01" & x"fa8" => data <= x"85";
when "01" & x"fa9" => data <= x"a8";
when "01" & x"faa" => data <= x"a5";
when "01" & x"fab" => data <= x"a9";
when "01" & x"fac" => data <= x"69";
when "01" & x"fad" => data <= x"00";
when "01" & x"fae" => data <= x"85";
when "01" & x"faf" => data <= x"a9";
when "01" & x"fb0" => data <= x"d8";
when "01" & x"fb1" => data <= x"18";
when "01" & x"fb2" => data <= x"20";
when "01" & x"fb3" => data <= x"b7";
when "01" & x"fb4" => data <= x"9f";
when "01" & x"fb5" => data <= x"a5";
when "01" & x"fb6" => data <= x"a8";
when "01" & x"fb7" => data <= x"48";
when "01" & x"fb8" => data <= x"08";
when "01" & x"fb9" => data <= x"20";
when "01" & x"fba" => data <= x"05";
when "01" & x"fbb" => data <= x"82";
when "01" & x"fbc" => data <= x"28";
when "01" & x"fbd" => data <= x"20";
when "01" & x"fbe" => data <= x"c1";
when "01" & x"fbf" => data <= x"9f";
when "01" & x"fc0" => data <= x"68";
when "01" & x"fc1" => data <= x"aa";
when "01" & x"fc2" => data <= x"b0";
when "01" & x"fc3" => data <= x"02";
when "01" & x"fc4" => data <= x"f0";
when "01" & x"fc5" => data <= x"08";
when "01" & x"fc6" => data <= x"20";
when "01" & x"fc7" => data <= x"ca";
when "01" & x"fc8" => data <= x"80";
when "01" & x"fc9" => data <= x"38";
when "01" & x"fca" => data <= x"60";
when "01" & x"fcb" => data <= x"20";
when "01" & x"fcc" => data <= x"ce";
when "01" & x"fcd" => data <= x"9f";
when "01" & x"fce" => data <= x"48";
when "01" & x"fcf" => data <= x"a9";
when "01" & x"fd0" => data <= x"20";
when "01" & x"fd1" => data <= x"20";
when "01" & x"fd2" => data <= x"9c";
when "01" & x"fd3" => data <= x"80";
when "01" & x"fd4" => data <= x"68";
when "01" & x"fd5" => data <= x"18";
when "01" & x"fd6" => data <= x"60";
when "01" & x"fd7" => data <= x"ba";
when "01" & x"fd8" => data <= x"a9";
when "01" & x"fd9" => data <= x"00";
when "01" & x"fda" => data <= x"9d";
when "01" & x"fdb" => data <= x"07";
when "01" & x"fdc" => data <= x"01";
when "01" & x"fdd" => data <= x"88";
when "01" & x"fde" => data <= x"c8";
when "01" & x"fdf" => data <= x"b1";
when "01" & x"fe0" => data <= x"f2";
when "01" & x"fe1" => data <= x"c9";
when "01" & x"fe2" => data <= x"20";
when "01" & x"fe3" => data <= x"f0";
when "01" & x"fe4" => data <= x"f9";
when "01" & x"fe5" => data <= x"c9";
when "01" & x"fe6" => data <= x"0d";
when "01" & x"fe7" => data <= x"d0";
when "01" & x"fe8" => data <= x"03";
when "01" & x"fe9" => data <= x"4c";
when "01" & x"fea" => data <= x"06";
when "01" & x"feb" => data <= x"9a";
when "01" & x"fec" => data <= x"a9";
when "01" & x"fed" => data <= x"00";
when "01" & x"fee" => data <= x"85";
when "01" & x"fef" => data <= x"a8";
when "01" & x"ff0" => data <= x"85";
when "01" & x"ff1" => data <= x"a9";
when "01" & x"ff2" => data <= x"48";
when "01" & x"ff3" => data <= x"98";
when "01" & x"ff4" => data <= x"18";
when "01" & x"ff5" => data <= x"65";
when "01" & x"ff6" => data <= x"f2";
when "01" & x"ff7" => data <= x"aa";
when "01" & x"ff8" => data <= x"a5";
when "01" & x"ff9" => data <= x"f3";
when "01" & x"ffa" => data <= x"69";
when "01" & x"ffb" => data <= x"00";
when "01" & x"ffc" => data <= x"a8";
when "01" & x"ffd" => data <= x"68";
when "01" & x"ffe" => data <= x"60";
when "01" & x"fff" => data <= x"6d";
when "10" & x"000" => data <= x"20";
when "10" & x"001" => data <= x"80";
when "10" & x"002" => data <= x"a1";
when "10" & x"003" => data <= x"68";
when "10" & x"004" => data <= x"85";
when "10" & x"005" => data <= x"b8";
when "10" & x"006" => data <= x"68";
when "10" & x"007" => data <= x"85";
when "10" & x"008" => data <= x"b9";
when "10" & x"009" => data <= x"20";
when "10" & x"00a" => data <= x"0f";
when "10" & x"00b" => data <= x"a0";
when "10" & x"00c" => data <= x"4c";
when "10" & x"00d" => data <= x"00";
when "10" & x"00e" => data <= x"01";
when "10" & x"00f" => data <= x"a0";
when "10" & x"010" => data <= x"00";
when "10" & x"011" => data <= x"8c";
when "10" & x"012" => data <= x"00";
when "10" & x"013" => data <= x"01";
when "10" & x"014" => data <= x"c8";
when "10" & x"015" => data <= x"f0";
when "10" & x"016" => data <= x"07";
when "10" & x"017" => data <= x"b1";
when "10" & x"018" => data <= x"b8";
when "10" & x"019" => data <= x"99";
when "10" & x"01a" => data <= x"00";
when "10" & x"01b" => data <= x"01";
when "10" & x"01c" => data <= x"d0";
when "10" & x"01d" => data <= x"f6";
when "10" & x"01e" => data <= x"60";
when "10" & x"01f" => data <= x"a2";
when "10" & x"020" => data <= x"ff";
when "10" & x"021" => data <= x"d0";
when "10" & x"022" => data <= x"02";
when "10" & x"023" => data <= x"a2";
when "10" & x"024" => data <= x"00";
when "10" & x"025" => data <= x"a0";
when "10" & x"026" => data <= x"ff";
when "10" & x"027" => data <= x"8c";
when "10" & x"028" => data <= x"82";
when "10" & x"029" => data <= x"10";
when "10" & x"02a" => data <= x"85";
when "10" & x"02b" => data <= x"b0";
when "10" & x"02c" => data <= x"86";
when "10" & x"02d" => data <= x"b1";
when "10" & x"02e" => data <= x"8d";
when "10" & x"02f" => data <= x"02";
when "10" & x"030" => data <= x"0d";
when "10" & x"031" => data <= x"20";
when "10" & x"032" => data <= x"80";
when "10" & x"033" => data <= x"a1";
when "10" & x"034" => data <= x"68";
when "10" & x"035" => data <= x"85";
when "10" & x"036" => data <= x"b8";
when "10" & x"037" => data <= x"68";
when "10" & x"038" => data <= x"85";
when "10" & x"039" => data <= x"b9";
when "10" & x"03a" => data <= x"20";
when "10" & x"03b" => data <= x"0f";
when "10" & x"03c" => data <= x"a0";
when "10" & x"03d" => data <= x"a5";
when "10" & x"03e" => data <= x"b0";
when "10" & x"03f" => data <= x"20";
when "10" & x"040" => data <= x"69";
when "10" & x"041" => data <= x"a0";
when "10" & x"042" => data <= x"a5";
when "10" & x"043" => data <= x"b1";
when "10" & x"044" => data <= x"f0";
when "10" & x"045" => data <= x"1b";
when "10" & x"046" => data <= x"a9";
when "10" & x"047" => data <= x"2f";
when "10" & x"048" => data <= x"99";
when "10" & x"049" => data <= x"00";
when "10" & x"04a" => data <= x"01";
when "10" & x"04b" => data <= x"c8";
when "10" & x"04c" => data <= x"ae";
when "10" & x"04d" => data <= x"41";
when "10" & x"04e" => data <= x"0d";
when "10" & x"04f" => data <= x"bd";
when "10" & x"050" => data <= x"44";
when "10" & x"051" => data <= x"0d";
when "10" & x"052" => data <= x"20";
when "10" & x"053" => data <= x"69";
when "10" & x"054" => data <= x"a0";
when "10" & x"055" => data <= x"bd";
when "10" & x"056" => data <= x"45";
when "10" & x"057" => data <= x"0d";
when "10" & x"058" => data <= x"20";
when "10" & x"059" => data <= x"69";
when "10" & x"05a" => data <= x"a0";
when "10" & x"05b" => data <= x"bd";
when "10" & x"05c" => data <= x"46";
when "10" & x"05d" => data <= x"0d";
when "10" & x"05e" => data <= x"20";
when "10" & x"05f" => data <= x"69";
when "10" & x"060" => data <= x"a0";
when "10" & x"061" => data <= x"a9";
when "10" & x"062" => data <= x"00";
when "10" & x"063" => data <= x"99";
when "10" & x"064" => data <= x"00";
when "10" & x"065" => data <= x"01";
when "10" & x"066" => data <= x"4c";
when "10" & x"067" => data <= x"00";
when "10" & x"068" => data <= x"01";
when "10" & x"069" => data <= x"48";
when "10" & x"06a" => data <= x"4a";
when "10" & x"06b" => data <= x"4a";
when "10" & x"06c" => data <= x"4a";
when "10" & x"06d" => data <= x"4a";
when "10" & x"06e" => data <= x"20";
when "10" & x"06f" => data <= x"74";
when "10" & x"070" => data <= x"a0";
when "10" & x"071" => data <= x"68";
when "10" & x"072" => data <= x"29";
when "10" & x"073" => data <= x"0f";
when "10" & x"074" => data <= x"18";
when "10" & x"075" => data <= x"69";
when "10" & x"076" => data <= x"30";
when "10" & x"077" => data <= x"c9";
when "10" & x"078" => data <= x"3a";
when "10" & x"079" => data <= x"90";
when "10" & x"07a" => data <= x"02";
when "10" & x"07b" => data <= x"69";
when "10" & x"07c" => data <= x"06";
when "10" & x"07d" => data <= x"99";
when "10" & x"07e" => data <= x"00";
when "10" & x"07f" => data <= x"01";
when "10" & x"080" => data <= x"c8";
when "10" & x"081" => data <= x"60";
when "10" & x"082" => data <= x"20";
when "10" & x"083" => data <= x"00";
when "10" & x"084" => data <= x"a0";
when "10" & x"085" => data <= x"11";
when "10" & x"086" => data <= x"45";
when "10" & x"087" => data <= x"73";
when "10" & x"088" => data <= x"63";
when "10" & x"089" => data <= x"61";
when "10" & x"08a" => data <= x"70";
when "10" & x"08b" => data <= x"65";
when "10" & x"08c" => data <= x"00";
when "10" & x"08d" => data <= x"48";
when "10" & x"08e" => data <= x"a9";
when "10" & x"08f" => data <= x"ff";
when "10" & x"090" => data <= x"8d";
when "10" & x"091" => data <= x"74";
when "10" & x"092" => data <= x"10";
when "10" & x"093" => data <= x"8d";
when "10" & x"094" => data <= x"75";
when "10" & x"095" => data <= x"10";
when "10" & x"096" => data <= x"68";
when "10" & x"097" => data <= x"60";
when "10" & x"098" => data <= x"48";
when "10" & x"099" => data <= x"a5";
when "10" & x"09a" => data <= x"be";
when "10" & x"09b" => data <= x"8d";
when "10" & x"09c" => data <= x"72";
when "10" & x"09d" => data <= x"10";
when "10" & x"09e" => data <= x"a5";
when "10" & x"09f" => data <= x"bf";
when "10" & x"0a0" => data <= x"8d";
when "10" & x"0a1" => data <= x"73";
when "10" & x"0a2" => data <= x"10";
when "10" & x"0a3" => data <= x"ad";
when "10" & x"0a4" => data <= x"74";
when "10" & x"0a5" => data <= x"10";
when "10" & x"0a6" => data <= x"2d";
when "10" & x"0a7" => data <= x"75";
when "10" & x"0a8" => data <= x"10";
when "10" & x"0a9" => data <= x"0d";
when "10" & x"0aa" => data <= x"d7";
when "10" & x"0ab" => data <= x"10";
when "10" & x"0ac" => data <= x"49";
when "10" & x"0ad" => data <= x"ff";
when "10" & x"0ae" => data <= x"8d";
when "10" & x"0af" => data <= x"d6";
when "10" & x"0b0" => data <= x"10";
when "10" & x"0b1" => data <= x"38";
when "10" & x"0b2" => data <= x"f0";
when "10" & x"0b3" => data <= x"0d";
when "10" & x"0b4" => data <= x"20";
when "10" & x"0b5" => data <= x"c3";
when "10" & x"0b6" => data <= x"a0";
when "10" & x"0b7" => data <= x"a2";
when "10" & x"0b8" => data <= x"72";
when "10" & x"0b9" => data <= x"a0";
when "10" & x"0ba" => data <= x"10";
when "10" & x"0bb" => data <= x"68";
when "10" & x"0bc" => data <= x"48";
when "10" & x"0bd" => data <= x"20";
when "10" & x"0be" => data <= x"06";
when "10" & x"0bf" => data <= x"04";
when "10" & x"0c0" => data <= x"18";
when "10" & x"0c1" => data <= x"68";
when "10" & x"0c2" => data <= x"60";
when "10" & x"0c3" => data <= x"48";
when "10" & x"0c4" => data <= x"a9";
when "10" & x"0c5" => data <= x"c1";
when "10" & x"0c6" => data <= x"20";
when "10" & x"0c7" => data <= x"06";
when "10" & x"0c8" => data <= x"04";
when "10" & x"0c9" => data <= x"90";
when "10" & x"0ca" => data <= x"f9";
when "10" & x"0cb" => data <= x"68";
when "10" & x"0cc" => data <= x"60";
when "10" & x"0cd" => data <= x"ad";
when "10" & x"0ce" => data <= x"d6";
when "10" & x"0cf" => data <= x"10";
when "10" & x"0d0" => data <= x"f0";
when "10" & x"0d1" => data <= x"05";
when "10" & x"0d2" => data <= x"a9";
when "10" & x"0d3" => data <= x"81";
when "10" & x"0d4" => data <= x"20";
when "10" & x"0d5" => data <= x"06";
when "10" & x"0d6" => data <= x"04";
when "10" & x"0d7" => data <= x"60";
when "10" & x"0d8" => data <= x"9d";
when "10" & x"0d9" => data <= x"05";
when "10" & x"0da" => data <= x"01";
when "10" & x"0db" => data <= x"20";
when "10" & x"0dc" => data <= x"e4";
when "10" & x"0dd" => data <= x"95";
when "10" & x"0de" => data <= x"08";
when "10" & x"0df" => data <= x"ad";
when "10" & x"0e0" => data <= x"81";
when "10" & x"0e1" => data <= x"10";
when "10" & x"0e2" => data <= x"f0";
when "10" & x"0e3" => data <= x"05";
when "10" & x"0e4" => data <= x"a9";
when "10" & x"0e5" => data <= x"81";
when "10" & x"0e6" => data <= x"20";
when "10" & x"0e7" => data <= x"06";
when "10" & x"0e8" => data <= x"04";
when "10" & x"0e9" => data <= x"28";
when "10" & x"0ea" => data <= x"60";
when "10" & x"0eb" => data <= x"f0";
when "10" & x"0ec" => data <= x"06";
when "10" & x"0ed" => data <= x"20";
when "10" & x"0ee" => data <= x"c3";
when "10" & x"0ef" => data <= x"a0";
when "10" & x"0f0" => data <= x"18";
when "10" & x"0f1" => data <= x"a9";
when "10" & x"0f2" => data <= x"ff";
when "10" & x"0f3" => data <= x"4c";
when "10" & x"0f4" => data <= x"17";
when "10" & x"0f5" => data <= x"96";
when "10" & x"0f6" => data <= x"c9";
when "10" & x"0f7" => data <= x"fe";
when "10" & x"0f8" => data <= x"90";
when "10" & x"0f9" => data <= x"5a";
when "10" & x"0fa" => data <= x"d0";
when "10" & x"0fb" => data <= x"1b";
when "10" & x"0fc" => data <= x"c0";
when "10" & x"0fd" => data <= x"00";
when "10" & x"0fe" => data <= x"f0";
when "10" & x"0ff" => data <= x"54";
when "10" & x"100" => data <= x"a2";
when "10" & x"101" => data <= x"06";
when "10" & x"102" => data <= x"a9";
when "10" & x"103" => data <= x"14";
when "10" & x"104" => data <= x"20";
when "10" & x"105" => data <= x"f4";
when "10" & x"106" => data <= x"ff";
when "10" & x"107" => data <= x"2c";
when "10" & x"108" => data <= x"e0";
when "10" & x"109" => data <= x"fe";
when "10" & x"10a" => data <= x"10";
when "10" & x"10b" => data <= x"fb";
when "10" & x"10c" => data <= x"ad";
when "10" & x"10d" => data <= x"e1";
when "10" & x"10e" => data <= x"fe";
when "10" & x"10f" => data <= x"f0";
when "10" & x"110" => data <= x"41";
when "10" & x"111" => data <= x"20";
when "10" & x"112" => data <= x"ee";
when "10" & x"113" => data <= x"ff";
when "10" & x"114" => data <= x"4c";
when "10" & x"115" => data <= x"07";
when "10" & x"116" => data <= x"a1";
when "10" & x"117" => data <= x"a9";
when "10" & x"118" => data <= x"ad";
when "10" & x"119" => data <= x"8d";
when "10" & x"11a" => data <= x"20";
when "10" & x"11b" => data <= x"02";
when "10" & x"11c" => data <= x"a9";
when "10" & x"11d" => data <= x"06";
when "10" & x"11e" => data <= x"8d";
when "10" & x"11f" => data <= x"21";
when "10" & x"120" => data <= x"02";
when "10" & x"121" => data <= x"a9";
when "10" & x"122" => data <= x"16";
when "10" & x"123" => data <= x"8d";
when "10" & x"124" => data <= x"02";
when "10" & x"125" => data <= x"02";
when "10" & x"126" => data <= x"a0";
when "10" & x"127" => data <= x"00";
when "10" & x"128" => data <= x"8c";
when "10" & x"129" => data <= x"03";
when "10" & x"12a" => data <= x"02";
when "10" & x"12b" => data <= x"a9";
when "10" & x"12c" => data <= x"8e";
when "10" & x"12d" => data <= x"8d";
when "10" & x"12e" => data <= x"e0";
when "10" & x"12f" => data <= x"fe";
when "10" & x"130" => data <= x"b9";
when "10" & x"131" => data <= x"03";
when "10" & x"132" => data <= x"8b";
when "10" & x"133" => data <= x"99";
when "10" & x"134" => data <= x"00";
when "10" & x"135" => data <= x"04";
when "10" & x"136" => data <= x"b9";
when "10" & x"137" => data <= x"03";
when "10" & x"138" => data <= x"8c";
when "10" & x"139" => data <= x"99";
when "10" & x"13a" => data <= x"00";
when "10" & x"13b" => data <= x"05";
when "10" & x"13c" => data <= x"b9";
when "10" & x"13d" => data <= x"03";
when "10" & x"13e" => data <= x"8d";
when "10" & x"13f" => data <= x"99";
when "10" & x"140" => data <= x"00";
when "10" & x"141" => data <= x"06";
when "10" & x"142" => data <= x"88";
when "10" & x"143" => data <= x"d0";
when "10" & x"144" => data <= x"eb";
when "10" & x"145" => data <= x"20";
when "10" & x"146" => data <= x"21";
when "10" & x"147" => data <= x"04";
when "10" & x"148" => data <= x"a2";
when "10" & x"149" => data <= x"40";
when "10" & x"14a" => data <= x"bd";
when "10" & x"14b" => data <= x"c2";
when "10" & x"14c" => data <= x"8a";
when "10" & x"14d" => data <= x"95";
when "10" & x"14e" => data <= x"16";
when "10" & x"14f" => data <= x"ca";
when "10" & x"150" => data <= x"10";
when "10" & x"151" => data <= x"f8";
when "10" & x"152" => data <= x"a9";
when "10" & x"153" => data <= x"00";
when "10" & x"154" => data <= x"60";
when "10" & x"155" => data <= x"a9";
when "10" & x"156" => data <= x"00";
when "10" & x"157" => data <= x"8d";
when "10" & x"158" => data <= x"04";
when "10" & x"159" => data <= x"0d";
when "10" & x"15a" => data <= x"a9";
when "10" & x"15b" => data <= x"ff";
when "10" & x"15c" => data <= x"8d";
when "10" & x"15d" => data <= x"52";
when "10" & x"15e" => data <= x"0d";
when "10" & x"15f" => data <= x"48";
when "10" & x"160" => data <= x"4c";
when "10" & x"161" => data <= x"3b";
when "10" & x"162" => data <= x"93";
when "10" & x"163" => data <= x"b9";
when "10" & x"164" => data <= x"14";
when "10" & x"165" => data <= x"11";
when "10" & x"166" => data <= x"99";
when "10" & x"167" => data <= x"10";
when "10" & x"168" => data <= x"11";
when "10" & x"169" => data <= x"b9";
when "10" & x"16a" => data <= x"15";
when "10" & x"16b" => data <= x"11";
when "10" & x"16c" => data <= x"99";
when "10" & x"16d" => data <= x"11";
when "10" & x"16e" => data <= x"11";
when "10" & x"16f" => data <= x"b9";
when "10" & x"170" => data <= x"16";
when "10" & x"171" => data <= x"11";
when "10" & x"172" => data <= x"99";
when "10" & x"173" => data <= x"12";
when "10" & x"174" => data <= x"11";
when "10" & x"175" => data <= x"60";
when "10" & x"176" => data <= x"60";
when "10" & x"177" => data <= x"a2";
when "10" & x"178" => data <= x"06";
when "10" & x"179" => data <= x"8e";
when "10" & x"17a" => data <= x"40";
when "10" & x"17b" => data <= x"fe";
when "10" & x"17c" => data <= x"e8";
when "10" & x"17d" => data <= x"8e";
when "10" & x"17e" => data <= x"40";
when "10" & x"17f" => data <= x"fe";
when "10" & x"180" => data <= x"60";
when "10" & x"181" => data <= x"a9";
when "10" & x"182" => data <= x"76";
when "10" & x"183" => data <= x"ea";
when "10" & x"184" => data <= x"ea";
when "10" & x"185" => data <= x"ea";
when "10" & x"186" => data <= x"ea";
when "10" & x"187" => data <= x"ea";
when "10" & x"188" => data <= x"ea";
when "10" & x"189" => data <= x"60";
when "10" & x"18a" => data <= x"48";
when "10" & x"18b" => data <= x"68";
when "10" & x"18c" => data <= x"20";
when "10" & x"18d" => data <= x"85";
when "10" & x"18e" => data <= x"a1";
when "10" & x"18f" => data <= x"60";
when "10" & x"190" => data <= x"ad";
when "10" & x"191" => data <= x"bb";
when "10" & x"192" => data <= x"fc";
when "10" & x"193" => data <= x"8d";
when "10" & x"194" => data <= x"3a";
when "10" & x"195" => data <= x"0d";
when "10" & x"196" => data <= x"ad";
when "10" & x"197" => data <= x"b2";
when "10" & x"198" => data <= x"fc";
when "10" & x"199" => data <= x"8d";
when "10" & x"19a" => data <= x"3b";
when "10" & x"19b" => data <= x"0d";
when "10" & x"19c" => data <= x"60";
when "10" & x"19d" => data <= x"a9";
when "10" & x"19e" => data <= x"08";
when "10" & x"19f" => data <= x"8d";
when "10" & x"1a0" => data <= x"bb";
when "10" & x"1a1" => data <= x"fc";
when "10" & x"1a2" => data <= x"ad";
when "10" & x"1a3" => data <= x"b2";
when "10" & x"1a4" => data <= x"fc";
when "10" & x"1a5" => data <= x"4d";
when "10" & x"1a6" => data <= x"4c";
when "10" & x"1a7" => data <= x"0d";
when "10" & x"1a8" => data <= x"0d";
when "10" & x"1a9" => data <= x"4b";
when "10" & x"1aa" => data <= x"0d";
when "10" & x"1ab" => data <= x"8d";
when "10" & x"1ac" => data <= x"b2";
when "10" & x"1ad" => data <= x"fc";
when "10" & x"1ae" => data <= x"ad";
when "10" & x"1af" => data <= x"4b";
when "10" & x"1b0" => data <= x"0d";
when "10" & x"1b1" => data <= x"0d";
when "10" & x"1b2" => data <= x"3f";
when "10" & x"1b3" => data <= x"0d";
when "10" & x"1b4" => data <= x"0d";
when "10" & x"1b5" => data <= x"51";
when "10" & x"1b6" => data <= x"0d";
when "10" & x"1b7" => data <= x"8d";
when "10" & x"1b8" => data <= x"b0";
when "10" & x"1b9" => data <= x"fc";
when "10" & x"1ba" => data <= x"ad";
when "10" & x"1bb" => data <= x"ba";
when "10" & x"1bc" => data <= x"fc";
when "10" & x"1bd" => data <= x"60";
when "10" & x"1be" => data <= x"ad";
when "10" & x"1bf" => data <= x"bd";
when "10" & x"1c0" => data <= x"fc";
when "10" & x"1c1" => data <= x"29";
when "10" & x"1c2" => data <= x"04";
when "10" & x"1c3" => data <= x"f0";
when "10" & x"1c4" => data <= x"f9";
when "10" & x"1c5" => data <= x"60";
when "10" & x"1c6" => data <= x"ad";
when "10" & x"1c7" => data <= x"4c";
when "10" & x"1c8" => data <= x"0d";
when "10" & x"1c9" => data <= x"0d";
when "10" & x"1ca" => data <= x"3f";
when "10" & x"1cb" => data <= x"0d";
when "10" & x"1cc" => data <= x"0d";
when "10" & x"1cd" => data <= x"51";
when "10" & x"1ce" => data <= x"0d";
when "10" & x"1cf" => data <= x"8d";
when "10" & x"1d0" => data <= x"b0";
when "10" & x"1d1" => data <= x"fc";
when "10" & x"1d2" => data <= x"ad";
when "10" & x"1d3" => data <= x"3b";
when "10" & x"1d4" => data <= x"0d";
when "10" & x"1d5" => data <= x"8d";
when "10" & x"1d6" => data <= x"b2";
when "10" & x"1d7" => data <= x"fc";
when "10" & x"1d8" => data <= x"ad";
when "10" & x"1d9" => data <= x"3a";
when "10" & x"1da" => data <= x"0d";
when "10" & x"1db" => data <= x"8d";
when "10" & x"1dc" => data <= x"bb";
when "10" & x"1dd" => data <= x"fc";
when "10" & x"1de" => data <= x"ad";
when "10" & x"1df" => data <= x"ba";
when "10" & x"1e0" => data <= x"fc";
when "10" & x"1e1" => data <= x"60";
when "10" & x"1e2" => data <= x"20";
when "10" & x"1e3" => data <= x"90";
when "10" & x"1e4" => data <= x"a1";
when "10" & x"1e5" => data <= x"20";
when "10" & x"1e6" => data <= x"9d";
when "10" & x"1e7" => data <= x"a1";
when "10" & x"1e8" => data <= x"20";
when "10" & x"1e9" => data <= x"be";
when "10" & x"1ea" => data <= x"a1";
when "10" & x"1eb" => data <= x"20";
when "10" & x"1ec" => data <= x"c6";
when "10" & x"1ed" => data <= x"a1";
when "10" & x"1ee" => data <= x"60";
when "10" & x"1ef" => data <= x"20";
when "10" & x"1f0" => data <= x"90";
when "10" & x"1f1" => data <= x"a1";
when "10" & x"1f2" => data <= x"20";
when "10" & x"1f3" => data <= x"9d";
when "10" & x"1f4" => data <= x"a1";
when "10" & x"1f5" => data <= x"c0";
when "10" & x"1f6" => data <= x"ff";
when "10" & x"1f7" => data <= x"f0";
when "10" & x"1f8" => data <= x"0b";
when "10" & x"1f9" => data <= x"20";
when "10" & x"1fa" => data <= x"be";
when "10" & x"1fb" => data <= x"a1";
when "10" & x"1fc" => data <= x"ad";
when "10" & x"1fd" => data <= x"ba";
when "10" & x"1fe" => data <= x"fc";
when "10" & x"1ff" => data <= x"91";
when "10" & x"200" => data <= x"a0";
when "10" & x"201" => data <= x"c8";
when "10" & x"202" => data <= x"d0";
when "10" & x"203" => data <= x"f1";
when "10" & x"204" => data <= x"20";
when "10" & x"205" => data <= x"be";
when "10" & x"206" => data <= x"a1";
when "10" & x"207" => data <= x"20";
when "10" & x"208" => data <= x"c6";
when "10" & x"209" => data <= x"a1";
when "10" & x"20a" => data <= x"91";
when "10" & x"20b" => data <= x"a0";
when "10" & x"20c" => data <= x"e8";
when "10" & x"20d" => data <= x"c8";
when "10" & x"20e" => data <= x"60";
when "10" & x"20f" => data <= x"ad";
when "10" & x"210" => data <= x"4b";
when "10" & x"211" => data <= x"0d";
when "10" & x"212" => data <= x"0d";
when "10" & x"213" => data <= x"3f";
when "10" & x"214" => data <= x"0d";
when "10" & x"215" => data <= x"0d";
when "10" & x"216" => data <= x"51";
when "10" & x"217" => data <= x"0d";
when "10" & x"218" => data <= x"aa";
when "10" & x"219" => data <= x"ad";
when "10" & x"21a" => data <= x"4c";
when "10" & x"21b" => data <= x"0d";
when "10" & x"21c" => data <= x"0d";
when "10" & x"21d" => data <= x"3f";
when "10" & x"21e" => data <= x"0d";
when "10" & x"21f" => data <= x"0d";
when "10" & x"220" => data <= x"51";
when "10" & x"221" => data <= x"0d";
when "10" & x"222" => data <= x"8e";
when "10" & x"223" => data <= x"b0";
when "10" & x"224" => data <= x"fc";
when "10" & x"225" => data <= x"8d";
when "10" & x"226" => data <= x"b0";
when "10" & x"227" => data <= x"fc";
when "10" & x"228" => data <= x"8e";
when "10" & x"229" => data <= x"b0";
when "10" & x"22a" => data <= x"fc";
when "10" & x"22b" => data <= x"8d";
when "10" & x"22c" => data <= x"b0";
when "10" & x"22d" => data <= x"fc";
when "10" & x"22e" => data <= x"8e";
when "10" & x"22f" => data <= x"b0";
when "10" & x"230" => data <= x"fc";
when "10" & x"231" => data <= x"8d";
when "10" & x"232" => data <= x"b0";
when "10" & x"233" => data <= x"fc";
when "10" & x"234" => data <= x"8e";
when "10" & x"235" => data <= x"b0";
when "10" & x"236" => data <= x"fc";
when "10" & x"237" => data <= x"8d";
when "10" & x"238" => data <= x"b0";
when "10" & x"239" => data <= x"fc";
when "10" & x"23a" => data <= x"8e";
when "10" & x"23b" => data <= x"b0";
when "10" & x"23c" => data <= x"fc";
when "10" & x"23d" => data <= x"8d";
when "10" & x"23e" => data <= x"b0";
when "10" & x"23f" => data <= x"fc";
when "10" & x"240" => data <= x"8e";
when "10" & x"241" => data <= x"b0";
when "10" & x"242" => data <= x"fc";
when "10" & x"243" => data <= x"8d";
when "10" & x"244" => data <= x"b0";
when "10" & x"245" => data <= x"fc";
when "10" & x"246" => data <= x"8e";
when "10" & x"247" => data <= x"b0";
when "10" & x"248" => data <= x"fc";
when "10" & x"249" => data <= x"8d";
when "10" & x"24a" => data <= x"b0";
when "10" & x"24b" => data <= x"fc";
when "10" & x"24c" => data <= x"8e";
when "10" & x"24d" => data <= x"b0";
when "10" & x"24e" => data <= x"fc";
when "10" & x"24f" => data <= x"8d";
when "10" & x"250" => data <= x"b0";
when "10" & x"251" => data <= x"fc";
when "10" & x"252" => data <= x"ad";
when "10" & x"253" => data <= x"ba";
when "10" & x"254" => data <= x"fc";
when "10" & x"255" => data <= x"60";
when "10" & x"256" => data <= x"a9";
when "10" & x"257" => data <= x"18";
when "10" & x"258" => data <= x"8d";
when "10" & x"259" => data <= x"bb";
when "10" & x"25a" => data <= x"fc";
when "10" & x"25b" => data <= x"a9";
when "10" & x"25c" => data <= x"1d";
when "10" & x"25d" => data <= x"8d";
when "10" & x"25e" => data <= x"b2";
when "10" & x"25f" => data <= x"fc";
when "10" & x"260" => data <= x"a9";
when "10" & x"261" => data <= x"14";
when "10" & x"262" => data <= x"8d";
when "10" & x"263" => data <= x"b0";
when "10" & x"264" => data <= x"fc";
when "10" & x"265" => data <= x"60";
when "10" & x"266" => data <= x"20";
when "10" & x"267" => data <= x"90";
when "10" & x"268" => data <= x"a1";
when "10" & x"269" => data <= x"20";
when "10" & x"26a" => data <= x"56";
when "10" & x"26b" => data <= x"a2";
when "10" & x"26c" => data <= x"68";
when "10" & x"26d" => data <= x"8d";
when "10" & x"26e" => data <= x"ba";
when "10" & x"26f" => data <= x"fc";
when "10" & x"270" => data <= x"20";
when "10" & x"271" => data <= x"be";
when "10" & x"272" => data <= x"a1";
when "10" & x"273" => data <= x"20";
when "10" & x"274" => data <= x"8a";
when "10" & x"275" => data <= x"a1";
when "10" & x"276" => data <= x"4c";
when "10" & x"277" => data <= x"c6";
when "10" & x"278" => data <= x"a1";
when "10" & x"279" => data <= x"20";
when "10" & x"27a" => data <= x"90";
when "10" & x"27b" => data <= x"a1";
when "10" & x"27c" => data <= x"20";
when "10" & x"27d" => data <= x"56";
when "10" & x"27e" => data <= x"a2";
when "10" & x"27f" => data <= x"b1";
when "10" & x"280" => data <= x"a0";
when "10" & x"281" => data <= x"8d";
when "10" & x"282" => data <= x"ba";
when "10" & x"283" => data <= x"fc";
when "10" & x"284" => data <= x"20";
when "10" & x"285" => data <= x"be";
when "10" & x"286" => data <= x"a1";
when "10" & x"287" => data <= x"c8";
when "10" & x"288" => data <= x"d0";
when "10" & x"289" => data <= x"f5";
when "10" & x"28a" => data <= x"4c";
when "10" & x"28b" => data <= x"c6";
when "10" & x"28c" => data <= x"a1";
when "10" & x"28d" => data <= x"ad";
when "10" & x"28e" => data <= x"3f";
when "10" & x"28f" => data <= x"0d";
when "10" & x"290" => data <= x"d0";
when "10" & x"291" => data <= x"e7";
when "10" & x"292" => data <= x"b1";
when "10" & x"293" => data <= x"a0";
when "10" & x"294" => data <= x"20";
when "10" & x"295" => data <= x"9b";
when "10" & x"296" => data <= x"a2";
when "10" & x"297" => data <= x"c8";
when "10" & x"298" => data <= x"d0";
when "10" & x"299" => data <= x"f8";
when "10" & x"29a" => data <= x"60";
when "10" & x"29b" => data <= x"86";
when "10" & x"29c" => data <= x"b0";
when "10" & x"29d" => data <= x"ae";
when "10" & x"29e" => data <= x"4a";
when "10" & x"29f" => data <= x"0d";
when "10" & x"2a0" => data <= x"18";
when "10" & x"2a1" => data <= x"2a";
when "10" & x"2a2" => data <= x"2a";
when "10" & x"2a3" => data <= x"ca";
when "10" & x"2a4" => data <= x"d0";
when "10" & x"2a5" => data <= x"fb";
when "10" & x"2a6" => data <= x"48";
when "10" & x"2a7" => data <= x"2d";
when "10" & x"2a8" => data <= x"4c";
when "10" & x"2a9" => data <= x"0d";
when "10" & x"2aa" => data <= x"0d";
when "10" & x"2ab" => data <= x"3f";
when "10" & x"2ac" => data <= x"0d";
when "10" & x"2ad" => data <= x"0d";
when "10" & x"2ae" => data <= x"51";
when "10" & x"2af" => data <= x"0d";
when "10" & x"2b0" => data <= x"8d";
when "10" & x"2b1" => data <= x"b0";
when "10" & x"2b2" => data <= x"fc";
when "10" & x"2b3" => data <= x"0d";
when "10" & x"2b4" => data <= x"4e";
when "10" & x"2b5" => data <= x"0d";
when "10" & x"2b6" => data <= x"8d";
when "10" & x"2b7" => data <= x"b0";
when "10" & x"2b8" => data <= x"fc";
when "10" & x"2b9" => data <= x"68";
when "10" & x"2ba" => data <= x"a2";
when "10" & x"2bb" => data <= x"07";
when "10" & x"2bc" => data <= x"2a";
when "10" & x"2bd" => data <= x"48";
when "10" & x"2be" => data <= x"2d";
when "10" & x"2bf" => data <= x"4c";
when "10" & x"2c0" => data <= x"0d";
when "10" & x"2c1" => data <= x"0d";
when "10" & x"2c2" => data <= x"3f";
when "10" & x"2c3" => data <= x"0d";
when "10" & x"2c4" => data <= x"0d";
when "10" & x"2c5" => data <= x"51";
when "10" & x"2c6" => data <= x"0d";
when "10" & x"2c7" => data <= x"2d";
when "10" & x"2c8" => data <= x"4d";
when "10" & x"2c9" => data <= x"0d";
when "10" & x"2ca" => data <= x"8d";
when "10" & x"2cb" => data <= x"b0";
when "10" & x"2cc" => data <= x"fc";
when "10" & x"2cd" => data <= x"0d";
when "10" & x"2ce" => data <= x"4e";
when "10" & x"2cf" => data <= x"0d";
when "10" & x"2d0" => data <= x"8d";
when "10" & x"2d1" => data <= x"b0";
when "10" & x"2d2" => data <= x"fc";
when "10" & x"2d3" => data <= x"68";
when "10" & x"2d4" => data <= x"ca";
when "10" & x"2d5" => data <= x"d0";
when "10" & x"2d6" => data <= x"e5";
when "10" & x"2d7" => data <= x"a6";
when "10" & x"2d8" => data <= x"b0";
when "10" & x"2d9" => data <= x"60";
when "10" & x"2da" => data <= x"2c";
when "10" & x"2db" => data <= x"40";
when "10" & x"2dc" => data <= x"0d";
when "10" & x"2dd" => data <= x"30";
when "10" & x"2de" => data <= x"47";
when "10" & x"2df" => data <= x"ad";
when "10" & x"2e0" => data <= x"4b";
when "10" & x"2e1" => data <= x"0d";
when "10" & x"2e2" => data <= x"0d";
when "10" & x"2e3" => data <= x"3f";
when "10" & x"2e4" => data <= x"0d";
when "10" & x"2e5" => data <= x"0d";
when "10" & x"2e6" => data <= x"51";
when "10" & x"2e7" => data <= x"0d";
when "10" & x"2e8" => data <= x"aa";
when "10" & x"2e9" => data <= x"ad";
when "10" & x"2ea" => data <= x"4c";
when "10" & x"2eb" => data <= x"0d";
when "10" & x"2ec" => data <= x"0d";
when "10" & x"2ed" => data <= x"3f";
when "10" & x"2ee" => data <= x"0d";
when "10" & x"2ef" => data <= x"0d";
when "10" & x"2f0" => data <= x"51";
when "10" & x"2f1" => data <= x"0d";
when "10" & x"2f2" => data <= x"8e";
when "10" & x"2f3" => data <= x"b0";
when "10" & x"2f4" => data <= x"fc";
when "10" & x"2f5" => data <= x"8d";
when "10" & x"2f6" => data <= x"b0";
when "10" & x"2f7" => data <= x"fc";
when "10" & x"2f8" => data <= x"8e";
when "10" & x"2f9" => data <= x"b0";
when "10" & x"2fa" => data <= x"fc";
when "10" & x"2fb" => data <= x"8d";
when "10" & x"2fc" => data <= x"b0";
when "10" & x"2fd" => data <= x"fc";
when "10" & x"2fe" => data <= x"8e";
when "10" & x"2ff" => data <= x"b0";
when "10" & x"300" => data <= x"fc";
when "10" & x"301" => data <= x"8d";
when "10" & x"302" => data <= x"b0";
when "10" & x"303" => data <= x"fc";
when "10" & x"304" => data <= x"8e";
when "10" & x"305" => data <= x"b0";
when "10" & x"306" => data <= x"fc";
when "10" & x"307" => data <= x"8d";
when "10" & x"308" => data <= x"b0";
when "10" & x"309" => data <= x"fc";
when "10" & x"30a" => data <= x"8e";
when "10" & x"30b" => data <= x"b0";
when "10" & x"30c" => data <= x"fc";
when "10" & x"30d" => data <= x"8d";
when "10" & x"30e" => data <= x"b0";
when "10" & x"30f" => data <= x"fc";
when "10" & x"310" => data <= x"8e";
when "10" & x"311" => data <= x"b0";
when "10" & x"312" => data <= x"fc";
when "10" & x"313" => data <= x"8d";
when "10" & x"314" => data <= x"b0";
when "10" & x"315" => data <= x"fc";
when "10" & x"316" => data <= x"8e";
when "10" & x"317" => data <= x"b0";
when "10" & x"318" => data <= x"fc";
when "10" & x"319" => data <= x"8d";
when "10" & x"31a" => data <= x"b0";
when "10" & x"31b" => data <= x"fc";
when "10" & x"31c" => data <= x"8e";
when "10" & x"31d" => data <= x"b0";
when "10" & x"31e" => data <= x"fc";
when "10" & x"31f" => data <= x"8d";
when "10" & x"320" => data <= x"b0";
when "10" & x"321" => data <= x"fc";
when "10" & x"322" => data <= x"88";
when "10" & x"323" => data <= x"d0";
when "10" & x"324" => data <= x"cd";
when "10" & x"325" => data <= x"60";
when "10" & x"326" => data <= x"a9";
when "10" & x"327" => data <= x"ff";
when "10" & x"328" => data <= x"8d";
when "10" & x"329" => data <= x"28";
when "10" & x"32a" => data <= x"fc";
when "10" & x"32b" => data <= x"ea";
when "10" & x"32c" => data <= x"ea";
when "10" & x"32d" => data <= x"ea";
when "10" & x"32e" => data <= x"88";
when "10" & x"32f" => data <= x"d0";
when "10" & x"330" => data <= x"f7";
when "10" & x"331" => data <= x"60";
when "10" & x"332" => data <= x"a2";
when "10" & x"333" => data <= x"00";
when "10" & x"334" => data <= x"2c";
when "10" & x"335" => data <= x"40";
when "10" & x"336" => data <= x"0d";
when "10" & x"337" => data <= x"30";
when "10" & x"338" => data <= x"46";
when "10" & x"339" => data <= x"8e";
when "10" & x"33a" => data <= x"41";
when "10" & x"33b" => data <= x"0d";
when "10" & x"33c" => data <= x"a0";
when "10" & x"33d" => data <= x"07";
when "10" & x"33e" => data <= x"bd";
when "10" & x"33f" => data <= x"42";
when "10" & x"340" => data <= x"0d";
when "10" & x"341" => data <= x"20";
when "10" & x"342" => data <= x"9b";
when "10" & x"343" => data <= x"a2";
when "10" & x"344" => data <= x"e8";
when "10" & x"345" => data <= x"88";
when "10" & x"346" => data <= x"d0";
when "10" & x"347" => data <= x"f6";
when "10" & x"348" => data <= x"20";
when "10" & x"349" => data <= x"4e";
when "10" & x"34a" => data <= x"a3";
when "10" & x"34b" => data <= x"4c";
when "10" & x"34c" => data <= x"28";
when "10" & x"34d" => data <= x"a2";
when "10" & x"34e" => data <= x"a0";
when "10" & x"34f" => data <= x"00";
when "10" & x"350" => data <= x"84";
when "10" & x"351" => data <= x"b0";
when "10" & x"352" => data <= x"ad";
when "10" & x"353" => data <= x"4b";
when "10" & x"354" => data <= x"0d";
when "10" & x"355" => data <= x"0d";
when "10" & x"356" => data <= x"3f";
when "10" & x"357" => data <= x"0d";
when "10" & x"358" => data <= x"0d";
when "10" & x"359" => data <= x"51";
when "10" & x"35a" => data <= x"0d";
when "10" & x"35b" => data <= x"aa";
when "10" & x"35c" => data <= x"ad";
when "10" & x"35d" => data <= x"4c";
when "10" & x"35e" => data <= x"0d";
when "10" & x"35f" => data <= x"0d";
when "10" & x"360" => data <= x"3f";
when "10" & x"361" => data <= x"0d";
when "10" & x"362" => data <= x"0d";
when "10" & x"363" => data <= x"51";
when "10" & x"364" => data <= x"0d";
when "10" & x"365" => data <= x"a8";
when "10" & x"366" => data <= x"c6";
when "10" & x"367" => data <= x"b0";
when "10" & x"368" => data <= x"f0";
when "10" & x"369" => data <= x"0f";
when "10" & x"36a" => data <= x"8e";
when "10" & x"36b" => data <= x"b0";
when "10" & x"36c" => data <= x"fc";
when "10" & x"36d" => data <= x"8c";
when "10" & x"36e" => data <= x"b0";
when "10" & x"36f" => data <= x"fc";
when "10" & x"370" => data <= x"ad";
when "10" & x"371" => data <= x"ba";
when "10" & x"372" => data <= x"fc";
when "10" & x"373" => data <= x"29";
when "10" & x"374" => data <= x"01";
when "10" & x"375" => data <= x"d0";
when "10" & x"376" => data <= x"ef";
when "10" & x"377" => data <= x"98";
when "10" & x"378" => data <= x"60";
when "10" & x"379" => data <= x"ad";
when "10" & x"37a" => data <= x"ba";
when "10" & x"37b" => data <= x"fc";
when "10" & x"37c" => data <= x"c9";
when "10" & x"37d" => data <= x"00";
when "10" & x"37e" => data <= x"60";
when "10" & x"37f" => data <= x"8e";
when "10" & x"380" => data <= x"41";
when "10" & x"381" => data <= x"0d";
when "10" & x"382" => data <= x"a0";
when "10" & x"383" => data <= x"08";
when "10" & x"384" => data <= x"bd";
when "10" & x"385" => data <= x"42";
when "10" & x"386" => data <= x"0d";
when "10" & x"387" => data <= x"8d";
when "10" & x"388" => data <= x"28";
when "10" & x"389" => data <= x"fc";
when "10" & x"38a" => data <= x"ea";
when "10" & x"38b" => data <= x"ea";
when "10" & x"38c" => data <= x"e8";
when "10" & x"38d" => data <= x"88";
when "10" & x"38e" => data <= x"d0";
when "10" & x"38f" => data <= x"f4";
when "10" & x"390" => data <= x"8d";
when "10" & x"391" => data <= x"28";
when "10" & x"392" => data <= x"fc";
when "10" & x"393" => data <= x"20";
when "10" & x"394" => data <= x"31";
when "10" & x"395" => data <= x"a3";
when "10" & x"396" => data <= x"ad";
when "10" & x"397" => data <= x"28";
when "10" & x"398" => data <= x"fc";
when "10" & x"399" => data <= x"10";
when "10" & x"39a" => data <= x"e3";
when "10" & x"39b" => data <= x"88";
when "10" & x"39c" => data <= x"d0";
when "10" & x"39d" => data <= x"f5";
when "10" & x"39e" => data <= x"4c";
when "10" & x"39f" => data <= x"7c";
when "10" & x"3a0" => data <= x"a3";
when "10" & x"3a1" => data <= x"2c";
when "10" & x"3a2" => data <= x"40";
when "10" & x"3a3" => data <= x"0d";
when "10" & x"3a4" => data <= x"30";
when "10" & x"3a5" => data <= x"08";
when "10" & x"3a6" => data <= x"20";
when "10" & x"3a7" => data <= x"e2";
when "10" & x"3a8" => data <= x"a1";
when "10" & x"3a9" => data <= x"c9";
when "10" & x"3aa" => data <= x"fe";
when "10" & x"3ab" => data <= x"d0";
when "10" & x"3ac" => data <= x"f9";
when "10" & x"3ad" => data <= x"60";
when "10" & x"3ae" => data <= x"a2";
when "10" & x"3af" => data <= x"ff";
when "10" & x"3b0" => data <= x"8e";
when "10" & x"3b1" => data <= x"28";
when "10" & x"3b2" => data <= x"fc";
when "10" & x"3b3" => data <= x"20";
when "10" & x"3b4" => data <= x"31";
when "10" & x"3b5" => data <= x"a3";
when "10" & x"3b6" => data <= x"ad";
when "10" & x"3b7" => data <= x"28";
when "10" & x"3b8" => data <= x"fc";
when "10" & x"3b9" => data <= x"c9";
when "10" & x"3ba" => data <= x"fe";
when "10" & x"3bb" => data <= x"d0";
when "10" & x"3bc" => data <= x"f3";
when "10" & x"3bd" => data <= x"60";
when "10" & x"3be" => data <= x"2c";
when "10" & x"3bf" => data <= x"40";
when "10" & x"3c0" => data <= x"0d";
when "10" & x"3c1" => data <= x"30";
when "10" & x"3c2" => data <= x"0d";
when "10" & x"3c3" => data <= x"ac";
when "10" & x"3c4" => data <= x"d6";
when "10" & x"3c5" => data <= x"10";
when "10" & x"3c6" => data <= x"d0";
when "10" & x"3c7" => data <= x"03";
when "10" & x"3c8" => data <= x"4c";
when "10" & x"3c9" => data <= x"ef";
when "10" & x"3ca" => data <= x"a1";
when "10" & x"3cb" => data <= x"a0";
when "10" & x"3cc" => data <= x"00";
when "10" & x"3cd" => data <= x"4c";
when "10" & x"3ce" => data <= x"0e";
when "10" & x"3cf" => data <= x"a4";
when "10" & x"3d0" => data <= x"a2";
when "10" & x"3d1" => data <= x"ff";
when "10" & x"3d2" => data <= x"8e";
when "10" & x"3d3" => data <= x"28";
when "10" & x"3d4" => data <= x"fc";
when "10" & x"3d5" => data <= x"ac";
when "10" & x"3d6" => data <= x"d6";
when "10" & x"3d7" => data <= x"10";
when "10" & x"3d8" => data <= x"d0";
when "10" & x"3d9" => data <= x"16";
when "10" & x"3da" => data <= x"ea";
when "10" & x"3db" => data <= x"ea";
when "10" & x"3dc" => data <= x"ea";
when "10" & x"3dd" => data <= x"ad";
when "10" & x"3de" => data <= x"28";
when "10" & x"3df" => data <= x"fc";
when "10" & x"3e0" => data <= x"8e";
when "10" & x"3e1" => data <= x"28";
when "10" & x"3e2" => data <= x"fc";
when "10" & x"3e3" => data <= x"91";
when "10" & x"3e4" => data <= x"a0";
when "10" & x"3e5" => data <= x"c8";
when "10" & x"3e6" => data <= x"c0";
when "10" & x"3e7" => data <= x"ff";
when "10" & x"3e8" => data <= x"d0";
when "10" & x"3e9" => data <= x"f3";
when "10" & x"3ea" => data <= x"ad";
when "10" & x"3eb" => data <= x"28";
when "10" & x"3ec" => data <= x"fc";
when "10" & x"3ed" => data <= x"91";
when "10" & x"3ee" => data <= x"a0";
when "10" & x"3ef" => data <= x"60";
when "10" & x"3f0" => data <= x"a0";
when "10" & x"3f1" => data <= x"00";
when "10" & x"3f2" => data <= x"4c";
when "10" & x"3f3" => data <= x"3e";
when "10" & x"3f4" => data <= x"a4";
when "10" & x"3f5" => data <= x"2c";
when "10" & x"3f6" => data <= x"40";
when "10" & x"3f7" => data <= x"0d";
when "10" & x"3f8" => data <= x"30";
when "10" & x"3f9" => data <= x"1e";
when "10" & x"3fa" => data <= x"ac";
when "10" & x"3fb" => data <= x"d6";
when "10" & x"3fc" => data <= x"10";
when "10" & x"3fd" => data <= x"d0";
when "10" & x"3fe" => data <= x"0c";
when "10" & x"3ff" => data <= x"20";
when "10" & x"400" => data <= x"e2";
when "10" & x"401" => data <= x"a1";
when "10" & x"402" => data <= x"91";
when "10" & x"403" => data <= x"a0";
when "10" & x"404" => data <= x"c8";
when "10" & x"405" => data <= x"ce";
when "10" & x"406" => data <= x"29";
when "10" & x"407" => data <= x"0d";
when "10" & x"408" => data <= x"d0";
when "10" & x"409" => data <= x"f5";
when "10" & x"40a" => data <= x"60";
when "10" & x"40b" => data <= x"ac";
when "10" & x"40c" => data <= x"29";
when "10" & x"40d" => data <= x"0d";
when "10" & x"40e" => data <= x"20";
when "10" & x"40f" => data <= x"e2";
when "10" & x"410" => data <= x"a1";
when "10" & x"411" => data <= x"8d";
when "10" & x"412" => data <= x"e5";
when "10" & x"413" => data <= x"fe";
when "10" & x"414" => data <= x"88";
when "10" & x"415" => data <= x"d0";
when "10" & x"416" => data <= x"f7";
when "10" & x"417" => data <= x"60";
when "10" & x"418" => data <= x"a2";
when "10" & x"419" => data <= x"ff";
when "10" & x"41a" => data <= x"8e";
when "10" & x"41b" => data <= x"28";
when "10" & x"41c" => data <= x"fc";
when "10" & x"41d" => data <= x"ac";
when "10" & x"41e" => data <= x"d6";
when "10" & x"41f" => data <= x"10";
when "10" & x"420" => data <= x"d0";
when "10" & x"421" => data <= x"19";
when "10" & x"422" => data <= x"ce";
when "10" & x"423" => data <= x"29";
when "10" & x"424" => data <= x"0d";
when "10" & x"425" => data <= x"f0";
when "10" & x"426" => data <= x"0e";
when "10" & x"427" => data <= x"ad";
when "10" & x"428" => data <= x"28";
when "10" & x"429" => data <= x"fc";
when "10" & x"42a" => data <= x"8e";
when "10" & x"42b" => data <= x"28";
when "10" & x"42c" => data <= x"fc";
when "10" & x"42d" => data <= x"91";
when "10" & x"42e" => data <= x"a0";
when "10" & x"42f" => data <= x"c8";
when "10" & x"430" => data <= x"ce";
when "10" & x"431" => data <= x"29";
when "10" & x"432" => data <= x"0d";
when "10" & x"433" => data <= x"d0";
when "10" & x"434" => data <= x"f2";
when "10" & x"435" => data <= x"ad";
when "10" & x"436" => data <= x"28";
when "10" & x"437" => data <= x"fc";
when "10" & x"438" => data <= x"91";
when "10" & x"439" => data <= x"a0";
when "10" & x"43a" => data <= x"60";
when "10" & x"43b" => data <= x"ac";
when "10" & x"43c" => data <= x"29";
when "10" & x"43d" => data <= x"0d";
when "10" & x"43e" => data <= x"88";
when "10" & x"43f" => data <= x"f0";
when "10" & x"440" => data <= x"1a";
when "10" & x"441" => data <= x"ea";
when "10" & x"442" => data <= x"ad";
when "10" & x"443" => data <= x"28";
when "10" & x"444" => data <= x"fc";
when "10" & x"445" => data <= x"8e";
when "10" & x"446" => data <= x"28";
when "10" & x"447" => data <= x"fc";
when "10" & x"448" => data <= x"8d";
when "10" & x"449" => data <= x"e5";
when "10" & x"44a" => data <= x"fe";
when "10" & x"44b" => data <= x"20";
when "10" & x"44c" => data <= x"31";
when "10" & x"44d" => data <= x"a3";
when "10" & x"44e" => data <= x"20";
when "10" & x"44f" => data <= x"31";
when "10" & x"450" => data <= x"a3";
when "10" & x"451" => data <= x"ea";
when "10" & x"452" => data <= x"ea";
when "10" & x"453" => data <= x"ea";
when "10" & x"454" => data <= x"88";
when "10" & x"455" => data <= x"d0";
when "10" & x"456" => data <= x"ea";
when "10" & x"457" => data <= x"ea";
when "10" & x"458" => data <= x"ea";
when "10" & x"459" => data <= x"ea";
when "10" & x"45a" => data <= x"ea";
when "10" & x"45b" => data <= x"ad";
when "10" & x"45c" => data <= x"28";
when "10" & x"45d" => data <= x"fc";
when "10" & x"45e" => data <= x"8d";
when "10" & x"45f" => data <= x"e5";
when "10" & x"460" => data <= x"fe";
when "10" & x"461" => data <= x"60";
when "10" & x"462" => data <= x"2c";
when "10" & x"463" => data <= x"40";
when "10" & x"464" => data <= x"0d";
when "10" & x"465" => data <= x"30";
when "10" & x"466" => data <= x"0c";
when "10" & x"467" => data <= x"a0";
when "10" & x"468" => data <= x"00";
when "10" & x"469" => data <= x"20";
when "10" & x"46a" => data <= x"e2";
when "10" & x"46b" => data <= x"a1";
when "10" & x"46c" => data <= x"99";
when "10" & x"46d" => data <= x"00";
when "10" & x"46e" => data <= x"0e";
when "10" & x"46f" => data <= x"c8";
when "10" & x"470" => data <= x"d0";
when "10" & x"471" => data <= x"f7";
when "10" & x"472" => data <= x"60";
when "10" & x"473" => data <= x"a0";
when "10" & x"474" => data <= x"00";
when "10" & x"475" => data <= x"a2";
when "10" & x"476" => data <= x"ff";
when "10" & x"477" => data <= x"8e";
when "10" & x"478" => data <= x"28";
when "10" & x"479" => data <= x"fc";
when "10" & x"47a" => data <= x"20";
when "10" & x"47b" => data <= x"31";
when "10" & x"47c" => data <= x"a3";
when "10" & x"47d" => data <= x"ad";
when "10" & x"47e" => data <= x"28";
when "10" & x"47f" => data <= x"fc";
when "10" & x"480" => data <= x"8e";
when "10" & x"481" => data <= x"28";
when "10" & x"482" => data <= x"fc";
when "10" & x"483" => data <= x"99";
when "10" & x"484" => data <= x"00";
when "10" & x"485" => data <= x"0e";
when "10" & x"486" => data <= x"c8";
when "10" & x"487" => data <= x"c0";
when "10" & x"488" => data <= x"ff";
when "10" & x"489" => data <= x"d0";
when "10" & x"48a" => data <= x"f2";
when "10" & x"48b" => data <= x"ad";
when "10" & x"48c" => data <= x"28";
when "10" & x"48d" => data <= x"fc";
when "10" & x"48e" => data <= x"99";
when "10" & x"48f" => data <= x"00";
when "10" & x"490" => data <= x"0e";
when "10" & x"491" => data <= x"60";
when "10" & x"492" => data <= x"2c";
when "10" & x"493" => data <= x"40";
when "10" & x"494" => data <= x"0d";
when "10" & x"495" => data <= x"30";
when "10" & x"496" => data <= x"0a";
when "10" & x"497" => data <= x"a0";
when "10" & x"498" => data <= x"02";
when "10" & x"499" => data <= x"20";
when "10" & x"49a" => data <= x"df";
when "10" & x"49b" => data <= x"a2";
when "10" & x"49c" => data <= x"a9";
when "10" & x"49d" => data <= x"fe";
when "10" & x"49e" => data <= x"4c";
when "10" & x"49f" => data <= x"9b";
when "10" & x"4a0" => data <= x"a2";
when "10" & x"4a1" => data <= x"a2";
when "10" & x"4a2" => data <= x"ff";
when "10" & x"4a3" => data <= x"8e";
when "10" & x"4a4" => data <= x"28";
when "10" & x"4a5" => data <= x"fc";
when "10" & x"4a6" => data <= x"20";
when "10" & x"4a7" => data <= x"31";
when "10" & x"4a8" => data <= x"a3";
when "10" & x"4a9" => data <= x"8e";
when "10" & x"4aa" => data <= x"28";
when "10" & x"4ab" => data <= x"fc";
when "10" & x"4ac" => data <= x"20";
when "10" & x"4ad" => data <= x"31";
when "10" & x"4ae" => data <= x"a3";
when "10" & x"4af" => data <= x"ca";
when "10" & x"4b0" => data <= x"8e";
when "10" & x"4b1" => data <= x"28";
when "10" & x"4b2" => data <= x"fc";
when "10" & x"4b3" => data <= x"60";
when "10" & x"4b4" => data <= x"a0";
when "10" & x"4b5" => data <= x"02";
when "10" & x"4b6" => data <= x"2c";
when "10" & x"4b7" => data <= x"40";
when "10" & x"4b8" => data <= x"0d";
when "10" & x"4b9" => data <= x"30";
when "10" & x"4ba" => data <= x"18";
when "10" & x"4bb" => data <= x"20";
when "10" & x"4bc" => data <= x"df";
when "10" & x"4bd" => data <= x"a2";
when "10" & x"4be" => data <= x"20";
when "10" & x"4bf" => data <= x"4e";
when "10" & x"4c0" => data <= x"a3";
when "10" & x"4c1" => data <= x"20";
when "10" & x"4c2" => data <= x"3a";
when "10" & x"4c3" => data <= x"a2";
when "10" & x"4c4" => data <= x"a8";
when "10" & x"4c5" => data <= x"29";
when "10" & x"4c6" => data <= x"1f";
when "10" & x"4c7" => data <= x"c9";
when "10" & x"4c8" => data <= x"05";
when "10" & x"4c9" => data <= x"d0";
when "10" & x"4ca" => data <= x"2b";
when "10" & x"4cb" => data <= x"20";
when "10" & x"4cc" => data <= x"e2";
when "10" & x"4cd" => data <= x"a1";
when "10" & x"4ce" => data <= x"c9";
when "10" & x"4cf" => data <= x"ff";
when "10" & x"4d0" => data <= x"d0";
when "10" & x"4d1" => data <= x"f9";
when "10" & x"4d2" => data <= x"60";
when "10" & x"4d3" => data <= x"20";
when "10" & x"4d4" => data <= x"26";
when "10" & x"4d5" => data <= x"a3";
when "10" & x"4d6" => data <= x"a2";
when "10" & x"4d7" => data <= x"ff";
when "10" & x"4d8" => data <= x"8e";
when "10" & x"4d9" => data <= x"28";
when "10" & x"4da" => data <= x"fc";
when "10" & x"4db" => data <= x"20";
when "10" & x"4dc" => data <= x"31";
when "10" & x"4dd" => data <= x"a3";
when "10" & x"4de" => data <= x"ad";
when "10" & x"4df" => data <= x"28";
when "10" & x"4e0" => data <= x"fc";
when "10" & x"4e1" => data <= x"a8";
when "10" & x"4e2" => data <= x"29";
when "10" & x"4e3" => data <= x"1f";
when "10" & x"4e4" => data <= x"c9";
when "10" & x"4e5" => data <= x"05";
when "10" & x"4e6" => data <= x"d0";
when "10" & x"4e7" => data <= x"0e";
when "10" & x"4e8" => data <= x"a9";
when "10" & x"4e9" => data <= x"ff";
when "10" & x"4ea" => data <= x"8e";
when "10" & x"4eb" => data <= x"28";
when "10" & x"4ec" => data <= x"fc";
when "10" & x"4ed" => data <= x"20";
when "10" & x"4ee" => data <= x"31";
when "10" & x"4ef" => data <= x"a3";
when "10" & x"4f0" => data <= x"cd";
when "10" & x"4f1" => data <= x"28";
when "10" & x"4f2" => data <= x"fc";
when "10" & x"4f3" => data <= x"d0";
when "10" & x"4f4" => data <= x"f5";
when "10" & x"4f5" => data <= x"60";
when "10" & x"4f6" => data <= x"98";
when "10" & x"4f7" => data <= x"20";
when "10" & x"4f8" => data <= x"1f";
when "10" & x"4f9" => data <= x"a0";
when "10" & x"4fa" => data <= x"c5";
when "10" & x"4fb" => data <= x"4d";
when "10" & x"4fc" => data <= x"4d";
when "10" & x"4fd" => data <= x"43";
when "10" & x"4fe" => data <= x"20";
when "10" & x"4ff" => data <= x"57";
when "10" & x"500" => data <= x"72";
when "10" & x"501" => data <= x"69";
when "10" & x"502" => data <= x"74";
when "10" & x"503" => data <= x"65";
when "10" & x"504" => data <= x"20";
when "10" & x"505" => data <= x"72";
when "10" & x"506" => data <= x"65";
when "10" & x"507" => data <= x"73";
when "10" & x"508" => data <= x"70";
when "10" & x"509" => data <= x"6f";
when "10" & x"50a" => data <= x"6e";
when "10" & x"50b" => data <= x"73";
when "10" & x"50c" => data <= x"65";
when "10" & x"50d" => data <= x"20";
when "10" & x"50e" => data <= x"66";
when "10" & x"50f" => data <= x"61";
when "10" & x"510" => data <= x"75";
when "10" & x"511" => data <= x"6c";
when "10" & x"512" => data <= x"74";
when "10" & x"513" => data <= x"20";
when "10" & x"514" => data <= x"00";
when "10" & x"515" => data <= x"2c";
when "10" & x"516" => data <= x"40";
when "10" & x"517" => data <= x"0d";
when "10" & x"518" => data <= x"30";
when "10" & x"519" => data <= x"14";
when "10" & x"51a" => data <= x"ac";
when "10" & x"51b" => data <= x"d6";
when "10" & x"51c" => data <= x"10";
when "10" & x"51d" => data <= x"d0";
when "10" & x"51e" => data <= x"03";
when "10" & x"51f" => data <= x"4c";
when "10" & x"520" => data <= x"8d";
when "10" & x"521" => data <= x"a2";
when "10" & x"522" => data <= x"a0";
when "10" & x"523" => data <= x"00";
when "10" & x"524" => data <= x"ad";
when "10" & x"525" => data <= x"e5";
when "10" & x"526" => data <= x"fe";
when "10" & x"527" => data <= x"20";
when "10" & x"528" => data <= x"9b";
when "10" & x"529" => data <= x"a2";
when "10" & x"52a" => data <= x"c8";
when "10" & x"52b" => data <= x"d0";
when "10" & x"52c" => data <= x"f7";
when "10" & x"52d" => data <= x"60";
when "10" & x"52e" => data <= x"ac";
when "10" & x"52f" => data <= x"d6";
when "10" & x"530" => data <= x"10";
when "10" & x"531" => data <= x"d0";
when "10" & x"532" => data <= x"09";
when "10" & x"533" => data <= x"b1";
when "10" & x"534" => data <= x"a0";
when "10" & x"535" => data <= x"8d";
when "10" & x"536" => data <= x"28";
when "10" & x"537" => data <= x"fc";
when "10" & x"538" => data <= x"c8";
when "10" & x"539" => data <= x"d0";
when "10" & x"53a" => data <= x"f8";
when "10" & x"53b" => data <= x"60";
when "10" & x"53c" => data <= x"a0";
when "10" & x"53d" => data <= x"00";
when "10" & x"53e" => data <= x"ad";
when "10" & x"53f" => data <= x"e5";
when "10" & x"540" => data <= x"fe";
when "10" & x"541" => data <= x"8d";
when "10" & x"542" => data <= x"28";
when "10" & x"543" => data <= x"fc";
when "10" & x"544" => data <= x"20";
when "10" & x"545" => data <= x"31";
when "10" & x"546" => data <= x"a3";
when "10" & x"547" => data <= x"20";
when "10" & x"548" => data <= x"31";
when "10" & x"549" => data <= x"a3";
when "10" & x"54a" => data <= x"20";
when "10" & x"54b" => data <= x"31";
when "10" & x"54c" => data <= x"a3";
when "10" & x"54d" => data <= x"c8";
when "10" & x"54e" => data <= x"d0";
when "10" & x"54f" => data <= x"ee";
when "10" & x"550" => data <= x"60";
when "10" & x"551" => data <= x"2c";
when "10" & x"552" => data <= x"40";
when "10" & x"553" => data <= x"0d";
when "10" & x"554" => data <= x"30";
when "10" & x"555" => data <= x"0c";
when "10" & x"556" => data <= x"a0";
when "10" & x"557" => data <= x"00";
when "10" & x"558" => data <= x"b9";
when "10" & x"559" => data <= x"00";
when "10" & x"55a" => data <= x"0e";
when "10" & x"55b" => data <= x"20";
when "10" & x"55c" => data <= x"9b";
when "10" & x"55d" => data <= x"a2";
when "10" & x"55e" => data <= x"c8";
when "10" & x"55f" => data <= x"d0";
when "10" & x"560" => data <= x"f7";
when "10" & x"561" => data <= x"60";
when "10" & x"562" => data <= x"a0";
when "10" & x"563" => data <= x"00";
when "10" & x"564" => data <= x"ea";
when "10" & x"565" => data <= x"b9";
when "10" & x"566" => data <= x"00";
when "10" & x"567" => data <= x"0e";
when "10" & x"568" => data <= x"8d";
when "10" & x"569" => data <= x"28";
when "10" & x"56a" => data <= x"fc";
when "10" & x"56b" => data <= x"c8";
when "10" & x"56c" => data <= x"d0";
when "10" & x"56d" => data <= x"f6";
when "10" & x"56e" => data <= x"60";
when "10" & x"56f" => data <= x"a2";
when "10" & x"570" => data <= x"00";
when "10" & x"571" => data <= x"9d";
when "10" & x"572" => data <= x"43";
when "10" & x"573" => data <= x"0d";
when "10" & x"574" => data <= x"a9";
when "10" & x"575" => data <= x"00";
when "10" & x"576" => data <= x"9d";
when "10" & x"577" => data <= x"44";
when "10" & x"578" => data <= x"0d";
when "10" & x"579" => data <= x"9d";
when "10" & x"57a" => data <= x"45";
when "10" & x"57b" => data <= x"0d";
when "10" & x"57c" => data <= x"9d";
when "10" & x"57d" => data <= x"46";
when "10" & x"57e" => data <= x"0d";
when "10" & x"57f" => data <= x"9d";
when "10" & x"580" => data <= x"47";
when "10" & x"581" => data <= x"0d";
when "10" & x"582" => data <= x"a9";
when "10" & x"583" => data <= x"ff";
when "10" & x"584" => data <= x"9d";
when "10" & x"585" => data <= x"42";
when "10" & x"586" => data <= x"0d";
when "10" & x"587" => data <= x"9d";
when "10" & x"588" => data <= x"48";
when "10" & x"589" => data <= x"0d";
when "10" & x"58a" => data <= x"9d";
when "10" & x"58b" => data <= x"49";
when "10" & x"58c" => data <= x"0d";
when "10" & x"58d" => data <= x"ae";
when "10" & x"58e" => data <= x"03";
when "10" & x"58f" => data <= x"0d";
when "10" & x"590" => data <= x"bd";
when "10" & x"591" => data <= x"ae";
when "10" & x"592" => data <= x"a5";
when "10" & x"593" => data <= x"8d";
when "10" & x"594" => data <= x"40";
when "10" & x"595" => data <= x"0d";
when "10" & x"596" => data <= x"60";
when "10" & x"597" => data <= x"2c";
when "10" & x"598" => data <= x"c9";
when "10" & x"599" => data <= x"10";
when "10" & x"59a" => data <= x"30";
when "10" & x"59b" => data <= x"11";
when "10" & x"59c" => data <= x"a9";
when "10" & x"59d" => data <= x"8f";
when "10" & x"59e" => data <= x"a2";
when "10" & x"59f" => data <= x"0c";
when "10" & x"5a0" => data <= x"a0";
when "10" & x"5a1" => data <= x"ff";
when "10" & x"5a2" => data <= x"20";
when "10" & x"5a3" => data <= x"f4";
when "10" & x"5a4" => data <= x"ff";
when "10" & x"5a5" => data <= x"8c";
when "10" & x"5a6" => data <= x"01";
when "10" & x"5a7" => data <= x"0d";
when "10" & x"5a8" => data <= x"a9";
when "10" & x"5a9" => data <= x"ff";
when "10" & x"5aa" => data <= x"8d";
when "10" & x"5ab" => data <= x"c9";
when "10" & x"5ac" => data <= x"10";
when "10" & x"5ad" => data <= x"60";
when "10" & x"5ae" => data <= x"00";
when "10" & x"5af" => data <= x"80";
when "10" & x"5b0" => data <= x"ad";
when "10" & x"5b1" => data <= x"4f";
when "10" & x"5b2" => data <= x"0d";
when "10" & x"5b3" => data <= x"f0";
when "10" & x"5b4" => data <= x"15";
when "10" & x"5b5" => data <= x"ad";
when "10" & x"5b6" => data <= x"3f";
when "10" & x"5b7" => data <= x"0d";
when "10" & x"5b8" => data <= x"d0";
when "10" & x"5b9" => data <= x"26";
when "10" & x"5ba" => data <= x"ad";
when "10" & x"5bb" => data <= x"50";
when "10" & x"5bc" => data <= x"0d";
when "10" & x"5bd" => data <= x"d0";
when "10" & x"5be" => data <= x"0b";
when "10" & x"5bf" => data <= x"ad";
when "10" & x"5c0" => data <= x"b2";
when "10" & x"5c1" => data <= x"fc";
when "10" & x"5c2" => data <= x"cd";
when "10" & x"5c3" => data <= x"4c";
when "10" & x"5c4" => data <= x"0d";
when "10" & x"5c5" => data <= x"f0";
when "10" & x"5c6" => data <= x"03";
when "10" & x"5c7" => data <= x"20";
when "10" & x"5c8" => data <= x"d6";
when "10" & x"5c9" => data <= x"a9";
when "10" & x"5ca" => data <= x"ad";
when "10" & x"5cb" => data <= x"4c";
when "10" & x"5cc" => data <= x"0d";
when "10" & x"5cd" => data <= x"2d";
when "10" & x"5ce" => data <= x"50";
when "10" & x"5cf" => data <= x"0d";
when "10" & x"5d0" => data <= x"d0";
when "10" & x"5d1" => data <= x"36";
when "10" & x"5d2" => data <= x"ad";
when "10" & x"5d3" => data <= x"4c";
when "10" & x"5d4" => data <= x"0d";
when "10" & x"5d5" => data <= x"0d";
when "10" & x"5d6" => data <= x"50";
when "10" & x"5d7" => data <= x"0d";
when "10" & x"5d8" => data <= x"8d";
when "10" & x"5d9" => data <= x"b2";
when "10" & x"5da" => data <= x"fc";
when "10" & x"5db" => data <= x"ad";
when "10" & x"5dc" => data <= x"3f";
when "10" & x"5dd" => data <= x"0d";
when "10" & x"5de" => data <= x"f0";
when "10" & x"5df" => data <= x"0a";
when "10" & x"5e0" => data <= x"a9";
when "10" & x"5e1" => data <= x"1f";
when "10" & x"5e2" => data <= x"8d";
when "10" & x"5e3" => data <= x"b2";
when "10" & x"5e4" => data <= x"fc";
when "10" & x"5e5" => data <= x"a9";
when "10" & x"5e6" => data <= x"00";
when "10" & x"5e7" => data <= x"8d";
when "10" & x"5e8" => data <= x"50";
when "10" & x"5e9" => data <= x"0d";
when "10" & x"5ea" => data <= x"ad";
when "10" & x"5eb" => data <= x"3f";
when "10" & x"5ec" => data <= x"0d";
when "10" & x"5ed" => data <= x"d0";
when "10" & x"5ee" => data <= x"03";
when "10" & x"5ef" => data <= x"0d";
when "10" & x"5f0" => data <= x"51";
when "10" & x"5f1" => data <= x"0d";
when "10" & x"5f2" => data <= x"8d";
when "10" & x"5f3" => data <= x"b0";
when "10" & x"5f4" => data <= x"fc";
when "10" & x"5f5" => data <= x"ad";
when "10" & x"5f6" => data <= x"bb";
when "10" & x"5f7" => data <= x"fc";
when "10" & x"5f8" => data <= x"29";
when "10" & x"5f9" => data <= x"e3";
when "10" & x"5fa" => data <= x"8d";
when "10" & x"5fb" => data <= x"bb";
when "10" & x"5fc" => data <= x"fc";
when "10" & x"5fd" => data <= x"a9";
when "10" & x"5fe" => data <= x"1c";
when "10" & x"5ff" => data <= x"8d";
when "10" & x"600" => data <= x"be";
when "10" & x"601" => data <= x"fc";
when "10" & x"602" => data <= x"a9";
when "10" & x"603" => data <= x"00";
when "10" & x"604" => data <= x"8d";
when "10" & x"605" => data <= x"ba";
when "10" & x"606" => data <= x"fc";
when "10" & x"607" => data <= x"60";
when "10" & x"608" => data <= x"20";
when "10" & x"609" => data <= x"00";
when "10" & x"60a" => data <= x"a0";
when "10" & x"60b" => data <= x"ff";
when "10" & x"60c" => data <= x"55";
when "10" & x"60d" => data <= x"73";
when "10" & x"60e" => data <= x"65";
when "10" & x"60f" => data <= x"72";
when "10" & x"610" => data <= x"20";
when "10" & x"611" => data <= x"70";
when "10" & x"612" => data <= x"6f";
when "10" & x"613" => data <= x"72";
when "10" & x"614" => data <= x"74";
when "10" & x"615" => data <= x"20";
when "10" & x"616" => data <= x"63";
when "10" & x"617" => data <= x"6f";
when "10" & x"618" => data <= x"6e";
when "10" & x"619" => data <= x"66";
when "10" & x"61a" => data <= x"6c";
when "10" & x"61b" => data <= x"69";
when "10" & x"61c" => data <= x"63";
when "10" & x"61d" => data <= x"74";
when "10" & x"61e" => data <= x"00";
when "10" & x"61f" => data <= x"ad";
when "10" & x"620" => data <= x"02";
when "10" & x"621" => data <= x"0d";
when "10" & x"622" => data <= x"c9";
when "10" & x"623" => data <= x"54";
when "10" & x"624" => data <= x"d0";
when "10" & x"625" => data <= x"04";
when "10" & x"626" => data <= x"20";
when "10" & x"627" => data <= x"b0";
when "10" & x"628" => data <= x"a5";
when "10" & x"629" => data <= x"60";
when "10" & x"62a" => data <= x"20";
when "10" & x"62b" => data <= x"43";
when "10" & x"62c" => data <= x"a6";
when "10" & x"62d" => data <= x"d0";
when "10" & x"62e" => data <= x"fa";
when "10" & x"62f" => data <= x"20";
when "10" & x"630" => data <= x"eb";
when "10" & x"631" => data <= x"a9";
when "10" & x"632" => data <= x"c9";
when "10" & x"633" => data <= x"ff";
when "10" & x"634" => data <= x"f0";
when "10" & x"635" => data <= x"f3";
when "10" & x"636" => data <= x"20";
when "10" & x"637" => data <= x"00";
when "10" & x"638" => data <= x"a0";
when "10" & x"639" => data <= x"ff";
when "10" & x"63a" => data <= x"43";
when "10" & x"63b" => data <= x"61";
when "10" & x"63c" => data <= x"72";
when "10" & x"63d" => data <= x"64";
when "10" & x"63e" => data <= x"3f";
when "10" & x"63f" => data <= x"00";
when "10" & x"640" => data <= x"20";
when "10" & x"641" => data <= x"76";
when "10" & x"642" => data <= x"a1";
when "10" & x"643" => data <= x"20";
when "10" & x"644" => data <= x"b0";
when "10" & x"645" => data <= x"a5";
when "10" & x"646" => data <= x"a0";
when "10" & x"647" => data <= x"0a";
when "10" & x"648" => data <= x"20";
when "10" & x"649" => data <= x"da";
when "10" & x"64a" => data <= x"a2";
when "10" & x"64b" => data <= x"a9";
when "10" & x"64c" => data <= x"40";
when "10" & x"64d" => data <= x"20";
when "10" & x"64e" => data <= x"6f";
when "10" & x"64f" => data <= x"a5";
when "10" & x"650" => data <= x"a9";
when "10" & x"651" => data <= x"95";
when "10" & x"652" => data <= x"8d";
when "10" & x"653" => data <= x"48";
when "10" & x"654" => data <= x"0d";
when "10" & x"655" => data <= x"20";
when "10" & x"656" => data <= x"32";
when "10" & x"657" => data <= x"a3";
when "10" & x"658" => data <= x"c9";
when "10" & x"659" => data <= x"01";
when "10" & x"65a" => data <= x"f0";
when "10" & x"65b" => data <= x"03";
when "10" & x"65c" => data <= x"4c";
when "10" & x"65d" => data <= x"07";
when "10" & x"65e" => data <= x"a7";
when "10" & x"65f" => data <= x"a9";
when "10" & x"660" => data <= x"01";
when "10" & x"661" => data <= x"8d";
when "10" & x"662" => data <= x"4f";
when "10" & x"663" => data <= x"0d";
when "10" & x"664" => data <= x"a9";
when "10" & x"665" => data <= x"48";
when "10" & x"666" => data <= x"20";
when "10" & x"667" => data <= x"6f";
when "10" & x"668" => data <= x"a5";
when "10" & x"669" => data <= x"a9";
when "10" & x"66a" => data <= x"01";
when "10" & x"66b" => data <= x"8d";
when "10" & x"66c" => data <= x"46";
when "10" & x"66d" => data <= x"0d";
when "10" & x"66e" => data <= x"a9";
when "10" & x"66f" => data <= x"aa";
when "10" & x"670" => data <= x"8d";
when "10" & x"671" => data <= x"47";
when "10" & x"672" => data <= x"0d";
when "10" & x"673" => data <= x"a9";
when "10" & x"674" => data <= x"87";
when "10" & x"675" => data <= x"8d";
when "10" & x"676" => data <= x"48";
when "10" & x"677" => data <= x"0d";
when "10" & x"678" => data <= x"20";
when "10" & x"679" => data <= x"32";
when "10" & x"67a" => data <= x"a3";
when "10" & x"67b" => data <= x"c9";
when "10" & x"67c" => data <= x"01";
when "10" & x"67d" => data <= x"f0";
when "10" & x"67e" => data <= x"20";
when "10" & x"67f" => data <= x"a9";
when "10" & x"680" => data <= x"02";
when "10" & x"681" => data <= x"8d";
when "10" & x"682" => data <= x"4f";
when "10" & x"683" => data <= x"0d";
when "10" & x"684" => data <= x"a9";
when "10" & x"685" => data <= x"41";
when "10" & x"686" => data <= x"20";
when "10" & x"687" => data <= x"6f";
when "10" & x"688" => data <= x"a5";
when "10" & x"689" => data <= x"20";
when "10" & x"68a" => data <= x"32";
when "10" & x"68b" => data <= x"a3";
when "10" & x"68c" => data <= x"c9";
when "10" & x"68d" => data <= x"02";
when "10" & x"68e" => data <= x"90";
when "10" & x"68f" => data <= x"03";
when "10" & x"690" => data <= x"4c";
when "10" & x"691" => data <= x"07";
when "10" & x"692" => data <= x"a7";
when "10" & x"693" => data <= x"c9";
when "10" & x"694" => data <= x"00";
when "10" & x"695" => data <= x"d0";
when "10" & x"696" => data <= x"ed";
when "10" & x"697" => data <= x"a9";
when "10" & x"698" => data <= x"02";
when "10" & x"699" => data <= x"8d";
when "10" & x"69a" => data <= x"4f";
when "10" & x"69b" => data <= x"0d";
when "10" & x"69c" => data <= x"4c";
when "10" & x"69d" => data <= x"e7";
when "10" & x"69e" => data <= x"a6";
when "10" & x"69f" => data <= x"20";
when "10" & x"6a0" => data <= x"e2";
when "10" & x"6a1" => data <= x"a1";
when "10" & x"6a2" => data <= x"20";
when "10" & x"6a3" => data <= x"e2";
when "10" & x"6a4" => data <= x"a1";
when "10" & x"6a5" => data <= x"20";
when "10" & x"6a6" => data <= x"e2";
when "10" & x"6a7" => data <= x"a1";
when "10" & x"6a8" => data <= x"20";
when "10" & x"6a9" => data <= x"e2";
when "10" & x"6aa" => data <= x"a1";
when "10" & x"6ab" => data <= x"a9";
when "10" & x"6ac" => data <= x"77";
when "10" & x"6ad" => data <= x"20";
when "10" & x"6ae" => data <= x"6f";
when "10" & x"6af" => data <= x"a5";
when "10" & x"6b0" => data <= x"20";
when "10" & x"6b1" => data <= x"32";
when "10" & x"6b2" => data <= x"a3";
when "10" & x"6b3" => data <= x"a9";
when "10" & x"6b4" => data <= x"69";
when "10" & x"6b5" => data <= x"20";
when "10" & x"6b6" => data <= x"6f";
when "10" & x"6b7" => data <= x"a5";
when "10" & x"6b8" => data <= x"a9";
when "10" & x"6b9" => data <= x"40";
when "10" & x"6ba" => data <= x"8d";
when "10" & x"6bb" => data <= x"44";
when "10" & x"6bc" => data <= x"0d";
when "10" & x"6bd" => data <= x"20";
when "10" & x"6be" => data <= x"32";
when "10" & x"6bf" => data <= x"a3";
when "10" & x"6c0" => data <= x"c9";
when "10" & x"6c1" => data <= x"00";
when "10" & x"6c2" => data <= x"d0";
when "10" & x"6c3" => data <= x"e7";
when "10" & x"6c4" => data <= x"a9";
when "10" & x"6c5" => data <= x"7a";
when "10" & x"6c6" => data <= x"20";
when "10" & x"6c7" => data <= x"6f";
when "10" & x"6c8" => data <= x"a5";
when "10" & x"6c9" => data <= x"20";
when "10" & x"6ca" => data <= x"32";
when "10" & x"6cb" => data <= x"a3";
when "10" & x"6cc" => data <= x"c9";
when "10" & x"6cd" => data <= x"00";
when "10" & x"6ce" => data <= x"d0";
when "10" & x"6cf" => data <= x"37";
when "10" & x"6d0" => data <= x"20";
when "10" & x"6d1" => data <= x"e2";
when "10" & x"6d2" => data <= x"a1";
when "10" & x"6d3" => data <= x"29";
when "10" & x"6d4" => data <= x"40";
when "10" & x"6d5" => data <= x"48";
when "10" & x"6d6" => data <= x"20";
when "10" & x"6d7" => data <= x"e2";
when "10" & x"6d8" => data <= x"a1";
when "10" & x"6d9" => data <= x"20";
when "10" & x"6da" => data <= x"e2";
when "10" & x"6db" => data <= x"a1";
when "10" & x"6dc" => data <= x"20";
when "10" & x"6dd" => data <= x"e2";
when "10" & x"6de" => data <= x"a1";
when "10" & x"6df" => data <= x"68";
when "10" & x"6e0" => data <= x"d0";
when "10" & x"6e1" => data <= x"05";
when "10" & x"6e2" => data <= x"a9";
when "10" & x"6e3" => data <= x"02";
when "10" & x"6e4" => data <= x"8d";
when "10" & x"6e5" => data <= x"4f";
when "10" & x"6e6" => data <= x"0d";
when "10" & x"6e7" => data <= x"a9";
when "10" & x"6e8" => data <= x"50";
when "10" & x"6e9" => data <= x"20";
when "10" & x"6ea" => data <= x"6f";
when "10" & x"6eb" => data <= x"a5";
when "10" & x"6ec" => data <= x"a9";
when "10" & x"6ed" => data <= x"02";
when "10" & x"6ee" => data <= x"8d";
when "10" & x"6ef" => data <= x"46";
when "10" & x"6f0" => data <= x"0d";
when "10" & x"6f1" => data <= x"20";
when "10" & x"6f2" => data <= x"32";
when "10" & x"6f3" => data <= x"a3";
when "10" & x"6f4" => data <= x"d0";
when "10" & x"6f5" => data <= x"2e";
when "10" & x"6f6" => data <= x"a9";
when "10" & x"6f7" => data <= x"54";
when "10" & x"6f8" => data <= x"8d";
when "10" & x"6f9" => data <= x"02";
when "10" & x"6fa" => data <= x"0d";
when "10" & x"6fb" => data <= x"ad";
when "10" & x"6fc" => data <= x"03";
when "10" & x"6fd" => data <= x"0d";
when "10" & x"6fe" => data <= x"8d";
when "10" & x"6ff" => data <= x"04";
when "10" & x"700" => data <= x"0d";
when "10" & x"701" => data <= x"20";
when "10" & x"702" => data <= x"80";
when "10" & x"703" => data <= x"a1";
when "10" & x"704" => data <= x"a9";
when "10" & x"705" => data <= x"ff";
when "10" & x"706" => data <= x"60";
when "10" & x"707" => data <= x"ae";
when "10" & x"708" => data <= x"03";
when "10" & x"709" => data <= x"0d";
when "10" & x"70a" => data <= x"e8";
when "10" & x"70b" => data <= x"e0";
when "10" & x"70c" => data <= x"02";
when "10" & x"70d" => data <= x"b0";
when "10" & x"70e" => data <= x"09";
when "10" & x"70f" => data <= x"8e";
when "10" & x"710" => data <= x"03";
when "10" & x"711" => data <= x"0d";
when "10" & x"712" => data <= x"20";
when "10" & x"713" => data <= x"8d";
when "10" & x"714" => data <= x"a5";
when "10" & x"715" => data <= x"4c";
when "10" & x"716" => data <= x"46";
when "10" & x"717" => data <= x"a6";
when "10" & x"718" => data <= x"a9";
when "10" & x"719" => data <= x"00";
when "10" & x"71a" => data <= x"8d";
when "10" & x"71b" => data <= x"03";
when "10" & x"71c" => data <= x"0d";
when "10" & x"71d" => data <= x"20";
when "10" & x"71e" => data <= x"8d";
when "10" & x"71f" => data <= x"a5";
when "10" & x"720" => data <= x"8d";
when "10" & x"721" => data <= x"02";
when "10" & x"722" => data <= x"0d";
when "10" & x"723" => data <= x"60";
when "10" & x"724" => data <= x"20";
when "10" & x"725" => data <= x"1f";
when "10" & x"726" => data <= x"a0";
when "10" & x"727" => data <= x"ff";
when "10" & x"728" => data <= x"53";
when "10" & x"729" => data <= x"65";
when "10" & x"72a" => data <= x"74";
when "10" & x"72b" => data <= x"20";
when "10" & x"72c" => data <= x"62";
when "10" & x"72d" => data <= x"6c";
when "10" & x"72e" => data <= x"6f";
when "10" & x"72f" => data <= x"63";
when "10" & x"730" => data <= x"6b";
when "10" & x"731" => data <= x"20";
when "10" & x"732" => data <= x"6c";
when "10" & x"733" => data <= x"65";
when "10" & x"734" => data <= x"6e";
when "10" & x"735" => data <= x"20";
when "10" & x"736" => data <= x"65";
when "10" & x"737" => data <= x"72";
when "10" & x"738" => data <= x"72";
when "10" & x"739" => data <= x"6f";
when "10" & x"73a" => data <= x"72";
when "10" & x"73b" => data <= x"20";
when "10" & x"73c" => data <= x"00";
when "10" & x"73d" => data <= x"a9";
when "10" & x"73e" => data <= x"51";
when "10" & x"73f" => data <= x"20";
when "10" & x"740" => data <= x"6f";
when "10" & x"741" => data <= x"a5";
when "10" & x"742" => data <= x"60";
when "10" & x"743" => data <= x"20";
when "10" & x"744" => data <= x"21";
when "10" & x"745" => data <= x"aa";
when "10" & x"746" => data <= x"20";
when "10" & x"747" => data <= x"32";
when "10" & x"748" => data <= x"a3";
when "10" & x"749" => data <= x"d0";
when "10" & x"74a" => data <= x"07";
when "10" & x"74b" => data <= x"20";
when "10" & x"74c" => data <= x"a1";
when "10" & x"74d" => data <= x"a3";
when "10" & x"74e" => data <= x"20";
when "10" & x"74f" => data <= x"83";
when "10" & x"750" => data <= x"aa";
when "10" & x"751" => data <= x"60";
when "10" & x"752" => data <= x"20";
when "10" & x"753" => data <= x"1f";
when "10" & x"754" => data <= x"a0";
when "10" & x"755" => data <= x"c5";
when "10" & x"756" => data <= x"4d";
when "10" & x"757" => data <= x"4d";
when "10" & x"758" => data <= x"43";
when "10" & x"759" => data <= x"20";
when "10" & x"75a" => data <= x"52";
when "10" & x"75b" => data <= x"65";
when "10" & x"75c" => data <= x"61";
when "10" & x"75d" => data <= x"64";
when "10" & x"75e" => data <= x"20";
when "10" & x"75f" => data <= x"66";
when "10" & x"760" => data <= x"61";
when "10" & x"761" => data <= x"75";
when "10" & x"762" => data <= x"6c";
when "10" & x"763" => data <= x"74";
when "10" & x"764" => data <= x"20";
when "10" & x"765" => data <= x"00";
when "10" & x"766" => data <= x"20";
when "10" & x"767" => data <= x"21";
when "10" & x"768" => data <= x"aa";
when "10" & x"769" => data <= x"20";
when "10" & x"76a" => data <= x"32";
when "10" & x"76b" => data <= x"a3";
when "10" & x"76c" => data <= x"d0";
when "10" & x"76d" => data <= x"07";
when "10" & x"76e" => data <= x"20";
when "10" & x"76f" => data <= x"92";
when "10" & x"770" => data <= x"a4";
when "10" & x"771" => data <= x"20";
when "10" & x"772" => data <= x"83";
when "10" & x"773" => data <= x"aa";
when "10" & x"774" => data <= x"60";
when "10" & x"775" => data <= x"20";
when "10" & x"776" => data <= x"1f";
when "10" & x"777" => data <= x"a0";
when "10" & x"778" => data <= x"c5";
when "10" & x"779" => data <= x"4d";
when "10" & x"77a" => data <= x"4d";
when "10" & x"77b" => data <= x"43";
when "10" & x"77c" => data <= x"20";
when "10" & x"77d" => data <= x"57";
when "10" & x"77e" => data <= x"72";
when "10" & x"77f" => data <= x"69";
when "10" & x"780" => data <= x"74";
when "10" & x"781" => data <= x"65";
when "10" & x"782" => data <= x"20";
when "10" & x"783" => data <= x"66";
when "10" & x"784" => data <= x"61";
when "10" & x"785" => data <= x"75";
when "10" & x"786" => data <= x"6c";
when "10" & x"787" => data <= x"74";
when "10" & x"788" => data <= x"20";
when "10" & x"789" => data <= x"00";
when "10" & x"78a" => data <= x"20";
when "10" & x"78b" => data <= x"76";
when "10" & x"78c" => data <= x"a1";
when "10" & x"78d" => data <= x"a9";
when "10" & x"78e" => data <= x"00";
when "10" & x"78f" => data <= x"8d";
when "10" & x"790" => data <= x"d6";
when "10" & x"791" => data <= x"10";
when "10" & x"792" => data <= x"85";
when "10" & x"793" => data <= x"a0";
when "10" & x"794" => data <= x"a9";
when "10" & x"795" => data <= x"0e";
when "10" & x"796" => data <= x"85";
when "10" & x"797" => data <= x"a1";
when "10" & x"798" => data <= x"60";
when "10" & x"799" => data <= x"20";
when "10" & x"79a" => data <= x"8a";
when "10" & x"79b" => data <= x"a7";
when "10" & x"79c" => data <= x"20";
when "10" & x"79d" => data <= x"3d";
when "10" & x"79e" => data <= x"a7";
when "10" & x"79f" => data <= x"20";
when "10" & x"7a0" => data <= x"43";
when "10" & x"7a1" => data <= x"a7";
when "10" & x"7a2" => data <= x"20";
when "10" & x"7a3" => data <= x"be";
when "10" & x"7a4" => data <= x"a3";
when "10" & x"7a5" => data <= x"e6";
when "10" & x"7a6" => data <= x"a1";
when "10" & x"7a7" => data <= x"20";
when "10" & x"7a8" => data <= x"be";
when "10" & x"7a9" => data <= x"a3";
when "10" & x"7aa" => data <= x"a0";
when "10" & x"7ab" => data <= x"02";
when "10" & x"7ac" => data <= x"20";
when "10" & x"7ad" => data <= x"da";
when "10" & x"7ae" => data <= x"a2";
when "10" & x"7af" => data <= x"4c";
when "10" & x"7b0" => data <= x"80";
when "10" & x"7b1" => data <= x"a1";
when "10" & x"7b2" => data <= x"20";
when "10" & x"7b3" => data <= x"8a";
when "10" & x"7b4" => data <= x"a7";
when "10" & x"7b5" => data <= x"a9";
when "10" & x"7b6" => data <= x"58";
when "10" & x"7b7" => data <= x"20";
when "10" & x"7b8" => data <= x"3f";
when "10" & x"7b9" => data <= x"a7";
when "10" & x"7ba" => data <= x"20";
when "10" & x"7bb" => data <= x"66";
when "10" & x"7bc" => data <= x"a7";
when "10" & x"7bd" => data <= x"20";
when "10" & x"7be" => data <= x"15";
when "10" & x"7bf" => data <= x"a5";
when "10" & x"7c0" => data <= x"e6";
when "10" & x"7c1" => data <= x"a1";
when "10" & x"7c2" => data <= x"20";
when "10" & x"7c3" => data <= x"15";
when "10" & x"7c4" => data <= x"a5";
when "10" & x"7c5" => data <= x"20";
when "10" & x"7c6" => data <= x"b4";
when "10" & x"7c7" => data <= x"a4";
when "10" & x"7c8" => data <= x"4c";
when "10" & x"7c9" => data <= x"80";
when "10" & x"7ca" => data <= x"a1";
when "10" & x"7cb" => data <= x"60";
when "10" & x"7cc" => data <= x"20";
when "10" & x"7cd" => data <= x"76";
when "10" & x"7ce" => data <= x"a1";
when "10" & x"7cf" => data <= x"20";
when "10" & x"7d0" => data <= x"d5";
when "10" & x"7d1" => data <= x"a7";
when "10" & x"7d2" => data <= x"4c";
when "10" & x"7d3" => data <= x"80";
when "10" & x"7d4" => data <= x"a1";
when "10" & x"7d5" => data <= x"ae";
when "10" & x"7d6" => data <= x"27";
when "10" & x"7d7" => data <= x"0d";
when "10" & x"7d8" => data <= x"f0";
when "10" & x"7d9" => data <= x"f1";
when "10" & x"7da" => data <= x"a9";
when "10" & x"7db" => data <= x"01";
when "10" & x"7dc" => data <= x"20";
when "10" & x"7dd" => data <= x"98";
when "10" & x"7de" => data <= x"a0";
when "10" & x"7df" => data <= x"ae";
when "10" & x"7e0" => data <= x"27";
when "10" & x"7e1" => data <= x"0d";
when "10" & x"7e2" => data <= x"2c";
when "10" & x"7e3" => data <= x"28";
when "10" & x"7e4" => data <= x"0d";
when "10" & x"7e5" => data <= x"10";
when "10" & x"7e6" => data <= x"01";
when "10" & x"7e7" => data <= x"e8";
when "10" & x"7e8" => data <= x"8e";
when "10" & x"7e9" => data <= x"27";
when "10" & x"7ea" => data <= x"0d";
when "10" & x"7eb" => data <= x"20";
when "10" & x"7ec" => data <= x"3d";
when "10" & x"7ed" => data <= x"a7";
when "10" & x"7ee" => data <= x"ae";
when "10" & x"7ef" => data <= x"27";
when "10" & x"7f0" => data <= x"0d";
when "10" & x"7f1" => data <= x"e0";
when "10" & x"7f2" => data <= x"03";
when "10" & x"7f3" => data <= x"b0";
when "10" & x"7f4" => data <= x"09";
when "10" & x"7f5" => data <= x"ad";
when "10" & x"7f6" => data <= x"29";
when "10" & x"7f7" => data <= x"0d";
when "10" & x"7f8" => data <= x"d0";
when "10" & x"7f9" => data <= x"46";
when "10" & x"7fa" => data <= x"e0";
when "10" & x"7fb" => data <= x"01";
when "10" & x"7fc" => data <= x"f0";
when "10" & x"7fd" => data <= x"39";
when "10" & x"7fe" => data <= x"2c";
when "10" & x"7ff" => data <= x"28";
when "10" & x"800" => data <= x"0d";
when "10" & x"801" => data <= x"10";
when "10" & x"802" => data <= x"0e";
when "10" & x"803" => data <= x"20";
when "10" & x"804" => data <= x"43";
when "10" & x"805" => data <= x"a7";
when "10" & x"806" => data <= x"a0";
when "10" & x"807" => data <= x"00";
when "10" & x"808" => data <= x"8c";
when "10" & x"809" => data <= x"28";
when "10" & x"80a" => data <= x"0d";
when "10" & x"80b" => data <= x"20";
when "10" & x"80c" => data <= x"da";
when "10" & x"80d" => data <= x"a2";
when "10" & x"80e" => data <= x"4c";
when "10" & x"80f" => data <= x"19";
when "10" & x"810" => data <= x"a8";
when "10" & x"811" => data <= x"20";
when "10" & x"812" => data <= x"43";
when "10" & x"813" => data <= x"a7";
when "10" & x"814" => data <= x"20";
when "10" & x"815" => data <= x"be";
when "10" & x"816" => data <= x"a3";
when "10" & x"817" => data <= x"e6";
when "10" & x"818" => data <= x"a1";
when "10" & x"819" => data <= x"20";
when "10" & x"81a" => data <= x"be";
when "10" & x"81b" => data <= x"a3";
when "10" & x"81c" => data <= x"e6";
when "10" & x"81d" => data <= x"a1";
when "10" & x"81e" => data <= x"a0";
when "10" & x"81f" => data <= x"02";
when "10" & x"820" => data <= x"20";
when "10" & x"821" => data <= x"da";
when "10" & x"822" => data <= x"a2";
when "10" & x"823" => data <= x"20";
when "10" & x"824" => data <= x"61";
when "10" & x"825" => data <= x"aa";
when "10" & x"826" => data <= x"ae";
when "10" & x"827" => data <= x"27";
when "10" & x"828" => data <= x"0d";
when "10" & x"829" => data <= x"ca";
when "10" & x"82a" => data <= x"ca";
when "10" & x"82b" => data <= x"f0";
when "10" & x"82c" => data <= x"9e";
when "10" & x"82d" => data <= x"8e";
when "10" & x"82e" => data <= x"27";
when "10" & x"82f" => data <= x"0d";
when "10" & x"830" => data <= x"e0";
when "10" & x"831" => data <= x"03";
when "10" & x"832" => data <= x"b0";
when "10" & x"833" => data <= x"dd";
when "10" & x"834" => data <= x"4c";
when "10" & x"835" => data <= x"f5";
when "10" & x"836" => data <= x"a7";
when "10" & x"837" => data <= x"20";
when "10" & x"838" => data <= x"43";
when "10" & x"839" => data <= x"a7";
when "10" & x"83a" => data <= x"20";
when "10" & x"83b" => data <= x"be";
when "10" & x"83c" => data <= x"a3";
when "10" & x"83d" => data <= x"4c";
when "10" & x"83e" => data <= x"6d";
when "10" & x"83f" => data <= x"a8";
when "10" & x"840" => data <= x"20";
when "10" & x"841" => data <= x"43";
when "10" & x"842" => data <= x"a7";
when "10" & x"843" => data <= x"2c";
when "10" & x"844" => data <= x"28";
when "10" & x"845" => data <= x"0d";
when "10" & x"846" => data <= x"10";
when "10" & x"847" => data <= x"0b";
when "10" & x"848" => data <= x"a0";
when "10" & x"849" => data <= x"00";
when "10" & x"84a" => data <= x"8c";
when "10" & x"84b" => data <= x"28";
when "10" & x"84c" => data <= x"0d";
when "10" & x"84d" => data <= x"20";
when "10" & x"84e" => data <= x"da";
when "10" & x"84f" => data <= x"a2";
when "10" & x"850" => data <= x"4c";
when "10" & x"851" => data <= x"5d";
when "10" & x"852" => data <= x"a8";
when "10" & x"853" => data <= x"ce";
when "10" & x"854" => data <= x"27";
when "10" & x"855" => data <= x"0d";
when "10" & x"856" => data <= x"f0";
when "10" & x"857" => data <= x"05";
when "10" & x"858" => data <= x"20";
when "10" & x"859" => data <= x"be";
when "10" & x"85a" => data <= x"a3";
when "10" & x"85b" => data <= x"e6";
when "10" & x"85c" => data <= x"a1";
when "10" & x"85d" => data <= x"20";
when "10" & x"85e" => data <= x"f5";
when "10" & x"85f" => data <= x"a3";
when "10" & x"860" => data <= x"98";
when "10" & x"861" => data <= x"49";
when "10" & x"862" => data <= x"ff";
when "10" & x"863" => data <= x"a8";
when "10" & x"864" => data <= x"c8";
when "10" & x"865" => data <= x"20";
when "10" & x"866" => data <= x"da";
when "10" & x"867" => data <= x"a2";
when "10" & x"868" => data <= x"ad";
when "10" & x"869" => data <= x"27";
when "10" & x"86a" => data <= x"0d";
when "10" & x"86b" => data <= x"d0";
when "10" & x"86c" => data <= x"05";
when "10" & x"86d" => data <= x"a0";
when "10" & x"86e" => data <= x"00";
when "10" & x"86f" => data <= x"20";
when "10" & x"870" => data <= x"da";
when "10" & x"871" => data <= x"a2";
when "10" & x"872" => data <= x"a0";
when "10" & x"873" => data <= x"02";
when "10" & x"874" => data <= x"4c";
when "10" & x"875" => data <= x"da";
when "10" & x"876" => data <= x"a2";
when "10" & x"877" => data <= x"60";
when "10" & x"878" => data <= x"20";
when "10" & x"879" => data <= x"76";
when "10" & x"87a" => data <= x"a1";
when "10" & x"87b" => data <= x"20";
when "10" & x"87c" => data <= x"81";
when "10" & x"87d" => data <= x"a8";
when "10" & x"87e" => data <= x"4c";
when "10" & x"87f" => data <= x"80";
when "10" & x"880" => data <= x"a1";
when "10" & x"881" => data <= x"ae";
when "10" & x"882" => data <= x"27";
when "10" & x"883" => data <= x"0d";
when "10" & x"884" => data <= x"f0";
when "10" & x"885" => data <= x"f1";
when "10" & x"886" => data <= x"a9";
when "10" & x"887" => data <= x"00";
when "10" & x"888" => data <= x"20";
when "10" & x"889" => data <= x"98";
when "10" & x"88a" => data <= x"a0";
when "10" & x"88b" => data <= x"a9";
when "10" & x"88c" => data <= x"58";
when "10" & x"88d" => data <= x"20";
when "10" & x"88e" => data <= x"3f";
when "10" & x"88f" => data <= x"a7";
when "10" & x"890" => data <= x"ae";
when "10" & x"891" => data <= x"27";
when "10" & x"892" => data <= x"0d";
when "10" & x"893" => data <= x"2c";
when "10" & x"894" => data <= x"28";
when "10" & x"895" => data <= x"0d";
when "10" & x"896" => data <= x"10";
when "10" & x"897" => data <= x"3a";
when "10" & x"898" => data <= x"a9";
when "10" & x"899" => data <= x"00";
when "10" & x"89a" => data <= x"8d";
when "10" & x"89b" => data <= x"28";
when "10" & x"89c" => data <= x"0d";
when "10" & x"89d" => data <= x"a9";
when "10" & x"89e" => data <= x"ff";
when "10" & x"89f" => data <= x"8d";
when "10" & x"8a0" => data <= x"82";
when "10" & x"8a1" => data <= x"10";
when "10" & x"8a2" => data <= x"a9";
when "10" & x"8a3" => data <= x"51";
when "10" & x"8a4" => data <= x"8d";
when "10" & x"8a5" => data <= x"43";
when "10" & x"8a6" => data <= x"0d";
when "10" & x"8a7" => data <= x"20";
when "10" & x"8a8" => data <= x"43";
when "10" & x"8a9" => data <= x"a7";
when "10" & x"8aa" => data <= x"20";
when "10" & x"8ab" => data <= x"62";
when "10" & x"8ac" => data <= x"a4";
when "10" & x"8ad" => data <= x"a0";
when "10" & x"8ae" => data <= x"00";
when "10" & x"8af" => data <= x"20";
when "10" & x"8b0" => data <= x"da";
when "10" & x"8b1" => data <= x"a2";
when "10" & x"8b2" => data <= x"a0";
when "10" & x"8b3" => data <= x"02";
when "10" & x"8b4" => data <= x"20";
when "10" & x"8b5" => data <= x"da";
when "10" & x"8b6" => data <= x"a2";
when "10" & x"8b7" => data <= x"a9";
when "10" & x"8b8" => data <= x"58";
when "10" & x"8b9" => data <= x"8d";
when "10" & x"8ba" => data <= x"43";
when "10" & x"8bb" => data <= x"0d";
when "10" & x"8bc" => data <= x"20";
when "10" & x"8bd" => data <= x"66";
when "10" & x"8be" => data <= x"a7";
when "10" & x"8bf" => data <= x"20";
when "10" & x"8c0" => data <= x"51";
when "10" & x"8c1" => data <= x"a5";
when "10" & x"8c2" => data <= x"20";
when "10" & x"8c3" => data <= x"15";
when "10" & x"8c4" => data <= x"a5";
when "10" & x"8c5" => data <= x"20";
when "10" & x"8c6" => data <= x"b4";
when "10" & x"8c7" => data <= x"a4";
when "10" & x"8c8" => data <= x"ce";
when "10" & x"8c9" => data <= x"27";
when "10" & x"8ca" => data <= x"0d";
when "10" & x"8cb" => data <= x"f0";
when "10" & x"8cc" => data <= x"aa";
when "10" & x"8cd" => data <= x"e6";
when "10" & x"8ce" => data <= x"a1";
when "10" & x"8cf" => data <= x"20";
when "10" & x"8d0" => data <= x"61";
when "10" & x"8d1" => data <= x"aa";
when "10" & x"8d2" => data <= x"ae";
when "10" & x"8d3" => data <= x"27";
when "10" & x"8d4" => data <= x"0d";
when "10" & x"8d5" => data <= x"f0";
when "10" & x"8d6" => data <= x"46";
when "10" & x"8d7" => data <= x"ca";
when "10" & x"8d8" => data <= x"d0";
when "10" & x"8d9" => data <= x"2b";
when "10" & x"8da" => data <= x"a9";
when "10" & x"8db" => data <= x"ff";
when "10" & x"8dc" => data <= x"8d";
when "10" & x"8dd" => data <= x"82";
when "10" & x"8de" => data <= x"10";
when "10" & x"8df" => data <= x"a9";
when "10" & x"8e0" => data <= x"51";
when "10" & x"8e1" => data <= x"8d";
when "10" & x"8e2" => data <= x"43";
when "10" & x"8e3" => data <= x"0d";
when "10" & x"8e4" => data <= x"20";
when "10" & x"8e5" => data <= x"43";
when "10" & x"8e6" => data <= x"a7";
when "10" & x"8e7" => data <= x"a0";
when "10" & x"8e8" => data <= x"00";
when "10" & x"8e9" => data <= x"20";
when "10" & x"8ea" => data <= x"da";
when "10" & x"8eb" => data <= x"a2";
when "10" & x"8ec" => data <= x"20";
when "10" & x"8ed" => data <= x"62";
when "10" & x"8ee" => data <= x"a4";
when "10" & x"8ef" => data <= x"a0";
when "10" & x"8f0" => data <= x"02";
when "10" & x"8f1" => data <= x"20";
when "10" & x"8f2" => data <= x"da";
when "10" & x"8f3" => data <= x"a2";
when "10" & x"8f4" => data <= x"a9";
when "10" & x"8f5" => data <= x"58";
when "10" & x"8f6" => data <= x"8d";
when "10" & x"8f7" => data <= x"43";
when "10" & x"8f8" => data <= x"0d";
when "10" & x"8f9" => data <= x"20";
when "10" & x"8fa" => data <= x"66";
when "10" & x"8fb" => data <= x"a7";
when "10" & x"8fc" => data <= x"20";
when "10" & x"8fd" => data <= x"15";
when "10" & x"8fe" => data <= x"a5";
when "10" & x"8ff" => data <= x"20";
when "10" & x"900" => data <= x"51";
when "10" & x"901" => data <= x"a5";
when "10" & x"902" => data <= x"4c";
when "10" & x"903" => data <= x"b4";
when "10" & x"904" => data <= x"a4";
when "10" & x"905" => data <= x"20";
when "10" & x"906" => data <= x"66";
when "10" & x"907" => data <= x"a7";
when "10" & x"908" => data <= x"20";
when "10" & x"909" => data <= x"15";
when "10" & x"90a" => data <= x"a5";
when "10" & x"90b" => data <= x"e6";
when "10" & x"90c" => data <= x"a1";
when "10" & x"90d" => data <= x"20";
when "10" & x"90e" => data <= x"15";
when "10" & x"90f" => data <= x"a5";
when "10" & x"910" => data <= x"e6";
when "10" & x"911" => data <= x"a1";
when "10" & x"912" => data <= x"20";
when "10" & x"913" => data <= x"b4";
when "10" & x"914" => data <= x"a4";
when "10" & x"915" => data <= x"ce";
when "10" & x"916" => data <= x"27";
when "10" & x"917" => data <= x"0d";
when "10" & x"918" => data <= x"ce";
when "10" & x"919" => data <= x"27";
when "10" & x"91a" => data <= x"0d";
when "10" & x"91b" => data <= x"d0";
when "10" & x"91c" => data <= x"b2";
when "10" & x"91d" => data <= x"60";
when "10" & x"91e" => data <= x"a9";
when "10" & x"91f" => data <= x"51";
when "10" & x"920" => data <= x"20";
when "10" & x"921" => data <= x"6f";
when "10" & x"922" => data <= x"a5";
when "10" & x"923" => data <= x"60";
when "10" & x"924" => data <= x"20";
when "10" & x"925" => data <= x"76";
when "10" & x"926" => data <= x"a1";
when "10" & x"927" => data <= x"20";
when "10" & x"928" => data <= x"43";
when "10" & x"929" => data <= x"a7";
when "10" & x"92a" => data <= x"a9";
when "10" & x"92b" => data <= x"5f";
when "10" & x"92c" => data <= x"85";
when "10" & x"92d" => data <= x"a0";
when "10" & x"92e" => data <= x"a9";
when "10" & x"92f" => data <= x"0d";
when "10" & x"930" => data <= x"85";
when "10" & x"931" => data <= x"a1";
when "10" & x"932" => data <= x"a9";
when "10" & x"933" => data <= x"08";
when "10" & x"934" => data <= x"8d";
when "10" & x"935" => data <= x"29";
when "10" & x"936" => data <= x"0d";
when "10" & x"937" => data <= x"20";
when "10" & x"938" => data <= x"f5";
when "10" & x"939" => data <= x"a3";
when "10" & x"93a" => data <= x"a0";
when "10" & x"93b" => data <= x"f8";
when "10" & x"93c" => data <= x"20";
when "10" & x"93d" => data <= x"da";
when "10" & x"93e" => data <= x"a2";
when "10" & x"93f" => data <= x"a9";
when "10" & x"940" => data <= x"67";
when "10" & x"941" => data <= x"85";
when "10" & x"942" => data <= x"a0";
when "10" & x"943" => data <= x"a9";
when "10" & x"944" => data <= x"08";
when "10" & x"945" => data <= x"8d";
when "10" & x"946" => data <= x"29";
when "10" & x"947" => data <= x"0d";
when "10" & x"948" => data <= x"20";
when "10" & x"949" => data <= x"f5";
when "10" & x"94a" => data <= x"a3";
when "10" & x"94b" => data <= x"a0";
when "10" & x"94c" => data <= x"fa";
when "10" & x"94d" => data <= x"20";
when "10" & x"94e" => data <= x"da";
when "10" & x"94f" => data <= x"a2";
when "10" & x"950" => data <= x"ad";
when "10" & x"951" => data <= x"4f";
when "10" & x"952" => data <= x"0d";
when "10" & x"953" => data <= x"c9";
when "10" & x"954" => data <= x"02";
when "10" & x"955" => data <= x"f0";
when "10" & x"956" => data <= x"1e";
when "10" & x"957" => data <= x"18";
when "10" & x"958" => data <= x"ad";
when "10" & x"959" => data <= x"47";
when "10" & x"95a" => data <= x"0d";
when "10" & x"95b" => data <= x"69";
when "10" & x"95c" => data <= x"90";
when "10" & x"95d" => data <= x"8d";
when "10" & x"95e" => data <= x"47";
when "10" & x"95f" => data <= x"0d";
when "10" & x"960" => data <= x"ad";
when "10" & x"961" => data <= x"46";
when "10" & x"962" => data <= x"0d";
when "10" & x"963" => data <= x"69";
when "10" & x"964" => data <= x"01";
when "10" & x"965" => data <= x"8d";
when "10" & x"966" => data <= x"46";
when "10" & x"967" => data <= x"0d";
when "10" & x"968" => data <= x"90";
when "10" & x"969" => data <= x"08";
when "10" & x"96a" => data <= x"ee";
when "10" & x"96b" => data <= x"45";
when "10" & x"96c" => data <= x"0d";
when "10" & x"96d" => data <= x"f0";
when "10" & x"96e" => data <= x"03";
when "10" & x"96f" => data <= x"ee";
when "10" & x"970" => data <= x"44";
when "10" & x"971" => data <= x"0d";
when "10" & x"972" => data <= x"4c";
when "10" & x"973" => data <= x"8b";
when "10" & x"974" => data <= x"a9";
when "10" & x"975" => data <= x"18";
when "10" & x"976" => data <= x"ad";
when "10" & x"977" => data <= x"46";
when "10" & x"978" => data <= x"0d";
when "10" & x"979" => data <= x"69";
when "10" & x"97a" => data <= x"20";
when "10" & x"97b" => data <= x"8d";
when "10" & x"97c" => data <= x"46";
when "10" & x"97d" => data <= x"0d";
when "10" & x"97e" => data <= x"ad";
when "10" & x"97f" => data <= x"45";
when "10" & x"980" => data <= x"0d";
when "10" & x"981" => data <= x"69";
when "10" & x"982" => data <= x"03";
when "10" & x"983" => data <= x"8d";
when "10" & x"984" => data <= x"45";
when "10" & x"985" => data <= x"0d";
when "10" & x"986" => data <= x"90";
when "10" & x"987" => data <= x"03";
when "10" & x"988" => data <= x"ee";
when "10" & x"989" => data <= x"44";
when "10" & x"98a" => data <= x"0d";
when "10" & x"98b" => data <= x"4c";
when "10" & x"98c" => data <= x"80";
when "10" & x"98d" => data <= x"a1";
when "10" & x"98e" => data <= x"60";
when "10" & x"98f" => data <= x"a9";
when "10" & x"990" => data <= x"00";
when "10" & x"991" => data <= x"8d";
when "10" & x"992" => data <= x"50";
when "10" & x"993" => data <= x"0d";
when "10" & x"994" => data <= x"8d";
when "10" & x"995" => data <= x"51";
when "10" & x"996" => data <= x"0d";
when "10" & x"997" => data <= x"20";
when "10" & x"998" => data <= x"eb";
when "10" & x"999" => data <= x"a9";
when "10" & x"99a" => data <= x"a9";
when "10" & x"99b" => data <= x"7a";
when "10" & x"99c" => data <= x"20";
when "10" & x"99d" => data <= x"f4";
when "10" & x"99e" => data <= x"ff";
when "10" & x"99f" => data <= x"8a";
when "10" & x"9a0" => data <= x"30";
when "10" & x"9a1" => data <= x"0d";
when "10" & x"9a2" => data <= x"c9";
when "10" & x"9a3" => data <= x"51";
when "10" & x"9a4" => data <= x"f0";
when "10" & x"9a5" => data <= x"04";
when "10" & x"9a6" => data <= x"c9";
when "10" & x"9a7" => data <= x"42";
when "10" & x"9a8" => data <= x"d0";
when "10" & x"9a9" => data <= x"e4";
when "10" & x"9aa" => data <= x"a9";
when "10" & x"9ab" => data <= x"78";
when "10" & x"9ac" => data <= x"20";
when "10" & x"9ad" => data <= x"f4";
when "10" & x"9ae" => data <= x"ff";
when "10" & x"9af" => data <= x"8e";
when "10" & x"9b0" => data <= x"52";
when "10" & x"9b1" => data <= x"0d";
when "10" & x"9b2" => data <= x"4c";
when "10" & x"9b3" => data <= x"20";
when "10" & x"9b4" => data <= x"93";
when "10" & x"9b5" => data <= x"ae";
when "10" & x"9b6" => data <= x"4a";
when "10" & x"9b7" => data <= x"0d";
when "10" & x"9b8" => data <= x"18";
when "10" & x"9b9" => data <= x"a9";
when "10" & x"9ba" => data <= x"80";
when "10" & x"9bb" => data <= x"2a";
when "10" & x"9bc" => data <= x"2a";
when "10" & x"9bd" => data <= x"ca";
when "10" & x"9be" => data <= x"d0";
when "10" & x"9bf" => data <= x"fb";
when "10" & x"9c0" => data <= x"8d";
when "10" & x"9c1" => data <= x"4b";
when "10" & x"9c2" => data <= x"0d";
when "10" & x"9c3" => data <= x"0a";
when "10" & x"9c4" => data <= x"8d";
when "10" & x"9c5" => data <= x"4e";
when "10" & x"9c6" => data <= x"0d";
when "10" & x"9c7" => data <= x"aa";
when "10" & x"9c8" => data <= x"18";
when "10" & x"9c9" => data <= x"6d";
when "10" & x"9ca" => data <= x"4b";
when "10" & x"9cb" => data <= x"0d";
when "10" & x"9cc" => data <= x"8d";
when "10" & x"9cd" => data <= x"4c";
when "10" & x"9ce" => data <= x"0d";
when "10" & x"9cf" => data <= x"8a";
when "10" & x"9d0" => data <= x"49";
when "10" & x"9d1" => data <= x"ff";
when "10" & x"9d2" => data <= x"8d";
when "10" & x"9d3" => data <= x"4d";
when "10" & x"9d4" => data <= x"0d";
when "10" & x"9d5" => data <= x"60";
when "10" & x"9d6" => data <= x"ad";
when "10" & x"9d7" => data <= x"b2";
when "10" & x"9d8" => data <= x"fc";
when "10" & x"9d9" => data <= x"8d";
when "10" & x"9da" => data <= x"50";
when "10" & x"9db" => data <= x"0d";
when "10" & x"9dc" => data <= x"49";
when "10" & x"9dd" => data <= x"ff";
when "10" & x"9de" => data <= x"8d";
when "10" & x"9df" => data <= x"51";
when "10" & x"9e0" => data <= x"0d";
when "10" & x"9e1" => data <= x"ad";
when "10" & x"9e2" => data <= x"b0";
when "10" & x"9e3" => data <= x"fc";
when "10" & x"9e4" => data <= x"4d";
when "10" & x"9e5" => data <= x"51";
when "10" & x"9e6" => data <= x"0d";
when "10" & x"9e7" => data <= x"8d";
when "10" & x"9e8" => data <= x"51";
when "10" & x"9e9" => data <= x"0d";
when "10" & x"9ea" => data <= x"60";
when "10" & x"9eb" => data <= x"a9";
when "10" & x"9ec" => data <= x"00";
when "10" & x"9ed" => data <= x"8d";
when "10" & x"9ee" => data <= x"3f";
when "10" & x"9ef" => data <= x"0d";
when "10" & x"9f0" => data <= x"8d";
when "10" & x"9f1" => data <= x"4f";
when "10" & x"9f2" => data <= x"0d";
when "10" & x"9f3" => data <= x"a2";
when "10" & x"9f4" => data <= x"04";
when "10" & x"9f5" => data <= x"8e";
when "10" & x"9f6" => data <= x"4a";
when "10" & x"9f7" => data <= x"0d";
when "10" & x"9f8" => data <= x"20";
when "10" & x"9f9" => data <= x"b5";
when "10" & x"9fa" => data <= x"a9";
when "10" & x"9fb" => data <= x"20";
when "10" & x"9fc" => data <= x"43";
when "10" & x"9fd" => data <= x"a6";
when "10" & x"9fe" => data <= x"c9";
when "10" & x"9ff" => data <= x"ff";
when "10" & x"a00" => data <= x"f0";
when "10" & x"a01" => data <= x"1e";
when "10" & x"a02" => data <= x"ae";
when "10" & x"a03" => data <= x"4a";
when "10" & x"a04" => data <= x"0d";
when "10" & x"a05" => data <= x"ca";
when "10" & x"a06" => data <= x"d0";
when "10" & x"a07" => data <= x"ed";
when "10" & x"a08" => data <= x"8e";
when "10" & x"a09" => data <= x"4a";
when "10" & x"a0a" => data <= x"0d";
when "10" & x"a0b" => data <= x"8e";
when "10" & x"a0c" => data <= x"4f";
when "10" & x"a0d" => data <= x"0d";
when "10" & x"a0e" => data <= x"ad";
when "10" & x"a0f" => data <= x"3f";
when "10" & x"a10" => data <= x"0d";
when "10" & x"a11" => data <= x"d0";
when "10" & x"a12" => data <= x"0a";
when "10" & x"a13" => data <= x"a2";
when "10" & x"a14" => data <= x"08";
when "10" & x"a15" => data <= x"8e";
when "10" & x"a16" => data <= x"3f";
when "10" & x"a17" => data <= x"0d";
when "10" & x"a18" => data <= x"a2";
when "10" & x"a19" => data <= x"01";
when "10" & x"a1a" => data <= x"4c";
when "10" & x"a1b" => data <= x"f5";
when "10" & x"a1c" => data <= x"a9";
when "10" & x"a1d" => data <= x"20";
when "10" & x"a1e" => data <= x"07";
when "10" & x"a1f" => data <= x"a7";
when "10" & x"a20" => data <= x"60";
when "10" & x"a21" => data <= x"ad";
when "10" & x"a22" => data <= x"4f";
when "10" & x"a23" => data <= x"0d";
when "10" & x"a24" => data <= x"c9";
when "10" & x"a25" => data <= x"02";
when "10" & x"a26" => data <= x"d0";
when "10" & x"a27" => data <= x"20";
when "10" & x"a28" => data <= x"ad";
when "10" & x"a29" => data <= x"26";
when "10" & x"a2a" => data <= x"0d";
when "10" & x"a2b" => data <= x"18";
when "10" & x"a2c" => data <= x"ac";
when "10" & x"a2d" => data <= x"25";
when "10" & x"a2e" => data <= x"0d";
when "10" & x"a2f" => data <= x"ae";
when "10" & x"a30" => data <= x"24";
when "10" & x"a31" => data <= x"0d";
when "10" & x"a32" => data <= x"ad";
when "10" & x"a33" => data <= x"23";
when "10" & x"a34" => data <= x"0d";
when "10" & x"a35" => data <= x"0a";
when "10" & x"a36" => data <= x"8d";
when "10" & x"a37" => data <= x"24";
when "10" & x"a38" => data <= x"0d";
when "10" & x"a39" => data <= x"8a";
when "10" & x"a3a" => data <= x"2a";
when "10" & x"a3b" => data <= x"8d";
when "10" & x"a3c" => data <= x"25";
when "10" & x"a3d" => data <= x"0d";
when "10" & x"a3e" => data <= x"98";
when "10" & x"a3f" => data <= x"2a";
when "10" & x"a40" => data <= x"8d";
when "10" & x"a41" => data <= x"26";
when "10" & x"a42" => data <= x"0d";
when "10" & x"a43" => data <= x"a9";
when "10" & x"a44" => data <= x"00";
when "10" & x"a45" => data <= x"8d";
when "10" & x"a46" => data <= x"23";
when "10" & x"a47" => data <= x"0d";
when "10" & x"a48" => data <= x"ad";
when "10" & x"a49" => data <= x"23";
when "10" & x"a4a" => data <= x"0d";
when "10" & x"a4b" => data <= x"8d";
when "10" & x"a4c" => data <= x"47";
when "10" & x"a4d" => data <= x"0d";
when "10" & x"a4e" => data <= x"ad";
when "10" & x"a4f" => data <= x"24";
when "10" & x"a50" => data <= x"0d";
when "10" & x"a51" => data <= x"8d";
when "10" & x"a52" => data <= x"46";
when "10" & x"a53" => data <= x"0d";
when "10" & x"a54" => data <= x"ad";
when "10" & x"a55" => data <= x"25";
when "10" & x"a56" => data <= x"0d";
when "10" & x"a57" => data <= x"8d";
when "10" & x"a58" => data <= x"45";
when "10" & x"a59" => data <= x"0d";
when "10" & x"a5a" => data <= x"ad";
when "10" & x"a5b" => data <= x"26";
when "10" & x"a5c" => data <= x"0d";
when "10" & x"a5d" => data <= x"8d";
when "10" & x"a5e" => data <= x"44";
when "10" & x"a5f" => data <= x"0d";
when "10" & x"a60" => data <= x"60";
when "10" & x"a61" => data <= x"18";
when "10" & x"a62" => data <= x"a9";
when "10" & x"a63" => data <= x"01";
when "10" & x"a64" => data <= x"6d";
when "10" & x"a65" => data <= x"23";
when "10" & x"a66" => data <= x"0d";
when "10" & x"a67" => data <= x"8d";
when "10" & x"a68" => data <= x"23";
when "10" & x"a69" => data <= x"0d";
when "10" & x"a6a" => data <= x"ad";
when "10" & x"a6b" => data <= x"24";
when "10" & x"a6c" => data <= x"0d";
when "10" & x"a6d" => data <= x"69";
when "10" & x"a6e" => data <= x"00";
when "10" & x"a6f" => data <= x"8d";
when "10" & x"a70" => data <= x"24";
when "10" & x"a71" => data <= x"0d";
when "10" & x"a72" => data <= x"ad";
when "10" & x"a73" => data <= x"25";
when "10" & x"a74" => data <= x"0d";
when "10" & x"a75" => data <= x"69";
when "10" & x"a76" => data <= x"00";
when "10" & x"a77" => data <= x"8d";
when "10" & x"a78" => data <= x"25";
when "10" & x"a79" => data <= x"0d";
when "10" & x"a7a" => data <= x"ad";
when "10" & x"a7b" => data <= x"26";
when "10" & x"a7c" => data <= x"0d";
when "10" & x"a7d" => data <= x"69";
when "10" & x"a7e" => data <= x"00";
when "10" & x"a7f" => data <= x"8d";
when "10" & x"a80" => data <= x"26";
when "10" & x"a81" => data <= x"0d";
when "10" & x"a82" => data <= x"60";
when "10" & x"a83" => data <= x"ad";
when "10" & x"a84" => data <= x"4f";
when "10" & x"a85" => data <= x"0d";
when "10" & x"a86" => data <= x"c9";
when "10" & x"a87" => data <= x"02";
when "10" & x"a88" => data <= x"d0";
when "10" & x"a89" => data <= x"1c";
when "10" & x"a8a" => data <= x"ac";
when "10" & x"a8b" => data <= x"24";
when "10" & x"a8c" => data <= x"0d";
when "10" & x"a8d" => data <= x"ae";
when "10" & x"a8e" => data <= x"25";
when "10" & x"a8f" => data <= x"0d";
when "10" & x"a90" => data <= x"ad";
when "10" & x"a91" => data <= x"26";
when "10" & x"a92" => data <= x"0d";
when "10" & x"a93" => data <= x"4a";
when "10" & x"a94" => data <= x"8d";
when "10" & x"a95" => data <= x"25";
when "10" & x"a96" => data <= x"0d";
when "10" & x"a97" => data <= x"8a";
when "10" & x"a98" => data <= x"6a";
when "10" & x"a99" => data <= x"8d";
when "10" & x"a9a" => data <= x"24";
when "10" & x"a9b" => data <= x"0d";
when "10" & x"a9c" => data <= x"98";
when "10" & x"a9d" => data <= x"6a";
when "10" & x"a9e" => data <= x"8d";
when "10" & x"a9f" => data <= x"23";
when "10" & x"aa0" => data <= x"0d";
when "10" & x"aa1" => data <= x"a9";
when "10" & x"aa2" => data <= x"00";
when "10" & x"aa3" => data <= x"8d";
when "10" & x"aa4" => data <= x"26";
when "10" & x"aa5" => data <= x"0d";
when "10" & x"aa6" => data <= x"60";
when "10" & x"aa7" => data <= x"ad";
when "10" & x"aa8" => data <= x"05";
when "10" & x"aa9" => data <= x"0d";
when "10" & x"aaa" => data <= x"c9";
when "10" & x"aab" => data <= x"54";
when "10" & x"aac" => data <= x"d0";
when "10" & x"aad" => data <= x"15";
when "10" & x"aae" => data <= x"ad";
when "10" & x"aaf" => data <= x"06";
when "10" & x"ab0" => data <= x"0d";
when "10" & x"ab1" => data <= x"4d";
when "10" & x"ab2" => data <= x"0a";
when "10" & x"ab3" => data <= x"0d";
when "10" & x"ab4" => data <= x"c9";
when "10" & x"ab5" => data <= x"ff";
when "10" & x"ab6" => data <= x"d0";
when "10" & x"ab7" => data <= x"0b";
when "10" & x"ab8" => data <= x"ad";
when "10" & x"ab9" => data <= x"07";
when "10" & x"aba" => data <= x"0d";
when "10" & x"abb" => data <= x"4d";
when "10" & x"abc" => data <= x"0b";
when "10" & x"abd" => data <= x"0d";
when "10" & x"abe" => data <= x"c9";
when "10" & x"abf" => data <= x"ff";
when "10" & x"ac0" => data <= x"d0";
when "10" & x"ac1" => data <= x"01";
when "10" & x"ac2" => data <= x"60";
when "10" & x"ac3" => data <= x"a2";
when "10" & x"ac4" => data <= x"0b";
when "10" & x"ac5" => data <= x"bd";
when "10" & x"ac6" => data <= x"22";
when "10" & x"ac7" => data <= x"0d";
when "10" & x"ac8" => data <= x"48";
when "10" & x"ac9" => data <= x"ca";
when "10" & x"aca" => data <= x"d0";
when "10" & x"acb" => data <= x"f9";
when "10" & x"acc" => data <= x"a9";
when "10" & x"acd" => data <= x"00";
when "10" & x"ace" => data <= x"8d";
when "10" & x"acf" => data <= x"23";
when "10" & x"ad0" => data <= x"0d";
when "10" & x"ad1" => data <= x"8d";
when "10" & x"ad2" => data <= x"24";
when "10" & x"ad3" => data <= x"0d";
when "10" & x"ad4" => data <= x"8d";
when "10" & x"ad5" => data <= x"25";
when "10" & x"ad6" => data <= x"0d";
when "10" & x"ad7" => data <= x"8d";
when "10" & x"ad8" => data <= x"26";
when "10" & x"ad9" => data <= x"0d";
when "10" & x"ada" => data <= x"20";
when "10" & x"adb" => data <= x"99";
when "10" & x"adc" => data <= x"a7";
when "10" & x"add" => data <= x"a9";
when "10" & x"ade" => data <= x"dd";
when "10" & x"adf" => data <= x"8d";
when "10" & x"ae0" => data <= x"82";
when "10" & x"ae1" => data <= x"10";
when "10" & x"ae2" => data <= x"20";
when "10" & x"ae3" => data <= x"00";
when "10" & x"ae4" => data <= x"ab";
when "10" & x"ae5" => data <= x"f0";
when "10" & x"ae6" => data <= x"29";
when "10" & x"ae7" => data <= x"a9";
when "10" & x"ae8" => data <= x"00";
when "10" & x"ae9" => data <= x"8d";
when "10" & x"aea" => data <= x"06";
when "10" & x"aeb" => data <= x"0d";
when "10" & x"aec" => data <= x"8d";
when "10" & x"aed" => data <= x"07";
when "10" & x"aee" => data <= x"0d";
when "10" & x"aef" => data <= x"8d";
when "10" & x"af0" => data <= x"08";
when "10" & x"af1" => data <= x"0d";
when "10" & x"af2" => data <= x"8d";
when "10" & x"af3" => data <= x"09";
when "10" & x"af4" => data <= x"0d";
when "10" & x"af5" => data <= x"a9";
when "10" & x"af6" => data <= x"ff";
when "10" & x"af7" => data <= x"8d";
when "10" & x"af8" => data <= x"0a";
when "10" & x"af9" => data <= x"0d";
when "10" & x"afa" => data <= x"8d";
when "10" & x"afb" => data <= x"0b";
when "10" & x"afc" => data <= x"0d";
when "10" & x"afd" => data <= x"4c";
when "10" & x"afe" => data <= x"e0";
when "10" & x"aff" => data <= x"ac";
when "10" & x"b00" => data <= x"ad";
when "10" & x"b01" => data <= x"fe";
when "10" & x"b02" => data <= x"0f";
when "10" & x"b03" => data <= x"c9";
when "10" & x"b04" => data <= x"55";
when "10" & x"b05" => data <= x"d0";
when "10" & x"b06" => data <= x"05";
when "10" & x"b07" => data <= x"ad";
when "10" & x"b08" => data <= x"ff";
when "10" & x"b09" => data <= x"0f";
when "10" & x"b0a" => data <= x"c9";
when "10" & x"b0b" => data <= x"aa";
when "10" & x"b0c" => data <= x"60";
when "10" & x"b0d" => data <= x"4c";
when "10" & x"b0e" => data <= x"f1";
when "10" & x"b0f" => data <= x"ac";
when "10" & x"b10" => data <= x"ad";
when "10" & x"b11" => data <= x"00";
when "10" & x"b12" => data <= x"0e";
when "10" & x"b13" => data <= x"c9";
when "10" & x"b14" => data <= x"eb";
when "10" & x"b15" => data <= x"d0";
when "10" & x"b16" => data <= x"0e";
when "10" & x"b17" => data <= x"ad";
when "10" & x"b18" => data <= x"02";
when "10" & x"b19" => data <= x"0e";
when "10" & x"b1a" => data <= x"c9";
when "10" & x"b1b" => data <= x"90";
when "10" & x"b1c" => data <= x"d0";
when "10" & x"b1d" => data <= x"07";
when "10" & x"b1e" => data <= x"ad";
when "10" & x"b1f" => data <= x"0c";
when "10" & x"b20" => data <= x"0e";
when "10" & x"b21" => data <= x"c9";
when "10" & x"b22" => data <= x"02";
when "10" & x"b23" => data <= x"f0";
when "10" & x"b24" => data <= x"26";
when "10" & x"b25" => data <= x"ad";
when "10" & x"b26" => data <= x"c6";
when "10" & x"b27" => data <= x"0f";
when "10" & x"b28" => data <= x"8d";
when "10" & x"b29" => data <= x"23";
when "10" & x"b2a" => data <= x"0d";
when "10" & x"b2b" => data <= x"ad";
when "10" & x"b2c" => data <= x"c7";
when "10" & x"b2d" => data <= x"0f";
when "10" & x"b2e" => data <= x"8d";
when "10" & x"b2f" => data <= x"24";
when "10" & x"b30" => data <= x"0d";
when "10" & x"b31" => data <= x"ad";
when "10" & x"b32" => data <= x"c8";
when "10" & x"b33" => data <= x"0f";
when "10" & x"b34" => data <= x"8d";
when "10" & x"b35" => data <= x"25";
when "10" & x"b36" => data <= x"0d";
when "10" & x"b37" => data <= x"ad";
when "10" & x"b38" => data <= x"c9";
when "10" & x"b39" => data <= x"0f";
when "10" & x"b3a" => data <= x"8d";
when "10" & x"b3b" => data <= x"26";
when "10" & x"b3c" => data <= x"0d";
when "10" & x"b3d" => data <= x"20";
when "10" & x"b3e" => data <= x"0a";
when "10" & x"b3f" => data <= x"ad";
when "10" & x"b40" => data <= x"20";
when "10" & x"b41" => data <= x"99";
when "10" & x"b42" => data <= x"a7";
when "10" & x"b43" => data <= x"20";
when "10" & x"b44" => data <= x"23";
when "10" & x"b45" => data <= x"ad";
when "10" & x"b46" => data <= x"20";
when "10" & x"b47" => data <= x"00";
when "10" & x"b48" => data <= x"ab";
when "10" & x"b49" => data <= x"d0";
when "10" & x"b4a" => data <= x"c2";
when "10" & x"b4b" => data <= x"ad";
when "10" & x"b4c" => data <= x"0b";
when "10" & x"b4d" => data <= x"0e";
when "10" & x"b4e" => data <= x"d0";
when "10" & x"b4f" => data <= x"bd";
when "10" & x"b50" => data <= x"ad";
when "10" & x"b51" => data <= x"0c";
when "10" & x"b52" => data <= x"0e";
when "10" & x"b53" => data <= x"c9";
when "10" & x"b54" => data <= x"02";
when "10" & x"b55" => data <= x"d0";
when "10" & x"b56" => data <= x"b6";
when "10" & x"b57" => data <= x"a2";
when "10" & x"b58" => data <= x"05";
when "10" & x"b59" => data <= x"0e";
when "10" & x"b5a" => data <= x"11";
when "10" & x"b5b" => data <= x"0e";
when "10" & x"b5c" => data <= x"2e";
when "10" & x"b5d" => data <= x"12";
when "10" & x"b5e" => data <= x"0e";
when "10" & x"b5f" => data <= x"ca";
when "10" & x"b60" => data <= x"d0";
when "10" & x"b61" => data <= x"f7";
when "10" & x"b62" => data <= x"4e";
when "10" & x"b63" => data <= x"12";
when "10" & x"b64" => data <= x"0e";
when "10" & x"b65" => data <= x"ad";
when "10" & x"b66" => data <= x"12";
when "10" & x"b67" => data <= x"0e";
when "10" & x"b68" => data <= x"8d";
when "10" & x"b69" => data <= x"39";
when "10" & x"b6a" => data <= x"0d";
when "10" & x"b6b" => data <= x"ad";
when "10" & x"b6c" => data <= x"0d";
when "10" & x"b6d" => data <= x"0e";
when "10" & x"b6e" => data <= x"8d";
when "10" & x"b6f" => data <= x"29";
when "10" & x"b70" => data <= x"0d";
when "10" & x"b71" => data <= x"18";
when "10" & x"b72" => data <= x"ad";
when "10" & x"b73" => data <= x"0e";
when "10" & x"b74" => data <= x"0e";
when "10" & x"b75" => data <= x"6d";
when "10" & x"b76" => data <= x"23";
when "10" & x"b77" => data <= x"0d";
when "10" & x"b78" => data <= x"8d";
when "10" & x"b79" => data <= x"23";
when "10" & x"b7a" => data <= x"0d";
when "10" & x"b7b" => data <= x"ad";
when "10" & x"b7c" => data <= x"0f";
when "10" & x"b7d" => data <= x"0e";
when "10" & x"b7e" => data <= x"6d";
when "10" & x"b7f" => data <= x"24";
when "10" & x"b80" => data <= x"0d";
when "10" & x"b81" => data <= x"8d";
when "10" & x"b82" => data <= x"24";
when "10" & x"b83" => data <= x"0d";
when "10" & x"b84" => data <= x"a9";
when "10" & x"b85" => data <= x"00";
when "10" & x"b86" => data <= x"6d";
when "10" & x"b87" => data <= x"25";
when "10" & x"b88" => data <= x"0d";
when "10" & x"b89" => data <= x"8d";
when "10" & x"b8a" => data <= x"25";
when "10" & x"b8b" => data <= x"0d";
when "10" & x"b8c" => data <= x"a9";
when "10" & x"b8d" => data <= x"00";
when "10" & x"b8e" => data <= x"6d";
when "10" & x"b8f" => data <= x"26";
when "10" & x"b90" => data <= x"0d";
when "10" & x"b91" => data <= x"8d";
when "10" & x"b92" => data <= x"26";
when "10" & x"b93" => data <= x"0d";
when "10" & x"b94" => data <= x"90";
when "10" & x"b95" => data <= x"03";
when "10" & x"b96" => data <= x"4c";
when "10" & x"b97" => data <= x"f1";
when "10" & x"b98" => data <= x"ac";
when "10" & x"b99" => data <= x"ad";
when "10" & x"b9a" => data <= x"11";
when "10" & x"b9b" => data <= x"0e";
when "10" & x"b9c" => data <= x"0d";
when "10" & x"b9d" => data <= x"12";
when "10" & x"b9e" => data <= x"0e";
when "10" & x"b9f" => data <= x"8d";
when "10" & x"ba0" => data <= x"22";
when "10" & x"ba1" => data <= x"0d";
when "10" & x"ba2" => data <= x"f0";
when "10" & x"ba3" => data <= x"14";
when "10" & x"ba4" => data <= x"a9";
when "10" & x"ba5" => data <= x"00";
when "10" & x"ba6" => data <= x"8d";
when "10" & x"ba7" => data <= x"26";
when "10" & x"ba8" => data <= x"0e";
when "10" & x"ba9" => data <= x"8d";
when "10" & x"baa" => data <= x"27";
when "10" & x"bab" => data <= x"0e";
when "10" & x"bac" => data <= x"ad";
when "10" & x"bad" => data <= x"16";
when "10" & x"bae" => data <= x"0e";
when "10" & x"baf" => data <= x"8d";
when "10" & x"bb0" => data <= x"24";
when "10" & x"bb1" => data <= x"0e";
when "10" & x"bb2" => data <= x"ad";
when "10" & x"bb3" => data <= x"17";
when "10" & x"bb4" => data <= x"0e";
when "10" & x"bb5" => data <= x"8d";
when "10" & x"bb6" => data <= x"25";
when "10" & x"bb7" => data <= x"0e";
when "10" & x"bb8" => data <= x"ae";
when "10" & x"bb9" => data <= x"10";
when "10" & x"bba" => data <= x"0e";
when "10" & x"bbb" => data <= x"18";
when "10" & x"bbc" => data <= x"ad";
when "10" & x"bbd" => data <= x"23";
when "10" & x"bbe" => data <= x"0d";
when "10" & x"bbf" => data <= x"6d";
when "10" & x"bc0" => data <= x"24";
when "10" & x"bc1" => data <= x"0e";
when "10" & x"bc2" => data <= x"8d";
when "10" & x"bc3" => data <= x"23";
when "10" & x"bc4" => data <= x"0d";
when "10" & x"bc5" => data <= x"ad";
when "10" & x"bc6" => data <= x"24";
when "10" & x"bc7" => data <= x"0d";
when "10" & x"bc8" => data <= x"6d";
when "10" & x"bc9" => data <= x"25";
when "10" & x"bca" => data <= x"0e";
when "10" & x"bcb" => data <= x"8d";
when "10" & x"bcc" => data <= x"24";
when "10" & x"bcd" => data <= x"0d";
when "10" & x"bce" => data <= x"ad";
when "10" & x"bcf" => data <= x"25";
when "10" & x"bd0" => data <= x"0d";
when "10" & x"bd1" => data <= x"6d";
when "10" & x"bd2" => data <= x"26";
when "10" & x"bd3" => data <= x"0e";
when "10" & x"bd4" => data <= x"8d";
when "10" & x"bd5" => data <= x"25";
when "10" & x"bd6" => data <= x"0d";
when "10" & x"bd7" => data <= x"ad";
when "10" & x"bd8" => data <= x"26";
when "10" & x"bd9" => data <= x"0d";
when "10" & x"bda" => data <= x"6d";
when "10" & x"bdb" => data <= x"27";
when "10" & x"bdc" => data <= x"0e";
when "10" & x"bdd" => data <= x"8d";
when "10" & x"bde" => data <= x"26";
when "10" & x"bdf" => data <= x"0d";
when "10" & x"be0" => data <= x"90";
when "10" & x"be1" => data <= x"03";
when "10" & x"be2" => data <= x"4c";
when "10" & x"be3" => data <= x"0d";
when "10" & x"be4" => data <= x"ab";
when "10" & x"be5" => data <= x"ca";
when "10" & x"be6" => data <= x"d0";
when "10" & x"be7" => data <= x"d3";
when "10" & x"be8" => data <= x"a9";
when "10" & x"be9" => data <= x"20";
when "10" & x"bea" => data <= x"8d";
when "10" & x"beb" => data <= x"21";
when "10" & x"bec" => data <= x"0d";
when "10" & x"bed" => data <= x"20";
when "10" & x"bee" => data <= x"0a";
when "10" & x"bef" => data <= x"ad";
when "10" & x"bf0" => data <= x"20";
when "10" & x"bf1" => data <= x"99";
when "10" & x"bf2" => data <= x"a7";
when "10" & x"bf3" => data <= x"20";
when "10" & x"bf4" => data <= x"23";
when "10" & x"bf5" => data <= x"ad";
when "10" & x"bf6" => data <= x"a9";
when "10" & x"bf7" => data <= x"00";
when "10" & x"bf8" => data <= x"85";
when "10" & x"bf9" => data <= x"a2";
when "10" & x"bfa" => data <= x"a9";
when "10" & x"bfb" => data <= x"0e";
when "10" & x"bfc" => data <= x"85";
when "10" & x"bfd" => data <= x"a3";
when "10" & x"bfe" => data <= x"a0";
when "10" & x"bff" => data <= x"0b";
when "10" & x"c00" => data <= x"b1";
when "10" & x"c01" => data <= x"a2";
when "10" & x"c02" => data <= x"29";
when "10" & x"c03" => data <= x"0f";
when "10" & x"c04" => data <= x"d0";
when "10" & x"c05" => data <= x"10";
when "10" & x"c06" => data <= x"a0";
when "10" & x"c07" => data <= x"00";
when "10" & x"c08" => data <= x"b1";
when "10" & x"c09" => data <= x"a2";
when "10" & x"c0a" => data <= x"d9";
when "10" & x"c0b" => data <= x"70";
when "10" & x"c0c" => data <= x"0d";
when "10" & x"c0d" => data <= x"d0";
when "10" & x"c0e" => data <= x"07";
when "10" & x"c0f" => data <= x"c8";
when "10" & x"c10" => data <= x"c0";
when "10" & x"c11" => data <= x"0b";
when "10" & x"c12" => data <= x"f0";
when "10" & x"c13" => data <= x"38";
when "10" & x"c14" => data <= x"d0";
when "10" & x"c15" => data <= x"f2";
when "10" & x"c16" => data <= x"18";
when "10" & x"c17" => data <= x"a5";
when "10" & x"c18" => data <= x"a2";
when "10" & x"c19" => data <= x"69";
when "10" & x"c1a" => data <= x"20";
when "10" & x"c1b" => data <= x"85";
when "10" & x"c1c" => data <= x"a2";
when "10" & x"c1d" => data <= x"d0";
when "10" & x"c1e" => data <= x"df";
when "10" & x"c1f" => data <= x"e6";
when "10" & x"c20" => data <= x"a3";
when "10" & x"c21" => data <= x"a5";
when "10" & x"c22" => data <= x"a3";
when "10" & x"c23" => data <= x"c9";
when "10" & x"c24" => data <= x"0f";
when "10" & x"c25" => data <= x"f0";
when "10" & x"c26" => data <= x"d7";
when "10" & x"c27" => data <= x"ce";
when "10" & x"c28" => data <= x"21";
when "10" & x"c29" => data <= x"0d";
when "10" & x"c2a" => data <= x"ad";
when "10" & x"c2b" => data <= x"21";
when "10" & x"c2c" => data <= x"0d";
when "10" & x"c2d" => data <= x"f0";
when "10" & x"c2e" => data <= x"08";
when "10" & x"c2f" => data <= x"a9";
when "10" & x"c30" => data <= x"01";
when "10" & x"c31" => data <= x"20";
when "10" & x"c32" => data <= x"3c";
when "10" & x"c33" => data <= x"ad";
when "10" & x"c34" => data <= x"4c";
when "10" & x"c35" => data <= x"ed";
when "10" & x"c36" => data <= x"ab";
when "10" & x"c37" => data <= x"20";
when "10" & x"c38" => data <= x"00";
when "10" & x"c39" => data <= x"a0";
when "10" & x"c3a" => data <= x"ff";
when "10" & x"c3b" => data <= x"49";
when "10" & x"c3c" => data <= x"6d";
when "10" & x"c3d" => data <= x"61";
when "10" & x"c3e" => data <= x"67";
when "10" & x"c3f" => data <= x"65";
when "10" & x"c40" => data <= x"20";
when "10" & x"c41" => data <= x"6e";
when "10" & x"c42" => data <= x"6f";
when "10" & x"c43" => data <= x"74";
when "10" & x"c44" => data <= x"20";
when "10" & x"c45" => data <= x"66";
when "10" & x"c46" => data <= x"6f";
when "10" & x"c47" => data <= x"75";
when "10" & x"c48" => data <= x"6e";
when "10" & x"c49" => data <= x"64";
when "10" & x"c4a" => data <= x"21";
when "10" & x"c4b" => data <= x"00";
when "10" & x"c4c" => data <= x"a0";
when "10" & x"c4d" => data <= x"14";
when "10" & x"c4e" => data <= x"b1";
when "10" & x"c4f" => data <= x"a2";
when "10" & x"c50" => data <= x"8d";
when "10" & x"c51" => data <= x"2c";
when "10" & x"c52" => data <= x"0d";
when "10" & x"c53" => data <= x"c8";
when "10" & x"c54" => data <= x"b1";
when "10" & x"c55" => data <= x"a2";
when "10" & x"c56" => data <= x"8d";
when "10" & x"c57" => data <= x"2d";
when "10" & x"c58" => data <= x"0d";
when "10" & x"c59" => data <= x"a0";
when "10" & x"c5a" => data <= x"1b";
when "10" & x"c5b" => data <= x"b1";
when "10" & x"c5c" => data <= x"a2";
when "10" & x"c5d" => data <= x"48";
when "10" & x"c5e" => data <= x"88";
when "10" & x"c5f" => data <= x"b1";
when "10" & x"c60" => data <= x"a2";
when "10" & x"c61" => data <= x"38";
when "10" & x"c62" => data <= x"e9";
when "10" & x"c63" => data <= x"02";
when "10" & x"c64" => data <= x"8d";
when "10" & x"c65" => data <= x"2a";
when "10" & x"c66" => data <= x"0d";
when "10" & x"c67" => data <= x"68";
when "10" & x"c68" => data <= x"e9";
when "10" & x"c69" => data <= x"00";
when "10" & x"c6a" => data <= x"8d";
when "10" & x"c6b" => data <= x"2b";
when "10" & x"c6c" => data <= x"0d";
when "10" & x"c6d" => data <= x"ad";
when "10" & x"c6e" => data <= x"2c";
when "10" & x"c6f" => data <= x"0d";
when "10" & x"c70" => data <= x"e9";
when "10" & x"c71" => data <= x"00";
when "10" & x"c72" => data <= x"8d";
when "10" & x"c73" => data <= x"2c";
when "10" & x"c74" => data <= x"0d";
when "10" & x"c75" => data <= x"ad";
when "10" & x"c76" => data <= x"2d";
when "10" & x"c77" => data <= x"0d";
when "10" & x"c78" => data <= x"e9";
when "10" & x"c79" => data <= x"00";
when "10" & x"c7a" => data <= x"8d";
when "10" & x"c7b" => data <= x"2d";
when "10" & x"c7c" => data <= x"0d";
when "10" & x"c7d" => data <= x"0d";
when "10" & x"c7e" => data <= x"2c";
when "10" & x"c7f" => data <= x"0d";
when "10" & x"c80" => data <= x"0d";
when "10" & x"c81" => data <= x"2b";
when "10" & x"c82" => data <= x"0d";
when "10" & x"c83" => data <= x"0d";
when "10" & x"c84" => data <= x"2a";
when "10" & x"c85" => data <= x"0d";
when "10" & x"c86" => data <= x"f0";
when "10" & x"c87" => data <= x"2b";
when "10" & x"c88" => data <= x"ae";
when "10" & x"c89" => data <= x"29";
when "10" & x"c8a" => data <= x"0d";
when "10" & x"c8b" => data <= x"18";
when "10" & x"c8c" => data <= x"ad";
when "10" & x"c8d" => data <= x"23";
when "10" & x"c8e" => data <= x"0d";
when "10" & x"c8f" => data <= x"6d";
when "10" & x"c90" => data <= x"2a";
when "10" & x"c91" => data <= x"0d";
when "10" & x"c92" => data <= x"8d";
when "10" & x"c93" => data <= x"23";
when "10" & x"c94" => data <= x"0d";
when "10" & x"c95" => data <= x"ad";
when "10" & x"c96" => data <= x"24";
when "10" & x"c97" => data <= x"0d";
when "10" & x"c98" => data <= x"6d";
when "10" & x"c99" => data <= x"2b";
when "10" & x"c9a" => data <= x"0d";
when "10" & x"c9b" => data <= x"8d";
when "10" & x"c9c" => data <= x"24";
when "10" & x"c9d" => data <= x"0d";
when "10" & x"c9e" => data <= x"ad";
when "10" & x"c9f" => data <= x"25";
when "10" & x"ca0" => data <= x"0d";
when "10" & x"ca1" => data <= x"6d";
when "10" & x"ca2" => data <= x"2c";
when "10" & x"ca3" => data <= x"0d";
when "10" & x"ca4" => data <= x"8d";
when "10" & x"ca5" => data <= x"25";
when "10" & x"ca6" => data <= x"0d";
when "10" & x"ca7" => data <= x"ad";
when "10" & x"ca8" => data <= x"26";
when "10" & x"ca9" => data <= x"0d";
when "10" & x"caa" => data <= x"6d";
when "10" & x"cab" => data <= x"2d";
when "10" & x"cac" => data <= x"0d";
when "10" & x"cad" => data <= x"8d";
when "10" & x"cae" => data <= x"26";
when "10" & x"caf" => data <= x"0d";
when "10" & x"cb0" => data <= x"ca";
when "10" & x"cb1" => data <= x"d0";
when "10" & x"cb2" => data <= x"d8";
when "10" & x"cb3" => data <= x"ad";
when "10" & x"cb4" => data <= x"22";
when "10" & x"cb5" => data <= x"0d";
when "10" & x"cb6" => data <= x"f0";
when "10" & x"cb7" => data <= x"06";
when "10" & x"cb8" => data <= x"ad";
when "10" & x"cb9" => data <= x"39";
when "10" & x"cba" => data <= x"0d";
when "10" & x"cbb" => data <= x"20";
when "10" & x"cbc" => data <= x"3c";
when "10" & x"cbd" => data <= x"ad";
when "10" & x"cbe" => data <= x"ad";
when "10" & x"cbf" => data <= x"23";
when "10" & x"cc0" => data <= x"0d";
when "10" & x"cc1" => data <= x"8d";
when "10" & x"cc2" => data <= x"06";
when "10" & x"cc3" => data <= x"0d";
when "10" & x"cc4" => data <= x"49";
when "10" & x"cc5" => data <= x"ff";
when "10" & x"cc6" => data <= x"8d";
when "10" & x"cc7" => data <= x"0a";
when "10" & x"cc8" => data <= x"0d";
when "10" & x"cc9" => data <= x"ad";
when "10" & x"cca" => data <= x"24";
when "10" & x"ccb" => data <= x"0d";
when "10" & x"ccc" => data <= x"8d";
when "10" & x"ccd" => data <= x"07";
when "10" & x"cce" => data <= x"0d";
when "10" & x"ccf" => data <= x"49";
when "10" & x"cd0" => data <= x"ff";
when "10" & x"cd1" => data <= x"8d";
when "10" & x"cd2" => data <= x"0b";
when "10" & x"cd3" => data <= x"0d";
when "10" & x"cd4" => data <= x"ad";
when "10" & x"cd5" => data <= x"25";
when "10" & x"cd6" => data <= x"0d";
when "10" & x"cd7" => data <= x"8d";
when "10" & x"cd8" => data <= x"08";
when "10" & x"cd9" => data <= x"0d";
when "10" & x"cda" => data <= x"ad";
when "10" & x"cdb" => data <= x"26";
when "10" & x"cdc" => data <= x"0d";
when "10" & x"cdd" => data <= x"8d";
when "10" & x"cde" => data <= x"09";
when "10" & x"cdf" => data <= x"0d";
when "10" & x"ce0" => data <= x"a9";
when "10" & x"ce1" => data <= x"54";
when "10" & x"ce2" => data <= x"8d";
when "10" & x"ce3" => data <= x"05";
when "10" & x"ce4" => data <= x"0d";
when "10" & x"ce5" => data <= x"a2";
when "10" & x"ce6" => data <= x"00";
when "10" & x"ce7" => data <= x"68";
when "10" & x"ce8" => data <= x"9d";
when "10" & x"ce9" => data <= x"23";
when "10" & x"cea" => data <= x"0d";
when "10" & x"ceb" => data <= x"e8";
when "10" & x"cec" => data <= x"e0";
when "10" & x"ced" => data <= x"0b";
when "10" & x"cee" => data <= x"d0";
when "10" & x"cef" => data <= x"f7";
when "10" & x"cf0" => data <= x"60";
when "10" & x"cf1" => data <= x"20";
when "10" & x"cf2" => data <= x"00";
when "10" & x"cf3" => data <= x"a0";
when "10" & x"cf4" => data <= x"ff";
when "10" & x"cf5" => data <= x"55";
when "10" & x"cf6" => data <= x"6e";
when "10" & x"cf7" => data <= x"72";
when "10" & x"cf8" => data <= x"65";
when "10" & x"cf9" => data <= x"63";
when "10" & x"cfa" => data <= x"6f";
when "10" & x"cfb" => data <= x"67";
when "10" & x"cfc" => data <= x"6e";
when "10" & x"cfd" => data <= x"69";
when "10" & x"cfe" => data <= x"73";
when "10" & x"cff" => data <= x"65";
when "10" & x"d00" => data <= x"64";
when "10" & x"d01" => data <= x"20";
when "10" & x"d02" => data <= x"66";
when "10" & x"d03" => data <= x"6f";
when "10" & x"d04" => data <= x"72";
when "10" & x"d05" => data <= x"6d";
when "10" & x"d06" => data <= x"61";
when "10" & x"d07" => data <= x"74";
when "10" & x"d08" => data <= x"21";
when "10" & x"d09" => data <= x"00";
when "10" & x"d0a" => data <= x"ad";
when "10" & x"d0b" => data <= x"23";
when "10" & x"d0c" => data <= x"0d";
when "10" & x"d0d" => data <= x"8d";
when "10" & x"d0e" => data <= x"06";
when "10" & x"d0f" => data <= x"0d";
when "10" & x"d10" => data <= x"ad";
when "10" & x"d11" => data <= x"24";
when "10" & x"d12" => data <= x"0d";
when "10" & x"d13" => data <= x"8d";
when "10" & x"d14" => data <= x"07";
when "10" & x"d15" => data <= x"0d";
when "10" & x"d16" => data <= x"ad";
when "10" & x"d17" => data <= x"25";
when "10" & x"d18" => data <= x"0d";
when "10" & x"d19" => data <= x"8d";
when "10" & x"d1a" => data <= x"08";
when "10" & x"d1b" => data <= x"0d";
when "10" & x"d1c" => data <= x"ad";
when "10" & x"d1d" => data <= x"26";
when "10" & x"d1e" => data <= x"0d";
when "10" & x"d1f" => data <= x"8d";
when "10" & x"d20" => data <= x"09";
when "10" & x"d21" => data <= x"0d";
when "10" & x"d22" => data <= x"60";
when "10" & x"d23" => data <= x"ad";
when "10" & x"d24" => data <= x"06";
when "10" & x"d25" => data <= x"0d";
when "10" & x"d26" => data <= x"8d";
when "10" & x"d27" => data <= x"23";
when "10" & x"d28" => data <= x"0d";
when "10" & x"d29" => data <= x"ad";
when "10" & x"d2a" => data <= x"07";
when "10" & x"d2b" => data <= x"0d";
when "10" & x"d2c" => data <= x"8d";
when "10" & x"d2d" => data <= x"24";
when "10" & x"d2e" => data <= x"0d";
when "10" & x"d2f" => data <= x"ad";
when "10" & x"d30" => data <= x"08";
when "10" & x"d31" => data <= x"0d";
when "10" & x"d32" => data <= x"8d";
when "10" & x"d33" => data <= x"25";
when "10" & x"d34" => data <= x"0d";
when "10" & x"d35" => data <= x"ad";
when "10" & x"d36" => data <= x"09";
when "10" & x"d37" => data <= x"0d";
when "10" & x"d38" => data <= x"8d";
when "10" & x"d39" => data <= x"26";
when "10" & x"d3a" => data <= x"0d";
when "10" & x"d3b" => data <= x"60";
when "10" & x"d3c" => data <= x"18";
when "10" & x"d3d" => data <= x"6d";
when "10" & x"d3e" => data <= x"23";
when "10" & x"d3f" => data <= x"0d";
when "10" & x"d40" => data <= x"8d";
when "10" & x"d41" => data <= x"23";
when "10" & x"d42" => data <= x"0d";
when "10" & x"d43" => data <= x"ad";
when "10" & x"d44" => data <= x"24";
when "10" & x"d45" => data <= x"0d";
when "10" & x"d46" => data <= x"69";
when "10" & x"d47" => data <= x"00";
when "10" & x"d48" => data <= x"8d";
when "10" & x"d49" => data <= x"24";
when "10" & x"d4a" => data <= x"0d";
when "10" & x"d4b" => data <= x"ad";
when "10" & x"d4c" => data <= x"25";
when "10" & x"d4d" => data <= x"0d";
when "10" & x"d4e" => data <= x"69";
when "10" & x"d4f" => data <= x"00";
when "10" & x"d50" => data <= x"8d";
when "10" & x"d51" => data <= x"25";
when "10" & x"d52" => data <= x"0d";
when "10" & x"d53" => data <= x"ad";
when "10" & x"d54" => data <= x"26";
when "10" & x"d55" => data <= x"0d";
when "10" & x"d56" => data <= x"69";
when "10" & x"d57" => data <= x"00";
when "10" & x"d58" => data <= x"8d";
when "10" & x"d59" => data <= x"26";
when "10" & x"d5a" => data <= x"0d";
when "10" & x"d5b" => data <= x"90";
when "10" & x"d5c" => data <= x"03";
when "10" & x"d5d" => data <= x"4c";
when "10" & x"d5e" => data <= x"f1";
when "10" & x"d5f" => data <= x"ac";
when "10" & x"d60" => data <= x"60";
when "10" & x"d61" => data <= x"42";
when "10" & x"d62" => data <= x"45";
when "10" & x"d63" => data <= x"45";
when "10" & x"d64" => data <= x"42";
when "10" & x"d65" => data <= x"20";
when "10" & x"d66" => data <= x"20";
when "10" & x"d67" => data <= x"20";
when "10" & x"d68" => data <= x"20";
when "10" & x"d69" => data <= x"4d";
when "10" & x"d6a" => data <= x"4d";
when "10" & x"d6b" => data <= x"42";
when "10" & x"d6c" => data <= x"08";
when "10" & x"d6d" => data <= x"aa";
when "10" & x"d6e" => data <= x"20";
when "10" & x"d6f" => data <= x"a1";
when "10" & x"d70" => data <= x"ad";
when "10" & x"d71" => data <= x"85";
when "10" & x"d72" => data <= x"b2";
when "10" & x"d73" => data <= x"48";
when "10" & x"d74" => data <= x"20";
when "10" & x"d75" => data <= x"bd";
when "10" & x"d76" => data <= x"ad";
when "10" & x"d77" => data <= x"8a";
when "10" & x"d78" => data <= x"e5";
when "10" & x"d79" => data <= x"b0";
when "10" & x"d7a" => data <= x"aa";
when "10" & x"d7b" => data <= x"68";
when "10" & x"d7c" => data <= x"20";
when "10" & x"d7d" => data <= x"a1";
when "10" & x"d7e" => data <= x"ad";
when "10" & x"d7f" => data <= x"48";
when "10" & x"d80" => data <= x"20";
when "10" & x"d81" => data <= x"bd";
when "10" & x"d82" => data <= x"ad";
when "10" & x"d83" => data <= x"a5";
when "10" & x"d84" => data <= x"b2";
when "10" & x"d85" => data <= x"e5";
when "10" & x"d86" => data <= x"b0";
when "10" & x"d87" => data <= x"0a";
when "10" & x"d88" => data <= x"0a";
when "10" & x"d89" => data <= x"0a";
when "10" & x"d8a" => data <= x"0a";
when "10" & x"d8b" => data <= x"85";
when "10" & x"d8c" => data <= x"b2";
when "10" & x"d8d" => data <= x"8a";
when "10" & x"d8e" => data <= x"05";
when "10" & x"d8f" => data <= x"b2";
when "10" & x"d90" => data <= x"aa";
when "10" & x"d91" => data <= x"68";
when "10" & x"d92" => data <= x"28";
when "10" & x"d93" => data <= x"90";
when "10" & x"d94" => data <= x"0b";
when "10" & x"d95" => data <= x"48";
when "10" & x"d96" => data <= x"8a";
when "10" & x"d97" => data <= x"f8";
when "10" & x"d98" => data <= x"18";
when "10" & x"d99" => data <= x"69";
when "10" & x"d9a" => data <= x"56";
when "10" & x"d9b" => data <= x"aa";
when "10" & x"d9c" => data <= x"68";
when "10" & x"d9d" => data <= x"69";
when "10" & x"d9e" => data <= x"02";
when "10" & x"d9f" => data <= x"d8";
when "10" & x"da0" => data <= x"60";
when "10" & x"da1" => data <= x"a0";
when "10" & x"da2" => data <= x"00";
when "10" & x"da3" => data <= x"84";
when "10" & x"da4" => data <= x"b1";
when "10" & x"da5" => data <= x"a0";
when "10" & x"da6" => data <= x"a0";
when "10" & x"da7" => data <= x"84";
when "10" & x"da8" => data <= x"b0";
when "10" & x"da9" => data <= x"a0";
when "10" & x"daa" => data <= x"05";
when "10" & x"dab" => data <= x"c5";
when "10" & x"dac" => data <= x"b0";
when "10" & x"dad" => data <= x"90";
when "10" & x"dae" => data <= x"04";
when "10" & x"daf" => data <= x"38";
when "10" & x"db0" => data <= x"e5";
when "10" & x"db1" => data <= x"b0";
when "10" & x"db2" => data <= x"38";
when "10" & x"db3" => data <= x"26";
when "10" & x"db4" => data <= x"b1";
when "10" & x"db5" => data <= x"46";
when "10" & x"db6" => data <= x"b0";
when "10" & x"db7" => data <= x"88";
when "10" & x"db8" => data <= x"d0";
when "10" & x"db9" => data <= x"f1";
when "10" & x"dba" => data <= x"a5";
when "10" & x"dbb" => data <= x"b1";
when "10" & x"dbc" => data <= x"60";
when "10" & x"dbd" => data <= x"48";
when "10" & x"dbe" => data <= x"0a";
when "10" & x"dbf" => data <= x"0a";
when "10" & x"dc0" => data <= x"0a";
when "10" & x"dc1" => data <= x"85";
when "10" & x"dc2" => data <= x"b0";
when "10" & x"dc3" => data <= x"68";
when "10" & x"dc4" => data <= x"0a";
when "10" & x"dc5" => data <= x"18";
when "10" & x"dc6" => data <= x"65";
when "10" & x"dc7" => data <= x"b0";
when "10" & x"dc8" => data <= x"85";
when "10" & x"dc9" => data <= x"b0";
when "10" & x"dca" => data <= x"38";
when "10" & x"dcb" => data <= x"60";
when "10" & x"dcc" => data <= x"e0";
when "10" & x"dcd" => data <= x"ff";
when "10" & x"dce" => data <= x"f0";
when "10" & x"dcf" => data <= x"35";
when "10" & x"dd0" => data <= x"bd";
when "10" & x"dd1" => data <= x"10";
when "10" & x"dd2" => data <= x"0d";
when "10" & x"dd3" => data <= x"30";
when "10" & x"dd4" => data <= x"30";
when "10" & x"dd5" => data <= x"49";
when "10" & x"dd6" => data <= x"ff";
when "10" & x"dd7" => data <= x"dd";
when "10" & x"dd8" => data <= x"18";
when "10" & x"dd9" => data <= x"0d";
when "10" & x"dda" => data <= x"d0";
when "10" & x"ddb" => data <= x"24";
when "10" & x"ddc" => data <= x"bd";
when "10" & x"ddd" => data <= x"0c";
when "10" & x"dde" => data <= x"0d";
when "10" & x"ddf" => data <= x"49";
when "10" & x"de0" => data <= x"ff";
when "10" & x"de1" => data <= x"dd";
when "10" & x"de2" => data <= x"14";
when "10" & x"de3" => data <= x"0d";
when "10" & x"de4" => data <= x"d0";
when "10" & x"de5" => data <= x"1a";
when "10" & x"de6" => data <= x"bd";
when "10" & x"de7" => data <= x"1c";
when "10" & x"de8" => data <= x"0d";
when "10" & x"de9" => data <= x"c9";
when "10" & x"dea" => data <= x"54";
when "10" & x"deb" => data <= x"f0";
when "10" & x"dec" => data <= x"29";
when "10" & x"ded" => data <= x"20";
when "10" & x"dee" => data <= x"00";
when "10" & x"def" => data <= x"a0";
when "10" & x"df0" => data <= x"c9";
when "10" & x"df1" => data <= x"44";
when "10" & x"df2" => data <= x"69";
when "10" & x"df3" => data <= x"73";
when "10" & x"df4" => data <= x"6b";
when "10" & x"df5" => data <= x"20";
when "10" & x"df6" => data <= x"72";
when "10" & x"df7" => data <= x"65";
when "10" & x"df8" => data <= x"61";
when "10" & x"df9" => data <= x"64";
when "10" & x"dfa" => data <= x"20";
when "10" & x"dfb" => data <= x"6f";
when "10" & x"dfc" => data <= x"6e";
when "10" & x"dfd" => data <= x"6c";
when "10" & x"dfe" => data <= x"79";
when "10" & x"dff" => data <= x"00";
when "10" & x"e00" => data <= x"a9";
when "10" & x"e01" => data <= x"ff";
when "10" & x"e02" => data <= x"9d";
when "10" & x"e03" => data <= x"10";
when "10" & x"e04" => data <= x"0d";
when "10" & x"e05" => data <= x"20";
when "10" & x"e06" => data <= x"00";
when "10" & x"e07" => data <= x"a0";
when "10" & x"e08" => data <= x"c7";
when "10" & x"e09" => data <= x"4e";
when "10" & x"e0a" => data <= x"6f";
when "10" & x"e0b" => data <= x"20";
when "10" & x"e0c" => data <= x"64";
when "10" & x"e0d" => data <= x"69";
when "10" & x"e0e" => data <= x"73";
when "10" & x"e0f" => data <= x"6b";
when "10" & x"e10" => data <= x"00";
when "10" & x"e11" => data <= x"a9";
when "10" & x"e12" => data <= x"54";
when "10" & x"e13" => data <= x"9d";
when "10" & x"e14" => data <= x"1c";
when "10" & x"e15" => data <= x"0d";
when "10" & x"e16" => data <= x"60";
when "10" & x"e17" => data <= x"a9";
when "10" & x"e18" => data <= x"00";
when "10" & x"e19" => data <= x"9d";
when "10" & x"e1a" => data <= x"1c";
when "10" & x"e1b" => data <= x"0d";
when "10" & x"e1c" => data <= x"60";
when "10" & x"e1d" => data <= x"bd";
when "10" & x"e1e" => data <= x"10";
when "10" & x"e1f" => data <= x"0d";
when "10" & x"e20" => data <= x"30";
when "10" & x"e21" => data <= x"e3";
when "10" & x"e22" => data <= x"6a";
when "10" & x"e23" => data <= x"bd";
when "10" & x"e24" => data <= x"0c";
when "10" & x"e25" => data <= x"0d";
when "10" & x"e26" => data <= x"08";
when "10" & x"e27" => data <= x"aa";
when "10" & x"e28" => data <= x"a9";
when "10" & x"e29" => data <= x"00";
when "10" & x"e2a" => data <= x"8d";
when "10" & x"e2b" => data <= x"23";
when "10" & x"e2c" => data <= x"0d";
when "10" & x"e2d" => data <= x"8d";
when "10" & x"e2e" => data <= x"26";
when "10" & x"e2f" => data <= x"0d";
when "10" & x"e30" => data <= x"2a";
when "10" & x"e31" => data <= x"48";
when "10" & x"e32" => data <= x"8d";
when "10" & x"e33" => data <= x"25";
when "10" & x"e34" => data <= x"0d";
when "10" & x"e35" => data <= x"8a";
when "10" & x"e36" => data <= x"0a";
when "10" & x"e37" => data <= x"2e";
when "10" & x"e38" => data <= x"25";
when "10" & x"e39" => data <= x"0d";
when "10" & x"e3a" => data <= x"8d";
when "10" & x"e3b" => data <= x"24";
when "10" & x"e3c" => data <= x"0d";
when "10" & x"e3d" => data <= x"8a";
when "10" & x"e3e" => data <= x"6d";
when "10" & x"e3f" => data <= x"24";
when "10" & x"e40" => data <= x"0d";
when "10" & x"e41" => data <= x"8d";
when "10" & x"e42" => data <= x"24";
when "10" & x"e43" => data <= x"0d";
when "10" & x"e44" => data <= x"68";
when "10" & x"e45" => data <= x"69";
when "10" & x"e46" => data <= x"00";
when "10" & x"e47" => data <= x"6d";
when "10" & x"e48" => data <= x"25";
when "10" & x"e49" => data <= x"0d";
when "10" & x"e4a" => data <= x"8d";
when "10" & x"e4b" => data <= x"25";
when "10" & x"e4c" => data <= x"0d";
when "10" & x"e4d" => data <= x"a9";
when "10" & x"e4e" => data <= x"00";
when "10" & x"e4f" => data <= x"6d";
when "10" & x"e50" => data <= x"26";
when "10" & x"e51" => data <= x"0d";
when "10" & x"e52" => data <= x"8d";
when "10" & x"e53" => data <= x"26";
when "10" & x"e54" => data <= x"0d";
when "10" & x"e55" => data <= x"6e";
when "10" & x"e56" => data <= x"23";
when "10" & x"e57" => data <= x"0d";
when "10" & x"e58" => data <= x"8a";
when "10" & x"e59" => data <= x"28";
when "10" & x"e5a" => data <= x"6a";
when "10" & x"e5b" => data <= x"6e";
when "10" & x"e5c" => data <= x"23";
when "10" & x"e5d" => data <= x"0d";
when "10" & x"e5e" => data <= x"4a";
when "10" & x"e5f" => data <= x"6e";
when "10" & x"e60" => data <= x"23";
when "10" & x"e61" => data <= x"0d";
when "10" & x"e62" => data <= x"4a";
when "10" & x"e63" => data <= x"6e";
when "10" & x"e64" => data <= x"23";
when "10" & x"e65" => data <= x"0d";
when "10" & x"e66" => data <= x"6d";
when "10" & x"e67" => data <= x"24";
when "10" & x"e68" => data <= x"0d";
when "10" & x"e69" => data <= x"8d";
when "10" & x"e6a" => data <= x"24";
when "10" & x"e6b" => data <= x"0d";
when "10" & x"e6c" => data <= x"ad";
when "10" & x"e6d" => data <= x"25";
when "10" & x"e6e" => data <= x"0d";
when "10" & x"e6f" => data <= x"69";
when "10" & x"e70" => data <= x"00";
when "10" & x"e71" => data <= x"8d";
when "10" & x"e72" => data <= x"25";
when "10" & x"e73" => data <= x"0d";
when "10" & x"e74" => data <= x"ad";
when "10" & x"e75" => data <= x"26";
when "10" & x"e76" => data <= x"0d";
when "10" & x"e77" => data <= x"69";
when "10" & x"e78" => data <= x"00";
when "10" & x"e79" => data <= x"8d";
when "10" & x"e7a" => data <= x"26";
when "10" & x"e7b" => data <= x"0d";
when "10" & x"e7c" => data <= x"6e";
when "10" & x"e7d" => data <= x"26";
when "10" & x"e7e" => data <= x"0d";
when "10" & x"e7f" => data <= x"6e";
when "10" & x"e80" => data <= x"25";
when "10" & x"e81" => data <= x"0d";
when "10" & x"e82" => data <= x"6e";
when "10" & x"e83" => data <= x"24";
when "10" & x"e84" => data <= x"0d";
when "10" & x"e85" => data <= x"6e";
when "10" & x"e86" => data <= x"23";
when "10" & x"e87" => data <= x"0d";
when "10" & x"e88" => data <= x"20";
when "10" & x"e89" => data <= x"a7";
when "10" & x"e8a" => data <= x"aa";
when "10" & x"e8b" => data <= x"38";
when "10" & x"e8c" => data <= x"ad";
when "10" & x"e8d" => data <= x"23";
when "10" & x"e8e" => data <= x"0d";
when "10" & x"e8f" => data <= x"09";
when "10" & x"e90" => data <= x"0f";
when "10" & x"e91" => data <= x"6d";
when "10" & x"e92" => data <= x"06";
when "10" & x"e93" => data <= x"0d";
when "10" & x"e94" => data <= x"8d";
when "10" & x"e95" => data <= x"23";
when "10" & x"e96" => data <= x"0d";
when "10" & x"e97" => data <= x"ad";
when "10" & x"e98" => data <= x"24";
when "10" & x"e99" => data <= x"0d";
when "10" & x"e9a" => data <= x"6d";
when "10" & x"e9b" => data <= x"07";
when "10" & x"e9c" => data <= x"0d";
when "10" & x"e9d" => data <= x"8d";
when "10" & x"e9e" => data <= x"24";
when "10" & x"e9f" => data <= x"0d";
when "10" & x"ea0" => data <= x"ad";
when "10" & x"ea1" => data <= x"25";
when "10" & x"ea2" => data <= x"0d";
when "10" & x"ea3" => data <= x"6d";
when "10" & x"ea4" => data <= x"08";
when "10" & x"ea5" => data <= x"0d";
when "10" & x"ea6" => data <= x"8d";
when "10" & x"ea7" => data <= x"25";
when "10" & x"ea8" => data <= x"0d";
when "10" & x"ea9" => data <= x"60";
when "10" & x"eaa" => data <= x"a5";
when "10" & x"eab" => data <= x"be";
when "10" & x"eac" => data <= x"85";
when "10" & x"ead" => data <= x"a0";
when "10" & x"eae" => data <= x"a5";
when "10" & x"eaf" => data <= x"bf";
when "10" & x"eb0" => data <= x"85";
when "10" & x"eb1" => data <= x"a1";
when "10" & x"eb2" => data <= x"a6";
when "10" & x"eb3" => data <= x"cf";
when "10" & x"eb4" => data <= x"20";
when "10" & x"eb5" => data <= x"1d";
when "10" & x"eb6" => data <= x"ae";
when "10" & x"eb7" => data <= x"18";
when "10" & x"eb8" => data <= x"a5";
when "10" & x"eb9" => data <= x"c4";
when "10" & x"eba" => data <= x"29";
when "10" & x"ebb" => data <= x"03";
when "10" & x"ebc" => data <= x"48";
when "10" & x"ebd" => data <= x"6a";
when "10" & x"ebe" => data <= x"48";
when "10" & x"ebf" => data <= x"a5";
when "10" & x"ec0" => data <= x"c5";
when "10" & x"ec1" => data <= x"6a";
when "10" & x"ec2" => data <= x"48";
when "10" & x"ec3" => data <= x"90";
when "10" & x"ec4" => data <= x"03";
when "10" & x"ec5" => data <= x"6e";
when "10" & x"ec6" => data <= x"28";
when "10" & x"ec7" => data <= x"0d";
when "10" & x"ec8" => data <= x"18";
when "10" & x"ec9" => data <= x"68";
when "10" & x"eca" => data <= x"6d";
when "10" & x"ecb" => data <= x"23";
when "10" & x"ecc" => data <= x"0d";
when "10" & x"ecd" => data <= x"8d";
when "10" & x"ece" => data <= x"23";
when "10" & x"ecf" => data <= x"0d";
when "10" & x"ed0" => data <= x"68";
when "10" & x"ed1" => data <= x"6d";
when "10" & x"ed2" => data <= x"24";
when "10" & x"ed3" => data <= x"0d";
when "10" & x"ed4" => data <= x"8d";
when "10" & x"ed5" => data <= x"24";
when "10" & x"ed6" => data <= x"0d";
when "10" & x"ed7" => data <= x"a9";
when "10" & x"ed8" => data <= x"00";
when "10" & x"ed9" => data <= x"6d";
when "10" & x"eda" => data <= x"25";
when "10" & x"edb" => data <= x"0d";
when "10" & x"edc" => data <= x"8d";
when "10" & x"edd" => data <= x"25";
when "10" & x"ede" => data <= x"0d";
when "10" & x"edf" => data <= x"a9";
when "10" & x"ee0" => data <= x"00";
when "10" & x"ee1" => data <= x"6d";
when "10" & x"ee2" => data <= x"26";
when "10" & x"ee3" => data <= x"0d";
when "10" & x"ee4" => data <= x"8d";
when "10" & x"ee5" => data <= x"26";
when "10" & x"ee6" => data <= x"0d";
when "10" & x"ee7" => data <= x"a5";
when "10" & x"ee8" => data <= x"c3";
when "10" & x"ee9" => data <= x"8d";
when "10" & x"eea" => data <= x"27";
when "10" & x"eeb" => data <= x"0d";
when "10" & x"eec" => data <= x"a5";
when "10" & x"eed" => data <= x"c4";
when "10" & x"eee" => data <= x"4a";
when "10" & x"eef" => data <= x"4a";
when "10" & x"ef0" => data <= x"4a";
when "10" & x"ef1" => data <= x"4a";
when "10" & x"ef2" => data <= x"29";
when "10" & x"ef3" => data <= x"03";
when "10" & x"ef4" => data <= x"d0";
when "10" & x"ef5" => data <= x"21";
when "10" & x"ef6" => data <= x"a5";
when "10" & x"ef7" => data <= x"c2";
when "10" & x"ef8" => data <= x"8d";
when "10" & x"ef9" => data <= x"29";
when "10" & x"efa" => data <= x"0d";
when "10" & x"efb" => data <= x"f0";
when "10" & x"efc" => data <= x"05";
when "10" & x"efd" => data <= x"ee";
when "10" & x"efe" => data <= x"27";
when "10" & x"eff" => data <= x"0d";
when "10" & x"f00" => data <= x"f0";
when "10" & x"f01" => data <= x"15";
when "10" & x"f02" => data <= x"18";
when "10" & x"f03" => data <= x"a5";
when "10" & x"f04" => data <= x"c5";
when "10" & x"f05" => data <= x"6d";
when "10" & x"f06" => data <= x"27";
when "10" & x"f07" => data <= x"0d";
when "10" & x"f08" => data <= x"aa";
when "10" & x"f09" => data <= x"68";
when "10" & x"f0a" => data <= x"69";
when "10" & x"f0b" => data <= x"00";
when "10" & x"f0c" => data <= x"c9";
when "10" & x"f0d" => data <= x"03";
when "10" & x"f0e" => data <= x"90";
when "10" & x"f0f" => data <= x"06";
when "10" & x"f10" => data <= x"d0";
when "10" & x"f11" => data <= x"17";
when "10" & x"f12" => data <= x"e0";
when "10" & x"f13" => data <= x"21";
when "10" & x"f14" => data <= x"b0";
when "10" & x"f15" => data <= x"13";
when "10" & x"f16" => data <= x"60";
when "10" & x"f17" => data <= x"20";
when "10" & x"f18" => data <= x"00";
when "10" & x"f19" => data <= x"a0";
when "10" & x"f1a" => data <= x"ff";
when "10" & x"f1b" => data <= x"42";
when "10" & x"f1c" => data <= x"6c";
when "10" & x"f1d" => data <= x"6f";
when "10" & x"f1e" => data <= x"63";
when "10" & x"f1f" => data <= x"6b";
when "10" & x"f20" => data <= x"20";
when "10" & x"f21" => data <= x"74";
when "10" & x"f22" => data <= x"6f";
when "10" & x"f23" => data <= x"6f";
when "10" & x"f24" => data <= x"20";
when "10" & x"f25" => data <= x"62";
when "10" & x"f26" => data <= x"69";
when "10" & x"f27" => data <= x"67";
when "10" & x"f28" => data <= x"00";
when "10" & x"f29" => data <= x"20";
when "10" & x"f2a" => data <= x"00";
when "10" & x"f2b" => data <= x"a0";
when "10" & x"f2c" => data <= x"ff";
when "10" & x"f2d" => data <= x"44";
when "10" & x"f2e" => data <= x"69";
when "10" & x"f2f" => data <= x"73";
when "10" & x"f30" => data <= x"6b";
when "10" & x"f31" => data <= x"20";
when "10" & x"f32" => data <= x"6f";
when "10" & x"f33" => data <= x"76";
when "10" & x"f34" => data <= x"65";
when "10" & x"f35" => data <= x"72";
when "10" & x"f36" => data <= x"66";
when "10" & x"f37" => data <= x"6c";
when "10" & x"f38" => data <= x"6f";
when "10" & x"f39" => data <= x"77";
when "10" & x"f3a" => data <= x"00";
when "10" & x"f3b" => data <= x"20";
when "10" & x"f3c" => data <= x"4d";
when "10" & x"f3d" => data <= x"83";
when "10" & x"f3e" => data <= x"20";
when "10" & x"f3f" => data <= x"58";
when "10" & x"f40" => data <= x"83";
when "10" & x"f41" => data <= x"20";
when "10" & x"f42" => data <= x"1f";
when "10" & x"f43" => data <= x"a6";
when "10" & x"f44" => data <= x"a6";
when "10" & x"f45" => data <= x"cf";
when "10" & x"f46" => data <= x"8e";
when "10" & x"f47" => data <= x"20";
when "10" & x"f48" => data <= x"0d";
when "10" & x"f49" => data <= x"20";
when "10" & x"f4a" => data <= x"1d";
when "10" & x"f4b" => data <= x"ae";
when "10" & x"f4c" => data <= x"20";
when "10" & x"f4d" => data <= x"99";
when "10" & x"f4e" => data <= x"a7";
when "10" & x"f4f" => data <= x"a5";
when "10" & x"f50" => data <= x"cf";
when "10" & x"f51" => data <= x"8d";
when "10" & x"f52" => data <= x"82";
when "10" & x"f53" => data <= x"10";
when "10" & x"f54" => data <= x"60";
when "10" & x"f55" => data <= x"20";
when "10" & x"f56" => data <= x"1f";
when "10" & x"f57" => data <= x"a6";
when "10" & x"f58" => data <= x"a6";
when "10" & x"f59" => data <= x"cf";
when "10" & x"f5a" => data <= x"20";
when "10" & x"f5b" => data <= x"cc";
when "10" & x"f5c" => data <= x"ad";
when "10" & x"f5d" => data <= x"20";
when "10" & x"f5e" => data <= x"1d";
when "10" & x"f5f" => data <= x"ae";
when "10" & x"f60" => data <= x"4c";
when "10" & x"f61" => data <= x"b2";
when "10" & x"f62" => data <= x"a7";
when "10" & x"f63" => data <= x"08";
when "10" & x"f64" => data <= x"48";
when "10" & x"f65" => data <= x"a0";
when "10" & x"f66" => data <= x"ff";
when "10" & x"f67" => data <= x"8c";
when "10" & x"f68" => data <= x"82";
when "10" & x"f69" => data <= x"10";
when "10" & x"f6a" => data <= x"c8";
when "10" & x"f6b" => data <= x"98";
when "10" & x"f6c" => data <= x"99";
when "10" & x"f6d" => data <= x"00";
when "10" & x"f6e" => data <= x"0e";
when "10" & x"f6f" => data <= x"99";
when "10" & x"f70" => data <= x"00";
when "10" & x"f71" => data <= x"0f";
when "10" & x"f72" => data <= x"c8";
when "10" & x"f73" => data <= x"d0";
when "10" & x"f74" => data <= x"f7";
when "10" & x"f75" => data <= x"a9";
when "10" & x"f76" => data <= x"03";
when "10" & x"f77" => data <= x"8d";
when "10" & x"f78" => data <= x"06";
when "10" & x"f79" => data <= x"0f";
when "10" & x"f7a" => data <= x"a9";
when "10" & x"f7b" => data <= x"20";
when "10" & x"f7c" => data <= x"8d";
when "10" & x"f7d" => data <= x"07";
when "10" & x"f7e" => data <= x"0f";
when "10" & x"f7f" => data <= x"20";
when "10" & x"f80" => data <= x"1f";
when "10" & x"f81" => data <= x"a6";
when "10" & x"f82" => data <= x"68";
when "10" & x"f83" => data <= x"28";
when "10" & x"f84" => data <= x"20";
when "10" & x"f85" => data <= x"26";
when "10" & x"f86" => data <= x"ae";
when "10" & x"f87" => data <= x"4c";
when "10" & x"f88" => data <= x"b2";
when "10" & x"f89" => data <= x"a7";
when "10" & x"f8a" => data <= x"20";
when "10" & x"f8b" => data <= x"1f";
when "10" & x"f8c" => data <= x"a6";
when "10" & x"f8d" => data <= x"20";
when "10" & x"f8e" => data <= x"aa";
when "10" & x"f8f" => data <= x"ae";
when "10" & x"f90" => data <= x"20";
when "10" & x"f91" => data <= x"cc";
when "10" & x"f92" => data <= x"a7";
when "10" & x"f93" => data <= x"20";
when "10" & x"f94" => data <= x"cd";
when "10" & x"f95" => data <= x"a0";
when "10" & x"f96" => data <= x"a9";
when "10" & x"f97" => data <= x"01";
when "10" & x"f98" => data <= x"60";
when "10" & x"f99" => data <= x"20";
when "10" & x"f9a" => data <= x"1f";
when "10" & x"f9b" => data <= x"a6";
when "10" & x"f9c" => data <= x"20";
when "10" & x"f9d" => data <= x"aa";
when "10" & x"f9e" => data <= x"ae";
when "10" & x"f9f" => data <= x"a6";
when "10" & x"fa0" => data <= x"cf";
when "10" & x"fa1" => data <= x"20";
when "10" & x"fa2" => data <= x"cc";
when "10" & x"fa3" => data <= x"ad";
when "10" & x"fa4" => data <= x"20";
when "10" & x"fa5" => data <= x"78";
when "10" & x"fa6" => data <= x"a8";
when "10" & x"fa7" => data <= x"20";
when "10" & x"fa8" => data <= x"cd";
when "10" & x"fa9" => data <= x"a0";
when "10" & x"faa" => data <= x"a9";
when "10" & x"fab" => data <= x"01";
when "10" & x"fac" => data <= x"60";
when "10" & x"fad" => data <= x"a8";
when "10" & x"fae" => data <= x"c8";
when "10" & x"faf" => data <= x"98";
when "10" & x"fb0" => data <= x"d0";
when "10" & x"fb1" => data <= x"01";
when "10" & x"fb2" => data <= x"38";
when "10" & x"fb3" => data <= x"2a";
when "10" & x"fb4" => data <= x"2a";
when "10" & x"fb5" => data <= x"2a";
when "10" & x"fb6" => data <= x"2a";
when "10" & x"fb7" => data <= x"2a";
when "10" & x"fb8" => data <= x"48";
when "10" & x"fb9" => data <= x"29";
when "10" & x"fba" => data <= x"1f";
when "10" & x"fbb" => data <= x"a8";
when "10" & x"fbc" => data <= x"68";
when "10" & x"fbd" => data <= x"09";
when "10" & x"fbe" => data <= x"1f";
when "10" & x"fbf" => data <= x"6a";
when "10" & x"fc0" => data <= x"60";
when "10" & x"fc1" => data <= x"20";
when "10" & x"fc2" => data <= x"ad";
when "10" & x"fc3" => data <= x"af";
when "10" & x"fc4" => data <= x"48";
when "10" & x"fc5" => data <= x"8a";
when "10" & x"fc6" => data <= x"48";
when "10" & x"fc7" => data <= x"98";
when "10" & x"fc8" => data <= x"48";
when "10" & x"fc9" => data <= x"20";
when "10" & x"fca" => data <= x"97";
when "10" & x"fcb" => data <= x"b0";
when "10" & x"fcc" => data <= x"68";
when "10" & x"fcd" => data <= x"6a";
when "10" & x"fce" => data <= x"68";
when "10" & x"fcf" => data <= x"aa";
when "10" & x"fd0" => data <= x"68";
when "10" & x"fd1" => data <= x"a8";
when "10" & x"fd2" => data <= x"b0";
when "10" & x"fd3" => data <= x"04";
when "10" & x"fd4" => data <= x"b9";
when "10" & x"fd5" => data <= x"00";
when "10" & x"fd6" => data <= x"0e";
when "10" & x"fd7" => data <= x"60";
when "10" & x"fd8" => data <= x"b9";
when "10" & x"fd9" => data <= x"00";
when "10" & x"fda" => data <= x"0f";
when "10" & x"fdb" => data <= x"60";
when "10" & x"fdc" => data <= x"08";
when "10" & x"fdd" => data <= x"48";
when "10" & x"fde" => data <= x"8d";
when "10" & x"fdf" => data <= x"5f";
when "10" & x"fe0" => data <= x"0d";
when "10" & x"fe1" => data <= x"a9";
when "10" & x"fe2" => data <= x"00";
when "10" & x"fe3" => data <= x"2a";
when "10" & x"fe4" => data <= x"8d";
when "10" & x"fe5" => data <= x"60";
when "10" & x"fe6" => data <= x"0d";
when "10" & x"fe7" => data <= x"8e";
when "10" & x"fe8" => data <= x"61";
when "10" & x"fe9" => data <= x"0d";
when "10" & x"fea" => data <= x"a2";
when "10" & x"feb" => data <= x"03";
when "10" & x"fec" => data <= x"ec";
when "10" & x"fed" => data <= x"61";
when "10" & x"fee" => data <= x"0d";
when "10" & x"fef" => data <= x"f0";
when "10" & x"ff0" => data <= x"15";
when "10" & x"ff1" => data <= x"bd";
when "10" & x"ff2" => data <= x"0c";
when "10" & x"ff3" => data <= x"0d";
when "10" & x"ff4" => data <= x"cd";
when "10" & x"ff5" => data <= x"5f";
when "10" & x"ff6" => data <= x"0d";
when "10" & x"ff7" => data <= x"d0";
when "10" & x"ff8" => data <= x"0d";
when "10" & x"ff9" => data <= x"bd";
when "10" & x"ffa" => data <= x"10";
when "10" & x"ffb" => data <= x"0d";
when "10" & x"ffc" => data <= x"cd";
when "10" & x"ffd" => data <= x"60";
when "10" & x"ffe" => data <= x"0d";
when "10" & x"fff" => data <= x"d0";
when "11" & x"000" => data <= x"05";
when "11" & x"001" => data <= x"a9";
when "11" & x"002" => data <= x"ff";
when "11" & x"003" => data <= x"9d";
when "11" & x"004" => data <= x"10";
when "11" & x"005" => data <= x"0d";
when "11" & x"006" => data <= x"ca";
when "11" & x"007" => data <= x"10";
when "11" & x"008" => data <= x"e3";
when "11" & x"009" => data <= x"ae";
when "11" & x"00a" => data <= x"61";
when "11" & x"00b" => data <= x"0d";
when "11" & x"00c" => data <= x"68";
when "11" & x"00d" => data <= x"28";
when "11" & x"00e" => data <= x"60";
when "11" & x"00f" => data <= x"08";
when "11" & x"010" => data <= x"48";
when "11" & x"011" => data <= x"9d";
when "11" & x"012" => data <= x"0c";
when "11" & x"013" => data <= x"0d";
when "11" & x"014" => data <= x"49";
when "11" & x"015" => data <= x"ff";
when "11" & x"016" => data <= x"9d";
when "11" & x"017" => data <= x"14";
when "11" & x"018" => data <= x"0d";
when "11" & x"019" => data <= x"a9";
when "11" & x"01a" => data <= x"00";
when "11" & x"01b" => data <= x"2a";
when "11" & x"01c" => data <= x"9d";
when "11" & x"01d" => data <= x"10";
when "11" & x"01e" => data <= x"0d";
when "11" & x"01f" => data <= x"49";
when "11" & x"020" => data <= x"ff";
when "11" & x"021" => data <= x"9d";
when "11" & x"022" => data <= x"18";
when "11" & x"023" => data <= x"0d";
when "11" & x"024" => data <= x"68";
when "11" & x"025" => data <= x"28";
when "11" & x"026" => data <= x"20";
when "11" & x"027" => data <= x"dc";
when "11" & x"028" => data <= x"af";
when "11" & x"029" => data <= x"20";
when "11" & x"02a" => data <= x"c1";
when "11" & x"02b" => data <= x"af";
when "11" & x"02c" => data <= x"30";
when "11" & x"02d" => data <= x"08";
when "11" & x"02e" => data <= x"f0";
when "11" & x"02f" => data <= x"03";
when "11" & x"030" => data <= x"4c";
when "11" & x"031" => data <= x"11";
when "11" & x"032" => data <= x"ae";
when "11" & x"033" => data <= x"4c";
when "11" & x"034" => data <= x"17";
when "11" & x"035" => data <= x"ae";
when "11" & x"036" => data <= x"a8";
when "11" & x"037" => data <= x"a9";
when "11" & x"038" => data <= x"ff";
when "11" & x"039" => data <= x"9d";
when "11" & x"03a" => data <= x"10";
when "11" & x"03b" => data <= x"0d";
when "11" & x"03c" => data <= x"c8";
when "11" & x"03d" => data <= x"d0";
when "11" & x"03e" => data <= x"1a";
when "11" & x"03f" => data <= x"20";
when "11" & x"040" => data <= x"00";
when "11" & x"041" => data <= x"a0";
when "11" & x"042" => data <= x"c7";
when "11" & x"043" => data <= x"44";
when "11" & x"044" => data <= x"69";
when "11" & x"045" => data <= x"73";
when "11" & x"046" => data <= x"6b";
when "11" & x"047" => data <= x"20";
when "11" & x"048" => data <= x"6e";
when "11" & x"049" => data <= x"75";
when "11" & x"04a" => data <= x"6d";
when "11" & x"04b" => data <= x"62";
when "11" & x"04c" => data <= x"65";
when "11" & x"04d" => data <= x"72";
when "11" & x"04e" => data <= x"20";
when "11" & x"04f" => data <= x"6e";
when "11" & x"050" => data <= x"6f";
when "11" & x"051" => data <= x"74";
when "11" & x"052" => data <= x"20";
when "11" & x"053" => data <= x"76";
when "11" & x"054" => data <= x"61";
when "11" & x"055" => data <= x"6c";
when "11" & x"056" => data <= x"69";
when "11" & x"057" => data <= x"64";
when "11" & x"058" => data <= x"00";
when "11" & x"059" => data <= x"20";
when "11" & x"05a" => data <= x"00";
when "11" & x"05b" => data <= x"a0";
when "11" & x"05c" => data <= x"c7";
when "11" & x"05d" => data <= x"44";
when "11" & x"05e" => data <= x"69";
when "11" & x"05f" => data <= x"73";
when "11" & x"060" => data <= x"6b";
when "11" & x"061" => data <= x"20";
when "11" & x"062" => data <= x"6e";
when "11" & x"063" => data <= x"6f";
when "11" & x"064" => data <= x"74";
when "11" & x"065" => data <= x"20";
when "11" & x"066" => data <= x"66";
when "11" & x"067" => data <= x"6f";
when "11" & x"068" => data <= x"72";
when "11" & x"069" => data <= x"6d";
when "11" & x"06a" => data <= x"61";
when "11" & x"06b" => data <= x"74";
when "11" & x"06c" => data <= x"74";
when "11" & x"06d" => data <= x"65";
when "11" & x"06e" => data <= x"64";
when "11" & x"06f" => data <= x"00";
when "11" & x"070" => data <= x"29";
when "11" & x"071" => data <= x"7f";
when "11" & x"072" => data <= x"48";
when "11" & x"073" => data <= x"20";
when "11" & x"074" => data <= x"a7";
when "11" & x"075" => data <= x"aa";
when "11" & x"076" => data <= x"18";
when "11" & x"077" => data <= x"68";
when "11" & x"078" => data <= x"6d";
when "11" & x"079" => data <= x"06";
when "11" & x"07a" => data <= x"0d";
when "11" & x"07b" => data <= x"8d";
when "11" & x"07c" => data <= x"23";
when "11" & x"07d" => data <= x"0d";
when "11" & x"07e" => data <= x"ad";
when "11" & x"07f" => data <= x"07";
when "11" & x"080" => data <= x"0d";
when "11" & x"081" => data <= x"69";
when "11" & x"082" => data <= x"00";
when "11" & x"083" => data <= x"8d";
when "11" & x"084" => data <= x"24";
when "11" & x"085" => data <= x"0d";
when "11" & x"086" => data <= x"ad";
when "11" & x"087" => data <= x"08";
when "11" & x"088" => data <= x"0d";
when "11" & x"089" => data <= x"69";
when "11" & x"08a" => data <= x"00";
when "11" & x"08b" => data <= x"8d";
when "11" & x"08c" => data <= x"25";
when "11" & x"08d" => data <= x"0d";
when "11" & x"08e" => data <= x"ad";
when "11" & x"08f" => data <= x"09";
when "11" & x"090" => data <= x"0d";
when "11" & x"091" => data <= x"69";
when "11" & x"092" => data <= x"00";
when "11" & x"093" => data <= x"8d";
when "11" & x"094" => data <= x"26";
when "11" & x"095" => data <= x"0d";
when "11" & x"096" => data <= x"60";
when "11" & x"097" => data <= x"29";
when "11" & x"098" => data <= x"fe";
when "11" & x"099" => data <= x"4a";
when "11" & x"09a" => data <= x"09";
when "11" & x"09b" => data <= x"80";
when "11" & x"09c" => data <= x"cd";
when "11" & x"09d" => data <= x"82";
when "11" & x"09e" => data <= x"10";
when "11" & x"09f" => data <= x"f0";
when "11" & x"0a0" => data <= x"f5";
when "11" & x"0a1" => data <= x"8d";
when "11" & x"0a2" => data <= x"82";
when "11" & x"0a3" => data <= x"10";
when "11" & x"0a4" => data <= x"48";
when "11" & x"0a5" => data <= x"20";
when "11" & x"0a6" => data <= x"1f";
when "11" & x"0a7" => data <= x"a6";
when "11" & x"0a8" => data <= x"68";
when "11" & x"0a9" => data <= x"20";
when "11" & x"0aa" => data <= x"70";
when "11" & x"0ab" => data <= x"b0";
when "11" & x"0ac" => data <= x"4c";
when "11" & x"0ad" => data <= x"99";
when "11" & x"0ae" => data <= x"a7";
when "11" & x"0af" => data <= x"8d";
when "11" & x"0b0" => data <= x"82";
when "11" & x"0b1" => data <= x"10";
when "11" & x"0b2" => data <= x"20";
when "11" & x"0b3" => data <= x"70";
when "11" & x"0b4" => data <= x"b0";
when "11" & x"0b5" => data <= x"4c";
when "11" & x"0b6" => data <= x"99";
when "11" & x"0b7" => data <= x"a7";
when "11" & x"0b8" => data <= x"20";
when "11" & x"0b9" => data <= x"1f";
when "11" & x"0ba" => data <= x"a6";
when "11" & x"0bb" => data <= x"ad";
when "11" & x"0bc" => data <= x"82";
when "11" & x"0bd" => data <= x"10";
when "11" & x"0be" => data <= x"20";
when "11" & x"0bf" => data <= x"70";
when "11" & x"0c0" => data <= x"b0";
when "11" & x"0c1" => data <= x"4c";
when "11" & x"0c2" => data <= x"b2";
when "11" & x"0c3" => data <= x"a7";
when "11" & x"0c4" => data <= x"ad";
when "11" & x"0c5" => data <= x"82";
when "11" & x"0c6" => data <= x"10";
when "11" & x"0c7" => data <= x"20";
when "11" & x"0c8" => data <= x"70";
when "11" & x"0c9" => data <= x"b0";
when "11" & x"0ca" => data <= x"4c";
when "11" & x"0cb" => data <= x"b2";
when "11" & x"0cc" => data <= x"a7";
when "11" & x"0cd" => data <= x"20";
when "11" & x"0ce" => data <= x"b8";
when "11" & x"0cf" => data <= x"b0";
when "11" & x"0d0" => data <= x"a2";
when "11" & x"0d1" => data <= x"03";
when "11" & x"0d2" => data <= x"20";
when "11" & x"0d3" => data <= x"d9";
when "11" & x"0d4" => data <= x"b0";
when "11" & x"0d5" => data <= x"ca";
when "11" & x"0d6" => data <= x"10";
when "11" & x"0d7" => data <= x"fa";
when "11" & x"0d8" => data <= x"60";
when "11" & x"0d9" => data <= x"bd";
when "11" & x"0da" => data <= x"10";
when "11" & x"0db" => data <= x"0d";
when "11" & x"0dc" => data <= x"30";
when "11" & x"0dd" => data <= x"2b";
when "11" & x"0de" => data <= x"49";
when "11" & x"0df" => data <= x"ff";
when "11" & x"0e0" => data <= x"dd";
when "11" & x"0e1" => data <= x"18";
when "11" & x"0e2" => data <= x"0d";
when "11" & x"0e3" => data <= x"d0";
when "11" & x"0e4" => data <= x"18";
when "11" & x"0e5" => data <= x"bd";
when "11" & x"0e6" => data <= x"0c";
when "11" & x"0e7" => data <= x"0d";
when "11" & x"0e8" => data <= x"49";
when "11" & x"0e9" => data <= x"ff";
when "11" & x"0ea" => data <= x"dd";
when "11" & x"0eb" => data <= x"14";
when "11" & x"0ec" => data <= x"0d";
when "11" & x"0ed" => data <= x"d0";
when "11" & x"0ee" => data <= x"0e";
when "11" & x"0ef" => data <= x"bd";
when "11" & x"0f0" => data <= x"10";
when "11" & x"0f1" => data <= x"0d";
when "11" & x"0f2" => data <= x"6a";
when "11" & x"0f3" => data <= x"bd";
when "11" & x"0f4" => data <= x"0c";
when "11" & x"0f5" => data <= x"0d";
when "11" & x"0f6" => data <= x"20";
when "11" & x"0f7" => data <= x"c1";
when "11" & x"0f8" => data <= x"af";
when "11" & x"0f9" => data <= x"f0";
when "11" & x"0fa" => data <= x"0b";
when "11" & x"0fb" => data <= x"10";
when "11" & x"0fc" => data <= x"07";
when "11" & x"0fd" => data <= x"a9";
when "11" & x"0fe" => data <= x"ff";
when "11" & x"0ff" => data <= x"9d";
when "11" & x"100" => data <= x"10";
when "11" & x"101" => data <= x"0d";
when "11" & x"102" => data <= x"d0";
when "11" & x"103" => data <= x"02";
when "11" & x"104" => data <= x"a9";
when "11" & x"105" => data <= x"54";
when "11" & x"106" => data <= x"9d";
when "11" & x"107" => data <= x"1c";
when "11" & x"108" => data <= x"0d";
when "11" & x"109" => data <= x"60";
when "11" & x"10a" => data <= x"a2";
when "11" & x"10b" => data <= x"00";
when "11" & x"10c" => data <= x"bd";
when "11" & x"10d" => data <= x"20";
when "11" & x"10e" => data <= x"b3";
when "11" & x"10f" => data <= x"9d";
when "11" & x"110" => data <= x"70";
when "11" & x"111" => data <= x"0d";
when "11" & x"112" => data <= x"e8";
when "11" & x"113" => data <= x"e0";
when "11" & x"114" => data <= x"0b";
when "11" & x"115" => data <= x"d0";
when "11" & x"116" => data <= x"f5";
when "11" & x"117" => data <= x"60";
when "11" & x"118" => data <= x"a2";
when "11" & x"119" => data <= x"6f";
when "11" & x"11a" => data <= x"a9";
when "11" & x"11b" => data <= x"00";
when "11" & x"11c" => data <= x"9d";
when "11" & x"11d" => data <= x"00";
when "11" & x"11e" => data <= x"0d";
when "11" & x"11f" => data <= x"ca";
when "11" & x"120" => data <= x"d0";
when "11" & x"121" => data <= x"fa";
when "11" & x"122" => data <= x"a9";
when "11" & x"123" => data <= x"40";
when "11" & x"124" => data <= x"9d";
when "11" & x"125" => data <= x"00";
when "11" & x"126" => data <= x"0d";
when "11" & x"127" => data <= x"60";
when "11" & x"128" => data <= x"20";
when "11" & x"129" => data <= x"0a";
when "11" & x"12a" => data <= x"b1";
when "11" & x"12b" => data <= x"20";
when "11" & x"12c" => data <= x"18";
when "11" & x"12d" => data <= x"b1";
when "11" & x"12e" => data <= x"a9";
when "11" & x"12f" => data <= x"ff";
when "11" & x"130" => data <= x"8d";
when "11" & x"131" => data <= x"52";
when "11" & x"132" => data <= x"0d";
when "11" & x"133" => data <= x"48";
when "11" & x"134" => data <= x"4c";
when "11" & x"135" => data <= x"3b";
when "11" & x"136" => data <= x"93";
when "11" & x"137" => data <= x"20";
when "11" & x"138" => data <= x"0a";
when "11" & x"139" => data <= x"b1";
when "11" & x"13a" => data <= x"20";
when "11" & x"13b" => data <= x"18";
when "11" & x"13c" => data <= x"b1";
when "11" & x"13d" => data <= x"a9";
when "11" & x"13e" => data <= x"80";
when "11" & x"13f" => data <= x"20";
when "11" & x"140" => data <= x"a1";
when "11" & x"141" => data <= x"b0";
when "11" & x"142" => data <= x"a2";
when "11" & x"143" => data <= x"00";
when "11" & x"144" => data <= x"ad";
when "11" & x"145" => data <= x"52";
when "11" & x"146" => data <= x"0d";
when "11" & x"147" => data <= x"c9";
when "11" & x"148" => data <= x"42";
when "11" & x"149" => data <= x"f0";
when "11" & x"14a" => data <= x"16";
when "11" & x"14b" => data <= x"bd";
when "11" & x"14c" => data <= x"10";
when "11" & x"14d" => data <= x"0d";
when "11" & x"14e" => data <= x"30";
when "11" & x"14f" => data <= x"43";
when "11" & x"150" => data <= x"49";
when "11" & x"151" => data <= x"ff";
when "11" & x"152" => data <= x"dd";
when "11" & x"153" => data <= x"18";
when "11" & x"154" => data <= x"0d";
when "11" & x"155" => data <= x"d0";
when "11" & x"156" => data <= x"0a";
when "11" & x"157" => data <= x"bd";
when "11" & x"158" => data <= x"0c";
when "11" & x"159" => data <= x"0d";
when "11" & x"15a" => data <= x"49";
when "11" & x"15b" => data <= x"ff";
when "11" & x"15c" => data <= x"dd";
when "11" & x"15d" => data <= x"14";
when "11" & x"15e" => data <= x"0d";
when "11" & x"15f" => data <= x"f0";
when "11" & x"160" => data <= x"16";
when "11" & x"161" => data <= x"bd";
when "11" & x"162" => data <= x"00";
when "11" & x"163" => data <= x"0e";
when "11" & x"164" => data <= x"9d";
when "11" & x"165" => data <= x"0c";
when "11" & x"166" => data <= x"0d";
when "11" & x"167" => data <= x"49";
when "11" & x"168" => data <= x"ff";
when "11" & x"169" => data <= x"9d";
when "11" & x"16a" => data <= x"14";
when "11" & x"16b" => data <= x"0d";
when "11" & x"16c" => data <= x"bd";
when "11" & x"16d" => data <= x"04";
when "11" & x"16e" => data <= x"0e";
when "11" & x"16f" => data <= x"9d";
when "11" & x"170" => data <= x"10";
when "11" & x"171" => data <= x"0d";
when "11" & x"172" => data <= x"49";
when "11" & x"173" => data <= x"ff";
when "11" & x"174" => data <= x"9d";
when "11" & x"175" => data <= x"18";
when "11" & x"176" => data <= x"0d";
when "11" & x"177" => data <= x"8a";
when "11" & x"178" => data <= x"f0";
when "11" & x"179" => data <= x"1e";
when "11" & x"17a" => data <= x"a8";
when "11" & x"17b" => data <= x"88";
when "11" & x"17c" => data <= x"bd";
when "11" & x"17d" => data <= x"10";
when "11" & x"17e" => data <= x"0d";
when "11" & x"17f" => data <= x"30";
when "11" & x"180" => data <= x"17";
when "11" & x"181" => data <= x"d9";
when "11" & x"182" => data <= x"10";
when "11" & x"183" => data <= x"0d";
when "11" & x"184" => data <= x"d0";
when "11" & x"185" => data <= x"08";
when "11" & x"186" => data <= x"bd";
when "11" & x"187" => data <= x"0c";
when "11" & x"188" => data <= x"0d";
when "11" & x"189" => data <= x"d9";
when "11" & x"18a" => data <= x"0c";
when "11" & x"18b" => data <= x"0d";
when "11" & x"18c" => data <= x"f0";
when "11" & x"18d" => data <= x"05";
when "11" & x"18e" => data <= x"88";
when "11" & x"18f" => data <= x"10";
when "11" & x"190" => data <= x"eb";
when "11" & x"191" => data <= x"30";
when "11" & x"192" => data <= x"05";
when "11" & x"193" => data <= x"a9";
when "11" & x"194" => data <= x"ff";
when "11" & x"195" => data <= x"9d";
when "11" & x"196" => data <= x"10";
when "11" & x"197" => data <= x"0d";
when "11" & x"198" => data <= x"e8";
when "11" & x"199" => data <= x"e0";
when "11" & x"19a" => data <= x"04";
when "11" & x"19b" => data <= x"d0";
when "11" & x"19c" => data <= x"a7";
when "11" & x"19d" => data <= x"4c";
when "11" & x"19e" => data <= x"d0";
when "11" & x"19f" => data <= x"b0";
when "11" & x"1a0" => data <= x"08";
when "11" & x"1a1" => data <= x"48";
when "11" & x"1a2" => data <= x"8d";
when "11" & x"1a3" => data <= x"53";
when "11" & x"1a4" => data <= x"0d";
when "11" & x"1a5" => data <= x"a9";
when "11" & x"1a6" => data <= x"00";
when "11" & x"1a7" => data <= x"2a";
when "11" & x"1a8" => data <= x"8d";
when "11" & x"1a9" => data <= x"54";
when "11" & x"1aa" => data <= x"0d";
when "11" & x"1ab" => data <= x"68";
when "11" & x"1ac" => data <= x"28";
when "11" & x"1ad" => data <= x"08";
when "11" & x"1ae" => data <= x"48";
when "11" & x"1af" => data <= x"20";
when "11" & x"1b0" => data <= x"6c";
when "11" & x"1b1" => data <= x"ad";
when "11" & x"1b2" => data <= x"8e";
when "11" & x"1b3" => data <= x"55";
when "11" & x"1b4" => data <= x"0d";
when "11" & x"1b5" => data <= x"8d";
when "11" & x"1b6" => data <= x"56";
when "11" & x"1b7" => data <= x"0d";
when "11" & x"1b8" => data <= x"68";
when "11" & x"1b9" => data <= x"28";
when "11" & x"1ba" => data <= x"20";
when "11" & x"1bb" => data <= x"ad";
when "11" & x"1bc" => data <= x"af";
when "11" & x"1bd" => data <= x"29";
when "11" & x"1be" => data <= x"f0";
when "11" & x"1bf" => data <= x"85";
when "11" & x"1c0" => data <= x"f2";
when "11" & x"1c1" => data <= x"98";
when "11" & x"1c2" => data <= x"29";
when "11" & x"1c3" => data <= x"01";
when "11" & x"1c4" => data <= x"09";
when "11" & x"1c5" => data <= x"0e";
when "11" & x"1c6" => data <= x"85";
when "11" & x"1c7" => data <= x"f3";
when "11" & x"1c8" => data <= x"98";
when "11" & x"1c9" => data <= x"29";
when "11" & x"1ca" => data <= x"fe";
when "11" & x"1cb" => data <= x"4a";
when "11" & x"1cc" => data <= x"09";
when "11" & x"1cd" => data <= x"80";
when "11" & x"1ce" => data <= x"8d";
when "11" & x"1cf" => data <= x"52";
when "11" & x"1d0" => data <= x"0d";
when "11" & x"1d1" => data <= x"20";
when "11" & x"1d2" => data <= x"9c";
when "11" & x"1d3" => data <= x"b0";
when "11" & x"1d4" => data <= x"4c";
when "11" & x"1d5" => data <= x"35";
when "11" & x"1d6" => data <= x"b2";
when "11" & x"1d7" => data <= x"a9";
when "11" & x"1d8" => data <= x"00";
when "11" & x"1d9" => data <= x"8d";
when "11" & x"1da" => data <= x"55";
when "11" & x"1db" => data <= x"0d";
when "11" & x"1dc" => data <= x"8d";
when "11" & x"1dd" => data <= x"56";
when "11" & x"1de" => data <= x"0d";
when "11" & x"1df" => data <= x"8d";
when "11" & x"1e0" => data <= x"53";
when "11" & x"1e1" => data <= x"0d";
when "11" & x"1e2" => data <= x"8d";
when "11" & x"1e3" => data <= x"54";
when "11" & x"1e4" => data <= x"0d";
when "11" & x"1e5" => data <= x"a9";
when "11" & x"1e6" => data <= x"10";
when "11" & x"1e7" => data <= x"85";
when "11" & x"1e8" => data <= x"f2";
when "11" & x"1e9" => data <= x"a9";
when "11" & x"1ea" => data <= x"0e";
when "11" & x"1eb" => data <= x"85";
when "11" & x"1ec" => data <= x"f3";
when "11" & x"1ed" => data <= x"a9";
when "11" & x"1ee" => data <= x"80";
when "11" & x"1ef" => data <= x"8d";
when "11" & x"1f0" => data <= x"52";
when "11" & x"1f1" => data <= x"0d";
when "11" & x"1f2" => data <= x"20";
when "11" & x"1f3" => data <= x"9c";
when "11" & x"1f4" => data <= x"b0";
when "11" & x"1f5" => data <= x"4c";
when "11" & x"1f6" => data <= x"35";
when "11" & x"1f7" => data <= x"b2";
when "11" & x"1f8" => data <= x"c9";
when "11" & x"1f9" => data <= x"ff";
when "11" & x"1fa" => data <= x"f0";
when "11" & x"1fb" => data <= x"41";
when "11" & x"1fc" => data <= x"18";
when "11" & x"1fd" => data <= x"a5";
when "11" & x"1fe" => data <= x"f2";
when "11" & x"1ff" => data <= x"69";
when "11" & x"200" => data <= x"10";
when "11" & x"201" => data <= x"85";
when "11" & x"202" => data <= x"f2";
when "11" & x"203" => data <= x"d0";
when "11" & x"204" => data <= x"18";
when "11" & x"205" => data <= x"a5";
when "11" & x"206" => data <= x"f3";
when "11" & x"207" => data <= x"49";
when "11" & x"208" => data <= x"01";
when "11" & x"209" => data <= x"85";
when "11" & x"20a" => data <= x"f3";
when "11" & x"20b" => data <= x"6a";
when "11" & x"20c" => data <= x"b0";
when "11" & x"20d" => data <= x"0f";
when "11" & x"20e" => data <= x"ad";
when "11" & x"20f" => data <= x"52";
when "11" & x"210" => data <= x"0d";
when "11" & x"211" => data <= x"69";
when "11" & x"212" => data <= x"01";
when "11" & x"213" => data <= x"c9";
when "11" & x"214" => data <= x"90";
when "11" & x"215" => data <= x"f0";
when "11" & x"216" => data <= x"26";
when "11" & x"217" => data <= x"8d";
when "11" & x"218" => data <= x"52";
when "11" & x"219" => data <= x"0d";
when "11" & x"21a" => data <= x"20";
when "11" & x"21b" => data <= x"9c";
when "11" & x"21c" => data <= x"b0";
when "11" & x"21d" => data <= x"ee";
when "11" & x"21e" => data <= x"53";
when "11" & x"21f" => data <= x"0d";
when "11" & x"220" => data <= x"d0";
when "11" & x"221" => data <= x"03";
when "11" & x"222" => data <= x"ee";
when "11" & x"223" => data <= x"54";
when "11" & x"224" => data <= x"0d";
when "11" & x"225" => data <= x"f8";
when "11" & x"226" => data <= x"18";
when "11" & x"227" => data <= x"ad";
when "11" & x"228" => data <= x"55";
when "11" & x"229" => data <= x"0d";
when "11" & x"22a" => data <= x"69";
when "11" & x"22b" => data <= x"01";
when "11" & x"22c" => data <= x"8d";
when "11" & x"22d" => data <= x"55";
when "11" & x"22e" => data <= x"0d";
when "11" & x"22f" => data <= x"90";
when "11" & x"230" => data <= x"03";
when "11" & x"231" => data <= x"ee";
when "11" & x"232" => data <= x"56";
when "11" & x"233" => data <= x"0d";
when "11" & x"234" => data <= x"d8";
when "11" & x"235" => data <= x"a0";
when "11" & x"236" => data <= x"0f";
when "11" & x"237" => data <= x"b1";
when "11" & x"238" => data <= x"f2";
when "11" & x"239" => data <= x"30";
when "11" & x"23a" => data <= x"bd";
when "11" & x"23b" => data <= x"18";
when "11" & x"23c" => data <= x"60";
when "11" & x"23d" => data <= x"a9";
when "11" & x"23e" => data <= x"ff";
when "11" & x"23f" => data <= x"8d";
when "11" & x"240" => data <= x"54";
when "11" & x"241" => data <= x"0d";
when "11" & x"242" => data <= x"38";
when "11" & x"243" => data <= x"60";
when "11" & x"244" => data <= x"20";
when "11" & x"245" => data <= x"1f";
when "11" & x"246" => data <= x"a6";
when "11" & x"247" => data <= x"a9";
when "11" & x"248" => data <= x"80";
when "11" & x"249" => data <= x"8d";
when "11" & x"24a" => data <= x"52";
when "11" & x"24b" => data <= x"0d";
when "11" & x"24c" => data <= x"20";
when "11" & x"24d" => data <= x"af";
when "11" & x"24e" => data <= x"b0";
when "11" & x"24f" => data <= x"a9";
when "11" & x"250" => data <= x"10";
when "11" & x"251" => data <= x"85";
when "11" & x"252" => data <= x"f2";
when "11" & x"253" => data <= x"a9";
when "11" & x"254" => data <= x"0e";
when "11" & x"255" => data <= x"85";
when "11" & x"256" => data <= x"f3";
when "11" & x"257" => data <= x"20";
when "11" & x"258" => data <= x"a7";
when "11" & x"259" => data <= x"aa";
when "11" & x"25a" => data <= x"18";
when "11" & x"25b" => data <= x"ad";
when "11" & x"25c" => data <= x"06";
when "11" & x"25d" => data <= x"0d";
when "11" & x"25e" => data <= x"69";
when "11" & x"25f" => data <= x"10";
when "11" & x"260" => data <= x"8d";
when "11" & x"261" => data <= x"23";
when "11" & x"262" => data <= x"0d";
when "11" & x"263" => data <= x"ad";
when "11" & x"264" => data <= x"07";
when "11" & x"265" => data <= x"0d";
when "11" & x"266" => data <= x"69";
when "11" & x"267" => data <= x"00";
when "11" & x"268" => data <= x"8d";
when "11" & x"269" => data <= x"24";
when "11" & x"26a" => data <= x"0d";
when "11" & x"26b" => data <= x"ad";
when "11" & x"26c" => data <= x"08";
when "11" & x"26d" => data <= x"0d";
when "11" & x"26e" => data <= x"69";
when "11" & x"26f" => data <= x"00";
when "11" & x"270" => data <= x"8d";
when "11" & x"271" => data <= x"25";
when "11" & x"272" => data <= x"0d";
when "11" & x"273" => data <= x"ad";
when "11" & x"274" => data <= x"09";
when "11" & x"275" => data <= x"0d";
when "11" & x"276" => data <= x"69";
when "11" & x"277" => data <= x"00";
when "11" & x"278" => data <= x"8d";
when "11" & x"279" => data <= x"09";
when "11" & x"27a" => data <= x"0d";
when "11" & x"27b" => data <= x"20";
when "11" & x"27c" => data <= x"1e";
when "11" & x"27d" => data <= x"a9";
when "11" & x"27e" => data <= x"a0";
when "11" & x"27f" => data <= x"0f";
when "11" & x"280" => data <= x"b1";
when "11" & x"281" => data <= x"f2";
when "11" & x"282" => data <= x"c9";
when "11" & x"283" => data <= x"ff";
when "11" & x"284" => data <= x"f0";
when "11" & x"285" => data <= x"39";
when "11" & x"286" => data <= x"20";
when "11" & x"287" => data <= x"24";
when "11" & x"288" => data <= x"a9";
when "11" & x"289" => data <= x"a0";
when "11" & x"28a" => data <= x"0b";
when "11" & x"28b" => data <= x"b9";
when "11" & x"28c" => data <= x"5f";
when "11" & x"28d" => data <= x"0d";
when "11" & x"28e" => data <= x"91";
when "11" & x"28f" => data <= x"f2";
when "11" & x"290" => data <= x"88";
when "11" & x"291" => data <= x"10";
when "11" & x"292" => data <= x"f8";
when "11" & x"293" => data <= x"18";
when "11" & x"294" => data <= x"a5";
when "11" & x"295" => data <= x"f2";
when "11" & x"296" => data <= x"69";
when "11" & x"297" => data <= x"10";
when "11" & x"298" => data <= x"85";
when "11" & x"299" => data <= x"f2";
when "11" & x"29a" => data <= x"d0";
when "11" & x"29b" => data <= x"e2";
when "11" & x"29c" => data <= x"a5";
when "11" & x"29d" => data <= x"f3";
when "11" & x"29e" => data <= x"49";
when "11" & x"29f" => data <= x"01";
when "11" & x"2a0" => data <= x"85";
when "11" & x"2a1" => data <= x"f3";
when "11" & x"2a2" => data <= x"6a";
when "11" & x"2a3" => data <= x"b0";
when "11" & x"2a4" => data <= x"d9";
when "11" & x"2a5" => data <= x"20";
when "11" & x"2a6" => data <= x"c4";
when "11" & x"2a7" => data <= x"b0";
when "11" & x"2a8" => data <= x"18";
when "11" & x"2a9" => data <= x"ad";
when "11" & x"2aa" => data <= x"52";
when "11" & x"2ab" => data <= x"0d";
when "11" & x"2ac" => data <= x"69";
when "11" & x"2ad" => data <= x"01";
when "11" & x"2ae" => data <= x"c9";
when "11" & x"2af" => data <= x"90";
when "11" & x"2b0" => data <= x"f0";
when "11" & x"2b1" => data <= x"18";
when "11" & x"2b2" => data <= x"8d";
when "11" & x"2b3" => data <= x"52";
when "11" & x"2b4" => data <= x"0d";
when "11" & x"2b5" => data <= x"24";
when "11" & x"2b6" => data <= x"ff";
when "11" & x"2b7" => data <= x"30";
when "11" & x"2b8" => data <= x"12";
when "11" & x"2b9" => data <= x"20";
when "11" & x"2ba" => data <= x"af";
when "11" & x"2bb" => data <= x"b0";
when "11" & x"2bc" => data <= x"4c";
when "11" & x"2bd" => data <= x"7e";
when "11" & x"2be" => data <= x"b2";
when "11" & x"2bf" => data <= x"a5";
when "11" & x"2c0" => data <= x"f2";
when "11" & x"2c1" => data <= x"d0";
when "11" & x"2c2" => data <= x"04";
when "11" & x"2c3" => data <= x"66";
when "11" & x"2c4" => data <= x"f3";
when "11" & x"2c5" => data <= x"90";
when "11" & x"2c6" => data <= x"03";
when "11" & x"2c7" => data <= x"20";
when "11" & x"2c8" => data <= x"c4";
when "11" & x"2c9" => data <= x"b0";
when "11" & x"2ca" => data <= x"60";
when "11" & x"2cb" => data <= x"4c";
when "11" & x"2cc" => data <= x"82";
when "11" & x"2cd" => data <= x"a0";
when "11" & x"2ce" => data <= x"a2";
when "11" & x"2cf" => data <= x"0b";
when "11" & x"2d0" => data <= x"a9";
when "11" & x"2d1" => data <= x"00";
when "11" & x"2d2" => data <= x"20";
when "11" & x"2d3" => data <= x"c6";
when "11" & x"2d4" => data <= x"88";
when "11" & x"2d5" => data <= x"9d";
when "11" & x"2d6" => data <= x"5f";
when "11" & x"2d7" => data <= x"0d";
when "11" & x"2d8" => data <= x"ca";
when "11" & x"2d9" => data <= x"10";
when "11" & x"2da" => data <= x"f7";
when "11" & x"2db" => data <= x"e8";
when "11" & x"2dc" => data <= x"20";
when "11" & x"2dd" => data <= x"c5";
when "11" & x"2de" => data <= x"ff";
when "11" & x"2df" => data <= x"b0";
when "11" & x"2e0" => data <= x"0a";
when "11" & x"2e1" => data <= x"20";
when "11" & x"2e2" => data <= x"c6";
when "11" & x"2e3" => data <= x"88";
when "11" & x"2e4" => data <= x"9d";
when "11" & x"2e5" => data <= x"5f";
when "11" & x"2e6" => data <= x"0d";
when "11" & x"2e7" => data <= x"e0";
when "11" & x"2e8" => data <= x"0b";
when "11" & x"2e9" => data <= x"90";
when "11" & x"2ea" => data <= x"f0";
when "11" & x"2eb" => data <= x"20";
when "11" & x"2ec" => data <= x"b4";
when "11" & x"2ed" => data <= x"8a";
when "11" & x"2ee" => data <= x"ae";
when "11" & x"2ef" => data <= x"82";
when "11" & x"2f0" => data <= x"10";
when "11" & x"2f1" => data <= x"bd";
when "11" & x"2f2" => data <= x"10";
when "11" & x"2f3" => data <= x"0d";
when "11" & x"2f4" => data <= x"6a";
when "11" & x"2f5" => data <= x"bd";
when "11" & x"2f6" => data <= x"0c";
when "11" & x"2f7" => data <= x"0d";
when "11" & x"2f8" => data <= x"20";
when "11" & x"2f9" => data <= x"ad";
when "11" & x"2fa" => data <= x"af";
when "11" & x"2fb" => data <= x"29";
when "11" & x"2fc" => data <= x"f0";
when "11" & x"2fd" => data <= x"48";
when "11" & x"2fe" => data <= x"98";
when "11" & x"2ff" => data <= x"48";
when "11" & x"300" => data <= x"29";
when "11" & x"301" => data <= x"fe";
when "11" & x"302" => data <= x"4a";
when "11" & x"303" => data <= x"09";
when "11" & x"304" => data <= x"80";
when "11" & x"305" => data <= x"20";
when "11" & x"306" => data <= x"a1";
when "11" & x"307" => data <= x"b0";
when "11" & x"308" => data <= x"68";
when "11" & x"309" => data <= x"18";
when "11" & x"30a" => data <= x"29";
when "11" & x"30b" => data <= x"01";
when "11" & x"30c" => data <= x"69";
when "11" & x"30d" => data <= x"0e";
when "11" & x"30e" => data <= x"85";
when "11" & x"30f" => data <= x"f3";
when "11" & x"310" => data <= x"68";
when "11" & x"311" => data <= x"85";
when "11" & x"312" => data <= x"f2";
when "11" & x"313" => data <= x"a0";
when "11" & x"314" => data <= x"0b";
when "11" & x"315" => data <= x"b9";
when "11" & x"316" => data <= x"5f";
when "11" & x"317" => data <= x"0d";
when "11" & x"318" => data <= x"91";
when "11" & x"319" => data <= x"f2";
when "11" & x"31a" => data <= x"88";
when "11" & x"31b" => data <= x"10";
when "11" & x"31c" => data <= x"f8";
when "11" & x"31d" => data <= x"4c";
when "11" & x"31e" => data <= x"b8";
when "11" & x"31f" => data <= x"b0";
when "11" & x"320" => data <= x"42";
when "11" & x"321" => data <= x"45";
when "11" & x"322" => data <= x"45";
when "11" & x"323" => data <= x"42";
when "11" & x"324" => data <= x"20";
when "11" & x"325" => data <= x"20";
when "11" & x"326" => data <= x"20";
when "11" & x"327" => data <= x"20";
when "11" & x"328" => data <= x"4d";
when "11" & x"329" => data <= x"4d";
when "11" & x"32a" => data <= x"42";
when "11" & x"32b" => data <= x"44";
when "11" & x"32c" => data <= x"49";
when "11" & x"32d" => data <= x"4e";
when "11" & x"32e" => data <= x"b8";
when "11" & x"32f" => data <= x"05";
when "11" & x"330" => data <= x"12";
when "11" & x"331" => data <= x"44";
when "11" & x"332" => data <= x"42";
when "11" & x"333" => data <= x"4f";
when "11" & x"334" => data <= x"4f";
when "11" & x"335" => data <= x"54";
when "11" & x"336" => data <= x"b7";
when "11" & x"337" => data <= x"fa";
when "11" & x"338" => data <= x"02";
when "11" & x"339" => data <= x"44";
when "11" & x"33a" => data <= x"43";
when "11" & x"33b" => data <= x"41";
when "11" & x"33c" => data <= x"54";
when "11" & x"33d" => data <= x"b8";
when "11" & x"33e" => data <= x"0b";
when "11" & x"33f" => data <= x"04";
when "11" & x"340" => data <= x"44";
when "11" & x"341" => data <= x"44";
when "11" & x"342" => data <= x"49";
when "11" & x"343" => data <= x"53";
when "11" & x"344" => data <= x"4b";
when "11" & x"345" => data <= x"53";
when "11" & x"346" => data <= x"b9";
when "11" & x"347" => data <= x"bb";
when "11" & x"348" => data <= x"01";
when "11" & x"349" => data <= x"44";
when "11" & x"34a" => data <= x"4c";
when "11" & x"34b" => data <= x"4f";
when "11" & x"34c" => data <= x"43";
when "11" & x"34d" => data <= x"4b";
when "11" & x"34e" => data <= x"ba";
when "11" & x"34f" => data <= x"01";
when "11" & x"350" => data <= x"02";
when "11" & x"351" => data <= x"44";
when "11" & x"352" => data <= x"55";
when "11" & x"353" => data <= x"4e";
when "11" & x"354" => data <= x"4c";
when "11" & x"355" => data <= x"4f";
when "11" & x"356" => data <= x"43";
when "11" & x"357" => data <= x"4b";
when "11" & x"358" => data <= x"ba";
when "11" & x"359" => data <= x"05";
when "11" & x"35a" => data <= x"02";
when "11" & x"35b" => data <= x"44";
when "11" & x"35c" => data <= x"46";
when "11" & x"35d" => data <= x"52";
when "11" & x"35e" => data <= x"45";
when "11" & x"35f" => data <= x"45";
when "11" & x"360" => data <= x"b8";
when "11" & x"361" => data <= x"f5";
when "11" & x"362" => data <= x"00";
when "11" & x"363" => data <= x"44";
when "11" & x"364" => data <= x"4b";
when "11" & x"365" => data <= x"49";
when "11" & x"366" => data <= x"4c";
when "11" & x"367" => data <= x"4c";
when "11" & x"368" => data <= x"ba";
when "11" & x"369" => data <= x"28";
when "11" & x"36a" => data <= x"03";
when "11" & x"36b" => data <= x"44";
when "11" & x"36c" => data <= x"52";
when "11" & x"36d" => data <= x"45";
when "11" & x"36e" => data <= x"53";
when "11" & x"36f" => data <= x"54";
when "11" & x"370" => data <= x"4f";
when "11" & x"371" => data <= x"52";
when "11" & x"372" => data <= x"45";
when "11" & x"373" => data <= x"ba";
when "11" & x"374" => data <= x"6b";
when "11" & x"375" => data <= x"03";
when "11" & x"376" => data <= x"44";
when "11" & x"377" => data <= x"4e";
when "11" & x"378" => data <= x"45";
when "11" & x"379" => data <= x"57";
when "11" & x"37a" => data <= x"ba";
when "11" & x"37b" => data <= x"c0";
when "11" & x"37c" => data <= x"01";
when "11" & x"37d" => data <= x"44";
when "11" & x"37e" => data <= x"46";
when "11" & x"37f" => data <= x"4f";
when "11" & x"380" => data <= x"52";
when "11" & x"381" => data <= x"4d";
when "11" & x"382" => data <= x"ba";
when "11" & x"383" => data <= x"63";
when "11" & x"384" => data <= x"03";
when "11" & x"385" => data <= x"44";
when "11" & x"386" => data <= x"4f";
when "11" & x"387" => data <= x"4e";
when "11" & x"388" => data <= x"42";
when "11" & x"389" => data <= x"4f";
when "11" & x"38a" => data <= x"4f";
when "11" & x"38b" => data <= x"54";
when "11" & x"38c" => data <= x"bb";
when "11" & x"38d" => data <= x"8e";
when "11" & x"38e" => data <= x"52";
when "11" & x"38f" => data <= x"44";
when "11" & x"390" => data <= x"52";
when "11" & x"391" => data <= x"45";
when "11" & x"392" => data <= x"43";
when "11" & x"393" => data <= x"41";
when "11" & x"394" => data <= x"54";
when "11" & x"395" => data <= x"b2";
when "11" & x"396" => data <= x"43";
when "11" & x"397" => data <= x"00";
when "11" & x"398" => data <= x"44";
when "11" & x"399" => data <= x"52";
when "11" & x"39a" => data <= x"4f";
when "11" & x"39b" => data <= x"4d";
when "11" & x"39c" => data <= x"bc";
when "11" & x"39d" => data <= x"1a";
when "11" & x"39e" => data <= x"86";
when "11" & x"39f" => data <= x"42";
when "11" & x"3a0" => data <= x"45";
when "11" & x"3a1" => data <= x"45";
when "11" & x"3a2" => data <= x"42";
when "11" & x"3a3" => data <= x"bb";
when "11" & x"3a4" => data <= x"a9";
when "11" & x"3a5" => data <= x"03";
when "11" & x"3a6" => data <= x"44";
when "11" & x"3a7" => data <= x"47";
when "11" & x"3a8" => data <= x"45";
when "11" & x"3a9" => data <= x"54";
when "11" & x"3aa" => data <= x"bc";
when "11" & x"3ab" => data <= x"14";
when "11" & x"3ac" => data <= x"00";
when "11" & x"3ad" => data <= x"44";
when "11" & x"3ae" => data <= x"50";
when "11" & x"3af" => data <= x"55";
when "11" & x"3b0" => data <= x"54";
when "11" & x"3b1" => data <= x"bc";
when "11" & x"3b2" => data <= x"17";
when "11" & x"3b3" => data <= x"00";
when "11" & x"3b4" => data <= x"44";
when "11" & x"3b5" => data <= x"41";
when "11" & x"3b6" => data <= x"42";
when "11" & x"3b7" => data <= x"4f";
when "11" & x"3b8" => data <= x"55";
when "11" & x"3b9" => data <= x"54";
when "11" & x"3ba" => data <= x"b4";
when "11" & x"3bb" => data <= x"32";
when "11" & x"3bc" => data <= x"00";
when "11" & x"3bd" => data <= x"87";
when "11" & x"3be" => data <= x"d6";
when "11" & x"3bf" => data <= x"00";
when "11" & x"3c0" => data <= x"44";
when "11" & x"3c1" => data <= x"55";
when "11" & x"3c2" => data <= x"54";
when "11" & x"3c3" => data <= x"49";
when "11" & x"3c4" => data <= x"4c";
when "11" & x"3c5" => data <= x"53";
when "11" & x"3c6" => data <= x"b4";
when "11" & x"3c7" => data <= x"03";
when "11" & x"3c8" => data <= x"00";
when "11" & x"3c9" => data <= x"b3";
when "11" & x"3ca" => data <= x"f5";
when "11" & x"3cb" => data <= x"00";
when "11" & x"3cc" => data <= x"a2";
when "11" & x"3cd" => data <= x"a0";
when "11" & x"3ce" => data <= x"b1";
when "11" & x"3cf" => data <= x"f2";
when "11" & x"3d0" => data <= x"c9";
when "11" & x"3d1" => data <= x"0d";
when "11" & x"3d2" => data <= x"d0";
when "11" & x"3d3" => data <= x"16";
when "11" & x"3d4" => data <= x"98";
when "11" & x"3d5" => data <= x"e8";
when "11" & x"3d6" => data <= x"a0";
when "11" & x"3d7" => data <= x"02";
when "11" & x"3d8" => data <= x"20";
when "11" & x"3d9" => data <= x"cb";
when "11" & x"3da" => data <= x"99";
when "11" & x"3db" => data <= x"20";
when "11" & x"3dc" => data <= x"44";
when "11" & x"3dd" => data <= x"b6";
when "11" & x"3de" => data <= x"20";
when "11" & x"3df" => data <= x"20";
when "11" & x"3e0" => data <= x"44";
when "11" & x"3e1" => data <= x"55";
when "11" & x"3e2" => data <= x"54";
when "11" & x"3e3" => data <= x"49";
when "11" & x"3e4" => data <= x"4c";
when "11" & x"3e5" => data <= x"53";
when "11" & x"3e6" => data <= x"00";
when "11" & x"3e7" => data <= x"4c";
when "11" & x"3e8" => data <= x"e7";
when "11" & x"3e9" => data <= x"ff";
when "11" & x"3ea" => data <= x"98";
when "11" & x"3eb" => data <= x"48";
when "11" & x"3ec" => data <= x"20";
when "11" & x"3ed" => data <= x"71";
when "11" & x"3ee" => data <= x"86";
when "11" & x"3ef" => data <= x"68";
when "11" & x"3f0" => data <= x"a8";
when "11" & x"3f1" => data <= x"a2";
when "11" & x"3f2" => data <= x"92";
when "11" & x"3f3" => data <= x"4c";
when "11" & x"3f4" => data <= x"6e";
when "11" & x"3f5" => data <= x"b4";
when "11" & x"3f6" => data <= x"c8";
when "11" & x"3f7" => data <= x"b1";
when "11" & x"3f8" => data <= x"f2";
when "11" & x"3f9" => data <= x"c9";
when "11" & x"3fa" => data <= x"0d";
when "11" & x"3fb" => data <= x"f0";
when "11" & x"3fc" => data <= x"06";
when "11" & x"3fd" => data <= x"c9";
when "11" & x"3fe" => data <= x"20";
when "11" & x"3ff" => data <= x"f0";
when "11" & x"400" => data <= x"f0";
when "11" & x"401" => data <= x"d0";
when "11" & x"402" => data <= x"f3";
when "11" & x"403" => data <= x"60";
when "11" & x"404" => data <= x"20";
when "11" & x"405" => data <= x"e7";
when "11" & x"406" => data <= x"ff";
when "11" & x"407" => data <= x"20";
when "11" & x"408" => data <= x"44";
when "11" & x"409" => data <= x"b6";
when "11" & x"40a" => data <= x"53";
when "11" & x"40b" => data <= x"50";
when "11" & x"40c" => data <= x"49";
when "11" & x"40d" => data <= x"20";
when "11" & x"40e" => data <= x"30";
when "11" & x"40f" => data <= x"2e";
when "11" & x"410" => data <= x"30";
when "11" & x"411" => data <= x"31";
when "11" & x"412" => data <= x"00";
when "11" & x"413" => data <= x"20";
when "11" & x"414" => data <= x"e7";
when "11" & x"415" => data <= x"ff";
when "11" & x"416" => data <= x"a2";
when "11" & x"417" => data <= x"00";
when "11" & x"418" => data <= x"a9";
when "11" & x"419" => data <= x"11";
when "11" & x"41a" => data <= x"86";
when "11" & x"41b" => data <= x"b5";
when "11" & x"41c" => data <= x"85";
when "11" & x"41d" => data <= x"bf";
when "11" & x"41e" => data <= x"a2";
when "11" & x"41f" => data <= x"00";
when "11" & x"420" => data <= x"a9";
when "11" & x"421" => data <= x"20";
when "11" & x"422" => data <= x"20";
when "11" & x"423" => data <= x"ee";
when "11" & x"424" => data <= x"ff";
when "11" & x"425" => data <= x"20";
when "11" & x"426" => data <= x"ee";
when "11" & x"427" => data <= x"ff";
when "11" & x"428" => data <= x"20";
when "11" & x"429" => data <= x"08";
when "11" & x"42a" => data <= x"b7";
when "11" & x"42b" => data <= x"20";
when "11" & x"42c" => data <= x"e7";
when "11" & x"42d" => data <= x"ff";
when "11" & x"42e" => data <= x"c6";
when "11" & x"42f" => data <= x"bf";
when "11" & x"430" => data <= x"d0";
when "11" & x"431" => data <= x"ee";
when "11" & x"432" => data <= x"60";
when "11" & x"433" => data <= x"20";
when "11" & x"434" => data <= x"44";
when "11" & x"435" => data <= x"b6";
when "11" & x"436" => data <= x"44";
when "11" & x"437" => data <= x"55";
when "11" & x"438" => data <= x"54";
when "11" & x"439" => data <= x"49";
when "11" & x"43a" => data <= x"4c";
when "11" & x"43b" => data <= x"53";
when "11" & x"43c" => data <= x"20";
when "11" & x"43d" => data <= x"62";
when "11" & x"43e" => data <= x"79";
when "11" & x"43f" => data <= x"20";
when "11" & x"440" => data <= x"4d";
when "11" & x"441" => data <= x"61";
when "11" & x"442" => data <= x"72";
when "11" & x"443" => data <= x"74";
when "11" & x"444" => data <= x"69";
when "11" & x"445" => data <= x"6e";
when "11" & x"446" => data <= x"20";
when "11" & x"447" => data <= x"4d";
when "11" & x"448" => data <= x"61";
when "11" & x"449" => data <= x"74";
when "11" & x"44a" => data <= x"68";
when "11" & x"44b" => data <= x"65";
when "11" & x"44c" => data <= x"72";
when "11" & x"44d" => data <= x"20";
when "11" & x"44e" => data <= x"0a";
when "11" & x"44f" => data <= x"0d";
when "11" & x"450" => data <= x"4d";
when "11" & x"451" => data <= x"4f";
when "11" & x"452" => data <= x"44";
when "11" & x"453" => data <= x"49";
when "11" & x"454" => data <= x"46";
when "11" & x"455" => data <= x"49";
when "11" & x"456" => data <= x"45";
when "11" & x"457" => data <= x"44";
when "11" & x"458" => data <= x"20";
when "11" & x"459" => data <= x"62";
when "11" & x"45a" => data <= x"79";
when "11" & x"45b" => data <= x"20";
when "11" & x"45c" => data <= x"64";
when "11" & x"45d" => data <= x"75";
when "11" & x"45e" => data <= x"69";
when "11" & x"45f" => data <= x"6b";
when "11" & x"460" => data <= x"6b";
when "11" & x"461" => data <= x"69";
when "11" & x"462" => data <= x"65";
when "11" & x"463" => data <= x"20";
when "11" & x"464" => data <= x"32";
when "11" & x"465" => data <= x"30";
when "11" & x"466" => data <= x"31";
when "11" & x"467" => data <= x"35";
when "11" & x"468" => data <= x"00";
when "11" & x"469" => data <= x"4c";
when "11" & x"46a" => data <= x"e7";
when "11" & x"46b" => data <= x"ff";
when "11" & x"46c" => data <= x"a2";
when "11" & x"46d" => data <= x"fd";
when "11" & x"46e" => data <= x"98";
when "11" & x"46f" => data <= x"48";
when "11" & x"470" => data <= x"e8";
when "11" & x"471" => data <= x"e8";
when "11" & x"472" => data <= x"68";
when "11" & x"473" => data <= x"48";
when "11" & x"474" => data <= x"a8";
when "11" & x"475" => data <= x"20";
when "11" & x"476" => data <= x"b0";
when "11" & x"477" => data <= x"b4";
when "11" & x"478" => data <= x"e8";
when "11" & x"479" => data <= x"bd";
when "11" & x"47a" => data <= x"2b";
when "11" & x"47b" => data <= x"b3";
when "11" & x"47c" => data <= x"30";
when "11" & x"47d" => data <= x"28";
when "11" & x"47e" => data <= x"86";
when "11" & x"47f" => data <= x"b5";
when "11" & x"480" => data <= x"ca";
when "11" & x"481" => data <= x"88";
when "11" & x"482" => data <= x"e8";
when "11" & x"483" => data <= x"c8";
when "11" & x"484" => data <= x"bd";
when "11" & x"485" => data <= x"2b";
when "11" & x"486" => data <= x"b3";
when "11" & x"487" => data <= x"30";
when "11" & x"488" => data <= x"16";
when "11" & x"489" => data <= x"51";
when "11" & x"48a" => data <= x"f2";
when "11" & x"48b" => data <= x"29";
when "11" & x"48c" => data <= x"5f";
when "11" & x"48d" => data <= x"f0";
when "11" & x"48e" => data <= x"f3";
when "11" & x"48f" => data <= x"ca";
when "11" & x"490" => data <= x"e8";
when "11" & x"491" => data <= x"bd";
when "11" & x"492" => data <= x"2b";
when "11" & x"493" => data <= x"b3";
when "11" & x"494" => data <= x"10";
when "11" & x"495" => data <= x"fa";
when "11" & x"496" => data <= x"b1";
when "11" & x"497" => data <= x"f2";
when "11" & x"498" => data <= x"c9";
when "11" & x"499" => data <= x"2e";
when "11" & x"49a" => data <= x"d0";
when "11" & x"49b" => data <= x"d4";
when "11" & x"49c" => data <= x"c8";
when "11" & x"49d" => data <= x"b0";
when "11" & x"49e" => data <= x"07";
when "11" & x"49f" => data <= x"b1";
when "11" & x"4a0" => data <= x"f2";
when "11" & x"4a1" => data <= x"20";
when "11" & x"4a2" => data <= x"ee";
when "11" & x"4a3" => data <= x"82";
when "11" & x"4a4" => data <= x"90";
when "11" & x"4a5" => data <= x"ca";
when "11" & x"4a6" => data <= x"68";
when "11" & x"4a7" => data <= x"bd";
when "11" & x"4a8" => data <= x"2b";
when "11" & x"4a9" => data <= x"b3";
when "11" & x"4aa" => data <= x"48";
when "11" & x"4ab" => data <= x"bd";
when "11" & x"4ac" => data <= x"2c";
when "11" & x"4ad" => data <= x"b3";
when "11" & x"4ae" => data <= x"48";
when "11" & x"4af" => data <= x"60";
when "11" & x"4b0" => data <= x"b1";
when "11" & x"4b1" => data <= x"f2";
when "11" & x"4b2" => data <= x"c9";
when "11" & x"4b3" => data <= x"0d";
when "11" & x"4b4" => data <= x"f0";
when "11" & x"4b5" => data <= x"08";
when "11" & x"4b6" => data <= x"c8";
when "11" & x"4b7" => data <= x"f0";
when "11" & x"4b8" => data <= x"07";
when "11" & x"4b9" => data <= x"c9";
when "11" & x"4ba" => data <= x"20";
when "11" & x"4bb" => data <= x"f0";
when "11" & x"4bc" => data <= x"f3";
when "11" & x"4bd" => data <= x"18";
when "11" & x"4be" => data <= x"88";
when "11" & x"4bf" => data <= x"60";
when "11" & x"4c0" => data <= x"4c";
when "11" & x"4c1" => data <= x"f5";
when "11" & x"4c2" => data <= x"b6";
when "11" & x"4c3" => data <= x"98";
when "11" & x"4c4" => data <= x"48";
when "11" & x"4c5" => data <= x"a9";
when "11" & x"4c6" => data <= x"00";
when "11" & x"4c7" => data <= x"8d";
when "11" & x"4c8" => data <= x"55";
when "11" & x"4c9" => data <= x"0d";
when "11" & x"4ca" => data <= x"8d";
when "11" & x"4cb" => data <= x"56";
when "11" & x"4cc" => data <= x"0d";
when "11" & x"4cd" => data <= x"20";
when "11" & x"4ce" => data <= x"b0";
when "11" & x"4cf" => data <= x"b4";
when "11" & x"4d0" => data <= x"b0";
when "11" & x"4d1" => data <= x"62";
when "11" & x"4d2" => data <= x"b1";
when "11" & x"4d3" => data <= x"f2";
when "11" & x"4d4" => data <= x"c9";
when "11" & x"4d5" => data <= x"0d";
when "11" & x"4d6" => data <= x"f0";
when "11" & x"4d7" => data <= x"5c";
when "11" & x"4d8" => data <= x"38";
when "11" & x"4d9" => data <= x"e9";
when "11" & x"4da" => data <= x"30";
when "11" & x"4db" => data <= x"30";
when "11" & x"4dc" => data <= x"57";
when "11" & x"4dd" => data <= x"c9";
when "11" & x"4de" => data <= x"0a";
when "11" & x"4df" => data <= x"b0";
when "11" & x"4e0" => data <= x"53";
when "11" & x"4e1" => data <= x"48";
when "11" & x"4e2" => data <= x"ad";
when "11" & x"4e3" => data <= x"55";
when "11" & x"4e4" => data <= x"0d";
when "11" & x"4e5" => data <= x"0a";
when "11" & x"4e6" => data <= x"48";
when "11" & x"4e7" => data <= x"2e";
when "11" & x"4e8" => data <= x"56";
when "11" & x"4e9" => data <= x"0d";
when "11" & x"4ea" => data <= x"ae";
when "11" & x"4eb" => data <= x"56";
when "11" & x"4ec" => data <= x"0d";
when "11" & x"4ed" => data <= x"0a";
when "11" & x"4ee" => data <= x"2e";
when "11" & x"4ef" => data <= x"56";
when "11" & x"4f0" => data <= x"0d";
when "11" & x"4f1" => data <= x"0a";
when "11" & x"4f2" => data <= x"2e";
when "11" & x"4f3" => data <= x"56";
when "11" & x"4f4" => data <= x"0d";
when "11" & x"4f5" => data <= x"8d";
when "11" & x"4f6" => data <= x"55";
when "11" & x"4f7" => data <= x"0d";
when "11" & x"4f8" => data <= x"68";
when "11" & x"4f9" => data <= x"6d";
when "11" & x"4fa" => data <= x"55";
when "11" & x"4fb" => data <= x"0d";
when "11" & x"4fc" => data <= x"8d";
when "11" & x"4fd" => data <= x"55";
when "11" & x"4fe" => data <= x"0d";
when "11" & x"4ff" => data <= x"8a";
when "11" & x"500" => data <= x"6d";
when "11" & x"501" => data <= x"56";
when "11" & x"502" => data <= x"0d";
when "11" & x"503" => data <= x"aa";
when "11" & x"504" => data <= x"68";
when "11" & x"505" => data <= x"6d";
when "11" & x"506" => data <= x"55";
when "11" & x"507" => data <= x"0d";
when "11" & x"508" => data <= x"8d";
when "11" & x"509" => data <= x"55";
when "11" & x"50a" => data <= x"0d";
when "11" & x"50b" => data <= x"8a";
when "11" & x"50c" => data <= x"69";
when "11" & x"50d" => data <= x"00";
when "11" & x"50e" => data <= x"8d";
when "11" & x"50f" => data <= x"56";
when "11" & x"510" => data <= x"0d";
when "11" & x"511" => data <= x"c9";
when "11" & x"512" => data <= x"02";
when "11" & x"513" => data <= x"b0";
when "11" & x"514" => data <= x"1f";
when "11" & x"515" => data <= x"c8";
when "11" & x"516" => data <= x"f0";
when "11" & x"517" => data <= x"1c";
when "11" & x"518" => data <= x"b1";
when "11" & x"519" => data <= x"f2";
when "11" & x"51a" => data <= x"c9";
when "11" & x"51b" => data <= x"0d";
when "11" & x"51c" => data <= x"f0";
when "11" & x"51d" => data <= x"04";
when "11" & x"51e" => data <= x"c9";
when "11" & x"51f" => data <= x"20";
when "11" & x"520" => data <= x"d0";
when "11" & x"521" => data <= x"b6";
when "11" & x"522" => data <= x"ae";
when "11" & x"523" => data <= x"55";
when "11" & x"524" => data <= x"0d";
when "11" & x"525" => data <= x"ad";
when "11" & x"526" => data <= x"56";
when "11" & x"527" => data <= x"0d";
when "11" & x"528" => data <= x"f0";
when "11" & x"529" => data <= x"04";
when "11" & x"52a" => data <= x"e8";
when "11" & x"52b" => data <= x"f0";
when "11" & x"52c" => data <= x"07";
when "11" & x"52d" => data <= x"ca";
when "11" & x"52e" => data <= x"68";
when "11" & x"52f" => data <= x"ad";
when "11" & x"530" => data <= x"56";
when "11" & x"531" => data <= x"0d";
when "11" & x"532" => data <= x"18";
when "11" & x"533" => data <= x"60";
when "11" & x"534" => data <= x"68";
when "11" & x"535" => data <= x"a8";
when "11" & x"536" => data <= x"a9";
when "11" & x"537" => data <= x"00";
when "11" & x"538" => data <= x"aa";
when "11" & x"539" => data <= x"38";
when "11" & x"53a" => data <= x"60";
when "11" & x"53b" => data <= x"a9";
when "11" & x"53c" => data <= x"0d";
when "11" & x"53d" => data <= x"8d";
when "11" & x"53e" => data <= x"5d";
when "11" & x"53f" => data <= x"0d";
when "11" & x"540" => data <= x"a2";
when "11" & x"541" => data <= x"00";
when "11" & x"542" => data <= x"8e";
when "11" & x"543" => data <= x"5e";
when "11" & x"544" => data <= x"0d";
when "11" & x"545" => data <= x"20";
when "11" & x"546" => data <= x"b0";
when "11" & x"547" => data <= x"b4";
when "11" & x"548" => data <= x"b0";
when "11" & x"549" => data <= x"49";
when "11" & x"54a" => data <= x"c9";
when "11" & x"54b" => data <= x"22";
when "11" & x"54c" => data <= x"d0";
when "11" & x"54d" => data <= x"04";
when "11" & x"54e" => data <= x"c8";
when "11" & x"54f" => data <= x"8d";
when "11" & x"550" => data <= x"5d";
when "11" & x"551" => data <= x"0d";
when "11" & x"552" => data <= x"b1";
when "11" & x"553" => data <= x"f2";
when "11" & x"554" => data <= x"c9";
when "11" & x"555" => data <= x"0d";
when "11" & x"556" => data <= x"f0";
when "11" & x"557" => data <= x"2c";
when "11" & x"558" => data <= x"c9";
when "11" & x"559" => data <= x"20";
when "11" & x"55a" => data <= x"d0";
when "11" & x"55b" => data <= x"0b";
when "11" & x"55c" => data <= x"90";
when "11" & x"55d" => data <= x"52";
when "11" & x"55e" => data <= x"ad";
when "11" & x"55f" => data <= x"5d";
when "11" & x"560" => data <= x"0d";
when "11" & x"561" => data <= x"c9";
when "11" & x"562" => data <= x"22";
when "11" & x"563" => data <= x"d0";
when "11" & x"564" => data <= x"28";
when "11" & x"565" => data <= x"a9";
when "11" & x"566" => data <= x"20";
when "11" & x"567" => data <= x"c9";
when "11" & x"568" => data <= x"22";
when "11" & x"569" => data <= x"f0";
when "11" & x"56a" => data <= x"19";
when "11" & x"56b" => data <= x"c9";
when "11" & x"56c" => data <= x"2a";
when "11" & x"56d" => data <= x"f0";
when "11" & x"56e" => data <= x"31";
when "11" & x"56f" => data <= x"c9";
when "11" & x"570" => data <= x"61";
when "11" & x"571" => data <= x"90";
when "11" & x"572" => data <= x"06";
when "11" & x"573" => data <= x"c9";
when "11" & x"574" => data <= x"7b";
when "11" & x"575" => data <= x"b0";
when "11" & x"576" => data <= x"02";
when "11" & x"577" => data <= x"49";
when "11" & x"578" => data <= x"20";
when "11" & x"579" => data <= x"9d";
when "11" & x"57a" => data <= x"5f";
when "11" & x"57b" => data <= x"0d";
when "11" & x"57c" => data <= x"c8";
when "11" & x"57d" => data <= x"e8";
when "11" & x"57e" => data <= x"e0";
when "11" & x"57f" => data <= x"0c";
when "11" & x"580" => data <= x"d0";
when "11" & x"581" => data <= x"d0";
when "11" & x"582" => data <= x"b1";
when "11" & x"583" => data <= x"f2";
when "11" & x"584" => data <= x"cd";
when "11" & x"585" => data <= x"5d";
when "11" & x"586" => data <= x"0d";
when "11" & x"587" => data <= x"d0";
when "11" & x"588" => data <= x"27";
when "11" & x"589" => data <= x"c9";
when "11" & x"58a" => data <= x"0d";
when "11" & x"58b" => data <= x"f0";
when "11" & x"58c" => data <= x"06";
when "11" & x"58d" => data <= x"c8";
when "11" & x"58e" => data <= x"20";
when "11" & x"58f" => data <= x"b0";
when "11" & x"590" => data <= x"b4";
when "11" & x"591" => data <= x"90";
when "11" & x"592" => data <= x"1d";
when "11" & x"593" => data <= x"8e";
when "11" & x"594" => data <= x"5c";
when "11" & x"595" => data <= x"0d";
when "11" & x"596" => data <= x"e0";
when "11" & x"597" => data <= x"0c";
when "11" & x"598" => data <= x"f0";
when "11" & x"599" => data <= x"05";
when "11" & x"59a" => data <= x"a9";
when "11" & x"59b" => data <= x"00";
when "11" & x"59c" => data <= x"9d";
when "11" & x"59d" => data <= x"5f";
when "11" & x"59e" => data <= x"0d";
when "11" & x"59f" => data <= x"60";
when "11" & x"5a0" => data <= x"8d";
when "11" & x"5a1" => data <= x"5e";
when "11" & x"5a2" => data <= x"0d";
when "11" & x"5a3" => data <= x"ad";
when "11" & x"5a4" => data <= x"5d";
when "11" & x"5a5" => data <= x"0d";
when "11" & x"5a6" => data <= x"c9";
when "11" & x"5a7" => data <= x"0d";
when "11" & x"5a8" => data <= x"f0";
when "11" & x"5a9" => data <= x"e3";
when "11" & x"5aa" => data <= x"c8";
when "11" & x"5ab" => data <= x"b1";
when "11" & x"5ac" => data <= x"f2";
when "11" & x"5ad" => data <= x"4c";
when "11" & x"5ae" => data <= x"84";
when "11" & x"5af" => data <= x"b5";
when "11" & x"5b0" => data <= x"4c";
when "11" & x"5b1" => data <= x"f5";
when "11" & x"5b2" => data <= x"b6";
when "11" & x"5b3" => data <= x"a0";
when "11" & x"5b4" => data <= x"00";
when "11" & x"5b5" => data <= x"ae";
when "11" & x"5b6" => data <= x"5c";
when "11" & x"5b7" => data <= x"0d";
when "11" & x"5b8" => data <= x"f0";
when "11" & x"5b9" => data <= x"17";
when "11" & x"5ba" => data <= x"b1";
when "11" & x"5bb" => data <= x"f2";
when "11" & x"5bc" => data <= x"f0";
when "11" & x"5bd" => data <= x"25";
when "11" & x"5be" => data <= x"c9";
when "11" & x"5bf" => data <= x"61";
when "11" & x"5c0" => data <= x"90";
when "11" & x"5c1" => data <= x"06";
when "11" & x"5c2" => data <= x"c9";
when "11" & x"5c3" => data <= x"7b";
when "11" & x"5c4" => data <= x"b0";
when "11" & x"5c5" => data <= x"02";
when "11" & x"5c6" => data <= x"49";
when "11" & x"5c7" => data <= x"20";
when "11" & x"5c8" => data <= x"d9";
when "11" & x"5c9" => data <= x"5f";
when "11" & x"5ca" => data <= x"0d";
when "11" & x"5cb" => data <= x"d0";
when "11" & x"5cc" => data <= x"16";
when "11" & x"5cd" => data <= x"c8";
when "11" & x"5ce" => data <= x"ca";
when "11" & x"5cf" => data <= x"d0";
when "11" & x"5d0" => data <= x"e9";
when "11" & x"5d1" => data <= x"b1";
when "11" & x"5d2" => data <= x"f2";
when "11" & x"5d3" => data <= x"f0";
when "11" & x"5d4" => data <= x"0c";
when "11" & x"5d5" => data <= x"ad";
when "11" & x"5d6" => data <= x"5c";
when "11" & x"5d7" => data <= x"0d";
when "11" & x"5d8" => data <= x"c9";
when "11" & x"5d9" => data <= x"0c";
when "11" & x"5da" => data <= x"f0";
when "11" & x"5db" => data <= x"05";
when "11" & x"5dc" => data <= x"ad";
when "11" & x"5dd" => data <= x"5e";
when "11" & x"5de" => data <= x"0d";
when "11" & x"5df" => data <= x"f0";
when "11" & x"5e0" => data <= x"02";
when "11" & x"5e1" => data <= x"18";
when "11" & x"5e2" => data <= x"60";
when "11" & x"5e3" => data <= x"38";
when "11" & x"5e4" => data <= x"60";
when "11" & x"5e5" => data <= x"b0";
when "11" & x"5e6" => data <= x"05";
when "11" & x"5e7" => data <= x"a9";
when "11" & x"5e8" => data <= x"20";
when "11" & x"5e9" => data <= x"20";
when "11" & x"5ea" => data <= x"ee";
when "11" & x"5eb" => data <= x"ff";
when "11" & x"5ec" => data <= x"a2";
when "11" & x"5ed" => data <= x"20";
when "11" & x"5ee" => data <= x"a0";
when "11" & x"5ef" => data <= x"04";
when "11" & x"5f0" => data <= x"ad";
when "11" & x"5f1" => data <= x"56";
when "11" & x"5f2" => data <= x"0d";
when "11" & x"5f3" => data <= x"20";
when "11" & x"5f4" => data <= x"26";
when "11" & x"5f5" => data <= x"b6";
when "11" & x"5f6" => data <= x"ad";
when "11" & x"5f7" => data <= x"55";
when "11" & x"5f8" => data <= x"0d";
when "11" & x"5f9" => data <= x"20";
when "11" & x"5fa" => data <= x"26";
when "11" & x"5fb" => data <= x"b6";
when "11" & x"5fc" => data <= x"a9";
when "11" & x"5fd" => data <= x"20";
when "11" & x"5fe" => data <= x"20";
when "11" & x"5ff" => data <= x"ee";
when "11" & x"600" => data <= x"ff";
when "11" & x"601" => data <= x"a0";
when "11" & x"602" => data <= x"00";
when "11" & x"603" => data <= x"b1";
when "11" & x"604" => data <= x"f2";
when "11" & x"605" => data <= x"f0";
when "11" & x"606" => data <= x"08";
when "11" & x"607" => data <= x"20";
when "11" & x"608" => data <= x"ee";
when "11" & x"609" => data <= x"ff";
when "11" & x"60a" => data <= x"c8";
when "11" & x"60b" => data <= x"c0";
when "11" & x"60c" => data <= x"0c";
when "11" & x"60d" => data <= x"d0";
when "11" & x"60e" => data <= x"f4";
when "11" & x"60f" => data <= x"a9";
when "11" & x"610" => data <= x"20";
when "11" & x"611" => data <= x"20";
when "11" & x"612" => data <= x"ee";
when "11" & x"613" => data <= x"ff";
when "11" & x"614" => data <= x"c8";
when "11" & x"615" => data <= x"c0";
when "11" & x"616" => data <= x"0d";
when "11" & x"617" => data <= x"d0";
when "11" & x"618" => data <= x"f8";
when "11" & x"619" => data <= x"aa";
when "11" & x"61a" => data <= x"a0";
when "11" & x"61b" => data <= x"0f";
when "11" & x"61c" => data <= x"b1";
when "11" & x"61d" => data <= x"f2";
when "11" & x"61e" => data <= x"d0";
when "11" & x"61f" => data <= x"02";
when "11" & x"620" => data <= x"a2";
when "11" & x"621" => data <= x"50";
when "11" & x"622" => data <= x"8a";
when "11" & x"623" => data <= x"4c";
when "11" & x"624" => data <= x"ee";
when "11" & x"625" => data <= x"ff";
when "11" & x"626" => data <= x"48";
when "11" & x"627" => data <= x"4a";
when "11" & x"628" => data <= x"4a";
when "11" & x"629" => data <= x"4a";
when "11" & x"62a" => data <= x"4a";
when "11" & x"62b" => data <= x"20";
when "11" & x"62c" => data <= x"2f";
when "11" & x"62d" => data <= x"b6";
when "11" & x"62e" => data <= x"68";
when "11" & x"62f" => data <= x"29";
when "11" & x"630" => data <= x"0f";
when "11" & x"631" => data <= x"f0";
when "11" & x"632" => data <= x"08";
when "11" & x"633" => data <= x"a2";
when "11" & x"634" => data <= x"30";
when "11" & x"635" => data <= x"18";
when "11" & x"636" => data <= x"69";
when "11" & x"637" => data <= x"30";
when "11" & x"638" => data <= x"4c";
when "11" & x"639" => data <= x"ee";
when "11" & x"63a" => data <= x"ff";
when "11" & x"63b" => data <= x"88";
when "11" & x"63c" => data <= x"d0";
when "11" & x"63d" => data <= x"02";
when "11" & x"63e" => data <= x"a2";
when "11" & x"63f" => data <= x"30";
when "11" & x"640" => data <= x"8a";
when "11" & x"641" => data <= x"4c";
when "11" & x"642" => data <= x"ee";
when "11" & x"643" => data <= x"ff";
when "11" & x"644" => data <= x"a2";
when "11" & x"645" => data <= x"00";
when "11" & x"646" => data <= x"68";
when "11" & x"647" => data <= x"85";
when "11" & x"648" => data <= x"a0";
when "11" & x"649" => data <= x"68";
when "11" & x"64a" => data <= x"85";
when "11" & x"64b" => data <= x"a1";
when "11" & x"64c" => data <= x"a0";
when "11" & x"64d" => data <= x"00";
when "11" & x"64e" => data <= x"f0";
when "11" & x"64f" => data <= x"07";
when "11" & x"650" => data <= x"b1";
when "11" & x"651" => data <= x"a0";
when "11" & x"652" => data <= x"f0";
when "11" & x"653" => data <= x"0b";
when "11" & x"654" => data <= x"20";
when "11" & x"655" => data <= x"66";
when "11" & x"656" => data <= x"b6";
when "11" & x"657" => data <= x"e6";
when "11" & x"658" => data <= x"a0";
when "11" & x"659" => data <= x"d0";
when "11" & x"65a" => data <= x"f5";
when "11" & x"65b" => data <= x"e6";
when "11" & x"65c" => data <= x"a1";
when "11" & x"65d" => data <= x"d0";
when "11" & x"65e" => data <= x"f1";
when "11" & x"65f" => data <= x"a5";
when "11" & x"660" => data <= x"a1";
when "11" & x"661" => data <= x"48";
when "11" & x"662" => data <= x"a5";
when "11" & x"663" => data <= x"a0";
when "11" & x"664" => data <= x"48";
when "11" & x"665" => data <= x"60";
when "11" & x"666" => data <= x"e0";
when "11" & x"667" => data <= x"00";
when "11" & x"668" => data <= x"d0";
when "11" & x"669" => data <= x"03";
when "11" & x"66a" => data <= x"4c";
when "11" & x"66b" => data <= x"ee";
when "11" & x"66c" => data <= x"ff";
when "11" & x"66d" => data <= x"9d";
when "11" & x"66e" => data <= x"00";
when "11" & x"66f" => data <= x"01";
when "11" & x"670" => data <= x"e8";
when "11" & x"671" => data <= x"60";
when "11" & x"672" => data <= x"08";
when "11" & x"673" => data <= x"10";
when "11" & x"674" => data <= x"1c";
when "11" & x"675" => data <= x"22";
when "11" & x"676" => data <= x"43";
when "11" & x"677" => data <= x"49";
when "11" & x"678" => data <= x"4f";
when "11" & x"679" => data <= x"58";
when "11" & x"67a" => data <= x"28";
when "11" & x"67b" => data <= x"3c";
when "11" & x"67c" => data <= x"64";
when "11" & x"67d" => data <= x"72";
when "11" & x"67e" => data <= x"76";
when "11" & x"67f" => data <= x"3e";
when "11" & x"680" => data <= x"29";
when "11" & x"681" => data <= x"00";
when "11" & x"682" => data <= x"3c";
when "11" & x"683" => data <= x"64";
when "11" & x"684" => data <= x"6e";
when "11" & x"685" => data <= x"6f";
when "11" & x"686" => data <= x"3e";
when "11" & x"687" => data <= x"2f";
when "11" & x"688" => data <= x"3c";
when "11" & x"689" => data <= x"64";
when "11" & x"68a" => data <= x"73";
when "11" & x"68b" => data <= x"70";
when "11" & x"68c" => data <= x"3e";
when "11" & x"68d" => data <= x"00";
when "11" & x"68e" => data <= x"3c";
when "11" & x"68f" => data <= x"64";
when "11" & x"690" => data <= x"6e";
when "11" & x"691" => data <= x"6f";
when "11" & x"692" => data <= x"3e";
when "11" & x"693" => data <= x"00";
when "11" & x"694" => data <= x"28";
when "11" & x"695" => data <= x"28";
when "11" & x"696" => data <= x"3c";
when "11" & x"697" => data <= x"66";
when "11" & x"698" => data <= x"72";
when "11" & x"699" => data <= x"6f";
when "11" & x"69a" => data <= x"6d";
when "11" & x"69b" => data <= x"20";
when "11" & x"69c" => data <= x"64";
when "11" & x"69d" => data <= x"6e";
when "11" & x"69e" => data <= x"6f";
when "11" & x"69f" => data <= x"3e";
when "11" & x"6a0" => data <= x"29";
when "11" & x"6a1" => data <= x"20";
when "11" & x"6a2" => data <= x"3c";
when "11" & x"6a3" => data <= x"74";
when "11" & x"6a4" => data <= x"6f";
when "11" & x"6a5" => data <= x"20";
when "11" & x"6a6" => data <= x"64";
when "11" & x"6a7" => data <= x"6e";
when "11" & x"6a8" => data <= x"6f";
when "11" & x"6a9" => data <= x"3e";
when "11" & x"6aa" => data <= x"29";
when "11" & x"6ab" => data <= x"20";
when "11" & x"6ac" => data <= x"28";
when "11" & x"6ad" => data <= x"3c";
when "11" & x"6ae" => data <= x"61";
when "11" & x"6af" => data <= x"64";
when "11" & x"6b0" => data <= x"73";
when "11" & x"6b1" => data <= x"70";
when "11" & x"6b2" => data <= x"3e";
when "11" & x"6b3" => data <= x"29";
when "11" & x"6b4" => data <= x"00";
when "11" & x"6b5" => data <= x"3c";
when "11" & x"6b6" => data <= x"64";
when "11" & x"6b7" => data <= x"72";
when "11" & x"6b8" => data <= x"76";
when "11" & x"6b9" => data <= x"3e";
when "11" & x"6ba" => data <= x"00";
when "11" & x"6bb" => data <= x"3c";
when "11" & x"6bc" => data <= x"66";
when "11" & x"6bd" => data <= x"73";
when "11" & x"6be" => data <= x"70";
when "11" & x"6bf" => data <= x"3e";
when "11" & x"6c0" => data <= x"00";
when "11" & x"6c1" => data <= x"28";
when "11" & x"6c2" => data <= x"3c";
when "11" & x"6c3" => data <= x"6d";
when "11" & x"6c4" => data <= x"6f";
when "11" & x"6c5" => data <= x"64";
when "11" & x"6c6" => data <= x"65";
when "11" & x"6c7" => data <= x"3e";
when "11" & x"6c8" => data <= x"29";
when "11" & x"6c9" => data <= x"00";
when "11" & x"6ca" => data <= x"28";
when "11" & x"6cb" => data <= x"3c";
when "11" & x"6cc" => data <= x"72";
when "11" & x"6cd" => data <= x"6f";
when "11" & x"6ce" => data <= x"6d";
when "11" & x"6cf" => data <= x"3e";
when "11" & x"6d0" => data <= x"29";
when "11" & x"6d1" => data <= x"00";
when "11" & x"6d2" => data <= x"48";
when "11" & x"6d3" => data <= x"4a";
when "11" & x"6d4" => data <= x"4a";
when "11" & x"6d5" => data <= x"4a";
when "11" & x"6d6" => data <= x"4a";
when "11" & x"6d7" => data <= x"20";
when "11" & x"6d8" => data <= x"dd";
when "11" & x"6d9" => data <= x"b6";
when "11" & x"6da" => data <= x"68";
when "11" & x"6db" => data <= x"29";
when "11" & x"6dc" => data <= x"0f";
when "11" & x"6dd" => data <= x"a8";
when "11" & x"6de" => data <= x"f0";
when "11" & x"6df" => data <= x"14";
when "11" & x"6e0" => data <= x"a9";
when "11" & x"6e1" => data <= x"20";
when "11" & x"6e2" => data <= x"20";
when "11" & x"6e3" => data <= x"66";
when "11" & x"6e4" => data <= x"b6";
when "11" & x"6e5" => data <= x"b9";
when "11" & x"6e6" => data <= x"71";
when "11" & x"6e7" => data <= x"b6";
when "11" & x"6e8" => data <= x"a8";
when "11" & x"6e9" => data <= x"b9";
when "11" & x"6ea" => data <= x"72";
when "11" & x"6eb" => data <= x"b6";
when "11" & x"6ec" => data <= x"f0";
when "11" & x"6ed" => data <= x"06";
when "11" & x"6ee" => data <= x"20";
when "11" & x"6ef" => data <= x"66";
when "11" & x"6f0" => data <= x"b6";
when "11" & x"6f1" => data <= x"c8";
when "11" & x"6f2" => data <= x"d0";
when "11" & x"6f3" => data <= x"f5";
when "11" & x"6f4" => data <= x"60";
when "11" & x"6f5" => data <= x"a2";
when "11" & x"6f6" => data <= x"00";
when "11" & x"6f7" => data <= x"8e";
when "11" & x"6f8" => data <= x"00";
when "11" & x"6f9" => data <= x"01";
when "11" & x"6fa" => data <= x"e8";
when "11" & x"6fb" => data <= x"20";
when "11" & x"6fc" => data <= x"46";
when "11" & x"6fd" => data <= x"b6";
when "11" & x"6fe" => data <= x"1a";
when "11" & x"6ff" => data <= x"53";
when "11" & x"700" => data <= x"79";
when "11" & x"701" => data <= x"6e";
when "11" & x"702" => data <= x"74";
when "11" & x"703" => data <= x"61";
when "11" & x"704" => data <= x"78";
when "11" & x"705" => data <= x"3a";
when "11" & x"706" => data <= x"20";
when "11" & x"707" => data <= x"00";
when "11" & x"708" => data <= x"a4";
when "11" & x"709" => data <= x"b5";
when "11" & x"70a" => data <= x"b9";
when "11" & x"70b" => data <= x"2b";
when "11" & x"70c" => data <= x"b3";
when "11" & x"70d" => data <= x"30";
when "11" & x"70e" => data <= x"06";
when "11" & x"70f" => data <= x"20";
when "11" & x"710" => data <= x"66";
when "11" & x"711" => data <= x"b6";
when "11" & x"712" => data <= x"c8";
when "11" & x"713" => data <= x"d0";
when "11" & x"714" => data <= x"f5";
when "11" & x"715" => data <= x"c8";
when "11" & x"716" => data <= x"c8";
when "11" & x"717" => data <= x"b9";
when "11" & x"718" => data <= x"2b";
when "11" & x"719" => data <= x"b3";
when "11" & x"71a" => data <= x"c8";
when "11" & x"71b" => data <= x"84";
when "11" & x"71c" => data <= x"b5";
when "11" & x"71d" => data <= x"20";
when "11" & x"71e" => data <= x"d2";
when "11" & x"71f" => data <= x"b6";
when "11" & x"720" => data <= x"e0";
when "11" & x"721" => data <= x"00";
when "11" & x"722" => data <= x"f0";
when "11" & x"723" => data <= x"08";
when "11" & x"724" => data <= x"a9";
when "11" & x"725" => data <= x"00";
when "11" & x"726" => data <= x"9d";
when "11" & x"727" => data <= x"00";
when "11" & x"728" => data <= x"01";
when "11" & x"729" => data <= x"4c";
when "11" & x"72a" => data <= x"00";
when "11" & x"72b" => data <= x"01";
when "11" & x"72c" => data <= x"60";
when "11" & x"72d" => data <= x"4c";
when "11" & x"72e" => data <= x"f5";
when "11" & x"72f" => data <= x"b6";
when "11" & x"730" => data <= x"20";
when "11" & x"731" => data <= x"b0";
when "11" & x"732" => data <= x"b4";
when "11" & x"733" => data <= x"b0";
when "11" & x"734" => data <= x"17";
when "11" & x"735" => data <= x"20";
when "11" & x"736" => data <= x"c3";
when "11" & x"737" => data <= x"b4";
when "11" & x"738" => data <= x"b0";
when "11" & x"739" => data <= x"bb";
when "11" & x"73a" => data <= x"48";
when "11" & x"73b" => data <= x"20";
when "11" & x"73c" => data <= x"b0";
when "11" & x"73d" => data <= x"b4";
when "11" & x"73e" => data <= x"68";
when "11" & x"73f" => data <= x"90";
when "11" & x"740" => data <= x"b4";
when "11" & x"741" => data <= x"d0";
when "11" & x"742" => data <= x"26";
when "11" & x"743" => data <= x"8a";
when "11" & x"744" => data <= x"8d";
when "11" & x"745" => data <= x"5b";
when "11" & x"746" => data <= x"0d";
when "11" & x"747" => data <= x"c9";
when "11" & x"748" => data <= x"04";
when "11" & x"749" => data <= x"b0";
when "11" & x"74a" => data <= x"1e";
when "11" & x"74b" => data <= x"60";
when "11" & x"74c" => data <= x"a5";
when "11" & x"74d" => data <= x"cf";
when "11" & x"74e" => data <= x"60";
when "11" & x"74f" => data <= x"20";
when "11" & x"750" => data <= x"b0";
when "11" & x"751" => data <= x"b4";
when "11" & x"752" => data <= x"b0";
when "11" & x"753" => data <= x"a1";
when "11" & x"754" => data <= x"20";
when "11" & x"755" => data <= x"c3";
when "11" & x"756" => data <= x"b4";
when "11" & x"757" => data <= x"b0";
when "11" & x"758" => data <= x"9c";
when "11" & x"759" => data <= x"48";
when "11" & x"75a" => data <= x"20";
when "11" & x"75b" => data <= x"b0";
when "11" & x"75c" => data <= x"b4";
when "11" & x"75d" => data <= x"68";
when "11" & x"75e" => data <= x"90";
when "11" & x"75f" => data <= x"95";
when "11" & x"760" => data <= x"60";
when "11" & x"761" => data <= x"20";
when "11" & x"762" => data <= x"b0";
when "11" & x"763" => data <= x"b4";
when "11" & x"764" => data <= x"b0";
when "11" & x"765" => data <= x"8f";
when "11" & x"766" => data <= x"4c";
when "11" & x"767" => data <= x"ba";
when "11" & x"768" => data <= x"b7";
when "11" & x"769" => data <= x"20";
when "11" & x"76a" => data <= x"00";
when "11" & x"76b" => data <= x"a0";
when "11" & x"76c" => data <= x"cd";
when "11" & x"76d" => data <= x"42";
when "11" & x"76e" => data <= x"61";
when "11" & x"76f" => data <= x"64";
when "11" & x"770" => data <= x"20";
when "11" & x"771" => data <= x"64";
when "11" & x"772" => data <= x"72";
when "11" & x"773" => data <= x"69";
when "11" & x"774" => data <= x"76";
when "11" & x"775" => data <= x"65";
when "11" & x"776" => data <= x"00";
when "11" & x"777" => data <= x"20";
when "11" & x"778" => data <= x"00";
when "11" & x"779" => data <= x"a0";
when "11" & x"77a" => data <= x"d6";
when "11" & x"77b" => data <= x"44";
when "11" & x"77c" => data <= x"69";
when "11" & x"77d" => data <= x"73";
when "11" & x"77e" => data <= x"6b";
when "11" & x"77f" => data <= x"20";
when "11" & x"780" => data <= x"6e";
when "11" & x"781" => data <= x"6f";
when "11" & x"782" => data <= x"74";
when "11" & x"783" => data <= x"20";
when "11" & x"784" => data <= x"66";
when "11" & x"785" => data <= x"6f";
when "11" & x"786" => data <= x"75";
when "11" & x"787" => data <= x"6e";
when "11" & x"788" => data <= x"64";
when "11" & x"789" => data <= x"00";
when "11" & x"78a" => data <= x"20";
when "11" & x"78b" => data <= x"b0";
when "11" & x"78c" => data <= x"b4";
when "11" & x"78d" => data <= x"b0";
when "11" & x"78e" => data <= x"9e";
when "11" & x"78f" => data <= x"a9";
when "11" & x"790" => data <= x"ff";
when "11" & x"791" => data <= x"20";
when "11" & x"792" => data <= x"a2";
when "11" & x"793" => data <= x"b7";
when "11" & x"794" => data <= x"08";
when "11" & x"795" => data <= x"e0";
when "11" & x"796" => data <= x"04";
when "11" & x"797" => data <= x"b0";
when "11" & x"798" => data <= x"33";
when "11" & x"799" => data <= x"28";
when "11" & x"79a" => data <= x"60";
when "11" & x"79b" => data <= x"20";
when "11" & x"79c" => data <= x"b0";
when "11" & x"79d" => data <= x"b4";
when "11" & x"79e" => data <= x"b0";
when "11" & x"79f" => data <= x"8d";
when "11" & x"7a0" => data <= x"a5";
when "11" & x"7a1" => data <= x"cf";
when "11" & x"7a2" => data <= x"8d";
when "11" & x"7a3" => data <= x"5b";
when "11" & x"7a4" => data <= x"0d";
when "11" & x"7a5" => data <= x"20";
when "11" & x"7a6" => data <= x"c3";
when "11" & x"7a7" => data <= x"b4";
when "11" & x"7a8" => data <= x"b0";
when "11" & x"7a9" => data <= x"26";
when "11" & x"7aa" => data <= x"48";
when "11" & x"7ab" => data <= x"20";
when "11" & x"7ac" => data <= x"b0";
when "11" & x"7ad" => data <= x"b4";
when "11" & x"7ae" => data <= x"b0";
when "11" & x"7af" => data <= x"15";
when "11" & x"7b0" => data <= x"68";
when "11" & x"7b1" => data <= x"d0";
when "11" & x"7b2" => data <= x"b6";
when "11" & x"7b3" => data <= x"e0";
when "11" & x"7b4" => data <= x"04";
when "11" & x"7b5" => data <= x"b0";
when "11" & x"7b6" => data <= x"b2";
when "11" & x"7b7" => data <= x"8e";
when "11" & x"7b8" => data <= x"5b";
when "11" & x"7b9" => data <= x"0d";
when "11" & x"7ba" => data <= x"20";
when "11" & x"7bb" => data <= x"c3";
when "11" & x"7bc" => data <= x"b4";
when "11" & x"7bd" => data <= x"b0";
when "11" & x"7be" => data <= x"11";
when "11" & x"7bf" => data <= x"48";
when "11" & x"7c0" => data <= x"20";
when "11" & x"7c1" => data <= x"b0";
when "11" & x"7c2" => data <= x"b4";
when "11" & x"7c3" => data <= x"90";
when "11" & x"7c4" => data <= x"07";
when "11" & x"7c5" => data <= x"68";
when "11" & x"7c6" => data <= x"6a";
when "11" & x"7c7" => data <= x"8a";
when "11" & x"7c8" => data <= x"ae";
when "11" & x"7c9" => data <= x"5b";
when "11" & x"7ca" => data <= x"0d";
when "11" & x"7cb" => data <= x"60";
when "11" & x"7cc" => data <= x"68";
when "11" & x"7cd" => data <= x"4c";
when "11" & x"7ce" => data <= x"f5";
when "11" & x"7cf" => data <= x"b6";
when "11" & x"7d0" => data <= x"20";
when "11" & x"7d1" => data <= x"3b";
when "11" & x"7d2" => data <= x"b5";
when "11" & x"7d3" => data <= x"20";
when "11" & x"7d4" => data <= x"d7";
when "11" & x"7d5" => data <= x"b1";
when "11" & x"7d6" => data <= x"ad";
when "11" & x"7d7" => data <= x"5c";
when "11" & x"7d8" => data <= x"0d";
when "11" & x"7d9" => data <= x"f0";
when "11" & x"7da" => data <= x"f2";
when "11" & x"7db" => data <= x"ad";
when "11" & x"7dc" => data <= x"5e";
when "11" & x"7dd" => data <= x"0d";
when "11" & x"7de" => data <= x"d0";
when "11" & x"7df" => data <= x"ed";
when "11" & x"7e0" => data <= x"ad";
when "11" & x"7e1" => data <= x"54";
when "11" & x"7e2" => data <= x"0d";
when "11" & x"7e3" => data <= x"30";
when "11" & x"7e4" => data <= x"92";
when "11" & x"7e5" => data <= x"20";
when "11" & x"7e6" => data <= x"b3";
when "11" & x"7e7" => data <= x"b5";
when "11" & x"7e8" => data <= x"90";
when "11" & x"7e9" => data <= x"06";
when "11" & x"7ea" => data <= x"20";
when "11" & x"7eb" => data <= x"fc";
when "11" & x"7ec" => data <= x"b1";
when "11" & x"7ed" => data <= x"4c";
when "11" & x"7ee" => data <= x"e0";
when "11" & x"7ef" => data <= x"b7";
when "11" & x"7f0" => data <= x"ad";
when "11" & x"7f1" => data <= x"54";
when "11" & x"7f2" => data <= x"0d";
when "11" & x"7f3" => data <= x"6a";
when "11" & x"7f4" => data <= x"ad";
when "11" & x"7f5" => data <= x"53";
when "11" & x"7f6" => data <= x"0d";
when "11" & x"7f7" => data <= x"ae";
when "11" & x"7f8" => data <= x"5b";
when "11" & x"7f9" => data <= x"0d";
when "11" & x"7fa" => data <= x"60";
when "11" & x"7fb" => data <= x"20";
when "11" & x"7fc" => data <= x"61";
when "11" & x"7fd" => data <= x"b7";
when "11" & x"7fe" => data <= x"a6";
when "11" & x"7ff" => data <= x"cf";
when "11" & x"800" => data <= x"20";
when "11" & x"801" => data <= x"0f";
when "11" & x"802" => data <= x"b0";
when "11" & x"803" => data <= x"4c";
when "11" & x"804" => data <= x"07";
when "11" & x"805" => data <= x"94";
when "11" & x"806" => data <= x"20";
when "11" & x"807" => data <= x"9b";
when "11" & x"808" => data <= x"b7";
when "11" & x"809" => data <= x"4c";
when "11" & x"80a" => data <= x"0f";
when "11" & x"80b" => data <= x"b0";
when "11" & x"80c" => data <= x"a9";
when "11" & x"80d" => data <= x"00";
when "11" & x"80e" => data <= x"8d";
when "11" & x"80f" => data <= x"57";
when "11" & x"810" => data <= x"0d";
when "11" & x"811" => data <= x"8d";
when "11" & x"812" => data <= x"58";
when "11" & x"813" => data <= x"0d";
when "11" & x"814" => data <= x"20";
when "11" & x"815" => data <= x"c3";
when "11" & x"816" => data <= x"b4";
when "11" & x"817" => data <= x"b0";
when "11" & x"818" => data <= x"2d";
when "11" & x"819" => data <= x"8e";
when "11" & x"81a" => data <= x"59";
when "11" & x"81b" => data <= x"0d";
when "11" & x"81c" => data <= x"8e";
when "11" & x"81d" => data <= x"53";
when "11" & x"81e" => data <= x"0d";
when "11" & x"81f" => data <= x"8d";
when "11" & x"820" => data <= x"5a";
when "11" & x"821" => data <= x"0d";
when "11" & x"822" => data <= x"8d";
when "11" & x"823" => data <= x"54";
when "11" & x"824" => data <= x"0d";
when "11" & x"825" => data <= x"20";
when "11" & x"826" => data <= x"c3";
when "11" & x"827" => data <= x"b4";
when "11" & x"828" => data <= x"b0";
when "11" & x"829" => data <= x"25";
when "11" & x"82a" => data <= x"8e";
when "11" & x"82b" => data <= x"59";
when "11" & x"82c" => data <= x"0d";
when "11" & x"82d" => data <= x"8d";
when "11" & x"82e" => data <= x"5a";
when "11" & x"82f" => data <= x"0d";
when "11" & x"830" => data <= x"ec";
when "11" & x"831" => data <= x"53";
when "11" & x"832" => data <= x"0d";
when "11" & x"833" => data <= x"ed";
when "11" & x"834" => data <= x"54";
when "11" & x"835" => data <= x"0d";
when "11" & x"836" => data <= x"10";
when "11" & x"837" => data <= x"1f";
when "11" & x"838" => data <= x"20";
when "11" & x"839" => data <= x"00";
when "11" & x"83a" => data <= x"a0";
when "11" & x"83b" => data <= x"ff";
when "11" & x"83c" => data <= x"42";
when "11" & x"83d" => data <= x"61";
when "11" & x"83e" => data <= x"64";
when "11" & x"83f" => data <= x"20";
when "11" & x"840" => data <= x"72";
when "11" & x"841" => data <= x"61";
when "11" & x"842" => data <= x"6e";
when "11" & x"843" => data <= x"67";
when "11" & x"844" => data <= x"65";
when "11" & x"845" => data <= x"00";
when "11" & x"846" => data <= x"a2";
when "11" & x"847" => data <= x"fe";
when "11" & x"848" => data <= x"8e";
when "11" & x"849" => data <= x"59";
when "11" & x"84a" => data <= x"0d";
when "11" & x"84b" => data <= x"e8";
when "11" & x"84c" => data <= x"8e";
when "11" & x"84d" => data <= x"5a";
when "11" & x"84e" => data <= x"0d";
when "11" & x"84f" => data <= x"a9";
when "11" & x"850" => data <= x"00";
when "11" & x"851" => data <= x"8d";
when "11" & x"852" => data <= x"53";
when "11" & x"853" => data <= x"0d";
when "11" & x"854" => data <= x"8d";
when "11" & x"855" => data <= x"54";
when "11" & x"856" => data <= x"0d";
when "11" & x"857" => data <= x"ee";
when "11" & x"858" => data <= x"59";
when "11" & x"859" => data <= x"0d";
when "11" & x"85a" => data <= x"d0";
when "11" & x"85b" => data <= x"03";
when "11" & x"85c" => data <= x"ee";
when "11" & x"85d" => data <= x"5a";
when "11" & x"85e" => data <= x"0d";
when "11" & x"85f" => data <= x"20";
when "11" & x"860" => data <= x"3b";
when "11" & x"861" => data <= x"b5";
when "11" & x"862" => data <= x"ad";
when "11" & x"863" => data <= x"54";
when "11" & x"864" => data <= x"0d";
when "11" & x"865" => data <= x"6a";
when "11" & x"866" => data <= x"ad";
when "11" & x"867" => data <= x"53";
when "11" & x"868" => data <= x"0d";
when "11" & x"869" => data <= x"20";
when "11" & x"86a" => data <= x"a0";
when "11" & x"86b" => data <= x"b1";
when "11" & x"86c" => data <= x"a2";
when "11" & x"86d" => data <= x"00";
when "11" & x"86e" => data <= x"ad";
when "11" & x"86f" => data <= x"5c";
when "11" & x"870" => data <= x"0d";
when "11" & x"871" => data <= x"d0";
when "11" & x"872" => data <= x"04";
when "11" & x"873" => data <= x"ca";
when "11" & x"874" => data <= x"8e";
when "11" & x"875" => data <= x"5e";
when "11" & x"876" => data <= x"0d";
when "11" & x"877" => data <= x"ad";
when "11" & x"878" => data <= x"54";
when "11" & x"879" => data <= x"0d";
when "11" & x"87a" => data <= x"30";
when "11" & x"87b" => data <= x"33";
when "11" & x"87c" => data <= x"ad";
when "11" & x"87d" => data <= x"53";
when "11" & x"87e" => data <= x"0d";
when "11" & x"87f" => data <= x"cd";
when "11" & x"880" => data <= x"59";
when "11" & x"881" => data <= x"0d";
when "11" & x"882" => data <= x"ad";
when "11" & x"883" => data <= x"54";
when "11" & x"884" => data <= x"0d";
when "11" & x"885" => data <= x"ed";
when "11" & x"886" => data <= x"5a";
when "11" & x"887" => data <= x"0d";
when "11" & x"888" => data <= x"b0";
when "11" & x"889" => data <= x"25";
when "11" & x"88a" => data <= x"20";
when "11" & x"88b" => data <= x"b3";
when "11" & x"88c" => data <= x"b5";
when "11" & x"88d" => data <= x"b0";
when "11" & x"88e" => data <= x"16";
when "11" & x"88f" => data <= x"20";
when "11" & x"890" => data <= x"e5";
when "11" & x"891" => data <= x"b5";
when "11" & x"892" => data <= x"f8";
when "11" & x"893" => data <= x"18";
when "11" & x"894" => data <= x"ad";
when "11" & x"895" => data <= x"57";
when "11" & x"896" => data <= x"0d";
when "11" & x"897" => data <= x"69";
when "11" & x"898" => data <= x"01";
when "11" & x"899" => data <= x"8d";
when "11" & x"89a" => data <= x"57";
when "11" & x"89b" => data <= x"0d";
when "11" & x"89c" => data <= x"ad";
when "11" & x"89d" => data <= x"58";
when "11" & x"89e" => data <= x"0d";
when "11" & x"89f" => data <= x"69";
when "11" & x"8a0" => data <= x"00";
when "11" & x"8a1" => data <= x"8d";
when "11" & x"8a2" => data <= x"58";
when "11" & x"8a3" => data <= x"0d";
when "11" & x"8a4" => data <= x"d8";
when "11" & x"8a5" => data <= x"24";
when "11" & x"8a6" => data <= x"ff";
when "11" & x"8a7" => data <= x"30";
when "11" & x"8a8" => data <= x"47";
when "11" & x"8a9" => data <= x"20";
when "11" & x"8aa" => data <= x"fc";
when "11" & x"8ab" => data <= x"b1";
when "11" & x"8ac" => data <= x"4c";
when "11" & x"8ad" => data <= x"77";
when "11" & x"8ae" => data <= x"b8";
when "11" & x"8af" => data <= x"a9";
when "11" & x"8b0" => data <= x"86";
when "11" & x"8b1" => data <= x"20";
when "11" & x"8b2" => data <= x"f4";
when "11" & x"8b3" => data <= x"ff";
when "11" & x"8b4" => data <= x"e0";
when "11" & x"8b5" => data <= x"00";
when "11" & x"8b6" => data <= x"f0";
when "11" & x"8b7" => data <= x"03";
when "11" & x"8b8" => data <= x"20";
when "11" & x"8b9" => data <= x"e7";
when "11" & x"8ba" => data <= x"ff";
when "11" & x"8bb" => data <= x"ad";
when "11" & x"8bc" => data <= x"58";
when "11" & x"8bd" => data <= x"0d";
when "11" & x"8be" => data <= x"a2";
when "11" & x"8bf" => data <= x"00";
when "11" & x"8c0" => data <= x"a0";
when "11" & x"8c1" => data <= x"04";
when "11" & x"8c2" => data <= x"20";
when "11" & x"8c3" => data <= x"26";
when "11" & x"8c4" => data <= x"b6";
when "11" & x"8c5" => data <= x"ad";
when "11" & x"8c6" => data <= x"57";
when "11" & x"8c7" => data <= x"0d";
when "11" & x"8c8" => data <= x"20";
when "11" & x"8c9" => data <= x"26";
when "11" & x"8ca" => data <= x"b6";
when "11" & x"8cb" => data <= x"20";
when "11" & x"8cc" => data <= x"44";
when "11" & x"8cd" => data <= x"b6";
when "11" & x"8ce" => data <= x"20";
when "11" & x"8cf" => data <= x"64";
when "11" & x"8d0" => data <= x"69";
when "11" & x"8d1" => data <= x"73";
when "11" & x"8d2" => data <= x"6b";
when "11" & x"8d3" => data <= x"00";
when "11" & x"8d4" => data <= x"ad";
when "11" & x"8d5" => data <= x"58";
when "11" & x"8d6" => data <= x"0d";
when "11" & x"8d7" => data <= x"d0";
when "11" & x"8d8" => data <= x"05";
when "11" & x"8d9" => data <= x"ce";
when "11" & x"8da" => data <= x"57";
when "11" & x"8db" => data <= x"0d";
when "11" & x"8dc" => data <= x"f0";
when "11" & x"8dd" => data <= x"05";
when "11" & x"8de" => data <= x"a9";
when "11" & x"8df" => data <= x"73";
when "11" & x"8e0" => data <= x"20";
when "11" & x"8e1" => data <= x"ee";
when "11" & x"8e2" => data <= x"ff";
when "11" & x"8e3" => data <= x"20";
when "11" & x"8e4" => data <= x"44";
when "11" & x"8e5" => data <= x"b6";
when "11" & x"8e6" => data <= x"20";
when "11" & x"8e7" => data <= x"66";
when "11" & x"8e8" => data <= x"6f";
when "11" & x"8e9" => data <= x"75";
when "11" & x"8ea" => data <= x"6e";
when "11" & x"8eb" => data <= x"64";
when "11" & x"8ec" => data <= x"00";
when "11" & x"8ed" => data <= x"4c";
when "11" & x"8ee" => data <= x"e7";
when "11" & x"8ef" => data <= x"ff";
when "11" & x"8f0" => data <= x"4c";
when "11" & x"8f1" => data <= x"82";
when "11" & x"8f2" => data <= x"a0";
when "11" & x"8f3" => data <= x"4c";
when "11" & x"8f4" => data <= x"f5";
when "11" & x"8f5" => data <= x"b6";
when "11" & x"8f6" => data <= x"20";
when "11" & x"8f7" => data <= x"b0";
when "11" & x"8f8" => data <= x"b4";
when "11" & x"8f9" => data <= x"90";
when "11" & x"8fa" => data <= x"f8";
when "11" & x"8fb" => data <= x"a2";
when "11" & x"8fc" => data <= x"00";
when "11" & x"8fd" => data <= x"8e";
when "11" & x"8fe" => data <= x"57";
when "11" & x"8ff" => data <= x"0d";
when "11" & x"900" => data <= x"8e";
when "11" & x"901" => data <= x"58";
when "11" & x"902" => data <= x"0d";
when "11" & x"903" => data <= x"8e";
when "11" & x"904" => data <= x"59";
when "11" & x"905" => data <= x"0d";
when "11" & x"906" => data <= x"8e";
when "11" & x"907" => data <= x"5a";
when "11" & x"908" => data <= x"0d";
when "11" & x"909" => data <= x"a9";
when "11" & x"90a" => data <= x"80";
when "11" & x"90b" => data <= x"20";
when "11" & x"90c" => data <= x"9c";
when "11" & x"90d" => data <= x"b0";
when "11" & x"90e" => data <= x"a9";
when "11" & x"90f" => data <= x"10";
when "11" & x"910" => data <= x"85";
when "11" & x"911" => data <= x"f2";
when "11" & x"912" => data <= x"a9";
when "11" & x"913" => data <= x"0e";
when "11" & x"914" => data <= x"85";
when "11" & x"915" => data <= x"f3";
when "11" & x"916" => data <= x"a0";
when "11" & x"917" => data <= x"0f";
when "11" & x"918" => data <= x"b1";
when "11" & x"919" => data <= x"f2";
when "11" & x"91a" => data <= x"c9";
when "11" & x"91b" => data <= x"ff";
when "11" & x"91c" => data <= x"f0";
when "11" & x"91d" => data <= x"42";
when "11" & x"91e" => data <= x"f8";
when "11" & x"91f" => data <= x"a8";
when "11" & x"920" => data <= x"10";
when "11" & x"921" => data <= x"0e";
when "11" & x"922" => data <= x"18";
when "11" & x"923" => data <= x"ad";
when "11" & x"924" => data <= x"57";
when "11" & x"925" => data <= x"0d";
when "11" & x"926" => data <= x"69";
when "11" & x"927" => data <= x"01";
when "11" & x"928" => data <= x"8d";
when "11" & x"929" => data <= x"57";
when "11" & x"92a" => data <= x"0d";
when "11" & x"92b" => data <= x"90";
when "11" & x"92c" => data <= x"03";
when "11" & x"92d" => data <= x"ee";
when "11" & x"92e" => data <= x"58";
when "11" & x"92f" => data <= x"0d";
when "11" & x"930" => data <= x"18";
when "11" & x"931" => data <= x"ad";
when "11" & x"932" => data <= x"59";
when "11" & x"933" => data <= x"0d";
when "11" & x"934" => data <= x"69";
when "11" & x"935" => data <= x"01";
when "11" & x"936" => data <= x"8d";
when "11" & x"937" => data <= x"59";
when "11" & x"938" => data <= x"0d";
when "11" & x"939" => data <= x"90";
when "11" & x"93a" => data <= x"03";
when "11" & x"93b" => data <= x"ee";
when "11" & x"93c" => data <= x"5a";
when "11" & x"93d" => data <= x"0d";
when "11" & x"93e" => data <= x"d8";
when "11" & x"93f" => data <= x"18";
when "11" & x"940" => data <= x"a5";
when "11" & x"941" => data <= x"f2";
when "11" & x"942" => data <= x"69";
when "11" & x"943" => data <= x"10";
when "11" & x"944" => data <= x"85";
when "11" & x"945" => data <= x"f2";
when "11" & x"946" => data <= x"d0";
when "11" & x"947" => data <= x"ce";
when "11" & x"948" => data <= x"a5";
when "11" & x"949" => data <= x"f3";
when "11" & x"94a" => data <= x"49";
when "11" & x"94b" => data <= x"01";
when "11" & x"94c" => data <= x"85";
when "11" & x"94d" => data <= x"f3";
when "11" & x"94e" => data <= x"6a";
when "11" & x"94f" => data <= x"b0";
when "11" & x"950" => data <= x"c5";
when "11" & x"951" => data <= x"ad";
when "11" & x"952" => data <= x"82";
when "11" & x"953" => data <= x"10";
when "11" & x"954" => data <= x"69";
when "11" & x"955" => data <= x"01";
when "11" & x"956" => data <= x"c9";
when "11" & x"957" => data <= x"90";
when "11" & x"958" => data <= x"f0";
when "11" & x"959" => data <= x"06";
when "11" & x"95a" => data <= x"20";
when "11" & x"95b" => data <= x"9c";
when "11" & x"95c" => data <= x"b0";
when "11" & x"95d" => data <= x"4c";
when "11" & x"95e" => data <= x"16";
when "11" & x"95f" => data <= x"b9";
when "11" & x"960" => data <= x"a0";
when "11" & x"961" => data <= x"04";
when "11" & x"962" => data <= x"a2";
when "11" & x"963" => data <= x"00";
when "11" & x"964" => data <= x"ad";
when "11" & x"965" => data <= x"58";
when "11" & x"966" => data <= x"0d";
when "11" & x"967" => data <= x"20";
when "11" & x"968" => data <= x"26";
when "11" & x"969" => data <= x"b6";
when "11" & x"96a" => data <= x"ad";
when "11" & x"96b" => data <= x"57";
when "11" & x"96c" => data <= x"0d";
when "11" & x"96d" => data <= x"20";
when "11" & x"96e" => data <= x"26";
when "11" & x"96f" => data <= x"b6";
when "11" & x"970" => data <= x"20";
when "11" & x"971" => data <= x"44";
when "11" & x"972" => data <= x"b6";
when "11" & x"973" => data <= x"20";
when "11" & x"974" => data <= x"6f";
when "11" & x"975" => data <= x"66";
when "11" & x"976" => data <= x"20";
when "11" & x"977" => data <= x"00";
when "11" & x"978" => data <= x"a2";
when "11" & x"979" => data <= x"00";
when "11" & x"97a" => data <= x"a0";
when "11" & x"97b" => data <= x"04";
when "11" & x"97c" => data <= x"ad";
when "11" & x"97d" => data <= x"5a";
when "11" & x"97e" => data <= x"0d";
when "11" & x"97f" => data <= x"20";
when "11" & x"980" => data <= x"26";
when "11" & x"981" => data <= x"b6";
when "11" & x"982" => data <= x"ad";
when "11" & x"983" => data <= x"59";
when "11" & x"984" => data <= x"0d";
when "11" & x"985" => data <= x"20";
when "11" & x"986" => data <= x"26";
when "11" & x"987" => data <= x"b6";
when "11" & x"988" => data <= x"20";
when "11" & x"989" => data <= x"44";
when "11" & x"98a" => data <= x"b6";
when "11" & x"98b" => data <= x"20";
when "11" & x"98c" => data <= x"64";
when "11" & x"98d" => data <= x"69";
when "11" & x"98e" => data <= x"73";
when "11" & x"98f" => data <= x"6b";
when "11" & x"990" => data <= x"00";
when "11" & x"991" => data <= x"ad";
when "11" & x"992" => data <= x"5a";
when "11" & x"993" => data <= x"0d";
when "11" & x"994" => data <= x"d0";
when "11" & x"995" => data <= x"07";
when "11" & x"996" => data <= x"ad";
when "11" & x"997" => data <= x"59";
when "11" & x"998" => data <= x"0d";
when "11" & x"999" => data <= x"c9";
when "11" & x"99a" => data <= x"01";
when "11" & x"99b" => data <= x"f0";
when "11" & x"99c" => data <= x"05";
when "11" & x"99d" => data <= x"a9";
when "11" & x"99e" => data <= x"73";
when "11" & x"99f" => data <= x"20";
when "11" & x"9a0" => data <= x"ee";
when "11" & x"9a1" => data <= x"ff";
when "11" & x"9a2" => data <= x"20";
when "11" & x"9a3" => data <= x"44";
when "11" & x"9a4" => data <= x"b6";
when "11" & x"9a5" => data <= x"20";
when "11" & x"9a6" => data <= x"66";
when "11" & x"9a7" => data <= x"72";
when "11" & x"9a8" => data <= x"65";
when "11" & x"9a9" => data <= x"65";
when "11" & x"9aa" => data <= x"20";
when "11" & x"9ab" => data <= x"28";
when "11" & x"9ac" => data <= x"75";
when "11" & x"9ad" => data <= x"6e";
when "11" & x"9ae" => data <= x"66";
when "11" & x"9af" => data <= x"6f";
when "11" & x"9b0" => data <= x"72";
when "11" & x"9b1" => data <= x"6d";
when "11" & x"9b2" => data <= x"61";
when "11" & x"9b3" => data <= x"74";
when "11" & x"9b4" => data <= x"74";
when "11" & x"9b5" => data <= x"65";
when "11" & x"9b6" => data <= x"64";
when "11" & x"9b7" => data <= x"29";
when "11" & x"9b8" => data <= x"00";
when "11" & x"9b9" => data <= x"4c";
when "11" & x"9ba" => data <= x"e7";
when "11" & x"9bb" => data <= x"ff";
when "11" & x"9bc" => data <= x"20";
when "11" & x"9bd" => data <= x"30";
when "11" & x"9be" => data <= x"b7";
when "11" & x"9bf" => data <= x"a2";
when "11" & x"9c0" => data <= x"04";
when "11" & x"9c1" => data <= x"8e";
when "11" & x"9c2" => data <= x"5b";
when "11" & x"9c3" => data <= x"0d";
when "11" & x"9c4" => data <= x"a2";
when "11" & x"9c5" => data <= x"00";
when "11" & x"9c6" => data <= x"b0";
when "11" & x"9c7" => data <= x"06";
when "11" & x"9c8" => data <= x"aa";
when "11" & x"9c9" => data <= x"e8";
when "11" & x"9ca" => data <= x"8e";
when "11" & x"9cb" => data <= x"5b";
when "11" & x"9cc" => data <= x"0d";
when "11" & x"9cd" => data <= x"ca";
when "11" & x"9ce" => data <= x"8a";
when "11" & x"9cf" => data <= x"48";
when "11" & x"9d0" => data <= x"a2";
when "11" & x"9d1" => data <= x"20";
when "11" & x"9d2" => data <= x"a0";
when "11" & x"9d3" => data <= x"02";
when "11" & x"9d4" => data <= x"20";
when "11" & x"9d5" => data <= x"26";
when "11" & x"9d6" => data <= x"b6";
when "11" & x"9d7" => data <= x"a9";
when "11" & x"9d8" => data <= x"3a";
when "11" & x"9d9" => data <= x"20";
when "11" & x"9da" => data <= x"ee";
when "11" & x"9db" => data <= x"ff";
when "11" & x"9dc" => data <= x"68";
when "11" & x"9dd" => data <= x"aa";
when "11" & x"9de" => data <= x"48";
when "11" & x"9df" => data <= x"bd";
when "11" & x"9e0" => data <= x"10";
when "11" & x"9e1" => data <= x"0d";
when "11" & x"9e2" => data <= x"30";
when "11" & x"9e3" => data <= x"0f";
when "11" & x"9e4" => data <= x"6a";
when "11" & x"9e5" => data <= x"bd";
when "11" & x"9e6" => data <= x"0c";
when "11" & x"9e7" => data <= x"0d";
when "11" & x"9e8" => data <= x"20";
when "11" & x"9e9" => data <= x"a0";
when "11" & x"9ea" => data <= x"b1";
when "11" & x"9eb" => data <= x"c9";
when "11" & x"9ec" => data <= x"ff";
when "11" & x"9ed" => data <= x"f0";
when "11" & x"9ee" => data <= x"04";
when "11" & x"9ef" => data <= x"38";
when "11" & x"9f0" => data <= x"20";
when "11" & x"9f1" => data <= x"e5";
when "11" & x"9f2" => data <= x"b5";
when "11" & x"9f3" => data <= x"20";
when "11" & x"9f4" => data <= x"e7";
when "11" & x"9f5" => data <= x"ff";
when "11" & x"9f6" => data <= x"68";
when "11" & x"9f7" => data <= x"aa";
when "11" & x"9f8" => data <= x"e8";
when "11" & x"9f9" => data <= x"ec";
when "11" & x"9fa" => data <= x"5b";
when "11" & x"9fb" => data <= x"0d";
when "11" & x"9fc" => data <= x"90";
when "11" & x"9fd" => data <= x"d0";
when "11" & x"9fe" => data <= x"60";
when "11" & x"9ff" => data <= x"4c";
when "11" & x"a00" => data <= x"f5";
when "11" & x"a01" => data <= x"b6";
when "11" & x"a02" => data <= x"a9";
when "11" & x"a03" => data <= x"00";
when "11" & x"a04" => data <= x"f0";
when "11" & x"a05" => data <= x"02";
when "11" & x"a06" => data <= x"a9";
when "11" & x"a07" => data <= x"0f";
when "11" & x"a08" => data <= x"48";
when "11" & x"a09" => data <= x"20";
when "11" & x"a0a" => data <= x"61";
when "11" & x"a0b" => data <= x"b7";
when "11" & x"a0c" => data <= x"20";
when "11" & x"a0d" => data <= x"c1";
when "11" & x"a0e" => data <= x"af";
when "11" & x"a0f" => data <= x"30";
when "11" & x"a10" => data <= x"0e";
when "11" & x"a11" => data <= x"68";
when "11" & x"a12" => data <= x"b0";
when "11" & x"a13" => data <= x"05";
when "11" & x"a14" => data <= x"99";
when "11" & x"a15" => data <= x"00";
when "11" & x"a16" => data <= x"0e";
when "11" & x"a17" => data <= x"90";
when "11" & x"a18" => data <= x"03";
when "11" & x"a19" => data <= x"99";
when "11" & x"a1a" => data <= x"00";
when "11" & x"a1b" => data <= x"0f";
when "11" & x"a1c" => data <= x"4c";
when "11" & x"a1d" => data <= x"cd";
when "11" & x"a1e" => data <= x"b0";
when "11" & x"a1f" => data <= x"c9";
when "11" & x"a20" => data <= x"ff";
when "11" & x"a21" => data <= x"f0";
when "11" & x"a22" => data <= x"03";
when "11" & x"a23" => data <= x"4c";
when "11" & x"a24" => data <= x"59";
when "11" & x"a25" => data <= x"b0";
when "11" & x"a26" => data <= x"4c";
when "11" & x"a27" => data <= x"3f";
when "11" & x"a28" => data <= x"b0";
when "11" & x"a29" => data <= x"20";
when "11" & x"a2a" => data <= x"bd";
when "11" & x"a2b" => data <= x"9b";
when "11" & x"a2c" => data <= x"20";
when "11" & x"a2d" => data <= x"4f";
when "11" & x"a2e" => data <= x"b7";
when "11" & x"a2f" => data <= x"6a";
when "11" & x"a30" => data <= x"08";
when "11" & x"a31" => data <= x"8a";
when "11" & x"a32" => data <= x"48";
when "11" & x"a33" => data <= x"20";
when "11" & x"a34" => data <= x"c1";
when "11" & x"a35" => data <= x"af";
when "11" & x"a36" => data <= x"30";
when "11" & x"a37" => data <= x"e7";
when "11" & x"a38" => data <= x"68";
when "11" & x"a39" => data <= x"28";
when "11" & x"a3a" => data <= x"20";
when "11" & x"a3b" => data <= x"a0";
when "11" & x"a3c" => data <= x"b1";
when "11" & x"a3d" => data <= x"20";
when "11" & x"a3e" => data <= x"44";
when "11" & x"a3f" => data <= x"b6";
when "11" & x"a40" => data <= x"4b";
when "11" & x"a41" => data <= x"69";
when "11" & x"a42" => data <= x"6c";
when "11" & x"a43" => data <= x"6c";
when "11" & x"a44" => data <= x"00";
when "11" & x"a45" => data <= x"38";
when "11" & x"a46" => data <= x"20";
when "11" & x"a47" => data <= x"e5";
when "11" & x"a48" => data <= x"b5";
when "11" & x"a49" => data <= x"20";
when "11" & x"a4a" => data <= x"44";
when "11" & x"a4b" => data <= x"b6";
when "11" & x"a4c" => data <= x"20";
when "11" & x"a4d" => data <= x"3a";
when "11" & x"a4e" => data <= x"20";
when "11" & x"a4f" => data <= x"00";
when "11" & x"a50" => data <= x"20";
when "11" & x"a51" => data <= x"9e";
when "11" & x"a52" => data <= x"9c";
when "11" & x"a53" => data <= x"08";
when "11" & x"a54" => data <= x"20";
when "11" & x"a55" => data <= x"e7";
when "11" & x"a56" => data <= x"ff";
when "11" & x"a57" => data <= x"28";
when "11" & x"a58" => data <= x"d0";
when "11" & x"a59" => data <= x"09";
when "11" & x"a5a" => data <= x"a0";
when "11" & x"a5b" => data <= x"0f";
when "11" & x"a5c" => data <= x"a9";
when "11" & x"a5d" => data <= x"f0";
when "11" & x"a5e" => data <= x"91";
when "11" & x"a5f" => data <= x"f2";
when "11" & x"a60" => data <= x"4c";
when "11" & x"a61" => data <= x"cd";
when "11" & x"a62" => data <= x"b0";
when "11" & x"a63" => data <= x"60";
when "11" & x"a64" => data <= x"a9";
when "11" & x"a65" => data <= x"00";
when "11" & x"a66" => data <= x"20";
when "11" & x"a67" => data <= x"6e";
when "11" & x"a68" => data <= x"ba";
when "11" & x"a69" => data <= x"4c";
when "11" & x"a6a" => data <= x"63";
when "11" & x"a6b" => data <= x"af";
when "11" & x"a6c" => data <= x"a9";
when "11" & x"a6d" => data <= x"01";
when "11" & x"a6e" => data <= x"8d";
when "11" & x"a6f" => data <= x"5f";
when "11" & x"a70" => data <= x"0d";
when "11" & x"a71" => data <= x"20";
when "11" & x"a72" => data <= x"4f";
when "11" & x"a73" => data <= x"b7";
when "11" & x"a74" => data <= x"6a";
when "11" & x"a75" => data <= x"08";
when "11" & x"a76" => data <= x"8a";
when "11" & x"a77" => data <= x"48";
when "11" & x"a78" => data <= x"20";
when "11" & x"a79" => data <= x"c1";
when "11" & x"a7a" => data <= x"af";
when "11" & x"a7b" => data <= x"10";
when "11" & x"a7c" => data <= x"26";
when "11" & x"a7d" => data <= x"aa";
when "11" & x"a7e" => data <= x"e8";
when "11" & x"a7f" => data <= x"f0";
when "11" & x"a80" => data <= x"3d";
when "11" & x"a81" => data <= x"98";
when "11" & x"a82" => data <= x"29";
when "11" & x"a83" => data <= x"f0";
when "11" & x"a84" => data <= x"85";
when "11" & x"a85" => data <= x"f2";
when "11" & x"a86" => data <= x"a0";
when "11" & x"a87" => data <= x"0e";
when "11" & x"a88" => data <= x"90";
when "11" & x"a89" => data <= x"01";
when "11" & x"a8a" => data <= x"c8";
when "11" & x"a8b" => data <= x"84";
when "11" & x"a8c" => data <= x"f3";
when "11" & x"a8d" => data <= x"a0";
when "11" & x"a8e" => data <= x"0f";
when "11" & x"a8f" => data <= x"98";
when "11" & x"a90" => data <= x"91";
when "11" & x"a91" => data <= x"f2";
when "11" & x"a92" => data <= x"ad";
when "11" & x"a93" => data <= x"5f";
when "11" & x"a94" => data <= x"0d";
when "11" & x"a95" => data <= x"d0";
when "11" & x"a96" => data <= x"06";
when "11" & x"a97" => data <= x"88";
when "11" & x"a98" => data <= x"91";
when "11" & x"a99" => data <= x"f2";
when "11" & x"a9a" => data <= x"88";
when "11" & x"a9b" => data <= x"10";
when "11" & x"a9c" => data <= x"fb";
when "11" & x"a9d" => data <= x"20";
when "11" & x"a9e" => data <= x"cd";
when "11" & x"a9f" => data <= x"b0";
when "11" & x"aa0" => data <= x"68";
when "11" & x"aa1" => data <= x"28";
when "11" & x"aa2" => data <= x"60";
when "11" & x"aa3" => data <= x"20";
when "11" & x"aa4" => data <= x"00";
when "11" & x"aa5" => data <= x"a0";
when "11" & x"aa6" => data <= x"ff";
when "11" & x"aa7" => data <= x"44";
when "11" & x"aa8" => data <= x"69";
when "11" & x"aa9" => data <= x"73";
when "11" & x"aaa" => data <= x"6b";
when "11" & x"aab" => data <= x"20";
when "11" & x"aac" => data <= x"61";
when "11" & x"aad" => data <= x"6c";
when "11" & x"aae" => data <= x"72";
when "11" & x"aaf" => data <= x"65";
when "11" & x"ab0" => data <= x"61";
when "11" & x"ab1" => data <= x"64";
when "11" & x"ab2" => data <= x"79";
when "11" & x"ab3" => data <= x"20";
when "11" & x"ab4" => data <= x"66";
when "11" & x"ab5" => data <= x"6f";
when "11" & x"ab6" => data <= x"72";
when "11" & x"ab7" => data <= x"6d";
when "11" & x"ab8" => data <= x"61";
when "11" & x"ab9" => data <= x"74";
when "11" & x"aba" => data <= x"74";
when "11" & x"abb" => data <= x"65";
when "11" & x"abc" => data <= x"64";
when "11" & x"abd" => data <= x"00";
when "11" & x"abe" => data <= x"4c";
when "11" & x"abf" => data <= x"3f";
when "11" & x"ac0" => data <= x"b0";
when "11" & x"ac1" => data <= x"20";
when "11" & x"ac2" => data <= x"30";
when "11" & x"ac3" => data <= x"b7";
when "11" & x"ac4" => data <= x"8d";
when "11" & x"ac5" => data <= x"5b";
when "11" & x"ac6" => data <= x"0d";
when "11" & x"ac7" => data <= x"20";
when "11" & x"ac8" => data <= x"25";
when "11" & x"ac9" => data <= x"bb";
when "11" & x"aca" => data <= x"08";
when "11" & x"acb" => data <= x"48";
when "11" & x"acc" => data <= x"a9";
when "11" & x"acd" => data <= x"0f";
when "11" & x"ace" => data <= x"91";
when "11" & x"acf" => data <= x"f2";
when "11" & x"ad0" => data <= x"88";
when "11" & x"ad1" => data <= x"a9";
when "11" & x"ad2" => data <= x"00";
when "11" & x"ad3" => data <= x"91";
when "11" & x"ad4" => data <= x"f2";
when "11" & x"ad5" => data <= x"88";
when "11" & x"ad6" => data <= x"10";
when "11" & x"ad7" => data <= x"fb";
when "11" & x"ad8" => data <= x"20";
when "11" & x"ad9" => data <= x"b8";
when "11" & x"ada" => data <= x"b0";
when "11" & x"adb" => data <= x"68";
when "11" & x"adc" => data <= x"28";
when "11" & x"add" => data <= x"08";
when "11" & x"ade" => data <= x"48";
when "11" & x"adf" => data <= x"20";
when "11" & x"ae0" => data <= x"63";
when "11" & x"ae1" => data <= x"af";
when "11" & x"ae2" => data <= x"68";
when "11" & x"ae3" => data <= x"28";
when "11" & x"ae4" => data <= x"08";
when "11" & x"ae5" => data <= x"48";
when "11" & x"ae6" => data <= x"ae";
when "11" & x"ae7" => data <= x"5b";
when "11" & x"ae8" => data <= x"0d";
when "11" & x"ae9" => data <= x"20";
when "11" & x"aea" => data <= x"0f";
when "11" & x"aeb" => data <= x"b0";
when "11" & x"aec" => data <= x"20";
when "11" & x"aed" => data <= x"44";
when "11" & x"aee" => data <= x"b6";
when "11" & x"aef" => data <= x"44";
when "11" & x"af0" => data <= x"69";
when "11" & x"af1" => data <= x"73";
when "11" & x"af2" => data <= x"6b";
when "11" & x"af3" => data <= x"20";
when "11" & x"af4" => data <= x"00";
when "11" & x"af5" => data <= x"68";
when "11" & x"af6" => data <= x"28";
when "11" & x"af7" => data <= x"20";
when "11" & x"af8" => data <= x"6c";
when "11" & x"af9" => data <= x"ad";
when "11" & x"afa" => data <= x"8e";
when "11" & x"afb" => data <= x"55";
when "11" & x"afc" => data <= x"0d";
when "11" & x"afd" => data <= x"a2";
when "11" & x"afe" => data <= x"00";
when "11" & x"aff" => data <= x"a0";
when "11" & x"b00" => data <= x"04";
when "11" & x"b01" => data <= x"20";
when "11" & x"b02" => data <= x"26";
when "11" & x"b03" => data <= x"b6";
when "11" & x"b04" => data <= x"ad";
when "11" & x"b05" => data <= x"55";
when "11" & x"b06" => data <= x"0d";
when "11" & x"b07" => data <= x"20";
when "11" & x"b08" => data <= x"26";
when "11" & x"b09" => data <= x"b6";
when "11" & x"b0a" => data <= x"20";
when "11" & x"b0b" => data <= x"44";
when "11" & x"b0c" => data <= x"b6";
when "11" & x"b0d" => data <= x"20";
when "11" & x"b0e" => data <= x"69";
when "11" & x"b0f" => data <= x"6e";
when "11" & x"b10" => data <= x"20";
when "11" & x"b11" => data <= x"64";
when "11" & x"b12" => data <= x"72";
when "11" & x"b13" => data <= x"69";
when "11" & x"b14" => data <= x"76";
when "11" & x"b15" => data <= x"65";
when "11" & x"b16" => data <= x"20";
when "11" & x"b17" => data <= x"00";
when "11" & x"b18" => data <= x"ad";
when "11" & x"b19" => data <= x"5b";
when "11" & x"b1a" => data <= x"0d";
when "11" & x"b1b" => data <= x"a2";
when "11" & x"b1c" => data <= x"00";
when "11" & x"b1d" => data <= x"a0";
when "11" & x"b1e" => data <= x"02";
when "11" & x"b1f" => data <= x"20";
when "11" & x"b20" => data <= x"26";
when "11" & x"b21" => data <= x"b6";
when "11" & x"b22" => data <= x"4c";
when "11" & x"b23" => data <= x"e7";
when "11" & x"b24" => data <= x"ff";
when "11" & x"b25" => data <= x"a9";
when "11" & x"b26" => data <= x"10";
when "11" & x"b27" => data <= x"85";
when "11" & x"b28" => data <= x"f2";
when "11" & x"b29" => data <= x"a9";
when "11" & x"b2a" => data <= x"0e";
when "11" & x"b2b" => data <= x"85";
when "11" & x"b2c" => data <= x"f3";
when "11" & x"b2d" => data <= x"a9";
when "11" & x"b2e" => data <= x"80";
when "11" & x"b2f" => data <= x"8d";
when "11" & x"b30" => data <= x"52";
when "11" & x"b31" => data <= x"0d";
when "11" & x"b32" => data <= x"20";
when "11" & x"b33" => data <= x"a1";
when "11" & x"b34" => data <= x"b0";
when "11" & x"b35" => data <= x"a9";
when "11" & x"b36" => data <= x"00";
when "11" & x"b37" => data <= x"8d";
when "11" & x"b38" => data <= x"53";
when "11" & x"b39" => data <= x"0d";
when "11" & x"b3a" => data <= x"8d";
when "11" & x"b3b" => data <= x"54";
when "11" & x"b3c" => data <= x"0d";
when "11" & x"b3d" => data <= x"a0";
when "11" & x"b3e" => data <= x"0f";
when "11" & x"b3f" => data <= x"b1";
when "11" & x"b40" => data <= x"f2";
when "11" & x"b41" => data <= x"10";
when "11" & x"b42" => data <= x"0c";
when "11" & x"b43" => data <= x"c9";
when "11" & x"b44" => data <= x"ff";
when "11" & x"b45" => data <= x"f0";
when "11" & x"b46" => data <= x"36";
when "11" & x"b47" => data <= x"ad";
when "11" & x"b48" => data <= x"54";
when "11" & x"b49" => data <= x"0d";
when "11" & x"b4a" => data <= x"6a";
when "11" & x"b4b" => data <= x"ad";
when "11" & x"b4c" => data <= x"53";
when "11" & x"b4d" => data <= x"0d";
when "11" & x"b4e" => data <= x"60";
when "11" & x"b4f" => data <= x"ee";
when "11" & x"b50" => data <= x"53";
when "11" & x"b51" => data <= x"0d";
when "11" & x"b52" => data <= x"d0";
when "11" & x"b53" => data <= x"03";
when "11" & x"b54" => data <= x"ee";
when "11" & x"b55" => data <= x"54";
when "11" & x"b56" => data <= x"0d";
when "11" & x"b57" => data <= x"18";
when "11" & x"b58" => data <= x"a5";
when "11" & x"b59" => data <= x"f2";
when "11" & x"b5a" => data <= x"69";
when "11" & x"b5b" => data <= x"10";
when "11" & x"b5c" => data <= x"85";
when "11" & x"b5d" => data <= x"f2";
when "11" & x"b5e" => data <= x"d0";
when "11" & x"b5f" => data <= x"df";
when "11" & x"b60" => data <= x"a5";
when "11" & x"b61" => data <= x"f3";
when "11" & x"b62" => data <= x"49";
when "11" & x"b63" => data <= x"01";
when "11" & x"b64" => data <= x"85";
when "11" & x"b65" => data <= x"f3";
when "11" & x"b66" => data <= x"29";
when "11" & x"b67" => data <= x"01";
when "11" & x"b68" => data <= x"d0";
when "11" & x"b69" => data <= x"d5";
when "11" & x"b6a" => data <= x"18";
when "11" & x"b6b" => data <= x"ad";
when "11" & x"b6c" => data <= x"52";
when "11" & x"b6d" => data <= x"0d";
when "11" & x"b6e" => data <= x"69";
when "11" & x"b6f" => data <= x"01";
when "11" & x"b70" => data <= x"c9";
when "11" & x"b71" => data <= x"90";
when "11" & x"b72" => data <= x"f0";
when "11" & x"b73" => data <= x"09";
when "11" & x"b74" => data <= x"8d";
when "11" & x"b75" => data <= x"52";
when "11" & x"b76" => data <= x"0d";
when "11" & x"b77" => data <= x"20";
when "11" & x"b78" => data <= x"a1";
when "11" & x"b79" => data <= x"b0";
when "11" & x"b7a" => data <= x"4c";
when "11" & x"b7b" => data <= x"3d";
when "11" & x"b7c" => data <= x"bb";
when "11" & x"b7d" => data <= x"20";
when "11" & x"b7e" => data <= x"00";
when "11" & x"b7f" => data <= x"a0";
when "11" & x"b80" => data <= x"ff";
when "11" & x"b81" => data <= x"4e";
when "11" & x"b82" => data <= x"6f";
when "11" & x"b83" => data <= x"20";
when "11" & x"b84" => data <= x"66";
when "11" & x"b85" => data <= x"72";
when "11" & x"b86" => data <= x"65";
when "11" & x"b87" => data <= x"65";
when "11" & x"b88" => data <= x"20";
when "11" & x"b89" => data <= x"64";
when "11" & x"b8a" => data <= x"69";
when "11" & x"b8b" => data <= x"73";
when "11" & x"b8c" => data <= x"6b";
when "11" & x"b8d" => data <= x"73";
when "11" & x"b8e" => data <= x"00";
when "11" & x"b8f" => data <= x"20";
when "11" & x"b90" => data <= x"8a";
when "11" & x"b91" => data <= x"b7";
when "11" & x"b92" => data <= x"08";
when "11" & x"b93" => data <= x"48";
when "11" & x"b94" => data <= x"8a";
when "11" & x"b95" => data <= x"48";
when "11" & x"b96" => data <= x"a9";
when "11" & x"b97" => data <= x"80";
when "11" & x"b98" => data <= x"20";
when "11" & x"b99" => data <= x"a1";
when "11" & x"b9a" => data <= x"b0";
when "11" & x"b9b" => data <= x"68";
when "11" & x"b9c" => data <= x"aa";
when "11" & x"b9d" => data <= x"68";
when "11" & x"b9e" => data <= x"9d";
when "11" & x"b9f" => data <= x"00";
when "11" & x"ba0" => data <= x"0e";
when "11" & x"ba1" => data <= x"68";
when "11" & x"ba2" => data <= x"29";
when "11" & x"ba3" => data <= x"01";
when "11" & x"ba4" => data <= x"9d";
when "11" & x"ba5" => data <= x"04";
when "11" & x"ba6" => data <= x"0e";
when "11" & x"ba7" => data <= x"4c";
when "11" & x"ba8" => data <= x"b8";
when "11" & x"ba9" => data <= x"b0";
when "11" & x"baa" => data <= x"20";
when "11" & x"bab" => data <= x"e4";
when "11" & x"bac" => data <= x"bb";
when "11" & x"bad" => data <= x"20";
when "11" & x"bae" => data <= x"b0";
when "11" & x"baf" => data <= x"b4";
when "11" & x"bb0" => data <= x"a2";
when "11" & x"bb1" => data <= x"00";
when "11" & x"bb2" => data <= x"b0";
when "11" & x"bb3" => data <= x"10";
when "11" & x"bb4" => data <= x"20";
when "11" & x"bb5" => data <= x"c3";
when "11" & x"bb6" => data <= x"b4";
when "11" & x"bb7" => data <= x"b0";
when "11" & x"bb8" => data <= x"17";
when "11" & x"bb9" => data <= x"c9";
when "11" & x"bba" => data <= x"00";
when "11" & x"bbb" => data <= x"d0";
when "11" & x"bbc" => data <= x"04";
when "11" & x"bbd" => data <= x"e0";
when "11" & x"bbe" => data <= x"00";
when "11" & x"bbf" => data <= x"f0";
when "11" & x"bc0" => data <= x"03";
when "11" & x"bc1" => data <= x"20";
when "11" & x"bc2" => data <= x"ef";
when "11" & x"bc3" => data <= x"bb";
when "11" & x"bc4" => data <= x"20";
when "11" & x"bc5" => data <= x"e2";
when "11" & x"bc6" => data <= x"8d";
when "11" & x"bc7" => data <= x"a2";
when "11" & x"bc8" => data <= x"ff";
when "11" & x"bc9" => data <= x"8a";
when "11" & x"bca" => data <= x"8d";
when "11" & x"bcb" => data <= x"52";
when "11" & x"bcc" => data <= x"0d";
when "11" & x"bcd" => data <= x"4c";
when "11" & x"bce" => data <= x"3a";
when "11" & x"bcf" => data <= x"b1";
when "11" & x"bd0" => data <= x"20";
when "11" & x"bd1" => data <= x"00";
when "11" & x"bd2" => data <= x"a0";
when "11" & x"bd3" => data <= x"ff";
when "11" & x"bd4" => data <= x"42";
when "11" & x"bd5" => data <= x"61";
when "11" & x"bd6" => data <= x"64";
when "11" & x"bd7" => data <= x"20";
when "11" & x"bd8" => data <= x"66";
when "11" & x"bd9" => data <= x"69";
when "11" & x"bda" => data <= x"6c";
when "11" & x"bdb" => data <= x"65";
when "11" & x"bdc" => data <= x"20";
when "11" & x"bdd" => data <= x"6e";
when "11" & x"bde" => data <= x"75";
when "11" & x"bdf" => data <= x"6d";
when "11" & x"be0" => data <= x"62";
when "11" & x"be1" => data <= x"65";
when "11" & x"be2" => data <= x"72";
when "11" & x"be3" => data <= x"00";
when "11" & x"be4" => data <= x"a2";
when "11" & x"be5" => data <= x"03";
when "11" & x"be6" => data <= x"a9";
when "11" & x"be7" => data <= x"20";
when "11" & x"be8" => data <= x"9d";
when "11" & x"be9" => data <= x"74";
when "11" & x"bea" => data <= x"0d";
when "11" & x"beb" => data <= x"ca";
when "11" & x"bec" => data <= x"10";
when "11" & x"bed" => data <= x"f8";
when "11" & x"bee" => data <= x"60";
when "11" & x"bef" => data <= x"c0";
when "11" & x"bf0" => data <= x"09";
when "11" & x"bf1" => data <= x"b0";
when "11" & x"bf2" => data <= x"dd";
when "11" & x"bf3" => data <= x"a0";
when "11" & x"bf4" => data <= x"03";
when "11" & x"bf5" => data <= x"b1";
when "11" & x"bf6" => data <= x"f2";
when "11" & x"bf7" => data <= x"29";
when "11" & x"bf8" => data <= x"4f";
when "11" & x"bf9" => data <= x"c9";
when "11" & x"bfa" => data <= x"42";
when "11" & x"bfb" => data <= x"d0";
when "11" & x"bfc" => data <= x"d3";
when "11" & x"bfd" => data <= x"a2";
when "11" & x"bfe" => data <= x"00";
when "11" & x"bff" => data <= x"c8";
when "11" & x"c00" => data <= x"b1";
when "11" & x"c01" => data <= x"f2";
when "11" & x"c02" => data <= x"c9";
when "11" & x"c03" => data <= x"20";
when "11" & x"c04" => data <= x"f0";
when "11" & x"c05" => data <= x"f9";
when "11" & x"c06" => data <= x"c9";
when "11" & x"c07" => data <= x"0d";
when "11" & x"c08" => data <= x"f0";
when "11" & x"c09" => data <= x"08";
when "11" & x"c0a" => data <= x"9d";
when "11" & x"c0b" => data <= x"74";
when "11" & x"c0c" => data <= x"0d";
when "11" & x"c0d" => data <= x"e8";
when "11" & x"c0e" => data <= x"e0";
when "11" & x"c0f" => data <= x"04";
when "11" & x"c10" => data <= x"90";
when "11" & x"c11" => data <= x"ed";
when "11" & x"c12" => data <= x"a2";
when "11" & x"c13" => data <= x"00";
when "11" & x"c14" => data <= x"60";
when "11" & x"c15" => data <= x"4c";
when "11" & x"c16" => data <= x"1e";
when "11" & x"c17" => data <= x"bc";
when "11" & x"c18" => data <= x"4c";
when "11" & x"c19" => data <= x"2b";
when "11" & x"c1a" => data <= x"bc";
when "11" & x"c1b" => data <= x"4c";
when "11" & x"c1c" => data <= x"38";
when "11" & x"c1d" => data <= x"bc";
when "11" & x"c1e" => data <= x"20";
when "11" & x"c1f" => data <= x"d8";
when "11" & x"c20" => data <= x"bd";
when "11" & x"c21" => data <= x"20";
when "11" & x"c22" => data <= x"a7";
when "11" & x"c23" => data <= x"bd";
when "11" & x"c24" => data <= x"20";
when "11" & x"c25" => data <= x"d0";
when "11" & x"c26" => data <= x"bd";
when "11" & x"c27" => data <= x"20";
when "11" & x"c28" => data <= x"05";
when "11" & x"c29" => data <= x"be";
when "11" & x"c2a" => data <= x"60";
when "11" & x"c2b" => data <= x"20";
when "11" & x"c2c" => data <= x"d8";
when "11" & x"c2d" => data <= x"bd";
when "11" & x"c2e" => data <= x"20";
when "11" & x"c2f" => data <= x"a7";
when "11" & x"c30" => data <= x"bd";
when "11" & x"c31" => data <= x"20";
when "11" & x"c32" => data <= x"d4";
when "11" & x"c33" => data <= x"bd";
when "11" & x"c34" => data <= x"20";
when "11" & x"c35" => data <= x"05";
when "11" & x"c36" => data <= x"be";
when "11" & x"c37" => data <= x"60";
when "11" & x"c38" => data <= x"a9";
when "11" & x"c39" => data <= x"00";
when "11" & x"c3a" => data <= x"8d";
when "11" & x"c3b" => data <= x"28";
when "11" & x"c3c" => data <= x"0d";
when "11" & x"c3d" => data <= x"20";
when "11" & x"c3e" => data <= x"c2";
when "11" & x"c3f" => data <= x"ff";
when "11" & x"c40" => data <= x"f0";
when "11" & x"c41" => data <= x"6e";
when "11" & x"c42" => data <= x"b1";
when "11" & x"c43" => data <= x"f2";
when "11" & x"c44" => data <= x"c8";
when "11" & x"c45" => data <= x"c9";
when "11" & x"c46" => data <= x"20";
when "11" & x"c47" => data <= x"f0";
when "11" & x"c48" => data <= x"f9";
when "11" & x"c49" => data <= x"b1";
when "11" & x"c4a" => data <= x"f2";
when "11" & x"c4b" => data <= x"88";
when "11" & x"c4c" => data <= x"c9";
when "11" & x"c4d" => data <= x"20";
when "11" & x"c4e" => data <= x"d0";
when "11" & x"c4f" => data <= x"24";
when "11" & x"c50" => data <= x"b1";
when "11" & x"c51" => data <= x"f2";
when "11" & x"c52" => data <= x"38";
when "11" & x"c53" => data <= x"e9";
when "11" & x"c54" => data <= x"30";
when "11" & x"c55" => data <= x"30";
when "11" & x"c56" => data <= x"1d";
when "11" & x"c57" => data <= x"c9";
when "11" & x"c58" => data <= x"0a";
when "11" & x"c59" => data <= x"90";
when "11" & x"c5a" => data <= x"14";
when "11" & x"c5b" => data <= x"e9";
when "11" & x"c5c" => data <= x"07";
when "11" & x"c5d" => data <= x"c9";
when "11" & x"c5e" => data <= x"0a";
when "11" & x"c5f" => data <= x"90";
when "11" & x"c60" => data <= x"13";
when "11" & x"c61" => data <= x"c9";
when "11" & x"c62" => data <= x"10";
when "11" & x"c63" => data <= x"90";
when "11" & x"c64" => data <= x"0a";
when "11" & x"c65" => data <= x"e9";
when "11" & x"c66" => data <= x"20";
when "11" & x"c67" => data <= x"c9";
when "11" & x"c68" => data <= x"0a";
when "11" & x"c69" => data <= x"90";
when "11" & x"c6a" => data <= x"09";
when "11" & x"c6b" => data <= x"c9";
when "11" & x"c6c" => data <= x"10";
when "11" & x"c6d" => data <= x"b0";
when "11" & x"c6e" => data <= x"05";
when "11" & x"c6f" => data <= x"c8";
when "11" & x"c70" => data <= x"c8";
when "11" & x"c71" => data <= x"8d";
when "11" & x"c72" => data <= x"28";
when "11" & x"c73" => data <= x"0d";
when "11" & x"c74" => data <= x"a5";
when "11" & x"c75" => data <= x"f4";
when "11" & x"c76" => data <= x"8d";
when "11" & x"c77" => data <= x"29";
when "11" & x"c78" => data <= x"0d";
when "11" & x"c79" => data <= x"98";
when "11" & x"c7a" => data <= x"48";
when "11" & x"c7b" => data <= x"a0";
when "11" & x"c7c" => data <= x"26";
when "11" & x"c7d" => data <= x"b9";
when "11" & x"c7e" => data <= x"81";
when "11" & x"c7f" => data <= x"bd";
when "11" & x"c80" => data <= x"99";
when "11" & x"c81" => data <= x"52";
when "11" & x"c82" => data <= x"0d";
when "11" & x"c83" => data <= x"88";
when "11" & x"c84" => data <= x"10";
when "11" & x"c85" => data <= x"f7";
when "11" & x"c86" => data <= x"a2";
when "11" & x"c87" => data <= x"0f";
when "11" & x"c88" => data <= x"20";
when "11" & x"c89" => data <= x"52";
when "11" & x"c8a" => data <= x"0d";
when "11" & x"c8b" => data <= x"68";
when "11" & x"c8c" => data <= x"a8";
when "11" & x"c8d" => data <= x"8e";
when "11" & x"c8e" => data <= x"28";
when "11" & x"c8f" => data <= x"0d";
when "11" & x"c90" => data <= x"8a";
when "11" & x"c91" => data <= x"10";
when "11" & x"c92" => data <= x"14";
when "11" & x"c93" => data <= x"20";
when "11" & x"c94" => data <= x"00";
when "11" & x"c95" => data <= x"a0";
when "11" & x"c96" => data <= x"ff";
when "11" & x"c97" => data <= x"4e";
when "11" & x"c98" => data <= x"6f";
when "11" & x"c99" => data <= x"20";
when "11" & x"c9a" => data <= x"53";
when "11" & x"c9b" => data <= x"69";
when "11" & x"c9c" => data <= x"64";
when "11" & x"c9d" => data <= x"65";
when "11" & x"c9e" => data <= x"77";
when "11" & x"c9f" => data <= x"61";
when "11" & x"ca0" => data <= x"79";
when "11" & x"ca1" => data <= x"73";
when "11" & x"ca2" => data <= x"20";
when "11" & x"ca3" => data <= x"52";
when "11" & x"ca4" => data <= x"41";
when "11" & x"ca5" => data <= x"4d";
when "11" & x"ca6" => data <= x"00";
when "11" & x"ca7" => data <= x"20";
when "11" & x"ca8" => data <= x"62";
when "11" & x"ca9" => data <= x"82";
when "11" & x"caa" => data <= x"18";
when "11" & x"cab" => data <= x"20";
when "11" & x"cac" => data <= x"c2";
when "11" & x"cad" => data <= x"ff";
when "11" & x"cae" => data <= x"d0";
when "11" & x"caf" => data <= x"03";
when "11" & x"cb0" => data <= x"4c";
when "11" & x"cb1" => data <= x"f5";
when "11" & x"cb2" => data <= x"b6";
when "11" & x"cb3" => data <= x"20";
when "11" & x"cb4" => data <= x"fe";
when "11" & x"cb5" => data <= x"80";
when "11" & x"cb6" => data <= x"98";
when "11" & x"cb7" => data <= x"20";
when "11" & x"cb8" => data <= x"71";
when "11" & x"cb9" => data <= x"82";
when "11" & x"cba" => data <= x"b9";
when "11" & x"cbb" => data <= x"0e";
when "11" & x"cbc" => data <= x"0f";
when "11" & x"cbd" => data <= x"48";
when "11" & x"cbe" => data <= x"29";
when "11" & x"cbf" => data <= x"03";
when "11" & x"cc0" => data <= x"85";
when "11" & x"cc1" => data <= x"a1";
when "11" & x"cc2" => data <= x"b9";
when "11" & x"cc3" => data <= x"0f";
when "11" & x"cc4" => data <= x"0f";
when "11" & x"cc5" => data <= x"85";
when "11" & x"cc6" => data <= x"a0";
when "11" & x"cc7" => data <= x"68";
when "11" & x"cc8" => data <= x"4a";
when "11" & x"cc9" => data <= x"4a";
when "11" & x"cca" => data <= x"29";
when "11" & x"ccb" => data <= x"03";
when "11" & x"ccc" => data <= x"f0";
when "11" & x"ccd" => data <= x"04";
when "11" & x"cce" => data <= x"49";
when "11" & x"ccf" => data <= x"03";
when "11" & x"cd0" => data <= x"d0";
when "11" & x"cd1" => data <= x"17";
when "11" & x"cd2" => data <= x"b9";
when "11" & x"cd3" => data <= x"0c";
when "11" & x"cd4" => data <= x"0f";
when "11" & x"cd5" => data <= x"d0";
when "11" & x"cd6" => data <= x"12";
when "11" & x"cd7" => data <= x"b9";
when "11" & x"cd8" => data <= x"0d";
when "11" & x"cd9" => data <= x"0f";
when "11" & x"cda" => data <= x"30";
when "11" & x"cdb" => data <= x"0d";
when "11" & x"cdc" => data <= x"8d";
when "11" & x"cdd" => data <= x"27";
when "11" & x"cde" => data <= x"0d";
when "11" & x"cdf" => data <= x"a2";
when "11" & x"ce0" => data <= x"05";
when "11" & x"ce1" => data <= x"c9";
when "11" & x"ce2" => data <= x"40";
when "11" & x"ce3" => data <= x"f0";
when "11" & x"ce4" => data <= x"15";
when "11" & x"ce5" => data <= x"0a";
when "11" & x"ce6" => data <= x"ca";
when "11" & x"ce7" => data <= x"d0";
when "11" & x"ce8" => data <= x"f8";
when "11" & x"ce9" => data <= x"20";
when "11" & x"cea" => data <= x"00";
when "11" & x"ceb" => data <= x"a0";
when "11" & x"cec" => data <= x"ff";
when "11" & x"ced" => data <= x"42";
when "11" & x"cee" => data <= x"61";
when "11" & x"cef" => data <= x"64";
when "11" & x"cf0" => data <= x"20";
when "11" & x"cf1" => data <= x"52";
when "11" & x"cf2" => data <= x"4f";
when "11" & x"cf3" => data <= x"4d";
when "11" & x"cf4" => data <= x"20";
when "11" & x"cf5" => data <= x"73";
when "11" & x"cf6" => data <= x"69";
when "11" & x"cf7" => data <= x"7a";
when "11" & x"cf8" => data <= x"65";
when "11" & x"cf9" => data <= x"00";
when "11" & x"cfa" => data <= x"4e";
when "11" & x"cfb" => data <= x"27";
when "11" & x"cfc" => data <= x"0d";
when "11" & x"cfd" => data <= x"a6";
when "11" & x"cfe" => data <= x"cf";
when "11" & x"cff" => data <= x"20";
when "11" & x"d00" => data <= x"1d";
when "11" & x"d01" => data <= x"ae";
when "11" & x"d02" => data <= x"18";
when "11" & x"d03" => data <= x"ad";
when "11" & x"d04" => data <= x"23";
when "11" & x"d05" => data <= x"0d";
when "11" & x"d06" => data <= x"65";
when "11" & x"d07" => data <= x"a0";
when "11" & x"d08" => data <= x"8d";
when "11" & x"d09" => data <= x"23";
when "11" & x"d0a" => data <= x"0d";
when "11" & x"d0b" => data <= x"ad";
when "11" & x"d0c" => data <= x"24";
when "11" & x"d0d" => data <= x"0d";
when "11" & x"d0e" => data <= x"65";
when "11" & x"d0f" => data <= x"a1";
when "11" & x"d10" => data <= x"8d";
when "11" & x"d11" => data <= x"24";
when "11" & x"d12" => data <= x"0d";
when "11" & x"d13" => data <= x"a9";
when "11" & x"d14" => data <= x"00";
when "11" & x"d15" => data <= x"6d";
when "11" & x"d16" => data <= x"25";
when "11" & x"d17" => data <= x"0d";
when "11" & x"d18" => data <= x"8d";
when "11" & x"d19" => data <= x"25";
when "11" & x"d1a" => data <= x"0d";
when "11" & x"d1b" => data <= x"a0";
when "11" & x"d1c" => data <= x"1c";
when "11" & x"d1d" => data <= x"b9";
when "11" & x"d1e" => data <= x"65";
when "11" & x"d1f" => data <= x"bd";
when "11" & x"d20" => data <= x"99";
when "11" & x"d21" => data <= x"52";
when "11" & x"d22" => data <= x"0d";
when "11" & x"d23" => data <= x"88";
when "11" & x"d24" => data <= x"10";
when "11" & x"d25" => data <= x"f7";
when "11" & x"d26" => data <= x"ad";
when "11" & x"d27" => data <= x"28";
when "11" & x"d28" => data <= x"0d";
when "11" & x"d29" => data <= x"8d";
when "11" & x"d2a" => data <= x"53";
when "11" & x"d2b" => data <= x"0d";
when "11" & x"d2c" => data <= x"ad";
when "11" & x"d2d" => data <= x"29";
when "11" & x"d2e" => data <= x"0d";
when "11" & x"d2f" => data <= x"8d";
when "11" & x"d30" => data <= x"69";
when "11" & x"d31" => data <= x"0d";
when "11" & x"d32" => data <= x"20";
when "11" & x"d33" => data <= x"1f";
when "11" & x"d34" => data <= x"a6";
when "11" & x"d35" => data <= x"a9";
when "11" & x"d36" => data <= x"ff";
when "11" & x"d37" => data <= x"8d";
when "11" & x"d38" => data <= x"82";
when "11" & x"d39" => data <= x"10";
when "11" & x"d3a" => data <= x"20";
when "11" & x"d3b" => data <= x"99";
when "11" & x"d3c" => data <= x"a7";
when "11" & x"d3d" => data <= x"20";
when "11" & x"d3e" => data <= x"52";
when "11" & x"d3f" => data <= x"0d";
when "11" & x"d40" => data <= x"18";
when "11" & x"d41" => data <= x"ad";
when "11" & x"d42" => data <= x"23";
when "11" & x"d43" => data <= x"0d";
when "11" & x"d44" => data <= x"69";
when "11" & x"d45" => data <= x"02";
when "11" & x"d46" => data <= x"8d";
when "11" & x"d47" => data <= x"23";
when "11" & x"d48" => data <= x"0d";
when "11" & x"d49" => data <= x"90";
when "11" & x"d4a" => data <= x"08";
when "11" & x"d4b" => data <= x"ee";
when "11" & x"d4c" => data <= x"24";
when "11" & x"d4d" => data <= x"0d";
when "11" & x"d4e" => data <= x"d0";
when "11" & x"d4f" => data <= x"03";
when "11" & x"d50" => data <= x"ee";
when "11" & x"d51" => data <= x"24";
when "11" & x"d52" => data <= x"0d";
when "11" & x"d53" => data <= x"ee";
when "11" & x"d54" => data <= x"5e";
when "11" & x"d55" => data <= x"0d";
when "11" & x"d56" => data <= x"ee";
when "11" & x"d57" => data <= x"5e";
when "11" & x"d58" => data <= x"0d";
when "11" & x"d59" => data <= x"ee";
when "11" & x"d5a" => data <= x"64";
when "11" & x"d5b" => data <= x"0d";
when "11" & x"d5c" => data <= x"ee";
when "11" & x"d5d" => data <= x"64";
when "11" & x"d5e" => data <= x"0d";
when "11" & x"d5f" => data <= x"ce";
when "11" & x"d60" => data <= x"27";
when "11" & x"d61" => data <= x"0d";
when "11" & x"d62" => data <= x"d0";
when "11" & x"d63" => data <= x"d6";
when "11" & x"d64" => data <= x"60";
when "11" & x"d65" => data <= x"a9";
when "11" & x"d66" => data <= x"00";
when "11" & x"d67" => data <= x"8d";
when "11" & x"d68" => data <= x"30";
when "11" & x"d69" => data <= x"fe";
when "11" & x"d6a" => data <= x"a0";
when "11" & x"d6b" => data <= x"00";
when "11" & x"d6c" => data <= x"b9";
when "11" & x"d6d" => data <= x"00";
when "11" & x"d6e" => data <= x"0e";
when "11" & x"d6f" => data <= x"99";
when "11" & x"d70" => data <= x"00";
when "11" & x"d71" => data <= x"80";
when "11" & x"d72" => data <= x"b9";
when "11" & x"d73" => data <= x"00";
when "11" & x"d74" => data <= x"0f";
when "11" & x"d75" => data <= x"99";
when "11" & x"d76" => data <= x"00";
when "11" & x"d77" => data <= x"81";
when "11" & x"d78" => data <= x"88";
when "11" & x"d79" => data <= x"d0";
when "11" & x"d7a" => data <= x"f1";
when "11" & x"d7b" => data <= x"a9";
when "11" & x"d7c" => data <= x"00";
when "11" & x"d7d" => data <= x"8d";
when "11" & x"d7e" => data <= x"30";
when "11" & x"d7f" => data <= x"fe";
when "11" & x"d80" => data <= x"60";
when "11" & x"d81" => data <= x"8e";
when "11" & x"d82" => data <= x"30";
when "11" & x"d83" => data <= x"fe";
when "11" & x"d84" => data <= x"ad";
when "11" & x"d85" => data <= x"ff";
when "11" & x"d86" => data <= x"bf";
when "11" & x"d87" => data <= x"a8";
when "11" & x"d88" => data <= x"49";
when "11" & x"d89" => data <= x"ff";
when "11" & x"d8a" => data <= x"8d";
when "11" & x"d8b" => data <= x"ff";
when "11" & x"d8c" => data <= x"bf";
when "11" & x"d8d" => data <= x"98";
when "11" & x"d8e" => data <= x"4d";
when "11" & x"d8f" => data <= x"ff";
when "11" & x"d90" => data <= x"bf";
when "11" & x"d91" => data <= x"8c";
when "11" & x"d92" => data <= x"ff";
when "11" & x"d93" => data <= x"bf";
when "11" & x"d94" => data <= x"c9";
when "11" & x"d95" => data <= x"ff";
when "11" & x"d96" => data <= x"d0";
when "11" & x"d97" => data <= x"05";
when "11" & x"d98" => data <= x"ce";
when "11" & x"d99" => data <= x"28";
when "11" & x"d9a" => data <= x"0d";
when "11" & x"d9b" => data <= x"30";
when "11" & x"d9c" => data <= x"03";
when "11" & x"d9d" => data <= x"ca";
when "11" & x"d9e" => data <= x"10";
when "11" & x"d9f" => data <= x"e1";
when "11" & x"da0" => data <= x"ad";
when "11" & x"da1" => data <= x"29";
when "11" & x"da2" => data <= x"0d";
when "11" & x"da3" => data <= x"8d";
when "11" & x"da4" => data <= x"30";
when "11" & x"da5" => data <= x"fe";
when "11" & x"da6" => data <= x"60";
when "11" & x"da7" => data <= x"a2";
when "11" & x"da8" => data <= x"0b";
when "11" & x"da9" => data <= x"bd";
when "11" & x"daa" => data <= x"32";
when "11" & x"dab" => data <= x"be";
when "11" & x"dac" => data <= x"9d";
when "11" & x"dad" => data <= x"70";
when "11" & x"dae" => data <= x"0d";
when "11" & x"daf" => data <= x"ca";
when "11" & x"db0" => data <= x"10";
when "11" & x"db1" => data <= x"f7";
when "11" & x"db2" => data <= x"e8";
when "11" & x"db3" => data <= x"8e";
when "11" & x"db4" => data <= x"05";
when "11" & x"db5" => data <= x"0d";
when "11" & x"db6" => data <= x"8e";
when "11" & x"db7" => data <= x"28";
when "11" & x"db8" => data <= x"0d";
when "11" & x"db9" => data <= x"a9";
when "11" & x"dba" => data <= x"40";
when "11" & x"dbb" => data <= x"8d";
when "11" & x"dbc" => data <= x"27";
when "11" & x"dbd" => data <= x"0d";
when "11" & x"dbe" => data <= x"0a";
when "11" & x"dbf" => data <= x"48";
when "11" & x"dc0" => data <= x"20";
when "11" & x"dc1" => data <= x"1f";
when "11" & x"dc2" => data <= x"a6";
when "11" & x"dc3" => data <= x"68";
when "11" & x"dc4" => data <= x"20";
when "11" & x"dc5" => data <= x"70";
when "11" & x"dc6" => data <= x"b0";
when "11" & x"dc7" => data <= x"a9";
when "11" & x"dc8" => data <= x"00";
when "11" & x"dc9" => data <= x"85";
when "11" & x"dca" => data <= x"a0";
when "11" & x"dcb" => data <= x"a9";
when "11" & x"dcc" => data <= x"20";
when "11" & x"dcd" => data <= x"85";
when "11" & x"dce" => data <= x"a1";
when "11" & x"dcf" => data <= x"60";
when "11" & x"dd0" => data <= x"20";
when "11" & x"dd1" => data <= x"cc";
when "11" & x"dd2" => data <= x"a7";
when "11" & x"dd3" => data <= x"60";
when "11" & x"dd4" => data <= x"20";
when "11" & x"dd5" => data <= x"78";
when "11" & x"dd6" => data <= x"a8";
when "11" & x"dd7" => data <= x"60";
when "11" & x"dd8" => data <= x"a2";
when "11" & x"dd9" => data <= x"0b";
when "11" & x"dda" => data <= x"bd";
when "11" & x"ddb" => data <= x"70";
when "11" & x"ddc" => data <= x"0d";
when "11" & x"ddd" => data <= x"9d";
when "11" & x"dde" => data <= x"60";
when "11" & x"ddf" => data <= x"0d";
when "11" & x"de0" => data <= x"ca";
when "11" & x"de1" => data <= x"10";
when "11" & x"de2" => data <= x"f7";
when "11" & x"de3" => data <= x"a2";
when "11" & x"de4" => data <= x"06";
when "11" & x"de5" => data <= x"bd";
when "11" & x"de6" => data <= x"05";
when "11" & x"de7" => data <= x"0d";
when "11" & x"de8" => data <= x"9d";
when "11" & x"de9" => data <= x"2e";
when "11" & x"dea" => data <= x"0d";
when "11" & x"deb" => data <= x"ca";
when "11" & x"dec" => data <= x"10";
when "11" & x"ded" => data <= x"f7";
when "11" & x"dee" => data <= x"ad";
when "11" & x"def" => data <= x"28";
when "11" & x"df0" => data <= x"0d";
when "11" & x"df1" => data <= x"8d";
when "11" & x"df2" => data <= x"35";
when "11" & x"df3" => data <= x"0d";
when "11" & x"df4" => data <= x"a5";
when "11" & x"df5" => data <= x"a0";
when "11" & x"df6" => data <= x"8d";
when "11" & x"df7" => data <= x"36";
when "11" & x"df8" => data <= x"0d";
when "11" & x"df9" => data <= x"a5";
when "11" & x"dfa" => data <= x"a1";
when "11" & x"dfb" => data <= x"8d";
when "11" & x"dfc" => data <= x"37";
when "11" & x"dfd" => data <= x"0d";
when "11" & x"dfe" => data <= x"ad";
when "11" & x"dff" => data <= x"27";
when "11" & x"e00" => data <= x"0d";
when "11" & x"e01" => data <= x"8d";
when "11" & x"e02" => data <= x"38";
when "11" & x"e03" => data <= x"0d";
when "11" & x"e04" => data <= x"60";
when "11" & x"e05" => data <= x"ad";
when "11" & x"e06" => data <= x"38";
when "11" & x"e07" => data <= x"0d";
when "11" & x"e08" => data <= x"8d";
when "11" & x"e09" => data <= x"27";
when "11" & x"e0a" => data <= x"0d";
when "11" & x"e0b" => data <= x"ad";
when "11" & x"e0c" => data <= x"37";
when "11" & x"e0d" => data <= x"0d";
when "11" & x"e0e" => data <= x"85";
when "11" & x"e0f" => data <= x"a1";
when "11" & x"e10" => data <= x"ad";
when "11" & x"e11" => data <= x"36";
when "11" & x"e12" => data <= x"0d";
when "11" & x"e13" => data <= x"85";
when "11" & x"e14" => data <= x"a0";
when "11" & x"e15" => data <= x"ad";
when "11" & x"e16" => data <= x"35";
when "11" & x"e17" => data <= x"0d";
when "11" & x"e18" => data <= x"8d";
when "11" & x"e19" => data <= x"28";
when "11" & x"e1a" => data <= x"0d";
when "11" & x"e1b" => data <= x"a2";
when "11" & x"e1c" => data <= x"06";
when "11" & x"e1d" => data <= x"bd";
when "11" & x"e1e" => data <= x"2e";
when "11" & x"e1f" => data <= x"0d";
when "11" & x"e20" => data <= x"9d";
when "11" & x"e21" => data <= x"05";
when "11" & x"e22" => data <= x"0d";
when "11" & x"e23" => data <= x"ca";
when "11" & x"e24" => data <= x"10";
when "11" & x"e25" => data <= x"f7";
when "11" & x"e26" => data <= x"a2";
when "11" & x"e27" => data <= x"0b";
when "11" & x"e28" => data <= x"bd";
when "11" & x"e29" => data <= x"60";
when "11" & x"e2a" => data <= x"0d";
when "11" & x"e2b" => data <= x"9d";
when "11" & x"e2c" => data <= x"70";
when "11" & x"e2d" => data <= x"0d";
when "11" & x"e2e" => data <= x"ca";
when "11" & x"e2f" => data <= x"10";
when "11" & x"e30" => data <= x"f7";
when "11" & x"e31" => data <= x"60";
when "11" & x"e32" => data <= x"49";
when "11" & x"e33" => data <= x"4e";
when "11" & x"e34" => data <= x"4f";
when "11" & x"e35" => data <= x"55";
when "11" & x"e36" => data <= x"54";
when "11" & x"e37" => data <= x"4d";
when "11" & x"e38" => data <= x"45";
when "11" & x"e39" => data <= x"4d";
when "11" & x"e3a" => data <= x"20";
when "11" & x"e3b" => data <= x"20";
when "11" & x"e3c" => data <= x"20";
when "11" & x"e3d" => data <= x"20";
when "11" & x"e3e" => data <= x"48";
when "11" & x"e3f" => data <= x"a5";
when "11" & x"e40" => data <= x"cf";
when "11" & x"e41" => data <= x"8d";
when "11" & x"e42" => data <= x"20";
when "11" & x"e43" => data <= x"0d";
when "11" & x"e44" => data <= x"68";
when "11" & x"e45" => data <= x"60";
when "11" & x"e46" => data <= x"a0";
when "11" & x"e47" => data <= x"00";
when "11" & x"e48" => data <= x"b1";
when "11" & x"e49" => data <= x"b0";
when "11" & x"e4a" => data <= x"30";
when "11" & x"e4b" => data <= x"07";
when "11" & x"e4c" => data <= x"29";
when "11" & x"e4d" => data <= x"03";
when "11" & x"e4e" => data <= x"85";
when "11" & x"e4f" => data <= x"cf";
when "11" & x"e50" => data <= x"8d";
when "11" & x"e51" => data <= x"20";
when "11" & x"e52" => data <= x"0d";
when "11" & x"e53" => data <= x"a0";
when "11" & x"e54" => data <= x"05";
when "11" & x"e55" => data <= x"b1";
when "11" & x"e56" => data <= x"b0";
when "11" & x"e57" => data <= x"18";
when "11" & x"e58" => data <= x"69";
when "11" & x"e59" => data <= x"07";
when "11" & x"e5a" => data <= x"85";
when "11" & x"e5b" => data <= x"be";
when "11" & x"e5c" => data <= x"20";
when "11" & x"e5d" => data <= x"6a";
when "11" & x"e5e" => data <= x"be";
when "11" & x"e5f" => data <= x"a4";
when "11" & x"e60" => data <= x"be";
when "11" & x"e61" => data <= x"b0";
when "11" & x"e62" => data <= x"02";
when "11" & x"e63" => data <= x"a9";
when "11" & x"e64" => data <= x"00";
when "11" & x"e65" => data <= x"91";
when "11" & x"e66" => data <= x"b0";
when "11" & x"e67" => data <= x"a9";
when "11" & x"e68" => data <= x"00";
when "11" & x"e69" => data <= x"60";
when "11" & x"e6a" => data <= x"c8";
when "11" & x"e6b" => data <= x"b1";
when "11" & x"e6c" => data <= x"b0";
when "11" & x"e6d" => data <= x"aa";
when "11" & x"e6e" => data <= x"29";
when "11" & x"e6f" => data <= x"3f";
when "11" & x"e70" => data <= x"85";
when "11" & x"e71" => data <= x"bf";
when "11" & x"e72" => data <= x"c9";
when "11" & x"e73" => data <= x"3a";
when "11" & x"e74" => data <= x"d0";
when "11" & x"e75" => data <= x"2f";
when "11" & x"e76" => data <= x"a5";
when "11" & x"e77" => data <= x"be";
when "11" & x"e78" => data <= x"c9";
when "11" & x"e79" => data <= x"09";
when "11" & x"e7a" => data <= x"d0";
when "11" & x"e7b" => data <= x"13";
when "11" & x"e7c" => data <= x"c8";
when "11" & x"e7d" => data <= x"b1";
when "11" & x"e7e" => data <= x"b0";
when "11" & x"e7f" => data <= x"c9";
when "11" & x"e80" => data <= x"23";
when "11" & x"e81" => data <= x"d0";
when "11" & x"e82" => data <= x"0c";
when "11" & x"e83" => data <= x"c8";
when "11" & x"e84" => data <= x"b1";
when "11" & x"e85" => data <= x"b0";
when "11" & x"e86" => data <= x"29";
when "11" & x"e87" => data <= x"20";
when "11" & x"e88" => data <= x"f0";
when "11" & x"e89" => data <= x"02";
when "11" & x"e8a" => data <= x"a9";
when "11" & x"e8b" => data <= x"02";
when "11" & x"e8c" => data <= x"8d";
when "11" & x"e8d" => data <= x"20";
when "11" & x"e8e" => data <= x"0d";
when "11" & x"e8f" => data <= x"18";
when "11" & x"e90" => data <= x"60";
when "11" & x"e91" => data <= x"a9";
when "11" & x"e92" => data <= x"1e";
when "11" & x"e93" => data <= x"38";
when "11" & x"e94" => data <= x"60";
when "11" & x"e95" => data <= x"a9";
when "11" & x"e96" => data <= x"10";
when "11" & x"e97" => data <= x"38";
when "11" & x"e98" => data <= x"60";
when "11" & x"e99" => data <= x"a9";
when "11" & x"e9a" => data <= x"12";
when "11" & x"e9b" => data <= x"38";
when "11" & x"e9c" => data <= x"60";
when "11" & x"e9d" => data <= x"a9";
when "11" & x"e9e" => data <= x"ff";
when "11" & x"e9f" => data <= x"38";
when "11" & x"ea0" => data <= x"60";
when "11" & x"ea1" => data <= x"a9";
when "11" & x"ea2" => data <= x"1e";
when "11" & x"ea3" => data <= x"38";
when "11" & x"ea4" => data <= x"60";
when "11" & x"ea5" => data <= x"a5";
when "11" & x"ea6" => data <= x"cf";
when "11" & x"ea7" => data <= x"6a";
when "11" & x"ea8" => data <= x"8a";
when "11" & x"ea9" => data <= x"90";
when "11" & x"eaa" => data <= x"02";
when "11" & x"eab" => data <= x"49";
when "11" & x"eac" => data <= x"c0";
when "11" & x"ead" => data <= x"2a";
when "11" & x"eae" => data <= x"90";
when "11" & x"eaf" => data <= x"0c";
when "11" & x"eb0" => data <= x"2a";
when "11" & x"eb1" => data <= x"b0";
when "11" & x"eb2" => data <= x"de";
when "11" & x"eb3" => data <= x"ad";
when "11" & x"eb4" => data <= x"20";
when "11" & x"eb5" => data <= x"0d";
when "11" & x"eb6" => data <= x"29";
when "11" & x"eb7" => data <= x"02";
when "11" & x"eb8" => data <= x"09";
when "11" & x"eb9" => data <= x"01";
when "11" & x"eba" => data <= x"d0";
when "11" & x"ebb" => data <= x"08";
when "11" & x"ebc" => data <= x"2a";
when "11" & x"ebd" => data <= x"90";
when "11" & x"ebe" => data <= x"d6";
when "11" & x"ebf" => data <= x"ad";
when "11" & x"ec0" => data <= x"20";
when "11" & x"ec1" => data <= x"0d";
when "11" & x"ec2" => data <= x"29";
when "11" & x"ec3" => data <= x"02";
when "11" & x"ec4" => data <= x"8d";
when "11" & x"ec5" => data <= x"20";
when "11" & x"ec6" => data <= x"0d";
when "11" & x"ec7" => data <= x"aa";
when "11" & x"ec8" => data <= x"86";
when "11" & x"ec9" => data <= x"c0";
when "11" & x"eca" => data <= x"bd";
when "11" & x"ecb" => data <= x"10";
when "11" & x"ecc" => data <= x"0d";
when "11" & x"ecd" => data <= x"30";
when "11" & x"ece" => data <= x"c6";
when "11" & x"ecf" => data <= x"a5";
when "11" & x"ed0" => data <= x"bf";
when "11" & x"ed1" => data <= x"c9";
when "11" & x"ed2" => data <= x"13";
when "11" & x"ed3" => data <= x"f0";
when "11" & x"ed4" => data <= x"0b";
when "11" & x"ed5" => data <= x"c9";
when "11" & x"ed6" => data <= x"0b";
when "11" & x"ed7" => data <= x"d0";
when "11" & x"ed8" => data <= x"b6";
when "11" & x"ed9" => data <= x"bd";
when "11" & x"eda" => data <= x"1c";
when "11" & x"edb" => data <= x"0d";
when "11" & x"edc" => data <= x"c9";
when "11" & x"edd" => data <= x"54";
when "11" & x"ede" => data <= x"d0";
when "11" & x"edf" => data <= x"b9";
when "11" & x"ee0" => data <= x"a5";
when "11" & x"ee1" => data <= x"be";
when "11" & x"ee2" => data <= x"c9";
when "11" & x"ee3" => data <= x"0a";
when "11" & x"ee4" => data <= x"d0";
when "11" & x"ee5" => data <= x"b7";
when "11" & x"ee6" => data <= x"20";
when "11" & x"ee7" => data <= x"1f";
when "11" & x"ee8" => data <= x"a6";
when "11" & x"ee9" => data <= x"a9";
when "11" & x"eea" => data <= x"00";
when "11" & x"eeb" => data <= x"85";
when "11" & x"eec" => data <= x"c5";
when "11" & x"eed" => data <= x"c8";
when "11" & x"eee" => data <= x"b1";
when "11" & x"eef" => data <= x"b0";
when "11" & x"ef0" => data <= x"c9";
when "11" & x"ef1" => data <= x"50";
when "11" & x"ef2" => data <= x"b0";
when "11" & x"ef3" => data <= x"9d";
when "11" & x"ef4" => data <= x"0a";
when "11" & x"ef5" => data <= x"85";
when "11" & x"ef6" => data <= x"c4";
when "11" & x"ef7" => data <= x"0a";
when "11" & x"ef8" => data <= x"26";
when "11" & x"ef9" => data <= x"c5";
when "11" & x"efa" => data <= x"0a";
when "11" & x"efb" => data <= x"26";
when "11" & x"efc" => data <= x"c5";
when "11" & x"efd" => data <= x"65";
when "11" & x"efe" => data <= x"c4";
when "11" & x"eff" => data <= x"85";
when "11" & x"f00" => data <= x"c4";
when "11" & x"f01" => data <= x"90";
when "11" & x"f02" => data <= x"02";
when "11" & x"f03" => data <= x"e6";
when "11" & x"f04" => data <= x"c5";
when "11" & x"f05" => data <= x"c8";
when "11" & x"f06" => data <= x"b1";
when "11" & x"f07" => data <= x"b0";
when "11" & x"f08" => data <= x"c9";
when "11" & x"f09" => data <= x"0a";
when "11" & x"f0a" => data <= x"b0";
when "11" & x"f0b" => data <= x"95";
when "11" & x"f0c" => data <= x"18";
when "11" & x"f0d" => data <= x"65";
when "11" & x"f0e" => data <= x"c4";
when "11" & x"f0f" => data <= x"85";
when "11" & x"f10" => data <= x"c4";
when "11" & x"f11" => data <= x"90";
when "11" & x"f12" => data <= x"02";
when "11" & x"f13" => data <= x"e6";
when "11" & x"f14" => data <= x"c5";
when "11" & x"f15" => data <= x"18";
when "11" & x"f16" => data <= x"a9";
when "11" & x"f17" => data <= x"00";
when "11" & x"f18" => data <= x"8d";
when "11" & x"f19" => data <= x"28";
when "11" & x"f1a" => data <= x"0d";
when "11" & x"f1b" => data <= x"a5";
when "11" & x"f1c" => data <= x"c5";
when "11" & x"f1d" => data <= x"6a";
when "11" & x"f1e" => data <= x"48";
when "11" & x"f1f" => data <= x"a5";
when "11" & x"f20" => data <= x"c4";
when "11" & x"f21" => data <= x"6a";
when "11" & x"f22" => data <= x"48";
when "11" & x"f23" => data <= x"90";
when "11" & x"f24" => data <= x"03";
when "11" & x"f25" => data <= x"6e";
when "11" & x"f26" => data <= x"28";
when "11" & x"f27" => data <= x"0d";
when "11" & x"f28" => data <= x"c8";
when "11" & x"f29" => data <= x"b1";
when "11" & x"f2a" => data <= x"b0";
when "11" & x"f2b" => data <= x"29";
when "11" & x"f2c" => data <= x"1f";
when "11" & x"f2d" => data <= x"8d";
when "11" & x"f2e" => data <= x"27";
when "11" & x"f2f" => data <= x"0d";
when "11" & x"f30" => data <= x"f0";
when "11" & x"f31" => data <= x"55";
when "11" & x"f32" => data <= x"18";
when "11" & x"f33" => data <= x"65";
when "11" & x"f34" => data <= x"c4";
when "11" & x"f35" => data <= x"aa";
when "11" & x"f36" => data <= x"a9";
when "11" & x"f37" => data <= x"00";
when "11" & x"f38" => data <= x"65";
when "11" & x"f39" => data <= x"c5";
when "11" & x"f3a" => data <= x"c9";
when "11" & x"f3b" => data <= x"03";
when "11" & x"f3c" => data <= x"90";
when "11" & x"f3d" => data <= x"06";
when "11" & x"f3e" => data <= x"d0";
when "11" & x"f3f" => data <= x"51";
when "11" & x"f40" => data <= x"e0";
when "11" & x"f41" => data <= x"21";
when "11" & x"f42" => data <= x"b0";
when "11" & x"f43" => data <= x"4d";
when "11" & x"f44" => data <= x"a6";
when "11" & x"f45" => data <= x"c0";
when "11" & x"f46" => data <= x"bd";
when "11" & x"f47" => data <= x"10";
when "11" & x"f48" => data <= x"0d";
when "11" & x"f49" => data <= x"6a";
when "11" & x"f4a" => data <= x"bd";
when "11" & x"f4b" => data <= x"0c";
when "11" & x"f4c" => data <= x"0d";
when "11" & x"f4d" => data <= x"20";
when "11" & x"f4e" => data <= x"26";
when "11" & x"f4f" => data <= x"ae";
when "11" & x"f50" => data <= x"18";
when "11" & x"f51" => data <= x"68";
when "11" & x"f52" => data <= x"6d";
when "11" & x"f53" => data <= x"23";
when "11" & x"f54" => data <= x"0d";
when "11" & x"f55" => data <= x"8d";
when "11" & x"f56" => data <= x"23";
when "11" & x"f57" => data <= x"0d";
when "11" & x"f58" => data <= x"68";
when "11" & x"f59" => data <= x"6d";
when "11" & x"f5a" => data <= x"24";
when "11" & x"f5b" => data <= x"0d";
when "11" & x"f5c" => data <= x"8d";
when "11" & x"f5d" => data <= x"24";
when "11" & x"f5e" => data <= x"0d";
when "11" & x"f5f" => data <= x"ad";
when "11" & x"f60" => data <= x"25";
when "11" & x"f61" => data <= x"0d";
when "11" & x"f62" => data <= x"69";
when "11" & x"f63" => data <= x"00";
when "11" & x"f64" => data <= x"8d";
when "11" & x"f65" => data <= x"25";
when "11" & x"f66" => data <= x"0d";
when "11" & x"f67" => data <= x"ad";
when "11" & x"f68" => data <= x"26";
when "11" & x"f69" => data <= x"0d";
when "11" & x"f6a" => data <= x"69";
when "11" & x"f6b" => data <= x"00";
when "11" & x"f6c" => data <= x"8d";
when "11" & x"f6d" => data <= x"26";
when "11" & x"f6e" => data <= x"0d";
when "11" & x"f6f" => data <= x"a0";
when "11" & x"f70" => data <= x"00";
when "11" & x"f71" => data <= x"8c";
when "11" & x"f72" => data <= x"29";
when "11" & x"f73" => data <= x"0d";
when "11" & x"f74" => data <= x"c8";
when "11" & x"f75" => data <= x"b1";
when "11" & x"f76" => data <= x"b0";
when "11" & x"f77" => data <= x"85";
when "11" & x"f78" => data <= x"a0";
when "11" & x"f79" => data <= x"c8";
when "11" & x"f7a" => data <= x"b1";
when "11" & x"f7b" => data <= x"b0";
when "11" & x"f7c" => data <= x"85";
when "11" & x"f7d" => data <= x"a1";
when "11" & x"f7e" => data <= x"a5";
when "11" & x"f7f" => data <= x"bf";
when "11" & x"f80" => data <= x"c9";
when "11" & x"f81" => data <= x"13";
when "11" & x"f82" => data <= x"f0";
when "11" & x"f83" => data <= x"05";
when "11" & x"f84" => data <= x"20";
when "11" & x"f85" => data <= x"9f";
when "11" & x"f86" => data <= x"af";
when "11" & x"f87" => data <= x"18";
when "11" & x"f88" => data <= x"60";
when "11" & x"f89" => data <= x"20";
when "11" & x"f8a" => data <= x"cc";
when "11" & x"f8b" => data <= x"a7";
when "11" & x"f8c" => data <= x"20";
when "11" & x"f8d" => data <= x"cd";
when "11" & x"f8e" => data <= x"a0";
when "11" & x"f8f" => data <= x"18";
when "11" & x"f90" => data <= x"60";
when "11" & x"f91" => data <= x"a9";
when "11" & x"f92" => data <= x"1e";
when "11" & x"f93" => data <= x"38";
when "11" & x"f94" => data <= x"60";
when "11" & x"f95" => data <= x"44";
when "11" & x"f96" => data <= x"55";
when "11" & x"f97" => data <= x"49";
when "11" & x"f98" => data <= x"4b";
when "11" & x"f99" => data <= x"20";
when "11" & x"f9a" => data <= x"44";
when "11" & x"f9b" => data <= x"55";
when "11" & x"f9c" => data <= x"49";
when "11" & x"f9d" => data <= x"4b";
when "11" & x"f9e" => data <= x"20";
when "11" & x"f9f" => data <= x"44";
when "11" & x"fa0" => data <= x"55";
when "11" & x"fa1" => data <= x"49";
when "11" & x"fa2" => data <= x"4b";
when "11" & x"fa3" => data <= x"20";
when "11" & x"fa4" => data <= x"44";
when "11" & x"fa5" => data <= x"55";
when "11" & x"fa6" => data <= x"49";
when "11" & x"fa7" => data <= x"4b";
when "11" & x"fa8" => data <= x"20";
when "11" & x"fa9" => data <= x"44";
when "11" & x"faa" => data <= x"55";
when "11" & x"fab" => data <= x"49";
when "11" & x"fac" => data <= x"4b";
when "11" & x"fad" => data <= x"20";
when "11" & x"fae" => data <= x"44";
when "11" & x"faf" => data <= x"55";
when "11" & x"fb0" => data <= x"49";
when "11" & x"fb1" => data <= x"4b";
when "11" & x"fb2" => data <= x"20";
when "11" & x"fb3" => data <= x"44";
when "11" & x"fb4" => data <= x"55";
when "11" & x"fb5" => data <= x"49";
when "11" & x"fb6" => data <= x"4b";
when "11" & x"fb7" => data <= x"20";
when "11" & x"fb8" => data <= x"44";
when "11" & x"fb9" => data <= x"55";
when "11" & x"fba" => data <= x"49";
when "11" & x"fbb" => data <= x"4b";
when "11" & x"fbc" => data <= x"20";
when "11" & x"fbd" => data <= x"44";
when "11" & x"fbe" => data <= x"55";
when "11" & x"fbf" => data <= x"49";
when "11" & x"fc0" => data <= x"4b";
when "11" & x"fc1" => data <= x"20";
when "11" & x"fc2" => data <= x"44";
when "11" & x"fc3" => data <= x"55";
when "11" & x"fc4" => data <= x"49";
when "11" & x"fc5" => data <= x"4b";
when "11" & x"fc6" => data <= x"20";
when "11" & x"fc7" => data <= x"44";
when "11" & x"fc8" => data <= x"55";
when "11" & x"fc9" => data <= x"49";
when "11" & x"fca" => data <= x"4b";
when "11" & x"fcb" => data <= x"20";
when "11" & x"fcc" => data <= x"44";
when "11" & x"fcd" => data <= x"55";
when "11" & x"fce" => data <= x"49";
when "11" & x"fcf" => data <= x"4b";
when "11" & x"fd0" => data <= x"20";
when "11" & x"fd1" => data <= x"44";
when "11" & x"fd2" => data <= x"55";
when "11" & x"fd3" => data <= x"49";
when "11" & x"fd4" => data <= x"4b";
when "11" & x"fd5" => data <= x"20";
when "11" & x"fd6" => data <= x"44";
when "11" & x"fd7" => data <= x"55";
when "11" & x"fd8" => data <= x"49";
when "11" & x"fd9" => data <= x"4b";
when "11" & x"fda" => data <= x"20";
when "11" & x"fdb" => data <= x"44";
when "11" & x"fdc" => data <= x"55";
when "11" & x"fdd" => data <= x"49";
when "11" & x"fde" => data <= x"4b";
when "11" & x"fdf" => data <= x"20";
when "11" & x"fe0" => data <= x"44";
when "11" & x"fe1" => data <= x"55";
when "11" & x"fe2" => data <= x"49";
when "11" & x"fe3" => data <= x"4b";
when "11" & x"fe4" => data <= x"20";
when "11" & x"fe5" => data <= x"44";
when "11" & x"fe6" => data <= x"55";
when "11" & x"fe7" => data <= x"49";
when "11" & x"fe8" => data <= x"4b";
when "11" & x"fe9" => data <= x"20";
when "11" & x"fea" => data <= x"44";
when "11" & x"feb" => data <= x"55";
when "11" & x"fec" => data <= x"49";
when "11" & x"fed" => data <= x"4b";
when "11" & x"fee" => data <= x"20";
when "11" & x"fef" => data <= x"44";
when "11" & x"ff0" => data <= x"55";
when "11" & x"ff1" => data <= x"49";
when "11" & x"ff2" => data <= x"4b";
when "11" & x"ff3" => data <= x"20";
when "11" & x"ff4" => data <= x"44";
when "11" & x"ff5" => data <= x"55";
when "11" & x"ff6" => data <= x"49";
when "11" & x"ff7" => data <= x"4b";
when "11" & x"ff8" => data <= x"20";
when "11" & x"ff9" => data <= x"44";
when "11" & x"ffa" => data <= x"55";
when "11" & x"ffb" => data <= x"49";
when "11" & x"ffc" => data <= x"4b";
when "11" & x"ffd" => data <= x"20";
when "11" & x"ffe" => data <= x"44";
when "11" & x"fff" => data <= x"00";
when others => data <= (others => '0');
end case;
end process;
end RTL;
| gpl-3.0 | 5a7e017da7832ce98a6180425d1b62c7 | 0.34714 | 2.668982 | false | false | false | false |
DreamIP/GPStudio | support/toolchain/caph/hdl/caph_toplevel/src/untokenize_flow.vhd | 1 | 2,613 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.caph_flow_pkg.all;
entity untokenize_flow is
generic(
IMAGE_WIDTH:integer := 320;
IMAGE_HEIGHT:integer := 240;
TOKEN_SIZE: integer := 10;
SIZE:integer:=8
);
port (
clk_caph: in std_logic;
clk_proc: in std_logic;
rst_n_i : in std_logic;
fifo_empty: in std_logic;
data_i : in std_logic_vector(TOKEN_SIZE-1 downto 0);
imwidth_i : in std_LOGIC_VECTOR(31 downto 0);
imheight_i : in std_LOGIC_VECTOR(31 downto 0);
fifo_unpile: out std_logic;
frame_valid_o :out std_logic;
data_valid_o :out std_logic;
data_o : out std_logic_vector (SIZE-1 downto 0)
);
end entity untokenize_flow;
architecture rtl of untokenize_flow is
signal frame_valid_s : std_logic;
signal data_valid_s : std_logic;
signal data_s : std_logic_vector (SIZE-1 downto 0);
signal frame_valid_sr : std_logic;
signal data_valid_sr : std_logic;
signal data_sr : std_logic_vector (SIZE-1 downto 0);
signal linecpt : integer range 0 to MAX_IMAGE_HEIGHT := 0;
begin
process(clk_caph,rst_n_i)
variable datacpt : integer range 0 to MAX_IMAGE_WIDTH := 0;
begin
if (rst_n_i = '0') then
frame_valid_s<='0';
data_valid_s<='0';
data_s <= (others=>'0');
datacpt := 0;
linecpt <= 0;
elsif rising_edge(clk_caph) then
data_valid_s <= '0';
if (data_i(TOKEN_SIZE-1 downto TOKEN_SIZE-2) = CaphHeader(Data)) then
data_s <= data_i(7 downto 0);
data_valid_s <= '1';
frame_valid_s <= '1';
datacpt := datacpt + 1;
if(datacpt = to_integer(unsigned(imwidth_i))) then
datacpt := 0;
linecpt <= linecpt+1;
end if;
end if;
if(linecpt= to_integer(unsigned(imheight_i))) then
frame_valid_s <= '0';
data_valid_s <= '0';
datacpt := 0;
linecpt <= 0;
end if;
end if;
end process;
fifo_unpile <= not(fifo_empty);
data_valid_o <= data_valid_s;
frame_valid_o <= frame_valid_s;
data_o <= data_s;
--SyncCLKPROC: process(clk_caph,rst_n_i)
--begin
-- if (rst_n_i = '0') then
-- data_sr <= (others=>'0');
-- data_valid_sr <= '0';
-- frame_valid_sr <= '0';
-- data_o <= (others=>'0');
-- data_valid_o <= '0';
-- frame_valid_o <= '0';
-- elsif rising_edge(clk_caph) then
--
-- data_sr <= data_s;
-- data_o <= data_sr;
--
-- data_valid_sr <= data_valid_s;
-- data_valid_o <= data_valid_sr;
--
-- frame_valid_sr <= frame_valid_s;
-- frame_valid_o <= frame_valid_sr;
--
-- end if;
--end process;
end architecture; | gpl-3.0 | 94484ebd4cd6a87b14a3b6897ed7aa41 | 0.586299 | 2.524638 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/IP/IP_complete_nomac.vhd | 1 | 15,305 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:43:16 06/04/2011
-- Design Name:
-- Module Name: IP_complete_nomac - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Implements complete IP stack with ARP (but no MAC)
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - separated RX and TX clocks
-- Revision 0.03 - Added mac_tx_tfirst
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
use work.arp;
use work.arpv2;
entity IP_complete_nomac is
generic (
use_arpv2 : boolean := true; -- use ARP with multipule entries. for signel entry, set
-- to false
no_default_gateway : boolean := false; -- set to false if communicating with devices accessed
-- through a "default gateway or router"
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in ip_control_type;
-- status signals
arp_pkt_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
ip_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tfirst : in std_logic;
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
end IP_complete_nomac;
architecture structural of IP_complete_nomac is
component IPv4
port(
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system control signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- system status signals
rx_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer RX signals
mac_data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in std_logic; -- indicates data_in valid on clock
mac_data_in_first : in std_logic;
mac_data_in_last : in std_logic; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
end component;
component arp
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 1; -- (added for compatibility with arpv2. this value not used in this impl)
MAX_ARP_ENTRIES : integer := 1 -- (added for compatibility with arpv2. this value not used in this impl)
);
port (
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
-- MAC layer RX signals
data_in_clk : in std_logic;
reset : in std_logic;
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_clk : in std_logic;
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in std_logic_vector (47 downto 0);
our_ip_address : in std_logic_vector (31 downto 0);
control : in arp_control_type;
req_count : out std_logic_vector(7 downto 0) -- count of arp pkts received
);
end component;
component tx_arbitrator
port(
clk : in std_logic;
reset : in std_logic;
req_1 : in std_logic;
grant_1 : out std_logic;
data_1 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_1 : in std_logic; -- tdata is valid
first_1 : in std_logic; -- indicates first byte of frame
last_1 : in std_logic; -- indicates last byte of frame
req_2 : in std_logic;
grant_2 : out std_logic;
data_2 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_2 : in std_logic; -- tdata is valid
first_2 : in std_logic; -- indicates first byte of frame
last_2 : in std_logic; -- indicates last byte of frame
data : out std_logic_vector(7 downto 0); -- data byte to tx
valid : out std_logic; -- tdata is valid
first : out std_logic; -- indicates first byte of frame
last : out std_logic -- indicates last byte of frame
);
end component;
-------------------
-- Configuration
--
-- Enable one of the following to specify which
-- implementation of the ARP layer to use
-------------------
-- for arp_layer : arp use entity work.arp; -- single slot arbitrator
-- for arp_layer : arp use entity work.arpv2; -- multislot arbitrator
---------------------------
-- Signals
---------------------------
-- ARP REQUEST
signal arp_req_req_int : arp_req_req_type;
signal arp_req_rslt_int : arp_req_rslt_type;
-- MAC arbitration busses
signal ip_mac_req : std_logic;
signal ip_mac_grant : std_logic;
signal ip_mac_data_out : std_logic_vector (7 downto 0);
signal ip_mac_valid : std_logic;
signal ip_mac_first : std_logic;
signal ip_mac_last : std_logic;
signal arp_mac_req : std_logic;
signal arp_mac_grant : std_logic;
signal arp_mac_data_out : std_logic_vector (7 downto 0);
signal arp_mac_valid : std_logic;
signal arp_mac_first : std_logic;
signal arp_mac_last : std_logic;
-- MAC RX bus
signal mac_rx_tready_int : std_logic;
-- MAC TX bus
signal mac_tx_tdata_int : std_logic_vector (7 downto 0);
signal mac_tx_tvalid_int : std_logic;
signal mac_tx_tfirst_int : std_logic;
signal mac_tx_tlast_int : std_logic;
-- control signals
signal mac_tx_granted_int : std_logic;
begin
mac_rx_tready_int <= '1'; -- enable the mac receiver
-- set followers
mac_tx_tdata <= mac_tx_tdata_int;
mac_tx_tvalid <= mac_tx_tvalid_int;
mac_tx_tfirst <= mac_tx_tfirst_int;
mac_tx_tlast <= mac_tx_tlast_int;
mac_rx_tready <= mac_rx_tready_int;
------------------------------------------------------------------------------
-- Instantiate the IP layer
------------------------------------------------------------------------------
IP_layer : IPv4 port map
(
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
ip_tx_result => ip_tx_result,
ip_tx_data_out_ready => ip_tx_data_out_ready,
ip_rx_start => ip_rx_start,
ip_rx => ip_rx,
rx_clk => rx_clk,
tx_clk => tx_clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
rx_pkt_count => ip_pkt_count,
arp_req_req => arp_req_req_int,
arp_req_rslt => arp_req_rslt_int,
mac_tx_req => ip_mac_req,
mac_tx_granted => ip_mac_grant,
mac_data_out_ready => mac_tx_tready,
mac_data_out_valid => ip_mac_valid,
mac_data_out_first => ip_mac_first,
mac_data_out_last => ip_mac_last,
mac_data_out => ip_mac_data_out,
mac_data_in => mac_rx_tdata,
mac_data_in_valid => mac_rx_tvalid,
mac_data_in_first => mac_rx_tfirst,
mac_data_in_last => mac_rx_tlast
);
------------------------------------------------------------------------------
-- Instantiate the ARP layer
------------------------------------------------------------------------------
signle_entry_arp: if (not use_arpv2) generate
arp_layer : entity work.arp
generic map (
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO,
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
port map(
-- request signals
arp_req_req => arp_req_req_int,
arp_req_rslt => arp_req_rslt_int,
-- rx signals
data_in_clk => rx_clk,
reset => reset,
data_in => mac_rx_tdata,
data_in_valid => mac_rx_tvalid,
data_in_last => mac_rx_tlast,
-- tx signals
mac_tx_req => arp_mac_req,
mac_tx_granted => arp_mac_grant,
data_out_clk => tx_clk,
data_out_ready => mac_tx_tready,
data_out_valid => arp_mac_valid,
data_out_first => arp_mac_first,
data_out_last => arp_mac_last,
data_out => arp_mac_data_out,
-- system signals
our_mac_address => our_mac_address,
our_ip_address => our_ip_address,
control => control.arp_controls,
req_count => arp_pkt_count
);
end generate signle_entry_arp;
multi_entry_arp: if (use_arpv2) generate
arp_layer : entity work.arpv2
generic map (
no_default_gateway => no_default_gateway,
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO,
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
port map(
-- request signals
arp_req_req => arp_req_req_int,
arp_req_rslt => arp_req_rslt_int,
-- rx signals
data_in_clk => rx_clk,
reset => reset,
data_in => mac_rx_tdata,
data_in_valid => mac_rx_tvalid,
data_in_last => mac_rx_tlast,
-- tx signals
mac_tx_req => arp_mac_req,
mac_tx_granted => arp_mac_grant,
data_out_clk => tx_clk,
data_out_ready => mac_tx_tready,
data_out_valid => arp_mac_valid,
data_out_first => arp_mac_first,
data_out_last => arp_mac_last,
data_out => arp_mac_data_out,
-- system signals
our_mac_address => our_mac_address,
our_ip_address => our_ip_address,
nwk_gateway => x"AC1B0601",
nwk_mask => x"FFFF0000",
control => control.arp_controls,
req_count => arp_pkt_count
);
end generate multi_entry_arp;
------------------------------------------------------------------------------
-- Instantiate the TX Arbitrator
------------------------------------------------------------------------------
mac_tx_arb : tx_arbitrator
port map(
clk => tx_clk,
reset => reset,
req_1 => ip_mac_req,
grant_1 => ip_mac_grant,
data_1 => ip_mac_data_out,
valid_1 => ip_mac_valid,
first_1 => ip_mac_first,
last_1 => ip_mac_last,
req_2 => arp_mac_req,
grant_2 => arp_mac_grant,
data_2 => arp_mac_data_out,
valid_2 => arp_mac_valid,
first_2 => arp_mac_first,
last_2 => arp_mac_last,
data => mac_tx_tdata_int,
valid => mac_tx_tvalid_int,
first => mac_tx_tfirst_int,
last => mac_tx_tlast_int
);
end structural;
| gpl-3.0 | b4b94f308aa510a6ea1388b532dde576 | 0.531526 | 3.63712 | false | false | false | false |
DreamIP/GPStudio | support/io/usb_cypress_CY7C68014A/hdl/usb_cypress_CY7C68014A_slave.vhd | 1 | 3,197 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity usb_cypress_CY7C68014A_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_enable : out std_logic;
flow_in0_enable : out std_logic;
flow_in1_enable : out std_logic;
flow_in2_enable : out std_logic;
flow_in3_enable : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end usb_cypress_CY7C68014A_slave;
architecture rtl of usb_cypress_CY7C68014A_slave is
-- Registers address
constant STATUS_REG_ADDR : natural := 0;
constant FLOW_IN0_REG_ADDR : natural := 1;
constant FLOW_IN1_REG_ADDR : natural := 2;
constant FLOW_IN2_REG_ADDR : natural := 3;
constant FLOW_IN3_REG_ADDR : natural := 4;
-- Internal registers
signal status_enable_reg : std_logic;
signal flow_in0_enable_reg : std_logic;
signal flow_in1_enable_reg : std_logic;
signal flow_in2_enable_reg : std_logic;
signal flow_in3_enable_reg : std_logic;
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_enable_reg <= '0';
flow_in0_enable_reg <= '0';
flow_in1_enable_reg <= '0';
flow_in2_enable_reg <= '0';
flow_in3_enable_reg <= '0';
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case to_integer(unsigned(addr_rel_i)) is
when STATUS_REG_ADDR =>
status_enable_reg <= datawr_i(0);
when FLOW_IN0_REG_ADDR =>
flow_in0_enable_reg <= datawr_i(0);
when FLOW_IN1_REG_ADDR =>
flow_in1_enable_reg <= datawr_i(0);
when FLOW_IN2_REG_ADDR =>
flow_in2_enable_reg <= datawr_i(0);
when FLOW_IN3_REG_ADDR =>
flow_in3_enable_reg <= datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case to_integer(unsigned(addr_rel_i)) is
when STATUS_REG_ADDR =>
datard_o <= "0000000000000000000000000000000" & status_enable_reg;
when FLOW_IN0_REG_ADDR =>
datard_o <= "0000000000000000000000000000000" & flow_in0_enable_reg;
when FLOW_IN1_REG_ADDR =>
datard_o <= "0000000000000000000000000000000" & flow_in1_enable_reg;
when FLOW_IN2_REG_ADDR =>
datard_o <= "0000000000000000000000000000000" & flow_in2_enable_reg;
when FLOW_IN3_REG_ADDR =>
datard_o <= "0000000000000000000000000000000" & flow_in3_enable_reg;
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_enable <= status_enable_reg;
flow_in0_enable <= flow_in0_enable_reg;
flow_in1_enable <= flow_in1_enable_reg;
flow_in2_enable <= flow_in2_enable_reg;
flow_in3_enable <= flow_in3_enable_reg;
end rtl;
| gpl-3.0 | 875b454459ae643a39555438c7947cc6 | 0.615264 | 2.854464 | false | false | false | false |
hoglet67/ElectronFpga | AtomBusMon/src/T80/T80_MCode.vhd | 1 | 55,129 | --------------------------------------------------------------------------------
-- ****
-- T80(c) core. Attempt to finish all undocumented features and provide
-- accurate timings.
-- Version 350.
-- Copyright (c) 2018 Sorgelig
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
-- correct implementation is still unclear.
--
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
-- Z80 compatible microprocessor core
--
-- Version : 0242
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
-- 0211 : Fixed IM 1
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
-- 0235 : Added IM 2 fix by Mike Johnson
-- 0238 : Added NoRead signal
-- 0238b: Fixed instruction timing for POP and DJNZ
-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
-- 0242 : Fixed I/O instruction timing, cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_MCode is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetWZ : out std_logic_vector(1 downto 0);
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end T80_MCode;
architecture rtl of T80_MCode is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
function is_cc_true(
F : std_logic_vector(7 downto 0);
cc : bit_vector(2 downto 0)
) return boolean is
begin
if Mode = 3 then
case cc is
when "000" => return F(Flag_S) = '0'; -- NZ
when "001" => return F(Flag_S) = '1'; -- Z
when "010" => return F(Flag_H) = '0'; -- NC
when "011" => return F(Flag_H) = '1'; -- C
when "100" => return false;
when "101" => return false;
when "110" => return false;
when "111" => return false;
end case;
else
case cc is
when "000" => return F(Flag_Z) = '0'; -- NZ
when "001" => return F(Flag_Z) = '1'; -- Z
when "010" => return F(Flag_C) = '0'; -- NC
when "011" => return F(Flag_C) = '1'; -- C
when "100" => return F(Flag_P) = '0'; -- PO
when "101" => return F(Flag_P) = '1'; -- PE
when "110" => return F(Flag_S) = '0'; -- P
when "111" => return F(Flag_S) = '1'; -- M
end case;
end if;
end;
begin
process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
variable DDD : std_logic_vector(2 downto 0);
variable SSS : std_logic_vector(2 downto 0);
variable DPair : std_logic_vector(1 downto 0);
variable IRB : bit_vector(7 downto 0);
begin
DDD := IR(5 downto 3);
SSS := IR(2 downto 0);
DPair := IR(5 downto 4);
IRB := to_bitvector(IR);
MCycles <= "001";
if MCycle = "001" then
TStates <= "100";
else
TStates <= "011";
end if;
Prefix <= "00";
Inc_PC <= '0';
Inc_WZ <= '0';
IncDec_16 <= "0000";
Read_To_Acc <= '0';
Read_To_Reg <= '0';
Set_BusB_To <= "0000";
Set_BusA_To <= "0000";
ALU_Op <= "0" & IR(5 downto 3);
Save_ALU <= '0';
PreserveC <= '0';
Arith16 <= '0';
IORQ <= '0';
Set_Addr_To <= aNone;
Jump <= '0';
JumpE <= '0';
JumpXY <= '0';
Call <= '0';
RstP <= '0';
LDZ <= '0';
LDW <= '0';
LDSPHL <= '0';
Special_LD <= "000";
ExchangeDH <= '0';
ExchangeRp <= '0';
ExchangeAF <= '0';
ExchangeRS <= '0';
I_DJNZ <= '0';
I_CPL <= '0';
I_CCF <= '0';
I_SCF <= '0';
I_RETN <= '0';
I_BT <= '0';
I_BC <= '0';
I_BTR <= '0';
I_RLD <= '0';
I_RRD <= '0';
I_INRC <= '0';
SetDI <= '0';
SetEI <= '0';
IMode <= "11";
Halt <= '0';
NoRead <= '0';
Write <= '0';
XYbit_undoc <= '0';
SetWZ <= "00";
case ISet is
when "00" =>
------------------------------------------------------------------------------
--
-- Unprefixed instructions
--
------------------------------------------------------------------------------
case IRB is
-- 8 BIT LOAD GROUP
when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-- LD r,r'
Set_BusB_To(2 downto 0) <= SSS;
ExchangeRp <= '1';
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-- LD r,n
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when others => null;
end case;
when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-- LD r,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when others => null;
end case;
when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-- LD (HL),r
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
when 2 =>
Write <= '1';
when others => null;
end case;
when "00110110" =>
-- LD (HL),n
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aXY;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
when 3 =>
Write <= '1';
when others => null;
end case;
when "00001010" =>
-- LD A,(BC)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "00011010" =>
-- LD A,(DE)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aDE;
when 2 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "00111010" =>
if Mode = 3 then
-- LDD A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Acc <= '1';
IncDec_16 <= "1110";
when others => null;
end case;
else
-- LD A,(nn)
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
when 4 =>
Read_To_Acc <= '1';
when others => null;
end case;
end if;
when "00000010" =>
-- LD (BC),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "0111";
SetWZ <= "10";
when 2 =>
Write <= '1';
when others => null;
end case;
when "00010010" =>
-- LD (DE),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aDE;
Set_BusB_To <= "0111";
SetWZ <= "10";
when 2 =>
Write <= '1';
when others => null;
end case;
when "00110010" =>
if Mode = 3 then
-- LDD (HL),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IncDec_16 <= "1110";
when others => null;
end case;
else
-- LD (nn),A
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
SetWZ <= "10";
Inc_PC <= '1';
Set_BusB_To <= "0111";
when 4 =>
Write <= '1';
when others => null;
end case;
end if;
-- 16 BIT LOAD GROUP
when "00000001"|"00010001"|"00100001"|"00110001" =>
-- LD dd,nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1000";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '1';
end if;
when 3 =>
Inc_PC <= '1';
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1001";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
when "00101010" =>
if Mode = 3 then
-- LDI A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Acc <= '1';
IncDec_16 <= "0110";
when others => null;
end case;
else
-- LD HL,(nn)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Set_BusA_To(2 downto 0) <= "101"; -- L
Read_To_Reg <= '1';
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Set_BusA_To(2 downto 0) <= "100"; -- H
Read_To_Reg <= '1';
when others => null;
end case;
end if;
when "00100010" =>
if Mode = 3 then
-- LDI (HL),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IncDec_16 <= "0110";
when others => null;
end case;
else
-- LD (nn),HL
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
Set_BusB_To <= "0101"; -- L
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
Set_BusB_To <= "0100"; -- H
when 5 =>
Write <= '1';
when others => null;
end case;
end if;
when "11111001" =>
-- LD SP,HL
TStates <= "110";
LDSPHL <= '1';
when "11000101"|"11010101"|"11100101"|"11110101" =>
-- PUSH qq
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_TO <= aSP;
if DPAIR = "11" then
Set_BusB_To <= "0111";
else
Set_BusB_To(2 downto 1) <= DPAIR;
Set_BusB_To(0) <= '0';
Set_BusB_To(3) <= '0';
end if;
when 2 =>
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
if DPAIR = "11" then
Set_BusB_To <= "1011";
else
Set_BusB_To(2 downto 1) <= DPAIR;
Set_BusB_To(0) <= '1';
Set_BusB_To(3) <= '0';
end if;
Write <= '1';
when 3 =>
Write <= '1';
when others => null;
end case;
when "11000001"|"11010001"|"11100001"|"11110001" =>
-- POP qq
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1011";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '1';
end if;
when 3 =>
IncDec_16 <= "0111";
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "0111";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
when "11101011" =>
if Mode /= 3 then
-- EX DE,HL
ExchangeDH <= '1';
end if;
when "00001000" =>
if Mode = 3 then
-- LD (nn),SP
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
Set_BusB_To <= "1000";
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
Set_BusB_To <= "1001";
when 5 =>
Write <= '1';
when others => null;
end case;
elsif Mode < 2 then
-- EX AF,AF'
ExchangeAF <= '1';
end if;
when "11011001" =>
if Mode = 3 then
-- RETI
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
I_RETN <= '1';
SetEI <= '1';
when others => null;
end case;
elsif Mode < 2 then
-- EXX
ExchangeRS <= '1';
end if;
when "11100011" =>
if Mode /= 3 then
-- EX (SP),HL
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aSP;
when 2 =>
Read_To_Reg <= '1';
Set_BusA_To <= "0101"; -- L, target of Read_To_Reg
Set_BusB_To <= "0101"; -- L, input of ALU
Set_Addr_To <= aSP;
LDZ <= '1'; -- also load Z
when 3 =>
IncDec_16 <= "0111"; -- Increment SP
Set_Addr_To <= aSP;
TStates <= "100";
Write <= '1';
when 4 =>
Read_To_Reg <= '1';
Set_BusA_To <= "0100"; -- H, target of Read_To_Reg
Set_BusB_To <= "0100"; -- H, input of ALU
Set_Addr_To <= aSP;
LDW <= '1'; -- also load Z
when 5 =>
IncDec_16 <= "1111"; -- Decrement SP
TStates <= "101";
Write <= '1';
when others => null;
end case;
end if;
-- The T80 implementation does:
--
-- (4) M1 fetch
-- (3) M2 Read (SP) -> L, Z
-- L -> ALU
-- (4) M3 Write ALU result -> (SP)
-- SP++
-- (3) M4 Read (SP) -> H, W
-- H -> ALU
-- (5) M5 Write ALU result -> (SP)
-- SP--
--
-- The Z80 does
-- (4) M1 fetch
-- (3) M2 Read (SP) -> Z
-- SP++
-- (4) M3 Read (SP) -> W
-- (3) M4 Write H -> (SP)
-- SP--
-- (5) M5 Write L -> (SP)
--
-- and somehow WZ -> HL at the end!
--
-- Attempt at a new version.
--
-- case to_integer(unsigned(MCycle)) is
-- when 1 =>
-- Set_Addr_To <= aSP;
-- when 2 =>
-- IncDec_16 <= "0111";
-- Read_To_Reg <= '1';
-- Set_BusA_To <= "0101";
-- Set_BusB_To <= "0101";
-- Set_Addr_To <= aSP;
-- LDZ <= '1';
-- when 3 =>
-- Read_To_Reg <= '1';
-- Set_BusA_To <= "0100";
-- Set_BusB_To <= "0100";
-- Set_Addr_To <= aSP;
-- TStates <= "100";
-- LDW <= '1';
-- when 4 =>
-- IncDec_16 <= "1111";
-- Set_Addr_To <= aSP;
-- Write <= '1';
-- when 5 =>
-- TStates <= "101";
-- Write <= '1';
-- when others => null;
-- end case;
-- end if;
-- 8 BIT ARITHMETIC AND LOGICAL GROUP
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-- ADD A,r
-- ADC A,r
-- SUB A,r
-- SBC A,r
-- AND A,r
-- OR A,r
-- XOR A,r
-- CP A,r
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
Read_To_Reg <= '1';
Save_ALU <= '1';
when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-- ADD A,(HL)
-- ADC A,(HL)
-- SUB A,(HL)
-- SBC A,(HL)
-- AND A,(HL)
-- OR A,(HL)
-- XOR A,(HL)
-- CP A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
when others => null;
end case;
when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-- ADD A,n
-- ADC A,n
-- SUB A,n
-- SBC A,n
-- AND A,n
-- OR A,n
-- XOR A,n
-- CP A,n
MCycles <= "010";
if MCycle = "010" then
Inc_PC <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
end if;
when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-- INC r
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0000";
when "00110100" =>
-- INC (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
TStates <= "100";
Set_Addr_To <= aXY;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0000";
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
when 3 =>
Write <= '1';
when others => null;
end case;
when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-- DEC r
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0010";
when "00110101" =>
-- DEC (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
TStates <= "100";
Set_Addr_To <= aXY;
ALU_Op <= "0010";
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
when 3 =>
Write <= '1';
when others => null;
end case;
-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
when "00100111" =>
-- DAA
Set_BusA_To(2 downto 0) <= "111";
Read_To_Reg <= '1';
ALU_Op <= "1100";
Save_ALU <= '1';
when "00101111" =>
-- CPL
I_CPL <= '1';
when "00111111" =>
-- CCF
I_CCF <= '1';
when "00110111" =>
-- SCF
I_SCF <= '1';
when "00000000" =>
if NMICycle = '1' then
-- NMI
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
Write <= '1';
when others => null;
end case;
elsif IntCycle = '1' then
-- INT (IM 2)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
LDZ <= '1';
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
--TStates <= "100";
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
--TStates <= "100";
Write <= '1';
when 4 =>
Inc_PC <= '1';
LDZ <= '1';
when 5 =>
Jump <= '1';
when others => null;
end case;
else
-- NOP
end if;
when "01110110" =>
-- HALT
Halt <= '1';
when "11110011" =>
-- DI
SetDI <= '1';
when "11111011" =>
-- EI
SetEI <= '1';
-- 16 BIT ARITHMETIC GROUP
when "00001001"|"00011001"|"00101001"|"00111001" =>
-- ADD HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
Arith16 <= '1';
SetWZ <= "11";
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
when others =>
Set_BusB_To <= "1001";
end case;
Arith16 <= '1';
when others =>
end case;
when "00000011"|"00010011"|"00100011"|"00110011" =>
-- INC ss
TStates <= "110";
IncDec_16(3 downto 2) <= "01";
IncDec_16(1 downto 0) <= DPair;
when "00001011"|"00011011"|"00101011"|"00111011" =>
-- DEC ss
TStates <= "110";
IncDec_16(3 downto 2) <= "11";
IncDec_16(1 downto 0) <= DPair;
-- ROTATE AND SHIFT GROUP
when "00000111"
-- RLCA
|"00010111"
-- RLA
|"00001111"
-- RRCA
|"00011111" =>
-- RRA
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
-- JUMP GROUP
when "11000011" =>
-- JP nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
Jump <= '1';
LDW <= '1';
when others => null;
end case;
when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
if IR(5) = '1' and Mode = 3 then
case IRB(4 downto 3) is
when "00" =>
-- LD ($FF00+C),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IORQ <= '1';
when others =>
end case;
when "01" =>
-- LD (nn),A
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
Set_BusB_To <= "0111";
when 4 =>
Write <= '1';
when others => null;
end case;
when "10" =>
-- LD A,($FF00+C)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
Read_To_Acc <= '1';
IORQ <= '1';
when others =>
end case;
when "11" =>
-- LD A,(nn)
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
when 4 =>
Read_To_Acc <= '1';
when others => null;
end case;
end case;
else
-- JP cc,nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
LDW <= '1';
Inc_PC <= '1';
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
Jump <= '1';
end if;
when others => null;
end case;
end if;
when "00011000" =>
if Mode /= 2 then
-- JR e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00111000" =>
if Mode /= 2 then
-- JR C,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_C) = '0' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00110000" =>
if Mode /= 2 then
-- JR NC,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_C) = '1' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00101000" =>
if Mode /= 2 then
-- JR Z,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_Z) = '0' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00100000" =>
if Mode /= 2 then
-- JR NZ,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_Z) = '1' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "11101001" =>
-- JP (HL)
JumpXY <= '1';
when "00010000" =>
if Mode = 3 then
I_DJNZ <= '1';
elsif Mode < 2 then
-- DJNZ,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
I_DJNZ <= '1';
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= "000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
I_DJNZ <= '1';
Inc_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
-- CALL AND RETURN GROUP
when "11001101" =>
-- CALL nn
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
IncDec_16 <= "1111";
Inc_PC <= '1';
TStates <= "100";
Set_Addr_To <= aSP;
LDW <= '1';
Set_BusB_To <= "1101";
when 4 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 5 =>
Write <= '1';
Call <= '1';
when others => null;
end case;
when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
if IR(5) = '0' or Mode /= 3 then
-- CALL cc,nn
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
LDW <= '1';
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
IncDec_16 <= "1111";
Set_Addr_TO <= aSP;
TStates <= "100";
Set_BusB_To <= "1101";
else
MCycles <= "011";
end if;
when 4 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 5 =>
Write <= '1';
Call <= '1';
when others => null;
end case;
end if;
when "11001001" =>
-- RET
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
--TStates <= "101";
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
when others => null;
end case;
when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
if IR(5) = '1' and Mode = 3 then
case IRB(4 downto 3) is
when "00" =>
-- LD ($FF00+nn),A
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
Set_BusB_To <= "0111";
when 3 =>
Write <= '1';
when others => null;
end case;
when "01" =>
-- ADD SP,n
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
ALU_Op <= "0000";
Inc_PC <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To <= "1000";
Set_BusB_To <= "0110";
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To <= "1001";
Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
when others =>
end case;
when "10" =>
-- LD A,($FF00+nn)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
when 3 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "11" =>
-- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Set_BusA_To(2 downto 0) <= "101"; -- L
Read_To_Reg <= '1';
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Set_BusA_To(2 downto 0) <= "100"; -- H
Read_To_Reg <= '1';
when others => null;
end case;
end case;
else
-- RET cc
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
Set_Addr_TO <= aSP;
else
MCycles <= "001";
end if;
TStates <= "101";
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
when others => null;
end case;
end if;
when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-- RST p
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
Write <= '1';
RstP <= '1';
when others => null;
end case;
-- INPUT AND OUTPUT GROUP
when "11011011" =>
if Mode /= 3 then
-- IN A,(n)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
when 3 =>
Read_To_Acc <= '1';
IORQ <= '1';
when others => null;
end case;
end if;
when "11010011" =>
if Mode /= 3 then
-- OUT (n),A
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
Set_BusB_To <= "0111";
when 3 =>
Write <= '1';
IORQ <= '1';
when others => null;
end case;
end if;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- MULTIBYTE INSTRUCTIONS
------------------------------------------------------------------------------
------------------------------------------------------------------------------
when "11001011" =>
if Mode /= 2 then
Prefix <= "01";
end if;
when "11101101" =>
if Mode < 2 then
Prefix <= "10";
end if;
when "11011101"|"11111101" =>
if Mode < 2 then
Prefix <= "11";
end if;
end case;
when "01" =>
------------------------------------------------------------------------------
--
-- CB prefixed instructions
--
------------------------------------------------------------------------------
Set_BusA_To(2 downto 0) <= IR(2 downto 0);
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
case IRB is
when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-- RLC r
-- RL r
-- RRC r
-- RR r
-- SLA r
-- SRA r
-- SRL r
-- SLL r (Undocumented) / SWAP r
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- R/S (IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-- RLC (HL)
-- RL (HL)
-- RRC (HL)
-- RR (HL)
-- SRA (HL)
-- SRL (HL)
-- SLA (HL)
-- SLL (HL) (Undocumented) / SWAP (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others =>
end case;
when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-- BIT b,r
if XY_State="00" then
if MCycle = "001" then
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
ALU_Op <= "1001";
end if;
else
-- BIT b,(IX+d), undocumented
MCycles <= "010";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1001";
TStates <= "100";
when others => null;
end case;
end if;
when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-- BIT b,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1001";
TStates <= "100";
when others => null;
end case;
when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-- SET b,r
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- SET b,(IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-- SET b,(HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-- RES b,r
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- RES b,(IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-- RES b,(HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end case;
when others =>
------------------------------------------------------------------------------
--
-- ED prefixed instructions
--
------------------------------------------------------------------------------
case IRB is
when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
| "10100100"|"10100101"|"10100110"|"10100111"
| "10101100"|"10101101"|"10101110"|"10101111"
| "10110100"|"10110101"|"10110110"|"10110111"
| "10111100"|"10111101"|"10111110"|"10111111"
|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
null; -- NOP, undocumented
when "01111110"|"01111111" =>
-- NOP, undocumented
null;
-- 8 BIT LOAD GROUP
when "01010111" =>
-- LD A,I
Special_LD <= "100";
TStates <= "101";
when "01011111" =>
-- LD A,R
Special_LD <= "101";
TStates <= "101";
when "01000111" =>
-- LD I,A
Special_LD <= "110";
TStates <= "101";
when "01001111" =>
-- LD R,A
Special_LD <= "111";
TStates <= "101";
-- 16 BIT LOAD GROUP
when "01001011"|"01011011"|"01101011"|"01111011" =>
-- LD dd,(nn)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Read_To_Reg <= '1';
if IR(5 downto 4) = "11" then
Set_BusA_To <= "1000";
else
Set_BusA_To(2 downto 1) <= IR(5 downto 4);
Set_BusA_To(0) <= '1';
end if;
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Read_To_Reg <= '1';
if IR(5 downto 4) = "11" then
Set_BusA_To <= "1001";
else
Set_BusA_To(2 downto 1) <= IR(5 downto 4);
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
when "01000011"|"01010011"|"01100011"|"01110011" =>
-- LD (nn),dd
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
if IR(5 downto 4) = "11" then
Set_BusB_To <= "1000";
else
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
Set_BusB_To(3) <= '0';
end if;
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
if IR(5 downto 4) = "11" then
Set_BusB_To <= "1001";
else
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '0';
Set_BusB_To(3) <= '0';
end if;
when 5 =>
Write <= '1';
when others => null;
end case;
when "10100000" | "10101000" | "10110000" | "10111000" =>
-- LDI, LDD, LDIR, LDDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
IncDec_16 <= "1100"; -- BC
when 2 =>
Set_BusB_To <= "0110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "0000";
Set_Addr_To <= aDE;
if IR(3) = '0' then
IncDec_16 <= "0110"; -- IX
else
IncDec_16 <= "1110";
end if;
when 3 =>
I_BT <= '1';
TStates <= "101";
Write <= '1';
if IR(3) = '0' then
IncDec_16 <= "0101"; -- DE
else
IncDec_16 <= "1101";
end if;
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "10100001" | "10101001" | "10110001" | "10111001" =>
-- CPI, CPD, CPIR, CPDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
IncDec_16 <= "1100"; -- BC
when 2 =>
Set_BusB_To <= "0110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "0111";
Save_ALU <= '1';
PreserveC <= '1';
if IR(3) = '0' then
IncDec_16 <= "0110";
else
IncDec_16 <= "1110";
end if;
when 3 =>
NoRead <= '1';
I_BC <= '1';
TStates <= "101";
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-- NEG
Alu_OP <= "0010";
Set_BusB_To <= "0111";
Set_BusA_To <= "1010";
Read_To_Acc <= '1';
Save_ALU <= '1';
when "01000110"|"01001110"|"01100110"|"01101110" =>
-- IM 0
IMode <= "00";
when "01010110"|"01110110" =>
-- IM 1
IMode <= "01";
when "01011110"|"01110111" =>
-- IM 2
IMode <= "10";
-- 16 bit arithmetic
when "01001010"|"01011010"|"01101010"|"01111010" =>
-- ADC HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "0001";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
SetWZ <= "11";
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '0';
when others =>
Set_BusB_To <= "1001";
end case;
when others =>
end case;
when "01000010"|"01010010"|"01100010"|"01110010" =>
-- SBC HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "0011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
SetWZ <= "11";
when 3 =>
NoRead <= '1';
ALU_Op <= "0011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
when others =>
Set_BusB_To <= "1001";
end case;
when others =>
end case;
when "01101111" =>
-- RLD -- Read in M2, not M3! fixed by Sorgelig
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Reg <= '1';
Set_BusB_To(2 downto 0) <= "110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1101";
Save_ALU <= '1';
when 3 =>
TStates <= "100";
I_RLD <= '1';
NoRead <= '1';
Set_Addr_To <= aXY;
when 4 =>
Write <= '1';
when others =>
end case;
when "01100111" =>
-- RRD -- Read in M2, not M3! fixed by Sorgelig
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Reg <= '1';
Set_BusB_To(2 downto 0) <= "110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1110";
Save_ALU <= '1';
when 3 =>
TStates <= "100";
I_RRD <= '1';
NoRead <= '1';
Set_Addr_To <= aXY;
when 4 =>
Write <= '1';
when others =>
end case;
when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-- RETI/RETN
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
LDW <= '1';
I_RETN <= '1';
when others => null;
end case;
when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-- IN r,(C)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
SetWZ <= "01";
when 2 =>
IORQ <= '1';
if IR(5 downto 3) /= "110" then
Read_To_Reg <= '1';
Set_BusA_To(2 downto 0) <= IR(5 downto 3);
end if;
I_INRC <= '1';
when others =>
end case;
when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-- OUT (C),r
-- OUT (C),0
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
SetWZ <= "01";
Set_BusB_To(2 downto 0) <= IR(5 downto 3);
if IR(5 downto 3) = "110" then
Set_BusB_To(3) <= '1';
end if;
when 2 =>
Write <= '1';
IORQ <= '1';
when others =>
end case;
when "10100010" | "10101010" | "10110010" | "10111010" =>
-- INI, IND, INIR, INDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
Set_Addr_To <= aBC;
Set_BusB_To <= "1010";
Set_BusA_To <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
SetWZ <= "11";
IncDec_16(3) <= IR(3);
when 2 =>
IORQ <= '1';
Set_BusB_To <= "0110";
Set_Addr_To <= aXY;
when 3 =>
if IR(3) = '0' then
IncDec_16 <= "0110";
else
IncDec_16 <= "1110";
end if;
Write <= '1';
I_BTR <= '1';
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "10100011" | "10101011" | "10110011" | "10111011" =>
-- OUTI, OUTD, OTIR, OTDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
Set_Addr_To <= aXY;
Set_BusB_To <= "1010";
Set_BusA_To <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
Set_BusB_To <= "0110";
Set_Addr_To <= aBC;
SetWZ <= "11";
IncDec_16(3) <= IR(3);
when 3 =>
if IR(3) = '0' then
IncDec_16 <= "0110";
else
IncDec_16 <= "1110";
end if;
IORQ <= '1';
Write <= '1';
I_BTR <= '1';
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
end case;
end case;
if Mode = 1 then
if MCycle = "001" then
-- TStates <= "100";
else
TStates <= "011";
end if;
end if;
if Mode = 3 then
if MCycle = "001" then
-- TStates <= "100";
else
TStates <= "100";
end if;
end if;
if Mode < 2 then
if MCycle = "110" then
Inc_PC <= '1';
if Mode = 1 then
Set_Addr_To <= aXY;
TStates <= "100";
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
end if;
if IRB = "00110110" or IRB = "11001011" then
Set_Addr_To <= aNone;
end if;
end if;
if MCycle = "111" then
if Mode = 0 then
TStates <= "101";
end if;
if ISet /= "01" then
Set_Addr_To <= aXY;
end if;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
if IRB = "00110110" or ISet = "01" then
-- LD (HL),n
Inc_PC <= '1';
else
NoRead <= '1';
end if;
end if;
end if;
end process;
end;
| gpl-3.0 | 15952a29ec5db071f95dcd9ad70b8a5e | 0.51082 | 3.012843 | false | false | false | false |
bpervan/simple-soc | pcores/led_axi_ip_v1_00_a/hdl/vhdl/user_logic.vhd | 1 | 9,394 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Tue Mar 25 15:35:46 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 1;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
LED : out std_logic_vector(7 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal led_i : std_logic_vector (7 downto 0);
--signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(0 to 0);
--signal slv_reg_read_sel : std_logic_vector(0 to 0);
--signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
--signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 downto 0);
--slv_reg_read_sel <= Bus2IP_RdCE(0 downto 0);
slv_write_ack <= Bus2IP_WrCE(0);
--slv_read_ack <= Bus2IP_RdCE(0);
-- implement slave model software accessible register(s)
LED_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
led_i <= (others => '0');
else
case slv_reg_write_sel is
when "1" =>
led_i <= Bus2IP_Data (7 downto 0);
when others => null;
end case;
end if;
end if;
end process LED_WRITE_PROC;
LED <= led_i;
-- implement slave model software accessible register(s) read mux
--SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is
--begin
--
-- case slv_reg_read_sel is
-- when "1" => slv_ip2bus_data <= slv_reg0;
--when others => slv_ip2bus_data <= (others => '0');
--end case;
--end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
--IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
-- (others => '0');
--IP2Bus_WrAck <= slv_write_ack;
--IP2Bus_RdAck <= slv_read_ack;
--IP2Bus_Error <= '0';
end IMP;
| mit | 47fa349c981ea296cda0924837642d7c | 0.466574 | 4.551357 | false | false | false | false |
DreamIP/GPStudio | support/component/gp_com/flow_to_com/flow_to_com.vhd | 1 | 7,785 | -- **************************************************************************
-- FLOW IN
-- **************************************************************************
-- This component is connected to USB Driver and generate FV/DV/data as outputs
-- 26/11/2014 - creation - C.Bourrasset
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ComFlow_pkg.all;
entity flow_to_com is
generic (
FLOW_SIZE : POSITIVE := 8;
DATA_HAL_SIZE : POSITIVE := 16;
FIFO_DEPTH : INTEGER := 1024;
FLOW_ID : INTEGER := 1;
PACKET_SIZE : INTEGER := 256;
FLAGS_CODES : my_array_t := InitFlagCodes
);
port (
clk_proc : in std_logic;
clk_hal : in std_logic;
rst_n : in std_logic;
in_data : in std_logic_vector(FLOW_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
enable_flow_i : in std_logic;
enable_global_i : in std_logic;
-- to arbitrer
rdreq_i : in std_logic;
data_o : out std_logic_vector(DATA_HAL_SIZE-1 downto 0);
flow_rdy_o : out std_logic;
f_empty_o : out std_logic;
size_packet_o : out std_logic_vector(15 downto 0)
);
end flow_to_com;
architecture rtl of flow_to_com is
---------------------------------------------------------
-- COMPONENT DECLARATION
---------------------------------------------------------
component fv_signal_synchroniser
port (
clk : in std_logic;
rst_n : in std_logic;
fv_i : in std_logic;
signal_i : in std_logic;
signal_o : out std_logic
);
end component;
component flowto16
generic (
INPUT_SIZE : INTEGER;
FIFO_DEPTH : INTEGER := 32
);
port (
rst_n : in std_logic;
clk : in std_logic;
in_data : in std_logic_vector(FLOW_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_data : out std_logic_vector(15 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component com_flow_fifo_tx
generic (
FIFO_DEPTH : INTEGER := 1024;
FLOW_ID : INTEGER := 1;
PACKET_SIZE : INTEGER := 256;
HAL_WIDTH : INTEGER := 16;
FLAGS_CODES : my_array_t := InitFlagCodes
);
port (
clk_proc : in std_logic;
clk_hal : in std_logic;
rst_n : in std_logic;
data_wr_i : in std_logic;
data_i : in std_logic_vector(15 downto 0);
rdreq_i : in std_logic;
flag_wr_i : in std_logic;
flag_i : in std_logic_vector(7 downto 0);
-- fifo pkt inputs
fifo_pkt_wr_i : in std_logic;
fifo_pkt_data_i : in std_logic_vector(15 downto 0);
-- to arbitrer
data_o : out std_logic_vector(HAL_WIDTH-1 downto 0);
flow_rdy_o : out std_logic;
f_empty_o : out std_logic;
fifos_f_o : out std_logic;
size_packet_o : out std_logic_vector(15 downto 0)
);
end component;
component write_flow is
generic (
PACKET_SIZE : INTEGER := 256;
FLAGS_CODES : my_array_t := InitFlagCodes
);
port (
clk : in std_logic;
rst_n : in std_logic;
in_data : in std_logic_vector(15 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
enable_i : in std_logic;
fifo_f_i : in std_logic;
data_wr_o : out std_logic;
data_o : out std_logic_vector(15 downto 0);
flag_wr_o : out std_logic;
flag_o : out std_logic_vector(7 downto 0);
fifo_pkt_wr_o : out std_logic;
fifo_pkt_data_o : out std_logic_vector(15 downto 0)
);
end component;
---------------------------------------------------------
-- SIGNALS FOR INTERCONNECT
---------------------------------------------------------
signal fifo_f_s : std_logic := '0';
signal data_wr_s : std_logic := '0';
signal data_s : std_logic_vector(15 downto 0) := (others=>'0');
signal in_data_s : std_logic_vector(15 downto 0);
signal in_fv_s : std_logic;
signal in_dv_s : std_logic;
signal enable_flow_sync : std_logic;
signal enable_global_sync : std_logic;
signal enable_s : std_logic;
signal fifo_pkt_wr_s : std_logic;
signal fifo_pkt_data_s : std_logic_vector(15 downto 0);
-- may add CDC component for flag
signal flag_s : std_logic_vector(7 downto 0) := (others=>'0');
signal flag_wr_s : std_logic := '0';
begin
-- Adapt input flow size to 16 bits
flowto16_inst : component flowto16
generic map (
INPUT_SIZE => FLOW_SIZE,
FIFO_DEPTH => 128
)
port map (
clk => clk_proc,
rst_n => rst_n,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => in_data_s,
out_fv => in_fv_s,
out_dv => in_dv_s
);
ENABLE_FLOW_INST : component fv_signal_synchroniser
port map (
clk => clk_proc,
rst_n => rst_n,
fv_i => in_fv_s,
signal_i => enable_flow_i,
signal_o => enable_flow_sync
);
ENABLE_GLOBAL_INST : component fv_signal_synchroniser
port map (
clk => clk_proc,
rst_n => rst_n,
fv_i => in_fv_s,
signal_i => enable_global_i,
signal_o => enable_global_sync
);
-- port map
WRFLOW_process : component write_flow
generic map (
PACKET_SIZE => PACKET_SIZE,
FLAGS_CODES => FLAGS_CODES
)
port map (
clk => clk_proc,
rst_n => rst_n,
in_data => in_data_s,
in_fv => in_fv_s,
in_dv => in_dv_s,
enable_i => enable_s,
fifo_f_i => fifo_f_s,
data_wr_o => data_wr_s,
data_o => data_s,
flag_wr_o => flag_wr_s ,
flag_o => flag_s,
fifo_pkt_wr_o => fifo_pkt_wr_s,
fifo_pkt_data_o => fifo_pkt_data_s
);
ComFlowFifoTX_inst : component com_flow_fifo_tx
generic map (
FIFO_DEPTH => FIFO_DEPTH,
FLOW_ID => FLOW_ID,
PACKET_SIZE => PACKET_SIZE,
FLAGS_CODES => FLAGS_CODES,
HAL_WIDTH => DATA_HAL_SIZE
)
port map (
clk_proc => clk_proc,
clk_hal => clk_hal,
rst_n => rst_n and enable_s,
data_wr_i => data_wr_s,
data_i => data_s,
rdreq_i => rdreq_i,
flag_wr_i => flag_wr_s,
flag_i => flag_s,
fifo_pkt_wr_i => fifo_pkt_wr_s,
fifo_pkt_data_i => fifo_pkt_data_s,
data_o => data_o,
flow_rdy_o => flow_rdy_o,
f_empty_o => f_empty_o,
fifos_f_o => fifo_f_s,
size_packet_o => size_packet_o
);
enable_s <= enable_flow_sync and enable_global_sync;
end rtl;
| gpl-3.0 | 9b797297e29ee4fd32f27694654a342f | 0.439435 | 3.537029 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/RGMII_MAC/gbe_mac.vhd | 1 | 5,483 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gbe_mac is
port(
iRst_n : IN STD_LOGIC;
---------------------------------------------------------------------------
-- RGMII Interface
---------------------------------------------------------------------------
ENET1_GTX_CLK : OUT STD_LOGIC;
ENET1_TX_EN : OUT STD_LOGIC;
ENET1_TX_DATA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ENET1_RX_CLK : IN STD_LOGIC;
ENET1_RX_DV : IN STD_LOGIC;
ENET1_RX_DATA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
--PHY
ENET1_PHY_RESET_L : out std_logic;
ENET1_PHY_MDC : out std_logic;
ENET1_PHY_MDIO : inout std_logic;
--TO UDP
iMAC_HAL : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
--RX
iUDP_rx_rdy : IN STD_LOGIC;
DATA_VALID_RX_OUT : OUT STD_LOGIC;
DATA_RX_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
SOF_RX_OUT : OUT STD_LOGIC;
EOF_RX_OUT : OUT STD_LOGIC;
--TX
DATA_VALID_TX_IN : IN STD_LOGIC;
DATA_TX_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SOF_TX_IN : IN STD_LOGIC;
EOF_TX_IN : IN STD_LOGIC;
MAC_RDY_IN : OUT STD_LOGIC;
CLK_OUT : OUT STD_LOGIC
);
end entity;
architecture rtl of gbe_mac is
component rgmii1000_io is
PORT (
iRst_n : IN STD_LOGIC;
---------------------------------------------------------------------------
-- RGMII Interface
---------------------------------------------------------------------------
TXC : OUT STD_LOGIC;
TX_CTL : OUT STD_LOGIC;
TD : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
RXC : IN STD_LOGIC;
RX_CTL : IN STD_LOGIC;
RD : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
---------------------------------------------------------------------------
-- data to PHY
---------------------------------------------------------------------------
iTxData : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
iTxEn : IN STD_LOGIC;
iTxErr : IN STD_LOGIC;
---------------------------------------------------------------------------
-- data from PHY
---------------------------------------------------------------------------
oRxData : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
oRxDV : OUT STD_LOGIC;
oRxErr : OUT STD_LOGIC;
---------------------------------------------------------------------------
-- clock for MAC controller
---------------------------------------------------------------------------
oEthClk : OUT STD_LOGIC
);
end component;
component rgmii_rx_top_2 is
port(
iEthClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
iMAC_HAL : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
iEnetRxData : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
iEnetRxDv : IN STD_LOGIC;
iEnetRxErr : IN STD_LOGIC;
iCheckSumIPCheck : IN STD_LOGIC;
iCheckSumTCPCheck : IN STD_LOGIC;
iCheckSumUDPCheck : IN STD_LOGIC;
iCheckSumICMPCheck : IN STD_LOGIC;
--USR IF
iUDP_rx_rdy : IN STD_lOGIC;
oData_rx : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
oData_valid : OUT STD_LOGIC;
oSOF : OUT STD_LOGIC;
oEOF : OUT STD_LOGIC
);
end component;
component rgmii_tx_top_2 IS
PORT (
iEthClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
oEnetTxData : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
oEnetTxEn : OUT STD_LOGIC;
oEnetTxErr : OUT STD_LOGIC;
--USR IF FROM "UDP COMPLETE"
iData_tx : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
iTxDataValid : IN STD_LOGIC;
iSOF : IN STD_LOGIC;
iEOF : IN STD_LOGIC;
oMACTxRdy : OUT STD_LOGIC
);
end component;
component eth_mdio is
Port(
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
E_RST_L : out STD_LOGIC;
E_MDC : out STD_LOGIC;
E_MDIO : inout STD_LOGIC);
end component;
signal cEthClk : std_logic;
signal cEnetRxDV, cEnetRxErr : std_logic;
signal cEnetTxEn, cEnetTxErr : std_logic;
signal cEnetRxData, cEnetTxData : std_logic_vector(7 downto 0);
begin
rgmii_rx_top_2_inst : rgmii_rx_top_2
PORT MAP(
iEthClk => cEthClk,
iRst_n => iRst_n,
iMAC_HAL => iMAC_HAL,
iEnetRxData => cEnetRxData,
iEnetRxDv => cEnetRxDV,
iEnetRxErr => cEnetRxErr,
iCheckSumIPCheck => '0',
iCheckSumTCPCheck => '0',
iCheckSumUDPCheck => '0',
iCheckSumICMPCheck => '0',
--USR IF
iUDP_rx_rdy => iUDP_rx_rdy,
oData_rx => DATA_RX_OUT,
oData_valid => DATA_VALID_RX_OUT,
oSOF => SOF_RX_OUT,
oEOF => EOF_RX_OUT
);
rgmii_tx_top_2_inst : rgmii_tx_top_2
PORT MAP(
iEthClk => cEthClk,
iRst_n => iRst_n,
oEnetTxData => cEnetTxData,
oEnetTxEn => cEnetTxEn,
oEnetTxErr => cEnetTxErr,
--USR IF FROM "UDP COMPLETE"
iData_tx => DATA_TX_IN,
iTxDataValid => DATA_VALID_TX_IN,
iSOF => SOF_TX_IN,
iEOF => EOF_TX_IN,
oMACTxRdy => MAC_RDY_IN
);
rgmii_io_1 : rgmii1000_io
PORT MAP (
iRst_n => iRst_n,
TXC => ENET1_GTX_CLK,
TX_CTL => ENET1_TX_EN,
TD => ENET1_TX_DATA,
RXC => ENET1_RX_CLK,
RX_CTL => ENET1_RX_DV,
RD => ENET1_RX_DATA,
iTxData => cEnetTxData,
iTxEn => cEnetTxEn,
iTxErr => cEnetTxErr,
oRxData => cEnetRxData,
oRxDV => cEnetRxDV,
oRxErr => cEnetRxErr,
oEthClk => cEthClk
);
CLK_OUT <= cEthClk;
eth_mdio_inst : eth_mdio
PORT MAP(
CLK => cEthClk,
RESET => iRst_n,
E_RST_L => ENET1_PHY_RESET_L,
E_MDC => ENET1_PHY_MDC,
E_MDIO => ENET1_PHY_MDIO
);
end architecture;
| gpl-3.0 | 080c9f236c471c2a6d864b738d679594 | 0.506292 | 2.890353 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/altera/hostinterface/src/alteraHostInterfaceRtl.vhd | 3 | 9,649 | -------------------------------------------------------------------------------
--! @file alteraHostInterface.vhd
--
--! @brief toplevel of host interface for Altera FPGA
--
--! @details This toplevel interfaces to Altera specific implementation.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity alteraHostInterface is
generic (
--! Version major
gVersionMajor : natural := 16#FF#;
--! Version minor
gVersionMinor : natural := 16#FF#;
--! Version revision
gVersionRevision : natural := 16#FF#;
--! Version count
gVersionCount : natural := 0;
-- Base address mapping
--! Base address Dynamic Buffer 0
gBaseDynBuf0 : natural := 16#00800#;
--! Base address Dynamic Buffer 1
gBaseDynBuf1 : natural := 16#01000#;
--! Base address Error Counter
gBaseErrCntr : natural := 16#01800#;
--! Base address TX NMT Queue
gBaseTxNmtQ : natural := 16#02800#;
--! Base address TX Generic Queue
gBaseTxGenQ : natural := 16#03800#;
--! Base address TX SyncRequest Queue
gBaseTxSynQ : natural := 16#04800#;
--! Base address TX Virtual Ethernet Queue
gBaseTxVetQ : natural := 16#05800#;
--! Base address RX Virtual Ethernet Queue
gBaseRxVetQ : natural := 16#06800#;
--! Base address Kernel-to-User Queue
gBaseK2UQ : natural := 16#07000#;
--! Base address User-to-Kernel Queue
gBaseU2KQ : natural := 16#09000#;
--! Base address Tpdo
gBasePdo : natural := 16#0B000#;
--! Base address Timesync
gBaseTimeSync : natural := 16#0E000#;
--! Base address Reserved (-1 = high address of Timesync)
gBaseRes : natural := 16#0E400#;
--! Host address width
gHostAddrWidth : natural := 16
);
port (
--! Clock Source input
csi_c0_clock : in std_logic;
--! Reset Source input
rsi_r0_reset : in std_logic;
-- Avalon Memory Mapped Slave for Host
--! Avalon-MM slave host address
avs_host_address : in std_logic_vector(gHostAddrWidth-1 downto 2);
--! Avalon-MM slave host byteenable
avs_host_byteenable : in std_logic_vector(3 downto 0);
--! Avalon-MM slave host read
avs_host_read : in std_logic;
--! Avalon-MM slave host readdata
avs_host_readdata : out std_logic_vector(31 downto 0);
--! Avalon-MM slave host write
avs_host_write : in std_logic;
--! Avalon-MM slave host writedata
avs_host_writedata : in std_logic_vector(31 downto 0);
--! Avalon-MM slave host waitrequest
avs_host_waitrequest : out std_logic;
-- Avalon Memory Mapped Slave for PCP
--! Avalon-MM slave pcp address
avs_pcp_address : in std_logic_vector(10 downto 2);
--! Avalon-MM slave pcp byteenable
avs_pcp_byteenable : in std_logic_vector(3 downto 0);
--! Avalon-MM slave pcp read
avs_pcp_read : in std_logic;
--! Avalon-MM slave pcp readdata
avs_pcp_readdata : out std_logic_vector(31 downto 0);
--! Avalon-MM slave pcp write
avs_pcp_write : in std_logic;
--! Avalon-MM slave pcp writedata
avs_pcp_writedata : in std_logic_vector(31 downto 0);
--! Avalon-MM slave pcp waitrequest
avs_pcp_waitrequest : out std_logic;
-- Avalon Memory Mapped Master for Host via Magic Bridge
--! Avalon-MM master hostBridge address
avm_hostBridge_address : out std_logic_vector(29 downto 0);
--! Avalon-MM master hostBridge byteenable
avm_hostBridge_byteenable : out std_logic_vector(3 downto 0);
--! Avalon-MM master hostBridge read
avm_hostBridge_read : out std_logic;
--! Avalon-MM master hostBridge readdata
avm_hostBridge_readdata : in std_logic_vector(31 downto 0);
--! Avalon-MM master hostBridge write
avm_hostBridge_write : out std_logic;
--! Avalon-MM master hostBridge writedata
avm_hostBridge_writedata : out std_logic_vector(31 downto 0);
--! Avalon-MM master hostBridge waitrequest
avm_hostBridge_waitrequest : in std_logic;
--! Interrupt receiver
inr_irqSync_irq : in std_logic;
--! Interrupt sender
ins_irqOut_irq : out std_logic;
--! External Sync Source
coe_ExtSync_exsync : in std_logic
);
end alteraHostInterface;
architecture rtl of alteraHostInterface is
--! The bridge translation lut is implemented in memory blocks to save logic resources.
--! If no M9K shall be used, set this constant to 0.
constant cBridgeUseMemBlock : natural := 1;
begin
--! The host interface
theHostInterface: entity work.hostInterface
generic map (
gVersionMajor => gVersionMajor,
gVersionMinor => gVersionMinor,
gVersionRevision => gVersionRevision,
gVersionCount => gVersionCount,
gBridgeUseMemBlock => cBridgeUseMemBlock,
gBaseDynBuf0 => gBaseDynBuf0,
gBaseDynBuf1 => gBaseDynBuf1,
gBaseErrCntr => gBaseErrCntr,
gBaseTxNmtQ => gBaseTxNmtQ,
gBaseTxGenQ => gBaseTxGenQ,
gBaseTxSynQ => gBaseTxSynQ,
gBaseTxVetQ => gBaseTxVetQ,
gBaseRxVetQ => gBaseRxVetQ,
gBaseK2UQ => gBaseK2UQ,
gBaseU2KQ => gBaseU2KQ,
gBasePdo => gBasePdo,
gBaseTimeSync => gBaseTimeSync,
gBaseRes => gBaseRes,
gHostAddrWidth => gHostAddrWidth
)
port map (
iClk => csi_c0_clock,
iRst => rsi_r0_reset,
iHostAddress => avs_host_address,
iHostByteenable => avs_host_byteenable,
iHostRead => avs_host_read,
oHostReaddata => avs_host_readdata,
iHostWrite => avs_host_write,
iHostWritedata => avs_host_writedata,
oHostWaitrequest => avs_host_waitrequest,
iPcpAddress => avs_pcp_address,
iPcpByteenable => avs_pcp_byteenable,
iPcpRead => avs_pcp_read,
oPcpReaddata => avs_pcp_readdata,
iPcpWrite => avs_pcp_write,
iPcpWritedata => avs_pcp_writedata,
oPcpWaitrequest => avs_pcp_waitrequest,
oHostBridgeAddress => avm_hostBridge_address,
oHostBridgeByteenable => avm_hostBridge_byteenable,
oHostBridgeRead => avm_hostBridge_read,
iHostBridgeReaddata => avm_hostBridge_readdata,
oHostBridgeWrite => avm_hostBridge_write,
oHostBridgeWritedata => avm_hostBridge_writedata,
iHostBridgeWaitrequest => avm_hostBridge_waitrequest,
iIrqIntSync => inr_irqSync_irq,
iIrqExtSync => coe_ExtSync_exsync,
oIrq => ins_irqOut_irq
);
end rtl;
| gpl-2.0 | 430dc2df9d240febedc8ac2a8a1f0a5b | 0.568245 | 4.883097 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/xilinx/memory/src/dpRamSplxNbe-rtl-a.vhd | 3 | 4,018 | -------------------------------------------------------------------------------
--! @file dpRamSplxNbe-a.vhd
--
--! @brief Simplex Dual Port Ram without byteenables
--
--! @details This is the Simplex DPRAM without byteenables for Xilinx platforms.
--! The DPRAM has one write and one read port only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
architecture rtl of dpRamSplxNbe is
--! Address width (used to generate size depending on address width)
constant cAddrWidth : natural := iAddress_A'length;
--! RAM size
constant cRamSize : natural := 2**cAddrWidth;
--! Type for data port
subtype tDataPort is std_logic_vector(gWordWidth-1 downto 0);
--! RAM type with given size
type tRam is array (cRamSize-1 downto 0) of tDataPort;
--! Shared variable to model and synthesize a DPR
shared variable vDpram : tRam := (others => (others => cInactivated));
--! Port B readport
signal readdataB : tDataPort;
begin
-- assign readdata to ports
oReaddata_B <= readdataB;
--! This process describes port A of the DPRAM. The write process considers
--! iWriteEnable_A.
PORTA : process(iClk_A)
begin
if rising_edge(iClk_A) then
if iEnable_A = cActivated then
if iWriteEnable_A = cActivated then
-- write byte to DPRAM
vDpram(to_integer(unsigned(iAddress_A))) := iWritedata_A;
end if; --writeenable
end if; --enable
end if;
end process PORTA;
--! This process describes port B of the DPRAM. The read process is done
--! with every rising iClk_B edge.
PORTB : process(iClk_B)
begin
if rising_edge(iClk_B) then
if iEnable_B = cActivated then
-- read word from DPRAM
readdataB <= vDpram(to_integer(unsigned(iAddress_B)));
end if; --enable
end if;
end process PORTB;
end architecture rtl;
| gpl-2.0 | 301fb77211ceba74dc047599055606ab | 0.634146 | 4.693925 | false | false | false | false |
DreamIP/GPStudio | support/component/gp_com/com_to_master_pi/com_to_master_pi.vhd | 1 | 5,829 | -- **************************************************************************
-- READ FLOW to params
-- *************************************************************************
-- Ce composant est connecte a un com_flow_fifo_rx en entree et gere une zone de params
-- 25/11/2014 - creation
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ComFlow_pkg.all;
use ieee.math_real.all;
entity com_to_master_pi is
generic (
FIFO_DEPTH : POSITIVE := 64;
FLOW_ID_SET : INTEGER := 12;
--FLOW_ID_GET : integer := 13
MASTER_ADDR_WIDTH : POSITIVE := 4;
DATA_HAL_SIZE : POSITIVE := 16
);
port (
clk_hal : in std_logic; -- clk_usb
clk_proc : in std_logic; -- clk_design
rst_n : in std_logic;
-- USB driver connexion
data_wr_i : in std_logic;
data_i : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
-- rdreq_i : in std_logic;
pktend_i : in std_logic;
fifo_full_o : out std_logic;
-- signaux pour wishbone
param_addr_o : out std_logic_vector(MASTER_ADDR_WIDTH-1 DOWNTO 0);
param_data_o : out std_logic_vector(31 downto 0);
param_wr_o : out std_logic;
-- may add RAM arbiter connexion
-- tmp signal to trigger caph update reg
tmp_update_port_o : out std_logic
);
end com_to_master_pi;
architecture rtl of com_to_master_pi is
component com_flow_fifo_rx
generic (
FIFO_DEPTH : POSITIVE := 64;
FLOW_ID : INTEGER := 12;
IN_SIZE : POSITIVE := 16;
OUT_SIZE : POSITIVE := 16
);
port (
clk_hal : in std_logic;
clk_proc : in std_logic;
rst_n : in std_logic;
data_wr_i : in std_logic;
data_i : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
rdreq_i : in std_logic;
pktend_i : in std_logic;
enable_i : in std_logic;
data_o : out std_logic_vector(15 downto 0);
flow_rdy_o : out std_logic;
f_empty_o : out std_logic;
fifos_f_o : out std_logic;
flag_o : out std_logic_vector(7 downto 0)
);
end component;
-- GET PARAMS :: TODO
------------------------------------------
-- On peut aussi faire sans ce composant: handshake manuel avec le driver USB + prise de bus memoire + depilage manuel
-- component com_flow_fifo_tx
-- generic (
-- FIFO_DEPTH : POSITIVE := 1024;
-- FLOW_ID : integer := 1;
-- PACKET_SIZE : integer := 512;
-- FLAGS_CODES : my_array_t := InitFlagCodes
-- );
-- port(
-- data_wr_i : in std_logic;
-- data_i : in std_logic_vector(15 downto 0);
-- rdreq_i : in std_logic;
-- pktend_i : in std_logic;
-- flag_i : in std_logic_vector(7 downto 0);
-- data_o : out std_logic_vector(15 downto 0);
-- flow_rdy_o: out std_logic;
-- f_empty_o : out std_logic;
-- fifos_f_o : out std_logic;
-- clk_hal : in std_logic;
-- clk_proc :in std_logic;
-- rst_n :in std_logic
-- );
-- end component;
component params_flow_decoder
generic (
MASTER_ADDR_WIDTH : POSITIVE := 10
);
port (
clk : in std_logic;
rst_n : in std_logic;
data_i : in std_logic_vector(15 downto 0);
flow_rdy_i : in std_logic;
f_empty_i : in std_logic;
flag_i : in std_logic_vector(7 downto 0);
read_data_o : out std_logic;
-- signaux pour wishbone
param_addr_o : out std_logic_vector(MASTER_ADDR_WIDTH-1 DOWNTO 0);
param_data_o : out std_logic_vector(31 downto 0);
param_wr_o : out std_logic;
update_port_o : out std_logic
);
end component;
-- SIGNAUX INTERNES POUR CONNEXION ENTRE COM_FLOW_FIFO_RW et READPARAMS
signal data_s : std_logic_vector(15 downto 0);
signal flow_rdy_s : std_logic := '0';
signal f_empty_s : std_logic := '0';
signal flag_s : std_logic_vector(7 downto 0);
signal rdreq_s : std_logic := '0';
signal param_data_s : std_logic_vector(31 downto 0);
begin
-- MAP COM_FLOW_FIFO_RX
COM_RX_PARAMS: component com_flow_fifo_rx
generic map (
FIFO_DEPTH => FIFO_DEPTH,
FLOW_ID => FLOW_ID_SET,
IN_SIZE => DATA_HAL_SIZE,
OUT_SIZE => 16
)
port map (
clk_hal => clk_hal,
clk_proc => clk_proc,
rst_n => rst_n,
data_wr_i => data_wr_i,
data_i => data_i,
rdreq_i => rdreq_s,
pktend_i => pktend_i,
enable_i => '1',
data_o => data_s,
flow_rdy_o => flow_rdy_s,
f_empty_o => f_empty_s,
fifos_f_o => fifo_full_o,
flag_o => flag_s
);
-- MAP COMPONENT READFLOW TO params
-- pour le get params faire un flag particulier qui va declencher une reecriture sur le flow de sortie
decoder_inst :component params_flow_decoder
generic map (
MASTER_ADDR_WIDTH => MASTER_ADDR_WIDTH
)
port map (
clk => clk_proc,
rst_n => rst_n,
data_i => data_s,
flow_rdy_i => flow_rdy_s,
f_empty_i => f_empty_s,
flag_i => flag_s,
read_data_o => rdreq_s,
param_addr_o => param_addr_o,
param_data_o => param_data_s,
param_wr_o => param_wr_o,
update_port_o => tmp_update_port_o
);
param_data_o <= param_data_s;
end rtl;
| gpl-3.0 | 9317d6af58cf32ec55cf250520905edd | 0.495454 | 3.336577 | false | false | false | false |
DreamIP/GPStudio | support/io/vga_out/hdl/PLL108.vhd | 1 | 17,486 | -- megafunction wizard: %Altera PLL v15.1%
-- GENERATION: XML
-- PLL108.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity PLL108 is
port (
refclk : in std_logic := '0'; -- refclk.clk
rst : in std_logic := '0'; -- reset.reset
outclk_0 : out std_logic -- outclk0.clk
);
end entity PLL108;
architecture rtl of PLL108 is
component PLL108_0002 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
locked : out std_logic -- export
);
end component PLL108_0002;
begin
pll108_inst : component PLL108_0002
port map (
refclk => refclk, -- refclk.clk
rst => rst, -- reset.reset
outclk_0 => outclk_0, -- outclk0.clk
locked => open -- (terminated)
);
end architecture rtl; -- of PLL108
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2017 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_pll" version="15.1" >
-- Retrieval info: <generic name="debug_print_output" value="false" />
-- Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
-- Retrieval info: <generic name="device_family" value="Cyclone V" />
-- Retrieval info: <generic name="device" value="5CEBA2F17A7" />
-- Retrieval info: <generic name="gui_device_speed_grade" value="1" />
-- Retrieval info: <generic name="gui_pll_mode" value="Fractional-N PLL" />
-- Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
-- Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
-- Retrieval info: <generic name="gui_operation_mode" value="direct" />
-- Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
-- Retrieval info: <generic name="gui_fractional_cout" value="32" />
-- Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
-- Retrieval info: <generic name="gui_use_locked" value="false" />
-- Retrieval info: <generic name="gui_en_adv_params" value="false" />
-- Retrieval info: <generic name="gui_number_of_clocks" value="1" />
-- Retrieval info: <generic name="gui_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_divide_factor_n" value="1" />
-- Retrieval info: <generic name="gui_cascade_counter0" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency0" value="108.0" />
-- Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units0" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle0" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter1" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units1" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle1" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter2" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units2" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle2" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter3" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units3" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle3" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter4" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units4" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle4" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter5" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units5" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle5" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter6" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units6" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle6" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter7" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units7" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle7" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter8" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units8" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle8" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter9" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units9" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle9" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter10" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units10" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle10" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter11" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units11" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle11" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter12" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units12" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle12" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter13" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units13" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle13" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter14" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units14" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle14" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter15" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units15" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle15" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter16" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units16" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle16" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter17" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units17" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle17" value="50" />
-- Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
-- Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
-- Retrieval info: <generic name="gui_en_reconf" value="false" />
-- Retrieval info: <generic name="gui_en_dps_ports" value="false" />
-- Retrieval info: <generic name="gui_en_phout_ports" value="false" />
-- Retrieval info: <generic name="gui_phout_division" value="1" />
-- Retrieval info: <generic name="gui_mif_generate" value="false" />
-- Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
-- Retrieval info: <generic name="gui_dps_cntr" value="C0" />
-- Retrieval info: <generic name="gui_dps_num" value="1" />
-- Retrieval info: <generic name="gui_dps_dir" value="Positive" />
-- Retrieval info: <generic name="gui_refclk_switch" value="false" />
-- Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
-- Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
-- Retrieval info: <generic name="gui_switchover_delay" value="0" />
-- Retrieval info: <generic name="gui_active_clk" value="false" />
-- Retrieval info: <generic name="gui_clk_bad" value="false" />
-- Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
-- Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
-- Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
-- Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
-- Retrieval info: </instance>
-- IPFS_FILES : PLL108.vho
-- RELATED_FILES: PLL108.vhd, PLL108_0002.v
| gpl-3.0 | 0597b8987a38f39f6e1c8ecc8f34bb80 | 0.68449 | 3.083407 | false | false | false | false |
DreamIP/GPStudio | support/process/negate/hdl/negate_process.vhd | 1 | 1,577 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity negate_process is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end negate_process;
architecture rtl of negate_process is
--signal negate_strength : std_logic_vector((IN_SIZE-1) downto 0) := (others=>'1');
begin
data_process : process (clk_proc, reset_n)
begin
if(reset_n='0') then
out_data <= (others => '0');
out_dv <= '0';
out_fv <= '0';
elsif(rising_edge(clk_proc)) then
out_dv <= in_dv;
out_fv <= in_fv;
-- enabled behavior --
if(status_reg_enable_bit = '1') then
-- valid data incoming --
if(in_dv='1' and in_fv='1') then
out_data <= not in_data;
end if;
else
-- disabled behaviour --
if(in_dv='1' and in_fv='1') then
out_data <= in_data;
end if;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | 5974adcdc2a65c7f63bbdbe61056af13 | 0.493976 | 3.179435 | false | false | false | false |
DreamIP/GPStudio | support/io/com/hdl/hal/eth_marvell_88e1111/hdl/eth_udp_filter.vhd | 1 | 4,062 | -- This code filters the incoming packet (MAC + IP) and extract some other infos such as size or the port.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_package.all;
entity eth_udp_filter is
port (
RXCLK : in std_logic;
reset_n : in std_logic;
RX_i : in gmii_t;
RX_o : out gmii_t;
mac_addr_hal_msb : in std_logic_vector(23 downto 0);
mac_addr_hal_lsb : in std_logic_vector(23 downto 0);
ip_hal : in std_logic_vector(31 downto 0);
port_detected : out std_logic_vector(15 downto 0)
);
end eth_udp_filter;
architecture RTL of eth_udp_filter is
type filter_fsm is (idle,mac,size_st,ip,port_st,data);
signal state : filter_fsm;
signal rcv_mac : std_logic_vector(47 downto 0);
signal rcv_ip : std_logic_vector(31 downto 0);
signal rcv_port : std_logic_vector(15 downto 0);
signal count : unsigned(7 downto 0);
signal rcv_size : std_logic_vector(15 downto 0);
signal count_data : unsigned(15 downto 0);
signal size_detected : unsigned(15 downto 0);
signal dv_dl : std_logic;
signal mac_f : flag;
signal ip_f : flag;
begin
process(RXCLK,reset_n)
begin
if reset_n='0' then
state <= idle;
count <= x"00";
mac_f.good <='0';
mac_f.bad <='0';
RX_o.dv <= '0';
RX_o.data <= x"00";
elsif RXCLK'event and RXCLK='1' then
dv_dl <= RX_i.dv;
case(state) is
when idle =>
if RX_i.dv = '1' and dv_dl='0' then
state <= mac;
count <= x"00";
rcv_mac(7 downto 0) <= RX_i.data;
elsif RX_i.dv = '0' then
mac_f.good <= '0';
mac_f.bad <= '0';
ip_f.bad <= '0';
ip_f.good <= '0';
end if;
-- Check if MAC address fit the value in eth_slave
when mac =>
if count = x"05" then
state <= size_st;
count <= x"00";
if rcv_mac = mac_addr_hal_msb & mac_addr_hal_lsb then
mac_f.good <='1';
else
mac_f.bad <='1';
end if;
else
rcv_mac <= rcv_mac(39 downto 0) & RX_i.data;
count <= count +1;
end if;
-- Get size of the packet
when size_st =>
count <= count +1;
if count > x"08" then
if count = x"0A" then
state <= ip;
count <= x"00";
end if;
rcv_size <= rcv_size(7 downto 0) & RX_i.data;
end if;
-- Check if IP address fit the value in eth_slave
when ip =>
size_detected <= unsigned(rcv_size) - x"1C"; -- 28 bytes of ip header + udp header
count <= count +1;
if count > x"0B" then
if count = x"10" then
state <= port_st;
count <= x"00";
if rcv_ip = ip_hal then
ip_f.good <='1';
else
ip_f.bad <='1';
end if;
else
rcv_ip <=rcv_ip(23 downto 0) & RX_i.data;
end if;
end if;
-- Get port
when port_st =>
count <= count +1;
if count > x"00" then
if count = x"03" then
state <= data;
count_data <= x"0000";
count <= x"00";
port_detected <= rcv_port;
else
rcv_port <=rcv_port(7 downto 0) & RX_i.data;
end if;
end if;
-- If MAC and IP are verified then the data is transmitted to the next block
when data =>
count <= count +1;
if count > x"02" then
if mac_f.good='1' and ip_f.good='1' then
count_data <= count_data+1;
if RX_i.dv='0' or count_data=size_detected then
state <= idle;
RX_o.dv <= '0';
else
RX_o <= RX_i;
end if;
else
state <= idle;
RX_o.dv <= '0';
RX_o.data <= x"00";
end if;
end if;
when others =>
state <= idle;
end case;
end if;
end process;
end RTL;
| gpl-3.0 | 83caca3de91324b6576c91ac9e3e0c05 | 0.493599 | 2.982379 | false | false | false | false |
DreamIP/GPStudio | support/process/subsample/subsample.vhd | 1 | 2,351 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
Use ieee.numeric_std.all;
ENTITY subsample IS
generic
(
Image_width : integer := 6;
Image_heigh : integer := 6;
pixel_depth : integer := 8;
pixel_parity: std_logic := '1'; -- 1: odd ; 0: even
line_parity: std_logic := '1' -- 1: odd ; 0: even
);
PORT(
clk,reset: in std_logic;
frame_valid_i, data_valid_i : in std_logic;
frame_valid_o, data_valid_o : out std_logic;
image_i: in std_logic_vector((pixel_depth)-1 downto 0);
image_o: out std_logic_vector((pixel_depth)-1 downto 0)
);
END subsample;
ARCHITECTURE rtl of subsample is
Begin
process(clk,reset)
variable pixel_count: std_logic_vector(10 downto 0);
variable line_count: std_logic_vector(10 downto 0);
begin
if( reset = '0' )then
image_o <= ((others => '0'));
pixel_count:=(others => '0');
line_count:=(others => '0');
elsif( clk'event and clk = '1' )then
if(data_valid_i= '1')then
-- pixel and line counter
pixel_count:=pixel_count+'1';
if(pixel_count= Image_width)then
line_count:=line_count+'1';
pixel_count:=(others => '0');
end if;
if(line_count= Image_heigh)then
line_count:=(others => '0');
end if;
-- each odd/even line is valid
if( line_count(0)= line_parity)then
-- each odd/even pixel is valid
if(pixel_count(0)= pixel_parity)then
image_o<=image_i;
data_valid_o<= '1';
else
image_o <= ((others => '0'));
data_valid_o<= '0';
end if;
else
image_o <= ((others => '0'));
data_valid_o<= '0';
end if;
end if;
end if;
end process;
frame_valid_o <= frame_valid_i;
END rtl; | gpl-3.0 | a9388b5b2340764978e8a4a5ac8d8d5c | 0.431306 | 3.998299 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator.vhd | 1 | 12,844 | -- tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.13.13:59:38
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator is
generic (
AV_ADDRESS_W : integer := 9;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(8 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_begintransfer : out std_logic; -- .begintransfer
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_chipselect : out std_logic; -- .chipselect
av_debugaccess : out std_logic; -- .debugaccess
av_beginbursttransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_clken : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_read : out std_logic;
av_readdatavalid : in std_logic := '0';
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(3 downto 0);
uav_clken : in std_logic := '0'
);
end entity tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator;
architecture rtl of tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(8 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_chipselect : out std_logic; -- chipselect
av_debugaccess : out std_logic; -- debugaccess
av_read : out std_logic; -- read
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_outputenable : out std_logic -- outputenable
);
end component altera_merlin_slave_translator;
begin
nios2_qsys_0_jtag_debug_module_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_begintransfer => av_begintransfer, -- .begintransfer
av_byteenable => av_byteenable, -- .byteenable
av_chipselect => av_chipselect, -- .chipselect
av_debugaccess => av_debugaccess, -- .debugaccess
av_read => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_outputenable => open -- (terminated)
);
end architecture rtl; -- of tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator
| gpl-2.0 | bd9a7136189ea944dfa73553dbffda27 | 0.435612 | 4.297089 | false | false | false | false |
DreamIP/GPStudio | support/component/gp_com/flow_to_com/flow_to_com_arb4.vhd | 1 | 5,632 | -- **************************************************************************
-- READ FLOW
-- **************************************************************************
-- Ce composant est connecte a un com_flow_fifo en entree et a un processing (FV/LV/Data) en sortie
--
-- 16/10/2014 - creation
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ComFlow_pkg.all;
-- Flow out arbiter 4 ways
entity flow_to_com_arb4 is
generic (
DATA_HAL_SIZE : POSITIVE := 16
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- fv 0 signals
rdreq_0_o : out std_logic;
data_0_i : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
flow_rdy_0_i : in std_logic;
f_empty_0_i : in std_logic;
size_packet_0_i : in std_logic_vector(15 downto 0);
-- fv 1 signals
rdreq_1_o : out std_logic;
data_1_i : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
flow_rdy_1_i : in std_logic;
f_empty_1_i : in std_logic;
size_packet_1_i : in std_logic_vector(15 downto 0);
-- fv 2 signals
rdreq_2_o : out std_logic;
data_2_i : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
flow_rdy_2_i : in std_logic;
f_empty_2_i : in std_logic;
size_packet_2_i : in std_logic_vector(15 downto 0);
-- fv 3 signals
rdreq_3_o : out std_logic;
data_3_i : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
flow_rdy_3_i : in std_logic;
f_empty_3_i : in std_logic;
size_packet_3_i : in std_logic_vector(15 downto 0);
-- fv usb signals
rdreq_usb_i : in std_logic;
data_usb_o : out std_logic_vector(DATA_HAL_SIZE-1 downto 0);
flow_rdy_usb_o : out std_logic;
f_empty_usb_o : out std_logic;
size_packet_o : out std_logic_vector(15 downto 0)
);
end flow_to_com_arb4;
architecture rtl of flow_to_com_arb4 is
---------------------------------------------------------
-- SIGNALS
---------------------------------------------------------
signal sel : std_logic_vector(1 downto 0) := (others=>'0');
type fsm_state_t is (Idle, Hold);
signal fsm_state : fsm_state_t := Idle;
signal rdreq_usb_r : std_logic := '0';
signal priority : unsigned(1 downto 0) := (others=>'0');
begin
FSM:process (clk, rst_n)
begin
if (rst_n = '0') then
sel <= "00";
rdreq_usb_r <= '0';
priority <= "00";
elsif rising_edge(clk) then
rdreq_usb_r <= rdreq_usb_i;
case (fsm_state) is
when Idle =>
if (flow_rdy_0_i = '1' or flow_rdy_1_i ='1' or flow_rdy_2_i ='1' or flow_rdy_3_i ='1') then
fsm_state <= Hold;
end if;
case priority is
when "00" =>
if (flow_rdy_0_i = '1') then
sel <= "00";
elsif (flow_rdy_1_i = '1') then
sel <= "01";
elsif (flow_rdy_2_i = '1') then
sel <= "10";
elsif (flow_rdy_3_i = '1') then
sel <= "11";
end if;
when "01" =>
if (flow_rdy_1_i = '1') then
sel <= "01";
elsif (flow_rdy_0_i = '1') then
sel <= "00";
elsif (flow_rdy_2_i = '1') then
sel <= "10";
elsif (flow_rdy_3_i = '1') then
sel <= "11";
end if;
when "10" =>
if (flow_rdy_2_i = '1') then
sel <= "10";
elsif (flow_rdy_0_i = '1') then
sel <= "00";
elsif (flow_rdy_1_i = '1') then
sel <= "01";
elsif (flow_rdy_3_i = '1') then
sel <= "11";
end if;
when "11" =>
if (flow_rdy_3_i = '1') then
sel <= "11";
elsif (flow_rdy_0_i = '1') then
sel <= "00";
elsif (flow_rdy_1_i = '1') then
sel <= "01";
elsif (flow_rdy_2_i = '1') then
sel <= "10";
end if;
end case;
when Hold =>
if (rdreq_usb_r='1' and rdreq_usb_i='0') then
priority <= priority + "1";
fsm_state <= Idle;
end if;
end case;
end if;
end process;
SEL_inst: process (sel, rdreq_usb_i,
data_0_i, flow_rdy_0_i, f_empty_0_i,
data_1_i, flow_rdy_1_i, f_empty_1_i,
data_2_i, flow_rdy_2_i, f_empty_2_i,
data_3_i, flow_rdy_3_i, f_empty_3_i)
begin
case (sel) is
when "00" =>
rdreq_0_o <= rdreq_usb_i;
rdreq_1_o <= '0';
rdreq_2_o <= '0';
rdreq_3_o <= '0';
data_usb_o <= data_0_i;
flow_rdy_usb_o <= flow_rdy_0_i;
f_empty_usb_o <= f_empty_0_i;
size_packet_o <= size_packet_0_i;
when "01" =>
rdreq_0_o <= '0';
rdreq_1_o <= rdreq_usb_i;
rdreq_2_o <= '0';
rdreq_3_o <= '0';
data_usb_o <= data_1_i;
flow_rdy_usb_o <= flow_rdy_1_i;
f_empty_usb_o <= f_empty_1_i;
size_packet_o <= size_packet_1_i;
when "10" =>
rdreq_0_o <= '0';
rdreq_1_o <= '0';
rdreq_2_o <= rdreq_usb_i;
rdreq_3_o <= '0';
data_usb_o <= data_2_i;
flow_rdy_usb_o <= flow_rdy_2_i;
f_empty_usb_o <= f_empty_2_i;
size_packet_o <= size_packet_2_i;
when "11" =>
rdreq_0_o <= '0';
rdreq_1_o <= '0';
rdreq_2_o <= '0';
rdreq_3_o <= rdreq_usb_i;
data_usb_o <= data_3_i;
flow_rdy_usb_o <= flow_rdy_3_i;
f_empty_usb_o <= f_empty_3_i;
size_packet_o <= size_packet_3_i;
when others =>
rdreq_0_o <= '0';
rdreq_1_o <= '0';
rdreq_2_o <= '0';
rdreq_3_o <= '0';
data_usb_o <= (others=>'0');
flow_rdy_usb_o <= '0';
f_empty_usb_o <= '0';
size_packet_o <= (others=>'0');
end case;
end process;
end rtl;
| gpl-3.0 | 940d5dbc254f8a6e3dfc6b325bf1a2bc | 0.472834 | 2.690874 | false | false | false | false |
hoglet67/ElectronFpga | AtomBusMon/src/T80/T80a.vhd | 1 | 11,067 | --
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247a
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
-- 0247 : Fixed bus req/ack cycle
--
-- 0247a: 7th of September, 2003 by Kazuhiro Tsujikawa ([email protected])
-- Fixed IORQ_n, RD_n, WR_n bus timing
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80a is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
-- Additions
TS : out std_logic_vector(2 downto 0);
Regs : out std_logic_vector(255 downto 0);
PdcData : out std_logic_vector(7 downto 0);
-- Original Signals
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
Din : in std_logic_vector(7 downto 0);
Dout : out std_logic_vector(7 downto 0);
Den : out std_logic
);
end T80a;
architecture rtl of T80a is
signal Reset_s : std_logic;
signal IntCycle_n : std_logic;
signal NMICycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal MREQ : std_logic;
signal MReq_Inhibit : std_logic;
signal IReq_Inhibit : std_logic; -- 0247a
signal Req_Inhibit : std_logic;
signal RD : std_logic;
signal MREQ_n_i : std_logic;
signal IORQ_n_i : std_logic;
signal RD_n_i : std_logic;
signal WR_n_i : std_logic;
signal WR_n_j : std_logic; -- 0247a
signal RFSH_n_i : std_logic;
signal BUSAK_n_i : std_logic;
signal A_i : std_logic_vector(15 downto 0);
signal DO : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal Wait_s : std_logic;
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
signal HALT_n_int : std_logic;
signal iack1 : std_logic;
signal iack2 : std_logic;
begin
BUSAK_n <= BUSAK_n_i;
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
RD_n_i <= not RD or (IORQ and IReq_Inhibit) or Req_Inhibit; -- DMB
WR_n_j <= WR_n_i or (IORQ and IReq_Inhibit); -- DMB
HALT_n <= HALT_n_int;
--Remove tristate as in ICE-Z80 this is implmeneted in Z80CpuMon
--MREQ_n <= MREQ_n_i; when BUSAK_n_i = '1' else 'Z';
--IORQ_n <= IORQ_n_i or IReq_Inhibit when BUSAK_n_i = '1' else 'Z'; -- 0247a
--RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
--WR_n <= WR_n_j when BUSAK_n_i = '1' else 'Z'; -- 0247a
--RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
--A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
MREQ_n <= MREQ_n_i;
IORQ_n <= IORQ_n_i or IReq_Inhibit or Req_inhibit; --DMB
RD_n <= RD_n_i;
WR_n <= WR_n_j; -- 0247a
RFSH_n <= RFSH_n_i;
A <= A_i;
Dout <= DO;
Den <= Write and BUSAK_n_i;
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
Reset_s <= '0';
elsif CLK_n'event and CLK_n = '1' then
Reset_s <= '1';
end if;
end process;
u0 : T80
generic map(
Mode => Mode,
IOWait => 1)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n_i,
HALT_n => HALT_n_int,
WAIT_n => Wait_s,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => Reset_s,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n_i,
CLK_n => CLK_n,
A => A_i,
DInst => Din,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n,
NMICycle_n => NMICycle_n,
REG => Regs(211 downto 0),
DIRSet => '0',
DIR => (others => '0')
);
Regs(255 downto 212) <= (others => '0');
process (CLK_n)
begin
if CLK_n'event and CLK_n = '0' then
if CEN = '1' then
Wait_s <= WAIT_n;
if TState = "011" and BUSAK_n_i = '1' then
DI_Reg <= to_x01(Din);
end if;
end if;
end if;
end process;
process (CLK_n) -- 0247a
begin
if CLK_n'event and CLK_n = '1' then
IReq_Inhibit <= (not IORQ) and IntCycle_n;
end if;
end process;
process (Reset_s,CLK_n) -- 0247a
begin
if Reset_s = '0' then
WR_n_i <= '1';
elsif CLK_n'event and CLK_n = '0' then
if CEN = '1' then
if (IORQ = '0') then
if TState = "010" then
WR_n_i <= not Write;
elsif Tstate = "011" then
WR_n_i <= '1';
end if;
else
if TState = "001" then -- DMB
WR_n_i <= not Write;
elsif Tstate = "011" then
WR_n_i <= '1';
end if;
end if;
end if;
end if;
end process;
process (Reset_s,CLK_n) -- 0247a
begin
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
if MCycle = "001" and TState = "010" and wait_s = '1' then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
end if;
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
MReq_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '0' then
if CEN = '1' then
if MCycle = "001" and TState = "010" then
MReq_Inhibit <= '1';
else
MReq_Inhibit <= '0';
end if;
end if;
end if;
end process;
process(Reset_s,CLK_n) -- 0247a
begin
if Reset_s = '0' then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
iack1 <= '0';
iack2 <= '0';
elsif CLK_n'event and CLK_n = '0' then
if CEN = '1' then
if MCycle = "001" then
if IntCycle_n = '1' then
-- Normal M1 Cycle
if TState = "001" then
RD <= '1';
MREQ <= '1';
IORQ_n_i <= '1';
end if;
else
-- Interupt Ack Cycle
-- 5 T-states: T1 T1 (auto wait) T1 (auto wait) T2 T3
-- Assert IORQ in middle of third T1
if TState = "001" then
iack1 <= '1';
iack2 <= iack1;
else
iack1 <= '0';
iack2 <= '0';
end if;
if iack2 = '1' then
IORQ_n_i <= '0';
end if;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '1';
end if;
if TState = "100" then
MREQ <= '0';
end if;
else
if TState = "001" and NoRead = '0' then
IORQ_n_i <= not IORQ;
MREQ <= not IORQ;
RD <= not Write; -- DMB
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
end if;
end if;
end if;
end if;
end process;
TS <= TState;
PdcData <= (not HALT_n_int) & (not NMICycle_n) & (not IntCycle_n) & "00000";
end;
| gpl-3.0 | 3ef363acb31944d363d82fb0f567101c | 0.476371 | 3.790068 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_Pixel_Scaler.vhd | 1 | 10,821 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module scales video streams on the DE boards. *
-- * *
-- ******************************************************************************
ENTITY Video_System_Pixel_Scaler IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
GENERIC (
DW :INTEGER := 29; -- Frame's Data Width
EW :INTEGER := 1; -- Frame's Empty Width
WIW :INTEGER := 8; -- Incoming frame's width's address width
HIW :INTEGER := 7; -- Incoming frame's height's address width
WIDTH_IN :INTEGER := 320;
WIDTH_DROP_MASK :STD_LOGIC_VECTOR( 3 DOWNTO 0) := B"0000";
HEIGHT_DROP_MASK :STD_LOGIC_VECTOR( 3 DOWNTO 0) := B"0000";
MH_WW :INTEGER := 8; -- Multiply height's incoming width's address width
MH_WIDTH_IN :INTEGER := 320; -- Multiply height's incoming width
MH_CW :INTEGER := 0; -- Multiply height's counter width
MW_CW :INTEGER := 0 -- Multiply width's counter width
);
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
stream_in_data :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_in_startofpacket :IN STD_LOGIC;
stream_in_endofpacket :IN STD_LOGIC;
stream_in_empty :IN STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_in_valid :IN STD_LOGIC;
stream_out_ready :IN STD_LOGIC;
-- Bidirectional
-- Outputs
stream_in_ready :BUFFER STD_LOGIC;
stream_out_data :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_empty :BUFFER STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_out_valid :BUFFER STD_LOGIC
);
END Video_System_Pixel_Scaler;
ARCHITECTURE Behaviour OF Video_System_Pixel_Scaler IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
SIGNAL internal_data :STD_LOGIC_VECTOR(DW DOWNTO 0);
SIGNAL internal_startofpacket :STD_LOGIC;
SIGNAL internal_endofpacket :STD_LOGIC;
SIGNAL internal_valid :STD_LOGIC;
SIGNAL internal_ready :STD_LOGIC;
-- Internal Registers
-- State Machine Registers
-- Integers
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
COMPONENT altera_up_video_scaler_multiply_height
GENERIC (
DW :INTEGER;
WW :INTEGER;
WIDTH :INTEGER;
CW :INTEGER
);
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
stream_in_data :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_in_startofpacket :IN STD_LOGIC;
stream_in_endofpacket :IN STD_LOGIC;
stream_in_valid :IN STD_LOGIC;
stream_out_ready :IN STD_LOGIC;
-- Bi-Directional
-- Outputs
stream_in_ready :BUFFER STD_LOGIC;
stream_out_data :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_valid :BUFFER STD_LOGIC
);
END COMPONENT;
COMPONENT altera_up_video_scaler_multiply_width
GENERIC (
DW :INTEGER;
CW :INTEGER
);
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
stream_in_data :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_in_startofpacket :IN STD_LOGIC;
stream_in_endofpacket :IN STD_LOGIC;
stream_in_valid :IN STD_LOGIC;
stream_out_ready :IN STD_LOGIC;
-- Bi-Directional
-- Outputs
stream_in_ready :BUFFER STD_LOGIC;
stream_out_data :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_valid :BUFFER STD_LOGIC
);
END COMPONENT;
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
-- Output Registers
-- Internal Registers
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
-- Output Assignments
stream_out_empty <= (OTHERS => '0');
-- Internal Assignments
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
Multiply_Height : altera_up_video_scaler_multiply_height
GENERIC MAP (
DW => DW,
WW => MH_WW,
WIDTH => MH_WIDTH_IN,
CW => MH_CW
)
PORT MAP (
-- Inputs
clk => clk,
reset => reset,
stream_in_data => stream_in_data,
stream_in_startofpacket => stream_in_startofpacket,
stream_in_endofpacket => stream_in_endofpacket,
stream_in_valid => stream_in_valid,
stream_out_ready => internal_ready,
-- Bi-Directional
-- Outputs
stream_in_ready => stream_in_ready,
stream_out_data => internal_data,
stream_out_startofpacket => internal_startofpacket,
stream_out_endofpacket => internal_endofpacket,
stream_out_valid => internal_valid
);
Multiply_Width : altera_up_video_scaler_multiply_width
GENERIC MAP (
DW => DW,
CW => MW_CW
)
PORT MAP (
-- Inputs
clk => clk,
reset => reset,
stream_in_data => internal_data,
stream_in_startofpacket => internal_startofpacket,
stream_in_endofpacket => internal_endofpacket,
stream_in_valid => internal_valid,
stream_out_ready => stream_out_ready,
-- Bi-Directional
-- Outputs
stream_in_ready => internal_ready,
stream_out_data => stream_out_data,
stream_out_startofpacket => stream_out_startofpacket,
stream_out_endofpacket => stream_out_endofpacket,
stream_out_valid => stream_out_valid
);
END Behaviour;
| gpl-2.0 | abb0ca6201a9240f7b070320e3af1fdd | 0.473062 | 4.273697 | false | false | false | false |
DreamIP/GPStudio | support/io/com/hdl/flow_to_com.vhd | 1 | 8,339 | -- This block receives a flow from a GPStudio block.
-- Depending on the data valid and flow valid, it add the GPStudio header (Start of Frame and End of Frame flags and the number of the packet)
-- before sending the data to the HAL block.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.com_package.all;
entity flow_to_com is
generic (
ID_FIFO : std_logic_vector(5 downto 0) := "000001";
FLOW_IN_SIZE : integer := 8;
DATA_WIDTH : integer := 8;
FIFO_DEPTH : integer := 2048;
ONE_PACKET : integer := 1450
);
port (
clk_hal : in std_logic;
clk_proc : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
flow_in_data : in std_logic_vector(FLOW_IN_SIZE-1 downto 0);
flow_in_fv : in std_logic;
flow_in_dv : in std_logic;
read_data : in std_logic;
ready : out std_logic;
data_size : out std_logic_vector(15 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end flow_to_com;
architecture RTL of flow_to_com is
type flow_to_com_fsm is (idle, gps_header, data_state);
signal state : flow_to_com_fsm; --Flow to hal FSM
signal count_fifo : std_logic_vector(15 downto 0);
signal one_packet_size : std_logic_vector(15 downto 0);
signal num_packet_s : std_logic_vector(7 downto 0);
signal ready_s : std_logic;
signal wrreq,rdreq : std_logic;
signal reset : std_logic;
signal flow_fv_dl : std_logic;
signal empty_fifo : std_logic;
signal rd_flags,wr_flags : std_logic;
signal empty_flags : std_logic;
signal data_flags : std_logic_vector(17 downto 0);
signal count_wr,count_wr_b : std_logic_vector(15 downto 0);
signal count_rd : std_logic_vector(15 downto 0);
signal pkt_size : std_logic_vector(15 downto 0);
signal sof,eof : std_logic;
signal data,data_out_s : std_logic_vector(7 downto 0);
signal flags_out : std_logic_vector(17 downto 0);
signal count_fsm : std_logic_vector(3 downto 0);
signal data_size_s : std_logic_vector(15 downto 0);
signal read_data_dl : std_logic;
signal rdreq_s : std_logic;
begin
reset <= not reset_n;
rd_flags <= '1' when read_data='1' and read_data_dl='0' and state=idle else '0';
ready <= '0' when empty_fifo='1' else ready_s;
one_packet_size <= std_logic_vector(to_unsigned(ONE_PACKET,16));
data_size <= data_size_s+x"2";
--- Write fifo only when enable
wrreq <= flow_in_dv when enable='1' else '0';
--- Fifo that contains data
fifo_data_inst : entity work.gp_dcfifo
generic map (DATA_WIDTH => 8,
FIFO_DEPTH => FIFO_DEPTH)
port map(
aclr => reset,
data => flow_in_data,
rdclk => clk_hal,
rdreq => rdreq,
wrclk => clk_proc,
wrreq => wrreq,
q => data,
rdempty => empty_fifo
);
--- Fifo that contains flags of the packets and their size
fifo_flags_inst : entity work.gp_dcfifo
generic map (DATA_WIDTH => 18,
FIFO_DEPTH => 256)
port map(
aclr => reset,
data => data_flags,
rdclk => clk_hal,
rdreq => rd_flags,
wrclk => clk_proc,
wrreq => wr_flags,
q => flags_out,
rdempty => empty_flags
);
data_flags <= sof & eof & pkt_size;
count_wr_b <= std_logic_vector(to_unsigned(to_integer(unsigned(count_wr)) rem ONE_PACKET,16));
pkt_size <= count_wr when count_wr<one_packet_size else
count_wr_b when eof='1' else
one_packet_size;
----- Set the write signals for fifo flags
process(clk_proc, reset_n)
begin
if reset_n='0' then
count_wr <= x"0000";
wr_flags <= '0';
sof <= '0';
eof <= '0';
elsif clk_proc'event and clk_proc='1' then
flow_fv_dl <= flow_in_fv;
--- Counting data write
if wrreq='1' then
count_wr <= count_wr+1;
elsif eof='1' then
count_wr <= x"0000";
end if;
--- Control fifo flags write
if (flow_in_fv='0' and flow_fv_dl='1') or (to_integer(unsigned(count_wr)) rem ONE_PACKET=0 and count_wr>=one_packet_size) then
wr_flags <= '1';
else
wr_flags <= '0';
end if;
--- Set flags for each packet
--- Set Start of Frame when a flow starts
if flow_in_fv='1' and flow_fv_dl='0' then
sof <= '1';
elsif eof='1' or count_wr>one_packet_size then
sof <= '0';
end if;
--- Set End of Frame when a flow ends
if flow_in_fv='0' and flow_fv_dl='1' then
eof <= '1';
elsif flow_in_fv='1' and flow_fv_dl='0' then
eof <= '0';
end if;
end if;
end process;
----- Set the read signals for fifo flags and place gps header when HAL starts to read
process(clk_hal, reset_n)
begin
if reset_n='0' then
count_rd <= x"0000";
data_size_s <= x"0000";
num_packet_s <= x"00";
elsif clk_hal'event and clk_hal='1' then
read_data_dl <= read_data;
--- Control fifo flags read
if rdreq='1' then
count_rd <= count_rd +1;
elsif state=idle then
count_rd <= x"0000";
end if;
--- Place gps header then read data from fifo
case state is
when idle =>
rdreq_s <= '0';
if rd_flags='1' then
state <= gps_header;
count_fsm <= x"0";
end if;
when gps_header =>
if read_data='1' then
count_fsm <= count_fsm+1;
if count_fsm=x"0" then
data_out_s <= ID_FIFO & flags_out(17 downto 16);
if flags_out(17)='1' then --- Increment numero of the packet only when SoF=0
num_packet_s <= x"00";
else
num_packet_s <= num_packet_s+1;
end if;
elsif count_fsm=x"1" then
data_out_s <= num_packet_s;
rdreq_s <= '1';
data_size_s <= flags_out(15 downto 0);
elsif count_fsm=x"2" then
state <= data_state;
data_out_s <= data;
end if;
end if;
when data_state =>
if read_data='1' then
rdreq_s <= '1';
if count_rd=data_size_s-x"1" or empty_fifo='1' then
state <= idle;
rdreq_s <= '0';
end if;
end if;
when others =>
state <= idle;
end case;
end if;
end process;
data_out <= data_out_s when state=gps_header else data;
rdreq <= '0' when (ready_s='0' or empty_fifo='1') else rdreq_s;
----- Set the ready signal
process(clk_hal, reset_n)
begin
if reset_n='0' then
ready_s <= '0';
elsif clk_hal'event and clk_hal='1' then
if empty_flags='0' and ready_s='0' then
ready_s <= '1';
elsif (state=data_state and count_rd=data_size_s-x"1") or (empty_fifo='1') then --- Not ready when a full packet has been read or when it's the last packet
ready_s <= '0';
end if;
end if;
end process;
end RTL;
| gpl-3.0 | f6a932fb04359dfdd66b794b987561c7 | 0.476556 | 3.751237 | false | false | false | false |
hoglet67/ElectronFpga | AtomBusMon/src/MC6809CpuMon.vhd | 1 | 12,849 | -------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : MC6808CpuMon.vhd
-- /___/ /\ Timestamp : 24/10/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: MC6808CpuMon
--Device: multiple
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MC6809CpuMon is
generic (
ClkMult : integer;
ClkDiv : integer;
ClkPer : real;
num_comparators : integer;
avr_prog_mem_size : integer
);
port (
-- Fast clock
clock : in std_logic;
-- Quadrature clocks
E : in std_logic;
Q : in std_logic;
--6809 Signals
DMA_n_BREQ_n : in std_logic;
-- 6809E Sig
TSC : in std_logic;
LIC : out std_logic;
AVMA : out std_logic;
BUSY : out std_logic;
-- Signals common to both 6809 and 6809E
RES_n : in std_logic;
NMI_n : in std_logic;
IRQ_n : in std_logic;
FIRQ_n : in std_logic;
HALT_n : in std_logic;
BS : out std_logic;
BA : out std_logic;
R_W_n : out std_logic;
Addr : out std_logic_vector(15 downto 0);
Data : inout std_logic_vector(7 downto 0);
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- Switches
sw_reset_cpu : in std_logic;
sw_reset_avr : in std_logic;
-- LEDs
led_bkpt : out std_logic;
led_trig0 : out std_logic;
led_trig1 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic;
-- Debugging signals
test1 : out std_logic;
test2 : out std_logic
);
end MC6809CpuMon;
architecture behavioral of MC6809CpuMon is
signal clock_avr : std_logic;
signal cpu_clk : std_logic;
signal cpu_reset_n : std_logic;
signal busmon_clk : std_logic;
signal R_W_n_int : std_logic;
signal NMI_sync : std_logic;
signal IRQ_sync : std_logic;
signal FIRQ_sync : std_logic;
signal HALT_sync : std_logic;
signal Addr_int : std_logic_vector(15 downto 0);
signal Din : std_logic_vector(7 downto 0);
signal Dout : std_logic_vector(7 downto 0);
signal Dbusmon : std_logic_vector(7 downto 0);
signal Sync_int : std_logic;
signal hold : std_logic;
signal memory_rd : std_logic;
signal memory_wr : std_logic;
signal memory_rd1 : std_logic;
signal memory_wr1 : std_logic;
signal memory_addr : std_logic_vector(15 downto 0);
signal memory_addr1 : std_logic_vector(15 downto 0);
signal memory_dout : std_logic_vector(7 downto 0);
signal memory_din : std_logic_vector(7 downto 0);
signal memory_done : std_logic;
signal Regs : std_logic_vector(111 downto 0);
signal Regs1 : std_logic_vector(255 downto 0);
signal last_PC : std_logic_vector(15 downto 0);
signal ifetch : std_logic;
signal ifetch1 : std_logic;
signal SS_Single : std_logic;
signal SS_Step : std_logic;
signal CountCycle : std_logic;
signal special : std_logic_vector(2 downto 0);
signal LIC_int : std_logic;
signal E_a : std_logic; -- E delayed by 0..20ns
signal E_b : std_logic; -- E delayed by 20..40ns
signal E_c : std_logic; -- E delayed by 40..60ns
signal E_d : std_logic; -- E delayed by 60..80ns
signal E_e : std_logic; -- E delayed by 80..100ns
signal E_f : std_logic; -- E delayed by 100..120ns
signal E_g : std_logic; -- E delayed by 120..140ns
signal E_h : std_logic; -- E delayed by 120..140ns
signal E_i : std_logic; -- E delayed by 120..140ns
signal data_wr : std_logic;
signal nRSTout : std_logic;
signal NMI_n_masked : std_logic;
signal IRQ_n_masked : std_logic;
signal FIRQ_n_masked : std_logic;
begin
LIC <= LIC_int;
-- The following outputs are not implemented
-- BUSY (6809E mode)
BUSY <= '0';
-- The following inputs are not implemented
-- DMA_n_BREQ_n (6809 mode)
inst_dcm0 : entity work.DCM0
generic map (
ClkMult => ClkMult,
ClkDiv => ClkDiv,
ClkPer => ClkPer
)
port map(
CLKIN_IN => clock,
CLKFX_OUT => clock_avr
);
mon : entity work.BusMonCore
generic map (
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
clock_avr => clock_avr,
busmon_clk => busmon_clk,
busmon_clken => '1',
cpu_clk => cpu_clk,
cpu_clken => '1',
Addr => Addr_int,
Data => Dbusmon,
Rd_n => not R_W_n_int,
Wr_n => R_W_n_int,
RdIO_n => '1',
WrIO_n => '1',
Sync => Sync_int,
Rdy => open,
nRSTin => RES_n,
nRSTout => cpu_reset_n,
CountCycle => CountCycle,
trig => trig,
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk,
Regs => Regs1,
RdMemOut => memory_rd,
WrMemOut => memory_wr,
RdIOOut => open,
WrIOOut => open,
AddrOut => memory_addr,
DataOut => memory_dout,
DataIn => memory_din,
Done => memory_done,
Special => special,
SS_Step => SS_Step,
SS_Single => SS_Single
);
FIRQ_n_masked <= FIRQ_n or special(2);
NMI_n_masked <= NMI_n or special(1);
IRQ_n_masked <= IRQ_n or special(0);
-- The CPU is slightly pipelined and the register update of the last
-- instruction overlaps with the opcode fetch of the next instruction.
--
-- If the single stepping stopped on the opcode fetch cycle, then the registers
-- valued would not accurately reflect the previous instruction.
--
-- To work around this, when single stepping, we stop on the cycle after
-- the opcode fetch, which means the program counter has advanced.
--
-- To hide this from the user single stepping, all we need to do is to
-- also pipeline the value of the program counter by one stage to compensate.
last_pc_gen : process(cpu_clk)
begin
if rising_edge(cpu_clk) then
if (hold = '0') then
last_PC <= Regs(95 downto 80);
end if;
end if;
end process;
Regs1( 79 downto 0) <= Regs( 79 downto 0);
Regs1( 95 downto 80) <= last_PC;
Regs1(111 downto 96) <= Regs(111 downto 96);
Regs1(255 downto 112) <= (others => '0');
inst_cpu09: entity work.cpu09 port map (
clk => cpu_clk,
rst => not cpu_reset_n,
vma => AVMA,
lic_out => LIC_int,
ifetch => ifetch,
opfetch => open,
ba => BA,
bs => BS,
addr => Addr_int,
rw => R_W_n_int,
data_out => Dout,
data_in => Din,
irq => IRQ_sync,
firq => FIRQ_sync,
nmi => NMI_sync,
halt => HALT_sync,
hold => hold,
Regs => Regs
);
-- Synchronize all external inputs, to avoid subtle bugs like missed interrupts
irq_gen : process(cpu_clk)
begin
if falling_edge(cpu_clk) then
NMI_sync <= not NMI_n_masked;
IRQ_sync <= not IRQ_n_masked;
FIRQ_sync <= not FIRQ_n_masked;
HALT_sync <= not HALT_n;
end if;
end process;
-- This block generates a sync signal that has the same characteristic as
-- a 6502 sync, i.e. asserted during the fetching the first byte of each instruction.
-- The below logic copes ifetch being active for all bytes of the instruction.
sync_gen : process(cpu_clk)
begin
if rising_edge(cpu_clk) then
if (hold = '0') then
ifetch1 <= ifetch and not LIC_int;
end if;
end if;
end process;
Sync_int <= ifetch and not ifetch1;
-- This block generates a hold signal that acts as the inverse of a clock enable
-- for the 6809. See comments above for why this is a cycle later than the way
-- we would do if for the 6502.
hold_gen : process(cpu_clk)
begin
if rising_edge(cpu_clk) then
if (Sync_int = '1') then
-- stop after the opcode has been fetched
hold <= SS_Single;
elsif (SS_Step = '1') then
-- start again when the single step command is issues
hold <= '0';
end if;
end if;
end process;
-- Only count cycles when the 6809 is actually running
CountCycle <= not hold;
-- this block delays memory_rd, memory_wr, memory_addr until the start of the next cpu clk cycle
-- necessary because the cpu mon block is clocked of the opposite edge of the clock
-- this allows a full cpu clk cycle for cpu mon reads and writes
mem_gen : process(cpu_clk)
begin
if rising_edge(cpu_clk) then
memory_rd1 <= memory_rd;
memory_wr1 <= memory_wr;
memory_addr1 <= memory_addr;
end if;
end process;
R_W_n <= 'Z' when TSC = '1' else
'1' when memory_rd1 = '1' else
'0' when memory_wr1 = '1' else
R_W_n_int;
Addr <= (others => 'Z') when TSC = '1' else
memory_addr1 when (memory_rd1 = '1' or memory_wr1 = '1') else
Addr_int;
data_latch : process(E)
begin
if falling_edge(E) then
Din <= Data;
memory_din <= Data;
end if;
end process;
Data <= memory_dout when TSC = '0' and data_wr = '1' and memory_wr1 = '1' else
Dout when TSC = '0' and data_wr = '1' and R_W_n_int = '0' and memory_rd1 = '0' else
(others => 'Z');
-- Version of data seen by the Bus Mon need to use Din rather than the
-- external bus value as by the rising edge of cpu_clk we will have stopped driving
-- the external bus. On the ALS version we get away way this, but on the GODIL
-- version, due to the pullups, we don't. So all write watch breakpoints see
-- the data bus as 0xFF.
Dbusmon <= Din when R_W_n_int = '1' else Dout;
memory_done <= memory_rd1 or memory_wr1;
-- Delayed/Deglitched version of the E clock
e_gen : process(clock)
begin
if rising_edge(clock) then
E_a <= E;
E_b <= E_a;
if E_b /= E_i then
E_c <= E_b;
end if;
E_d <= E_c;
E_e <= E_d;
E_f <= E_e;
E_g <= E_f;
E_h <= E_g;
E_i <= E_h;
end if;
end process;
-- Main clock timing control
-- E_c is delayed by 40-60ns
-- On a real 6809 the output delay (to ADDR, RNW, BA, BS) is 65ns (measured)
cpu_clk <= not E_c;
busmon_clk <= E_c;
-- Data bus write timing control
--
-- When data_wr is 0 the bus is high impedence
--
-- This avoids bus conflicts when the direction of the data bus
-- changes from read to write (or visa versa).
--
-- Note: on the dragon this is not critical; setting to '1' seemed to work
data_wr <= Q or E;
-- Spare pins used for testing
test1 <= E_a;
test2 <= E_c;
end behavioral;
| gpl-3.0 | 3160ba24975c81dbec8ed46d119e4ad5 | 0.501128 | 3.768035 | false | false | false | false |
DreamIP/GPStudio | support/io/mt9/hdl/mt9_config_i2c.vhd | 1 | 11,632 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library std;
entity mt9_config_i2c is
port(
reset_n : in std_logic;
mt9_extclk : in std_logic;
mt9_sclk : in std_logic;
mt9_sclkdouble : in std_logic;
mt9_extclk_o : out std_logic;
mt9_reset_n_o : out std_logic;
mt9_standby_o : out std_logic;
mt9_oe_n_o : out std_logic;
mt9_trigger_o : out std_logic;
mt9_saddr_o : out std_logic;
mt9_sdata_io : inout std_logic;
mt9_sclk_o : out std_logic;
-- connections from mt9_config_i2c
xstart_i : in std_logic_vector(15 downto 0);
ystart_i : in std_logic_vector(15 downto 0);
xend_i : in std_logic_vector(15 downto 0);
yend_i : in std_logic_vector(15 downto 0);
autoexp_i : in std_logic;
autoexptarget_i : in std_logic_vector(15 downto 0);
autoexpvmin_i : in std_logic_vector(15 downto 0);
autoexpvmax_i : in std_logic_vector(15 downto 0);
autoexpstepmin_i : in std_logic_vector(15 downto 0);
autoexpstepmax_i : in std_logic_vector(15 downto 0);
autoexpdampofset_i : in std_logic_vector(15 downto 0);
autoexpdampgain_i : in std_logic_vector(15 downto 0);
autoexpdampmax_i : in std_logic_vector(15 downto 0);
flipvert_i : in std_logic;
mirrorx_i : in std_logic;
binning_i : in std_logic;
integtime_i : in std_logic_vector(15 downto 0);
linelenght_i : in std_logic_vector(15 downto 0);
send_reconf_i : in std_logic;
mt9_conf_done_o : out std_logic
);
end mt9_config_i2c;
architecture rtl of mt9_config_i2c is
constant GEN_NUM_REG : integer := 20;
-- MT9 I2C constant for comunication
constant MT9_I2C_SLAVE_ADDR : std_logic_vector(7 downto 0) := x"20";
constant Y_ADDR_START_I2CREG : std_logic_vector(15 downto 0) := x"3002";
constant X_ADDR_START_I2CREG : std_logic_vector(15 downto 0) := x"3004";
constant Y_ADDR_END_I2CREG : std_logic_vector(15 downto 0) := x"3006";
constant X_ADDR_END_I2CREG : std_logic_vector(15 downto 0) := x"3008";
constant RESET_REGISTER_I2CREG : std_logic_vector(15 downto 0) := x"301A";
constant COARSE_INTEGR_TIME_I2CREG : std_logic_vector(15 downto 0) := x"3012";
constant AE_CTRL_REG_I2CREG : std_logic_vector(15 downto 0) := x"3100";
constant AE_TARGET_I2CREG : std_logic_vector(15 downto 0) := x"3102";
constant AE_MINEX_I2CREG : std_logic_vector(15 downto 0) := x"311E";
constant AE_MAXEX_I2CREG : std_logic_vector(15 downto 0) := x"311C";
constant AE_MINSTEP_I2CREG : std_logic_vector(15 downto 0) := x"3108";
constant AE_MAXSTEP_I2CREG : std_logic_vector(15 downto 0) := x"310A";
constant AE_DAMPOFSET_I2CREG : std_logic_vector(15 downto 0) := x"310C";
constant AE_DAMPGAIN_I2CREG : std_logic_vector(15 downto 0) := x"310E";
constant AE_DAMPMAX_I2CREG : std_logic_vector(15 downto 0) := x"3110";
constant EMBEDDED_DATA_CTRL_I2CREG : std_logic_vector(15 downto 0) := x"3064";
constant PLL_MULTIPLIER_I2CREG : std_logic_vector(15 downto 0) := x"3030";
constant LINE_LENGHT_PCK_I2CREG : std_logic_vector(15 downto 0) := x"300C";
constant READ_MODE_I2CREG : std_logic_vector(15 downto 0) := x"3040";
constant DIG_BINNIGN_I2CREG : std_logic_vector(15 downto 0) := x"3032";
-- counter for power up timer and reset
signal p0_cnt1 : integer range 1 to 200000 := 1;
-- internal state of send_config_proc
type p1_sm is (w_init, wait_config, w_start, w_slave_addr_wr, w_ack1, w_reg_addr_msb, w_ack2, w_reg_addr_lsb, w_ack3, w_write_data_msb, w_ack4, w_write_data_lsb, w_ack5, w_stop, w_fin);
signal p1_state : p1_sm := w_init;
signal p1_tempo : integer range 1 to 20000000*4 := 1;
signal p1_cnt1 : integer range 0 to 8 := 0;
signal int_cnt_reg_write : integer range 0 to 10 := 0;
signal int_slave_addr_wr: std_logic_vector(7 downto 0) := MT9_I2C_SLAVE_ADDR;
-- array of value and adress to send via i2c
type reg_tab is array (0 to GEN_NUM_REG+1) of std_logic_vector(15 downto 0);
signal int_reg_start_addr: reg_tab := (others=>(others=>'0'));
signal int_reg_start_data: reg_tab := (others=>(others=>'0'));
signal mt9_conf_done : std_logic;
signal int_reset_n : std_logic;
signal timer_start : std_logic := '0';
begin
mt9_extclk_o <= mt9_extclk;
mt9_oe_n_o <= '0';
mt9_standby_o <= '0';
mt9_trigger_o <= '1';
mt9_saddr_o <= '0';
mt9_reset_n_o <= int_reset_n;
mt9_sclk_o <= mt9_sclk;
int_slave_addr_wr <= MT9_I2C_SLAVE_ADDR;
-- Reset register & i/o configuration
int_reg_start_addr(0) <= RESET_REGISTER_I2CREG; -- reset register
int_reg_start_data(0) <= x"01DC"; --
-- Y address start
int_reg_start_addr(1) <= Y_ADDR_START_I2CREG;
int_reg_start_data(1) <= ystart_i;
-- Y address end (reg_3006-reg_3002+1)
int_reg_start_addr(2) <= Y_ADDR_END_I2CREG;
int_reg_start_data(2) <= yend_i;
-- X address start
int_reg_start_addr(3) <= X_ADDR_START_I2CREG;
int_reg_start_data(3) <= xstart_i;
-- X address end (reg_3008-reg_3004+1)
int_reg_start_addr(4) <= X_ADDR_END_I2CREG;
int_reg_start_data(4) <= xend_i;
-- Coarse Integration Time = R0x3012 * RawTime. (RawTime = 50 µs)
int_reg_start_addr(5) <= COARSE_INTEGR_TIME_I2CREG;
int_reg_start_data(5) <= integtime_i; --x"00E6";
int_reg_start_addr(6) <= AE_CTRL_REG_I2CREG; -- Auto Exposure
WITH autoexp_i SELECT
int_reg_start_data(6) <= x"0000" WHEN '0',
x"0013" WHEN '1',
x"0000" WHEN OTHERS;
-- Autoexposure control: x"0000" disables AE,
-- x"0001" enables AE,
-- x"0003" enables AE + auto analog gain
-- x"0013" enables AE + auto_gain (digital & analog)
int_reg_start_addr(7) <= EMBEDDED_DATA_CTRL_I2CREG; -- Embedded data
int_reg_start_data(7) <= x"1802"; -- 1802: disabled embeded data
-- 1982: enabled embeded data (default)
int_reg_start_addr(8) <= PLL_MULTIPLIER_I2CREG; -- pll_multiplier
int_reg_start_data(8) <= x"002C"; -- multiplier set to 44
int_reg_start_addr(9) <= LINE_LENGHT_PCK_I2CREG; -- line lenght reg
int_reg_start_data(9) <= linelenght_i;
int_reg_start_addr(10) <= DIG_BINNIGN_I2CREG; -- binning
int_reg_start_data(10) <= "0000000000" & binning_i & "000" & binning_i & "0";
int_reg_start_addr(11) <= READ_MODE_I2CREG; -- mirror x and y
int_reg_start_data(11) <= flipvert_i & mirrorx_i & "00000000000000";
int_reg_start_addr(12) <= AE_TARGET_I2CREG; -- target AE
int_reg_start_data(12) <= autoexptarget_i;
int_reg_start_addr(13) <= AE_MINEX_I2CREG; -- min AE exposure value
int_reg_start_data(13) <= autoexpvmin_i;
int_reg_start_addr(14) <= AE_MAXEX_I2CREG; -- max AE exposure value
int_reg_start_data(14) <= autoexpvmax_i;
int_reg_start_addr(15) <= AE_MINSTEP_I2CREG; -- min AE step value
int_reg_start_data(15) <= autoexpstepmin_i;
int_reg_start_addr(16) <= AE_MAXSTEP_I2CREG; -- max AE step value
int_reg_start_data(16) <= autoexpstepmax_i;
int_reg_start_addr(17) <= AE_DAMPOFSET_I2CREG; -- Adjusts step size and settling speed
int_reg_start_data(17) <= autoexpdampofset_i;
int_reg_start_addr(18) <= AE_DAMPGAIN_I2CREG; -- Adjusts step size and settling speed
int_reg_start_data(18) <= autoexpdampgain_i;
int_reg_start_addr(19) <= AE_DAMPMAX_I2CREG; -- Max value allowed for recursiveDamp
int_reg_start_data(19) <= autoexpdampmax_i;
timer_start_proc : process(reset_n, mt9_extclk)
begin
if(reset_n = '0') then
p0_cnt1 <= 1;
timer_start <= '0';
elsif(rising_edge(mt9_extclk)) then
if( p0_cnt1 < 20000) then
int_reset_n <= '1';
timer_start <= '0';
p0_cnt1 <= p0_cnt1 + 1;
elsif(p0_cnt1 < 190000) then
p0_cnt1 <= p0_cnt1 + 1;
int_reset_n <= '0';
else
int_reset_n <= '1';
timer_start <= '1';
end if;
end if;
end process;
send_config_proc : process(reset_n, mt9_sclkdouble, timer_start)
begin
if(reset_n = '0' or timer_start = '0') then
p1_state <= w_init;
mt9_conf_done <= '0';
p1_tempo <= 1;
elsif(rising_edge(mt9_sclkdouble)) then
case p1_state is
when w_init =>
mt9_conf_done <= '0';
if(p1_tempo = 400000)then
p1_state <= wait_config;
else
p1_tempo <= p1_tempo + 1;
p1_state <= w_init;
end if;
when wait_config =>
mt9_sdata_io <= '1';
if(send_reconf_i = '1') then
p1_state <= w_start;
int_cnt_reg_write <= 0;
end if;
when w_start =>
if(mt9_sclk = '1')then
mt9_sdata_io <= '0';
p1_cnt1 <= 0;
p1_state <= w_slave_addr_wr;
end if;
when w_slave_addr_wr =>
if(mt9_sclk = '0')then
if( p1_cnt1 < 8 )then
mt9_sdata_io <= int_slave_addr_wr(7-p1_cnt1);
p1_cnt1 <= p1_cnt1 + 1;
p1_state <= w_slave_addr_wr;
else
mt9_sdata_io <= 'Z';
p1_state <= w_ack1;
end if;
end if;
when w_ack1 =>
p1_cnt1 <= 0;
mt9_sdata_io <= 'Z';
if(mt9_sclk = '1')then
p1_state <= w_reg_addr_msb;
end if;
when w_reg_addr_msb =>
if(mt9_sclk = '0')then
if( p1_cnt1 < 8 )then
mt9_sdata_io <= int_reg_start_addr(int_cnt_reg_write)(15-p1_cnt1);
p1_cnt1 <= p1_cnt1 + 1;
p1_state <= w_reg_addr_msb;
else
mt9_sdata_io <= 'Z';
p1_cnt1 <= 0;
p1_state <= w_ack2;
end if;
end if;
when w_ack2 =>
mt9_sdata_io <= 'Z';
if(mt9_sclk = '1')then
p1_state <= w_reg_addr_lsb;
end if;
when w_reg_addr_lsb =>
if(mt9_sclk = '0')then
if( p1_cnt1 < 8 )then
mt9_sdata_io <= int_reg_start_addr(int_cnt_reg_write)(7-p1_cnt1);
p1_cnt1 <= p1_cnt1 + 1;
p1_state <= w_reg_addr_lsb;
else
mt9_sdata_io <= 'Z';
p1_cnt1 <= 0;
p1_state <= w_ack3;
end if;
end if;
when w_ack3 =>
mt9_sdata_io <= 'Z';
if(mt9_sclk = '1')then
p1_state <= w_write_data_msb;
end if;
when w_write_data_msb =>
if(mt9_sclk = '0')then
if( p1_cnt1 < 8 )then
mt9_sdata_io <= int_reg_start_data(int_cnt_reg_write)(15-p1_cnt1);
p1_cnt1 <= p1_cnt1 + 1;
p1_state <= w_write_data_msb;
else
mt9_sdata_io <= 'Z';
p1_cnt1 <= 0;
p1_state <= w_ack4;
end if;
end if;
when w_ack4 =>
mt9_sdata_io <= 'Z';
if(mt9_sclk = '1')then
p1_state <= w_write_data_lsb;
end if;
when w_write_data_lsb =>
if(mt9_sclk = '0')then
if( p1_cnt1 < 8 )then
mt9_sdata_io <= int_reg_start_data(int_cnt_reg_write)(7-p1_cnt1);
p1_cnt1 <= p1_cnt1 + 1;
p1_state <= w_write_data_lsb;
else
mt9_sdata_io <= 'Z';
p1_cnt1 <= 0;
p1_state <= w_ack5;
end if;
end if;
when w_ack5 =>
mt9_sdata_io <= '0';
if(mt9_sclk = '1')then
p1_state <= w_stop;
end if;
when w_stop =>
if(mt9_sclk = '1')then
mt9_sdata_io<= '1';
p1_cnt1 <= 0;
p1_tempo <= 1;
if( int_cnt_reg_write = GEN_NUM_REG-1)then
p1_state <= w_fin;
else
int_cnt_reg_write <= int_cnt_reg_write+1;
p1_state <= w_start;
end if;
end if;
when w_fin =>
mt9_sdata_io <= '1';
mt9_conf_done <= '1';
p1_state <= wait_config;
when others =>
end case;
end if;
end process;
mt9_conf_done_o <= mt9_conf_done;
end rtl;
| gpl-3.0 | cd2704fed00756352daa8ca50be51e49 | 0.585848 | 2.453797 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system.vhd | 1 | 721,373 | -- tracking_camera_system.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.13.13:59:38
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tracking_camera_system is
port (
altpll_0_c0_clk : out std_logic; -- altpll_0_c0.clk
character_lcd_0_external_interface_DATA : inout std_logic_vector(7 downto 0) := (others => '0'); -- character_lcd_0_external_interface.DATA
character_lcd_0_external_interface_ON : out std_logic; -- .ON
character_lcd_0_external_interface_BLON : out std_logic; -- .BLON
character_lcd_0_external_interface_EN : out std_logic; -- .EN
character_lcd_0_external_interface_RS : out std_logic; -- .RS
character_lcd_0_external_interface_RW : out std_logic; -- .RW
switch_0_external_connection_export : in std_logic := '0'; -- switch_0_external_connection.export
servo_pwm_0_conduit_end_0_export : out std_logic; -- servo_pwm_0_conduit_end_0.export
reset_reset_n : in std_logic := '0'; -- reset.reset_n
switch_external_connection_export : in std_logic := '0'; -- switch_external_connection.export
clk_clk : in std_logic := '0'; -- clk.clk
sdram_0_wire_addr : out std_logic_vector(11 downto 0); -- sdram_0_wire.addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- .ba
sdram_0_wire_cas_n : out std_logic; -- .cas_n
sdram_0_wire_cke : out std_logic; -- .cke
sdram_0_wire_cs_n : out std_logic; -- .cs_n
sdram_0_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm
sdram_0_wire_ras_n : out std_logic; -- .ras_n
sdram_0_wire_we_n : out std_logic; -- .we_n
green_leds_external_connection_export : out std_logic_vector(7 downto 0); -- green_leds_external_connection.export
sram_0_external_interface_DQ : inout std_logic_vector(15 downto 0) := (others => '0'); -- sram_0_external_interface.DQ
sram_0_external_interface_ADDR : out std_logic_vector(17 downto 0); -- .ADDR
sram_0_external_interface_LB_N : out std_logic; -- .LB_N
sram_0_external_interface_UB_N : out std_logic; -- .UB_N
sram_0_external_interface_CE_N : out std_logic; -- .CE_N
sram_0_external_interface_OE_N : out std_logic; -- .OE_N
sram_0_external_interface_WE_N : out std_logic -- .WE_N
);
end entity tracking_camera_system;
architecture rtl of tracking_camera_system is
component tracking_camera_system_nios2_qsys_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
d_address : out std_logic_vector(24 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
d_readdatavalid : in std_logic := 'X'; -- readdatavalid
jtag_debug_module_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(24 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
i_readdatavalid : in std_logic := 'X'; -- readdatavalid
d_irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
jtag_debug_module_resetrequest : out std_logic; -- reset
jtag_debug_module_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
jtag_debug_module_begintransfer : in std_logic := 'X'; -- begintransfer
jtag_debug_module_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
jtag_debug_module_debugaccess : in std_logic := 'X'; -- debugaccess
jtag_debug_module_readdata : out std_logic_vector(31 downto 0); -- readdata
jtag_debug_module_select : in std_logic := 'X'; -- chipselect
jtag_debug_module_write : in std_logic := 'X'; -- write
jtag_debug_module_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
no_ci_readra : out std_logic -- readra
);
end component tracking_camera_system_nios2_qsys_0;
component tracking_camera_system_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(11 downto 0) := (others => 'X'); -- address
chipselect : in std_logic := 'X'; -- chipselect
clken : in std_logic := 'X'; -- clken
readdata : out std_logic_vector(31 downto 0); -- readdata
write : in std_logic := 'X'; -- write
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X' -- reset
);
end component tracking_camera_system_onchip_memory2_0;
component tracking_camera_system_sysid_qsys_0 is
port (
clock : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
readdata : out std_logic_vector(31 downto 0); -- readdata
address : in std_logic := 'X' -- address
);
end component tracking_camera_system_sysid_qsys_0;
component tracking_camera_system_timer_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
chipselect : in std_logic := 'X'; -- chipselect
write_n : in std_logic := 'X'; -- write_n
irq : out std_logic -- irq
);
end component tracking_camera_system_timer_0;
component tracking_camera_system_jtag_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
rst_n : in std_logic := 'X'; -- reset_n
av_chipselect : in std_logic := 'X'; -- chipselect
av_address : in std_logic := 'X'; -- address
av_read_n : in std_logic := 'X'; -- read_n
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_write_n : in std_logic := 'X'; -- write_n
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_waitrequest : out std_logic; -- waitrequest
av_irq : out std_logic -- irq
);
end component tracking_camera_system_jtag_uart_0;
component tracking_camera_system_character_lcd_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
address : in std_logic := 'X'; -- address
chipselect : in std_logic := 'X'; -- chipselect
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(7 downto 0); -- readdata
waitrequest : out std_logic; -- waitrequest
LCD_DATA : inout std_logic_vector(7 downto 0) := (others => 'X'); -- export
LCD_ON : out std_logic; -- export
LCD_BLON : out std_logic; -- export
LCD_EN : out std_logic; -- export
LCD_RS : out std_logic; -- export
LCD_RW : out std_logic -- export
);
end component tracking_camera_system_character_lcd_0;
component tracking_camera_system_green_leds is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
out_port : out std_logic_vector(7 downto 0) -- export
);
end component tracking_camera_system_green_leds;
component tracking_camera_system_switch is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic := 'X' -- export
);
end component tracking_camera_system_switch;
component tracking_camera_system_altpll_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
c0 : out std_logic; -- clk
c1 : out std_logic; -- clk
areset : in std_logic := 'X'; -- export
locked : out std_logic; -- export
phasedone : out std_logic -- export
);
end component tracking_camera_system_altpll_0;
component tracking_camera_system_sdram_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
az_addr : in std_logic_vector(21 downto 0) := (others => 'X'); -- address
az_be_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable_n
az_cs : in std_logic := 'X'; -- chipselect
az_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
az_rd_n : in std_logic := 'X'; -- read_n
az_wr_n : in std_logic := 'X'; -- write_n
za_data : out std_logic_vector(15 downto 0); -- readdata
za_valid : out std_logic; -- readdatavalid
za_waitrequest : out std_logic; -- waitrequest
zs_addr : out std_logic_vector(11 downto 0); -- export
zs_ba : out std_logic_vector(1 downto 0); -- export
zs_cas_n : out std_logic; -- export
zs_cke : out std_logic; -- export
zs_cs_n : out std_logic; -- export
zs_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
zs_dqm : out std_logic_vector(1 downto 0); -- export
zs_ras_n : out std_logic; -- export
zs_we_n : out std_logic -- export
);
end component tracking_camera_system_sdram_0;
component tracking_camera_system_sram_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
SRAM_DQ : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
SRAM_ADDR : out std_logic_vector(17 downto 0); -- export
SRAM_LB_N : out std_logic; -- export
SRAM_UB_N : out std_logic; -- export
SRAM_CE_N : out std_logic; -- export
SRAM_OE_N : out std_logic; -- export
SRAM_WE_N : out std_logic; -- export
address : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
readdatavalid : out std_logic -- readdatavalid
);
end component tracking_camera_system_sram_0;
component tracking_camera_system_servo_pwm_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
coe_servo : out std_logic; -- export
avs_s0_write_n : in std_logic := 'X'; -- write_n
avs_s0_writedata : in std_logic_vector(7 downto 0) := (others => 'X') -- writedata
);
end component tracking_camera_system_servo_pwm_0;
component tracking_camera_system_nios2_qsys_0_instruction_master_translator is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : out std_logic_vector(24 downto 0); -- address
uav_burstcount : out std_logic_vector(2 downto 0); -- burstcount
uav_read : out std_logic; -- read
uav_write : out std_logic; -- write
uav_waitrequest : in std_logic := 'X'; -- waitrequest
uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
uav_byteenable : out std_logic_vector(3 downto 0); -- byteenable
uav_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
uav_writedata : out std_logic_vector(31 downto 0); -- writedata
uav_lock : out std_logic; -- lock
uav_debugaccess : out std_logic; -- debugaccess
av_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
av_waitrequest : out std_logic; -- waitrequest
av_read : in std_logic := 'X'; -- read
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_readdatavalid : out std_logic -- readdatavalid
);
end component tracking_camera_system_nios2_qsys_0_instruction_master_translator;
component tracking_camera_system_nios2_qsys_0_data_master_translator is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : out std_logic_vector(24 downto 0); -- address
uav_burstcount : out std_logic_vector(2 downto 0); -- burstcount
uav_read : out std_logic; -- read
uav_write : out std_logic; -- write
uav_waitrequest : in std_logic := 'X'; -- waitrequest
uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
uav_byteenable : out std_logic_vector(3 downto 0); -- byteenable
uav_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
uav_writedata : out std_logic_vector(31 downto 0); -- writedata
uav_lock : out std_logic; -- lock
uav_debugaccess : out std_logic; -- debugaccess
av_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
av_waitrequest : out std_logic; -- waitrequest
av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
av_read : in std_logic := 'X'; -- read
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_readdatavalid : out std_logic; -- readdatavalid
av_write : in std_logic := 'X'; -- write
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_debugaccess : in std_logic := 'X' -- debugaccess
);
end component tracking_camera_system_nios2_qsys_0_data_master_translator;
component tracking_camera_system_nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
av_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
av_write : in std_logic := 'X'; -- write
av_read : in std_logic := 'X'; -- read
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_waitrequest : out std_logic; -- waitrequest
av_readdatavalid : out std_logic; -- readdatavalid
av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
av_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
av_debugaccess : in std_logic := 'X'; -- debugaccess
av_lock : in std_logic := 'X'; -- lock
cp_valid : out std_logic; -- valid
cp_data : out std_logic_vector(99 downto 0); -- data
cp_startofpacket : out std_logic; -- startofpacket
cp_endofpacket : out std_logic; -- endofpacket
cp_ready : in std_logic := 'X'; -- ready
rp_valid : in std_logic := 'X'; -- valid
rp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
rp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rp_startofpacket : in std_logic := 'X'; -- startofpacket
rp_endofpacket : in std_logic := 'X'; -- endofpacket
rp_ready : out std_logic -- ready
);
end component tracking_camera_system_nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent;
component tracking_camera_system_nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
av_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
av_write : in std_logic := 'X'; -- write
av_read : in std_logic := 'X'; -- read
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_waitrequest : out std_logic; -- waitrequest
av_readdatavalid : out std_logic; -- readdatavalid
av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
av_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
av_debugaccess : in std_logic := 'X'; -- debugaccess
av_lock : in std_logic := 'X'; -- lock
cp_valid : out std_logic; -- valid
cp_data : out std_logic_vector(99 downto 0); -- data
cp_startofpacket : out std_logic; -- startofpacket
cp_endofpacket : out std_logic; -- endofpacket
cp_ready : in std_logic := 'X'; -- ready
rp_valid : in std_logic := 'X'; -- valid
rp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
rp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rp_startofpacket : in std_logic := 'X'; -- startofpacket
rp_endofpacket : in std_logic := 'X'; -- endofpacket
rp_ready : out std_logic -- ready
);
end component tracking_camera_system_nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent;
component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(99 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(100 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo;
component tracking_camera_system_onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(99 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component tracking_camera_system_onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_sdram_0_s1_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(1 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(1 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(15 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(81 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(82 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(82 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(15 downto 0) -- data
);
end component tracking_camera_system_sdram_0_s1_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(82 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(82 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo;
component tracking_camera_system_sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(1 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(1 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(15 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(81 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(82 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(82 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(15 downto 0) -- data
);
end component tracking_camera_system_sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(82 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(82 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo;
component tracking_camera_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(99 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component tracking_camera_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
out_data : out std_logic_vector(31 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X' -- ready
);
end component tracking_camera_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo;
component tracking_camera_system_sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(99 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component tracking_camera_system_sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_timer_0_s1_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(99 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component tracking_camera_system_timer_0_s1_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(99 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic; -- burstcount
m0_byteenable : out std_logic; -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(7 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(72 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(73 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(73 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(7 downto 0) -- data
);
end component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(73 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(73 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo;
component tracking_camera_system_green_leds_s1_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(99 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component tracking_camera_system_green_leds_s1_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_switch_s1_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(99 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component tracking_camera_system_switch_s1_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_servo_pwm_0_s0_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic; -- burstcount
m0_byteenable : out std_logic; -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(7 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(72 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(73 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(73 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(7 downto 0) -- data
);
end component tracking_camera_system_servo_pwm_0_s0_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_switch_0_s1_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(99 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component tracking_camera_system_switch_0_s1_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_addr_router is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_addr_router;
component tracking_camera_system_addr_router_001 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_addr_router_001;
component tracking_camera_system_id_router is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_id_router;
component tracking_camera_system_id_router_002 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(81 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_id_router_002;
component tracking_camera_system_id_router_004 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_id_router_004;
component tracking_camera_system_id_router_008 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(72 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_id_router_008;
component tracking_camera_system_limiter is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
cmd_sink_ready : out std_logic; -- ready
cmd_sink_valid : in std_logic := 'X'; -- valid
cmd_sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cmd_sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
cmd_sink_startofpacket : in std_logic := 'X'; -- startofpacket
cmd_sink_endofpacket : in std_logic := 'X'; -- endofpacket
cmd_src_ready : in std_logic := 'X'; -- ready
cmd_src_data : out std_logic_vector(99 downto 0); -- data
cmd_src_channel : out std_logic_vector(12 downto 0); -- channel
cmd_src_startofpacket : out std_logic; -- startofpacket
cmd_src_endofpacket : out std_logic; -- endofpacket
rsp_sink_ready : out std_logic; -- ready
rsp_sink_valid : in std_logic := 'X'; -- valid
rsp_sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rsp_sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
rsp_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rsp_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rsp_src_ready : in std_logic := 'X'; -- ready
rsp_src_valid : out std_logic; -- valid
rsp_src_data : out std_logic_vector(99 downto 0); -- data
rsp_src_channel : out std_logic_vector(12 downto 0); -- channel
rsp_src_startofpacket : out std_logic; -- startofpacket
rsp_src_endofpacket : out std_logic; -- endofpacket
cmd_src_valid : out std_logic_vector(12 downto 0) -- data
);
end component tracking_camera_system_limiter;
component tracking_camera_system_burst_adapter is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink0_valid : in std_logic := 'X'; -- valid
sink0_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink0_ready : out std_logic; -- ready
source0_valid : out std_logic; -- valid
source0_data : out std_logic_vector(81 downto 0); -- data
source0_channel : out std_logic_vector(12 downto 0); -- channel
source0_startofpacket : out std_logic; -- startofpacket
source0_endofpacket : out std_logic; -- endofpacket
source0_ready : in std_logic := 'X' -- ready
);
end component tracking_camera_system_burst_adapter;
component tracking_camera_system_burst_adapter_002 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink0_valid : in std_logic := 'X'; -- valid
sink0_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink0_ready : out std_logic; -- ready
source0_valid : out std_logic; -- valid
source0_data : out std_logic_vector(72 downto 0); -- data
source0_channel : out std_logic_vector(12 downto 0); -- channel
source0_startofpacket : out std_logic; -- startofpacket
source0_endofpacket : out std_logic; -- endofpacket
source0_ready : in std_logic := 'X' -- ready
);
end component tracking_camera_system_burst_adapter_002;
component tracking_camera_system_rst_controller is
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic -- reset
);
end component tracking_camera_system_rst_controller;
component tracking_camera_system_cmd_xbar_demux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(12 downto 0) := (others => 'X'); -- data
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(99 downto 0); -- data
src0_channel : out std_logic_vector(12 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic; -- endofpacket
src1_ready : in std_logic := 'X'; -- ready
src1_valid : out std_logic; -- valid
src1_data : out std_logic_vector(99 downto 0); -- data
src1_channel : out std_logic_vector(12 downto 0); -- channel
src1_startofpacket : out std_logic; -- startofpacket
src1_endofpacket : out std_logic; -- endofpacket
src2_ready : in std_logic := 'X'; -- ready
src2_valid : out std_logic; -- valid
src2_data : out std_logic_vector(99 downto 0); -- data
src2_channel : out std_logic_vector(12 downto 0); -- channel
src2_startofpacket : out std_logic; -- startofpacket
src2_endofpacket : out std_logic; -- endofpacket
src3_ready : in std_logic := 'X'; -- ready
src3_valid : out std_logic; -- valid
src3_data : out std_logic_vector(99 downto 0); -- data
src3_channel : out std_logic_vector(12 downto 0); -- channel
src3_startofpacket : out std_logic; -- startofpacket
src3_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_cmd_xbar_demux;
component tracking_camera_system_cmd_xbar_demux_001 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(12 downto 0) := (others => 'X'); -- data
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(99 downto 0); -- data
src0_channel : out std_logic_vector(12 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic; -- endofpacket
src1_ready : in std_logic := 'X'; -- ready
src1_valid : out std_logic; -- valid
src1_data : out std_logic_vector(99 downto 0); -- data
src1_channel : out std_logic_vector(12 downto 0); -- channel
src1_startofpacket : out std_logic; -- startofpacket
src1_endofpacket : out std_logic; -- endofpacket
src2_ready : in std_logic := 'X'; -- ready
src2_valid : out std_logic; -- valid
src2_data : out std_logic_vector(99 downto 0); -- data
src2_channel : out std_logic_vector(12 downto 0); -- channel
src2_startofpacket : out std_logic; -- startofpacket
src2_endofpacket : out std_logic; -- endofpacket
src3_ready : in std_logic := 'X'; -- ready
src3_valid : out std_logic; -- valid
src3_data : out std_logic_vector(99 downto 0); -- data
src3_channel : out std_logic_vector(12 downto 0); -- channel
src3_startofpacket : out std_logic; -- startofpacket
src3_endofpacket : out std_logic; -- endofpacket
src4_ready : in std_logic := 'X'; -- ready
src4_valid : out std_logic; -- valid
src4_data : out std_logic_vector(99 downto 0); -- data
src4_channel : out std_logic_vector(12 downto 0); -- channel
src4_startofpacket : out std_logic; -- startofpacket
src4_endofpacket : out std_logic; -- endofpacket
src5_ready : in std_logic := 'X'; -- ready
src5_valid : out std_logic; -- valid
src5_data : out std_logic_vector(99 downto 0); -- data
src5_channel : out std_logic_vector(12 downto 0); -- channel
src5_startofpacket : out std_logic; -- startofpacket
src5_endofpacket : out std_logic; -- endofpacket
src6_ready : in std_logic := 'X'; -- ready
src6_valid : out std_logic; -- valid
src6_data : out std_logic_vector(99 downto 0); -- data
src6_channel : out std_logic_vector(12 downto 0); -- channel
src6_startofpacket : out std_logic; -- startofpacket
src6_endofpacket : out std_logic; -- endofpacket
src7_ready : in std_logic := 'X'; -- ready
src7_valid : out std_logic; -- valid
src7_data : out std_logic_vector(99 downto 0); -- data
src7_channel : out std_logic_vector(12 downto 0); -- channel
src7_startofpacket : out std_logic; -- startofpacket
src7_endofpacket : out std_logic; -- endofpacket
src8_ready : in std_logic := 'X'; -- ready
src8_valid : out std_logic; -- valid
src8_data : out std_logic_vector(99 downto 0); -- data
src8_channel : out std_logic_vector(12 downto 0); -- channel
src8_startofpacket : out std_logic; -- startofpacket
src8_endofpacket : out std_logic; -- endofpacket
src9_ready : in std_logic := 'X'; -- ready
src9_valid : out std_logic; -- valid
src9_data : out std_logic_vector(99 downto 0); -- data
src9_channel : out std_logic_vector(12 downto 0); -- channel
src9_startofpacket : out std_logic; -- startofpacket
src9_endofpacket : out std_logic; -- endofpacket
src10_ready : in std_logic := 'X'; -- ready
src10_valid : out std_logic; -- valid
src10_data : out std_logic_vector(99 downto 0); -- data
src10_channel : out std_logic_vector(12 downto 0); -- channel
src10_startofpacket : out std_logic; -- startofpacket
src10_endofpacket : out std_logic; -- endofpacket
src11_ready : in std_logic := 'X'; -- ready
src11_valid : out std_logic; -- valid
src11_data : out std_logic_vector(99 downto 0); -- data
src11_channel : out std_logic_vector(12 downto 0); -- channel
src11_startofpacket : out std_logic; -- startofpacket
src11_endofpacket : out std_logic; -- endofpacket
src12_ready : in std_logic := 'X'; -- ready
src12_valid : out std_logic; -- valid
src12_data : out std_logic_vector(99 downto 0); -- data
src12_channel : out std_logic_vector(12 downto 0); -- channel
src12_startofpacket : out std_logic; -- startofpacket
src12_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_cmd_xbar_demux_001;
component tracking_camera_system_cmd_xbar_mux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X' -- endofpacket
);
end component tracking_camera_system_cmd_xbar_mux;
component tracking_camera_system_rsp_xbar_demux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(99 downto 0); -- data
src0_channel : out std_logic_vector(12 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic; -- endofpacket
src1_ready : in std_logic := 'X'; -- ready
src1_valid : out std_logic; -- valid
src1_data : out std_logic_vector(99 downto 0); -- data
src1_channel : out std_logic_vector(12 downto 0); -- channel
src1_startofpacket : out std_logic; -- startofpacket
src1_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_rsp_xbar_demux;
component tracking_camera_system_rsp_xbar_demux_004 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(99 downto 0); -- data
src0_channel : out std_logic_vector(12 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_rsp_xbar_demux_004;
component tracking_camera_system_rsp_xbar_mux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X'; -- endofpacket
sink2_ready : out std_logic; -- ready
sink2_valid : in std_logic := 'X'; -- valid
sink2_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink2_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink2_startofpacket : in std_logic := 'X'; -- startofpacket
sink2_endofpacket : in std_logic := 'X'; -- endofpacket
sink3_ready : out std_logic; -- ready
sink3_valid : in std_logic := 'X'; -- valid
sink3_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink3_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink3_startofpacket : in std_logic := 'X'; -- startofpacket
sink3_endofpacket : in std_logic := 'X' -- endofpacket
);
end component tracking_camera_system_rsp_xbar_mux;
component tracking_camera_system_rsp_xbar_mux_001 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X'; -- endofpacket
sink2_ready : out std_logic; -- ready
sink2_valid : in std_logic := 'X'; -- valid
sink2_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink2_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink2_startofpacket : in std_logic := 'X'; -- startofpacket
sink2_endofpacket : in std_logic := 'X'; -- endofpacket
sink3_ready : out std_logic; -- ready
sink3_valid : in std_logic := 'X'; -- valid
sink3_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink3_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink3_startofpacket : in std_logic := 'X'; -- startofpacket
sink3_endofpacket : in std_logic := 'X'; -- endofpacket
sink4_ready : out std_logic; -- ready
sink4_valid : in std_logic := 'X'; -- valid
sink4_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink4_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink4_startofpacket : in std_logic := 'X'; -- startofpacket
sink4_endofpacket : in std_logic := 'X'; -- endofpacket
sink5_ready : out std_logic; -- ready
sink5_valid : in std_logic := 'X'; -- valid
sink5_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink5_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink5_startofpacket : in std_logic := 'X'; -- startofpacket
sink5_endofpacket : in std_logic := 'X'; -- endofpacket
sink6_ready : out std_logic; -- ready
sink6_valid : in std_logic := 'X'; -- valid
sink6_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink6_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink6_startofpacket : in std_logic := 'X'; -- startofpacket
sink6_endofpacket : in std_logic := 'X'; -- endofpacket
sink7_ready : out std_logic; -- ready
sink7_valid : in std_logic := 'X'; -- valid
sink7_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink7_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink7_startofpacket : in std_logic := 'X'; -- startofpacket
sink7_endofpacket : in std_logic := 'X'; -- endofpacket
sink8_ready : out std_logic; -- ready
sink8_valid : in std_logic := 'X'; -- valid
sink8_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink8_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink8_startofpacket : in std_logic := 'X'; -- startofpacket
sink8_endofpacket : in std_logic := 'X'; -- endofpacket
sink9_ready : out std_logic; -- ready
sink9_valid : in std_logic := 'X'; -- valid
sink9_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink9_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink9_startofpacket : in std_logic := 'X'; -- startofpacket
sink9_endofpacket : in std_logic := 'X'; -- endofpacket
sink10_ready : out std_logic; -- ready
sink10_valid : in std_logic := 'X'; -- valid
sink10_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink10_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink10_startofpacket : in std_logic := 'X'; -- startofpacket
sink10_endofpacket : in std_logic := 'X'; -- endofpacket
sink11_ready : out std_logic; -- ready
sink11_valid : in std_logic := 'X'; -- valid
sink11_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink11_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink11_startofpacket : in std_logic := 'X'; -- startofpacket
sink11_endofpacket : in std_logic := 'X'; -- endofpacket
sink12_ready : out std_logic; -- ready
sink12_valid : in std_logic := 'X'; -- valid
sink12_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink12_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink12_startofpacket : in std_logic := 'X'; -- startofpacket
sink12_endofpacket : in std_logic := 'X' -- endofpacket
);
end component tracking_camera_system_rsp_xbar_mux_001;
component tracking_camera_system_width_adapter is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(81 downto 0); -- data
out_channel : out std_logic_vector(12 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic -- startofpacket
);
end component tracking_camera_system_width_adapter;
component tracking_camera_system_width_adapter_001 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(99 downto 0); -- data
out_channel : out std_logic_vector(12 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic -- startofpacket
);
end component tracking_camera_system_width_adapter_001;
component tracking_camera_system_width_adapter_004 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(72 downto 0); -- data
out_channel : out std_logic_vector(12 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic -- startofpacket
);
end component tracking_camera_system_width_adapter_004;
component tracking_camera_system_width_adapter_005 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(99 downto 0); -- data
out_channel : out std_logic_vector(12 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic -- startofpacket
);
end component tracking_camera_system_width_adapter_005;
component tracking_camera_system_crosser is
port (
in_clk : in std_logic := 'X'; -- clk
in_reset : in std_logic := 'X'; -- reset
out_clk : in std_logic := 'X'; -- clk
out_reset : in std_logic := 'X'; -- reset
in_ready : out std_logic; -- ready
in_valid : in std_logic := 'X'; -- valid
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
out_ready : in std_logic := 'X'; -- ready
out_valid : out std_logic; -- valid
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
out_channel : out std_logic_vector(12 downto 0); -- channel
out_data : out std_logic_vector(99 downto 0) -- data
);
end component tracking_camera_system_crosser;
component tracking_camera_system_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
receiver1_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component tracking_camera_system_irq_mapper;
component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(8 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_chipselect : out std_logic; -- chipselect
av_debugaccess : out std_logic; -- debugaccess
av_read : out std_logic; -- read
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_outputenable : out std_logic -- outputenable
);
end component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator;
component tracking_camera_system_onchip_memory2_0_s1_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(11 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component tracking_camera_system_onchip_memory2_0_s1_translator;
component tracking_camera_system_sdram_0_s1_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(21 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_byteenable : out std_logic_vector(1 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_writebyteenable : out std_logic_vector(1 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component tracking_camera_system_sdram_0_s1_translator;
component tracking_camera_system_sram_0_avalon_sram_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(17 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_byteenable : out std_logic_vector(1 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(1 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component tracking_camera_system_sram_0_avalon_sram_slave_translator;
component tracking_camera_system_altpll_0_pll_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component tracking_camera_system_altpll_0_pll_slave_translator;
component tracking_camera_system_sysid_qsys_0_control_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(0 downto 0); -- address
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component tracking_camera_system_sysid_qsys_0_control_slave_translator;
component tracking_camera_system_timer_0_s1_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(2 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_chipselect : out std_logic; -- chipselect
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component tracking_camera_system_timer_0_s1_translator;
component tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(0 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator;
component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(7 downto 0); -- readdata
uav_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(0 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(7 downto 0); -- writedata
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator;
component tracking_camera_system_green_leds_s1_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_chipselect : out std_logic; -- chipselect
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component tracking_camera_system_green_leds_s1_translator;
signal altpll_0_c1_clk : std_logic; -- altpll_0:c1 -> [addr_router:clk, addr_router_001:clk, burst_adapter:clk, burst_adapter_001:clk, burst_adapter_002:clk, burst_adapter_003:clk, character_lcd_0:clk, character_lcd_0_avalon_lcd_slave_translator:clk, character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:clk, character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, cmd_xbar_demux:clk, cmd_xbar_demux_001:clk, cmd_xbar_mux:clk, cmd_xbar_mux_001:clk, cmd_xbar_mux_002:clk, cmd_xbar_mux_003:clk, crosser:in_clk, crosser_001:out_clk, green_leds:clk, green_leds_s1_translator:clk, green_leds_s1_translator_avalon_universal_slave_0_agent:clk, green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, id_router:clk, id_router_001:clk, id_router_002:clk, id_router_003:clk, id_router_005:clk, id_router_006:clk, id_router_007:clk, id_router_008:clk, id_router_009:clk, id_router_010:clk, id_router_011:clk, id_router_012:clk, irq_mapper:clk, jtag_uart_0:clk, jtag_uart_0_avalon_jtag_slave_translator:clk, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:clk, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, limiter:clk, limiter_001:clk, nios2_qsys_0:clk, nios2_qsys_0_data_master_translator:clk, nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:clk, nios2_qsys_0_instruction_master_translator:clk, nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:clk, nios2_qsys_0_jtag_debug_module_translator:clk, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:clk, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, onchip_memory2_0:clk, onchip_memory2_0_s1_translator:clk, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:clk, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, rsp_xbar_demux:clk, rsp_xbar_demux_001:clk, rsp_xbar_demux_002:clk, rsp_xbar_demux_003:clk, rsp_xbar_demux_005:clk, rsp_xbar_demux_006:clk, rsp_xbar_demux_007:clk, rsp_xbar_demux_008:clk, rsp_xbar_demux_009:clk, rsp_xbar_demux_010:clk, rsp_xbar_demux_011:clk, rsp_xbar_demux_012:clk, rsp_xbar_mux:clk, rsp_xbar_mux_001:clk, rst_controller:clk, sdram_0:clk, sdram_0_s1_translator:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, servo_pwm_0:clk, servo_pwm_0_s0_translator:clk, servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:clk, servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, sram_0:clk, sram_0_avalon_sram_slave_translator:clk, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:clk, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, switch:clk, switch_0:clk, switch_0_s1_translator:clk, switch_0_s1_translator_avalon_universal_slave_0_agent:clk, switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, switch_s1_translator:clk, switch_s1_translator_avalon_universal_slave_0_agent:clk, switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, sysid_qsys_0:clock, sysid_qsys_0_control_slave_translator:clk, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:clk, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, timer_0:clk, timer_0_s1_translator:clk, timer_0_s1_translator_avalon_universal_slave_0_agent:clk, timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, width_adapter:clk, width_adapter_001:clk, width_adapter_002:clk, width_adapter_003:clk, width_adapter_004:clk, width_adapter_005:clk, width_adapter_006:clk, width_adapter_007:clk]
signal nios2_qsys_0_instruction_master_waitrequest : std_logic; -- nios2_qsys_0_instruction_master_translator:av_waitrequest -> nios2_qsys_0:i_waitrequest
signal nios2_qsys_0_instruction_master_address : std_logic_vector(24 downto 0); -- nios2_qsys_0:i_address -> nios2_qsys_0_instruction_master_translator:av_address
signal nios2_qsys_0_instruction_master_read : std_logic; -- nios2_qsys_0:i_read -> nios2_qsys_0_instruction_master_translator:av_read
signal nios2_qsys_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_instruction_master_translator:av_readdata -> nios2_qsys_0:i_readdata
signal nios2_qsys_0_instruction_master_readdatavalid : std_logic; -- nios2_qsys_0_instruction_master_translator:av_readdatavalid -> nios2_qsys_0:i_readdatavalid
signal nios2_qsys_0_data_master_waitrequest : std_logic; -- nios2_qsys_0_data_master_translator:av_waitrequest -> nios2_qsys_0:d_waitrequest
signal nios2_qsys_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0:d_writedata -> nios2_qsys_0_data_master_translator:av_writedata
signal nios2_qsys_0_data_master_address : std_logic_vector(24 downto 0); -- nios2_qsys_0:d_address -> nios2_qsys_0_data_master_translator:av_address
signal nios2_qsys_0_data_master_write : std_logic; -- nios2_qsys_0:d_write -> nios2_qsys_0_data_master_translator:av_write
signal nios2_qsys_0_data_master_read : std_logic; -- nios2_qsys_0:d_read -> nios2_qsys_0_data_master_translator:av_read
signal nios2_qsys_0_data_master_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_data_master_translator:av_readdata -> nios2_qsys_0:d_readdata
signal nios2_qsys_0_data_master_debugaccess : std_logic; -- nios2_qsys_0:jtag_debug_module_debugaccess_to_roms -> nios2_qsys_0_data_master_translator:av_debugaccess
signal nios2_qsys_0_data_master_readdatavalid : std_logic; -- nios2_qsys_0_data_master_translator:av_readdatavalid -> nios2_qsys_0:d_readdatavalid
signal nios2_qsys_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0:d_byteenable -> nios2_qsys_0_data_master_translator:av_byteenable
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0_jtag_debug_module_translator:av_writedata -> nios2_qsys_0:jtag_debug_module_writedata
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address : std_logic_vector(8 downto 0); -- nios2_qsys_0_jtag_debug_module_translator:av_address -> nios2_qsys_0:jtag_debug_module_address
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_chipselect : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:av_chipselect -> nios2_qsys_0:jtag_debug_module_select
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:av_write -> nios2_qsys_0:jtag_debug_module_write
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0:jtag_debug_module_readdata -> nios2_qsys_0_jtag_debug_module_translator:av_readdata
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:av_begintransfer -> nios2_qsys_0:jtag_debug_module_begintransfer
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:av_debugaccess -> nios2_qsys_0:jtag_debug_module_debugaccess
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0_jtag_debug_module_translator:av_byteenable -> nios2_qsys_0:jtag_debug_module_byteenable
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- onchip_memory2_0_s1_translator:av_writedata -> onchip_memory2_0:writedata
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_address : std_logic_vector(11 downto 0); -- onchip_memory2_0_s1_translator:av_address -> onchip_memory2_0:address
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- onchip_memory2_0_s1_translator:av_chipselect -> onchip_memory2_0:chipselect
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken : std_logic; -- onchip_memory2_0_s1_translator:av_clken -> onchip_memory2_0:clken
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_write : std_logic; -- onchip_memory2_0_s1_translator:av_write -> onchip_memory2_0:write
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> onchip_memory2_0_s1_translator:av_readdata
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- onchip_memory2_0_s1_translator:av_byteenable -> onchip_memory2_0:byteenable
signal sdram_0_s1_translator_avalon_anti_slave_0_waitrequest : std_logic; -- sdram_0:za_waitrequest -> sdram_0_s1_translator:av_waitrequest
signal sdram_0_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(15 downto 0); -- sdram_0_s1_translator:av_writedata -> sdram_0:az_data
signal sdram_0_s1_translator_avalon_anti_slave_0_address : std_logic_vector(21 downto 0); -- sdram_0_s1_translator:av_address -> sdram_0:az_addr
signal sdram_0_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- sdram_0_s1_translator:av_chipselect -> sdram_0:az_cs
signal sdram_0_s1_translator_avalon_anti_slave_0_write : std_logic; -- sdram_0_s1_translator:av_write -> sdram_0_s1_translator_avalon_anti_slave_0_write:in
signal sdram_0_s1_translator_avalon_anti_slave_0_read : std_logic; -- sdram_0_s1_translator:av_read -> sdram_0_s1_translator_avalon_anti_slave_0_read:in
signal sdram_0_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(15 downto 0); -- sdram_0:za_data -> sdram_0_s1_translator:av_readdata
signal sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid : std_logic; -- sdram_0:za_valid -> sdram_0_s1_translator:av_readdatavalid
signal sdram_0_s1_translator_avalon_anti_slave_0_byteenable : std_logic_vector(1 downto 0); -- sdram_0_s1_translator:av_byteenable -> sdram_0_s1_translator_avalon_anti_slave_0_byteenable:in
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(15 downto 0); -- sram_0_avalon_sram_slave_translator:av_writedata -> sram_0:writedata
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address : std_logic_vector(17 downto 0); -- sram_0_avalon_sram_slave_translator:av_address -> sram_0:address
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write : std_logic; -- sram_0_avalon_sram_slave_translator:av_write -> sram_0:write
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read : std_logic; -- sram_0_avalon_sram_slave_translator:av_read -> sram_0:read
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(15 downto 0); -- sram_0:readdata -> sram_0_avalon_sram_slave_translator:av_readdata
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid : std_logic; -- sram_0:readdatavalid -> sram_0_avalon_sram_slave_translator:av_readdatavalid
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(1 downto 0); -- sram_0_avalon_sram_slave_translator:av_byteenable -> sram_0:byteenable
signal altpll_0_pll_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- altpll_0_pll_slave_translator:av_writedata -> altpll_0:writedata
signal altpll_0_pll_slave_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- altpll_0_pll_slave_translator:av_address -> altpll_0:address
signal altpll_0_pll_slave_translator_avalon_anti_slave_0_write : std_logic; -- altpll_0_pll_slave_translator:av_write -> altpll_0:write
signal altpll_0_pll_slave_translator_avalon_anti_slave_0_read : std_logic; -- altpll_0_pll_slave_translator:av_read -> altpll_0:read
signal altpll_0_pll_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- altpll_0:readdata -> altpll_0_pll_slave_translator:av_readdata
signal sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address : std_logic_vector(0 downto 0); -- sysid_qsys_0_control_slave_translator:av_address -> sysid_qsys_0:address
signal sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- sysid_qsys_0:readdata -> sysid_qsys_0_control_slave_translator:av_readdata
signal timer_0_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(15 downto 0); -- timer_0_s1_translator:av_writedata -> timer_0:writedata
signal timer_0_s1_translator_avalon_anti_slave_0_address : std_logic_vector(2 downto 0); -- timer_0_s1_translator:av_address -> timer_0:address
signal timer_0_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- timer_0_s1_translator:av_chipselect -> timer_0:chipselect
signal timer_0_s1_translator_avalon_anti_slave_0_write : std_logic; -- timer_0_s1_translator:av_write -> timer_0_s1_translator_avalon_anti_slave_0_write:in
signal timer_0_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(15 downto 0); -- timer_0:readdata -> timer_0_s1_translator:av_readdata
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest : std_logic; -- jtag_uart_0:av_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator:av_waitrequest
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator:av_writedata -> jtag_uart_0:av_writedata
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address : std_logic_vector(0 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator:av_address -> jtag_uart_0:av_address
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:av_chipselect -> jtag_uart_0:av_chipselect
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:av_write -> jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write:in
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:av_read -> jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read:in
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- jtag_uart_0:av_readdata -> jtag_uart_0_avalon_jtag_slave_translator:av_readdata
signal character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_waitrequest : std_logic; -- character_lcd_0:waitrequest -> character_lcd_0_avalon_lcd_slave_translator:av_waitrequest
signal character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(7 downto 0); -- character_lcd_0_avalon_lcd_slave_translator:av_writedata -> character_lcd_0:writedata
signal character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_address : std_logic_vector(0 downto 0); -- character_lcd_0_avalon_lcd_slave_translator:av_address -> character_lcd_0:address
signal character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_chipselect : std_logic; -- character_lcd_0_avalon_lcd_slave_translator:av_chipselect -> character_lcd_0:chipselect
signal character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_write : std_logic; -- character_lcd_0_avalon_lcd_slave_translator:av_write -> character_lcd_0:write
signal character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_read : std_logic; -- character_lcd_0_avalon_lcd_slave_translator:av_read -> character_lcd_0:read
signal character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(7 downto 0); -- character_lcd_0:readdata -> character_lcd_0_avalon_lcd_slave_translator:av_readdata
signal green_leds_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- green_leds_s1_translator:av_writedata -> green_leds:writedata
signal green_leds_s1_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- green_leds_s1_translator:av_address -> green_leds:address
signal green_leds_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- green_leds_s1_translator:av_chipselect -> green_leds:chipselect
signal green_leds_s1_translator_avalon_anti_slave_0_write : std_logic; -- green_leds_s1_translator:av_write -> green_leds_s1_translator_avalon_anti_slave_0_write:in
signal green_leds_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- green_leds:readdata -> green_leds_s1_translator:av_readdata
signal switch_s1_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- switch_s1_translator:av_address -> switch:address
signal switch_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- switch:readdata -> switch_s1_translator:av_readdata
signal servo_pwm_0_s0_translator_avalon_anti_slave_0_writedata : std_logic_vector(7 downto 0); -- servo_pwm_0_s0_translator:av_writedata -> servo_pwm_0:avs_s0_writedata
signal servo_pwm_0_s0_translator_avalon_anti_slave_0_write : std_logic; -- servo_pwm_0_s0_translator:av_write -> servo_pwm_0_s0_translator_avalon_anti_slave_0_write:in
signal switch_0_s1_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- switch_0_s1_translator:av_address -> switch_0:address
signal switch_0_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- switch_0:readdata -> switch_0_s1_translator:av_readdata
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_0_instruction_master_translator:uav_waitrequest
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(2 downto 0); -- nios2_qsys_0_instruction_master_translator:uav_burstcount -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0_instruction_master_translator:uav_writedata -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address : std_logic_vector(24 downto 0); -- nios2_qsys_0_instruction_master_translator:uav_address -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_address
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock : std_logic; -- nios2_qsys_0_instruction_master_translator:uav_lock -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_lock
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write : std_logic; -- nios2_qsys_0_instruction_master_translator:uav_write -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_write
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read : std_logic; -- nios2_qsys_0_instruction_master_translator:uav_read -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_read
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_0_instruction_master_translator:uav_readdata
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- nios2_qsys_0_instruction_master_translator:uav_debugaccess -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0_instruction_master_translator:uav_byteenable -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_0_instruction_master_translator:uav_readdatavalid
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_0_data_master_translator:uav_waitrequest
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(2 downto 0); -- nios2_qsys_0_data_master_translator:uav_burstcount -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_burstcount
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0_data_master_translator:uav_writedata -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_writedata
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_address : std_logic_vector(24 downto 0); -- nios2_qsys_0_data_master_translator:uav_address -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_address
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock : std_logic; -- nios2_qsys_0_data_master_translator:uav_lock -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_lock
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_write : std_logic; -- nios2_qsys_0_data_master_translator:uav_write -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_write
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_read : std_logic; -- nios2_qsys_0_data_master_translator:uav_read -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_read
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_0_data_master_translator:uav_readdata
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- nios2_qsys_0_data_master_translator:uav_debugaccess -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0_data_master_translator:uav_byteenable -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_byteenable
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_0_data_master_translator:uav_readdatavalid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:uav_waitrequest -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> nios2_qsys_0_jtag_debug_module_translator:uav_burstcount
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> nios2_qsys_0_jtag_debug_module_translator:uav_writedata
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> nios2_qsys_0_jtag_debug_module_translator:uav_address
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> nios2_qsys_0_jtag_debug_module_translator:uav_write
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> nios2_qsys_0_jtag_debug_module_translator:uav_lock
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> nios2_qsys_0_jtag_debug_module_translator:uav_read
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_jtag_debug_module_translator:uav_readdata -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:uav_readdatavalid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> nios2_qsys_0_jtag_debug_module_translator:uav_debugaccess
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> nios2_qsys_0_jtag_debug_module_translator:uav_byteenable
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- sdram_0_s1_translator:uav_waitrequest -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(1 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sdram_0_s1_translator:uav_burstcount
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(15 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sdram_0_s1_translator:uav_writedata
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> sdram_0_s1_translator:uav_address
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> sdram_0_s1_translator:uav_write
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sdram_0_s1_translator:uav_lock
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> sdram_0_s1_translator:uav_read
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(15 downto 0); -- sdram_0_s1_translator:uav_readdata -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- sdram_0_s1_translator:uav_readdatavalid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sdram_0_s1_translator:uav_debugaccess
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(1 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sdram_0_s1_translator:uav_byteenable
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(82 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(82 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(15 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- sram_0_avalon_sram_slave_translator:uav_waitrequest -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(1 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sram_0_avalon_sram_slave_translator:uav_burstcount
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(15 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sram_0_avalon_sram_slave_translator:uav_writedata
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_address -> sram_0_avalon_sram_slave_translator:uav_address
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_write -> sram_0_avalon_sram_slave_translator:uav_write
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sram_0_avalon_sram_slave_translator:uav_lock
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_read -> sram_0_avalon_sram_slave_translator:uav_read
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(15 downto 0); -- sram_0_avalon_sram_slave_translator:uav_readdata -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- sram_0_avalon_sram_slave_translator:uav_readdatavalid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sram_0_avalon_sram_slave_translator:uav_debugaccess
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(1 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sram_0_avalon_sram_slave_translator:uav_byteenable
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(82 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(82 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(15 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- altpll_0_pll_slave_translator:uav_waitrequest -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> altpll_0_pll_slave_translator:uav_burstcount
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> altpll_0_pll_slave_translator:uav_writedata
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_address -> altpll_0_pll_slave_translator:uav_address
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_write -> altpll_0_pll_slave_translator:uav_write
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_lock -> altpll_0_pll_slave_translator:uav_lock
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_read -> altpll_0_pll_slave_translator:uav_read
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- altpll_0_pll_slave_translator:uav_readdata -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- altpll_0_pll_slave_translator:uav_readdatavalid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> altpll_0_pll_slave_translator:uav_debugaccess
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> altpll_0_pll_slave_translator:uav_byteenable
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data : std_logic_vector(31 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- sysid_qsys_0_control_slave_translator:uav_waitrequest -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sysid_qsys_0_control_slave_translator:uav_burstcount
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sysid_qsys_0_control_slave_translator:uav_writedata
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> sysid_qsys_0_control_slave_translator:uav_address
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> sysid_qsys_0_control_slave_translator:uav_write
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sysid_qsys_0_control_slave_translator:uav_lock
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> sysid_qsys_0_control_slave_translator:uav_read
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- sysid_qsys_0_control_slave_translator:uav_readdata -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- sysid_qsys_0_control_slave_translator:uav_readdatavalid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sysid_qsys_0_control_slave_translator:uav_debugaccess
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sysid_qsys_0_control_slave_translator:uav_byteenable
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- timer_0_s1_translator:uav_waitrequest -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> timer_0_s1_translator:uav_burstcount
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> timer_0_s1_translator:uav_writedata
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> timer_0_s1_translator:uav_address
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> timer_0_s1_translator:uav_write
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> timer_0_s1_translator:uav_lock
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> timer_0_s1_translator:uav_read
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- timer_0_s1_translator:uav_readdata -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- timer_0_s1_translator:uav_readdatavalid -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> timer_0_s1_translator:uav_debugaccess
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> timer_0_s1_translator:uav_byteenable
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_0_avalon_jtag_slave_translator:uav_burstcount
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_0_avalon_jtag_slave_translator:uav_writedata
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_0_avalon_jtag_slave_translator:uav_address
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_0_avalon_jtag_slave_translator:uav_write
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_0_avalon_jtag_slave_translator:uav_lock
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_0_avalon_jtag_slave_translator:uav_read
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_0_avalon_jtag_slave_translator:uav_debugaccess
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_0_avalon_jtag_slave_translator:uav_byteenable
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- character_lcd_0_avalon_lcd_slave_translator:uav_waitrequest -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> character_lcd_0_avalon_lcd_slave_translator:uav_burstcount
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(7 downto 0); -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> character_lcd_0_avalon_lcd_slave_translator:uav_writedata
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_address -> character_lcd_0_avalon_lcd_slave_translator:uav_address
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_write -> character_lcd_0_avalon_lcd_slave_translator:uav_write
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_lock -> character_lcd_0_avalon_lcd_slave_translator:uav_lock
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_read -> character_lcd_0_avalon_lcd_slave_translator:uav_read
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(7 downto 0); -- character_lcd_0_avalon_lcd_slave_translator:uav_readdata -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- character_lcd_0_avalon_lcd_slave_translator:uav_readdatavalid -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> character_lcd_0_avalon_lcd_slave_translator:uav_debugaccess
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> character_lcd_0_avalon_lcd_slave_translator:uav_byteenable
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(73 downto 0); -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(73 downto 0); -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(7 downto 0); -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- green_leds_s1_translator:uav_waitrequest -> green_leds_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> green_leds_s1_translator:uav_burstcount
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> green_leds_s1_translator:uav_writedata
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_address -> green_leds_s1_translator:uav_address
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_write -> green_leds_s1_translator:uav_write
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_lock -> green_leds_s1_translator:uav_lock
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_read -> green_leds_s1_translator:uav_read
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- green_leds_s1_translator:uav_readdata -> green_leds_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- green_leds_s1_translator:uav_readdatavalid -> green_leds_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> green_leds_s1_translator:uav_debugaccess
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> green_leds_s1_translator:uav_byteenable
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- switch_s1_translator:uav_waitrequest -> switch_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- switch_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> switch_s1_translator:uav_burstcount
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- switch_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> switch_s1_translator:uav_writedata
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- switch_s1_translator_avalon_universal_slave_0_agent:m0_address -> switch_s1_translator:uav_address
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:m0_write -> switch_s1_translator:uav_write
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:m0_lock -> switch_s1_translator:uav_lock
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:m0_read -> switch_s1_translator:uav_read
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- switch_s1_translator:uav_readdata -> switch_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- switch_s1_translator:uav_readdatavalid -> switch_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> switch_s1_translator:uav_debugaccess
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- switch_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> switch_s1_translator:uav_byteenable
signal switch_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal switch_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal switch_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal switch_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- switch_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal switch_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> switch_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> switch_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> switch_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> switch_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> switch_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> switch_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- switch_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> switch_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> switch_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- servo_pwm_0_s0_translator:uav_waitrequest -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_burstcount -> servo_pwm_0_s0_translator:uav_burstcount
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(7 downto 0); -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_writedata -> servo_pwm_0_s0_translator:uav_writedata
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_address -> servo_pwm_0_s0_translator:uav_address
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_write -> servo_pwm_0_s0_translator:uav_write
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_lock -> servo_pwm_0_s0_translator:uav_lock
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_read -> servo_pwm_0_s0_translator:uav_read
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(7 downto 0); -- servo_pwm_0_s0_translator:uav_readdata -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_readdata
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- servo_pwm_0_s0_translator:uav_readdatavalid -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> servo_pwm_0_s0_translator:uav_debugaccess
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_byteenable -> servo_pwm_0_s0_translator:uav_byteenable
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_source_valid -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(73 downto 0); -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_source_data -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_source_ready
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(73 downto 0); -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_data
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(7 downto 0); -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- switch_0_s1_translator:uav_waitrequest -> switch_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- switch_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> switch_0_s1_translator:uav_burstcount
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- switch_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> switch_0_s1_translator:uav_writedata
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- switch_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> switch_0_s1_translator:uav_address
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> switch_0_s1_translator:uav_write
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> switch_0_s1_translator:uav_lock
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> switch_0_s1_translator:uav_read
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- switch_0_s1_translator:uav_readdata -> switch_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- switch_0_s1_translator:uav_readdatavalid -> switch_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> switch_0_s1_translator:uav_debugaccess
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- switch_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> switch_0_s1_translator:uav_byteenable
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- switch_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> switch_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> switch_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> switch_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> switch_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> switch_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> switch_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- switch_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> switch_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> switch_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(99 downto 0); -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router:sink_ready -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(99 downto 0); -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router_001:sink_ready -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_ready
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router:sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_001:sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(81 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_002:sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(81 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_003:sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_004:sink_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_005:sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_006:sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_007:sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(72 downto 0); -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_008:sink_ready -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_009:sink_endofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_009:sink_valid
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_009:sink_startofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_009:sink_data
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_009:sink_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal switch_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_010:sink_endofpacket
signal switch_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_010:sink_valid
signal switch_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_010:sink_startofpacket
signal switch_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- switch_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_010:sink_data
signal switch_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_010:sink_ready -> switch_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_011:sink_endofpacket
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_011:sink_valid
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_011:sink_startofpacket
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(72 downto 0); -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_011:sink_data
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_011:sink_ready -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rp_ready
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_012:sink_endofpacket
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_012:sink_valid
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_012:sink_startofpacket
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- switch_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_012:sink_data
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_012:sink_ready -> switch_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal addr_router_src_endofpacket : std_logic; -- addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket
signal addr_router_src_valid : std_logic; -- addr_router:src_valid -> limiter:cmd_sink_valid
signal addr_router_src_startofpacket : std_logic; -- addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket
signal addr_router_src_data : std_logic_vector(99 downto 0); -- addr_router:src_data -> limiter:cmd_sink_data
signal addr_router_src_channel : std_logic_vector(12 downto 0); -- addr_router:src_channel -> limiter:cmd_sink_channel
signal addr_router_src_ready : std_logic; -- limiter:cmd_sink_ready -> addr_router:src_ready
signal limiter_rsp_src_endofpacket : std_logic; -- limiter:rsp_src_endofpacket -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
signal limiter_rsp_src_valid : std_logic; -- limiter:rsp_src_valid -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
signal limiter_rsp_src_startofpacket : std_logic; -- limiter:rsp_src_startofpacket -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
signal limiter_rsp_src_data : std_logic_vector(99 downto 0); -- limiter:rsp_src_data -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_data
signal limiter_rsp_src_channel : std_logic_vector(12 downto 0); -- limiter:rsp_src_channel -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
signal limiter_rsp_src_ready : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready
signal addr_router_001_src_endofpacket : std_logic; -- addr_router_001:src_endofpacket -> limiter_001:cmd_sink_endofpacket
signal addr_router_001_src_valid : std_logic; -- addr_router_001:src_valid -> limiter_001:cmd_sink_valid
signal addr_router_001_src_startofpacket : std_logic; -- addr_router_001:src_startofpacket -> limiter_001:cmd_sink_startofpacket
signal addr_router_001_src_data : std_logic_vector(99 downto 0); -- addr_router_001:src_data -> limiter_001:cmd_sink_data
signal addr_router_001_src_channel : std_logic_vector(12 downto 0); -- addr_router_001:src_channel -> limiter_001:cmd_sink_channel
signal addr_router_001_src_ready : std_logic; -- limiter_001:cmd_sink_ready -> addr_router_001:src_ready
signal limiter_001_rsp_src_endofpacket : std_logic; -- limiter_001:rsp_src_endofpacket -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
signal limiter_001_rsp_src_valid : std_logic; -- limiter_001:rsp_src_valid -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_valid
signal limiter_001_rsp_src_startofpacket : std_logic; -- limiter_001:rsp_src_startofpacket -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
signal limiter_001_rsp_src_data : std_logic_vector(99 downto 0); -- limiter_001:rsp_src_data -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_data
signal limiter_001_rsp_src_channel : std_logic_vector(12 downto 0); -- limiter_001:rsp_src_channel -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_channel
signal limiter_001_rsp_src_ready : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter_001:rsp_src_ready
signal burst_adapter_source0_endofpacket : std_logic; -- burst_adapter:source0_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal burst_adapter_source0_valid : std_logic; -- burst_adapter:source0_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal burst_adapter_source0_startofpacket : std_logic; -- burst_adapter:source0_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal burst_adapter_source0_data : std_logic_vector(81 downto 0); -- burst_adapter:source0_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_data
signal burst_adapter_source0_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
signal burst_adapter_source0_channel : std_logic_vector(12 downto 0); -- burst_adapter:source0_channel -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal burst_adapter_001_source0_endofpacket : std_logic; -- burst_adapter_001:source0_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal burst_adapter_001_source0_valid : std_logic; -- burst_adapter_001:source0_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal burst_adapter_001_source0_startofpacket : std_logic; -- burst_adapter_001:source0_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal burst_adapter_001_source0_data : std_logic_vector(81 downto 0); -- burst_adapter_001:source0_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_data
signal burst_adapter_001_source0_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter_001:source0_ready
signal burst_adapter_001_source0_channel : std_logic_vector(12 downto 0); -- burst_adapter_001:source0_channel -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal burst_adapter_002_source0_endofpacket : std_logic; -- burst_adapter_002:source0_endofpacket -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal burst_adapter_002_source0_valid : std_logic; -- burst_adapter_002:source0_valid -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal burst_adapter_002_source0_startofpacket : std_logic; -- burst_adapter_002:source0_startofpacket -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal burst_adapter_002_source0_data : std_logic_vector(72 downto 0); -- burst_adapter_002:source0_data -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:cp_data
signal burst_adapter_002_source0_ready : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter_002:source0_ready
signal burst_adapter_002_source0_channel : std_logic_vector(12 downto 0); -- burst_adapter_002:source0_channel -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal burst_adapter_003_source0_endofpacket : std_logic; -- burst_adapter_003:source0_endofpacket -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal burst_adapter_003_source0_valid : std_logic; -- burst_adapter_003:source0_valid -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:cp_valid
signal burst_adapter_003_source0_startofpacket : std_logic; -- burst_adapter_003:source0_startofpacket -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal burst_adapter_003_source0_data : std_logic_vector(72 downto 0); -- burst_adapter_003:source0_data -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:cp_data
signal burst_adapter_003_source0_ready : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter_003:source0_ready
signal burst_adapter_003_source0_channel : std_logic_vector(12 downto 0); -- burst_adapter_003:source0_channel -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:cp_channel
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [addr_router:reset, addr_router_001:reset, burst_adapter:reset, burst_adapter_001:reset, burst_adapter_002:reset, burst_adapter_003:reset, character_lcd_0:reset, character_lcd_0_avalon_lcd_slave_translator:reset, character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:reset, character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, cmd_xbar_mux_002:reset, cmd_xbar_mux_003:reset, crosser:in_reset, crosser_001:out_reset, green_leds_s1_translator:reset, green_leds_s1_translator_avalon_universal_slave_0_agent:reset, green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, id_router_009:reset, id_router_010:reset, id_router_011:reset, id_router_012:reset, irq_mapper:reset, jtag_uart_0_avalon_jtag_slave_translator:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, limiter:reset, limiter_001:reset, nios2_qsys_0_data_master_translator:reset, nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_0_instruction_master_translator:reset, nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_0_jtag_debug_module_translator:reset, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory2_0:reset, onchip_memory2_0_s1_translator:reset, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_demux_009:reset, rsp_xbar_demux_010:reset, rsp_xbar_demux_011:reset, rsp_xbar_demux_012:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, rst_controller_reset_out_reset:in, sdram_0_s1_translator:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, servo_pwm_0_s0_translator:reset, servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:reset, servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sram_0:reset, sram_0_avalon_sram_slave_translator:reset, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:reset, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, switch_0_s1_translator:reset, switch_0_s1_translator_avalon_universal_slave_0_agent:reset, switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, switch_s1_translator:reset, switch_s1_translator_avalon_universal_slave_0_agent:reset, switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sysid_qsys_0_control_slave_translator:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, timer_0_s1_translator:reset, timer_0_s1_translator_avalon_universal_slave_0_agent:reset, timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, width_adapter:reset, width_adapter_001:reset, width_adapter_002:reset, width_adapter_003:reset, width_adapter_004:reset, width_adapter_005:reset, width_adapter_006:reset, width_adapter_007:reset]
signal nios2_qsys_0_jtag_debug_module_reset_reset : std_logic; -- nios2_qsys_0:jtag_debug_module_resetrequest -> [rst_controller:reset_in1, rst_controller_001:reset_in1]
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [altpll_0:reset, altpll_0_pll_slave_translator:reset, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:reset, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, crosser:out_reset, crosser_001:in_reset, id_router_004:reset, rsp_xbar_demux_004:reset]
signal cmd_xbar_demux_src0_endofpacket : std_logic; -- cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
signal cmd_xbar_demux_src0_valid : std_logic; -- cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
signal cmd_xbar_demux_src0_startofpacket : std_logic; -- cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
signal cmd_xbar_demux_src0_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
signal cmd_xbar_demux_src0_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
signal cmd_xbar_demux_src0_ready : std_logic; -- cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
signal cmd_xbar_demux_src1_endofpacket : std_logic; -- cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
signal cmd_xbar_demux_src1_valid : std_logic; -- cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid
signal cmd_xbar_demux_src1_startofpacket : std_logic; -- cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
signal cmd_xbar_demux_src1_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data
signal cmd_xbar_demux_src1_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel
signal cmd_xbar_demux_src1_ready : std_logic; -- cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready
signal cmd_xbar_demux_src2_endofpacket : std_logic; -- cmd_xbar_demux:src2_endofpacket -> cmd_xbar_mux_002:sink0_endofpacket
signal cmd_xbar_demux_src2_valid : std_logic; -- cmd_xbar_demux:src2_valid -> cmd_xbar_mux_002:sink0_valid
signal cmd_xbar_demux_src2_startofpacket : std_logic; -- cmd_xbar_demux:src2_startofpacket -> cmd_xbar_mux_002:sink0_startofpacket
signal cmd_xbar_demux_src2_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src2_data -> cmd_xbar_mux_002:sink0_data
signal cmd_xbar_demux_src2_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src2_channel -> cmd_xbar_mux_002:sink0_channel
signal cmd_xbar_demux_src2_ready : std_logic; -- cmd_xbar_mux_002:sink0_ready -> cmd_xbar_demux:src2_ready
signal cmd_xbar_demux_src3_endofpacket : std_logic; -- cmd_xbar_demux:src3_endofpacket -> cmd_xbar_mux_003:sink0_endofpacket
signal cmd_xbar_demux_src3_valid : std_logic; -- cmd_xbar_demux:src3_valid -> cmd_xbar_mux_003:sink0_valid
signal cmd_xbar_demux_src3_startofpacket : std_logic; -- cmd_xbar_demux:src3_startofpacket -> cmd_xbar_mux_003:sink0_startofpacket
signal cmd_xbar_demux_src3_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src3_data -> cmd_xbar_mux_003:sink0_data
signal cmd_xbar_demux_src3_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src3_channel -> cmd_xbar_mux_003:sink0_channel
signal cmd_xbar_demux_src3_ready : std_logic; -- cmd_xbar_mux_003:sink0_ready -> cmd_xbar_demux:src3_ready
signal cmd_xbar_demux_001_src0_endofpacket : std_logic; -- cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
signal cmd_xbar_demux_001_src0_valid : std_logic; -- cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
signal cmd_xbar_demux_001_src0_startofpacket : std_logic; -- cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
signal cmd_xbar_demux_001_src0_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
signal cmd_xbar_demux_001_src0_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
signal cmd_xbar_demux_001_src0_ready : std_logic; -- cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
signal cmd_xbar_demux_001_src1_endofpacket : std_logic; -- cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
signal cmd_xbar_demux_001_src1_valid : std_logic; -- cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid
signal cmd_xbar_demux_001_src1_startofpacket : std_logic; -- cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
signal cmd_xbar_demux_001_src1_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data
signal cmd_xbar_demux_001_src1_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel
signal cmd_xbar_demux_001_src1_ready : std_logic; -- cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready
signal cmd_xbar_demux_001_src2_endofpacket : std_logic; -- cmd_xbar_demux_001:src2_endofpacket -> cmd_xbar_mux_002:sink1_endofpacket
signal cmd_xbar_demux_001_src2_valid : std_logic; -- cmd_xbar_demux_001:src2_valid -> cmd_xbar_mux_002:sink1_valid
signal cmd_xbar_demux_001_src2_startofpacket : std_logic; -- cmd_xbar_demux_001:src2_startofpacket -> cmd_xbar_mux_002:sink1_startofpacket
signal cmd_xbar_demux_001_src2_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src2_data -> cmd_xbar_mux_002:sink1_data
signal cmd_xbar_demux_001_src2_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src2_channel -> cmd_xbar_mux_002:sink1_channel
signal cmd_xbar_demux_001_src2_ready : std_logic; -- cmd_xbar_mux_002:sink1_ready -> cmd_xbar_demux_001:src2_ready
signal cmd_xbar_demux_001_src3_endofpacket : std_logic; -- cmd_xbar_demux_001:src3_endofpacket -> cmd_xbar_mux_003:sink1_endofpacket
signal cmd_xbar_demux_001_src3_valid : std_logic; -- cmd_xbar_demux_001:src3_valid -> cmd_xbar_mux_003:sink1_valid
signal cmd_xbar_demux_001_src3_startofpacket : std_logic; -- cmd_xbar_demux_001:src3_startofpacket -> cmd_xbar_mux_003:sink1_startofpacket
signal cmd_xbar_demux_001_src3_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src3_data -> cmd_xbar_mux_003:sink1_data
signal cmd_xbar_demux_001_src3_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src3_channel -> cmd_xbar_mux_003:sink1_channel
signal cmd_xbar_demux_001_src3_ready : std_logic; -- cmd_xbar_mux_003:sink1_ready -> cmd_xbar_demux_001:src3_ready
signal cmd_xbar_demux_001_src5_endofpacket : std_logic; -- cmd_xbar_demux_001:src5_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src5_valid : std_logic; -- cmd_xbar_demux_001:src5_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src5_startofpacket : std_logic; -- cmd_xbar_demux_001:src5_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src5_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src5_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src5_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src5_channel -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src6_endofpacket : std_logic; -- cmd_xbar_demux_001:src6_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src6_valid : std_logic; -- cmd_xbar_demux_001:src6_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src6_startofpacket : std_logic; -- cmd_xbar_demux_001:src6_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src6_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src6_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src6_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src6_channel -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src7_endofpacket : std_logic; -- cmd_xbar_demux_001:src7_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src7_valid : std_logic; -- cmd_xbar_demux_001:src7_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src7_startofpacket : std_logic; -- cmd_xbar_demux_001:src7_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src7_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src7_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src7_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src7_channel -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src8_endofpacket : std_logic; -- cmd_xbar_demux_001:src8_endofpacket -> width_adapter_004:in_endofpacket
signal cmd_xbar_demux_001_src8_valid : std_logic; -- cmd_xbar_demux_001:src8_valid -> width_adapter_004:in_valid
signal cmd_xbar_demux_001_src8_startofpacket : std_logic; -- cmd_xbar_demux_001:src8_startofpacket -> width_adapter_004:in_startofpacket
signal cmd_xbar_demux_001_src8_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src8_data -> width_adapter_004:in_data
signal cmd_xbar_demux_001_src8_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src8_channel -> width_adapter_004:in_channel
signal cmd_xbar_demux_001_src9_endofpacket : std_logic; -- cmd_xbar_demux_001:src9_endofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src9_valid : std_logic; -- cmd_xbar_demux_001:src9_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src9_startofpacket : std_logic; -- cmd_xbar_demux_001:src9_startofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src9_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src9_data -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src9_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src9_channel -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src10_endofpacket : std_logic; -- cmd_xbar_demux_001:src10_endofpacket -> switch_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src10_valid : std_logic; -- cmd_xbar_demux_001:src10_valid -> switch_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src10_startofpacket : std_logic; -- cmd_xbar_demux_001:src10_startofpacket -> switch_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src10_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src10_data -> switch_s1_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src10_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src10_channel -> switch_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src11_endofpacket : std_logic; -- cmd_xbar_demux_001:src11_endofpacket -> width_adapter_006:in_endofpacket
signal cmd_xbar_demux_001_src11_valid : std_logic; -- cmd_xbar_demux_001:src11_valid -> width_adapter_006:in_valid
signal cmd_xbar_demux_001_src11_startofpacket : std_logic; -- cmd_xbar_demux_001:src11_startofpacket -> width_adapter_006:in_startofpacket
signal cmd_xbar_demux_001_src11_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src11_data -> width_adapter_006:in_data
signal cmd_xbar_demux_001_src11_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src11_channel -> width_adapter_006:in_channel
signal cmd_xbar_demux_001_src12_endofpacket : std_logic; -- cmd_xbar_demux_001:src12_endofpacket -> switch_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src12_valid : std_logic; -- cmd_xbar_demux_001:src12_valid -> switch_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src12_startofpacket : std_logic; -- cmd_xbar_demux_001:src12_startofpacket -> switch_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src12_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src12_data -> switch_0_s1_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src12_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src12_channel -> switch_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal rsp_xbar_demux_src0_endofpacket : std_logic; -- rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
signal rsp_xbar_demux_src0_valid : std_logic; -- rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
signal rsp_xbar_demux_src0_startofpacket : std_logic; -- rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
signal rsp_xbar_demux_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
signal rsp_xbar_demux_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
signal rsp_xbar_demux_src0_ready : std_logic; -- rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
signal rsp_xbar_demux_src1_endofpacket : std_logic; -- rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
signal rsp_xbar_demux_src1_valid : std_logic; -- rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
signal rsp_xbar_demux_src1_startofpacket : std_logic; -- rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
signal rsp_xbar_demux_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
signal rsp_xbar_demux_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
signal rsp_xbar_demux_src1_ready : std_logic; -- rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
signal rsp_xbar_demux_001_src0_endofpacket : std_logic; -- rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
signal rsp_xbar_demux_001_src0_valid : std_logic; -- rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
signal rsp_xbar_demux_001_src0_startofpacket : std_logic; -- rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
signal rsp_xbar_demux_001_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
signal rsp_xbar_demux_001_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
signal rsp_xbar_demux_001_src0_ready : std_logic; -- rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
signal rsp_xbar_demux_001_src1_endofpacket : std_logic; -- rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
signal rsp_xbar_demux_001_src1_valid : std_logic; -- rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid
signal rsp_xbar_demux_001_src1_startofpacket : std_logic; -- rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
signal rsp_xbar_demux_001_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data
signal rsp_xbar_demux_001_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel
signal rsp_xbar_demux_001_src1_ready : std_logic; -- rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready
signal rsp_xbar_demux_002_src0_endofpacket : std_logic; -- rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux:sink2_endofpacket
signal rsp_xbar_demux_002_src0_valid : std_logic; -- rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux:sink2_valid
signal rsp_xbar_demux_002_src0_startofpacket : std_logic; -- rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux:sink2_startofpacket
signal rsp_xbar_demux_002_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_002:src0_data -> rsp_xbar_mux:sink2_data
signal rsp_xbar_demux_002_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux:sink2_channel
signal rsp_xbar_demux_002_src0_ready : std_logic; -- rsp_xbar_mux:sink2_ready -> rsp_xbar_demux_002:src0_ready
signal rsp_xbar_demux_002_src1_endofpacket : std_logic; -- rsp_xbar_demux_002:src1_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket
signal rsp_xbar_demux_002_src1_valid : std_logic; -- rsp_xbar_demux_002:src1_valid -> rsp_xbar_mux_001:sink2_valid
signal rsp_xbar_demux_002_src1_startofpacket : std_logic; -- rsp_xbar_demux_002:src1_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket
signal rsp_xbar_demux_002_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_002:src1_data -> rsp_xbar_mux_001:sink2_data
signal rsp_xbar_demux_002_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_002:src1_channel -> rsp_xbar_mux_001:sink2_channel
signal rsp_xbar_demux_002_src1_ready : std_logic; -- rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src1_ready
signal rsp_xbar_demux_003_src0_endofpacket : std_logic; -- rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux:sink3_endofpacket
signal rsp_xbar_demux_003_src0_valid : std_logic; -- rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux:sink3_valid
signal rsp_xbar_demux_003_src0_startofpacket : std_logic; -- rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux:sink3_startofpacket
signal rsp_xbar_demux_003_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_003:src0_data -> rsp_xbar_mux:sink3_data
signal rsp_xbar_demux_003_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux:sink3_channel
signal rsp_xbar_demux_003_src0_ready : std_logic; -- rsp_xbar_mux:sink3_ready -> rsp_xbar_demux_003:src0_ready
signal rsp_xbar_demux_003_src1_endofpacket : std_logic; -- rsp_xbar_demux_003:src1_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket
signal rsp_xbar_demux_003_src1_valid : std_logic; -- rsp_xbar_demux_003:src1_valid -> rsp_xbar_mux_001:sink3_valid
signal rsp_xbar_demux_003_src1_startofpacket : std_logic; -- rsp_xbar_demux_003:src1_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket
signal rsp_xbar_demux_003_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_003:src1_data -> rsp_xbar_mux_001:sink3_data
signal rsp_xbar_demux_003_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_003:src1_channel -> rsp_xbar_mux_001:sink3_channel
signal rsp_xbar_demux_003_src1_ready : std_logic; -- rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src1_ready
signal rsp_xbar_demux_005_src0_endofpacket : std_logic; -- rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket
signal rsp_xbar_demux_005_src0_valid : std_logic; -- rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid
signal rsp_xbar_demux_005_src0_startofpacket : std_logic; -- rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket
signal rsp_xbar_demux_005_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data
signal rsp_xbar_demux_005_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel
signal rsp_xbar_demux_005_src0_ready : std_logic; -- rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready
signal rsp_xbar_demux_006_src0_endofpacket : std_logic; -- rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket
signal rsp_xbar_demux_006_src0_valid : std_logic; -- rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid
signal rsp_xbar_demux_006_src0_startofpacket : std_logic; -- rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket
signal rsp_xbar_demux_006_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data
signal rsp_xbar_demux_006_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel
signal rsp_xbar_demux_006_src0_ready : std_logic; -- rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready
signal rsp_xbar_demux_007_src0_endofpacket : std_logic; -- rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket
signal rsp_xbar_demux_007_src0_valid : std_logic; -- rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid
signal rsp_xbar_demux_007_src0_startofpacket : std_logic; -- rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket
signal rsp_xbar_demux_007_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data
signal rsp_xbar_demux_007_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel
signal rsp_xbar_demux_007_src0_ready : std_logic; -- rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready
signal rsp_xbar_demux_008_src0_endofpacket : std_logic; -- rsp_xbar_demux_008:src0_endofpacket -> rsp_xbar_mux_001:sink8_endofpacket
signal rsp_xbar_demux_008_src0_valid : std_logic; -- rsp_xbar_demux_008:src0_valid -> rsp_xbar_mux_001:sink8_valid
signal rsp_xbar_demux_008_src0_startofpacket : std_logic; -- rsp_xbar_demux_008:src0_startofpacket -> rsp_xbar_mux_001:sink8_startofpacket
signal rsp_xbar_demux_008_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_008:src0_data -> rsp_xbar_mux_001:sink8_data
signal rsp_xbar_demux_008_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_008:src0_channel -> rsp_xbar_mux_001:sink8_channel
signal rsp_xbar_demux_008_src0_ready : std_logic; -- rsp_xbar_mux_001:sink8_ready -> rsp_xbar_demux_008:src0_ready
signal rsp_xbar_demux_009_src0_endofpacket : std_logic; -- rsp_xbar_demux_009:src0_endofpacket -> rsp_xbar_mux_001:sink9_endofpacket
signal rsp_xbar_demux_009_src0_valid : std_logic; -- rsp_xbar_demux_009:src0_valid -> rsp_xbar_mux_001:sink9_valid
signal rsp_xbar_demux_009_src0_startofpacket : std_logic; -- rsp_xbar_demux_009:src0_startofpacket -> rsp_xbar_mux_001:sink9_startofpacket
signal rsp_xbar_demux_009_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_009:src0_data -> rsp_xbar_mux_001:sink9_data
signal rsp_xbar_demux_009_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_009:src0_channel -> rsp_xbar_mux_001:sink9_channel
signal rsp_xbar_demux_009_src0_ready : std_logic; -- rsp_xbar_mux_001:sink9_ready -> rsp_xbar_demux_009:src0_ready
signal rsp_xbar_demux_010_src0_endofpacket : std_logic; -- rsp_xbar_demux_010:src0_endofpacket -> rsp_xbar_mux_001:sink10_endofpacket
signal rsp_xbar_demux_010_src0_valid : std_logic; -- rsp_xbar_demux_010:src0_valid -> rsp_xbar_mux_001:sink10_valid
signal rsp_xbar_demux_010_src0_startofpacket : std_logic; -- rsp_xbar_demux_010:src0_startofpacket -> rsp_xbar_mux_001:sink10_startofpacket
signal rsp_xbar_demux_010_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_010:src0_data -> rsp_xbar_mux_001:sink10_data
signal rsp_xbar_demux_010_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_010:src0_channel -> rsp_xbar_mux_001:sink10_channel
signal rsp_xbar_demux_010_src0_ready : std_logic; -- rsp_xbar_mux_001:sink10_ready -> rsp_xbar_demux_010:src0_ready
signal rsp_xbar_demux_011_src0_endofpacket : std_logic; -- rsp_xbar_demux_011:src0_endofpacket -> rsp_xbar_mux_001:sink11_endofpacket
signal rsp_xbar_demux_011_src0_valid : std_logic; -- rsp_xbar_demux_011:src0_valid -> rsp_xbar_mux_001:sink11_valid
signal rsp_xbar_demux_011_src0_startofpacket : std_logic; -- rsp_xbar_demux_011:src0_startofpacket -> rsp_xbar_mux_001:sink11_startofpacket
signal rsp_xbar_demux_011_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_011:src0_data -> rsp_xbar_mux_001:sink11_data
signal rsp_xbar_demux_011_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_011:src0_channel -> rsp_xbar_mux_001:sink11_channel
signal rsp_xbar_demux_011_src0_ready : std_logic; -- rsp_xbar_mux_001:sink11_ready -> rsp_xbar_demux_011:src0_ready
signal rsp_xbar_demux_012_src0_endofpacket : std_logic; -- rsp_xbar_demux_012:src0_endofpacket -> rsp_xbar_mux_001:sink12_endofpacket
signal rsp_xbar_demux_012_src0_valid : std_logic; -- rsp_xbar_demux_012:src0_valid -> rsp_xbar_mux_001:sink12_valid
signal rsp_xbar_demux_012_src0_startofpacket : std_logic; -- rsp_xbar_demux_012:src0_startofpacket -> rsp_xbar_mux_001:sink12_startofpacket
signal rsp_xbar_demux_012_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_012:src0_data -> rsp_xbar_mux_001:sink12_data
signal rsp_xbar_demux_012_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_012:src0_channel -> rsp_xbar_mux_001:sink12_channel
signal rsp_xbar_demux_012_src0_ready : std_logic; -- rsp_xbar_mux_001:sink12_ready -> rsp_xbar_demux_012:src0_ready
signal limiter_cmd_src_endofpacket : std_logic; -- limiter:cmd_src_endofpacket -> cmd_xbar_demux:sink_endofpacket
signal limiter_cmd_src_startofpacket : std_logic; -- limiter:cmd_src_startofpacket -> cmd_xbar_demux:sink_startofpacket
signal limiter_cmd_src_data : std_logic_vector(99 downto 0); -- limiter:cmd_src_data -> cmd_xbar_demux:sink_data
signal limiter_cmd_src_channel : std_logic_vector(12 downto 0); -- limiter:cmd_src_channel -> cmd_xbar_demux:sink_channel
signal limiter_cmd_src_ready : std_logic; -- cmd_xbar_demux:sink_ready -> limiter:cmd_src_ready
signal rsp_xbar_mux_src_endofpacket : std_logic; -- rsp_xbar_mux:src_endofpacket -> limiter:rsp_sink_endofpacket
signal rsp_xbar_mux_src_valid : std_logic; -- rsp_xbar_mux:src_valid -> limiter:rsp_sink_valid
signal rsp_xbar_mux_src_startofpacket : std_logic; -- rsp_xbar_mux:src_startofpacket -> limiter:rsp_sink_startofpacket
signal rsp_xbar_mux_src_data : std_logic_vector(99 downto 0); -- rsp_xbar_mux:src_data -> limiter:rsp_sink_data
signal rsp_xbar_mux_src_channel : std_logic_vector(12 downto 0); -- rsp_xbar_mux:src_channel -> limiter:rsp_sink_channel
signal rsp_xbar_mux_src_ready : std_logic; -- limiter:rsp_sink_ready -> rsp_xbar_mux:src_ready
signal limiter_001_cmd_src_endofpacket : std_logic; -- limiter_001:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
signal limiter_001_cmd_src_startofpacket : std_logic; -- limiter_001:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
signal limiter_001_cmd_src_data : std_logic_vector(99 downto 0); -- limiter_001:cmd_src_data -> cmd_xbar_demux_001:sink_data
signal limiter_001_cmd_src_channel : std_logic_vector(12 downto 0); -- limiter_001:cmd_src_channel -> cmd_xbar_demux_001:sink_channel
signal limiter_001_cmd_src_ready : std_logic; -- cmd_xbar_demux_001:sink_ready -> limiter_001:cmd_src_ready
signal rsp_xbar_mux_001_src_endofpacket : std_logic; -- rsp_xbar_mux_001:src_endofpacket -> limiter_001:rsp_sink_endofpacket
signal rsp_xbar_mux_001_src_valid : std_logic; -- rsp_xbar_mux_001:src_valid -> limiter_001:rsp_sink_valid
signal rsp_xbar_mux_001_src_startofpacket : std_logic; -- rsp_xbar_mux_001:src_startofpacket -> limiter_001:rsp_sink_startofpacket
signal rsp_xbar_mux_001_src_data : std_logic_vector(99 downto 0); -- rsp_xbar_mux_001:src_data -> limiter_001:rsp_sink_data
signal rsp_xbar_mux_001_src_channel : std_logic_vector(12 downto 0); -- rsp_xbar_mux_001:src_channel -> limiter_001:rsp_sink_channel
signal rsp_xbar_mux_001_src_ready : std_logic; -- limiter_001:rsp_sink_ready -> rsp_xbar_mux_001:src_ready
signal cmd_xbar_mux_src_endofpacket : std_logic; -- cmd_xbar_mux:src_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_mux_src_valid : std_logic; -- cmd_xbar_mux:src_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_mux_src_startofpacket : std_logic; -- cmd_xbar_mux:src_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_mux_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux:src_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_mux_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux:src_channel -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_mux_src_ready : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready
signal id_router_src_endofpacket : std_logic; -- id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
signal id_router_src_valid : std_logic; -- id_router:src_valid -> rsp_xbar_demux:sink_valid
signal id_router_src_startofpacket : std_logic; -- id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
signal id_router_src_data : std_logic_vector(99 downto 0); -- id_router:src_data -> rsp_xbar_demux:sink_data
signal id_router_src_channel : std_logic_vector(12 downto 0); -- id_router:src_channel -> rsp_xbar_demux:sink_channel
signal id_router_src_ready : std_logic; -- rsp_xbar_demux:sink_ready -> id_router:src_ready
signal cmd_xbar_mux_001_src_endofpacket : std_logic; -- cmd_xbar_mux_001:src_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_mux_001_src_valid : std_logic; -- cmd_xbar_mux_001:src_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_mux_001_src_startofpacket : std_logic; -- cmd_xbar_mux_001:src_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_mux_001_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux_001:src_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_mux_001_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux_001:src_channel -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_mux_001_src_ready : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_001:src_ready
signal id_router_001_src_endofpacket : std_logic; -- id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
signal id_router_001_src_valid : std_logic; -- id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
signal id_router_001_src_startofpacket : std_logic; -- id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
signal id_router_001_src_data : std_logic_vector(99 downto 0); -- id_router_001:src_data -> rsp_xbar_demux_001:sink_data
signal id_router_001_src_channel : std_logic_vector(12 downto 0); -- id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
signal id_router_001_src_ready : std_logic; -- rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
signal crosser_out_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_ready -> crosser:out_ready
signal id_router_004_src_endofpacket : std_logic; -- id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
signal id_router_004_src_valid : std_logic; -- id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
signal id_router_004_src_startofpacket : std_logic; -- id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
signal id_router_004_src_data : std_logic_vector(99 downto 0); -- id_router_004:src_data -> rsp_xbar_demux_004:sink_data
signal id_router_004_src_channel : std_logic_vector(12 downto 0); -- id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
signal id_router_004_src_ready : std_logic; -- rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
signal cmd_xbar_demux_001_src5_ready : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready
signal id_router_005_src_endofpacket : std_logic; -- id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
signal id_router_005_src_valid : std_logic; -- id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
signal id_router_005_src_startofpacket : std_logic; -- id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
signal id_router_005_src_data : std_logic_vector(99 downto 0); -- id_router_005:src_data -> rsp_xbar_demux_005:sink_data
signal id_router_005_src_channel : std_logic_vector(12 downto 0); -- id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
signal id_router_005_src_ready : std_logic; -- rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
signal cmd_xbar_demux_001_src6_ready : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready
signal id_router_006_src_endofpacket : std_logic; -- id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket
signal id_router_006_src_valid : std_logic; -- id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid
signal id_router_006_src_startofpacket : std_logic; -- id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket
signal id_router_006_src_data : std_logic_vector(99 downto 0); -- id_router_006:src_data -> rsp_xbar_demux_006:sink_data
signal id_router_006_src_channel : std_logic_vector(12 downto 0); -- id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel
signal id_router_006_src_ready : std_logic; -- rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready
signal cmd_xbar_demux_001_src7_ready : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready
signal id_router_007_src_endofpacket : std_logic; -- id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket
signal id_router_007_src_valid : std_logic; -- id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid
signal id_router_007_src_startofpacket : std_logic; -- id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket
signal id_router_007_src_data : std_logic_vector(99 downto 0); -- id_router_007:src_data -> rsp_xbar_demux_007:sink_data
signal id_router_007_src_channel : std_logic_vector(12 downto 0); -- id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel
signal id_router_007_src_ready : std_logic; -- rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready
signal cmd_xbar_demux_001_src9_ready : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src9_ready
signal id_router_009_src_endofpacket : std_logic; -- id_router_009:src_endofpacket -> rsp_xbar_demux_009:sink_endofpacket
signal id_router_009_src_valid : std_logic; -- id_router_009:src_valid -> rsp_xbar_demux_009:sink_valid
signal id_router_009_src_startofpacket : std_logic; -- id_router_009:src_startofpacket -> rsp_xbar_demux_009:sink_startofpacket
signal id_router_009_src_data : std_logic_vector(99 downto 0); -- id_router_009:src_data -> rsp_xbar_demux_009:sink_data
signal id_router_009_src_channel : std_logic_vector(12 downto 0); -- id_router_009:src_channel -> rsp_xbar_demux_009:sink_channel
signal id_router_009_src_ready : std_logic; -- rsp_xbar_demux_009:sink_ready -> id_router_009:src_ready
signal cmd_xbar_demux_001_src10_ready : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src10_ready
signal id_router_010_src_endofpacket : std_logic; -- id_router_010:src_endofpacket -> rsp_xbar_demux_010:sink_endofpacket
signal id_router_010_src_valid : std_logic; -- id_router_010:src_valid -> rsp_xbar_demux_010:sink_valid
signal id_router_010_src_startofpacket : std_logic; -- id_router_010:src_startofpacket -> rsp_xbar_demux_010:sink_startofpacket
signal id_router_010_src_data : std_logic_vector(99 downto 0); -- id_router_010:src_data -> rsp_xbar_demux_010:sink_data
signal id_router_010_src_channel : std_logic_vector(12 downto 0); -- id_router_010:src_channel -> rsp_xbar_demux_010:sink_channel
signal id_router_010_src_ready : std_logic; -- rsp_xbar_demux_010:sink_ready -> id_router_010:src_ready
signal cmd_xbar_demux_001_src12_ready : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src12_ready
signal id_router_012_src_endofpacket : std_logic; -- id_router_012:src_endofpacket -> rsp_xbar_demux_012:sink_endofpacket
signal id_router_012_src_valid : std_logic; -- id_router_012:src_valid -> rsp_xbar_demux_012:sink_valid
signal id_router_012_src_startofpacket : std_logic; -- id_router_012:src_startofpacket -> rsp_xbar_demux_012:sink_startofpacket
signal id_router_012_src_data : std_logic_vector(99 downto 0); -- id_router_012:src_data -> rsp_xbar_demux_012:sink_data
signal id_router_012_src_channel : std_logic_vector(12 downto 0); -- id_router_012:src_channel -> rsp_xbar_demux_012:sink_channel
signal id_router_012_src_ready : std_logic; -- rsp_xbar_demux_012:sink_ready -> id_router_012:src_ready
signal cmd_xbar_mux_002_src_endofpacket : std_logic; -- cmd_xbar_mux_002:src_endofpacket -> width_adapter:in_endofpacket
signal cmd_xbar_mux_002_src_valid : std_logic; -- cmd_xbar_mux_002:src_valid -> width_adapter:in_valid
signal cmd_xbar_mux_002_src_startofpacket : std_logic; -- cmd_xbar_mux_002:src_startofpacket -> width_adapter:in_startofpacket
signal cmd_xbar_mux_002_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux_002:src_data -> width_adapter:in_data
signal cmd_xbar_mux_002_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux_002:src_channel -> width_adapter:in_channel
signal cmd_xbar_mux_002_src_ready : std_logic; -- width_adapter:in_ready -> cmd_xbar_mux_002:src_ready
signal width_adapter_src_endofpacket : std_logic; -- width_adapter:out_endofpacket -> burst_adapter:sink0_endofpacket
signal width_adapter_src_valid : std_logic; -- width_adapter:out_valid -> burst_adapter:sink0_valid
signal width_adapter_src_startofpacket : std_logic; -- width_adapter:out_startofpacket -> burst_adapter:sink0_startofpacket
signal width_adapter_src_data : std_logic_vector(81 downto 0); -- width_adapter:out_data -> burst_adapter:sink0_data
signal width_adapter_src_ready : std_logic; -- burst_adapter:sink0_ready -> width_adapter:out_ready
signal width_adapter_src_channel : std_logic_vector(12 downto 0); -- width_adapter:out_channel -> burst_adapter:sink0_channel
signal id_router_002_src_endofpacket : std_logic; -- id_router_002:src_endofpacket -> width_adapter_001:in_endofpacket
signal id_router_002_src_valid : std_logic; -- id_router_002:src_valid -> width_adapter_001:in_valid
signal id_router_002_src_startofpacket : std_logic; -- id_router_002:src_startofpacket -> width_adapter_001:in_startofpacket
signal id_router_002_src_data : std_logic_vector(81 downto 0); -- id_router_002:src_data -> width_adapter_001:in_data
signal id_router_002_src_channel : std_logic_vector(12 downto 0); -- id_router_002:src_channel -> width_adapter_001:in_channel
signal id_router_002_src_ready : std_logic; -- width_adapter_001:in_ready -> id_router_002:src_ready
signal width_adapter_001_src_endofpacket : std_logic; -- width_adapter_001:out_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
signal width_adapter_001_src_valid : std_logic; -- width_adapter_001:out_valid -> rsp_xbar_demux_002:sink_valid
signal width_adapter_001_src_startofpacket : std_logic; -- width_adapter_001:out_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
signal width_adapter_001_src_data : std_logic_vector(99 downto 0); -- width_adapter_001:out_data -> rsp_xbar_demux_002:sink_data
signal width_adapter_001_src_ready : std_logic; -- rsp_xbar_demux_002:sink_ready -> width_adapter_001:out_ready
signal width_adapter_001_src_channel : std_logic_vector(12 downto 0); -- width_adapter_001:out_channel -> rsp_xbar_demux_002:sink_channel
signal cmd_xbar_mux_003_src_endofpacket : std_logic; -- cmd_xbar_mux_003:src_endofpacket -> width_adapter_002:in_endofpacket
signal cmd_xbar_mux_003_src_valid : std_logic; -- cmd_xbar_mux_003:src_valid -> width_adapter_002:in_valid
signal cmd_xbar_mux_003_src_startofpacket : std_logic; -- cmd_xbar_mux_003:src_startofpacket -> width_adapter_002:in_startofpacket
signal cmd_xbar_mux_003_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux_003:src_data -> width_adapter_002:in_data
signal cmd_xbar_mux_003_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux_003:src_channel -> width_adapter_002:in_channel
signal cmd_xbar_mux_003_src_ready : std_logic; -- width_adapter_002:in_ready -> cmd_xbar_mux_003:src_ready
signal width_adapter_002_src_endofpacket : std_logic; -- width_adapter_002:out_endofpacket -> burst_adapter_001:sink0_endofpacket
signal width_adapter_002_src_valid : std_logic; -- width_adapter_002:out_valid -> burst_adapter_001:sink0_valid
signal width_adapter_002_src_startofpacket : std_logic; -- width_adapter_002:out_startofpacket -> burst_adapter_001:sink0_startofpacket
signal width_adapter_002_src_data : std_logic_vector(81 downto 0); -- width_adapter_002:out_data -> burst_adapter_001:sink0_data
signal width_adapter_002_src_ready : std_logic; -- burst_adapter_001:sink0_ready -> width_adapter_002:out_ready
signal width_adapter_002_src_channel : std_logic_vector(12 downto 0); -- width_adapter_002:out_channel -> burst_adapter_001:sink0_channel
signal id_router_003_src_endofpacket : std_logic; -- id_router_003:src_endofpacket -> width_adapter_003:in_endofpacket
signal id_router_003_src_valid : std_logic; -- id_router_003:src_valid -> width_adapter_003:in_valid
signal id_router_003_src_startofpacket : std_logic; -- id_router_003:src_startofpacket -> width_adapter_003:in_startofpacket
signal id_router_003_src_data : std_logic_vector(81 downto 0); -- id_router_003:src_data -> width_adapter_003:in_data
signal id_router_003_src_channel : std_logic_vector(12 downto 0); -- id_router_003:src_channel -> width_adapter_003:in_channel
signal id_router_003_src_ready : std_logic; -- width_adapter_003:in_ready -> id_router_003:src_ready
signal width_adapter_003_src_endofpacket : std_logic; -- width_adapter_003:out_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
signal width_adapter_003_src_valid : std_logic; -- width_adapter_003:out_valid -> rsp_xbar_demux_003:sink_valid
signal width_adapter_003_src_startofpacket : std_logic; -- width_adapter_003:out_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
signal width_adapter_003_src_data : std_logic_vector(99 downto 0); -- width_adapter_003:out_data -> rsp_xbar_demux_003:sink_data
signal width_adapter_003_src_ready : std_logic; -- rsp_xbar_demux_003:sink_ready -> width_adapter_003:out_ready
signal width_adapter_003_src_channel : std_logic_vector(12 downto 0); -- width_adapter_003:out_channel -> rsp_xbar_demux_003:sink_channel
signal cmd_xbar_demux_001_src8_ready : std_logic; -- width_adapter_004:in_ready -> cmd_xbar_demux_001:src8_ready
signal width_adapter_004_src_endofpacket : std_logic; -- width_adapter_004:out_endofpacket -> burst_adapter_002:sink0_endofpacket
signal width_adapter_004_src_valid : std_logic; -- width_adapter_004:out_valid -> burst_adapter_002:sink0_valid
signal width_adapter_004_src_startofpacket : std_logic; -- width_adapter_004:out_startofpacket -> burst_adapter_002:sink0_startofpacket
signal width_adapter_004_src_data : std_logic_vector(72 downto 0); -- width_adapter_004:out_data -> burst_adapter_002:sink0_data
signal width_adapter_004_src_ready : std_logic; -- burst_adapter_002:sink0_ready -> width_adapter_004:out_ready
signal width_adapter_004_src_channel : std_logic_vector(12 downto 0); -- width_adapter_004:out_channel -> burst_adapter_002:sink0_channel
signal id_router_008_src_endofpacket : std_logic; -- id_router_008:src_endofpacket -> width_adapter_005:in_endofpacket
signal id_router_008_src_valid : std_logic; -- id_router_008:src_valid -> width_adapter_005:in_valid
signal id_router_008_src_startofpacket : std_logic; -- id_router_008:src_startofpacket -> width_adapter_005:in_startofpacket
signal id_router_008_src_data : std_logic_vector(72 downto 0); -- id_router_008:src_data -> width_adapter_005:in_data
signal id_router_008_src_channel : std_logic_vector(12 downto 0); -- id_router_008:src_channel -> width_adapter_005:in_channel
signal id_router_008_src_ready : std_logic; -- width_adapter_005:in_ready -> id_router_008:src_ready
signal width_adapter_005_src_endofpacket : std_logic; -- width_adapter_005:out_endofpacket -> rsp_xbar_demux_008:sink_endofpacket
signal width_adapter_005_src_valid : std_logic; -- width_adapter_005:out_valid -> rsp_xbar_demux_008:sink_valid
signal width_adapter_005_src_startofpacket : std_logic; -- width_adapter_005:out_startofpacket -> rsp_xbar_demux_008:sink_startofpacket
signal width_adapter_005_src_data : std_logic_vector(99 downto 0); -- width_adapter_005:out_data -> rsp_xbar_demux_008:sink_data
signal width_adapter_005_src_ready : std_logic; -- rsp_xbar_demux_008:sink_ready -> width_adapter_005:out_ready
signal width_adapter_005_src_channel : std_logic_vector(12 downto 0); -- width_adapter_005:out_channel -> rsp_xbar_demux_008:sink_channel
signal cmd_xbar_demux_001_src11_ready : std_logic; -- width_adapter_006:in_ready -> cmd_xbar_demux_001:src11_ready
signal width_adapter_006_src_endofpacket : std_logic; -- width_adapter_006:out_endofpacket -> burst_adapter_003:sink0_endofpacket
signal width_adapter_006_src_valid : std_logic; -- width_adapter_006:out_valid -> burst_adapter_003:sink0_valid
signal width_adapter_006_src_startofpacket : std_logic; -- width_adapter_006:out_startofpacket -> burst_adapter_003:sink0_startofpacket
signal width_adapter_006_src_data : std_logic_vector(72 downto 0); -- width_adapter_006:out_data -> burst_adapter_003:sink0_data
signal width_adapter_006_src_ready : std_logic; -- burst_adapter_003:sink0_ready -> width_adapter_006:out_ready
signal width_adapter_006_src_channel : std_logic_vector(12 downto 0); -- width_adapter_006:out_channel -> burst_adapter_003:sink0_channel
signal id_router_011_src_endofpacket : std_logic; -- id_router_011:src_endofpacket -> width_adapter_007:in_endofpacket
signal id_router_011_src_valid : std_logic; -- id_router_011:src_valid -> width_adapter_007:in_valid
signal id_router_011_src_startofpacket : std_logic; -- id_router_011:src_startofpacket -> width_adapter_007:in_startofpacket
signal id_router_011_src_data : std_logic_vector(72 downto 0); -- id_router_011:src_data -> width_adapter_007:in_data
signal id_router_011_src_channel : std_logic_vector(12 downto 0); -- id_router_011:src_channel -> width_adapter_007:in_channel
signal id_router_011_src_ready : std_logic; -- width_adapter_007:in_ready -> id_router_011:src_ready
signal width_adapter_007_src_endofpacket : std_logic; -- width_adapter_007:out_endofpacket -> rsp_xbar_demux_011:sink_endofpacket
signal width_adapter_007_src_valid : std_logic; -- width_adapter_007:out_valid -> rsp_xbar_demux_011:sink_valid
signal width_adapter_007_src_startofpacket : std_logic; -- width_adapter_007:out_startofpacket -> rsp_xbar_demux_011:sink_startofpacket
signal width_adapter_007_src_data : std_logic_vector(99 downto 0); -- width_adapter_007:out_data -> rsp_xbar_demux_011:sink_data
signal width_adapter_007_src_ready : std_logic; -- rsp_xbar_demux_011:sink_ready -> width_adapter_007:out_ready
signal width_adapter_007_src_channel : std_logic_vector(12 downto 0); -- width_adapter_007:out_channel -> rsp_xbar_demux_011:sink_channel
signal crosser_out_endofpacket : std_logic; -- crosser:out_endofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal crosser_out_valid : std_logic; -- crosser:out_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal crosser_out_startofpacket : std_logic; -- crosser:out_startofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal crosser_out_data : std_logic_vector(99 downto 0); -- crosser:out_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_data
signal crosser_out_channel : std_logic_vector(12 downto 0); -- crosser:out_channel -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src4_endofpacket : std_logic; -- cmd_xbar_demux_001:src4_endofpacket -> crosser:in_endofpacket
signal cmd_xbar_demux_001_src4_valid : std_logic; -- cmd_xbar_demux_001:src4_valid -> crosser:in_valid
signal cmd_xbar_demux_001_src4_startofpacket : std_logic; -- cmd_xbar_demux_001:src4_startofpacket -> crosser:in_startofpacket
signal cmd_xbar_demux_001_src4_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src4_data -> crosser:in_data
signal cmd_xbar_demux_001_src4_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src4_channel -> crosser:in_channel
signal cmd_xbar_demux_001_src4_ready : std_logic; -- crosser:in_ready -> cmd_xbar_demux_001:src4_ready
signal crosser_001_out_endofpacket : std_logic; -- crosser_001:out_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket
signal crosser_001_out_valid : std_logic; -- crosser_001:out_valid -> rsp_xbar_mux_001:sink4_valid
signal crosser_001_out_startofpacket : std_logic; -- crosser_001:out_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket
signal crosser_001_out_data : std_logic_vector(99 downto 0); -- crosser_001:out_data -> rsp_xbar_mux_001:sink4_data
signal crosser_001_out_channel : std_logic_vector(12 downto 0); -- crosser_001:out_channel -> rsp_xbar_mux_001:sink4_channel
signal crosser_001_out_ready : std_logic; -- rsp_xbar_mux_001:sink4_ready -> crosser_001:out_ready
signal rsp_xbar_demux_004_src0_endofpacket : std_logic; -- rsp_xbar_demux_004:src0_endofpacket -> crosser_001:in_endofpacket
signal rsp_xbar_demux_004_src0_valid : std_logic; -- rsp_xbar_demux_004:src0_valid -> crosser_001:in_valid
signal rsp_xbar_demux_004_src0_startofpacket : std_logic; -- rsp_xbar_demux_004:src0_startofpacket -> crosser_001:in_startofpacket
signal rsp_xbar_demux_004_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_004:src0_data -> crosser_001:in_data
signal rsp_xbar_demux_004_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_004:src0_channel -> crosser_001:in_channel
signal rsp_xbar_demux_004_src0_ready : std_logic; -- crosser_001:in_ready -> rsp_xbar_demux_004:src0_ready
signal limiter_cmd_valid_data : std_logic_vector(12 downto 0); -- limiter:cmd_src_valid -> cmd_xbar_demux:sink_valid
signal limiter_001_cmd_valid_data : std_logic_vector(12 downto 0); -- limiter_001:cmd_src_valid -> cmd_xbar_demux_001:sink_valid
signal irq_mapper_receiver0_irq : std_logic; -- timer_0:irq -> irq_mapper:receiver0_irq
signal irq_mapper_receiver1_irq : std_logic; -- jtag_uart_0:av_irq -> irq_mapper:receiver1_irq
signal nios2_qsys_0_d_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_qsys_0:d_irq
signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> [rst_controller:reset_in0, rst_controller_001:reset_in0]
signal sdram_0_s1_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- sdram_0_s1_translator_avalon_anti_slave_0_write:inv -> sdram_0:az_wr_n
signal sdram_0_s1_translator_avalon_anti_slave_0_read_ports_inv : std_logic; -- sdram_0_s1_translator_avalon_anti_slave_0_read:inv -> sdram_0:az_rd_n
signal sdram_0_s1_translator_avalon_anti_slave_0_byteenable_ports_inv : std_logic_vector(1 downto 0); -- sdram_0_s1_translator_avalon_anti_slave_0_byteenable:inv -> sdram_0:az_be_n
signal timer_0_s1_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- timer_0_s1_translator_avalon_anti_slave_0_write:inv -> timer_0:write_n
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write:inv -> jtag_uart_0:av_write_n
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read_ports_inv : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read:inv -> jtag_uart_0:av_read_n
signal green_leds_s1_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- green_leds_s1_translator_avalon_anti_slave_0_write:inv -> green_leds:write_n
signal servo_pwm_0_s0_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- servo_pwm_0_s0_translator_avalon_anti_slave_0_write:inv -> servo_pwm_0:avs_s0_write_n
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> [green_leds:reset_n, jtag_uart_0:rst_n, nios2_qsys_0:reset_n, sdram_0:reset_n, servo_pwm_0:reset_n, switch:reset_n, switch_0:reset_n, sysid_qsys_0:reset_n, timer_0:reset_n]
begin
nios2_qsys_0 : component tracking_camera_system_nios2_qsys_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset_n.reset_n
d_address => nios2_qsys_0_data_master_address, -- data_master.address
d_byteenable => nios2_qsys_0_data_master_byteenable, -- .byteenable
d_read => nios2_qsys_0_data_master_read, -- .read
d_readdata => nios2_qsys_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_qsys_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_qsys_0_data_master_write, -- .write
d_writedata => nios2_qsys_0_data_master_writedata, -- .writedata
d_readdatavalid => nios2_qsys_0_data_master_readdatavalid, -- .readdatavalid
jtag_debug_module_debugaccess_to_roms => nios2_qsys_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_qsys_0_instruction_master_address, -- instruction_master.address
i_read => nios2_qsys_0_instruction_master_read, -- .read
i_readdata => nios2_qsys_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_qsys_0_instruction_master_waitrequest, -- .waitrequest
i_readdatavalid => nios2_qsys_0_instruction_master_readdatavalid, -- .readdatavalid
d_irq => nios2_qsys_0_d_irq_irq, -- d_irq.irq
jtag_debug_module_resetrequest => nios2_qsys_0_jtag_debug_module_reset_reset, -- jtag_debug_module_reset.reset
jtag_debug_module_address => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address, -- jtag_debug_module.address
jtag_debug_module_begintransfer => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer, -- .begintransfer
jtag_debug_module_byteenable => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable, -- .byteenable
jtag_debug_module_debugaccess => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess
jtag_debug_module_readdata => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata, -- .readdata
jtag_debug_module_select => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_chipselect, -- .chipselect
jtag_debug_module_write => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write, -- .write
jtag_debug_module_writedata => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata, -- .writedata
no_ci_readra => open -- custom_instruction_master.readra
);
onchip_memory2_0 : component tracking_camera_system_onchip_memory2_0
port map (
clk => altpll_0_c1_clk, -- clk1.clk
address => onchip_memory2_0_s1_translator_avalon_anti_slave_0_address, -- s1.address
chipselect => onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
clken => onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken, -- .clken
readdata => onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
write => onchip_memory2_0_s1_translator_avalon_anti_slave_0_write, -- .write
writedata => onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
byteenable => onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable, -- .byteenable
reset => rst_controller_reset_out_reset -- reset1.reset
);
sysid_qsys_0 : component tracking_camera_system_sysid_qsys_0
port map (
clock => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
readdata => sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata, -- control_slave.readdata
address => sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address(0) -- .address
);
timer_0 : component tracking_camera_system_timer_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => timer_0_s1_translator_avalon_anti_slave_0_address, -- s1.address
writedata => timer_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
readdata => timer_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
chipselect => timer_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
write_n => timer_0_s1_translator_avalon_anti_slave_0_write_ports_inv, -- .write_n
irq => irq_mapper_receiver0_irq -- irq.irq
);
jtag_uart_0 : component tracking_camera_system_jtag_uart_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
rst_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
av_chipselect => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect, -- avalon_jtag_slave.chipselect
av_address => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address(0), -- .address
av_read_n => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read_ports_inv, -- .read_n
av_readdata => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_write_n => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write_ports_inv, -- .write_n
av_writedata => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_waitrequest => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_irq => irq_mapper_receiver1_irq -- irq.irq
);
character_lcd_0 : component tracking_camera_system_character_lcd_0
port map (
clk => altpll_0_c1_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
address => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_address(0), -- avalon_lcd_slave.address
chipselect => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_chipselect, -- .chipselect
read => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_read, -- .read
write => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_write, -- .write
writedata => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
readdata => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
waitrequest => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
LCD_DATA => character_lcd_0_external_interface_DATA, -- external_interface.export
LCD_ON => character_lcd_0_external_interface_ON, -- .export
LCD_BLON => character_lcd_0_external_interface_BLON, -- .export
LCD_EN => character_lcd_0_external_interface_EN, -- .export
LCD_RS => character_lcd_0_external_interface_RS, -- .export
LCD_RW => character_lcd_0_external_interface_RW -- .export
);
green_leds : component tracking_camera_system_green_leds
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => green_leds_s1_translator_avalon_anti_slave_0_address, -- s1.address
write_n => green_leds_s1_translator_avalon_anti_slave_0_write_ports_inv, -- .write_n
writedata => green_leds_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
chipselect => green_leds_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
readdata => green_leds_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
out_port => green_leds_external_connection_export -- external_connection.export
);
switch : component tracking_camera_system_switch
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => switch_s1_translator_avalon_anti_slave_0_address, -- s1.address
readdata => switch_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
in_port => switch_external_connection_export -- external_connection.export
);
altpll_0 : component tracking_camera_system_altpll_0
port map (
clk => clk_clk, -- inclk_interface.clk
reset => rst_controller_001_reset_out_reset, -- inclk_interface_reset.reset
read => altpll_0_pll_slave_translator_avalon_anti_slave_0_read, -- pll_slave.read
write => altpll_0_pll_slave_translator_avalon_anti_slave_0_write, -- .write
address => altpll_0_pll_slave_translator_avalon_anti_slave_0_address, -- .address
readdata => altpll_0_pll_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
writedata => altpll_0_pll_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
c0 => altpll_0_c0_clk, -- c0.clk
c1 => altpll_0_c1_clk, -- c1.clk
areset => open, -- areset_conduit.export
locked => open, -- locked_conduit.export
phasedone => open -- phasedone_conduit.export
);
sdram_0 : component tracking_camera_system_sdram_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
az_addr => sdram_0_s1_translator_avalon_anti_slave_0_address, -- s1.address
az_be_n => sdram_0_s1_translator_avalon_anti_slave_0_byteenable_ports_inv, -- .byteenable_n
az_cs => sdram_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
az_data => sdram_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
az_rd_n => sdram_0_s1_translator_avalon_anti_slave_0_read_ports_inv, -- .read_n
az_wr_n => sdram_0_s1_translator_avalon_anti_slave_0_write_ports_inv, -- .write_n
za_data => sdram_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
za_valid => sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
za_waitrequest => sdram_0_s1_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
zs_addr => sdram_0_wire_addr, -- wire.export
zs_ba => sdram_0_wire_ba, -- .export
zs_cas_n => sdram_0_wire_cas_n, -- .export
zs_cke => sdram_0_wire_cke, -- .export
zs_cs_n => sdram_0_wire_cs_n, -- .export
zs_dq => sdram_0_wire_dq, -- .export
zs_dqm => sdram_0_wire_dqm, -- .export
zs_ras_n => sdram_0_wire_ras_n, -- .export
zs_we_n => sdram_0_wire_we_n -- .export
);
sram_0 : component tracking_camera_system_sram_0
port map (
clk => altpll_0_c1_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
SRAM_DQ => sram_0_external_interface_DQ, -- external_interface.export
SRAM_ADDR => sram_0_external_interface_ADDR, -- .export
SRAM_LB_N => sram_0_external_interface_LB_N, -- .export
SRAM_UB_N => sram_0_external_interface_UB_N, -- .export
SRAM_CE_N => sram_0_external_interface_CE_N, -- .export
SRAM_OE_N => sram_0_external_interface_OE_N, -- .export
SRAM_WE_N => sram_0_external_interface_WE_N, -- .export
address => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address, -- avalon_sram_slave.address
byteenable => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
read => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read, -- .read
write => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write, -- .write
writedata => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
readdata => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
readdatavalid => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid -- .readdatavalid
);
servo_pwm_0 : component tracking_camera_system_servo_pwm_0
port map (
clk => altpll_0_c1_clk, -- clock.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
coe_servo => servo_pwm_0_conduit_end_0_export, -- conduit_end_0.export
avs_s0_write_n => servo_pwm_0_s0_translator_avalon_anti_slave_0_write_ports_inv, -- s0.write_n
avs_s0_writedata => servo_pwm_0_s0_translator_avalon_anti_slave_0_writedata -- .writedata
);
switch_0 : component tracking_camera_system_switch
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => switch_0_s1_translator_avalon_anti_slave_0_address, -- s1.address
readdata => switch_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
in_port => switch_0_external_connection_export -- external_connection.export
);
nios2_qsys_0_instruction_master_translator : component tracking_camera_system_nios2_qsys_0_instruction_master_translator
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
uav_burstcount => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
uav_read => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read, -- .read
uav_write => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write, -- .write
uav_waitrequest => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
uav_readdatavalid => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
uav_byteenable => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
uav_readdata => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata, -- .readdata
uav_writedata => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata, -- .writedata
uav_lock => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock, -- .lock
uav_debugaccess => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_address => nios2_qsys_0_instruction_master_address, -- avalon_anti_master_0.address
av_waitrequest => nios2_qsys_0_instruction_master_waitrequest, -- .waitrequest
av_read => nios2_qsys_0_instruction_master_read, -- .read
av_readdata => nios2_qsys_0_instruction_master_readdata, -- .readdata
av_readdatavalid => nios2_qsys_0_instruction_master_readdatavalid -- .readdatavalid
);
nios2_qsys_0_data_master_translator : component tracking_camera_system_nios2_qsys_0_data_master_translator
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => nios2_qsys_0_data_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
uav_burstcount => nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
uav_read => nios2_qsys_0_data_master_translator_avalon_universal_master_0_read, -- .read
uav_write => nios2_qsys_0_data_master_translator_avalon_universal_master_0_write, -- .write
uav_waitrequest => nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
uav_readdatavalid => nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
uav_byteenable => nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
uav_readdata => nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata, -- .readdata
uav_writedata => nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata, -- .writedata
uav_lock => nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock, -- .lock
uav_debugaccess => nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_address => nios2_qsys_0_data_master_address, -- avalon_anti_master_0.address
av_waitrequest => nios2_qsys_0_data_master_waitrequest, -- .waitrequest
av_byteenable => nios2_qsys_0_data_master_byteenable, -- .byteenable
av_read => nios2_qsys_0_data_master_read, -- .read
av_readdata => nios2_qsys_0_data_master_readdata, -- .readdata
av_readdatavalid => nios2_qsys_0_data_master_readdatavalid, -- .readdatavalid
av_write => nios2_qsys_0_data_master_write, -- .write
av_writedata => nios2_qsys_0_data_master_writedata, -- .writedata
av_debugaccess => nios2_qsys_0_data_master_debugaccess -- .debugaccess
);
nios2_qsys_0_jtag_debug_module_translator : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator
generic map (
AV_ADDRESS_W => 9,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write, -- .write
av_readdata => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata, -- .writedata
av_begintransfer => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer, -- .begintransfer
av_byteenable => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_chipselect => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_debugaccess => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess
av_read => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_outputenable => open -- (terminated)
);
onchip_memory2_0_s1_translator : component tracking_camera_system_onchip_memory2_0_s1_translator
generic map (
AV_ADDRESS_W => 12,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 1,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => onchip_memory2_0_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => onchip_memory2_0_s1_translator_avalon_anti_slave_0_write, -- .write
av_readdata => onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_chipselect => onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_clken => onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken, -- .clken
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
sdram_0_s1_translator : component tracking_camera_system_sdram_0_s1_translator
generic map (
AV_ADDRESS_W => 22,
AV_DATA_W => 16,
UAV_DATA_W => 16,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 2,
UAV_BYTEENABLE_W => 2,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 2,
AV_READLATENCY => 0,
USE_READDATAVALID => 1,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 2,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => sdram_0_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => sdram_0_s1_translator_avalon_anti_slave_0_write, -- .write
av_read => sdram_0_s1_translator_avalon_anti_slave_0_read, -- .read
av_readdata => sdram_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => sdram_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => sdram_0_s1_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_readdatavalid => sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
av_waitrequest => sdram_0_s1_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_chipselect => sdram_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
sram_0_avalon_sram_slave_translator : component tracking_camera_system_sram_0_avalon_sram_slave_translator
generic map (
AV_ADDRESS_W => 18,
AV_DATA_W => 16,
UAV_DATA_W => 16,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 2,
UAV_BYTEENABLE_W => 2,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 2,
AV_READLATENCY => 0,
USE_READDATAVALID => 1,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 2,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_readdatavalid => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
altpll_0_pll_slave_translator : component tracking_camera_system_altpll_0_pll_slave_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => altpll_0_pll_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => altpll_0_pll_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => altpll_0_pll_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => altpll_0_pll_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => altpll_0_pll_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
sysid_qsys_0_control_slave_translator : component tracking_camera_system_sysid_qsys_0_control_slave_translator
generic map (
AV_ADDRESS_W => 1,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_readdata => sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_write => open, -- (terminated)
av_read => open, -- (terminated)
av_writedata => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
timer_0_s1_translator : component tracking_camera_system_timer_0_s1_translator
generic map (
AV_ADDRESS_W => 3,
AV_DATA_W => 16,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => timer_0_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => timer_0_s1_translator_avalon_anti_slave_0_write, -- .write
av_readdata => timer_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => timer_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
av_chipselect => timer_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
jtag_uart_0_avalon_jtag_slave_translator : component tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator
generic map (
AV_ADDRESS_W => 1,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_waitrequest => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_chipselect => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
character_lcd_0_avalon_lcd_slave_translator : component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator
generic map (
AV_ADDRESS_W => 1,
AV_DATA_W => 8,
UAV_DATA_W => 8,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 1,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 1,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 1,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount(0) => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable(0) => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_waitrequest => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_chipselect => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
green_leds_s1_translator : component tracking_camera_system_green_leds_s1_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => green_leds_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => green_leds_s1_translator_avalon_anti_slave_0_write, -- .write
av_readdata => green_leds_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => green_leds_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
av_chipselect => green_leds_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
switch_s1_translator : component tracking_camera_system_green_leds_s1_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => switch_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => switch_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => switch_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => switch_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => switch_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => switch_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => switch_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => switch_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => switch_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => switch_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => switch_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => switch_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_readdata => switch_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_write => open, -- (terminated)
av_read => open, -- (terminated)
av_writedata => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
servo_pwm_0_s0_translator : component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator
generic map (
AV_ADDRESS_W => 1,
AV_DATA_W => 8,
UAV_DATA_W => 8,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 1,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 1,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 1,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount(0) => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable(0) => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_write => servo_pwm_0_s0_translator_avalon_anti_slave_0_write, -- avalon_anti_slave_0.write
av_writedata => servo_pwm_0_s0_translator_avalon_anti_slave_0_writedata, -- .writedata
av_address => open, -- (terminated)
av_read => open, -- (terminated)
av_readdata => "10101101", -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
switch_0_s1_translator : component tracking_camera_system_green_leds_s1_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => switch_0_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_readdata => switch_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_write => open, -- (terminated)
av_read => open, -- (terminated)
av_writedata => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent : component tracking_camera_system_nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
av_address => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address, -- av.address
av_write => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write, -- .write
av_read => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read, -- .read
av_writedata => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata, -- .writedata
av_readdata => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata, -- .readdata
av_waitrequest => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
av_readdatavalid => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
av_byteenable => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
av_burstcount => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
av_debugaccess => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_lock => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock, -- .lock
cp_valid => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
cp_data => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
cp_startofpacket => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
cp_endofpacket => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
cp_ready => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
rp_valid => limiter_rsp_src_valid, -- rp.valid
rp_data => limiter_rsp_src_data, -- .data
rp_channel => limiter_rsp_src_channel, -- .channel
rp_startofpacket => limiter_rsp_src_startofpacket, -- .startofpacket
rp_endofpacket => limiter_rsp_src_endofpacket, -- .endofpacket
rp_ready => limiter_rsp_src_ready -- .ready
);
nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent : component tracking_camera_system_nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
av_address => nios2_qsys_0_data_master_translator_avalon_universal_master_0_address, -- av.address
av_write => nios2_qsys_0_data_master_translator_avalon_universal_master_0_write, -- .write
av_read => nios2_qsys_0_data_master_translator_avalon_universal_master_0_read, -- .read
av_writedata => nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata, -- .writedata
av_readdata => nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata, -- .readdata
av_waitrequest => nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
av_readdatavalid => nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
av_byteenable => nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
av_burstcount => nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
av_debugaccess => nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_lock => nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock, -- .lock
cp_valid => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
cp_data => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
cp_startofpacket => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
cp_endofpacket => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
cp_ready => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
rp_valid => limiter_001_rsp_src_valid, -- rp.valid
rp_data => limiter_001_rsp_src_data, -- .data
rp_channel => limiter_001_rsp_src_channel, -- .channel
rp_startofpacket => limiter_001_rsp_src_startofpacket, -- .startofpacket
rp_endofpacket => limiter_001_rsp_src_endofpacket, -- .endofpacket
rp_ready => limiter_001_rsp_src_ready -- .ready
);
nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_mux_src_ready, -- cp.ready
cp_valid => cmd_xbar_mux_src_valid, -- .valid
cp_data => cmd_xbar_mux_src_data, -- .data
cp_startofpacket => cmd_xbar_mux_src_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_mux_src_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_mux_src_channel, -- .channel
rf_sink_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent : component tracking_camera_system_onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_mux_001_src_ready, -- cp.ready
cp_valid => cmd_xbar_mux_001_src_valid, -- .valid
cp_data => cmd_xbar_mux_001_src_data, -- .data
cp_startofpacket => cmd_xbar_mux_001_src_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_mux_001_src_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_mux_001_src_channel, -- .channel
rf_sink_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
sdram_0_s1_translator_avalon_universal_slave_0_agent : component tracking_camera_system_sdram_0_s1_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => burst_adapter_source0_ready, -- cp.ready
cp_valid => burst_adapter_source0_valid, -- .valid
cp_data => burst_adapter_source0_data, -- .data
cp_startofpacket => burst_adapter_source0_startofpacket, -- .startofpacket
cp_endofpacket => burst_adapter_source0_endofpacket, -- .endofpacket
cp_channel => burst_adapter_source0_channel, -- .channel
rf_sink_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent : component tracking_camera_system_sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => burst_adapter_001_source0_ready, -- cp.ready
cp_valid => burst_adapter_001_source0_valid, -- .valid
cp_data => burst_adapter_001_source0_data, -- .data
cp_startofpacket => burst_adapter_001_source0_startofpacket, -- .startofpacket
cp_endofpacket => burst_adapter_001_source0_endofpacket, -- .endofpacket
cp_channel => burst_adapter_001_source0_channel, -- .channel
rf_sink_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
altpll_0_pll_slave_translator_avalon_universal_slave_0_agent : component tracking_camera_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => crosser_out_ready, -- cp.ready
cp_valid => crosser_out_valid, -- .valid
cp_data => crosser_out_data, -- .data
cp_startofpacket => crosser_out_startofpacket, -- .startofpacket
cp_endofpacket => crosser_out_endofpacket, -- .endofpacket
cp_channel => crosser_out_channel, -- .channel
rf_sink_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
rdata_fifo_sink_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- .data
rdata_fifo_src_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo : component tracking_camera_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- in.data
in_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
in_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- .ready
out_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- out.data
out_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
out_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready -- .ready
);
sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent : component tracking_camera_system_sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src5_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src5_valid, -- .valid
cp_data => cmd_xbar_demux_001_src5_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src5_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src5_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src5_channel, -- .channel
rf_sink_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
timer_0_s1_translator_avalon_universal_slave_0_agent : component tracking_camera_system_timer_0_s1_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src6_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src6_valid, -- .valid
cp_data => cmd_xbar_demux_001_src6_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src6_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src6_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src6_channel, -- .channel
rf_sink_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent : component tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src7_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src7_valid, -- .valid
cp_data => cmd_xbar_demux_001_src7_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src7_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src7_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src7_channel, -- .channel
rf_sink_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent : component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => burst_adapter_002_source0_ready, -- cp.ready
cp_valid => burst_adapter_002_source0_valid, -- .valid
cp_data => burst_adapter_002_source0_data, -- .data
cp_startofpacket => burst_adapter_002_source0_startofpacket, -- .startofpacket
cp_endofpacket => burst_adapter_002_source0_endofpacket, -- .endofpacket
cp_channel => burst_adapter_002_source0_channel, -- .channel
rf_sink_ready => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
green_leds_s1_translator_avalon_universal_slave_0_agent : component tracking_camera_system_green_leds_s1_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src9_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src9_valid, -- .valid
cp_data => cmd_xbar_demux_001_src9_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src9_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src9_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src9_channel, -- .channel
rf_sink_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
switch_s1_translator_avalon_universal_slave_0_agent : component tracking_camera_system_switch_s1_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => switch_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => switch_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => switch_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => switch_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => switch_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => switch_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => switch_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => switch_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => switch_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => switch_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => switch_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => switch_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => switch_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => switch_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src10_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src10_valid, -- .valid
cp_data => cmd_xbar_demux_001_src10_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src10_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src10_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src10_channel, -- .channel
rf_sink_ready => switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => switch_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => switch_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => switch_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => switch_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => switch_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => switch_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
servo_pwm_0_s0_translator_avalon_universal_slave_0_agent : component tracking_camera_system_servo_pwm_0_s0_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => burst_adapter_003_source0_ready, -- cp.ready
cp_valid => burst_adapter_003_source0_valid, -- .valid
cp_data => burst_adapter_003_source0_data, -- .data
cp_startofpacket => burst_adapter_003_source0_startofpacket, -- .startofpacket
cp_endofpacket => burst_adapter_003_source0_endofpacket, -- .endofpacket
cp_channel => burst_adapter_003_source0_channel, -- .channel
rf_sink_ready => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
switch_0_s1_translator_avalon_universal_slave_0_agent : component tracking_camera_system_switch_0_s1_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => switch_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => switch_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => switch_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src12_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src12_valid, -- .valid
cp_data => cmd_xbar_demux_001_src12_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src12_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src12_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src12_channel, -- .channel
rf_sink_ready => switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
addr_router : component tracking_camera_system_addr_router
port map (
sink_ready => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
sink_valid => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
sink_data => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
sink_startofpacket => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
sink_endofpacket => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => addr_router_src_ready, -- src.ready
src_valid => addr_router_src_valid, -- .valid
src_data => addr_router_src_data, -- .data
src_channel => addr_router_src_channel, -- .channel
src_startofpacket => addr_router_src_startofpacket, -- .startofpacket
src_endofpacket => addr_router_src_endofpacket -- .endofpacket
);
addr_router_001 : component tracking_camera_system_addr_router_001
port map (
sink_ready => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
sink_valid => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
sink_data => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
sink_startofpacket => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
sink_endofpacket => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => addr_router_001_src_ready, -- src.ready
src_valid => addr_router_001_src_valid, -- .valid
src_data => addr_router_001_src_data, -- .data
src_channel => addr_router_001_src_channel, -- .channel
src_startofpacket => addr_router_001_src_startofpacket, -- .startofpacket
src_endofpacket => addr_router_001_src_endofpacket -- .endofpacket
);
id_router : component tracking_camera_system_id_router
port map (
sink_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_src_ready, -- src.ready
src_valid => id_router_src_valid, -- .valid
src_data => id_router_src_data, -- .data
src_channel => id_router_src_channel, -- .channel
src_startofpacket => id_router_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_src_endofpacket -- .endofpacket
);
id_router_001 : component tracking_camera_system_id_router
port map (
sink_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_001_src_ready, -- src.ready
src_valid => id_router_001_src_valid, -- .valid
src_data => id_router_001_src_data, -- .data
src_channel => id_router_001_src_channel, -- .channel
src_startofpacket => id_router_001_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_001_src_endofpacket -- .endofpacket
);
id_router_002 : component tracking_camera_system_id_router_002
port map (
sink_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_002_src_ready, -- src.ready
src_valid => id_router_002_src_valid, -- .valid
src_data => id_router_002_src_data, -- .data
src_channel => id_router_002_src_channel, -- .channel
src_startofpacket => id_router_002_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_002_src_endofpacket -- .endofpacket
);
id_router_003 : component tracking_camera_system_id_router_002
port map (
sink_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_003_src_ready, -- src.ready
src_valid => id_router_003_src_valid, -- .valid
src_data => id_router_003_src_data, -- .data
src_channel => id_router_003_src_channel, -- .channel
src_startofpacket => id_router_003_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_003_src_endofpacket -- .endofpacket
);
id_router_004 : component tracking_camera_system_id_router_004
port map (
sink_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_004_src_ready, -- src.ready
src_valid => id_router_004_src_valid, -- .valid
src_data => id_router_004_src_data, -- .data
src_channel => id_router_004_src_channel, -- .channel
src_startofpacket => id_router_004_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_004_src_endofpacket -- .endofpacket
);
id_router_005 : component tracking_camera_system_id_router_004
port map (
sink_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_005_src_ready, -- src.ready
src_valid => id_router_005_src_valid, -- .valid
src_data => id_router_005_src_data, -- .data
src_channel => id_router_005_src_channel, -- .channel
src_startofpacket => id_router_005_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_005_src_endofpacket -- .endofpacket
);
id_router_006 : component tracking_camera_system_id_router_004
port map (
sink_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_006_src_ready, -- src.ready
src_valid => id_router_006_src_valid, -- .valid
src_data => id_router_006_src_data, -- .data
src_channel => id_router_006_src_channel, -- .channel
src_startofpacket => id_router_006_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_006_src_endofpacket -- .endofpacket
);
id_router_007 : component tracking_camera_system_id_router_004
port map (
sink_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_007_src_ready, -- src.ready
src_valid => id_router_007_src_valid, -- .valid
src_data => id_router_007_src_data, -- .data
src_channel => id_router_007_src_channel, -- .channel
src_startofpacket => id_router_007_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_007_src_endofpacket -- .endofpacket
);
id_router_008 : component tracking_camera_system_id_router_008
port map (
sink_ready => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_008_src_ready, -- src.ready
src_valid => id_router_008_src_valid, -- .valid
src_data => id_router_008_src_data, -- .data
src_channel => id_router_008_src_channel, -- .channel
src_startofpacket => id_router_008_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_008_src_endofpacket -- .endofpacket
);
id_router_009 : component tracking_camera_system_id_router_004
port map (
sink_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_009_src_ready, -- src.ready
src_valid => id_router_009_src_valid, -- .valid
src_data => id_router_009_src_data, -- .data
src_channel => id_router_009_src_channel, -- .channel
src_startofpacket => id_router_009_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_009_src_endofpacket -- .endofpacket
);
id_router_010 : component tracking_camera_system_id_router_004
port map (
sink_ready => switch_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => switch_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => switch_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_010_src_ready, -- src.ready
src_valid => id_router_010_src_valid, -- .valid
src_data => id_router_010_src_data, -- .data
src_channel => id_router_010_src_channel, -- .channel
src_startofpacket => id_router_010_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_010_src_endofpacket -- .endofpacket
);
id_router_011 : component tracking_camera_system_id_router_008
port map (
sink_ready => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_011_src_ready, -- src.ready
src_valid => id_router_011_src_valid, -- .valid
src_data => id_router_011_src_data, -- .data
src_channel => id_router_011_src_channel, -- .channel
src_startofpacket => id_router_011_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_011_src_endofpacket -- .endofpacket
);
id_router_012 : component tracking_camera_system_id_router_004
port map (
sink_ready => switch_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => switch_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => switch_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_012_src_ready, -- src.ready
src_valid => id_router_012_src_valid, -- .valid
src_data => id_router_012_src_data, -- .data
src_channel => id_router_012_src_channel, -- .channel
src_startofpacket => id_router_012_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_012_src_endofpacket -- .endofpacket
);
limiter : component tracking_camera_system_limiter
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
cmd_sink_ready => addr_router_src_ready, -- cmd_sink.ready
cmd_sink_valid => addr_router_src_valid, -- .valid
cmd_sink_data => addr_router_src_data, -- .data
cmd_sink_channel => addr_router_src_channel, -- .channel
cmd_sink_startofpacket => addr_router_src_startofpacket, -- .startofpacket
cmd_sink_endofpacket => addr_router_src_endofpacket, -- .endofpacket
cmd_src_ready => limiter_cmd_src_ready, -- cmd_src.ready
cmd_src_data => limiter_cmd_src_data, -- .data
cmd_src_channel => limiter_cmd_src_channel, -- .channel
cmd_src_startofpacket => limiter_cmd_src_startofpacket, -- .startofpacket
cmd_src_endofpacket => limiter_cmd_src_endofpacket, -- .endofpacket
rsp_sink_ready => rsp_xbar_mux_src_ready, -- rsp_sink.ready
rsp_sink_valid => rsp_xbar_mux_src_valid, -- .valid
rsp_sink_channel => rsp_xbar_mux_src_channel, -- .channel
rsp_sink_data => rsp_xbar_mux_src_data, -- .data
rsp_sink_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket
rsp_sink_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket
rsp_src_ready => limiter_rsp_src_ready, -- rsp_src.ready
rsp_src_valid => limiter_rsp_src_valid, -- .valid
rsp_src_data => limiter_rsp_src_data, -- .data
rsp_src_channel => limiter_rsp_src_channel, -- .channel
rsp_src_startofpacket => limiter_rsp_src_startofpacket, -- .startofpacket
rsp_src_endofpacket => limiter_rsp_src_endofpacket, -- .endofpacket
cmd_src_valid => limiter_cmd_valid_data -- cmd_valid.data
);
limiter_001 : component tracking_camera_system_limiter
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
cmd_sink_ready => addr_router_001_src_ready, -- cmd_sink.ready
cmd_sink_valid => addr_router_001_src_valid, -- .valid
cmd_sink_data => addr_router_001_src_data, -- .data
cmd_sink_channel => addr_router_001_src_channel, -- .channel
cmd_sink_startofpacket => addr_router_001_src_startofpacket, -- .startofpacket
cmd_sink_endofpacket => addr_router_001_src_endofpacket, -- .endofpacket
cmd_src_ready => limiter_001_cmd_src_ready, -- cmd_src.ready
cmd_src_data => limiter_001_cmd_src_data, -- .data
cmd_src_channel => limiter_001_cmd_src_channel, -- .channel
cmd_src_startofpacket => limiter_001_cmd_src_startofpacket, -- .startofpacket
cmd_src_endofpacket => limiter_001_cmd_src_endofpacket, -- .endofpacket
rsp_sink_ready => rsp_xbar_mux_001_src_ready, -- rsp_sink.ready
rsp_sink_valid => rsp_xbar_mux_001_src_valid, -- .valid
rsp_sink_channel => rsp_xbar_mux_001_src_channel, -- .channel
rsp_sink_data => rsp_xbar_mux_001_src_data, -- .data
rsp_sink_startofpacket => rsp_xbar_mux_001_src_startofpacket, -- .startofpacket
rsp_sink_endofpacket => rsp_xbar_mux_001_src_endofpacket, -- .endofpacket
rsp_src_ready => limiter_001_rsp_src_ready, -- rsp_src.ready
rsp_src_valid => limiter_001_rsp_src_valid, -- .valid
rsp_src_data => limiter_001_rsp_src_data, -- .data
rsp_src_channel => limiter_001_rsp_src_channel, -- .channel
rsp_src_startofpacket => limiter_001_rsp_src_startofpacket, -- .startofpacket
rsp_src_endofpacket => limiter_001_rsp_src_endofpacket, -- .endofpacket
cmd_src_valid => limiter_001_cmd_valid_data -- cmd_valid.data
);
burst_adapter : component tracking_camera_system_burst_adapter
port map (
clk => altpll_0_c1_clk, -- cr0.clk
reset => rst_controller_reset_out_reset, -- cr0_reset.reset
sink0_valid => width_adapter_src_valid, -- sink0.valid
sink0_data => width_adapter_src_data, -- .data
sink0_channel => width_adapter_src_channel, -- .channel
sink0_startofpacket => width_adapter_src_startofpacket, -- .startofpacket
sink0_endofpacket => width_adapter_src_endofpacket, -- .endofpacket
sink0_ready => width_adapter_src_ready, -- .ready
source0_valid => burst_adapter_source0_valid, -- source0.valid
source0_data => burst_adapter_source0_data, -- .data
source0_channel => burst_adapter_source0_channel, -- .channel
source0_startofpacket => burst_adapter_source0_startofpacket, -- .startofpacket
source0_endofpacket => burst_adapter_source0_endofpacket, -- .endofpacket
source0_ready => burst_adapter_source0_ready -- .ready
);
burst_adapter_001 : component tracking_camera_system_burst_adapter
port map (
clk => altpll_0_c1_clk, -- cr0.clk
reset => rst_controller_reset_out_reset, -- cr0_reset.reset
sink0_valid => width_adapter_002_src_valid, -- sink0.valid
sink0_data => width_adapter_002_src_data, -- .data
sink0_channel => width_adapter_002_src_channel, -- .channel
sink0_startofpacket => width_adapter_002_src_startofpacket, -- .startofpacket
sink0_endofpacket => width_adapter_002_src_endofpacket, -- .endofpacket
sink0_ready => width_adapter_002_src_ready, -- .ready
source0_valid => burst_adapter_001_source0_valid, -- source0.valid
source0_data => burst_adapter_001_source0_data, -- .data
source0_channel => burst_adapter_001_source0_channel, -- .channel
source0_startofpacket => burst_adapter_001_source0_startofpacket, -- .startofpacket
source0_endofpacket => burst_adapter_001_source0_endofpacket, -- .endofpacket
source0_ready => burst_adapter_001_source0_ready -- .ready
);
burst_adapter_002 : component tracking_camera_system_burst_adapter_002
port map (
clk => altpll_0_c1_clk, -- cr0.clk
reset => rst_controller_reset_out_reset, -- cr0_reset.reset
sink0_valid => width_adapter_004_src_valid, -- sink0.valid
sink0_data => width_adapter_004_src_data, -- .data
sink0_channel => width_adapter_004_src_channel, -- .channel
sink0_startofpacket => width_adapter_004_src_startofpacket, -- .startofpacket
sink0_endofpacket => width_adapter_004_src_endofpacket, -- .endofpacket
sink0_ready => width_adapter_004_src_ready, -- .ready
source0_valid => burst_adapter_002_source0_valid, -- source0.valid
source0_data => burst_adapter_002_source0_data, -- .data
source0_channel => burst_adapter_002_source0_channel, -- .channel
source0_startofpacket => burst_adapter_002_source0_startofpacket, -- .startofpacket
source0_endofpacket => burst_adapter_002_source0_endofpacket, -- .endofpacket
source0_ready => burst_adapter_002_source0_ready -- .ready
);
burst_adapter_003 : component tracking_camera_system_burst_adapter_002
port map (
clk => altpll_0_c1_clk, -- cr0.clk
reset => rst_controller_reset_out_reset, -- cr0_reset.reset
sink0_valid => width_adapter_006_src_valid, -- sink0.valid
sink0_data => width_adapter_006_src_data, -- .data
sink0_channel => width_adapter_006_src_channel, -- .channel
sink0_startofpacket => width_adapter_006_src_startofpacket, -- .startofpacket
sink0_endofpacket => width_adapter_006_src_endofpacket, -- .endofpacket
sink0_ready => width_adapter_006_src_ready, -- .ready
source0_valid => burst_adapter_003_source0_valid, -- source0.valid
source0_data => burst_adapter_003_source0_data, -- .data
source0_channel => burst_adapter_003_source0_channel, -- .channel
source0_startofpacket => burst_adapter_003_source0_startofpacket, -- .startofpacket
source0_endofpacket => burst_adapter_003_source0_endofpacket, -- .endofpacket
source0_ready => burst_adapter_003_source0_ready -- .ready
);
rst_controller : component tracking_camera_system_rst_controller
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
reset_in1 => nios2_qsys_0_jtag_debug_module_reset_reset, -- reset_in1.reset
clk => altpll_0_c1_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset -- reset_out.reset
);
rst_controller_001 : component tracking_camera_system_rst_controller
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
reset_in1 => nios2_qsys_0_jtag_debug_module_reset_reset, -- reset_in1.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset -- reset_out.reset
);
cmd_xbar_demux : component tracking_camera_system_cmd_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => limiter_cmd_src_ready, -- sink.ready
sink_channel => limiter_cmd_src_channel, -- .channel
sink_data => limiter_cmd_src_data, -- .data
sink_startofpacket => limiter_cmd_src_startofpacket, -- .startofpacket
sink_endofpacket => limiter_cmd_src_endofpacket, -- .endofpacket
sink_valid => limiter_cmd_valid_data, -- sink_valid.data
src0_ready => cmd_xbar_demux_src0_ready, -- src0.ready
src0_valid => cmd_xbar_demux_src0_valid, -- .valid
src0_data => cmd_xbar_demux_src0_data, -- .data
src0_channel => cmd_xbar_demux_src0_channel, -- .channel
src0_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket
src0_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket
src1_ready => cmd_xbar_demux_src1_ready, -- src1.ready
src1_valid => cmd_xbar_demux_src1_valid, -- .valid
src1_data => cmd_xbar_demux_src1_data, -- .data
src1_channel => cmd_xbar_demux_src1_channel, -- .channel
src1_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket
src1_endofpacket => cmd_xbar_demux_src1_endofpacket, -- .endofpacket
src2_ready => cmd_xbar_demux_src2_ready, -- src2.ready
src2_valid => cmd_xbar_demux_src2_valid, -- .valid
src2_data => cmd_xbar_demux_src2_data, -- .data
src2_channel => cmd_xbar_demux_src2_channel, -- .channel
src2_startofpacket => cmd_xbar_demux_src2_startofpacket, -- .startofpacket
src2_endofpacket => cmd_xbar_demux_src2_endofpacket, -- .endofpacket
src3_ready => cmd_xbar_demux_src3_ready, -- src3.ready
src3_valid => cmd_xbar_demux_src3_valid, -- .valid
src3_data => cmd_xbar_demux_src3_data, -- .data
src3_channel => cmd_xbar_demux_src3_channel, -- .channel
src3_startofpacket => cmd_xbar_demux_src3_startofpacket, -- .startofpacket
src3_endofpacket => cmd_xbar_demux_src3_endofpacket -- .endofpacket
);
cmd_xbar_demux_001 : component tracking_camera_system_cmd_xbar_demux_001
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => limiter_001_cmd_src_ready, -- sink.ready
sink_channel => limiter_001_cmd_src_channel, -- .channel
sink_data => limiter_001_cmd_src_data, -- .data
sink_startofpacket => limiter_001_cmd_src_startofpacket, -- .startofpacket
sink_endofpacket => limiter_001_cmd_src_endofpacket, -- .endofpacket
sink_valid => limiter_001_cmd_valid_data, -- sink_valid.data
src0_ready => cmd_xbar_demux_001_src0_ready, -- src0.ready
src0_valid => cmd_xbar_demux_001_src0_valid, -- .valid
src0_data => cmd_xbar_demux_001_src0_data, -- .data
src0_channel => cmd_xbar_demux_001_src0_channel, -- .channel
src0_startofpacket => cmd_xbar_demux_001_src0_startofpacket, -- .startofpacket
src0_endofpacket => cmd_xbar_demux_001_src0_endofpacket, -- .endofpacket
src1_ready => cmd_xbar_demux_001_src1_ready, -- src1.ready
src1_valid => cmd_xbar_demux_001_src1_valid, -- .valid
src1_data => cmd_xbar_demux_001_src1_data, -- .data
src1_channel => cmd_xbar_demux_001_src1_channel, -- .channel
src1_startofpacket => cmd_xbar_demux_001_src1_startofpacket, -- .startofpacket
src1_endofpacket => cmd_xbar_demux_001_src1_endofpacket, -- .endofpacket
src2_ready => cmd_xbar_demux_001_src2_ready, -- src2.ready
src2_valid => cmd_xbar_demux_001_src2_valid, -- .valid
src2_data => cmd_xbar_demux_001_src2_data, -- .data
src2_channel => cmd_xbar_demux_001_src2_channel, -- .channel
src2_startofpacket => cmd_xbar_demux_001_src2_startofpacket, -- .startofpacket
src2_endofpacket => cmd_xbar_demux_001_src2_endofpacket, -- .endofpacket
src3_ready => cmd_xbar_demux_001_src3_ready, -- src3.ready
src3_valid => cmd_xbar_demux_001_src3_valid, -- .valid
src3_data => cmd_xbar_demux_001_src3_data, -- .data
src3_channel => cmd_xbar_demux_001_src3_channel, -- .channel
src3_startofpacket => cmd_xbar_demux_001_src3_startofpacket, -- .startofpacket
src3_endofpacket => cmd_xbar_demux_001_src3_endofpacket, -- .endofpacket
src4_ready => cmd_xbar_demux_001_src4_ready, -- src4.ready
src4_valid => cmd_xbar_demux_001_src4_valid, -- .valid
src4_data => cmd_xbar_demux_001_src4_data, -- .data
src4_channel => cmd_xbar_demux_001_src4_channel, -- .channel
src4_startofpacket => cmd_xbar_demux_001_src4_startofpacket, -- .startofpacket
src4_endofpacket => cmd_xbar_demux_001_src4_endofpacket, -- .endofpacket
src5_ready => cmd_xbar_demux_001_src5_ready, -- src5.ready
src5_valid => cmd_xbar_demux_001_src5_valid, -- .valid
src5_data => cmd_xbar_demux_001_src5_data, -- .data
src5_channel => cmd_xbar_demux_001_src5_channel, -- .channel
src5_startofpacket => cmd_xbar_demux_001_src5_startofpacket, -- .startofpacket
src5_endofpacket => cmd_xbar_demux_001_src5_endofpacket, -- .endofpacket
src6_ready => cmd_xbar_demux_001_src6_ready, -- src6.ready
src6_valid => cmd_xbar_demux_001_src6_valid, -- .valid
src6_data => cmd_xbar_demux_001_src6_data, -- .data
src6_channel => cmd_xbar_demux_001_src6_channel, -- .channel
src6_startofpacket => cmd_xbar_demux_001_src6_startofpacket, -- .startofpacket
src6_endofpacket => cmd_xbar_demux_001_src6_endofpacket, -- .endofpacket
src7_ready => cmd_xbar_demux_001_src7_ready, -- src7.ready
src7_valid => cmd_xbar_demux_001_src7_valid, -- .valid
src7_data => cmd_xbar_demux_001_src7_data, -- .data
src7_channel => cmd_xbar_demux_001_src7_channel, -- .channel
src7_startofpacket => cmd_xbar_demux_001_src7_startofpacket, -- .startofpacket
src7_endofpacket => cmd_xbar_demux_001_src7_endofpacket, -- .endofpacket
src8_ready => cmd_xbar_demux_001_src8_ready, -- src8.ready
src8_valid => cmd_xbar_demux_001_src8_valid, -- .valid
src8_data => cmd_xbar_demux_001_src8_data, -- .data
src8_channel => cmd_xbar_demux_001_src8_channel, -- .channel
src8_startofpacket => cmd_xbar_demux_001_src8_startofpacket, -- .startofpacket
src8_endofpacket => cmd_xbar_demux_001_src8_endofpacket, -- .endofpacket
src9_ready => cmd_xbar_demux_001_src9_ready, -- src9.ready
src9_valid => cmd_xbar_demux_001_src9_valid, -- .valid
src9_data => cmd_xbar_demux_001_src9_data, -- .data
src9_channel => cmd_xbar_demux_001_src9_channel, -- .channel
src9_startofpacket => cmd_xbar_demux_001_src9_startofpacket, -- .startofpacket
src9_endofpacket => cmd_xbar_demux_001_src9_endofpacket, -- .endofpacket
src10_ready => cmd_xbar_demux_001_src10_ready, -- src10.ready
src10_valid => cmd_xbar_demux_001_src10_valid, -- .valid
src10_data => cmd_xbar_demux_001_src10_data, -- .data
src10_channel => cmd_xbar_demux_001_src10_channel, -- .channel
src10_startofpacket => cmd_xbar_demux_001_src10_startofpacket, -- .startofpacket
src10_endofpacket => cmd_xbar_demux_001_src10_endofpacket, -- .endofpacket
src11_ready => cmd_xbar_demux_001_src11_ready, -- src11.ready
src11_valid => cmd_xbar_demux_001_src11_valid, -- .valid
src11_data => cmd_xbar_demux_001_src11_data, -- .data
src11_channel => cmd_xbar_demux_001_src11_channel, -- .channel
src11_startofpacket => cmd_xbar_demux_001_src11_startofpacket, -- .startofpacket
src11_endofpacket => cmd_xbar_demux_001_src11_endofpacket, -- .endofpacket
src12_ready => cmd_xbar_demux_001_src12_ready, -- src12.ready
src12_valid => cmd_xbar_demux_001_src12_valid, -- .valid
src12_data => cmd_xbar_demux_001_src12_data, -- .data
src12_channel => cmd_xbar_demux_001_src12_channel, -- .channel
src12_startofpacket => cmd_xbar_demux_001_src12_startofpacket, -- .startofpacket
src12_endofpacket => cmd_xbar_demux_001_src12_endofpacket -- .endofpacket
);
cmd_xbar_mux : component tracking_camera_system_cmd_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_src_ready, -- src.ready
src_valid => cmd_xbar_mux_src_valid, -- .valid
src_data => cmd_xbar_mux_src_data, -- .data
src_channel => cmd_xbar_mux_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src0_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src0_valid, -- .valid
sink0_channel => cmd_xbar_demux_src0_channel, -- .channel
sink0_data => cmd_xbar_demux_src0_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src0_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src0_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src0_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src0_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src0_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src0_endofpacket -- .endofpacket
);
cmd_xbar_mux_001 : component tracking_camera_system_cmd_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_001_src_ready, -- src.ready
src_valid => cmd_xbar_mux_001_src_valid, -- .valid
src_data => cmd_xbar_mux_001_src_data, -- .data
src_channel => cmd_xbar_mux_001_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_001_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_001_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src1_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src1_valid, -- .valid
sink0_channel => cmd_xbar_demux_src1_channel, -- .channel
sink0_data => cmd_xbar_demux_src1_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src1_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src1_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src1_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src1_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src1_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src1_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src1_endofpacket -- .endofpacket
);
cmd_xbar_mux_002 : component tracking_camera_system_cmd_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_002_src_ready, -- src.ready
src_valid => cmd_xbar_mux_002_src_valid, -- .valid
src_data => cmd_xbar_mux_002_src_data, -- .data
src_channel => cmd_xbar_mux_002_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_002_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_002_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src2_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src2_valid, -- .valid
sink0_channel => cmd_xbar_demux_src2_channel, -- .channel
sink0_data => cmd_xbar_demux_src2_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src2_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src2_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src2_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src2_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src2_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src2_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src2_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src2_endofpacket -- .endofpacket
);
cmd_xbar_mux_003 : component tracking_camera_system_cmd_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_003_src_ready, -- src.ready
src_valid => cmd_xbar_mux_003_src_valid, -- .valid
src_data => cmd_xbar_mux_003_src_data, -- .data
src_channel => cmd_xbar_mux_003_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_003_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_003_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src3_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src3_valid, -- .valid
sink0_channel => cmd_xbar_demux_src3_channel, -- .channel
sink0_data => cmd_xbar_demux_src3_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src3_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src3_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src3_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src3_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src3_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src3_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src3_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src3_endofpacket -- .endofpacket
);
rsp_xbar_demux : component tracking_camera_system_rsp_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_src_ready, -- sink.ready
sink_channel => id_router_src_channel, -- .channel
sink_data => id_router_src_data, -- .data
sink_startofpacket => id_router_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_src_valid, -- .valid
src0_ready => rsp_xbar_demux_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_src0_valid, -- .valid
src0_data => rsp_xbar_demux_src0_data, -- .data
src0_channel => rsp_xbar_demux_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_src1_valid, -- .valid
src1_data => rsp_xbar_demux_src1_data, -- .data
src1_channel => rsp_xbar_demux_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_001 : component tracking_camera_system_rsp_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_001_src_ready, -- sink.ready
sink_channel => id_router_001_src_channel, -- .channel
sink_data => id_router_001_src_data, -- .data
sink_startofpacket => id_router_001_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_001_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_001_src_valid, -- .valid
src0_ready => rsp_xbar_demux_001_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_001_src0_valid, -- .valid
src0_data => rsp_xbar_demux_001_src0_data, -- .data
src0_channel => rsp_xbar_demux_001_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_001_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_001_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_001_src1_valid, -- .valid
src1_data => rsp_xbar_demux_001_src1_data, -- .data
src1_channel => rsp_xbar_demux_001_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_001_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_001_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_002 : component tracking_camera_system_rsp_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_001_src_ready, -- sink.ready
sink_channel => width_adapter_001_src_channel, -- .channel
sink_data => width_adapter_001_src_data, -- .data
sink_startofpacket => width_adapter_001_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_001_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_001_src_valid, -- .valid
src0_ready => rsp_xbar_demux_002_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_002_src0_valid, -- .valid
src0_data => rsp_xbar_demux_002_src0_data, -- .data
src0_channel => rsp_xbar_demux_002_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_002_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_002_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_002_src1_valid, -- .valid
src1_data => rsp_xbar_demux_002_src1_data, -- .data
src1_channel => rsp_xbar_demux_002_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_002_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_002_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_003 : component tracking_camera_system_rsp_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_003_src_ready, -- sink.ready
sink_channel => width_adapter_003_src_channel, -- .channel
sink_data => width_adapter_003_src_data, -- .data
sink_startofpacket => width_adapter_003_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_003_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_003_src_valid, -- .valid
src0_ready => rsp_xbar_demux_003_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_003_src0_valid, -- .valid
src0_data => rsp_xbar_demux_003_src0_data, -- .data
src0_channel => rsp_xbar_demux_003_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_003_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_003_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_003_src1_valid, -- .valid
src1_data => rsp_xbar_demux_003_src1_data, -- .data
src1_channel => rsp_xbar_demux_003_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_003_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_003_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_004 : component tracking_camera_system_rsp_xbar_demux_004
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_004_src_ready, -- sink.ready
sink_channel => id_router_004_src_channel, -- .channel
sink_data => id_router_004_src_data, -- .data
sink_startofpacket => id_router_004_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_004_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_004_src_valid, -- .valid
src0_ready => rsp_xbar_demux_004_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_004_src0_valid, -- .valid
src0_data => rsp_xbar_demux_004_src0_data, -- .data
src0_channel => rsp_xbar_demux_004_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_004_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_005 : component tracking_camera_system_rsp_xbar_demux_004
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_005_src_ready, -- sink.ready
sink_channel => id_router_005_src_channel, -- .channel
sink_data => id_router_005_src_data, -- .data
sink_startofpacket => id_router_005_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_005_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_005_src_valid, -- .valid
src0_ready => rsp_xbar_demux_005_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_005_src0_valid, -- .valid
src0_data => rsp_xbar_demux_005_src0_data, -- .data
src0_channel => rsp_xbar_demux_005_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_005_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_006 : component tracking_camera_system_rsp_xbar_demux_004
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_006_src_ready, -- sink.ready
sink_channel => id_router_006_src_channel, -- .channel
sink_data => id_router_006_src_data, -- .data
sink_startofpacket => id_router_006_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_006_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_006_src_valid, -- .valid
src0_ready => rsp_xbar_demux_006_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_006_src0_valid, -- .valid
src0_data => rsp_xbar_demux_006_src0_data, -- .data
src0_channel => rsp_xbar_demux_006_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_006_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_006_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_007 : component tracking_camera_system_rsp_xbar_demux_004
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_007_src_ready, -- sink.ready
sink_channel => id_router_007_src_channel, -- .channel
sink_data => id_router_007_src_data, -- .data
sink_startofpacket => id_router_007_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_007_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_007_src_valid, -- .valid
src0_ready => rsp_xbar_demux_007_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_007_src0_valid, -- .valid
src0_data => rsp_xbar_demux_007_src0_data, -- .data
src0_channel => rsp_xbar_demux_007_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_007_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_007_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_008 : component tracking_camera_system_rsp_xbar_demux_004
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_005_src_ready, -- sink.ready
sink_channel => width_adapter_005_src_channel, -- .channel
sink_data => width_adapter_005_src_data, -- .data
sink_startofpacket => width_adapter_005_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_005_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_005_src_valid, -- .valid
src0_ready => rsp_xbar_demux_008_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_008_src0_valid, -- .valid
src0_data => rsp_xbar_demux_008_src0_data, -- .data
src0_channel => rsp_xbar_demux_008_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_008_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_008_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_009 : component tracking_camera_system_rsp_xbar_demux_004
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_009_src_ready, -- sink.ready
sink_channel => id_router_009_src_channel, -- .channel
sink_data => id_router_009_src_data, -- .data
sink_startofpacket => id_router_009_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_009_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_009_src_valid, -- .valid
src0_ready => rsp_xbar_demux_009_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_009_src0_valid, -- .valid
src0_data => rsp_xbar_demux_009_src0_data, -- .data
src0_channel => rsp_xbar_demux_009_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_009_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_009_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_010 : component tracking_camera_system_rsp_xbar_demux_004
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_010_src_ready, -- sink.ready
sink_channel => id_router_010_src_channel, -- .channel
sink_data => id_router_010_src_data, -- .data
sink_startofpacket => id_router_010_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_010_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_010_src_valid, -- .valid
src0_ready => rsp_xbar_demux_010_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_010_src0_valid, -- .valid
src0_data => rsp_xbar_demux_010_src0_data, -- .data
src0_channel => rsp_xbar_demux_010_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_010_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_010_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_011 : component tracking_camera_system_rsp_xbar_demux_004
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_007_src_ready, -- sink.ready
sink_channel => width_adapter_007_src_channel, -- .channel
sink_data => width_adapter_007_src_data, -- .data
sink_startofpacket => width_adapter_007_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_007_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_007_src_valid, -- .valid
src0_ready => rsp_xbar_demux_011_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_011_src0_valid, -- .valid
src0_data => rsp_xbar_demux_011_src0_data, -- .data
src0_channel => rsp_xbar_demux_011_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_011_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_011_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_012 : component tracking_camera_system_rsp_xbar_demux_004
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_012_src_ready, -- sink.ready
sink_channel => id_router_012_src_channel, -- .channel
sink_data => id_router_012_src_data, -- .data
sink_startofpacket => id_router_012_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_012_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_012_src_valid, -- .valid
src0_ready => rsp_xbar_demux_012_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_012_src0_valid, -- .valid
src0_data => rsp_xbar_demux_012_src0_data, -- .data
src0_channel => rsp_xbar_demux_012_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_012_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_012_src0_endofpacket -- .endofpacket
);
rsp_xbar_mux : component tracking_camera_system_rsp_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => rsp_xbar_mux_src_ready, -- src.ready
src_valid => rsp_xbar_mux_src_valid, -- .valid
src_data => rsp_xbar_mux_src_data, -- .data
src_channel => rsp_xbar_mux_src_channel, -- .channel
src_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket
src_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket
sink0_ready => rsp_xbar_demux_src0_ready, -- sink0.ready
sink0_valid => rsp_xbar_demux_src0_valid, -- .valid
sink0_channel => rsp_xbar_demux_src0_channel, -- .channel
sink0_data => rsp_xbar_demux_src0_data, -- .data
sink0_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket
sink0_endofpacket => rsp_xbar_demux_src0_endofpacket, -- .endofpacket
sink1_ready => rsp_xbar_demux_001_src0_ready, -- sink1.ready
sink1_valid => rsp_xbar_demux_001_src0_valid, -- .valid
sink1_channel => rsp_xbar_demux_001_src0_channel, -- .channel
sink1_data => rsp_xbar_demux_001_src0_data, -- .data
sink1_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket
sink1_endofpacket => rsp_xbar_demux_001_src0_endofpacket, -- .endofpacket
sink2_ready => rsp_xbar_demux_002_src0_ready, -- sink2.ready
sink2_valid => rsp_xbar_demux_002_src0_valid, -- .valid
sink2_channel => rsp_xbar_demux_002_src0_channel, -- .channel
sink2_data => rsp_xbar_demux_002_src0_data, -- .data
sink2_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket
sink2_endofpacket => rsp_xbar_demux_002_src0_endofpacket, -- .endofpacket
sink3_ready => rsp_xbar_demux_003_src0_ready, -- sink3.ready
sink3_valid => rsp_xbar_demux_003_src0_valid, -- .valid
sink3_channel => rsp_xbar_demux_003_src0_channel, -- .channel
sink3_data => rsp_xbar_demux_003_src0_data, -- .data
sink3_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket
sink3_endofpacket => rsp_xbar_demux_003_src0_endofpacket -- .endofpacket
);
rsp_xbar_mux_001 : component tracking_camera_system_rsp_xbar_mux_001
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => rsp_xbar_mux_001_src_ready, -- src.ready
src_valid => rsp_xbar_mux_001_src_valid, -- .valid
src_data => rsp_xbar_mux_001_src_data, -- .data
src_channel => rsp_xbar_mux_001_src_channel, -- .channel
src_startofpacket => rsp_xbar_mux_001_src_startofpacket, -- .startofpacket
src_endofpacket => rsp_xbar_mux_001_src_endofpacket, -- .endofpacket
sink0_ready => rsp_xbar_demux_src1_ready, -- sink0.ready
sink0_valid => rsp_xbar_demux_src1_valid, -- .valid
sink0_channel => rsp_xbar_demux_src1_channel, -- .channel
sink0_data => rsp_xbar_demux_src1_data, -- .data
sink0_startofpacket => rsp_xbar_demux_src1_startofpacket, -- .startofpacket
sink0_endofpacket => rsp_xbar_demux_src1_endofpacket, -- .endofpacket
sink1_ready => rsp_xbar_demux_001_src1_ready, -- sink1.ready
sink1_valid => rsp_xbar_demux_001_src1_valid, -- .valid
sink1_channel => rsp_xbar_demux_001_src1_channel, -- .channel
sink1_data => rsp_xbar_demux_001_src1_data, -- .data
sink1_startofpacket => rsp_xbar_demux_001_src1_startofpacket, -- .startofpacket
sink1_endofpacket => rsp_xbar_demux_001_src1_endofpacket, -- .endofpacket
sink2_ready => rsp_xbar_demux_002_src1_ready, -- sink2.ready
sink2_valid => rsp_xbar_demux_002_src1_valid, -- .valid
sink2_channel => rsp_xbar_demux_002_src1_channel, -- .channel
sink2_data => rsp_xbar_demux_002_src1_data, -- .data
sink2_startofpacket => rsp_xbar_demux_002_src1_startofpacket, -- .startofpacket
sink2_endofpacket => rsp_xbar_demux_002_src1_endofpacket, -- .endofpacket
sink3_ready => rsp_xbar_demux_003_src1_ready, -- sink3.ready
sink3_valid => rsp_xbar_demux_003_src1_valid, -- .valid
sink3_channel => rsp_xbar_demux_003_src1_channel, -- .channel
sink3_data => rsp_xbar_demux_003_src1_data, -- .data
sink3_startofpacket => rsp_xbar_demux_003_src1_startofpacket, -- .startofpacket
sink3_endofpacket => rsp_xbar_demux_003_src1_endofpacket, -- .endofpacket
sink4_ready => crosser_001_out_ready, -- sink4.ready
sink4_valid => crosser_001_out_valid, -- .valid
sink4_channel => crosser_001_out_channel, -- .channel
sink4_data => crosser_001_out_data, -- .data
sink4_startofpacket => crosser_001_out_startofpacket, -- .startofpacket
sink4_endofpacket => crosser_001_out_endofpacket, -- .endofpacket
sink5_ready => rsp_xbar_demux_005_src0_ready, -- sink5.ready
sink5_valid => rsp_xbar_demux_005_src0_valid, -- .valid
sink5_channel => rsp_xbar_demux_005_src0_channel, -- .channel
sink5_data => rsp_xbar_demux_005_src0_data, -- .data
sink5_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket
sink5_endofpacket => rsp_xbar_demux_005_src0_endofpacket, -- .endofpacket
sink6_ready => rsp_xbar_demux_006_src0_ready, -- sink6.ready
sink6_valid => rsp_xbar_demux_006_src0_valid, -- .valid
sink6_channel => rsp_xbar_demux_006_src0_channel, -- .channel
sink6_data => rsp_xbar_demux_006_src0_data, -- .data
sink6_startofpacket => rsp_xbar_demux_006_src0_startofpacket, -- .startofpacket
sink6_endofpacket => rsp_xbar_demux_006_src0_endofpacket, -- .endofpacket
sink7_ready => rsp_xbar_demux_007_src0_ready, -- sink7.ready
sink7_valid => rsp_xbar_demux_007_src0_valid, -- .valid
sink7_channel => rsp_xbar_demux_007_src0_channel, -- .channel
sink7_data => rsp_xbar_demux_007_src0_data, -- .data
sink7_startofpacket => rsp_xbar_demux_007_src0_startofpacket, -- .startofpacket
sink7_endofpacket => rsp_xbar_demux_007_src0_endofpacket, -- .endofpacket
sink8_ready => rsp_xbar_demux_008_src0_ready, -- sink8.ready
sink8_valid => rsp_xbar_demux_008_src0_valid, -- .valid
sink8_channel => rsp_xbar_demux_008_src0_channel, -- .channel
sink8_data => rsp_xbar_demux_008_src0_data, -- .data
sink8_startofpacket => rsp_xbar_demux_008_src0_startofpacket, -- .startofpacket
sink8_endofpacket => rsp_xbar_demux_008_src0_endofpacket, -- .endofpacket
sink9_ready => rsp_xbar_demux_009_src0_ready, -- sink9.ready
sink9_valid => rsp_xbar_demux_009_src0_valid, -- .valid
sink9_channel => rsp_xbar_demux_009_src0_channel, -- .channel
sink9_data => rsp_xbar_demux_009_src0_data, -- .data
sink9_startofpacket => rsp_xbar_demux_009_src0_startofpacket, -- .startofpacket
sink9_endofpacket => rsp_xbar_demux_009_src0_endofpacket, -- .endofpacket
sink10_ready => rsp_xbar_demux_010_src0_ready, -- sink10.ready
sink10_valid => rsp_xbar_demux_010_src0_valid, -- .valid
sink10_channel => rsp_xbar_demux_010_src0_channel, -- .channel
sink10_data => rsp_xbar_demux_010_src0_data, -- .data
sink10_startofpacket => rsp_xbar_demux_010_src0_startofpacket, -- .startofpacket
sink10_endofpacket => rsp_xbar_demux_010_src0_endofpacket, -- .endofpacket
sink11_ready => rsp_xbar_demux_011_src0_ready, -- sink11.ready
sink11_valid => rsp_xbar_demux_011_src0_valid, -- .valid
sink11_channel => rsp_xbar_demux_011_src0_channel, -- .channel
sink11_data => rsp_xbar_demux_011_src0_data, -- .data
sink11_startofpacket => rsp_xbar_demux_011_src0_startofpacket, -- .startofpacket
sink11_endofpacket => rsp_xbar_demux_011_src0_endofpacket, -- .endofpacket
sink12_ready => rsp_xbar_demux_012_src0_ready, -- sink12.ready
sink12_valid => rsp_xbar_demux_012_src0_valid, -- .valid
sink12_channel => rsp_xbar_demux_012_src0_channel, -- .channel
sink12_data => rsp_xbar_demux_012_src0_data, -- .data
sink12_startofpacket => rsp_xbar_demux_012_src0_startofpacket, -- .startofpacket
sink12_endofpacket => rsp_xbar_demux_012_src0_endofpacket -- .endofpacket
);
width_adapter : component tracking_camera_system_width_adapter
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_mux_002_src_valid, -- sink.valid
in_channel => cmd_xbar_mux_002_src_channel, -- .channel
in_startofpacket => cmd_xbar_mux_002_src_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_mux_002_src_endofpacket, -- .endofpacket
in_ready => cmd_xbar_mux_002_src_ready, -- .ready
in_data => cmd_xbar_mux_002_src_data, -- .data
out_endofpacket => width_adapter_src_endofpacket, -- src.endofpacket
out_data => width_adapter_src_data, -- .data
out_channel => width_adapter_src_channel, -- .channel
out_valid => width_adapter_src_valid, -- .valid
out_ready => width_adapter_src_ready, -- .ready
out_startofpacket => width_adapter_src_startofpacket -- .startofpacket
);
width_adapter_001 : component tracking_camera_system_width_adapter_001
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => id_router_002_src_valid, -- sink.valid
in_channel => id_router_002_src_channel, -- .channel
in_startofpacket => id_router_002_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_002_src_endofpacket, -- .endofpacket
in_ready => id_router_002_src_ready, -- .ready
in_data => id_router_002_src_data, -- .data
out_endofpacket => width_adapter_001_src_endofpacket, -- src.endofpacket
out_data => width_adapter_001_src_data, -- .data
out_channel => width_adapter_001_src_channel, -- .channel
out_valid => width_adapter_001_src_valid, -- .valid
out_ready => width_adapter_001_src_ready, -- .ready
out_startofpacket => width_adapter_001_src_startofpacket -- .startofpacket
);
width_adapter_002 : component tracking_camera_system_width_adapter
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_mux_003_src_valid, -- sink.valid
in_channel => cmd_xbar_mux_003_src_channel, -- .channel
in_startofpacket => cmd_xbar_mux_003_src_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_mux_003_src_endofpacket, -- .endofpacket
in_ready => cmd_xbar_mux_003_src_ready, -- .ready
in_data => cmd_xbar_mux_003_src_data, -- .data
out_endofpacket => width_adapter_002_src_endofpacket, -- src.endofpacket
out_data => width_adapter_002_src_data, -- .data
out_channel => width_adapter_002_src_channel, -- .channel
out_valid => width_adapter_002_src_valid, -- .valid
out_ready => width_adapter_002_src_ready, -- .ready
out_startofpacket => width_adapter_002_src_startofpacket -- .startofpacket
);
width_adapter_003 : component tracking_camera_system_width_adapter_001
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => id_router_003_src_valid, -- sink.valid
in_channel => id_router_003_src_channel, -- .channel
in_startofpacket => id_router_003_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_003_src_endofpacket, -- .endofpacket
in_ready => id_router_003_src_ready, -- .ready
in_data => id_router_003_src_data, -- .data
out_endofpacket => width_adapter_003_src_endofpacket, -- src.endofpacket
out_data => width_adapter_003_src_data, -- .data
out_channel => width_adapter_003_src_channel, -- .channel
out_valid => width_adapter_003_src_valid, -- .valid
out_ready => width_adapter_003_src_ready, -- .ready
out_startofpacket => width_adapter_003_src_startofpacket -- .startofpacket
);
width_adapter_004 : component tracking_camera_system_width_adapter_004
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_001_src8_valid, -- sink.valid
in_channel => cmd_xbar_demux_001_src8_channel, -- .channel
in_startofpacket => cmd_xbar_demux_001_src8_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_001_src8_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_001_src8_ready, -- .ready
in_data => cmd_xbar_demux_001_src8_data, -- .data
out_endofpacket => width_adapter_004_src_endofpacket, -- src.endofpacket
out_data => width_adapter_004_src_data, -- .data
out_channel => width_adapter_004_src_channel, -- .channel
out_valid => width_adapter_004_src_valid, -- .valid
out_ready => width_adapter_004_src_ready, -- .ready
out_startofpacket => width_adapter_004_src_startofpacket -- .startofpacket
);
width_adapter_005 : component tracking_camera_system_width_adapter_005
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => id_router_008_src_valid, -- sink.valid
in_channel => id_router_008_src_channel, -- .channel
in_startofpacket => id_router_008_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_008_src_endofpacket, -- .endofpacket
in_ready => id_router_008_src_ready, -- .ready
in_data => id_router_008_src_data, -- .data
out_endofpacket => width_adapter_005_src_endofpacket, -- src.endofpacket
out_data => width_adapter_005_src_data, -- .data
out_channel => width_adapter_005_src_channel, -- .channel
out_valid => width_adapter_005_src_valid, -- .valid
out_ready => width_adapter_005_src_ready, -- .ready
out_startofpacket => width_adapter_005_src_startofpacket -- .startofpacket
);
width_adapter_006 : component tracking_camera_system_width_adapter_004
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_001_src11_valid, -- sink.valid
in_channel => cmd_xbar_demux_001_src11_channel, -- .channel
in_startofpacket => cmd_xbar_demux_001_src11_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_001_src11_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_001_src11_ready, -- .ready
in_data => cmd_xbar_demux_001_src11_data, -- .data
out_endofpacket => width_adapter_006_src_endofpacket, -- src.endofpacket
out_data => width_adapter_006_src_data, -- .data
out_channel => width_adapter_006_src_channel, -- .channel
out_valid => width_adapter_006_src_valid, -- .valid
out_ready => width_adapter_006_src_ready, -- .ready
out_startofpacket => width_adapter_006_src_startofpacket -- .startofpacket
);
width_adapter_007 : component tracking_camera_system_width_adapter_005
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => id_router_011_src_valid, -- sink.valid
in_channel => id_router_011_src_channel, -- .channel
in_startofpacket => id_router_011_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_011_src_endofpacket, -- .endofpacket
in_ready => id_router_011_src_ready, -- .ready
in_data => id_router_011_src_data, -- .data
out_endofpacket => width_adapter_007_src_endofpacket, -- src.endofpacket
out_data => width_adapter_007_src_data, -- .data
out_channel => width_adapter_007_src_channel, -- .channel
out_valid => width_adapter_007_src_valid, -- .valid
out_ready => width_adapter_007_src_ready, -- .ready
out_startofpacket => width_adapter_007_src_startofpacket -- .startofpacket
);
crosser : component tracking_camera_system_crosser
port map (
in_clk => altpll_0_c1_clk, -- in_clk.clk
in_reset => rst_controller_reset_out_reset, -- in_clk_reset.reset
out_clk => clk_clk, -- out_clk.clk
out_reset => rst_controller_001_reset_out_reset, -- out_clk_reset.reset
in_ready => cmd_xbar_demux_001_src4_ready, -- in.ready
in_valid => cmd_xbar_demux_001_src4_valid, -- .valid
in_startofpacket => cmd_xbar_demux_001_src4_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_001_src4_endofpacket, -- .endofpacket
in_channel => cmd_xbar_demux_001_src4_channel, -- .channel
in_data => cmd_xbar_demux_001_src4_data, -- .data
out_ready => crosser_out_ready, -- out.ready
out_valid => crosser_out_valid, -- .valid
out_startofpacket => crosser_out_startofpacket, -- .startofpacket
out_endofpacket => crosser_out_endofpacket, -- .endofpacket
out_channel => crosser_out_channel, -- .channel
out_data => crosser_out_data -- .data
);
crosser_001 : component tracking_camera_system_crosser
port map (
in_clk => clk_clk, -- in_clk.clk
in_reset => rst_controller_001_reset_out_reset, -- in_clk_reset.reset
out_clk => altpll_0_c1_clk, -- out_clk.clk
out_reset => rst_controller_reset_out_reset, -- out_clk_reset.reset
in_ready => rsp_xbar_demux_004_src0_ready, -- in.ready
in_valid => rsp_xbar_demux_004_src0_valid, -- .valid
in_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket
in_endofpacket => rsp_xbar_demux_004_src0_endofpacket, -- .endofpacket
in_channel => rsp_xbar_demux_004_src0_channel, -- .channel
in_data => rsp_xbar_demux_004_src0_data, -- .data
out_ready => crosser_001_out_ready, -- out.ready
out_valid => crosser_001_out_valid, -- .valid
out_startofpacket => crosser_001_out_startofpacket, -- .startofpacket
out_endofpacket => crosser_001_out_endofpacket, -- .endofpacket
out_channel => crosser_001_out_channel, -- .channel
out_data => crosser_001_out_data -- .data
);
irq_mapper : component tracking_camera_system_irq_mapper
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq
sender_irq => nios2_qsys_0_d_irq_irq -- sender.irq
);
reset_reset_n_ports_inv <= not reset_reset_n;
sdram_0_s1_translator_avalon_anti_slave_0_write_ports_inv <= not sdram_0_s1_translator_avalon_anti_slave_0_write;
sdram_0_s1_translator_avalon_anti_slave_0_read_ports_inv <= not sdram_0_s1_translator_avalon_anti_slave_0_read;
sdram_0_s1_translator_avalon_anti_slave_0_byteenable_ports_inv <= not sdram_0_s1_translator_avalon_anti_slave_0_byteenable;
timer_0_s1_translator_avalon_anti_slave_0_write_ports_inv <= not timer_0_s1_translator_avalon_anti_slave_0_write;
jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write_ports_inv <= not jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write;
jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read_ports_inv <= not jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read;
green_leds_s1_translator_avalon_anti_slave_0_write_ports_inv <= not green_leds_s1_translator_avalon_anti_slave_0_write;
servo_pwm_0_s0_translator_avalon_anti_slave_0_write_ports_inv <= not servo_pwm_0_s0_translator_avalon_anti_slave_0_write;
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
end architecture rtl; -- of tracking_camera_system
| gpl-2.0 | 4738da2b4411989286b601d3923672e3 | 0.505517 | 4.012309 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_Video_In_Decoder.vhd | 1 | 10,180 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module decodes video input streams on the DE boards. *
-- * *
-- ******************************************************************************
ENTITY Video_System_Video_In_Decoder IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
GENERIC (
IW :INTEGER := 7;
OW :INTEGER := 15;
FW :INTEGER := 17;
PIXELS :INTEGER := 1280
);
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
TD_CLK27 :IN STD_LOGIC;
TD_DATA :IN STD_LOGIC_VECTOR( 7 DOWNTO 0);
TD_HS :IN STD_LOGIC;
TD_VS :IN STD_LOGIC;
stream_out_ready :IN STD_LOGIC;
-- Bidirectional
-- Outputs
TD_RESET :BUFFER STD_LOGIC;
overflow_flag :BUFFER STD_LOGIC;
stream_out_data :BUFFER STD_LOGIC_VECTOR(OW DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_empty :BUFFER STD_LOGIC;
stream_out_valid :BUFFER STD_LOGIC
);
END Video_System_Video_In_Decoder;
ARCHITECTURE Behaviour OF Video_System_Video_In_Decoder IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
SIGNAL video_clk :STD_LOGIC;
SIGNAL decoded_pixel :STD_LOGIC_VECTOR(OW DOWNTO 0);
SIGNAL decoded_startofpacket :STD_LOGIC;
SIGNAL decoded_endofpacket :STD_LOGIC;
SIGNAL decoded_valid :STD_LOGIC;
SIGNAL data_from_fifo :STD_LOGIC_VECTOR(FW DOWNTO 0);
SIGNAL fifo_used_words :STD_LOGIC_VECTOR( 6 DOWNTO 0);
SIGNAL wrusedw :STD_LOGIC_VECTOR( 6 DOWNTO 0);
SIGNAL wrfull :STD_LOGIC;
SIGNAL rdempty :STD_LOGIC;
-- Internal Registers
SIGNAL reached_start_of_frame :STD_LOGIC;
-- State Machine Registers
-- Integers
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
COMPONENT altera_up_video_itu_656_decoder
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
TD_DATA :IN STD_LOGIC_VECTOR( 7 DOWNTO 0);
ready :IN STD_LOGIC;
-- Bidirectionals
-- Outputs
data :BUFFER STD_LOGIC_VECTOR(OW DOWNTO 0);
startofpacket :BUFFER STD_LOGIC;
endofpacket :BUFFER STD_LOGIC;
valid :BUFFER STD_LOGIC
);
END COMPONENT;
COMPONENT altera_up_video_dual_clock_fifo
GENERIC (
DW :INTEGER
);
PORT (
-- Inputs
wrclk :IN STD_LOGIC;
wrreq :IN STD_LOGIC;
data :IN STD_LOGIC_VECTOR((OW + 2) DOWNTO 0);
rdclk :IN STD_LOGIC;
rdreq :IN STD_LOGIC;
-- Bidirectionals
-- Outputs
wrusedw :BUFFER STD_LOGIC_VECTOR( 6 DOWNTO 0);
wrfull :BUFFER STD_LOGIC;
q :BUFFER STD_LOGIC_VECTOR(FW DOWNTO 0);
rdusedw :BUFFER STD_LOGIC_VECTOR( 6 DOWNTO 0);
rdempty :BUFFER STD_LOGIC
);
END COMPONENT;
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
-- Output Registers
PROCESS (video_clk)
BEGIN
IF video_clk'EVENT AND video_clk = '1' THEN
IF (reset = '1') THEN
overflow_flag <= '0';
ELSIF ((decoded_valid = '1') AND (reached_start_of_frame = '1') AND
(wrfull = '1')) THEN
overflow_flag <= '1';
END IF;
END IF;
END PROCESS;
-- Internal Registers
PROCESS (video_clk)
BEGIN
IF video_clk'EVENT AND video_clk = '1' THEN
IF (reset = '1') THEN
reached_start_of_frame <= '0';
ELSIF ((decoded_valid = '1') AND (decoded_startofpacket = '1')) THEN
reached_start_of_frame <= '1';
END IF;
END IF;
END PROCESS;
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
-- Output Assignments
TD_RESET <= '1';
stream_out_data <= data_from_fifo( OW DOWNTO 0);
stream_out_startofpacket <= data_from_fifo((FW - 1));
stream_out_endofpacket <= data_from_fifo(FW);
stream_out_empty <= '0';
stream_out_valid <= NOT rdempty;
-- Internal Assignments
video_clk <= TD_CLK27;
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
-- NTSC Video In Decoding
ITU_R_656_Decoder : altera_up_video_itu_656_decoder
PORT MAP (
-- Inputs
clk => video_clk,
reset => reset,
TD_DATA => TD_DATA,
ready => decoded_valid AND NOT wrfull,
-- Bidirectionals
-- Outputs
data => decoded_pixel,
startofpacket => decoded_startofpacket,
endofpacket => decoded_endofpacket,
valid => decoded_valid
);
Video_In_Dual_Clock_FIFO : altera_up_video_dual_clock_fifo
GENERIC MAP (
DW => (FW + 1)
)
PORT MAP (
-- Inputs
wrclk => video_clk,
wrreq => decoded_valid AND reached_start_of_frame AND NOT wrfull,
data => decoded_endofpacket & decoded_startofpacket & decoded_pixel,
rdclk => clk,
rdreq => stream_out_valid AND stream_out_ready,
-- Bidirectionals
-- Outputs
wrusedw => wrusedw,
wrfull => wrfull,
q => data_from_fifo,
rdusedw => fifo_used_words,
rdempty => rdempty
);
END Behaviour;
| gpl-2.0 | 94839a714f6b957e4fbd829e9c3ed974 | 0.462475 | 4.31905 | false | false | false | false |
Reiuiji/ECE368-Lab | Examples/Templates/VHDL-Template-Structural.vhd | 1 | 1,663 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Class: ECE 368 Digital Design
-- Engineer: [Engineer 1]
-- [Engineer 2]
--
-- Create Date: [Date]
-- Module Name: [Module Name]
-- Project Name: [Project Name]
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description:
-- [Insert Description]
--
-- Notes:
-- [Insert Notes]
--
-- Revision:
-- [Insert Revision]
--
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity [Name]_TopLevel_design is
PORT (
CLOCK : in STD_LOGIC;
[IN_Port0] : in STD_LOGIC;
[IN_Port1] : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
[OUT_Port0] : out STD_LOGIC;
[OUT_Port1] : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end [Name]_TopLevel_design;
architecture Structural of [Name]_TopLevel_design is
signal [IN_Port0] : in STD_LOGIC;
signal [IN_Port1] : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
signal [OUT_Port0] : out STD_LOGIC;
signal [OUT_Port1] : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
begin
[OUT_PORT] <= [DATA_OUT];
----- Structural Components: -----
-- [Name] UNIT
[Name]_Unit : entity work.Unit_File
port map (
--COMPONENT SIGNAL
CLOCK => CLOCK,
[IN_Port0] => [IN_Port0],
[IN_Port1] => [IN_Port1],
[OUT_Port0] => [OUT_Port0],
[OUT_Port1] => [OUT_Port1]
);
end Structural;
| mit | ae5f9c3c62d3470aa1f9d2fa7e2b3293 | 0.529765 | 3.260784 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_CPU_jtag_debug_module_wrapper.vhd | 1 | 14,911 | --Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_jtag_debug_module_wrapper is
port (
-- inputs:
signal MonDReg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal break_readreg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal dbrk_hit0_latch : IN STD_LOGIC;
signal dbrk_hit1_latch : IN STD_LOGIC;
signal dbrk_hit2_latch : IN STD_LOGIC;
signal dbrk_hit3_latch : IN STD_LOGIC;
signal debugack : IN STD_LOGIC;
signal monitor_error : IN STD_LOGIC;
signal monitor_ready : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal resetlatch : IN STD_LOGIC;
signal tracemem_on : IN STD_LOGIC;
signal tracemem_trcdata : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tracemem_tw : IN STD_LOGIC;
signal trc_im_addr : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal trc_on : IN STD_LOGIC;
signal trc_wrap : IN STD_LOGIC;
signal trigbrktype : IN STD_LOGIC;
signal trigger_state_1 : IN STD_LOGIC;
-- outputs:
signal jdo : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : OUT STD_LOGIC;
signal st_ready_test_idle : OUT STD_LOGIC;
signal take_action_break_a : OUT STD_LOGIC;
signal take_action_break_b : OUT STD_LOGIC;
signal take_action_break_c : OUT STD_LOGIC;
signal take_action_ocimem_a : OUT STD_LOGIC;
signal take_action_ocimem_b : OUT STD_LOGIC;
signal take_action_tracectrl : OUT STD_LOGIC;
signal take_action_tracemem_a : OUT STD_LOGIC;
signal take_action_tracemem_b : OUT STD_LOGIC;
signal take_no_action_break_a : OUT STD_LOGIC;
signal take_no_action_break_b : OUT STD_LOGIC;
signal take_no_action_break_c : OUT STD_LOGIC;
signal take_no_action_ocimem_a : OUT STD_LOGIC;
signal take_no_action_tracemem_a : OUT STD_LOGIC
);
end entity Video_System_CPU_jtag_debug_module_wrapper;
architecture europa of Video_System_CPU_jtag_debug_module_wrapper is
component Video_System_CPU_jtag_debug_module_tck is
port (
-- inputs:
signal MonDReg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal break_readreg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dbrk_hit0_latch : IN STD_LOGIC;
signal dbrk_hit1_latch : IN STD_LOGIC;
signal dbrk_hit2_latch : IN STD_LOGIC;
signal dbrk_hit3_latch : IN STD_LOGIC;
signal debugack : IN STD_LOGIC;
signal ir_in : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal jtag_state_rti : IN STD_LOGIC;
signal monitor_error : IN STD_LOGIC;
signal monitor_ready : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal resetlatch : IN STD_LOGIC;
signal tck : IN STD_LOGIC;
signal tdi : IN STD_LOGIC;
signal tracemem_on : IN STD_LOGIC;
signal tracemem_trcdata : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tracemem_tw : IN STD_LOGIC;
signal trc_im_addr : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal trc_on : IN STD_LOGIC;
signal trc_wrap : IN STD_LOGIC;
signal trigbrktype : IN STD_LOGIC;
signal trigger_state_1 : IN STD_LOGIC;
signal vs_cdr : IN STD_LOGIC;
signal vs_sdr : IN STD_LOGIC;
signal vs_uir : IN STD_LOGIC;
-- outputs:
signal ir_out : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal jrst_n : OUT STD_LOGIC;
signal sr : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
signal st_ready_test_idle : OUT STD_LOGIC;
signal tdo : OUT STD_LOGIC
);
end component Video_System_CPU_jtag_debug_module_tck;
component Video_System_CPU_jtag_debug_module_sysclk is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal ir_in : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal sr : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal vs_udr : IN STD_LOGIC;
signal vs_uir : IN STD_LOGIC;
-- outputs:
signal jdo : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
signal take_action_break_a : OUT STD_LOGIC;
signal take_action_break_b : OUT STD_LOGIC;
signal take_action_break_c : OUT STD_LOGIC;
signal take_action_ocimem_a : OUT STD_LOGIC;
signal take_action_ocimem_b : OUT STD_LOGIC;
signal take_action_tracectrl : OUT STD_LOGIC;
signal take_action_tracemem_a : OUT STD_LOGIC;
signal take_action_tracemem_b : OUT STD_LOGIC;
signal take_no_action_break_a : OUT STD_LOGIC;
signal take_no_action_break_b : OUT STD_LOGIC;
signal take_no_action_break_c : OUT STD_LOGIC;
signal take_no_action_ocimem_a : OUT STD_LOGIC;
signal take_no_action_tracemem_a : OUT STD_LOGIC
);
end component Video_System_CPU_jtag_debug_module_sysclk;
--synthesis read_comments_as_HDL on
-- component sld_virtual_jtag_basic is
--GENERIC (
-- sld_auto_instance_index : STRING;
-- sld_instance_index : NATURAL;
-- sld_ir_width : NATURAL;
-- sld_mfg_id : NATURAL;
-- sld_sim_action : STRING;
-- sld_sim_n_scan : NATURAL;
-- sld_sim_total_length : NATURAL;
-- sld_type_id : NATURAL;
-- sld_version : NATURAL
-- );
-- PORT (
-- signal virtual_state_udr : OUT STD_LOGIC;
-- signal ir_in : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal tdi : OUT STD_LOGIC;
-- signal virtual_state_sdr : OUT STD_LOGIC;
-- signal jtag_state_rti : OUT STD_LOGIC;
-- signal tck : OUT STD_LOGIC;
-- signal virtual_state_cdr : OUT STD_LOGIC;
-- signal virtual_state_uir : OUT STD_LOGIC;
-- signal ir_out : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal tdo : IN STD_LOGIC
-- );
-- end component sld_virtual_jtag_basic;
--synthesis read_comments_as_HDL off
signal internal_jdo : STD_LOGIC_VECTOR (37 DOWNTO 0);
signal internal_jrst_n : STD_LOGIC;
signal internal_st_ready_test_idle : STD_LOGIC;
signal internal_take_action_break_a : STD_LOGIC;
signal internal_take_action_break_b : STD_LOGIC;
signal internal_take_action_break_c : STD_LOGIC;
signal internal_take_action_ocimem_a : STD_LOGIC;
signal internal_take_action_ocimem_b : STD_LOGIC;
signal internal_take_action_tracectrl : STD_LOGIC;
signal internal_take_action_tracemem_a : STD_LOGIC;
signal internal_take_action_tracemem_b : STD_LOGIC;
signal internal_take_no_action_break_a : STD_LOGIC;
signal internal_take_no_action_break_b : STD_LOGIC;
signal internal_take_no_action_break_c : STD_LOGIC;
signal internal_take_no_action_ocimem_a : STD_LOGIC;
signal internal_take_no_action_tracemem_a : STD_LOGIC;
signal sr : STD_LOGIC_VECTOR (37 DOWNTO 0);
signal vji_cdr : STD_LOGIC;
signal vji_ir_in : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal vji_ir_out : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal vji_rti : STD_LOGIC;
signal vji_sdr : STD_LOGIC;
signal vji_tck : STD_LOGIC;
signal vji_tdi : STD_LOGIC;
signal vji_tdo : STD_LOGIC;
signal vji_udr : STD_LOGIC;
signal vji_uir : STD_LOGIC;
begin
--Change the sld_virtual_jtag_basic's defparams to
--switch between a regular Nios II or an internally embedded Nios II.
--For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
--For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
--the_Video_System_CPU_jtag_debug_module_tck, which is an e_instance
the_Video_System_CPU_jtag_debug_module_tck : Video_System_CPU_jtag_debug_module_tck
port map(
ir_out => vji_ir_out,
jrst_n => internal_jrst_n,
sr => sr,
st_ready_test_idle => internal_st_ready_test_idle,
tdo => vji_tdo,
MonDReg => MonDReg,
break_readreg => break_readreg,
dbrk_hit0_latch => dbrk_hit0_latch,
dbrk_hit1_latch => dbrk_hit1_latch,
dbrk_hit2_latch => dbrk_hit2_latch,
dbrk_hit3_latch => dbrk_hit3_latch,
debugack => debugack,
ir_in => vji_ir_in,
jtag_state_rti => vji_rti,
monitor_error => monitor_error,
monitor_ready => monitor_ready,
reset_n => reset_n,
resetlatch => resetlatch,
tck => vji_tck,
tdi => vji_tdi,
tracemem_on => tracemem_on,
tracemem_trcdata => tracemem_trcdata,
tracemem_tw => tracemem_tw,
trc_im_addr => trc_im_addr,
trc_on => trc_on,
trc_wrap => trc_wrap,
trigbrktype => trigbrktype,
trigger_state_1 => trigger_state_1,
vs_cdr => vji_cdr,
vs_sdr => vji_sdr,
vs_uir => vji_uir
);
--the_Video_System_CPU_jtag_debug_module_sysclk, which is an e_instance
the_Video_System_CPU_jtag_debug_module_sysclk : Video_System_CPU_jtag_debug_module_sysclk
port map(
jdo => internal_jdo,
take_action_break_a => internal_take_action_break_a,
take_action_break_b => internal_take_action_break_b,
take_action_break_c => internal_take_action_break_c,
take_action_ocimem_a => internal_take_action_ocimem_a,
take_action_ocimem_b => internal_take_action_ocimem_b,
take_action_tracectrl => internal_take_action_tracectrl,
take_action_tracemem_a => internal_take_action_tracemem_a,
take_action_tracemem_b => internal_take_action_tracemem_b,
take_no_action_break_a => internal_take_no_action_break_a,
take_no_action_break_b => internal_take_no_action_break_b,
take_no_action_break_c => internal_take_no_action_break_c,
take_no_action_ocimem_a => internal_take_no_action_ocimem_a,
take_no_action_tracemem_a => internal_take_no_action_tracemem_a,
clk => clk,
ir_in => vji_ir_in,
sr => sr,
vs_udr => vji_udr,
vs_uir => vji_uir
);
--vhdl renameroo for output signals
jdo <= internal_jdo;
--vhdl renameroo for output signals
jrst_n <= internal_jrst_n;
--vhdl renameroo for output signals
st_ready_test_idle <= internal_st_ready_test_idle;
--vhdl renameroo for output signals
take_action_break_a <= internal_take_action_break_a;
--vhdl renameroo for output signals
take_action_break_b <= internal_take_action_break_b;
--vhdl renameroo for output signals
take_action_break_c <= internal_take_action_break_c;
--vhdl renameroo for output signals
take_action_ocimem_a <= internal_take_action_ocimem_a;
--vhdl renameroo for output signals
take_action_ocimem_b <= internal_take_action_ocimem_b;
--vhdl renameroo for output signals
take_action_tracectrl <= internal_take_action_tracectrl;
--vhdl renameroo for output signals
take_action_tracemem_a <= internal_take_action_tracemem_a;
--vhdl renameroo for output signals
take_action_tracemem_b <= internal_take_action_tracemem_b;
--vhdl renameroo for output signals
take_no_action_break_a <= internal_take_no_action_break_a;
--vhdl renameroo for output signals
take_no_action_break_b <= internal_take_no_action_break_b;
--vhdl renameroo for output signals
take_no_action_break_c <= internal_take_no_action_break_c;
--vhdl renameroo for output signals
take_no_action_ocimem_a <= internal_take_no_action_ocimem_a;
--vhdl renameroo for output signals
take_no_action_tracemem_a <= internal_take_no_action_tracemem_a;
--synthesis translate_off
vji_tck <= std_logic'('0');
vji_tdi <= std_logic'('0');
vji_sdr <= std_logic'('0');
vji_cdr <= std_logic'('0');
vji_rti <= std_logic'('0');
vji_uir <= std_logic'('0');
vji_udr <= std_logic'('0');
vji_ir_in <= std_logic_vector'("00");
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- Video_System_CPU_jtag_debug_module_phy : sld_virtual_jtag_basic
-- generic map(
-- sld_auto_instance_index => "YES",
-- sld_instance_index => 0,
-- sld_ir_width => 2,
-- sld_mfg_id => 70,
-- sld_sim_action => "",
-- sld_sim_n_scan => 0,
-- sld_sim_total_length => 0,
-- sld_type_id => 34,
-- sld_version => 3
-- )
-- port map(
-- ir_in => vji_ir_in,
-- ir_out => vji_ir_out,
-- jtag_state_rti => vji_rti,
-- tck => vji_tck,
-- tdi => vji_tdi,
-- tdo => vji_tdo,
-- virtual_state_cdr => vji_cdr,
-- virtual_state_sdr => vji_sdr,
-- virtual_state_udr => vji_udr,
-- virtual_state_uir => vji_uir
-- );
--
--synthesis read_comments_as_HDL off
end europa;
| gpl-2.0 | 48db77cdd0d92fa85e8a959e9bece8d4 | 0.581383 | 3.797046 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/boards/terasic-de2-115/mn-dual-hostif-gpio/quartus/toplevel.vhd | 3 | 16,343 | -------------------------------------------------------------------------------
--! @file toplevel.vhd
--
--! @brief Toplevel of dual Nios MN design
--
--! @details This is the toplevel of the dual Nios MN FPGA design for the
--! INK DE2-115 Evaluation Board.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library libcommon;
use libcommon.global.all;
entity toplevel is
port (
-- 50 MHZ CLK IN
EXT_CLK : in std_logic;
-- PHY Interfaces
PHY_GXCLK : out std_logic_vector(1 downto 0);
PHY_LINK_n : in std_logic_vector(1 downto 0);
PHY_RXCLK : in std_logic_vector(1 downto 0);
PHY_RXER : in std_logic_vector(1 downto 0);
PHY_RXDV : in std_logic_vector(1 downto 0);
PHY_RXD : in std_logic_vector(7 downto 0);
PHY_TXCLK : in std_logic_vector(1 downto 0);
PHY_TXER : out std_logic_vector(1 downto 0);
PHY_TXEN : out std_logic_vector(1 downto 0);
PHY_TXD : out std_logic_vector(7 downto 0);
PHY_MDIO : inout std_logic_vector(1 downto 0);
PHY_MDC : out std_logic_vector(1 downto 0);
PHY_RESET_n : out std_logic_vector(1 downto 0);
-- EPCS
EPCS_DCLK : out std_logic;
EPCS_SCE : out std_logic;
EPCS_SDO : out std_logic;
EPCS_DATA0 : in std_logic;
-- 2 MB SRAM
SRAM_CE_n : out std_logic;
SRAM_OE_n : out std_logic;
SRAM_WE_n : out std_logic;
SRAM_ADDR : out std_logic_vector(20 downto 1);
SRAM_BE_n : out std_logic_vector(1 downto 0);
SRAM_DQ : inout std_logic_vector(15 downto 0);
-- 64 MBx2 SDRAM
SDRAM_CLK : out std_logic;
SDRAM_CAS_n : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CS_n : out std_logic;
SDRAM_RAS_n : out std_logic;
SDRAM_WE_n : out std_logic;
SDRAM_ADDR : out std_logic_vector(12 downto 0);
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_DQM : out std_logic_vector(3 downto 0);
SDRAM_DQ : inout std_logic_vector(31 downto 0);
-- FLASH 8Mx8
CFI_FLASH_ADDR : out std_logic_vector(22 downto 0);
CFI_FLASH_DATA : inout std_logic_vector(7 downto 0);
CFI_FLASH_WE_n : out std_logic;
CFI_FLASH_CE_n : out std_logic;
CFI_FLASH_OE_n : out std_logic;
CFI_FLASH_RESET_n : out std_logic;
CFI_FLASH_WP_n : out std_logic;
CFI_FLASH_RY : in std_logic;
-- LED
LEDG : out std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(15 downto 0);
-- KEY
KEY_n : in std_logic_vector(3 downto 0);
-- LCD
LCD_ON : out std_logic;
LCD_BLON : out std_logic;
LCD_DQ : inout std_logic_vector(7 downto 0);
LCD_E : out std_logic;
LCD_RS : out std_logic;
LCD_RW : out std_logic;
-- BENCHMARK
BENCHMARK : out std_logic_vector(7 downto 0);
-- BENCHMARK_AP
BENCHMARK_AP : out std_logic_vector(7 downto 0)
);
end toplevel;
architecture rtl of toplevel is
component mnDualHostifGpio is
port (
clk25_clk : in std_logic;
clk50_clk : in std_logic := 'X';
clk100_clk : in std_logic;
reset_reset_n : in std_logic := 'X';
tri_state_sram_0_tcm_address_out : out std_logic_vector(20 downto 0);
tri_state_sram_0_tcm_byteenable_n_out : out std_logic_vector(1 downto 0);
tri_state_sram_0_tcm_read_n_out : out std_logic;
tri_state_sram_0_tcm_write_n_out : out std_logic;
tri_state_sram_0_tcm_data_out : inout std_logic_vector(15 downto 0) := (others => 'X');
tri_state_sram_0_tcm_chipselect_n_out : out std_logic;
pcp_0_benchmark_pio_export : out std_logic_vector(7 downto 0);
-- OPENMAC
openmac_0_mii_txEnable : out std_logic_vector(1 downto 0);
openmac_0_mii_txData : out std_logic_vector(7 downto 0);
openmac_0_mii_txClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxError : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxDataValid : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxData : in std_logic_vector(7 downto 0) := (others => 'X');
openmac_0_mii_rxClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_smi_nPhyRst : out std_logic_vector(1 downto 0);
openmac_0_smi_clk : out std_logic_vector(1 downto 0);
openmac_0_smi_dio : inout std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_pktactivity_export : out std_logic;
host_0_benchmark_pio_export : out std_logic_vector(7 downto 0);
powerlink_led_export : out std_logic_vector(1 downto 0);
epcs_flash_dclk : out std_logic;
epcs_flash_sce : out std_logic;
epcs_flash_sdo : out std_logic;
epcs_flash_data0 : in std_logic := 'X';
sdram_0_addr : out std_logic_vector(12 downto 0);
sdram_0_ba : out std_logic_vector(1 downto 0);
sdram_0_cas_n : out std_logic;
sdram_0_cke : out std_logic;
sdram_0_cs_n : out std_logic;
sdram_0_dq : inout std_logic_vector(31 downto 0) := (others => 'X');
sdram_0_dqm : out std_logic_vector(3 downto 0);
sdram_0_ras_n : out std_logic;
sdram_0_we_n : out std_logic;
lcd_data : inout std_logic_vector(7 downto 0) := (others => 'X');
lcd_E : out std_logic;
lcd_RS : out std_logic;
lcd_RW : out std_logic;
-- CPU RESET REQUEST
pcp_0_cpu_resetrequest_resetrequest : in std_logic := 'X';
pcp_0_cpu_resetrequest_resettaken : out std_logic;
-- CFI FLASH FOR HOST
tristate_cfi_flash_0_tcm_address_out : out std_logic_vector(22 downto 0);
tristate_cfi_flash_0_tcm_read_n_out : out std_logic;
tristate_cfi_flash_0_tcm_write_n_out : out std_logic;
tristate_cfi_flash_0_tcm_data_out : inout std_logic_vector(7 downto 0) := (others => 'X');
tristate_cfi_flash_0_tcm_chipselect_n_out : out std_logic;
-- Application ports
app_pio_in_port : in std_logic_vector(31 downto 0) := (others => 'X');
app_pio_out_port : out std_logic_vector(31 downto 0)
);
end component mnDualHostifGpio;
-- PLL component
component pll
port (
inclk0 : in std_logic;
c0 : out std_logic;
c1 : out std_logic;
c2 : out std_logic;
c3 : out std_logic;
locked : out std_logic
);
end component;
signal clk25 : std_logic;
signal clk50 : std_logic;
signal clk100 : std_logic;
signal clk100_p : std_logic;
signal pllLocked : std_logic;
signal sramAddr : std_logic_vector(SRAM_ADDR'high downto 0);
signal plk_status_error : std_logic_vector(1 downto 0);
signal openmac_activity : std_logic;
signal app_input : std_logic_vector(31 downto 0);
begin
SRAM_ADDR <= sramAddr(SRAM_ADDR'range);
PHY_GXCLK <= (others => '0');
PHY_TXER <= (others => '0');
LCD_ON <= '1';
LCD_BLON <= '1';
SDRAM_CLK <= clk100_p;
CFI_FLASH_RESET_n <= cnInactivated;
CFI_FLASH_WP_n <= cnInactivated;
---------------------------------------------------------------------------
-- Green LED assignments
LEDG <= plk_status_error(0) & -- POWERLINK Status LED
"000" & -- Reserved
(openmac_activity and not PHY_LINK_n(0)) & -- Gated activity
not PHY_LINK_n(0) & -- Link
(openmac_activity and not PHY_LINK_n(1)) & -- Gated activity
not PHY_LINK_n(1); -- Link
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Red LED assignments
LEDR <= x"000" & -- Reserved
"000" & -- Reserved
plk_status_error(1); -- POWERLINK Error LED
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Application Input and Output assignments
-- Input: Map KEY nibble to Application Input
app_input <= x"0000000" & not KEY_n;
---------------------------------------------------------------------------
inst : component mnDualHostifGpio
port map (
clk25_clk => clk25,
clk50_clk => clk50,
clk100_clk => clk100,
reset_reset_n => pllLocked,
pcp_0_cpu_resetrequest_resetrequest => '0',
pcp_0_cpu_resetrequest_resettaken => open,
openmac_0_mii_txEnable => PHY_TXEN,
openmac_0_mii_txData => PHY_TXD,
openmac_0_mii_txClk => PHY_TXCLK,
openmac_0_mii_rxError => PHY_RXER,
openmac_0_mii_rxDataValid => PHY_RXDV,
openmac_0_mii_rxData => PHY_RXD,
openmac_0_mii_rxClk => PHY_RXCLK,
openmac_0_smi_nPhyRst => PHY_RESET_n,
openmac_0_smi_clk => PHY_MDC,
openmac_0_smi_dio => PHY_MDIO,
openmac_0_pktactivity_export => openmac_activity,
tri_state_sram_0_tcm_address_out => sramAddr,
tri_state_sram_0_tcm_read_n_out => SRAM_OE_n,
tri_state_sram_0_tcm_byteenable_n_out => SRAM_BE_n,
tri_state_sram_0_tcm_write_n_out => SRAM_WE_n,
tri_state_sram_0_tcm_data_out => SRAM_DQ,
tri_state_sram_0_tcm_chipselect_n_out => SRAM_CE_n,
pcp_0_benchmark_pio_export => BENCHMARK,
powerlink_led_export => plk_status_error,
host_0_benchmark_pio_export => BENCHMARK_AP,
epcs_flash_dclk => EPCS_DCLK,
epcs_flash_sce => EPCS_SCE,
epcs_flash_sdo => EPCS_SDO,
epcs_flash_data0 => EPCS_DATA0,
sdram_0_addr => SDRAM_ADDR,
sdram_0_ba => SDRAM_BA,
sdram_0_cas_n => SDRAM_CAS_n,
sdram_0_cke => SDRAM_CKE,
sdram_0_cs_n => SDRAM_CS_n,
sdram_0_dq => SDRAM_DQ,
sdram_0_dqm => SDRAM_DQM,
sdram_0_ras_n => SDRAM_RAS_n,
sdram_0_we_n => SDRAM_WE_n,
lcd_data => LCD_DQ,
lcd_E => LCD_E,
lcd_RS => LCD_RS,
lcd_RW => LCD_RW,
tristate_cfi_flash_0_tcm_address_out => CFI_FLASH_ADDR,
tristate_cfi_flash_0_tcm_read_n_out => CFI_FLASH_OE_n,
tristate_cfi_flash_0_tcm_write_n_out => CFI_FLASH_WE_n,
tristate_cfi_flash_0_tcm_data_out => CFI_FLASH_DATA,
tristate_cfi_flash_0_tcm_chipselect_n_out => CFI_FLASH_CE_n,
app_pio_in_port => app_input,
app_pio_out_port => open
);
-- Pll Instance
pllInst : pll
port map (
inclk0 => EXT_CLK,
c0 => clk50,
c1 => clk100,
c2 => clk25,
c3 => clk100_p,
locked => pllLocked
);
end rtl;
| gpl-2.0 | 91eb2b65ba90837efd21cf03c16f407e | 0.43615 | 4.279393 | false | false | false | false |
DreamIP/GPStudio | support/process/median/hdl/median.vhd | 1 | 3,870 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity median is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end median;
architecture rtl of median is
component median_process
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_width : in std_logic_vector(15 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component median_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal widthimg_reg_width : std_logic_vector (15 downto 0);
begin
median_process_inst : median_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_width => widthimg_reg_width,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
median_slave_inst : median_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_width => widthimg_reg_width,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
| gpl-3.0 | 09cf1e6235dcb9cdd23c997c897d1e40 | 0.460207 | 3.391762 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/RGMII_MAC/rgmii_tx_top_2.vhd | 1 | 4,272 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY rgmii_tx_top_2 IS
PORT (
iEthClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
oEnetTxData : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
oEnetTxEn : OUT STD_LOGIC;
oEnetTxErr : OUT STD_LOGIC;
-- iCheckSumIPGen : IN STD_LOGIC;
-- iCheckSumTCPGen : IN STD_LOGIC;
-- iCheckSumUDPGen : IN STD_LOGIC;
-- iCheckSumICMPGen : IN STD_LOGIC;
--USR IF FROM "UDP COMPLETE"
iData_tx : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
iTxDataValid : IN STD_LOGIC;
iSOF : IN STD_LOGIC;
iEOF : IN STD_LOGIC;
oMACTxRdy : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE RTL OF rgmii_tx_top_2 is
COMPONENT rgmii_tx_2 IS
PORT (
iClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
-- from fifo
iTxData : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
--iSOF : IN STD_LOGIC;
--iEOF : IN STD_LOGIC;
iFFempty : IN STD_LOGIC;
oTRANSMIT_DONE : OUT STD_LOGIC;
iReadReq : OUT STD_LOGIC;
-- signals TO PHY
oTxData : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
oTxEn : OUT STD_LOGIC;
oTxErr : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fifo_tx_udp IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
signal rst_ff_int, ff_rdreq_int, ff_wrreq_int, ff_empty_int, ff_full_int, oTRANSMIT_DONE_int : std_logic;
signal iData_tx_delayed_int, cTxData : std_logic_vector(7 downto 0);
type state_ff is (init, s0, s1, s2, s3);
signal state : state_ff;
begin
ff_tx_udp_inst : fifo_tx_udp
PORT MAP(
aclr => rst_ff_int,
clock => iEthClk,
data => iData_tx_delayed_int,--iData_tx,
rdreq => ff_rdreq_int,
wrreq => ff_wrreq_int,
empty => ff_empty_int,
full => ff_full_int,
q => cTxData
);
rgmii_tx_inst : rgmii_tx_2
PORT MAP (
iClk => iEthClk,
iRst_n => iRst_n,
iTxData => cTxData,
iFFempty => ff_empty_int,
oTRANSMIT_DONE=> oTRANSMIT_DONE_int,
iReadReq => ff_rdreq_int,
--iEOF => eof
oTxData => oEnetTxData,--oEnetTxData,
oTxEn => oEnetTxEn,--oEnetTxEn,
oTxErr => oEnetTxErr);
process(iEthClk, iRst_n)
begin
if iRst_n = '0' then
iData_tx_delayed_int <= (others => '0');
elsif rising_edge(iEthClk) then
iData_tx_delayed_int <= iData_tx;
end if;
end process;
process(iEthClk, iRst_n)
begin
if iRst_n = '0' then
rst_ff_int <= '1';
oMACTxRdy <= '0';
ff_wrreq_int <= '0';
state <= init;
elsif rising_edge(iEthClk) then
case state is
when init =>
rst_ff_int <= '1';
oMACTxRdy <= '0';
ff_wrreq_int <= '0';
state <= s0;
when s0 =>--MAC IS READY
rst_ff_int <= '0';
ff_wrreq_int <= '0';
if ff_full_int = '0' then
oMACTxRdy <= '1';
state <= s1;
else
oMACTxRdy <= '0';
state <= s0;
end if;
when s1 =>--SOF STARTING
rst_ff_int <= '0';
if ff_full_int = '0' then
oMACTxRdy <= '1';
if iTxDataValid = '1' then
if iSOF = '1' then -- signal de start
ff_wrreq_int <= '1';
state <= s2;
--else--sinon on attend eof sans ecrire
end if;
else
ff_wrreq_int <= '0';
state <= s1;
end if;
else
oMACTxRdy <= '0';
ff_wrreq_int <= '0';
state <= s1;
end if;
when s2 =>--DATA TO FF
rst_ff_int <= '0';
if ff_full_int = '0' then
oMACTxRdy <= '1';
if iTxDataValid = '1' then
if iEOF = '1' then --signal de fin d'écriture
ff_wrreq_int <= '1';
state <= s3;
else
ff_wrreq_int <= '1';--on continue d'écrire dans FF
state <= s2;
end if;
else
ff_wrreq_int <= '0';
state <= s2;
end if;
else
oMACTxRdy <= '0';
ff_wrreq_int <= '0';
state <= s3;
end if;
when s3 =>
ff_wrreq_int <= '0';
if oTRANSMIT_DONE_int = '1' then
rst_ff_int <= '1';
oMACTxRdy <= '0';
state <= s0;
end if;
when others =>
rst_ff_int <= '1';
oMACTxRdy <= '0';
ff_wrreq_int <= '0';
state <= init;
end case;
end if;
end process;
END ARCHITECTURE; | gpl-3.0 | 9775060a6e93a13dcac8fe970551efec | 0.560656 | 2.481116 | false | false | false | false |
hoglet67/ElectronFpga | src/xilinx/ElectronUla_duo.vhd | 1 | 8,161 | --------------------------------------------------------------------------------
-- Copyright (c) 2016 David Banks
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : ElectronUla_duo.vhd
-- /___/ /\ Timestamp : 17/09/2016
-- \ \ / \
-- \___\/\___\
--
--Design Name: ElectronUla_duo
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- TODO:
-- NMI_n needs adding
-- HS_n needs adding
-- RAM lines need adding (RA7..0, RD3..0, RAS, CAS, WE)
entity ElectronULA_duo is
port (
clk_in : in std_logic;
-- CPU Interface
clk_out : out std_logic;
addr : in std_logic_vector(15 downto 0);
data : inout std_logic_vector(7 downto 0);
R_W_n : in std_logic;
RST_n : inout std_logic;
IRQ_n : out std_logic;
-- Data Bus Enble
DBE_n : out std_logic;
-- Rom Enable
ROM_n : out std_logic;
-- Video
red : out std_logic;
green : out std_logic;
blue : out std_logic;
csync : out std_logic;
-- Audio
sound : out std_logic;
-- Keyboard
kbd : in std_logic_vector(3 downto 0);
caps : out std_logic;
-- Cassette
casIn : in std_logic;
casOut : out std_logic;
casMO : out std_logic;
-- SD Card
SDMISO : in std_logic;
SDSS : out std_logic;
SDCLK : out std_logic;
SDMOSI : out std_logic;
-- Misc
ARDUINO_RESET : out std_logic;
SW1 : in std_logic;
LED : out std_logic
);
end;
architecture behavioral of ElectronULA_duo is
signal clock_x : std_logic;
signal clock_16 : std_logic;
signal clock_24 : std_logic;
signal clock_32 : std_logic;
signal clock_33 : std_logic;
signal clock_40 : std_logic;
signal led_counter : std_logic_vector(23 downto 0);
signal clk_counter : std_logic_vector(2 downto 0);
signal cpu_clken : std_logic;
signal data_in : std_logic_vector(7 downto 0);
signal ula_enable : std_logic;
signal ula_data : std_logic_vector(7 downto 0);
signal ula_irq_n : std_logic;
signal video_red : std_logic_vector(3 downto 0);
signal video_green : std_logic_vector(3 downto 0);
signal video_blue : std_logic_vector(3 downto 0);
signal video_hsync : std_logic;
signal video_vsync : std_logic;
signal rom_latch : std_logic_vector(3 downto 0);
signal powerup_reset_n : std_logic;
signal reset_counter : std_logic_vector (15 downto 0);
signal rom_enable : std_logic;
signal rom_data : std_logic_vector(7 downto 0);
signal rom_we : std_logic;
signal turbo : std_logic_vector(1 downto 0);
signal caps_led : std_logic;
begin
inst_dcm_16_32 : entity work.dcm3 port map(
CLKIN_IN => clk_in,
-- used as a video clock when the ULA is in 50Hz VGA Mode
CLKFX_OUT => clock_x
);
inst_pll: entity work.pll2 port map(
-- 16 MHz input clock
CLKIN_IN => clock_x,
-- the main system clock, and also the video clock in sRGB mode
CLK0_OUT => clock_16,
-- used as a 24.00MHz for the SAA5050 in Mode 7
CLK1_OUT => clock_24,
-- used as a output clock MIST scan doubler for the SAA5050 in Mode 7
CLK2_OUT => clock_32,
-- used as a video clock when the ULA is in 60Hz VGA Mode
CLK3_OUT => clock_40
);
inst_dcm_16_33 : entity work.dcm2 port map(
CLKIN_IN => clk_in,
-- used as a video clock when the ULA is in 50Hz VGA Mode
CLKFX_OUT => clock_33
);
-- TODO
-- clk_out is not correct as the low time is always 250ns
clk_gen : process(clock_16)
begin
if rising_edge(clock_16) then
if cpu_clken = '1' then
clk_counter <= (others => '0');
clk_out <= '0';
elsif clk_counter(2) = '0' then
clk_counter <= clk_counter + 1;
else
clk_out <= '1';
end if;
end if;
end process;
ula : entity work.ElectronULA
generic map (
IncludeMMC => true,
Include32KRAM => true,
IncludeVGA => true,
IncludeJafaMode7 => true
)
port map (
clk_16M00 => clock_16,
clk_24M00 => clock_24,
clk_32M00 => clock_32,
clk_33M33 => clock_33,
clk_40M00 => clock_40,
-- CPU Interface
addr => addr,
data_in => data_in,
data_out => ula_data,
data_en => ula_enable,
R_W_n => R_W_n,
RST_n => RST_n,
IRQ_n => ula_irq_n,
NMI_n => '1',
-- Rom Enable
ROM_n => ROM_n,
-- Video
red => video_red,
green => video_green,
blue => video_blue,
vsync => video_vsync,
hsync => video_hsync,
-- Audio
sound => sound,
-- SD Card
SDMISO => SDMISO,
SDSS => SDSS,
SDCLK => SDCLK,
SDMOSI => SDMOSI,
-- Casette
casIn => casIn,
casOut => casOut,
-- Keyboard
kbd => kbd,
-- MISC
caps => caps_led,
motor => casMO,
rom_latch => rom_latch,
mode_init => "00",
-- Clock Generation
cpu_clken_out => cpu_clken,
turbo => turbo,
turbo_out => turbo
);
red <= video_red(3);
green <= video_green(3);
blue <= video_blue(3);
csync <= video_hsync;
caps <= not caps_led;
-- IRQ is open collector to avoid contention with the expansion bus
IRQ_n <= '0' when ula_irq_n = '0' else 'Z';
-- Enable data bus transceiver when ULA or ROM selected
DBE_n <= '0' when ula_enable = '1' or rom_enable = '1' else '1';
data_in <= data;
data <= rom_data when R_W_n = '1' and rom_enable = '1' else
ula_data when R_W_n = '1' and ula_enable = '1' else
"ZZZZZZZZ";
--------------------------------------------------------
-- Paged ROM
--------------------------------------------------------
rom_enable <= '1' when addr(15 downto 14) = "10" and rom_latch(3 downto 1) = "111" else '0';
rom_we <= '1' when rom_enable = '1' and cpu_clken = '1' else '0';
rom : entity work.expansion_rom port map(
clk => clock_16,
we => rom_we,
addr => rom_latch(0) & addr(13 downto 0),
data_in => data_in,
data_out => rom_data
);
--------------------------------------------------------
-- Speed LED
--------------------------------------------------------
led_gen : process(clock_16)
begin
if rising_edge(clock_16) then
led_counter <= led_counter + 1;
end if;
end process;
LED <= led_counter(led_counter'high - to_integer(unsigned(turbo)));
--------------------------------------------------------
-- Power Up Reset Generation
--------------------------------------------------------
reset_gen : process(clock_16)
begin
if rising_edge(clock_16) then
if (reset_counter(reset_counter'high) = '0') then
reset_counter <= reset_counter + 1;
end if;
powerup_reset_n <= reset_counter(reset_counter'high);
end if;
end process;
-- Reset is open collector to avoid contention when BREAK pressed
RST_n <= '0' when powerup_reset_n = '0' else 'Z';
-- Hold the Duo's Arduino core in reset
ARDUINO_RESET <= SW1;
end behavioral;
| gpl-3.0 | bf17a0e36f1c11b109db89ff6dd03d51 | 0.46808 | 3.72989 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_AV_Config.vhd | 1 | 20,604 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module sends and receives data from the audio's and TV in's *
-- * control registers for the chips on Altera's DE2 board. Plus, it can *
-- * send and receive data from the TRDB_DC2 and TRDB_LCM add-on modules. *
-- * *
-- ******************************************************************************
ENTITY Video_System_AV_Config IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
address :IN STD_LOGIC_VECTOR( 1 DOWNTO 0);
byteenable :IN STD_LOGIC_VECTOR( 3 DOWNTO 0);
read :IN STD_LOGIC;
write :IN STD_LOGIC;
writedata :IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Bidirectionals
I2C_SDAT :INOUT STD_LOGIC;
-- Outputs
readdata :BUFFER STD_LOGIC_VECTOR(31 DOWNTO 0);
waitrequest :BUFFER STD_LOGIC;
irq :BUFFER STD_LOGIC;
I2C_SCEN :BUFFER STD_LOGIC;
I2C_SCLK :BUFFER STD_LOGIC
);
END Video_System_AV_Config;
ARCHITECTURE Behaviour OF Video_System_AV_Config IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
CONSTANT DW :INTEGER := 26; -- Serial protocol's datawidth
CONSTANT CFG_TYPE :STD_LOGIC_VECTOR(7 DOWNTO 0) := B"00000010";
CONSTANT READ_MASK :STD_LOGIC_VECTOR(26 DOWNTO 0) := B"00000000" & '1' & B"11111111" & '0' & B"00000000" & '1';
CONSTANT WRITE_MASK :STD_LOGIC_VECTOR(26 DOWNTO 0) := B"00000000" & '1' & B"00000000" & '1' & B"00000000" & '1';
CONSTANT RESTART_COUNTER :STD_LOGIC_VECTOR(4 DOWNTO 0) := (0 => '1', 3 => '1', OTHERS => '0'); -- (SBCW DOWNTO 0)
-- Auto init parameters
CONSTANT AIRS :INTEGER := 50; -- Auto Init ROM's size
CONSTANT AIAW :INTEGER := 5; -- Auto Init ROM's address width
CONSTANT AUD_LINE_IN_LC :STD_LOGIC_VECTOR(8 DOWNTO 0) := B"000011010";
CONSTANT AUD_LINE_IN_RC :STD_LOGIC_VECTOR(8 DOWNTO 0) := B"000011010";
CONSTANT AUD_LINE_OUT_LC :STD_LOGIC_VECTOR(8 DOWNTO 0) := B"001111011";
CONSTANT AUD_LINE_OUT_RC :STD_LOGIC_VECTOR(8 DOWNTO 0) := B"001111011";
CONSTANT AUD_ADC_PATH :STD_LOGIC_VECTOR(8 DOWNTO 0) := B"010010101";
CONSTANT AUD_DAC_PATH :STD_LOGIC_VECTOR(8 DOWNTO 0) := B"000000110";
CONSTANT AUD_POWER :STD_LOGIC_VECTOR(8 DOWNTO 0) := B"000000000";
CONSTANT AUD_DATA_FORMAT :STD_LOGIC_VECTOR(8 DOWNTO 0) := B"001001001";
CONSTANT AUD_SAMPLE_CTRL :STD_LOGIC_VECTOR(8 DOWNTO 0) := B"000000000";
CONSTANT AUD_SET_ACTIVE :STD_LOGIC_VECTOR(8 DOWNTO 0) := B"000000001";
-- Serial Bus Controller parameters
CONSTANT SBCW :INTEGER := 4; -- Serial bus counter's width
CONSTANT SCCW :INTEGER := 11; -- Slow clock's counter's width
-- States for finite state machine
TYPE State_Type IS ( STATE_0_IDLE,
STATE_1_PRE_WRITE,
STATE_2_WRITE_TRANSFER,
STATE_3_POST_WRITE,
STATE_4_PRE_READ,
STATE_5_READ_TRANSFER,
STATE_6_POST_READ
);
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
SIGNAL internal_reset :STD_LOGIC;
-- Auto init signals
SIGNAL rom_address :STD_LOGIC_VECTOR(AIAW DOWNTO 0);
SIGNAL rom_data :STD_LOGIC_VECTOR(DW DOWNTO 0);
SIGNAL ack :STD_LOGIC;
SIGNAL auto_init_data :STD_LOGIC_VECTOR(DW DOWNTO 0);
SIGNAL auto_init_transfer_en :STD_LOGIC;
SIGNAL auto_init_complete :STD_LOGIC;
SIGNAL auto_init_error :STD_LOGIC;
-- Serial controller signals
SIGNAL transfer_mask :STD_LOGIC_VECTOR(DW DOWNTO 0);
SIGNAL data_to_controller :STD_LOGIC_VECTOR(DW DOWNTO 0);
SIGNAL data_to_controller_on_restart :STD_LOGIC_VECTOR(DW DOWNTO 0);
SIGNAL data_from_controller :STD_LOGIC_VECTOR(DW DOWNTO 0);
SIGNAL start_transfer :STD_LOGIC;
SIGNAL transfer_complete :STD_LOGIC;
-- Internal Registers
SIGNAL control_reg :STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL address_reg :STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL data_reg :STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL start_external_transfer :STD_LOGIC;
SIGNAL external_read_transfer :STD_LOGIC;
SIGNAL address_for_transfer :STD_LOGIC_VECTOR( 7 DOWNTO 0);
SIGNAL device_for_transfer :STD_LOGIC_VECTOR( 1 DOWNTO 0);
-- State Machine Registers
SIGNAL ns_serial_transfer : State_Type;
SIGNAL s_serial_transfer : State_Type;
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
COMPONENT altera_up_av_config_auto_init
GENERIC (
ROM_SIZE :INTEGER;
AW :INTEGER;
DW :INTEGER
);
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
clear_error :IN STD_LOGIC;
ack :IN STD_LOGIC;
transfer_complete :IN STD_LOGIC;
rom_data :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
-- Bidirectionals
-- Outputs
data_out :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0);
transfer_data :BUFFER STD_LOGIC;
rom_address :BUFFER STD_LOGIC_VECTOR(AIAW DOWNTO 0);
auto_init_complete :BUFFER STD_LOGIC;
auto_init_error :BUFFER STD_LOGIC
);
END COMPONENT;
COMPONENT altera_up_av_config_auto_init_ob_de2_35
GENERIC (
VID_INPUT_CONTROL :STD_LOGIC_VECTOR(15 DOWNTO 0);
VID_CHROMA_GAIN_1 :STD_LOGIC_VECTOR(15 DOWNTO 0);
VID_CHROMA_GAIN_2 :STD_LOGIC_VECTOR(15 DOWNTO 0);
AUD_LINE_IN_LC :STD_LOGIC_VECTOR(8 DOWNTO 0);
AUD_LINE_IN_RC :STD_LOGIC_VECTOR(8 DOWNTO 0);
AUD_LINE_OUT_LC :STD_LOGIC_VECTOR(8 DOWNTO 0);
AUD_LINE_OUT_RC :STD_LOGIC_VECTOR(8 DOWNTO 0);
AUD_ADC_PATH :STD_LOGIC_VECTOR(8 DOWNTO 0);
AUD_DAC_PATH :STD_LOGIC_VECTOR(8 DOWNTO 0);
AUD_POWER :STD_LOGIC_VECTOR(8 DOWNTO 0);
AUD_DATA_FORMAT :STD_LOGIC_VECTOR(8 DOWNTO 0);
AUD_SAMPLE_CTRL :STD_LOGIC_VECTOR(8 DOWNTO 0);
AUD_SET_ACTIVE :STD_LOGIC_VECTOR(8 DOWNTO 0)
);
PORT (
-- Inputs
rom_address :IN STD_LOGIC_VECTOR(AIAW DOWNTO 0);
-- Bidirectionals
-- Outputs
rom_data :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0)
);
END COMPONENT;
COMPONENT altera_up_av_config_serial_bus_controller
GENERIC (
DW :INTEGER;
CW :INTEGER;
SCCW :INTEGER
);
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
start_transfer :IN STD_LOGIC;
data_in :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
transfer_mask :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
restart_counter :IN STD_LOGIC_VECTOR(SBCW DOWNTO 0);
restart_data_in :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
restart_transfer_mask :IN STD_LOGIC_VECTOR(26 DOWNTO 0);
-- Bidirectionals
serial_data :INOUT STD_LOGIC;
-- Outputs
serial_clk :BUFFER STD_LOGIC;
serial_en :BUFFER STD_LOGIC;
data_out :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0);
transfer_complete :BUFFER STD_LOGIC
);
END COMPONENT;
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (internal_reset = '1') THEN
s_serial_transfer <= STATE_0_IDLE;
ELSE
s_serial_transfer <= ns_serial_transfer;
END IF;
END IF;
END PROCESS;
PROCESS (ns_serial_transfer, s_serial_transfer, transfer_complete,
auto_init_complete, write, address, read, control_reg)
BEGIN
-- Defaults
ns_serial_transfer <= STATE_0_IDLE;
CASE (s_serial_transfer) IS
WHEN STATE_0_IDLE =>
IF ((transfer_complete = '1') OR (auto_init_complete = '0')) THEN
ns_serial_transfer <= STATE_0_IDLE;
ELSIF ((write = '1') AND (address = B"11")) THEN
ns_serial_transfer <= STATE_1_PRE_WRITE;
ELSIF ((read = '1') AND (address = B"11")) THEN
IF (control_reg(17 DOWNTO 16) = B"00") THEN
ns_serial_transfer <= STATE_6_POST_READ;
ELSE
ns_serial_transfer <= STATE_4_PRE_READ;
END IF;
ELSE
ns_serial_transfer <= STATE_0_IDLE;
END IF;
WHEN STATE_1_PRE_WRITE =>
ns_serial_transfer <= STATE_2_WRITE_TRANSFER;
WHEN STATE_2_WRITE_TRANSFER =>
IF (transfer_complete = '1') THEN
ns_serial_transfer <= STATE_3_POST_WRITE;
ELSE
ns_serial_transfer <= STATE_2_WRITE_TRANSFER;
END IF;
WHEN STATE_3_POST_WRITE =>
ns_serial_transfer <= STATE_0_IDLE;
WHEN STATE_4_PRE_READ =>
ns_serial_transfer <= STATE_5_READ_TRANSFER;
WHEN STATE_5_READ_TRANSFER =>
IF (transfer_complete = '1') THEN
ns_serial_transfer <= STATE_6_POST_READ;
ELSE
ns_serial_transfer <= STATE_5_READ_TRANSFER;
END IF;
WHEN STATE_6_POST_READ =>
ns_serial_transfer <= STATE_0_IDLE;
WHEN OTHERS =>
ns_serial_transfer <= STATE_0_IDLE;
END CASE;
END PROCESS;
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
-- Output regsiters
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (internal_reset = '1') THEN
readdata <= B"00000000000000000000000000000000";
ELSIF (read = '1') THEN
IF (address = B"00") THEN
readdata <= control_reg;
ELSIF (address = B"01") THEN
readdata <= B"00000000" & CFG_TYPE & B"0000000" &
(auto_init_complete AND NOT auto_init_error) & B"000000" &
(NOT start_external_transfer AND auto_init_complete) &
ack;
ELSIF (address = B"10") THEN
readdata <= address_reg;
ELSIF (control_reg(17 DOWNTO 16) = B"00") THEN
readdata <= B"00000000000000000000000" &
data_from_controller(10) &
data_from_controller( 8 DOWNTO 1);
ELSE
readdata <= B"000000000000000000000000" & data_from_controller( 8 DOWNTO 1);
END IF;
END IF;
END IF;
END PROCESS;
-- Internal regsiters
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (internal_reset = '1') THEN
control_reg <= B"00000000000000000000000000000000";
address_reg <= B"00000000000000000000000000000000";
data_reg <= B"00000000000000000000000000000000";
ELSIF ((write = '1') AND (waitrequest = '0')) THEN
-- Write to control register
IF ((address = B"00") AND (byteenable(0) = '1')) THEN
control_reg( 2 DOWNTO 1) <= writedata( 2 DOWNTO 1);
END IF;
IF ((address = B"00") AND (byteenable(2) = '1')) THEN
control_reg(17 DOWNTO 16) <= writedata(17 DOWNTO 16);
-- Write to address register
END IF;
IF ((address = B"10") AND (byteenable(0) = '1')) THEN
address_reg( 7 DOWNTO 0) <= writedata( 7 DOWNTO 0);
-- Write to data register
END IF;
IF ((address = B"11") AND (byteenable(0) = '1')) THEN
data_reg( 7 DOWNTO 0) <= writedata( 7 DOWNTO 0);
END IF;
IF ((address = B"11") AND (byteenable(1) = '1')) THEN
data_reg(15 DOWNTO 8) <= writedata(15 DOWNTO 8);
END IF;
IF ((address = B"11") AND (byteenable(2) = '1')) THEN
data_reg(23 DOWNTO 16) <= writedata(23 DOWNTO 16);
END IF;
IF ((address = B"11") AND (byteenable(3) = '1')) THEN
data_reg(31 DOWNTO 24) <= writedata(31 DOWNTO 24);
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (internal_reset = '1') THEN
start_external_transfer <= '0';
external_read_transfer <= '0';
address_for_transfer <= B"00000000";
device_for_transfer <= B"00";
ELSIF (transfer_complete = '1') THEN
start_external_transfer <= '0';
external_read_transfer <= '0';
address_for_transfer <= B"00000000";
ELSIF (s_serial_transfer = STATE_1_PRE_WRITE) THEN
start_external_transfer <= '1';
external_read_transfer <= '0';
address_for_transfer <= address_reg(7 DOWNTO 0);
device_for_transfer <= control_reg(17 DOWNTO 16);
ELSIF (s_serial_transfer = STATE_4_PRE_READ) THEN
start_external_transfer <= '1';
external_read_transfer <= '1';
address_for_transfer <= address_reg(7 DOWNTO 0);
device_for_transfer <= control_reg(17 DOWNTO 16);
END IF;
END IF;
END PROCESS;
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
-- Output Assignments
waitrequest <= '1' WHEN
((address = B"11") AND (write = '1') AND (s_serial_transfer /= STATE_1_PRE_WRITE)) OR
((address = B"11") AND (read = '1') AND (s_serial_transfer /= STATE_6_POST_READ))
ELSE '0';
irq <= '1' WHEN (control_reg(1) = '1') AND (start_external_transfer = '0') AND (auto_init_complete = '1');
-- Internal Assignments
internal_reset <= '1' WHEN (reset = '1') OR
((address = B"00") AND (write = '1') AND (byteenable(0) = '1') AND (writedata(0) = '1'))
ELSE '0';
-- Signals to the serial controller
transfer_mask <= WRITE_MASK;
data_to_controller <=
auto_init_data WHEN (auto_init_complete = '0') ELSE
(B"00110100" & '0' & address_for_transfer(6 DOWNTO 0) & data_reg(8) & '0' & data_reg(7 DOWNTO 0) & '0')
WHEN (device_for_transfer = B"00") ELSE
(B"01000000" & '0' & address_for_transfer(7 DOWNTO 0) & external_read_transfer & data_reg(7 DOWNTO 0) & '0')
WHEN (device_for_transfer = B"01") ELSE
(B"01000010" & '0' & address_for_transfer(7 DOWNTO 0) & external_read_transfer & data_reg(7 DOWNTO 0) & '0');
data_to_controller_on_restart <=
(B"01000001" & '0' & B"00000000" & '0' & B"00000000" & ack) WHEN (device_for_transfer = B"01") ELSE
(B"01000011" & '0' & B"00000000" & '0' & B"00000000" & ack);
start_transfer <= start_external_transfer WHEN (auto_init_complete = '1') ELSE auto_init_transfer_en;
-- Signals from the serial controller
ack <= data_from_controller(18) OR
data_from_controller( 9) OR
data_from_controller( 0);
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
AV_Config_Auto_Init : altera_up_av_config_auto_init
GENERIC MAP (
ROM_SIZE => AIRS,
AW => AIAW,
DW => DW
)
PORT MAP (
-- Inputs
clk => clk,
reset => internal_reset,
clear_error => '0',
ack => ack,
transfer_complete => transfer_complete,
rom_data => rom_data,
-- Bidirectionals
-- Outputs
data_out => auto_init_data,
transfer_data => auto_init_transfer_en,
rom_address => rom_address,
auto_init_complete => auto_init_complete,
auto_init_error => auto_init_error
);
Auto_Init_OB_Devices_ROM : altera_up_av_config_auto_init_ob_de2_35
GENERIC MAP (
VID_INPUT_CONTROL => B"0000000001000000",
VID_CHROMA_GAIN_1 => B"0010110111110100",
VID_CHROMA_GAIN_2 => B"0010111000000000",
AUD_LINE_IN_LC => AUD_LINE_IN_LC,
AUD_LINE_IN_RC => AUD_LINE_IN_RC,
AUD_LINE_OUT_LC => AUD_LINE_OUT_LC,
AUD_LINE_OUT_RC => AUD_LINE_OUT_RC,
AUD_ADC_PATH => AUD_ADC_PATH,
AUD_DAC_PATH => AUD_DAC_PATH,
AUD_POWER => AUD_POWER,
AUD_DATA_FORMAT => AUD_DATA_FORMAT,
AUD_SAMPLE_CTRL => AUD_SAMPLE_CTRL,
AUD_SET_ACTIVE => AUD_SET_ACTIVE
)
PORT MAP (
-- Inputs
rom_address => rom_address,
-- Bidirectionals
-- Outputs
rom_data => rom_data
);
Serial_Bus_Controller : altera_up_av_config_serial_bus_controller
GENERIC MAP (
DW => DW,
CW => SBCW,
SCCW => SCCW
)
PORT MAP (
-- Inputs
clk => clk,
reset => internal_reset,
start_transfer => start_transfer,
data_in => data_to_controller,
transfer_mask => transfer_mask,
restart_counter => RESTART_COUNTER,
restart_data_in => data_to_controller_on_restart,
restart_transfer_mask => READ_MASK,
-- Bidirectionals
serial_data => I2C_SDAT,
-- Outputs
serial_clk => I2C_SCLK,
serial_en => I2C_SCEN,
data_out => data_from_controller,
transfer_complete => transfer_complete
);
END Behaviour;
| gpl-2.0 | 1e9fd7644e535f32f445dc15f829f630 | 0.547175 | 3.389373 | false | false | false | false |
hoglet67/ElectronFpga | src/xilinx/DCM/dcm3.vhd | 1 | 2,015 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm3 is
port (CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic);
end dcm3;
architecture BEHAVIORAL of dcm3 is
signal CLK0_BUF : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLKFX_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 4.0, -- 32.00 = 16 * 20 / 10
CLKFX_MULTIPLY => 20,
CLKFX_DIVIDE => 10,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 62.50,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => CLK0_BUF,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => CLK0_BUF,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| gpl-3.0 | 8ab34eb906510728a84ae683a59f38c4 | 0.402978 | 4.314775 | false | false | false | false |
ou-cse-378/vhdl-tetris | whypcore.vhd | 1 | 7,449 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: Whypcore.vhd
-- // Date: 12/9/2004
-- // Description: WHYP Core
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity whypcore is
port (
p : out STD_LOGIC_VECTOR(15 downto 0);
destro : in STD_LOGIC_VECTOR(2 downto 0);
m : in STD_LOGIC_VECTOR(15 downto 0);
SW : in std_logic_vector(7 downto 0);
BTN4 : in std_logic;
b : in STD_LOGIC;
clk : in STD_LOGIC;
clr : in STD_LOGIC;
digload : out STD_LOGIC;
ldload: out STD_LOGIC;
t : out STD_LOGIC_VECTOR(15 downto 0);
o_Clear_Lines : out std_logic
);
end whypcore;
architecture Behavioral of whypcore is
component mux2g
generic(width:positive);
Port (
a : in std_logic_vector(width-1 downto 0);
b : in std_logic_vector(width-1 downto 0);
sel : in std_logic;
y : out std_logic_vector(width-1 downto 0)
);
end component;
component PC
port (
d : in STD_LOGIC_VECTOR (15 downto 0);
clr : in STD_LOGIC;
clk : in STD_LOGIC;
inc : in STD_LOGIC;
pload : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
component plus1a
Port ( input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(15 downto 0));
end component;
component reg
generic(width: positive);
port (
d : in STD_LOGIC_VECTOR (width-1 downto 0);
load : in STD_LOGIC;
clr : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (width-1 downto 0)
);
end component;
component WC16C_control
port (
oClearLines : out std_logic;
icode : in STD_LOGIC_VECTOR (15 downto 0);
M : in STD_LOGIC_VECTOR (15 downto 0);
BTN4 : in std_logic;
clr : in STD_LOGIC;
clk : in STD_LOGIC;
fcode : out STD_LOGIC_VECTOR (5 downto 0);
pinc : out STD_LOGIC;
pload : out STD_LOGIC;
tload : out STD_LOGIC;
nload : out STD_LOGIC;
digload : out STD_LOGIC;
iload : out STD_LOGIC;
dpush : out STD_LOGIC;
dpop : out STD_LOGIC;
tsel : out STD_LOGIC_VECTOR (2 downto 0);
nsel : out STD_LOGIC_VECTOR (1 downto 0);
ssel : out STD_LOGIC;
R : in STD_LOGIC_VECTOR (15 downto 0);
T : in STD_LOGIC_VECTOR (15 downto 0);
rsel : out STD_LOGIC;
rload : out STD_LOGIC;
rdec : out STD_LOGIC;
rpush : out STD_LOGIC;
rpop : out STD_LOGIC;
ldload : out STD_LOGIC;
psel : out STD_LOGIC;
rinsel : out STD_LOGIC
);
end component;
component ReturnStack
Port ( Rin : in std_logic_vector(15 downto 0);
rsel : in std_logic;
rload : in std_logic;
rdec : in std_logic;
clr : in std_logic;
clk : in std_logic;
rpush : in std_logic;
rpop : in std_logic;
R : out std_logic_vector(15 downto 0));
end component;
component mux8g
generic(width:positive);
Port (
a : in std_logic_vector(width-1 downto 0);
b : in std_logic_vector(width-1 downto 0);
c : in std_logic_vector(width-1 downto 0);
d : in std_logic_vector(width-1 downto 0);
e : in std_logic_vector(width-1 downto 0);
f : in std_logic_vector(width-1 downto 0);
g : in std_logic_vector(width-1 downto 0);
h : in std_logic_vector(width-1 downto 0);
sel : in std_logic_vector(2 downto 0);
y : out std_logic_vector(width-1 downto 0)
);
end component;
component datastack
port (
TLoad : in std_logic;
y1 : in STD_LOGIC_VECTOR(15 downto 0);
nsel : in STD_LOGIC_VECTOR(1 downto 0);
nload : in STD_LOGIC;
ssel : in STD_LOGIC;
clk : in STD_LOGIC;
clr : in STD_LOGIC;
dpush : in STD_LOGIC;
dpop : in STD_LOGIC;
Tin : in STD_LOGIC_VECTOR(15 downto 0);
T : out STD_LOGIC_VECTOR(15 downto 0);
N : out STD_LOGIC_VECTOR(15 downto 0);
N2 : out STD_LOGIC_VECTOR(15 downto 0)
);
end component;
component funit1
generic(width:positive);
port (
a : in STD_LOGIC_VECTOR(width-1 downto 0);
b : in STD_LOGIC_VECTOR(width-1 downto 0);
sel : in STD_LOGIC_VECTOR(5 downto 0);
y : out STD_LOGIC_VECTOR(width-1 downto 0)
);
end component;
constant bus_width: positive := 16;
signal Y: std_logic_vector(15 downto 0);
signal tC : std_logic_vector(15 downto 0);
signal tE : std_logic_vector(15 downto 0);
signal Y1: std_logic_vector(15 downto 0);
signal T1: std_logic_vector(15 downto 0);
signal TIN: std_logic_vector(15 downto 0);
signal N: std_logic_vector(15 downto 0);
signal N2: std_logic_vector(15 downto 0);
signal ICODE: std_logic_vector(15 downto 0);
signal FCODE: std_logic_vector(5 downto 0);
signal ILOAD: std_logic;
signal R: std_logic_vector(15 downto 0);
signal E1: std_logic_vector(15 downto 0);
signal E2: std_logic_vector(15 downto 0);
signal PLOAD: std_logic;
signal TLOAD: std_logic;
signal NLOAD: std_logic;
signal PINC: std_logic;
signal NSEL: std_logic_vector(1 downto 0);
signal DPUSH: std_logic;
signal DPOP: std_logic;
signal TSEL: std_logic_vector(2 downto 0);
signal SSEL: std_logic;
signal Pin: std_logic_vector(15 downto 0);
signal PS: std_logic_vector(15 downto 0);
signal P1: std_logic_vector(15 downto 0);
signal Rin: std_logic_vector(15 downto 0);
signal rsel: std_logic;
signal rload: std_logic;
signal rdec: std_logic;
signal rpush: std_logic;
signal rpop: std_logic;
signal rinsel: std_logic;
signal psel: STD_LOGIC;
begin
T <= T1;
P <= PS;
tE <= "0000000000000" & destro(2) & destro(1) & destro(0);
tC <= "00000000" & SW;
SWpmux : mux2g generic map (width => bus_width) port map
( a => M, b => R, sel => psel, y => Pin );
SWpc : pc port map
( d => Pin, clr => CLR, clk => CLK, inc => PINC, pload => PLOAD, q => PS );
SWplus1a : plus1a port map
( input => PS, output => P1 );
SWir : reg generic map (width => bus_width) port map
( d => M, load => ILOAD, clr => CLR, clk => CLK, q => ICODE );
SWwc16ccontrol : WC16C_control port map
( R => R, icode => ICODE, oClearLines => o_Clear_Lines, BTN4 => BTN4, M => M, clr => CLR, clk => CLK, fcode => FCODE, pinc => PINC, pload => PLOAD, tload => TLOAD, nload => NLOAD, digload => DIGLOAD, iload => ILOAD, dpush => DPUSH, dpop => DPOP, tsel => TSEL, nsel => NSEL, ssel => SSEL, T => T1, ldload => ldload, rload => rload, rdec => rdec, rinsel => rinsel, rsel => rsel, rpush => rpush, rpop => rpop, psel => psel );
SWrmux : mux2g generic map (width => bus_width) port map
( a => P1, b => T1, sel => rinsel, y => Rin );
SWreturnstack : ReturnStack port map
( Rin => Rin, rsel => rsel, rload => rload, rdec => rdec, clr => clr, clk => clk, rpush => rpush, rpop => rpop, r => R );
SWtmux : mux8g generic map (width => bus_width) port map
( a => Y, b => M, c => tC , d => R, e => tE, f => "0000000000000000", g => N2, h => N, sel => TSEL, y => TIN );
SWdatastack : datastack port map
( Tload => TLOAD, y1 => Y1, nsel => NSEL, nload => NLOAD, ssel => SSEL, clk => CLK, clr => CLR, dpush => DPUSH, dpop => DPOP, tin => TIN, N => N, N2 => N2, T => T1 );
SWfunit1 : funit1 generic map (width => bus_width) port map
( a => T1, b => N, sel => FCODE, y => Y );
end behavioral; | mit | 6229f9c893d6199be219b2eb0325734f | 0.59847 | 3.03669 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_Video_Scaler.vhd | 1 | 9,614 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module scales video streams on the DE boards. *
-- * *
-- ******************************************************************************
ENTITY Video_System_Video_Scaler IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
GENERIC (
DW :INTEGER := 15; -- Frame's Data Width
EW :INTEGER := 0; -- Frame's Empty Width
WIW :INTEGER := 9; -- Incoming frame's width's address width
HIW :INTEGER := 7; -- Incoming frame's height's address width
WIDTH_IN :INTEGER := 640;
WIDTH_DROP_MASK :STD_LOGIC_VECTOR( 3 DOWNTO 0) := B"0101";
HEIGHT_DROP_MASK :STD_LOGIC_VECTOR( 3 DOWNTO 0) := B"0000";
MH_WW :INTEGER := 8; -- Multiply height's incoming width's address width
MH_WIDTH_IN :INTEGER := 320; -- Multiply height's incoming width
MH_CW :INTEGER := 0; -- Multiply height's counter width
MW_CW :INTEGER := 0 -- Multiply width's counter width
);
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
stream_in_data :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_in_startofpacket :IN STD_LOGIC;
stream_in_endofpacket :IN STD_LOGIC;
stream_in_empty :IN STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_in_valid :IN STD_LOGIC;
stream_out_ready :IN STD_LOGIC;
-- Bidirectional
-- Outputs
stream_in_ready :BUFFER STD_LOGIC;
stream_out_data :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_empty :BUFFER STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_out_valid :BUFFER STD_LOGIC
);
END Video_System_Video_Scaler;
ARCHITECTURE Behaviour OF Video_System_Video_Scaler IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
SIGNAL internal_data :STD_LOGIC_VECTOR(DW DOWNTO 0);
SIGNAL internal_startofpacket :STD_LOGIC;
SIGNAL internal_endofpacket :STD_LOGIC;
SIGNAL internal_valid :STD_LOGIC;
SIGNAL internal_ready :STD_LOGIC;
-- Internal Registers
-- State Machine Registers
-- Integers
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
COMPONENT altera_up_video_scaler_shrink
GENERIC (
DW :INTEGER;
WW :INTEGER;
HW :INTEGER;
WIDTH_IN :INTEGER;
WIDTH_DROP_MASK :STD_LOGIC_VECTOR( 3 DOWNTO 0);
HEIGHT_DROP_MASK :STD_LOGIC_VECTOR( 3 DOWNTO 0)
);
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
stream_in_data :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_in_startofpacket :IN STD_LOGIC;
stream_in_endofpacket :IN STD_LOGIC;
stream_in_valid :IN STD_LOGIC;
stream_out_ready :IN STD_LOGIC;
-- Bidirectional
-- Outputs
stream_in_ready :BUFFER STD_LOGIC;
stream_out_data :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_valid :BUFFER STD_LOGIC
);
END COMPONENT;
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
-- Output Registers
-- Internal Registers
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
-- Output Assignments
stream_out_empty <= (OTHERS => '0');
-- Internal Assignments
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
Shrink_Frame : altera_up_video_scaler_shrink
GENERIC MAP (
DW => DW,
WW => WIW,
HW => HIW,
WIDTH_IN => WIDTH_IN,
WIDTH_DROP_MASK => WIDTH_DROP_MASK,
HEIGHT_DROP_MASK => HEIGHT_DROP_MASK
)
PORT MAP (
-- Inputs
clk => clk,
reset => reset,
stream_in_data => stream_in_data,
stream_in_startofpacket => stream_in_startofpacket,
stream_in_endofpacket => stream_in_endofpacket,
stream_in_valid => stream_in_valid,
stream_out_ready => stream_out_ready,
-- Bidirectional
-- Outputs
stream_in_ready => stream_in_ready,
stream_out_data => stream_out_data,
stream_out_startofpacket => stream_out_startofpacket,
stream_out_endofpacket => stream_out_endofpacket,
stream_out_valid => stream_out_valid
);
END Behaviour;
| gpl-2.0 | 28325017e18b9d31de9c11f3115fe849 | 0.452153 | 4.552083 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/simul/simul_pkg.vhdl | 1 | 11,558 | --
-- Simul Package
-- Package of Simul, with additional procedures and functions only for simulations.
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2015-2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library STD;
use STD.textio.all;
package Simul is
----------------------------------------------------------------------------
-- Print
----------------------------------------------------------------------------
procedure print(message: character; reps: positive:=1);
procedure print(message: string; reps: positive:=1);
----------------------------------------------------------------------------
-- Convertions
----------------------------------------------------------------------------
function hex2bin(arg: string) return string;
function bin2hex(arg: string) return string;
function to_str(arg: std_logic_vector; format: character:='B') return string;
function to_str(arg: unsigned; format: character:='B') return string;
function to_str(arg: signed; format: character:='B') return string;
function to_str(arg: integer) return string;
function to_char(arg: integer) return character;
function to_char(arg: std_logic) return character;
function to_char(arg: std_logic_vector(7 downto 0)) return character;
function to_logic(arg: character) return std_logic;
function to_vector(arg: string) return std_logic_vector;
----------------------------------------------------------------------------
-- Read/Write
----------------------------------------------------------------------------
procedure read(l: inout line; value: out std_logic);
procedure read(l: inout line; value: out std_logic; good: out boolean);
procedure read(l: inout line; value: out std_logic_vector);
procedure read(l: inout line; value: out std_logic_vector; good: out boolean);
procedure write(l: inout line; value: in std_logic);
procedure write(l: inout line; value: in std_logic_vector);
----------------------------------------------------------------------------
-- Components
----------------------------------------------------------------------------
component Clock is
generic(
FREQUENCY : positive:=25e6; -- Hz
PERIOD : time:=0 sec; -- Used insted of FREQUENCY when greater than 0 sec
RESET_CLKS : real:=1.5 -- Reset duration expresed in clocks
);
port(
clk_o : out std_logic;
rst_o : out std_logic;
stop_i : in boolean:=FALSE -- Stop clock generation
);
end component Clock;
----------------------------------------------------------------------------
end package Simul;
package body Simul is
----------------------------------------------------------------------------
-- Print
----------------------------------------------------------------------------
procedure print(message: character; reps: positive:=1) is
variable l : line;
begin
for i in 1 to reps loop
write(l,message);
end loop;
writeline(output,l);
end procedure print;
procedure print(message: string; reps: positive:=1) is
variable l : line;
begin
for i in 1 to reps loop
write(l,message);
end loop;
writeline(output,l);
end procedure print;
----------------------------------------------------------------------------
-- Conversions bin <> hex
----------------------------------------------------------------------------
function hex2bin(arg: string) return string is
variable bin : string(1 to (arg'length * 4));
variable index : integer;
variable char : character;
begin
index := 1;
for i in arg'range loop
char := arg(i);
case char is
when '0' => bin(index to index+3) := "0000";
when '1' => bin(index to index+3) := "0001";
when '2' => bin(index to index+3) := "0010";
when '3' => bin(index to index+3) := "0011";
when '4' => bin(index to index+3) := "0100";
when '5' => bin(index to index+3) := "0101";
when '6' => bin(index to index+3) := "0110";
when '7' => bin(index to index+3) := "0111";
when '8' => bin(index to index+3) := "1000";
when '9' => bin(index to index+3) := "1001";
when 'A'|'a' => bin(index to index+3) := "1010";
when 'B'|'b' => bin(index to index+3) := "1011";
when 'C'|'c' => bin(index to index+3) := "1100";
when 'D'|'d' => bin(index to index+3) := "1101";
when 'E'|'e' => bin(index to index+3) := "1110";
when 'F'|'f' => bin(index to index+3) := "1111";
--
when 'Z'|'z' => bin(index to index+3) := "ZZZZ";
when 'L'|'l' => bin(index to index+3) := "LLLL";
when 'H'|'h' => bin(index to index+3) := "HHHH";
when 'U'|'u' => bin(index to index+3) := "UUUU";
when 'W'|'w' => bin(index to index+3) := "WWWW";
when others => bin(index to index+3) := "XXXX";
end case;
index := index + 4;
end loop;
return bin;
end hex2bin;
function bin2hex(arg: string) return string is
constant high : positive:=arg'length/4;
variable hex : string(1 to high);
variable index : integer;
variable str : string(1 to 4);
begin
index := 0;
for i in 1 to high loop
str := arg((i*4-3) to (i*4));
case str is
when "0000" => hex(index+1):='0';
when "0001" => hex(index+1):='1';
when "0010" => hex(index+1):='2';
when "0011" => hex(index+1):='3';
when "0100" => hex(index+1):='4';
when "0101" => hex(index+1):='5';
when "0110" => hex(index+1):='6';
when "0111" => hex(index+1):='7';
when "1000" => hex(index+1):='8';
when "1001" => hex(index+1):='9';
when "1010" => hex(index+1):='A';
when "1011" => hex(index+1):='B';
when "1100" => hex(index+1):='C';
when "1101" => hex(index+1):='D';
when "1110" => hex(index+1):='E';
when "1111" => hex(index+1):='F';
--
when "ZZZZ" => hex(index+1):='Z';
when "LLLL" => hex(index+1):='L';
when "HHHH" => hex(index+1):='H';
when "UUUU" => hex(index+1):='U';
when "WWWW" => hex(index+1):='W';
when others => hex(index+1):='X';
end case;
index := index + 1;
end loop;
return hex;
end function bin2hex;
----------------------------------------------------------------------------
-- Conversions to string
----------------------------------------------------------------------------
function to_str(arg: std_logic_vector; format: character:='B') return string is
variable str : string (1 to arg'length);
variable index : integer;
begin
index := 1;
for i in arg'range loop
str(index) := to_char(arg(i));
index := index + 1;
end loop;
if format='B' or format='b' then
return str;
end if;
if format='H' or format='h' then
return bin2hex(str);
end if;
report "to_str: unsupported format parameter ("&format&")" severity failure;
return str;
end to_str;
function to_str(arg: unsigned; format: character:='B') return string is
begin
return to_str(std_logic_vector(arg), format);
end function to_str;
function to_str(arg: signed; format: character:='B') return string is
begin
return to_str(std_logic_vector(arg), format);
end function to_str;
function to_str(arg: integer) return string is
begin
return integer'image(arg);
end function to_str;
----------------------------------------------------------------------------
-- Conversions to char
----------------------------------------------------------------------------
function to_char(arg: integer) return character is
begin
return character'val(arg);
end to_char;
function to_char(arg: std_logic) return character is
variable str : string(1 to 3);
begin
str:=std_logic'image(arg);
return str(2);
end to_char;
function to_char(arg: std_logic_vector(7 downto 0)) return character is
begin
return character'val(to_integer(unsigned(arg)));
end function to_char;
----------------------------------------------------------------------------
-- Conversions to standard logic
----------------------------------------------------------------------------
function to_logic(arg: character) return std_logic is
variable sl: std_logic;
begin
case arg is
when '0' => sl := '0';
when '1' => sl := '1';
when '-' => sl := '-';
when 'U'|'u' => sl := 'U';
when 'X'|'x' => sl := 'X';
when 'Z'|'z' => sl := 'Z';
when 'W'|'w' => sl := 'W';
when 'L'|'l' => sl := 'L';
when 'H'|'h' => sl := 'H';
when others => sl := 'X';
end case;
return sl;
end to_logic;
function to_vector(arg: string) return std_logic_vector is
variable slv : std_logic_vector(arg'length-1 downto 0);
variable index : integer;
begin
index := arg'length-1;
for i in arg'range loop
slv(index) := to_logic(arg(i));
index := index - 1;
end loop;
return slv;
end to_vector;
----------------------------------------------------------------------------
-- Read/Write
----------------------------------------------------------------------------
procedure read(l: inout line; value: out std_logic) is
variable str : string(1 downto 1);
begin
read(l,str);
value:=to_logic(str(1));
end procedure read;
procedure read(l: inout line; value: out std_logic; good: out boolean) is
variable str : string(1 downto 1);
variable ok : boolean;
begin
read(l,str,ok);
good:=ok;
if ok then
value:=to_logic(str(1));
end if;
end procedure read;
procedure read(l: inout line; value: out std_logic_vector) is
variable str : string(value'length downto 1);
begin
read(l,str);
value:=to_vector(str);
end procedure read;
procedure read(l: inout line; value: out std_logic_vector; good: out boolean) is
variable str : string(value'length downto 1);
variable ok : boolean;
begin
read(l,str,ok);
good:=ok;
if ok then
value:=to_vector(str);
end if;
end procedure read;
procedure write(l: inout line; value: in std_logic) is
variable str : string(3 downto 1);
begin
str:=std_logic'image(value);
write(l,str(2));
end procedure write;
procedure write(l: inout line; value: in std_logic_vector) is
variable str : string(3 downto 1);
begin
for i in value'range loop
str:=std_logic'image(value(i));
write(l,str(2));
end loop;
end procedure write;
----------------------------------------------------------------------------
end package body Simul;
| bsd-3-clause | 27666967628bef4d32fa1f87ad276256 | 0.462796 | 4.212099 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/mems/FIFO.vhdl | 1 | 8,496 | --
-- FIFO
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017-2019 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
-- Description:
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library FPGALIB;
use FPGALIB.MEMS.all;
use FPGALIB.Numeric.all;
use FPGALIB.Sync.all;
--! A FIFO which could be configured as synchronous or asynchronous.
--! In synchronous mode, the clock in both sides, write and read, must be the
--! same. In asynchronous mode, the clocks can be unrelated and so extra
--! resources for CDC are employed.
--! There are full, almost full and overflow indications in the Write side and
--! valid, empty, almost empty and underflow indications in the Read side.
--! The almost empty and full indications can be configured by generics, as
--! the offset to reach empty and full respectively.
entity FIFO is
generic (
DWIDTH : positive:=8; --! Data width (bits)
DEPTH : positive:=8; --! Buffer memory depth (even)
OUTREG : boolean :=FALSE; --! Optional Output Register
AFULLOFFSET : positive:=1; --! Almost FULL OFFSET
AEMPTYOFFSET : positive:=1; --! Almost EMPTY OFFSET
ASYNC : boolean :=TRUE --! Asynchronous FIFO
);
port (
-- write side
wclk_i : in std_logic; --! Write Clock
wrst_i : in std_logic; --! Write Reset
wen_i : in std_logic; --! Write Enable
data_i : in std_logic_vector(DWIDTH-1 downto 0); --! Data Input
full_o : out std_logic; --! Full Flag
afull_o : out std_logic; --! Almost Full Flag
overflow_o : out std_logic; --! Overflow Flag
-- read side
rclk_i : in std_logic; --! Read Clock
rrst_i : in std_logic; --! Read Reset
ren_i : in std_logic; --! Read enable
data_o : out std_logic_vector(DWIDTH-1 downto 0); --! Data Output
empty_o : out std_logic; --! Empty flag
aempty_o : out std_logic; --! Almost Empty flag
underflow_o : out std_logic; --! Underflow Flag
valid_o : out std_logic --! Read Valid
);
end entity FIFO;
--! @brief Architecture definition of the FIFO.
architecture RTL of FIFO is
------------------------------------------------------------------------------------------------
-- Constants
------------------------------------------------------------------------------------------------
constant EVEN_DEPTH : positive := DEPTH + (DEPTH rem 2); -- To ensure only even values
constant AWIDTH : positive := clog2(EVEN_DEPTH); -- Address width in bits
constant DIFF_DEPTH : natural := 2**AWIDTH-EVEN_DEPTH;
------------------------------------------------------------------------------------------------
-- Signals
------------------------------------------------------------------------------------------------
signal rst : std_logic;
signal wen, ren : std_logic;
signal full, full_r : std_logic;
signal empty, empty_r : std_logic;
signal wr_addr, rd_addr : std_logic_vector(AWIDTH-1 downto 0);
signal valid_r : std_logic_vector(1 downto 0):=(others => '0');
-- Extra bit used for empty and full generation
signal wr_ptr_r, wr_ptr, rd_in_wr_ptr : unsigned(AWIDTH downto 0):=(others => '0');
signal rd_ptr_r, rd_ptr, wr_in_rd_ptr : unsigned(AWIDTH downto 0):=(others => '0');
-- For asynchronous version
signal wr_bin, rd_in_wr_bin : unsigned(AWIDTH downto 0);
signal rd_bin, wr_in_rd_bin : unsigned(AWIDTH downto 0);
------------------------------------------------------------------------------------------------
-- Functions
------------------------------------------------------------------------------------------------
function next_ptr(ena : std_logic; ptr: unsigned) return unsigned is
variable ret : unsigned(ptr'range);
begin
if ena='1' and ptr(AWIDTH-1 downto 0)=EVEN_DEPTH-1 then
ret := (not(ptr(AWIDTH)), others => '0');
elsif ena='1' then
ret := ptr + 1;
else
ret := ptr;
end if;
return ret;
end next_ptr;
function diff_ptr(wr_ptr, rd_ptr : unsigned) return unsigned is
variable status : std_logic_vector(1 downto 0);
variable wr_aux, rd_aux : unsigned(wr_ptr'range);
begin
status := wr_ptr(AWIDTH)&rd_ptr(AWIDTH);
case status is
when "00" | "11" =>
return wr_ptr - rd_ptr;
when "10" =>
return wr_ptr - DIFF_DEPTH - rd_ptr;
when "01" =>
wr_aux := not(wr_ptr(AWIDTH))&wr_ptr(AWIDTH-1 downto 0);
rd_aux := not(rd_ptr(AWIDTH))&rd_ptr(AWIDTH-1 downto 0);
return wr_aux - DIFF_DEPTH - rd_aux;
when others =>
wr_aux := (others => '0');
end case;
return wr_aux;
end diff_ptr;
begin
rst <= wrst_i or rrst_i;
i_memory: SimpleDualPortRAM
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH,
DEPTH => EVEN_DEPTH,
OUTREG => OUTREG
)
port map (
clk1_i => wclk_i,
clk2_i => rclk_i,
wen1_i => wen,
addr1_i => wr_addr,
addr2_i => rd_addr,
data1_i => data_i,
data2_o => data_o
);
g_sync: if not(ASYNC) generate
rd_in_wr_ptr <= rd_ptr_r;
wr_in_rd_ptr <= wr_ptr_r;
end generate g_sync;
g_async: if ASYNC generate
-----------------------------------
-- From read to write side (CDC) --
-----------------------------------
rd_bin <= rd_ptr_r + DIFF_DEPTH when rd_ptr_r(AWIDTH)='0' else rd_ptr_r;
i_sync_rd2wr: gray_sync
generic map(WIDTH => AWIDTH+1, DEPTH => 2)
port map(clk_i => wclk_i, data_i => rd_bin, data_o => rd_in_wr_bin);
rd_in_wr_ptr <= rd_in_wr_bin - DIFF_DEPTH when rd_in_wr_bin(AWIDTH)='0' else rd_in_wr_bin;
-----------------------------------
-- From write to read side (CDC) --
-----------------------------------
wr_bin <= wr_ptr_r + DIFF_DEPTH when wr_ptr_r(AWIDTH)='0' else wr_ptr_r;
i_sync_wr2rd: gray_sync
generic map(WIDTH => AWIDTH+1, DEPTH => 2)
port map(clk_i => rclk_i, data_i => wr_bin, data_o => wr_in_rd_bin);
wr_in_rd_ptr <= wr_in_rd_bin - DIFF_DEPTH when wr_in_rd_bin(AWIDTH)='0' else wr_in_rd_bin;
end generate g_async;
------------------------------------------------------------------------------------------------
-- Write Side
------------------------------------------------------------------------------------------------
wr_addr <= std_logic_vector(wr_ptr_r(AWIDTH-1 downto 0));
wen <= '1' when wen_i='1' and full_r/='1' else '0';
p_write:
process(wclk_i)
begin
if rising_edge(wclk_i) then
full_r <= '0';
if rst='1' then
wr_ptr_r <= (others => '0');
else
wr_ptr_r <= wr_ptr;
full_r <= full;
end if;
end if;
end process p_write;
wr_ptr <= next_ptr(wen, wr_ptr_r);
full <= '1' when diff_ptr(wr_ptr, rd_in_wr_ptr) = EVEN_DEPTH else '0';
full_o <= full;
afull_o <= '1' when diff_ptr(wr_ptr, rd_in_wr_ptr) >= EVEN_DEPTH-AFULLOFFSET else '0';
overflow_o <= '1' when wen_i='1' and full_r='1' else '0';
------------------------------------------------------------------------------------------------
-- Read Side
------------------------------------------------------------------------------------------------
rd_addr <= std_logic_vector(rd_ptr_r(AWIDTH-1 downto 0));
ren <= '1' when ren_i='1' and empty_r/='1' else '0';
p_read:
process(rclk_i)
begin
if rising_edge(rclk_i) then
empty_r <= '1';
valid_r(0) <= ren;
valid_r(1) <= valid_r(0);
if rst='1' then
rd_ptr_r <= (others => '0');
valid_r <= (others => '0');
else
rd_ptr_r <= rd_ptr;
empty_r <= empty;
end if;
end if;
end process p_read;
rd_ptr <= next_ptr(ren, rd_ptr_r);
empty <= '1' when diff_ptr(wr_in_rd_ptr, rd_ptr) = 0 else '0';
empty_o <= empty;
aempty_o <= '1' when diff_ptr(wr_in_rd_ptr, rd_ptr) <= AEMPTYOFFSET else '0';
underflow_o <= '1' when ren_i='1' and empty_r='1' else '0';
valid_o <= valid_r(1) when OUTREG else valid_r(0);
end architecture RTL;
| bsd-3-clause | 560483e5975d146256442bd0be59b98d | 0.483051 | 3.710044 | false | false | false | false |
marzoul/PoC | tb/io/uart/uart_rx_tb.vhdl | 1 | 3,824 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Module: uart_rx_tb
--
-- Authors: Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- Testbench for arith_counter_bcd
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
use PoC.simulation.all;
use PoC.uart.all;
entity uart_rx_tb is
end entity;
architecture tb of uart_rx_tb is
constant CLOCK_FREQ : FREQ := 100 MHz;
constant BAUDRATE : BAUD := 4.2 MBd;
signal Clock : STD_LOGIC;
signal Reset : STD_LOGIC;
signal BitClock : STD_LOGIC;
signal BitClock_x8 : STD_LOGIC;
signal UART_RX : STD_LOGIC;
signal RX_Strobe : STD_LOGIC;
signal RX_Data : T_SLV_8;
function simGenerateWaveform_UART_Word(Data : T_SLV_8; Baudrate : BAUD := 115.200 kBd) return T_SIM_WAVEFORM_SL is
constant BIT_TIME : TIME := to_time(to_freq(Baudrate));
variable Result : T_SIM_WAVEFORM_SL(0 to 9) := (others => (Delay => BIT_TIME, Value => '-'));
begin
Result(0).Value := '0';
for i in Data'range loop
Result(i + 1).Value := Data(i);
end loop;
Result(9).Value := '1';
return Result;
end function;
function simGenerateWaveform_UART_Stream(Data : T_SLVV_8; Baudrate : BAUD := 115.200 kBd) return T_SIM_WAVEFORM_SL is
variable Result : T_SIM_WAVEFORM_SL(0 to (Data'length * 10) - 1);
begin
for i in Data'range loop
Result(i * 10 to ((i + 1) * 10) - 1) := simGenerateWaveform_UART_Word(Data(i), BAUDRATE);
end loop;
return Result;
end function;
constant DATA_STREAM : T_SLVV_8 := (x"12", x"45", x"FE", x"C4", x"02");
begin
simGenerateClock(Clock, CLOCK_FREQ);
simGenerateWaveform(Reset, simGenerateWaveform_Reset(Pause => 50 ns));
simGenerateWaveform(UART_RX, simGenerateWaveform_UART_Stream(DATA_STREAM, BAUDRATE), '1');
bclk : entity PoC.uart_bclk
generic map (
CLOCK_FREQ => CLOCK_FREQ,
BAUDRATE => BAUDRATE
)
port map (
clk => Clock,
rst => Reset,
bclk => BitClock,
bclk_x8 => BitClock_x8
);
RX : entity PoC.uart_rx
generic map (
OUT_REGS => FALSE
)
port map (
clk => Clock,
rst => Reset,
bclk_x8 => BitClock_x8,
dos => RX_Strobe,
dout => RX_Data,
rxd => UART_RX
);
process
begin
for i in DATA_STREAM'range loop
wait until rising_edge(Clock) and (RX_Strobe = '1');
report TIME'image(NOW) severity NOTE;
tbAssert((RX_Data = DATA_STREAM(i)), "Data Byte " & INTEGER'image(i) & " received: " & to_string(RX_Data, 'h') & " expected: " & to_string(DATA_STREAM(i), 'h'));
end loop;
wait for 1 us;
simStop;
tbPrintResult;
wait;
end process;
end architecture;
| apache-2.0 | 5a650741f1f1f8e264a37c6105d4e4b4 | 0.607479 | 3.197324 | false | false | false | false |
DreamIP/GPStudio | support/process/harris/hdl/harris_pack.vhd | 1 | 3,116 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--use ieee.math_real.all;
library std;
library altera_mf;
use altera_mf.altera_mf_components.all;
package harris_package_components is
shared variable RESULT_LENGTH:integer:=44;
shared variable FILTER_RESULT_LENGTH:integer:=28;
type pixel_matrix is array (0 to 6,0 to 6) of std_logic_vector(7 downto 0);
type filter_matrix is array (0 to 6,0 to 6) of std_logic_vector((FILTER_RESULT_LENGTH-1) downto 0);
component LPM_MULT
generic ( LPM_WIDTHA : natural;
LPM_WIDTHB : natural;
LPM_WIDTHS : natural:=1;
LPM_WIDTHP : natural;
LPM_REPRESENTATION : string:="SIGNED";
LPM_PIPELINE : natural:=0;
LPM_TYPE : string;
LPM_HINT : string:="UNUSED");
port ( DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
ACLR : in std_logic :='0';
SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0):=(OTHERS=>'0');
RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
end component;
component LPM_COMPARE
generic ( LPM_WIDTH : natural:=RESULT_LENGTH;
LPM_REPRESENTATION : string:="SIGNED";
LPM_PIPELINE : natural:=0;
LPM_TYPE : string:="LPM_COMPARE";
LPM_HINT : string:="UNUSED");
port ( DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
ACLR : in std_logic :='0';
AGB : out std_logic;
AGEB : out std_logic;
AEB : out std_logic;
ANEB : out std_logic;
ALB : out std_logic;
ALEB : out std_logic);
end component;
component LPM_ADD_SUB
generic ( LPM_WIDTH : natural:=RESULT_LENGTH;
LPM_DIRECTION : string:="ADD";
LPM_REPRESENTATION : string:="SIGNED";
LPM_PIPELINE : natural:=0;
LPM_TYPE : string:="LPM_ADD_SUB";
LPM_HINT : string:="UNUSED");
port ( DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
ACLR : in std_logic:='0';
CLOCK : in std_logic:='0';
CLKEN : in std_logic:='1';
CIN : in std_logic:='Z';
ADD_SUB : in std_logic:='1';
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
COUT : out std_logic;
OVERFLOW : out std_logic);
end component;
end harris_package_components;
| gpl-3.0 | 14bfdb1bbc4d90fffa7f2dca111f204f | 0.476573 | 4.176944 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/video_system_cpu_jtag_debug_module_translator.vhd | 1 | 12,740 | -- video_system_cpu_jtag_debug_module_translator.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.09.14:34:21
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity video_system_cpu_jtag_debug_module_translator is
generic (
AV_ADDRESS_W : integer := 9;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(31 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(8 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_begintransfer : out std_logic; -- .begintransfer
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_chipselect : out std_logic; -- .chipselect
av_debugaccess : out std_logic; -- .debugaccess
av_beginbursttransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_clken : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_read : out std_logic;
av_readdatavalid : in std_logic := '0';
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(3 downto 0);
uav_clken : in std_logic := '0'
);
end entity video_system_cpu_jtag_debug_module_translator;
architecture rtl of video_system_cpu_jtag_debug_module_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(8 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_chipselect : out std_logic; -- chipselect
av_debugaccess : out std_logic; -- debugaccess
av_read : out std_logic; -- read
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_outputenable : out std_logic -- outputenable
);
end component altera_merlin_slave_translator;
begin
cpu_jtag_debug_module_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_begintransfer => av_begintransfer, -- .begintransfer
av_byteenable => av_byteenable, -- .byteenable
av_chipselect => av_chipselect, -- .chipselect
av_debugaccess => av_debugaccess, -- .debugaccess
av_read => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_outputenable => open -- (terminated)
);
end architecture rtl; -- of video_system_cpu_jtag_debug_module_translator
| gpl-2.0 | 38f970e9be1479fc1de22a805ae74a2f | 0.432339 | 4.320109 | false | false | false | false |
DreamIP/GPStudio | support/process/AveragingFilter/hdl/AveragingFilter.vhd | 1 | 3,953 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity AveragingFilter is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end AveragingFilter;
architecture rtl of AveragingFilter is
component AveragingFilter_process
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_width : in std_logic_vector(15 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component AveragingFilter_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal widthimg_reg_width : std_logic_vector (15 downto 0);
begin
AveragingFilter_process_inst : AveragingFilter_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_width => widthimg_reg_width,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
AveragingFilter_slave_inst : AveragingFilter_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_width => widthimg_reg_width,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
| gpl-3.0 | f5697e632c62016d7656975d53a63f26 | 0.471035 | 3.390223 | false | false | false | false |
ou-cse-378/vhdl-tetris | funit1.vhd | 1 | 3,489 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: funit1.vhd
-- // Date: 12/9/2004
-- // Description: ALU Functional Unit
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity funit1 is
generic(width:positive);
port (
a : in STD_LOGIC_VECTOR(width-1 downto 0);
b : in STD_LOGIC_VECTOR(width-1 downto 0);
sel : in STD_LOGIC_VECTOR(5 downto 0);
y : out STD_LOGIC_VECTOR(width-1 downto 0)
);
end funit1;
architecture funit1_arch of funit1 is
begin
funit_1: process(a, b, sel)
variable true, false, z: STD_LOGIC_VECTOR (width-1 downto 0);
variable avs, bvs: signed (width-1 downto 0);
begin
-- true is all ones; false is all zeros
for i in 0 to width-1 loop
true(i) := '1';
false(i) := '0';
z(i) := '0';
avs(i) := a(i);
bvs(i) := b(i);
end loop;
case sel is
when "010000" => -- +
y <= b + a;
when "010001" => -- -
y <= b - a;
when "010010" => -- 1+
y <= a + 1;
when "010011" => -- 1-
y <= a - 1;
when "010100" => -- COMPLIMENT
y <= not(a);
when "010101" => -- AND
y <= b AND a;
when "010110" => -- OR
y <= b OR a;
when "010111" => -- XOR
y <= b XOR a;
when "011000" => -- 2*
y <= a(width-2 downto 0) & '0';
when "011001" => -- U2/
y <= '0' & a(width-1 downto 1);
when "011010" => -- 2/
y <= a(width-1) & a(width-1 downto 1);
when "011011" => -- RSHIFT
y <= SHR(b,a);
when "011100" => -- LSHIFT
y <= SHL(b,a);
--when "011101" => -- Reserved for multiplication
-- y <=
--when "011110" => -- Reserved for division
-- y <=
when "100000" => -- TRUE
y <= true;
when "100001" => -- FALSE
y <= false;
when "100010" => -- NOT 0=
if a = false then
y <= true;
else
y <= false;
end if;
when "100011" => -- 0<
if a < 0 then
y <= true;
else
y <= false;
end if;
when "100100" => -- U>
if b > a then
y <= true;
else
y <= false;
end if;
when "100101" => -- U<
if b < a then
y <= true;
else
y <= false;
end if;
when "100110" => -- =
if b = a then
y <= true;
else
y <= false;
end if;
when "100111" => -- U>=
if b >= a then
y <= true;
else
y <= false;
end if;
when "101000" => -- U<=
if b <= a then
y <= true;
else
y <= false;
end if;
when "101001" => -- <>
if b /= a then
y <= true;
else
y <= false;
end if;
when "101010" => -- >
if bvs > avs then
y <= true;
else
y <= false;
end if;
when "101011" => -- <
if bvs < avs then
y <= true;
else
y <= false;
end if;
when "101100" => -- >=
if bvs >= avs then
y <= true;
else
y <= false;
end if;
when others => -- <=
if bvs <= avs then
y <= true;
else
y <= false;
end if;
end case;
end process funit_1;
end funit1_arch; | mit | 6117a00cba2e70bd935cb470674a3124 | 0.421611 | 2.949281 | false | false | false | false |
SonicFrog/ArchOrd | progcounter.vhdl | 1 | 1,005 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ProgCounter is
port (
Reset : in std_logic;
Clk : in std_logic;
MaxCount : in std_logic_vector(3 downto 0);
Load : in std_logic;
Count : out std_logic_vector(3 downto 0):
Zero : out std_logic
);
end entity; --ProgCounter
architecture synth of progcounter is
signal max_value : std_logic_vector(3 downto 0);
signal current_value : std_logic_vector(3 downto 0);
begin
Zero <= current_value = 0;
--Process handling reset and setting the maximum count
load : process(Clk, Reset, MaxCount)
begin
if falling_edge(clk) then
if Reset = '1' then
current_value <= (others => '0');
elsif Load = '1' then
max_value <= MaxCount;
end if;
end if;
end process;
--Process handling the counting
counting : process(clk)
begin
if falling_edge(clk) then
current_value <= current_value + 1;
end if;
end process;
end architecture ; -- synth | gpl-2.0 | edd41c6a5b4a21aee4b2f7c780220e83 | 0.677612 | 2.830986 | false | false | false | false |
DreamIP/GPStudio | support/component/gp_com/com_to_flow/com_flow_fifo_rx.vhd | 1 | 12,552 | -- **************************************************************************
-- ComFlowFifo
-- **************************************************************************
--
-- 16/10/2014 - creation
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity com_flow_fifo_rx is
generic (
FIFO_DEPTH : POSITIVE := 1024;
FLOW_ID : INTEGER := 1;
IN_SIZE : POSITIVE := 16;
OUT_SIZE : POSITIVE := 16
);
port (
clk_hal : in std_logic;
clk_proc : in std_logic;
rst_n : in std_logic;
data_wr_i : in std_logic;
data_i : in std_logic_vector(IN_SIZE-1 downto 0);
rdreq_i : in std_logic;
pktend_i : in std_logic;
enable_i : in std_logic;
data_o : out std_logic_vector(OUT_SIZE-1 downto 0);
flow_rdy_o : out std_logic;
f_empty_o : out std_logic;
fifos_f_o : out std_logic;
flag_o : out std_logic_vector(7 downto 0)
);
end com_flow_fifo_rx;
architecture rtl of com_flow_fifo_rx is
---------------------------------------------------------
-- COMPONENT DECLARATION
---------------------------------------------------------
component fifo_com_rx IS
generic (
DEPTH : POSITIVE := FIFO_DEPTH;
IN_SIZE : POSITIVE;
OUT_SIZE : POSITIVE
);
port (
aclr : in std_logic := '0';
data : in std_logic_vector(IN_SIZE-1 downto 0);
rdclk : in std_logic;
rdreq : in std_logic;
wrclk : in std_logic;
wrreq : in std_logic;
q : out std_logic_vector(OUT_SIZE-1 downto 0);
rdempty : out std_logic;
wrfull : out std_logic
);
end component;
component synchronizer
generic (
CDC_SYNC_FF_CHAIN_DEPTH: integer := 2 -- CDC Flip flop Chain depth
);
port (
signal_i : in std_logic;
signal_o : out std_logic;
clk_i : in std_logic;
clk_o : in std_logic
);
end component;
---------------------------------------------------------
-- SIGNALS
---------------------------------------------------------
-------------
-- FIFO 1 SIGNALS
-------------
signal fifo_1_data_s : std_logic_vector(IN_SIZE-1 downto 0) := (others=>'0');
signal fifo_1_wrclk_s : std_logic := '0';
signal fifo_1_wrreq_s : std_logic := '0';
signal fifo_1_wrfull_s : std_logic := '0';
signal fifo_1_q_s : std_logic_vector(OUT_SIZE-1 downto 0) := (others=>'0');
signal fifo_1_rdclk_s : std_logic := '0';
signal fifo_1_rdreq_s : std_logic := '0';
signal fifo_1_rdempty_s : std_logic := '0';
-- registers
signal fifo_1_readable : std_logic := '0';
signal fifo_1_rdempty_r : std_logic := '0';
signal fifo_1_rdempty_rr : std_logic := '0';
signal flag_fifo1 : std_logic_vector(7 downto 0) := (others=>'0');
signal fifo_1_aclr_s : std_logic :='0';
-------------
-- FIFO 2 SIGNALS
-------------
signal fifo_2_data_s : std_logic_vector(IN_SIZE-1 downto 0) := (others=>'0');
signal fifo_2_wrclk_s : std_logic := '0';
signal fifo_2_wrreq_s : std_logic := '0';
signal fifo_2_wrfull_s : std_logic := '0';
signal fifo_2_q_s : std_logic_vector(OUT_SIZE-1 downto 0) := (others=>'0');
signal fifo_2_rdclk_s : std_logic := '0';
signal fifo_2_rdreq_s : std_logic := '0';
signal fifo_2_rdempty_s : std_logic := '0';
signal fifo_2_aclr_s : std_logic := '0';
-- registers
signal fifo_2_readable : std_logic := '0';
signal fifo_2_rdempty_r : std_logic := '0';
signal fifo_2_rdempty_rr : std_logic := '0';
signal flag_fifo2 : std_logic_vector(7 downto 0) := (others=>'0');
-------------
-- FSM Signal
-------------
type fsm_state_t is (Idle, Flag8, DecodeFN, DecodeFN8, DecodeFN8_low, ReceivePacket, SwapFifos, Full, tmp);
signal fsm_state : fsm_state_t := Idle;
-- mux/demux fifos
signal fifo_sel : std_logic:= '0';
-- flag
signal data_wr_r : std_logic:= '0';
signal data_wr_r2 : std_logic:= '0';
signal frame_number : std_logic_vector(15 downto 0) := (others=>'0');
signal cur_fifo_wrreq_s : std_logic := '0';
signal cur_fifo_data_s : std_logic_vector(IN_SIZE-1 downto 0) := (others=>'0');
signal cur_fifo_readable : std_logic := '0';
signal cur_fifo_readable_r : std_logic := '0';
signal other_fifo_readable : std_logic := '0';
signal cur_fifo_full_s : std_logic := '0';
signal flow_rdy_s : std_logic := '0';
begin
-------
-- MAP CLK
-------
fifo_1_wrclk_s <= clk_hal;
fifo_2_wrclk_s <= clk_hal;
fifo_1_rdclk_s <= clk_proc;
fifo_2_rdclk_s <= clk_proc;
flow_rdy_s <= fifo_1_readable or fifo_2_readable;
FIFO_1 : fifo_com_rx
generic map (
DEPTH => FIFO_DEPTH,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
aclr => fifo_1_aclr_s,
data => fifo_1_data_s,
rdclk => fifo_1_rdclk_s,
rdreq => fifo_1_rdreq_s,
wrclk => fifo_1_wrclk_s,
wrreq => fifo_1_wrreq_s,
q => fifo_1_q_s,
rdempty => fifo_1_rdempty_s,
wrfull => fifo_1_wrfull_s
);
FIFO_2 : fifo_com_rx
generic map (
DEPTH => FIFO_DEPTH,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
aclr => fifo_2_aclr_s,
data => fifo_2_data_s,
rdclk => fifo_2_rdclk_s,
rdreq => fifo_2_rdreq_s,
wrclk => fifo_2_wrclk_s,
wrreq => fifo_2_wrreq_s,
q => fifo_2_q_s,
rdempty => fifo_2_rdempty_s,
wrfull => fifo_2_wrfull_s
);
-- CDC Synchronizer
Sync_inst : component synchronizer
generic map (
CDC_SYNC_FF_CHAIN_DEPTH => 2
)
port map (
clk_i => clk_hal,
clk_o => clk_proc,
signal_i => flow_rdy_s,
signal_o => flow_rdy_o
);
fifo_1_aclr_s <= not(rst_n or enable_i);
fifo_2_aclr_s <= not(rst_n or enable_i);
FSM : process (clk_hal, rst_n)
begin
if (rst_n = '0') then
cur_fifo_wrreq_s <= '0';
fifos_f_o <='0';
cur_fifo_readable <= '0';
fifo_sel <= '0';
fsm_state <= Idle;
-- flag_s <= (others=>'0');
-- data_wr_r <='0';
frame_number <= (others=>'0');
elsif (rising_edge(clk_hal)) then
data_wr_r <= data_wr_i;
data_wr_r2 <= data_wr_r;
case fsm_state is
when Idle =>
-- si un packet vient de l USB
if (enable_i='1' and data_wr_r ='0' and data_wr_i ='1') then
-- flag_s <= data_i; le flag est gere dans un process specifique
-- on check si le paquet est pour nous
if (data_i(IN_SIZE-1 downto IN_SIZE-8) = std_logic_vector(to_unsigned(FLOW_ID,8)) ) then
if(IN_SIZE = 16) then
fsm_state <= DecodeFN;
else
fsm_state <= Flag8;
end if;
else
fsm_state <= Idle;
end if;
end if;
when Flag8 =>
fsm_state <= DecodeFN8;
-- on lit le frane number
when DecodeFN =>
frame_number(IN_SIZE-1 downto 0) <= data_i;
fsm_state <= ReceivePacket;
when DecodeFN8 =>
frame_number(15 downto 8) <= data_i(7 downto 0);
fsm_state <= DecodeFN8_low;
when DecodeFN8_low =>
frame_number(7 downto 0) <= data_i(7 downto 0);
fsm_state <= ReceivePacket;
-- reception du packet USB
when ReceivePacket =>
cur_fifo_wrreq_s <= '1'; -- on ecrit la fifo courante
cur_fifo_data_s <= data_i;
if (cur_fifo_full_s = '1' or pktend_i = '1') then
-- si le paquet est arrive on indique que
-- la fifo courante est disponible à la lecture en sortie
cur_fifo_readable <= '1';
cur_fifo_wrreq_s <= '0'; -- deassert cur_fifo_wrreq
-- si les deux fifos sont full => etat FULL
if (other_fifo_readable ='1') then
fsm_state <= Full;
else -- sinon on swap les deux fifos
-- fifo_sel <= not (fifo_sel);
-- fsm_state <= Idle;
fsm_state <= SwapFifos;
end if;
end if;
when SwapFifos =>
cur_fifo_readable <= '0';
fifo_sel <= not (fifo_sel);
fsm_state <= Idle;
when Full =>
fifos_f_o <= '1';
if (other_fifo_readable='0') then
-- fifo_sel <= not (fifo_sel);
-- fsm_state <= tmp;
fifos_f_o <= '0';
cur_fifo_readable <= '0';
fifo_sel <= not (fifo_sel);
fsm_state <= Idle;
end if;
-- TODO A enlever: creer un coup d'horloge d'attente apres une fin de full
when tmp =>
fifos_f_o <='0';
cur_fifo_readable <= '0';
fifo_sel <= not (fifo_sel);
fsm_state <= Idle;
end case;
end if;
end process;
-- Gere l'etat des flags fifos pretes a etre lues
READABLE_PROCESS : process(clk_hal, rst_n)
begin
if (rst_n = '0') then
fifo_1_readable <='0';
fifo_2_readable <='0';
elsif rising_edge(clk_hal) then
-- register values for rising/falling edge detection on signals
fifo_1_rdempty_r <= fifo_1_rdempty_s;
fifo_1_rdempty_rr <= fifo_1_rdempty_r; -- double registert to prevent for CDC metastability
fifo_2_rdempty_r <= fifo_2_rdempty_s;
fifo_2_rdempty_rr <= fifo_2_rdempty_r;
--~ if (fifo_1_rdempty_r ='0' and fifo_1_rdempty_s='1') then
if (fifo_1_rdempty_rr ='0' and fifo_1_rdempty_r='1') then
fifo_1_readable <= '0';
end if;
--~ if (fifo_2_rdempty_r ='0' and fifo_2_rdempty_s='1') then
if (fifo_2_rdempty_rr ='0' and fifo_2_rdempty_r='1') then
fifo_2_readable <= '0';
end if;
case (fifo_sel) is -- mise a jour
when '0' =>
fifo_1_readable <= cur_fifo_readable;
-- fifo_2_readable <= fifo_2_readable;
when '1' =>
-- fifo_1_readable <= fifo_1_readable;
fifo_2_readable <= cur_fifo_readable;
when others =>
fifo_1_readable <= '0';
fifo_2_readable <= '0';
end case;
end if;
end process;
--
FLAG_PROCESS : process(clk_hal, rst_n)
begin
if (rst_n = '0') then
flag_fifo1 <= (others=>'0');
flag_fifo2 <= (others=>'0');
elsif rising_edge(clk_hal) then
--data_wr_r <= data_wr_i; -- deja fait dans le FSM Process
if ((data_wr_r ='0' and data_wr_i = '1' and IN_SIZE=16) or (data_wr_r2 ='0' and data_wr_i = '1' and IN_SIZE=8)) then
case (fifo_sel) is -- mise a jour
when '0' =>
-- le flag est situé dans les 8 LSB du premier mot qui arrive dans l'USB
flag_fifo1 <= data_i(7 downto 0);
when '1' =>
flag_fifo2 <= data_i(7 downto 0);
when others =>
flag_fifo1 <= (others=>'0');
flag_fifo2 <= (others=>'0');
end case;
else
flag_fifo1 <= flag_fifo1;
flag_fifo2 <= flag_fifo2;
end if;
end if;
end process;
-- en cas de dysfonctionnement, gerer le flag_o dans le process FLAG_PROCESS
-- utiliser le signal de lecture pour mettre àjour le registre flag_o
with fifo_sel select
flag_o <= flag_fifo1 when '1',
flag_fifo2 when '0',
(others=>'0') when others;
-- fifos connection according to sel position
FIFO_SEL_MUX : process (fifo_sel,cur_fifo_data_s,cur_fifo_wrreq_s,fifo_1_readable,fifo_2_readable,fifo_1_wrfull_s,fifo_2_wrfull_s,rdreq_i,fifo_1_q_s,fifo_2_q_s,fifo_1_rdempty_s,fifo_2_rdempty_s)
begin
case (fifo_sel) is
when '0' =>
fifo_1_wrreq_s <= cur_fifo_wrreq_s;
fifo_1_data_s <= cur_fifo_data_s;
fifo_2_data_s <= (others=>'0');
fifo_2_wrreq_s <= '0';
other_fifo_readable <= fifo_2_readable;
cur_fifo_full_s <= fifo_1_wrfull_s;
-- Flag et signaux pour lecture dans fifos
fifo_1_rdreq_s <= '0';
fifo_2_rdreq_s <= rdreq_i;
data_o <= fifo_2_q_s;
f_empty_o <= fifo_2_rdempty_s;
when '1' =>
fifo_1_wrreq_s <= '0';
fifo_2_wrreq_s <= cur_fifo_wrreq_s;
fifo_1_data_s <= (others=>'0');
fifo_2_data_s <= cur_fifo_data_s;
other_fifo_readable <= fifo_1_readable;
cur_fifo_full_s <= fifo_2_wrfull_s;
-- Flag et signaux pour lecture dans fifos
fifo_1_rdreq_s <= rdreq_i;
fifo_2_rdreq_s <= '0';
data_o <= fifo_1_q_s;
f_empty_o <= fifo_1_rdempty_s;
when others =>
fifo_1_wrreq_s <= cur_fifo_wrreq_s;
fifo_2_wrreq_s <= '0';
end case;
end process;
end rtl;
| gpl-3.0 | 405ceb933c88d607a759d20fd7886e97 | 0.52081 | 2.931744 | false | false | false | false |
ou-cse-378/vhdl-tetris | tetris_control.vhd | 1 | 33,721 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: tetris_control.vhd
-- // Date: 12/9/2004
-- // Description: Tetris program controller
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity tetris_control is
port
(
clk: in STD_LOGIC;
clr: in STD_LOGIC;
i_buttons: in STD_LOGIC_VECTOR(7 downto 0); -- controller buttons vector
i_block_code: in STD_LOGIC_VECTOR(2 downto 0); -- 0..7, chooses next block
o_load_xpos: out STD_LOGIC; -- '1' when xreg should be loaded with xpos
o_xpos_val: out STD_LOGIC_VECTOR(3 downto 0); -- 0..9 < 16
o_load_ypos: out STD_LOGIC; -- '1' when yreg should be loaded with ypos
o_ypos_val: out STD_LOGIC_VECTOR(4 downto 0); -- 0..19 < 32
o_load_block: out STD_LOGIC; -- '1' when blockreg should be loaded with shape
o_block_val: out STD_LOGIC_VECTOR(15 downto 0); -- 4x4 block, '1' = SOLID
o_paused: out STD_LOGIC; -- '1' when the game is paused
-- // for fetching rows into and out of tetris_control / ramtable
i_row_val: in STD_LOGIC_VECTOR(15 downto 0);
o_row_fetch: out STD_LOGIC; -- '1' when i_row_val should be loaded for i_row_no
o_row_load: out STD_LOGIC; -- '1' when o_row_val should br put for o_row_no
o_row_no: out STD_LOGIC_VECTOR(4 downto 0); -- 0..19 < 32
o_row_val: out STD_LOGIC_VECTOR(15 downto 0);
o_Lines_Destroyed : out std_logic_vector(2 downto 0);
i_Clear_Lines : in std_logic
);
end tetris_control;
architecture tetris_control_arch of tetris_control is
type state_type is
(
startup,
purge,
wait_for_start,
read_nes_pad,
make_block,
move_left,
move_right,
move_down,
check_down,
check_down2,
rot_right,
rot_left,
fetch_in_row0,
fetch_in_row1,
fetch_in_row2,
write_out_row0,
write_out_row,
kill_row,
kill_row2,
kill_row3,
kill_row4
);
-- // the number of clock cycles that pass before the block will drop
-- // 50,000,000 = 1 Hz = 1 second
constant C_READ_GAME_INPUT_MAX_TICKS: positive := 50000000;
--constant C_READ_GAME_INPUT_MAX_TICKS: positive := 20;
-- // the number of ticks to wait between controller commands (buffering)
constant C_MASTER_READ_WAIT_TICKS: positive := 25000000 / 5;
--constant C_MASTER_READ_WAIT_TICKS: positive := 10;
-- // the grid offset for to the first position (x,y) on screen
constant C_GRID_OFFSET: positive := 3;
constant C_READ_BUTTON_A_WAIT_TICKS: positive := C_MASTER_READ_WAIT_TICKS*2;
constant C_READ_BUTTON_B_WAIT_TICKS: positive := C_MASTER_READ_WAIT_TICKS*2;
constant C_READ_BUTTON_SELECT_WAIT_TICKS: positive := C_MASTER_READ_WAIT_TICKS;
constant C_READ_BUTTON_START_WAIT_TICKS: positive := C_MASTER_READ_WAIT_TICKS*4;
constant C_READ_BUTTON_UP_WAIT_TICKS: positive := C_MASTER_READ_WAIT_TICKS/2;
constant C_READ_BUTTON_DOWN_WAIT_TICKS: positive := C_MASTER_READ_WAIT_TICKS/2;
constant C_READ_BUTTON_LEFT_WAIT_TICKS: positive := C_MASTER_READ_WAIT_TICKS/2;
constant C_READ_BUTTON_RIGHT_WAIT_TICKS: positive := C_MASTER_READ_WAIT_TICKS/2;
-- // indexes to breakout the individual buttons from the button vector
constant BUTTON_A: integer := 7;
constant BUTTON_B: integer := 6;
constant BUTTON_SELECT: integer := 5;
constant BUTTON_START: integer := 4;
constant BUTTON_UP: integer := 3;
constant BUTTON_DOWN: integer := 2;
constant BUTTON_LEFT: integer := 1;
constant BUTTON_RIGHT: integer := 0;
-- // the current count of clock cycles past since the last reset
signal t_read_game_input_ticks: std_logic_vector(31 downto 0) := X"00000000";
-- // counts up the number of rows that have been "purged" / reset
signal t_purge_counter : integer := 0;
signal t_Lines_Destroyed : std_logic_vector(2 downto 0) := "000";
signal t_kill_counter : integer := 0;
-- // the number of ticks that the controller input is disabled
signal t_button_a_wait_ticks_remain: std_logic_vector(31 downto 0) := X"00000000";
signal t_button_b_wait_ticks_remain: std_logic_vector(31 downto 0) := X"00000000";
signal t_button_select_wait_ticks_remain: std_logic_vector(31 downto 0) := X"00000000";
signal t_button_start_wait_ticks_remain: std_logic_vector(31 downto 0) := X"00000000";
signal t_button_up_wait_ticks_remain: std_logic_vector(31 downto 0) := X"00000000";
signal t_button_down_wait_ticks_remain: std_logic_vector(31 downto 0) := X"00000000";
signal t_button_left_wait_ticks_remain: std_logic_vector(31 downto 0) := X"00000000";
signal t_button_right_wait_ticks_remain: std_logic_vector(31 downto 0) := X"00000000";
signal t_lines_killed : std_logic_vector(2 downto 0) := "000";
signal t_condense_inner_counter : integer := 23;
signal t_condense_outer_counter : integer := 0;
signal t_Shift_row : std_logic := '0';
signal t_condenseB : std_logic_vector(15 downto 0) := "0000000000000000";
signal t_condenseA : std_logic_vector(15 downto 0) := "0000000000000000";
-- // signals holding for the states set for the program
signal current_state, next_state: state_type;
-- // the current block shape
signal t_block_val : std_logic_vector(15 downto 0) := X"0000";
-- // the x-position of the block on the grid
signal t_xpos : std_logic_vector(3 downto 0) := "0011";
-- // the y-position of the block on the grid
signal t_ypos : std_logic_vector(4 downto 0) := "00011";
-- // '1' when the read_nes_pad state should write out rows / make block
signal t_down_movement_done : std_logic := '0';
-- // '1' when the fetch_row routines should stop looping
signal t_row_fetches_done : std_logic := '1';
-- // temp work variable for storing the last row processed in reading / writing
signal t_last_row_processed : std_logic_vector(4 downto 0) := "00011";
-- // cached row data around and below the current piece
signal t_row0_data : std_logic_vector(15 downto 0) := X"0000";
signal t_row1_data : std_logic_vector(15 downto 0) := X"0000";
signal t_row2_data : std_logic_vector(15 downto 0) := X"0000";
signal t_row3_data : std_logic_vector(15 downto 0) := X"0000";
signal t_row4_data : std_logic_vector(15 downto 0) := X"0000";
begin
-- // =================================================================
-- // process for clear, setting up first state, next state progression
-- // also increments counter for clock cycles processed
-- // =================================================================
synch: process(clk, clr)
begin
if clr = '1' then -- on clear
current_state <= startup;
elsif (clk'event and clk = '1') then -- on the rising edge of the clock
-- // set the next state
current_state <= next_state;
end if;
end process synch;
-- // =================================================================
-- // process for setting up the next state based on the current state
-- // =================================================================
C1: process(current_state,
t_read_game_input_ticks,
t_button_a_wait_ticks_remain,
t_button_b_wait_ticks_remain,
t_button_select_wait_ticks_remain,
t_button_start_wait_ticks_remain,
t_button_up_wait_ticks_remain,
t_button_down_wait_ticks_remain,
t_button_left_wait_ticks_remain,
t_button_right_wait_ticks_remain,
i_buttons,
t_last_row_processed,
t_purge_counter, t_block_val, t_row_fetches_done, t_down_movement_done, t_ypos, t_kill_counter,t_condense_outer_counter, t_Shift_row,t_condense_inner_counter)
begin
case current_state is
when startup =>
next_state <= purge;
when purge =>
if t_purge_counter < 32 then
next_state <= purge;
else
next_state <= wait_for_start;
end if;
when wait_for_start =>
-- // wait for START button depressed, else keep waiting
if i_buttons(BUTTON_START) = '1' then
if t_button_start_wait_ticks_remain = X"00000000" then
-- // TRUE when we haven't recently done something on button press
if t_block_val /= X"0000" then
next_state <= read_nes_pad;
else
next_state <= make_block;
end if;
else
-- // OR FALSE when we need to just keep waiting (next_state <= this)
next_state <= wait_for_start;
end if;
else
next_state <= wait_for_start;
end if;
when read_nes_pad =>
-- // we get out of the read loop state when we have spent a certain number
-- // of clock ticks here, the move and rot states return back to here
if t_read_game_input_ticks < C_READ_GAME_INPUT_MAX_TICKS then
-- // ==============================================
-- // ALL IN GAME BUTTON next states are set here
-- // ==============================================
if i_buttons(BUTTON_LEFT) = '1' then
if t_button_left_wait_ticks_remain = X"00000000" then
-- // TRUE when we haven't recently done something on button press
next_state <= move_left;
else
-- // OR FALSE when we need to just keep waiting (next_state <= this)
next_state <= read_nes_pad;
end if;
elsif i_buttons(BUTTON_RIGHT) = '1' then
if t_button_right_wait_ticks_remain = X"00000000" then
-- // TRUE when we haven't recently done something on button press
next_state <= move_right;
else
-- // OR FALSE when we need to just keep waiting (next_state <= this)
next_state <= read_nes_pad;
end if;
elsif i_buttons(BUTTON_B) = '1' then
if t_button_b_wait_ticks_remain = X"00000000" then
-- // TRUE when we haven't recently done something on button press
next_state <= rot_left;
else
-- // OR FALSE when we need to just keep waiting (next_state <= this)
next_state <= read_nes_pad;
end if;
elsif i_buttons(BUTTON_A) = '1' then
if t_button_a_wait_ticks_remain = X"00000000" then
-- // TRUE when we haven't recently done something on button press
next_state <= rot_right;
else
-- // OR FALSE when we need to just keep waiting (next_state <= this)
next_state <= read_nes_pad;
end if;
elsif i_buttons(BUTTON_START) = '1' then
if t_button_start_wait_ticks_remain = X"00000000" then
-- // TRUE when we haven't recently done something on button press
next_state <= wait_for_start;
else
-- // OR FALSE when we need to just keep waiting (next_state <= this)
next_state <= read_nes_pad;
end if;
elsif i_buttons(BUTTON_DOWN) = '1' then
if t_button_down_wait_ticks_remain = X"00000000" then
-- // TRUE when we haven't recently done something on button press
next_state <= move_down;
else
-- // OR FALSE when we need to just keep waiting (next_state <= this)
next_state <= read_nes_pad;
end if;
else
next_state <= read_nes_pad;
end if;
else
next_state <= move_down;
end if;
when make_block =>
-- // pull random number from random number generator
-- // use random number to get a block and write it into
-- // current block description RAM
-- // dump the starting block position out to the xreg, yreg
next_state <= read_nes_pad;
when fetch_in_row0 =>
next_state <= fetch_in_row1;
when fetch_in_row1 =>
if t_row_fetches_done /= '1' then
next_state <= fetch_in_row2;
else
next_state <= check_down;
end if;
when fetch_in_row2 =>
next_state <= fetch_in_row1;
when check_down =>
next_state <= check_down2;
when check_down2 =>
if t_down_movement_done = '1' then
next_state <= write_out_row0;
else
next_state <= read_nes_pad;
end if;
when move_down =>
next_state <= fetch_in_row0;
when move_left =>
next_state <= read_nes_pad;
when move_right =>
next_state <= read_nes_pad;
when rot_left =>
next_state <= read_nes_pad;
when rot_right =>
next_state <= read_nes_pad;
when write_out_row0 =>
next_state <= write_out_row;
when write_out_row =>
if t_last_row_processed = t_ypos + 4 then
next_state <= kill_row;
else
next_state <= write_out_row;
end if;
when kill_row =>
if t_kill_counter <= 22 then
next_state <= kill_row2;
else
next_state <= kill_row4;
end if;
when kill_row2 =>
next_state <= kill_row3;
when kill_row3 =>
next_state <= kill_row;
when kill_row4 =>
next_state <= make_block; --condense0;
end case;
end process C1;
C2: process(current_state, clr, clk)
-- // is set to '1' when the process should clear current clock
-- // cycle count to zero rather than increment it
variable p_read_game_input_clear: std_logic := '0';
-- // temp variable used by make block
variable p_block_val: std_logic_vector(15 downto 0) := X"0000";
-- // what the block would look like rotated to the left
variable p_block_left : std_logic_vector(15 downto 0) := X"0000";
-- // what the block would look like rotated to the right
variable p_block_right : std_logic_vector(15 downto 0) := X"0000";
-- // temporary variables
variable p_tmp_work : std_logic_vector(3 downto 0) := "0000";
variable p_tmp_var : std_logic := '0';
-- // temporary x,y position
variable p_ypos : integer range 26 downto 0 := 0;
variable p_xpos : integer range 16 downto 0 := 0;
-- // the data behind / near the block at its current position
variable p_data_behind_block : std_logic_vector(15 downto 0) := X"0000";
variable p_data_below_block : std_logic_vector(3 downto 0) := "0000";
variable p_data_right_of_block : std_logic_vector(3 downto 0) := "0000";
variable p_data_left_of_block : std_logic_vector(3 downto 0) := "0000";
-- // '1' when named action is allowed for the current state of block
variable p_move_down_ok : std_logic := '0';
variable p_move_left_ok : std_logic := '0';
variable p_move_right_ok : std_logic := '0';
variable p_rotate_right_ok : std_logic := '0';
variable p_rotate_left_ok : std_logic := '0';
-- // row data if the current t_block were committed to the row data
variable p_row0_final_data : std_logic_vector(15 downto 0) := X"0000";
variable p_row1_final_data : std_logic_vector(15 downto 0) := X"0000";
variable p_row2_final_data : std_logic_vector(15 downto 0) := X"0000";
variable p_row3_final_data : std_logic_vector(15 downto 0) := X"0000";
-- // first filled columns and rows
variable p_first_filled_column_from_left : integer := 0;
variable p_first_filled_column_from_right : integer := 0;
variable p_first_filled_row_from_bottom : integer := 0;
begin
if (clr = '1') then
t_Shift_row <= '0';
t_condenseA <= "0000000000000000";
t_condenseB <= "0000000000000000";
t_condense_inner_counter <= 23;
t_condense_outer_counter <= 0;
t_read_game_input_ticks <= X"00000000";
t_purge_counter <= 0;
t_button_a_wait_ticks_remain <= X"00000000";
t_button_b_wait_ticks_remain <= X"00000000";
t_button_select_wait_ticks_remain <= X"00000000";
t_button_start_wait_ticks_remain <= X"00000000";
t_button_up_wait_ticks_remain <= X"00000000";
t_button_down_wait_ticks_remain <= X"00000000";
t_button_left_wait_ticks_remain <= X"00000000";
t_button_right_wait_ticks_remain <= X"00000000";
t_Lines_Destroyed <= "000";
o_Lines_Destroyed <= "000";
t_block_val <= X"0000";
t_xpos <= "0011";
t_ypos <= "00011";
t_down_movement_done <= '0';
t_row_fetches_done <= '1';
t_last_row_processed <= "00011";
t_row0_data <= X"0000";
t_row1_data <= X"0000";
t_row2_data <= X"0000";
t_row3_data <= X"0000";
t_row4_data <= X"0000";
t_kill_counter <= 3;
p_read_game_input_clear := '0';
p_block_val := X"0000";
p_block_left := X"0000";
p_block_right := X"0000";
p_tmp_work := "0000";
p_tmp_var := '0';
p_ypos := 0;
p_xpos := 0;
p_data_behind_block := X"0000";
p_data_below_block := "0000";
p_data_right_of_block := "0000";
p_data_left_of_block := "0000";
p_move_down_ok := '0';
p_move_left_ok := '0';
p_move_right_ok := '0';
p_rotate_right_ok := '0';
p_rotate_left_ok := '0';
p_row0_final_data := X"0000";
p_row1_final_data := X"0000";
p_row2_final_data := X"0000";
p_row3_final_data := X"0000";
p_first_filled_column_from_left := 0;
p_first_filled_column_from_right := 0;
p_first_filled_row_from_bottom := 0;
t_Shift_row <= '0';
elsif (clk'event and clk = '1') then
if i_Clear_Lines = '1' then
t_Lines_Destroyed <= "000";
o_Lines_Destroyed <= t_Lines_Destroyed;
end if;
-- // by default, don't load new xpos, ypos, or blocks
o_load_xpos <= '0';
o_xpos_val <= "0000";
o_load_ypos <= '0';
o_ypos_val <= "00000";
o_load_block <= '0';
o_block_val <= X"0000";
o_row_fetch <= '0';
o_row_load <= '0';
o_row_no <= "00000";
o_row_val <= X"0000";
p_block_val := t_block_val;
p_xpos := CONV_INTEGER(t_xpos);
p_ypos := CONV_INTEGER(t_ypos);
p_read_game_input_clear := '0';
p_tmp_var := '0';
-- // by default we are not paused
o_paused <= '0';
-- // predetermine the rotated forms of the current piece
p_block_left := p_block_val(3) & p_block_val(7) & p_block_val(11) & p_block_val(15) &
p_block_val(2) & p_block_val(6) & p_block_val(10) & p_block_val(14) &
p_block_val(1) & p_block_val(5) & p_block_val(9) & p_block_val(13) &
p_block_val(0) & p_block_val(4) & p_block_val(8) & p_block_val(12);
p_block_right := p_block_val(12) & p_block_val(8) & p_block_val(4) & p_block_val(0) &
p_block_val(13) & p_block_val(9) & p_block_val(5) & p_block_val(1) &
p_block_val(14) & p_block_val(10) & p_block_val(6) & p_block_val(2) &
p_block_val(15) & p_block_val(11) & p_block_val(7) & p_block_val(3);
-- // fetch data behind / near the block using the position of the current block
for i in 0 to 3 loop
p_data_behind_block(15 - i) := t_row0_data(15 - p_xpos - i);
p_data_behind_block(11 - i) := t_row1_data(15 - p_xpos - i);
p_data_behind_block(7 - i) := t_row2_data(15 - p_xpos - i);
p_data_behind_block(3 - i) := t_row3_data(15 - p_xpos - i);
end loop;
-- // find the first row (from bottom to top) on the piece that contains a bit
if ((t_block_val(12) or t_block_val(13) or t_block_val(14) or t_block_val(15)) = '1') then
p_first_filled_row_from_bottom := 3;
elsif ((t_block_val(8) or t_block_val(9) or t_block_val(10) or t_block_val(11)) = '1') then
p_first_filled_row_from_bottom := 2;
elsif ((t_block_val(4) or t_block_val(5) or t_block_val(6) or t_block_val(7)) = '1') then
p_first_filled_row_from_bottom := 1;
else
p_first_filled_row_from_bottom := 0;
end if;
-- // find the first column (from right to left) on the piece that contains a bit
if ((t_block_val(3) or t_block_val(7) or t_block_val(11) or t_block_val(15)) = '1') then
p_first_filled_column_from_right := 3;
elsif ((t_block_val(2) or t_block_val(6) or t_block_val(10) or t_block_val(14)) = '1') then
p_first_filled_column_from_right := 2;
elsif ((t_block_val(1) or t_block_val(5) or t_block_val(9) or t_block_val(13)) = '1') then
p_first_filled_column_from_right := 1;
else
p_first_filled_column_from_right := 0;
end if;
-- // find the first column (from left to right) on the piece that contains a bit
if ((t_block_val(0) or t_block_val(4) or t_block_val(8) or t_block_val(12)) = '1') then
p_first_filled_column_from_left := 0;
elsif ((t_block_val(1) or t_block_val(5) or t_block_val(9) or t_block_val(13)) = '1') then
p_first_filled_column_from_left := 1;
elsif ((t_block_val(2) or t_block_val(6) or t_block_val(10) or t_block_val(14)) = '1') then
p_first_filled_column_from_left := 2;
else
p_first_filled_column_from_left := 3;
end if;
-- // fetch data below
for i in 0 to 3 loop
p_data_below_block(3 - i) := t_row4_data(15 - p_xpos - i);
end loop;
-- // fetch data to the right
--Changed from 0...3 to 1...4
p_data_right_of_block(3 downto 0) := t_row0_data(15 - p_xpos - 4) &
t_row1_data(15 - p_xpos - 4) &
t_row2_data(15 - p_xpos - 4) &
t_row3_data(15 - p_xpos - 4);
-- // fetch data to the left
p_data_left_of_block(3 downto 0) := t_row0_data(15 - p_xpos + 1) &
t_row1_data(15 - p_xpos + 1) &
t_row2_data(15 - p_xpos + 1) &
t_row3_data(15 - p_xpos + 1);
-- // ===========================================================
-- // perform checks to see if movements are allowed
-- // ===========================================================
-- // check downward movement
p_tmp_var := '1';
for i in 0 to 3 loop
p_tmp_var := p_tmp_var and (p_data_below_block(i) nand t_block_val(i));
end loop;
for i in 0 to 11 loop
p_tmp_var := p_tmp_var and (p_data_behind_block(i) nand t_block_val(i+4));
end loop;
if p_tmp_var = '1' then
p_move_down_ok := '1';
else
p_move_down_ok := '0';
end if;
-- // check left movement
p_tmp_var := '1';
for i in 0 to 15 loop
if i /= 15 and i /= 11 and i /= 7 and i /= 3 then -- exclude farthest right column
p_tmp_var := (p_tmp_var and (p_data_behind_block(i + 1) nand t_block_val(i)));
end if;
end loop; -- check farthest left data column
for i in 0 to 3 loop
p_tmp_var := p_tmp_var and (t_block_val(4*i+3) nand p_data_left_of_block(i));
end loop;
if p_tmp_var = '1' then
p_move_left_ok := '1';
else
p_move_left_ok := '0';
end if;
-- // check right movement
p_tmp_var := '1';
for i in 0 to 15 loop
if i /= 0 and i /= 4 and i /= 8 and i /= 12 then -- exclude farthest left column
p_tmp_var := (p_tmp_var and (p_data_behind_block(i - 1) nand t_block_val(i)));
end if;
end loop; -- check farthest right column
for i in 0 to 3 loop
p_tmp_var := p_tmp_var and (t_block_val(4*i) nand p_data_right_of_block(i));
end loop;
if p_tmp_var = '1' then
p_move_right_ok := '1';
else
p_move_right_ok := '0';
end if;
-- // check left rotation
p_tmp_var := '1';
for i in 0 to 15 loop
p_tmp_var := p_tmp_var and (p_data_behind_block(i) nand p_block_left(i));
end loop;
if p_tmp_var = '1' then
p_rotate_left_ok := '1';
else
p_rotate_left_ok := '0';
end if;
-- // check right rotation
p_tmp_var := '1';
for i in 0 to 15 loop
p_tmp_var := p_tmp_var and (p_data_behind_block(i) nand p_block_right(i));
end loop;
if p_tmp_var = '1' then
p_rotate_right_ok := '1';
else
p_rotate_right_ok := '0';
end if;
-- // =============================================================
-- // build the final piece data that will be used when writing out
-- // =============================================================
p_row0_final_data(15 downto 0) := t_row0_data(15 downto 0);
p_row1_final_data(15 downto 0) := t_row1_data(15 downto 0);
p_row2_final_data(15 downto 0) := t_row2_data(15 downto 0);
p_row3_final_data(15 downto 0) := t_row3_data(15 downto 0);
for i in 0 to 3 loop
p_row0_final_data(15 - p_xpos - i) := (t_block_val(15 - i) or t_row0_data(15 - p_xpos - i));
p_row1_final_data(15 - p_xpos - i) := (t_block_val(11 - i) or t_row1_data(15 - p_xpos - i));
p_row2_final_data(15 - p_xpos - i) := (t_block_val(7 - i) or t_row2_data(15 - p_xpos - i));
p_row3_final_data(15 - p_xpos - i) := (t_block_val(3 - i) or t_row3_data(15 - p_xpos - i));
end loop;
case current_state is
when startup =>
t_purge_counter <= 0;
when purge =>
if t_purge_counter < 3 or t_purge_counter > 22 then
o_row_val <= "1111111111111111";
else
o_row_val <= "1110000000000111";
end if;
o_row_load <= '1';
o_row_no <= CONV_STD_LOGIC_VECTOR(t_purge_counter, 5);
t_purge_counter <= t_purge_counter + 1;
when wait_for_start =>
-- // wait for START button depressed, else keep waiting
o_paused <= '1';
if (i_buttons(BUTTON_START) = '1') then
t_button_start_wait_ticks_remain <= CONV_STD_LOGIC_VECTOR(C_READ_BUTTON_START_WAIT_TICKS, 32);
end if;
when read_nes_pad =>
-- // check for controller keystrokes
when fetch_in_row0 =>
t_last_row_processed <= conv_std_logic_vector(p_ypos,5);
when fetch_in_row1 =>
o_row_fetch <= '1';
o_row_no <= t_last_row_processed;
when fetch_in_row2 =>
if (t_last_row_processed /= p_ypos + 5) then
-- // shift all rows up and shift in new row to bottom
t_row0_data <= t_row1_data;
t_row1_data <= t_row2_data;
t_row2_data <= t_row3_data;
t_row3_data <= t_row4_data;
t_row4_data <= i_row_val;
--for i in 0 to 15 loop --backwards read
-- t_row4_data(i) <= i_row_val(15 - i);
--end loop;
t_last_row_processed <= t_last_row_processed + 1;
else
t_row_fetches_done <= '1';
end if;
when move_left =>
-- // move the xreg position left
if p_move_left_ok = '1' then
o_load_xpos <= '1';
p_xpos := p_xpos - 1;
o_xpos_val <= CONV_STD_LOGIC_VECTOR(p_xpos, 4);
t_xpos <= CONV_STD_LOGIC_VECTOR(p_xpos, 4);
t_button_left_wait_ticks_remain <= CONV_STD_LOGIC_VECTOR(C_READ_BUTTON_LEFT_WAIT_TICKS, 32);
end if;
when move_right =>
-- // move the xreg position right
if p_move_right_ok = '1' then
o_load_xpos <= '1';
p_xpos := p_xpos + 1;
o_xpos_val <= CONV_STD_LOGIC_VECTOR(p_xpos, 4);
t_xpos <= CONV_STD_LOGIC_VECTOR(p_xpos, 4);
t_button_right_wait_ticks_remain <= CONV_STD_LOGIC_VECTOR(C_READ_BUTTON_RIGHT_WAIT_TICKS, 32);
end if;
when move_down =>
when check_down =>
t_row_fetches_done <= '0';
if p_move_down_ok = '0' then
t_down_movement_done <= '1';
end if;
if p_move_down_ok = '1' then
t_down_movement_done <= '0';
-- // decrement the yreg position
o_load_ypos <= '1';
p_ypos := p_ypos + 1;
o_ypos_val <= CONV_STD_LOGIC_VECTOR(p_ypos, 5);
t_ypos <= CONV_STD_LOGIC_VECTOR(p_ypos, 5);
-- // the block has moved down, reset the allowed input time
p_read_game_input_clear := '1';
t_button_down_wait_ticks_remain <= CONV_STD_LOGIC_VECTOR(C_READ_BUTTON_DOWN_WAIT_TICKS, 32);
else
--t_last_row_processed <= CONV_STD_LOGIC_VECTOR(p_ypos, 5) - 1;
end if;
when check_down2 =>
when rot_left =>
-- // rotate the piece left
if p_rotate_left_ok = '1' then
o_load_block <= '1';
t_block_val <= p_block_left;
o_block_val <= p_block_left;
p_block_val := p_block_left;
t_button_b_wait_ticks_remain <= CONV_STD_LOGIC_VECTOR(C_READ_BUTTON_B_WAIT_TICKS, 32);
end if;
when rot_right =>
-- // rotate the piece right
if p_rotate_right_ok = '1' then
o_load_block <= '1';
t_block_val <= p_block_right;
o_block_val <= p_block_right;
p_block_val := p_block_right;
t_button_a_wait_ticks_remain <= CONV_STD_LOGIC_VECTOR(C_READ_BUTTON_A_WAIT_TICKS, 32);
end if;
when make_block =>
-- // pull random number from random number generator
-- // use random number to get a block and write it into
-- // current block description RAM
-- // dump the starting block position out to the xreg, yreg
--Reset killed lines counter.
t_last_row_processed <= CONV_STD_LOGIC_VECTOR(C_GRID_OFFSET, 5);
o_load_xpos <= '1';
o_load_ypos <= '1';
o_xpos_val <= CONV_STD_LOGIC_VECTOR(C_GRID_OFFSET + 4, 4); -- 7, middle (x) of screen (+3 offset border)
o_ypos_val <= CONV_STD_LOGIC_VECTOR(C_GRID_OFFSET, 5); -- 3, top (y) of screen (+3 offset border)
-- // also store current x,y position stored in signals
t_xpos <= CONV_STD_LOGIC_VECTOR(C_GRID_OFFSET + 4, 4);
t_ypos <= CONV_STD_LOGIC_VECTOR(C_GRID_OFFSET, 5);
o_load_block <= '1';
if i_block_code = "000" then
p_block_val := "1010" & -- custom "cup" block
"1010" & -- a REAL PAIN
"1110" &
"0000";
elsif i_block_code = "001" then
p_block_val := "0000" & -- square block
"0110" &
"0110" &
"0000";
elsif i_block_code = "010" then
p_block_val := "0010" & -- tee block
"0110" &
"0010" &
"0000";
elsif i_block_code = "011" then
p_block_val := "0100" & -- bolt right block
"0110" &
"0010" &
"0000";
elsif i_block_code = "100" then
p_block_val := "0010" & -- bolt left block
"0110" &
"0100" &
"0000";
elsif i_block_code = "101" then
p_block_val := "0010" & -- arch left block
"0010" &
"0110" &
"0000";
elsif i_block_code = "110" then
p_block_val := "0100" & -- arch right block
"0100" &
"0110" &
"0000";
elsif i_block_code = "111" then
p_block_val := "0100" & -- the legendary pipe block
"0100" &
"0100" &
"0100";
end if;
t_block_val <= p_block_val;
o_block_val <= p_block_val;
when kill_row =>
--Read in row
o_row_no <= conv_std_logic_vector(t_kill_counter, 5);
when kill_row2 =>
--Make comparison.
if i_row_val = "1111111111111111" and t_kill_counter >= 3 and t_kill_counter <= 22 then
o_row_val <= "1110000000000111";
o_row_no <= conv_std_logic_vector(t_kill_counter, 5);
o_row_load <= '1';
t_lines_killed <= t_lines_killed + 1;
end if;
when kill_row3 =>
t_kill_counter <= t_kill_counter + 1;
when kill_row4 =>
t_kill_counter <= 0;
t_Lines_Destroyed <= t_lines_killed;
o_Lines_Destroyed <= t_Lines_Destroyed;
t_lines_killed <= "000";
when write_out_row0 =>
t_last_row_processed <= conv_std_logic_vector(p_ypos,5);
when write_out_row =>
t_down_movement_done <= '0';
if t_last_row_processed = p_ypos then
o_row_val <= p_row0_final_data;
o_row_load <= '1';
o_row_no <= CONV_STD_LOGIC_VECTOR(p_ypos, 5);
elsif t_last_row_processed = p_ypos + 1 then
o_row_val <= p_row1_final_data;
o_row_load <= '1';
o_row_no <= CONV_STD_LOGIC_VECTOR(p_ypos + 1, 5);
elsif t_last_row_processed = p_ypos + 2 then
o_row_val <= p_row2_final_data;
o_row_load <= '1';
o_row_no <= CONV_STD_LOGIC_VECTOR(p_ypos + 2, 5);
elsif t_last_row_processed = p_ypos + 3 then
o_row_val <= p_row3_final_data ;
o_row_load <= '1';
o_row_no <= CONV_STD_LOGIC_VECTOR(p_ypos + 3, 5);
end if;
t_last_row_processed <= t_last_row_processed + 1;
end case;
-- // either increment or clear the number of ticks that have passed
if p_read_game_input_clear = '1' then
t_read_game_input_ticks <= X"00000000";
else
t_read_game_input_ticks <= t_read_game_input_ticks + 1;
end if;
-- // decrement the no of clock cycles the read counters must wait
if t_button_a_wait_ticks_remain > X"00000000" then
t_button_a_wait_ticks_remain <= t_button_a_wait_ticks_remain - 1;
end if;
if t_button_b_wait_ticks_remain > X"00000000" then
t_button_b_wait_ticks_remain <= t_button_b_wait_ticks_remain - 1;
end if;
if t_button_start_wait_ticks_remain > X"00000000" then
t_button_start_wait_ticks_remain <= t_button_start_wait_ticks_remain - 1;
end if;
if t_button_select_wait_ticks_remain > X"00000000" then
t_button_select_wait_ticks_remain <= t_button_select_wait_ticks_remain - 1;
end if;
if t_button_up_wait_ticks_remain > X"00000000" then
t_button_up_wait_ticks_remain <= t_button_up_wait_ticks_remain - 1;
end if;
if t_button_down_wait_ticks_remain > X"00000000" then
t_button_down_wait_ticks_remain <= t_button_down_wait_ticks_remain - 1;
end if;
if t_button_left_wait_ticks_remain > X"00000000" then
t_button_left_wait_ticks_remain <= t_button_left_wait_ticks_remain - 1;
end if;
if t_button_right_wait_ticks_remain > X"00000000" then
t_button_right_wait_ticks_remain <= t_button_right_wait_ticks_remain - 1;
end if;
end if; -- // matching endif for clk='1' and clk'event
end process C2;
end; | mit | fbab7772e1d9484e943439c3b05617ab | 0.570238 | 3.032191 | false | false | false | false |
hoglet67/ElectronFpga | AtomBusMon/src/BusMonCore.vhd | 1 | 25,094 | --------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : BusMonCore.vhd
-- /___/ /\ Timestamp : 30/05/2015
-- \ \ / \
-- \___\/\___\
--
--Design Name: AtomBusMon
--Device: XC3S250E
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.OhoPack.all ;
entity BusMonCore is
generic (
num_comparators : integer := 8;
reg_width : integer := 46;
fifo_width : integer := 72;
avr_data_mem_size : integer := 1024 * 2; -- 2K is the mimimum
avr_prog_mem_size : integer := 1024 * 8 -- Default is 8K, 6809 amd Z80 need 9K
);
port (
clock_avr : in std_logic;
busmon_clk : in std_logic;
busmon_clken : in std_logic;
cpu_clk : in std_logic;
cpu_clken : in std_logic;
-- CPU Signals
Addr : in std_logic_vector(15 downto 0);
Data : in std_logic_vector(7 downto 0);
Rd_n : in std_logic;
Wr_n : in std_logic;
RdIO_n : in std_logic;
WrIO_n : in std_logic;
Sync : in std_logic;
Rdy : out std_logic;
nRSTin : in std_logic;
nRSTout : out std_logic;
CountCycle : in std_logic;
-- CPU Registers
-- unused in pure bus monitor mode
Regs : in std_logic_vector(255 downto 0);
-- CPI Specific data
PdcData : in std_logic_vector(7 downto 0) := x"00";
-- CPU Memory Read/Write
-- unused in pure bus monitor mode
RdMemOut : out std_logic;
WrMemOut : out std_logic;
RdIOOut : out std_logic;
WrIOOut : out std_logic;
ExecOut : out std_logic;
AddrOut : out std_logic_vector(15 downto 0);
DataOut : out std_logic_vector(7 downto 0);
DataIn : in std_logic_vector(7 downto 0);
Done : in std_logic;
-- Special outputs (function is CPU specific)
Special : out std_logic_vector(2 downto 0);
-- Single Step interface
SS_Single : out std_logic;
SS_Step : out std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- AVR Serial Port
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- Switches
sw_reset_cpu : in std_logic;
sw_reset_avr : in std_logic;
-- LEDs
led_bkpt : out std_logic;
led_trig0 : out std_logic;
led_trig1 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic
);
end BusMonCore;
architecture behavioral of BusMonCore is
signal cpu_reset_n : std_logic;
signal nrst_avr : std_logic;
signal nrst1 : std_logic;
signal nrst2 : std_logic;
signal nrst3 : std_logic;
-- debounce time is 2^17 / 16MHz = 8.192ms
signal nrst_counter : unsigned(17 downto 0);
signal dy_counter : std_logic_vector(31 downto 0);
signal dy_data : y2d_type ;
signal mux : std_logic_vector(7 downto 0);
signal muxsel : std_logic_vector(5 downto 0);
signal cmd_edge : std_logic;
signal cmd_edge1 : std_logic;
signal cmd_edge2 : std_logic;
signal cmd_ack : std_logic;
signal cmd_ack1 : std_logic;
signal cmd_ack2 : std_logic;
signal cmd : std_logic_vector(5 downto 0);
signal addr_sync : std_logic_vector(15 downto 0);
signal addr_inst : std_logic_vector(15 downto 0);
signal Addr1 : std_logic_vector(15 downto 0);
signal Data1 : std_logic_vector(7 downto 0);
signal ext_clk : std_logic;
signal timer0Count : std_logic_vector(23 downto 0);
signal timer1Count : std_logic_vector(23 downto 0);
signal cycleCount : std_logic_vector(23 downto 0);
signal instrCount : std_logic_vector(23 downto 0);
signal single : std_logic;
signal reset : std_logic;
signal step : std_logic;
signal bw_status : std_logic_vector(3 downto 0);
signal bw_status1 : std_logic_vector(3 downto 0);
signal auto_inc : std_logic;
signal brkpt_reg : std_logic_vector(num_comparators * reg_width - 1 downto 0);
signal brkpt_enable : std_logic;
signal brkpt_active : std_logic;
signal brkpt_active1 : std_logic;
signal watch_active : std_logic;
signal fifo_din : std_logic_vector(fifo_width - 1 downto 0);
signal fifo_dout : std_logic_vector(fifo_width - 1 downto 0);
signal fifo_empty : std_logic;
signal fifo_full : std_logic;
signal fifo_not_empty1 : std_logic;
signal fifo_not_empty2 : std_logic;
signal fifo_rd : std_logic;
signal fifo_rd_en : std_logic;
signal fifo_wr : std_logic;
signal fifo_wr_en : std_logic;
signal fifo_rst : std_logic;
signal memory_rd : std_logic;
signal memory_wr : std_logic;
signal io_rd : std_logic;
signal io_wr : std_logic;
signal exec : std_logic;
signal addr_dout_reg : std_logic_vector(23 downto 0);
signal din_reg : std_logic_vector(7 downto 0);
signal Rdy_int : std_logic;
signal unused_d6 : std_logic;
signal unused_d7 : std_logic;
signal last_done : std_logic;
signal cmd_done : std_logic;
signal reset_counter : std_logic_vector(9 downto 0);
signal dropped_counter : std_logic_vector(3 downto 0);
signal timer_mode : std_logic_vector(1 downto 0);
begin
inst_oho_dy1 : entity work.Oho_Dy1 port map (
dy_clock => clock_avr,
dy_rst_n => '1',
dy_data => dy_data,
dy_update => '1',
dy_frame => open,
dy_frameend => open,
dy_frameend_c => open,
dy_pwm => "1010",
dy_counter => dy_counter,
dy_sclk => tdin,
dy_ser => tcclk,
dy_rclk => tmosi
);
Inst_AVR8: entity work.AVR8
generic map(
CDATAMEMSIZE => avr_data_mem_size,
CPROGMEMSIZE => avr_prog_mem_size
)
port map(
clk16M => clock_avr,
nrst => nrst_avr,
portain => PdcData,
portaout => open,
-- Command Port
portbin(0) => '0',
portbin(1) => '0',
portbin(2) => '0',
portbin(3) => '0',
portbin(4) => '0',
portbin(5) => '0',
portbin(6) => '0',
portbin(7) => '0',
portbout(0) => cmd(0),
portbout(1) => cmd(1),
portbout(2) => cmd(2),
portbout(3) => cmd(3),
portbout(4) => cmd(4),
portbout(5) => cmd(5),
portbout(6) => cmd_edge,
portbout(7) => open,
-- Status Port
portdin(0) => '0',
portdin(1) => '0',
portdin(2) => '0',
portdin(3) => '0',
portdin(4) => '0',
portdin(5) => '0',
portdin(6) => cmd_ack2,
portdin(7) => fifo_not_empty2,
portdout(0) => muxsel(0),
portdout(1) => muxsel(1),
portdout(2) => muxsel(2),
portdout(3) => muxsel(3),
portdout(4) => muxsel(4),
portdout(5) => muxsel(5),
portdout(6) => unused_d6,
portdout(7) => unused_d7,
-- Mux Port
portein => mux,
porteout => open,
spi_mosio => open,
spi_scko => open,
spi_misoi => '0',
rxd => avr_RxD,
txd => avr_TxD
);
-- Syncronise signals crossing busmon_clk / clock_avr boundary
process (clock_avr)
begin
if rising_edge(clock_avr) then
fifo_not_empty1 <= not fifo_empty;
fifo_not_empty2 <= fifo_not_empty1;
cmd_ack1 <= cmd_ack;
cmd_ack2 <= cmd_ack1;
end if;
end process;
WatchEvents_inst : entity work.WatchEvents port map(
clk => busmon_clk,
srst => fifo_rst,
din => fifo_din,
wr_en => fifo_wr_en,
rd_en => fifo_rd_en,
dout => fifo_dout,
full => fifo_full,
empty => fifo_empty
);
fifo_wr_en <= fifo_wr and busmon_clken;
fifo_rd_en <= fifo_rd and busmon_clken;
-- The fifo is writen the cycle after the break point
-- Addr1 is the address bus delayed by 1 cycle
-- DataWr1 is the data being written delayed by 1 cycle
-- DataRd is the data being read, that is already one cycle late
-- bw_state1(1) is 1 for writes, and 0 for reads
fifo_din <= instrCount & dropped_counter & bw_status1 & Data1 & Addr1 & addr_inst;
-- Implement a 4-bit saturating counter of the number of dropped events
process (busmon_clk)
begin
if rising_edge(busmon_clk) then
if busmon_clken = '1' then
if fifo_rst = '1' then
dropped_counter <= x"0";
elsif fifo_wr_en = '1' then
if fifo_full = '1' then
if dropped_counter /= x"F" then
dropped_counter <= dropped_counter + 1;
end if;
else
dropped_counter <= x"0";
end if;
end if;
end if;
end if;
end process;
led_trig0 <= trig(0);
led_trig1 <= trig(1);
led_bkpt <= brkpt_active;
nrst_avr <= not sw_reset_avr;
-- OHO DY1 Display for Testing
dy_data(0) <= hex & "0000" & Addr(3 downto 0);
dy_data(1) <= hex & "0000" & Addr(7 downto 4);
dy_data(2) <= hex & "0000" & "00" & sw_reset_avr & sw_reset_cpu;
mux <= addr_inst(7 downto 0) when muxsel = 0 else
addr_inst(15 downto 8) when muxsel = 1 else
din_reg when muxsel = 2 else
instrCount(23 downto 16) when muxsel = 3 else
instrCount(7 downto 0) when muxsel = 4 else
instrCount(15 downto 8) when muxsel = 5 else
fifo_dout(7 downto 0) when muxsel = 6 else
fifo_dout(15 downto 8) when muxsel = 7 else
fifo_dout(23 downto 16) when muxsel = 8 else
fifo_dout(31 downto 24) when muxsel = 9 else
fifo_dout(39 downto 32) when muxsel = 10 else
fifo_dout(47 downto 40) when muxsel = 11 else
fifo_dout(55 downto 48) when muxsel = 12 else
fifo_dout(63 downto 56) when muxsel = 13 else
fifo_dout(71 downto 64) when muxsel = 14 else
Regs(8 * to_integer(unsigned(muxsel(4 downto 0))) + 7 downto 8 * to_integer(unsigned(muxsel(4 downto 0))));
-- Combinatorial set of comparators to decode breakpoint/watch addresses
brkpt_active_process: process (brkpt_reg, brkpt_enable, Addr, Sync, Rd_n, Wr_n, RdIO_n, WrIO_n, trig)
variable i : integer;
variable reg_addr : std_logic_vector(15 downto 0);
variable reg_mask : std_logic_vector(15 downto 0);
variable reg_mode_bmr : std_logic;
variable reg_mode_bmw : std_logic;
variable reg_mode_bir : std_logic;
variable reg_mode_biw : std_logic;
variable reg_mode_bx : std_logic;
variable reg_mode_wmr : std_logic;
variable reg_mode_wmw : std_logic;
variable reg_mode_wir : std_logic;
variable reg_mode_wiw : std_logic;
variable reg_mode_wx : std_logic;
variable reg_mode_all : std_logic_vector(9 downto 0);
variable bactive : std_logic;
variable wactive : std_logic;
variable status : std_logic_vector(3 downto 0);
variable trigval : std_logic;
begin
bactive := '0';
wactive := '0';
status := (others => '0');
if (brkpt_enable = '1') then
for i in 0 to num_comparators - 1 loop
reg_addr := brkpt_reg(i * reg_width + 15 downto i * reg_width);
reg_mask := brkpt_reg(i * reg_width + 31 downto i * reg_width + 16);
reg_mode_bmr := brkpt_reg(i * reg_width + 32);
reg_mode_wmr := brkpt_reg(i * reg_width + 33);
reg_mode_bmw := brkpt_reg(i * reg_width + 34);
reg_mode_wmw := brkpt_reg(i * reg_width + 35);
reg_mode_bir := brkpt_reg(i * reg_width + 36);
reg_mode_wir := brkpt_reg(i * reg_width + 37);
reg_mode_biw := brkpt_reg(i * reg_width + 38);
reg_mode_wiw := brkpt_reg(i * reg_width + 39);
reg_mode_bx := brkpt_reg(i * reg_width + 40);
reg_mode_wx := brkpt_reg(i * reg_width + 41);
reg_mode_all := brkpt_reg(i * reg_width + 41 downto i * reg_width + 32);
trigval := brkpt_reg(i * reg_width + 42 + to_integer(unsigned(trig)));
if (trigval = '1' and ((Addr and reg_mask) = reg_addr or (reg_mode_all = "0000000000"))) then
if (Sync = '1') then
if (reg_mode_bx = '1') then
bactive := '1';
status := "1000";
elsif (reg_mode_wx = '1') then
wactive := '1';
status := "1001";
end if;
elsif (Rd_n = '0') then
if (reg_mode_bmr = '1') then
bactive := '1';
status := "0000";
elsif (reg_mode_wmr = '1') then
wactive := '1';
status := "0001";
end if;
elsif (Wr_n = '0') then
if (reg_mode_bmw = '1') then
bactive := '1';
status := "0010";
elsif (reg_mode_wmw = '1') then
wactive := '1';
status := "0011";
end if;
elsif (RdIO_n = '0') then
if (reg_mode_bir = '1') then
bactive := '1';
status := "0100";
elsif (reg_mode_wir = '1') then
wactive := '1';
status := "0101";
end if;
elsif (WrIO_n = '0') then
if (reg_mode_biw = '1') then
bactive := '1';
status := "0110";
elsif (reg_mode_wiw = '1') then
wactive := '1';
status := "0111";
end if;
end if;
end if;
end loop;
end if;
watch_active <= wactive;
brkpt_active <= bactive;
bw_status <= status;
end process;
-- CPU Control Commands
-- 00000x Enable/Disable single stepping
-- 00001x Enable/Disable breakpoints / watches
-- 00010x Load breakpoint / watch register
-- 00011x Reset CPU
-- 001000 Singe Step CPU
-- 001001 Read FIFO
-- 001010 Reset FIFO
-- 001011 Unused
-- 00110x Load address/data register
-- 00111x Unused
-- 010000 Read Memory
-- 010001 Read Memory and Auto Inc Address
-- 010010 Write Memory
-- 010011 Write Memory and Auto Inc Address
-- 010100 Read IO
-- 010101 Read IO and Auto Inc Address
-- 010110 Write IO
-- 010111 Write IO and Auto Inc Address
-- 011000 Execute 6502 instruction
-- 0111xx Unused
-- 011x1x Unused
-- 011xx1 Unused
-- 100xxx Special
-- 1010xx Timer Mode
-- 00 - count cpu cycles where clken = 1 and CountCycle = 1
-- 01 - count cpu cycles where clken = 1 (ignoring CountCycle)
-- 10 - free running timer, using busmon_clk as the source
-- 11 - free running timer, using trig0 as the source
-- Use trig0 to drive a free running counter for absolute timings
ext_clk <= trig(0);
timer1Process: process (ext_clk)
begin
if rising_edge(ext_clk) then
timer1Count <= timer1Count + 1;
end if;
end process;
cpuProcess: process (busmon_clk)
begin
if rising_edge(busmon_clk) then
timer0Count <= timer0Count + 1;
if busmon_clken = '1' then
-- Cycle counter
if (cpu_reset_n = '0') then
cycleCount <= (others => '0');
elsif (CountCycle = '1' or timer_mode(0) = '1') then
cycleCount <= cycleCount + 1;
end if;
-- Command processing
cmd_edge1 <= cmd_edge;
cmd_edge2 <= cmd_edge1;
fifo_rd <= '0';
fifo_wr <= '0';
fifo_rst <= '0';
memory_rd <= '0';
memory_wr <= '0';
io_rd <= '0';
io_wr <= '0';
exec <= '0';
SS_Step <= '0';
if (cmd_edge2 /= cmd_edge1) then
if (cmd(5 downto 1) = "00000") then
single <= cmd(0);
end if;
if (cmd(5 downto 1) = "00001") then
brkpt_enable <= cmd(0);
end if;
if (cmd(5 downto 1) = "00010") then
brkpt_reg <= cmd(0) & brkpt_reg(brkpt_reg'length - 1 downto 1);
end if;
if (cmd(5 downto 1) = "00110") then
addr_dout_reg <= cmd(0) & addr_dout_reg(addr_dout_reg'length - 1 downto 1);
end if;
if (cmd(5 downto 1) = "00011") then
reset <= cmd(0);
end if;
if (cmd(5 downto 0) = "01001") then
fifo_rd <= '1';
end if;
if (cmd(5 downto 0) = "01010") then
fifo_rst <= '1';
end if;
if (cmd(5 downto 1) = "01000") then
memory_rd <= '1';
auto_inc <= cmd(0);
end if;
if (cmd(5 downto 1) = "01001") then
memory_wr <= '1';
auto_inc <= cmd(0);
end if;
if (cmd(5 downto 1) = "01010") then
io_rd <= '1';
auto_inc <= cmd(0);
end if;
if (cmd(5 downto 1) = "01011") then
io_wr <= '1';
auto_inc <= cmd(0);
end if;
if (cmd(5 downto 0) = "011000") then
exec <= '1';
end if;
if (cmd(5 downto 3) = "100") then
Special <= cmd(2 downto 0);
end if;
if (cmd(5 downto 2) = "1010") then
timer_mode <= cmd(1 downto 0);
end if;
-- Acknowlege certain commands immediately
if cmd(5 downto 4) /= "01" then
cmd_ack <= not cmd_ack;
end if;
end if;
if cmd_done = '1' then
-- Acknowlege memory access commands when thet complete
cmd_ack <= not cmd_ack;
-- Auto increment the memory address reg the cycle after a rd/wr
if auto_inc = '1' then
addr_dout_reg(23 downto 8) <= addr_dout_reg(23 downto 8) + 1;
end if;
end if;
-- Single Stepping
if (brkpt_active = '1') then
single <= '1';
end if;
if ((single = '0') or (cmd_edge2 /= cmd_edge1 and cmd = "001000")) then
Rdy_int <= (not brkpt_active);
SS_Step <= (not brkpt_active);
else
Rdy_int <= (not Sync);
end if;
-- Latch instruction address for the whole cycle
if (Sync = '1') then
addr_inst <= Addr;
if timer_mode = "10" then
instrCount <= timer0Count;
elsif timer_mode = "11" then
instrCount <= timer1Count;
else
instrCount <= cycleCount;
end if;
end if;
-- Breakpoints and Watches written to the FIFO
brkpt_active1 <= brkpt_active;
bw_status1 <= bw_status;
if watch_active = '1' or (brkpt_active = '1' and brkpt_active1 = '0') then
fifo_wr <= '1';
Addr1 <= Addr;
end if;
end if;
end if;
end process;
dataProcess: process (cpu_clk)
begin
if rising_edge(cpu_clk) then
if cpu_clken = '1' then
-- Latch the data bus for use in watches
Data1 <= Data;
-- Latch memory read in response to a read command
if (Done = '1') then
din_reg <= DataIn;
end if;
-- Delay the increnting of the address by one cycle
last_done <= Done;
if Done = '1' and last_done = '0' then
cmd_done <= '1';
else
cmd_done <= '0';
end if;
end if;
end if;
end process;
Rdy <= Rdy_int;
RdMemOut <= memory_rd;
WrMemOut <= memory_wr;
RdIOOut <= io_rd;
WrIOOut <= io_wr;
AddrOut <= addr_dout_reg(23 downto 8);
DataOut <= addr_dout_reg(7 downto 0);
SS_Single <= single;
ExecOut <= exec;
-- Reset Logic
-- Generate a short (~1ms @ 1MHz) power up reset pulse
--
-- This is in case FPGA configuration takes longer than
-- the length of the host system reset pulse.
--
-- Some 6502 cores (particularly the AlanD core) needs
-- reset to be asserted to start.
-- Debounce nRSTin using clock_avr as this is always 16MHz
-- nrst1 is the possibly glitchy input
-- nrst2 is the filtered output
process(clock_avr)
begin
if rising_edge(clock_avr) then
-- Syncronise nRSTin
nrst1 <= nRSTin and (not sw_reset_cpu);
-- De-glitch NRST
if nrst1 = '0' then
nrst_counter <= to_unsigned(0, nrst_counter'length);
nrst2 <= '0';
elsif nrst_counter(nrst_counter'high) = '0' then
nrst_counter <= nrst_counter + 1;
else
nrst2 <= '1';
end if;
end if;
end process;
process(cpu_clk)
begin
if rising_edge(cpu_clk) then
if cpu_clken = '1' then
if reset_counter(reset_counter'high) = '0' then
reset_counter <= reset_counter + 1;
end if;
nrst3 <= nrst2 and reset_counter(reset_counter'high) and (not reset);
cpu_reset_n <= nrst3;
end if;
end if;
end process;
nRSTout <= cpu_reset_n;
end behavioral;
| gpl-3.0 | 2ae4a65063662a6bfe235a3f89c6c7c4 | 0.448952 | 4.098318 | false | false | false | false |
DreamIP/GPStudio | support/process/detectroi/hdl/detectroi_slave.vhd | 1 | 3,615 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity detectroi_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
in_size_reg_in_w_reg : out std_logic_vector(11 downto 0);
in_size_reg_in_h_reg : out std_logic_vector(11 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end detectroi_slave;
architecture rtl of detectroi_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant IN_SIZE_REG_REG_ADDR : natural := 1;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal in_size_reg_in_w_reg_reg : std_logic_vector (11 downto 0);
signal in_size_reg_in_h_reg_reg : std_logic_vector (11 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
in_size_reg_in_w_reg_reg <= "000000000000";
in_size_reg_in_h_reg_reg <= "000000000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case to_integer(unsigned(addr_rel_i)) is
when STATUS_REG_REG_ADDR =>
status_reg_enable_bit_reg <= datawr_i(0);
when IN_SIZE_REG_REG_ADDR =>
in_size_reg_in_w_reg_reg <= datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
in_size_reg_in_h_reg_reg <= datawr_i(27) & datawr_i(26) & datawr_i(25) & datawr_i(24) & datawr_i(23) & datawr_i(22) & datawr_i(21) & datawr_i(20) & datawr_i(19) & datawr_i(18) & datawr_i(17) & datawr_i(16);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case to_integer(unsigned(addr_rel_i)) is
when STATUS_REG_REG_ADDR =>
datard_o <= "0000000000000000000000000000000" & status_reg_enable_bit_reg;
when IN_SIZE_REG_REG_ADDR =>
datard_o <= "0000" & in_size_reg_in_h_reg_reg(11) & in_size_reg_in_h_reg_reg(10) & in_size_reg_in_h_reg_reg(9) & in_size_reg_in_h_reg_reg(8) & in_size_reg_in_h_reg_reg(7) & in_size_reg_in_h_reg_reg(6) & in_size_reg_in_h_reg_reg(5) & in_size_reg_in_h_reg_reg(4) & in_size_reg_in_h_reg_reg(3) & in_size_reg_in_h_reg_reg(2) & in_size_reg_in_h_reg_reg(1) & in_size_reg_in_h_reg_reg(0) & "0000" & in_size_reg_in_w_reg_reg(11) & in_size_reg_in_w_reg_reg(10) & in_size_reg_in_w_reg_reg(9) & in_size_reg_in_w_reg_reg(8) & in_size_reg_in_w_reg_reg(7) & in_size_reg_in_w_reg_reg(6) & in_size_reg_in_w_reg_reg(5) & in_size_reg_in_w_reg_reg(4) & in_size_reg_in_w_reg_reg(3) & in_size_reg_in_w_reg_reg(2) & in_size_reg_in_w_reg_reg(1) & in_size_reg_in_w_reg_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
in_size_reg_in_w_reg <= in_size_reg_in_w_reg_reg;
in_size_reg_in_h_reg <= in_size_reg_in_h_reg_reg;
end rtl;
| gpl-3.0 | f90f59b147c60910eb2fdf442dc1e201 | 0.580913 | 2.50173 | false | false | false | false |
DreamIP/GPStudio | support/toolchain/caph/hdl/caph_toplevel/src/fifo_route_matrix.vhd | 1 | 9,109 | -- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo
-- ============================================================
-- File Name: fifo_route_matrix.vhd
-- Megafunction Name(s):
-- dcfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.math_real.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY fifo_route_matrix IS
GENERIC
(
DEPTH : POSITIVE;
DATA_SIZE : POSITIVE
);
PORT
(
aclr : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR (DATA_SIZE-1 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (DATA_SIZE-1 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (integer(ceil(log2(real(DEPTH))))-1 DOWNTO 0);
wrfull : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (integer(ceil(log2(real(DEPTH))))-1 DOWNTO 0)
);
END fifo_route_matrix;
ARCHITECTURE SYN OF fifo_route_matrix IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (DATA_SIZE-1 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (integer(ceil(log2(real(DEPTH))))-1 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (integer(ceil(log2(real(DEPTH))))-1 DOWNTO 0);
COMPONENT dcfifo
GENERIC (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
rdclk : IN STD_LOGIC ;
wrfull : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (DATA_SIZE-1 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (integer(ceil(log2(real(DEPTH))))-1 DOWNTO 0);
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (DATA_SIZE-1 DOWNTO 0);
rdreq : IN STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (integer(ceil(log2(real(DEPTH))))-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
wrfull <= sub_wire0;
q <= sub_wire1(DATA_SIZE-1 DOWNTO 0);
rdempty <= sub_wire2;
wrusedw <= sub_wire3(integer(ceil(log2(real(DEPTH))))-1 DOWNTO 0);
rdusedw <= sub_wire4(integer(ceil(log2(real(DEPTH))))-1 DOWNTO 0);
dcfifo_component : dcfifo
GENERIC MAP (
intended_device_family => "Cyclone III",
lpm_numwords => DEPTH,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => DATA_SIZE,
lpm_widthu => integer(ceil(log2(real(DEPTH)))),
overflow_checking => "ON",
rdsync_delaypipe => 2,
read_aclr_synch => "OFF",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 2
)
PORT MAP (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data,
rdreq => rdreq,
wrfull => sub_wire0,
q => sub_wire1,
rdempty => sub_wire2,
wrusedw => sub_wire3,
rdusedw => sub_wire4
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "32768"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "0"
-- Retrieval info: PRIVATE: Width NUMERIC "16"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "16"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32768"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "15"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
-- Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: rdusedw 0 0 15 0 OUTPUT NODEFVAL "rdusedw[14..0]"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: USED_PORT: wrusedw 0 0 15 0 OUTPUT NODEFVAL "wrusedw[14..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-- Retrieval info: CONNECT: rdusedw 0 0 15 0 @rdusedw 0 0 15 0
-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-- Retrieval info: CONNECT: wrusedw 0 0 15 0 @wrusedw 0 0 15 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_com.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_com.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_com.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_com.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_com_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_com_tx.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_com_tx.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_com_tx.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_com_tx.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_com_tx_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | 3a5a0ebe367f76d46e1ee7309e6749d1 | 0.656933 | 3.384987 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/mmSlaveConv-rtl-ea.vhd | 3 | 13,931 | -------------------------------------------------------------------------------
--! @file mmSlaveConv-rtl-ea.vhd
--
--! @brief Memory mapped slave interface converter
--
--! @details The slave interface converter is fixed to a 16 bit memory mapped
--! slave, connected to a 32 bit master. The conversion also considers
--! little/big endian (gEndian).
--! Note: Tested with openmacTop entity only!
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity mmSlaveConv is
generic (
--! Endianness of interconnect
gEndian : string := "little";
--! Memory mapped master address width
gMasterAddrWidth : natural := 10
);
port (
--! Reset
iRst : in std_logic;
--! Clock
iClk : in std_logic;
-- Memory mapped master input
--! Master select
iMaster_select : in std_logic;
--! Master write
iMaster_write : in std_logic;
--! Master read
iMaster_read : in std_logic;
--! Master byteenable
iMaster_byteenable : in std_logic_vector(3 downto 0);
--! Master writedata
iMaster_writedata : in std_logic_vector(31 downto 0);
--! Master readdata
oMaster_readdata : out std_logic_vector(31 downto 0);
--! Master address (byte address)
iMaster_address : in std_logic_vector(gMasterAddrWidth-1 downto 0);
--! Master write acknowledge
oMaster_WriteAck : out std_logic;
--! Master read acknowledge
oMaster_ReadAck : out std_logic;
-- Memory mapped slave output
--! Slave select
oSlave_select : out std_logic;
--! Slave write
oSlave_write : out std_logic;
--! Slave read
oSlave_read : out std_logic;
--! Slave address (word address)
oSlave_address : out std_logic_vector(gMasterAddrWidth-1 downto 0);
--! Slave byteenable
oSlave_byteenable : out std_logic_vector(1 downto 0);
--! Slave readdata
iSlave_readdata : in std_logic_vector(15 downto 0);
--! Slave writedata
oSlave_writedata : out std_logic_vector(15 downto 0);
--! Slave acknowledge
iSlave_ack : in std_logic
);
end mmSlaveConv;
architecture rtl of mmSlaveConv is
--! Access fsm_reg type
type tAccessFsm is (
sIdle,
sDoAccess
);
--! Access type
type tAccess is (
sNone,
sDword,
sWord
);
--! Access fsm_reg current state
signal fsm_reg : tAccessFsm;
--! Access fsm_reg next state
signal fsm_next : tAccessFsm;
--! Current master access type
signal masterAccess : tAccess;
--! Counter width
constant cCounterWidth : natural := 2;
--! Counter register
signal counter_reg : std_logic_vector(cCounterWidth-1 downto 0);
--! Next counter register
signal counter_next : std_logic_vector(cCounterWidth-1 downto 0);
--! Counter register load value
signal counter_loadValue : std_logic_vector(cCounterWidth-1 downto 0);
--! Load counter register with counter_loadValue
signal counter_load : std_logic;
--! Decrement counter value by one
signal counter_decrement : std_logic;
--! counter_reg is zero
signal counter_isZero : std_logic;
--! counter_reg is one
signal counter_isOne : std_logic;
--! counter_reg is two
signal counter_isTwo : std_logic;
--! Master acknowledge
signal masterAck : std_logic;
--! Register to store slave readdata word
signal wordStore_reg : std_logic_vector(iSlave_readdata'range);
--! Next value of slave readdata word register
signal wordStore_next : std_logic_vector(wordStore_reg'range);
begin
---------------------------------------------------------------------------
-- Assign outputs
---------------------------------------------------------------------------
oSlave_select <= iMaster_select;
oSlave_write <= iMaster_write and iMaster_select;
oSlave_read <= iMaster_read and iMaster_select;
oMaster_WriteAck <= masterAck and iMaster_write and iMaster_select;
oMaster_ReadAck <= masterAck and iMaster_read and iMaster_select;
--! This process assigns the master readdata port controlled by the current
--! conversion state.
assignMasterPath : process (
iSlave_readdata, wordStore_reg,
masterAccess
)
begin
if masterAccess = sDword then
oMaster_readdata <= iSlave_readdata & wordStore_reg;
else
oMaster_readdata <= iSlave_readdata & iSlave_readdata;
end if;
end process assignMasterPath;
--! This process assigns the slave address, byteenable and writedata controlled
--! by the current conversion state.
assignSlavePath : process (
iMaster_address, iMaster_byteenable, iMaster_writedata,
counter_reg, counter_isOne,
masterAccess
)
begin
-----------------------------------------------------------------------
-- Slave address
-----------------------------------------------------------------------
--default assignment
oSlave_address <= iMaster_address;
if masterAccess = sDword then
case to_integer(unsigned(counter_reg)) is
when 0 | 2 =>
-- First word of dword access
if gEndian = "little" then
oSlave_address(1) <= cInactivated;
else
oSlave_address(1) <= cActivated;
end if;
when 1 =>
-- Second word of dword access
if gEndian = "little" then
oSlave_address(1) <= cActivated;
else
oSlave_address(1) <= cInactivated;
end if;
when others =>
null; --allowed due to default assignment
end case;
end if;
-----------------------------------------------------------------------
-- Slave byteenable
-----------------------------------------------------------------------
if masterAccess = sDword then
oSlave_byteenable <= (others => cActivated);
else
oSlave_byteenable <= iMaster_byteenable(3 downto 2) or iMaster_byteenable(1 downto 0);
end if;
-----------------------------------------------------------------------
-- Slave writedata
-----------------------------------------------------------------------
if (masterAccess = sDword and counter_isOne = cActivated) or iMaster_address(1) = cActivated then
oSlave_writedata <= iMaster_writedata(31 downto 16);
else
oSlave_writedata <= iMaster_writedata(15 downto 0);
end if;
end process assignSlavePath;
--! This process assigns the registers.
regProc : process(iRst, iClk)
begin
if iRst = cActivated then
counter_reg <= (others => cInactivated);
fsm_reg <= sIdle;
wordStore_reg <= (others => cInactivated);
elsif rising_edge(iClk) then
counter_reg <= counter_next;
fsm_reg <= fsm_next;
wordStore_reg <= wordStore_next;
end if;
end process;
--! This process assigns the register next signals.
assignRegNext : process (
iSlave_readdata, iSlave_ack,
wordStore_reg, fsm_reg, counter_reg,
counter_load, counter_loadValue, counter_decrement, counter_isZero,
counter_isTwo, masterAccess
)
begin
-- default assignments
wordStore_next <= wordStore_reg;
fsm_next <= fsm_reg;
counter_next <= counter_reg;
-----------------------------------------------------------------------
-- Counter
-----------------------------------------------------------------------
if counter_load = cActivated then
counter_next <= counter_loadValue;
elsif counter_decrement = cActivated and masterAccess = sDword then
counter_next <= std_logic_vector(unsigned(counter_reg) - 1);
end if;
-----------------------------------------------------------------------
-- Access FSM
-----------------------------------------------------------------------
if counter_isZero = cActivated then
case fsm_reg is
when sIdle =>
if masterAccess = sDword then
fsm_next <= sDoAccess;
end if;
when sDoAccess =>
if masterAccess = sNone then
fsm_next <= sIdle;
end if;
end case;
end if;
-----------------------------------------------------------------------
-- Store slave readdata word
-----------------------------------------------------------------------
if iSlave_ack = cActivated and masterAccess = sDword and counter_isTwo = cActivated then
wordStore_next <= iSlave_readdata;
end if;
end process assignRegNext;
counter_decrement <= iSlave_ack and iMaster_select;
--! This process assigns internal control signals.
assignInternal : process (
iSlave_ack,
iMaster_select, iMaster_byteenable, iMaster_read,
counter_reg, counter_isOne, masterAccess, fsm_reg, fsm_next
)
begin
-----------------------------------------------------------------------
-- Master acknowledge
-----------------------------------------------------------------------
if iSlave_ack = cActivated and masterAccess = sDword and counter_isOne = cActivated then
masterAck <= cActivated;
elsif iSlave_ack = cActivated and masterAccess = sWord then
masterAck <= cActivated;
else
masterAck <= cInactivated;
end if;
-----------------------------------------------------------------------
-- Master access state
-----------------------------------------------------------------------
if iMaster_select = cInactivated then
masterAccess <= sNone;
elsif iMaster_byteenable = "1111" then
masterAccess <= sDword;
else
masterAccess <= sWord;
end if;
-----------------------------------------------------------------------
-- Counter
-----------------------------------------------------------------------
--default
counter_isZero <= cInactivated;
counter_isOne <= cInactivated;
counter_isTwo <= cInactivated;
-- assign counter_is* signals
case to_integer(unsigned(counter_reg)) is
when 0 =>
counter_isZero <= cActivated;
when 1 =>
counter_isOne <= cActivated;
when 2 =>
counter_isTwo <= cActivated;
when others =>
null; --is allowed due to default assignment
end case;
-- assign counter load
if fsm_next = sDoAccess and fsm_reg = sIdle then
counter_load <= cActivated;
else
counter_load <= cInactivated;
end if;
-- assign counter load value
if iMaster_byteenable = "1111" and iMaster_read = cActivated then
counter_loadValue <= "10";
else
counter_loadValue <= "01";
end if;
end process assignInternal;
end rtl;
| gpl-2.0 | 54bc089443fcd5812ac5e7e5df0abaa5 | 0.51109 | 5.374614 | false | false | false | false |
DreamIP/GPStudio | support/process/draw/hdl/draw.vhd | 1 | 4,265 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity draw is
generic (
CLK_PROC_FREQ : integer;
IMG_SIZE : integer;
COORD_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------ Img flow -----------------------
Img_data : in std_logic_vector(IMG_SIZE-1 downto 0);
Img_fv : in std_logic;
Img_dv : in std_logic;
----------------------- coord flow ----------------------
coord_data : out std_logic_vector(COORD_SIZE-1 downto 0);
coord_fv : out std_logic;
coord_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end draw;
architecture rtl of draw is
component draw_process
generic (
CLK_PROC_FREQ : integer;
IMG_SIZE : integer;
COORD_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
inImg_size_reg_in_w_reg : in std_logic_vector(11 downto 0);
inImg_size_reg_in_h_reg : in std_logic_vector(11 downto 0);
------------------------ Img flow -----------------------
Img_data : in std_logic_vector(IMG_SIZE-1 downto 0);
Img_fv : in std_logic;
Img_dv : in std_logic;
----------------------- coord flow ----------------------
coord_data : out std_logic_vector(COORD_SIZE-1 downto 0);
coord_fv : out std_logic;
coord_dv : out std_logic
);
end component;
component draw_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
inImg_size_reg_in_w_reg : out std_logic_vector(11 downto 0);
inImg_size_reg_in_h_reg : out std_logic_vector(11 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal inImg_size_reg_in_w_reg : std_logic_vector (11 downto 0);
signal inImg_size_reg_in_h_reg : std_logic_vector (11 downto 0);
begin
draw_process_inst : draw_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
IMG_SIZE => IMG_SIZE,
COORD_SIZE => COORD_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
inImg_size_reg_in_w_reg => inImg_size_reg_in_w_reg,
inImg_size_reg_in_h_reg => inImg_size_reg_in_h_reg,
Img_data => Img_data,
Img_fv => Img_fv,
Img_dv => Img_dv,
coord_data => coord_data,
coord_fv => coord_fv,
coord_dv => coord_dv
);
draw_slave_inst : draw_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
inImg_size_reg_in_w_reg => inImg_size_reg_in_w_reg,
inImg_size_reg_in_h_reg => inImg_size_reg_in_h_reg,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
| gpl-3.0 | 2ca0cca1a3741aab7f4bb7875fb89c54 | 0.464478 | 3.303641 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/RGMII_MAC/fifo_tx_udp.vhd | 1 | 6,850 | -- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
-- ============================================================
-- File Name: fifo_tx_udp.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY fifo_tx_udp IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END fifo_tx_udp;
ARCHITECTURE SYN OF fifo_tx_udp IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wrreq : IN STD_LOGIC
);
END COMPONENT;
BEGIN
empty <= sub_wire0;
full <= sub_wire1;
q <= sub_wire2(7 DOWNTO 0);
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
intended_device_family => "Cyclone III",
lpm_numwords => 2048,
lpm_showahead => "OFF",
lpm_type => "scfifo",
lpm_width => 8,
lpm_widthu => 11,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
aclr => aclr,
clock => clock,
data => data,
rdreq => rdreq,
wrreq => wrreq,
empty => sub_wire0,
full => sub_wire1,
q => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "2048"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "0"
-- Retrieval info: PRIVATE: Width NUMERIC "8"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "8"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_tx_udp.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_tx_udp.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_tx_udp.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_tx_udp.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_tx_udp_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | 55c498886971e8944c7f57393b6be3d5 | 0.663066 | 3.512821 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/hostinterface/src/hostInterfaceRtl.vhd | 3 | 20,598 | -------------------------------------------------------------------------------
--! @file hostInterface.vhd
--
--! @brief toplevel of host interface
--
--! @details The toplevel instantiates the necessary components for the
--! host interface like the Dynamic Bridge and the Status-/Control Registers.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2017
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use host interface package for specific types
use work.hostInterfacePkg.all;
entity hostInterface is
generic (
--! Version major
gVersionMajor : natural := 16#FF#;
--! Version minor
gVersionMinor : natural := 16#FF#;
--! Version revision
gVersionRevision : natural := 16#FF#;
--! Version count
gVersionCount : natural := 0;
--! Use memory blocks or registers for translation address storage (registers = 0, memory blocks /= 0)
gBridgeUseMemBlock : natural := 0;
-- Base address mapping
--! Base address Dynamic Buffer 0
gBaseDynBuf0 : natural := 16#00800#;
--! Base address Dynamic Buffer 1
gBaseDynBuf1 : natural := 16#01000#;
--! Base address Error Counter
gBaseErrCntr : natural := 16#01800#;
--! Base address TX NMT Queue
gBaseTxNmtQ : natural := 16#02800#;
--! Base address TX Generic Queue
gBaseTxGenQ : natural := 16#03800#;
--! Base address TX SyncRequest Queue
gBaseTxSynQ : natural := 16#04800#;
--! Base address TX Virtual Ethernet Queue
gBaseTxVetQ : natural := 16#05800#;
--! Base address RX Virtual Ethernet Queue
gBaseRxVetQ : natural := 16#06800#;
--! Base address Kernel-to-User Queue
gBaseK2UQ : natural := 16#07000#;
--! Base address User-to-Kernel Queue
gBaseU2KQ : natural := 16#09000#;
--! Base address Pdo
gBasePdo : natural := 16#0B000#;
--! Base address Timesync
gBaseTimeSync : natural := 16#0E000#;
--! Base address Reserved (-1 = high address of Timesync)
gBaseRes : natural := 16#0E400#;
--! Host address width
gHostAddrWidth : natural := 16
);
port (
--! Clock Source input
iClk : in std_logic;
--! Reset Source input
iRst : in std_logic;
-- Memory Mapped Slave for Host
--! MM slave host address
iHostAddress : in std_logic_vector(gHostAddrWidth-1 downto 2);
--! MM slave host byteenable
iHostByteenable : in std_logic_vector(3 downto 0);
--! MM slave host read
iHostRead : in std_logic;
--! MM slave host readdata
oHostReaddata : out std_logic_vector(31 downto 0);
--! MM slave host write
iHostWrite : in std_logic;
--! MM slave host writedata
iHostWritedata : in std_logic_vector(31 downto 0);
--! MM slave host waitrequest
oHostWaitrequest : out std_logic;
-- Memory Mapped Slave for PCP
--! MM slave pcp address
iPcpAddress : in std_logic_vector(10 downto 2);
--! MM slave pcp byteenable
iPcpByteenable : in std_logic_vector(3 downto 0);
--! MM slave pcp read
iPcpRead : in std_logic;
--! MM slave pcp readdata
oPcpReaddata : out std_logic_vector(31 downto 0);
--! MM slave pcp write
iPcpWrite : in std_logic;
--! MM slave pcp writedata
iPcpWritedata : in std_logic_vector(31 downto 0);
--! MM slave pcp waitrequest
oPcpWaitrequest : out std_logic;
-- Memory Mapped Master for Host via Dynamic Bridge
--! MM master hostBridge address
oHostBridgeAddress : out std_logic_vector(29 downto 0);
--! MM master hostBridge byteenable
oHostBridgeByteenable : out std_logic_vector(3 downto 0);
--! MM master hostBridge read
oHostBridgeRead : out std_logic;
--! MM master hostBridge readdata
iHostBridgeReaddata : in std_logic_vector(31 downto 0);
--! MM master hostBridge write
oHostBridgeWrite : out std_logic;
--! MM master hostBridge writedata
oHostBridgeWritedata : out std_logic_vector(31 downto 0);
--! MM master hostBridge waitrequest
iHostBridgeWaitrequest : in std_logic;
--! Interrupt internal sync signal (from openMAC)
iIrqIntSync : in std_logic;
--! External sync source
iIrqExtSync : in std_logic;
--! Interrupt output signal
oIrq : out std_logic
);
end hostInterface;
architecture Rtl of hostInterface is
--! Magic
constant cMagic : natural := 16#504C4B00#;
--! Base address array
constant cBaseAddressArray : tArrayStd32 := (
std_logic_vector(to_unsigned(gBaseDynBuf0, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseDynBuf1, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseErrCntr, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTxNmtQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTxGenQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTxSynQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTxVetQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseRxVetQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseK2UQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseU2KQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBasePdo, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTimeSync, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseRes, cArrayStd32ElementSize))
);
--! Base address array count
constant cBaseAddressArrayCount : natural := cBaseAddressArray'length;
--! Base address set by host
constant cBaseAddressHostCount : natural := 2;
--! Base address set by pcp
constant cBaseAddressPcpCount : natural := cBaseAddressArrayCount-cBaseAddressHostCount;
--! Number of interrupt sources (sync not included)
constant cIrqSourceCount : natural := 3;
--! Bridge fsm type
type tFsm is (
sIdle,
sReqAddr,
sAccess,
sDone
);
--! select the bridge logic
signal bridgeSel : std_logic;
--! invalid address range selected
signal invalidSel : std_logic;
--! select status control registers
signal statCtrlSel : std_logic;
--! write status control register
signal statCtrlWrite : std_logic;
--! read status control register
signal statCtrlRead : std_logic;
--! waitrequest from status/control
signal statCtrlWaitrequest : std_logic;
--! readdata from status/control
signal statCtrlReaddata : std_logic_vector(oHostReaddata'range);
--! Bridge request signal
signal bridgeRequest : std_logic;
--! Bridge enable control
signal bridgeEnable : std_logic;
--! Bridge address is valid
signal bridgeAddrValid : std_logic;
--! The magic bridge outputs the dword address
signal hostBridgeAddress_dword : std_logic_vector(oHostBridgeAddress'length-1 downto 2);
--! Bridge transfer done strobe
signal bridgeTfDone : std_logic;
--! Bridge read data
signal bridgeReaddata : std_logic_vector(iHostBridgeReaddata'range);
--! Bridge state machine
signal fsm : tFsm;
--! Bridge state machine, next state
signal fsm_next : tFsm;
-- base set signals
--! BaseSet Write
signal baseSetWrite : std_logic;
--! BaseSet Read
signal baseSetRead : std_logic;
--! BaseSet byteenable
signal baseSetByteenable : std_logic_vector(3 downto 0);
--! BaseSet Writedata
signal baseSetWritedata : std_logic_vector(hostBridgeAddress_dword'range);
--! BaseSet Readdata
signal baseSetReaddata : std_logic_vector(hostBridgeAddress_dword'range);
--! BaseSet Address
signal baseSetAddress : std_logic_vector(logDualis(cBaseAddressArrayCount)-1 downto 0);
--! BaseSet acknowledge
signal baseSetAck : std_logic;
-- interrupt signals
--! Irq master enable
signal irqMasterEnable : std_logic;
--! Irq source enable
signal irqSourceEnable : std_logic_vector(cIrqSourceCount downto 0);
--! Irq acknowledge
signal irqAcknowledge : std_logic_vector(cIrqSourceCount downto 0);
--! Irq source pending
signal irqSourcePending : std_logic_vector(cIrqSourceCount downto 0);
--! Irq source set (no sync!)
signal irqSourceSet : std_logic_vector(cIrqSourceCount downto 1);
--! sync signal
signal syncSig : std_logic;
--! synchronized ext sync
signal extSync_sync : std_logic;
--! external sync signal
signal extSyncEnable : std_logic;
--! external sync config
signal extSyncConfig : std_logic_vector(cExtSyncEdgeConfigWidth-1 downto 0);
--! external sync signal detected rising edge
signal extSync_rising : std_logic;
--! external sync signal detected falling edge
signal extSync_falling : std_logic;
--! external sync signal detected any edge
signal extSync_any : std_logic;
begin
assert (2**gHostAddrWidth-1 >= gBaseRes-1)
report "The host side high address cannot be addressed! Increase gHostAddrWidth generic!"
severity failure;
-- select status/control registers if host address is below 2 kB
statCtrlSel <= cActivated when iHostAddress < cBaseAddressArray(0)(iHostAddress'range) else
cInactivated;
-- select invalid address
invalidSel <= cActivated when iHostAddress >= cBaseAddressArray(cBaseAddressArrayCount-1)(iHostAddress'range) else
cInactivated;
-- bridge is selected if status/control registers are not accessed
bridgeSel <= cInactivated when bridgeEnable = cInactivated else
cInactivated when invalidSel = cActivated else
cInactivated when statCtrlSel = cActivated else
cActivated;
-- create write and read strobe for status/control registers
statCtrlWrite <= iHostWrite and statCtrlSel;
statCtrlRead <= iHostRead and statCtrlSel;
-- host waitrequest from status/control, bridge or invalid
oHostWaitrequest <= statCtrlWaitrequest when statCtrlSel = cActivated else
not (iHostWrite or iHostRead) when invalidSel = cActivated else
cInactivated when bridgeEnable = cInactivated else
not bridgeTfDone when bridgeSel = cActivated else
cActivated;
-- host readdata from status/control or bridge
oHostReaddata <= bridgeReaddata when bridgeSel = cActivated else
statCtrlReaddata when statCtrlSel = cActivated else
(others => cInactivated);
-- select external sync if enabled, otherwise rx irq signal
syncSig <= iIrqIntSync when extSyncEnable /= cActivated else
extSync_rising when extSyncConfig = cExtSyncEdgeRis else
extSync_falling when extSyncConfig = cExtSyncEdgeFal else
extSync_any when extSyncConfig = cExtSyncEdgeAny else
cInactivated;
--! The bridge state machine handles the address translation of
--! dynamicBridge and finalizes the access to the host bridge master.
theFsmCom : process (
fsm,
bridgeSel,
bridgeAddrValid,
iHostRead,
iHostWrite,
iHostBridgeWaitrequest
)
begin
--default
fsm_next <= fsm;
case fsm is
when sIdle =>
if ( (iHostRead = cActivated or iHostWrite = cActivated) and
bridgeSel = cActivated) then
fsm_next <= sReqAddr;
end if;
when sReqAddr =>
if bridgeAddrValid = cActivated then
fsm_next <= sAccess;
end if;
when sAccess =>
if iHostBridgeWaitrequest = cInactivated then
fsm_next <= sDone;
end if;
when sDone =>
fsm_next <= sIdle;
end case;
end process;
bridgeRequest <= cActivated when fsm = sReqAddr else cInactivated;
bridgeTfDone <= cActivated when fsm = sDone else cInactivated;
--! Clock process to assign registers.
theClkPro : process(iRst, iClk)
begin
if iRst = cActivated then
fsm <= sIdle;
oHostBridgeAddress <= (others => cInactivated);
oHostBridgeByteenable <= (others => cInactivated);
oHostBridgeRead <= cInactivated;
oHostBridgeWrite <= cInactivated;
oHostBridgeWritedata <= (others => cInactivated);
elsif rising_edge(iClk) then
fsm <= fsm_next;
if iHostBridgeWaitrequest = cInactivated then
oHostBridgeRead <= cInactivated;
oHostBridgeWrite <= cInactivated;
bridgeReaddata <= iHostBridgeReaddata;
end if;
if bridgeAddrValid = cActivated then
oHostBridgeAddress <= hostBridgeAddress_dword & "00";
oHostBridgeByteenable <= iHostByteenable;
oHostBridgeRead <= iHostRead;
oHostBridgeWrite <= iHostWrite;
oHostBridgeWritedata <= iHostWritedata;
end if;
end if;
end process;
--! The synchronizer which protects us from crazy effects!
theSynchronizer : entity libcommon.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iRst,
iClk => iClk,
iAsync => iIrqExtSync,
oSync => extSync_sync
);
--! The Edge Detector for external sync
theExtSyncEdgeDet : entity libcommon.edgedetector
port map (
iArst => iRst,
iClk => iClk,
iEnable => cActivated,
iData => extSync_sync,
oRising => extSync_rising,
oFalling => extSync_falling,
oAny => extSync_any
);
--! The Dynamic Bridge
theDynamicBridge : entity work.dynamicBridge
generic map (
gAddressSpaceCount => cBaseAddressArrayCount-1,
gUseMemBlock => gBridgeUseMemBlock,
gBaseAddressArray => cBaseAddressArray
)
port map (
iClk => iClk,
iRst => iRst,
iBridgeAddress => iHostAddress,
iBridgeRequest => bridgeRequest,
oBridgeAddress => hostBridgeAddress_dword,
oBridgeSelectAny => open,
oBridgeSelect => open,
oBridgeValid => bridgeAddrValid,
iBaseSetWrite => baseSetWrite,
iBaseSetRead => baseSetRead,
iBaseSetByteenable => baseSetByteenable,
iBaseSetAddress => baseSetAddress,
iBaseSetData => baseSetWritedata,
oBaseSetData => baseSetReaddata,
oBaseSetAck => basesetAck
);
--! The Irq Generator
theIrqGen : entity work.irqGen
generic map (
gIrqSourceCount => cIrqSourceCount
)
port map (
iClk => iClk,
iRst => iRst,
iSync => syncSig,
iIrqSource => irqSourceSet,
oIrq => oIrq,
iIrqMasterEnable => irqMasterEnable,
iIrqSourceEnable => irqSourceEnable,
iIrqAcknowledge => irqAcknowledge,
oIrgPending => irqSourcePending
);
--! The Status-/Control Registers
theStCtrlReg : entity work.statusControlReg
generic map (
gMagic => cMagic,
gVersionMajor => gVersionMajor,
gVersionMinor => gVersionMinor,
gVersionRevision => gVersionRevision,
gVersionCount => gVersionCount,
gHostBaseSet => cBaseAddressHostCount,
gPcpBaseSet => cBaseAddressPcpCount,
gIrqSourceCount => cIrqSourceCount
)
port map (
iClk => iClk,
iRst => iRst,
iHostRead => statCtrlRead,
iHostWrite => statCtrlWrite,
iHostByteenable => iHostByteenable,
iHostAddress => iHostAddress(10 downto 2),
oHostReaddata => statCtrlReaddata,
iHostWritedata => iHostWritedata,
oHostWaitrequest => statCtrlWaitrequest,
iPcpRead => iPcpRead,
iPcpWrite => iPcpWrite,
iPcpByteenable => iPcpByteenable,
iPcpAddress => iPcpAddress,
oPcpReaddata => oPcpReaddata,
iPcpWritedata => iPcpWritedata,
oPcpWaitrequest => oPcpWaitrequest,
oBaseSetWrite => baseSetWrite,
oBaseSetRead => baseSetRead,
oBaseSetByteenable => baseSetByteenable,
oBaseSetAddress => baseSetAddress,
iBaseSetData => baseSetReaddata,
oBaseSetData => baseSetWritedata,
iBaseSetAck => basesetAck,
oIrqMasterEnable => irqMasterEnable,
oIrqSourceEnable => irqSourceEnable,
oIrqAcknowledge => irqAcknowledge,
oIrqSet => irqSourceSet,
iIrqPending => irqSourcePending,
oExtSyncEnable => extSyncEnable,
oExtSyncConfig => extSyncConfig,
oBridgeEnable => bridgeEnable
);
end Rtl;
| gpl-2.0 | 376f5aaac31affd7b791d93d68634a27 | 0.589038 | 5.255933 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_Video_Clipper.vhd | 1 | 12,809 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
USE ieee.numeric_std.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module clips video streams on the DE boards. *
-- * *
-- ******************************************************************************
ENTITY Video_System_Video_Clipper IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
GENERIC (
DW :INTEGER := 15; -- Frame's data width
EW :INTEGER := 0; -- Frame's empty width
WIDTH_IN :INTEGER := 720; -- Incoming frame's width in pixels
HEIGHT_IN :INTEGER := 244; -- Incoming frame's height in lines
WW_IN :INTEGER := 9; -- Incoming frame's width's address width
HW_IN :INTEGER := 7; -- Incoming frame's height's address width
DROP_PIXELS_AT_START :INTEGER := 40;
DROP_PIXELS_AT_END :INTEGER := 40;
DROP_LINES_AT_START :INTEGER := 2;
DROP_LINES_AT_END :INTEGER := 2;
WIDTH_OUT :INTEGER := 640; -- Final frame's width in pixels
HEIGHT_OUT :INTEGER := 240; -- Final frame's height in lines
WW_OUT :INTEGER := 9; -- Final frame's width's address width
HW_OUT :INTEGER := 7; -- Final frame's height's address width
ADD_PIXELS_AT_START :INTEGER := 0;
ADD_PIXELS_AT_END :INTEGER := 0;
ADD_LINES_AT_START :INTEGER := 0;
ADD_LINES_AT_END :INTEGER := 0;
ADD_DATA :STD_LOGIC_VECTOR(15 DOWNTO 0) := B"0000000000000000" -- Data value for added pixels
);
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
stream_in_data :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_in_startofpacket :IN STD_LOGIC;
stream_in_endofpacket :IN STD_LOGIC;
stream_in_empty :IN STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_in_valid :IN STD_LOGIC;
stream_out_ready :IN STD_LOGIC;
-- Bidirectional
-- Outputs
stream_in_ready :BUFFER STD_LOGIC;
stream_out_data :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_empty :BUFFER STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_out_valid :BUFFER STD_LOGIC
);
END Video_System_Video_Clipper;
ARCHITECTURE Behaviour OF Video_System_Video_Clipper IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
SIGNAL internal_data :STD_LOGIC_VECTOR(DW DOWNTO 0);
SIGNAL internal_startofpacket :STD_LOGIC;
SIGNAL internal_endofpacket :STD_LOGIC;
SIGNAL internal_empty :STD_LOGIC_VECTOR(EW DOWNTO 0);
SIGNAL internal_valid :STD_LOGIC;
SIGNAL internal_ready :STD_LOGIC;
-- Internal Registers
-- State Machine Registers
-- Integers
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
COMPONENT altera_up_video_clipper_drop
GENERIC (
DW :INTEGER;
EW :INTEGER;
IMAGE_WIDTH :INTEGER;
IMAGE_HEIGHT :INTEGER;
WW :INTEGER;
HW :INTEGER;
DROP_PIXELS_AT_START :INTEGER;
DROP_PIXELS_AT_END :INTEGER;
DROP_LINES_AT_START :INTEGER;
DROP_LINES_AT_END :INTEGER;
ADD_DATA :STD_LOGIC_VECTOR(15 DOWNTO 0)
);
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
stream_in_data :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_in_startofpacket :IN STD_LOGIC;
stream_in_endofpacket :IN STD_LOGIC;
stream_in_empty :IN STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_in_valid :IN STD_LOGIC;
stream_out_ready :IN STD_LOGIC;
-- Bidirectional
-- Outputs
stream_in_ready :BUFFER STD_LOGIC;
stream_out_data :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_empty :BUFFER STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_out_valid :BUFFER STD_LOGIC
);
END COMPONENT;
COMPONENT altera_up_video_clipper_add
GENERIC (
DW :INTEGER;
EW :INTEGER;
IMAGE_WIDTH :INTEGER;
IMAGE_HEIGHT :INTEGER;
WW :INTEGER;
HW :INTEGER;
ADD_PIXELS_AT_START :INTEGER;
ADD_PIXELS_AT_END :INTEGER;
ADD_LINES_AT_START :INTEGER;
ADD_LINES_AT_END :INTEGER;
ADD_DATA :STD_LOGIC_VECTOR(15 DOWNTO 0)
);
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
stream_in_data :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_in_startofpacket :IN STD_LOGIC;
stream_in_endofpacket :IN STD_LOGIC;
stream_in_empty :IN STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_in_valid :IN STD_LOGIC;
stream_out_ready :IN STD_LOGIC;
-- Bidirectional
-- Outputs
stream_in_ready :BUFFER STD_LOGIC;
stream_out_data :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_empty :BUFFER STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_out_valid :BUFFER STD_LOGIC
);
END COMPONENT;
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
-- Output Registers
-- Internal Registers
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
-- Output Assignments
-- Internal Assignments
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
Clipper_Drop : altera_up_video_clipper_drop
GENERIC MAP (
DW => DW,
EW => EW,
IMAGE_WIDTH => WIDTH_IN,
IMAGE_HEIGHT => HEIGHT_IN,
WW => WW_IN,
HW => HW_IN,
DROP_PIXELS_AT_START => DROP_PIXELS_AT_START,
DROP_PIXELS_AT_END => DROP_PIXELS_AT_END,
DROP_LINES_AT_START => DROP_LINES_AT_START,
DROP_LINES_AT_END => DROP_LINES_AT_END,
ADD_DATA => ADD_DATA
)
PORT MAP (
-- Inputs
clk => clk,
reset => reset,
stream_in_data => stream_in_data,
stream_in_startofpacket => stream_in_startofpacket,
stream_in_endofpacket => stream_in_endofpacket,
stream_in_empty => stream_in_empty,
stream_in_valid => stream_in_valid,
stream_out_ready => internal_ready,
-- Bidirectional
-- Outputs
stream_in_ready => stream_in_ready,
stream_out_data => internal_data,
stream_out_startofpacket => internal_startofpacket,
stream_out_endofpacket => internal_endofpacket,
stream_out_empty => internal_empty,
stream_out_valid => internal_valid
);
Clipper_Add : altera_up_video_clipper_add
GENERIC MAP (
DW => DW,
EW => EW,
IMAGE_WIDTH => WIDTH_OUT,
IMAGE_HEIGHT => HEIGHT_OUT,
WW => WW_OUT,
HW => HW_OUT,
ADD_PIXELS_AT_START => ADD_PIXELS_AT_START,
ADD_PIXELS_AT_END => ADD_PIXELS_AT_END,
ADD_LINES_AT_START => ADD_LINES_AT_START,
ADD_LINES_AT_END => ADD_LINES_AT_END,
ADD_DATA => ADD_DATA
)
PORT MAP (
-- Inputs
clk => clk,
reset => reset,
stream_in_data => internal_data,
stream_in_startofpacket => internal_startofpacket,
stream_in_endofpacket => internal_endofpacket,
stream_in_empty => internal_empty,
stream_in_valid => internal_valid,
stream_out_ready => stream_out_ready,
-- Bidirectional
-- Outputs
stream_in_ready => internal_ready,
stream_out_data => stream_out_data,
stream_out_startofpacket => stream_out_startofpacket,
stream_out_endofpacket => stream_out_endofpacket,
stream_out_empty => stream_out_empty,
stream_out_valid => stream_out_valid
);
END Behaviour;
| gpl-2.0 | 8585dac182c0e2e5ecce13c8f5a5e391 | 0.491529 | 3.885047 | false | false | false | false |
DreamIP/GPStudio | support/process/sobel/hdl/sobel_slave.vhd | 1 | 3,040 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity sobel_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end sobel_slave;
architecture rtl of sobel_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant WIDTHIMG_REG_REG_ADDR : natural := 1;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal widthimg_reg_width_reg : std_logic_vector (15 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
widthimg_reg_width_reg <= "0000000000000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
status_reg_enable_bit_reg <= datawr_i(0);
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
widthimg_reg_width_reg <= datawr_i(15) & datawr_i(14) & datawr_i(13) & datawr_i(12) & datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000000000000000000" & status_reg_enable_bit_reg;
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000" & widthimg_reg_width_reg(15) & widthimg_reg_width_reg(14) & widthimg_reg_width_reg(13) & widthimg_reg_width_reg(12) & widthimg_reg_width_reg(11) & widthimg_reg_width_reg(10) & widthimg_reg_width_reg(9) & widthimg_reg_width_reg(8) & widthimg_reg_width_reg(7) & widthimg_reg_width_reg(6) & widthimg_reg_width_reg(5) & widthimg_reg_width_reg(4) & widthimg_reg_width_reg(3) & widthimg_reg_width_reg(2) & widthimg_reg_width_reg(1) & widthimg_reg_width_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
widthimg_reg_width <= widthimg_reg_width_reg;
end rtl;
| gpl-3.0 | 3c23e17dff015e32365c5f4ecf2276d1 | 0.593092 | 2.881517 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/openmacTimer-rtl-ea.vhd | 3 | 11,296 | -------------------------------------------------------------------------------
--! @file openmacTimer-rtl-ea.vhd
--
--! @brief OpenMAC timer module
--
--! @details This is the openMAC timer module. It supports accessing the MAC
--! time and generating interrupts.
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use openmac package
use work.openmacPkg.all;
entity openmacTimer is
generic (
--! Data width of iMacTime
gMacTimeWidth : natural := 32;
--! Generate second timer
gMacTimer_2ndTimer : boolean := false;
--! Width of pulse register
gTimerPulseRegWidth : integer := 9;
--! Enable pulse width control
gTimerEnablePulseWidth : boolean := false
);
port (
--! Reset
iRst : in std_logic;
--! Clock (same like MAC)
iClk : in std_logic;
--! Write
iWrite : in std_logic;
--! Address (dword addressing!)
iAddress : in std_logic_vector(4 downto 2);
--! Byteenable
iByteenable : in std_logic_vector(3 downto 0);
--! Write data
iWritedata : in std_logic_vector(31 downto 0);
--! Read data
oReaddata : out std_logic_vector(31 downto 0);
--! MAC time
iMacTime : in std_logic_vector(gMacTimeWidth-1 downto 0);
--! Interrupt of first timer (level triggered)
oIrq : out std_logic;
--! Pulse output of second timer
oPulse : out std_logic
);
end openmacTimer;
architecture rtl of openmacTimer is
signal irqEnable : std_logic;
signal pulseEnable : std_logic;
signal irqCompareValue : std_logic_vector(iMacTime'range);
signal pulseCompareValue : std_logic_vector(iMacTime'range);
signal pulseWidthCount : std_logic_vector(gTimerPulseRegWidth-1 downto 0);
signal pulseWidthCountPreset : std_logic_vector(gTimerPulseRegWidth-1 downto 0);
signal pulseWidthCountTc : std_logic;
signal irq : std_logic;
signal pulse : std_logic;
constant cPulseWidthCountZero : std_logic_vector(pulseWidthCount'range) := (others => cInactivated);
begin
oIrq <= irq;
oPulse <= pulse when gMacTimer_2ndTimer = TRUE else cInactivated;
pulseWidthCountTc <= cActivated when pulseWidthCountPreset = cPulseWidthCountZero else
cActivated when pulseWidthCount = pulseWidthCountPreset else
cInactivated;
--! This process generates the interrupt and pulse signals and handles the
--! register writes.
REGPROC : process(iRst, iClk)
begin
if iRst = '1' then
irqEnable <= cInactivated;
irqCompareValue <= (others => cInactivated);
irq <= cInactivated;
if gMacTimer_2ndTimer = TRUE then
pulseEnable <= cInactivated;
pulseCompareValue <= (others => cInactivated);
pulse <= cInactivated;
if gTimerEnablePulseWidth = TRUE then
pulseWidthCount <= (others => cInactivated);
pulseWidthCountPreset <= (others => cInactivated);
end if;
end if;
elsif rising_edge(iClk) then
-- Interrupt generation (oIrq)
if irqEnable = cActivated and iMacTime = irqCompareValue then
irq <= cActivated;
end if;
-- Pulse generation (oPulse) without pulse width control
-- Activates pulse only for one clock cycle (iClk)!
if gMacTimer_2ndTimer and not gTimerEnablePulseWidth then
if pulseEnable = cActivated and iMacTime = pulseCompareValue then
pulse <= cActivated;
else
pulse <= cInactivated;
end if;
end if;
-- Pulse generation (oPulse) with pulse width control
-- Pulse stays active until pulseWidthCount expires.
if gMacTimer_2ndTimer and gTimerEnablePulseWidth then
if pulseEnable = cActivated then
if iMacTime = pulseCompareValue then
pulse <= cActivated;
-- The counter starts with value 1, otherwise it would
-- counter one additional cycle unnecessarily.
pulseWidthCount <= (0 => cActivated, others => cInactivated);
elsif pulse = cActivated and pulseWidthCountTc = cActivated then
pulse <= cInactivated;
else
pulseWidthCount <= std_logic_vector(unsigned(pulseWidthCount) + 1);
end if;
else
-- Pull the pulse signal back to zero since it is deactivated.
pulse <= cInactivated;
end if;
end if;
--memory mapping
if iWrite = '1' then
case iAddress is
when "000" => -- 0x00
-- Enable/disable at offset 0x0
if iByteenable(0) = cActivated then
irqEnable <= iWritedata(0);
end if;
-- Ack at offset 0x1
if iByteenable(1) = cActivated and iWritedata(8) = cActivated then
irq <= cInactivated;
end if;
when "001" => -- 0x04
for i in irqCompareValue'range loop
if iByteenable(i / cByteLength) = cActivated then
irqCompareValue(i) <= iWritedata(i);
irq <= cInactivated;
end if;
end loop;
when "010" => -- 0x08
null; -- reserved
when "011" => -- 0x0C
null; -- RO (MACTIME)
when "100" => -- 0x10
if gMacTimer_2ndTimer = TRUE then
if iByteenable(0) = cActivated then
pulseEnable <= iWritedata(0);
end if;
end if;
when "101" => -- 0x14
if gMacTimer_2ndTimer = TRUE then
for i in pulseCompareValue'range loop
if iByteenable(i / cByteLength) = cActivated then
pulseCompareValue(i) <= iWritedata(i);
pulse <= cInactivated;
end if;
end loop;
end if;
when "110" => -- 0x18
if gMacTimer_2ndTimer = TRUE then
if gTimerEnablePulseWidth = TRUE then
pulseWidthCountPreset <= iWritedata(gTimerPulseRegWidth-1 downto 0);
end if;
end if;
when "111" => -- 0x1C
null; -- RO (MACTIME)
when others =>
assert (FALSE)
report "Write in forbidden area?"
severity failure;
end case;
end if;
end if;
end process REGPROC;
ASSIGN_RD : process (
iAddress, iMacTime,
irq, irqEnable, irqCompareValue,
pulseEnable, pulseCompareValue, pulseWidthCountPreset
)
begin
--default is all zero
oReaddata <= (others => cInactivated);
case iAddress is
when "000" => -- 0x00
oReaddata(1) <= irq;
oReaddata(0) <= irqEnable;
when "001" => -- 0x04
oReaddata(irqCompareValue'range) <= irqCompareValue;
when "010" => -- 0x08
null;
when "011" => -- 0x0C
oReaddata(iMacTime'range) <= iMacTime;
when "100" => -- 0x10
if gMacTimer_2ndTimer = TRUE then
oReaddata(0) <= pulseEnable;
end if;
when "101" => -- 0x14
if gMacTimer_2ndTimer = TRUE then
oReaddata <= pulseCompareValue;
end if;
when "110" => -- 0x18
if gMacTimer_2ndTimer = TRUE and gTimerEnablePulseWidth = TRUE then
oReaddata(pulseWidthCountPreset'range) <= pulseWidthCountPreset;
end if;
when "111" => -- 0x1C
if gMacTimer_2ndTimer = TRUE then
oReaddata(iMacTime'range) <= iMacTime;
end if;
when others =>
NULL; --this is okay, since default assignment is above!
end case;
end process ASSIGN_RD;
end rtl;
| gpl-2.0 | 6afb88e2f9a1a160cf2ba55560dd4d0f | 0.514076 | 5.363723 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/altera/memory/src/dpRamSplx-rtl-a.vhd | 3 | 3,553 | --! @file dpRamSplx-rtl-a.vhd
--
--! @brief Simplex Dual Port Ram Register Transfer Level Architecture
--
--! @details This is the Simplex DPRAM intended for synthesis on Altera
--! platforms only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
-- Architecture : rtl
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use altera_mf library
library altera_mf;
use altera_mf.altera_mf_components.all;
architecture rtl of dpRamSplx is
begin
altsyncram_component : altsyncram
generic map (
operation_mode => "DUAL_PORT",
intended_device_family => "Cyclone IV",
init_file => gInitFile,
numwords_a => gNumberOfWordsA,
numwords_b => gNumberOfWordsB,
widthad_a => logDualis(gNumberOfWordsA),
widthad_b => logDualis(gNumberOfWordsB),
width_a => gWordWidthA,
width_b => gWordWidthB,
width_byteena_a => gByteenableWidthA,
width_byteena_b => gByteenableWidthA
)
port map (
clock0 => iClk_A,
clocken0 => iEnable_A,
wren_a => iWriteEnable_A,
address_a => iAddress_A,
byteena_a => iByteenable_A,
data_a => iWritedata_A,
clock1 => iClk_B,
clocken1 => iEnable_B,
address_b => iAddress_B,
q_b => oReaddata_B
);
end architecture rtl;
| gpl-2.0 | d986a7fff9e3e61b16e3e1220a50a03f | 0.582325 | 4.769128 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_sysid_qsys_0_control_slave_translator.vhd | 1 | 12,335 | -- tracking_camera_system_sysid_qsys_0_control_slave_translator.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.13.13:59:38
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tracking_camera_system_sysid_qsys_0_control_slave_translator is
generic (
AV_ADDRESS_W : integer := 1;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(0 downto 0); -- avalon_anti_slave_0.address
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_byteenable : out std_logic_vector(3 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_read : out std_logic;
av_readdatavalid : in std_logic := '0';
av_waitrequest : in std_logic := '0';
av_write : out std_logic;
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writedata : out std_logic_vector(31 downto 0);
uav_clken : in std_logic := '0'
);
end entity tracking_camera_system_sysid_qsys_0_control_slave_translator;
architecture rtl of tracking_camera_system_sysid_qsys_0_control_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(0 downto 0); -- address
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component altera_merlin_slave_translator;
begin
sysid_qsys_0_control_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_readdata => av_readdata, -- .readdata
av_write => open, -- (terminated)
av_read => open, -- (terminated)
av_writedata => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
end architecture rtl; -- of tracking_camera_system_sysid_qsys_0_control_slave_translator
| gpl-2.0 | 68aba47c3552e74b00e15869a2966c11 | 0.443859 | 4.202726 | false | false | false | false |
DreamIP/GPStudio | support/process/sconv/tb/tb_conv.vhd | 1 | 2,623 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_conv is
end tb_conv;
architecture tb_arc of tb_conv is
signal in_datas, w11s , w12s , w13s , w21s , w22s , w23s , w31s , w32s , w33s , out_datas : std_logic_vector (7 downto 0) := "00000000";
signal in_dvs,in_fvs,mrs,out_dvs,out_fvs : std_logic := '0';
signal clks : std_logic := '0';
component conv
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer
);
port(
clk : in std_logic;
reset : in std_logic;
-- IN FLOW
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
--IN kernel
w11,w12,w13,w21,w22,w23,w31,w32,w33 : in std_logic_vector ((PIX_WIDTH-1) downto 0);
--OUT flow
out_data : out std_logic_vector (7 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
begin
i : conv
generic map(
LINE_WIDTH_MAX => 5,
PIX_WIDTH => 8
)
port map (
clks,
mrs,
in_datas,
in_fvs,
in_dvs,
w11s , w12s , w13s , w21s , w22s , w23s , w31s , w32s , w33s,
out_datas,
out_fvs,
out_dvs
);
clks <= not (clks) after 50 ns;
stim_dv : process
begin
in_dvs <= '0';
wait for 100 ns;
in_dvs <= '1';
wait for 500 ns;
in_dvs <= '0';
wait for 200 ns;
in_dvs <= '1';
wait for 100 ns;
in_dvs <= '0';
wait for 100 ns;
in_dvs <= '1';
wait for 100 ns;
in_dvs <= '0';
wait for 100 ns;
end process;
stim_fv : process
begin
in_fvs <= '0';
wait for 100 ns;
in_fvs <= '1';
wait for 2000 ns;
end process;
test : process
variable i : integer := 0;
begin
in_datas <= "00000000";
mrs <= '1';
wait for 100 ns;
mrs <= '0';
w11s <= std_logic_vector(to_unsigned(1,8));
w12s <= std_logic_vector(to_unsigned(1,8));
w13s <= std_logic_vector(to_unsigned(1,8));
w21s <= std_logic_vector(to_unsigned(1,8));
w22s <= std_logic_vector(to_unsigned(1,8));
w23s <= std_logic_vector(to_unsigned(1,8));
w31s <= std_logic_vector(to_unsigned(1,8));
w32s <= std_logic_vector(to_unsigned(1,8));
w33s <= std_logic_vector(to_unsigned(1,8));
for i in 1 to 100 loop
wait for 50 ns;
in_datas <= std_logic_vector(to_unsigned(i,8));
end loop;
end process;
end tb_arc;
| gpl-3.0 | 23b169d7f9b288bf8a095ba9bcdcb545 | 0.513915 | 2.546602 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/verif/blink.vhdl | 1 | 987 | --
-- Blink
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2015 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
entity Blink is
generic (
FREQUENCY : positive:=25e6;
SECONDS : positive:=1
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
blink_o : out std_logic
);
end entity Blink;
architecture RTL of Blink is
constant DIV : positive:=FREQUENCY*SECONDS-1;
signal blink : std_logic;
begin
do_blink:
process (clk_i)
variable cnt: natural range 0 to DIV:=0;
begin
if rising_edge(clk_i) then
if rst_i='1' then
cnt:=0;
blink <= '0';
else
if cnt=DIV then
cnt:=0;
blink <= not(blink);
else
cnt:=cnt+1;
end if;
end if;
end if;
end process do_blink;
blink_o <= blink;
end architecture RTL;
| bsd-3-clause | 77efdf59b510841adfabfe1710b6ef2b | 0.530902 | 3.525 | false | false | false | false |
DreamIP/GPStudio | support/io/mpu/hdl/mpu_i2c.vhd | 1 | 10,609 | --------------------------------------------------------------------------------------
-- This bloc handles the control of the i2c communication block (mpu_i2c_master.vhd)
-- It receive the data and place them into a FIFO. When a full sample is detected,
-- data are sent to usb block.
--------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.mpu_pkg.all;
ENTITY mpu_i2c IS
PORT(
clk : in std_logic;
en : in std_logic; --Enable
reset_n : IN STD_LOGIC; --active low reset
config_button : in std_logic; --active la config des registres de l'IMU
trigger : in std_logic; --lance une lecture du registre (possibilité de burst read)
data_read : out std_logic_vector(7 downto 0); --données lues
fifo_wr_en : out std_logic; --écriture des données dans la fifo
spl_rate : in std_logic_vector(7 downto 0); --Parametres
gyro_config : in std_logic_vector(1 downto 0); --
accel_config : in std_logic_vector(1 downto 0); --
gain_compass : in std_logic_vector(2 downto 0);
freq_compass : in std_logic_vector(2 downto 0);
reset_fifo_buffer : in std_logic; --Reset le buffer de la FIFO
run_conf : out std_logic;
rd_fifo_count : in std_LOGIC;
sda : INOUT STD_LOGIC; --serial data output of i2c bus
scl : INOUT STD_LOGIC --serial clock output of i2c bus
);
END mpu_i2c;
ARCHITECTURE behavioral OF mpu_i2c IS
signal clk_s : std_logic;
signal reset_n_s : std_logic;
signal ena_s : std_logic;
signal rw_s : std_logic;
signal data_wr_s : std_logic_vector(7 downto 0);
signal addr_s : std_logic_vector(6 downto 0);
signal busy_s : std_logic;
signal data_rd_s : std_logic_vector(7 downto 0);
signal end_rw_s : std_logic;
signal master_ack_flag : std_logic;
signal register_number : std_logic_vector(7 downto 0);
signal data_to_w : std_logic_vector(7 downto 0);
signal prev_end_rw : std_logic;
signal count_ack : unsigned(7 downto 0);
signal detect_config : std_logic;
signal trig_read_dl : std_logic;
signal trig : std_logic;
signal op_counter_f : std_logic;
signal op_counter_f_dl : std_logic;
signal op_counter : unsigned(7 downto 0);
signal reset_fifo_flag : std_logic;
signal reset_fifo_dl : std_logic;
signal run_conf_s : std_logic;
signal rd_fifo_count_dl : std_logic;
type state_fsm is (idle,init,read_state, write_state);
signal state : state_fsm;
type state_config is (waiting, config);
signal state_conf : state_config;
begin
mpu_i2c_master_inst : entity work.mpu_i2c_master(logic)
generic map (input_clk => 50_000_000 ,bus_clk => 400_000)
port map(
clk => clk,
reset_n => reset_n,
end_rw => end_rw_s,
master_ack_flag => master_ack_flag,
op_counter => op_counter_f,
fifo_wr_en => fifo_wr_en,
ena => ena_s,
addr => addr_s,
rw => rw_s,
data_wr => data_wr_s,
busy => busy_s,
data_rd => data_rd_s,
ack_error => open,
sda => sda,
scl => scl
);
------ I2C controller
process(clk,reset_n)
begin
if reset_n='0' then
state <= idle;
rw_s <= '1';
ena_s <= '0';
elsif clk'event and clk='1' then
trig_read_dl <= trigger;
trig <= trigger and not trig_read_dl;
prev_end_rw <= end_rw_s;
reset_fifo_dl <= reset_fifo_buffer;
reset_fifo_flag <= (reset_fifo_buffer and not reset_fifo_dl) or (rd_fifo_count and not rd_fifo_count_dl);
rd_fifo_count_dl <= rd_fifo_count;
case (state) is
when idle =>
if en='1' then
if (busy_s='0' and (trig='1' or run_conf_s='1')) or reset_fifo_flag='1' then ----- Start of communication detected
state <= init;
else
state <= idle;
end if;
end if;
when init =>
rw_s <= '0';
ena_s <= '1';
data_wr_s <= register_number;
if state_conf=config or reset_fifo_buffer='1' then ----- Write mode : configuration
state <= write_state;
else
if end_rw_s = '1' then ----- Read mode : data acquisition
state <= read_state;
end if;
end if;
when read_state =>
rw_s <= '1';
if master_ack_flag = '1' then
data_read <= data_rd_s;
if end_rw_s='1' and prev_end_rw='0' then
count_ack <= count_ack +1;
state <= read_state;
end if;
if count_ack=x"14" or (count_ack=x"2" and rd_fifo_count='1') then ----- Full sample detected in the FIFO
state <= idle;
ena_s <= '0';
count_ack <= x"00";
end if;
end if;
when write_state =>
rw_s <= '0';
if end_rw_s='1' and prev_end_rw='0' then ----- Counting acknowledges
count_ack <= count_ack +1;
state <= write_state;
end if;
if count_ack =x"01" then
data_wr_s <= data_to_w; ----- Sending data to write in the MPU internal register
elsif count_ack=x"02" then
state <= idle;
ena_s <= '0';
count_ack <= x"00";
else
data_wr_s <= register_number; ----- Sending the internal register ID
end if;
when others =>
state <= idle;
end case;
end if;
end process;
------ Configuration step by step of the MPU-6050 with user settings
process(clk, reset_n)
begin
if reset_n ='0' then
register_number <= x"00";
data_to_w <= x"00";
op_counter <= x"00";
addr_s <= ADDR_I2C_MPU;
run_conf_s <= '0';
elsif clk'event and clk='1' then
----- Counting configuration operations
op_counter_f_dl <= op_counter_f;
if op_counter_f='1' and op_counter_f_dl='0' then
if (op_counter < x"12") then
op_counter <= op_counter +1;
else
op_counter <= x"00";
end if;
end if;
case(state_conf) is
when waiting =>
op_counter <= x"00";
----- Reset fifo buffer to avoid latence issues
if reset_fifo_buffer='1' then
addr_s <= ADDR_I2C_MPU;
register_number <= USER_CTRL;
data_to_w <= x"64";
----- Reading data from the internal FIFO of the MPU-6050
elsif rd_fifo_count='1' then
addr_s <= ADDR_I2C_MPU;
register_number <= x"72";--3A int status
data_to_w <= x"00";
else
addr_s <= ADDR_I2C_MPU;
register_number <= FIFO_READ;
data_to_w <= x"00";
end if;
----- Modification of the configuration settings detected, starting a configuration sequence
if config_button = '1' then
state_conf <= config;
else
state_conf <= waiting;
run_conf_s <= '0';
end if;
when config =>
----- Sortie du mode "Pause"
if op_counter=x"00" then
addr_s <= ADDR_I2C_MPU;
register_number <= PWR_MGMT_1;
data_to_w <= x"01";
run_conf_s <= '1';
----- FIFO enable
elsif op_counter=x"01" then
register_number <= USER_CTRL;
data_to_w <= x"40";
----- Accelerometer configuration
elsif op_counter=x"02" then
register_number <= ACCEL_CONFIG_REG;
data_to_w <= "000" & accel_config & "000";
------ Sample rate
elsif op_counter=x"03" then
register_number <= SMPLRT_DIV;
data_to_w <= spl_rate;
----- Data to place in internal FIFO
elsif op_counter = x"04" then
register_number <= FIFO_EN;
data_to_w <= x"F9";---x"F8" sans compass
----- Gyroscope configuration
elsif op_counter=x"05" then
register_number <= GYRO_CONFIG_REG;
data_to_w <= "000" & gyro_config & "000";
----- Bypassing MPU : I2C bus directly connected to compass
elsif op_counter=x"06" then
register_number <= BYPASS_MPU;
data_to_w <= x"02";
----- Compass sample rate
elsif op_counter=x"07" then
addr_s <= ADDR_I2C_COMPASS;
register_number <= COMPASS_CONF_A;
data_to_w <= "011" & freq_compass & "00";
----- Compass automatic mode activation
elsif op_counter=x"08" then
register_number <= COMPASS_MODE;
data_to_w <= x"00";
----- Compass gain value
elsif op_counter=x"09" then
register_number <= COMPASS_CONF_B;
data_to_w <= gain_compass & "00000";
----- Disable bypass
elsif op_counter=x"0A" then
addr_s <= ADDR_I2C_MPU;
register_number <= BYPASS_MPU;
data_to_w <= x"00";
----- MPU set to master on his auxiliary I2C bus
elsif op_counter=x"0B" then
register_number <= USER_CTRL;
data_to_w <= x"60";
----- Auxiliary I2C bus frequency set to 400kHz
elsif op_counter=x"0C" then
register_number <= I2C_MST_CTRL;
data_to_w <= x"0D";
----- I2C address of compass + mode read
elsif op_counter=x"0D" then
register_number <= I2C_SLV0_ADDR;
data_to_w <= x"9E";
----- Internal register from compass from which the data will be read
elsif op_counter=x"0E" then
register_number <= I2C_SLV0_REG;
data_to_w <= x"03";
----- Enable the acquisition of the 6 bytes of data from compass
elsif op_counter=x"0F" then
register_number <= I2C_SLV0_CTRL;
data_to_w <= x"86";
----- Enable data ready interrupt
elsif op_counter=x"10" then
register_number <= x"38";
data_to_w <= x"01";
elsif op_counter=x"11" then
register_number <= USER_CTRL;
data_to_w <= x"64";
state_conf <= waiting;
run_conf_s <= '0';
else
register_number <= x"00";
end if;
when others =>
state_conf <= waiting;
end case;
end if;
end process;
run_conf <= run_conf_s;
end behavioral;
| gpl-3.0 | 9dea2c348eaa3cafe9189237133c216b | 0.520698 | 3.043042 | false | true | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/lutFileRtl.vhd | 3 | 3,409 | -------------------------------------------------------------------------------
--! @file lutFileRtl.vhd
--
--! @brief Look-up table file implementation
--
--! @details This look-up table file stores initialization values (generics)
--! in LUT resources.
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity lutFile is
generic (
gLutCount : natural := 4;
gLutWidth : natural := 32;
gLutInitValue : std_logic_vector :=
x"1111_1111" & x"2222_2222" & x"3333_3333" & x"4444_4444"
);
port (
iAddrRead : in std_logic_vector(LogDualis(gLutCount)-1 downto 0);
oData : out std_logic_vector
);
end lutFile;
architecture Rtl of lutFile is
constant cLutFile : std_logic_vector(gLutCount*gLutWidth-1 downto 0) :=
gLutInitValue;
signal lutOutput : std_logic_vector(gLutWidth-1 downto 0);
begin
--Lut File is a bitstream that is blockwise (gLutWidth) read with
--respect to iAddrRead.
bitSelect : process(iAddrRead)
begin
--default
lutOutput <= (others => '0');
for i in gLutWidth-1 downto 0 loop
--assign selected bits in Lut File to output
lutOutput(i) <= cLutFile
( (gLutCount-1-to_integer(unsigned(iAddrRead)))*gLutWidth + i );
end loop;
end process;
--! downscale lut width to output
oData <= lutOutput(oData'range);
end Rtl;
| gpl-2.0 | 389a7f1f5bc8808b662408b3415d7fcb | 0.634204 | 4.364917 | false | false | false | false |
DreamIP/GPStudio | support/io/gps/hdl/gps_slave.vhd | 1 | 2,542 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity gps_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
enable_reg : out std_logic_vector(31 downto 0);
sat_reg : out std_logic_vector(31 downto 0);
update_reg : out std_logic_vector(31 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end gps_slave;
architecture rtl of gps_slave is
-- Registers address
constant ENABLE_REG_REG_ADDR : natural := 0;
constant SAT_REG_REG_ADDR : natural := 1;
constant UPDATE_REG_REG_ADDR : natural := 2;
-- Internal registers
signal enable_reg_reg : std_logic_vector (31 downto 0);
signal sat_reg_reg : std_logic_vector (31 downto 0);
signal update_reg_reg : std_logic_vector (31 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
enable_reg_reg <= x"00000000";
sat_reg_reg <= x"00000000";
update_reg_reg <= x"00000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(ENABLE_REG_REG_ADDR, 2))=>
enable_reg_reg <= datawr_i;
when std_logic_vector(to_unsigned(SAT_REG_REG_ADDR, 2))=>
sat_reg_reg <= datawr_i;
when std_logic_vector(to_unsigned(UPDATE_REG_REG_ADDR, 2))=>
update_reg_reg <= datawr_i;
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(ENABLE_REG_REG_ADDR, 2))=>
datard_o <= enable_reg_reg;
when std_logic_vector(to_unsigned(SAT_REG_REG_ADDR, 2))=>
datard_o <= sat_reg_reg;
when std_logic_vector(to_unsigned(UPDATE_REG_REG_ADDR, 2))=>
datard_o <= update_reg_reg;
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
enable_reg <= enable_reg_reg;
sat_reg <= sat_reg_reg;
update_reg <= update_reg_reg;
end rtl;
| gpl-3.0 | b29495b210bf2f1ed68e9b99de38a2ff | 0.580645 | 2.935335 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/phyMgmt-rtl-ea.vhd | 3 | 9,447 | -------------------------------------------------------------------------------
--! @file phyMgmt-rtl-ea.vhd
--
--! @brief OpenMAC phy management module
--
--! @details This is the openMAC phy management module to configure the connected
--! phys via SMI (= serial management interface).
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity phyMgmt is
port (
--! Reset
iRst : in std_logic;
--! Clock
iClk : in std_logic;
--! Address (word addresses)
iAddress : in std_logic_vector(3 downto 1);
--! Select
iSelect : in std_logic;
--! Byteenale (low-active)
inByteenable : in std_logic_vector(1 downto 0);
--! Write (low-active)
inWrite : in std_logic;
--! Writedata
iWritedata : in std_logic_vector(15 downto 0);
--! Readdata
oReaddata : out std_logic_vector(15 downto 0);
--! SMI Clock
oSmiClk : out std_logic;
--! SMI data input
iSmiDataIn : in std_logic;
--! SMI data output
oSmiDataOut : out std_logic;
--! SMI data output enable
oSmiDataOutEnable : out std_logic;
--! Phy reset (low-active)
onPhyReset : out std_logic
);
end entity phyMgmt;
architecture rtl of phyMgmt is
--! This is the shift register to serialize write and read data.
signal shift_reg : std_logic_vector(31 downto 0);
--! This is the generated SMI clock.
signal smiClk : std_logic;
--! This is the clock divider vector to generate smiClk.
signal clkDivider : std_logic_vector(4 downto 0);
--! This alias triggers shifting the shift register.
alias doShift : std_logic is clkDivider(clkDivider'high);
--! This is the bit counter for serializing.
signal bit_cnt : std_logic_vector(2 downto 0);
--! This is the byte counter for serializing.
signal byte_cnt : std_logic_vector(2 downto 0);
--! This flag signalizes activity.
signal runActive : std_logic;
--! This flag signalizes a busy shift register.
signal shiftBusy : std_logic;
--! This signal is used to control the phy reset (low active).
signal nPhyReset : std_logic;
--! This is the internal SMI data output.
signal smiDataOut : std_logic;
--! This is the internal SMI data output enable.
signal smiDataOutEnable : std_logic;
begin
---------------------------------------------------------------------------
-- Assign outputs
---------------------------------------------------------------------------
oSmiClk <= smiClk;
oSmiDataOut <= smiDataOut;
oSmiDataOutEnable <= smiDataOutEnable;
onPhyReset <= nPhyReset;
--! This process assigns the readdata vector.
ASSIGN_READDATA : process (
nPhyReset,
shiftBusy,
shift_reg,
iAddress
)
begin
-- default is zero
oReaddata <= (others => cInactivated);
if iAddress(1) = cInactivated then
oReaddata(7) <= nPhyReset;
oReaddata(0) <= shiftBusy;
else
oReaddata <= shift_reg(15 downto 0);
end if;
end process ASSIGN_READDATA;
--! This process generates the SMI signals and assigns memory mapped writes.
doSMI : process (iRst, iClk)
begin
if iRst = cActivated then
smiClk <= cInactivated;
runActive <= cInactivated;
shiftBusy <= cInactivated;
smiDataOutEnable <= cActivated;
smiDataOut <= cActivated;
nPhyReset <= cnActivated;
bit_cnt <= (others => cInactivated);
byte_cnt <= (others => cInactivated);
shift_reg <= x"0000abcd";
clkDivider <= (others => cInactivated);
elsif rising_edge(iClk) then
if doShift = cActivated then
clkDivider <= std_logic_vector(to_unsigned(8, clkDivider'length) + 1);
smiClk <= not smiClk;
else
clkDivider <= std_logic_vector(unsigned(clkDivider) - 1);
end if;
if (iSelect = cActivated and inWrite = cnActivated and shiftBusy = cInactivated and
iAddress(2) = cActivated and inByteenable(0) = cnActivated) then
nPhyReset <= iWritedata(7);
end if;
if (iSelect = cActivated and inWrite = cnActivated and shiftBusy = cInactivated and
iAddress(2) = cInactivated) then
if iAddress(1) = cInactivated then
if inByteenable(1) = cnActivated then
shift_reg(31 downto 24) <= iWritedata(15 downto 8);
end if;
if inByteenable(0) = cnActivated then
shift_reg(23 downto 16) <= iWritedata(7 downto 0);
shiftBusy <= cActivated;
end if;
else
if inByteenable(1) = cnActivated then
shift_reg(15 downto 8) <= iWritedata(15 downto 8);
end if;
if inByteenable(0) = cnActivated then
shift_reg(7 downto 0) <= iWritedata(7 downto 0);
end if;
end if;
else
if doShift = cActivated and smiClk = cActivated then
if runActive = cInactivated and shiftBusy = cActivated then
runActive <= cActivated;
byte_cnt <= "111";
bit_cnt <= "111";
else
if byte_cnt(2) = cInactivated and shiftBusy = cActivated then
smiDataOut <= shift_reg(31);
shift_reg <= shift_reg(30 downto 0) & iSmiDataIn;
end if;
bit_cnt <= std_logic_vector(unsigned(bit_cnt) - 1);
if bit_cnt = std_logic_vector(to_unsigned(0, bit_cnt'length)) then
byte_cnt <= std_logic_vector(unsigned(byte_cnt) - 1);
if byte_cnt = std_logic_vector(to_unsigned(0, byte_cnt'length)) then
shiftBusy <= cInactivated;
runActive <= cInactivated;
end if;
end if;
if (byte_cnt = std_logic_vector(to_unsigned(2, byte_cnt'length)) and
bit_cnt = std_logic_vector(to_unsigned(1, bit_cnt'length)) and
shift_reg(31) = cInactivated) then
smiDataOutEnable <= cInactivated;
end if;
end if;
if shiftBusy = cInactivated or runActive = cInactivated then
smiDataOut <= cActivated;
smiDataOutEnable <= cActivated;
end if;
end if;
end if;
end if;
end process doSMI;
end rtl; | gpl-2.0 | 9ed628f9929ba2a60a6760b731b6776a | 0.525246 | 5.041089 | false | false | false | false |
hoglet67/ElectronFpga | src/xilinx/DCM/pll1.vhd | 1 | 3,496 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity pll1 is
port
(-- Clock in ports
CLKIN_IN : in std_logic;
-- Clock out ports
CLK0_OUT : out std_logic;
CLK1_OUT : out std_logic;
CLK2_OUT : out std_logic;
CLK3_OUT : out std_logic
);
end pll1;
architecture xilinx of pll1 is
signal GND_BIT : std_logic;
signal CLKFBOUT : std_logic;
signal CLKFB : std_logic;
signal CLKFBIN : std_logic;
signal CLKIN : std_logic;
signal CLK0 : std_logic;
signal CLK0_BUF : std_logic;
signal CLK1 : std_logic;
signal CLK1_BUF : std_logic;
signal CLK2 : std_logic;
signal CLK2_BUF : std_logic;
signal CLK3 : std_logic;
signal CLK3_BUF : std_logic;
begin
GND_BIT <= '0';
-- This PLL completely de-skews the clock network wrt the input pin
-- Note: the BUFIO2 instance needed manually placing in the .ucf file
-- Clock input io2 buffer
CLKIN_BUFIO2_INST : BUFIO2
port map (I => CLKIN_IN, DIVCLK => CLKIN);
-- Clock feedback output buffer
CLKFB_BUFG_INST : BUFG
port map (I => CLKFBOUT, O => CLKFB);
-- Clock feedback io2 buffer
CLKFB_BUFIO2FB_INST : BUFIO2FB
port map (I => CLKFB, O => CLKFBIN);
-- CLK0 output buffer
CLK0_BUFG_INST : BUFG
port map (I => CLK0, O => CLK0_BUF);
CLK0_OUT <= CLK0_BUF;
-- CLK1 output buffer
CLK1_BUFG_INST : BUFG
port map (I => CLK1, O => CLK1_BUF);
CLK1_OUT <= CLK1_BUF;
-- CLK2 output buffer
CLK2_BUFG_INST : BUFG
port map (I => CLK2, O => CLK2_BUF);
CLK2_OUT <= CLK2_BUF;
-- CLK3 output buffer
CLK3_BUFG_INST : BUFG
port map (I => CLK3, O => CLK3_BUF);
CLK3_OUT <= CLK3_BUF;
INST_PLL : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS", -- not sure this is correct
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 15, -- 32 x 15 = 480MHz
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 30, -- 480 / 30 = 16MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 20, -- 480 / 20 = 24 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 15, -- 480 / 15 = 32 MHz
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DIVIDE => 12, -- 480 / 12 = 40 MHZ
CLKOUT3_PHASE => 0.000,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map (
-- Input clock control
CLKIN => CLKIN,
CLKFBIN => CLKFBIN,
-- Output clocks
CLKFBOUT => CLKFBOUT,
CLKOUT0 => CLK0,
CLKOUT1 => CLK1,
CLKOUT2 => CLK2,
CLKOUT3 => CLK3,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => GND_BIT
);
end xilinx;
| gpl-3.0 | b0c3eec188c4443933a96090c15683ea | 0.499714 | 3.67613 | false | false | false | false |
hoglet67/ElectronFpga | src/xilinx/bootstrap.vhd | 1 | 11,060 | --------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : bootstrap.vhd
-- /___/ /\ Timestamp : 28/07/2015
-- \ \ / \
-- \___\/\___\
--
--Design Name: bootstrap
--Device: Spartan6 LX9
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity bootstrap is
generic (
-- start address of user data in FLASH
user_address : std_logic_vector(23 downto 0) := x"060000";
-- length user data in flash
user_length : std_logic_vector(23 downto 0) := x"040000"
);
port (
clock : in std_logic;
-- initiate bootstrap
powerup_reset_n : in std_logic;
-- high when FLASH is being copied to SRAM, can be used by user as active high reset
bootstrap_busy : out std_logic;
-- interface from design
RAM_nOE : in std_logic;
RAM_nWE : in std_logic;
RAM_nCS : in std_logic;
RAM_A : in std_logic_vector (18 downto 0);
RAM_Din : in std_logic_vector (7 downto 0);
RAM_Dout : out std_logic_vector (7 downto 0);
-- interface to external SRAM
SRAM_nOE : out std_logic;
SRAM_nWE : out std_logic;
SRAM_nCS : out std_logic;
SRAM_A : out std_logic_vector (20 downto 0);
SRAM_D : inout std_logic_vector (7 downto 0);
-- interface to external FLASH
FLASH_CS : out std_logic; -- Active low FLASH chip select
FLASH_SI : out std_logic; -- Serial output to FLASH chip SI pin
FLASH_CK : out std_logic; -- FLASH clock
FLASH_SO : in std_logic -- Serial input from FLASH chip SO pin
);
end;
architecture behavioral of bootstrap is
-- internal signals for SRAM interface
signal SRAM_Din : std_logic_vector (7 downto 0);
signal SRAM_nDOE : std_logic_vector (7 downto 0);
signal SRAM_nWE_int : std_logic;
-- an internal clock enable, avoiding gated clocks
signal clock_en : std_logic := '0';
--
-- bootstrap signals
--
signal flash_init : std_logic; -- when low places FLASH driver in init state
signal flash_Done : std_logic; -- FLASH init finished when high
signal flash_data : std_logic_vector(7 downto 0);
-- bootstrap control of SRAM, these signals connect to SRAM when boostrap_busy = '1'
signal bs_A : std_logic_vector(18 downto 0);
signal bs_Din : std_logic_vector(7 downto 0);
signal bs_nCS : std_logic;
signal bs_nWE : std_logic;
signal bs_nOE : std_logic;
signal bs_busy : std_logic;
-- for bootstrap state machine
type BS_STATE_TYPE is (
INIT, START_READ_FLASH, READ_FLASH, FLASH0, FLASH1, FLASH2, FLASH3, FLASH4, FLASH5, FLASH6, FLASH7,
WAIT0, WAIT1, WAIT2, WAIT3, WAIT4, WAIT5, WAIT6, WAIT7, WAIT8, WAIT9, WAIT10, WAIT11
);
signal bs_state : BS_STATE_TYPE := INIT;
begin
bootstrap_busy <= bs_busy;
--------------------------------------------------------
-- SRAM Multiplexor
--------------------------------------------------------
SRAM_Din <= bs_Din when bs_busy = '1' else RAM_Din;
SRAM_A(18 downto 0) <= bs_A when bs_busy = '1' else RAM_A;
SRAM_A(19) <= '0';
SRAM_A(20) <= '0';
SRAM_nCS <= bs_nCS when bs_busy = '1' else RAM_nCS;
SRAM_nOE <= bs_nOE when bs_busy = '1' else RAM_nOE;
--------------------------------------------------------
-- Generate a gated RAM WE and Dout tristate controls
--------------------------------------------------------
-- The point of all this is to avoid conflicts with the SRAM
-- where the data bus changes direction
-- On the falling edge of clock_32, SRAM_nWE goes low if SRAM_nWE_int is low
-- On the rising edhe of clock_32, SRAM_nWE goes high again
SRAM_nWE_int <= bs_nWE when bs_busy = '1' else RAM_nWE;
rx_clk_ddr : ODDR2
port map (
Q => SRAM_nWE,
C0 => not clock,
C1 => clock,
CE => '1',
D0 => SRAM_nWE_int,
D1 => '1',
R => '0',
S => '0'
);
gen_sram_data_io: for i in 0 to 7 generate
-- replicate the ODDR2 for each data bit, because of limited routing
oddr2x : ODDR2
port map (
Q => SRAM_nDOE(i),
C0 => not clock,
C1 => clock,
CE => '1',
D0 => SRAM_nWE_int,
D1 => '1',
R => '0',
S => '0'
);
-- the active low tristate connects directly to the IOBUFT in the same IOB
iobufx : IOBUF
generic map (
DRIVE => 8
)
port map (
O => RAM_Dout(i),
I => SRAM_Din(i),
IO => SRAM_D(i),
T => SRAM_nDOE(i)
);
end generate;
--------------------------------------------------------
-- Bootstrap SRAM from SPI FLASH
--------------------------------------------------------
-- flash clock enable toggles on alternate cycles
process(clock)
begin
if rising_edge(clock) then
clock_en <= not clock_en;
end if;
end process;
-- bootstrap state machine
state_bootstrap : process(clock, powerup_reset_n)
begin
if powerup_reset_n = '0' then -- external reset pin
bs_state <= INIT; -- move state machine to INIT state
elsif rising_edge(clock) then
if clock_en = '1' then
case bs_state is
when INIT =>
bs_busy <= '1'; -- indicate bootstrap in progress (holds user in reset)
flash_init <= '0'; -- signal FLASH to begin init
bs_A <= (others => '1'); -- SRAM address all ones (becomes zero on first increment)
bs_nCS <= '0'; -- SRAM always selected during bootstrap
bs_nOE <= '1'; -- SRAM output disabled during bootstrap
bs_nWE <= '1'; -- SRAM write enable inactive default state
bs_state <= START_READ_FLASH;
when START_READ_FLASH =>
flash_init <= '1'; -- allow FLASH to exit init state
if flash_Done = '0' then -- wait for FLASH init to begin
bs_state <= READ_FLASH;
end if;
when READ_FLASH =>
if flash_Done = '1' then -- wait for FLASH init to complete
bs_state <= WAIT0;
end if;
when WAIT0 => -- wait for the first FLASH byte to be available
bs_state <= WAIT1;
when WAIT1 =>
bs_state <= WAIT2;
when WAIT2 =>
bs_state <= WAIT3;
when WAIT3 =>
bs_state <= WAIT4;
when WAIT4 =>
bs_state <= WAIT5;
when WAIT5 =>
bs_state <= WAIT6;
when WAIT6 =>
bs_state <= WAIT7;
when WAIT7 =>
bs_state <= WAIT8;
when WAIT8 =>
bs_state <= FLASH0;
when WAIT9 =>
bs_state <= WAIT10;
when WAIT10 =>
bs_state <= WAIT11;
when WAIT11 =>
bs_state <= FLASH0;
-- every 8 clock cycles (32M/8 = 2Mhz) we have a new byte from FLASH
-- use this ample time to write it to SRAM, we just have to toggle nWE
when FLASH0 =>
bs_A <= bs_A + 1; -- increment SRAM address
bs_state <= FLASH1; -- idle
when FLASH1 =>
bs_Din( 7 downto 0) <= flash_data; -- place byte on SRAM data bus
bs_state <= FLASH2; -- idle
when FLASH2 =>
bs_nWE <= '0'; -- SRAM write enable
bs_state <= FLASH3;
when FLASH3 =>
bs_state <= FLASH4; -- idle
when FLASH4 =>
bs_state <= FLASH5; -- idle
when FLASH5 =>
bs_state <= FLASH6; -- idle
when FLASH6 =>
bs_nWE <= '1'; -- SRAM write disable
bs_state <= FLASH7;
when FLASH7 =>
if "000" & bs_A = user_length then -- when we've reached end address
bs_busy <= '0'; -- indicate bootsrap is done
flash_init <= '0'; -- place FLASH in init state
bs_state <= FLASH7; -- remain in this state until reset
else
bs_state <= FLASH0; -- else loop back
end if;
when others => -- catch all, never reached
bs_state <= INIT;
end case;
end if;
end if;
end process;
-- FLASH chip SPI driver
u_flash : entity work.spi_flash port map (
flash_clk => clock,
flash_clken => clock_en,
flash_init => flash_init,
flash_addr => user_address,
flash_data => flash_data,
flash_Done => flash_Done,
U_FLASH_CK => FLASH_CK,
U_FLASH_CS => FLASH_CS,
U_FLASH_SI => FLASH_SI,
U_FLASH_SO => FLASH_SO
);
end behavioral;
| gpl-3.0 | 020bb3c773a7f01e6ab21211ba7aed8a | 0.41311 | 4.631491 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/sync/divider.vhdl | 1 | 922 | --
-- Divider
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2015-2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
entity Divider is
generic(
DIV : positive range 2 to positive'high:=2
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
ena_i : in std_logic:='1';
ena_o : out std_logic
);
end entity Divider;
architecture RTL of Divider is
signal cnt_r : integer range 0 to DIV-1;
begin
do_div: process (clk_i)
begin
if rising_edge(clk_i) then
ena_o <= '0';
if rst_i='1' then
cnt_r <= 0;
elsif ena_i='1' then
if cnt_r=DIV-1 then
cnt_r <= 0;
ena_o <= '1';
else
cnt_r <= cnt_r+1;
end if;
end if;
end if;
end process do_div;
end architecture RTL;
| bsd-3-clause | 556ee2b6233dc9a252c9d969f39e9b1f | 0.520607 | 3.281139 | false | false | false | false |
DreamIP/GPStudio | support/io/d5m/hdl/RGB2GRY.vhd | 1 | 3,726 | -------------------------------------------------------------------------------
-- Copyright Institut Pascal Equipe Dream (19-10-2016)
-- Francois Berry, El Mehdi Abdali, Maxime Pelcat
-- This software is a computer program whose purpose is to manage dynamic
-- partial reconfiguration.
-- This software is governed by the CeCILL-C license under French law and
-- abiding by the rules of distribution of free software. You can use,
-- modify and/ or redistribute the software under the terms of the CeCILL-C
-- license as circulated by CEA, CNRS and INRIA at the following URL
-- "http://www.cecill.info".
-- As a counterpart to the access to the source code and rights to copy,
-- modify and redistribute granted by the license, users are provided only
-- with a limited warranty and the software's author, the holder of the
-- economic rights, and the successive licensors have only limited
-- liability.
-- In this respect, the user's attention is drawn to the risks associated
-- with loading, using, modifying and/or developing or reproducing the
-- software by the user in light of its specific status of free software,
-- that may mean that it is complicated to manipulate, and that also
-- therefore means that it is reserved for developers and experienced
-- professionals having in-depth computer knowledge. Users are therefore
-- encouraged to load and test the software's suitability as regards their
-- requirements in conditions enabling the security of their systems and/or
-- data to be ensured and, more generally, to use and operate it in the
-- same conditions as regards security.
-- The fact that you are presently reading this means that you have had
-- knowledge of the CeCILL-C license and that you accept its terms.
-------------------------------------------------------------------------------
-- Doxygen Comments -----------------------------------------------------------
--! @file RGB2GRY.vhd
--
--! @brief Converting RGB values into an 8-bit gray value
--! @author Francois Berry, El Mehdi Abdali, Maxime Pelcat
--! @board SoCKit from Arrow and Terasic
--! @version 1.0
--! @date 16/11/2016
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity RGB2GRY is
port(
clk : in std_logic;
reset : in std_logic;
---------------------------------------
src_CCD_R : in std_logic_vector(11 downto 0); -- Inputing 12-bit RGB
src_CCD_G : in std_logic_vector(11 downto 0);
src_CCD_B : in std_logic_vector(11 downto 0);
oCCD_GRY : out std_logic_vector(7 downto 0) -- Keeping the 8 most significant bits of gray scale
);
end entity RGB2GRY;
architecture arch of RGB2GRY is
begin
process(clk)
variable gray : unsigned(13 downto 0); -- Variable for computing the sum of RGB, dividing by 3 and keeping the 8 MSBs
variable vector_gray : std_logic_vector(13 downto 0) := (others => '0');
begin
if(clk'event and clk = '1') then
-- summing over 14 bitsthe 3 components
gray := unsigned("00" & src_CCD_R)+unsigned("00" & src_CCD_G)+unsigned("00" & src_CCD_B);
-- x*1/3 about = x/4 + x/16 + x/64 + x/256 + x/1024 + x/4096
--gray := (gray/4) + (gray/16) + (gray/64) + (gray/256) + (gray/1024);
gray := ("00" & gray(13 downto 2)) + ("0000" & gray(13 downto 4));-- + ("000000" & gray(13 downto 6)) + ("00000000" & gray(13 downto 8)) + ("0000000000" & gray(13 downto 10));
if(gray > "00111111110000") then
gray := "00111111110000";
end if;
vector_gray := std_logic_vector(gray);
oCCD_GRY <= vector_gray(11 downto 4);
end if;
end process;
end arch;
| gpl-3.0 | a7744f058ae437445acabd6b34f95caa | 0.627214 | 3.707463 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/xilinx/memory/src/dpRam-rtl-a.vhd | 3 | 5,334 | --! @file dpRam-bhv-a.vhd
--
--! @brief Dual Port Ram Register Transfer Level Architecture
--
--! @details This is the DPRAM intended for synthesis on Xilinx Spartan 6 only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
-- Architecture : rtl
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
architecture rtl of dpRam is
--! Width of a byte
constant cByte : natural := 8;
--! Address width (used to generate size depending on address width)
constant cAddrWidth : natural := iAddress_A'length;
--! RAM size
constant cRamSize : natural := 2**cAddrWidth;
--! Type for data port
subtype tDataPort is std_logic_vector(gWordWidth-1 downto 0);
--! RAM type with given size
type tRam is array (cRamSize-1 downto 0) of tDataPort;
--! Shared variable to model and synthesize a DPR
shared variable vDpram : tRam := (others => (others => cInactivated));
--! Port A readport
signal readdataA : tDataPort;
--! Port B readport
signal readdataB : tDataPort;
begin
assert (gInitFile = "UNUSED")
report "Memory initialization is not supported in this architecture!"
severity warning;
-- assign readdata to ports
oReaddata_A <= readdataA;
oReaddata_B <= readdataB;
--! This process describes port A of the DPRAM. The write process considers
--! iWriteEnable_A and iByteenable_A. The read process is done with every
--! rising iClk_A edge.
PORTA : process(iClk_A)
begin
if rising_edge(iClk_A) then
if iEnable_A = cActivated then
for i in iByteenable_A'range loop
if ((iByteenable_A(i) = cActivated) and (iWriteEnable_A = cActivated)) then
-- write byte to DPRAM
vDpram(to_integer(unsigned(iAddress_A)))(
(i+1)*cByte-1 downto i*cByte
) := iWritedata_A(
(i+1)*cByte-1 downto i*cByte
);
end if; --byteenable
end loop;
-- read word from DPRAM
readdataA <= vDpram(to_integer(unsigned(iAddress_A)));
end if; --enable
end if;
end process PORTA;
--! This process describes port B of the DPRAM. The write process considers
--! iWriteEnable_B and iByteenable_B. The read process is done with every
--! rising iClk_B edge.
PORTB : process(iClk_B)
begin
if rising_edge(iClk_B) then
if iEnable_B = cActivated then
for i in iByteenable_B'range loop
if ((iByteenable_B(i) = cActivated) and (iWriteEnable_B = cActivated)) then
-- write byte to DPRAM
vDpram(to_integer(unsigned(iAddress_B)))(
(i+1)*cByte-1 downto i*cByte
) := iWritedata_B(
(i+1)*cByte-1 downto i*cByte
);
end if; --byteenable
end loop;
-- read word from DPRAM
readdataB <= vDpram(to_integer(unsigned(iAddress_B)));
end if; --enable
end if;
end process PORTB;
end architecture rtl;
| gpl-2.0 | a2f6f8784ab6f09221cafaf80bd7ca74 | 0.595051 | 4.77957 | false | false | false | false |
SonicFrog/ArchOrd | findmax.vhdl | 1 | 2,328 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity maxfinder is
port (
startaddr : in std_logic_vector(15 downto 0);
len : in std_logic_vector(15 downto 0);
start : in std_logic;
reset_n : in std_logic;
clk : in std_logic;
rddata : in std_logic_vector(7 downto 0);
rdaddr : out std_logic_vector(15 downto 0);
max : out std_logic_vector(255 downto 0);
done : out std_logic
);
end maxfinder;
architecture synth of findmax is
type state is (S, R, C);
signal current_state, future_state : state;
signal shift_reg : std_logic_vector(255 downto 0);
signal current_max, future_max : std_logic_vector(255 downto 0);
signal address, future_address : std_logic_vector(15 downto 0);
signal current_len, future_len : std_logic_vector(15 downto 0);
begin
rdaddr <= address;
max <= current_max;
sync_state : process(clk)
begin
if reset_n = '0' then
current_state <= S;
shift_reg <= (others => '0');
current_max <= (others => '0');
address <= (others => '0');
elsif rising_edge(clk) then
current_state <= future_state;
current_max <= future_max;
current_len <= future_len;
address <= future_address;
current_max <= future_max;
end if;
end process;
state_proc : process(rddata, len_left)
begin
future_state <= current_state;
future_address <= address;
future_len <= current_len;
future_address <= address;
future_max <= current_max
done <= '0';
case current_state is
when S => -- Waiting for start
if start = '1' then
future_state <= R;
address <= startaddr;
len_left <= len;
end if;
when R => -- Reading the number from memory
shift_reg <= shift_reg(247 downto 8) & rddata(7 downto 0);
if rddata(7) = '1' then
future_state <= C;
else
future_address <= address + 1;
future_len <= len_left - 1;
end if;
when C => -- Done reading doing the comparison
if current_max < shift_reg then
future_max <= shift_reg;
end if;
if current_len = 0 then
future_state <= E;
else
future_state <= R;
end if;
when E => -- Read up until staddr + len
done <= '1';
future_state <= S;
when others =>
future_state <= S
end case;
end process;
end architecture ; -- synth | gpl-2.0 | 97f33c6079a76ed88e7637056a0e61ec | 0.627148 | 2.891925 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/parallelinterface/src/prlMaster-rtl-ea.vhd | 3 | 13,028 | -------------------------------------------------------------------------------
--! @file prlMaster-rtl-ea.vhd
--! @brief Multiplexed memory mapped master
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--! Use standard ieee library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Use numeric std
use ieee.numeric_std.all;
--! Use libcommon library
library libcommon;
--! Use global package
use libcommon.global.all;
entity prlMaster is
generic (
--! Enable multiplexed address/data-bus mode (0 = FALSE)
gEnableMux : natural := 0;
--! Data bus width
gDataWidth : natural := 16;
--! Address bus width
gAddrWidth : natural := 16;
--! Address low
gAddrLow : natural := 0;
--! Ad bus width (valid when gEnableMux /= FALSE)
gAdWidth : natural := 16
);
port (
--! Clock
iClk : in std_logic;
--! Reset
iRst : in std_logic;
-- Memory mapped slave
--! Address
iSlv_address : in std_logic_vector(gAddrWidth-1 downto gAddrLow);
--! Read strobe
iSlv_read : in std_logic;
--! Readdata
oSlv_readdata : out std_logic_vector(gDataWidth-1 downto 0);
--! Write strobe
iSlv_write : in std_logic;
--! Writedata
iSlv_writedata : in std_logic_vector(gDataWidth-1 downto 0);
--! Waitrequest
oSlv_waitrequest : out std_logic;
--! Byteenable
iSlv_byteenable : in std_logic_vector(gDataWidth/8-1 downto 0);
-- Memory mapped multiplexed master
--! Chipselect
oPrlMst_cs : out std_logic;
-- Multiplexed AD-bus
--! Multiplexed address data bus input
iPrlMst_ad_i : in std_logic_vector(gAdWidth-1 downto 0);
--! Multiplexed address data bus output
oPrlMst_ad_o : out std_logic_vector(gAdWidth-1 downto 0);
--! Multiplexed address data bus enable
oPrlMst_ad_oen : out std_logic;
-- Demultiplexed AD-bus
--! Address bus
oPrlMst_addr : out std_logic_vector(gAddrWidth-1 downto 0);
--! Data bus in
iPrlMst_data_i : in std_logic_vector(gDataWidth-1 downto 0);
--! Data bus out
oPrlMst_data_o : out std_logic_vector(gDataWidth-1 downto 0);
--! Data bus outenable
oPrlMst_data_oen : out std_logic;
--! Byteenable
oPrlMst_be : out std_logic_vector(gDataWidth/8-1 downto 0);
--! Address latch enable
oPrlMst_ale : out std_logic;
--! Write strobe
oPrlMst_wr : out std_logic;
--! Read strobe
oPrlMst_rd : out std_logic;
--! Acknowledge
iPrlMst_ack : in std_logic
);
end entity prlMaster;
architecture rtl of prlMaster is
constant cCount_AleDisable : std_logic_vector := "011";
constant cCount_AleExit : std_logic_vector := "101";
constant cCount_max : std_logic_vector := "111";
constant cCountWidth : natural := cCount_max'length;
-- State machine for bus timing
type tFsm is (
sIdle,
sAle,
sWrd,
sHold
);
-- Synchronized ack signal
signal ack : std_logic;
-- Rising edge of ack signal
signal ack_p : std_logic;
--! This record holds all output registers to the bus.
type tReg is record
address : std_logic_vector(gAddrWidth-1 downto 0);
byteenable : std_logic_vector(gDataWidth/8-1 downto 0);
write : std_logic;
read : std_logic;
chipselect : std_logic;
data : std_logic_vector(gDataWidth-1 downto 0);
data_oen : std_logic;
data_in : std_logic_vector(gDataWidth-1 downto 0);
ad : std_logic_vector(gAdWidth-1 downto 0);
ad_oen : std_logic;
ale : std_logic;
fsm : tFsm;
count : std_logic_vector(cCountWidth-1 downto 0);
count_rst : std_logic;
end record;
-- Initialization vector of output registers
constant cRegInit : tReg := (
address => (others => cInactivated),
byteenable => (others => cInactivated),
write => cInactivated,
read => cInactivated,
chipselect => cInactivated,
data => (others => cInactivated),
data_oen => cInactivated,
data_in => (others => cInactivated),
ad => (others => cInactivated),
ad_oen => cInactivated,
ale => cInactivated,
fsm => sIdle,
count => (others => cInactivated),
count_rst => cInactivated
);
-- Register state
signal reg : tReg;
-- Next register state
signal reg_next : tReg;
begin
-- MAP IOs
oSlv_waitrequest <= not ack_p;
oSlv_readdata <= reg.data_in;
oPrlMst_be <= reg.byteenable;
oPrlMst_wr <= reg.write;
oPrlMst_rd <= reg.read;
oPrlMst_cs <= reg.chipselect;
--! Generate mux bus IOs. Demux bus is incactive.
genMux : if gEnableMux /= 0 generate
-- MUX
oPrlMst_ale <= reg.ale;
oPrlMst_ad_o <= reg.ad;
oPrlMst_ad_oen <= reg.ad_oen;
oPrlMst_addr <= (others => cInactivated);
oPrlMst_data_o <= (others => cInactivated);
oPrlMst_data_oen <= cInactivated;
-- iPrlMst_data_i is ignored
end generate genMux;
--! Generate demux bus IOs. Mux bus is incactive.
genDemux : if gEnableMux = 0 generate
-- DEMUX
oPrlMst_addr <= reg.address;
oPrlMst_data_o <= reg.data;
oPrlMst_data_oen <= reg.data_oen;
oPrlMst_ale <= cInactivated;
oPrlMst_ad_o <= (others => cInactivated);
oPrlMst_ad_oen <= cInactivated;
-- iPrlMst_ad_i is ignored
end generate genDemux;
--! This is the clock register process.
regClk : process(iRst, iClk)
begin
if iRst = cActivated then
reg <= cRegInit;
elsif rising_edge(iClk) then
reg <= reg_next;
end if;
end process regClk;
--! This is the next register state process.
combReg : process (
reg, ack,
iSlv_read,
iSlv_write,
iSlv_byteenable,
iSlv_address,
iSlv_writedata,
iPrlMst_ad_i,
iPrlMst_data_i
)
begin
-- default
reg_next <= reg;
-- counter reset active by default
reg_next.count_rst <= cActivated;
if reg.count_rst = cActivated then
reg_next.count <= (others => cInactivated);
else
reg_next.count <= std_logic_vector(unsigned(reg.count) + 1);
end if;
case reg.fsm is
when sIdle =>
reg_next.chipselect <= cInactivated;
reg_next.ale <= cInactivated;
reg_next.ad_oen <= cInactivated;
reg_next.data_oen <= cInactivated;
reg_next.read <= cInactivated;
reg_next.write <= cInactivated;
-- Start transaction if there is either a read or write.
if iSlv_write = cActivated or iSlv_read = cActivated then
reg_next.chipselect <= cActivated;
reg_next.byteenable <= iSlv_byteenable;
if gEnableMux /= 0 then
-- MUX mode
reg_next.fsm <= sAle;
reg_next.ale <= cActivated;
reg_next.ad_oen <= cActivated;
reg_next.ad <= (others => cInactivated);
reg_next.ad(iSlv_address'range) <= iSlv_address;
else
-- DEMUX mode
reg_next.fsm <= sWrd;
reg_next.write <= iSlv_write;
reg_next.read <= iSlv_read;
reg_next.data <= iSlv_writedata;
reg_next.data_oen <= iSlv_write;
reg_next.address <= iSlv_address;
end if;
end if;
when sAle =>
-- Use counter to generate ale timing.
reg_next.count_rst <= cInactivated;
if reg.count = cCount_AleDisable then
reg_next.ale <= cInactivated;
elsif reg.count = cCount_AleExit then
reg_next.count_rst <= cActivated;
reg_next.fsm <= sWrd;
reg_next.write <= iSlv_write;
reg_next.read <= iSlv_read;
reg_next.ad_oen <= iSlv_write;
reg_next.ad <= (others => cInactivated);
reg_next.ad(iSlv_writedata'range) <= iSlv_writedata;
end if;
when sWrd =>
if ack = cActivated then
reg_next.fsm <= sHold;
reg_next.count_rst <= cActivated;
reg_next.chipselect <= cInactivated;
reg_next.read <= cInactivated;
reg_next.write <= cInactivated;
reg_next.ad_oen <= cInactivated;
reg_next.data_oen <= cInactivated;
if reg.read = cActivated then
if gEnableMux /= 0 then
reg_next.data_in <= iPrlMst_ad_i(reg.data_in'range);
else
reg_next.data_in <= iPrlMst_data_i(reg.data_in'range);
end if;
end if;
end if;
when sHold =>
if ack = cInactivated then
reg_next.fsm <= sIdle;
reg_next.count_rst <= cActivated;
end if;
end case;
end process combReg;
--! Synchronizer to sync ack input.
syncAck : entity libcommon.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iRst,
iClk => iClk,
iAsync => iPrlMst_ack,
oSync => ack
);
--! Detect rising edge of ack signal to generate waitrequest neg. pulse.
edgeAck : entity libcommon.edgedetector
port map (
iArst => iRst,
iClk => iClk,
iEnable => cActivated,
iData => ack,
oRising => ack_p,
oFalling => open,
oAny => open
);
end architecture rtl;
| gpl-2.0 | 8557d1b6ea4fa31c39976dcb049403c8 | 0.508981 | 4.649536 | false | false | false | false |
zatslogic/UDI_example | core_project/core_project.srcs/sources_1/ip/mult_16_x_16_res_32/mult_gen_v11_2/simulation/mult_gen_v11_2.vhd | 1 | 20,295 | -- $RCSfile: mult_gen_v11_2.vhd,v $ $Revision: 1.4 $ $Date: 2010/03/19 10:56:59 $
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
library xilinxcorelib;
use xilinxcorelib.bip_utils_pkg_v2_0.all;
use xilinxcorelib.mult_gen_pkg_v11_2.all;
entity mult_gen_v11_2 is
generic (
C_VERBOSITY : integer := 0;
C_MODEL_TYPE : integer := 0;
C_XDEVICEFAMILY : string := "virtex4";
C_A_WIDTH : integer := 18;
C_A_TYPE : integer := 0;
C_B_WIDTH : integer := 18;
C_B_TYPE : integer := 0;
C_OUT_HIGH : integer := 35;
C_OUT_LOW : integer := 0;
C_MULT_TYPE : integer := 1;
C_OPTIMIZE_GOAL : integer := 1;
C_HAS_CE : integer := 0;
C_HAS_SCLR : integer := 0;
C_CE_OVERRIDES_SCLR : integer := 1;
C_LATENCY : integer := -1;
C_CCM_IMP : integer := 0;
C_B_VALUE : string := "111111111111111111";
C_HAS_ZERO_DETECT : integer := 0;
C_ROUND_OUTPUT : integer := 0;
C_ROUND_PT : integer := 0);
port (
CLK : in std_logic := '1';
A : in std_logic_vector(C_A_WIDTH-1 downto 0) := (others => '0');
B : in std_logic_vector(C_B_WIDTH-1 downto 0) := (others => '0');
CE : in std_logic := '1';
SCLR : in std_logic := '0';
ZERO_DETECT : out std_logic_vector(1 downto 0) := (others => '0');
P : out std_logic_vector(C_OUT_HIGH-C_OUT_LOW downto 0) := (others => '0');
PCASC : out std_logic_vector(47 downto 0) := (others => '0'));
end mult_gen_v11_2;
architecture behavioral of mult_gen_v11_2 is
constant validated_generics : T_RESOLVED_GENERICS := check_generics(
C_XDEVICEFAMILY,
C_A_WIDTH,
C_A_TYPE,
C_B_WIDTH,
C_B_TYPE,
C_OUT_HIGH,
C_OUT_LOW,
C_MULT_TYPE,
C_OPTIMIZE_GOAL,
C_HAS_CE,
C_HAS_SCLR,
C_CE_OVERRIDES_SCLR,
C_LATENCY,
C_CCM_IMP,
C_B_VALUE,
C_HAS_ZERO_DETECT,
C_ROUND_OUTPUT,
C_ROUND_PT);
-- Resolved generics, after they have passed through check_generics
constant R_A_WIDTH : integer := validated_generics.R_A_WIDTH;
constant R_A_TYPE : integer := validated_generics.R_A_TYPE;
constant R_B_WIDTH : integer := validated_generics.R_B_WIDTH;
constant R_B_TYPE : integer := validated_generics.R_B_TYPE;
constant R_OUT_HIGH : integer := validated_generics.R_OUT_HIGH;
constant R_OUT_LOW : integer := validated_generics.R_OUT_LOW;
constant R_MULT_TYPE : integer := validated_generics.R_MULT_TYPE;
constant R_OPT_GOAL : integer := validated_generics.R_OPT_GOAL;
constant R_HAS_CE : integer := validated_generics.R_HAS_CE;
constant R_HAS_SCLR : integer := validated_generics.R_HAS_SCLR;
constant R_CE_OVERRIDES_SCLR : integer := validated_generics.R_CE_OVERRIDES_SCLR;
constant R_LATENCY : integer := validated_generics.R_LATENCY;
constant R_CCM_IMP : integer := validated_generics.R_CCM_IMP;
constant R_B_VALUE : string(1 to R_B_WIDTH) := validated_generics.R_B_VALUE(1 to R_B_WIDTH);
constant R_HAS_ZERO_DETECT : integer := validated_generics.R_HAS_ZERO_DETECT;
constant R_ROUND_OUTPUT : integer := validated_generics.R_ROUND_OUTPUT;
constant R_ROUND_PT : integer := validated_generics.R_ROUND_PT;
type T_PIPE is array (0 to MAX_PIPE_STAGES-1) of integer range 0 to 1;
function get_pipeline_depth(pipe_delay : integer) return integer is
variable accum : integer := 0;
variable int_value : integer := 0;
variable pipe_array : T_PIPE := (others => 0);
begin
if pipe_delay >= PIPELINE_CFG_BREAKPT then
-- custom pipeline CONFIGURATION
-- subract the breakpoint value
int_value := pipe_delay-PIPELINE_CFG_BREAKPT;
-- convert the resulting integer value to a binary representation
for x in 0 to MAX_PIPE_STAGES-1 loop -- max_reg
pipe_array(x) := sl_to_int(int_to_slv(int_value, MAX_PIPE_STAGES)(x));
end loop; -- x
-- accumulate all the bits in the resulting 'binary' integer array to get pipeline latency
for i in 0 to binary_width_of_integer(int_value)-1 loop
accum := accum + pipe_array(i);
end loop; -- i
-- ASSERT false REPORT "returned a custom pipeline delay of " & INTEGER'image(accum) SEVERITY note;
return accum;
else
-- use c_latency directly
-- ASSERT false REPORT "returned a simple delay of " & INTEGER'image(pipe_delay) SEVERITY note;
return pipe_delay;
end if;
end function get_pipeline_depth;
constant max_a_width : integer := 64;
constant max_b_width : integer := 64;
signal ai : std_logic_vector(R_A_WIDTH downto 0) := (others => '0');
signal bi : std_logic_vector(R_B_WIDTH downto 0) := (others => '0');
signal ce_i : std_logic := '1';
signal sclr_i : std_logic := '0';
signal pm : std_logic_vector(127 downto 0) := (others => '0');
signal pm_round : std_logic_vector(pm'range) := (others => '0');
signal pi : std_logic_vector(pm'range) := (others => '0');
signal zero_detect_i : std_logic_vector(1 downto 0) := (others => '0');
constant pipeline_latency : integer := get_pipeline_depth(R_LATENCY);
-- purpose: configures the rounding constant when symmetric rounding is to be implemented
function get_rounding_const(round_output, round_pt : integer) return std_logic_vector is
variable ret : std_logic_vector(47 downto 0) := (others => '0');
begin -- FUNCTION get
if round_pt /= 0 then
-- no point in trying to round if we have the full output width!
for i in ret'low to ret'high loop
if i = round_pt-1 then
exit;
end if;
ret(i) := '1';
end loop; -- i
end if;
return ret;
end function get_rounding_const;
constant round_const : std_logic_vector(47 downto 0) := get_rounding_const(R_ROUND_OUTPUT, R_ROUND_PT);
-- pipelined versions of the multiplier's input MSBs to allow correct rounding
signal ai_round : std_logic := '0';
signal bi_round : std_logic := '0';
-- purpose: checks if the supplied constant is exactly a power of two, assuming that the constant is unsigned
function check_const_power_two (const : string; const_type : integer) return boolean is
variable leading_zeros : integer := 0;
variable trailing_zeros : integer := 0;
constant const_len : integer := const'length;
variable sum : integer := 0;
begin -- FUNCTION check_const_power_two
if const_type = C_UNSIGNED then
-- count leading zeros
-- account for TO and DOWNTO strings
if const'ascending then
for i in const'left to const'right loop
if const(i) = '0' then
leading_zeros := leading_zeros + 1;
end if;
if const(i) = '1' then
exit;
end if;
end loop; -- i
else -- const'descending
for i in const'left downto const'right loop
if const(i) = '0' then
leading_zeros := leading_zeros + 1;
end if;
if const(i) = '1' then
exit;
end if;
end loop; -- i
end if;
-- count trailing zeros
-- account for TO and DOWNTO strings
if const'ascending then
for i in const'right downto const'left loop
if const(i) = '0' then
trailing_zeros := trailing_zeros + 1;
end if;
if const(i) = '1' then
exit;
end if;
end loop; -- i
else -- const'descending
for i in const'right to const'left loop
if const(i) = '0' then
trailing_zeros := trailing_zeros + 1;
end if;
if const(i) = '1' then
exit;
end if;
end loop; -- i
end if;
-- add the trailing and leading zero counts - if const_len - (sum) == 1
-- then the constant is exactly a power of two
sum := leading_zeros + trailing_zeros;
if (const_len - sum) = 1 then
return true;
else
return false;
end if;
else -- signed data
return false;
end if;
end function check_const_power_two;
begin
parallel_multiplier : if R_MULT_TYPE = LUT or R_MULT_TYPE = EMBEDDED_MULT or R_MULT_TYPE = FIXED_CCM generate
-- we need a separate SCLR signal for the BRAM implementations of the CCM
-- since the address registers on the BRAMs don't have an SCLR - only the
-- output and fabric speed-up registers do
signal bram_addr_sclr : std_logic := '0';
begin
-- some extra generates to aid ModelSim debugging
is_fixed_ccm : if R_MULT_TYPE = FIXED_CCM generate
-- do nothing
end generate is_fixed_ccm;
is_parallel_mult : if R_MULT_TYPE = LUT or R_MULT_TYPE = EMBEDDED_MULT generate
-- do nothing
end generate is_parallel_mult;
-- adjust operands for signed/unsigned
a_signed : if R_A_TYPE = C_SIGNED generate
ai <= a(a'high) & a;
end generate a_signed;
a_unsigned : if R_A_TYPE = C_UNSIGNED generate
ai <= "0" & a;
end generate a_unsigned;
b_signed : if R_B_TYPE = C_SIGNED generate
bi <= b(b'high) & b;
end generate b_signed;
b_unsigned : if R_B_TYPE = C_UNSIGNED generate
bi <= "0" & b;
end generate b_unsigned;
-- sort out CE and SCLR
has_ce : if R_HAS_CE /= 0 generate
ce_i <= ce;
end generate has_ce;
no_ce : if R_HAS_CE = 0 generate
ce_i <= '1';
end generate no_ce;
has_sclr : if R_HAS_SCLR /= 0 generate
ce_overrides_sclr : if R_CE_OVERRIDES_SCLR /= 0 generate
sclr_i <= sclr and ce_i;
end generate ce_overrides_sclr;
sclr_overrides_ce : if R_CE_OVERRIDES_SCLR = 0 generate
sclr_i <= sclr;
end generate sclr_overrides_ce;
end generate has_sclr;
no_sclr : if R_HAS_SCLR = 0 generate
sclr_i <= '0';
end generate no_sclr;
parm : if R_MULT_TYPE = LUT or R_MULT_TYPE = EMBEDDED_MULT generate
-- do the multiply and expand the product to the full allowed width
signed_multiply : if R_A_TYPE = C_SIGNED or R_B_TYPE = C_SIGNED generate
pm <= std_logic_vector(RESIZE(signed(ieee.std_logic_signed."*"(ai, bi)), MAX_PRODUCT_WIDTH));
end generate signed_multiply;
unsigned_multiply : if not(R_A_TYPE = C_SIGNED or R_B_TYPE = C_SIGNED) generate
pm <= std_logic_vector(RESIZE(unsigned(ieee.std_logic_unsigned."*"(ai, bi)), MAX_PRODUCT_WIDTH));
end generate unsigned_multiply;
end generate parm;
ccm : if R_MULT_TYPE = FIXED_CCM generate
signal b_value_ext : std_logic_vector(R_B_VALUE'length downto 0) := (others => '0');
begin
-- manually sign- (or zero-) extend the B constant value
us_b_value_ext : if R_B_TYPE = C_UNSIGNED generate
b_value_ext <= std_logic_vector(resize(unsigned(str_to_slv(R_B_VALUE)), b_value_ext'length));
end generate us_b_value_ext;
s_b_value_ext : if R_B_TYPE = C_SIGNED generate
b_value_ext <= std_logic_vector(resize(signed(str_to_slv(R_B_VALUE)), b_value_ext'length));
end generate s_b_value_ext;
-- do the multiply and expand the product to the full allowed width
signed_multiply : if R_A_TYPE = C_SIGNED or R_B_TYPE = C_SIGNED generate
pm <= std_logic_vector(RESIZE(signed(ieee.std_logic_signed."*"(ai, b_value_ext)), MAX_PRODUCT_WIDTH));
end generate signed_multiply;
unsigned_multiply : if not(R_A_TYPE = C_SIGNED or R_B_TYPE = C_SIGNED) generate
pm <= std_logic_vector(RESIZE(unsigned(ieee.std_logic_unsigned."*"(ai, b_value_ext)), MAX_PRODUCT_WIDTH));
end generate unsigned_multiply;
end generate ccm;
-- implement any required symmetric rounding on the output
do_round : if R_ROUND_OUTPUT /= 0 and R_ROUND_PT > 0 generate
pm_round <= not(ai(ai'high) xor bi(bi'high)) + round_const + pm;
end generate do_round;
no_round : if R_ROUND_OUTPUT = 0 or R_ROUND_PT = 0 generate
pm_round <= pm;
end generate no_round;
-- configure the SCLR for the BRAM CCM, if applicable
-- Need an additional check for if the constant is exactly +one because we
-- only need a delay line to model that and it doesn't need a separate SCLR
is_bram_ccm : if R_MULT_TYPE = FIXED_CCM and R_CCM_IMP = BRAM and not(check_const_power_two(R_B_VALUE, R_B_TYPE)) generate
bram_addr_sclr <= '0';
end generate is_bram_ccm;
not_bram_ccm : if not(R_MULT_TYPE = FIXED_CCM and R_CCM_IMP = BRAM and not(check_const_power_two(R_B_VALUE, R_B_TYPE))) generate
bram_addr_sclr <= sclr_i;
end generate not_bram_ccm;
-- implement the pipelining as a delay line
pipe0 : if pipeline_latency = 0 generate
pi <= pm_round;
end generate pipe0;
pipe1 : if pipeline_latency = 1 generate
process (clk) is
begin
if rising_edge(clk) then
if bram_addr_sclr = '1' then
pi <= (others => '0');
else
if ce_i = '1' then
pi <= pm_round;
end if;
end if;
end if;
end process;
end generate pipe1;
pipe2 : if pipeline_latency = 2 generate
signal ff : std_logic_vector(pi'range) := (others => '0');
begin
-- create single-cycle delay with separate SCLR
process (clk) is
begin
if rising_edge(clk) then
if bram_addr_sclr = '1' then
ff <= (others => '0');
else
if ce_i = '1' then
ff <= pm_round;
end if;
end if;
end if;
end process;
-- create another single-cycle delay with global SCLR
process (clk) is
begin
if rising_edge(clk) then
if sclr_i = '1' then
pi <= (others => '0');
else
if ce_i = '1' then
pi <= ff;
end if;
end if;
end if;
end process;
end generate pipe2;
pipeX : if pipeline_latency > 2 generate
type T_DELAY is array (0 to pipeline_latency-2) of std_logic_vector(pi'range);
signal delay_line : T_DELAY := (others => (others => '0'));
signal ff : std_logic_vector(pi'range) := (others => '0');
begin
-- create single-cycle delay with separate SCLR
process (clk) is
begin
if rising_edge(clk) then
if bram_addr_sclr = '1' then
ff <= (others => '0');
else
if ce_i = '1' then
ff <= pm_round;
end if;
end if;
end if;
end process;
-- create delay LINE
process (clk) is
begin
if rising_edge(clk) then
if sclr_i = '1' then
delay_line <= (others => (others => '0'));
else
if ce_i = '1' then
delay_line <= ff & delay_line(0 to pipeline_latency-3);
end if;
end if;
end if;
end process;
pi <= delay_line(pipeline_latency-2);
end generate pipeX;
-- pick out the requested slice of the full-width product
-- p <= pi(R_OUT_HIGH downto R_OUT_LOW);
-- Using the full MAX_PRODUCT_WIDTH product doesn't work for cases where
-- symmetric rounding has been used and the product is extended above the MSB.
-- We need to pull out the true full product (sum of input widths) and then
-- (un)sign-extend that back up to the 128 bits, then pull out the bits
-- that the user wants. Phew!
assign_outputs : if true generate
-- the maximum output product width
signal max_product : std_logic_vector(MAX_PRODUCT_WIDTH-1 downto 0) := (others => '0');
begin
-- extend the result to the full allowable output width
usign : if R_A_TYPE /= C_SIGNED and R_B_TYPE /= C_SIGNED generate
max_product <= std_logic_vector(RESIZE(unsigned(pi(R_A_WIDTH+R_B_WIDTH-1 downto 0)), MAX_PRODUCT_WIDTH));
end generate usign;
sign : if R_A_TYPE = C_SIGNED or R_B_TYPE = C_SIGNED generate
max_product <= std_logic_vector(RESIZE(signed(pi(R_A_WIDTH+R_B_WIDTH-1 downto 0)), MAX_PRODUCT_WIDTH));
end generate sign;
-- if output requested is shorter than full output product, just pick out that slice
P <= max_product(R_OUT_HIGH downto R_OUT_LOW);
end generate assign_outputs;
has_zero_detect : if R_HAS_ZERO_DETECT /= 0 and R_MULT_TYPE /= FIXED_CCM generate
constant zeros : std_logic_vector(R_A_WIDTH-3 downto 0) := (others => '0');
begin
-- rather than performing bit-true modelling, we just duplicate the
-- output for all parallel multipliers
-- NOTE THAT THE *AND* OF THESE TWO SIGNALS IS CHECKED IN THE TESTBENCH
-- AND THIS MODEL WILL NOT MATCH ALL MULTIPLIER VARIANTS EXACTLY
-- THE ASSUMPTION IS THAT THE FPO CORE (WHICH IS THE ONLY USER OF THIS
-- FEATURE) WILL ALWAYS *AND* THE TWO OUTPUTS IN SOME EXTERNAL LOGIC
zero_detect(0) <= '1' when pi(R_A_WIDTH-3 downto 0) = zeros else '0';
zero_detect(1) <= '1' when pi(R_A_WIDTH-3 downto 0) = zeros else '0';
end generate has_zero_detect;
end generate parallel_multiplier;
end architecture behavioral;
| gpl-3.0 | 9c59c6816eaf0e09dc3b2806efce3bf1 | 0.595664 | 3.739635 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/UDP/UDP_Complete_nomac.vhd | 1 | 12,928 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:38:49 06/13/2011
-- Design Name:
-- Module Name: UDP_Complete_nomac - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - separated RX and TX clocks
-- Revision 0.03 - Added mac_tx_tfirst
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity UDP_Complete_nomac is
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- UDP TX signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data
-- UDP RX signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- IP RX signals
ip_rx_hdr : out ipv4_rx_header_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in udp_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tfirst : in std_logic;
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
end UDP_Complete_nomac;
architecture structural of UDP_Complete_nomac is
------------------------------------------------------------------------------
-- Component Declaration for TX_ARBITRATOR
------------------------------------------------------------------------------
component tx_arbitrator_over_ip
port(
clk : in std_logic;
reset : in std_logic;
req_1 : in std_logic;
grant_1 : out std_logic;
data_1 : in ipv4_tx_type; -- data byte to tx
req_2 : in std_logic;
grant_2 : out std_logic;
data_2 : in ipv4_tx_type; -- data byte to tx
data : out ipv4_tx_type -- data byte to tx
);
end component;
------------------------------------------------------------------------------
-- Component Declaration for ICMP
------------------------------------------------------------------------------
COMPONENT icmp
PORT(
ip_rx_start : in std_logic; -- indicates receipt of ip frame.
ip_rx : in ipv4_rx_type;
ip_tx_start : out std_logic;
ip_tx_data_out_rdy : in std_logic;
ip_tx_result : in std_logic_vector(1 downto 0);
icmp_tx : out ipv4_tx_type;
icmp_rx_count : out std_logic_vector(15 downto 0);
icmp_tx_count : out std_logic_vector(15 downto 0);
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic;
req_ip_layer : out std_logic;
granted_ip_layer : in std_logic
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for UDP TX
------------------------------------------------------------------------------
COMPONENT UDP_TX
PORT(
-- UDP Layer signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
-- IP layer TX signals
ip_tx_start : out std_logic;
ip_tx : out ipv4_tx_type; -- IP tx cxns
ip_tx_result : in std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : in std_logic; -- indicates IP TX is ready to take data
--arbit
req_ip_layer : out std_logic;
granted_ip_layer : in std_logic
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for UDP RX
------------------------------------------------------------------------------
COMPONENT UDP_RX
PORT(
-- UDP Layer signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- system signals
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- IP layer RX signals
ip_rx_start : in std_logic; -- indicates receipt of ip header
ip_rx : in ipv4_rx_type
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for the IP layer
------------------------------------------------------------------------------
component IP_complete_nomac
generic (
use_arpv2 : boolean := true;
no_default_gateway: boolean := true;
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in ip_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tfirst : in std_logic;
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
end component;
-- IP TX connectivity
signal ip_tx_int : ipv4_tx_type;
signal ip_tx_start_int : std_logic;
signal ip_tx_result_int : std_logic_vector (1 downto 0);
signal ip_tx_data_out_ready_int : std_logic;
-- IP RX connectivity
signal ip_rx_int : ipv4_rx_type;
signal ip_rx_start_int : std_logic := '0';
signal ip_1_tx_start_int, ip_2_tx_start_int : std_logic;
signal data_arbit_int, data_icmp_tx_int, data_udp_tx_int : ipv4_tx_type;
signal req_1_int, grant_1_int, req_2_int, grant_2_int : std_logic;
signal icmp_rx_count_int, icmp_tx_count_int : std_logic_vector(15 downto 0);
begin
-- ip_tx_int.data.data_out_valid <= data_arbit_int.data.data_out_valid;
-- ip_tx_int.data.data_out_last <= data_arbit_int.data.data_out_last;
-- ip_tx_int.data.data_out <= data_arbit_int.data.data_out;
ip_tx_int <= data_arbit_int;
ip_tx_start_int <= ip_1_tx_start_int when grant_1_int = '1' else ip_2_tx_start_int;
tx_arbitrator_over_ip_block : tx_arbitrator_over_ip
PORT MAP(
clk => tx_clk,
reset => reset,
req_1 => req_1_int,
grant_1 => grant_1_int,
data_1 => data_udp_tx_int, -- data byte to tx from UDP
req_2 => req_2_int,
grant_2 => grant_2_int,
data_2 => data_icmp_tx_int, -- data byte to tx from ICMP
data => data_arbit_int
);
icmp_block : icmp
PORT MAP(
ip_rx_start => ip_rx_start_int,
ip_rx => ip_rx_int,
-- IP layer TX signals
ip_tx_start => ip_2_tx_start_int,
ip_tx_data_out_rdy => ip_tx_data_out_ready_int,
ip_tx_result => ip_tx_result_int,
-- ICMP layer TX signals
icmp_tx => data_icmp_tx_int,
icmp_rx_count => icmp_rx_count_int,
icmp_tx_count => icmp_tx_count_int,
rx_clk => rx_clk,
tx_clk => tx_clk,
reset => reset,
req_ip_layer => req_2_int,
granted_ip_layer => grant_2_int
);
-- output followers
ip_rx_hdr <= ip_rx_int.hdr;
-- Instantiate the UDP TX block
udp_tx_block: UDP_TX
PORT MAP (
-- UDP Layer signals
udp_tx_start => udp_tx_start,
udp_txi => udp_txi,
udp_tx_result => udp_tx_result,
udp_tx_data_out_ready=> udp_tx_data_out_ready,
-- system signals
clk => tx_clk,
reset => reset,
-- IP layer TX signals
ip_tx_start => ip_1_tx_start_int,
ip_tx => data_udp_tx_int,--ip_tx_int,
ip_tx_result => ip_tx_result_int,
ip_tx_data_out_ready => ip_tx_data_out_ready_int,
req_ip_layer => req_1_int,
granted_ip_layer => grant_1_int
);
-- Instantiate the UDP RX block
udp_rx_block: UDP_RX PORT MAP (
-- UDP Layer signals
udp_rxo => udp_rxo,
udp_rx_start => udp_rx_start,
-- system signals
clk => rx_clk,
reset => reset,
-- IP layer RX signals
ip_rx_start => ip_rx_start_int,
ip_rx => ip_rx_int
);
------------------------------------------------------------------------------
-- Instantiate the IP layer
------------------------------------------------------------------------------
IP_block : IP_complete_nomac
generic map (
use_arpv2 => false,
no_default_gateway => false,--
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO,
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
PORT MAP (
-- IP interface
ip_tx_start => ip_tx_start_int,
ip_tx => ip_tx_int,
ip_tx_result => ip_tx_result_int,
ip_tx_data_out_ready => ip_tx_data_out_ready_int,
ip_rx_start => ip_rx_start_int,
ip_rx => ip_rx_int,
-- System interface
rx_clk => rx_clk,
tx_clk => tx_clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
control => control.ip_controls,
-- status signals
arp_pkt_count => arp_pkt_count,
ip_pkt_count => ip_pkt_count,
-- MAC Transmitter
mac_tx_tdata => mac_tx_tdata,
mac_tx_tvalid => mac_tx_tvalid,
mac_tx_tready => mac_tx_tready,
mac_tx_tfirst => mac_tx_tfirst,
mac_tx_tlast => mac_tx_tlast,
-- MAC Receiver
mac_rx_tdata => mac_rx_tdata,
mac_rx_tvalid => mac_rx_tvalid,
mac_rx_tready => mac_rx_tready,
mac_rx_tfirst => mac_rx_tfirst,
mac_rx_tlast => mac_rx_tlast
);
end structural;
| gpl-3.0 | b93e4757bd84f756054391b7e34ae8f3 | 0.533803 | 3.132542 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_CPU.vhd | 1 | 324,011 | --Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.all;
entity Video_System_CPU_register_bank_a_module is
generic (
lpm_file : STRING := "UNUSED"
);
port (
-- inputs:
signal clock : IN STD_LOGIC;
signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rdaddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal wraddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal wren : IN STD_LOGIC;
-- outputs:
signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity Video_System_CPU_register_bank_a_module;
architecture europa of Video_System_CPU_register_bank_a_module is
component altsyncram is
GENERIC (
address_reg_b : STRING;
init_file : STRING;
maximum_depth : NATURAL;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_reg_b : STRING;
ram_block_type : STRING;
rdcontrol_reg_b : STRING;
read_during_write_mode_mixed_ports : STRING;
width_a : NATURAL;
width_b : NATURAL;
widthad_a : NATURAL;
widthad_b : NATURAL
);
PORT (
signal q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal wren_a : IN STD_LOGIC;
signal clock0 : IN STD_LOGIC;
signal address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal address_b : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component altsyncram;
signal ram_q : STD_LOGIC_VECTOR (31 DOWNTO 0);
begin
q <= ram_q;
the_altsyncram : altsyncram
generic map(
address_reg_b => "CLOCK0",
init_file => lpm_file,
maximum_depth => 0,
numwords_a => 32,
numwords_b => 32,
operation_mode => "DUAL_PORT",
outdata_reg_b => "UNREGISTERED",
ram_block_type => "AUTO",
rdcontrol_reg_b => "CLOCK0",
read_during_write_mode_mixed_ports => "DONT_CARE",
width_a => 32,
width_b => 32,
widthad_a => 5,
widthad_b => 5
)
port map(
address_a => wraddress,
address_b => rdaddress,
clock0 => clock,
data_a => data,
q_b => ram_q,
wren_a => wren
);
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.all;
entity Video_System_CPU_register_bank_b_module is
generic (
lpm_file : STRING := "UNUSED"
);
port (
-- inputs:
signal clock : IN STD_LOGIC;
signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rdaddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal wraddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal wren : IN STD_LOGIC;
-- outputs:
signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity Video_System_CPU_register_bank_b_module;
architecture europa of Video_System_CPU_register_bank_b_module is
component altsyncram is
GENERIC (
address_reg_b : STRING;
init_file : STRING;
maximum_depth : NATURAL;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_reg_b : STRING;
ram_block_type : STRING;
rdcontrol_reg_b : STRING;
read_during_write_mode_mixed_ports : STRING;
width_a : NATURAL;
width_b : NATURAL;
widthad_a : NATURAL;
widthad_b : NATURAL
);
PORT (
signal q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal wren_a : IN STD_LOGIC;
signal clock0 : IN STD_LOGIC;
signal address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal address_b : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component altsyncram;
signal ram_q : STD_LOGIC_VECTOR (31 DOWNTO 0);
begin
q <= ram_q;
the_altsyncram : altsyncram
generic map(
address_reg_b => "CLOCK0",
init_file => lpm_file,
maximum_depth => 0,
numwords_a => 32,
numwords_b => 32,
operation_mode => "DUAL_PORT",
outdata_reg_b => "UNREGISTERED",
ram_block_type => "AUTO",
rdcontrol_reg_b => "CLOCK0",
read_during_write_mode_mixed_ports => "DONT_CARE",
width_a => 32,
width_b => 32,
widthad_a => 5,
widthad_b => 5
)
port map(
address_a => wraddress,
address_b => rdaddress,
clock0 => clock,
data_a => data,
q_b => ram_q,
wren_a => wren
);
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_debug is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dbrk_break : IN STD_LOGIC;
signal debugreq : IN STD_LOGIC;
signal hbreak_enabled : IN STD_LOGIC;
signal jdo : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal ocireg_ers : IN STD_LOGIC;
signal ocireg_mrs : IN STD_LOGIC;
signal reset : IN STD_LOGIC;
signal st_ready_test_idle : IN STD_LOGIC;
signal take_action_ocimem_a : IN STD_LOGIC;
signal take_action_ocireg : IN STD_LOGIC;
signal xbrk_break : IN STD_LOGIC;
-- outputs:
signal debugack : OUT STD_LOGIC;
signal monitor_error : OUT STD_LOGIC;
signal monitor_go : OUT STD_LOGIC;
signal monitor_ready : OUT STD_LOGIC;
signal oci_hbreak_req : OUT STD_LOGIC;
signal resetlatch : OUT STD_LOGIC;
signal resetrequest : OUT STD_LOGIC
);
end entity Video_System_CPU_nios2_oci_debug;
architecture europa of Video_System_CPU_nios2_oci_debug is
signal internal_debugack : STD_LOGIC;
signal internal_resetlatch : STD_LOGIC;
signal jtag_break : STD_LOGIC;
signal probepresent : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of jtag_break : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
attribute ALTERA_ATTRIBUTE of monitor_error : signal is "SUPPRESS_DA_RULE_INTERNAL=D101";
attribute ALTERA_ATTRIBUTE of monitor_go : signal is "SUPPRESS_DA_RULE_INTERNAL=D101";
attribute ALTERA_ATTRIBUTE of monitor_ready : signal is "SUPPRESS_DA_RULE_INTERNAL=D101";
attribute ALTERA_ATTRIBUTE of probepresent : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
attribute ALTERA_ATTRIBUTE of resetlatch : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
attribute ALTERA_ATTRIBUTE of resetrequest : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
begin
process (clk, jrst_n)
begin
if jrst_n = '0' then
probepresent <= std_logic'('0');
resetrequest <= std_logic'('0');
jtag_break <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(take_action_ocimem_a) = '1' then
resetrequest <= jdo(22);
jtag_break <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(jdo(21)) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector((std_logic'(jdo(20)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(jtag_break))))));
probepresent <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(jdo(19)) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector((std_logic'(jdo(18)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(probepresent))))));
internal_resetlatch <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(jdo(24)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(internal_resetlatch)))));
elsif std_logic'(reset) = '1' then
jtag_break <= probepresent;
internal_resetlatch <= std_logic'('1');
elsif std_logic'(((NOT internal_debugack AND debugreq) AND probepresent)) = '1' then
jtag_break <= std_logic'('1');
end if;
end if;
end process;
process (clk, jrst_n)
begin
if jrst_n = '0' then
monitor_ready <= std_logic'('0');
monitor_error <= std_logic'('0');
monitor_go <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((take_action_ocimem_a AND jdo(25))) = '1' then
monitor_ready <= std_logic'('0');
elsif std_logic'((take_action_ocireg AND ocireg_mrs)) = '1' then
monitor_ready <= std_logic'('1');
end if;
if std_logic'((take_action_ocimem_a AND jdo(25))) = '1' then
monitor_error <= std_logic'('0');
elsif std_logic'((take_action_ocireg AND ocireg_ers)) = '1' then
monitor_error <= std_logic'('1');
end if;
if std_logic'((take_action_ocimem_a AND jdo(23))) = '1' then
monitor_go <= std_logic'('1');
elsif std_logic'(st_ready_test_idle) = '1' then
monitor_go <= std_logic'('0');
end if;
end if;
end process;
oci_hbreak_req <= ((jtag_break OR dbrk_break) OR xbrk_break) OR debugreq;
internal_debugack <= NOT hbreak_enabled;
--vhdl renameroo for output signals
debugack <= internal_debugack;
--vhdl renameroo for output signals
resetlatch <= internal_resetlatch;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.all;
entity Video_System_CPU_ociram_lpm_dram_bdp_component_module is
generic (
lpm_file : STRING := "UNUSED"
);
port (
-- inputs:
signal address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal clock0 : IN STD_LOGIC;
signal clock1 : IN STD_LOGIC;
signal clocken0 : IN STD_LOGIC;
signal clocken1 : IN STD_LOGIC;
signal data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal wren_a : IN STD_LOGIC;
signal wren_b : IN STD_LOGIC;
-- outputs:
signal q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity Video_System_CPU_ociram_lpm_dram_bdp_component_module;
architecture europa of Video_System_CPU_ociram_lpm_dram_bdp_component_module is
component altsyncram is
GENERIC (
address_aclr_a : STRING;
address_aclr_b : STRING;
address_reg_b : STRING;
indata_aclr_a : STRING;
indata_aclr_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
ram_block_type : STRING;
read_during_write_mode_mixed_ports : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
widthad_a : NATURAL;
widthad_b : NATURAL;
wrcontrol_aclr_a : STRING;
wrcontrol_aclr_b : STRING
);
PORT (
signal q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal wren_a : IN STD_LOGIC;
signal data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal clock0 : IN STD_LOGIC;
signal clocken0 : IN STD_LOGIC;
signal byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal clocken1 : IN STD_LOGIC;
signal wren_b : IN STD_LOGIC;
signal clock1 : IN STD_LOGIC;
signal address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component altsyncram;
signal internal_q_a : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_q_b : STD_LOGIC_VECTOR (31 DOWNTO 0);
begin
the_altsyncram : altsyncram
generic map(
address_aclr_a => "NONE",
address_aclr_b => "NONE",
address_reg_b => "CLOCK1",
indata_aclr_a => "NONE",
indata_aclr_b => "NONE",
init_file => lpm_file,
intended_device_family => "CYCLONEII",
lpm_type => "altsyncram",
numwords_a => 256,
numwords_b => 256,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
ram_block_type => "AUTO",
read_during_write_mode_mixed_ports => "OLD_DATA",
width_a => 32,
width_b => 32,
width_byteena_a => 4,
widthad_a => 8,
widthad_b => 8,
wrcontrol_aclr_a => "NONE",
wrcontrol_aclr_b => "NONE"
)
port map(
address_a => address_a,
address_b => address_b,
byteena_a => byteena_a,
clock0 => clock0,
clock1 => clock1,
clocken0 => clocken0,
clocken1 => clocken1,
data_a => data_a,
data_b => data_b,
q_a => internal_q_a,
q_b => internal_q_b,
wren_a => wren_a,
wren_b => wren_b
);
--vhdl renameroo for output signals
q_a <= internal_q_a;
--vhdl renameroo for output signals
q_b <= internal_q_b;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_ocimem is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
signal begintransfer : IN STD_LOGIC;
signal byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal chipselect : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal debugaccess : IN STD_LOGIC;
signal jdo : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal resetrequest : IN STD_LOGIC;
signal take_action_ocimem_a : IN STD_LOGIC;
signal take_action_ocimem_b : IN STD_LOGIC;
signal take_no_action_ocimem_a : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal MonDReg : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oci_ram_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity Video_System_CPU_nios2_ocimem;
architecture europa of Video_System_CPU_nios2_ocimem is
component Video_System_CPU_ociram_lpm_dram_bdp_component_module is
generic (
lpm_file : STRING := "UNUSED"
);
port (
-- inputs:
signal address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal clock0 : IN STD_LOGIC;
signal clock1 : IN STD_LOGIC;
signal clocken0 : IN STD_LOGIC;
signal clocken1 : IN STD_LOGIC;
signal data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal wren_a : IN STD_LOGIC;
signal wren_b : IN STD_LOGIC;
-- outputs:
signal q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component Video_System_CPU_ociram_lpm_dram_bdp_component_module;
signal MonAReg : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal MonRd : STD_LOGIC;
signal MonRd1 : STD_LOGIC;
signal MonWr : STD_LOGIC;
signal avalon : STD_LOGIC;
signal cfgdout : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_MonDReg : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_oci_ram_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal module_input : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal module_input1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal module_input2 : STD_LOGIC;
signal module_input3 : STD_LOGIC;
signal module_input4 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal module_input5 : STD_LOGIC;
signal sramdout : STD_LOGIC_VECTOR (31 DOWNTO 0);
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of MonDReg, MonAReg, MonRd1, MonRd, MonWr : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103,R101""";
--synthesis translate_off
constant Video_System_CPU_ociram_lpm_dram_bdp_component_lpm_file : string := "Video_System_CPU_ociram_default_contents.hex";
--synthesis translate_on
--synthesis read_comments_as_HDL on
--constant Video_System_CPU_ociram_lpm_dram_bdp_component_lpm_file : string := "Video_System_CPU_ociram_default_contents.mif";
--synthesis read_comments_as_HDL off
begin
avalon <= begintransfer AND NOT resetrequest;
process (clk, jrst_n)
begin
if jrst_n = '0' then
MonWr <= std_logic'('0');
MonRd <= std_logic'('0');
MonRd1 <= std_logic'('0');
MonAReg <= std_logic_vector'("00000000000");
internal_MonDReg <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(take_no_action_ocimem_a) = '1' then
MonAReg(10 DOWNTO 2) <= A_EXT (((std_logic_vector'("000000000000000000000000") & (MonAReg(10 DOWNTO 2))) + std_logic_vector'("000000000000000000000000000000001")), 9);
MonRd <= std_logic'('1');
elsif std_logic'(take_action_ocimem_a) = '1' then
MonAReg(10 DOWNTO 2) <= Std_Logic_Vector'(A_ToStdLogicVector(jdo(17)) & jdo(33 DOWNTO 26));
MonRd <= std_logic'('1');
elsif std_logic'(take_action_ocimem_b) = '1' then
MonAReg(10 DOWNTO 2) <= A_EXT (((std_logic_vector'("000000000000000000000000") & (MonAReg(10 DOWNTO 2))) + std_logic_vector'("000000000000000000000000000000001")), 9);
internal_MonDReg <= jdo(34 DOWNTO 3);
MonWr <= std_logic'('1');
else
if std_logic'(NOT avalon) = '1' then
MonWr <= std_logic'('0');
MonRd <= std_logic'('0');
end if;
if std_logic'(MonRd1) = '1' then
internal_MonDReg <= A_WE_StdLogicVector((std_logic'(MonAReg(10)) = '1'), cfgdout, sramdout);
end if;
end if;
MonRd1 <= MonRd;
end if;
end process;
--Video_System_CPU_ociram_lpm_dram_bdp_component, which is an nios_tdp_ram
Video_System_CPU_ociram_lpm_dram_bdp_component : Video_System_CPU_ociram_lpm_dram_bdp_component_module
generic map(
lpm_file => Video_System_CPU_ociram_lpm_dram_bdp_component_lpm_file
)
port map(
q_a => internal_oci_ram_readdata,
q_b => sramdout,
address_a => module_input,
address_b => module_input1,
byteena_a => byteenable,
clock0 => clk,
clock1 => clk,
clocken0 => module_input2,
clocken1 => module_input3,
data_a => writedata,
data_b => module_input4,
wren_a => module_input5,
wren_b => MonWr
);
module_input <= address(7 DOWNTO 0);
module_input1 <= MonAReg(9 DOWNTO 2);
module_input2 <= std_logic'('1');
module_input3 <= std_logic'('1');
module_input4 <= internal_MonDReg(31 DOWNTO 0);
module_input5 <= ((chipselect AND write) AND debugaccess) AND NOT address(8);
cfgdout <= A_WE_StdLogicVector(((MonAReg(4 DOWNTO 2) = std_logic_vector'("000"))), std_logic_vector'("00000000000010000100000000100000"), A_WE_StdLogicVector(((MonAReg(4 DOWNTO 2) = std_logic_vector'("001"))), std_logic_vector'("00000000000000000001010000010100"), A_WE_StdLogicVector(((MonAReg(4 DOWNTO 2) = std_logic_vector'("010"))), std_logic_vector'("00000000000001000000000000000000"), A_WE_StdLogicVector(((MonAReg(4 DOWNTO 2) = std_logic_vector'("011"))), std_logic_vector'("00000000000000000000000000000000"), A_WE_StdLogicVector(((MonAReg(4 DOWNTO 2) = std_logic_vector'("100"))), std_logic_vector'("00100000000000000000000000000000"), A_WE_StdLogicVector(((MonAReg(4 DOWNTO 2) = std_logic_vector'("101"))), std_logic_vector'("00000000000010000100000000000000"), A_WE_StdLogicVector(((MonAReg(4 DOWNTO 2) = std_logic_vector'("110"))), std_logic_vector'("00000000000000000000000000000000"), std_logic_vector'("00000000000000000000000000000000"))))))));
--vhdl renameroo for output signals
MonDReg <= internal_MonDReg;
--vhdl renameroo for output signals
oci_ram_readdata <= internal_oci_ram_readdata;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_avalon_reg is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
signal chipselect : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal debugaccess : IN STD_LOGIC;
signal monitor_error : IN STD_LOGIC;
signal monitor_go : IN STD_LOGIC;
signal monitor_ready : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal oci_ienable : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oci_reg_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oci_single_step_mode : OUT STD_LOGIC;
signal ocireg_ers : OUT STD_LOGIC;
signal ocireg_mrs : OUT STD_LOGIC;
signal take_action_ocireg : OUT STD_LOGIC
);
end entity Video_System_CPU_nios2_avalon_reg;
architecture europa of Video_System_CPU_nios2_avalon_reg is
signal internal_oci_ienable1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_oci_single_step_mode1 : STD_LOGIC;
signal internal_take_action_ocireg : STD_LOGIC;
signal oci_reg_00_addressed : STD_LOGIC;
signal oci_reg_01_addressed : STD_LOGIC;
signal ocireg_sstep : STD_LOGIC;
signal take_action_oci_intr_mask_reg : STD_LOGIC;
signal write_strobe : STD_LOGIC;
begin
oci_reg_00_addressed <= to_std_logic((address = std_logic_vector'("100000000")));
oci_reg_01_addressed <= to_std_logic((address = std_logic_vector'("100000001")));
write_strobe <= (chipselect AND write) AND debugaccess;
internal_take_action_ocireg <= write_strobe AND oci_reg_00_addressed;
take_action_oci_intr_mask_reg <= write_strobe AND oci_reg_01_addressed;
ocireg_ers <= writedata(1);
ocireg_mrs <= writedata(0);
ocireg_sstep <= writedata(3);
oci_reg_readdata <= A_WE_StdLogicVector((std_logic'(oci_reg_00_addressed) = '1'), Std_Logic_Vector'(std_logic_vector'("0000000000000000000000000000") & A_ToStdLogicVector(internal_oci_single_step_mode1) & A_ToStdLogicVector(monitor_go) & A_ToStdLogicVector(monitor_ready) & A_ToStdLogicVector(monitor_error)), A_WE_StdLogicVector((std_logic'(oci_reg_01_addressed) = '1'), internal_oci_ienable1, std_logic_vector'("00000000000000000000000000000000")));
process (clk, reset_n)
begin
if reset_n = '0' then
internal_oci_single_step_mode1 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(internal_take_action_ocireg) = '1' then
internal_oci_single_step_mode1 <= ocireg_sstep;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
internal_oci_ienable1 <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(take_action_oci_intr_mask_reg) = '1' then
internal_oci_ienable1 <= writedata OR NOT (std_logic_vector'("00000000000000000000000000000000"));
end if;
end if;
end process;
--vhdl renameroo for output signals
oci_ienable <= internal_oci_ienable1;
--vhdl renameroo for output signals
oci_single_step_mode <= internal_oci_single_step_mode1;
--vhdl renameroo for output signals
take_action_ocireg <= internal_take_action_ocireg;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_break is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dbrk_break : IN STD_LOGIC;
signal dbrk_goto0 : IN STD_LOGIC;
signal dbrk_goto1 : IN STD_LOGIC;
signal jdo : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal take_action_break_a : IN STD_LOGIC;
signal take_action_break_b : IN STD_LOGIC;
signal take_action_break_c : IN STD_LOGIC;
signal take_no_action_break_a : IN STD_LOGIC;
signal take_no_action_break_b : IN STD_LOGIC;
signal take_no_action_break_c : IN STD_LOGIC;
signal xbrk_goto0 : IN STD_LOGIC;
signal xbrk_goto1 : IN STD_LOGIC;
-- outputs:
signal break_readreg : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dbrk_hit0_latch : OUT STD_LOGIC;
signal dbrk_hit1_latch : OUT STD_LOGIC;
signal dbrk_hit2_latch : OUT STD_LOGIC;
signal dbrk_hit3_latch : OUT STD_LOGIC;
signal trigbrktype : OUT STD_LOGIC;
signal trigger_state_0 : OUT STD_LOGIC;
signal trigger_state_1 : OUT STD_LOGIC;
signal xbrk_ctrl0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl2 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl3 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end entity Video_System_CPU_nios2_oci_break;
architecture europa of Video_System_CPU_nios2_oci_break is
signal break_a_wpr : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal break_a_wpr_high_bits : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal break_a_wpr_low_bits : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal break_b_rr : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal break_c_rr : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal dbrk0_high_value : STD_LOGIC;
signal dbrk0_low_value : STD_LOGIC;
signal dbrk1_high_value : STD_LOGIC;
signal dbrk1_low_value : STD_LOGIC;
signal dbrk2_high_value : STD_LOGIC;
signal dbrk2_low_value : STD_LOGIC;
signal dbrk3_high_value : STD_LOGIC;
signal dbrk3_low_value : STD_LOGIC;
signal internal_trigger_state_0 : STD_LOGIC;
signal internal_trigger_state_1 : STD_LOGIC;
signal take_action_any_break : STD_LOGIC;
signal trigger_state : STD_LOGIC;
signal xbrk0_value : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal xbrk1_value : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal xbrk2_value : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal xbrk3_value : STD_LOGIC_VECTOR (31 DOWNTO 0);
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of break_readreg : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
attribute ALTERA_ATTRIBUTE of trigbrktype : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
attribute ALTERA_ATTRIBUTE of xbrk_ctrl0 : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
attribute ALTERA_ATTRIBUTE of xbrk_ctrl1 : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
attribute ALTERA_ATTRIBUTE of xbrk_ctrl2 : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
attribute ALTERA_ATTRIBUTE of xbrk_ctrl3 : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
begin
break_a_wpr <= jdo(35 DOWNTO 32);
break_a_wpr_high_bits <= break_a_wpr(3 DOWNTO 2);
break_a_wpr_low_bits <= break_a_wpr(1 DOWNTO 0);
break_b_rr <= jdo(33 DOWNTO 32);
break_c_rr <= jdo(33 DOWNTO 32);
take_action_any_break <= (take_action_break_a OR take_action_break_b) OR take_action_break_c;
process (clk, jrst_n)
begin
if jrst_n = '0' then
xbrk_ctrl0 <= std_logic_vector'("00000000");
xbrk_ctrl1 <= std_logic_vector'("00000000");
xbrk_ctrl2 <= std_logic_vector'("00000000");
xbrk_ctrl3 <= std_logic_vector'("00000000");
trigbrktype <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(take_action_any_break) = '1' then
trigbrktype <= std_logic'('0');
elsif std_logic'(dbrk_break) = '1' then
trigbrktype <= std_logic'('1');
end if;
if std_logic'(take_action_break_b) = '1' then
if ((break_b_rr = std_logic_vector'("00"))) AND ((std_logic_vector'("00000000000000000000000000000000")>=std_logic_vector'("00000000000000000000000000000001"))) then
xbrk_ctrl0(0) <= jdo(27);
xbrk_ctrl0(1) <= jdo(28);
xbrk_ctrl0(2) <= jdo(29);
xbrk_ctrl0(3) <= jdo(30);
xbrk_ctrl0(4) <= jdo(21);
xbrk_ctrl0(5) <= jdo(20);
xbrk_ctrl0(6) <= jdo(19);
xbrk_ctrl0(7) <= jdo(18);
end if;
if ((break_b_rr = std_logic_vector'("01"))) AND ((std_logic_vector'("00000000000000000000000000000000")>=std_logic_vector'("00000000000000000000000000000010"))) then
xbrk_ctrl1(0) <= jdo(27);
xbrk_ctrl1(1) <= jdo(28);
xbrk_ctrl1(2) <= jdo(29);
xbrk_ctrl1(3) <= jdo(30);
xbrk_ctrl1(4) <= jdo(21);
xbrk_ctrl1(5) <= jdo(20);
xbrk_ctrl1(6) <= jdo(19);
xbrk_ctrl1(7) <= jdo(18);
end if;
if ((break_b_rr = std_logic_vector'("10"))) AND ((std_logic_vector'("00000000000000000000000000000000")>=std_logic_vector'("00000000000000000000000000000011"))) then
xbrk_ctrl2(0) <= jdo(27);
xbrk_ctrl2(1) <= jdo(28);
xbrk_ctrl2(2) <= jdo(29);
xbrk_ctrl2(3) <= jdo(30);
xbrk_ctrl2(4) <= jdo(21);
xbrk_ctrl2(5) <= jdo(20);
xbrk_ctrl2(6) <= jdo(19);
xbrk_ctrl2(7) <= jdo(18);
end if;
if ((break_b_rr = std_logic_vector'("11"))) AND ((std_logic_vector'("00000000000000000000000000000000")>=std_logic_vector'("00000000000000000000000000000100"))) then
xbrk_ctrl3(0) <= jdo(27);
xbrk_ctrl3(1) <= jdo(28);
xbrk_ctrl3(2) <= jdo(29);
xbrk_ctrl3(3) <= jdo(30);
xbrk_ctrl3(4) <= jdo(21);
xbrk_ctrl3(5) <= jdo(20);
xbrk_ctrl3(6) <= jdo(19);
xbrk_ctrl3(7) <= jdo(18);
end if;
end if;
end if;
end process;
dbrk_hit0_latch <= std_logic'('0');
dbrk0_low_value <= std_logic'('0');
dbrk0_high_value <= std_logic'('0');
dbrk_hit1_latch <= std_logic'('0');
dbrk1_low_value <= std_logic'('0');
dbrk1_high_value <= std_logic'('0');
dbrk_hit2_latch <= std_logic'('0');
dbrk2_low_value <= std_logic'('0');
dbrk2_high_value <= std_logic'('0');
dbrk_hit3_latch <= std_logic'('0');
dbrk3_low_value <= std_logic'('0');
dbrk3_high_value <= std_logic'('0');
xbrk0_value <= std_logic_vector'("00000000000000000000000000000000");
xbrk1_value <= std_logic_vector'("00000000000000000000000000000000");
xbrk2_value <= std_logic_vector'("00000000000000000000000000000000");
xbrk3_value <= std_logic_vector'("00000000000000000000000000000000");
process (clk, jrst_n)
begin
if jrst_n = '0' then
break_readreg <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(take_action_any_break) = '1' then
break_readreg <= jdo(31 DOWNTO 0);
elsif std_logic'(take_no_action_break_a) = '1' then
case break_a_wpr_high_bits is
when std_logic_vector'("00") =>
case break_a_wpr_low_bits is -- synthesis full_case
when std_logic_vector'("00") =>
break_readreg <= xbrk0_value;
-- when std_logic_vector'("00")
when std_logic_vector'("01") =>
break_readreg <= xbrk1_value;
-- when std_logic_vector'("01")
when std_logic_vector'("10") =>
break_readreg <= xbrk2_value;
-- when std_logic_vector'("10")
when std_logic_vector'("11") =>
break_readreg <= xbrk3_value;
-- when std_logic_vector'("11")
when others =>
-- when others
end case; -- break_a_wpr_low_bits
-- when std_logic_vector'("00")
when std_logic_vector'("01") =>
break_readreg <= std_logic_vector'("00000000000000000000000000000000");
-- when std_logic_vector'("01")
when std_logic_vector'("10") =>
case break_a_wpr_low_bits is -- synthesis full_case
when std_logic_vector'("00") =>
break_readreg <= std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dbrk0_low_value));
-- when std_logic_vector'("00")
when std_logic_vector'("01") =>
break_readreg <= std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dbrk1_low_value));
-- when std_logic_vector'("01")
when std_logic_vector'("10") =>
break_readreg <= std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dbrk2_low_value));
-- when std_logic_vector'("10")
when std_logic_vector'("11") =>
break_readreg <= std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dbrk3_low_value));
-- when std_logic_vector'("11")
when others =>
-- when others
end case; -- break_a_wpr_low_bits
-- when std_logic_vector'("10")
when std_logic_vector'("11") =>
case break_a_wpr_low_bits is -- synthesis full_case
when std_logic_vector'("00") =>
break_readreg <= std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dbrk0_high_value));
-- when std_logic_vector'("00")
when std_logic_vector'("01") =>
break_readreg <= std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dbrk1_high_value));
-- when std_logic_vector'("01")
when std_logic_vector'("10") =>
break_readreg <= std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dbrk2_high_value));
-- when std_logic_vector'("10")
when std_logic_vector'("11") =>
break_readreg <= std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dbrk3_high_value));
-- when std_logic_vector'("11")
when others =>
-- when others
end case; -- break_a_wpr_low_bits
-- when std_logic_vector'("11")
when others =>
-- when others
end case; -- break_a_wpr_high_bits
elsif std_logic'(take_no_action_break_b) = '1' then
break_readreg <= jdo(31 DOWNTO 0);
elsif std_logic'(take_no_action_break_c) = '1' then
break_readreg <= jdo(31 DOWNTO 0);
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
trigger_state <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((internal_trigger_state_1 AND ((xbrk_goto0 OR dbrk_goto0)))) = '1' then
trigger_state <= std_logic'('0');
elsif std_logic'((internal_trigger_state_0 AND ((xbrk_goto1 OR dbrk_goto1)))) = '1' then
trigger_state <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
end if;
end if;
end process;
internal_trigger_state_0 <= NOT trigger_state;
internal_trigger_state_1 <= trigger_state;
--vhdl renameroo for output signals
trigger_state_0 <= internal_trigger_state_0;
--vhdl renameroo for output signals
trigger_state_1 <= internal_trigger_state_1;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_xbrk is
port (
-- inputs:
signal D_valid : IN STD_LOGIC;
signal E_valid : IN STD_LOGIC;
signal F_pc : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal trigger_state_0 : IN STD_LOGIC;
signal trigger_state_1 : IN STD_LOGIC;
signal xbrk_ctrl0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl2 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl3 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- outputs:
signal xbrk_break : OUT STD_LOGIC;
signal xbrk_goto0 : OUT STD_LOGIC;
signal xbrk_goto1 : OUT STD_LOGIC;
signal xbrk_traceoff : OUT STD_LOGIC;
signal xbrk_traceon : OUT STD_LOGIC;
signal xbrk_trigout : OUT STD_LOGIC
);
end entity Video_System_CPU_nios2_oci_xbrk;
architecture europa of Video_System_CPU_nios2_oci_xbrk is
signal D_cpu_addr_en : STD_LOGIC;
signal E_cpu_addr_en : STD_LOGIC;
signal E_xbrk_goto0 : STD_LOGIC;
signal E_xbrk_goto1 : STD_LOGIC;
signal E_xbrk_traceoff : STD_LOGIC;
signal E_xbrk_traceon : STD_LOGIC;
signal E_xbrk_trigout : STD_LOGIC;
signal cpu_i_address : STD_LOGIC_VECTOR (19 DOWNTO 0);
signal xbrk0_armed : STD_LOGIC;
signal xbrk0_break_hit : STD_LOGIC;
signal xbrk0_goto0_hit : STD_LOGIC;
signal xbrk0_goto1_hit : STD_LOGIC;
signal xbrk0_toff_hit : STD_LOGIC;
signal xbrk0_ton_hit : STD_LOGIC;
signal xbrk0_tout_hit : STD_LOGIC;
signal xbrk1_armed : STD_LOGIC;
signal xbrk1_break_hit : STD_LOGIC;
signal xbrk1_goto0_hit : STD_LOGIC;
signal xbrk1_goto1_hit : STD_LOGIC;
signal xbrk1_toff_hit : STD_LOGIC;
signal xbrk1_ton_hit : STD_LOGIC;
signal xbrk1_tout_hit : STD_LOGIC;
signal xbrk2_armed : STD_LOGIC;
signal xbrk2_break_hit : STD_LOGIC;
signal xbrk2_goto0_hit : STD_LOGIC;
signal xbrk2_goto1_hit : STD_LOGIC;
signal xbrk2_toff_hit : STD_LOGIC;
signal xbrk2_ton_hit : STD_LOGIC;
signal xbrk2_tout_hit : STD_LOGIC;
signal xbrk3_armed : STD_LOGIC;
signal xbrk3_break_hit : STD_LOGIC;
signal xbrk3_goto0_hit : STD_LOGIC;
signal xbrk3_goto1_hit : STD_LOGIC;
signal xbrk3_toff_hit : STD_LOGIC;
signal xbrk3_ton_hit : STD_LOGIC;
signal xbrk3_tout_hit : STD_LOGIC;
signal xbrk_break_hit : STD_LOGIC;
signal xbrk_goto0_hit : STD_LOGIC;
signal xbrk_goto1_hit : STD_LOGIC;
signal xbrk_toff_hit : STD_LOGIC;
signal xbrk_ton_hit : STD_LOGIC;
signal xbrk_tout_hit : STD_LOGIC;
begin
cpu_i_address <= F_pc & std_logic_vector'("00");
D_cpu_addr_en <= D_valid;
E_cpu_addr_en <= E_valid;
xbrk0_break_hit <= std_logic'('0');
xbrk0_ton_hit <= std_logic'('0');
xbrk0_toff_hit <= std_logic'('0');
xbrk0_tout_hit <= std_logic'('0');
xbrk0_goto0_hit <= std_logic'('0');
xbrk0_goto1_hit <= std_logic'('0');
xbrk1_break_hit <= std_logic'('0');
xbrk1_ton_hit <= std_logic'('0');
xbrk1_toff_hit <= std_logic'('0');
xbrk1_tout_hit <= std_logic'('0');
xbrk1_goto0_hit <= std_logic'('0');
xbrk1_goto1_hit <= std_logic'('0');
xbrk2_break_hit <= std_logic'('0');
xbrk2_ton_hit <= std_logic'('0');
xbrk2_toff_hit <= std_logic'('0');
xbrk2_tout_hit <= std_logic'('0');
xbrk2_goto0_hit <= std_logic'('0');
xbrk2_goto1_hit <= std_logic'('0');
xbrk3_break_hit <= std_logic'('0');
xbrk3_ton_hit <= std_logic'('0');
xbrk3_toff_hit <= std_logic'('0');
xbrk3_tout_hit <= std_logic'('0');
xbrk3_goto0_hit <= std_logic'('0');
xbrk3_goto1_hit <= std_logic'('0');
xbrk_break_hit <= (((xbrk0_break_hit) OR (xbrk1_break_hit)) OR (xbrk2_break_hit)) OR (xbrk3_break_hit);
xbrk_ton_hit <= (((xbrk0_ton_hit) OR (xbrk1_ton_hit)) OR (xbrk2_ton_hit)) OR (xbrk3_ton_hit);
xbrk_toff_hit <= (((xbrk0_toff_hit) OR (xbrk1_toff_hit)) OR (xbrk2_toff_hit)) OR (xbrk3_toff_hit);
xbrk_tout_hit <= (((xbrk0_tout_hit) OR (xbrk1_tout_hit)) OR (xbrk2_tout_hit)) OR (xbrk3_tout_hit);
xbrk_goto0_hit <= (((xbrk0_goto0_hit) OR (xbrk1_goto0_hit)) OR (xbrk2_goto0_hit)) OR (xbrk3_goto0_hit);
xbrk_goto1_hit <= (((xbrk0_goto1_hit) OR (xbrk1_goto1_hit)) OR (xbrk2_goto1_hit)) OR (xbrk3_goto1_hit);
process (clk, reset_n)
begin
if reset_n = '0' then
xbrk_break <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(E_cpu_addr_en) = '1' then
xbrk_break <= xbrk_break_hit;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_xbrk_traceon <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(E_cpu_addr_en) = '1' then
E_xbrk_traceon <= xbrk_ton_hit;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_xbrk_traceoff <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(E_cpu_addr_en) = '1' then
E_xbrk_traceoff <= xbrk_toff_hit;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_xbrk_trigout <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(E_cpu_addr_en) = '1' then
E_xbrk_trigout <= xbrk_tout_hit;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_xbrk_goto0 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(E_cpu_addr_en) = '1' then
E_xbrk_goto0 <= xbrk_goto0_hit;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_xbrk_goto1 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(E_cpu_addr_en) = '1' then
E_xbrk_goto1 <= xbrk_goto1_hit;
end if;
end if;
end process;
xbrk_traceon <= std_logic'('0');
xbrk_traceoff <= std_logic'('0');
xbrk_trigout <= std_logic'('0');
xbrk_goto0 <= std_logic'('0');
xbrk_goto1 <= std_logic'('0');
xbrk0_armed <= ((xbrk_ctrl0(4) AND trigger_state_0)) OR ((xbrk_ctrl0(5) AND trigger_state_1));
xbrk1_armed <= ((xbrk_ctrl1(4) AND trigger_state_0)) OR ((xbrk_ctrl1(5) AND trigger_state_1));
xbrk2_armed <= ((xbrk_ctrl2(4) AND trigger_state_0)) OR ((xbrk_ctrl2(5) AND trigger_state_1));
xbrk3_armed <= ((xbrk_ctrl3(4) AND trigger_state_0)) OR ((xbrk_ctrl3(5) AND trigger_state_1));
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_dbrk is
port (
-- inputs:
signal E_st_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal av_ld_data_aligned_filtered : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal d_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal d_read : IN STD_LOGIC;
signal d_waitrequest : IN STD_LOGIC;
signal d_write : IN STD_LOGIC;
signal debugack : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal cpu_d_address : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
signal cpu_d_read : OUT STD_LOGIC;
signal cpu_d_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal cpu_d_wait : OUT STD_LOGIC;
signal cpu_d_write : OUT STD_LOGIC;
signal cpu_d_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dbrk_break : OUT STD_LOGIC;
signal dbrk_goto0 : OUT STD_LOGIC;
signal dbrk_goto1 : OUT STD_LOGIC;
signal dbrk_traceme : OUT STD_LOGIC;
signal dbrk_traceoff : OUT STD_LOGIC;
signal dbrk_traceon : OUT STD_LOGIC;
signal dbrk_trigout : OUT STD_LOGIC
);
end entity Video_System_CPU_nios2_oci_dbrk;
architecture europa of Video_System_CPU_nios2_oci_dbrk is
signal dbrk0_armed : STD_LOGIC;
signal dbrk0_break_pulse : STD_LOGIC;
signal dbrk0_goto0 : STD_LOGIC;
signal dbrk0_goto1 : STD_LOGIC;
signal dbrk0_traceme : STD_LOGIC;
signal dbrk0_traceoff : STD_LOGIC;
signal dbrk0_traceon : STD_LOGIC;
signal dbrk0_trigout : STD_LOGIC;
signal dbrk1_armed : STD_LOGIC;
signal dbrk1_break_pulse : STD_LOGIC;
signal dbrk1_goto0 : STD_LOGIC;
signal dbrk1_goto1 : STD_LOGIC;
signal dbrk1_traceme : STD_LOGIC;
signal dbrk1_traceoff : STD_LOGIC;
signal dbrk1_traceon : STD_LOGIC;
signal dbrk1_trigout : STD_LOGIC;
signal dbrk2_armed : STD_LOGIC;
signal dbrk2_break_pulse : STD_LOGIC;
signal dbrk2_goto0 : STD_LOGIC;
signal dbrk2_goto1 : STD_LOGIC;
signal dbrk2_traceme : STD_LOGIC;
signal dbrk2_traceoff : STD_LOGIC;
signal dbrk2_traceon : STD_LOGIC;
signal dbrk2_trigout : STD_LOGIC;
signal dbrk3_armed : STD_LOGIC;
signal dbrk3_break_pulse : STD_LOGIC;
signal dbrk3_goto0 : STD_LOGIC;
signal dbrk3_goto1 : STD_LOGIC;
signal dbrk3_traceme : STD_LOGIC;
signal dbrk3_traceoff : STD_LOGIC;
signal dbrk3_traceon : STD_LOGIC;
signal dbrk3_trigout : STD_LOGIC;
signal dbrk_break_pulse : STD_LOGIC;
signal dbrk_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_cpu_d_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_cpu_d_write : STD_LOGIC;
signal internal_cpu_d_writedata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_dbrk_break : STD_LOGIC;
begin
cpu_d_address <= d_address;
internal_cpu_d_readdata <= av_ld_data_aligned_filtered;
cpu_d_read <= d_read;
internal_cpu_d_writedata <= E_st_data;
internal_cpu_d_write <= d_write;
cpu_d_wait <= d_waitrequest;
dbrk_data <= A_WE_StdLogicVector((std_logic'(internal_cpu_d_write) = '1'), internal_cpu_d_writedata, internal_cpu_d_readdata);
process (clk, reset_n)
begin
if reset_n = '0' then
internal_dbrk_break <= std_logic'('0');
elsif clk'event and clk = '1' then
internal_dbrk_break <= A_WE_StdLogic((std_logic'(internal_dbrk_break) = '1'), NOT debugack, dbrk_break_pulse);
end if;
end process;
dbrk0_armed <= std_logic'('0');
dbrk0_trigout <= std_logic'('0');
dbrk0_break_pulse <= std_logic'('0');
dbrk0_traceoff <= std_logic'('0');
dbrk0_traceon <= std_logic'('0');
dbrk0_traceme <= std_logic'('0');
dbrk0_goto0 <= std_logic'('0');
dbrk0_goto1 <= std_logic'('0');
dbrk1_armed <= std_logic'('0');
dbrk1_trigout <= std_logic'('0');
dbrk1_break_pulse <= std_logic'('0');
dbrk1_traceoff <= std_logic'('0');
dbrk1_traceon <= std_logic'('0');
dbrk1_traceme <= std_logic'('0');
dbrk1_goto0 <= std_logic'('0');
dbrk1_goto1 <= std_logic'('0');
dbrk2_armed <= std_logic'('0');
dbrk2_trigout <= std_logic'('0');
dbrk2_break_pulse <= std_logic'('0');
dbrk2_traceoff <= std_logic'('0');
dbrk2_traceon <= std_logic'('0');
dbrk2_traceme <= std_logic'('0');
dbrk2_goto0 <= std_logic'('0');
dbrk2_goto1 <= std_logic'('0');
dbrk3_armed <= std_logic'('0');
dbrk3_trigout <= std_logic'('0');
dbrk3_break_pulse <= std_logic'('0');
dbrk3_traceoff <= std_logic'('0');
dbrk3_traceon <= std_logic'('0');
dbrk3_traceme <= std_logic'('0');
dbrk3_goto0 <= std_logic'('0');
dbrk3_goto1 <= std_logic'('0');
process (clk, reset_n)
begin
if reset_n = '0' then
dbrk_trigout <= std_logic'('0');
dbrk_break_pulse <= std_logic'('0');
dbrk_traceoff <= std_logic'('0');
dbrk_traceon <= std_logic'('0');
dbrk_traceme <= std_logic'('0');
dbrk_goto0 <= std_logic'('0');
dbrk_goto1 <= std_logic'('0');
elsif clk'event and clk = '1' then
dbrk_trigout <= ((dbrk0_trigout OR dbrk1_trigout) OR dbrk2_trigout) OR dbrk3_trigout;
dbrk_break_pulse <= ((dbrk0_break_pulse OR dbrk1_break_pulse) OR dbrk2_break_pulse) OR dbrk3_break_pulse;
dbrk_traceoff <= ((dbrk0_traceoff OR dbrk1_traceoff) OR dbrk2_traceoff) OR dbrk3_traceoff;
dbrk_traceon <= ((dbrk0_traceon OR dbrk1_traceon) OR dbrk2_traceon) OR dbrk3_traceon;
dbrk_traceme <= ((dbrk0_traceme OR dbrk1_traceme) OR dbrk2_traceme) OR dbrk3_traceme;
dbrk_goto0 <= ((dbrk0_goto0 OR dbrk1_goto0) OR dbrk2_goto0) OR dbrk3_goto0;
dbrk_goto1 <= ((dbrk0_goto1 OR dbrk1_goto1) OR dbrk2_goto1) OR dbrk3_goto1;
end if;
end process;
--vhdl renameroo for output signals
cpu_d_readdata <= internal_cpu_d_readdata;
--vhdl renameroo for output signals
cpu_d_write <= internal_cpu_d_write;
--vhdl renameroo for output signals
cpu_d_writedata <= internal_cpu_d_writedata;
--vhdl renameroo for output signals
dbrk_break <= internal_dbrk_break;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_itrace is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dbrk_traceoff : IN STD_LOGIC;
signal dbrk_traceon : IN STD_LOGIC;
signal jdo : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal take_action_tracectrl : IN STD_LOGIC;
signal trc_enb : IN STD_LOGIC;
signal xbrk_traceoff : IN STD_LOGIC;
signal xbrk_traceon : IN STD_LOGIC;
signal xbrk_wrap_traceoff : IN STD_LOGIC;
-- outputs:
signal dct_buffer : OUT STD_LOGIC_VECTOR (29 DOWNTO 0);
signal dct_count : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal itm : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal trc_ctrl : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal trc_on : OUT STD_LOGIC
);
end entity Video_System_CPU_nios2_oci_itrace;
architecture europa of Video_System_CPU_nios2_oci_itrace is
signal curr_pid : STD_LOGIC;
signal dct_code : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal dct_is_taken : STD_LOGIC;
signal excaddr : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal instr_retired : STD_LOGIC;
signal internal_dct_buffer : STD_LOGIC_VECTOR (29 DOWNTO 0);
signal internal_dct_count : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal internal_trc_ctrl : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal internal_trc_on : STD_LOGIC;
signal is_advanced_exception : STD_LOGIC;
signal is_cond_dct : STD_LOGIC;
signal is_dct : STD_LOGIC;
signal is_exception_no_break : STD_LOGIC;
signal is_fast_tlb_miss_exception : STD_LOGIC;
signal is_idct : STD_LOGIC;
signal not_in_debug_mode : STD_LOGIC;
signal pending_curr_pid : STD_LOGIC;
signal pending_excaddr : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pending_exctype : STD_LOGIC;
signal pending_frametype : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal pending_prev_pid : STD_LOGIC;
signal prev_pid : STD_LOGIC;
signal prev_pid_valid : STD_LOGIC;
signal record_dct_outcome_in_sync : STD_LOGIC;
signal record_itrace : STD_LOGIC;
signal retired_pcb : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal snapped_curr_pid : STD_LOGIC;
signal snapped_pid : STD_LOGIC;
signal snapped_prev_pid : STD_LOGIC;
signal sync_code : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal sync_interval : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal sync_pending : STD_LOGIC;
signal sync_timer : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal sync_timer_next : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal trc_clear : STD_LOGIC;
signal trc_ctrl_reg : STD_LOGIC_VECTOR (10 DOWNTO 0);
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of curr_pid : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of dct_buffer : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of dct_count : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of itm : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of pending_curr_pid : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of pending_exctype : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of pending_frametype : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of pending_prev_pid : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of prev_pid : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of prev_pid_valid : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of snapped_curr_pid : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of snapped_pid : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of snapped_prev_pid : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of sync_timer : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of trc_clear : signal is "SUPPRESS_DA_RULE_INTERNAL=D101";
attribute ALTERA_ATTRIBUTE of trc_ctrl_reg : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103,R101""";
begin
is_cond_dct <= std_logic'('0');
is_dct <= std_logic'('0');
dct_is_taken <= std_logic'('0');
is_idct <= std_logic'('0');
retired_pcb <= std_logic_vector'("00000000000000000000000000000000");
not_in_debug_mode <= std_logic'('0');
instr_retired <= std_logic'('0');
is_advanced_exception <= std_logic'('0');
is_exception_no_break <= std_logic'('0');
is_fast_tlb_miss_exception <= std_logic'('0');
curr_pid <= std_logic'('0');
excaddr <= std_logic_vector'("00000000000000000000000000000000");
sync_code <= internal_trc_ctrl(3 DOWNTO 2);
sync_interval <= Std_Logic_Vector'(A_ToStdLogicVector((sync_code(1) AND sync_code(0))) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector((sync_code(1) AND NOT sync_code(0))) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector((NOT sync_code(1) AND sync_code(0))) & std_logic_vector'("00"));
sync_pending <= to_std_logic(((std_logic_vector'("0000000000000000000000000") & (sync_timer)) = std_logic_vector'("00000000000000000000000000000000")));
record_dct_outcome_in_sync <= dct_is_taken AND sync_pending;
sync_timer_next <= A_EXT (A_WE_StdLogicVector((std_logic'(sync_pending) = '1'), (std_logic_vector'("00000000000000000000000000") & (sync_timer)), (((std_logic_vector'("00000000000000000000000000") & (sync_timer)) - std_logic_vector'("000000000000000000000000000000001")))), 7);
record_itrace <= internal_trc_on AND internal_trc_ctrl(4);
dct_code <= Std_Logic_Vector'(A_ToStdLogicVector(is_cond_dct) & A_ToStdLogicVector(dct_is_taken));
process (clk, jrst_n)
begin
if jrst_n = '0' then
trc_clear <= std_logic'('0');
elsif clk'event and clk = '1' then
trc_clear <= (NOT trc_enb AND take_action_tracectrl) AND jdo(4);
end if;
end process;
process (clk, jrst_n)
begin
if jrst_n = '0' then
itm <= std_logic_vector'("000000000000000000000000000000000000");
internal_dct_buffer <= std_logic_vector'("000000000000000000000000000000");
internal_dct_count <= std_logic_vector'("0000");
sync_timer <= std_logic_vector'("0000000");
pending_frametype <= std_logic_vector'("0000");
pending_exctype <= std_logic'('0');
pending_excaddr <= std_logic_vector'("00000000000000000000000000000000");
prev_pid <= std_logic'('0');
prev_pid_valid <= std_logic'('0');
snapped_pid <= std_logic'('0');
snapped_curr_pid <= std_logic'('0');
snapped_prev_pid <= std_logic'('0');
pending_curr_pid <= std_logic'('0');
pending_prev_pid <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((trc_clear OR ((NOT(or_reduce(std_logic_vector'("00000000000000000000000000000000"))) AND NOT(or_reduce(std_logic_vector'("00000000000000000000000000000000"))))))) = '1' then
itm <= std_logic_vector'("000000000000000000000000000000000000");
internal_dct_buffer <= std_logic_vector'("000000000000000000000000000000");
internal_dct_count <= std_logic_vector'("0000");
sync_timer <= std_logic_vector'("0000000");
pending_frametype <= std_logic_vector'("0000");
pending_exctype <= std_logic'('0');
pending_excaddr <= std_logic_vector'("00000000000000000000000000000000");
prev_pid <= std_logic'('0');
prev_pid_valid <= std_logic'('0');
snapped_pid <= std_logic'('0');
snapped_curr_pid <= std_logic'('0');
snapped_prev_pid <= std_logic'('0');
pending_curr_pid <= std_logic'('0');
pending_prev_pid <= std_logic'('0');
else
if std_logic'(NOT(prev_pid_valid)) = '1' then
prev_pid <= curr_pid;
prev_pid_valid <= std_logic'('1');
end if;
if std_logic'(((to_std_logic(((std_logic'(curr_pid) /= std_logic'(prev_pid)))) AND prev_pid_valid) AND NOT(snapped_pid))) = '1' then
snapped_pid <= std_logic'('1');
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
prev_pid <= curr_pid;
prev_pid_valid <= std_logic'('1');
end if;
if std_logic'((instr_retired OR is_advanced_exception)) = '1' then
if std_logic'(NOT record_itrace) = '1' then
pending_frametype <= std_logic_vector'("1010");
elsif std_logic'(is_exception_no_break) = '1' then
pending_frametype <= std_logic_vector'("0010");
pending_excaddr <= excaddr;
if std_logic'(is_fast_tlb_miss_exception) = '1' then
pending_exctype <= std_logic'('1');
else
pending_exctype <= std_logic'('0');
end if;
elsif std_logic'(is_idct) = '1' then
pending_frametype <= std_logic_vector'("1001");
elsif std_logic'(record_dct_outcome_in_sync) = '1' then
pending_frametype <= std_logic_vector'("1000");
elsif std_logic'((NOT(is_dct) AND snapped_pid)) = '1' then
pending_frametype <= std_logic_vector'("0011");
pending_curr_pid <= snapped_curr_pid;
pending_prev_pid <= snapped_prev_pid;
snapped_pid <= std_logic'('0');
else
pending_frametype <= std_logic_vector'("0000");
end if;
if std_logic'((to_std_logic((((std_logic_vector'("0000000000000000000000000000") & (internal_dct_count)) /= std_logic_vector'("00000000000000000000000000000000")))) AND (((((NOT record_itrace OR is_exception_no_break) OR is_idct) OR record_dct_outcome_in_sync) OR ((NOT(is_dct) AND snapped_pid)))))) = '1' then
itm <= Std_Logic_Vector'(std_logic_vector'("0001") & internal_dct_buffer & std_logic_vector'("00"));
internal_dct_buffer <= std_logic_vector'("000000000000000000000000000000");
internal_dct_count <= std_logic_vector'("0000");
sync_timer <= sync_timer_next;
else
if std_logic'((((record_itrace AND ((is_dct AND to_std_logic(((internal_dct_count /= std_logic_vector'("1111"))))))) AND NOT record_dct_outcome_in_sync) AND NOT is_advanced_exception)) = '1' then
internal_dct_buffer <= dct_code & internal_dct_buffer(29 DOWNTO 2);
internal_dct_count <= A_EXT (((std_logic_vector'("00000000000000000000000000000") & (internal_dct_count)) + std_logic_vector'("000000000000000000000000000000001")), 4);
end if;
if std_logic'((record_itrace AND to_std_logic(((pending_frametype = std_logic_vector'("0010")))))) = '1' then
itm <= Std_Logic_Vector'(std_logic_vector'("0010") & pending_excaddr(31 DOWNTO 1) & A_ToStdLogicVector(pending_exctype));
elsif std_logic'((record_itrace AND to_std_logic((((((pending_frametype = std_logic_vector'("1000"))) OR ((pending_frametype = std_logic_vector'("1010")))) OR ((pending_frametype = std_logic_vector'("1001")))))))) = '1' then
itm <= pending_frametype & retired_pcb;
sync_timer <= sync_interval;
if ((((std_logic_vector'("00000000000000000000000000000000") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(to_std_logic(((((pending_frametype = std_logic_vector'("1000"))) OR ((pending_frametype = std_logic_vector'("1010")))))))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT(snapped_pid))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(prev_pid_valid))))) /= std_logic_vector'("00000000000000000000000000000000") then
snapped_pid <= std_logic'('1');
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
end if;
elsif ((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(record_itrace))) AND std_logic_vector'("00000000000000000000000000000000")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(to_std_logic(((pending_frametype = std_logic_vector'("0011"))))))))) /= std_logic_vector'("00000000000000000000000000000000") then
itm <= std_logic_vector'("00000000000000000000000000") & (Std_Logic_Vector'(std_logic_vector'("0011") & std_logic_vector'("00") & A_ToStdLogicVector(pending_prev_pid) & std_logic_vector'("00") & A_ToStdLogicVector(pending_curr_pid)));
elsif std_logic'((record_itrace AND is_dct)) = '1' then
if internal_dct_count = std_logic_vector'("1111") then
itm <= Std_Logic_Vector'(std_logic_vector'("0001") & dct_code & internal_dct_buffer);
internal_dct_buffer <= std_logic_vector'("000000000000000000000000000000");
internal_dct_count <= std_logic_vector'("0000");
sync_timer <= sync_timer_next;
else
itm <= std_logic_vector'("000000000000000000000000000000000000");
end if;
else
itm <= Std_Logic_Vector'(std_logic_vector'("0000") & std_logic_vector'("00000000000000000000000000000000"));
end if;
end if;
else
itm <= Std_Logic_Vector'(std_logic_vector'("0000") & std_logic_vector'("00000000000000000000000000000000"));
end if;
end if;
end if;
end process;
process (clk, jrst_n)
begin
if jrst_n = '0' then
trc_ctrl_reg(0) <= std_logic'('0');
trc_ctrl_reg(1) <= std_logic'('0');
trc_ctrl_reg(3 DOWNTO 2) <= std_logic_vector'("00");
trc_ctrl_reg(4) <= std_logic'('0');
trc_ctrl_reg(7 DOWNTO 5) <= std_logic_vector'("000");
trc_ctrl_reg(8) <= std_logic'('0');
trc_ctrl_reg(9) <= std_logic'('0');
trc_ctrl_reg(10) <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(take_action_tracectrl) = '1' then
trc_ctrl_reg(0) <= jdo(5);
trc_ctrl_reg(1) <= jdo(6);
trc_ctrl_reg(3 DOWNTO 2) <= jdo(8 DOWNTO 7);
trc_ctrl_reg(4) <= jdo(9);
trc_ctrl_reg(9) <= jdo(14);
trc_ctrl_reg(10) <= jdo(2);
if true then
trc_ctrl_reg(7 DOWNTO 5) <= jdo(12 DOWNTO 10);
end if;
if ((std_logic_vector'("00000000000000000000000000000000") AND std_logic_vector'("00000000000000000000000000000000"))) /= std_logic_vector'("00000000000000000000000000000000") then
trc_ctrl_reg(8) <= jdo(13);
end if;
elsif std_logic'(xbrk_wrap_traceoff) = '1' then
trc_ctrl_reg(1) <= std_logic'('0');
trc_ctrl_reg(0) <= std_logic'('0');
elsif std_logic'((dbrk_traceoff OR xbrk_traceoff)) = '1' then
trc_ctrl_reg(1) <= std_logic'('0');
elsif std_logic'((trc_ctrl_reg(0) AND ((dbrk_traceon OR xbrk_traceon)))) = '1' then
trc_ctrl_reg(1) <= std_logic'('1');
end if;
end if;
end process;
internal_trc_ctrl <= A_EXT (A_WE_StdLogicVector((std_logic'(((or_reduce(std_logic_vector'("00000000000000000000000000000000")) OR or_reduce(std_logic_vector'("00000000000000000000000000000000"))))) = '1'), (std_logic_vector'("000000000000000") & (Std_Logic_Vector'(std_logic_vector'("000000") & trc_ctrl_reg))), std_logic_vector'("00000000000000000000000000000000")), 16);
internal_trc_on <= internal_trc_ctrl(1) AND ((internal_trc_ctrl(9) OR not_in_debug_mode));
--vhdl renameroo for output signals
dct_buffer <= internal_dct_buffer;
--vhdl renameroo for output signals
dct_count <= internal_dct_count;
--vhdl renameroo for output signals
trc_ctrl <= internal_trc_ctrl;
--vhdl renameroo for output signals
trc_on <= internal_trc_on;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_td_mode is
port (
-- inputs:
signal ctrl : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
-- outputs:
signal td_mode : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
end entity Video_System_CPU_nios2_oci_td_mode;
architecture europa of Video_System_CPU_nios2_oci_td_mode is
signal ctrl_bits_for_mux : STD_LOGIC_VECTOR (2 DOWNTO 0);
begin
ctrl_bits_for_mux <= ctrl(7 DOWNTO 5);
process (ctrl_bits_for_mux)
begin
case ctrl_bits_for_mux is
when std_logic_vector'("000") =>
td_mode <= std_logic_vector'("0000");
-- when std_logic_vector'("000")
when std_logic_vector'("001") =>
td_mode <= std_logic_vector'("1000");
-- when std_logic_vector'("001")
when std_logic_vector'("010") =>
td_mode <= std_logic_vector'("0100");
-- when std_logic_vector'("010")
when std_logic_vector'("011") =>
td_mode <= std_logic_vector'("1100");
-- when std_logic_vector'("011")
when std_logic_vector'("100") =>
td_mode <= std_logic_vector'("0010");
-- when std_logic_vector'("100")
when std_logic_vector'("101") =>
td_mode <= std_logic_vector'("1010");
-- when std_logic_vector'("101")
when std_logic_vector'("110") =>
td_mode <= std_logic_vector'("0101");
-- when std_logic_vector'("110")
when std_logic_vector'("111") =>
td_mode <= std_logic_vector'("1111");
-- when std_logic_vector'("111")
when others =>
-- when others
end case; -- ctrl_bits_for_mux
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_dtrace is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal cpu_d_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal cpu_d_read : IN STD_LOGIC;
signal cpu_d_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal cpu_d_wait : IN STD_LOGIC;
signal cpu_d_write : IN STD_LOGIC;
signal cpu_d_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal trc_ctrl : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- outputs:
signal atm : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal dtm : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end entity Video_System_CPU_nios2_oci_dtrace;
architecture europa of Video_System_CPU_nios2_oci_dtrace is
component Video_System_CPU_nios2_oci_td_mode is
port (
-- inputs:
signal ctrl : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
-- outputs:
signal td_mode : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
end component Video_System_CPU_nios2_oci_td_mode;
signal cpu_d_address_0_padded : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal cpu_d_readdata_0_padded : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal cpu_d_writedata_0_padded : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal module_input6 : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal record_load_addr : STD_LOGIC;
signal record_load_data : STD_LOGIC;
signal record_store_addr : STD_LOGIC;
signal record_store_data : STD_LOGIC;
signal td_mode_trc_ctrl : STD_LOGIC_VECTOR (3 DOWNTO 0);
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of atm : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of dtm : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
begin
cpu_d_writedata_0_padded <= cpu_d_writedata OR std_logic_vector'("00000000000000000000000000000000");
cpu_d_readdata_0_padded <= cpu_d_readdata OR std_logic_vector'("00000000000000000000000000000000");
cpu_d_address_0_padded <= (std_logic_vector'("000000000000") & (cpu_d_address)) OR std_logic_vector'("00000000000000000000000000000000");
--Video_System_CPU_nios2_oci_trc_ctrl_td_mode, which is an e_instance
Video_System_CPU_nios2_oci_trc_ctrl_td_mode : Video_System_CPU_nios2_oci_td_mode
port map(
td_mode => td_mode_trc_ctrl,
ctrl => module_input6
);
module_input6 <= trc_ctrl(8 DOWNTO 0);
(record_load_addr, record_store_addr, record_load_data, record_store_data) <= td_mode_trc_ctrl;
process (clk, jrst_n)
begin
if jrst_n = '0' then
atm <= std_logic_vector'("000000000000000000000000000000000000");
dtm <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if (std_logic_vector'("00000000000000000000000000000000")) /= std_logic_vector'("00000000000000000000000000000000") then
if std_logic'(((cpu_d_write AND NOT cpu_d_wait) AND record_store_addr)) = '1' then
atm <= Std_Logic_Vector'(std_logic_vector'("0101") & cpu_d_address_0_padded);
elsif std_logic'(((cpu_d_read AND NOT cpu_d_wait) AND record_load_addr)) = '1' then
atm <= Std_Logic_Vector'(std_logic_vector'("0100") & cpu_d_address_0_padded);
else
atm <= Std_Logic_Vector'(std_logic_vector'("0000") & cpu_d_address_0_padded);
end if;
if std_logic'(((cpu_d_write AND NOT cpu_d_wait) AND record_store_data)) = '1' then
dtm <= Std_Logic_Vector'(std_logic_vector'("0111") & cpu_d_writedata_0_padded);
elsif std_logic'(((cpu_d_read AND NOT cpu_d_wait) AND record_load_data)) = '1' then
dtm <= Std_Logic_Vector'(std_logic_vector'("0110") & cpu_d_readdata_0_padded);
else
dtm <= Std_Logic_Vector'(std_logic_vector'("0000") & cpu_d_readdata_0_padded);
end if;
else
atm <= std_logic_vector'("000000000000000000000000000000000000");
dtm <= std_logic_vector'("000000000000000000000000000000000000");
end if;
end if;
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_compute_tm_count is
port (
-- inputs:
signal atm_valid : IN STD_LOGIC;
signal dtm_valid : IN STD_LOGIC;
signal itm_valid : IN STD_LOGIC;
-- outputs:
signal compute_tm_count : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
end entity Video_System_CPU_nios2_oci_compute_tm_count;
architecture europa of Video_System_CPU_nios2_oci_compute_tm_count is
signal switch_for_mux : STD_LOGIC_VECTOR (2 DOWNTO 0);
begin
switch_for_mux <= Std_Logic_Vector'(A_ToStdLogicVector(itm_valid) & A_ToStdLogicVector(atm_valid) & A_ToStdLogicVector(dtm_valid));
process (switch_for_mux)
begin
case switch_for_mux is
when std_logic_vector'("000") =>
compute_tm_count <= std_logic_vector'("00");
-- when std_logic_vector'("000")
when std_logic_vector'("001") =>
compute_tm_count <= std_logic_vector'("01");
-- when std_logic_vector'("001")
when std_logic_vector'("010") =>
compute_tm_count <= std_logic_vector'("01");
-- when std_logic_vector'("010")
when std_logic_vector'("011") =>
compute_tm_count <= std_logic_vector'("10");
-- when std_logic_vector'("011")
when std_logic_vector'("100") =>
compute_tm_count <= std_logic_vector'("01");
-- when std_logic_vector'("100")
when std_logic_vector'("101") =>
compute_tm_count <= std_logic_vector'("10");
-- when std_logic_vector'("101")
when std_logic_vector'("110") =>
compute_tm_count <= std_logic_vector'("10");
-- when std_logic_vector'("110")
when std_logic_vector'("111") =>
compute_tm_count <= std_logic_vector'("11");
-- when std_logic_vector'("111")
when others =>
-- when others
end case; -- switch_for_mux
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_fifowp_inc is
port (
-- inputs:
signal free2 : IN STD_LOGIC;
signal free3 : IN STD_LOGIC;
signal tm_count : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- outputs:
signal fifowp_inc : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
end entity Video_System_CPU_nios2_oci_fifowp_inc;
architecture europa of Video_System_CPU_nios2_oci_fifowp_inc is
begin
process (free2, free3, tm_count)
begin
if std_logic'((free3 AND to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (tm_count)) = std_logic_vector'("00000000000000000000000000000011")))))) = '1' then
fifowp_inc <= std_logic_vector'("0011");
elsif std_logic'((free2 AND to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (tm_count))>=std_logic_vector'("00000000000000000000000000000010")))))) = '1' then
fifowp_inc <= std_logic_vector'("0010");
elsif (std_logic_vector'("000000000000000000000000000000") & (tm_count))>=std_logic_vector'("00000000000000000000000000000001") then
fifowp_inc <= std_logic_vector'("0001");
else
fifowp_inc <= std_logic_vector'("0000");
end if;
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_fifocount_inc is
port (
-- inputs:
signal empty : IN STD_LOGIC;
signal free2 : IN STD_LOGIC;
signal free3 : IN STD_LOGIC;
signal tm_count : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- outputs:
signal fifocount_inc : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
end entity Video_System_CPU_nios2_oci_fifocount_inc;
architecture europa of Video_System_CPU_nios2_oci_fifocount_inc is
begin
process (empty, free2, free3, tm_count)
begin
if std_logic'(empty) = '1' then
fifocount_inc <= std_logic_vector'("000") & (tm_count(1 DOWNTO 0));
elsif std_logic'((free3 AND to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (tm_count)) = std_logic_vector'("00000000000000000000000000000011")))))) = '1' then
fifocount_inc <= std_logic_vector'("00010");
elsif std_logic'((free2 AND to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (tm_count))>=std_logic_vector'("00000000000000000000000000000010")))))) = '1' then
fifocount_inc <= std_logic_vector'("00001");
elsif (std_logic_vector'("000000000000000000000000000000") & (tm_count))>=std_logic_vector'("00000000000000000000000000000001") then
fifocount_inc <= std_logic_vector'("00000");
else
fifocount_inc <= A_REP(std_logic'('1'), 5);
end if;
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_fifo is
port (
-- inputs:
signal atm : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal dbrk_traceme : IN STD_LOGIC;
signal dbrk_traceoff : IN STD_LOGIC;
signal dbrk_traceon : IN STD_LOGIC;
signal dct_buffer : IN STD_LOGIC_VECTOR (29 DOWNTO 0);
signal dct_count : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dtm : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal itm : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal test_ending : IN STD_LOGIC;
signal test_has_ended : IN STD_LOGIC;
signal trc_on : IN STD_LOGIC;
-- outputs:
signal tw : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end entity Video_System_CPU_nios2_oci_fifo;
architecture europa of Video_System_CPU_nios2_oci_fifo is
component Video_System_CPU_nios2_oci_compute_tm_count is
port (
-- inputs:
signal atm_valid : IN STD_LOGIC;
signal dtm_valid : IN STD_LOGIC;
signal itm_valid : IN STD_LOGIC;
-- outputs:
signal compute_tm_count : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
end component Video_System_CPU_nios2_oci_compute_tm_count;
component Video_System_CPU_nios2_oci_fifowp_inc is
port (
-- inputs:
signal free2 : IN STD_LOGIC;
signal free3 : IN STD_LOGIC;
signal tm_count : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- outputs:
signal fifowp_inc : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
end component Video_System_CPU_nios2_oci_fifowp_inc;
component Video_System_CPU_nios2_oci_fifocount_inc is
port (
-- inputs:
signal empty : IN STD_LOGIC;
signal free2 : IN STD_LOGIC;
signal free3 : IN STD_LOGIC;
signal tm_count : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- outputs:
signal fifocount_inc : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
end component Video_System_CPU_nios2_oci_fifocount_inc;
component Video_System_CPU_oci_test_bench is
port (
-- inputs:
signal dct_buffer : IN STD_LOGIC_VECTOR (29 DOWNTO 0);
signal dct_count : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal test_ending : IN STD_LOGIC;
signal test_has_ended : IN STD_LOGIC
);
end component Video_System_CPU_oci_test_bench;
signal atm_valid : STD_LOGIC;
signal compute_tm_count_tm_count : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal dtm_valid : STD_LOGIC;
signal empty : STD_LOGIC;
signal fifo_0 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_0_enable : STD_LOGIC;
signal fifo_0_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_1 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_10 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_10_enable : STD_LOGIC;
signal fifo_10_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_11 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_11_enable : STD_LOGIC;
signal fifo_11_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_12 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_12_enable : STD_LOGIC;
signal fifo_12_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_13 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_13_enable : STD_LOGIC;
signal fifo_13_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_14 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_14_enable : STD_LOGIC;
signal fifo_14_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_15 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_15_enable : STD_LOGIC;
signal fifo_15_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_1_enable : STD_LOGIC;
signal fifo_1_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_2 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_2_enable : STD_LOGIC;
signal fifo_2_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_3 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_3_enable : STD_LOGIC;
signal fifo_3_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_4 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_4_enable : STD_LOGIC;
signal fifo_4_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_5 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_5_enable : STD_LOGIC;
signal fifo_5_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_6 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_6_enable : STD_LOGIC;
signal fifo_6_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_7 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_7_enable : STD_LOGIC;
signal fifo_7_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_8 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_8_enable : STD_LOGIC;
signal fifo_8_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_9 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_9_enable : STD_LOGIC;
signal fifo_9_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_read_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifocount : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal fifocount_inc_fifocount : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal fifohead : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fiforp : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal fifowp : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal fifowp1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal fifowp2 : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal fifowp_inc_fifowp : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal free2 : STD_LOGIC;
signal free3 : STD_LOGIC;
signal itm_valid : STD_LOGIC;
signal ovf_pending : STD_LOGIC;
signal ovr_pending_atm : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal ovr_pending_dtm : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tm_count : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal tm_count_ge1 : STD_LOGIC;
signal tm_count_ge2 : STD_LOGIC;
signal tm_count_ge3 : STD_LOGIC;
signal trc_this : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of fifocount : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of fiforp : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of fifowp : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of ovf_pending : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
begin
trc_this <= (trc_on OR ((dbrk_traceon AND NOT dbrk_traceoff))) OR dbrk_traceme;
itm_valid <= or_reduce(itm(35 DOWNTO 32));
atm_valid <= or_reduce(atm(35 DOWNTO 32)) AND trc_this;
dtm_valid <= or_reduce(dtm(35 DOWNTO 32)) AND trc_this;
free2 <= NOT fifocount(4);
free3 <= NOT fifocount(4) AND nand_reduce(fifocount(3 DOWNTO 0));
empty <= NOT or_reduce(fifocount);
fifowp1 <= A_EXT (((std_logic_vector'("00000000000000000000000000000") & (fifowp)) + std_logic_vector'("000000000000000000000000000000001")), 4);
fifowp2 <= A_EXT (((std_logic_vector'("00000000000000000000000000000") & (fifowp)) + std_logic_vector'("000000000000000000000000000000010")), 4);
--Video_System_CPU_nios2_oci_compute_tm_count_tm_count, which is an e_instance
Video_System_CPU_nios2_oci_compute_tm_count_tm_count : Video_System_CPU_nios2_oci_compute_tm_count
port map(
compute_tm_count => compute_tm_count_tm_count,
atm_valid => atm_valid,
dtm_valid => dtm_valid,
itm_valid => itm_valid
);
tm_count <= compute_tm_count_tm_count;
--Video_System_CPU_nios2_oci_fifowp_inc_fifowp, which is an e_instance
Video_System_CPU_nios2_oci_fifowp_inc_fifowp : Video_System_CPU_nios2_oci_fifowp_inc
port map(
fifowp_inc => fifowp_inc_fifowp,
free2 => free2,
free3 => free3,
tm_count => tm_count
);
--Video_System_CPU_nios2_oci_fifocount_inc_fifocount, which is an e_instance
Video_System_CPU_nios2_oci_fifocount_inc_fifocount : Video_System_CPU_nios2_oci_fifocount_inc
port map(
fifocount_inc => fifocount_inc_fifocount,
empty => empty,
free2 => free2,
free3 => free3,
tm_count => tm_count
);
--the_Video_System_CPU_oci_test_bench, which is an e_instance
the_Video_System_CPU_oci_test_bench : Video_System_CPU_oci_test_bench
port map(
dct_buffer => dct_buffer,
dct_count => dct_count,
test_ending => test_ending,
test_has_ended => test_has_ended
);
process (clk, jrst_n)
begin
if jrst_n = '0' then
fiforp <= std_logic_vector'("0000");
fifowp <= std_logic_vector'("0000");
fifocount <= std_logic_vector'("00000");
ovf_pending <= std_logic'('1');
elsif clk'event and clk = '1' then
fifowp <= A_EXT (((std_logic_vector'("0") & (fifowp)) + (std_logic_vector'("0") & (fifowp_inc_fifowp))), 4);
fifocount <= A_EXT (((std_logic_vector'("0") & (fifocount)) + (std_logic_vector'("0") & (fifocount_inc_fifocount))), 5);
if std_logic'(NOT empty) = '1' then
fiforp <= A_EXT (((std_logic_vector'("00000000000000000000000000000") & (fiforp)) + std_logic_vector'("000000000000000000000000000000001")), 4);
end if;
if std_logic'(((NOT trc_this OR ((NOT free2 AND tm_count(1)))) OR ((NOT free3 AND (and_reduce(tm_count)))))) = '1' then
ovf_pending <= std_logic'('1');
elsif std_logic'((atm_valid OR dtm_valid)) = '1' then
ovf_pending <= std_logic'('0');
end if;
end if;
end process;
fifohead <= fifo_read_mux;
tw <= A_WE_StdLogicVector(((std_logic_vector'("00000000000000000000000000000000")) /= std_logic_vector'("00000000000000000000000000000000")), ((A_WE_StdLogicVector((std_logic'(empty) = '1'), std_logic_vector'("0000"), fifohead(35 DOWNTO 32))) & fifohead(31 DOWNTO 0)), itm);
fifo_0_enable <= (((to_std_logic(((fifowp = std_logic_vector'("0000")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("0000"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("0000"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_0 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_0_enable) = '1' then
fifo_0 <= fifo_0_mux;
end if;
end if;
end process;
fifo_0_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0000")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0000")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0000")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0000")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0000")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0000")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_1_enable <= (((to_std_logic(((fifowp = std_logic_vector'("0001")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("0001"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("0001"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_1 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_1_enable) = '1' then
fifo_1 <= fifo_1_mux;
end if;
end if;
end process;
fifo_1_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0001")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0001")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0001")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0001")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0001")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0001")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_2_enable <= (((to_std_logic(((fifowp = std_logic_vector'("0010")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("0010"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("0010"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_2 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_2_enable) = '1' then
fifo_2 <= fifo_2_mux;
end if;
end if;
end process;
fifo_2_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0010")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0010")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0010")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0010")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0010")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0010")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_3_enable <= (((to_std_logic(((fifowp = std_logic_vector'("0011")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("0011"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("0011"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_3 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_3_enable) = '1' then
fifo_3 <= fifo_3_mux;
end if;
end if;
end process;
fifo_3_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0011")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0011")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0011")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0011")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0011")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0011")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_4_enable <= (((to_std_logic(((fifowp = std_logic_vector'("0100")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("0100"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("0100"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_4 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_4_enable) = '1' then
fifo_4 <= fifo_4_mux;
end if;
end if;
end process;
fifo_4_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0100")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0100")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0100")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0100")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0100")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0100")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_5_enable <= (((to_std_logic(((fifowp = std_logic_vector'("0101")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("0101"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("0101"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_5 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_5_enable) = '1' then
fifo_5 <= fifo_5_mux;
end if;
end if;
end process;
fifo_5_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0101")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0101")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0101")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0101")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0101")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0101")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_6_enable <= (((to_std_logic(((fifowp = std_logic_vector'("0110")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("0110"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("0110"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_6 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_6_enable) = '1' then
fifo_6 <= fifo_6_mux;
end if;
end if;
end process;
fifo_6_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0110")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0110")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0110")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0110")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0110")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0110")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_7_enable <= (((to_std_logic(((fifowp = std_logic_vector'("0111")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("0111"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("0111"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_7 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_7_enable) = '1' then
fifo_7 <= fifo_7_mux;
end if;
end if;
end process;
fifo_7_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0111")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0111")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0111")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0111")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0111")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0111")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_8_enable <= (((to_std_logic(((fifowp = std_logic_vector'("1000")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("1000"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("1000"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_8 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_8_enable) = '1' then
fifo_8 <= fifo_8_mux;
end if;
end if;
end process;
fifo_8_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1000")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1000")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1000")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1000")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1000")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1000")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_9_enable <= (((to_std_logic(((fifowp = std_logic_vector'("1001")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("1001"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("1001"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_9 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_9_enable) = '1' then
fifo_9 <= fifo_9_mux;
end if;
end if;
end process;
fifo_9_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1001")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1001")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1001")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1001")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1001")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1001")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_10_enable <= (((to_std_logic(((fifowp = std_logic_vector'("1010")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("1010"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("1010"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_10 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_10_enable) = '1' then
fifo_10 <= fifo_10_mux;
end if;
end if;
end process;
fifo_10_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1010")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1010")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1010")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1010")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1010")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1010")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_11_enable <= (((to_std_logic(((fifowp = std_logic_vector'("1011")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("1011"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("1011"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_11 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_11_enable) = '1' then
fifo_11 <= fifo_11_mux;
end if;
end if;
end process;
fifo_11_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1011")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1011")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1011")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1011")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1011")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1011")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_12_enable <= (((to_std_logic(((fifowp = std_logic_vector'("1100")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("1100"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("1100"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_12 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_12_enable) = '1' then
fifo_12 <= fifo_12_mux;
end if;
end if;
end process;
fifo_12_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1100")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1100")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1100")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1100")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1100")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1100")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_13_enable <= (((to_std_logic(((fifowp = std_logic_vector'("1101")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("1101"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("1101"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_13 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_13_enable) = '1' then
fifo_13 <= fifo_13_mux;
end if;
end if;
end process;
fifo_13_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1101")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1101")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1101")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1101")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1101")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1101")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_14_enable <= (((to_std_logic(((fifowp = std_logic_vector'("1110")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("1110"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("1110"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_14 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_14_enable) = '1' then
fifo_14 <= fifo_14_mux;
end if;
end if;
end process;
fifo_14_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1110")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1110")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1110")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1110")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1110")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1110")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_15_enable <= (((to_std_logic(((fifowp = std_logic_vector'("1111")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("1111"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("1111"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_15 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_15_enable) = '1' then
fifo_15 <= fifo_15_mux;
end if;
end if;
end process;
fifo_15_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1111")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1111")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1111")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1111")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1111")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1111")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
tm_count_ge1 <= or_reduce(tm_count);
tm_count_ge2 <= tm_count(1);
tm_count_ge3 <= and_reduce(tm_count);
ovr_pending_atm <= Std_Logic_Vector'(A_ToStdLogicVector(ovf_pending) & atm(34 DOWNTO 0));
ovr_pending_dtm <= Std_Logic_Vector'(A_ToStdLogicVector(ovf_pending) & dtm(34 DOWNTO 0));
fifo_read_mux <= A_WE_StdLogicVector(((fiforp = std_logic_vector'("0000"))), fifo_0, A_WE_StdLogicVector(((fiforp = std_logic_vector'("0001"))), fifo_1, A_WE_StdLogicVector(((fiforp = std_logic_vector'("0010"))), fifo_2, A_WE_StdLogicVector(((fiforp = std_logic_vector'("0011"))), fifo_3, A_WE_StdLogicVector(((fiforp = std_logic_vector'("0100"))), fifo_4, A_WE_StdLogicVector(((fiforp = std_logic_vector'("0101"))), fifo_5, A_WE_StdLogicVector(((fiforp = std_logic_vector'("0110"))), fifo_6, A_WE_StdLogicVector(((fiforp = std_logic_vector'("0111"))), fifo_7, A_WE_StdLogicVector(((fiforp = std_logic_vector'("1000"))), fifo_8, A_WE_StdLogicVector(((fiforp = std_logic_vector'("1001"))), fifo_9, A_WE_StdLogicVector(((fiforp = std_logic_vector'("1010"))), fifo_10, A_WE_StdLogicVector(((fiforp = std_logic_vector'("1011"))), fifo_11, A_WE_StdLogicVector(((fiforp = std_logic_vector'("1100"))), fifo_12, A_WE_StdLogicVector(((fiforp = std_logic_vector'("1101"))), fifo_13, A_WE_StdLogicVector(((fiforp = std_logic_vector'("1110"))), fifo_14, fifo_15)))))))))))))));
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_pib is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal clkx2 : IN STD_LOGIC;
signal jrst_n : IN STD_LOGIC;
signal tw : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
-- outputs:
signal tr_clk : OUT STD_LOGIC;
signal tr_data : OUT STD_LOGIC_VECTOR (17 DOWNTO 0)
);
end entity Video_System_CPU_nios2_oci_pib;
architecture europa of Video_System_CPU_nios2_oci_pib is
signal phase : STD_LOGIC;
signal tr_clk_reg : STD_LOGIC;
signal tr_data_reg : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal x1 : STD_LOGIC;
signal x2 : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of tr_clk_reg : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of tr_data_reg : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of x1 : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of x2 : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
begin
phase <= x1 XOR x2;
process (clk, jrst_n)
begin
if jrst_n = '0' then
x1 <= std_logic'('0');
elsif clk'event and clk = '1' then
x1 <= NOT x1;
end if;
end process;
process (clkx2, jrst_n)
begin
if jrst_n = '0' then
x2 <= std_logic'('0');
tr_clk_reg <= std_logic'('0');
tr_data_reg <= std_logic_vector'("000000000000000000");
elsif clkx2'event and clkx2 = '1' then
x2 <= x1;
tr_clk_reg <= NOT phase;
tr_data_reg <= A_WE_StdLogicVector((std_logic'(phase) = '1'), tw(17 DOWNTO 0), tw(35 DOWNTO 18));
end if;
end process;
tr_clk <= Vector_To_Std_Logic(A_WE_StdLogicVector(((std_logic_vector'("00000000000000000000000000000000")) /= std_logic_vector'("00000000000000000000000000000000")), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(tr_clk_reg))), std_logic_vector'("00000000000000000000000000000000")));
tr_data <= A_EXT (A_WE_StdLogicVector(((std_logic_vector'("00000000000000000000000000000000")) /= std_logic_vector'("00000000000000000000000000000000")), (std_logic_vector'("00000000000000") & (tr_data_reg)), std_logic_vector'("00000000000000000000000000000000")), 18);
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.all;
entity Video_System_CPU_traceram_lpm_dram_bdp_component_module is
generic (
lpm_file : STRING := "UNUSED"
);
port (
-- inputs:
signal address_a : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal address_b : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal clock0 : IN STD_LOGIC;
signal clock1 : IN STD_LOGIC;
signal clocken0 : IN STD_LOGIC;
signal clocken1 : IN STD_LOGIC;
signal data_a : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal data_b : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal wren_a : IN STD_LOGIC;
signal wren_b : IN STD_LOGIC;
-- outputs:
signal q_a : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal q_b : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end entity Video_System_CPU_traceram_lpm_dram_bdp_component_module;
architecture europa of Video_System_CPU_traceram_lpm_dram_bdp_component_module is
component altsyncram is
GENERIC (
address_aclr_a : STRING;
address_aclr_b : STRING;
address_reg_b : STRING;
indata_aclr_a : STRING;
indata_aclr_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
ram_block_type : STRING;
read_during_write_mode_mixed_ports : STRING;
width_a : NATURAL;
width_b : NATURAL;
widthad_a : NATURAL;
widthad_b : NATURAL;
wrcontrol_aclr_a : STRING;
wrcontrol_aclr_b : STRING
);
PORT (
signal q_b : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal q_a : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal wren_a : IN STD_LOGIC;
signal data_b : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal clock0 : IN STD_LOGIC;
signal clocken0 : IN STD_LOGIC;
signal clocken1 : IN STD_LOGIC;
signal clock1 : IN STD_LOGIC;
signal wren_b : IN STD_LOGIC;
signal address_a : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal address_b : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal data_a : IN STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end component altsyncram;
signal internal_q_a1 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal internal_q_b1 : STD_LOGIC_VECTOR (35 DOWNTO 0);
begin
the_altsyncram : altsyncram
generic map(
address_aclr_a => "NONE",
address_aclr_b => "NONE",
address_reg_b => "CLOCK1",
indata_aclr_a => "NONE",
indata_aclr_b => "NONE",
init_file => lpm_file,
intended_device_family => "CYCLONEII",
lpm_type => "altsyncram",
numwords_a => 128,
numwords_b => 128,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
ram_block_type => "AUTO",
read_during_write_mode_mixed_ports => "OLD_DATA",
width_a => 36,
width_b => 36,
widthad_a => 7,
widthad_b => 7,
wrcontrol_aclr_a => "NONE",
wrcontrol_aclr_b => "NONE"
)
port map(
address_a => address_a,
address_b => address_b,
clock0 => clock0,
clock1 => clock1,
clocken0 => clocken0,
clocken1 => clocken1,
data_a => data_a,
data_b => data_b,
q_a => internal_q_a1,
q_b => internal_q_b1,
wren_a => wren_a,
wren_b => wren_b
);
--vhdl renameroo for output signals
q_a <= internal_q_a1;
--vhdl renameroo for output signals
q_b <= internal_q_b1;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_im is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal jdo : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal take_action_tracectrl : IN STD_LOGIC;
signal take_action_tracemem_a : IN STD_LOGIC;
signal take_action_tracemem_b : IN STD_LOGIC;
signal take_no_action_tracemem_a : IN STD_LOGIC;
signal trc_ctrl : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal tw : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
-- outputs:
signal tracemem_on : OUT STD_LOGIC;
signal tracemem_trcdata : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tracemem_tw : OUT STD_LOGIC;
signal trc_enb : OUT STD_LOGIC;
signal trc_im_addr : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
signal trc_wrap : OUT STD_LOGIC;
signal xbrk_wrap_traceoff : OUT STD_LOGIC
);
end entity Video_System_CPU_nios2_oci_im;
architecture europa of Video_System_CPU_nios2_oci_im is
component Video_System_CPU_traceram_lpm_dram_bdp_component_module is
generic (
lpm_file : STRING := "UNUSED"
);
port (
-- inputs:
signal address_a : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal address_b : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal clock0 : IN STD_LOGIC;
signal clock1 : IN STD_LOGIC;
signal clocken0 : IN STD_LOGIC;
signal clocken1 : IN STD_LOGIC;
signal data_a : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal data_b : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal wren_a : IN STD_LOGIC;
signal wren_b : IN STD_LOGIC;
-- outputs:
signal q_a : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal q_b : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end component Video_System_CPU_traceram_lpm_dram_bdp_component_module;
signal internal_trc_enb : STD_LOGIC;
signal internal_trc_im_addr : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal internal_trc_wrap : STD_LOGIC;
signal module_input10 : STD_LOGIC;
signal module_input7 : STD_LOGIC;
signal module_input8 : STD_LOGIC;
signal module_input9 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal trc_im_data : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal trc_jtag_addr : STD_LOGIC_VECTOR (16 DOWNTO 0);
signal trc_jtag_data : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal trc_on_chip : STD_LOGIC;
signal tw_valid : STD_LOGIC;
signal unused_bdpram_port_q_a : STD_LOGIC_VECTOR (35 DOWNTO 0);
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of trc_im_addr : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103,R101""";
attribute ALTERA_ATTRIBUTE of trc_jtag_addr : signal is "SUPPRESS_DA_RULE_INTERNAL=D101";
attribute ALTERA_ATTRIBUTE of trc_wrap : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103,R101""";
constant Video_System_CPU_traceram_lpm_dram_bdp_component_lpm_file : string := "";
begin
trc_im_data <= tw;
process (clk, jrst_n)
begin
if jrst_n = '0' then
internal_trc_im_addr <= std_logic_vector'("0000000");
internal_trc_wrap <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(NOT(or_reduce(std_logic_vector'("00000000000000000000000000000000")))) = '1' then
internal_trc_im_addr <= std_logic_vector'("0000000");
internal_trc_wrap <= std_logic'('0');
elsif std_logic'((take_action_tracectrl AND ((jdo(4) OR jdo(3))))) = '1' then
if std_logic'(jdo(4)) = '1' then
internal_trc_im_addr <= std_logic_vector'("0000000");
end if;
if std_logic'(jdo(3)) = '1' then
internal_trc_wrap <= std_logic'('0');
end if;
elsif std_logic'(((internal_trc_enb AND trc_on_chip) AND tw_valid)) = '1' then
internal_trc_im_addr <= A_EXT (((std_logic_vector'("00000000000000000000000000") & (internal_trc_im_addr)) + std_logic_vector'("000000000000000000000000000000001")), 7);
if std_logic'(and_reduce(internal_trc_im_addr)) = '1' then
internal_trc_wrap <= std_logic'('1');
end if;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
trc_jtag_addr <= std_logic_vector'("00000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(((take_action_tracemem_a OR take_no_action_tracemem_a) OR take_action_tracemem_b)) = '1' then
trc_jtag_addr <= A_EXT (A_WE_StdLogicVector((std_logic'(take_action_tracemem_a) = '1'), (std_logic_vector'("0000000000000000") & (jdo(35 DOWNTO 19))), ((std_logic_vector'("0000000000000000") & (trc_jtag_addr)) + std_logic_vector'("000000000000000000000000000000001"))), 17);
end if;
end if;
end process;
internal_trc_enb <= trc_ctrl(0);
trc_on_chip <= NOT trc_ctrl(8);
tw_valid <= or_reduce(trc_im_data(35 DOWNTO 32));
xbrk_wrap_traceoff <= trc_ctrl(10) AND internal_trc_wrap;
tracemem_trcdata <= A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000000000"))) /= std_logic_vector'("00000000000000000000000000000000")), trc_jtag_data, std_logic_vector'("000000000000000000000000000000000000"));
tracemem_tw <= internal_trc_wrap;
tracemem_on <= internal_trc_enb;
--Video_System_CPU_traceram_lpm_dram_bdp_component, which is an nios_tdp_ram
Video_System_CPU_traceram_lpm_dram_bdp_component : Video_System_CPU_traceram_lpm_dram_bdp_component_module
generic map(
lpm_file => Video_System_CPU_traceram_lpm_dram_bdp_component_lpm_file
)
port map(
q_a => unused_bdpram_port_q_a,
q_b => trc_jtag_data,
address_a => internal_trc_im_addr,
address_b => trc_jtag_addr (6 DOWNTO 0),
clock0 => clk,
clock1 => clk,
clocken0 => module_input7,
clocken1 => module_input8,
data_a => trc_im_data,
data_b => module_input9,
wren_a => module_input10,
wren_b => take_action_tracemem_b
);
module_input7 <= std_logic'('1');
module_input8 <= std_logic'('1');
module_input9 <= jdo(36 DOWNTO 1);
module_input10 <= tw_valid AND internal_trc_enb;
--vhdl renameroo for output signals
trc_enb <= internal_trc_enb;
--vhdl renameroo for output signals
trc_im_addr <= internal_trc_im_addr;
--vhdl renameroo for output signals
trc_wrap <= internal_trc_wrap;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_performance_monitors is
end entity Video_System_CPU_nios2_performance_monitors;
architecture europa of Video_System_CPU_nios2_performance_monitors is
begin
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci is
port (
-- inputs:
signal D_valid : IN STD_LOGIC;
signal E_st_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_valid : IN STD_LOGIC;
signal F_pc : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
signal address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
signal av_ld_data_aligned_filtered : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal begintransfer : IN STD_LOGIC;
signal byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal chipselect : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal d_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal d_read : IN STD_LOGIC;
signal d_waitrequest : IN STD_LOGIC;
signal d_write : IN STD_LOGIC;
signal debugaccess : IN STD_LOGIC;
signal hbreak_enabled : IN STD_LOGIC;
signal reset : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal test_ending : IN STD_LOGIC;
signal test_has_ended : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal jtag_debug_module_debugaccess_to_roms : OUT STD_LOGIC;
signal oci_hbreak_req : OUT STD_LOGIC;
signal oci_ienable : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oci_single_step_mode : OUT STD_LOGIC;
signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal resetrequest : OUT STD_LOGIC
);
end entity Video_System_CPU_nios2_oci;
architecture europa of Video_System_CPU_nios2_oci is
component Video_System_CPU_nios2_oci_debug is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dbrk_break : IN STD_LOGIC;
signal debugreq : IN STD_LOGIC;
signal hbreak_enabled : IN STD_LOGIC;
signal jdo : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal ocireg_ers : IN STD_LOGIC;
signal ocireg_mrs : IN STD_LOGIC;
signal reset : IN STD_LOGIC;
signal st_ready_test_idle : IN STD_LOGIC;
signal take_action_ocimem_a : IN STD_LOGIC;
signal take_action_ocireg : IN STD_LOGIC;
signal xbrk_break : IN STD_LOGIC;
-- outputs:
signal debugack : OUT STD_LOGIC;
signal monitor_error : OUT STD_LOGIC;
signal monitor_go : OUT STD_LOGIC;
signal monitor_ready : OUT STD_LOGIC;
signal oci_hbreak_req : OUT STD_LOGIC;
signal resetlatch : OUT STD_LOGIC;
signal resetrequest : OUT STD_LOGIC
);
end component Video_System_CPU_nios2_oci_debug;
component Video_System_CPU_nios2_ocimem is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
signal begintransfer : IN STD_LOGIC;
signal byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal chipselect : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal debugaccess : IN STD_LOGIC;
signal jdo : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal resetrequest : IN STD_LOGIC;
signal take_action_ocimem_a : IN STD_LOGIC;
signal take_action_ocimem_b : IN STD_LOGIC;
signal take_no_action_ocimem_a : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal MonDReg : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oci_ram_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component Video_System_CPU_nios2_ocimem;
component Video_System_CPU_nios2_avalon_reg is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
signal chipselect : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal debugaccess : IN STD_LOGIC;
signal monitor_error : IN STD_LOGIC;
signal monitor_go : IN STD_LOGIC;
signal monitor_ready : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal oci_ienable : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oci_reg_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oci_single_step_mode : OUT STD_LOGIC;
signal ocireg_ers : OUT STD_LOGIC;
signal ocireg_mrs : OUT STD_LOGIC;
signal take_action_ocireg : OUT STD_LOGIC
);
end component Video_System_CPU_nios2_avalon_reg;
component Video_System_CPU_nios2_oci_break is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dbrk_break : IN STD_LOGIC;
signal dbrk_goto0 : IN STD_LOGIC;
signal dbrk_goto1 : IN STD_LOGIC;
signal jdo : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal take_action_break_a : IN STD_LOGIC;
signal take_action_break_b : IN STD_LOGIC;
signal take_action_break_c : IN STD_LOGIC;
signal take_no_action_break_a : IN STD_LOGIC;
signal take_no_action_break_b : IN STD_LOGIC;
signal take_no_action_break_c : IN STD_LOGIC;
signal xbrk_goto0 : IN STD_LOGIC;
signal xbrk_goto1 : IN STD_LOGIC;
-- outputs:
signal break_readreg : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dbrk_hit0_latch : OUT STD_LOGIC;
signal dbrk_hit1_latch : OUT STD_LOGIC;
signal dbrk_hit2_latch : OUT STD_LOGIC;
signal dbrk_hit3_latch : OUT STD_LOGIC;
signal trigbrktype : OUT STD_LOGIC;
signal trigger_state_0 : OUT STD_LOGIC;
signal trigger_state_1 : OUT STD_LOGIC;
signal xbrk_ctrl0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl2 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl3 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component Video_System_CPU_nios2_oci_break;
component Video_System_CPU_nios2_oci_xbrk is
port (
-- inputs:
signal D_valid : IN STD_LOGIC;
signal E_valid : IN STD_LOGIC;
signal F_pc : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal trigger_state_0 : IN STD_LOGIC;
signal trigger_state_1 : IN STD_LOGIC;
signal xbrk_ctrl0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl2 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl3 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- outputs:
signal xbrk_break : OUT STD_LOGIC;
signal xbrk_goto0 : OUT STD_LOGIC;
signal xbrk_goto1 : OUT STD_LOGIC;
signal xbrk_traceoff : OUT STD_LOGIC;
signal xbrk_traceon : OUT STD_LOGIC;
signal xbrk_trigout : OUT STD_LOGIC
);
end component Video_System_CPU_nios2_oci_xbrk;
component Video_System_CPU_nios2_oci_dbrk is
port (
-- inputs:
signal E_st_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal av_ld_data_aligned_filtered : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal d_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal d_read : IN STD_LOGIC;
signal d_waitrequest : IN STD_LOGIC;
signal d_write : IN STD_LOGIC;
signal debugack : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal cpu_d_address : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
signal cpu_d_read : OUT STD_LOGIC;
signal cpu_d_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal cpu_d_wait : OUT STD_LOGIC;
signal cpu_d_write : OUT STD_LOGIC;
signal cpu_d_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dbrk_break : OUT STD_LOGIC;
signal dbrk_goto0 : OUT STD_LOGIC;
signal dbrk_goto1 : OUT STD_LOGIC;
signal dbrk_traceme : OUT STD_LOGIC;
signal dbrk_traceoff : OUT STD_LOGIC;
signal dbrk_traceon : OUT STD_LOGIC;
signal dbrk_trigout : OUT STD_LOGIC
);
end component Video_System_CPU_nios2_oci_dbrk;
component Video_System_CPU_nios2_oci_itrace is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dbrk_traceoff : IN STD_LOGIC;
signal dbrk_traceon : IN STD_LOGIC;
signal jdo : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal take_action_tracectrl : IN STD_LOGIC;
signal trc_enb : IN STD_LOGIC;
signal xbrk_traceoff : IN STD_LOGIC;
signal xbrk_traceon : IN STD_LOGIC;
signal xbrk_wrap_traceoff : IN STD_LOGIC;
-- outputs:
signal dct_buffer : OUT STD_LOGIC_VECTOR (29 DOWNTO 0);
signal dct_count : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal itm : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal trc_ctrl : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal trc_on : OUT STD_LOGIC
);
end component Video_System_CPU_nios2_oci_itrace;
component Video_System_CPU_nios2_oci_dtrace is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal cpu_d_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal cpu_d_read : IN STD_LOGIC;
signal cpu_d_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal cpu_d_wait : IN STD_LOGIC;
signal cpu_d_write : IN STD_LOGIC;
signal cpu_d_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal trc_ctrl : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- outputs:
signal atm : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal dtm : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end component Video_System_CPU_nios2_oci_dtrace;
component Video_System_CPU_nios2_oci_fifo is
port (
-- inputs:
signal atm : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal dbrk_traceme : IN STD_LOGIC;
signal dbrk_traceoff : IN STD_LOGIC;
signal dbrk_traceon : IN STD_LOGIC;
signal dct_buffer : IN STD_LOGIC_VECTOR (29 DOWNTO 0);
signal dct_count : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dtm : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal itm : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal test_ending : IN STD_LOGIC;
signal test_has_ended : IN STD_LOGIC;
signal trc_on : IN STD_LOGIC;
-- outputs:
signal tw : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end component Video_System_CPU_nios2_oci_fifo;
component Video_System_CPU_nios2_oci_pib is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal clkx2 : IN STD_LOGIC;
signal jrst_n : IN STD_LOGIC;
signal tw : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
-- outputs:
signal tr_clk : OUT STD_LOGIC;
signal tr_data : OUT STD_LOGIC_VECTOR (17 DOWNTO 0)
);
end component Video_System_CPU_nios2_oci_pib;
component Video_System_CPU_nios2_oci_im is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal jdo : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal take_action_tracectrl : IN STD_LOGIC;
signal take_action_tracemem_a : IN STD_LOGIC;
signal take_action_tracemem_b : IN STD_LOGIC;
signal take_no_action_tracemem_a : IN STD_LOGIC;
signal trc_ctrl : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal tw : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
-- outputs:
signal tracemem_on : OUT STD_LOGIC;
signal tracemem_trcdata : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tracemem_tw : OUT STD_LOGIC;
signal trc_enb : OUT STD_LOGIC;
signal trc_im_addr : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
signal trc_wrap : OUT STD_LOGIC;
signal xbrk_wrap_traceoff : OUT STD_LOGIC
);
end component Video_System_CPU_nios2_oci_im;
component Video_System_CPU_nios2_performance_monitors is
end component Video_System_CPU_nios2_performance_monitors;
component Video_System_CPU_jtag_debug_module_wrapper is
port (
-- inputs:
signal MonDReg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal break_readreg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal dbrk_hit0_latch : IN STD_LOGIC;
signal dbrk_hit1_latch : IN STD_LOGIC;
signal dbrk_hit2_latch : IN STD_LOGIC;
signal dbrk_hit3_latch : IN STD_LOGIC;
signal debugack : IN STD_LOGIC;
signal monitor_error : IN STD_LOGIC;
signal monitor_ready : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal resetlatch : IN STD_LOGIC;
signal tracemem_on : IN STD_LOGIC;
signal tracemem_trcdata : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tracemem_tw : IN STD_LOGIC;
signal trc_im_addr : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal trc_on : IN STD_LOGIC;
signal trc_wrap : IN STD_LOGIC;
signal trigbrktype : IN STD_LOGIC;
signal trigger_state_1 : IN STD_LOGIC;
-- outputs:
signal jdo : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : OUT STD_LOGIC;
signal st_ready_test_idle : OUT STD_LOGIC;
signal take_action_break_a : OUT STD_LOGIC;
signal take_action_break_b : OUT STD_LOGIC;
signal take_action_break_c : OUT STD_LOGIC;
signal take_action_ocimem_a : OUT STD_LOGIC;
signal take_action_ocimem_b : OUT STD_LOGIC;
signal take_action_tracectrl : OUT STD_LOGIC;
signal take_action_tracemem_a : OUT STD_LOGIC;
signal take_action_tracemem_b : OUT STD_LOGIC;
signal take_no_action_break_a : OUT STD_LOGIC;
signal take_no_action_break_b : OUT STD_LOGIC;
signal take_no_action_break_c : OUT STD_LOGIC;
signal take_no_action_ocimem_a : OUT STD_LOGIC;
signal take_no_action_tracemem_a : OUT STD_LOGIC
);
end component Video_System_CPU_jtag_debug_module_wrapper;
signal MonDReg : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal atm : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal break_readreg : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal clkx2 : STD_LOGIC;
signal cpu_d_address : STD_LOGIC_VECTOR (19 DOWNTO 0);
signal cpu_d_read : STD_LOGIC;
signal cpu_d_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal cpu_d_wait : STD_LOGIC;
signal cpu_d_write : STD_LOGIC;
signal cpu_d_writedata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dbrk_break : STD_LOGIC;
signal dbrk_goto0 : STD_LOGIC;
signal dbrk_goto1 : STD_LOGIC;
signal dbrk_hit0_latch : STD_LOGIC;
signal dbrk_hit1_latch : STD_LOGIC;
signal dbrk_hit2_latch : STD_LOGIC;
signal dbrk_hit3_latch : STD_LOGIC;
signal dbrk_traceme : STD_LOGIC;
signal dbrk_traceoff : STD_LOGIC;
signal dbrk_traceon : STD_LOGIC;
signal dbrk_trigout : STD_LOGIC;
signal dct_buffer : STD_LOGIC_VECTOR (29 DOWNTO 0);
signal dct_count : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal debugack : STD_LOGIC;
signal debugreq : STD_LOGIC;
signal dtm : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal dummy_sink : STD_LOGIC;
signal internal_oci_hbreak_req : STD_LOGIC;
signal internal_oci_ienable : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_oci_single_step_mode : STD_LOGIC;
signal internal_resetrequest : STD_LOGIC;
signal itm : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal jdo : STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : STD_LOGIC;
signal monitor_error : STD_LOGIC;
signal monitor_go : STD_LOGIC;
signal monitor_ready : STD_LOGIC;
signal oci_ram_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oci_reg_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ocireg_ers : STD_LOGIC;
signal ocireg_mrs : STD_LOGIC;
signal resetlatch : STD_LOGIC;
signal st_ready_test_idle : STD_LOGIC;
signal take_action_break_a : STD_LOGIC;
signal take_action_break_b : STD_LOGIC;
signal take_action_break_c : STD_LOGIC;
signal take_action_ocimem_a : STD_LOGIC;
signal take_action_ocimem_b : STD_LOGIC;
signal take_action_ocireg : STD_LOGIC;
signal take_action_tracectrl : STD_LOGIC;
signal take_action_tracemem_a : STD_LOGIC;
signal take_action_tracemem_b : STD_LOGIC;
signal take_no_action_break_a : STD_LOGIC;
signal take_no_action_break_b : STD_LOGIC;
signal take_no_action_break_c : STD_LOGIC;
signal take_no_action_ocimem_a : STD_LOGIC;
signal take_no_action_tracemem_a : STD_LOGIC;
signal tr_clk : STD_LOGIC;
signal tr_data : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal tracemem_on : STD_LOGIC;
signal tracemem_trcdata : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tracemem_tw : STD_LOGIC;
signal trc_ctrl : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal trc_enb : STD_LOGIC;
signal trc_im_addr : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal trc_on : STD_LOGIC;
signal trc_wrap : STD_LOGIC;
signal trigbrktype : STD_LOGIC;
signal trigger_state_0 : STD_LOGIC;
signal trigger_state_1 : STD_LOGIC;
signal trigout : STD_LOGIC;
signal tw : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal xbrk_break : STD_LOGIC;
signal xbrk_ctrl0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl2 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl3 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_goto0 : STD_LOGIC;
signal xbrk_goto1 : STD_LOGIC;
signal xbrk_traceoff : STD_LOGIC;
signal xbrk_traceon : STD_LOGIC;
signal xbrk_trigout : STD_LOGIC;
signal xbrk_wrap_traceoff : STD_LOGIC;
begin
--the_Video_System_CPU_nios2_oci_debug, which is an e_instance
the_Video_System_CPU_nios2_oci_debug : Video_System_CPU_nios2_oci_debug
port map(
debugack => debugack,
monitor_error => monitor_error,
monitor_go => monitor_go,
monitor_ready => monitor_ready,
oci_hbreak_req => internal_oci_hbreak_req,
resetlatch => resetlatch,
resetrequest => internal_resetrequest,
clk => clk,
dbrk_break => dbrk_break,
debugreq => debugreq,
hbreak_enabled => hbreak_enabled,
jdo => jdo,
jrst_n => jrst_n,
ocireg_ers => ocireg_ers,
ocireg_mrs => ocireg_mrs,
reset => reset,
st_ready_test_idle => st_ready_test_idle,
take_action_ocimem_a => take_action_ocimem_a,
take_action_ocireg => take_action_ocireg,
xbrk_break => xbrk_break
);
--the_Video_System_CPU_nios2_ocimem, which is an e_instance
the_Video_System_CPU_nios2_ocimem : Video_System_CPU_nios2_ocimem
port map(
MonDReg => MonDReg,
oci_ram_readdata => oci_ram_readdata,
address => address,
begintransfer => begintransfer,
byteenable => byteenable,
chipselect => chipselect,
clk => clk,
debugaccess => debugaccess,
jdo => jdo,
jrst_n => jrst_n,
resetrequest => internal_resetrequest,
take_action_ocimem_a => take_action_ocimem_a,
take_action_ocimem_b => take_action_ocimem_b,
take_no_action_ocimem_a => take_no_action_ocimem_a,
write => write,
writedata => writedata
);
--the_Video_System_CPU_nios2_avalon_reg, which is an e_instance
the_Video_System_CPU_nios2_avalon_reg : Video_System_CPU_nios2_avalon_reg
port map(
oci_ienable => internal_oci_ienable,
oci_reg_readdata => oci_reg_readdata,
oci_single_step_mode => internal_oci_single_step_mode,
ocireg_ers => ocireg_ers,
ocireg_mrs => ocireg_mrs,
take_action_ocireg => take_action_ocireg,
address => address,
chipselect => chipselect,
clk => clk,
debugaccess => debugaccess,
monitor_error => monitor_error,
monitor_go => monitor_go,
monitor_ready => monitor_ready,
reset_n => reset_n,
write => write,
writedata => writedata
);
--the_Video_System_CPU_nios2_oci_break, which is an e_instance
the_Video_System_CPU_nios2_oci_break : Video_System_CPU_nios2_oci_break
port map(
break_readreg => break_readreg,
dbrk_hit0_latch => dbrk_hit0_latch,
dbrk_hit1_latch => dbrk_hit1_latch,
dbrk_hit2_latch => dbrk_hit2_latch,
dbrk_hit3_latch => dbrk_hit3_latch,
trigbrktype => trigbrktype,
trigger_state_0 => trigger_state_0,
trigger_state_1 => trigger_state_1,
xbrk_ctrl0 => xbrk_ctrl0,
xbrk_ctrl1 => xbrk_ctrl1,
xbrk_ctrl2 => xbrk_ctrl2,
xbrk_ctrl3 => xbrk_ctrl3,
clk => clk,
dbrk_break => dbrk_break,
dbrk_goto0 => dbrk_goto0,
dbrk_goto1 => dbrk_goto1,
jdo => jdo,
jrst_n => jrst_n,
reset_n => reset_n,
take_action_break_a => take_action_break_a,
take_action_break_b => take_action_break_b,
take_action_break_c => take_action_break_c,
take_no_action_break_a => take_no_action_break_a,
take_no_action_break_b => take_no_action_break_b,
take_no_action_break_c => take_no_action_break_c,
xbrk_goto0 => xbrk_goto0,
xbrk_goto1 => xbrk_goto1
);
--the_Video_System_CPU_nios2_oci_xbrk, which is an e_instance
the_Video_System_CPU_nios2_oci_xbrk : Video_System_CPU_nios2_oci_xbrk
port map(
xbrk_break => xbrk_break,
xbrk_goto0 => xbrk_goto0,
xbrk_goto1 => xbrk_goto1,
xbrk_traceoff => xbrk_traceoff,
xbrk_traceon => xbrk_traceon,
xbrk_trigout => xbrk_trigout,
D_valid => D_valid,
E_valid => E_valid,
F_pc => F_pc,
clk => clk,
reset_n => reset_n,
trigger_state_0 => trigger_state_0,
trigger_state_1 => trigger_state_1,
xbrk_ctrl0 => xbrk_ctrl0,
xbrk_ctrl1 => xbrk_ctrl1,
xbrk_ctrl2 => xbrk_ctrl2,
xbrk_ctrl3 => xbrk_ctrl3
);
--the_Video_System_CPU_nios2_oci_dbrk, which is an e_instance
the_Video_System_CPU_nios2_oci_dbrk : Video_System_CPU_nios2_oci_dbrk
port map(
cpu_d_address => cpu_d_address,
cpu_d_read => cpu_d_read,
cpu_d_readdata => cpu_d_readdata,
cpu_d_wait => cpu_d_wait,
cpu_d_write => cpu_d_write,
cpu_d_writedata => cpu_d_writedata,
dbrk_break => dbrk_break,
dbrk_goto0 => dbrk_goto0,
dbrk_goto1 => dbrk_goto1,
dbrk_traceme => dbrk_traceme,
dbrk_traceoff => dbrk_traceoff,
dbrk_traceon => dbrk_traceon,
dbrk_trigout => dbrk_trigout,
E_st_data => E_st_data,
av_ld_data_aligned_filtered => av_ld_data_aligned_filtered,
clk => clk,
d_address => d_address,
d_read => d_read,
d_waitrequest => d_waitrequest,
d_write => d_write,
debugack => debugack,
reset_n => reset_n
);
--the_Video_System_CPU_nios2_oci_itrace, which is an e_instance
the_Video_System_CPU_nios2_oci_itrace : Video_System_CPU_nios2_oci_itrace
port map(
dct_buffer => dct_buffer,
dct_count => dct_count,
itm => itm,
trc_ctrl => trc_ctrl,
trc_on => trc_on,
clk => clk,
dbrk_traceoff => dbrk_traceoff,
dbrk_traceon => dbrk_traceon,
jdo => jdo (15 DOWNTO 0),
jrst_n => jrst_n,
take_action_tracectrl => take_action_tracectrl,
trc_enb => trc_enb,
xbrk_traceoff => xbrk_traceoff,
xbrk_traceon => xbrk_traceon,
xbrk_wrap_traceoff => xbrk_wrap_traceoff
);
--the_Video_System_CPU_nios2_oci_dtrace, which is an e_instance
the_Video_System_CPU_nios2_oci_dtrace : Video_System_CPU_nios2_oci_dtrace
port map(
atm => atm,
dtm => dtm,
clk => clk,
cpu_d_address => cpu_d_address,
cpu_d_read => cpu_d_read,
cpu_d_readdata => cpu_d_readdata,
cpu_d_wait => cpu_d_wait,
cpu_d_write => cpu_d_write,
cpu_d_writedata => cpu_d_writedata,
jrst_n => jrst_n,
trc_ctrl => trc_ctrl
);
--the_Video_System_CPU_nios2_oci_fifo, which is an e_instance
the_Video_System_CPU_nios2_oci_fifo : Video_System_CPU_nios2_oci_fifo
port map(
tw => tw,
atm => atm,
clk => clk,
dbrk_traceme => dbrk_traceme,
dbrk_traceoff => dbrk_traceoff,
dbrk_traceon => dbrk_traceon,
dct_buffer => dct_buffer,
dct_count => dct_count,
dtm => dtm,
itm => itm,
jrst_n => jrst_n,
reset_n => reset_n,
test_ending => test_ending,
test_has_ended => test_has_ended,
trc_on => trc_on
);
--the_Video_System_CPU_nios2_oci_pib, which is an e_instance
the_Video_System_CPU_nios2_oci_pib : Video_System_CPU_nios2_oci_pib
port map(
tr_clk => tr_clk,
tr_data => tr_data,
clk => clk,
clkx2 => clkx2,
jrst_n => jrst_n,
tw => tw
);
--the_Video_System_CPU_nios2_oci_im, which is an e_instance
the_Video_System_CPU_nios2_oci_im : Video_System_CPU_nios2_oci_im
port map(
tracemem_on => tracemem_on,
tracemem_trcdata => tracemem_trcdata,
tracemem_tw => tracemem_tw,
trc_enb => trc_enb,
trc_im_addr => trc_im_addr,
trc_wrap => trc_wrap,
xbrk_wrap_traceoff => xbrk_wrap_traceoff,
clk => clk,
jdo => jdo,
jrst_n => jrst_n,
reset_n => reset_n,
take_action_tracectrl => take_action_tracectrl,
take_action_tracemem_a => take_action_tracemem_a,
take_action_tracemem_b => take_action_tracemem_b,
take_no_action_tracemem_a => take_no_action_tracemem_a,
trc_ctrl => trc_ctrl,
tw => tw
);
trigout <= dbrk_trigout OR xbrk_trigout;
readdata <= A_WE_StdLogicVector((std_logic'(address(8)) = '1'), oci_reg_readdata, oci_ram_readdata);
jtag_debug_module_debugaccess_to_roms <= debugack;
--the_Video_System_CPU_jtag_debug_module_wrapper, which is an e_instance
the_Video_System_CPU_jtag_debug_module_wrapper : Video_System_CPU_jtag_debug_module_wrapper
port map(
jdo => jdo,
jrst_n => jrst_n,
st_ready_test_idle => st_ready_test_idle,
take_action_break_a => take_action_break_a,
take_action_break_b => take_action_break_b,
take_action_break_c => take_action_break_c,
take_action_ocimem_a => take_action_ocimem_a,
take_action_ocimem_b => take_action_ocimem_b,
take_action_tracectrl => take_action_tracectrl,
take_action_tracemem_a => take_action_tracemem_a,
take_action_tracemem_b => take_action_tracemem_b,
take_no_action_break_a => take_no_action_break_a,
take_no_action_break_b => take_no_action_break_b,
take_no_action_break_c => take_no_action_break_c,
take_no_action_ocimem_a => take_no_action_ocimem_a,
take_no_action_tracemem_a => take_no_action_tracemem_a,
MonDReg => MonDReg,
break_readreg => break_readreg,
clk => clk,
dbrk_hit0_latch => dbrk_hit0_latch,
dbrk_hit1_latch => dbrk_hit1_latch,
dbrk_hit2_latch => dbrk_hit2_latch,
dbrk_hit3_latch => dbrk_hit3_latch,
debugack => debugack,
monitor_error => monitor_error,
monitor_ready => monitor_ready,
reset_n => reset_n,
resetlatch => resetlatch,
tracemem_on => tracemem_on,
tracemem_trcdata => tracemem_trcdata,
tracemem_tw => tracemem_tw,
trc_im_addr => trc_im_addr,
trc_on => trc_on,
trc_wrap => trc_wrap,
trigbrktype => trigbrktype,
trigger_state_1 => trigger_state_1
);
--dummy sink, which is an e_mux
dummy_sink <= Vector_To_Std_Logic(((((std_logic_vector'("00000000000000000") & (A_TOSTDLOGICVECTOR(tr_clk))) OR tr_data) OR (std_logic_vector'("00000000000000000") & (A_TOSTDLOGICVECTOR(trigout)))) OR (std_logic_vector'("00000000000000000") & (A_TOSTDLOGICVECTOR(debugack)))));
debugreq <= std_logic'('0');
clkx2 <= std_logic'('0');
--vhdl renameroo for output signals
oci_hbreak_req <= internal_oci_hbreak_req;
--vhdl renameroo for output signals
oci_ienable <= internal_oci_ienable;
--vhdl renameroo for output signals
oci_single_step_mode <= internal_oci_single_step_mode;
--vhdl renameroo for output signals
resetrequest <= internal_resetrequest;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal d_irq : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal d_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal d_waitrequest : IN STD_LOGIC;
signal i_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal i_waitrequest : IN STD_LOGIC;
signal jtag_debug_module_address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
signal jtag_debug_module_begintransfer : IN STD_LOGIC;
signal jtag_debug_module_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal jtag_debug_module_debugaccess : IN STD_LOGIC;
signal jtag_debug_module_select : IN STD_LOGIC;
signal jtag_debug_module_write : IN STD_LOGIC;
signal jtag_debug_module_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d_address : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
signal d_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal d_read : OUT STD_LOGIC;
signal d_write : OUT STD_LOGIC;
signal d_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal i_address : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
signal i_read : OUT STD_LOGIC;
signal jtag_debug_module_debugaccess_to_roms : OUT STD_LOGIC;
signal jtag_debug_module_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal jtag_debug_module_resetrequest : OUT STD_LOGIC;
signal no_ci_readra : OUT STD_LOGIC
);
end entity Video_System_CPU;
architecture europa of Video_System_CPU is
component Video_System_CPU_test_bench is
port (
-- inputs:
signal D_iw : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal D_iw_op : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
signal D_iw_opx : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
signal D_valid : IN STD_LOGIC;
signal E_alu_result : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_mem_byte_en : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal E_st_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_valid : IN STD_LOGIC;
signal F_pcb : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal F_valid : IN STD_LOGIC;
signal R_ctrl_exception : IN STD_LOGIC;
signal R_ctrl_ld : IN STD_LOGIC;
signal R_ctrl_ld_non_io : IN STD_LOGIC;
signal R_dst_regnum : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal R_wr_dst_reg : IN STD_LOGIC;
signal W_bstatus_reg : IN STD_LOGIC;
signal W_cmp_result : IN STD_LOGIC;
signal W_estatus_reg : IN STD_LOGIC;
signal W_ienable_reg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_ipending_reg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_mem_baddr : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal W_rf_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_status_reg : IN STD_LOGIC;
signal W_valid : IN STD_LOGIC;
signal W_vinst : IN STD_LOGIC_VECTOR (55 DOWNTO 0);
signal W_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal av_ld_data_aligned_unfiltered : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal d_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal d_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal d_read : IN STD_LOGIC;
signal d_write_nxt : IN STD_LOGIC;
signal i_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal i_read : IN STD_LOGIC;
signal i_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal i_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal av_ld_data_aligned_filtered : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal d_write : OUT STD_LOGIC;
signal test_has_ended : OUT STD_LOGIC
);
end component Video_System_CPU_test_bench;
component Video_System_CPU_register_bank_a_module is
generic (
lpm_file : STRING := "UNUSED"
);
port (
-- inputs:
signal clock : IN STD_LOGIC;
signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rdaddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal wraddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal wren : IN STD_LOGIC;
-- outputs:
signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component Video_System_CPU_register_bank_a_module;
component Video_System_CPU_register_bank_b_module is
generic (
lpm_file : STRING := "UNUSED"
);
port (
-- inputs:
signal clock : IN STD_LOGIC;
signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rdaddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal wraddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal wren : IN STD_LOGIC;
-- outputs:
signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component Video_System_CPU_register_bank_b_module;
component Video_System_CPU_nios2_oci is
port (
-- inputs:
signal D_valid : IN STD_LOGIC;
signal E_st_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_valid : IN STD_LOGIC;
signal F_pc : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
signal address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
signal av_ld_data_aligned_filtered : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal begintransfer : IN STD_LOGIC;
signal byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal chipselect : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal d_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal d_read : IN STD_LOGIC;
signal d_waitrequest : IN STD_LOGIC;
signal d_write : IN STD_LOGIC;
signal debugaccess : IN STD_LOGIC;
signal hbreak_enabled : IN STD_LOGIC;
signal reset : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal test_ending : IN STD_LOGIC;
signal test_has_ended : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal jtag_debug_module_debugaccess_to_roms : OUT STD_LOGIC;
signal oci_hbreak_req : OUT STD_LOGIC;
signal oci_ienable : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oci_single_step_mode : OUT STD_LOGIC;
signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal resetrequest : OUT STD_LOGIC
);
end component Video_System_CPU_nios2_oci;
signal D_compare_op : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal D_ctrl_alu_force_xor : STD_LOGIC;
signal D_ctrl_alu_signed_comparison : STD_LOGIC;
signal D_ctrl_alu_subtract : STD_LOGIC;
signal D_ctrl_b_is_dst : STD_LOGIC;
signal D_ctrl_br : STD_LOGIC;
signal D_ctrl_br_cmp : STD_LOGIC;
signal D_ctrl_br_uncond : STD_LOGIC;
signal D_ctrl_break : STD_LOGIC;
signal D_ctrl_crst : STD_LOGIC;
signal D_ctrl_custom : STD_LOGIC;
signal D_ctrl_custom_multi : STD_LOGIC;
signal D_ctrl_exception : STD_LOGIC;
signal D_ctrl_force_src2_zero : STD_LOGIC;
signal D_ctrl_hi_imm16 : STD_LOGIC;
signal D_ctrl_ignore_dst : STD_LOGIC;
signal D_ctrl_implicit_dst_eretaddr : STD_LOGIC;
signal D_ctrl_implicit_dst_retaddr : STD_LOGIC;
signal D_ctrl_jmp_direct : STD_LOGIC;
signal D_ctrl_jmp_indirect : STD_LOGIC;
signal D_ctrl_ld : STD_LOGIC;
signal D_ctrl_ld_io : STD_LOGIC;
signal D_ctrl_ld_non_io : STD_LOGIC;
signal D_ctrl_ld_signed : STD_LOGIC;
signal D_ctrl_logic : STD_LOGIC;
signal D_ctrl_rdctl_inst : STD_LOGIC;
signal D_ctrl_retaddr : STD_LOGIC;
signal D_ctrl_rot_right : STD_LOGIC;
signal D_ctrl_shift_logical : STD_LOGIC;
signal D_ctrl_shift_right_arith : STD_LOGIC;
signal D_ctrl_shift_rot : STD_LOGIC;
signal D_ctrl_shift_rot_right : STD_LOGIC;
signal D_ctrl_src2_choose_imm : STD_LOGIC;
signal D_ctrl_st : STD_LOGIC;
signal D_ctrl_uncond_cti_non_br : STD_LOGIC;
signal D_ctrl_unsigned_lo_imm16 : STD_LOGIC;
signal D_ctrl_wrctl_inst : STD_LOGIC;
signal D_dst_regnum : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal D_inst : STD_LOGIC_VECTOR (55 DOWNTO 0);
signal D_iw : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal D_iw_a : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal D_iw_b : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal D_iw_c : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal D_iw_control_regnum : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal D_iw_custom_n : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal D_iw_custom_readra : STD_LOGIC;
signal D_iw_custom_readrb : STD_LOGIC;
signal D_iw_custom_writerc : STD_LOGIC;
signal D_iw_imm16 : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal D_iw_imm26 : STD_LOGIC_VECTOR (25 DOWNTO 0);
signal D_iw_imm5 : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal D_iw_memsz : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal D_iw_op : STD_LOGIC_VECTOR (5 DOWNTO 0);
signal D_iw_opx : STD_LOGIC_VECTOR (5 DOWNTO 0);
signal D_iw_shift_imm5 : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal D_iw_trap_break_imm5 : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal D_jmp_direct_target_waddr : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal D_logic_op : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal D_logic_op_raw : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal D_mem16 : STD_LOGIC;
signal D_mem32 : STD_LOGIC;
signal D_mem8 : STD_LOGIC;
signal D_op_add : STD_LOGIC;
signal D_op_addi : STD_LOGIC;
signal D_op_and : STD_LOGIC;
signal D_op_andhi : STD_LOGIC;
signal D_op_andi : STD_LOGIC;
signal D_op_beq : STD_LOGIC;
signal D_op_bge : STD_LOGIC;
signal D_op_bgeu : STD_LOGIC;
signal D_op_blt : STD_LOGIC;
signal D_op_bltu : STD_LOGIC;
signal D_op_bne : STD_LOGIC;
signal D_op_br : STD_LOGIC;
signal D_op_break : STD_LOGIC;
signal D_op_bret : STD_LOGIC;
signal D_op_call : STD_LOGIC;
signal D_op_callr : STD_LOGIC;
signal D_op_cmpeq : STD_LOGIC;
signal D_op_cmpeqi : STD_LOGIC;
signal D_op_cmpge : STD_LOGIC;
signal D_op_cmpgei : STD_LOGIC;
signal D_op_cmpgeu : STD_LOGIC;
signal D_op_cmpgeui : STD_LOGIC;
signal D_op_cmplt : STD_LOGIC;
signal D_op_cmplti : STD_LOGIC;
signal D_op_cmpltu : STD_LOGIC;
signal D_op_cmpltui : STD_LOGIC;
signal D_op_cmpne : STD_LOGIC;
signal D_op_cmpnei : STD_LOGIC;
signal D_op_crst : STD_LOGIC;
signal D_op_custom : STD_LOGIC;
signal D_op_div : STD_LOGIC;
signal D_op_divu : STD_LOGIC;
signal D_op_eret : STD_LOGIC;
signal D_op_flushd : STD_LOGIC;
signal D_op_flushda : STD_LOGIC;
signal D_op_flushi : STD_LOGIC;
signal D_op_flushp : STD_LOGIC;
signal D_op_hbreak : STD_LOGIC;
signal D_op_initd : STD_LOGIC;
signal D_op_initda : STD_LOGIC;
signal D_op_initi : STD_LOGIC;
signal D_op_intr : STD_LOGIC;
signal D_op_jmp : STD_LOGIC;
signal D_op_jmpi : STD_LOGIC;
signal D_op_ldb : STD_LOGIC;
signal D_op_ldbio : STD_LOGIC;
signal D_op_ldbu : STD_LOGIC;
signal D_op_ldbuio : STD_LOGIC;
signal D_op_ldh : STD_LOGIC;
signal D_op_ldhio : STD_LOGIC;
signal D_op_ldhu : STD_LOGIC;
signal D_op_ldhuio : STD_LOGIC;
signal D_op_ldl : STD_LOGIC;
signal D_op_ldw : STD_LOGIC;
signal D_op_ldwio : STD_LOGIC;
signal D_op_mul : STD_LOGIC;
signal D_op_muli : STD_LOGIC;
signal D_op_mulxss : STD_LOGIC;
signal D_op_mulxsu : STD_LOGIC;
signal D_op_mulxuu : STD_LOGIC;
signal D_op_nextpc : STD_LOGIC;
signal D_op_nor : STD_LOGIC;
signal D_op_opx : STD_LOGIC;
signal D_op_or : STD_LOGIC;
signal D_op_orhi : STD_LOGIC;
signal D_op_ori : STD_LOGIC;
signal D_op_rdctl : STD_LOGIC;
signal D_op_rdprs : STD_LOGIC;
signal D_op_ret : STD_LOGIC;
signal D_op_rol : STD_LOGIC;
signal D_op_roli : STD_LOGIC;
signal D_op_ror : STD_LOGIC;
signal D_op_rsv02 : STD_LOGIC;
signal D_op_rsv09 : STD_LOGIC;
signal D_op_rsv10 : STD_LOGIC;
signal D_op_rsv17 : STD_LOGIC;
signal D_op_rsv18 : STD_LOGIC;
signal D_op_rsv25 : STD_LOGIC;
signal D_op_rsv26 : STD_LOGIC;
signal D_op_rsv33 : STD_LOGIC;
signal D_op_rsv34 : STD_LOGIC;
signal D_op_rsv41 : STD_LOGIC;
signal D_op_rsv42 : STD_LOGIC;
signal D_op_rsv49 : STD_LOGIC;
signal D_op_rsv57 : STD_LOGIC;
signal D_op_rsv61 : STD_LOGIC;
signal D_op_rsv62 : STD_LOGIC;
signal D_op_rsv63 : STD_LOGIC;
signal D_op_rsvx00 : STD_LOGIC;
signal D_op_rsvx10 : STD_LOGIC;
signal D_op_rsvx15 : STD_LOGIC;
signal D_op_rsvx17 : STD_LOGIC;
signal D_op_rsvx21 : STD_LOGIC;
signal D_op_rsvx25 : STD_LOGIC;
signal D_op_rsvx33 : STD_LOGIC;
signal D_op_rsvx34 : STD_LOGIC;
signal D_op_rsvx35 : STD_LOGIC;
signal D_op_rsvx42 : STD_LOGIC;
signal D_op_rsvx43 : STD_LOGIC;
signal D_op_rsvx44 : STD_LOGIC;
signal D_op_rsvx47 : STD_LOGIC;
signal D_op_rsvx50 : STD_LOGIC;
signal D_op_rsvx51 : STD_LOGIC;
signal D_op_rsvx55 : STD_LOGIC;
signal D_op_rsvx56 : STD_LOGIC;
signal D_op_rsvx60 : STD_LOGIC;
signal D_op_rsvx63 : STD_LOGIC;
signal D_op_sll : STD_LOGIC;
signal D_op_slli : STD_LOGIC;
signal D_op_sra : STD_LOGIC;
signal D_op_srai : STD_LOGIC;
signal D_op_srl : STD_LOGIC;
signal D_op_srli : STD_LOGIC;
signal D_op_stb : STD_LOGIC;
signal D_op_stbio : STD_LOGIC;
signal D_op_stc : STD_LOGIC;
signal D_op_sth : STD_LOGIC;
signal D_op_sthio : STD_LOGIC;
signal D_op_stw : STD_LOGIC;
signal D_op_stwio : STD_LOGIC;
signal D_op_sub : STD_LOGIC;
signal D_op_sync : STD_LOGIC;
signal D_op_trap : STD_LOGIC;
signal D_op_wrctl : STD_LOGIC;
signal D_op_wrprs : STD_LOGIC;
signal D_op_xor : STD_LOGIC;
signal D_op_xorhi : STD_LOGIC;
signal D_op_xori : STD_LOGIC;
signal D_valid : STD_LOGIC;
signal D_vinst : STD_LOGIC_VECTOR (55 DOWNTO 0);
signal D_wr_dst_reg : STD_LOGIC;
signal E_alu_result : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_alu_sub : STD_LOGIC;
signal E_arith_result : STD_LOGIC_VECTOR (32 DOWNTO 0);
signal E_arith_src1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_arith_src2 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_ci_multi_stall : STD_LOGIC;
signal E_ci_result : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_cmp_result : STD_LOGIC;
signal E_control_rd_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_eq : STD_LOGIC;
signal E_invert_arith_src_msb : STD_LOGIC;
signal E_ld_stall : STD_LOGIC;
signal E_logic_result : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_logic_result_is_0 : STD_LOGIC;
signal E_lt : STD_LOGIC;
signal E_mem_baddr : STD_LOGIC_VECTOR (19 DOWNTO 0);
signal E_mem_byte_en : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal E_new_inst : STD_LOGIC;
signal E_shift_rot_cnt : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal E_shift_rot_cnt_nxt : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal E_shift_rot_done : STD_LOGIC;
signal E_shift_rot_fill_bit : STD_LOGIC;
signal E_shift_rot_result : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_shift_rot_result_nxt : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_shift_rot_stall : STD_LOGIC;
signal E_src1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_src2 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_st_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_st_stall : STD_LOGIC;
signal E_stall : STD_LOGIC;
signal E_valid : STD_LOGIC;
signal E_vinst : STD_LOGIC_VECTOR (55 DOWNTO 0);
signal E_wrctl_bstatus : STD_LOGIC;
signal E_wrctl_estatus : STD_LOGIC;
signal E_wrctl_ienable : STD_LOGIC;
signal E_wrctl_status : STD_LOGIC;
signal F_av_iw : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal F_av_iw_a : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_av_iw_b : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_av_iw_c : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_av_iw_control_regnum : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal F_av_iw_custom_n : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal F_av_iw_custom_readra : STD_LOGIC;
signal F_av_iw_custom_readrb : STD_LOGIC;
signal F_av_iw_custom_writerc : STD_LOGIC;
signal F_av_iw_imm16 : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal F_av_iw_imm26 : STD_LOGIC_VECTOR (25 DOWNTO 0);
signal F_av_iw_imm5 : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_av_iw_memsz : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal F_av_iw_op : STD_LOGIC_VECTOR (5 DOWNTO 0);
signal F_av_iw_opx : STD_LOGIC_VECTOR (5 DOWNTO 0);
signal F_av_iw_shift_imm5 : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_av_iw_trap_break_imm5 : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_av_mem16 : STD_LOGIC;
signal F_av_mem32 : STD_LOGIC;
signal F_av_mem8 : STD_LOGIC;
signal F_inst : STD_LOGIC_VECTOR (55 DOWNTO 0);
signal F_iw : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal F_iw_a : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_iw_b : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_iw_c : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_iw_control_regnum : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal F_iw_custom_n : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal F_iw_custom_readra : STD_LOGIC;
signal F_iw_custom_readrb : STD_LOGIC;
signal F_iw_custom_writerc : STD_LOGIC;
signal F_iw_imm16 : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal F_iw_imm26 : STD_LOGIC_VECTOR (25 DOWNTO 0);
signal F_iw_imm5 : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_iw_memsz : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal F_iw_op : STD_LOGIC_VECTOR (5 DOWNTO 0);
signal F_iw_opx : STD_LOGIC_VECTOR (5 DOWNTO 0);
signal F_iw_shift_imm5 : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_iw_trap_break_imm5 : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_mem16 : STD_LOGIC;
signal F_mem32 : STD_LOGIC;
signal F_mem8 : STD_LOGIC;
signal F_op_add : STD_LOGIC;
signal F_op_addi : STD_LOGIC;
signal F_op_and : STD_LOGIC;
signal F_op_andhi : STD_LOGIC;
signal F_op_andi : STD_LOGIC;
signal F_op_beq : STD_LOGIC;
signal F_op_bge : STD_LOGIC;
signal F_op_bgeu : STD_LOGIC;
signal F_op_blt : STD_LOGIC;
signal F_op_bltu : STD_LOGIC;
signal F_op_bne : STD_LOGIC;
signal F_op_br : STD_LOGIC;
signal F_op_break : STD_LOGIC;
signal F_op_bret : STD_LOGIC;
signal F_op_call : STD_LOGIC;
signal F_op_callr : STD_LOGIC;
signal F_op_cmpeq : STD_LOGIC;
signal F_op_cmpeqi : STD_LOGIC;
signal F_op_cmpge : STD_LOGIC;
signal F_op_cmpgei : STD_LOGIC;
signal F_op_cmpgeu : STD_LOGIC;
signal F_op_cmpgeui : STD_LOGIC;
signal F_op_cmplt : STD_LOGIC;
signal F_op_cmplti : STD_LOGIC;
signal F_op_cmpltu : STD_LOGIC;
signal F_op_cmpltui : STD_LOGIC;
signal F_op_cmpne : STD_LOGIC;
signal F_op_cmpnei : STD_LOGIC;
signal F_op_crst : STD_LOGIC;
signal F_op_custom : STD_LOGIC;
signal F_op_div : STD_LOGIC;
signal F_op_divu : STD_LOGIC;
signal F_op_eret : STD_LOGIC;
signal F_op_flushd : STD_LOGIC;
signal F_op_flushda : STD_LOGIC;
signal F_op_flushi : STD_LOGIC;
signal F_op_flushp : STD_LOGIC;
signal F_op_hbreak : STD_LOGIC;
signal F_op_initd : STD_LOGIC;
signal F_op_initda : STD_LOGIC;
signal F_op_initi : STD_LOGIC;
signal F_op_intr : STD_LOGIC;
signal F_op_jmp : STD_LOGIC;
signal F_op_jmpi : STD_LOGIC;
signal F_op_ldb : STD_LOGIC;
signal F_op_ldbio : STD_LOGIC;
signal F_op_ldbu : STD_LOGIC;
signal F_op_ldbuio : STD_LOGIC;
signal F_op_ldh : STD_LOGIC;
signal F_op_ldhio : STD_LOGIC;
signal F_op_ldhu : STD_LOGIC;
signal F_op_ldhuio : STD_LOGIC;
signal F_op_ldl : STD_LOGIC;
signal F_op_ldw : STD_LOGIC;
signal F_op_ldwio : STD_LOGIC;
signal F_op_mul : STD_LOGIC;
signal F_op_muli : STD_LOGIC;
signal F_op_mulxss : STD_LOGIC;
signal F_op_mulxsu : STD_LOGIC;
signal F_op_mulxuu : STD_LOGIC;
signal F_op_nextpc : STD_LOGIC;
signal F_op_nor : STD_LOGIC;
signal F_op_opx : STD_LOGIC;
signal F_op_or : STD_LOGIC;
signal F_op_orhi : STD_LOGIC;
signal F_op_ori : STD_LOGIC;
signal F_op_rdctl : STD_LOGIC;
signal F_op_rdprs : STD_LOGIC;
signal F_op_ret : STD_LOGIC;
signal F_op_rol : STD_LOGIC;
signal F_op_roli : STD_LOGIC;
signal F_op_ror : STD_LOGIC;
signal F_op_rsv02 : STD_LOGIC;
signal F_op_rsv09 : STD_LOGIC;
signal F_op_rsv10 : STD_LOGIC;
signal F_op_rsv17 : STD_LOGIC;
signal F_op_rsv18 : STD_LOGIC;
signal F_op_rsv25 : STD_LOGIC;
signal F_op_rsv26 : STD_LOGIC;
signal F_op_rsv33 : STD_LOGIC;
signal F_op_rsv34 : STD_LOGIC;
signal F_op_rsv41 : STD_LOGIC;
signal F_op_rsv42 : STD_LOGIC;
signal F_op_rsv49 : STD_LOGIC;
signal F_op_rsv57 : STD_LOGIC;
signal F_op_rsv61 : STD_LOGIC;
signal F_op_rsv62 : STD_LOGIC;
signal F_op_rsv63 : STD_LOGIC;
signal F_op_rsvx00 : STD_LOGIC;
signal F_op_rsvx10 : STD_LOGIC;
signal F_op_rsvx15 : STD_LOGIC;
signal F_op_rsvx17 : STD_LOGIC;
signal F_op_rsvx21 : STD_LOGIC;
signal F_op_rsvx25 : STD_LOGIC;
signal F_op_rsvx33 : STD_LOGIC;
signal F_op_rsvx34 : STD_LOGIC;
signal F_op_rsvx35 : STD_LOGIC;
signal F_op_rsvx42 : STD_LOGIC;
signal F_op_rsvx43 : STD_LOGIC;
signal F_op_rsvx44 : STD_LOGIC;
signal F_op_rsvx47 : STD_LOGIC;
signal F_op_rsvx50 : STD_LOGIC;
signal F_op_rsvx51 : STD_LOGIC;
signal F_op_rsvx55 : STD_LOGIC;
signal F_op_rsvx56 : STD_LOGIC;
signal F_op_rsvx60 : STD_LOGIC;
signal F_op_rsvx63 : STD_LOGIC;
signal F_op_sll : STD_LOGIC;
signal F_op_slli : STD_LOGIC;
signal F_op_sra : STD_LOGIC;
signal F_op_srai : STD_LOGIC;
signal F_op_srl : STD_LOGIC;
signal F_op_srli : STD_LOGIC;
signal F_op_stb : STD_LOGIC;
signal F_op_stbio : STD_LOGIC;
signal F_op_stc : STD_LOGIC;
signal F_op_sth : STD_LOGIC;
signal F_op_sthio : STD_LOGIC;
signal F_op_stw : STD_LOGIC;
signal F_op_stwio : STD_LOGIC;
signal F_op_sub : STD_LOGIC;
signal F_op_sync : STD_LOGIC;
signal F_op_trap : STD_LOGIC;
signal F_op_wrctl : STD_LOGIC;
signal F_op_wrprs : STD_LOGIC;
signal F_op_xor : STD_LOGIC;
signal F_op_xorhi : STD_LOGIC;
signal F_op_xori : STD_LOGIC;
signal F_pc : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal F_pc_en : STD_LOGIC;
signal F_pc_no_crst_nxt : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal F_pc_nxt : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal F_pc_plus_one : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal F_pc_sel_nxt : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal F_pcb : STD_LOGIC_VECTOR (19 DOWNTO 0);
signal F_pcb_nxt : STD_LOGIC_VECTOR (19 DOWNTO 0);
signal F_pcb_plus_four : STD_LOGIC_VECTOR (19 DOWNTO 0);
signal F_valid : STD_LOGIC;
signal F_vinst : STD_LOGIC_VECTOR (55 DOWNTO 0);
signal R_compare_op : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal R_ctrl_alu_force_xor : STD_LOGIC;
signal R_ctrl_alu_force_xor_nxt : STD_LOGIC;
signal R_ctrl_alu_signed_comparison : STD_LOGIC;
signal R_ctrl_alu_signed_comparison_nxt : STD_LOGIC;
signal R_ctrl_alu_subtract : STD_LOGIC;
signal R_ctrl_alu_subtract_nxt : STD_LOGIC;
signal R_ctrl_b_is_dst : STD_LOGIC;
signal R_ctrl_b_is_dst_nxt : STD_LOGIC;
signal R_ctrl_br : STD_LOGIC;
signal R_ctrl_br_cmp : STD_LOGIC;
signal R_ctrl_br_cmp_nxt : STD_LOGIC;
signal R_ctrl_br_nxt : STD_LOGIC;
signal R_ctrl_br_uncond : STD_LOGIC;
signal R_ctrl_br_uncond_nxt : STD_LOGIC;
signal R_ctrl_break : STD_LOGIC;
signal R_ctrl_break_nxt : STD_LOGIC;
signal R_ctrl_crst : STD_LOGIC;
signal R_ctrl_crst_nxt : STD_LOGIC;
signal R_ctrl_custom : STD_LOGIC;
signal R_ctrl_custom_multi : STD_LOGIC;
signal R_ctrl_custom_multi_nxt : STD_LOGIC;
signal R_ctrl_custom_nxt : STD_LOGIC;
signal R_ctrl_exception : STD_LOGIC;
signal R_ctrl_exception_nxt : STD_LOGIC;
signal R_ctrl_force_src2_zero : STD_LOGIC;
signal R_ctrl_force_src2_zero_nxt : STD_LOGIC;
signal R_ctrl_hi_imm16 : STD_LOGIC;
signal R_ctrl_hi_imm16_nxt : STD_LOGIC;
signal R_ctrl_ignore_dst : STD_LOGIC;
signal R_ctrl_ignore_dst_nxt : STD_LOGIC;
signal R_ctrl_implicit_dst_eretaddr : STD_LOGIC;
signal R_ctrl_implicit_dst_eretaddr_nxt : STD_LOGIC;
signal R_ctrl_implicit_dst_retaddr : STD_LOGIC;
signal R_ctrl_implicit_dst_retaddr_nxt : STD_LOGIC;
signal R_ctrl_jmp_direct : STD_LOGIC;
signal R_ctrl_jmp_direct_nxt : STD_LOGIC;
signal R_ctrl_jmp_indirect : STD_LOGIC;
signal R_ctrl_jmp_indirect_nxt : STD_LOGIC;
signal R_ctrl_ld : STD_LOGIC;
signal R_ctrl_ld_io : STD_LOGIC;
signal R_ctrl_ld_io_nxt : STD_LOGIC;
signal R_ctrl_ld_non_io : STD_LOGIC;
signal R_ctrl_ld_non_io_nxt : STD_LOGIC;
signal R_ctrl_ld_nxt : STD_LOGIC;
signal R_ctrl_ld_signed : STD_LOGIC;
signal R_ctrl_ld_signed_nxt : STD_LOGIC;
signal R_ctrl_logic : STD_LOGIC;
signal R_ctrl_logic_nxt : STD_LOGIC;
signal R_ctrl_rdctl_inst : STD_LOGIC;
signal R_ctrl_rdctl_inst_nxt : STD_LOGIC;
signal R_ctrl_retaddr : STD_LOGIC;
signal R_ctrl_retaddr_nxt : STD_LOGIC;
signal R_ctrl_rot_right : STD_LOGIC;
signal R_ctrl_rot_right_nxt : STD_LOGIC;
signal R_ctrl_shift_logical : STD_LOGIC;
signal R_ctrl_shift_logical_nxt : STD_LOGIC;
signal R_ctrl_shift_right_arith : STD_LOGIC;
signal R_ctrl_shift_right_arith_nxt : STD_LOGIC;
signal R_ctrl_shift_rot : STD_LOGIC;
signal R_ctrl_shift_rot_nxt : STD_LOGIC;
signal R_ctrl_shift_rot_right : STD_LOGIC;
signal R_ctrl_shift_rot_right_nxt : STD_LOGIC;
signal R_ctrl_src2_choose_imm : STD_LOGIC;
signal R_ctrl_src2_choose_imm_nxt : STD_LOGIC;
signal R_ctrl_st : STD_LOGIC;
signal R_ctrl_st_nxt : STD_LOGIC;
signal R_ctrl_uncond_cti_non_br : STD_LOGIC;
signal R_ctrl_uncond_cti_non_br_nxt : STD_LOGIC;
signal R_ctrl_unsigned_lo_imm16 : STD_LOGIC;
signal R_ctrl_unsigned_lo_imm16_nxt : STD_LOGIC;
signal R_ctrl_wrctl_inst : STD_LOGIC;
signal R_ctrl_wrctl_inst_nxt : STD_LOGIC;
signal R_dst_regnum : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal R_en : STD_LOGIC;
signal R_logic_op : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal R_rf_a : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal R_rf_b : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal R_src1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal R_src2 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal R_src2_hi : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal R_src2_lo : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal R_src2_use_imm : STD_LOGIC;
signal R_stb_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal R_sth_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal R_valid : STD_LOGIC;
signal R_vinst : STD_LOGIC_VECTOR (55 DOWNTO 0);
signal R_wr_dst_reg : STD_LOGIC;
signal W_alu_result : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_br_taken : STD_LOGIC;
signal W_bstatus_reg : STD_LOGIC;
signal W_bstatus_reg_inst_nxt : STD_LOGIC;
signal W_bstatus_reg_nxt : STD_LOGIC;
signal W_cmp_result : STD_LOGIC;
signal W_control_rd_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_estatus_reg : STD_LOGIC;
signal W_estatus_reg_inst_nxt : STD_LOGIC;
signal W_estatus_reg_nxt : STD_LOGIC;
signal W_ienable_reg : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_ienable_reg_nxt : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_ipending_reg : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_ipending_reg_nxt : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_mem_baddr : STD_LOGIC_VECTOR (19 DOWNTO 0);
signal W_rf_wr_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_rf_wren : STD_LOGIC;
signal W_status_reg : STD_LOGIC;
signal W_status_reg_pie : STD_LOGIC;
signal W_status_reg_pie_inst_nxt : STD_LOGIC;
signal W_status_reg_pie_nxt : STD_LOGIC;
signal W_valid : STD_LOGIC;
signal W_vinst : STD_LOGIC_VECTOR (55 DOWNTO 0);
signal W_wr_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_wr_data_non_zero : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal av_fill_bit : STD_LOGIC;
signal av_ld_align_cycle : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal av_ld_align_cycle_nxt : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal av_ld_align_one_more_cycle : STD_LOGIC;
signal av_ld_aligning_data : STD_LOGIC;
signal av_ld_aligning_data_nxt : STD_LOGIC;
signal av_ld_byte0_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal av_ld_byte0_data_nxt : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal av_ld_byte1_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal av_ld_byte1_data_en : STD_LOGIC;
signal av_ld_byte1_data_nxt : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal av_ld_byte2_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal av_ld_byte2_data_nxt : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal av_ld_byte3_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal av_ld_byte3_data_nxt : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal av_ld_data_aligned_filtered : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal av_ld_data_aligned_unfiltered : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal av_ld_done : STD_LOGIC;
signal av_ld_extend : STD_LOGIC;
signal av_ld_getting_data : STD_LOGIC;
signal av_ld_rshift8 : STD_LOGIC;
signal av_ld_waiting_for_data : STD_LOGIC;
signal av_ld_waiting_for_data_nxt : STD_LOGIC;
signal av_sign_bit : STD_LOGIC;
signal d_read_nxt : STD_LOGIC;
signal d_write_nxt : STD_LOGIC;
signal hbreak_enabled : STD_LOGIC;
signal hbreak_pending : STD_LOGIC;
signal hbreak_pending_nxt : STD_LOGIC;
signal hbreak_req : STD_LOGIC;
signal i_read_nxt : STD_LOGIC;
signal iactive : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_d_address : STD_LOGIC_VECTOR (19 DOWNTO 0);
signal internal_d_byteenable : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal internal_d_read : STD_LOGIC;
signal internal_d_write : STD_LOGIC;
signal internal_i_address : STD_LOGIC_VECTOR (19 DOWNTO 0);
signal internal_i_read : STD_LOGIC;
signal internal_jtag_debug_module_debugaccess_to_roms : STD_LOGIC;
signal internal_jtag_debug_module_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_jtag_debug_module_resetrequest : STD_LOGIC;
signal intr_req : STD_LOGIC;
signal jtag_debug_module_clk : STD_LOGIC;
signal jtag_debug_module_reset : STD_LOGIC;
signal oci_hbreak_req : STD_LOGIC;
signal oci_ienable : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oci_single_step_mode : STD_LOGIC;
signal oci_tb_hbreak_req : STD_LOGIC;
signal test_ending : STD_LOGIC;
signal test_has_ended : STD_LOGIC;
signal wait_for_one_post_bret_inst : STD_LOGIC;
attribute ALTERA_IP_DEBUG_VISIBLE : boolean;
attribute ALTERA_IP_DEBUG_VISIBLE of D_iw : signal is true;
attribute ALTERA_IP_DEBUG_VISIBLE of F_pc : signal is true;
attribute ALTERA_IP_DEBUG_VISIBLE of R_dst_regnum : signal is true;
attribute ALTERA_IP_DEBUG_VISIBLE of W_valid : signal is true;
--synthesis translate_off
constant Video_System_CPU_register_bank_a_lpm_file : string := "Video_System_CPU_rf_ram_a.hex";
--synthesis translate_on
--synthesis read_comments_as_HDL on
--constant Video_System_CPU_register_bank_a_lpm_file : string := "Video_System_CPU_rf_ram_a.mif";
--synthesis read_comments_as_HDL off
--synthesis translate_off
constant Video_System_CPU_register_bank_b_lpm_file : string := "Video_System_CPU_rf_ram_b.hex";
--synthesis translate_on
--synthesis read_comments_as_HDL on
--constant Video_System_CPU_register_bank_b_lpm_file : string := "Video_System_CPU_rf_ram_b.mif";
--synthesis read_comments_as_HDL off
begin
--the_Video_System_CPU_test_bench, which is an e_instance
the_Video_System_CPU_test_bench : Video_System_CPU_test_bench
port map(
av_ld_data_aligned_filtered => av_ld_data_aligned_filtered,
d_write => internal_d_write,
test_has_ended => test_has_ended,
D_iw => D_iw,
D_iw_op => D_iw_op,
D_iw_opx => D_iw_opx,
D_valid => D_valid,
E_alu_result => E_alu_result,
E_mem_byte_en => E_mem_byte_en,
E_st_data => E_st_data,
E_valid => E_valid,
F_pcb => F_pcb,
F_valid => F_valid,
R_ctrl_exception => R_ctrl_exception,
R_ctrl_ld => R_ctrl_ld,
R_ctrl_ld_non_io => R_ctrl_ld_non_io,
R_dst_regnum => R_dst_regnum,
R_wr_dst_reg => R_wr_dst_reg,
W_bstatus_reg => W_bstatus_reg,
W_cmp_result => W_cmp_result,
W_estatus_reg => W_estatus_reg,
W_ienable_reg => W_ienable_reg,
W_ipending_reg => W_ipending_reg,
W_mem_baddr => W_mem_baddr,
W_rf_wr_data => W_rf_wr_data,
W_status_reg => W_status_reg,
W_valid => W_valid,
W_vinst => W_vinst,
W_wr_data => W_wr_data,
av_ld_data_aligned_unfiltered => av_ld_data_aligned_unfiltered,
clk => clk,
d_address => internal_d_address,
d_byteenable => internal_d_byteenable,
d_read => internal_d_read,
d_write_nxt => d_write_nxt,
i_address => internal_i_address,
i_read => internal_i_read,
i_readdata => i_readdata,
i_waitrequest => i_waitrequest,
reset_n => reset_n
);
F_av_iw_a <= F_av_iw(31 DOWNTO 27);
F_av_iw_b <= F_av_iw(26 DOWNTO 22);
F_av_iw_c <= F_av_iw(21 DOWNTO 17);
F_av_iw_custom_n <= F_av_iw(13 DOWNTO 6);
F_av_iw_custom_readra <= F_av_iw(16);
F_av_iw_custom_readrb <= F_av_iw(15);
F_av_iw_custom_writerc <= F_av_iw(14);
F_av_iw_opx <= F_av_iw(16 DOWNTO 11);
F_av_iw_op <= F_av_iw(5 DOWNTO 0);
F_av_iw_shift_imm5 <= F_av_iw(10 DOWNTO 6);
F_av_iw_trap_break_imm5 <= F_av_iw(10 DOWNTO 6);
F_av_iw_imm5 <= F_av_iw(10 DOWNTO 6);
F_av_iw_imm16 <= F_av_iw(21 DOWNTO 6);
F_av_iw_imm26 <= F_av_iw(31 DOWNTO 6);
F_av_iw_memsz <= F_av_iw(4 DOWNTO 3);
F_av_iw_control_regnum <= F_av_iw(8 DOWNTO 6);
F_av_mem8 <= to_std_logic((F_av_iw_memsz = std_logic_vector'("00")));
F_av_mem16 <= to_std_logic((F_av_iw_memsz = std_logic_vector'("01")));
F_av_mem32 <= to_std_logic((std_logic'(F_av_iw_memsz(1)) = std_logic'(std_logic'('1'))));
F_iw_a <= F_iw(31 DOWNTO 27);
F_iw_b <= F_iw(26 DOWNTO 22);
F_iw_c <= F_iw(21 DOWNTO 17);
F_iw_custom_n <= F_iw(13 DOWNTO 6);
F_iw_custom_readra <= F_iw(16);
F_iw_custom_readrb <= F_iw(15);
F_iw_custom_writerc <= F_iw(14);
F_iw_opx <= F_iw(16 DOWNTO 11);
F_iw_op <= F_iw(5 DOWNTO 0);
F_iw_shift_imm5 <= F_iw(10 DOWNTO 6);
F_iw_trap_break_imm5 <= F_iw(10 DOWNTO 6);
F_iw_imm5 <= F_iw(10 DOWNTO 6);
F_iw_imm16 <= F_iw(21 DOWNTO 6);
F_iw_imm26 <= F_iw(31 DOWNTO 6);
F_iw_memsz <= F_iw(4 DOWNTO 3);
F_iw_control_regnum <= F_iw(8 DOWNTO 6);
F_mem8 <= to_std_logic((F_iw_memsz = std_logic_vector'("00")));
F_mem16 <= to_std_logic((F_iw_memsz = std_logic_vector'("01")));
F_mem32 <= to_std_logic((std_logic'(F_iw_memsz(1)) = std_logic'(std_logic'('1'))));
D_iw_a <= D_iw(31 DOWNTO 27);
D_iw_b <= D_iw(26 DOWNTO 22);
D_iw_c <= D_iw(21 DOWNTO 17);
D_iw_custom_n <= D_iw(13 DOWNTO 6);
D_iw_custom_readra <= D_iw(16);
D_iw_custom_readrb <= D_iw(15);
D_iw_custom_writerc <= D_iw(14);
D_iw_opx <= D_iw(16 DOWNTO 11);
D_iw_op <= D_iw(5 DOWNTO 0);
D_iw_shift_imm5 <= D_iw(10 DOWNTO 6);
D_iw_trap_break_imm5 <= D_iw(10 DOWNTO 6);
D_iw_imm5 <= D_iw(10 DOWNTO 6);
D_iw_imm16 <= D_iw(21 DOWNTO 6);
D_iw_imm26 <= D_iw(31 DOWNTO 6);
D_iw_memsz <= D_iw(4 DOWNTO 3);
D_iw_control_regnum <= D_iw(8 DOWNTO 6);
D_mem8 <= to_std_logic((D_iw_memsz = std_logic_vector'("00")));
D_mem16 <= to_std_logic((D_iw_memsz = std_logic_vector'("01")));
D_mem32 <= to_std_logic((std_logic'(D_iw_memsz(1)) = std_logic'(std_logic'('1'))));
F_op_call <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000000000")));
F_op_jmpi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000000001")));
F_op_ldbu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000000011")));
F_op_addi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000000100")));
F_op_stb <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000000101")));
F_op_br <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000000110")));
F_op_ldb <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000000111")));
F_op_cmpgei <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000001000")));
F_op_ldhu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000001011")));
F_op_andi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000001100")));
F_op_sth <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000001101")));
F_op_bge <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000001110")));
F_op_ldh <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000001111")));
F_op_cmplti <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000010000")));
F_op_initda <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000010011")));
F_op_ori <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000010100")));
F_op_stw <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000010101")));
F_op_blt <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000010110")));
F_op_ldw <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000010111")));
F_op_cmpnei <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000011000")));
F_op_flushda <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000011011")));
F_op_xori <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000011100")));
F_op_stc <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000011101")));
F_op_bne <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000011110")));
F_op_ldl <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000011111")));
F_op_cmpeqi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000100000")));
F_op_ldbuio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000100011")));
F_op_muli <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000100100")));
F_op_stbio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000100101")));
F_op_beq <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000100110")));
F_op_ldbio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000100111")));
F_op_cmpgeui <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000101000")));
F_op_ldhuio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000101011")));
F_op_andhi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000101100")));
F_op_sthio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000101101")));
F_op_bgeu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000101110")));
F_op_ldhio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000101111")));
F_op_cmpltui <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000110000")));
F_op_initd <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000110011")));
F_op_orhi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000110100")));
F_op_stwio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000110101")));
F_op_bltu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000110110")));
F_op_ldwio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000110111")));
F_op_rdprs <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000111000")));
F_op_flushd <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000111011")));
F_op_xorhi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000111100")));
F_op_rsv02 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000000010")));
F_op_rsv09 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000001001")));
F_op_rsv10 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000001010")));
F_op_rsv17 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000010001")));
F_op_rsv18 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000010010")));
F_op_rsv25 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000011001")));
F_op_rsv26 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000011010")));
F_op_rsv33 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000100001")));
F_op_rsv34 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000100010")));
F_op_rsv41 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000101001")));
F_op_rsv42 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000101010")));
F_op_rsv49 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000110001")));
F_op_rsv57 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000111001")));
F_op_rsv61 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000111101")));
F_op_rsv62 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000111110")));
F_op_rsv63 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000111111")));
F_op_eret <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000000001"))));
F_op_roli <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000000010"))));
F_op_rol <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000000011"))));
F_op_flushp <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000000100"))));
F_op_ret <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000000101"))));
F_op_nor <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000000110"))));
F_op_mulxuu <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000000111"))));
F_op_cmpge <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000001000"))));
F_op_bret <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000001001"))));
F_op_ror <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000001011"))));
F_op_flushi <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000001100"))));
F_op_jmp <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000001101"))));
F_op_and <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000001110"))));
F_op_cmplt <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000010000"))));
F_op_slli <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000010010"))));
F_op_sll <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000010011"))));
F_op_wrprs <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000010100"))));
F_op_or <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000010110"))));
F_op_mulxsu <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000010111"))));
F_op_cmpne <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000011000"))));
F_op_srli <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000011010"))));
F_op_srl <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000011011"))));
F_op_nextpc <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000011100"))));
F_op_callr <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000011101"))));
F_op_xor <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000011110"))));
F_op_mulxss <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000011111"))));
F_op_cmpeq <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000100000"))));
F_op_divu <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000100100"))));
F_op_div <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000100101"))));
F_op_rdctl <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000100110"))));
F_op_mul <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000100111"))));
F_op_cmpgeu <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000101000"))));
F_op_initi <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000101001"))));
F_op_trap <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000101101"))));
F_op_wrctl <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000101110"))));
F_op_cmpltu <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000110000"))));
F_op_add <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000110001"))));
F_op_break <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000110100"))));
F_op_hbreak <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000110101"))));
F_op_sync <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000110110"))));
F_op_sub <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000111001"))));
F_op_srai <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000111010"))));
F_op_sra <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000111011"))));
F_op_intr <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000111101"))));
F_op_crst <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000111110"))));
F_op_rsvx00 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000000000"))));
F_op_rsvx10 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000001010"))));
F_op_rsvx15 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000001111"))));
F_op_rsvx17 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000010001"))));
F_op_rsvx21 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000010101"))));
F_op_rsvx25 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000011001"))));
F_op_rsvx33 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000100001"))));
F_op_rsvx34 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000100010"))));
F_op_rsvx35 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000100011"))));
F_op_rsvx42 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000101010"))));
F_op_rsvx43 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000101011"))));
F_op_rsvx44 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000101100"))));
F_op_rsvx47 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000101111"))));
F_op_rsvx50 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000110010"))));
F_op_rsvx51 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000110011"))));
F_op_rsvx55 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000110111"))));
F_op_rsvx56 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000111000"))));
F_op_rsvx60 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000111100"))));
F_op_rsvx63 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000111111"))));
F_op_opx <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000111010")));
F_op_custom <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000110010")));
D_op_call <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000000")));
D_op_jmpi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000001")));
D_op_ldbu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000011")));
D_op_addi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000100")));
D_op_stb <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000101")));
D_op_br <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000110")));
D_op_ldb <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000111")));
D_op_cmpgei <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001000")));
D_op_ldhu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001011")));
D_op_andi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001100")));
D_op_sth <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001101")));
D_op_bge <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001110")));
D_op_ldh <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001111")));
D_op_cmplti <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010000")));
D_op_initda <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010011")));
D_op_ori <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010100")));
D_op_stw <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010101")));
D_op_blt <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010110")));
D_op_ldw <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010111")));
D_op_cmpnei <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011000")));
D_op_flushda <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011011")));
D_op_xori <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011100")));
D_op_stc <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011101")));
D_op_bne <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011110")));
D_op_ldl <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011111")));
D_op_cmpeqi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100000")));
D_op_ldbuio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100011")));
D_op_muli <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100100")));
D_op_stbio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100101")));
D_op_beq <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100110")));
D_op_ldbio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100111")));
D_op_cmpgeui <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101000")));
D_op_ldhuio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101011")));
D_op_andhi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101100")));
D_op_sthio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101101")));
D_op_bgeu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101110")));
D_op_ldhio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101111")));
D_op_cmpltui <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110000")));
D_op_initd <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110011")));
D_op_orhi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110100")));
D_op_stwio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110101")));
D_op_bltu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110110")));
D_op_ldwio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110111")));
D_op_rdprs <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111000")));
D_op_flushd <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111011")));
D_op_xorhi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111100")));
D_op_rsv02 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000010")));
D_op_rsv09 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001001")));
D_op_rsv10 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001010")));
D_op_rsv17 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010001")));
D_op_rsv18 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010010")));
D_op_rsv25 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011001")));
D_op_rsv26 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011010")));
D_op_rsv33 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100001")));
D_op_rsv34 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100010")));
D_op_rsv41 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101001")));
D_op_rsv42 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101010")));
D_op_rsv49 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110001")));
D_op_rsv57 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111001")));
D_op_rsv61 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111101")));
D_op_rsv62 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111110")));
D_op_rsv63 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111111")));
D_op_eret <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000001"))));
D_op_roli <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000010"))));
D_op_rol <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000011"))));
D_op_flushp <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000100"))));
D_op_ret <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000101"))));
D_op_nor <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000110"))));
D_op_mulxuu <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000111"))));
D_op_cmpge <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001000"))));
D_op_bret <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001001"))));
D_op_ror <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001011"))));
D_op_flushi <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001100"))));
D_op_jmp <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001101"))));
D_op_and <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001110"))));
D_op_cmplt <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010000"))));
D_op_slli <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010010"))));
D_op_sll <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010011"))));
D_op_wrprs <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010100"))));
D_op_or <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010110"))));
D_op_mulxsu <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010111"))));
D_op_cmpne <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011000"))));
D_op_srli <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011010"))));
D_op_srl <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011011"))));
D_op_nextpc <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011100"))));
D_op_callr <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011101"))));
D_op_xor <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011110"))));
D_op_mulxss <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011111"))));
D_op_cmpeq <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100000"))));
D_op_divu <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100100"))));
D_op_div <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100101"))));
D_op_rdctl <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100110"))));
D_op_mul <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100111"))));
D_op_cmpgeu <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101000"))));
D_op_initi <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101001"))));
D_op_trap <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101101"))));
D_op_wrctl <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101110"))));
D_op_cmpltu <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110000"))));
D_op_add <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110001"))));
D_op_break <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110100"))));
D_op_hbreak <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110101"))));
D_op_sync <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110110"))));
D_op_sub <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111001"))));
D_op_srai <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111010"))));
D_op_sra <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111011"))));
D_op_intr <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111101"))));
D_op_crst <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111110"))));
D_op_rsvx00 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000000"))));
D_op_rsvx10 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001010"))));
D_op_rsvx15 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001111"))));
D_op_rsvx17 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010001"))));
D_op_rsvx21 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010101"))));
D_op_rsvx25 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011001"))));
D_op_rsvx33 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100001"))));
D_op_rsvx34 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100010"))));
D_op_rsvx35 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100011"))));
D_op_rsvx42 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101010"))));
D_op_rsvx43 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101011"))));
D_op_rsvx44 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101100"))));
D_op_rsvx47 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101111"))));
D_op_rsvx50 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110010"))));
D_op_rsvx51 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110011"))));
D_op_rsvx55 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110111"))));
D_op_rsvx56 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111000"))));
D_op_rsvx60 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111100"))));
D_op_rsvx63 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111111"))));
D_op_opx <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111010")));
D_op_custom <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110010")));
R_en <= std_logic'('1');
E_ci_result <= std_logic_vector'("00000000000000000000000000000000");
--custom_instruction_master, which is an e_custom_instruction_master
no_ci_readra <= std_logic'('0');
E_ci_multi_stall <= std_logic'('0');
iactive <= d_irq(31 DOWNTO 0) AND std_logic_vector'("00000000000000000000000000000000");
F_pc_sel_nxt <= A_WE_StdLogicVector((std_logic'(R_ctrl_exception) = '1'), std_logic_vector'("00"), A_WE_StdLogicVector((std_logic'(R_ctrl_break) = '1'), std_logic_vector'("01"), A_WE_StdLogicVector((std_logic'(((W_br_taken OR R_ctrl_uncond_cti_non_br))) = '1'), std_logic_vector'("10"), std_logic_vector'("11"))));
F_pc_no_crst_nxt <= A_EXT (A_WE_StdLogicVector(((F_pc_sel_nxt = std_logic_vector'("00"))), std_logic_vector'("00000000000000100001000000001000"), A_WE_StdLogicVector(((F_pc_sel_nxt = std_logic_vector'("01"))), std_logic_vector'("00000000000000100010001000001000"), (std_logic_vector'("00000000000000") & (A_WE_StdLogicVector(((F_pc_sel_nxt = std_logic_vector'("10"))), E_arith_result(19 DOWNTO 2), F_pc_plus_one))))), 18);
F_pc_nxt <= F_pc_no_crst_nxt;
F_pcb_nxt <= F_pc_nxt & std_logic_vector'("00");
F_pc_en <= W_valid;
F_pc_plus_one <= A_EXT (((std_logic_vector'("000000000000000") & (F_pc)) + std_logic_vector'("000000000000000000000000000000001")), 18);
process (clk, reset_n)
begin
if reset_n = '0' then
F_pc <= std_logic_vector'("100001000000000000");
elsif clk'event and clk = '1' then
if std_logic'(F_pc_en) = '1' then
F_pc <= F_pc_nxt;
end if;
end if;
end process;
F_pcb <= F_pc & std_logic_vector'("00");
F_pcb_plus_four <= F_pc_plus_one & std_logic_vector'("00");
F_valid <= internal_i_read AND NOT i_waitrequest;
i_read_nxt <= W_valid OR ((internal_i_read AND i_waitrequest));
internal_i_address <= F_pc & std_logic_vector'("00");
process (clk, reset_n)
begin
if reset_n = '0' then
internal_i_read <= std_logic'('1');
elsif clk'event and clk = '1' then
internal_i_read <= i_read_nxt;
end if;
end process;
oci_tb_hbreak_req <= oci_hbreak_req;
hbreak_req <= (((oci_tb_hbreak_req OR hbreak_pending)) AND hbreak_enabled) AND NOT ((wait_for_one_post_bret_inst AND NOT W_valid));
hbreak_pending_nxt <= A_WE_StdLogic((std_logic'(hbreak_pending) = '1'), hbreak_enabled, hbreak_req);
process (clk, reset_n)
begin
if reset_n = '0' then
wait_for_one_post_bret_inst <= std_logic'('0');
elsif clk'event and clk = '1' then
wait_for_one_post_bret_inst <= A_WE_StdLogic((std_logic'(((NOT hbreak_enabled AND oci_single_step_mode))) = '1'), std_logic'('1'), A_WE_StdLogic((std_logic'(((F_valid OR NOT oci_single_step_mode))) = '1'), std_logic'('0'), wait_for_one_post_bret_inst));
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
hbreak_pending <= std_logic'('0');
elsif clk'event and clk = '1' then
hbreak_pending <= hbreak_pending_nxt;
end if;
end process;
intr_req <= W_status_reg_pie AND to_std_logic(((W_ipending_reg /= std_logic_vector'("00000000000000000000000000000000"))));
F_av_iw <= i_readdata;
F_iw <= A_WE_StdLogicVector((std_logic'(hbreak_req) = '1'), std_logic_vector'("00000000001111011010100000111010"), A_WE_StdLogicVector((std_logic'(std_logic'('0')) = '1'), std_logic_vector'("00000000000000011111000000111010"), A_WE_StdLogicVector((std_logic'(intr_req) = '1'), std_logic_vector'("00000000001110111110100000111010"), F_av_iw)));
process (clk, reset_n)
begin
if reset_n = '0' then
D_iw <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(F_valid) = '1' then
D_iw <= F_iw;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
D_valid <= std_logic'('0');
elsif clk'event and clk = '1' then
D_valid <= F_valid;
end if;
end process;
D_dst_regnum <= A_WE_StdLogicVector((std_logic'(D_ctrl_implicit_dst_retaddr) = '1'), std_logic_vector'("11111"), A_WE_StdLogicVector((std_logic'(D_ctrl_implicit_dst_eretaddr) = '1'), std_logic_vector'("11101"), A_WE_StdLogicVector((std_logic'(D_ctrl_b_is_dst) = '1'), D_iw_b, D_iw_c)));
D_wr_dst_reg <= to_std_logic((((std_logic_vector'("000000000000000000000000000") & (D_dst_regnum)) /= std_logic_vector'("00000000000000000000000000000000")))) AND NOT D_ctrl_ignore_dst;
D_logic_op_raw <= A_WE_StdLogicVector((std_logic'(D_op_opx) = '1'), D_iw_opx(4 DOWNTO 3), D_iw_op(4 DOWNTO 3));
D_logic_op <= A_WE_StdLogicVector((std_logic'(D_ctrl_alu_force_xor) = '1'), std_logic_vector'("11"), D_logic_op_raw);
D_compare_op <= A_WE_StdLogicVector((std_logic'(D_op_opx) = '1'), D_iw_opx(4 DOWNTO 3), D_iw_op(4 DOWNTO 3));
D_jmp_direct_target_waddr <= A_EXT (D_iw(31 DOWNTO 6), 18);
process (clk, reset_n)
begin
if reset_n = '0' then
R_valid <= std_logic'('0');
elsif clk'event and clk = '1' then
R_valid <= D_valid;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
R_wr_dst_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
R_wr_dst_reg <= D_wr_dst_reg;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
R_dst_regnum <= std_logic_vector'("00000");
elsif clk'event and clk = '1' then
R_dst_regnum <= D_dst_regnum;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
R_logic_op <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
R_logic_op <= D_logic_op;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
R_compare_op <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
R_compare_op <= D_compare_op;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
R_src2_use_imm <= std_logic'('0');
elsif clk'event and clk = '1' then
R_src2_use_imm <= D_ctrl_src2_choose_imm OR ((D_ctrl_br AND R_valid));
end if;
end process;
W_rf_wren <= ((R_wr_dst_reg AND W_valid)) OR NOT reset_n;
W_rf_wr_data <= A_WE_StdLogicVector((std_logic'(R_ctrl_ld) = '1'), av_ld_data_aligned_filtered, W_wr_data);
--Video_System_CPU_register_bank_a, which is an nios_sdp_ram
Video_System_CPU_register_bank_a : Video_System_CPU_register_bank_a_module
generic map(
lpm_file => Video_System_CPU_register_bank_a_lpm_file
)
port map(
q => R_rf_a,
clock => clk,
data => W_rf_wr_data,
rdaddress => D_iw_a,
wraddress => R_dst_regnum,
wren => W_rf_wren
);
--Video_System_CPU_register_bank_b, which is an nios_sdp_ram
Video_System_CPU_register_bank_b : Video_System_CPU_register_bank_b_module
generic map(
lpm_file => Video_System_CPU_register_bank_b_lpm_file
)
port map(
q => R_rf_b,
clock => clk,
data => W_rf_wr_data,
rdaddress => D_iw_b,
wraddress => R_dst_regnum,
wren => W_rf_wren
);
R_src1 <= A_WE_StdLogicVector((std_logic'(((((R_ctrl_br AND E_valid)) OR ((R_ctrl_retaddr AND R_valid))))) = '1'), (std_logic_vector'("000000000000") & ((F_pc_plus_one & std_logic_vector'("00")))), A_WE_StdLogicVector((std_logic'(((R_ctrl_jmp_direct AND E_valid))) = '1'), (std_logic_vector'("000000000000") & ((D_jmp_direct_target_waddr & std_logic_vector'("00")))), R_rf_a));
R_src2_lo <= A_WE_StdLogicVector((std_logic'(((R_ctrl_force_src2_zero OR R_ctrl_hi_imm16))) = '1'), std_logic_vector'("0000000000000000"), A_WE_StdLogicVector((std_logic'((R_src2_use_imm)) = '1'), D_iw_imm16, R_rf_b(15 DOWNTO 0)));
R_src2_hi <= A_WE_StdLogicVector((std_logic'(((R_ctrl_force_src2_zero OR R_ctrl_unsigned_lo_imm16))) = '1'), std_logic_vector'("0000000000000000"), A_WE_StdLogicVector((std_logic'((R_ctrl_hi_imm16)) = '1'), D_iw_imm16, A_WE_StdLogicVector((std_logic'((R_src2_use_imm)) = '1'), A_REP(D_iw_imm16(15) , 16), R_rf_b(31 DOWNTO 16))));
R_src2 <= R_src2_hi & R_src2_lo;
process (clk, reset_n)
begin
if reset_n = '0' then
E_valid <= std_logic'('0');
elsif clk'event and clk = '1' then
E_valid <= R_valid OR E_stall;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_new_inst <= std_logic'('0');
elsif clk'event and clk = '1' then
E_new_inst <= R_valid;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_src1 <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
E_src1 <= R_src1;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_src2 <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
E_src2 <= R_src2;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_invert_arith_src_msb <= std_logic'('0');
elsif clk'event and clk = '1' then
E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison AND R_valid;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_alu_sub <= std_logic'('0');
elsif clk'event and clk = '1' then
E_alu_sub <= D_ctrl_alu_subtract AND R_valid;
end if;
end process;
E_stall <= ((E_shift_rot_stall OR E_ld_stall) OR E_st_stall) OR E_ci_multi_stall;
E_arith_src1 <= Std_Logic_Vector'(A_ToStdLogicVector((E_src1(31) XOR E_invert_arith_src_msb)) & E_src1(30 DOWNTO 0));
E_arith_src2 <= Std_Logic_Vector'(A_ToStdLogicVector((E_src2(31) XOR E_invert_arith_src_msb)) & E_src2(30 DOWNTO 0));
E_arith_result <= A_WE_StdLogicVector((std_logic'(E_alu_sub) = '1'), ((std_logic_vector'("0") & (E_arith_src1)) - (std_logic_vector'("0") & (E_arith_src2))), ((std_logic_vector'("0") & (E_arith_src1)) + (std_logic_vector'("0") & (E_arith_src2))));
E_mem_baddr <= E_arith_result(19 DOWNTO 0);
E_logic_result <= A_WE_StdLogicVector(((R_logic_op = std_logic_vector'("00"))), (NOT ((E_src1 OR E_src2))), A_WE_StdLogicVector(((R_logic_op = std_logic_vector'("01"))), ((E_src1 AND E_src2)), A_WE_StdLogicVector(((R_logic_op = std_logic_vector'("10"))), ((E_src1 OR E_src2)), ((E_src1 XOR E_src2)))));
E_logic_result_is_0 <= to_std_logic((E_logic_result = std_logic_vector'("00000000000000000000000000000000")));
E_eq <= E_logic_result_is_0;
E_lt <= E_arith_result(32);
E_cmp_result <= A_WE_StdLogic(((R_compare_op = std_logic_vector'("00"))), E_eq, A_WE_StdLogic(((R_compare_op = std_logic_vector'("01"))), NOT E_lt, A_WE_StdLogic(((R_compare_op = std_logic_vector'("10"))), E_lt, NOT E_eq)));
E_shift_rot_cnt_nxt <= A_EXT (A_WE_StdLogicVector((std_logic'(E_new_inst) = '1'), (std_logic_vector'("0000000000000000000000000000") & (E_src2(4 DOWNTO 0))), ((std_logic_vector'("0000000000000000000000000000") & (E_shift_rot_cnt)) - std_logic_vector'("000000000000000000000000000000001"))), 5);
E_shift_rot_done <= to_std_logic((((std_logic_vector'("000000000000000000000000000") & (E_shift_rot_cnt)) = std_logic_vector'("00000000000000000000000000000000")))) AND NOT E_new_inst;
E_shift_rot_stall <= (R_ctrl_shift_rot AND E_valid) AND NOT E_shift_rot_done;
E_shift_rot_fill_bit <= A_WE_StdLogic((std_logic'(R_ctrl_shift_logical) = '1'), std_logic'('0'), (A_WE_StdLogic((std_logic'(R_ctrl_rot_right) = '1'), E_shift_rot_result(0), E_shift_rot_result(31))));
E_shift_rot_result_nxt <= A_WE_StdLogicVector((std_logic'((E_new_inst)) = '1'), E_src1, A_WE_StdLogicVector((std_logic'((R_ctrl_shift_rot_right)) = '1'), Std_Logic_Vector'(A_ToStdLogicVector(E_shift_rot_fill_bit) & E_shift_rot_result(31 DOWNTO 1)), Std_Logic_Vector'(E_shift_rot_result(30 DOWNTO 0) & A_ToStdLogicVector(E_shift_rot_fill_bit))));
process (clk, reset_n)
begin
if reset_n = '0' then
E_shift_rot_result <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
E_shift_rot_result <= E_shift_rot_result_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_shift_rot_cnt <= std_logic_vector'("00000");
elsif clk'event and clk = '1' then
E_shift_rot_cnt <= E_shift_rot_cnt_nxt;
end if;
end process;
E_control_rd_data <= A_WE_StdLogicVector(((D_iw_control_regnum = std_logic_vector'("000"))), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(W_status_reg))), A_WE_StdLogicVector(((D_iw_control_regnum = std_logic_vector'("001"))), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(W_estatus_reg))), A_WE_StdLogicVector(((D_iw_control_regnum = std_logic_vector'("010"))), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(W_bstatus_reg))), A_WE_StdLogicVector(((D_iw_control_regnum = std_logic_vector'("011"))), W_ienable_reg, A_WE_StdLogicVector(((D_iw_control_regnum = std_logic_vector'("100"))), W_ipending_reg, std_logic_vector'("00000000000000000000000000000000"))))));
E_alu_result <= A_EXT (A_WE_StdLogicVector((std_logic'(((R_ctrl_br_cmp OR R_ctrl_rdctl_inst))) = '1'), std_logic_vector'("000000000000000000000000000000000"), A_WE_StdLogicVector((std_logic'((R_ctrl_shift_rot)) = '1'), (std_logic_vector'("0") & (E_shift_rot_result)), A_WE_StdLogicVector((std_logic'((R_ctrl_logic)) = '1'), (std_logic_vector'("0") & (E_logic_result)), A_WE_StdLogicVector((std_logic'((R_ctrl_custom)) = '1'), (std_logic_vector'("0") & (E_ci_result)), E_arith_result)))), 32);
R_stb_data <= R_rf_b(7 DOWNTO 0);
R_sth_data <= R_rf_b(15 DOWNTO 0);
E_st_data <= A_WE_StdLogicVector((std_logic'((D_mem8)) = '1'), (R_stb_data & R_stb_data & R_stb_data & R_stb_data), A_WE_StdLogicVector((std_logic'((D_mem16)) = '1'), (R_sth_data & R_sth_data), R_rf_b));
E_mem_byte_en <= A_WE_StdLogicVector((((D_iw_memsz & E_mem_baddr(1 DOWNTO 0)) = Std_Logic_Vector'(std_logic_vector'("00") & std_logic_vector'("00")))), std_logic_vector'("0001"), A_WE_StdLogicVector((((D_iw_memsz & E_mem_baddr(1 DOWNTO 0)) = Std_Logic_Vector'(std_logic_vector'("00") & std_logic_vector'("01")))), std_logic_vector'("0010"), A_WE_StdLogicVector((((D_iw_memsz & E_mem_baddr(1 DOWNTO 0)) = Std_Logic_Vector'(std_logic_vector'("00") & std_logic_vector'("10")))), std_logic_vector'("0100"), A_WE_StdLogicVector((((D_iw_memsz & E_mem_baddr(1 DOWNTO 0)) = Std_Logic_Vector'(std_logic_vector'("00") & std_logic_vector'("11")))), std_logic_vector'("1000"), A_WE_StdLogicVector((((D_iw_memsz & E_mem_baddr(1 DOWNTO 0)) = Std_Logic_Vector'(std_logic_vector'("01") & std_logic_vector'("00")))), std_logic_vector'("0011"), A_WE_StdLogicVector((((D_iw_memsz & E_mem_baddr(1 DOWNTO 0)) = Std_Logic_Vector'(std_logic_vector'("01") & std_logic_vector'("01")))), std_logic_vector'("0011"), A_WE_StdLogicVector((((D_iw_memsz & E_mem_baddr(1 DOWNTO 0)) = Std_Logic_Vector'(std_logic_vector'("01") & std_logic_vector'("10")))), std_logic_vector'("1100"), A_WE_StdLogicVector((((D_iw_memsz & E_mem_baddr(1 DOWNTO 0)) = Std_Logic_Vector'(std_logic_vector'("01") & std_logic_vector'("11")))), std_logic_vector'("1100"), std_logic_vector'("1111")))))))));
d_read_nxt <= ((R_ctrl_ld AND E_new_inst)) OR ((internal_d_read AND d_waitrequest));
E_ld_stall <= R_ctrl_ld AND ((((E_valid AND NOT av_ld_done)) OR E_new_inst));
d_write_nxt <= ((R_ctrl_st AND E_new_inst)) OR ((internal_d_write AND d_waitrequest));
E_st_stall <= d_write_nxt;
internal_d_address <= W_mem_baddr;
av_ld_getting_data <= internal_d_read AND NOT d_waitrequest;
process (clk, reset_n)
begin
if reset_n = '0' then
internal_d_read <= std_logic'('0');
elsif clk'event and clk = '1' then
internal_d_read <= d_read_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
d_writedata <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
d_writedata <= E_st_data;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
internal_d_byteenable <= std_logic_vector'("0000");
elsif clk'event and clk = '1' then
internal_d_byteenable <= E_mem_byte_en;
end if;
end process;
av_ld_align_cycle_nxt <= A_EXT (A_WE_StdLogicVector((std_logic'(av_ld_getting_data) = '1'), std_logic_vector'("000000000000000000000000000000000"), (((std_logic_vector'("0000000000000000000000000000000") & (av_ld_align_cycle)) + std_logic_vector'("000000000000000000000000000000001")))), 2);
av_ld_align_one_more_cycle <= to_std_logic(((std_logic_vector'("000000000000000000000000000000") & (av_ld_align_cycle)) = (A_WE_StdLogicVector((std_logic'(D_mem16) = '1'), std_logic_vector'("00000000000000000000000000000010"), std_logic_vector'("00000000000000000000000000000011")))));
av_ld_aligning_data_nxt <= A_WE_StdLogic((std_logic'(av_ld_aligning_data) = '1'), NOT av_ld_align_one_more_cycle, ((NOT D_mem32 AND av_ld_getting_data)));
av_ld_waiting_for_data_nxt <= A_WE_StdLogic((std_logic'(av_ld_waiting_for_data) = '1'), NOT av_ld_getting_data, ((R_ctrl_ld AND E_new_inst)));
av_ld_done <= NOT av_ld_waiting_for_data_nxt AND ((D_mem32 OR NOT av_ld_aligning_data_nxt));
av_ld_rshift8 <= av_ld_aligning_data AND to_std_logic(((av_ld_align_cycle<(W_mem_baddr(1 DOWNTO 0)))));
av_ld_extend <= av_ld_aligning_data;
av_ld_byte0_data_nxt <= A_WE_StdLogicVector((std_logic'(av_ld_rshift8) = '1'), av_ld_byte1_data, A_WE_StdLogicVector((std_logic'(av_ld_extend) = '1'), av_ld_byte0_data, d_readdata(7 DOWNTO 0)));
av_ld_byte1_data_nxt <= A_WE_StdLogicVector((std_logic'(av_ld_rshift8) = '1'), av_ld_byte2_data, A_WE_StdLogicVector((std_logic'(av_ld_extend) = '1'), A_REP(av_fill_bit, 8), d_readdata(15 DOWNTO 8)));
av_ld_byte2_data_nxt <= A_WE_StdLogicVector((std_logic'(av_ld_rshift8) = '1'), av_ld_byte3_data, A_WE_StdLogicVector((std_logic'(av_ld_extend) = '1'), A_REP(av_fill_bit, 8), d_readdata(23 DOWNTO 16)));
av_ld_byte3_data_nxt <= A_WE_StdLogicVector((std_logic'(av_ld_rshift8) = '1'), av_ld_byte3_data, A_WE_StdLogicVector((std_logic'(av_ld_extend) = '1'), A_REP(av_fill_bit, 8), d_readdata(31 DOWNTO 24)));
av_ld_byte1_data_en <= NOT (((av_ld_extend AND D_mem16) AND NOT av_ld_rshift8));
av_ld_data_aligned_unfiltered <= av_ld_byte3_data & av_ld_byte2_data & av_ld_byte1_data & av_ld_byte0_data;
av_sign_bit <= A_WE_StdLogic((std_logic'(D_mem16) = '1'), av_ld_byte1_data(7), av_ld_byte0_data(7));
av_fill_bit <= av_sign_bit AND R_ctrl_ld_signed;
process (clk, reset_n)
begin
if reset_n = '0' then
av_ld_align_cycle <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
av_ld_align_cycle <= av_ld_align_cycle_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
av_ld_waiting_for_data <= std_logic'('0');
elsif clk'event and clk = '1' then
av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
av_ld_aligning_data <= std_logic'('0');
elsif clk'event and clk = '1' then
av_ld_aligning_data <= av_ld_aligning_data_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
av_ld_byte0_data <= std_logic_vector'("00000000");
elsif clk'event and clk = '1' then
av_ld_byte0_data <= av_ld_byte0_data_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
av_ld_byte1_data <= std_logic_vector'("00000000");
elsif clk'event and clk = '1' then
if std_logic'(av_ld_byte1_data_en) = '1' then
av_ld_byte1_data <= av_ld_byte1_data_nxt;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
av_ld_byte2_data <= std_logic_vector'("00000000");
elsif clk'event and clk = '1' then
av_ld_byte2_data <= av_ld_byte2_data_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
av_ld_byte3_data <= std_logic_vector'("00000000");
elsif clk'event and clk = '1' then
av_ld_byte3_data <= av_ld_byte3_data_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
W_valid <= std_logic'('0');
elsif clk'event and clk = '1' then
W_valid <= E_valid AND NOT E_stall;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
W_control_rd_data <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
W_control_rd_data <= E_control_rd_data;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
W_cmp_result <= std_logic'('0');
elsif clk'event and clk = '1' then
W_cmp_result <= E_cmp_result;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
W_alu_result <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
W_alu_result <= E_alu_result;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
W_status_reg_pie <= std_logic'('0');
elsif clk'event and clk = '1' then
W_status_reg_pie <= W_status_reg_pie_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
W_estatus_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
W_estatus_reg <= W_estatus_reg_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
W_bstatus_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
W_bstatus_reg <= W_bstatus_reg_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
W_ienable_reg <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
W_ienable_reg <= W_ienable_reg_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
W_ipending_reg <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
W_ipending_reg <= W_ipending_reg_nxt;
end if;
end process;
W_wr_data_non_zero <= A_WE_StdLogicVector((std_logic'(R_ctrl_br_cmp) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(W_cmp_result))), A_WE_StdLogicVector((std_logic'(R_ctrl_rdctl_inst) = '1'), W_control_rd_data, W_alu_result(31 DOWNTO 0)));
W_wr_data <= W_wr_data_non_zero;
W_br_taken <= R_ctrl_br AND W_cmp_result;
W_mem_baddr <= W_alu_result(19 DOWNTO 0);
W_status_reg <= W_status_reg_pie;
E_wrctl_status <= R_ctrl_wrctl_inst AND to_std_logic(((D_iw_control_regnum = std_logic_vector'("000"))));
E_wrctl_estatus <= R_ctrl_wrctl_inst AND to_std_logic(((D_iw_control_regnum = std_logic_vector'("001"))));
E_wrctl_bstatus <= R_ctrl_wrctl_inst AND to_std_logic(((D_iw_control_regnum = std_logic_vector'("010"))));
E_wrctl_ienable <= R_ctrl_wrctl_inst AND to_std_logic(((D_iw_control_regnum = std_logic_vector'("011"))));
W_status_reg_pie_inst_nxt <= A_WE_StdLogic((std_logic'((((R_ctrl_exception OR R_ctrl_break) OR R_ctrl_crst))) = '1'), std_logic'('0'), A_WE_StdLogic((std_logic'((D_op_eret)) = '1'), W_estatus_reg, A_WE_StdLogic((std_logic'((D_op_bret)) = '1'), W_bstatus_reg, A_WE_StdLogic((std_logic'((E_wrctl_status)) = '1'), E_src1(0), W_status_reg_pie))));
W_status_reg_pie_nxt <= A_WE_StdLogic((std_logic'(E_valid) = '1'), W_status_reg_pie_inst_nxt, W_status_reg_pie);
W_estatus_reg_inst_nxt <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((R_ctrl_crst)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(A_WE_StdLogic((std_logic'((R_ctrl_exception)) = '1'), W_status_reg, A_WE_StdLogic((std_logic'((E_wrctl_estatus)) = '1'), E_src1(0), W_estatus_reg)))))));
W_estatus_reg_nxt <= A_WE_StdLogic((std_logic'(E_valid) = '1'), W_estatus_reg_inst_nxt, W_estatus_reg);
W_bstatus_reg_inst_nxt <= A_WE_StdLogic((std_logic'((R_ctrl_break)) = '1'), W_status_reg, A_WE_StdLogic((std_logic'((E_wrctl_bstatus)) = '1'), E_src1(0), W_bstatus_reg));
W_bstatus_reg_nxt <= A_WE_StdLogic((std_logic'(E_valid) = '1'), W_bstatus_reg_inst_nxt, W_bstatus_reg);
W_ienable_reg_nxt <= (A_WE_StdLogicVector((std_logic'(((E_wrctl_ienable AND E_valid))) = '1'), E_src1(31 DOWNTO 0), W_ienable_reg)) AND std_logic_vector'("00000000000000000000000000000000");
W_ipending_reg_nxt <= ((iactive AND W_ienable_reg) AND oci_ienable) AND std_logic_vector'("00000000000000000000000000000000");
process (clk, reset_n)
begin
if reset_n = '0' then
hbreak_enabled <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(E_valid) = '1' then
hbreak_enabled <= A_WE_StdLogic((std_logic'(R_ctrl_break) = '1'), std_logic'('0'), A_WE_StdLogic((std_logic'(D_op_bret) = '1'), std_logic'('1'), hbreak_enabled));
end if;
end if;
end process;
--the_Video_System_CPU_nios2_oci, which is an e_instance
the_Video_System_CPU_nios2_oci : Video_System_CPU_nios2_oci
port map(
jtag_debug_module_debugaccess_to_roms => internal_jtag_debug_module_debugaccess_to_roms,
oci_hbreak_req => oci_hbreak_req,
oci_ienable => oci_ienable,
oci_single_step_mode => oci_single_step_mode,
readdata => internal_jtag_debug_module_readdata,
resetrequest => internal_jtag_debug_module_resetrequest,
D_valid => D_valid,
E_st_data => E_st_data,
E_valid => E_valid,
F_pc => F_pc,
address => jtag_debug_module_address,
av_ld_data_aligned_filtered => av_ld_data_aligned_filtered,
begintransfer => jtag_debug_module_begintransfer,
byteenable => jtag_debug_module_byteenable,
chipselect => jtag_debug_module_select,
clk => jtag_debug_module_clk,
d_address => internal_d_address,
d_read => internal_d_read,
d_waitrequest => d_waitrequest,
d_write => internal_d_write,
debugaccess => jtag_debug_module_debugaccess,
hbreak_enabled => hbreak_enabled,
reset => jtag_debug_module_reset,
reset_n => reset_n,
test_ending => test_ending,
test_has_ended => test_has_ended,
write => jtag_debug_module_write,
writedata => jtag_debug_module_writedata
);
--jtag_debug_module, which is an e_avalon_slave
jtag_debug_module_clk <= clk;
jtag_debug_module_reset <= NOT reset_n;
D_ctrl_custom <= std_logic'('0');
R_ctrl_custom_nxt <= D_ctrl_custom;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_custom <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_custom <= R_ctrl_custom_nxt;
end if;
end if;
end process;
D_ctrl_custom_multi <= std_logic'('0');
R_ctrl_custom_multi_nxt <= D_ctrl_custom_multi;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_custom_multi <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt;
end if;
end if;
end process;
D_ctrl_jmp_indirect <= ((((((D_op_eret OR D_op_bret) OR D_op_rsvx17) OR D_op_rsvx25) OR D_op_ret) OR D_op_jmp) OR D_op_rsvx21) OR D_op_callr;
R_ctrl_jmp_indirect_nxt <= D_ctrl_jmp_indirect;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_jmp_indirect <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt;
end if;
end if;
end process;
D_ctrl_jmp_direct <= D_op_call OR D_op_jmpi;
R_ctrl_jmp_direct_nxt <= D_ctrl_jmp_direct;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_jmp_direct <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt;
end if;
end if;
end process;
D_ctrl_implicit_dst_retaddr <= D_op_call OR D_op_rsv02;
R_ctrl_implicit_dst_retaddr_nxt <= D_ctrl_implicit_dst_retaddr;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_implicit_dst_retaddr <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt;
end if;
end if;
end process;
D_ctrl_implicit_dst_eretaddr <= (((((D_op_div OR D_op_divu) OR D_op_mul) OR D_op_muli) OR D_op_mulxss) OR D_op_mulxsu) OR D_op_mulxuu;
R_ctrl_implicit_dst_eretaddr_nxt <= D_ctrl_implicit_dst_eretaddr;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_implicit_dst_eretaddr <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt;
end if;
end if;
end process;
D_ctrl_exception <= (((((((((D_op_trap OR D_op_rsvx44) OR D_op_div) OR D_op_divu) OR D_op_mul) OR D_op_muli) OR D_op_mulxss) OR D_op_mulxsu) OR D_op_mulxuu) OR D_op_intr) OR D_op_rsvx60;
R_ctrl_exception_nxt <= D_ctrl_exception;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_exception <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_exception <= R_ctrl_exception_nxt;
end if;
end if;
end process;
D_ctrl_break <= D_op_break OR D_op_hbreak;
R_ctrl_break_nxt <= D_ctrl_break;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_break <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_break <= R_ctrl_break_nxt;
end if;
end if;
end process;
D_ctrl_crst <= D_op_crst OR D_op_rsvx63;
R_ctrl_crst_nxt <= D_ctrl_crst;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_crst <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_crst <= R_ctrl_crst_nxt;
end if;
end if;
end process;
D_ctrl_uncond_cti_non_br <= ((((((((D_op_call OR D_op_jmpi) OR D_op_eret) OR D_op_bret) OR D_op_rsvx17) OR D_op_rsvx25) OR D_op_ret) OR D_op_jmp) OR D_op_rsvx21) OR D_op_callr;
R_ctrl_uncond_cti_non_br_nxt <= D_ctrl_uncond_cti_non_br;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_uncond_cti_non_br <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt;
end if;
end if;
end process;
D_ctrl_retaddr <= (((((((((((((((D_op_call OR D_op_rsv02) OR D_op_nextpc) OR D_op_callr) OR D_op_trap) OR D_op_rsvx44) OR D_op_div) OR D_op_divu) OR D_op_mul) OR D_op_muli) OR D_op_mulxss) OR D_op_mulxsu) OR D_op_mulxuu) OR D_op_intr) OR D_op_rsvx60) OR D_op_break) OR D_op_hbreak;
R_ctrl_retaddr_nxt <= D_ctrl_retaddr;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_retaddr <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_retaddr <= R_ctrl_retaddr_nxt;
end if;
end if;
end process;
D_ctrl_shift_logical <= ((D_op_slli OR D_op_sll) OR D_op_srli) OR D_op_srl;
R_ctrl_shift_logical_nxt <= D_ctrl_shift_logical;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_shift_logical <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt;
end if;
end if;
end process;
D_ctrl_shift_right_arith <= D_op_srai OR D_op_sra;
R_ctrl_shift_right_arith_nxt <= D_ctrl_shift_right_arith;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_shift_right_arith <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt;
end if;
end if;
end process;
D_ctrl_rot_right <= ((D_op_rsvx10 OR D_op_ror) OR D_op_rsvx42) OR D_op_rsvx43;
R_ctrl_rot_right_nxt <= D_ctrl_rot_right;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_rot_right <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_rot_right <= R_ctrl_rot_right_nxt;
end if;
end if;
end process;
D_ctrl_shift_rot_right <= ((((((D_op_srli OR D_op_srl) OR D_op_srai) OR D_op_sra) OR D_op_rsvx10) OR D_op_ror) OR D_op_rsvx42) OR D_op_rsvx43;
R_ctrl_shift_rot_right_nxt <= D_ctrl_shift_rot_right;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_shift_rot_right <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt;
end if;
end if;
end process;
D_ctrl_shift_rot <= ((((((((((((((D_op_slli OR D_op_rsvx50) OR D_op_sll) OR D_op_rsvx51) OR D_op_roli) OR D_op_rsvx34) OR D_op_rol) OR D_op_rsvx35) OR D_op_srli) OR D_op_srl) OR D_op_srai) OR D_op_sra) OR D_op_rsvx10) OR D_op_ror) OR D_op_rsvx42) OR D_op_rsvx43;
R_ctrl_shift_rot_nxt <= D_ctrl_shift_rot;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_shift_rot <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt;
end if;
end if;
end process;
D_ctrl_logic <= ((((((((D_op_and OR D_op_or) OR D_op_xor) OR D_op_nor) OR D_op_andhi) OR D_op_orhi) OR D_op_xorhi) OR D_op_andi) OR D_op_ori) OR D_op_xori;
R_ctrl_logic_nxt <= D_ctrl_logic;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_logic <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_logic <= R_ctrl_logic_nxt;
end if;
end if;
end process;
D_ctrl_hi_imm16 <= (D_op_andhi OR D_op_orhi) OR D_op_xorhi;
R_ctrl_hi_imm16_nxt <= D_ctrl_hi_imm16;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_hi_imm16 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt;
end if;
end if;
end process;
D_ctrl_unsigned_lo_imm16 <= (((((((((((D_op_cmpgeui OR D_op_cmpltui) OR D_op_andi) OR D_op_ori) OR D_op_xori) OR D_op_roli) OR D_op_rsvx10) OR D_op_slli) OR D_op_srli) OR D_op_rsvx34) OR D_op_rsvx42) OR D_op_rsvx50) OR D_op_srai;
R_ctrl_unsigned_lo_imm16_nxt <= D_ctrl_unsigned_lo_imm16;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_unsigned_lo_imm16 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt;
end if;
end if;
end process;
D_ctrl_br_uncond <= D_op_br OR D_op_rsv02;
R_ctrl_br_uncond_nxt <= D_ctrl_br_uncond;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_br_uncond <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt;
end if;
end if;
end process;
D_ctrl_br <= ((((((D_op_br OR D_op_bge) OR D_op_blt) OR D_op_bne) OR D_op_beq) OR D_op_bgeu) OR D_op_bltu) OR D_op_rsv62;
R_ctrl_br_nxt <= D_ctrl_br;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_br <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_br <= R_ctrl_br_nxt;
end if;
end if;
end process;
D_ctrl_alu_subtract <= ((((((((((((((D_op_sub OR D_op_rsvx25) OR D_op_cmplti) OR D_op_cmpltui) OR D_op_cmplt) OR D_op_cmpltu) OR D_op_blt) OR D_op_bltu) OR D_op_cmpgei) OR D_op_cmpgeui) OR D_op_cmpge) OR D_op_cmpgeu) OR D_op_bge) OR D_op_rsv10) OR D_op_bgeu) OR D_op_rsv42;
R_ctrl_alu_subtract_nxt <= D_ctrl_alu_subtract;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_alu_subtract <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt;
end if;
end if;
end process;
D_ctrl_alu_signed_comparison <= ((((D_op_cmpge OR D_op_cmpgei) OR D_op_cmplt) OR D_op_cmplti) OR D_op_bge) OR D_op_blt;
R_ctrl_alu_signed_comparison_nxt <= D_ctrl_alu_signed_comparison;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_alu_signed_comparison <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt;
end if;
end if;
end process;
D_ctrl_br_cmp <= ((((((((((((((((((((D_op_br OR D_op_bge) OR D_op_blt) OR D_op_bne) OR D_op_beq) OR D_op_bgeu) OR D_op_bltu) OR D_op_rsv62) OR D_op_cmpgei) OR D_op_cmplti) OR D_op_cmpnei) OR D_op_cmpgeui) OR D_op_cmpltui) OR D_op_cmpeqi) OR D_op_rsvx00) OR D_op_cmpge) OR D_op_cmplt) OR D_op_cmpne) OR D_op_cmpgeu) OR D_op_cmpltu) OR D_op_cmpeq) OR D_op_rsvx56;
R_ctrl_br_cmp_nxt <= D_ctrl_br_cmp;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_br_cmp <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt;
end if;
end if;
end process;
D_ctrl_ld_signed <= ((((((D_op_ldb OR D_op_ldh) OR D_op_ldl) OR D_op_ldw) OR D_op_ldbio) OR D_op_ldhio) OR D_op_ldwio) OR D_op_rsv63;
R_ctrl_ld_signed_nxt <= D_ctrl_ld_signed;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_ld_signed <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt;
end if;
end if;
end process;
D_ctrl_ld <= ((((((((((D_op_ldb OR D_op_ldh) OR D_op_ldl) OR D_op_ldw) OR D_op_ldbio) OR D_op_ldhio) OR D_op_ldwio) OR D_op_rsv63) OR D_op_ldbu) OR D_op_ldhu) OR D_op_ldbuio) OR D_op_ldhuio;
R_ctrl_ld_nxt <= D_ctrl_ld;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_ld <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_ld <= R_ctrl_ld_nxt;
end if;
end if;
end process;
D_ctrl_ld_non_io <= ((((D_op_ldbu OR D_op_ldhu) OR D_op_ldb) OR D_op_ldh) OR D_op_ldw) OR D_op_ldl;
R_ctrl_ld_non_io_nxt <= D_ctrl_ld_non_io;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_ld_non_io <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt;
end if;
end if;
end process;
D_ctrl_st <= ((((((D_op_stb OR D_op_sth) OR D_op_stw) OR D_op_stc) OR D_op_stbio) OR D_op_sthio) OR D_op_stwio) OR D_op_rsv61;
R_ctrl_st_nxt <= D_ctrl_st;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_st <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_st <= R_ctrl_st_nxt;
end if;
end if;
end process;
D_ctrl_ld_io <= ((((D_op_ldbuio OR D_op_ldhuio) OR D_op_ldbio) OR D_op_ldhio) OR D_op_ldwio) OR D_op_rsv63;
R_ctrl_ld_io_nxt <= D_ctrl_ld_io;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_ld_io <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_ld_io <= R_ctrl_ld_io_nxt;
end if;
end if;
end process;
D_ctrl_b_is_dst <= (((((((((((((((((((((((((((((((((((((D_op_addi OR D_op_andhi) OR D_op_orhi) OR D_op_xorhi) OR D_op_andi) OR D_op_ori) OR D_op_xori) OR D_op_call) OR D_op_rdprs) OR D_op_cmpgei) OR D_op_cmplti) OR D_op_cmpnei) OR D_op_cmpgeui) OR D_op_cmpltui) OR D_op_cmpeqi) OR D_op_jmpi) OR D_op_rsv09) OR D_op_rsv17) OR D_op_rsv25) OR D_op_rsv33) OR D_op_rsv41) OR D_op_rsv49) OR D_op_rsv57) OR D_op_ldb) OR D_op_ldh) OR D_op_ldl) OR D_op_ldw) OR D_op_ldbio) OR D_op_ldhio) OR D_op_ldwio) OR D_op_rsv63) OR D_op_ldbu) OR D_op_ldhu) OR D_op_ldbuio) OR D_op_ldhuio) OR D_op_initd) OR D_op_initda) OR D_op_flushd) OR D_op_flushda;
R_ctrl_b_is_dst_nxt <= D_ctrl_b_is_dst;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_b_is_dst <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt;
end if;
end if;
end process;
D_ctrl_ignore_dst <= ((((((((((((((((((((((D_op_br OR D_op_bge) OR D_op_blt) OR D_op_bne) OR D_op_beq) OR D_op_bgeu) OR D_op_bltu) OR D_op_rsv62) OR D_op_stb) OR D_op_sth) OR D_op_stw) OR D_op_stc) OR D_op_stbio) OR D_op_sthio) OR D_op_stwio) OR D_op_rsv61) OR D_op_jmpi) OR D_op_rsv09) OR D_op_rsv17) OR D_op_rsv25) OR D_op_rsv33) OR D_op_rsv41) OR D_op_rsv49) OR D_op_rsv57;
R_ctrl_ignore_dst_nxt <= D_ctrl_ignore_dst;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_ignore_dst <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt;
end if;
end if;
end process;
D_ctrl_src2_choose_imm <= (((((((((((((((((((((((((((((((((((((((((((((((((((((D_op_addi OR D_op_andhi) OR D_op_orhi) OR D_op_xorhi) OR D_op_andi) OR D_op_ori) OR D_op_xori) OR D_op_call) OR D_op_rdprs) OR D_op_cmpgei) OR D_op_cmplti) OR D_op_cmpnei) OR D_op_cmpgeui) OR D_op_cmpltui) OR D_op_cmpeqi) OR D_op_jmpi) OR D_op_rsv09) OR D_op_rsv17) OR D_op_rsv25) OR D_op_rsv33) OR D_op_rsv41) OR D_op_rsv49) OR D_op_rsv57) OR D_op_ldb) OR D_op_ldh) OR D_op_ldl) OR D_op_ldw) OR D_op_ldbio) OR D_op_ldhio) OR D_op_ldwio) OR D_op_rsv63) OR D_op_ldbu) OR D_op_ldhu) OR D_op_ldbuio) OR D_op_ldhuio) OR D_op_initd) OR D_op_initda) OR D_op_flushd) OR D_op_flushda) OR D_op_stb) OR D_op_sth) OR D_op_stw) OR D_op_stc) OR D_op_stbio) OR D_op_sthio) OR D_op_stwio) OR D_op_rsv61) OR D_op_roli) OR D_op_rsvx10) OR D_op_slli) OR D_op_srli) OR D_op_rsvx34) OR D_op_rsvx42) OR D_op_rsvx50) OR D_op_srai;
R_ctrl_src2_choose_imm_nxt <= D_ctrl_src2_choose_imm;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_src2_choose_imm <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt;
end if;
end if;
end process;
D_ctrl_wrctl_inst <= D_op_wrctl;
R_ctrl_wrctl_inst_nxt <= D_ctrl_wrctl_inst;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_wrctl_inst <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt;
end if;
end if;
end process;
D_ctrl_rdctl_inst <= D_op_rdctl;
R_ctrl_rdctl_inst_nxt <= D_ctrl_rdctl_inst;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_rdctl_inst <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt;
end if;
end if;
end process;
D_ctrl_force_src2_zero <= ((((((((((((((((D_op_call OR D_op_rsv02) OR D_op_nextpc) OR D_op_callr) OR D_op_trap) OR D_op_rsvx44) OR D_op_intr) OR D_op_rsvx60) OR D_op_break) OR D_op_hbreak) OR D_op_eret) OR D_op_bret) OR D_op_rsvx17) OR D_op_rsvx25) OR D_op_ret) OR D_op_jmp) OR D_op_rsvx21) OR D_op_jmpi;
R_ctrl_force_src2_zero_nxt <= D_ctrl_force_src2_zero;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_force_src2_zero <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt;
end if;
end if;
end process;
D_ctrl_alu_force_xor <= ((((((((((((((((D_op_cmpgei OR D_op_cmpgeui) OR D_op_cmpeqi) OR D_op_cmpge) OR D_op_cmpgeu) OR D_op_cmpeq) OR D_op_cmpnei) OR D_op_cmpne) OR D_op_bge) OR D_op_rsv10) OR D_op_bgeu) OR D_op_rsv42) OR D_op_beq) OR D_op_rsv34) OR D_op_bne) OR D_op_rsv62) OR D_op_br) OR D_op_rsv02;
R_ctrl_alu_force_xor_nxt <= D_ctrl_alu_force_xor;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_alu_force_xor <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt;
end if;
end if;
end process;
--data_master, which is an e_avalon_master
--instruction_master, which is an e_avalon_master
--vhdl renameroo for output signals
d_address <= internal_d_address;
--vhdl renameroo for output signals
d_byteenable <= internal_d_byteenable;
--vhdl renameroo for output signals
d_read <= internal_d_read;
--vhdl renameroo for output signals
d_write <= internal_d_write;
--vhdl renameroo for output signals
i_address <= internal_i_address;
--vhdl renameroo for output signals
i_read <= internal_i_read;
--vhdl renameroo for output signals
jtag_debug_module_debugaccess_to_roms <= internal_jtag_debug_module_debugaccess_to_roms;
--vhdl renameroo for output signals
jtag_debug_module_readdata <= internal_jtag_debug_module_readdata;
--vhdl renameroo for output signals
jtag_debug_module_resetrequest <= internal_jtag_debug_module_resetrequest;
--synthesis translate_off
F_inst <= A_WE_StdLogicVector((std_logic'((F_op_call)) = '1'), std_logic_vector'("00100000001000000010000001100011011000010110110001101100"), A_WE_StdLogicVector((std_logic'((F_op_jmpi)) = '1'), std_logic_vector'("00100000001000000010000001101010011011010111000001101001"), A_WE_StdLogicVector((std_logic'((F_op_ldbu)) = '1'), std_logic_vector'("00100000001000000010000001101100011001000110001001110101"), A_WE_StdLogicVector((std_logic'((F_op_addi)) = '1'), std_logic_vector'("00100000001000000010000001100001011001000110010001101001"), A_WE_StdLogicVector((std_logic'((F_op_stb)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111010001100010"), A_WE_StdLogicVector((std_logic'((F_op_br)) = '1'), std_logic_vector'("00100000001000000010000000100000001000000110001001110010"), A_WE_StdLogicVector((std_logic'((F_op_ldb)) = '1'), std_logic_vector'("00100000001000000010000000100000011011000110010001100010"), A_WE_StdLogicVector((std_logic'((F_op_cmpgei)) = '1'), std_logic_vector'("00100000011000110110110101110000011001110110010101101001"), A_WE_StdLogicVector((std_logic'((F_op_ldhu)) = '1'), std_logic_vector'("00100000001000000010000001101100011001000110100001110101"), A_WE_StdLogicVector((std_logic'((F_op_andi)) = '1'), std_logic_vector'("00100000001000000010000001100001011011100110010001101001"), A_WE_StdLogicVector((std_logic'((F_op_sth)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111010001101000"), A_WE_StdLogicVector((std_logic'((F_op_bge)) = '1'), std_logic_vector'("00100000001000000010000000100000011000100110011101100101"), A_WE_StdLogicVector((std_logic'((F_op_ldh)) = '1'), std_logic_vector'("00100000001000000010000000100000011011000110010001101000"), A_WE_StdLogicVector((std_logic'((F_op_cmplti)) = '1'), std_logic_vector'("00100000011000110110110101110000011011000111010001101001"), A_WE_StdLogicVector((std_logic'((F_op_initda)) = '1'), std_logic_vector'("00100000011010010110111001101001011101000110010001100001"), A_WE_StdLogicVector((std_logic'((F_op_ori)) = '1'), std_logic_vector'("00100000001000000010000000100000011011110111001001101001"), A_WE_StdLogicVector((std_logic'((F_op_stw)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111010001110111"), A_WE_StdLogicVector((std_logic'((F_op_blt)) = '1'), std_logic_vector'("00100000001000000010000000100000011000100110110001110100"), A_WE_StdLogicVector((std_logic'((F_op_ldw)) = '1'), std_logic_vector'("00100000001000000010000000100000011011000110010001110111"), A_WE_StdLogicVector((std_logic'((F_op_cmpnei)) = '1'), std_logic_vector'("00100000011000110110110101110000011011100110010101101001"), A_WE_StdLogicVector((std_logic'((F_op_flushda)) = '1'), std_logic_vector'("01100110011011000111010101110011011010000110010001100001"), A_WE_StdLogicVector((std_logic'((F_op_xori)) = '1'), std_logic_vector'("00100000001000000010000001111000011011110111001001101001"), A_WE_StdLogicVector((std_logic'((F_op_bne)) = '1'), std_logic_vector'("00100000001000000010000000100000011000100110111001100101"), A_WE_StdLogicVector((std_logic'((F_op_cmpeqi)) = '1'), std_logic_vector'("00100000011000110110110101110000011001010111000101101001"), A_WE_StdLogicVector((std_logic'((F_op_ldbuio)) = '1'), std_logic_vector'("00100000011011000110010001100010011101010110100101101111"), A_WE_StdLogicVector((std_logic'((F_op_muli)) = '1'), std_logic_vector'("00100000001000000010000001101101011101010110110001101001"), A_WE_StdLogicVector((std_logic'((F_op_stbio)) = '1'), std_logic_vector'("00100000001000000111001101110100011000100110100101101111"), A_WE_StdLogicVector((std_logic'((F_op_beq)) = '1'), std_logic_vector'("00100000001000000010000000100000011000100110010101110001"), A_WE_StdLogicVector((std_logic'((F_op_ldbio)) = '1'), std_logic_vector'("00100000001000000110110001100100011000100110100101101111"), A_WE_StdLogicVector((std_logic'((F_op_cmpgeui)) = '1'), std_logic_vector'("01100011011011010111000001100111011001010111010101101001"), A_WE_StdLogicVector((std_logic'((F_op_ldhuio)) = '1'), std_logic_vector'("00100000011011000110010001101000011101010110100101101111"), A_WE_StdLogicVector((std_logic'((F_op_andhi)) = '1'), std_logic_vector'("00100000001000000110000101101110011001000110100001101001"), A_WE_StdLogicVector((std_logic'((F_op_sthio)) = '1'), std_logic_vector'("00100000001000000111001101110100011010000110100101101111"), A_WE_StdLogicVector((std_logic'((F_op_bgeu)) = '1'), std_logic_vector'("00100000001000000010000001100010011001110110010101110101"), A_WE_StdLogicVector((std_logic'((F_op_ldhio)) = '1'), std_logic_vector'("00100000001000000110110001100100011010000110100101101111"), A_WE_StdLogicVector((std_logic'((F_op_cmpltui)) = '1'), std_logic_vector'("01100011011011010111000001101100011101000111010101101001"), A_WE_StdLogicVector((std_logic'((F_op_initd)) = '1'), std_logic_vector'("00100000001000000110100101101110011010010111010001100100"), A_WE_StdLogicVector((std_logic'((F_op_orhi)) = '1'), std_logic_vector'("00100000001000000010000001101111011100100110100001101001"), A_WE_StdLogicVector((std_logic'((F_op_stwio)) = '1'), std_logic_vector'("00100000001000000111001101110100011101110110100101101111"), A_WE_StdLogicVector((std_logic'((F_op_bltu)) = '1'), std_logic_vector'("00100000001000000010000001100010011011000111010001110101"), A_WE_StdLogicVector((std_logic'((F_op_ldwio)) = '1'), std_logic_vector'("00100000001000000110110001100100011101110110100101101111"), A_WE_StdLogicVector((std_logic'((F_op_flushd)) = '1'), std_logic_vector'("00100000011001100110110001110101011100110110100001100100"), A_WE_StdLogicVector((std_logic'((F_op_xorhi)) = '1'), std_logic_vector'("00100000001000000111100001101111011100100110100001101001"), A_WE_StdLogicVector((std_logic'((F_op_eret)) = '1'), std_logic_vector'("00100000001000000010000001100101011100100110010101110100"), A_WE_StdLogicVector((std_logic'((F_op_roli)) = '1'), std_logic_vector'("00100000001000000010000001110010011011110110110001101001"), A_WE_StdLogicVector((std_logic'((F_op_rol)) = '1'), std_logic_vector'("00100000001000000010000000100000011100100110111101101100"), A_WE_StdLogicVector((std_logic'((F_op_flushp)) = '1'), std_logic_vector'("00100000011001100110110001110101011100110110100001110000"), A_WE_StdLogicVector((std_logic'((F_op_ret)) = '1'), std_logic_vector'("00100000001000000010000000100000011100100110010101110100"), A_WE_StdLogicVector((std_logic'((F_op_nor)) = '1'), std_logic_vector'("00100000001000000010000000100000011011100110111101110010"), A_WE_StdLogicVector((std_logic'((F_op_mulxuu)) = '1'), std_logic_vector'("00100000011011010111010101101100011110000111010101110101"), A_WE_StdLogicVector((std_logic'((F_op_cmpge)) = '1'), std_logic_vector'("00100000001000000110001101101101011100000110011101100101"), A_WE_StdLogicVector((std_logic'((F_op_bret)) = '1'), std_logic_vector'("00100000001000000010000001100010011100100110010101110100"), A_WE_StdLogicVector((std_logic'((F_op_ror)) = '1'), std_logic_vector'("00100000001000000010000000100000011100100110111101110010"), A_WE_StdLogicVector((std_logic'((F_op_flushi)) = '1'), std_logic_vector'("00100000011001100110110001110101011100110110100001101001"), A_WE_StdLogicVector((std_logic'((F_op_jmp)) = '1'), std_logic_vector'("00100000001000000010000000100000011010100110110101110000"), A_WE_StdLogicVector((std_logic'((F_op_and)) = '1'), std_logic_vector'("00100000001000000010000000100000011000010110111001100100"), A_WE_StdLogicVector((std_logic'((F_op_cmplt)) = '1'), std_logic_vector'("00100000001000000110001101101101011100000110110001110100"), A_WE_StdLogicVector((std_logic'((F_op_slli)) = '1'), std_logic_vector'("00100000001000000010000001110011011011000110110001101001"), A_WE_StdLogicVector((std_logic'((F_op_sll)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110110110001101100"), A_WE_StdLogicVector((std_logic'((F_op_or)) = '1'), std_logic_vector'("00100000001000000010000000100000001000000110111101110010"), A_WE_StdLogicVector((std_logic'((F_op_mulxsu)) = '1'), std_logic_vector'("00100000011011010111010101101100011110000111001101110101"), A_WE_StdLogicVector((std_logic'((F_op_cmpne)) = '1'), std_logic_vector'("00100000001000000110001101101101011100000110111001100101"), A_WE_StdLogicVector((std_logic'((F_op_srli)) = '1'), std_logic_vector'("00100000001000000010000001110011011100100110110001101001"), A_WE_StdLogicVector((std_logic'((F_op_srl)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111001001101100"), A_WE_StdLogicVector((std_logic'((F_op_nextpc)) = '1'), std_logic_vector'("00100000011011100110010101111000011101000111000001100011"), A_WE_StdLogicVector((std_logic'((F_op_callr)) = '1'), std_logic_vector'("00100000001000000110001101100001011011000110110001110010"), A_WE_StdLogicVector((std_logic'((F_op_xor)) = '1'), std_logic_vector'("00100000001000000010000000100000011110000110111101110010"), A_WE_StdLogicVector((std_logic'((F_op_mulxss)) = '1'), std_logic_vector'("00100000011011010111010101101100011110000111001101110011"), A_WE_StdLogicVector((std_logic'((F_op_cmpeq)) = '1'), std_logic_vector'("00100000001000000110001101101101011100000110010101110001"), A_WE_StdLogicVector((std_logic'((F_op_divu)) = '1'), std_logic_vector'("00100000001000000010000001100100011010010111011001110101"), A_WE_StdLogicVector((std_logic'((F_op_div)) = '1'), std_logic_vector'("00100000001000000010000000100000011001000110100101110110"), A_WE_StdLogicVector((std_logic'((F_op_rdctl)) = '1'), std_logic_vector'("00100000001000000111001001100100011000110111010001101100"), A_WE_StdLogicVector((std_logic'((F_op_mul)) = '1'), std_logic_vector'("00100000001000000010000000100000011011010111010101101100"), A_WE_StdLogicVector((std_logic'((F_op_cmpgeu)) = '1'), std_logic_vector'("00100000011000110110110101110000011001110110010101110101"), A_WE_StdLogicVector((std_logic'((F_op_initi)) = '1'), std_logic_vector'("00100000001000000110100101101110011010010111010001101001"), A_WE_StdLogicVector((std_logic'((F_op_trap)) = '1'), std_logic_vector'("00100000001000000010000001110100011100100110000101110000"), A_WE_StdLogicVector((std_logic'((F_op_wrctl)) = '1'), std_logic_vector'("00100000001000000111011101110010011000110111010001101100"), A_WE_StdLogicVector((std_logic'((F_op_cmpltu)) = '1'), std_logic_vector'("00100000011000110110110101110000011011000111010001110101"), A_WE_StdLogicVector((std_logic'((F_op_add)) = '1'), std_logic_vector'("00100000001000000010000000100000011000010110010001100100"), A_WE_StdLogicVector((std_logic'((F_op_break)) = '1'), std_logic_vector'("00100000001000000110001001110010011001010110000101101011"), A_WE_StdLogicVector((std_logic'((F_op_hbreak)) = '1'), std_logic_vector'("00100000011010000110001001110010011001010110000101101011"), A_WE_StdLogicVector((std_logic'((F_op_sync)) = '1'), std_logic_vector'("00100000001000000010000001110011011110010110111001100011"), A_WE_StdLogicVector((std_logic'((F_op_sub)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111010101100010"), A_WE_StdLogicVector((std_logic'((F_op_srai)) = '1'), std_logic_vector'("00100000001000000010000001110011011100100110000101101001"), A_WE_StdLogicVector((std_logic'((F_op_sra)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111001001100001"), A_WE_StdLogicVector((std_logic'((F_op_intr)) = '1'), std_logic_vector'("00100000001000000010000001101001011011100111010001110010"), std_logic_vector'("00100000001000000010000000100000010000100100000101000100")))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))));
D_inst <= A_WE_StdLogicVector((std_logic'((D_op_call)) = '1'), std_logic_vector'("00100000001000000010000001100011011000010110110001101100"), A_WE_StdLogicVector((std_logic'((D_op_jmpi)) = '1'), std_logic_vector'("00100000001000000010000001101010011011010111000001101001"), A_WE_StdLogicVector((std_logic'((D_op_ldbu)) = '1'), std_logic_vector'("00100000001000000010000001101100011001000110001001110101"), A_WE_StdLogicVector((std_logic'((D_op_addi)) = '1'), std_logic_vector'("00100000001000000010000001100001011001000110010001101001"), A_WE_StdLogicVector((std_logic'((D_op_stb)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111010001100010"), A_WE_StdLogicVector((std_logic'((D_op_br)) = '1'), std_logic_vector'("00100000001000000010000000100000001000000110001001110010"), A_WE_StdLogicVector((std_logic'((D_op_ldb)) = '1'), std_logic_vector'("00100000001000000010000000100000011011000110010001100010"), A_WE_StdLogicVector((std_logic'((D_op_cmpgei)) = '1'), std_logic_vector'("00100000011000110110110101110000011001110110010101101001"), A_WE_StdLogicVector((std_logic'((D_op_ldhu)) = '1'), std_logic_vector'("00100000001000000010000001101100011001000110100001110101"), A_WE_StdLogicVector((std_logic'((D_op_andi)) = '1'), std_logic_vector'("00100000001000000010000001100001011011100110010001101001"), A_WE_StdLogicVector((std_logic'((D_op_sth)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111010001101000"), A_WE_StdLogicVector((std_logic'((D_op_bge)) = '1'), std_logic_vector'("00100000001000000010000000100000011000100110011101100101"), A_WE_StdLogicVector((std_logic'((D_op_ldh)) = '1'), std_logic_vector'("00100000001000000010000000100000011011000110010001101000"), A_WE_StdLogicVector((std_logic'((D_op_cmplti)) = '1'), std_logic_vector'("00100000011000110110110101110000011011000111010001101001"), A_WE_StdLogicVector((std_logic'((D_op_initda)) = '1'), std_logic_vector'("00100000011010010110111001101001011101000110010001100001"), A_WE_StdLogicVector((std_logic'((D_op_ori)) = '1'), std_logic_vector'("00100000001000000010000000100000011011110111001001101001"), A_WE_StdLogicVector((std_logic'((D_op_stw)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111010001110111"), A_WE_StdLogicVector((std_logic'((D_op_blt)) = '1'), std_logic_vector'("00100000001000000010000000100000011000100110110001110100"), A_WE_StdLogicVector((std_logic'((D_op_ldw)) = '1'), std_logic_vector'("00100000001000000010000000100000011011000110010001110111"), A_WE_StdLogicVector((std_logic'((D_op_cmpnei)) = '1'), std_logic_vector'("00100000011000110110110101110000011011100110010101101001"), A_WE_StdLogicVector((std_logic'((D_op_flushda)) = '1'), std_logic_vector'("01100110011011000111010101110011011010000110010001100001"), A_WE_StdLogicVector((std_logic'((D_op_xori)) = '1'), std_logic_vector'("00100000001000000010000001111000011011110111001001101001"), A_WE_StdLogicVector((std_logic'((D_op_bne)) = '1'), std_logic_vector'("00100000001000000010000000100000011000100110111001100101"), A_WE_StdLogicVector((std_logic'((D_op_cmpeqi)) = '1'), std_logic_vector'("00100000011000110110110101110000011001010111000101101001"), A_WE_StdLogicVector((std_logic'((D_op_ldbuio)) = '1'), std_logic_vector'("00100000011011000110010001100010011101010110100101101111"), A_WE_StdLogicVector((std_logic'((D_op_muli)) = '1'), std_logic_vector'("00100000001000000010000001101101011101010110110001101001"), A_WE_StdLogicVector((std_logic'((D_op_stbio)) = '1'), std_logic_vector'("00100000001000000111001101110100011000100110100101101111"), A_WE_StdLogicVector((std_logic'((D_op_beq)) = '1'), std_logic_vector'("00100000001000000010000000100000011000100110010101110001"), A_WE_StdLogicVector((std_logic'((D_op_ldbio)) = '1'), std_logic_vector'("00100000001000000110110001100100011000100110100101101111"), A_WE_StdLogicVector((std_logic'((D_op_cmpgeui)) = '1'), std_logic_vector'("01100011011011010111000001100111011001010111010101101001"), A_WE_StdLogicVector((std_logic'((D_op_ldhuio)) = '1'), std_logic_vector'("00100000011011000110010001101000011101010110100101101111"), A_WE_StdLogicVector((std_logic'((D_op_andhi)) = '1'), std_logic_vector'("00100000001000000110000101101110011001000110100001101001"), A_WE_StdLogicVector((std_logic'((D_op_sthio)) = '1'), std_logic_vector'("00100000001000000111001101110100011010000110100101101111"), A_WE_StdLogicVector((std_logic'((D_op_bgeu)) = '1'), std_logic_vector'("00100000001000000010000001100010011001110110010101110101"), A_WE_StdLogicVector((std_logic'((D_op_ldhio)) = '1'), std_logic_vector'("00100000001000000110110001100100011010000110100101101111"), A_WE_StdLogicVector((std_logic'((D_op_cmpltui)) = '1'), std_logic_vector'("01100011011011010111000001101100011101000111010101101001"), A_WE_StdLogicVector((std_logic'((D_op_initd)) = '1'), std_logic_vector'("00100000001000000110100101101110011010010111010001100100"), A_WE_StdLogicVector((std_logic'((D_op_orhi)) = '1'), std_logic_vector'("00100000001000000010000001101111011100100110100001101001"), A_WE_StdLogicVector((std_logic'((D_op_stwio)) = '1'), std_logic_vector'("00100000001000000111001101110100011101110110100101101111"), A_WE_StdLogicVector((std_logic'((D_op_bltu)) = '1'), std_logic_vector'("00100000001000000010000001100010011011000111010001110101"), A_WE_StdLogicVector((std_logic'((D_op_ldwio)) = '1'), std_logic_vector'("00100000001000000110110001100100011101110110100101101111"), A_WE_StdLogicVector((std_logic'((D_op_flushd)) = '1'), std_logic_vector'("00100000011001100110110001110101011100110110100001100100"), A_WE_StdLogicVector((std_logic'((D_op_xorhi)) = '1'), std_logic_vector'("00100000001000000111100001101111011100100110100001101001"), A_WE_StdLogicVector((std_logic'((D_op_eret)) = '1'), std_logic_vector'("00100000001000000010000001100101011100100110010101110100"), A_WE_StdLogicVector((std_logic'((D_op_roli)) = '1'), std_logic_vector'("00100000001000000010000001110010011011110110110001101001"), A_WE_StdLogicVector((std_logic'((D_op_rol)) = '1'), std_logic_vector'("00100000001000000010000000100000011100100110111101101100"), A_WE_StdLogicVector((std_logic'((D_op_flushp)) = '1'), std_logic_vector'("00100000011001100110110001110101011100110110100001110000"), A_WE_StdLogicVector((std_logic'((D_op_ret)) = '1'), std_logic_vector'("00100000001000000010000000100000011100100110010101110100"), A_WE_StdLogicVector((std_logic'((D_op_nor)) = '1'), std_logic_vector'("00100000001000000010000000100000011011100110111101110010"), A_WE_StdLogicVector((std_logic'((D_op_mulxuu)) = '1'), std_logic_vector'("00100000011011010111010101101100011110000111010101110101"), A_WE_StdLogicVector((std_logic'((D_op_cmpge)) = '1'), std_logic_vector'("00100000001000000110001101101101011100000110011101100101"), A_WE_StdLogicVector((std_logic'((D_op_bret)) = '1'), std_logic_vector'("00100000001000000010000001100010011100100110010101110100"), A_WE_StdLogicVector((std_logic'((D_op_ror)) = '1'), std_logic_vector'("00100000001000000010000000100000011100100110111101110010"), A_WE_StdLogicVector((std_logic'((D_op_flushi)) = '1'), std_logic_vector'("00100000011001100110110001110101011100110110100001101001"), A_WE_StdLogicVector((std_logic'((D_op_jmp)) = '1'), std_logic_vector'("00100000001000000010000000100000011010100110110101110000"), A_WE_StdLogicVector((std_logic'((D_op_and)) = '1'), std_logic_vector'("00100000001000000010000000100000011000010110111001100100"), A_WE_StdLogicVector((std_logic'((D_op_cmplt)) = '1'), std_logic_vector'("00100000001000000110001101101101011100000110110001110100"), A_WE_StdLogicVector((std_logic'((D_op_slli)) = '1'), std_logic_vector'("00100000001000000010000001110011011011000110110001101001"), A_WE_StdLogicVector((std_logic'((D_op_sll)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110110110001101100"), A_WE_StdLogicVector((std_logic'((D_op_or)) = '1'), std_logic_vector'("00100000001000000010000000100000001000000110111101110010"), A_WE_StdLogicVector((std_logic'((D_op_mulxsu)) = '1'), std_logic_vector'("00100000011011010111010101101100011110000111001101110101"), A_WE_StdLogicVector((std_logic'((D_op_cmpne)) = '1'), std_logic_vector'("00100000001000000110001101101101011100000110111001100101"), A_WE_StdLogicVector((std_logic'((D_op_srli)) = '1'), std_logic_vector'("00100000001000000010000001110011011100100110110001101001"), A_WE_StdLogicVector((std_logic'((D_op_srl)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111001001101100"), A_WE_StdLogicVector((std_logic'((D_op_nextpc)) = '1'), std_logic_vector'("00100000011011100110010101111000011101000111000001100011"), A_WE_StdLogicVector((std_logic'((D_op_callr)) = '1'), std_logic_vector'("00100000001000000110001101100001011011000110110001110010"), A_WE_StdLogicVector((std_logic'((D_op_xor)) = '1'), std_logic_vector'("00100000001000000010000000100000011110000110111101110010"), A_WE_StdLogicVector((std_logic'((D_op_mulxss)) = '1'), std_logic_vector'("00100000011011010111010101101100011110000111001101110011"), A_WE_StdLogicVector((std_logic'((D_op_cmpeq)) = '1'), std_logic_vector'("00100000001000000110001101101101011100000110010101110001"), A_WE_StdLogicVector((std_logic'((D_op_divu)) = '1'), std_logic_vector'("00100000001000000010000001100100011010010111011001110101"), A_WE_StdLogicVector((std_logic'((D_op_div)) = '1'), std_logic_vector'("00100000001000000010000000100000011001000110100101110110"), A_WE_StdLogicVector((std_logic'((D_op_rdctl)) = '1'), std_logic_vector'("00100000001000000111001001100100011000110111010001101100"), A_WE_StdLogicVector((std_logic'((D_op_mul)) = '1'), std_logic_vector'("00100000001000000010000000100000011011010111010101101100"), A_WE_StdLogicVector((std_logic'((D_op_cmpgeu)) = '1'), std_logic_vector'("00100000011000110110110101110000011001110110010101110101"), A_WE_StdLogicVector((std_logic'((D_op_initi)) = '1'), std_logic_vector'("00100000001000000110100101101110011010010111010001101001"), A_WE_StdLogicVector((std_logic'((D_op_trap)) = '1'), std_logic_vector'("00100000001000000010000001110100011100100110000101110000"), A_WE_StdLogicVector((std_logic'((D_op_wrctl)) = '1'), std_logic_vector'("00100000001000000111011101110010011000110111010001101100"), A_WE_StdLogicVector((std_logic'((D_op_cmpltu)) = '1'), std_logic_vector'("00100000011000110110110101110000011011000111010001110101"), A_WE_StdLogicVector((std_logic'((D_op_add)) = '1'), std_logic_vector'("00100000001000000010000000100000011000010110010001100100"), A_WE_StdLogicVector((std_logic'((D_op_break)) = '1'), std_logic_vector'("00100000001000000110001001110010011001010110000101101011"), A_WE_StdLogicVector((std_logic'((D_op_hbreak)) = '1'), std_logic_vector'("00100000011010000110001001110010011001010110000101101011"), A_WE_StdLogicVector((std_logic'((D_op_sync)) = '1'), std_logic_vector'("00100000001000000010000001110011011110010110111001100011"), A_WE_StdLogicVector((std_logic'((D_op_sub)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111010101100010"), A_WE_StdLogicVector((std_logic'((D_op_srai)) = '1'), std_logic_vector'("00100000001000000010000001110011011100100110000101101001"), A_WE_StdLogicVector((std_logic'((D_op_sra)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111001001100001"), A_WE_StdLogicVector((std_logic'((D_op_intr)) = '1'), std_logic_vector'("00100000001000000010000001101001011011100111010001110010"), std_logic_vector'("00100000001000000010000000100000010000100100000101000100")))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))));
F_vinst <= A_WE_StdLogicVector((std_logic'(F_valid) = '1'), F_inst, A_REP_VECTOR(std_logic_vector'("00101101"), 7));
D_vinst <= A_WE_StdLogicVector((std_logic'(D_valid) = '1'), D_inst, A_REP_VECTOR(std_logic_vector'("00101101"), 7));
R_vinst <= A_WE_StdLogicVector((std_logic'(R_valid) = '1'), D_inst, A_REP_VECTOR(std_logic_vector'("00101101"), 7));
E_vinst <= A_WE_StdLogicVector((std_logic'(E_valid) = '1'), D_inst, A_REP_VECTOR(std_logic_vector'("00101101"), 7));
W_vinst <= A_WE_StdLogicVector((std_logic'(W_valid) = '1'), D_inst, A_REP_VECTOR(std_logic_vector'("00101101"), 7));
--synthesis translate_on
end europa;
| gpl-2.0 | ecd6384a9bb48eef1c085a8f8b83494a | 0.611047 | 3.481219 | false | false | false | false |
DreamIP/GPStudio | support/io/com/hdl/com_to_flow.vhd | 1 | 4,310 | -- This block extracts the GPStudio header and gets flags Start of Frame and End of Frame.
-- It outputs a flow depending on this header (generate Flow valid and Data valid according to the flags).
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.com_package.all;
entity com_to_flow is
generic (
ID_FIFO : std_logic_vector(5 downto 0):="000001";
FLOW_OUT_SIZE : integer := 8;
DATA_WIDTH : integer := 8;
FIFO_DEPTH : integer := 2048
);
port (
clk_hal : in std_logic;
clk_proc : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
flow_out_data : out std_logic_vector(FLOW_OUT_SIZE-1 downto 0);
flow_out_fv : out std_logic;
flow_out_dv : out std_logic;
write_data : in std_logic;
data_in : in std_logic_vector(7 downto 0)
);
end com_to_flow;
architecture RTL of com_to_flow is
type fsm_com_to_flow is (idle, header, wr_data_st);
signal state : fsm_com_to_flow;
signal reset : std_logic;
signal empty_fifo : std_logic;
signal empty_fifo_dl : std_logic;
signal wrreq : std_logic;
signal set_wrreq : std_logic;
signal rdreq,rdreq_dl : std_logic;
signal sof : std_logic;
signal eof : std_logic;
signal write_data_dl : std_logic;
signal id_detected : std_logic_vector(5 downto 0);
begin
reset <= not reset_n;
--- Fifo that synchronizes data of the flow on clk_proc
fifo_data_inst : entity work.gp_dcfifo
generic map (DATA_WIDTH => 8,
FIFO_DEPTH => FIFO_DEPTH)
port map(
aclr => reset,
data => data_in,
rdclk => clk_proc,
rdreq => rdreq,
wrclk => clk_hal,
wrreq => wrreq,
q => flow_out_data,
rdempty => empty_fifo
);
--- Filter and remove GPStudio header to get flags and write only the data in the FIFO
process(clk_hal, reset_n)
begin
if reset_n='0' then
sof <= '0';
eof <= '0';
id_detected <= "000000";
elsif clk_hal'event and clk_hal='1' then
write_data_dl <= write_data;
case(state) is
when idle =>
set_wrreq <= '0';
if write_data='1' and write_data_dl='0' then
sof <= data_in(1);
eof <= data_in(0);
id_detected <= data_in(7 downto 2);
state <= header;
end if;
when header =>
if write_data='1' then
if id_detected=ID_FIFO then
state <= wr_data_st;
set_wrreq <= '1';
else
state <= idle;
set_wrreq <= '0';
end if;
end if;
when wr_data_st =>
if write_data='0' and write_data_dl='0' then
state <= idle;
end if;
when others =>
state <= idle;
end case;
end if;
end process;
wrreq <= set_wrreq when state=idle or state=header else
write_data;
--- Set data valid, flow valid and control the read request of the fifo
process(clk_proc, reset_n)
begin
if reset_n='0' then
rdreq <= '0';
flow_out_fv <= '0';
elsif clk_proc'event and clk_proc='1' then
rdreq <= not empty_fifo;
rdreq_dl <= rdreq;
empty_fifo_dl <= empty_fifo;
if rdreq='1' and rdreq_dl='0' then
if sof='1' then
flow_out_fv <= '1';
end if;
elsif empty_fifo='1' and empty_fifo_dl='0' then
if eof='1' then
flow_out_fv <= '0';
end if;
end if;
end if;
end process;
flow_out_dv <= rdreq_dl and not empty_fifo;
end RTL;
| gpl-3.0 | c3abe143b21e8b9e01fd96c1a97a4d23 | 0.470998 | 3.886384 | false | false | false | false |
DreamIP/GPStudio | support/process/negate/hdl/negate_slave.vhd | 1 | 1,868 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity negate_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end negate_slave;
architecture rtl of negate_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 2))=>
status_reg_enable_bit_reg <= datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 2))=>
datard_o <= "0000000000000000000000000000000" & status_reg_enable_bit_reg;
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
end rtl;
| gpl-3.0 | c07ad63e7c0a69654144c68cff22476f | 0.543897 | 3.171477 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/binaryEncoderRtl.vhd | 3 | 4,039 | -------------------------------------------------------------------------------
--! @file binaryEncoderRtl.vhd
--
--! @brief Generic Binary Encoder with reduced or-operation
--
--! @details This generic binary encoder can be configured to any width,
--! however, mind base 2 values. In order to reduce the complexity of the
--! synthesized circuit the reduced or-operation is applied.
-- (Borrowed from academic.csuohio.edu/chu_p and applied coding styles)
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity binaryEncoder is
generic (
--! One-hot data width
gDataWidth : natural := 8
);
port (
--! One hot code input
iOneHot : in std_logic_vector(gDataWidth-1 downto 0);
--! Binary encoded output
oBinary : out std_logic_vector(LogDualis(gDataWidth)-1 downto 0)
);
end binaryEncoder;
architecture rtl of binaryEncoder is
type tMaskArray is array(LogDualis(gDataWidth)-1 downto 0) of
std_logic_vector(gDataWidth-1 downto 0);
signal mask : tMaskArray;
function genOrMask return tMaskArray is
variable vOrMask: tMaskArray;
begin
for i in (LogDualis(gDataWidth)-1) downto 0 loop
for j in (gDataWidth-1) downto 0 loop
if (j/(2**i) mod 2)= 1 then
vOrMask(i)(j) := '1';
else
vOrMask(i)(j) := '0';
end if;
end loop;
end loop;
return vOrMask;
end function;
begin
mask <= genOrMask;
process (
mask,
iOneHot
)
variable rowVector : std_logic_vector(gDataWidth-1 downto 0);
variable tempBit : std_logic;
begin
for i in (LogDualis(gDataWidth)-1) downto 0 loop
rowVector := iOneHot and mask(i);
-- reduced or operation
tempBit := '0';
for j in (gDataWidth-1) downto 0 loop
tempBit := tempBit or rowVector(j);
end loop;
oBinary(i) <= tempBit;
end loop;
end process;
end rtl;
| gpl-2.0 | 4a86c377e7af77e574ca109622aa004c | 0.618965 | 4.49277 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/convRmiiToMii-rtl-ea.vhd | 3 | 11,024 | -------------------------------------------------------------------------------
--! @file convRmiiToMii-rtl-ea.vhd
--
--! @brief RMII-to-MII converter
--
--! @details This is an RMII-to-MII converter to convert MII phy traces to RMII.
--! Example: MII PHY <--> RMII-to-MII converter <--> RMII MAC
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use openmac package
use work.openmacPkg.all;
entity convRmiiToMii is
port (
--! Reset
iRst : in std_logic;
--! RMII Clock
iClk : in std_logic;
--! RMII transmit path
iRmiiTx : in tRmiiPath;
--! RMII receive path
oRmiiRx : out tRmiiPath;
--! MII receive clock
iMiiRxClk : in std_logic;
--! MII receive path
iMiiRx : in tMiiPath;
--! MII receive error
iMiiRxError : in std_logic;
--! MII transmit clock
iMiiTxClk : in std_logic;
--! MII transmit path
oMiiTx : out tMiiPath
);
end convRmiiToMii;
architecture rtl of convRmiiToMii is
constant DIBIT_SIZE : integer := 2;
constant NIBBLE_SIZE : integer := 4;
begin
TX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_full, fifo_empty, fifo_valid, txEnable_reg : std_logic;
signal fifo_wr, fifo_rd : std_logic;
signal fifo_din : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout, txData_reg : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector (FIFO_NIBBLES_LOG2-1 downto 0);
--necessary for clr fifo
signal aclr, rTxEn_l : std_logic;
--convert dibits to nibble
signal sel_dibit : std_logic;
signal fifo_din_reg : std_logic_vector(iRmiiTx.data'range);
begin
fifo_din <= iRmiiTx.data & fifo_din_reg;
fifo_wr <= sel_dibit;
--convert dibits to nibble (to fit to fifo)
process(iClk, iRst)
begin
if iRst = cActivated then
sel_dibit <= cInactivated;
fifo_din_reg <= (others => cInactivated);
elsif iClk = cActivated and iClk'event then
if iRmiiTx.enable = cActivated then
sel_dibit <= not sel_dibit;
if sel_dibit = cInactivated then
fifo_din_reg <= iRmiiTx.data;
end if;
else
sel_dibit <= cInactivated;
end if;
end if;
end process;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
oMiiTx.data <= txData_reg;
oMiiTx.enable <= txEnable_reg;
process(iMiiTxClk, iRst)
begin
if iRst = cActivated then
fifo_rd <= cInactivated;
fifo_valid <= cInactivated;
txData_reg <= (others => cInactivated);
txEnable_reg <= cInactivated;
elsif iMiiTxClk = cActivated and iMiiTxClk'event then
txData_reg <= fifo_dout;
txEnable_reg <= fifo_valid;
if fifo_rd = cInactivated and fifo_half = cActivated then
fifo_rd <= cActivated;
elsif fifo_rd = cActivated and fifo_empty = cActivated then
fifo_rd <= cInactivated;
end if;
if fifo_rd = cActivated and fifo_rdUsedWord > std_logic_vector(to_unsigned(1, fifo_rdUsedWord'length)) then
fifo_valid <= cActivated;
else
fifo_valid <= cInactivated;
end if;
end if;
end process;
--! This is the asynchronous FIFO used to decouple RMII from MII.
TXFIFO : entity work.asyncFifo
generic map (
gDataWidth => NIBBLE_SIZE,
gWordSize => 2**FIFO_NIBBLES_LOG2,
gSyncStages => 2,
gMemRes => "ON"
)
port map (
iAclr => aclr,
iWrClk => iClk,
iWrReq => fifo_wr,
iWrData => fifo_din,
oWrEmpty => open,
oWrFull => fifo_full,
oWrUsedw => open,
iRdClk => iMiiTxClk,
iRdReq => fifo_rd,
oRdData => fifo_dout,
oRdEmpty => fifo_empty,
oRdFull => open,
oRdUsedw => fifo_rdUsedWord
);
--sync Mii Tx En (=fifo_valid) to wr clk
process(iClk, iRst)
begin
if iRst = cActivated then
aclr <= cActivated; --reset fifo
rTxEn_l <= cInactivated;
elsif iClk = cActivated and iClk'event then
rTxEn_l <= iRmiiTx.enable;
aclr <= cInactivated; --default
--clear the full fifo after TX on RMII side is done
if fifo_full = cActivated and rTxEn_l = cActivated and iRmiiTx.enable = cInactivated then
aclr <= cActivated;
end if;
end if;
end process;
end block;
RX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_empty, fifo_valid : std_logic;
signal rxDataValid_reg, fifo_rd : std_logic;
signal rxError_reg : std_logic;
signal fifo_wr : std_logic;
signal rxData_reg : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
signal fifo_wrUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
--convert nibble to dibits
signal sel_dibit : std_logic;
signal fifo_rd_s : std_logic;
begin
process(iMiiRxClk, iRst)
begin
if iRst = cActivated then
rxData_reg <= (others => cInactivated);
rxDataValid_reg <= cInactivated;
rxError_reg <= cInactivated;
elsif iMiiRxClk = cActivated and iMiiRxClk'event then
rxData_reg <= iMiiRx.data;
rxDataValid_reg <= iMiiRx.enable;
rxError_reg <= iMiiRxError;
end if;
end process;
fifo_wr <= rxDataValid_reg and not rxError_reg;
oRmiiRx.data <= fifo_dout(fifo_dout'right+1 downto 0) when sel_dibit = cActivated else
fifo_dout(fifo_dout'left downto fifo_dout'left-1);
oRmiiRx.enable <= fifo_valid;
fifo_rd <= fifo_rd_s and not sel_dibit;
process(iClk, iRst)
begin
if iRst = cActivated then
sel_dibit <= cInactivated;
elsif iClk = cActivated and iClk'event then
if fifo_rd_s = cActivated or fifo_valid = cActivated then
sel_dibit <= not sel_dibit;
else
sel_dibit <= cInactivated;
end if;
end if;
end process;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
process(iClk, iRst)
begin
if iRst = cActivated then
fifo_rd_s <= cInactivated;
fifo_valid <= cInactivated;
elsif iClk = cActivated and iClk'event then
if fifo_rd_s = cInactivated and fifo_half = cActivated then
fifo_rd_s <= cActivated;
elsif fifo_rd_s = cActivated and fifo_empty = cActivated then
fifo_rd_s <= cInactivated;
end if;
if fifo_rd_s = cActivated then
fifo_valid <= cActivated;
else
fifo_valid <= cInactivated;
end if;
end if;
end process;
--! This is the asynchronous FIFO used to decouple RMII from MII.
RXFIFO : entity work.asyncFifo
generic map (
gDataWidth => NIBBLE_SIZE,
gWordSize => 2**FIFO_NIBBLES_LOG2,
gSyncStages => 2,
gMemRes => "ON"
)
port map (
iAclr => iRst,
iWrClk => iMiiRxClk,
iWrReq => fifo_wr,
iWrData => rxData_reg,
oWrEmpty => open,
oWrFull => open,
oWrUsedw => open,
iRdClk => iClk,
iRdReq => fifo_rd,
oRdData => fifo_dout,
oRdEmpty => fifo_empty,
oRdFull => open,
oRdUsedw => fifo_rdUsedWord
);
end block;
end rtl;
| gpl-2.0 | 98651def4ca2e2f811a19fee215c6bc1 | 0.529935 | 4.73743 | false | false | false | false |
bpervan/simple-soc | pcores/led_axi_ip_v1_00_a/hdl/vhdl/led_axi_ip.vhd | 1 | 16,687 | ------------------------------------------------------------------------------
-- led_axi_ip.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: led_axi_ip.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue Mar 25 15:35:46 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library led_axi_ip_v1_00_a;
use led_axi_ip_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity led_axi_ip is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
LED : out std_logic_vector (7 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity led_axi_ip;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of led_axi_ip is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 1;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity led_axi_ip_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
LED => LED,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
| mit | 26e4fc7adeea08477af84d2147c0daa2 | 0.457182 | 4.1572 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/ICMP/icmp.vhd | 1 | 18,234 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.axi.all;
use work.ipv4_types.all;
entity icmp is
port(
ip_rx_start : in std_logic; -- indicates receipt of ip frame.
ip_rx : in ipv4_rx_type;
ip_tx_start : out std_logic;
ip_tx_data_out_rdy : in std_logic;
ip_tx_result : in std_logic_vector(1 downto 0);
icmp_tx : out ipv4_tx_type;
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic;
icmp_rx_count : out std_logic_vector(15 downto 0);
icmp_tx_count : out std_logic_vector(15 downto 0);
req_ip_layer : out std_logic;
granted_ip_layer : in std_logic
);
end entity;
architecture rtl of icmp is
--RX side
type state_0 is(idle, echo_request, code, checksum_1, checksum_2, identifier_1, identifier_2, sequence_number_1, sequence_number_2, data_odd,
data_even, last_data_odd, last_data_even, start_req_tx, wait_for_last);
signal state_rx : state_0;
signal data_to_crc, data_in : std_logic_vector(7 downto 0);
signal data_word : std_logic_vector(15 downto 0);
signal data_length, data_length_1 : std_logic_vector(15 downto 0);
signal checksum_long : std_logic_vector(16 downto 0);
signal checksumInt, checksum : std_logic_vector(15 downto 0);
signal checksum_icmp : std_logic_vector(15 downto 0);
signal data_icmp : std_logic;
signal crc_init, crc_en, crc_en_2 : std_logic;
signal odd_event : std_logic;
signal start_tx : std_logic;
--FF
signal ff_reset_int, ff_rdreq_int, ff_wrreq_int, ff_empty_int, ff_full_int : std_logic;
signal ff_data_in_int, ff_data_out_int : std_logic_vector(7 downto 0);
--TX side
type state_1 is(idle_tx, echo_reply_tx, code_tx, checksum_1_tx, checksum_2_tx, identifier_1_tx, identifier_2_tx, sequence_number_1_tx, sequence_number_2_tx, data_tx, reload_ff_read_req);
signal state_tx : state_1;
signal ack_start_tx, transmit_done : std_logic;
signal checksum_tx_0, checksum_tx_1 : std_logic_vector(15 downto 0);
signal dst_ip, dst_ip_0, dst_ip_1 : std_logic_vector(31 downto 0);
signal icmp_tx_data_tmp : std_logic_vector(7 downto 0);
signal icmp_tx_dv_tmp, icmp_tx_first_tmp : std_logic;
signal icmp_tx_last, icmp_tx_dv, icmp_tx_first : std_logic;
signal icmp_tx_data : std_logic_vector(7 downto 0);
signal icmp_data_length : std_logic_vector(15 downto 0);
--test purpose
signal en_count_rx_int, en_count_tx_int : std_logic;
signal icmp_rx_count_int, icmp_tx_count_int : std_logic_vector(15 downto 0);
begin
data_in <= ip_rx.data.data_in;
-----FIFO SYNC clock domains & store data icmp
ff_icmp_inst : entity work.ff_icmp PORT MAP (
aclr => ff_reset_int,
data => ff_data_in_int,--data_in,
rdclk => tx_clk,
rdreq => ff_rdreq_int,
wrclk => rx_clk,
wrreq => ff_wrreq_int,
q => ff_data_out_int,
rdempty => ff_empty_int,
wrfull => ff_full_int
);
-----CHECKSUM COMPUTE
checksumInt <= checksum_long(15 downto 0) + checksum_long(16);
checksum <= NOT checksumInt;
process(rx_clk)
begin
if rising_edge(rx_clk) then
crc_en_2 <= crc_en;
if crc_init = '1' then
checksum_long <= (others => '0');
elsif crc_en_2 = '1' then
checksum_long <= ('0' & checkSumInt) + ('0' & data_word);
end if;
end if;
end process;
process(tx_clk)--sync stage
begin
if rising_edge(tx_clk) then
checksum_tx_0 <= checksum;
checksum_tx_1 <= checksum_tx_0;
dst_ip_0 <= dst_ip;--ip_rx.hdr.src_ip_addr;
dst_ip_1 <= dst_ip_0;
data_length_1 <= data_length;
icmp_data_length <= data_length_1;
end if;
end process;
icmp_rx_count <= icmp_rx_count_int;
-----STATES RX
process(rx_clk, reset)
begin
if reset = '1' then
en_count_rx_int<= '0';
icmp_rx_count_int<= (others => '0');
dst_ip <= (others => '0');
data_word <= (others => '0');
data_length <= (others => '0');
ff_reset_int <= '0';
ff_wrreq_int <= '0';
ff_data_in_int <= (others => '0');
crc_init <= '1';
crc_en <= '0';
odd_event <= '0';
start_tx <= '0';
state_rx <= idle;
elsif rising_edge(rx_clk) then
en_count_rx_int <= '0';
data_word <= data_word(7 downto 0) & ff_data_in_int;
if en_count_rx_int = '1' then
icmp_rx_count_int <= icmp_rx_count_int + 1;
end if;
case state_rx is
-------------------------------------------
when idle =>
odd_event <= '0';
start_tx <= '0';
if transmit_done = '1' then
dst_ip <= (others => '0');
crc_init <= '1';
crc_en <= '0';
data_length <= (others => '0');
ff_reset_int <= '1';
ff_wrreq_int <= '0';
ff_data_in_int <= (others => '0');
state_rx <= echo_request;
else
dst_ip <= dst_ip;
crc_init <= '0';
crc_en <= '0';
data_length <= data_length;
ff_reset_int <= '0';
ff_wrreq_int <= '0';
ff_data_in_int <= (others => '0');
state_rx <= idle;
end if;
-------------------------------------------
when echo_request =>
ff_reset_int <= '0';
ff_wrreq_int <= '0';
crc_init <= '0';
odd_event <= '0';
start_tx <= '0';
if ip_rx.data.data_in_valid = '1' and ip_rx_start = '1' then
if ip_rx.hdr.protocol = x"01" and ip_rx.hdr.is_valid = '1' then
dst_ip <= ip_rx.hdr.src_ip_addr;
if data_in = x"08" then --only take echo request
ff_data_in_int <= (others => '0');--reply for crc
crc_en <= '0';
data_length <= ip_rx.hdr.data_length;
state_rx <= code;
else
crc_en <= '0';
ff_data_in_int <= (others => '0');
data_length <= (others => '0');
state_rx <= wait_for_last;
end if;
else
crc_en <= '0';
ff_data_in_int <= (others => '0');
data_length <= (others => '0');
state_rx <= wait_for_last;
end if;
else
crc_en <= '0';
ff_data_in_int <= (others => '0');
data_length <= (others => '0');
state_rx <= echo_request;--idle;
end if;
-------------------------------------------
when code =>
ff_reset_int <= '0';
ff_wrreq_int <= '0';
ff_data_in_int <= (others => '0');
crc_init <= '0';
odd_event <= '0';
start_tx <= '0';
if data_length > 504 then --can not handle such big data 504
crc_en <= '0';
data_length <= (others => '0');
state_rx <= wait_for_last;
else
data_length <= data_length;
if ip_rx.data.data_in_valid = '1' then
crc_en <= '1';
state_rx <= checksum_1;
else
crc_en <= '0';
state_rx <= code;
end if;
end if;
-------------------------------------------
when checksum_1 =>
ff_reset_int <= '0';
ff_wrreq_int <= '0';
ff_data_in_int <= (others => '0');
crc_init <= '0';
data_length <= data_length;
--odd_event <= '0';
start_tx <= '0';
if ip_rx.data.data_in_valid = '1' then
crc_en <= '0';
odd_event <= '1';--checksum non pris en compte dans le calcul
state_rx <= checksum_2;
else
crc_en <= '0';
odd_event <= '0';
state_rx <= checksum_1;
end if;
-------------------------------------------
when checksum_2 =>
ff_reset_int <= '0';
ff_wrreq_int <= '0';
ff_data_in_int <= (others => '0');
crc_init <= '0';
data_length <= data_length;
--odd_event <= '0';
start_tx <= '0';
if ip_rx.data.data_in_valid = '1' then
crc_en <= '1';
odd_event <= '1';--checksum non pris en compte dans le calcul
state_rx <= identifier_1;
else
crc_en <= '0';
odd_event <= '0';
state_rx <= checksum_2;
end if;
-------------------------------------------
when identifier_1 =>
ff_reset_int <= '0';
ff_data_in_int <= data_in;
crc_init <= '0';
data_length <= data_length;
odd_event <= '0';
start_tx <= '0';
if ip_rx.data.data_in_valid = '1' then
ff_wrreq_int<= '1';
crc_en <= '0';
data_length <= data_length;
state_rx <= identifier_2;
else
ff_wrreq_int<= '0';
crc_en <= '0';
data_length <= data_length;
state_rx <= identifier_1;
end if;
-------------------------------------------
when identifier_2 =>
ff_reset_int <= '0';
ff_data_in_int <= data_in;
crc_init <= '0';
data_length <= data_length;
odd_event <= '0';
start_tx <= '0';
if ip_rx.data.data_in_valid = '1' then
ff_wrreq_int<= '1';
crc_en <= '1';
data_length <= data_length;
state_rx <= sequence_number_1;
else
ff_wrreq_int<= '0';
crc_en <= '0';
data_length <= data_length;
state_rx <= identifier_2;
end if;
-------------------------------------------
when sequence_number_1 =>
ff_reset_int <= '0';
ff_data_in_int <= data_in;
crc_init <= '0';
data_length <= data_length;
odd_event <= '0';
start_tx <= '0';
if ip_rx.data.data_in_valid = '1' then
ff_wrreq_int<= '1';
crc_en <= '0';
data_length <= data_length;
state_rx <= sequence_number_2;
else
ff_wrreq_int<= '0';
crc_en <= '0';
data_length <= data_length;
state_rx <= sequence_number_1;
end if;
-------------------------------------------
when sequence_number_2 =>
ff_reset_int <= '0';
ff_data_in_int <= data_in;
crc_init <= '0';
data_length <= data_length;
odd_event <= '0';
start_tx <= '0';
if ip_rx.data.data_in_valid = '1' then
crc_en <= '1';
ff_wrreq_int<= '1';
data_length <= data_length;
state_rx <= data_odd;
else
crc_en <= '0';
ff_wrreq_int<= '0';
data_length <= data_length;
state_rx <= sequence_number_2;
end if;
-------------------------------------------
when data_odd =>
ff_reset_int <= '0';
ff_data_in_int <= data_in;
crc_init <= '0';
data_length <= data_length;
start_tx <= '0';
if ip_rx.data.data_in_valid = '1' then
if ip_rx.data.data_in_last = '1' then
crc_en <= '0';
ff_wrreq_int<= '1';
data_length <= data_length;
odd_event <= '1';
state_rx <= last_data_odd;--ajouter un octet à zero pour le checksum
else
crc_en <= '0';
ff_wrreq_int<= '1';
data_length <= data_length;
odd_event <= '0';
state_rx <= data_even;
end if;
else
crc_en <= '0';
ff_wrreq_int<= '0';
data_length <= data_length;
odd_event <= '0';
state_rx <= data_odd;
end if;
-------------------------------------------
when data_even =>
ff_reset_int <= '0';
ff_data_in_int <= data_in;
crc_init <= '0';
data_length <= data_length;
odd_event <= '0';
start_tx <= '0';
if ip_rx.data.data_in_valid = '1' then
if ip_rx.data.data_in_last = '1' then
crc_en <= '1';
ff_wrreq_int<= '1';
data_length <= data_length;
state_rx <= last_data_even;
else
crc_en <= '1';
ff_wrreq_int<= '1';
data_length <= data_length;
state_rx <= data_odd;
end if;
else
crc_en <= '0';
ff_wrreq_int<= '0';
data_length <= data_length;
state_rx <= data_even;
end if;
-------------------------------------------
when last_data_odd =>
ff_reset_int <= '0';
ff_wrreq_int <= '0';
ff_data_in_int <= (others => '0');
crc_en <= '1';
crc_init <= '0';
data_length <= data_length;
odd_event <= '0';
start_tx <= '0';
state_rx <= start_req_tx;
-------------------------------------------
when last_data_even =>
ff_reset_int <= '0';
ff_wrreq_int <= '0';
ff_data_in_int <= data_in;
crc_en <= '0';
crc_init <= '0';
data_length <= data_length;
odd_event <= '0';
start_tx <= '0';
state_rx <= start_req_tx;
-------------------------------------------
when start_req_tx =>
ff_reset_int <= '0';
ff_wrreq_int <= '0';
--ff_data_in_int <= (others => '0');
crc_en <= '0';
crc_init <= '0';
data_length <= data_length;
odd_event <= '0';
if ack_start_tx = '1' then
en_count_rx_int <= '1';
start_tx <= '0';
state_rx <= idle;
else
start_tx <= '1';
state_rx <= start_req_tx;
end if;
-------------------------------------------
when wait_for_last =>
ff_reset_int <= '1';
ff_wrreq_int <= '0';
crc_en <= '0';
crc_init <= '1';
data_length <= (others => '0');
odd_event <= '0';
start_tx <= '0';
if ip_rx.data.data_in_last = '1' then
state_rx <= idle;
else
state_rx <= wait_for_last;
end if;
when others =>
end case;
end if;
end process;
-----STATES TX
icmp_tx.data.data_out <= icmp_tx_data_tmp;--icmp_tx_data;
icmp_tx.data.data_out_valid <= icmp_tx_dv or icmp_tx_dv_tmp ;--icmp_tx_dv;
icmp_tx.data.data_out_last <= icmp_tx_last;
icmp_tx.hdr.protocol <= x"01";
icmp_tx.hdr.data_length <= icmp_data_length;
icmp_tx.hdr.dst_ip_addr <= dst_ip_1;
icmp_tx_count <= icmp_tx_count_int;
process(tx_clk, reset)
begin
if reset = '1' then
en_count_tx_int <= '0';
icmp_tx_count_int <= (others => '0');
ip_tx_start <= '0';
ff_rdreq_int <= '0';
ack_start_tx <= '0';
req_ip_layer <= '0';
transmit_done <= '1';
icmp_tx_data_tmp <= (others => '0');
icmp_tx_data <= (others => '0');
icmp_tx_dv_tmp <= '0';
icmp_tx_dv <= '0';
icmp_tx_first_tmp <= '0';
icmp_tx_first <= '0';
icmp_tx_last <= '0';
state_tx <= idle_tx;
elsif rising_edge(tx_clk) then
en_count_tx_int <= '0';
if en_count_tx_int = '1' then
icmp_tx_count_int <= icmp_tx_count_int + 1;
end if;
icmp_tx_data <= icmp_tx_data_tmp;
icmp_tx_dv <= icmp_tx_dv_tmp;
icmp_tx_first <= icmp_tx_first_tmp;
case state_tx is
when idle_tx =>
ff_rdreq_int <= '0';
--req_ip_layer <= '0';
if start_tx = '1' then
--ack_start_tx <= '1';--acknowledge to rx, rx can go idle
--transmit_done <= '0';
if granted_ip_layer = '1' then--arbiter granted us access to ip_tx layer
ip_tx_start <= '1';--tell ip layer to start fsm
req_ip_layer <= '1';
ack_start_tx <= '1';--acknowledge to rx, rx can go idle
transmit_done <= '0';
icmp_tx_data_tmp <= (others => '0');
icmp_tx_dv_tmp <= '0';
icmp_tx_first_tmp <= '0';
icmp_tx_last <= '0';
state_tx <= echo_reply_tx;
else
ip_tx_start <= '0';
req_ip_layer <= '1';
ack_start_tx <= '0';
transmit_done <= '1';
icmp_tx_data_tmp <= (others => '0');
icmp_tx_dv_tmp <= '0';
icmp_tx_first_tmp <= '0';
icmp_tx_last <= '0';
state_tx <= idle_tx;
end if;
else
ip_tx_start <= '0';
req_ip_layer <= '0';
ack_start_tx <= '0';
transmit_done <= '1';
icmp_tx_data_tmp <= (others => '0');
icmp_tx_dv_tmp <= '0';
icmp_tx_first_tmp <= '0';
icmp_tx_last <= '0';
state_tx <= idle_tx;
end if;
--when WAIT_GRANTED =>
when echo_reply_tx =>
ip_tx_start <= '0';
if ip_tx_data_out_rdy = '1' then
ff_rdreq_int <= '0';
ack_start_tx <= '0';
req_ip_layer <= '1';
transmit_done <= '0';
icmp_tx_data_tmp <= (others => '0');--type = reply
icmp_tx_dv_tmp <= '1';
icmp_tx_first_tmp <= '1';--first byte
icmp_tx_last <= '0';
state_tx <= code_tx;
end if;
when code_tx =>
if ip_tx_data_out_rdy = '1' then
ip_tx_start <= '0';
ff_rdreq_int <= '0';
ack_start_tx <= '0';
req_ip_layer <= '1';
transmit_done <= '0';
icmp_tx_data_tmp <= (others => '0');--code = 0
icmp_tx_dv_tmp <= '1';
icmp_tx_first_tmp <= '0';--
icmp_tx_last <= '0';
state_tx <= checksum_1_tx;
end if;
when checksum_1_tx =>
if ip_tx_data_out_rdy = '1' then
ip_tx_start <= '0';
ff_rdreq_int <= '1';
ack_start_tx <= '0';
req_ip_layer <= '1';
transmit_done <= '0';
icmp_tx_data_tmp <= checksum_tx_1(15 downto 8);--checksum MSB
icmp_tx_dv_tmp <= '1';
icmp_tx_first_tmp <= '0';--
icmp_tx_last <= '0';
state_tx <= checksum_2_tx;
end if;
when checksum_2_tx =>
if ip_tx_data_out_rdy = '1' then
ip_tx_start <= '0';
ff_rdreq_int <= '1';
ack_start_tx <= '0';
req_ip_layer <= '1';
transmit_done <= '0';
icmp_tx_data_tmp <= checksum_tx_1(7 downto 0);--checksum LSB
icmp_tx_dv_tmp <= '1';
icmp_tx_first_tmp <= '0';
icmp_tx_last <= '0';
state_tx <= data_tx;
end if;
when data_tx =>
ip_tx_start <= '0';
if ip_tx_data_out_rdy = '1' then
if ff_empty_int = '1' then
en_count_tx_int <= '1';
ff_rdreq_int <= '0';
ack_start_tx <= '0';
req_ip_layer <= '0';
transmit_done <= '1';
icmp_tx_data_tmp <= ff_data_out_int;--checksum LSB
icmp_tx_dv_tmp <= '0';
icmp_tx_first_tmp <= '0';
icmp_tx_last <= '1';
state_tx <= idle_tx;
else
ff_rdreq_int <= '1';
ack_start_tx <= '0';
req_ip_layer <= '1';
transmit_done <= '0';
icmp_tx_data_tmp <= ff_data_out_int;--checksum LSB
icmp_tx_dv_tmp <= '1';
icmp_tx_first_tmp <= '0';
icmp_tx_last <= '0';
state_tx <= data_tx;
end if;
else
ff_rdreq_int <= '0';
ack_start_tx <= '0';
req_ip_layer <= '1';
transmit_done <= '0';
icmp_tx_data_tmp <= ff_data_out_int;--checksum LSB
icmp_tx_dv_tmp <= '0';
icmp_tx_first_tmp <= '0';
icmp_tx_last <= '0';
state_tx <= reload_ff_read_req;
end if;
when reload_ff_read_req =>--pas certain
if ip_tx_data_out_rdy = '1' then
ip_tx_start <= '0';
ff_rdreq_int <= '1';
ack_start_tx <= '0';
req_ip_layer <= '1';
transmit_done <= '0';
icmp_tx_data_tmp <= ff_data_out_int;--checksum LSB
icmp_tx_dv_tmp <= '0';
icmp_tx_first_tmp <= '0';
icmp_tx_last <= '0';
state_tx <= data_tx;
end if;
when others =>
ip_tx_start <= '0';
ff_rdreq_int <= '0';
ack_start_tx <= '0';
req_ip_layer <= '0';
transmit_done <= '1';
icmp_tx_data_tmp <= (others => '0');
icmp_tx_dv_tmp <= '0';
icmp_tx_first_tmp <= '0';
icmp_tx_last <= '0';
state_tx <= idle_tx;
end case;
end if;
end process;
end architecture;
| gpl-3.0 | 4df08ff325dccba2a113592c7020e5b8 | 0.507377 | 2.433987 | false | false | false | false |
buserror/xc3sprog | bscan_spi/bscan_s3_spi_isf.vhd | 5 | 4,693 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
end top;
architecture Behavioral of top is
signal CAPTURE: std_logic;
signal UPDATE: std_logic;
signal DRCK1: std_logic;
signal TDI: std_logic;
signal TDO1: std_logic;
signal CSB: std_logic := '1';
signal header: std_logic_vector(47 downto 0);
signal len: std_logic_vector(15 downto 0);
signal have_header : std_logic := '0';
signal MISO: std_logic;
signal MOSI: std_logic;
signal SEL1: std_logic;
signal SHIFT: std_logic;
signal RESET: std_logic;
signal CS_GO: std_logic := '0';
signal CS_GO_PREP: std_logic := '0';
signal CS_STOP: std_logic := '0';
signal CS_STOP_PREP: std_logic := '0';
signal RAM_RADDR: std_logic_vector(13 downto 0);
signal RAM_WADDR: std_logic_vector(13 downto 0);
signal DRCK1_INV : std_logic;
signal RAM_DO: std_logic_vector(0 downto 0);
signal RAM_DI: std_logic_vector(0 downto 0);
signal RAM_WE: std_logic := '0';
begin
DRCK1_INV <= not DRCK1;
RAMB16_S1_S1_inst : RAMB16_S1_S1
port map (
DOA => RAM_DO, -- Port A 1-bit Data Output
DOB => open, -- Port B 1-bit Data Output
ADDRA => RAM_RADDR, -- Port A 14-bit Address Input
ADDRB => RAM_WADDR, -- Port B 14-bit Address Input
CLKA => DRCK1_inv, -- Port A Clock
CLKB => DRCK1, -- Port B Clock
DIA => "0", -- Port A 1-bit Data Input
DIB => RAM_DI, -- Port B 1-bit Data Input
ENA => '1', -- Port A RAM Enable Input
ENB => '1', -- PortB RAM Enable Input
SSRA => '0', -- Port A Synchronous Set/Reset Input
SSRB => '0', -- Port B Synchronous Set/Reset Input
WEA => '0', -- Port A Write Enable Input
WEB => RAM_WE -- Port B Write Enable Input
);
BSCAN_SPARTAN3A_inst : BSCAN_SPARTAN3A
port map (
CAPTURE => CAPTURE, -- CAPTURE output from TAP controller
DRCK1 => DRCK1, -- Data register output for USER1 functions
DRCK2 => open, -- Data register output for USER2 functions
RESET => RESET, -- Reset output from TAP controller
SEL1 => SEL1, -- USER1 active output
SEL2 => open, -- USER2 active output
SHIFT => SHIFT, -- SHIFT output from TAP controller
TCK => open, -- TCK output from TAP controller
TDI => TDI, -- TDI output from TAP controller
TMS => open, -- TMS output from TAP controller
UPDATE => UPDATE, -- UPDATE output from TAP controller
TDO1 => TDO1, --TDO1, -- Data input for USER1 function
TDO2 => '0' -- Data input for USER2 function
);
SPI_ACCESS_inst : SPI_ACCESS
generic map (
SIM_DEVICE => "UNSPECIFIED" --"3S50AN", "3S200AN", "3S400AN", "3S700AN", "3S1400AN"
)
port map (
MISO => MISO, --TDO1, -- Serial output data from SPI PROM
CLK => DRCK1, -- SPI PROM clock input
CSB => CSB, -- SPI PROM enable input
MOSI => MOSI -- Serial input data to SPI PROM
);
MOSI <= TDI;
CSB <= '0' when CS_GO = '1' and CS_STOP = '0' else '1';
RAM_DI <= MISO & "";
TDO1 <= RAM_DO(0);
-- falling edges
process(DRCK1, CAPTURE, RESET, UPDATE, SEL1)
begin
if CAPTURE = '1' or RESET='1' or UPDATE='1' or SEL1='0' then
have_header <= '0';
-- disable CSB
CS_GO_PREP <= '0';
CS_STOP <= '0';
elsif falling_edge(DRCK1) then
-- disable CSB?
CS_STOP <= CS_STOP_PREP;
-- waiting for header?
if have_header='0' then
-- got magic + len
if header(46 downto 15) = x"59a659a6" then
len <= header(14 downto 0) & "0";
have_header <= '1';
-- enable CSB on rising edge (if len > 0?)
if (header(14 downto 0) & "0") /= x"0000" then
CS_GO_PREP <= '1';
end if;
end if;
elsif len /= x"0000" then
len <= len - 1;
end if;
end if;
end process;
-- rising edges
process(DRCK1, CAPTURE, RESET, UPDATE, SEL1)
begin
if CAPTURE = '1' or RESET='1' or UPDATE='1' or SEL1='0' then
-- disable CSB
CS_GO <= '0';
CS_STOP_PREP <= '0';
RAM_WADDR <= (others => '0');
RAM_RADDR <= (others => '0');
RAM_WE <= '0';
elsif rising_edge(DRCK1) then
RAM_RADDR <= RAM_RADDR + 1;
RAM_WE <= not CSB;
if RAM_WE='1' then
RAM_WADDR <= RAM_WADDR + 1;
end if;
header <= header(46 downto 0) & TDI;
-- enable CSB?
CS_GO <= CS_GO_PREP;
-- disable CSB on falling edge
if CS_GO = '1' and len = x"0000" then
CS_STOP_PREP <= '1';
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 8b5da027c725d4b65bcffef70e6e94ad | 0.576177 | 3.143336 | false | false | false | false |
bpervan/simple-soc | pcores/uart_cntrl_v1_00_a/hdl/vhdl/user_logic.vhd | 1 | 11,006 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Thu Mar 27 15:00:40 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
library uart_cntrl_v1_00_a;
use uart_cntrl_v1_00_a.UARTController;
use uart_cntrl_v1_00_a.BaudRateGenerator;
use uart_cntrl_v1_00_a.UARTReciever;
use uart_cntrl_v1_00_a.UARTTransmitter;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 1;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
rx : in std_logic;
tx : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
-- component UARTController port (
-- clk : in STD_LOGIC;
-- rst : in STD_LOGIC;
-- rx : in STD_LOGIC;
-- w_data : in STD_LOGIC_VECTOR (7 downto 0);
-- w_start : in STD_LOGIC;
-- tx : out STD_LOGIC;
-- w_done : out STD_LOGIC;
-- r_data : out STD_LOGIC_VECTOR (7 downto 0);
-- r_done : out STD_LOGIC
-- );
-- end component;
--USER signal declarations added here, as needed for user logic
signal UART_clk : std_logic;
signal UART_rst : std_logic;
signal UART_wstart : std_logic;
signal UART_wdone : std_logic;
signal UART_rdone : std_logic;
signal indata : std_logic_vector (7 downto 0);
signal outdata : std_logic_vector (7 downto 0);
signal UART_rx : std_logic;
signal UART_tx : std_logic;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(0 to 0);
signal slv_reg_read_sel : std_logic_vector(0 to 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
UARTC: entity work.UARTController port map (UART_clk, UART_rst, UART_rx,
outdata, UART_wstart, UART_tx, UART_wdone, indata, UART_rdone);
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
-- slv_reg_write_sel <= Bus2IP_WrCE(0 downto 0);
-- slv_reg_read_sel <= Bus2IP_RdCE(0 downto 0);
-- slv_write_ack <= Bus2IP_WrCE(0);
-- slv_read_ack <= Bus2IP_RdCE(0);
UART_clk <= Bus2IP_Clk;
UART_rst <= Bus2IP_Resetn;
outdata <= Bus2IP_Data (7 downto 0);
UART_wstart <= Bus2IP_WrCE(0);
UART_rx <= rx;
-- implement slave model software accessible register(s)
-- SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
-- begin
--
--
-- if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
-- if Bus2IP_Resetn = '0' then
-- slv_reg0 <= (others => '0');
-- else
-- case slv_reg_write_sel is
-- when "1" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when others => null;
-- end case;
-- end if;
-- end if;
--
-- end process SLAVE_REG_WRITE_PROC;
--
-- -- implement slave model software accessible register(s) read mux
-- SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is
-- begin
--
-- case slv_reg_read_sel is
-- when "1" => slv_ip2bus_data <= slv_reg0;
-- when others => slv_ip2bus_data <= (others => '0');
-- end case;
--
-- end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
--IP2Bus_Data(7 downto 0) <= indata;
IP2Bus_Data(7 downto 0) <= indata when UART_rdone = '1' else (others => '0');
IP2Bus_WrAck <= UART_wdone;
IP2Bus_RdAck <= UART_rdone;
tx <= UART_tx;
Bus2IP_RdCE(0) <= '0' when UART_rdone = '1' else '1';
-- IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
-- (others => '0');
--
-- IP2Bus_WrAck <= slv_write_ack;
-- IP2Bus_RdAck <= slv_read_ack;
-- IP2Bus_Error <= '0';
end IMP;
| mit | f3b61a95fed1991d933949ab02083b6b | 0.488915 | 4.053775 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/RGMII_MAC/rgmii_mdio.vhd | 1 | 8,490 | -------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : rgmii_mdio.vhd
-- Author : liyi <[email protected]>
-- Company : OE@HUST
-- Created : 2012-12-02
-- Last update: 2012-12-02
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-12-02 1.0 liyi Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
-------------------------------------------------------------------------------
ENTITY rgmii_mdio IS
PORT (
iWbClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
---------------------------------------------------------------------------
-- signals from register file
---------------------------------------------------------------------------
iPHYAddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
iRegAddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
iNoPre : IN STD_LOGIC;
iData2PHY : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
iClkDiv : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
iRdOp : IN STD_LOGIC;
iWrOp : IN STD_LOGIC;
---------------------------------------------------------------------------
-- signals to register file
---------------------------------------------------------------------------
oDataFromPHY : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- data from PHY registers
oDataFromPHYValid : OUT STD_LOGIC; -- only valid for 1 clock cycle
oClrRdOp : OUT STD_LOGIC; -- only valid for 1 clock cycle
oClrWrOp : OUT STD_LOGIC; -- only valid for 1 clock cycle
oMDIOBusy : OUT STD_LOGIC; -- manegement is busy
---------------------------------------------------------------------------
-- Management interface
---------------------------------------------------------------------------
iMDI : IN STD_LOGIC;
oMDHz : OUT STD_LOGIC; -- mdio is in HighZ state
oMDC : OUT STD_LOGIC
);
END ENTITY rgmii_mdio;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF rgmii_mdio IS
SIGNAL rdPend, wrPend : STD_LOGIC;
SIGNAL endOp : STD_LOGIC;
SIGNAL busy : STD_LOGIC;
SIGNAL sendEn : BOOLEAN; -- Data is output on sendEn. Delay it slightly from the
--clock to ensure setup and hold timing is met
SIGNAL receiveEn : BOOLEAN; -- Sample read data just before rising edge of MDC
BEGIN -- ARCHITECTURE rtl
-----------------------------------------------------------------------------
-- receive command from wishbone
-----------------------------------------------------------------------------
oMDIOBusy <= busy;
busy <= wrPend OR rdPend;
PROCESS (iWbClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
rdPend <= '0';
wrPend <= '0';
oClrWrOp <= '0';
oClrRdOp <= '0';
ELSIF rising_edge(iWbClk) THEN
oClrWrOp <= '0';
oClrRdOp <= '0';
IF busy = '0' THEN
IF iRdOp = '1' THEN
rdPend <= '1';
oClrRdOp <= '1';
ELSIF iWrOp = '1' THEN
wrPend <= '1';
oClrWrOp <= '1';
END IF;
ELSIF endOp = '1' THEN
rdPend <= '0';
wrPend <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- MDC generation
-----------------------------------------------------------------------------
mdcGen : BLOCK IS
SIGNAL mdc : STD_LOGIC;
SIGNAL mdcClkDiv : INTEGER RANGE 0 TO 127;
SIGNAL clkDivTmp : INTEGER RANGE 0 TO 126;
BEGIN -- BLOCK mdc
oMDC <= mdc;
clkDivTmp <= 1 WHEN iClkDiv < 4 ELSE (conv_integer(iClkDiv(7 DOWNTO 1))-1);
sendEn <= mdc = '1' AND mdcClkDiv = 0; -- falling edge send
receiveEn <= mdc = '0' AND mdcClkDiv = 0; -- rising edge receive
PROCESS (iWbClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
mdc <= '0';
mdcClkDiv <= 0;
ELSIF rising_edge(iWbClk) THEN
IF mdcClkDiv = 0 THEN
mdcClkDiv <= clkDivTmp;
mdc <= NOT mdc;
ELSE
mdcClkDiv <= mdcClkDiv - 1;
END IF;
END IF;
END PROCESS;
END BLOCK mdcGen;
operation : BLOCK IS
TYPE state_t IS (PREAMBLE, IDLE, CTRL, WRITE, READ);
SIGNAL state : state_t;
SIGNAL bitCnt : INTEGER RANGE 0 TO 31;
SIGNAL shiftReg : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN -- BLOCK operation
PROCESS (iWbClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
oMDHz <= '1';
state <= PREAMBLE;
endOp <= '0';
bitCnt <= 0;
shiftReg <= (OTHERS => '0');
oDataFromPHYValid <= '0';
oDataFromPHY <= (OTHERS => '0');
ELSIF rising_edge(iWbClk) THEN
endOp <= '0';
oDataFromPHYValid <= '0';
CASE state IS
WHEN PREAMBLE =>
IF sendEn THEN
bitCnt <= bitCnt + 1;
oMDHz <= '1';
IF bitCnt = 30 THEN
state <= IDLE;
END IF;
END IF;
WHEN IDLE =>
IF sendEn THEN
IF busy = '1' THEN -- start transaction
oMDHz <= '0'; -- firstbit of start word
state <= CTRL;
bitCnt <= 0;
shiftReg <= iData2PHY;
END IF;
END IF;
WHEN CTRL =>
IF sendEn THEN
bitCnt <= bitCnt + 1;
CASE bitCnt IS
WHEN 0 => oMDHz <= '1'; -- second bit of start word
-- OPCODE. 1 then 0 for read, 0 then 1 for write
WHEN 1 => oMDHz <= rdPend;
WHEN 2 => oMDHz <= NOT rdPend;
-- PHY address
WHEN 3 => oMDHz <= iPHYAddr(4);
WHEN 4 => oMDHz <= iPHYAddr(3);
WHEN 5 => oMDHz <= iPHYAddr(2);
WHEN 6 => oMDHz <= iPHYAddr(1);
WHEN 7 => oMDHz <= iPHYAddr(0);
-- Register address
WHEN 8 => oMDHz <= iRegAddr(4);
WHEN 9 => oMDHz <= iRegAddr(3);
WHEN 10 => oMDHz <= iRegAddr(2);
WHEN 11 => oMDHz <= iRegAddr(1);
WHEN 12 => oMDHz <= iRegAddr(0);
-- TA
WHEN 13 => oMDHz <= '1';
WHEN 14 =>
IF rdPend = '0' THEN
state <= WRITE;
oMDHz <= '0';
bitCnt <= 0;
END IF;
WHEN 15 =>
state <= READ;
bitCnt <= 0;
WHEN OTHERS => NULL;
END CASE;
END IF;
WHEN WRITE =>
IF sendEn THEN
oMDHz <= shiftReg(15);
shiftReg <= shiftReg(14 DOWNTO 0) & '0';
bitCnt <= bitCnt + 1;
IF bitCnt = 15 THEN
endOp <= '1';
bitCnt <= 0;
IF iNoPre = '1' THEN
state <= IDLE;
ELSE
state <= PREAMBLE;
END IF;
END IF;
END IF;
WHEN READ =>
IF receiveEn THEN
bitCnt <= bitCnt + 1;
shiftReg <= shiftReg(14 DOWNTO 0) & iMDI;
IF bitCnt = 15 THEN
bitCnt <= 0;
endOp <= '1';
oDataFromPHY <= shiftReg(14 DOWNTO 0) & iMDI;
oDataFromPHYValid <= '1';
IF iNoPre = '1' THEN
state <= IDLE;
ELSE
state <= PREAMBLE;
END IF;
END IF;
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
END BLOCK operation;
END ARCHITECTURE rtl;
| gpl-3.0 | f26f94b5403a2a47b2a83688e5c70ae6 | 0.388457 | 4.634279 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/phyActGen-rtl-ea.vhd | 3 | 5,164 | -------------------------------------------------------------------------------
--! @file phyActGen-rtl-ea.vhd
--
--! @brief Phy activity generator
--
--! @details The phy activity generator generates a free-running clock-synchronous
--! packet activity signal. This signal can be used to drive an LED.
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity phyActGen is
generic (
--! Generated activity frequency of oActivity [Hz]
gActivityFreq : natural := 6;
--! Clock frequency of iClk [Hz]
gClkFreq : natural := 50e6
);
port (
--! Reset
iRst : in std_logic;
--! Clock
iClk : in std_logic;
--! MAC Tx enable signal
iTxEnable : in std_logic;
--! MAC Rx data valid signal
iRxValid : in std_logic;
--! Generated activity signal
oActivity : out std_logic
);
end phyActGen;
architecture rtl of phyActGen is
--! Obtain maximum counter value to achieve activity frequency
constant cCntMaxValue : natural := gClkFreq / gActivityFreq;
--! Obtain counter width
constant cCntWidth : natural := logDualis(cCntMaxValue);
--! The counter
signal counter : std_logic_vector(cCntWidth-1 downto 0);
--! Constant for counter value zero
constant cCntIsZero : std_logic_vector(counter'range) := (others => cInactivated);
--! Terminal counter
signal counterTc : std_logic;
--! Trigger activity in next cycle due to packet activity
signal triggerActivity : std_logic;
--! Enable activity
signal enableActivity : std_logic;
begin
oActivity <= counter(counter'high) when enableActivity = cActivated else
cInactivated;
ledCntr : process(iRst, iClk)
begin
if iRst = cActivated then
triggerActivity <= cInactivated;
enableActivity <= cInactivated;
elsif rising_edge(iClk) then
--monoflop, of course no default value!
if triggerActivity = cActivated and counterTc = cActivated then
--counter overflow and activity within last cycle
enableActivity <= cActivated;
elsif counterTc = cActivated then
--counter overflow but no activity
enableActivity <= cInactivated;
end if;
--monoflop, of course no default value!
if counterTc = cActivated then
--count cycle over, reset trigger
triggerActivity <= cInactivated;
elsif iTxEnable = cActivated or iRxValid = cActivated then
--activity within cycle
triggerActivity <= cActivated;
end if;
end if;
end process;
theFreeRunCnt : process(iClk, iRst)
begin
if iRst = cActivated then
counter <= (others => cInactivated);
elsif iClk = cActivated and iClk'event then
counter <= std_logic_vector(unsigned(counter) - 1);
end if;
end process;
counterTc <= cActivated when counter = cCntIsZero else
cInactivated;
end rtl;
| gpl-2.0 | c70f0f555a9b0a4224147509ad091c84 | 0.618125 | 4.970164 | false | false | false | false |
DreamIP/GPStudio | support/process/harris/hdl/harris_process.vhd | 1 | 20,898 | -------------------------------------------------------------------------------
-- Copyright Institut Pascal Equipe Dream (19-10-2016)
-- Francois Berry, El Mehdi Abdali, Maxime Pelcat
-- This software is a computer program whose purpose is to manage dynamic
-- partial reconfiguration.
-- This software is governed by the CeCILL-C license under French law and
-- abiding by the rules of distribution of free software. You can use,
-- modify and/ or redistribute the software under the terms of the CeCILL-C
-- license as circulated by CEA, CNRS and INRIA at the following URL
-- "http://www.cecill.info".
-- As a counterpart to the access to the source code and rights to copy,
-- modify and redistribute granted by the license, users are provided only
-- with a limited warranty and the software's author, the holder of the
-- economic rights, and the successive licensors have only limited
-- liability.
-- In this respect, the user's attention is drawn to the risks associated
-- with loading, using, modifying and/or developing or reproducing the
-- software by the user in light of its specific status of free software,
-- that may mean that it is complicated to manipulate, and that also
-- therefore means that it is reserved for developers and experienced
-- professionals having in-depth computer knowledge. Users are therefore
-- encouraged to load and test the software's suitability as regards their
-- requirements in conditions enabling the security of their systems and/or
-- data to be ensured and, more generally, to use and operate it in the
-- same conditions as regards security.
-- The fact that you are presently reading this means that you have had
-- knowledge of the CeCILL-C license and that you accept its terms.
-------------------------------------------------------------------------------
-- Doxygen Comments -----------------------------------------------------------
--! @file harris_process.vhd
--
--! @brief harris key points extractor
--! @author Francois Berry, El Mehdi Abdali, Maxime Pelcat
--! @board SoCKit from Arrow and Terasic
--! @version 1.0
--! @date 09/05/2017
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
library altera_mf;
use altera_mf.altera_mf_components.all;
use work.window_extractor_pkg.all;
entity harris_process is
generic
(
line_width_max : integer;
pix_width : integer
);
port
(
clk_proc : in std_logic;
reset_n : in std_logic;
in_data : in std_logic_vector((pix_width-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_data : out std_logic_vector (pix_width-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0)
);
end harris_process;
architecture arch of harris_process is
constant result_length : integer := 52;
constant filter_result_length : integer := 28;
signal fv_signal,
out_clk_dv : std_logic := '0';
signal pixel_window_computing : generic_pixel_window(0 to 4, 0 to 4)(59 downto 0);
signal pixel_window_filtering : generic_pixel_window(0 to 6, 0 to 6)((result_length-1) downto 0);
signal gradient_window_computing : generic_pixel_window(0 to 2, 0 to 2)((pix_width-1) downto 0);
signal out_clk_fv : std_logic;
signal out_clk_dv_2 : std_logic;
signal harris_threshold : std_logic_vector((result_length-1) downto 0):= x"0000014DC9380";
signal fv_signal_3 : std_logic;
signal dv_signal_3 : std_logic;
shared variable conv_value_x,
conv_value_y : signed(17 downto 0) := to_signed(0,18);
shared variable Ixx,Ixy,Iyy : signed(31 downto 0) := to_signed(0,32);
shared variable Ixx_connection,
Ixy_connection,
Iyy_connection : std_logic_vector(19 downto 0);
shared variable conv_value : integer := 0;
shared variable cast_36_bits : std_logic_vector(35 downto 0);
shared variable Ixx_vec,Iyy_vec : std_logic_vector(31 downto 0);
shared variable filtered_score : std_logic_vector(result_length-1 downto 0);
shared variable comp_s : std_logic := '0';
shared variable mult_a,mult_b,
mult_2_a,mult_2_b,
mult_3_a,mult_3_b : std_logic_vector(31 downto 0);
signal mult_s,mult_2_s,
mult_3_s,comp_a,
comp_a_2,comp_b,
comp_b_2,add_a_1,
add_b_1,add_b_2,
add_s_inter,add_s : std_logic_vector((result_length-1) downto 0);
type keypoints_coord is array (99 downto 0) of std_logic_vector(15 downto 0); -- PARAM TO CHANGE
signal x_keypoint : keypoints_coord;
signal y_keypoint : keypoints_coord;
signal frame_buffer : std_logic_vector(3199 downto 0); -- PARAM TO CHANGE
signal frame_buffer_has_been_filled : std_logic;
signal frame_buffer_has_been_sent : std_logic;
signal frame_buffer_position : unsigned(12 downto 0); -- PARAM TO CHANGE
component generic_window_extractor is
generic
(
line_width_max : integer;
pix_width : integer;
matrix_width : integer
);
port
(
clk : in std_logic;
reset_n : in std_logic;
in_data : in std_logic_vector((pix_width-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_fv : out std_logic;
out_dv : out std_logic;
widthimg_i : in std_logic_vector(15 downto 0);
pixel_window : out generic_pixel_window(0 to matrix_width-1, 0 to matrix_width-1)(pix_width-1 downto 0)
);
end component;
component LPM_MULT
generic
(
LPM_WIDTHA : natural;
LPM_WIDTHB : natural;
LPM_WIDTHS : natural:=1;
LPM_WIDTHP : natural;
LPM_REPRESENTATION : string:="SIGNED";
LPM_PIPELINE : natural:=0;
LPM_TYPE : string;
LPM_HINT : string:="UNUSED"
);
port
(
DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
ACLR : in std_logic :='0';
SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0):=(OTHERS=>'0');
RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0)
);
end component;
component LPM_ADD_SUB
generic
(
LPM_WIDTH : natural:=44;
LPM_DIRECTION : string:="ADD";
LPM_REPRESENTATION : string:="SIGNED";
LPM_PIPELINE : natural:=0;
LPM_TYPE : string:="LPM_ADD_SUB";
LPM_HINT : string:="UNUSED"
);
port
(
DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
ACLR : in std_logic:='0';
CLOCK : in std_logic:='0';
CLKEN : in std_logic:='1';
CIN : in std_logic:='Z';
ADD_SUB : in std_logic:='1';
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
COUT : out std_logic;
OVERFLOW : out std_logic
);
end component;
component LPM_COMPARE
generic
(
LPM_WIDTH : natural:=44;
LPM_REPRESENTATION : string:="SIGNED";
LPM_PIPELINE : natural:=0;
LPM_TYPE : string:="LPM_COMPARE";
LPM_HINT : string:="UNUSED"
);
port
(
DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
ACLR : in std_logic :='0';
AGB : out std_logic;
AGEB : out std_logic;
AEB : out std_logic;
ANEB : out std_logic;
ALB : out std_logic;
ALEB : out std_logic
);
end component;
begin
gradient_window_extractor : generic_window_extractor
generic map
(
line_width_max => line_width_max,
pix_width => 8,
matrix_width => 3
)
port map
(
clk => clk_proc,
reset_n => reset_n,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_fv => fv_signal_3,
out_dv => dv_signal_3,
widthimg_i => widthimg_i,
pixel_window => gradient_window_computing
);
computing_window_extractor : generic_window_extractor
generic map
(
line_width_max => line_width_max,
pix_width => 60,--pix_width,
matrix_width => 5
)
port map
(
clk => clk_proc,
reset_n => reset_n,
in_data => Ixx_connection & Ixy_connection & Iyy_connection,
in_fv => fv_signal_3,--in_fv,
in_dv => dv_signal_3,--in_dv,
out_fv => fv_signal,
out_dv => out_clk_dv,
widthimg_i => widthimg_i,
pixel_window => pixel_window_computing
);
filtering_window_extractor : generic_window_extractor
generic map
(
line_width_max => line_width_max,
pix_width => result_length,
matrix_width => 7
)
port map
(
clk => clk_proc,
reset_n => reset_n,
in_data => filtered_score,
in_fv => in_fv,
in_dv => out_clk_dv,
out_fv => out_clk_fv,
out_dv => out_clk_dv_2,
widthimg_i => widthimg_i,
pixel_window => pixel_window_filtering
);
mult_inst:LPM_MULT
generic map
(
LPM_WIDTHA => result_length/2,
LPM_WIDTHB => result_length/2,
LPM_WIDTHS => 1,
LPM_WIDTHP => result_length,
LPM_REPRESENTATION => "SIGNED",
LPM_PIPELINE => 0,
LPM_TYPE => "LPM_MULT",
LPM_HINT => "UNUSED"
)
port map
(
DATAA => mult_a((result_length/2)-1 downto 0),
DATAB => mult_b((result_length/2)-1 downto 0),
ACLR => '0',
RESULT => mult_s(result_length-1 downto 0)
);
mult_inst_2:LPM_MULT
generic map
(
LPM_WIDTHA => result_length/2,
LPM_WIDTHB => result_length/2,
LPM_WIDTHS => 1,
LPM_WIDTHP => result_length,
LPM_REPRESENTATION => "SIGNED",
LPM_PIPELINE => 0,
LPM_TYPE => "LPM_MULT",
LPM_HINT => "UNUSED"
)
port map
(
DATAA => mult_2_a((result_length/2)-1 downto 0),
DATAB => mult_2_b((result_length/2)-1 downto 0),
ACLR => '0',
RESULT => mult_2_s(result_length-1 downto 0)
);
mult_inst_3:LPM_MULT
generic map
(
LPM_WIDTHA => result_length/2,
LPM_WIDTHB => result_length/2,
LPM_WIDTHS => 1,
LPM_WIDTHP => result_length,
LPM_REPRESENTATION => "SIGNED",
LPM_PIPELINE => 0,
LPM_TYPE => "LPM_MULT",
LPM_HINT => "UNUSED"
)
port map
(
DATAA => mult_3_a((result_length/2)-1 downto 0),
DATAB => mult_3_b((result_length/2)-1 downto 0),
ACLR => '0',
RESULT => mult_3_s(result_length-1 downto 0)
);
comp_inst_1: LPM_COMPARE
generic map
(
LPM_WIDTH => result_length,
LPM_REPRESENTATION => "SIGNED",
LPM_PIPELINE => 0,
LPM_TYPE => "LPM_COMPARE",
LPM_HINT => "UNUSED"
)
port map
(
DATAA => add_s,
DATAB => harris_threshold,
ACLR => '0',
AGB => comp_s
);
lpm_add_sub_inst_1 : LPM_ADD_SUB
generic map
(
LPM_WIDTH => result_length,
LPM_DIRECTION => "DEFAULT",
LPM_REPRESENTATION => "SIGNED",
LPM_PIPELINE => 0,
LPM_TYPE => "LPM_ADD_SUB",
LPM_HINT => "UNUSED"
)
port map
(
DATAA => mult_s,
DATAB => mult_3_s,
ACLR => '0',
CIN => '0',
ADD_SUB => '0',
RESULT => add_s_inter
);
lpm_add_sub_inst_2 : LPM_ADD_SUB
generic map
(
LPM_WIDTH => result_length,
LPM_DIRECTION => "DEFAULT",
LPM_REPRESENTATION => "SIGNED",
LPM_PIPELINE => 0,
LPM_TYPE => "LPM_ADD_SUB",
LPM_HINT => "UNUSED"
)
port map
(
DATAA => add_s_inter,
DATAB => mult_2_s,
ACLR => '0',
CIN => '0',
ADD_SUB => '0',
RESULT => add_s
);
process (clk_proc, reset_n)
variable x_pos,y_pos : unsigned(15 downto 0);
variable zero_number : integer := 0;
variable max_i : integer := 0;
variable max_j : integer := 0;
variable temp_max : std_logic_vector(filter_result_length-1 downto 0);
variable conv_x_std_vector : std_logic_vector(17 downto 0);
variable conv_y_std_vector : std_logic_vector(17 downto 0);
variable keypoint_index : integer :=0;
variable c : integer :=0;
begin
if(reset_n='0') then
x_pos := to_unsigned(0, 16);
y_pos := to_unsigned(0, 16);
keypoint_index := 0;
x_keypoint <= ((others =>(others =>'0')));
y_keypoint <= ((others =>(others =>'0')));
c :=0;
--Cleaning frame buffer
frame_buffer <= (others=>'0');
--Cleaning signals used to fill buffer
frame_buffer_has_been_filled <= '0';
frame_buffer_has_been_sent <= '0';
out_fv <= '0';
out_dv <= '0';
out_data <= (others=>'0');
elsif(rising_edge(clk_proc)) then
if(in_dv='1') then
--/* compute positions */--
if (x_pos = (unsigned(widthimg_i) - 1)) then
x_pos := to_unsigned(0, 16);
y_pos := y_pos + 1;
else
x_pos := x_pos + 1;
end if;
conv_value := to_integer(unsigned(gradient_window_computing(1,1)));
Ixx := to_signed(+0,32);
Ixy := to_signed(+0,32);
Iyy := to_signed(+0,32);
--/* computing the gradient over x and y */--
conv_value_x := to_signed(0,18);
conv_value_y := to_signed(0,18);
conv_value_x := conv_value_x + signed('0' & gradient_window_computing(0,0)) - signed('0' & gradient_window_computing(0,2))
+ signed('0' & gradient_window_computing(1,0)) - signed('0' & gradient_window_computing(1,2))
+ signed('0' & gradient_window_computing(2,0)) - signed('0' & gradient_window_computing(2,2));
conv_value_y := conv_value_y + signed('0' & gradient_window_computing(0,0)) - signed('0' & gradient_window_computing(2,0))
+ signed('0' & gradient_window_computing(0,1)) - signed('0' & gradient_window_computing(2,1))
+ signed('0' & gradient_window_computing(0,2)) - signed('0' & gradient_window_computing(2,2));
cast_36_bits := std_logic_vector(conv_value_x*conv_value_x);
Ixx_connection := cast_36_bits(19 downto 0);
cast_36_bits := std_logic_vector(conv_value_x*conv_value_y);
Ixy_connection := cast_36_bits(19 downto 0);
cast_36_bits := std_logic_vector(conv_value_y*conv_value_y);
Iyy_connection := cast_36_bits(19 downto 0);
--/* computing the harris score */--
for i in 0 to 4 loop
for j in 0 to 4 loop
Ixx := Ixx + signed(pixel_window_computing(i,j)(59 downto 40));
Ixy := Ixy + signed(pixel_window_computing(i,j)(39 downto 20));
Iyy := Iyy + signed(pixel_window_computing(i,j)(19 downto 0));
end loop;
end loop;
mult_a := std_logic_vector(Ixx);
mult_b := std_logic_vector(Iyy);
Ixx_vec := std_logic_vector(Ixx+Iyy);
Iyy_vec := Ixx_vec(31) & Ixx_vec(31) & Ixx_vec(31) & Ixx_vec(31) & Ixx_vec(31 downto 4);
mult_2_a := Ixx_vec;
mult_2_b := Iyy_vec;
Iyy_vec := std_logic_vector(Ixy);
mult_3_a := Iyy_vec;
mult_3_b := Iyy_vec;
if(comp_s='1') then
filtered_score := add_s;
else
filtered_score := (others=>'0');
end if;
--/* filtering part */--
zero_number := 0;
max_i := 0;
max_j := 0;
temp_max := (others => '0');
for i in 0 to 6 loop
for j in 0 to 6 loop
if (signed(pixel_window_filtering(i,j)(result_length-1 downto result_length-filter_result_length))=0) then
zero_number := zero_number + 1;
else
if signed(pixel_window_filtering(i,j)(result_length-1 downto result_length-filter_result_length)) > signed(temp_max) then
temp_max := pixel_window_filtering(i,j)(result_length-1 downto result_length-filter_result_length);
max_i := i;
max_j := j;
end if;
end if;
end loop;
end loop;
if (max_i=3) and (max_j=3) and (zero_number < 25) then
-- conv_value := 0;
x_keypoint(keypoint_index) <= std_logic_vector(x_pos-to_unsigned(7,16));
y_keypoint(keypoint_index) <= std_logic_vector(y_pos-to_unsigned(7,16));
keypoint_index := keypoint_index+1;
end if;
end if;
out_fv <= '0';
out_dv <= '0';
out_data <= (others=>'0');
if(in_fv ='0')then
x_pos := to_unsigned(0, 16);
y_pos := to_unsigned(0, 16);
keypoint_index := 0;
if(frame_buffer_has_been_filled = '0')then
--We send frame coordinates only if there is something to send
if(frame_buffer_has_been_sent = '0')then
frame_buffer <= (others => '0');
c:=0;
for l in 0 to 99 loop
frame_buffer(c+15 downto c) <= x_keypoint(l);
frame_buffer(c+31 downto c+16) <= y_keypoint(l);
c := c+32;
end loop;
-- Get buffer ready to send
frame_buffer_has_been_filled <= '1';
frame_buffer_position <= (others=>'0');
end if;
else
--send coord
out_fv <= '1';
out_dv <= '1';
out_data <= frame_buffer(to_integer(frame_buffer_position)+7 downto to_integer(frame_buffer_position));
-- PARAM TO CHANGE
if(frame_buffer_position >= 3201)then -- Value = 32*number_of_points + 1
frame_buffer_has_been_filled <= '0';
frame_buffer_has_been_sent <= '1';
x_pos := to_unsigned(0, 16);
y_pos := to_unsigned(0, 16);
keypoint_index := 0;
c:=0;
x_keypoint <= ((others =>(others =>'0')));
y_keypoint <= ((others =>(others =>'0')));
else
frame_buffer_position <= frame_buffer_position + to_unsigned(8,9);
end if;
end if;
else
out_fv <= '0';
out_dv <= '0';
out_data <= (others=>'0');
frame_buffer_has_been_sent <= '0';
end if;
else
end if;
end process;
end arch;
| gpl-3.0 | 83f4f811973c2db3ad0a5dd6d643e393 | 0.490095 | 3.545038 | false | false | false | false |
ou-cse-378/vhdl-tetris | stack32x16.vhd | 1 | 2,427 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: stack32x16.vhd
-- // Date: 12/9/2004
-- // Description: basic implementation of a stack
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity stack32x16 is
port (
d : in STD_LOGIC_VECTOR(15 downto 0);
clk : in STD_LOGIC;
clr : in STD_LOGIC;
push : in STD_LOGIC;
pop : in STD_LOGIC;
full : out STD_LOGIC;
empty : out STD_LOGIC;
q : out STD_LOGIC_VECTOR(15 downto 0)
);
end stack32x16;
architecture Behavioral of stack32x16 is
component dpram32x16
port (
A : IN std_logic_VECTOR(4 downto 0);
CLK : IN std_logic;
D : IN std_logic_VECTOR(15 downto 0);
WE : IN std_logic;
DPRA : IN std_logic_VECTOR(4 downto 0);
DPO : OUT std_logic_VECTOR(15 downto 0);
SPO : OUT std_logic_VECTOR(15 downto 0));
END component;
component stack_ctrl
port (
clr : in STD_LOGIC;
clk : in STD_LOGIC;
push : in STD_LOGIC;
pop : in STD_LOGIC;
we : out STD_LOGIC;
amsel : out STD_LOGIC;
wr_addr : out STD_LOGIC_VECTOR(4 downto 0);
rd_addr : out STD_LOGIC_VECTOR(4 downto 0);
full : out STD_LOGIC;
empty : out STD_LOGIC
);
end component;
component mux2g
generic(width:positive);
Port (
a : in std_logic_vector(4 downto 0);
b : in std_logic_vector(4 downto 0);
sel : in std_logic;
y : out std_logic_vector(4 downto 0)
);
end component;
constant bus_width: positive := 5;
signal WE: std_logic;
signal AMSEL: std_logic;
signal WR_ADDR: std_logic_vector(4 downto 0);
signal WR2_ADDR: std_logic_vector(4 downto 0);
signal RD_ADDR: std_logic_vector(4 downto 0);
signal O: std_logic_VECTOR(15 downto 0);
begin
SWdpram : dpram32x16 port map
( A => WR2_ADDR, DPRA => RD_ADDR, WE => WE, CLK => CLK, D => D, DPO => Q, SPO => O );
SWstackctrl32 : stack_ctrl port map
( clr => CLR, clk => CLK, push => PUSH, pop => POP, we => WE, amsel => AMSEL, wr_addr => WR_ADDR, rd_addr => RD_ADDR, full => full, empty => empty );
SWmux2g: mux2g generic map (width => bus_width) port map
( a => WR_ADDR, b => RD_ADDR, sel => AMSEL, y => WR2_ADDR );
end behavioral; | mit | 66c1a1a3c0f4a5f0c31b98d14c07f17d | 0.570251 | 3.257718 | false | false | false | false |
DreamIP/GPStudio | support/process/fastfilter/hdl/components/fastfilterElement.vhd | 1 | 4,374 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fastfilter_types.all;
entity fastfilterElement is
generic(
KERNEL_SIZE : integer;
PIXEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in pixel_array (0 to KERNEL_SIZE * KERNEL_SIZE - 1);
in_dv : in std_logic;
in_fv : in std_logic;
in_kernel : in pixel_array (0 to KERNEL_SIZE * KERNEL_SIZE - 1);
in_norm : in std_logic_vector(PIXEL_SIZE-1 downto 0);
out_data : out std_logic_vector(PIXEL_SIZE-1 downto 0);
out_dv : out std_logic;
out_fv : out std_logic
);
end fastfilterElement;
architecture bhv of fastfilterElement is
-- Signals
type pixel_array_s1 is array (0 to KERNEL_SIZE * KERNEL_SIZE - 1) of signed (PIXEL_SIZE downto 0);
signal px : pixel_array_s1 ;
signal kernel_s : pixel_array_s1 ;
signal res : signed (PIXEL_SIZE downto 0);
signal all_valid : std_logic;
signal tmp0 : signed(pixel_size downto 0);
signal tmp1 : signed(pixel_size downto 0);
signal tmp2 : signed(pixel_size downto 0);
signal tmp3 : signed(pixel_size downto 0);
signal tmp4 : signed(pixel_size downto 0);
signal tmp5 : signed(pixel_size downto 0);
signal tmp6 : signed(pixel_size downto 0);
signal tmp7 : signed(pixel_size downto 0);
signal tmp8 : signed(pixel_size downto 0);
signal tmp9 : signed(pixel_size downto 0);
signal tmp10 : signed(pixel_size downto 0);
signal tmp11 : signed(pixel_size downto 0);
signal tmp12 : signed(pixel_size downto 0);
signal px1 : signed(pixel_size downto 0);
signal px2 : signed(pixel_size downto 0);
signal px3 : signed(pixel_size downto 0);
begin
-- All valid : Logic and
all_valid <= in_dv and in_fv and enable;
UNSIGNED_CAST : for i in 0 to ( KERNEL_SIZE * KERNEL_SIZE - 1 ) generate
px(i) <= signed('0' & in_data(i));
end generate;
process(clk)
begin
if (all_valid='1') then
tmp0 <= px(0);
tmp1 <= px(1);
tmp2 <= px(2);
tmp3 <= px(3);
tmp4 <= px(4);
tmp5 <= px(5);
tmp6 <= px(6);
tmp7 <= px(7);
tmp8 <= px(8);
tmp9 <= px(9);
tmp10 <= px(10);
tmp11 <= px(11);
tmp12 <= px(12);
px1 <= px(13);
px2 <= px(18);
px3 <= px(17);
if ( (tmp12(0) = '1')
and (tmp0(0) = '0')
and (tmp1(0) = '0')
and (tmp2(0) = '0')
and (tmp3(0) = '0')
and (tmp4(0) = '0')
and (tmp5(0) = '0')
and (tmp6(0) = '0')
and (tmp7(0) = '0')
and (tmp8(0) = '0')
and (tmp9(0) = '0')
and (tmp10(0) = '0')
and (tmp11(0) = '0')) then
if ( px1(0) = '1' and px2(0) = '0' and px3(0) = '0' and px1 < tmp11 ) then
res <= (others => '1');
elsif ( px1(0) = '0' and px2(0) = '1' and px3(0) = '0' and px2 < tmp11 ) then
res <= (others => '1');
elsif ( px1(0) = '0' and px2(0) = '0' and px3(0) = '1' and px3 < tmp11 ) then
res <= (others => '1');
elsif ( px1(0) = '1' and px2(0) = '1' and px3(0) = '0' and px1 < tmp11 and px2 < tmp11) then
res <= (others => '1');
elsif ( px1(0) = '1' and px2(0) = '0' and px3(0) = '1' and px1 < tmp11 and px3 < tmp11 ) then
res <= (others => '1');
elsif ( px1(0) = '0' and px2(0) = '1' and px3(0) = '1' and px2 < tmp11 and px3 < tmp11 ) then
res <= (others => '1');
elsif ( px1(0) = '1' and px2(0) = '1' and px3(0) = '0' and px1 < tmp11 and px2 < tmp11 ) then
res <= (others => '1');
elsif ( px1(0) = '1' and px2(0) = '1' and px3(0) = '1' and px1 < tmp11 and px3 < tmp11 and px2 < tmp11) then
res <= (others => '1');
elsif ( px1(0) = '0' and px2(0) = '0' and px3(0) = '0' ) then
res <= (others => '1');
end if;
else
res <= px(11);
end if;
end if;
out_data <= std_logic_vector (res(PIXEL_SIZE-1 downto 0));
end process;
out_fv <= in_fv;
out_dv <= in_dv;
end bhv;
| gpl-3.0 | e744aece54ca09573c97d7ac4333c7bb | 0.499086 | 2.690037 | false | false | false | false |
DreamIP/GPStudio | support/process/roi/hdl/roi.vhd | 1 | 5,648 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity roi is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end roi;
architecture rtl of roi is
component roi_process
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
status_reg_bypass_bit : in std_logic;
in_size_reg_in_w_reg : in std_logic_vector(11 downto 0);
in_size_reg_in_h_reg : in std_logic_vector(11 downto 0);
out_size_reg_out_w_reg : in std_logic_vector(11 downto 0);
out_size_reg_out_h_reg : in std_logic_vector(11 downto 0);
out_offset_reg_out_x_reg : in std_logic_vector(11 downto 0);
out_offset_reg_out_y_reg : in std_logic_vector(11 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component roi_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
status_reg_bypass_bit : out std_logic;
in_size_reg_in_w_reg : out std_logic_vector(11 downto 0);
in_size_reg_in_h_reg : out std_logic_vector(11 downto 0);
out_size_reg_out_w_reg : out std_logic_vector(11 downto 0);
out_size_reg_out_h_reg : out std_logic_vector(11 downto 0);
out_offset_reg_out_x_reg : out std_logic_vector(11 downto 0);
out_offset_reg_out_y_reg : out std_logic_vector(11 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal status_reg_bypass_bit : std_logic;
signal in_size_reg_in_w_reg : std_logic_vector (11 downto 0);
signal in_size_reg_in_h_reg : std_logic_vector (11 downto 0);
signal out_size_reg_out_w_reg : std_logic_vector (11 downto 0);
signal out_size_reg_out_h_reg : std_logic_vector (11 downto 0);
signal out_offset_reg_out_x_reg : std_logic_vector (11 downto 0);
signal out_offset_reg_out_y_reg : std_logic_vector (11 downto 0);
begin
roi_process_inst : roi_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
status_reg_bypass_bit => status_reg_bypass_bit,
in_size_reg_in_w_reg => in_size_reg_in_w_reg,
in_size_reg_in_h_reg => in_size_reg_in_h_reg,
out_size_reg_out_w_reg => out_size_reg_out_w_reg,
out_size_reg_out_h_reg => out_size_reg_out_h_reg,
out_offset_reg_out_x_reg => out_offset_reg_out_x_reg,
out_offset_reg_out_y_reg => out_offset_reg_out_y_reg,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
roi_slave_inst : roi_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
status_reg_bypass_bit => status_reg_bypass_bit,
in_size_reg_in_w_reg => in_size_reg_in_w_reg,
in_size_reg_in_h_reg => in_size_reg_in_h_reg,
out_size_reg_out_w_reg => out_size_reg_out_w_reg,
out_size_reg_out_h_reg => out_size_reg_out_h_reg,
out_offset_reg_out_x_reg => out_offset_reg_out_x_reg,
out_offset_reg_out_y_reg => out_offset_reg_out_y_reg,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
| gpl-3.0 | 61ecddd01ce9139f9d89100eff25cfb1 | 0.505489 | 2.993111 | false | false | false | false |
ou-cse-378/vhdl-tetris | reg.vhd | 1 | 1,228 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: reg.vhd
-- // Date: 12/9/2004
-- // Description: generic register
-- // Class: CSE 378
-- =================================================================================
-- //
-- // d(n-1 downto 0)
-- // |
-- // ______I______
-- // clr --I| |
-- // | reg |I-- clk
-- // load --I|_____________|
-- // O
-- // |
-- // q(n-1 downto 0)
-- //
library IEEE;
use IEEE.std_logic_1164.all;
entity reg is
generic(width: positive);
port
(
d: in STD_LOGIC_VECTOR (width-1 downto 0);
load: in STD_LOGIC;
clr: in STD_LOGIC;
clk: in STD_LOGIC;
q: out STD_LOGIC_VECTOR (width-1 downto 0)
);
end reg;
architecture reg_arch of reg is
begin
process(clk, clr)
begin
if clr = '1' then
for i in width-1 downto 0 loop
q(i) <= '0';
end loop;
elsif (clk'event and clk = '1') then
if load = '1' then
q <= d;
end if;
end if;
end process;
end reg_arch;
| mit | 9dc74ccd867308d8dff0e87cc4986244 | 0.381922 | 3.611765 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/axiwrapper/src/axiLiteMasterWrapper-rtl-ea.vhd | 3 | 19,308 | -------------------------------------------------------------------------------
--! @file axiLiteMasterWrapper-rtl-ea.vhd
--
--! @brief AXI lite master wrapper on avalon master interface signals
--
--! @details This will convert avalon master interface signals to AXI master
--! interface signals.
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014, B&R Industrial Automation GmbH
-- Copyright (c) 2014, Kalycito Infotech Private Limited.
--- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--! Use standard ieee library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Use libcommon library
library libcommon;
--! Use Global Library
use libcommon.global.all;
entity axiLiteMasterWrapper is
generic (
--! Address width for AXI bus interface
gAddrWidth : integer := 32;
--! Data width for AXI bus interface
gDataWidth : integer := 32
);
port (
--! Global Clock for AXI
iAclk : in std_logic;
--! Global Reset for AXI
inAReset : in std_logic;
--! Address for Write Address Channel
oAwaddr : out std_logic_vector(gAddrWidth-1 downto 0);
--! Protection for Write Address Channel
oAwprot : out std_logic_vector(2 downto 0);
--! AddressValid for Write Address Channel
oAwvalid : out std_logic;
--! AddressReady for Write Address Channel
iAwready : in std_logic;
--! WriteData for Write Data Channel
oWdata : out std_logic_vector(gDataWidth-1 downto 0);
--! WriteStrobe for Write Data Channel
oWstrb : out std_logic_vector(gDataWidth/8-1 downto 0);
--! WriteValid for Write Data Channel
oWvalid : out std_logic;
--! WriteReady for Write Data Channel
iWready : in std_logic;
--! WriteLast for Write Data Channel to indicate last write operations
oWlast : out std_logic;
--! WriteResponse for Write Response Channel
iBresp : in std_logic_vector(1 downto 0); --unused input
--! ResponseValid for Write Response Channel
iBvalid : in std_logic;
--! ResponaseReady for Write Response Channel
oBready : out std_logic;
--! ReadAddress for Read Address Channel
oAraddr : out std_logic_vector(gAddrWidth-1 downto 0);
--! ReadAddressProtection for Read Address Channel
oArprot : out std_logic_vector(2 downto 0);
--! ReadAddressValid for Read Address Channel
oArvalid : out std_logic;
--! ReadAddressReady for Read Address Channel
iArready : in std_logic;
--! ReadData for Read Data Channel
iRdata : in std_logic_vector(gDataWidth-1 downto 0);
--TODO: Remove unused input pin
--! ReadResponse for Read Data Channel
iRresp : in std_logic_vector(1 downto 0);
--! ReadValid for Read Data Channel
iRvalid : in std_logic;
--! ReadReady for Read Data Channel
oRready : out std_logic;
--! Host Interface IP Clock
iAvalonClk : in std_logic;
--! Host Interface Reset
iAvalonReset : in std_logic;
--! Read signal for Avalon Master Interface
iAvalonRead : in std_logic;
--! Write Signal for Avalon Master interface
iAvalonWrite : in std_logic;
--! Address for Avalon Master Interface
iAvalonAddr : in std_logic_vector(gAddrWidth-1 downto 0);
--! Byte Enable for Avalon Master interface
iAvalonBE : in std_logic_vector(3 downto 0);
--! Wait request for Avalon Master Interface
oAvalonWaitReq : out std_logic;
--! Wait Request for Avalon Master Interface
oAvalonReadValid : out std_logic;
--! Read Data for Avalon Master Interface
oAvalonReadData : out std_logic_vector(gDataWidth-1 downto 0);
--! Write Data for Avaon Master Interface
iAvalonWriteData : in std_logic_vector(gDataWidth-1 downto 0)
);
end axiLiteMasterWrapper;
architecture rtl of axiLiteMasterWrapper is
--! Axi-lite master FSM type
type tFsm is (
sINIT,
sAWVALID,
sWVALID,
sBREADY,
sARVALID,
sRREADY,
sWRITE_DONE,
sREAD_DONE
);
--! synchronized fsm state
signal fsm : tFsm;
--! combinational fsm state
signal fsm_next : tFsm;
--! Avalon Interface sync FSM
type tAvalonFsm is (
sStart,
sWait,
sDone
);
--! synchronized Avalon fsm state
signal avmFsm : tAvalonFsm ;
--! combinational fsm sate for Avalon fsm
signal avmFsm_next : tAvalonFsm ;
--Handle Avalon Master
--! Avalon Address
signal avmAddress : std_logic_vector (31 downto 0);
--! Avalon Address temporary signal
signal avmAddress_next : std_logic_vector (31 downto 0);
--! Avalon Read Signal
signal avmRead : std_logic;
--! Avalon Read Signal temporary signal
signal avmRead_next : std_logic;
--! Avalon Write Signal
signal avmWrite : std_logic;
--! Avalon Write Signal temporary signal
signal avmWrite_next : std_logic;
--! Avalon Write Data
signal avmWdata : std_logic_vector (31 downto 0);
--! Avalon Write Data Signal temporary signal
signal avmWdata_next : std_logic_vector (31 downto 0);
--! Avalon Read Data
signal avmRdata : std_logic_vector (31 downto 0);
--! Avalon Read Data temporary Signal
signal avmRdata_next : std_logic_vector (31 downto 0);
--! Avalon start operation
signal avmStart : std_logic;
--! Avalon start operation temporary signal
signal avmStart_next : std_logic;
--! Avalon Byte Enable
signal avmBE : std_logic_vector (3 downto 0);
--! Avalon Byte Enable Signal temporary signal
signal avmBE_next : std_logic_vector (3 downto 0);
--! Avalon Wait Signal
signal avmWait : std_logic;
-- Handle Avalon Master
--! Complete transfer between AXI and Avalon
signal done_transfer : std_logic;
--! Read Ready for Valid Read operations
signal RReady : std_logic;
--! Write operation complete
signal writeOp_done : std_logic;
--! Read operation complete
signal readOp_done : std_logic;
--! Read Data latch for hold data
signal readData : std_logic_vector(31 downto 0);
begin
--AXI Master Signals
-- Secure write is not enabled for read/write operations
oAwprot <= "000";
oArprot <= "000";
--Master signal for AXI interface
oAwaddr <= avmAddress;
oAraddr <= avmAddress;
oWdata <= avmWdata;
-- Only read or write at a time and Read will always 32bit
oWstrb <= avmBE;
-- Memory operations (AXI4) demands presence of WLAST (active for last data)
oWlast <= cActivated;
oAwvalid <= cActivated when fsm = sINIT and avmWrite = cActivated else
cActivated when fsm = sAWVALID else
cInactivated;
oWvalid <= cActivated when fsm = sINIT and avmWrite = cActivated else
cActivated when fsm = sAWVALID else
cActivated when fsm = sWVALID else
cInactivated;
oBready <= cActivated when fsm = sWRITE_DONE and iBvalid = cActivated else
cActivated when fsm = sBREADY else
cInactivated;
oArvalid <= cActivated when fsm = sINIT and avmRead = cActivated else
cActivated when fsm = sARVALID else
cInactivated;
RReady <= cActivated when fsm = sREAD_DONE and iRvalid = cActivated else
cInactivated;
oRready <= RReady;
-- Flop with Enable pin? Anyway passed through a register on Avalon side to
-- avoid latch issues.
--FIXME: bring into fsm
--! Hold the data while it is valid
REG_RDATA: process(iAclk)
begin
if rising_edge (iAclk) then
if inAReset = cnActivated then
readData <= x"00000000";
elsif(iRvalid = cActivated) then
readData <= iRdata;
end if;
end if;
end process REG_RDATA;
RReady <= cActivated when fsm = sREAD_DONE and iRvalid = cActivated else
cInactivated;
-- Completion of Read/Write Operations
done_transfer <= writeOp_done or readOp_done;
writeOp_done <= cActivated when fsm = sWRITE_DONE else
cInactivated;
readOp_done <= cActivated when fsm = sREAD_DONE else
cInactivated;
-- Master FSM
--TODO: Explain logic if possible with Diagram in doxygen
--! Clock Based Process for tFsm changes
SEQ_LOGIC : process(iAclk)
begin
if rising_edge (iAclk) then
if inAReset = cnActivated then
fsm <= sINIT;
else
fsm <= fsm_next;
end if;
end if;
end process SEQ_LOGIC;
-- Combinational Logics
--TODO: Explain logic if possible with Diagram in doxygen
--! Master FSM for AXI-lite interface
COMB_LOGIC : process (
fsm,
avmRead,
avmWrite,
avmStart,
iAwready,
iWready,
iBvalid,
iArready,
iRvalid
)
begin
-- Default Values for signals
fsm_next <= fsm;
case fsm is
when sINIT =>
-- Read Operations
if avmRead = cActivated then
fsm_next <= sARVALID;
if iArready = cActivated then
if iRvalid = cActivated then
fsm_next <= sREAD_DONE;
else
fsm_next <= sRREADY;
end if;
else
fsm_next <= sARVALID;
end if;
-- Write Operations
elsif avmWrite = cActivated then
fsm_next <= sAWVALID;
if iAwready = cActivated then
if iWready = cActivated then
if iBvalid = cActivated then
fsm_next <= sWRITE_DONE;
else
fsm_next <= sBREADY;
end if;
else
fsm_next <= sWVALID;
end if;
else
fsm_next <= sAWVALID;
end if;
else
fsm_next <= sINIT;
end if;
when sAWVALID =>
if iAwready = cActivated then
if iWready = cActivated then
if iBvalid = cActivated then
fsm_next <= sWRITE_DONE;
else
fsm_next <= sBREADY;
end if;
else
fsm_next <= sWVALID;
end if;
else
fsm_next <= sAWVALID;
end if;
when sWVALID =>
if iWready = cActivated then
if iBvalid = cActivated then
fsm_next <= sWRITE_DONE;
else
fsm_next <= sBREADY;
end if;
else
fsm_next <= sWVALID;
end if;
when sBREADY =>
if iBvalid = cActivated then
fsm_next <= sWRITE_DONE;
else
fsm_next <= sBREADY;
end if;
when sARVALID =>
if iArready = cActivated then
if iRvalid = cActivated then
fsm_next <= sREAD_DONE;
else
fsm_next <= sRREADY;
end if;
else
fsm_next <= sARVALID;
end if;
when sRREADY =>
if iRvalid = cActivated then
fsm_next <= sREAD_DONE;
else
fsm_next <= sRREADY;
end if;
when sWRITE_DONE =>
--Wait for Complete activity at avalon side
if(avmStart = cInactivated) then
fsm_next <= sINIT;
else
fsm_next <= sWRITE_DONE;
end if;
when sREAD_DONE =>
--Wait for Complete activity at avalon side
if(avmStart = cInactivated) then
fsm_next <= sINIT;
else
fsm_next <= sREAD_DONE;
end if;
when others =>
null;
end case;
end process COMB_LOGIC;
-- Avalon Interface signal crossing through FSM Register the inputs from
-- Avalon and Pass to AXI to avoid glitches on Master side due to different
-- clock domains
--! Sync Clock domains between Avalon & AXI through a handshaking system
AVM_SYNC: process (iAvalonClk)
begin
if rising_edge (iAvalonClk) then
if iAvalonReset = cActivated then
avmFsm <= sStart;
avmAddress <= x"00000000";
avmRead <= cInactivated;
avmWrite <= cInactivated;
avmRdata <= x"00000000";
avmWdata <= x"00000000";
avmStart <= cInactivated;
avmBE <= x"0";
else
avmFsm <= avmFsm_next ;
avmAddress <= avmAddress_next;
avmRead <= avmRead_next;
avmWrite <= avmWrite_next;
avmRdata <= avmRdata_next;
avmWdata <= avmWdata_next;
avmStart <= avmStart_next;
avmBE <= avmBE_next;
end if;
end if;
end process AVM_SYNC;
-- Split the design for better timing
--! Combinational logic part for FSM
AVM_COM: process ( iAvalonRead,
iAvalonWrite,
iAvalonWriteData,
iAvalonAddr,
iAvalonBE,
readData,
done_transfer,
avmFsm,
avmRead,
avmWrite,
avmStart,
avmAddress,
avmRdata,
avmWdata,
avmBE
)
begin
--Default/Initialization of temporary registers
avmFsm_next <= avmFsm ;
avmAddress_next <= avmAddress;
avmRead_next <= avmRead;
avmWrite_next <= avmWrite;
avmRdata_next <= avmRdata;
avmWdata_next <= avmWdata;
avmStart_next <= avmStart;
avmBE_next <= avmBE;
case avmFsm is
when sStart =>
avmAddress_next <= iAvalonAddr ;
avmBE_next <= iAvalonBE ;
if iAvalonRead = cActivated then
avmFsm_next <= sWait;
avmStart_next <= cActivated ;
avmRead_next <= cActivated ;
elsif iAvalonWrite = cActivated then
avmFsm_next <= sWait;
avmStart_next <= cActivated ;
avmWrite_next <= cActivated;
avmWdata_next <= iAvalonWriteData;
else
avmFsm_next <= sStart;
avmStart_next <= cInactivated ;
avmRead_next <= cInactivated ;
avmWrite_next <= cInactivated;
avmWdata_next <= x"00000000";
end if;
--Wait until the transfer get completed at AXI
when sWait =>
avmStart_next <= avmStart;
avmRead_next <= avmRead ;
avmWrite_next <= avmWrite;
if(done_transfer = cActivated) then
avmFsm_next <= sDone;
-- Only for Read operations
if(iAvalonRead = cActivated) then
avmRdata_next <= readData;
else
avmRdata_next <= avmRdata;
end if;
else
avmFsm_next <= sWait;
end if;
-- Handshake between two FSM domains
when sDone =>
if (done_transfer = cActivated) then
avmRead_next <= cInactivated ;
avmWrite_next <= cInactivated;
avmStart_next <= cInactivated ;
avmFsm_next <= sStart;
else
avmRead_next <= avmRead ;
avmWrite_next <= avmWrite;
avmStart_next <= avmStart;
avmFsm_next <= sDone;
end if;
end case;
end process AVM_COM;
--Avalon Interface signals
oAvalonReadData <= readData;
oAvalonReadValid <= not avmWait;
oAvalonWaitReq <= avmWait;
avmWait <= cInactivated when avmFsm = sDone else
cActivated ;
end rtl;
| gpl-2.0 | acb7437ff5eeee59bc8e72ab360c89cc | 0.52688 | 5.201509 | false | false | false | false |
DreamIP/GPStudio | support/process/fastfilter/hdl/fastfilter_slave.vhd | 1 | 913 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fastfilter_slave is
port(
clk_proc : in std_logic;
reset_n : in std_logic;
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0);
enable_o : out std_logic
);
end fastfilter_slave;
architecture rtl of fastfilter_slave is
constant ENABLE_REG_ADDR : natural := 0;
signal enable_reg : std_logic;
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
enable_reg <= '0';
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(ENABLE_REG_ADDR, 2)) => enable_reg <= datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
enable_o <= enable_reg;
end rtl;
| gpl-3.0 | 962392fe10d66a85e6af7b45ffdbb5da | 0.642935 | 2.480978 | false | false | false | false |
bpervan/simple-soc | pcores/uart_cntrl_v1_00_a/hdl/vhdl/uart_cntrl.vhd | 1 | 16,691 | ------------------------------------------------------------------------------
-- uart_cntrl.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: uart_cntrl.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Thu Mar 27 15:00:40 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library uart_cntrl_v1_00_a;
use uart_cntrl_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity uart_cntrl is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
RX : in std_logic;
TX : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity uart_cntrl;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of uart_cntrl is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 1;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity uart_cntrl_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
tx => TX,
rx => RX,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
| mit | 4ffa53e50febb0a38a2324f533c35e7c | 0.457492 | 4.169623 | false | false | false | false |
DreamIP/GPStudio | support/process/threshold/hdl/threshold_slave.vhd | 1 | 1,781 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity threshold_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
threshold_reg : out std_logic_vector(31 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end threshold_slave;
architecture rtl of threshold_slave is
-- Registers address
constant THRESHOLD_REG_REG_ADDR : natural := 0;
-- Internal registers
signal threshold_reg_reg : std_logic_vector (31 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
threshold_reg_reg <= x"00000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(THRESHOLD_REG_REG_ADDR, 2))=>
threshold_reg_reg <= datawr_i;
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(THRESHOLD_REG_REG_ADDR, 2))=>
datard_o <= threshold_reg_reg;
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
threshold_reg <= threshold_reg_reg;
end rtl;
| gpl-3.0 | 65b62f04313d9f135edfa80282114dcc | 0.560359 | 3.141093 | false | false | false | false |
ou-cse-378/vhdl-tetris | promscore.vhd | 1 | 1,044 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: promscore.vhd
-- // Date: 12/9/2004
-- // Description: WHYP PROM
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use opcodes.all;
entity Promscore is
port (
addr : in STD_LOGIC_VECTOR (15 downto 0);
M : out STD_LOGIC_VECTOR (15 downto 0)
);
end Promscore;
architecture Promscore_arch of Promscore is
type rom_array is array (NATURAL range <>) of STD_LOGIC_VECTOR (15 downto 0);
constant rom: rom_array := (
JMP, --0
X"0002", --1
DESTROFETCH, --2
CLEARLINES, --3
plus, --5
dup, --6
digstore, --7
JMP, --8
X"0002", --9
X"0000" --A
);
begin
process(addr)
variable j: integer;
begin
j := conv_integer(addr);
M <= rom(j);
end process;
end Promscore_arch;
| mit | 5a24fbea99369d3b288b19220bd3ea50 | 0.499042 | 3.135135 | false | false | false | false |
DreamIP/GPStudio | support/process/draw/hdl/draw_process.vhd | 1 | 10,907 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity draw_process is
generic (
CLK_PROC_FREQ : integer;
IMG_SIZE : integer;
COORD_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
inImg_size_reg_in_w_reg : in std_logic_vector(11 downto 0);
inImg_size_reg_in_h_reg : in std_logic_vector(11 downto 0);
------------------------ Img flow -----------------------
Img_data : in std_logic_vector(IMG_SIZE-1 downto 0);
Img_fv : in std_logic;
Img_dv : in std_logic;
----------------------- coord flow ----------------------
coord_data : out std_logic_vector(COORD_SIZE-1 downto 0);
coord_fv : out std_logic;
coord_dv : out std_logic
);
end draw_process;
architecture rtl of draw_process is
--process data_process vars
signal enabled : std_logic;
type keypoints_coord is array (49 downto 0) of std_logic_vector(15 downto 0);
signal x_keypoint : keypoints_coord;
signal y_keypoint : keypoints_coord;
--Coord over serial line related vars
signal frame_buffer : std_logic_vector(1599 downto 0); -- PARAM TO CHANGE
signal frame_buffer_has_been_filled : std_logic;
signal frame_buffer_has_been_sent : std_logic;
signal frame_buffer_position : unsigned(12 downto 0); -- PARAM TO CHANGE
begin
data_process : process (clk_proc, reset_n)
variable c : integer :=0;
begin
if(reset_n='0') then
--Cleaning frame buffer
frame_buffer <= (others=>'0');
--Cleaning signals used to fill buffer
frame_buffer_has_been_filled <= '0';
frame_buffer_has_been_sent <= '0';
coord_fv <= '0';
coord_dv <= '0';
coord_data <= (others=>'0');
--Cleaning flags
enabled <= '0';
x_keypoint <= ((others =>(others =>'0')));
y_keypoint <= ((others =>(others =>'0')));
elsif(rising_edge(clk_proc)) then
if(Img_dv='1')then
x_keypoint(0) <= std_logic_vector(to_unsigned(10,16)); -- x0
y_keypoint(0) <= std_logic_vector(to_unsigned(10,16)); -- x0
x_keypoint(1) <= std_logic_vector(to_unsigned(12,16)); --
y_keypoint(1) <= std_logic_vector(to_unsigned(12,16)); --
x_keypoint(2) <= std_logic_vector(to_unsigned(14,16)); --
y_keypoint(2) <= std_logic_vector(to_unsigned(14,16)); --
x_keypoint(3) <= std_logic_vector(to_unsigned(16,16)); --
y_keypoint(3) <= std_logic_vector(to_unsigned(16,16)); --
x_keypoint(4) <= std_logic_vector(to_unsigned(18,16)); --
y_keypoint(4) <= std_logic_vector(to_unsigned(18,16)); --
x_keypoint(5) <= std_logic_vector(to_unsigned(20,16)); --
y_keypoint(5) <= std_logic_vector(to_unsigned(20,16)); --
x_keypoint(6) <= std_logic_vector(to_unsigned(22,16)); --
y_keypoint(6) <= std_logic_vector(to_unsigned(22,16)); --
x_keypoint(7) <= std_logic_vector(to_unsigned(24,16)); --
y_keypoint(7) <= std_logic_vector(to_unsigned(24,16)); --
x_keypoint(8) <= std_logic_vector(to_unsigned(26,16)); --
y_keypoint(8) <= std_logic_vector(to_unsigned(26,16)); --
x_keypoint(9) <= std_logic_vector(to_unsigned(28,16)); --
y_keypoint(9) <= std_logic_vector(to_unsigned(28,16)); --
---------------------------------------------------------
x_keypoint(10) <= std_logic_vector(to_unsigned(30,16)); -- x10
y_keypoint(10) <= std_logic_vector(to_unsigned(30,16)); -- x10
x_keypoint(11) <= std_logic_vector(to_unsigned(32,16)); --
y_keypoint(11) <= std_logic_vector(to_unsigned(32,16)); --
x_keypoint(12) <= std_logic_vector(to_unsigned(34,16)); --
y_keypoint(12) <= std_logic_vector(to_unsigned(34,16)); --
x_keypoint(13) <= std_logic_vector(to_unsigned(36,16)); --
y_keypoint(13) <= std_logic_vector(to_unsigned(36,16)); --
x_keypoint(14) <= std_logic_vector(to_unsigned(38,16)); --
y_keypoint(14) <= std_logic_vector(to_unsigned(38,16)); --
x_keypoint(15) <= std_logic_vector(to_unsigned(40,16)); --
y_keypoint(15) <= std_logic_vector(to_unsigned(40,16)); --
x_keypoint(16) <= std_logic_vector(to_unsigned(42,16)); --
y_keypoint(16) <= std_logic_vector(to_unsigned(42,16)); --
x_keypoint(17) <= std_logic_vector(to_unsigned(44,16)); --
y_keypoint(17) <= std_logic_vector(to_unsigned(44,16)); --
x_keypoint(18) <= std_logic_vector(to_unsigned(46,16)); --
y_keypoint(18) <= std_logic_vector(to_unsigned(46,16)); --
x_keypoint(19) <= std_logic_vector(to_unsigned(48,16)); --
y_keypoint(19) <= std_logic_vector(to_unsigned(48,16)); --
---------------------------------------------------------
x_keypoint(20) <= std_logic_vector(to_unsigned(50,16)); -- x20
y_keypoint(20) <= std_logic_vector(to_unsigned(50,16)); -- x20
x_keypoint(21) <= std_logic_vector(to_unsigned(52,16)); --
y_keypoint(21) <= std_logic_vector(to_unsigned(52,16)); --
x_keypoint(22) <= std_logic_vector(to_unsigned(54,16)); --
y_keypoint(22) <= std_logic_vector(to_unsigned(54,16)); --
x_keypoint(23) <= std_logic_vector(to_unsigned(56,16)); --
y_keypoint(23) <= std_logic_vector(to_unsigned(56,16)); --
x_keypoint(24) <= std_logic_vector(to_unsigned(58,16)); --
y_keypoint(24) <= std_logic_vector(to_unsigned(58,16)); --
x_keypoint(25) <= std_logic_vector(to_unsigned(60,16)); --
y_keypoint(25) <= std_logic_vector(to_unsigned(60,16)); --
x_keypoint(26) <= std_logic_vector(to_unsigned(62,16)); --
y_keypoint(26) <= std_logic_vector(to_unsigned(62,16)); --
x_keypoint(27) <= std_logic_vector(to_unsigned(64,16)); --
y_keypoint(27) <= std_logic_vector(to_unsigned(64,16)); --
x_keypoint(28) <= std_logic_vector(to_unsigned(66,16)); --
y_keypoint(28) <= std_logic_vector(to_unsigned(66,16)); --
x_keypoint(29) <= std_logic_vector(to_unsigned(68,16)); --
y_keypoint(29) <= std_logic_vector(to_unsigned(68,16)); --
-- ---------------------------------------------------------
x_keypoint(30) <= std_logic_vector(to_unsigned(70,16)); -- x30
y_keypoint(30) <= std_logic_vector(to_unsigned(70,16)); -- x30
x_keypoint(31) <= std_logic_vector(to_unsigned(72,16)); --
y_keypoint(31) <= std_logic_vector(to_unsigned(72,16)); --
x_keypoint(32) <= std_logic_vector(to_unsigned(74,16)); --
y_keypoint(32) <= std_logic_vector(to_unsigned(74,16)); --
x_keypoint(33) <= std_logic_vector(to_unsigned(76,16)); --
y_keypoint(33) <= std_logic_vector(to_unsigned(76,16)); --
x_keypoint(34) <= std_logic_vector(to_unsigned(78,16)); --
y_keypoint(34) <= std_logic_vector(to_unsigned(78,16)); --
x_keypoint(35) <= std_logic_vector(to_unsigned(80,16)); --
y_keypoint(35) <= std_logic_vector(to_unsigned(80,16)); --
x_keypoint(36) <= std_logic_vector(to_unsigned(82,16)); --
y_keypoint(36) <= std_logic_vector(to_unsigned(82,16)); --
x_keypoint(37) <= std_logic_vector(to_unsigned(84,16)); --
y_keypoint(37) <= std_logic_vector(to_unsigned(84,16)); --
x_keypoint(38) <= std_logic_vector(to_unsigned(86,16)); --
y_keypoint(38) <= std_logic_vector(to_unsigned(86,16)); --
x_keypoint(39) <= std_logic_vector(to_unsigned(88,16)); --
y_keypoint(39) <= std_logic_vector(to_unsigned(88,16)); --
-- ---------------------------------------------------------
x_keypoint(40) <= std_logic_vector(to_unsigned(90,16)); -- x40
y_keypoint(40) <= std_logic_vector(to_unsigned(90,16)); -- x40
x_keypoint(41) <= std_logic_vector(to_unsigned(92,16)); --
y_keypoint(41) <= std_logic_vector(to_unsigned(92,16)); --
x_keypoint(42) <= std_logic_vector(to_unsigned(94,16)); --
y_keypoint(42) <= std_logic_vector(to_unsigned(94,16)); --
x_keypoint(43) <= std_logic_vector(to_unsigned(96,16)); --
y_keypoint(43) <= std_logic_vector(to_unsigned(96,16)); --
x_keypoint(44) <= std_logic_vector(to_unsigned(98,16)); --
y_keypoint(44) <= std_logic_vector(to_unsigned(98,16)); --
x_keypoint(45) <= std_logic_vector(to_unsigned(100,16)); --
y_keypoint(45) <= std_logic_vector(to_unsigned(100,16)); --
x_keypoint(46) <= std_logic_vector(to_unsigned(102,16)); --
y_keypoint(46) <= std_logic_vector(to_unsigned(102,16)); --
x_keypoint(47) <= std_logic_vector(to_unsigned(104,16)); --
y_keypoint(47) <= std_logic_vector(to_unsigned(104,16)); --
x_keypoint(48) <= std_logic_vector(to_unsigned(106,16)); --
y_keypoint(48) <= std_logic_vector(to_unsigned(106,16)); --
x_keypoint(49) <= std_logic_vector(to_unsigned(108,16)); --
y_keypoint(49) <= std_logic_vector(to_unsigned(108,16)); --
-- ---------------------------------------------------------
end if;
coord_fv <= '0';
coord_dv <= '0';
coord_data <= (others=>'0');
if(Img_fv = '0') then
--
if(frame_buffer_has_been_filled = '0')then
--We send frame coordinates only if there is something to send
if(enabled = '1' and frame_buffer_has_been_sent = '0')then
frame_buffer <= (others => '0');
c := 0;
for i in 0 to 49 loop
frame_buffer(c+15 downto c) <= x_keypoint(i);
frame_buffer(c+31 downto c+16) <= y_keypoint(i);
c := c+32;
end loop;
-- Get buffer ready to send
frame_buffer_has_been_filled <= '1';
frame_buffer_position <= (others=>'0');
end if;
else
--send coord
coord_fv <= '1';
coord_dv <= '1';
coord_data <= frame_buffer(to_integer(frame_buffer_position)+7 downto to_integer(frame_buffer_position));
-- PARAM TO CHANGE
if(frame_buffer_position >= 1601)then -- Value = 32*number_of_points + 1
frame_buffer_has_been_filled <= '0';
frame_buffer_has_been_sent <= '1';
c := 0;
else
frame_buffer_position <= frame_buffer_position + to_unsigned(8,9);
end if;
end if;
enabled <= status_reg_enable_bit;
else
coord_fv <= '0';
coord_dv <= '0';
coord_data <= (others=>'0');
frame_buffer_has_been_sent <= '0';
end if;
end if;
end process;
end rtl;
| gpl-3.0 | f1b3f5df4d7c40508dd3571557365ccc | 0.539745 | 3.008828 | false | false | false | false |
DreamIP/GPStudio | support/io/d5m/hdl/d5m.vhd | 1 | 3,012 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity d5m is
generic (
CLK_PROC_FREQ : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
--------------------- external ports --------------------
ccd_pixclk : in std_logic;
ccd_data : in std_logic_vector(11 downto 0);
ccd_xclkin : out std_logic;
ccd_reset : out std_logic;
ccd_trigger : out std_logic;
ccd_lval : in std_logic;
ccd_fval : in std_logic;
i2c_sdata : inout std_logic;
i2c_sclk : out std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end d5m;
architecture rtl of d5m is
--/*D5M controller */--
component d5m_controller
generic
(
pixel_address_width : integer
);
port
(
clk : in std_logic;
reset_n : in std_logic;
ccd_trigger : out std_logic;
ccd_xclkin : out std_logic;
ccd_reset : out std_logic;
ccd_data : in std_logic_vector(11 downto 0);
ccd_fval : in std_logic;
ccd_lval : in std_logic;
ccd_pixclk : in std_logic;
i2c_sclk : out std_logic;
i_exposure_adj : in std_logic;
i2c_sdata : inout std_logic;
pix_address : out std_logic_vector(pixel_address_width-1 downto 0);
oRed,
oGreen,
oBlue,
data : out std_logic_vector(7 downto 0);
dv,
fv : out std_logic
);
end component d5m_controller;
signal status_reg_enable_bit : std_logic;
signal pixel_address : std_logic_vector(31 downto 0) := (others => '0');
begin
d5m_controller_inst : d5m_controller
generic map
(
pixel_address_width => 19
)
port map
(
-- External I/Os
clk => clk_proc,
ccd_xclkin => ccd_xclkin,
ccd_trigger => ccd_trigger,
ccd_reset => ccd_reset,
ccd_data => ccd_data,
ccd_fval => ccd_fval,
ccd_lval => ccd_lval,
ccd_pixclk => ccd_pixclk,
i_exposure_adj => '0',
reset_n => reset_n,
i2c_sclk => i2c_sclk,
i2c_sdata => i2c_sdata,
pix_address => pixel_address(18 downto 0),
-- Output flow
data => out_data,
dv => out_dv,
fv => out_fv
);
end rtl;
| gpl-3.0 | 0db8a6c0f781a083e7d84d95870044ba | 0.47842 | 3.35412 | false | false | false | false |
DreamIP/GPStudio | support/process/detectroi/hdl/detectroi.vhd | 1 | 4,099 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity detectroi is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
COORD_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
----------------------- coord flow ----------------------
coord_data : out std_logic_vector(COORD_SIZE-1 downto 0);
coord_fv : out std_logic;
coord_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end detectroi;
architecture rtl of detectroi is
component detectroi_process
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
COORD_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
in_size_reg_in_w_reg : in std_logic_vector(11 downto 0);
in_size_reg_in_h_reg : in std_logic_vector(11 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
----------------------- coord flow ----------------------
coord_data : out std_logic_vector(COORD_SIZE-1 downto 0);
coord_fv : out std_logic;
coord_dv : out std_logic
);
end component;
component detectroi_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
in_size_reg_in_w_reg : out std_logic_vector(11 downto 0);
in_size_reg_in_h_reg : out std_logic_vector(11 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal in_size_reg_in_w_reg : std_logic_vector (11 downto 0);
signal in_size_reg_in_h_reg : std_logic_vector (11 downto 0);
begin
detectroi_process_inst : detectroi_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
IN_SIZE => IN_SIZE,
COORD_SIZE => COORD_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
in_size_reg_in_w_reg => in_size_reg_in_w_reg,
in_size_reg_in_h_reg => in_size_reg_in_h_reg,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
coord_data => coord_data,
coord_fv => coord_fv,
coord_dv => coord_dv
);
detectroi_slave_inst : detectroi_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
in_size_reg_in_w_reg => in_size_reg_in_w_reg,
in_size_reg_in_h_reg => in_size_reg_in_h_reg,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
| gpl-3.0 | 04c57a52db0ae7b28ea06249efd2f9f1 | 0.479141 | 3.204848 | false | false | false | false |
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