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DreamIP/GPStudio | support/process/AveragingFilter/hdl/AveragingFilter_slave.vhd | 1 | 3,070 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity AveragingFilter_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end AveragingFilter_slave;
architecture rtl of AveragingFilter_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant WIDTHIMG_REG_REG_ADDR : natural := 1;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal widthimg_reg_width_reg : std_logic_vector (15 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
widthimg_reg_width_reg <= "0000000000000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
status_reg_enable_bit_reg <= datawr_i(0);
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
widthimg_reg_width_reg <= datawr_i(15) & datawr_i(14) & datawr_i(13) & datawr_i(12) & datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000000000000000000" & status_reg_enable_bit_reg;
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000" & widthimg_reg_width_reg(15) & widthimg_reg_width_reg(14) & widthimg_reg_width_reg(13) & widthimg_reg_width_reg(12) & widthimg_reg_width_reg(11) & widthimg_reg_width_reg(10) & widthimg_reg_width_reg(9) & widthimg_reg_width_reg(8) & widthimg_reg_width_reg(7) & widthimg_reg_width_reg(6) & widthimg_reg_width_reg(5) & widthimg_reg_width_reg(4) & widthimg_reg_width_reg(3) & widthimg_reg_width_reg(2) & widthimg_reg_width_reg(1) & widthimg_reg_width_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
widthimg_reg_width <= widthimg_reg_width_reg;
end rtl;
| gpl-3.0 | 315aec16f38a477176b806becd26ecff | 0.597068 | 2.885338 | false | false | false | false |
DreamIP/GPStudio | support/io/usb_cypress_CY7C68014A/hdl/usb_cypress_CY7C68014A.vhd | 1 | 10,945 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ComFlow_pkg.all;
-- Top level du driver USB
-- 4 output flows max
-- 2 input flow max
-- TODO
-- PASSER LES Identifiants de FLOW en générique du driver:
-- ca permettrait de specifier les valeurs des identifiants des trames par GPStudio
-- Header trame USB
-- TRAME USB 16 bits : permier mot header: FLOW ID/FLAG (8b/8b)
-- : second mot header : Packet number (16b)
entity usb_cypress_CY7C68014A is
generic (
MASTER_ADDR_WIDTH : integer;
IN0_SIZE : integer := 8;
IN1_SIZE : integer := 8;
IN2_SIZE : integer := 8;
IN3_SIZE : integer := 8;
OUT0_SIZE : integer := 16;
OUT1_SIZE : integer := 16;
IN0_NBWORDS : integer := 32768;
IN1_NBWORDS : integer := 32768;
IN2_NBWORDS : integer := 1280;
IN3_NBWORDS : integer := 1280;
OUT0_NBWORDS : integer := 1024;
OUT1_NBWORDS : integer := 1024;
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
clk_hal : out std_logic;
reset : out std_logic;
------ external ports ------
rst : in std_logic;
ifclk : in std_logic;
flaga : in std_logic;
flagb : in std_logic;
flagc : in std_logic;
flagd : in std_logic;
fd_io : inout std_logic_vector(15 downto 0);
sloe : out std_logic;
slrd : out std_logic;
slwr : out std_logic;
pktend : out std_logic;
addr : out std_logic_vector(1 downto 0);
------ in0 flow ------
in0_data : in std_logic_vector(IN0_SIZE-1 downto 0);
in0_fv : in std_logic;
in0_dv : in std_logic;
------ in1 flow ------
in1_data : in std_logic_vector(IN1_SIZE-1 downto 0);
in1_fv : in std_logic;
in1_dv : in std_logic;
------ in2 flow ------
in2_data : in std_logic_vector(IN2_SIZE-1 downto 0);
in2_fv : in std_logic;
in2_dv : in std_logic;
------ in3 flow ------
in3_data : in std_logic_vector(IN3_SIZE-1 downto 0);
in3_fv : in std_logic;
in3_dv : in std_logic;
------ out0 flow ------
out0_data : out std_logic_vector(OUT0_SIZE-1 downto 0);
out0_fv : out std_logic;
out0_dv : out std_logic;
------ out1 flow ------
out1_data : out std_logic_vector(OUT1_SIZE-1 downto 0);
out1_fv : out std_logic;
out1_dv : out std_logic;
---- ===== Masters =====
------ bus_master ------
master_addr_o : out std_logic_vector(MASTER_ADDR_WIDTH-1 downto 0);
master_wr_o : out std_logic;
master_rd_o : out std_logic;
master_datawr_o : out std_logic_vector(31 downto 0);
master_datard_i : in std_logic_vector(31 downto 0);
---- ===== Slaves =====
------ bus_sl ------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of usb_cypress_CY7C68014A is
constant DATA_HAL_SIZE : INTEGER := 16;
constant CLK_HAL_FREQ : INTEGER := 48000000;
-- SLAVE BUS
signal status_enable : std_logic := '0';
signal flow_in0_enable : std_logic := '0';
signal flow_in1_enable : std_logic := '0';
signal flow_in2_enable : std_logic := '0';
signal flow_in3_enable : std_logic := '0';
-- USBFLOW_IN
signal hal_out_data : std_logic_vector(DATA_HAL_SIZE-1 downto 0) := (others => '0');
signal hal_out_data_wr : std_logic := '0';
signal hal_out_data_full : std_logic := '0';
signal hal_out_data_end : std_logic := '0';
-- USBFLOW OUT
signal hal_in_data : std_logic_vector(DATA_HAL_SIZE-1 downto 0) := (others => '0');
signal hal_in_empty : std_logic := '0';
signal hal_in_rd : std_logic := '0';
signal hal_in_rdy : std_logic := '0';
signal hal_in_size_packet : std_logic_vector(15 downto 0) := (others => '0');
-- FLOW_PARAMS
signal update_port_s : std_logic := '0';
-- clock
signal clk_hal_s : std_logic := '0';
component usb_cypress_CY7C68014A_hal
port (
usb_ifclk : in std_logic;
usb_flaga : in std_logic;
usb_flagb : in std_logic;
usb_flagc : in std_logic;
usb_flagd : in std_logic;
usb_fd_io : inout std_logic_vector(15 downto 0);
usb_sloe : out std_logic;
usb_slrd : out std_logic;
usb_slwr : out std_logic;
usb_pktend : out std_logic;
usb_addr : out std_logic_vector(1 downto 0);
usb_rst : in std_logic;
out_data_o : out std_logic_vector(15 downto 0);
out_data_wr_o : out std_logic;
out_data_full_i : in std_logic;
out_data_end_o : out std_logic;
in_data_i : in std_logic_vector(15 downto 0);
in_data_rd_o : out std_logic;
in_data_empty_i : in std_logic;
in_data_rdy_i : in std_logic
);
end component;
component usb_cypress_CY7C68014A_slave
generic (
CLK_PROC_FREQ : INTEGER
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_enable : out std_logic;
flow_in0_enable : out std_logic;
flow_in1_enable : out std_logic;
flow_in2_enable : out std_logic;
flow_in3_enable : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
begin
reset <= rst;
-- USB HAL, control of USB cypress
usb_hal_inst : usb_cypress_CY7C68014A_hal
port map (
usb_ifclk => ifclk,
usb_flaga => flaga,
usb_flagb => flagb,
usb_flagc => flagc,
usb_flagd => flagd,
usb_fd_io => fd_io,
usb_sloe => sloe,
usb_slrd => slrd,
usb_slwr => slwr,
usb_pktend => pktend,
usb_rst => rst,
usb_addr => addr,
out_data_o => hal_out_data,
out_data_wr_o => hal_out_data_wr,
out_data_full_i => hal_out_data_full,
out_data_end_o => hal_out_data_end,
in_data_i => hal_in_data,
in_data_rd_o => hal_in_rd,
in_data_empty_i => hal_in_empty,
in_data_rdy_i => hal_in_rdy
);
-- slave
usb_slave_inst : component usb_cypress_CY7C68014A_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => rst,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
datawr_i => datawr_i,
rd_i => rd_i,
datard_o => datard_o,
status_enable => status_enable,
flow_in0_enable => flow_in0_enable,
flow_in1_enable => flow_in1_enable,
flow_in2_enable => flow_in2_enable,
flow_in3_enable => flow_in3_enable
);
-- com controler
gp_com_inst : component gp_com
generic map (
IN0_SIZE => IN0_SIZE,
IN1_SIZE => IN1_SIZE,
IN2_SIZE => IN2_SIZE,
IN3_SIZE => IN3_SIZE,
OUT0_SIZE => OUT0_SIZE,
OUT1_SIZE => OUT1_SIZE,
IN0_NBWORDS => IN0_NBWORDS,
IN1_NBWORDS => IN1_NBWORDS,
IN2_NBWORDS => IN2_NBWORDS,
IN3_NBWORDS => IN3_NBWORDS,
OUT0_NBWORDS => OUT0_NBWORDS,
OUT1_NBWORDS => OUT1_NBWORDS,
CLK_PROC_FREQ => CLK_PROC_FREQ,
CLK_HAL_FREQ => CLK_HAL_FREQ,
DATA_HAL_SIZE => DATA_HAL_SIZE,
PACKET_HAL_SIZE => 256,
MASTER_ADDR_WIDTH => MASTER_ADDR_WIDTH
)
port map (
clk_proc => clk_proc,
reset_n => rst,
clk_hal => clk_hal_s,
from_hal_data => hal_out_data,
from_hal_wr => hal_out_data_wr,
from_hal_full => hal_out_data_full,
from_hal_pktend => hal_out_data_end,
to_hal_data => hal_in_data,
to_hal_rd => hal_in_rd,
to_hal_empty => hal_in_empty,
to_hal_rdy => hal_in_rdy,
to_hal_size_packet => hal_in_size_packet,
status_enable => status_enable,
flow_in0_enable => flow_in0_enable,
flow_in1_enable => flow_in1_enable,
flow_in2_enable => flow_in2_enable,
flow_in3_enable => flow_in3_enable,
in0_data => in0_data,
in0_fv => in0_fv,
in0_dv => in0_dv,
in1_data => in1_data,
in1_fv => in1_fv,
in1_dv => in1_dv,
in2_data => in2_data,
in2_fv => in2_fv,
in2_dv => in2_dv,
in3_data => in3_data,
in3_fv => in3_fv,
in3_dv => in3_dv,
out0_data => out0_data,
out0_fv => out0_fv,
out0_dv => out0_dv,
out1_data => out1_data,
out1_fv => out1_fv,
out1_dv => out1_dv,
master_addr_o => master_addr_o,
master_wr_o => master_wr_o,
master_rd_o => master_rd_o,
master_datawr_o => master_datawr_o,
master_datard_i => master_datard_i
);
clk_hal_s <= ifclk;
clk_hal <= clk_hal_s;
end rtl;
| gpl-3.0 | 8d169568205f41e5b2ebde13274c71b3 | 0.455085 | 3.417552 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/sync/testbench/boundary_tb.vhdl | 1 | 2,332 | --
-- Boundary Testbench
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.Simul.all;
use FPGALIB.Sync.all;
entity Boundary_Tb is
end entity Boundary_Tb;
architecture Test of Boundary_Tb is
constant FREQUENCY : positive:=150e6;
signal clk, rst : std_logic;
signal stop : boolean;
-- dut
constant PATTERN : std_logic_vector(3 downto 0):="1111";
type comma_t is array(0 to 23) of std_logic_vector (3 downto 0);
signal comma_in : comma_t:=(
"0000", -- aligned
"0000", -- aligned
"0000", -- aligned
"1000", -- 3
"0111", -- 3
"0000", -- 3
"1100", -- 2
"0011", -- 2
"0000", -- 2
"0000", -- 2
"1110", -- 1
"0001", -- 1
"0000", -- 1
"0000", -- 1
"1111", -- aligned
"0000", -- aligned
"0110", -- aligned
"1001", -- aligned
"0100", -- aligned
"0100", -- aligned
others => "0000"
);
signal index : natural:=0;
signal comma_aux, comma_out : std_logic_vector (3 downto 0);
signal data_out : std_logic_vector (31 downto 0);
begin
do_clk: Clock
generic map(FREQUENCY => FREQUENCY)
port map(clk_o => clk, rst_o => rst, stop_i => stop);
dut: Boundary
port map(
clk_i => clk,
pattern_i => PATTERN,
comma_i => comma_aux,
data_i => x"01234567",
comma_o => comma_out,
data_o => data_out
);
feeder: process
begin
wait until rising_edge(clk) and rst='0';
for i in 0 to 20 loop
comma_aux <= comma_in(i);
wait until rising_edge(clk);
end loop;
wait;
end process feeder;
checker: process
begin
wait until rising_edge(clk) and rst='0';
wait until rising_edge(clk) and comma_out="1111";
assert data_out=x"23456701";
wait until rising_edge(clk) and comma_out="1111";
assert data_out=x"45670123";
wait until rising_edge(clk) and comma_out="1111";
assert data_out=x"67012345";
wait until rising_edge(clk) and comma_out="1111";
assert data_out=x"01234567";
stop <= TRUE;
wait;
end process checker;
end architecture Test;
| bsd-3-clause | 00642ea5e4fed271403765606a35fcb6 | 0.563465 | 3.4858 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/sync/ffchain.vhdl | 1 | 1,200 | --
-- FF Chain
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2015-2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
entity FFchain is
generic(
WIDTH : positive:=8;
DEPTH : positive:=2
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
ena_i : in std_logic;
data_i : in std_logic_vector(WIDTH-1 downto 0);
data_o : out std_logic_vector(WIDTH-1 downto 0)
);
end entity FFchain;
architecture RTL of FFchain is
type ff_array is array (0 to DEPTH-1) of std_logic_vector(WIDTH-1 downto 0);
signal data_r : ff_array :=(others => (others => '0'));
begin
do_chain:
process (clk_i)
begin
if rising_edge(clk_i) then
if rst_i='1' then
data_r <= (others => (others => '0'));
elsif ena_i='1' then
for i in 0 to DEPTH-1 loop
if i=0 then
data_r(0) <= data_i;
else
data_r(i) <= data_r(i-1);
end if;
end loop;
end if;
end if;
end process do_chain;
data_o <= data_r(DEPTH-1);
end architecture RTL;
| bsd-3-clause | 64a32b2180dba9e7701034110221ed39 | 0.533333 | 3.217158 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_Dual_Clock_FIFO.vhd | 1 | 9,129 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
USE ieee.numeric_std.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module is a buffer that can be used the transfer streaming data from *
-- * one clock domain to another. *
-- * *
-- ******************************************************************************
ENTITY Video_System_Dual_Clock_FIFO IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
GENERIC (
DW :INTEGER := 29; -- Frame's data width
EW :INTEGER := 1 -- Frame's empty width
);
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
clk_stream_in :IN STD_LOGIC;
reset_stream_in :IN STD_LOGIC;
clk_stream_out :IN STD_LOGIC;
reset_stream_out :IN STD_LOGIC;
stream_in_data :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_in_startofpacket :IN STD_LOGIC;
stream_in_endofpacket :IN STD_LOGIC;
stream_in_empty :IN STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_in_valid :IN STD_LOGIC;
stream_out_ready :IN STD_LOGIC;
-- Bi-Directional
-- Outputs
stream_in_ready :BUFFER STD_LOGIC;
stream_out_data :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_empty :BUFFER STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_out_valid :BUFFER STD_LOGIC
);
END Video_System_Dual_Clock_FIFO;
ARCHITECTURE Behaviour OF Video_System_Dual_Clock_FIFO IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
SIGNAL fifo_wr_used :STD_LOGIC_VECTOR( 6 DOWNTO 0);
SIGNAL fifo_empty :STD_LOGIC;
SIGNAL q :STD_LOGIC_VECTOR((DW + 2) DOWNTO 0);
-- Internal Registers
-- State Machine Registers
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
COMPONENT dcfifo
GENERIC (
intended_device_family :STRING;
lpm_hint :STRING;
lpm_numwords :INTEGER;
lpm_showahead :STRING;
lpm_type :STRING;
lpm_width :INTEGER;
lpm_widthu :INTEGER;
overflow_checking :STRING;
rdsync_delaypipe :INTEGER;
underflow_checking :STRING;
use_eab :STRING;
wrsync_delaypipe :INTEGER
);
PORT (
-- Inputs
wrclk :IN STD_LOGIC;
wrreq :IN STD_LOGIC;
data :IN STD_LOGIC_VECTOR((DW + 2) DOWNTO 0);
rdclk :IN STD_LOGIC;
rdreq :IN STD_LOGIC;
-- Outputs
wrusedw :BUFFER STD_LOGIC_VECTOR( 6 DOWNTO 0);
rdempty :BUFFER STD_LOGIC;
q :BUFFER STD_LOGIC_VECTOR((DW + 2) DOWNTO 0)
-- synopsys translate_off
-- synopsys translate_on
);
END COMPONENT;
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
-- Output assignments
stream_in_ready <= NOT (AND_REDUCE (fifo_wr_used( 6 DOWNTO 4)));
stream_out_empty <= (OTHERS => '0');
stream_out_valid <= NOT fifo_empty;
stream_out_data <= q((DW + 2) DOWNTO 2);
stream_out_endofpacket <= q(1);
stream_out_startofpacket <= q(0);
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
Data_FIFO : dcfifo
GENERIC MAP (
intended_device_family => "Cyclone II",
lpm_hint => "MAXIMIZE_SPEED=7,",
lpm_numwords => 128,
lpm_showahead => "ON",
lpm_type => "dcfifo",
lpm_width => DW + 3,
lpm_widthu => 7,
overflow_checking => "OFF",
rdsync_delaypipe => 5,
underflow_checking => "OFF",
use_eab => "ON",
wrsync_delaypipe => 5
)
PORT MAP (
-- Inputs
wrclk => clk_stream_in,
wrreq => stream_in_ready AND stream_in_valid,
data => stream_in_data & stream_in_endofpacket & stream_in_startofpacket,
rdclk => clk_stream_out,
rdreq => stream_out_ready AND NOT fifo_empty,
-- Outputs
wrusedw => fifo_wr_used,
rdempty => fifo_empty,
q => q
-- synopsys translate_off
-- synopsys translate_on
);
END Behaviour;
| gpl-2.0 | 6b24c20dc0c79c8d63b9991940bcbb57 | 0.442984 | 4.55994 | false | false | false | false |
DreamIP/GPStudio | support/component/neighExtractor/taps.vhd | 1 | 2,759 | ---------------------------------------------------------------------------------
-- Design Name : neighExtractor
-- File Name : neighExtractor.vhd
-- Function : Extracts a generic neighborhood from serial in_data
-- Coder : Kamel Eddine ABDELOUAHAB
-- Institution : Institut Pascal
---------------------------------------------------------------------------------
-- taps_data(0) taps_data(KERNEL_SIZE-1)
-- ^ ^
-- | |
-- ------- | ------- ------- | ---------------------------
-- | | | | | | | | | |
-- in_data --->| |---|--> | |-- ... -> | |---|-->| BUFFER |---> out_data
-- | | | | | | | SIZE =(TAPS_WIDTH-KERNEL)|
-- | | | | | | | |
-- ------- ------- ------- ---------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cnn_types.all;
entity taps is
generic (
PIXEL_SIZE : integer;
TAPS_WIDTH : integer;
KERNEL_SIZE : integer
);
port (
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE-1 downto 0);
taps_data : out pixel_array (0 to KERNEL_SIZE -1 );
out_data : out std_logic_vector (PIXEL_SIZE-1 downto 0)
);
end taps;
architecture bhv of taps is
signal cell : pixel_array (0 to TAPS_WIDTH-1);
begin
process(clk)
variable i : integer := 0;
begin
if ( reset_n = '0' ) then
cell <= (others =>(others => '0'));
out_data <= (others => '0');
taps_data <= (others =>(others => '0'));
elsif (rising_edge(clk)) then
if (enable='1') then
cell(0) <= in_data;
for i in 1 to (TAPS_WIDTH-1) loop
cell(i) <= cell(i-1);
end loop;
taps_data <= cell(0 to KERNEL_SIZE-1);
out_data <= cell(TAPS_WIDTH-1);
end if;
end if;
end process;
end bhv;
| gpl-3.0 | 883d9a6dd0be4be21625d5e8b4bbcc64 | 0.310982 | 4.500816 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_Pixel_Buffer.vhd | 1 | 8,203 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module chipselects reads and writes to the sram, with 2-cycle *
-- * read latency and one cycle write latency. *
-- * *
-- ******************************************************************************
ENTITY Video_System_Pixel_Buffer IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
address :IN STD_LOGIC_VECTOR(17 DOWNTO 0);
byteenable :IN STD_LOGIC_VECTOR( 1 DOWNTO 0);
read :IN STD_LOGIC;
write :IN STD_LOGIC;
writedata :IN STD_LOGIC_VECTOR(15 DOWNTO 0);
-- Bi-Directional
SRAM_DQ :INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- SRAM Data bus 16 Bits
-- Outputs
readdata :BUFFER STD_LOGIC_VECTOR(15 DOWNTO 0);
readdatavalid :BUFFER STD_LOGIC;
SRAM_ADDR :BUFFER STD_LOGIC_VECTOR(17 DOWNTO 0); -- SRAM Address bus 18 Bits
SRAM_LB_N :BUFFER STD_LOGIC; -- SRAM Low-byte Data Mask
SRAM_UB_N :BUFFER STD_LOGIC; -- SRAM High-byte Data Mask
SRAM_CE_N :BUFFER STD_LOGIC; -- SRAM Chip chipselect
SRAM_OE_N :BUFFER STD_LOGIC; -- SRAM Output chipselect
SRAM_WE_N :BUFFER STD_LOGIC -- SRAM Write chipselect
);
END Video_System_Pixel_Buffer;
ARCHITECTURE Behaviour OF Video_System_Pixel_Buffer IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
-- Internal Registers
SIGNAL is_read :STD_LOGIC;
SIGNAL is_write :STD_LOGIC;
SIGNAL writedata_reg :STD_LOGIC_VECTOR(15 DOWNTO 0);
-- State Machine Registers
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
-- Output Registers
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
readdata <= SRAM_DQ;
readdatavalid <= is_read;
SRAM_ADDR <= address;
SRAM_LB_N <= NOT (byteenable(0) AND (read OR write));
SRAM_UB_N <= NOT (byteenable(1) AND (read OR write));
SRAM_CE_N <= NOT (read OR write);
SRAM_OE_N <= NOT read;
SRAM_WE_N <= NOT write;
END IF;
END PROCESS;
-- Internal Registers
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
is_read <= '0';
ELSE
is_read <= read;
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
is_write <= '0';
ELSE
is_write <= write;
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
writedata_reg <= writedata;
END IF;
END PROCESS;
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
-- Output Assignments
SRAM_DQ <= writedata_reg WHEN (is_write = '1') ELSE (OTHERS => 'Z');
-- Internal Assignments
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
END Behaviour;
| gpl-2.0 | 9d5461ce1e27df250fdda9e55d2776f2 | 0.420944 | 4.989659 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/verif/verif_pkg.vhdl | 1 | 2,135 | --
-- Verif Package
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016-2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
package Verif is
component Blink is
generic (
FREQUENCY : positive:=25e6;
SECONDS : positive:=1
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
blink_o : out std_logic
);
end component Blink;
component LoopCheck is
generic (
DWIDTH : positive:=8
);
port (
-- Producer side
tx_clk_i : in std_logic;
tx_rst_i : in std_logic;
tx_stb_i : in std_logic;
tx_data_i : in std_logic_vector(DWIDTH-1 downto 0);
tx_data_o : out std_logic_vector(DWIDTH-1 downto 0);
-- Consumer side
rx_clk_i : in std_logic;
rx_rst_i : in std_logic;
rx_stb_i : in std_logic;
rx_data_i : in std_logic_vector(DWIDTH-1 downto 0);
rx_errors_o : out std_logic_vector(4 downto 0)
);
end component LoopCheck;
component TransLoop is
generic (
DBYTES : positive:=4; -- Data bytes
TSIZE : positive:=1e4; -- Total size
FSIZE : positive:=2048 -- Frame size
);
port (
-- TX side
tx_clk_i : in std_logic;
tx_rst_i : in std_logic;
tx_data_i : in std_logic_vector(DBYTES*8-1 downto 0);
tx_data_o : out std_logic_vector(DBYTES*8-1 downto 0);
tx_isk_o : out std_logic_vector(DBYTES-1 downto 0);
tx_ready_i : in std_logic;
-- RX side
rx_clk_i : in std_logic;
rx_rst_i : in std_logic;
rx_data_i : in std_logic_vector(DBYTES*8-1 downto 0);
rx_isk_i : in std_logic_vector(DBYTES-1 downto 0);
rx_errors_o : out std_logic_vector(4 downto 0);
rx_finish_o : out std_logic;
rx_cycles_o : out std_logic_vector(31 downto 0)
);
end component TransLoop;
end package Verif;
| bsd-3-clause | 022a481a24790de08c0bc601f0006cd6 | 0.523653 | 3.249619 | false | false | false | false |
DreamIP/GPStudio | support/io/com/hdl/com.vhd | 1 | 6,077 | -- Top level of the com block, contains the flow to com and com to flow mux.
-- Also instantiates the flow to com and com to flow block.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.com_package.all;
entity com is
generic (
FIFO_IN_N : integer := 4;
FIFO_IN_ID : fifo_ID := ("000001","000010","000011",x"000100",others=>"000000");
FIFO_IN_SIZE : fifo_size := (2048,1024,2048,512,others=>0);
ONE_PACKET : integer := 1450;
FIFO_OUT_N : integer := 3;
FIFO_OUT_ID : fifo_ID := ("110000","100001","100010",others=>x"100000");--- the first one is the master ID
FIFO_OUT_SIZE : fifo_size := (512,1024,others=>0)
);
port (
clk_hal : in std_logic;
clk_proc : in std_logic;
reset_n : in std_logic;
--- From flows in to HAL
data_o : out std_logic_vector(7 downto 0);
data_size_o : out std_logic_vector(15 downto 0);
read_data_i : in std_logic;
ready_o : out std_logic;
hal_ready : in std_logic;
--- Flow to master
flow_master : out flow_t;
--- From HAL to flows out
data_i : in std_logic_vector(7 downto 0);
write_i : in std_logic;
--- Flows in and out
flow_in0 : in flow_t;
flow_in1 : in flow_t;
flow_in2 : in flow_t;
flow_in3 : in flow_t;
flow_out0 : out flow_t;
flow_out1 : out flow_t;
--- Parameters from slave
enable_eth : in std_logic;
enable_in0 : in std_logic;
enable_in1 : in std_logic;
enable_in2 : in std_logic;
enable_in3 : in std_logic
);
end com;
architecture RTL of com is
----- Signals for fifos receiving flows (flow_to_com)
signal ready : array_std_logic;
signal enable_i : array_std_logic;
signal read_data : array_std_logic;
signal fifo_in_flow_i : array_flow_t;
signal data : array_bus8;
signal data_size : array_bus16;
signal count_in,count_in_dl : integer range 0 to fifo_in_N-1;
signal HAL_busy_dl : std_logic;
signal wait_for_hal : std_logic;
signal ready_dl,ready_s : std_logic;
signal hal_ready_dl : std_logic;
----- Signals for fifos sending flows (com_to_flow)
signal enable_o : std_logic;
signal fifo_out_flow_o : array_flow_t;
begin
---------------------------------------------------------------------------------------------------------
-------------------------- FLOW_TO_COM_MUX
---------------------------------------------------------------------------------------------------------
----- Checking ready signals from fifos receiving flows
process(clk_hal,reset_n)
begin
if reset_n ='0' then
count_in <= 0;
wait_for_hal <= '0';
elsif clk_hal'event and clk_hal='1' then
ready_dl <= ready(count_in);
if ready(count_in)='0' and ready_dl='1' then
wait_for_hal <= '1';
elsif wait_for_hal='1' and hal_ready='1' then --- Increment count between each packet sent
wait_for_hal <= '0';
count_in <= count_in+1;
elsif wait_for_hal='0' and hal_ready='1' and ready(count_in)='0' and read_data_i='0' then --- Increment when flow not ready
count_in <= count_in+1;
end if;
end if;
end process;
ready_s <= '0' when wait_for_hal='1' else ready(count_in);
ready_o <= ready_s;
data_o <= data(count_in);
data_size_o <= data_size(count_in);
read_data(count_in) <= read_data_i;
----- Instantiating fifo receiving flows
flow_to_com_gen : for i in 0 to FIFO_IN_N-1 generate
flow_to_com_inst : entity work.flow_to_com
generic map (
ID_FIFO => fifo_in_ID(i),
FIFO_DEPTH => fifo_in_size(i),
ONE_PACKET => (ONE_PACKET)
)
port map (
clk_hal => clk_hal,
clk_proc => clk_proc,
reset_n => reset_n,
enable => enable_i(i),
flow_in => fifo_in_flow_i(i),
data_size => data_size(i),
read_data => read_data(i),
ready => ready(i),
data_out => data(i)
);
end generate flow_to_com_gen;
------------à generer
fifo_in_flow_i(0) <= flow_in0;
fifo_in_flow_i(1) <= flow_in1;
fifo_in_flow_i(2) <= flow_in2;
fifo_in_flow_i(3) <= flow_in3;
---------------------------------------------------------------------------------------------------------
-------------------------- COM_TO_FLOW_MUX
---------------------------------------------------------------------------------------------------------
----- Instantiating com_to_flows blocks
com_to_flow_gen : for i in 0 to FIFO_OUT_N-1 generate
com_to_flow_inst : entity work.com_to_flow
generic map (
ID_FIFO => fifo_out_ID(i),
FIFO_DEPTH => fifo_out_size(i))
port map (
clk_hal => clk_hal,
clk_proc => clk_proc,
reset_n => reset_n,
enable => enable_o,
flow_out => fifo_out_flow_o(i),
write_data => write_i,
data_in => data_i
);
end generate com_to_flow_gen;
flow_master <= fifo_out_flow_o(0);
flow_out0 <= fifo_out_flow_o(1);
flow_out1 <= fifo_out_flow_o(2);
----- Enable flows in and out
enable_i(0) <= enable_eth and enable_in0;
enable_i(1) <= enable_eth and enable_in1;
enable_i(2) <= enable_eth and enable_in2;
enable_i(3) <= enable_eth and enable_in3;
enable_o <= '1';
end RTL;
| gpl-3.0 | 87349a596bc79fbd36e8e3d2ff9d1bf4 | 0.462475 | 3.565728 | false | false | false | false |
DreamIP/GPStudio | support/toolchain/caph/hdl/caph_lib/fifo_fb.vhd | 1 | 6,878 | -----------------------------------------------------------------------------------------
-- --
-- This file is part of the CAPH Compiler distribution --
-- http://caph.univ-bpclermont.fr --
-- --
-- Jocelyn SEROT, Francois BERRY --
-- {Jocelyn.Serot,Francois.Berry}@univ-bpclermont.fr --
-- --
-- Copyright 2011-2015 Jocelyn SEROT. All rights reserved. --
-- This file is distributed under the terms of the GNU Library General Public License --
-- with the special exception on linking described in file ../LICENSE. --
-- --
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_fb is
generic
(
depth : integer := 8; -- FIFO depth (number of cells)
size : integer := 8; -- FIFO width (size in bits of each cell)
threshold : integer := 32 -- Threshold for switching from a "small" (LE-based) to a "big" (RAM-based) implementation
);
port (
full : out std_logic;
datain : in std_logic_vector (size-1 downto 0);
enw : in std_logic;
empty : out std_logic;
dataout : out std_logic_vector(size-1 downto 0);
enr : in std_logic;
clk : in std_logic;
rst: in std_logic
);
end fifo_fb;
architecture archi of fifo_fb is
constant ad_Max : integer range 0 to depth-1:= depth-1;
constant ad_Min : integer range 0 to depth-1:= 0;
type fifo_length is array ( 0 to depth-1) of std_logic_vector((size-1) downto 0);
signal tmp: fifo_length ;
signal address: integer range 0 to depth-1 := ad_Max;
signal we_a,enr_c,enw_c:std_logic;
signal readaddr : natural range 0 to depth-1;
signal writeaddr : natural range 0 to depth-1;
signal cnt, cnt_c : integer range 0 to depth-1:=0;
signal inputD,outputD,inputR,outputR: STD_LOGIC_VECTOR (size-1 DOWNTO 0);
component single_clock_ram is
generic ( depth: integer := 10; size: integer := 10);
PORT (
clock: IN STD_LOGIC;
data: IN STD_LOGIC_VECTOR (size-1 DOWNTO 0);
write_address: IN INTEGER RANGE 0 to depth-1;
read_address: IN INTEGER RANGE 0 to depth-1;
we: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR (size-1 DOWNTO 0)
);
end component;
begin
SMALL_FIFO: if depth<threshold generate
shift_reg: process (clk) -- shift register
begin
if (clk'event and clk='1' ) then
if (enr='1' and enw='0') then -- read
for i in 0 to ad_Max-1 loop
tmp(i+1) <= tmp(i);
end loop;
end if;
if (enw='1' and enr='1') then -- read & write
if (address = ad_Max) then -- Tester cette condition .... !!
tmp(address)<=datain; -- J'ai envelevé le -1 ici
else
for i in 0 to ad_Max-1 loop
tmp(i+1) <= tmp(i);
end loop;
tmp(address+1)<=datain; -- j'ai rajouté +1
end if;
end if;
if (enw='1' and enr='0') then -- write
tmp(address)<=datain;
end if;
end if;
end process shift_reg;
counter : process(clk, rst) -- write address computation
begin
if ( rst='0' ) then
address <= ad_Max;
elsif (clk='1' and clk'event) then
if (enr = '1' and enw='0' and address < ad_Max) then -- read
-- Read a new data in FIFO when is not empty
-- Read a new data in FIFO and Write simultaneously => No increment
-- that's why wr='0'
address <= address + 1;
end if;
if (enw = '1' and enr='0' and address > ad_Min) then -- write
-- Write a new data in FIFO when is not full
-- Read a new data in FIFO and Write simultaneously => No increment
-- that's why rd='0'
address <= address - 1;
end if;
if (enw = '1' and enr='1' and address= ad_Max) then -- read & write
address <= address;
end if;
end if;
end process counter;
flags : process(address,enw,enr) -- empty/full flag generation
begin
if ( address > ad_Max-1 ) then
-- if ( enr='1' and address > (ad_Max-2) ) then
empty<= '1';
else
empty <='0';
end if;
if ( address < ad_Min+1 ) then
-- if (enw = '1' and address < (ad_Min+2) ) then
full<= '1';
else
full <='0';
end if;
end process flags;
dataout <= tmp(depth-1);
end generate;
BIG_FIFO: if depth>=threshold generate
MEM :single_clock_ram generic map (depth,size) port map (clk,inputR,writeaddr, readaddr, enw, outputR );
process(clk)
begin
if ( clk'event and clk='1' ) then
enw_c<=enw;
enr_c<=enr;
cnt_c<=cnt;
end if;
end process ;
MUX: process(datain, outputD,outputR,enw_c,enr_c,cnt_c)
-- Bypass when the FIFO is empty and we write and read simulaneoulsy
begin
if (cnt_c=0 and enr_c='1' and enw_c='1') then
inputD<= datain;
inputR<= (others => 'X');
dataout<= outputD;
else
inputR<= datain;
inputD<= (others => 'X');
dataout<= outputR;
end if;
end process MUX;
flags: process(cnt)
begin
if ( cnt = 0 ) then empty <= '1'; else empty <='0'; end if;
if ( cnt = depth ) then full<= '1'; else full <='0';end if;
end process flags;
process(clk,rst)
begin
if ( rst='0' ) then
readaddr <= 0;
writeaddr <= 0;
cnt <= 0;
elsif ( clk'event and clk='1' ) then
outputD<= inputD;
if ( enr = '1' ) then -- Read
if ( readaddr = depth-1 ) then
readaddr <= 0; -- circular buffer
else
readaddr <= readaddr + 1;
end if;
end if;
if ( enw = '1' and cnt < depth ) then -- Write
if ( writeaddr = depth-1 ) then
writeaddr <= 0; -- circular buffer
else
writeaddr <= writeaddr + 1;
end if;
end if;
if ( enw = '1' and enr = '0' and cnt < depth ) then
cnt <= cnt + 1;
elsif ( enw = '0' and enr = '1' and cnt > 0) then
cnt <= cnt - 1;
end if;
end if;
end process;
end generate;
end archi;
| gpl-3.0 | 094900c64cc5bdc6ec2edbb1761cf2e9 | 0.48517 | 3.781198 | false | false | false | false |
DreamIP/GPStudio | support/process/harris/hdl/pipliner_7x7.vhd | 1 | 8,678 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
library std;
library altera_mf;
use altera_mf.altera_mf_components.all;
use work.harris_package_components.all;
--use work.harris_package_variables.all;
entity pipliner_7x7 is
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer;
HALF_WINDOW_WIDTH: integer -- The total window's width is :(HALF_WINDOW_WIDTH*2+1) : Should be an odd number
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0);
pixel_table_7_7 : out pixel_matrix
);
end pipliner_7x7;
architecture rtl of pipliner_7x7 is
type pixel_mask is array (0 to 2,0 to 2) of signed((PIX_WIDTH) downto 0);
type pix_out_signal is array (0 to 5) of std_logic_vector((PIX_WIDTH-1) downto 0);
--type pixel_matrix is array (0 to 6,0 to 6) of std_logic_vector((PIX_WIDTH-1) downto 0);
--type filter_matrix is array (0 to 6,0 to 6) of std_logic_vector(RESULT_LENGTH downto 0);
constant RESULT_LENGHT : integer := 64;
constant FIFO_LENGHT : integer := LINE_WIDTH_MAX-7;
constant FIFO_LENGHT_WIDTH : integer := integer(ceil(log2(real(FIFO_LENGHT))));
constant Ix_sobel_mask:pixel_mask:=((to_signed(-1,9),to_signed(0,9),to_signed(1,9)),(to_signed(-1,9),to_signed(0,9),to_signed(1,9)),(to_signed(-1,9),to_signed(0,9),to_signed(1,9)));
constant Iy_sobel_mask:pixel_mask:=((to_signed(-1,9),to_signed(-1,9),to_signed(-1,9)),(to_signed(0,9),to_signed(0,9),to_signed(0,9)),(to_signed(1,9),to_signed(1,9),to_signed(1,9)));
signal fv_signal,out_clk_dv:std_logic;
signal widthimg_temp : std_logic_vector(15 downto 0):=widthimg_i;
signal sig_wrreq:std_logic:='1';
signal sig_rdreq:std_logic:='0';
signal line_pix_out:pix_out_signal;
shared variable R:std_logic_vector((RESULT_LENGHT-1) downto 0);
shared variable Prev_R_max:std_logic_vector((RESULT_LENGHT-1) downto 0):=x"00000001DCD65000";
shared variable R_max:std_logic_vector((RESULT_LENGHT-1) downto 0):=x"00000001DCD65000";
shared variable conv_value_x,conv_value_y:signed(17 downto 0):=to_signed(0,18);
shared variable conv_value:integer:=0;
shared variable param_changing_reset:std_logic:='0';
shared variable Ixx,Ixy,Iyy:signed(31 downto 0):=to_signed(0,32);
shared variable cast_36_bits:std_logic_vector(35 downto 0);
shared variable aclr:std_logic:='0';
shared variable Ixx_vec,Iyy_vec:std_logic_vector(31 downto 0);
shared variable mult_a,mult_b,mult_2_a,mult_2_b,mult_3_a,mult_3_b:std_logic_vector(31 downto 0);
shared variable mult_s,mult_2_s,mult_3_s,comp_a,comp_a_2,comp_b,comp_b_2,add_a_1,add_b_1,add_b_2,add_s_inter,add_s :std_logic_vector(63 downto 0);
shared variable comp_s,comp_s_2:std_logic:='1';
shared variable pixel_matrix_kernel:pixel_matrix;
component scfifo
generic
( LPM_WIDTH: POSITIVE;
LPM_WIDTHU: POSITIVE;
LPM_NUMWORDS: POSITIVE;
LPM_SHOWAHEAD: STRING := "OFF";
ALLOW_RWCYCLE_WHEN_FULL: STRING := "OFF";
OVERFLOW_CHECKING: STRING:= "ON";
UNDERFLOW_CHECKING: STRING:= "ON"
);
port
(
data: in std_logic_vector(LPM_WIDTH-1 downto 0);
clock, wrreq, rdreq, aclr: in std_logic;
full, empty, almost_full, almost_empty: out std_logic;
q: out std_logic_vector(LPM_WIDTH-1 downto 0);
usedw: out std_logic_vector(LPM_WIDTHU-1 downto 0)
);
end component;
begin
sig_wrreq<='1';
G_1 : for i in 0 to 5 generate
line_fifo : scfifo
generic map (
LPM_WIDTH =>PIX_WIDTH,
LPM_WIDTHU =>FIFO_LENGHT_WIDTH,
LPM_NUMWORDS =>FIFO_LENGHT
)
port map(
data => pixel_matrix_kernel(i+1,0),
clock => clk_proc,
wrreq => in_dv,
q => line_pix_out(i),
rdreq => sig_rdreq and in_dv,
aclr =>param_changing_reset or(not(reset_n))
);
end generate;
process (clk_proc, reset_n)
variable x_pos,y_pos : unsigned(15 downto 0);
variable counter:integer:=0;
begin
fv_signal<=in_fv;
if(reset_n='0') then
x_pos := to_unsigned(0, 16);
y_pos := to_unsigned(0, 16);
out_clk_dv<='0';
elsif(rising_edge(clk_proc)) then
fv_signal<=in_fv;
out_clk_dv<='0';
if(in_fv='0') then
x_pos := to_unsigned(0, 16);y_pos := to_unsigned(0, 16);
out_clk_dv<='0';
------------------------------------------------------------------------------------------------------
elsif(in_dv='1') then
counter:=counter+1;
if(counter=(unsigned(widthimg_i)-8)) then
sig_rdreq<='1';
end if;
out_clk_dv<='1';
for o in 0 to 6 loop
for p in 0 to 5 loop
pixel_matrix_kernel(o,p):=pixel_matrix_kernel(o,p+1);
end loop;
if (o<6) then
pixel_matrix_kernel(o,6):=line_pix_out(o);
end if;
end loop;
pixel_matrix_kernel(6,6):=in_data;
----------- end of line ----------------
if(x_pos=unsigned(widthimg_i)) then
y_pos := y_pos+1;
x_pos := to_unsigned (1, 16);
else
x_pos := x_pos+1;
end if;
-----------------------------------------
----------------------- bloquage et débloquage de l'horloge -----------------------------------------------------
if (y_pos<=to_unsigned (HALF_WINDOW_WIDTH-1, 16)) then
out_clk_dv<='0';
end if;
----------------------- blocage de bords spéciale pour les deux premiers élements de bords ----------------------
if (x_pos<=to_unsigned (HALF_WINDOW_WIDTH, 16)) then
if (y_pos=to_unsigned (3, 16)) then
out_clk_dv<='0';
end if;
end if;
-----------------------------------------------------------------------------------------------------------------
else
end if;
-------------- changing widthimg_i parameter---------------------------------------------------------------------
if (unsigned(widthimg_i)=unsigned(widthimg_temp)) then
param_changing_reset:='0';
else
param_changing_reset:='1';
counter:=0;
sig_rdreq<='0';
end if;
widthimg_temp<=widthimg_i;
-----------------------------------------------------------------------------
else
end if;
end process;
out_data<= std_logic_vector(to_unsigned(conv_value, 8));
out_dv <= out_clk_dv;
out_fv <= fv_signal;
pixel_table_7_7<=pixel_matrix_kernel;
end rtl;
| gpl-3.0 | 983a72673404162cb6a8f0f5c0961211 | 0.438847 | 3.94677 | false | false | false | false |
DreamIP/GPStudio | support/toolchain/caph/hdl/caph_lib/port_out.vhd | 1 | 2,243 | -----------------------------------------------------------------------------------------
-- --
-- This file is part of the CAPH Compiler distribution --
-- http://caph.univ-bpclermont.fr --
-- --
-- Jocelyn SEROT --
-- [email protected] --
-- --
-- Copyright 2011-2015 Jocelyn SEROT. All rights reserved. --
-- This file is distributed under the terms of the GNU Library General Public License --
-- with the special exception on linking described in file ../LICENSE. --
-- --
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
entity port_out is
generic ( filename: string := "result.in"; size: integer := 10 );
port ( empty : in std_logic;
din : in std_logic_vector(size-1 downto 0);
rd : out std_logic; -- read (pop) signal, active 1 on clk^
clk : in std_logic;
rst : in std_logic
);
end port_out;
architecture beh of port_out is
begin
process
file output_file: text;
variable file_line: line;
variable token: integer;
variable eof: boolean;
begin
rd <= '0';
eof := false;
file_open(output_file,filename,WRITE_MODE);
while not eof loop
wait until rising_edge(clk);
if ( empty = '0' ) then
write (file_line,to_bitvector(din));
writeline (output_file,file_line);
rd <= '1';
wait until rising_edge(clk);
rd <= '0';
end if;
end loop; -- TODO: set eof when run is completed ?
file_close(output_file);
wait;
end process;
end;
| gpl-3.0 | 917c199ddca044c0bea5dd7610043471 | 0.399911 | 4.962389 | false | false | false | false |
DreamIP/GPStudio | support/process/harris/hdl/harris.vhd | 1 | 2,497 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity harris is
generic (
LINE_WIDTH_MAX : integer := 320;
IN_SIZE : integer := 8;
OUT_SIZE : integer := 8;
CLK_PROC_FREQ : integer := 48000000
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
in_data : in std_logic_vector((IN_SIZE-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_data : out std_logic_vector((OUT_SIZE-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end harris;
architecture rtl of harris is
component harris_slave
port (
clk_proc : in std_logic;
reset_n : in std_logic;
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0);
enable_o : out std_logic;
widthimg_o : out std_logic_vector(15 downto 0)
);
end component;
component harris_process
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0)
);
end component;
signal enable_s : std_logic;
signal widthimg_s : std_logic_vector(15 downto 0);
begin
harris_slave_inst : harris_slave
port map (
clk_proc => clk_proc,
reset_n => reset_n,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o,
enable_o => enable_s,
widthimg_o => widthimg_s
);
harris_process_inst : harris_process
generic map (
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
PIX_WIDTH => IN_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv,
enable_i => enable_s,
widthimg_i => widthimg_s
);
end rtl;
| gpl-3.0 | 4fcca34032969821b5fd74d67fcac5a2 | 0.579896 | 2.331466 | false | false | false | false |
DreamIP/GPStudio | support/process/erode/hdl/erode_process.vhd | 1 | 6,453 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity erode_process is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_value : in std_logic_vector(15 downto 0);
heigtimg_reg_value : in std_logic_vector(15 downto 0);
er00_reg_m00 : in std_logic_vector(7 downto 0);
er01_reg_m01 : in std_logic_vector(7 downto 0);
er02_reg_m02 : in std_logic_vector(7 downto 0);
er10_reg_m10 : in std_logic_vector(7 downto 0);
er11_reg_m11 : in std_logic_vector(7 downto 0);
er12_reg_m12 : in std_logic_vector(7 downto 0);
er20_reg_m20 : in std_logic_vector(7 downto 0);
er21_reg_m21 : in std_logic_vector(7 downto 0);
er22_reg_m22 : in std_logic_vector(7 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end erode_process;
architecture rtl of erode_process is
component matrix_extractor
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer;
OUTVALUE_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
------------------------ matrix out ---------------------
p00, p01, p02 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p10, p11, p12 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p20, p21, p22 : out std_logic_vector((PIX_WIDTH-1) downto 0);
matrix_dv : out std_logic;
---------------------- computed value -------------------
value_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
value_dv : in std_logic;
------------------------- params ------------------------
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0)
);
end component;
-- neighbors extraction
signal p00, p01, p02 : std_logic_vector((IN_SIZE-1) downto 0);
signal p10, p11, p12 : std_logic_vector((IN_SIZE-1) downto 0);
signal p20, p21, p22 : std_logic_vector((IN_SIZE-1) downto 0);
signal matrix_dv : std_logic;
-- Erosion matrix
-- 0 1 0 e00 e01 e02
-- 1 1 1 e10 e11 e12
-- 0 1 0 e20 e21 e22
signal e00, e01, e02 : unsigned((IN_SIZE-1) downto 0);
signal e10, e11, e12 : unsigned((IN_SIZE-1) downto 0);
signal e20, e21, e22 : unsigned((IN_SIZE-1) downto 0);
-- parsing back from value to flow
signal value_data : std_logic_vector((IN_SIZE-1) downto 0);
signal value_dv : std_logic;
signal out_fv_s : std_logic;
signal enable_s : std_logic;
signal erode_dv : std_logic;
begin
matrix_extractor_inst : matrix_extractor
generic map (
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
PIX_WIDTH => IN_SIZE,
OUTVALUE_WIDTH => IN_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
p00 => p00, p01 => p01, p02 => p02,
p10 => p10, p11 => p11, p12 => p12,
p20 => p20, p21 => p21, p22 => p22,
matrix_dv => matrix_dv,
value_data => value_data,
value_dv => value_dv,
out_data => out_data,
out_fv => out_fv_s,
out_dv => out_dv,
enable_i => status_reg_enable_bit,
widthimg_i => widthimg_reg_value
);
data_process : process (clk_proc, reset_n, matrix_dv)
variable val : unsigned((IN_SIZE-1) downto 0);
begin
if(reset_n='0') then
enable_s <= '0';
erode_dv <= '0';
value_dv <= '0';
elsif(rising_edge(clk_proc)) then
-- Waiting for an image flow
if(in_fv = '0') then
-- Update params here, between two images processing
enable_s <= status_reg_enable_bit;
e00 <= unsigned(er00_reg_m00);
e01 <= unsigned(er01_reg_m01);
e02 <= unsigned(er02_reg_m02);
e10 <= unsigned(er10_reg_m10);
e11 <= unsigned(er11_reg_m11);
e12 <= unsigned(er12_reg_m12);
e20 <= unsigned(er20_reg_m20);
e21 <= unsigned(er21_reg_m21);
e22 <= unsigned(er22_reg_m22);
value_dv <= '0';
end if;
-- A matrix is available to process
erode_dv <= '0';
if(matrix_dv = '1' and enable_s = '1') then
val := (others => '1');
--
if(e00 /=0) then
if(val>unsigned(p00)) then
val := unsigned(p00);
end if;
end if;
--
if(e01 /=0) then
if(val>unsigned(p01)) then
val := unsigned(p01);
end if;
end if;
--
if(e02 /=0) then
if(val>unsigned(p02)) then
val := unsigned(p02);
end if;
end if;
--
if(e10 /=0) then
if(val>unsigned(p10)) then
val := unsigned(p10);
end if;
end if;
--
if(e11 /=0) then
if(val>unsigned(p11)) then
val := unsigned(p11);
end if;
end if;
--
if(e12 /=0) then
if(val>unsigned(p12)) then
val := unsigned(p12);
end if;
end if;
--
if(e20 /=0) then
if(val>unsigned(p20)) then
val := unsigned(p20);
end if;
end if;
--
if(e21 /=0) then
if(val>unsigned(p21)) then
val := unsigned(p21);
end if;
end if;
--
if(e22 /=0) then
if(val>unsigned(p22)) then
val := unsigned(p22);
end if;
end if;
erode_dv <= '1';
end if;
-- Matrix process has ended
if(enable_s = '1' and erode_dv = '1') then
value_data <= std_logic_vector(val)(OUT_SIZE -1 downto 0);
value_dv <= '1';
else
value_dv <= '0';
end if;
end if;
end process;
out_fv <= enable_s and out_fv_s;
end rtl;
| gpl-3.0 | 3d3a041aa0aba89e4db660a872570e95 | 0.525492 | 2.857839 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/hostinterface/src/dynamicBridgeRtl.vhd | 3 | 16,557 | -------------------------------------------------------------------------------
--! @file dynamicBridgeRtl.vhd
--
--! @brief Dynamic Bridge for translating static to dynamic memory spaces
--
--! @details The Dynamic Bridge component translates a static memory mapping
--! into a dynamic memory map that can be changed during runtime.
--! This enhances the functionality of an ordinary memory mapped bridge logic.
--! Additionally several memory spaces can be configured (compilation).
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! need reduce or operation
use ieee.std_logic_misc.OR_REDUCE;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use host interface package for specific types
use work.hostInterfacePkg.all;
-------------------------------------------------------------------------------
--! @brief Dynamic bridge translates a fixed address space into a flexible one.
-------------------------------------------------------------------------------
--! @details
--! The dynamic bridge has an input port with a fixed (before runtime) memory
--! mapping, which is translated to a flexible address space mapping.
--! The flexible address space can be changed during runtime in order to
--! redirect accesses from the input to other locations.
--! The base addresses for the static port are set by generic gBaseAddressArray.
--! The base addresses for the dynamic port are set through the BaseSet port
-------------------------------------------------------------------------------
entity dynamicBridge is
generic (
--! number of static address spaces
gAddressSpaceCount : natural := 2;
--! select wheather DPRAM or registers will be used as memory (false = 0, true /= 0)
gUseMemBlock : integer := 0;
--! base addresses in static address space (note: last-1 = high address)
gBaseAddressArray : tArrayStd32 := (x"0000_1000" , x"0000_2000" , x"0000_3000")
);
port (
-- Global
--! component-wide clock signal
iClk : in std_logic;
--! component-wide reset signal
iRst : in std_logic;
-- Bridge
--! address of static address space
iBridgeAddress : in std_logic_vector;
--! Request strobe
iBridgeRequest : in std_logic;
--! address of dynamic address space (translated input)
oBridgeAddress : out std_logic_vector;
--! Select signal of any address space selected
oBridgeSelectAny : out std_logic;
--! select signals of all address spaces
oBridgeSelect : out std_logic_vector(gAddressSpaceCount-1 downto 0);
--! Bridge output valid
oBridgeValid : out std_logic;
-- BaseSet Memory Mapped Write Bus
--! BaseSet write strobe
iBaseSetWrite : in std_logic;
--! BaseSet read strobe
iBaseSetRead : in std_logic;
--! BaseSet byteenable
iBaseSetByteenable : in std_logic_vector;
--! BaseSet address bus
iBaseSetAddress : in std_logic_vector(LogDualis(gAddressSpaceCount)-1 downto 0);
--! BaseSet write data bus
iBaseSetData : in std_logic_vector;
--! BaseSet read data bus
oBaseSetData : out std_logic_vector;
--! BaseSet acknowledge
oBaseSetAck : out std_logic
);
end dynamicBridge;
-------------------------------------------------------------------------------
--! @brief Register Transfer Level of Dynamic Bridge device
-------------------------------------------------------------------------------
--! @details
--! The dynamic bridge rtl applies generated address decoders
--! to generate select signals for the static address spaces.
--! The select signals are forwarded register file holding the base address
--! offsets in the dynamic memory space. The input address is manipulated with
--! arithmetic operators to gain the output address. The lut file holds the
--! base addresses in the static memory space.
-------------------------------------------------------------------------------
architecture rtl of dynamicBridge is
--! Bridge cycle delay
constant cBridgeCycleDelay : natural := 3;
--! Bridge read path enable all bytes
constant cByteenableAllOnes : std_logic_vector(iBaseSetByteenable'range) :=
(others => cActivated);
--! convert address array into stream
constant cBaseAddressArrayStd : std_logic_vector
((gAddressSpaceCount+1)*cArrayStd32ElementSize-1 downto 0) :=
CONV_STDLOGICVECTOR(gBaseAddressArray, gBaseAddressArray'length);
--! Input address register
signal inAddrReg : std_logic_vector(iBridgeAddress'range);
--! Request rising edge
signal bridgeRequest_rising : std_logic;
--! Input address store strobe
signal inAddrStore : std_logic;
--! Request acknowledge terminal count strobe
signal reqAckTcnt : std_logic;
--! address decoder select signals one hot coded
signal addrDecSelOneHot : std_logic_vector(gAddressSpaceCount-1 downto 0);
--! address decoder select signals binary coded
signal addrDecSelBinary : std_logic_vector(LogDualis(gAddressSpaceCount)-1 downto 0);
--! selected static lut file base offset
signal lutFileBase : std_logic_vector(inAddrReg'range);
--! Base address in bridge master environment
signal addrSpaceOffset : std_logic_vector(inAddrReg'range);
--! Base address in bridge master environment (unregistered)
signal addrSpaceOffset_unreg : std_logic_vector(inAddrReg'range);
--! Dynamic address offset within selected static space
signal dynamicOffset : std_logic_vector(iBaseSetData'range);
--! Translated address
signal translateAddress : std_logic_vector(maximum(iBaseSetData'high, oBridgeAddress'high) downto inAddrReg'low);
begin
-- assert
assert (cBridgeCycleDelay > 0)
report "Set cBridgeCycleDelay > 0"
severity failure;
-- export
oBridgeSelect <= addrDecSelOneHot;
oBridgeSelectAny <= OR_REDUCE(addrDecSelOneHot);
oBridgeValid <= reqAckTcnt;
oBridgeAddress <= translateAddress(oBridgeAddress'range);
--! Store the input address with the request strobe
storeAddr : process(iRst, iClk)
begin
if iRst = cActivated then
inAddrReg <= (others => cInactivated);
elsif rising_edge(iClk) then
if inAddrStore = cActivated then
inAddrReg <= iBridgeAddress;
end if;
end if;
end process;
--! Get rising edge of request signaling
reqEdge : entity libcommon.edgedetector
port map (
iArst => iRst,
iClk => iClk,
iEnable => cActivated,
iData => iBridgeRequest,
oRising => bridgeRequest_rising,
oFalling => open,
oAny => open
);
inAddrStore <= bridgeRequest_rising;
--! Generate the request acknowledge signal
reqAck : entity libcommon.cnt
generic map (
gCntWidth => logDualis(cBridgeCycleDelay+1),
gTcntVal => cBridgeCycleDelay
)
port map (
iArst => iRst,
iClk => iClk,
iEnable => iBridgeRequest,
iSrst => cInactivated,
oCnt => open,
oTcnt => reqAckTcnt
);
--! Generate Address Decoders
genAddressDecoder : for i in 0 to gAddressSpaceCount-1 generate
insAddressDecoder : entity libcommon.addrDecode
generic map (
gAddrWidth => inAddrReg'length,
gBaseAddr => to_integer(unsigned(gBaseAddressArray(i)(inAddrReg'range))),
gHighAddr => to_integer(unsigned(gBaseAddressArray(i+1)(inAddrReg'range))-1)
)
port map (
iEnable => iBridgeRequest,
iAddress => inAddrReg,
oSelect => addrDecSelOneHot(i)
);
end generate;
--! Convert one hot from address decoder to binary
insBinaryEncoder : entity libcommon.binaryEncoder
generic map (
gDataWidth => gAddressSpaceCount
)
port map (
iOneHot => addrDecSelOneHot,
oBinary => addrDecSelBinary
);
--! select static base address in lut file
insLutFile : entity libcommon.lutFile
generic map (
gLutCount => gAddressSpaceCount,
gLutWidth => cArrayStd32ElementSize,
gLutInitValue => cBaseAddressArrayStd(cBaseAddressArrayStd'left downto cArrayStd32ElementSize)
-- omit high address of last memory map
)
port map (
iAddrRead => addrDecSelBinary,
oData => lutFileBase
);
-- calculate address offset within static space
addrSpaceOffset_unreg <= std_logic_vector(
unsigned(inAddrReg) - unsigned(lutFileBase)
);
--! Registers to break combinational path of lut file output.
regAddrSpace : process(iRst, iClk)
begin
if iRst = cActivated then
addrSpaceOffset <= (others => cInactivated);
elsif rising_edge(iClk) then
addrSpaceOffset <= addrSpaceOffset_unreg;
end if;
end process;
REGFILE : if gUseMemBlock = 0 generate
signal dynamicOffset_unreg : std_logic_vector(dynamicOffset'range);
begin
--! select dynamic base address in register file
insRegFile : entity libcommon.registerFile
generic map (
gRegCount => gAddressSpaceCount
)
port map (
iClk => iClk,
iRst => iRst,
iWriteA => iBaseSetWrite,
iWriteB => cInactivated, -- write port B unused
iByteenableA => iBaseSetByteenable,
iByteenableB => cByteenableAllOnes,
iAddrA => iBaseSetAddress,
iAddrB => addrDecSelBinary,
iWritedataA => iBaseSetData,
oReaddataA => oBaseSetData,
iWritedataB => iBaseSetData, -- write port B unused
oReaddataB => dynamicOffset_unreg
);
regDynOff : process(iRst, iClk)
begin
if iRst = cActivated then
dynamicOffset <= (others => cInactivated);
elsif rising_edge(iClk) then
dynamicOffset <= dynamicOffset_unreg;
end if;
end process;
BASESETACK : oBaseSetAck <= iBaseSetWrite or iBaseSetRead;
end generate REGFILE;
genDPRAM : if gUseMemBlock /= 0 generate
-- Clip dpr word width to values of power 2 (e.g. 8, 16, 32)
constant cDprWordWidth : natural := 2**logDualis(iBaseSetData'length);
constant cDprAddrWidth : natural := logDualis(gAddressSpaceCount);
constant cDprReadDel : natural := 1;
type tDprPort is record
write : std_logic;
read : std_logic;
address : std_logic_vector(cDprAddrWidth-1 downto 0);
byteenable : std_logic_vector(cDprWordWidth/8-1 downto 0);
writedata : std_logic_vector(cDprWordWidth-1 downto 0);
readdata : std_logic_vector(cDprWordWidth-1 downto 0);
end record;
signal dprPortA : tDprPort;
signal dprPortA_readAck : std_logic;
signal dprPortB : tDprPort;
begin
--! This combinatoric process assigns base sets to the dpr.
--! The default assignments avoid warnings in synthesize tools.
dprAssign : process (
iBaseSetByteenable,
iBaseSetData
)
begin
--default assignments
dprPortA.byteenable <= (others => cInactivated);
dprPortA.writedata <= (others => cInactivated);
dprPortB.byteenable <= (others => cInactivated);
dprPortB.writedata <= (others => cInactivated);
dprPortA.byteenable(iBaseSetByteenable'range) <= iBaseSetByteenable;
dprPortA.writedata(iBaseSetData'range) <= iBaseSetData;
dprPortB.byteenable <= (others => cInactivated);
dprPortB.writedata(iBaseSetData'range) <= iBaseSetData;
end process;
dprPortA.write <= iBaseSetWrite;
dprPortA.read <= iBaseSetRead;
dprPortA.address <= iBaseSetAddress;
oBaseSetData <= dprPortA.readdata(oBaseSetData'range);
dprPortB.write <= cInactivated; --unused
dprPortB.read <= cActivated; --unused
dprPortB.address <= addrDecSelBinary;
dynamicOffset <= dprPortB.readdata(dynamicOffset'range);
insDPRAM: entity work.dpRam
generic map(
gWordWidth => cDprWordWidth,
gNumberOfWords => gAddressSpaceCount
)
port map(
iClk_A => iClk,
iEnable_A => cActivated,
iWriteEnable_A => dprPortA.write,
iAddress_A => dprPortA.address,
iByteEnable_A => dprPortA.byteenable,
iWritedata_A => dprPortA.writedata,
oReaddata_A => dprPortA.readdata,
iClk_B => iClk,
iEnable_B => cActivated,
iWriteEnable_B => dprPortB.write,
iAddress_B => dprPortB.address,
iByteEnable_B => dprPortB.byteenable,
iWritedata_B => dprPortB.writedata,
oReaddata_B => dprPortB.readdata
);
BASESETACK : oBaseSetAck <= dprPortA.write or dprPortA_readAck;
--! Generate the read acknowledge signal
rdAck : entity libcommon.cnt
generic map (
gCntWidth => logDualis(cDprReadDel+1),
gTcntVal => cDprReadDel
)
port map (
iArst => iRst,
iClk => iClk,
iEnable => dprPortA.read,
iSrst => cInactivated,
oCnt => open,
oTcnt => dprPortA_readAck
);
end generate genDPRAM;
-- calculate translated address offset in dynamic space
translateAddress <= std_logic_vector(
unsigned(dynamicOffset) + unsigned(addrSpaceOffset)
);
end rtl;
| gpl-2.0 | c03362acedbce80f906f4fbbe6e401cf | 0.5896 | 5.09603 | false | false | false | false |
Reiuiji/ECE368-Lab | Examples/Templates/VHDL-Template-TestBench.vhd | 1 | 2,672 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Class: ECE 368 Digital Design
-- Engineer: [Engineer 1]
-- [Engineer 2]
--
-- Create Date: [Date]
-- Module Name: [Module Name]
-- Project Name: [Project Name]
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description:
-- [Insert Description]
--
-- Notes:
-- [Insert Notes]
--
-- Revision:
-- [Insert Revision]
--
---------------------------------------------------
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity [Name]_tb is
end [Name]_tb;
architecture Behavioral of [Name] is
component [ComponentName] is
generic(
[VariableName]:integer:=8
);
port (
CLK : in STD_LOGIC;
[IN_Port0] : in STD_LOGIC;
[IN_Port1] : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
[OUT_Port0] : out STD_LOGIC;
[OUT_Port1] : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
signal CLK : STD_LOGIC := '0';
signal RESET : STD_LOGIC := '0';
begin
-- Instantiate the Unit Under Testing (UUT)
uut: [ComponentName] port map(
CLK => CLK : in STD_LOGIC;
[IN_Port0] => [IN_Port0] : in STD_LOGIC;
[IN_Port1] => [IN_Port1] : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
[OUT_Port0] => [OUT_Port0] : out STD_LOGIC;
[OUT_Port1] => [OUT_Port1] : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
m50MHZ_CLK: process
begin
CLK <= '0'; wait for period;
CLK <= '1'; wait for period;
end process m50MHZ_CLK;
tb : process
begin
-- Wait 100 ns for global reset to finish
wait for 100 ns;
report "Starting [name] Test Bench" severity NOTE;
----- Unit Test -----
--Reset
RESET <= '1'; wait for period;
RESET <= '0'; wait for period;
assert ([OUT_Port0] = 00) report "Failed READ. [OUT_Port0]=" & integer'image(to_integer(unsigned([OUT_Port0]))) severity ERROR;
-- Test each input via loop
for i in 0 to 256 loop
[IN_Port0] <= x"F0";
[OUT_Port0] <= '0'; wait for period;
[OUT_Port0] <= '1'; wait for period;
[IN_Port0] <= std_logic_vector(to_signed(i,IN_Port0'length)); wait for 2*period;
[OUT_Port0] <= '0'; wait for period;
[OUT_Port0] <= '1'; wait for period;
end loop;
end process;
end Behavioral;
| mit | 17700ba17c04f2e9c45a9e85875de044 | 0.533308 | 3.479167 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/boards/terasic-de2-115/cn-single-gpio/quartus/toplevel.vhd | 3 | 15,214 | -------------------------------------------------------------------------------
--! @file toplevel.vhd
--
--! @brief Toplevel of Nios CN FPGA directIO part
--
--! @details This is the toplevel of the Nios CN FPGA directIO design for the
--! INK DE2-115 Evaluation Board.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library libcommon;
use libcommon.global.all;
entity toplevel is
port (
-- 50 MHZ CLK IN
EXT_CLK : in std_logic;
-- PHY Interfaces
PHY_GXCLK : out std_logic_vector(1 downto 0);
PHY_LINK_n : in std_logic_vector(1 downto 0);
PHY_RXCLK : in std_logic_vector(1 downto 0);
PHY_RXER : in std_logic_vector(1 downto 0);
PHY_RXDV : in std_logic_vector(1 downto 0);
PHY_RXD : in std_logic_vector(7 downto 0);
PHY_TXCLK : in std_logic_vector(1 downto 0);
PHY_TXER : out std_logic_vector(1 downto 0);
PHY_TXEN : out std_logic_vector(1 downto 0);
PHY_TXD : out std_logic_vector(7 downto 0);
PHY_MDIO : inout std_logic_vector(1 downto 0);
PHY_MDC : out std_logic_vector(1 downto 0);
PHY_RESET_n : out std_logic_vector(1 downto 0);
-- EPCS
EPCS_DCLK : out std_logic;
EPCS_SCE : out std_logic;
EPCS_SDO : out std_logic;
EPCS_DATA0 : in std_logic;
-- 2 MB SRAM
SRAM_CE_n : out std_logic;
SRAM_OE_n : out std_logic;
SRAM_WE_n : out std_logic;
SRAM_ADDR : out std_logic_vector(20 downto 1);
SRAM_BE_n : out std_logic_vector(1 downto 0);
SRAM_DQ : inout std_logic_vector(15 downto 0);
-- NODE_SWITCH
NODE_SWITCH : in std_logic_vector(7 downto 0);
-- KEY
KEY_n : in std_logic_vector(3 downto 0);
-- LED
LEDG : out std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(15 downto 0);
-- HEX LED
HEX0 : out std_logic_vector(6 downto 0);
HEX1 : out std_logic_vector(6 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
-- BENCHMARK_OUT
BENCHMARK : out std_logic_vector(7 downto 0);
-- LCD
LCD_ON : out std_logic;
LCD_BLON : out std_logic;
LCD_DQ : inout std_logic_vector(7 downto 0);
LCD_E : out std_logic;
LCD_RS : out std_logic;
LCD_RW : out std_logic
);
end toplevel;
architecture rtl of toplevel is
component cnSingleGpio is
port (
clk25_clk : in std_logic := 'X';
clk50_clk : in std_logic := 'X';
reset_reset_n : in std_logic := 'X';
clk100_clk : in std_logic := 'X';
-- SRAM
tri_state_0_tcm_address_out : out std_logic_vector(20 downto 0);
tri_state_0_tcm_byteenable_n_out : out std_logic_vector(1 downto 0);
tri_state_0_tcm_read_n_out : out std_logic;
tri_state_0_tcm_write_n_out : out std_logic;
tri_state_0_tcm_data_out : inout std_logic_vector(15 downto 0) := (others => 'X');
tri_state_0_tcm_chipselect_n_out : out std_logic;
-- OPENMAC
openmac_0_mii_txEnable : out std_logic_vector(1 downto 0);
openmac_0_mii_txData : out std_logic_vector(7 downto 0);
openmac_0_mii_txClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxError : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxDataValid : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxData : in std_logic_vector(7 downto 0) := (others => 'X');
openmac_0_mii_rxClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_smi_nPhyRst : out std_logic_vector(1 downto 0);
openmac_0_smi_clk : out std_logic_vector(1 downto 0);
openmac_0_smi_dio : inout std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_pktactivity_export : out std_logic;
-- BENCHMARK
pcp_0_benchmark_pio_export : out std_logic_vector(7 downto 0);
-- EPCS
epcs_flash_dclk : out std_logic;
epcs_flash_sce : out std_logic;
epcs_flash_sdo : out std_logic;
epcs_flash_data0 : in std_logic := 'X';
-- LCD
lcd_data : inout std_logic_vector(7 downto 0) := (others => 'X');
lcd_E : out std_logic;
lcd_RS : out std_logic;
lcd_RW : out std_logic;
-- NODE SWITCH
node_switch_pio_export : in std_logic_vector(7 downto 0) := (others => 'X');
-- STATUS ERROR LED
powerlink_led_export : out std_logic_vector(1 downto 0);
-- CPU RESET REQUEST
pcp_0_cpu_resetrequest_resetrequest : in std_logic := 'X';
pcp_0_cpu_resetrequest_resettaken : out std_logic;
-- Application ports
app_pio_in_port : in std_logic_vector(31 downto 0) := (others => 'X');
app_pio_out_port : out std_logic_vector(31 downto 0)
);
end component cnSingleGpio;
-- PLL component
component pll
port (
inclk0 : in std_logic;
c0 : out std_logic;
c1 : out std_logic;
c2 : out std_logic;
c3 : out std_logic;
locked : out std_logic
);
end component;
signal clk25 : std_logic;
signal clk50 : std_logic;
signal clk100 : std_logic;
signal pllLocked : std_logic;
signal sramAddr : std_logic_vector(SRAM_ADDR'high downto 0);
signal plk_status_error : std_logic_vector(1 downto 0);
signal openmac_activity : std_logic;
type tSevenSegArray is array (natural range <>) of std_logic_vector(6 downto 0);
constant cNumberOfHex : natural := 8;
signal hex : std_logic_vector(cNumberOfHex*4-1 downto 0);
signal sevenSegArray : tSevenSegArray(cNumberOfHex-1 downto 0);
signal app_input : std_logic_vector(31 downto 0);
signal app_output : std_logic_vector(31 downto 0);
begin
SRAM_ADDR <= sramAddr(SRAM_ADDR'range);
PHY_GXCLK <= (others => '0');
PHY_TXER <= (others => '0');
LCD_ON <= '1';
LCD_BLON <= '1';
---------------------------------------------------------------------------
-- Green LED assignments
LEDG <= plk_status_error(0) & -- POWERLINK Status LED
"000" & -- Reserved
(openmac_activity and not PHY_LINK_n(0)) & -- Gated activity
not PHY_LINK_n(0) & -- Link
(openmac_activity and not PHY_LINK_n(1)) & -- Gated activity
not PHY_LINK_n(1); -- Link
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Red LED assignments
LEDR <= x"000" & -- Reserved
"000" & -- Reserved
plk_status_error(1); -- POWERLINK Error LED
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Application Input and Output assignments
-- Input: Map KEY nibble to Application Input
app_input <= x"0000000" & not KEY_n;
-- Output: Map Application Output to HEX LEDs
hex <= app_output;
---------------------------------------------------------------------------
inst : component cnSingleGpio
port map (
clk25_clk => clk25,
clk50_clk => clk50,
clk100_clk => clk100,
reset_reset_n => pllLocked,
pcp_0_cpu_resetrequest_resetrequest => '0',
pcp_0_cpu_resetrequest_resettaken => open,
openmac_0_mii_txEnable => PHY_TXEN,
openmac_0_mii_txData => PHY_TXD,
openmac_0_mii_txClk => PHY_TXCLK,
openmac_0_mii_rxError => PHY_RXER,
openmac_0_mii_rxDataValid => PHY_RXDV,
openmac_0_mii_rxData => PHY_RXD,
openmac_0_mii_rxClk => PHY_RXCLK,
openmac_0_smi_nPhyRst => PHY_RESET_n,
openmac_0_smi_clk => PHY_MDC,
openmac_0_smi_dio => PHY_MDIO,
openmac_0_pktactivity_export => openmac_activity,
tri_state_0_tcm_address_out => sramAddr,
tri_state_0_tcm_read_n_out => SRAM_OE_n,
tri_state_0_tcm_byteenable_n_out => SRAM_BE_n,
tri_state_0_tcm_write_n_out => SRAM_WE_n,
tri_state_0_tcm_data_out => SRAM_DQ,
tri_state_0_tcm_chipselect_n_out => SRAM_CE_n,
pcp_0_benchmark_pio_export => BENCHMARK,
epcs_flash_dclk => EPCS_DCLK,
epcs_flash_sce => EPCS_SCE,
epcs_flash_sdo => EPCS_SDO,
epcs_flash_data0 => EPCS_DATA0,
node_switch_pio_export => NODE_SWITCH,
powerlink_led_export => plk_status_error,
lcd_data => LCD_DQ,
lcd_E => LCD_E,
lcd_RS => LCD_RS,
lcd_RW => LCD_RW,
app_pio_in_port => app_input,
app_pio_out_port => app_output
);
-- Pll Instance
pllInst : pll
port map (
inclk0 => EXT_CLK,
c0 => clk50,
c1 => clk100,
c2 => clk25,
c3 => open,
locked => pllLocked
);
-- bcd to 7 segment
genBcdTo7Seg : for i in cNumberOfHex-1 downto 0 generate
signal tmpHex : std_logic_vector(3 downto 0);
signal tmpSev : std_logic_vector(6 downto 0);
begin
tmpHex <= hex((i+1)*4-1 downto i*4);
sevenSegArray(i) <= tmpSev;
bcdTo7Seg0 : entity libcommon.bcd2led
port map (
iBcdVal => tmpHex,
oLed => open,
onLed => tmpSev
);
end generate genBcdTo7Seg;
-- assign outports to array
HEX0 <= sevenSegArray(0);
HEX1 <= sevenSegArray(1);
HEX2 <= sevenSegArray(2);
HEX3 <= sevenSegArray(3);
HEX4 <= sevenSegArray(4);
HEX5 <= sevenSegArray(5);
HEX6 <= sevenSegArray(6);
HEX7 <= sevenSegArray(7);
end rtl;
| gpl-2.0 | 9bb93e0ce02b82cc97b9ca6c8ca40947 | 0.435914 | 4.509188 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/sync/boundary.vhdl | 1 | 1,892 | --
-- Boundary
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
entity Boundary is
generic(
BYTES : positive:=4
);
port(
clk_i : in std_logic;
pattern_i : in std_logic_vector(BYTES-1 downto 0);
comma_i : in std_logic_vector(BYTES-1 downto 0);
data_i : in std_logic_vector(BYTES*8-1 downto 0);
comma_o : out std_logic_vector(BYTES-1 downto 0);
data_o : out std_logic_vector(BYTES*8-1 downto 0)
);
end entity Boundary;
architecture RTL of Boundary is
constant BYTES2 : positive:=BYTES*2;
constant BYTES3 : positive:=BYTES*3;
constant WIDTH : positive:=BYTES*8;
constant WIDTH2 : positive:=WIDTH*2;
constant WIDTH3 : positive:=WIDTH*3;
signal comma_r1, comma_r2 : std_logic_vector(BYTES-1 downto 0);
signal comma : std_logic_vector(BYTES3-1 downto 0);
signal data_r1, data_r2 : std_logic_vector(WIDTH-1 downto 0);
signal data : std_logic_vector(WIDTH3-1 downto 0);
signal index : natural range 0 to BYTES-1:=0;
begin
do_reg: process (clk_i)
begin
if rising_edge(clk_i) then
comma_r1 <= comma_i;
comma_r2 <= comma_r1;
data_r1 <= data_i;
data_r2 <= data_r1;
end if;
end process;
comma <= comma_i & comma_r1 & comma_r2;
data <= data_i & data_r1 & data_r2;
do_boundary: process (clk_i)
begin
if rising_edge(clk_i) then
for i in 0 to BYTES-1 loop
if comma(BYTES2+i-1 downto BYTES+i)=pattern_i then
index <= i;
end if;
end loop;
end if;
end process;
comma_o <= comma(BYTES+index-1 downto index);
data_o <= data(WIDTH+index*8-1 downto index*8);
end architecture RTL;
| bsd-3-clause | 96eda5e466ab8e5e29c4c13113cea3cf | 0.592495 | 3.179832 | false | false | false | false |
DreamIP/GPStudio | support/process/conv/hdl/conv_process.vhd | 1 | 6,501 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity conv_process is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer;
WEIGHT_SIZE : integer := 8
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_width : in std_logic_vector(15 downto 0);
w00_reg_m00 : in std_logic_vector(7 downto 0);
w01_reg_m01 : in std_logic_vector(7 downto 0);
w02_reg_m02 : in std_logic_vector(7 downto 0);
w10_reg_m10 : in std_logic_vector(7 downto 0);
w11_reg_m11 : in std_logic_vector(7 downto 0);
w12_reg_m12 : in std_logic_vector(7 downto 0);
w20_reg_m20 : in std_logic_vector(7 downto 0);
w21_reg_m21 : in std_logic_vector(7 downto 0);
w22_reg_m22 : in std_logic_vector(7 downto 0);
norm_reg_norm : in std_logic_vector(3 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end conv_process;
architecture rtl of conv_process is
component matrix_extractor
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer;
OUTVALUE_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
------------------------ matrix out ---------------------
p00, p01, p02 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p10, p11, p12 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p20, p21, p22 : out std_logic_vector((PIX_WIDTH-1) downto 0);
matrix_dv : out std_logic;
---------------------- computed value -------------------
value_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
value_dv : in std_logic;
------------------------- params ------------------------
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0)
);
end component;
-- buffered kernell weights and norm
signal w00, w01, w02 : signed((IN_SIZE-1) downto 0);
signal w10, w11, w12 : signed((IN_SIZE-1) downto 0);
signal w20, w21, w22 : signed((IN_SIZE-1) downto 0);
signal norm : std_logic_vector(3 downto 0);
-- neighbors extraction
signal p00, p01, p02 : std_logic_vector((IN_SIZE-1) downto 0);
signal p10, p11, p12 : std_logic_vector((IN_SIZE-1) downto 0);
signal p20, p21, p22 : std_logic_vector((IN_SIZE-1) downto 0);
signal matrix_dv : std_logic;
-- products calculation
signal prod00, prod01, prod02 : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
signal prod10, prod11, prod12 : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
signal prod20, prod21, prod22 : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
signal prod_dv : std_logic;
signal value_data : std_logic_vector((IN_SIZE-1) downto 0);
signal value_dv : std_logic;
signal out_fv_s : std_logic;
signal enable_s : std_logic;
begin
matrix_extractor_inst : matrix_extractor
generic map (
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
PIX_WIDTH => IN_SIZE,
OUTVALUE_WIDTH => IN_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
p00 => p00, p01 => p01, p02 => p02,
p10 => p10, p11 => p11, p12 => p12,
p20 => p20, p21 => p21, p22 => p22,
matrix_dv => matrix_dv,
value_data => value_data,
value_dv => value_dv,
out_data => out_data,
out_fv => out_fv_s,
out_dv => out_dv,
enable_i => status_reg_enable_bit,
widthimg_i => widthimg_reg_width
);
process (clk_proc, reset_n, matrix_dv)
variable sum : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
begin
if(reset_n='0') then
enable_s <= '0';
prod_dv <= '0';
value_dv <= '0';
elsif(rising_edge(clk_proc)) then
if(in_fv = '0') then
w00 <= signed(w00_reg_m00);
w01 <= signed(w01_reg_m01);
w02 <= signed(w02_reg_m02);
w10 <= signed(w10_reg_m10);
w11 <= signed(w11_reg_m11);
w12 <= signed(w12_reg_m12);
w20 <= signed(w20_reg_m20);
w21 <= signed(w21_reg_m21);
w22 <= signed(w22_reg_m22);
norm <= norm_reg_norm;
enable_s <= status_reg_enable_bit;
prod_dv <= '0';
value_dv <= '0';
end if;
-- product calculation pipeline stage
prod_dv <= '0';
if(matrix_dv = '1' and enable_s = '1') then
prod00 <= w00 * signed('0' & p00);
prod01 <= w01 * signed('0' & p01);
prod02 <= w02 * signed('0' & p02);
prod10 <= w10 * signed('0' & p10);
prod11 <= w11 * signed('0' & p11);
prod12 <= w12 * signed('0' & p12);
prod20 <= w20 * signed('0' & p20);
prod21 <= w21 * signed('0' & p21);
prod22 <= w22 * signed('0' & p22);
prod_dv <= '1';
end if;
if(prod_dv='1' and enable_s = '1') then
sum := prod00 + prod01 + prod02 +
prod10 + prod11 + prod12 +
prod20 + prod21 + prod22;
if (sum(sum'left) = '1') then
sum := (others => '0');
end if;
value_data <= std_logic_vector(shift_right(unsigned(sum), to_integer(unsigned(norm)))(OUT_SIZE -1 downto 0));
value_dv <= '1';
else
value_dv <= '0';
end if;
end if;
end process;
out_fv <= enable_s and out_fv_s;
end rtl;
| gpl-3.0 | 0ec29a61b4ccb1fab171a21e683a7f81 | 0.501154 | 3.129995 | false | false | false | false |
DreamIP/GPStudio | support/io/mpu/hdl/mpu_acqui.vhd | 1 | 9,916 | --------------------------------------------------------------------------------------
-- The configuration settings choose by the user are read here. If a modification is
-- detected, a configuration is started with the new values.
-- This bloc generates the triggers to acquire data at the sample rate define by user.
--------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.mpu_pkg.all;
entity mpu_acqui is
port (
clk_proc : in std_logic;
reset : in std_logic;
sda : inout std_logic;
scl : inout std_logic;
AD0 : out std_logic;
parameters : in param;
accelero : out flow;
gyroscope : out flow;
compass : out flow
);
end mpu_acqui;
architecture RTL of mpu_acqui is
signal en : std_logic;
signal spl_rate : std_logic_vector(7 downto 0);
signal gyro_config : std_logic_vector(1 downto 0);
signal accel_config : std_logic_vector(1 downto 0);
signal gain_compass : std_logic_vector(2 downto 0);
signal freq_compass : std_logic_vector(2 downto 0);
signal trigger : std_logic;
signal config_button : std_logic;
signal wr_en : std_logic;
signal rd_en : std_logic;
signal rd_en_dl : std_logic;
signal data_fifo_in : std_logic_vector(7 downto 0);
signal count_fifo : std_logic_vector(5 downto 0);
signal wr_en_dl : std_logic;
signal wr_en_flag : std_logic;
signal reset_fifo_buffer: std_logic;
signal trigger_auto : std_logic;
signal config_change : std_logic;
signal en_dl : std_logic;
signal spl_rate_dl : std_logic_vector(7 downto 0);
signal gyro_config_dl : std_logic_vector(1 downto 0);
signal accel_config_dl : std_logic_vector(1 downto 0);
signal gain_compass_dl : std_logic_vector(2 downto 0);
signal freq_compass_dl : std_logic_vector(2 downto 0);
signal run_conf : std_logic;
signal not_reset : std_logic;
signal data_fifo_out : std_logic_vector(7 downto 0);
signal rd_accel,rd_gyro : std_logic;
signal rd_comp : std_logic;
signal count_rst_fifo : unsigned(3 downto 0);
signal count_param : integer range 0 TO 30_000_000;
signal spl_ratex2 : unsigned(8 downto 0);
signal COUNT_ONE_ACQUI : INTEGER RANGE 0 TO 30_000_000;
signal spl_rate_mpu : std_logic_vector(7 downto 0);
signal rd_fifo_count : std_logic;
signal rd_comp_dl : std_logic;
signal ready : std_logic;
signal rd_ready_f : std_logic;
signal fifo_mpu_count : std_logic_vector(15 downto 0);
signal fifo_mpu_res : unsigned(15 downto 0);
signal data_read : std_logic_vector(7 downto 0);
signal wr_en_fifo : std_logic;
begin
mpu_i2c_inst : entity work.mpu_i2c(behavioral) port map (
clk => clk_proc,
en => en,
reset_n => reset,
config_button => config_button,
trigger => trigger,
data_read => data_read,
fifo_wr_en => wr_en,
spl_rate => spl_rate_mpu,
gyro_config => gyro_config,
accel_config => accel_config,
gain_compass => gain_compass,
freq_compass => freq_compass,
reset_fifo_buffer => reset_fifo_buffer,
run_conf => run_conf,
rd_fifo_count => rd_fifo_count,
sda => sda,
scl => scl
);
mpu_fifo_inst_1 : entity work.mpu_fifo(syn) port map (
aclr => not_reset,
data => data_fifo_in,
rdclk => clk_proc,
rdreq => rd_en,
wrclk => clk_proc,
wrreq => wr_en_fifo,
q => data_fifo_out,
rdempty => open,
rdusedw => count_fifo,
wrfull => open
);
mpu_off_inst : entity work.offset_correction(RTL) port map (
clk => clk_proc,
reset => reset,
enable => en,
rd_fifo_count => rd_fifo_count,
parameters => parameters,
wr_en_flag => wr_en_flag,
wr_fifo => wr_en_fifo,
data_i => data_read,
data_o => data_fifo_in
);
------ Generates triggers in order to read data from mpu. Check the mpu internal FIFO count bytes between each trigger
process(clk_proc,reset)
begin
if reset='0' then
trigger_auto <= '0';
reset_fifo_buffer <= '0';
count_param <= 0;
count_rst_fifo <= x"0";
rd_fifo_count <= '0';
elsif clk_proc'event and clk_proc='1' then ----- Generates triggers for reading data from mpu
if en='1' then
if spl_rate <= x"0F" then
spl_rate_mpu <= x"84"; --60.15hz
elsif spl_rate <= x"1E" then
spl_rate_mpu <= x"57"; --90.9hz
elsif spl_rate <= x"3C" then
spl_rate_mpu <= x"34"; --150.9hz
else
spl_rate_mpu <= x"19";
end if;
if run_conf='0' then
count_param <= count_param + 1;
if count_param < COUNT_ONE_ACQUI-TRIGGER_OR_RST_FIFO_T then
rd_fifo_count <= '0';
if count_rst_fifo = x"1" then
trigger_auto <= '1';
reset_fifo_buffer <= '0';
else
trigger_auto <= '0';
reset_fifo_buffer <= '1';
end if;
elsif count_param <= COUNT_ONE_ACQUI-COUNT_FIFO_BYTES_T then
reset_fifo_buffer <= '0';
trigger_auto <= '0';
if count_rst_fifo=x"0" then
rd_fifo_count <= '1';
end if;
elsif count_param <= COUNT_ONE_ACQUI then
if count_param = COUNT_ONE_ACQUI then
count_rst_fifo <= count_rst_fifo+1;
count_param <= 0;
if count_rst_fifo = x"1" then
count_rst_fifo <= x"0";
end if;
end if;
end if;
else
count_rst_fifo <= x"0";
count_param <= 0;
trigger_auto <= '0';
reset_fifo_buffer <= '0';
rd_fifo_count <= '0';
end if;
else
count_rst_fifo <= x"0";
count_param <= 0;
trigger_auto <= '0';
reset_fifo_buffer <= '0';
rd_fifo_count <= '0';
end if;
end if;
end process;
------ Get the parameters set by user.
process(clk_proc,reset)
begin
if reset='0' then
spl_rate_dl <= x"00";
accel_config_dl <= "00";
gyro_config_dl <= "00";
gain_compass_dl <= "000";
freq_compass_dl <= "000";
en_dl <= '0';
elsif clk_proc'event and clk_proc='1' then
----- Assignation of the parameters
en <= parameters(0)(31);
spl_rate <= parameters(0)(30 downto 23);
gyro_config <= parameters(0)(22 downto 21);
accel_config <= parameters(0)(20 downto 19);
gain_compass <= parameters(0)(18 downto 16);
freq_compass <= parameters(0)(15 downto 13);
config_button <= config_change;
----- Keep data to detect a change on the configuration
spl_rate_dl <= spl_rate;
accel_config_dl <= accel_config;
gyro_config_dl <= gyro_config;
gain_compass_dl <= gain_compass;
freq_compass_dl <= freq_compass;
en_dl <= en;
end if;
end process;
------ Set Read and Write flags for the FIFO and set data_valid/flow_valid for each flow.
process(clk_proc,reset)
begin
if reset='0' then
rd_en_dl <= '0';
rd_en <= '0';
rd_accel <= '0';
rd_gyro <= '0';
rd_comp <= '0';
wr_en_dl <= '0';
wr_en_flag <= '0';
elsif clk_proc'event and clk_proc='1' then
wr_en_dl <= wr_en;
wr_en_flag <= wr_en and not wr_en_dl;
rd_en_dl <= rd_en;
rd_comp_dl <= rd_comp;
----- Reading FIFO and set data_valid and flow_valid for each flow
if rd_fifo_count='1' then
if count_fifo = "000010" then
rd_en <= '1';
elsif count_fifo = "000001" then
rd_en <= '0';
end if;
else
if rd_en='1' then
if count_fifo = "010100" then
rd_accel <= '1';
elsif count_fifo = "001111" then
rd_accel <= '0';
elsif count_fifo = "001101" then
rd_gyro <= '1';
elsif count_fifo = "000111" then
rd_comp <= '1';
rd_gyro <= '0';
elsif count_fifo = "000010" then
rd_en <= '0';
rd_gyro <= '0';
end if;
else
if count_fifo = "010100" then
rd_en <= '1';
elsif count_fifo = "000000" then
rd_comp <= '0';
end if;
end if;
end if;
end if;
end process;
------ After reading how many bytes are in the FIFO of the mpu, we look if there are only full samples.
------ If one sample is not full, then the data is not read (flag 'ready'=0).
process(clk_proc,reset)
begin
if reset = '0' then
ready <= '0';
fifo_mpu_res <= x"0000";
fifo_mpu_count <= x"0000";
elsif clk_proc'event and clk_proc = '1' then ----- Generate write enable flag for the FIFO
if rd_ready_f='1' then
fifo_mpu_count <= fifo_mpu_count(7 downto 0) & data_fifo_out;
else
fifo_mpu_res <= unsigned(fifo_mpu_count) rem 20;
end if;
if fifo_mpu_res=x"0000" then
ready <= '1';
else
ready <= '0';
end if;
end if;
end process;
AD0 <= AD0_value; -- For mpu i2c address
not_reset <= not reset; -- Fifo asynchronous reset
trigger <= trigger_auto when en='1' else '0'; -- Set trigger when enable
rd_ready_f <= rd_en_dl and rd_fifo_count and rd_en; -- Reading Fifo count bytes from mpu
----- Determine the time between each trigger
spl_ratex2 <= unsigned(spl_rate)&'0';
COUNT_ONE_ACQUI <= to_integer(clk_50M/spl_ratex2);
----- Detecting a modification of the configuration
config_change <= '1' when (spl_rate/=spl_rate_dl or gyro_config/=gyro_config_dl or accel_config/=accel_config_dl
or gain_compass/=gain_compass_dl or freq_compass/=freq_compass_dl) or en/=en_dl
else '0';
----- Set output flows
accelero.dv <= rd_accel and ready;
accelero.fv <= rd_accel and ready;
accelero.data <= data_fifo_out;
gyroscope.dv <= rd_gyro and ready;
gyroscope.fv <= rd_gyro and ready;
gyroscope.data <= data_fifo_out;
compass.dv <= rd_comp and rd_en_dl and ready;
compass.fv <= rd_comp and rd_en_dl and ready;
compass.data <= data_fifo_out;
end RTL;
| gpl-3.0 | ee0a837e0cd6411778c3c23774e58e1e | 0.578257 | 2.758275 | false | true | false | false |
ou-cse-378/vhdl-tetris | reg2.vhd | 1 | 1,168 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: reg2.vhd
-- // Date: 12/9/2004
-- // Description: n line register
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg2 is
generic(width: positive);
port (
d : in STD_LOGIC_VECTOR (width-1 downto 0);
load : in STD_LOGIC;
dec : in STD_LOGIC;
clr : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (width-1 downto 0)
);
end reg2;
architecture reg2_arch of reg2 is
signal temp : std_logic_vector (width-1 downto 0);
begin
process(clk, clr)
begin
if clr = '1' then
for i in width-1 downto 0 loop
q(i) <= '0';
end loop;
elsif (clk'event and clk = '1') then
if load = '1' then
temp <= d;
elsif dec = '1' then
temp <= temp - '1' ;
end if;
end if;
q <= temp;
end process;
end reg2_arch;
| mit | d472b9998f99999fdf8944a165c0df9e | 0.482877 | 3.486567 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/niosII_microc_lab1.vhd | 1 | 12,190 | -- Nancy Minderman
-- [email protected]
-- This file makes extensive use of Altera template structures.
-- This file is the top-level file for lab 1 winter 2014 for version 12.1sp1 on Windows 7
-- A library clause declares a name as a library. It
-- does not create the library; it simply forward declares
-- it.
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
-- SIGNED and UNSIGNED types, and relevant functions
use ieee.numeric_std.all;
-- Basic sequential functions and concurrent procedures
use ieee.VITAL_Primitives.all;
use work.DE2_CONSTANTS.all;
entity niosII_microc_lab1 is
port
(
-- Input ports and 50 MHz Clock
KEY : in std_logic_vector (0 downto 0);
SW : in std_logic_vector (0 downto 0);
CLOCK_50 : in std_logic;
-- Green leds on board
LEDG : out DE2_LED_GREEN;
-- LCD on board
LCD_BLON : out std_logic;
LCD_ON : out std_logic;
LCD_DATA : inout DE2_LCD_DATA_BUS;
LCD_RS : out std_logic;
LCD_EN : out std_logic;
LCD_RW : out std_logic;
-- SDRAM on board
--DRAM_ADDR : out std_logic_vector (11 downto 0);
DRAM_ADDR : out DE2_SDRAM_ADDR_BUS;
DRAM_BA_0 : out std_logic;
DRAM_BA_1 : out std_logic;
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
--DRAM_DQ : inout std_logic_vector (15 downto 0);
DRAM_DQ : inout DE2_SDRAM_DATA_BUS;
DRAM_LDQM : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
-- SRAM on board
SRAM_ADDR : out DE2_SRAM_ADDR_BUS;
SRAM_DQ : inout DE2_SRAM_DATA_BUS;
SRAM_WE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
SRAM_CE_N : out std_logic;
-- VGA Controller
VGA_R : OUT STD_LOGIC_VECTOR (9 downto 0);
VGA_B : OUT STD_LOGIC_VECTOR (9 downto 0);
VGA_G : OUT STD_LOGIC_VECTOR (9 downto 0);
VGA_CLK: OUT STD_LOGIC;
VGA_BLANK: OUT STD_LOGIC;
VGA_HS: OUT STD_LOGIC;
VGA_VS: OUT STD_LOGIC;
VGA_SYNC: OUT STD_LOGIC;
I2C_SDAT : inout std_logic := 'X'; -- SDAT
I2C_SCLK : out std_logic;
TD_CLK27 : in std_logic := 'X'; -- TD_CLK27
TD_DATA : in std_logic_vector(7 downto 0) := (others => 'X'); -- TD_DATA
TD_HS : in std_logic := 'X'; -- TD_HS
TD_VS : in std_logic := 'X'; -- TD_VS
TD_RESET : out std_logic -- TD_RESET
--overflow_flag_from_the_Video_In_Decoder : out std_logic
);
end niosII_microc_lab1;
architecture structure of niosII_microc_lab1 is
-- Declarations (optional)
component video_sys is
port (
VGA_CLK_from_the_VGA_Controller : out std_logic; -- CLK
VGA_HS_from_the_VGA_Controller : out std_logic; -- HS
VGA_VS_from_the_VGA_Controller : out std_logic; -- VS
VGA_BLANK_from_the_VGA_Controller : out std_logic; -- BLANK
VGA_SYNC_from_the_VGA_Controller : out std_logic; -- SYNC
VGA_R_from_the_VGA_Controller : out std_logic_vector(9 downto 0); -- R
VGA_G_from_the_VGA_Controller : out std_logic_vector(9 downto 0); -- G
VGA_B_from_the_VGA_Controller : out std_logic_vector(9 downto 0); -- B
clk_0 : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
I2C_SDAT_to_and_from_the_AV_Config : inout std_logic := 'X'; -- SDAT
I2C_SCLK_from_the_AV_Config : out std_logic; -- SCLK
SRAM_DQ_to_and_from_the_Pixel_Buffer : inout DE2_SRAM_DATA_BUS := (others => 'X'); -- DQ
SRAM_ADDR_from_the_Pixel_Buffer : out DE2_SRAM_ADDR_BUS; -- ADDR
SRAM_LB_N_from_the_Pixel_Buffer : out std_logic; -- LB_N
SRAM_UB_N_from_the_Pixel_Buffer : out std_logic; -- UB_N
SRAM_CE_N_from_the_Pixel_Buffer : out std_logic; -- CE_N
SRAM_OE_N_from_the_Pixel_Buffer : out std_logic; -- OE_N
SRAM_WE_N_from_the_Pixel_Buffer : out std_logic; -- WE_N
TD_CLK27_to_the_Video_In_Decoder : in std_logic := 'X'; -- TD_CLK27
TD_DATA_to_the_Video_In_Decoder : in std_logic_vector(7 downto 0) := (others => 'X'); -- TD_DATA
TD_HS_to_the_Video_In_Decoder : in std_logic := 'X'; -- TD_HS
TD_VS_to_the_Video_In_Decoder : in std_logic := 'X'; -- TD_VS
TD_RESET_from_the_Video_In_Decoder : out std_logic; -- TD_RESET
--overflow_flag_from_the_Video_In_Decoder : out std_logic -- overflow_flag
sdram_0_wire_addr : out DE2_SDRAM_ADDR_BUS; -- addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_0_wire_cas_n : out std_logic; -- cas_n
sdram_0_wire_cke : out std_logic; -- cke
sdram_0_wire_cs_n : out std_logic; -- cs_n
sdram_0_wire_dq : inout DE2_SDRAM_DATA_BUS := (others => 'X'); -- dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_0_wire_ras_n : out std_logic; -- ras_n
sdram_0_wire_we_n : out std_logic;
clock_signals_sdram_clk_clk : out std_logic;
led_external_connection_export : out DE2_LED_GREEN
);
end component video_sys;
-- These signals are for matching the provided IP core to
-- The specific SDRAM chip in our system
signal BA : std_logic_vector (1 downto 0);
signal DQM : std_logic_vector (1 downto 0);
begin
DRAM_BA_1 <= BA(1);
DRAM_BA_0 <= BA(0);
DRAM_UDQM <= DQM(1);
DRAM_LDQM <= DQM(0);
-- Component Instantiation Statement (optional)
u0 : component video_sys
port map (
VGA_CLK_from_the_VGA_Controller => VGA_CLK, -- VGA_Controller_external_interface.CLK
VGA_HS_from_the_VGA_Controller => VGA_HS, -- .HS
VGA_VS_from_the_VGA_Controller => VGA_VS, -- .VS
VGA_BLANK_from_the_VGA_Controller => VGA_BLANK, -- .BLANK
VGA_SYNC_from_the_VGA_Controller => VGA_SYNC, -- .SYNC
VGA_R_from_the_VGA_Controller => VGA_R, -- .R
VGA_G_from_the_VGA_Controller => VGA_G, -- .G
VGA_B_from_the_VGA_Controller => VGA_B, -- .B
clk_0 => CLOCK_50, -- clk_0_clk_in.clk
reset_n => KEY(0), -- clk_0_clk_in_reset.reset_n
I2C_SDAT_to_and_from_the_AV_Config => I2C_SDAT, -- AV_Config_external_interface.SDAT
I2C_SCLK_from_the_AV_Config => I2C_SCLK, -- .SCLK
SRAM_DQ_to_and_from_the_Pixel_Buffer => SRAM_DQ, -- Pixel_Buffer_external_interface.DQ
SRAM_ADDR_from_the_Pixel_Buffer => SRAM_ADDR, -- .ADDR
SRAM_LB_N_from_the_Pixel_Buffer => SRAM_LB_N, -- .LB_N
SRAM_UB_N_from_the_Pixel_Buffer => SRAM_UB_N, -- .UB_N
SRAM_CE_N_from_the_Pixel_Buffer => SRAM_CE_N, -- .CE_N
SRAM_OE_N_from_the_Pixel_Buffer => SRAM_OE_N, -- .OE_N
SRAM_WE_N_from_the_Pixel_Buffer => SRAM_WE_N, -- .WE_N
TD_CLK27_to_the_Video_In_Decoder => TD_CLK27, -- Video_In_Decoder_external_interface.TD_CLK27
TD_DATA_to_the_Video_In_Decoder => TD_DATA, -- .TD_DATA
TD_HS_to_the_Video_In_Decoder => TD_HS, -- .TD_HS
TD_VS_to_the_Video_In_Decoder => TD_VS, -- .TD_VS
TD_RESET_from_the_Video_In_Decoder => TD_RESET, -- .TD_RESET
--overflow_flag_from_the_Video_In_Decoder => overflow_flag -- .overflow_flag
sdram_0_wire_addr => DRAM_ADDR, -- sdram_0_wire.addr
sdram_0_wire_ba => BA, -- .ba
sdram_0_wire_cas_n => DRAM_CAS_N, -- .cas_n
sdram_0_wire_cke => DRAM_CKE, -- .cke
sdram_0_wire_cs_n => DRAM_CS_N, -- .cs_n
sdram_0_wire_dq => DRAM_DQ, -- .dq
sdram_0_wire_dqm => DQM, -- .dqm
sdram_0_wire_ras_n => DRAM_RAS_N, -- .ras_n
sdram_0_wire_we_n => DRAM_WE_N,
clock_signals_sdram_clk_clk => DRAM_CLK,
led_external_connection_export => LEDG
);
end structure;
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
package DE2_CONSTANTS is
type DE2_SDRAM_ADDR_BUS is array(11 downto 0) of std_logic;
type DE2_SDRAM_DATA_BUS is array(15 downto 0) of std_logic;
type DE2_LCD_DATA_BUS is array(7 downto 0) of std_logic;
type DE2_LED_GREEN is array(7 downto 0) of std_logic;
type DE2_SRAM_ADDR_BUS is array(17 downto 0) of std_logic;
type DE2_SRAM_DATA_BUS is array(15 downto 0) of std_logic;
end DE2_CONSTANTS;
| gpl-2.0 | 9b412bb93957fd376584b88c7ce2d8a9 | 0.420509 | 3.773994 | false | false | false | false |
DreamIP/GPStudio | support/component/gp_fifo/hdl/tb/tb_gp_fifo.vhd | 1 | 3,389 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library ALTERA_MF;
use ALTERA_MF.all;
entity tb_fifo is
end tb_fifo;
architecture sim of tb_fifo is
---------------------------------------------------------
-- CONSTANTS
---------------------------------------------------------
constant FIFO_DEPTH_CONST : positive:=4;
constant DATA_WIDTH_CONST : positive:=8;
---------------------------------------------------------
-- SIGNALS
---------------------------------------------------------
signal clk_s : std_logic;
signal reset_n_s : std_logic;
signal data_wr_s : std_logic;
signal data_in_s : std_logic_vector(DATA_WIDTH_CONST-1 downto 0);
signal full_s : std_logic;
signal data_rd_s : std_logic;
signal data_ou_s : std_logic_vector(DATA_WIDTH_CONST-1 downto 0);
signal empty_s : std_logic;
---------------------------------------------------------
-- C.U.T
---------------------------------------------------------
component gp_fifo
generic (
DATA_WIDTH : positive;
FIFO_DEPTH : positive
);
port (
clk : in std_logic;
reset_n : in std_logic;
data_wr : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
full : out std_logic;
data_rd : in std_logic;
data_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
empty : out std_logic
);
end component;
begin
---------------------------------------------------------
-- C.U.T INSTANSTATION
---------------------------------------------------------
gp_fifo_inst : gp_fifo
generic map(
DATA_WIDTH => DATA_WIDTH_CONST,
FIFO_DEPTH => FIFO_DEPTH_CONST
)
port map(
clk => clk_s,
reset_n => reset_n_s,
data_wr => data_wr_s,
data_in => data_in_s,
full => full_s,
data_rd => data_rd_s,
data_out => data_ou_s,
empty => empty_s
);
---------------------------------------------------------
-- STIMULUS
---------------------------------------------------------
-- Clock
clk_stim : process
begin
clk_s <= '1';
wait for 20 ns;
clk_s <= '0';
wait for 20 ns;
end process;
-- Initial Reset
init_reset : process
begin
reset_n_s <= '0' ;
wait for 50 ns ;
reset_n_s <= '1' ;
wait for 340 ns;
end process;
-- Write in FIFO stimulus
dw_stim : process
begin
data_wr_s <= '0';
wait for 60 ns;
data_wr_s <= '1';
wait for 40 ns;
data_wr_s <= '0';
wait for 20 ns;
data_wr_s <= '1';
wait for 60 ns;
data_wr_s <= '0';
wait for 20 ns;
data_wr_s <= '1';
wait for 40 ns;
data_wr_s <= '0';
wait for 60 ns;
end process;
-- Read From FIFO simulus
rd_stim : process
begin
data_rd_s <= '0';
wait for 160 ns;
data_rd_s <= '1';
wait for 40 ns;
data_rd_s <= '0';
wait for 20 ns;
data_rd_s <= '1';
wait for 60 ns;
data_rd_s <= '0';
wait for 20 ns;
data_rd_s <= '1';
wait for 40 ns;
end process;
-- In data stimulus
data_stim : process
variable i : integer := 0;
begin
for i in 1 to 100 loop
data_in_s <= std_logic_vector(to_unsigned(i,DATA_WIDTH_CONST));
wait for 20 ns;
end loop;
end process;
end architecture;
| gpl-3.0 | faf9e3115fbe06f87a40618361c26f08 | 0.44851 | 3.075318 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/boards/terasic-de2i-150/common/ipcore/pll/pll.vhd | 5 | 19,403 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire8_bv(0 DOWNTO 0) <= "0";
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
sub_wire5 <= sub_wire0(2);
sub_wire4 <= sub_wire0(0);
sub_wire2 <= sub_wire0(3);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c3 <= sub_wire2;
locked <= sub_wire3;
c0 <= sub_wire4;
c2 <= sub_wire5;
sub_wire6 <= inclk0;
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
clk2_divide_by => 2,
clk2_duty_cycle => 50,
clk2_multiply_by => 5,
clk2_phase_shift => "0",
clk3_divide_by => 2,
clk3_duty_cycle => 50,
clk3_multiply_by => 1,
clk3_phase_shift => "0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV GX",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NO_COMPENSATION",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire7,
clk => sub_wire0,
locked => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "2"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "2"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "125.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "25.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "5"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "125.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-2.0 | 827da55f6c770e31985dadf94664092e | 0.700407 | 3.268699 | false | false | false | false |
ou-cse-378/vhdl-tetris | seg7dec.vhd | 1 | 1,409 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: seg7dec
-- // Date: 12/9/2004
-- // Description: Display Component
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity seg7dec is
port (
q : in STD_LOGIC_VECTOR(3 downto 0);
AtoG : out STD_LOGIC_VECTOR(6 downto 0));
end seg7dec;
architecture seg7dec_arch of seg7dec is
begin
process(q)
begin
case q is
when "0000" => AtoG <= "0000001";
when "0001" => AtoG <= "1001111";
when "0010" => AtoG <= "0010010";
when "0011" => AtoG <= "0000110";
when "0100" => AtoG <= "1001100";
when "0101" => AtoG <= "0100100";
when "0110" => AtoG <= "0100000";
when "0111" => AtoG <= "0001101";
when "1000" => AtoG <= "0000000";
when "1001" => AtoG <= "0000100";
when "1010" => AtoG <= "0001000";
when "1011" => AtoG <= "1100000";
when "1100" => AtoG <= "0110001";
when "1101" => AtoG <= "1000010";
when "1110" => AtoG <= "0110000";
when others => AtoG <= "0111000";
end case;
end process;
end seg7dec_arch;
| mit | 7629b599005d836b4580527419b78fc9 | 0.433641 | 3.935754 | false | false | false | false |
bpervan/simple-soc | pcores/uart_cntrl_v1_00_a/hdl/vhdl/BaudRateGenerator.vhd | 1 | 1,381 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:25 03/11/2014
-- Design Name:
-- Module Name: BaudRateGenerator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BaudRateGenerator is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
tick : out STD_LOGIC);
end BaudRateGenerator;
architecture Behavioral of BaudRateGenerator is
signal brojac, brojacNext : unsigned (9 downto 0);
begin
process (clk, rst)
begin
if(rst = '0') then
brojac <= "0000000000";
else
if (clk'event and clk = '1') then
brojac <= brojacNext;
end if;
end if;
end process;
brojacNext <= "0000000000" when brojac = 651 else
brojac + 1;
tick <= '1' when brojac = 651 else '0';
end Behavioral;
| mit | e280bec74327ec0b10b4a5ce6bfdbae4 | 0.5916 | 3.762943 | false | false | false | false |
hoglet67/ElectronFpga | src/common/MC6522/m6522.vhd | 1 | 28,662 | --
-- A simulation model of VIC20 hardware
-- Copyright (c) MikeJ - March 2003
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email [email protected]
--
--
-- Revision list
--
-- version 004 fixes to PB7 T1 control and Mode 0 Shift Register operation
-- version 003 fix reset of T1/T2 IFR flags if T1/T2 is reload via reg5/reg9 from wolfgang (WoS)
-- Ported to numeric_std and simulation fix for signal initializations from arnim laeuger
-- version 002 fix from Mark McDougall, untested
-- version 001 initial release
-- not very sure about the shift register, documentation is a bit light.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity M6522 is
port (
I_RS : in std_logic_vector(3 downto 0);
I_DATA : in std_logic_vector(7 downto 0);
O_DATA : out std_logic_vector(7 downto 0);
O_DATA_OE_L : out std_logic;
I_RW_L : in std_logic;
I_CS1 : in std_logic;
I_CS2_L : in std_logic;
O_IRQ_L : out std_logic; -- note, not open drain
-- port a
I_CA1 : in std_logic;
I_CA2 : in std_logic;
O_CA2 : out std_logic;
O_CA2_OE_L : out std_logic;
I_PA : in std_logic_vector(7 downto 0);
O_PA : out std_logic_vector(7 downto 0);
O_PA_OE_L : out std_logic_vector(7 downto 0);
-- port b
I_CB1 : in std_logic;
O_CB1 : out std_logic;
O_CB1_OE_L : out std_logic;
I_CB2 : in std_logic;
O_CB2 : out std_logic;
O_CB2_OE_L : out std_logic;
I_PB : in std_logic_vector(7 downto 0);
O_PB : out std_logic_vector(7 downto 0);
O_PB_OE_L : out std_logic_vector(7 downto 0);
I_P2_H : in std_logic; -- high for phase 2 clock ____----__
RESET_L : in std_logic;
ENA_4 : in std_logic; -- clk enable
CLK : in std_logic
);
end;
architecture RTL of M6522 is
signal phase : std_logic_vector(1 downto 0):="00";
signal p2_h_t1 : std_logic;
signal cs : std_logic;
-- registers
signal r_ddra : std_logic_vector(7 downto 0);
signal r_ora : std_logic_vector(7 downto 0);
signal r_ira : std_logic_vector(7 downto 0);
signal r_ddrb : std_logic_vector(7 downto 0);
signal r_orb : std_logic_vector(7 downto 0);
signal r_irb : std_logic_vector(7 downto 0);
signal r_t1l_l : std_logic_vector(7 downto 0);
signal r_t1l_h : std_logic_vector(7 downto 0);
signal r_t2l_l : std_logic_vector(7 downto 0);
signal r_t2l_h : std_logic_vector(7 downto 0); -- not in real chip
signal r_sr : std_logic_vector(7 downto 0);
signal r_acr : std_logic_vector(7 downto 0);
signal r_pcr : std_logic_vector(7 downto 0);
signal r_ifr : std_logic_vector(7 downto 0);
signal r_ier : std_logic_vector(6 downto 0);
signal sr_write_ena : boolean;
signal sr_read_ena : boolean;
signal ifr_write_ena : boolean;
signal ier_write_ena : boolean;
signal clear_irq : std_logic_vector(7 downto 0);
signal load_data : std_logic_vector(7 downto 0);
-- timer 1
signal t1c : std_logic_vector(15 downto 0) := (others => '1'); -- simulators may not catch up w/o init here...
signal t1c_active : boolean;
signal t1c_done : boolean;
signal t1_w_reset_int : boolean;
signal t1_r_reset_int : boolean;
signal t1_load_counter : boolean;
signal t1_reload_counter : boolean;
signal t1_toggle : std_logic;
signal t1_irq : std_logic := '0';
-- timer 2
signal t2c : std_logic_vector(15 downto 0) := (others => '1'); -- simulators may not catch up w/o init here...
signal t2c_active : boolean;
signal t2c_done : boolean;
signal t2_pb6 : std_logic;
signal t2_pb6_t1 : std_logic;
signal t2_w_reset_int : boolean;
signal t2_r_reset_int : boolean;
signal t2_load_counter : boolean;
signal t2_reload_counter : boolean;
signal t2_irq : std_logic := '0';
signal t2_sr_ena : boolean;
-- shift reg
signal sr_cnt : std_logic_vector(3 downto 0);
signal sr_cb1_oe_l : std_logic;
signal sr_cb1_out : std_logic;
signal sr_drive_cb2 : std_logic;
signal sr_strobe : std_logic;
signal sr_strobe_t1 : std_logic;
signal sr_strobe_falling : boolean;
signal sr_strobe_rising : boolean;
signal sr_irq : std_logic;
signal sr_out : std_logic;
signal sr_off_delay : std_logic;
-- io
signal w_orb_hs : std_logic;
signal w_ora_hs : std_logic;
signal r_irb_hs : std_logic;
signal r_ira_hs : std_logic;
signal ca_hs_sr : std_logic;
signal ca_hs_pulse : std_logic;
signal cb_hs_sr : std_logic;
signal cb_hs_pulse : std_logic;
signal cb1_in_mux : std_logic;
signal ca1_ip_reg : std_logic;
signal cb1_ip_reg : std_logic;
signal ca1_int : boolean;
signal cb1_int : boolean;
signal ca1_irq : std_logic;
signal cb1_irq : std_logic;
signal ca2_ip_reg : std_logic;
signal cb2_ip_reg : std_logic;
signal ca2_int : boolean;
signal cb2_int : boolean;
signal ca2_irq : std_logic;
signal cb2_irq : std_logic;
signal final_irq : std_logic;
begin
p_phase : process
begin
-- internal clock phase
wait until rising_edge(CLK);
if (ENA_4 = '1') then
p2_h_t1 <= I_P2_H;
if (p2_h_t1 = '0') and (I_P2_H = '1') then
phase <= "11";
else
phase <= phase + "1";
end if;
end if;
end process;
p_cs : process(I_CS1, I_CS2_L, I_P2_H)
begin
cs <= '0';
if (I_CS1 = '1') and (I_CS2_L = '0') and (I_P2_H = '1') then
cs <= '1';
end if;
end process;
-- peripheral control reg (pcr)
-- 0 ca1 interrupt control (0 +ve edge, 1 -ve edge)
-- 3..1 ca2 operation
-- 000 input -ve edge
-- 001 independend interrupt input -ve edge
-- 010 input +ve edge
-- 011 independend interrupt input +ve edge
-- 100 handshake output
-- 101 pulse output
-- 110 low output
-- 111 high output
-- 7..4 as 3..0 for cb1,cb2
-- auxiliary control reg (acr)
-- 0 input latch PA (0 disable, 1 enable)
-- 1 input latch PB (0 disable, 1 enable)
-- 4..2 shift reg control
-- 000 disable
-- 001 shift in using t2
-- 010 shift in using o2
-- 011 shift in using ext clk
-- 100 shift out free running t2 rate
-- 101 shift out using t2
-- 101 shift out using o2
-- 101 shift out using ext clk
-- 5 t2 timer control (0 timed interrupt, 1 count down with pulses on pb6)
-- 7..6 t1 timer control
-- 00 timed interrupt each time t1 is loaded pb7 disable
-- 01 continuous interrupts pb7 disable
-- 00 timed interrupt each time t1 is loaded pb7 one shot output
-- 01 continuous interrupts pb7 square wave output
--
p_write_reg_reset : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
r_ora <= x"00"; r_orb <= x"00";
r_ddra <= x"00"; r_ddrb <= x"00";
r_acr <= x"00"; r_pcr <= x"00";
w_orb_hs <= '0';
w_ora_hs <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
w_orb_hs <= '0';
w_ora_hs <= '0';
if (cs = '1') and (I_RW_L = '0') then
case I_RS is
when x"0" => r_orb <= I_DATA; w_orb_hs <= '1';
when x"1" => r_ora <= I_DATA; w_ora_hs <= '1';
when x"2" => r_ddrb <= I_DATA;
when x"3" => r_ddra <= I_DATA;
when x"B" => r_acr <= I_DATA;
when x"C" => r_pcr <= I_DATA;
when x"F" => r_ora <= I_DATA;
when others => null;
end case;
end if;
if r_acr(7) = '1' then
-- DMB: Forgetting to clear B7 broke Acornsoft Planetoid
if t1_load_counter then
r_orb(7) <= '0'; -- writing T1C-H resets bit 7
elsif t1_toggle = '1' then
r_orb(7) <= not r_orb(7); -- toggle
end if;
end if;
end if;
end if;
end process;
p_write_reg : process (RESET_L, CLK) is
begin
if (RESET_L = '0') then
-- The spec says, this is not reset.
-- Fact is that the 1541 VIA1 timer won't work,
-- as the firmware ONLY sets the r_t1l_h latch!!!!
r_t1l_l <= (others => '0');
r_t1l_h <= (others => '0');
r_t2l_l <= (others => '0');
r_t2l_h <= (others => '0');
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
t1_w_reset_int <= false;
t1_load_counter <= false;
t2_w_reset_int <= false;
t2_load_counter <= false;
load_data <= x"00";
sr_write_ena <= false;
ifr_write_ena <= false;
ier_write_ena <= false;
if (cs = '1') and (I_RW_L = '0') then
load_data <= I_DATA;
case I_RS is
when x"4" => r_t1l_l <= I_DATA;
when x"5" => r_t1l_h <= I_DATA; t1_w_reset_int <= true;
t1_load_counter <= true;
when x"6" => r_t1l_l <= I_DATA;
when x"7" => r_t1l_h <= I_DATA; t1_w_reset_int <= true;
when x"8" => r_t2l_l <= I_DATA;
when x"9" => r_t2l_h <= I_DATA; t2_w_reset_int <= true;
t2_load_counter <= true;
when x"A" => sr_write_ena <= true;
when x"D" => ifr_write_ena <= true;
when x"E" => ier_write_ena <= true;
when others => null;
end case;
end if;
end if;
end if;
end process;
p_oe : process(cs, I_RW_L)
begin
O_DATA_OE_L <= '1';
if (cs = '1') and (I_RW_L = '1') then
O_DATA_OE_L <= '0';
end if;
end process;
p_read : process(cs, I_RW_L, I_RS, r_irb, r_ira, r_ddrb, r_ddra, t1c, r_t1l_l,
r_t1l_h, t2c, r_sr, r_acr, r_pcr, r_ifr, r_ier, r_orb)
begin
t1_r_reset_int <= false;
t2_r_reset_int <= false;
sr_read_ena <= false;
r_irb_hs <= '0';
r_ira_hs <= '0';
O_DATA <= x"00"; -- default
if (cs = '1') and (I_RW_L = '1') then
case I_RS is
--when x"0" => O_DATA <= r_irb; r_irb_hs <= '1';
-- fix from Mark McDougall, untested
when x"0" => O_DATA <= (r_irb and not r_ddrb) or (r_orb and r_ddrb); r_irb_hs <= '1';
when x"1" => O_DATA <= r_ira; r_ira_hs <= '1';
when x"2" => O_DATA <= r_ddrb;
when x"3" => O_DATA <= r_ddra;
when x"4" => O_DATA <= t1c( 7 downto 0); t1_r_reset_int <= true;
when x"5" => O_DATA <= t1c(15 downto 8);
when x"6" => O_DATA <= r_t1l_l;
when x"7" => O_DATA <= r_t1l_h;
when x"8" => O_DATA <= t2c( 7 downto 0); t2_r_reset_int <= true;
when x"9" => O_DATA <= t2c(15 downto 8);
when x"A" => O_DATA <= r_sr; sr_read_ena <= true;
when x"B" => O_DATA <= r_acr;
when x"C" => O_DATA <= r_pcr;
when x"D" => O_DATA <= r_ifr;
when x"E" => O_DATA <= ('0' & r_ier);
when x"F" => O_DATA <= r_ira;
when others => null;
end case;
end if;
end process;
--
-- IO
--
p_ca1_cb1_sel : process(sr_cb1_oe_l, sr_cb1_out, I_CB1)
begin
-- if the shift register is enabled, cb1 may be an output
-- in this case, we should listen to the CB1_OUT for the interrupt
if (sr_cb1_oe_l = '1') then
cb1_in_mux <= I_CB1;
else
cb1_in_mux <= sr_cb1_out;
end if;
end process;
p_ca1_cb1_int : process(r_pcr, ca1_ip_reg, I_CA1, cb1_ip_reg, cb1_in_mux)
begin
if (r_pcr(0) = '0') then -- ca1 control
-- negative edge
ca1_int <= (ca1_ip_reg = '1') and (I_CA1 = '0');
else
-- positive edge
ca1_int <= (ca1_ip_reg = '0') and (I_CA1 = '1');
end if;
if (r_pcr(4) = '0') then -- cb1 control
-- negative edge
cb1_int <= (cb1_ip_reg = '1') and (cb1_in_mux = '0');
else
-- positive edge
cb1_int <= (cb1_ip_reg = '0') and (cb1_in_mux = '1');
end if;
end process;
p_ca2_cb2_int : process(r_pcr, ca2_ip_reg, I_CA2, cb2_ip_reg, I_CB2)
begin
ca2_int <= false;
if (r_pcr(3) = '0') then -- ca2 input
if (r_pcr(2) = '0') then -- ca2 edge
-- negative edge
ca2_int <= (ca2_ip_reg = '1') and (I_CA2 = '0');
else
-- positive edge
ca2_int <= (ca2_ip_reg = '0') and (I_CA2 = '1');
end if;
end if;
cb2_int <= false;
if (r_pcr(7) = '0') then -- cb2 input
if (r_pcr(6) = '0') then -- cb2 edge
-- negative edge
cb2_int <= (cb2_ip_reg = '1') and (I_CB2 = '0');
else
-- positive edge
cb2_int <= (cb2_ip_reg = '0') and (I_CB2 = '1');
end if;
end if;
end process;
p_ca2_cb2 : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
O_CA2 <= '0';
O_CA2_OE_L <= '1';
O_CB2 <= '0';
O_CB2_OE_L <= '1';
ca_hs_sr <= '0';
ca_hs_pulse <= '0';
cb_hs_sr <= '0';
cb_hs_pulse <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- ca
if (phase = "00") and ((w_ora_hs = '1') or (r_ira_hs = '1')) then
ca_hs_sr <= '1';
elsif ca1_int then
ca_hs_sr <= '0';
end if;
if (phase = "00") then
ca_hs_pulse <= w_ora_hs or r_ira_hs;
end if;
O_CA2_OE_L <= not r_pcr(3); -- ca2 output
case r_pcr(3 downto 1) is
when "000" => O_CA2 <= '0'; -- input
when "001" => O_CA2 <= '0'; -- input
when "010" => O_CA2 <= '0'; -- input
when "011" => O_CA2 <= '0'; -- input
when "100" => O_CA2 <= not (ca_hs_sr); -- handshake
when "101" => O_CA2 <= not (ca_hs_pulse); -- pulse
when "110" => O_CA2 <= '0'; -- low
when "111" => O_CA2 <= '1'; -- high
when others => null;
end case;
-- cb
if (phase = "00") and (w_orb_hs = '1') then
cb_hs_sr <= '1';
elsif cb1_int then
cb_hs_sr <= '0';
end if;
if (phase = "00") then
cb_hs_pulse <= w_orb_hs;
end if;
O_CB2_OE_L <= not (r_pcr(7) or sr_drive_cb2); -- cb2 output or serial
if (sr_drive_cb2 = '1') then -- serial output
O_CB2 <= sr_out;
else
case r_pcr(7 downto 5) is
when "000" => O_CB2 <= '0'; -- input
when "001" => O_CB2 <= '0'; -- input
when "010" => O_CB2 <= '0'; -- input
when "011" => O_CB2 <= '0'; -- input
when "100" => O_CB2 <= not (cb_hs_sr); -- handshake
when "101" => O_CB2 <= not (cb_hs_pulse); -- pulse
when "110" => O_CB2 <= '0'; -- low
when "111" => O_CB2 <= '1'; -- high
when others => null;
end case;
end if;
end if;
end if;
end process;
O_CB1 <= sr_cb1_out;
O_CB1_OE_L <= sr_cb1_oe_l;
p_ca_cb_irq : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
ca1_irq <= '0';
ca2_irq <= '0';
cb1_irq <= '0';
cb2_irq <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- not pretty
if ca1_int then
ca1_irq <= '1';
elsif (r_ira_hs = '1') or (w_ora_hs = '1') or (clear_irq(1) = '1') then
ca1_irq <= '0';
end if;
if ca2_int then
ca2_irq <= '1';
else
if (((r_ira_hs = '1') or (w_ora_hs = '1')) and (r_pcr(1) = '0')) or
(clear_irq(0) = '1') then
ca2_irq <= '0';
end if;
end if;
if cb1_int then
cb1_irq <= '1';
elsif (r_irb_hs = '1') or (w_orb_hs = '1') or (clear_irq(4) = '1') then
cb1_irq <= '0';
end if;
if cb2_int then
cb2_irq <= '1';
else
if (((r_irb_hs = '1') or (w_orb_hs = '1')) and (r_pcr(5) = '0')) or
(clear_irq(3) = '1') then
cb2_irq <= '0';
end if;
end if;
end if;
end if;
end process;
p_input_reg : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
ca1_ip_reg <= '0';
cb1_ip_reg <= '0';
ca2_ip_reg <= '0';
cb2_ip_reg <= '0';
r_ira <= x"00";
r_irb <= x"00";
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- we have a fast clock, so we can have input registers
ca1_ip_reg <= I_CA1;
cb1_ip_reg <= cb1_in_mux;
ca2_ip_reg <= I_CA2;
cb2_ip_reg <= I_CB2;
if (r_acr(0) = '0') then
r_ira <= I_PA;
else -- enable latching
if ca1_int then
r_ira <= I_PA;
end if;
end if;
if (r_acr(1) = '0') then
r_irb <= I_PB;
else -- enable latching
if cb1_int then
r_irb <= I_PB;
end if;
end if;
end if;
end if;
end process;
p_buffers : process(r_ddra, r_ora, r_ddrb, r_acr, r_orb)
begin
-- data direction reg (ddr) 0 = input, 1 = output
O_PA <= r_ora;
O_PA_OE_L <= not r_ddra;
if (r_acr(7) = '1') then -- not clear if r_ddrb(7) must be 1 as well
O_PB_OE_L(7) <= '0'; -- an output if under t1 control
else
O_PB_OE_L(7) <= not (r_ddrb(7));
end if;
O_PB_OE_L(6 downto 0) <= not r_ddrb(6 downto 0);
O_PB(7 downto 0) <= r_orb(7 downto 0);
end process;
--
-- Timer 1
--
p_timer1_done : process
variable done : boolean;
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
done := (t1c = x"0000");
t1c_done <= done and (phase = "11");
if (phase = "11") then
t1_reload_counter <= done and (r_acr(6) = '1');
end if;
if t1_load_counter then -- done reset on load!
t1c_done <= false;
end if;
end if;
end process;
p_timer1 : process
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
if t1_load_counter or (t1_reload_counter and phase = "11") then
t1c( 7 downto 0) <= r_t1l_l;
t1c(15 downto 8) <= r_t1l_h;
elsif (phase="11") then
t1c <= t1c - "1";
end if;
if t1_load_counter or t1_reload_counter then
t1c_active <= true;
elsif t1c_done then
t1c_active <= false;
end if;
t1_toggle <= '0';
if t1c_active and t1c_done then
t1_toggle <= '1';
t1_irq <= '1';
elsif t1_w_reset_int or t1_r_reset_int or (clear_irq(6) = '1') then
t1_irq <= '0';
end if;
if t1_load_counter then -- irq reset on load!
t1_irq <= '0';
end if;
end if;
end process;
--
-- Timer2
--
p_timer2_pb6_input : process
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
if (phase = "01") then -- leading edge p2_h
t2_pb6 <= I_PB(6);
t2_pb6_t1 <= t2_pb6;
end if;
end if;
end process;
p_timer2_done : process
variable done : boolean;
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
done := (t2c = x"0000");
t2c_done <= done and (phase = "11");
if (phase = "11") then
t2_reload_counter <= done;
end if;
if t2_load_counter then -- done reset on load!
t2c_done <= false;
end if;
end if;
end process;
p_timer2 : process
variable ena : boolean;
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
if (r_acr(5) = '0') then
ena := true;
else
ena := (t2_pb6_t1 = '1') and (t2_pb6 = '0'); -- falling edge
end if;
if t2_load_counter or (t2_reload_counter and phase = "11") then
-- not sure if t2c_reload should be here. Does timer2 just continue to
-- count down, or is it reloaded ? Reloaded makes more sense if using
-- it to generate a clock for the shift register.
t2c( 7 downto 0) <= r_t2l_l;
t2c(15 downto 8) <= r_t2l_h;
else
if (phase="11") and ena then -- or count mode
t2c <= t2c - "1";
end if;
end if;
t2_sr_ena <= (t2c(7 downto 0) = x"00") and (phase = "11");
if t2_load_counter then
t2c_active <= true;
elsif t2c_done then
t2c_active <= false;
end if;
if t2c_active and t2c_done then
t2_irq <= '1';
elsif t2_w_reset_int or t2_r_reset_int or (clear_irq(5) = '1') then
t2_irq <= '0';
end if;
if t2_load_counter then -- irq reset on load!
t2_irq <= '0';
end if;
end if;
end process;
--
-- Shift Register
--
p_sr : process(RESET_L, CLK)
variable dir_out : std_logic;
variable ena : std_logic;
variable cb1_op : std_logic;
variable cb1_ip : std_logic;
variable use_t2 : std_logic;
variable free_run : std_logic;
variable sr_count_ena : boolean;
begin
if (RESET_L = '0') then
r_sr <= x"00";
sr_drive_cb2 <= '0';
sr_cb1_oe_l <= '1';
sr_cb1_out <= '0';
sr_strobe <= '1';
sr_cnt <= "0000";
sr_irq <= '0';
sr_out <= '1';
sr_off_delay <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- decode mode
dir_out := r_acr(4); -- output on cb2
cb1_op := '0';
cb1_ip := '0';
use_t2 := '0';
free_run := '0';
-- DMB: SR still runs even in disabled mode (on rising edge of CB1).
-- It just doesn't generate any interrupts.
-- Ref BBC micro advanced user guide p409
case r_acr(4 downto 2) is
-- DMB: in disabled mode, configure cb1 as an input
when "000" => ena := '0'; cb1_ip := '1';
when "001" => ena := '1'; cb1_op := '1'; use_t2 := '1';
when "010" => ena := '1'; cb1_op := '1';
when "011" => ena := '1'; cb1_ip := '1';
when "100" => ena := '1'; use_t2 := '1'; free_run := '1';
when "101" => ena := '1'; cb1_op := '1'; use_t2 := '1';
when "110" => ena := '1';
when "111" => ena := '1'; cb1_ip := '1';
when others => null;
end case;
-- clock select
-- DMB: in disabled mode, strobe from cb1
if (cb1_ip = '1') then
sr_strobe <= I_CB1;
else
if (sr_cnt(3) = '0') and (free_run = '0') then
sr_strobe <= '1';
else
if ((use_t2 = '1') and t2_sr_ena) or
((use_t2 = '0') and (phase = "00")) then
sr_strobe <= not sr_strobe;
end if;
end if;
end if;
-- latch on rising edge, shift on falling edge
if sr_write_ena then
r_sr <= load_data;
else
-- DMB: allow shifting in all modes
if (dir_out = '0') then
-- input
if (sr_cnt(3) = '1') or (cb1_ip = '1') then
if sr_strobe_rising then
r_sr(0) <= I_CB2;
elsif sr_strobe_falling then
r_sr(7 downto 1) <= r_sr(6 downto 0);
end if;
end if;
sr_out <= '1';
else
-- output
if (sr_cnt(3) = '1') or (sr_off_delay = '1') or (cb1_ip = '1') or (free_run = '1') then
if sr_strobe_falling then
r_sr(7 downto 1) <= r_sr(6 downto 0);
r_sr(0) <= r_sr(7);
sr_out <= r_sr(7);
end if;
else
sr_out <= '1';
end if;
end if;
end if;
sr_count_ena := sr_strobe_rising;
-- DMB: reseting sr_count when not enabled cause the sr to
-- start running immediately it was enabled, which is incorrect
-- and broke the latest SmartSPI ROM on the BBC Micro
if ena = '1' and (sr_write_ena or sr_read_ena) then
-- some documentation says sr bit in IFR must be set as well ?
sr_cnt <= "1000";
elsif sr_count_ena and (sr_cnt(3) = '1') then
sr_cnt <= sr_cnt + "1";
end if;
if (phase = "00") then
sr_off_delay <= sr_cnt(3); -- give some hold time when shifting out
end if;
if sr_count_ena and (sr_cnt = "1111") and (ena = '1') and (free_run = '0') then
sr_irq <= '1';
elsif sr_write_ena or sr_read_ena or (clear_irq(2) = '1') then
sr_irq <= '0';
end if;
-- assign ops
sr_drive_cb2 <= dir_out;
sr_cb1_oe_l <= not cb1_op;
sr_cb1_out <= sr_strobe;
end if;
end if;
end process;
p_sr_strobe_rise_fall : process
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
sr_strobe_t1 <= sr_strobe;
sr_strobe_rising <= (sr_strobe_t1 = '0') and (sr_strobe = '1');
sr_strobe_falling <= (sr_strobe_t1 = '1') and (sr_strobe = '0');
end if;
end process;
--
-- Interrupts
--
p_ier : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
r_ier <= "0000000";
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
if ier_write_ena then
if (load_data(7) = '1') then
-- set
r_ier <= r_ier or load_data(6 downto 0);
else
-- clear
r_ier <= r_ier and not load_data(6 downto 0);
end if;
end if;
end if;
end if;
end process;
p_ifr : process(t1_irq, t2_irq, final_irq, ca1_irq, ca2_irq, sr_irq,
cb1_irq, cb2_irq)
begin
r_ifr(7) <= final_irq;
r_ifr(6) <= t1_irq;
r_ifr(5) <= t2_irq;
r_ifr(4) <= cb1_irq;
r_ifr(3) <= cb2_irq;
r_ifr(2) <= sr_irq;
r_ifr(1) <= ca1_irq;
r_ifr(0) <= ca2_irq;
O_IRQ_L <= not final_irq;
end process;
p_irq : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
final_irq <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
if ((r_ifr(6 downto 0) and r_ier(6 downto 0)) = "0000000") then
final_irq <= '0'; -- no interrupts
else
final_irq <= '1';
end if;
end if;
end if;
end process;
p_clear_irq : process(ifr_write_ena, load_data)
begin
clear_irq <= x"00";
if ifr_write_ena then
clear_irq <= load_data;
end if;
end process;
end architecture RTL;
| gpl-3.0 | 669006afc9fdb59c83170351b0ec671f | 0.498988 | 3.047204 | false | false | false | false |
DreamIP/GPStudio | support/process/gaussian/hdl/gaussian.vhd | 1 | 3,892 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity gaussian is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end gaussian;
architecture rtl of gaussian is
component gaussian_process
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_width : in std_logic_vector(15 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component gaussian_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal widthimg_reg_width : std_logic_vector (15 downto 0);
begin
gaussian_process_inst : gaussian_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_width => widthimg_reg_width,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
gaussian_slave_inst : gaussian_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_width => widthimg_reg_width,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
| gpl-3.0 | 1372347c50e4d70add5c1b2817103a35 | 0.46223 | 3.358067 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/global.vhd | 3 | 6,574 | -------------------------------------------------------------------------------
-- Global package
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package Global is
constant cActivated : std_logic := '1';
constant cInactivated : std_logic := '0';
constant cnActivated : std_logic := '0';
constant cnInactivated : std_logic := '1';
constant cByteLength : natural := 8;
constant cWordLength : natural := 2 * cByteLength;
constant cFalse : natural := 0;
constant cTrue : natural := 1;
function LogDualis(cNumber : natural) return natural;
function maximum (a : natural; b : natural) return natural;
function minimum (a : natural; b : natural) return natural;
function integerToBoolean (a : integer) return boolean;
function booleanToInteger (a : boolean) return integer;
function byteSwap (iVector : std_logic_vector) return std_logic_vector;
function wordSwap (iVector : std_logic_vector) return std_logic_vector;
function reduceOr (iVector : std_logic_vector) return std_logic;
function reduceAnd (iVector : std_logic_vector) return std_logic;
end Global;
package body Global is
function LogDualis(cNumber : natural) return natural is
variable vClimbUp : natural := 1;
variable vResult : natural := 0;
begin
while vClimbUp < cNumber loop
vClimbUp := vClimbUp * 2;
vResult := vResult+1;
end loop;
return vResult;
end LogDualis;
function maximum (a : natural; b : natural) return natural is
variable vRes : natural;
begin
if a > b then
vRes := a;
else
vRes := b;
end if;
return vRes;
end function;
function minimum (a : natural; b : natural) return natural is
variable vRes : natural;
begin
if a < b then
vRes := a;
else
vRes := b;
end if;
return vRes;
end function;
function integerToBoolean (a : integer) return boolean is
variable vRes : boolean;
begin
if a = cFalse then
vRes := false;
else
vRes := true;
end if;
return vRes;
end function;
function booleanToInteger (a : boolean) return integer is
variable vRes : integer;
begin
if a = false then
vRes := cFalse;
else
vRes := cTrue;
end if;
return vRes;
end function;
function byteSwap (iVector : std_logic_vector) return std_logic_vector is
variable vResult : std_logic_vector(iVector'range);
variable vLeftIndex : natural;
variable vRightIndex : natural;
begin
assert ((iVector'length mod cByteLength) = 0)
report "Byte swapping can't be done with that vector!"
severity failure;
for i in iVector'length / cByteLength downto 1 loop
vLeftIndex := i;
vRightIndex := iVector'length / cByteLength - i + 1;
vResult(vLeftIndex * cByteLength - 1 downto (vLeftIndex-1) * cByteLength) :=
iVector(vRightIndex * cByteLength - 1 downto (vRightIndex-1) * cByteLength);
end loop;
return vResult;
end function;
function wordSwap (iVector : std_logic_vector) return std_logic_vector is
variable vResult : std_logic_vector(iVector'range);
variable vLeftIndex : natural;
variable vRightIndex : natural;
begin
assert ((iVector'length mod cWordLength) = 0)
report "Word swapping can't be done with that vector!"
severity failure;
for i in iVector'length / cWordLength downto 1 loop
vLeftIndex := i;
vRightIndex := iVector'length / cWordLength - i + 1;
vResult(vLeftIndex * cWordLength - 1 downto (vLeftIndex-1) * cWordLength) :=
iVector(vRightIndex * cWordLength - 1 downto (vRightIndex-1) * cWordLength);
end loop;
return vResult;
end function;
function reduceOr (iVector : std_logic_vector) return std_logic is
variable vRes_tmp : std_logic;
begin
-- initialize result variable
vRes_tmp := cInactivated;
for i in iVector'range loop
vRes_tmp := vRes_tmp or iVector(i);
end loop;
return vRes_tmp;
end function;
function reduceAnd (iVector : std_logic_vector) return std_logic is
variable vRes_tmp : std_logic;
begin
-- initialize result variable
vRes_tmp := cActivated;
for i in iVector'range loop
vRes_tmp := vRes_tmp and iVector(i);
end loop;
return vRes_tmp;
end function;
end Global; | gpl-2.0 | 0627d26e551ddbb0cdc8cd8ab24c3e4d | 0.618193 | 4.587579 | false | false | false | false |
DreamIP/GPStudio | support/io/leds/hdl/leds.vhd | 1 | 1,193 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity leds is
generic (
CLK_PROC_FREQ : integer := 48000000;
LEDCOUNT : integer := 1
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
--------------------- external ports --------------------
o : out std_logic_vector(LEDCOUNT-1 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end leds;
architecture rtl of leds is
constant ENABLE_REG_ADDR : natural := 0;
signal led_reg : std_logic_vector(LEDCOUNT-1 downto 0);
begin
process (clk_proc, reset_n)
begin
if (reset_n='0') then
led_reg <= (others => '0');
elsif (clk_proc'event and clk_proc='1') then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(ENABLE_REG_ADDR, 2))=>
led_reg <= datawr_i(LEDCOUNT-1 downto 0);
when others=>
end case;
end if;
end if;
end process;
o <= led_reg;
end rtl;
| gpl-3.0 | 9d50a0624875a8ae4aad8e5bf54258db | 0.566639 | 2.95297 | false | false | false | false |
buserror/xc3sprog | bscan_spi/bscan_xc7_spi.vhd | 3 | 6,593 | --
-- XC3SPROG ISF File for Trenz Electronic TE0741 Kintex module
-- Author: Antti Lukats
-- converted from V5 version
--
-- Green user LED will be steady ON
-- Red user LED will be ON during SPI Chip select activation
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is port (
RLED : out std_logic;
GLED : out std_logic;
MOSI_ext : out std_logic;
MISO_ext : in std_logic;
IO2 : inout std_logic; -- WP
IO3 : inout std_logic; -- HOLD/RESET
CSB_ext : out std_logic
);
end top;
architecture Behavioral of top is
signal CAPTURE: std_logic;
signal UPDATE: std_logic;
signal DRCK1: std_logic;
signal TDI: std_logic;
signal TDO1: std_logic;
signal CSB: std_logic := '1';
signal header: std_logic_vector(47 downto 0);
signal len: std_logic_vector(15 downto 0);
signal have_header : std_logic := '0';
signal MISO: std_logic;
signal MOSI: std_logic;
signal SEL1: std_logic;
signal SHIFT: std_logic;
signal RESET: std_logic;
signal CS_GO: std_logic := '0';
signal CS_GO_PREP: std_logic := '0';
signal CS_STOP: std_logic := '0';
signal CS_STOP_PREP: std_logic := '0';
signal RAM_RADDR: std_logic_vector(13 downto 0);
signal RAM_WADDR: std_logic_vector(13 downto 0);
signal DRCK1_INV : std_logic;
signal RAM_DO: std_logic_vector(0 downto 0);
signal RAM_DI: std_logic_vector(0 downto 0);
signal RAM_WE: std_logic := '0';
begin
IO2 <= '1';
IO3 <= '1';
RLED <= not CSB;
GLED <= '1';
MISO <= MISO_ext;
MOSI_ext <= MOSI;
CSB_ext <= CSB;
DRCK1_INV <= not DRCK1;
RAMB16_S1_S1_inst : RAMB16_S1_S1
port map (
DOA => RAM_DO, -- Port A 1-bit Data Output
DOB => open, -- Port B 1-bit Data Output
ADDRA => RAM_RADDR, -- Port A 14-bit Address Input
ADDRB => RAM_WADDR, -- Port B 14-bit Address Input
CLKA => DRCK1_inv, -- Port A Clock
CLKB => DRCK1, -- Port B Clock
DIA => "0", -- Port A 1-bit Data Input
DIB => RAM_DI, -- Port B 1-bit Data Input
ENA => '1', -- Port A RAM Enable Input
ENB => '1', -- PortB RAM Enable Input
SSRA => '0', -- Port A Synchronous Set/Reset Input
SSRB => '0', -- Port B Synchronous Set/Reset Input
WEA => '0', -- Port A Write Enable Input
WEB => RAM_WE -- Port B Write Enable Input
);
BSCANE2_inst : BSCANE2
generic map (
JTAG_CHAIN => 1 -- Value for USER command.
)
port map (
CAPTURE => CAPTURE, -- 1-bit output: CAPTURE output from TAP controller.
DRCK => DRCK1, -- 1-bit output: Gated TCK output. When SEL is asserted, DRCK toggles when CAPTURE or
-- SHIFT are asserted.
RESET => RESET, -- 1-bit output: Reset output for TAP controller.
RUNTEST => open, -- 1-bit output: Output asserted when TAP controller is in Run Test/Idle state.
SEL => SEL1, -- 1-bit output: USER instruction active output.
SHIFT => SHIFT, -- 1-bit output: SHIFT output from TAP controller.
TCK => open, -- 1-bit output: Test Clock output. Fabric connection to TAP Clock pin.
TDI => TDI, -- 1-bit output: Test Data Input (TDI) output from TAP controller.
TMS => open, -- 1-bit output: Test Mode Select output. Fabric connection to TAP.
UPDATE => UPDATE, -- 1-bit output: UPDATE output from TAP controller
TDO => TDO1 -- 1-bit input: Test Data Output (TDO) input for USER function.
);
STARTUPE2_inst : STARTUPE2
generic map (
PROG_USR => "FALSE", -- Activate program event security feature. Requires encrypted bitstreams.
SIM_CCLK_FREQ => 0.0 -- Set the Configuration Clock Frequency(ns) for simulation.
)
port map (
CFGCLK => open, -- 1-bit output: Configuration main clock output
CFGMCLK => open, -- 1-bit output: Configuration internal oscillator clock output
EOS => open, -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => open, -- 1-bit output: PROGRAM request to fabric output
CLK => '0', -- 1-bit input: User start-up clock input
GSR => '0', -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
KEYCLEARB => '0' , -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
PACK => '1', -- 1-bit input: PROGRAM acknowledge input
USRCCLKO => DRCK1, -- 1-bit input: User CCLK input
USRCCLKTS => '0', -- 1-bit input: User CCLK 3-state enable input
USRDONEO => '1', -- 1-bit input: User DONE pin output control
USRDONETS => '1' -- 1-bit input: User DONE 3-state enable output
);
MOSI <= TDI;
CSB <= '0' when CS_GO = '1' and CS_STOP = '0' else '1';
RAM_DI <= MISO & "";
TDO1 <= RAM_DO(0);
-- falling edges
process(DRCK1, CAPTURE, RESET, UPDATE, SEL1)
begin
if CAPTURE = '1' or RESET='1' or UPDATE='1' or SEL1='0' then
have_header <= '0';
-- disable CSB
CS_GO_PREP <= '0';
CS_STOP <= '0';
elsif falling_edge(DRCK1) then
-- disable CSB?
CS_STOP <= CS_STOP_PREP;
-- waiting for header?
if have_header='0' then
-- got magic + len
if header(46 downto 15) = x"59a659a6" then
len <= header(14 downto 0) & "0";
have_header <= '1';
-- enable CSB on rising edge (if len > 0?)
if (header(14 downto 0) & "0") /= x"0000" then
CS_GO_PREP <= '1';
end if;
end if;
elsif len /= x"0000" then
len <= len - 1;
end if;
end if;
end process;
-- rising edges
process(DRCK1, CAPTURE, RESET, UPDATE, SEL1)
begin
if CAPTURE = '1' or RESET='1' or UPDATE='1' or SEL1='0' then
-- disable CSB
CS_GO <= '0';
CS_STOP_PREP <= '0';
RAM_WADDR <= (others => '0');
RAM_RADDR <= (others => '0');
RAM_WE <= '0';
elsif rising_edge(DRCK1) then
RAM_RADDR <= RAM_RADDR + 1;
RAM_WE <= not CSB;
if RAM_WE='1' then
RAM_WADDR <= RAM_WADDR + 1;
end if;
header <= header(46 downto 0) & TDI;
-- enable CSB?
CS_GO <= CS_GO_PREP;
-- disable CSB on falling edge
if CS_GO = '1' and len = x"0000" then
CS_STOP_PREP <= '1';
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 9726631094a490e166625ff69e5b644a | 0.583953 | 3.278468 | false | false | false | false |
zatslogic/UDI_example | tb/ip/mult_16_x_16_res_32.vhd | 1 | 4,355 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v11_2;
USE mult_gen_v11_2.mult_gen_v11_2;
ENTITY mult_16_x_16_res_32 IS
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END mult_16_x_16_res_32;
ARCHITECTURE mult_16_x_16_res_32_arch OF mult_16_x_16_res_32 IS
COMPONENT mult_gen_v11_2 IS
GENERIC (
c_verbosity : INTEGER;
c_model_type : INTEGER;
c_xdevicefamily : STRING;
c_a_width : INTEGER;
c_a_type : INTEGER;
c_b_width : INTEGER;
c_b_type : INTEGER;
c_out_high : INTEGER;
c_out_low : INTEGER;
c_mult_type : INTEGER;
c_optimize_goal : INTEGER;
c_has_ce : INTEGER;
c_has_sclr : INTEGER;
c_ce_overrides_sclr : INTEGER;
c_latency : INTEGER;
c_ccm_imp : INTEGER;
c_b_value : STRING;
c_has_zero_detect : INTEGER;
c_round_output : INTEGER;
c_round_pt : INTEGER
);
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
ce : IN STD_LOGIC;
sclr : IN STD_LOGIC;
zero_detect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
pcasc : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
);
END COMPONENT mult_gen_v11_2;
BEGIN
U0 : mult_gen_v11_2
GENERIC MAP (
c_verbosity => 0,
c_model_type => 0,
c_xdevicefamily => "artix7",
c_a_width => 16,
c_a_type => 0,
c_b_width => 16,
c_b_type => 0,
c_out_high => 31,
c_out_low => 0,
c_mult_type => 1,
c_optimize_goal => 1,
c_has_ce => 0,
c_has_sclr => 0,
c_ce_overrides_sclr => 0,
c_latency => 1,
c_ccm_imp => 0,
c_b_value => "10000001",
c_has_zero_detect => 0,
c_round_output => 0,
c_round_pt => 0
)
PORT MAP (
clk => clk,
a => a,
b => b,
ce => '1',
sclr => '0',
p => p
);
END mult_16_x_16_res_32_arch;
| gpl-3.0 | b18007d3c4e761d3f2cb2948f746bb1f | 0.653272 | 3.558007 | false | false | false | false |
ou-cse-378/vhdl-tetris | RGB_Controller.vhd | 1 | 8,121 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: RGB_Controller.vhd
-- // Date: 12/9/2004
-- // Description: Outputs RGB values to the VGA Controller
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RGB_Controller is
Port ( oRGB : out std_logic_vector(2 downto 0);
iClk : in std_logic;
iClr : in std_logic;
iPaused : in std_logic;
iBlock: in std_logic_vector(15 downto 0); --Block rows fom Block RAM
oBlockAddr : out std_logic_vector(4 downto 0); --address for block ram
iBlockY : in std_logic_vector(4 downto 0); --encoded Y
iBlockX : in std_logic_vector(3 downto 0); --encoded X
iBlockReg : in std_logic_vector(15 downto 0));
end RGB_Controller;
architecture Behavioral of RGB_Controller is
Signal tHCounter, tVCounter: std_logic_vector(10 downto 0) := "00000000000";
Signal tRGB : std_logic_vector(2 downto 0) := "000";
Signal tGFCurrentX : integer range 0 to 10 := 0; --Current X on Game Field being rendered, set in Pixel Counter Process
signal tGFCurrentY : integer range 0 to 21 := 0; --Current Y on Game Field being rendered, set in Line Counter Process
constant GBCOLOR : std_logic_vector(2 downto 0) := "111";
constant BLOCKCOLOR : std_logic_vector(2 downto 0) := "010";
constant PAUSEDCOLOR : std_logic_vector(2 downto 0) := "110";
-- Game Boundary is 3 boxes, specified by and upper left and lower right coordinate
type GBValues is array (NATURAL range <>) of integer;
--Each vertical column is a box. The GBX1, GBY1, GBX2, GBY2 specify the
--upper left and lower right corners of the boxes
constant GBX1 : GBValues :=(40, 245, 40);
constant GBY1 : GBValues :=(40, 40, 440);
constant GBX2 : GBValues :=(45, 250, 250);
constant GBY2 : GBValues :=(440, 440, 445);
constant PBX1 : GBValues := (0, 0, 0, 630);
constant PBX2 : GBValues := (640, 640, 10, 640);
constant PBY1 : GBValues := (0, 470, 10, 10);
constant PBY2 : GBValues := (10, 480, 470, 470);
constant GFX1 : integer := 45;
constant GFX2 : integer := 245;
constant GFY1 : integer := 40;
constant GFY2 : integer := 440;
Constant HFRONTPORCHSTART : integer := 640; --640
constant HPULSESTART : integer := HFRONTPORCHSTART + 17; --17
constant HBACKPORCHSTART : integer := HPULSESTART + 96; --96
constant HENDOFLINE : integer := HBACKPORCHSTART + 46; --47
Constant VFRONTPORCHSTART : integer := 480; --480
constant VPULSESTART : integer := VFRONTPORCHSTART + 10; --10
constant VBACKPORCHSTART : integer := VPULSESTART + 2; --2
constant VENDOFFRAME : integer := VBACKPORCHSTART + 29; --29
begin
PixelCounter: process(iClk, iClr, tHCounter, tVCounter)
variable tHBlockPixelCounter, tVBlockPixelCounter : integer range 0 to 20 := 0;
begin
if iClr = '1' then
tHCounter <= "00000000000";
tVCounter <= "00000000000";
tHBlockPixelCounter := 0;
tVBlockPixelCounter := 0;
tGFCurrentX <= 0;
tGFCurrentY <= 0;
elsif (iClk'event and iClk = '1') then
if tHCounter < HENDOFLINE then
tHCounter <= tHCounter + 1;
else
tHCounter <= "00000000000";
if tVCounter < VENDOFFRAME then
tVCounter <= tVCounter + 1;
else
tVCounter <= "00000000000";
end if;
end if;
--Count pixels if we're in the game field.
if tVCounter >= GFY1 and tVCounter < GFY2 and tHCounter >= GFX1 and tHCounter < GFX2 then
tHBlockPixelCounter := tHBlockPixelCounter + 1;
end if;
if tHBlockPixelCounter = 20 then
tHBlockPixelCounter := 0;
if tGFCurrentX < 9 then
tGFCurrentX <= tGFCurrentX + 1;
else
tGFCurrentX <= 0;
if tVBlockPixelCounter = 19 then
tVBlockPixelCounter := 0;
if tGFCurrentY < 19 then
tGFCurrentY <= tGFCurrentY + 1;
else
tGFCurrentY <= 0;
end if;
else
tVBlockPixelCounter := tVBlockPixelCounter + 1;
end if;
end if;
end if;
end if;
end process;
oBlockAddr <= conv_std_logic_vector((tGFCurrentY + 3), 5) when iClr = '0' else "00000";
RGBLoad: process(iClk, iClr)
variable tTempY : integer := 0;
variable tTempX : integer := 0;
variable tBlockRow : std_logic_vector(9 downto 0) := "0000000000";
begin
if iClr = '1' then
tRGB <= "000";
tTempX := 0;
tTempY := 0;
tBlockRow :="0000000000";
elsif (iClk'event and iClk = '1') then
--Draws Game Boundry
tRGB <= "000";
for i in 0 to 2 loop
if tVCounter >= GBY1(i) and tVCounter < GBY2(i) and tHCounter >= GBX1(i) and tHCounter < GBX2(i) then
tRGB <= GBCOLOR;
end if;
end loop;
if iPaused = '1' then
for i in 0 to 3 loop
if tVCounter >= PBY1(i) and tVCounter < PBY2(i) and tHCounter >= PBX1(i) and tHCounter < PBX2(i) then
tRGB <= PAUSEDCOLOR;
end if;
end loop;
end if;
--Draw Blocks
if tVCounter >= GFY1 and tVCounter < GFY2 and tHCounter >= GFX1 and tHCounter < GFX2 then
tTempX := conv_integer(iBlockX) - 3;
tTempY := conv_integer(iBlockY) - 3;
tBlockRow(9 downto 0) := iBlock(12 downto 3);
if tGFCurrentY = tTempY then
if tGFCurrentX = tTempX then
tBlockRow(9 - tGFCurrentX) := tBlockrow(9 - tGFCurrentX) OR iBlockreg(15);
elsif tGFCurrentX = tTempX + 1 then
tBlockRow(9 - tGFCurrentX) := tBlockrow(9 - tGFCurrentX) OR iBlockreg(14);
elsif tGFCurrentX = tTempX + 2 then
tBlockRow(9 - tGFCurrentX) := tBlockrow(9 - tGFCurrentX) OR iBlockreg(13);
elsif tGFCurrentX = tTempX + 3 then
tBlockRow(9 - tGFCurrentX) := tBlockrow(9 - tGFCurrentX) OR iBlockreg(12);
end if;
end if;
if tGFCurrentY = tTempY + 1 then
if tGFCurrentX = tTempX then
tBlockRow(9 - tGFCurrentX) := tBlockrow(9 - tGFCurrentX) OR iBlockreg(11);
elsif tGFCurrentX = tTempX + 1 then
tBlockRow(9 - tGFCurrentX) := tBlockrow(9 - tGFCurrentX) OR iBlockreg(10);
elsif tGFCurrentX = tTempX + 2 then
tBlockRow(9 - tGFCurrentX) := tBlockrow(9 - tGFCurrentX) OR iBlockreg(9);
elsif tGFCurrentX = tTempX + 3 then
tBlockRow(9 - tGFCurrentX) := tBlockrow(9 - tGFCurrentX) OR iBlockreg(8);
end if;
end if;
if tGFCurrentY = tTempY + 2 then
if tGFCurrentX = tTempX then
tBlockRow(9 - tGFCurrentX) := tBlockrow(9 - tGFCurrentX) OR iBlockreg(7);
elsif tGFCurrentX = tTempX + 1 then
tBlockRow(9 - tGFCurrentX) := tBlockrow(9 - tGFCurrentX) OR iBlockreg(6);
elsif tGFCurrentX = tTempX + 2 then
tBlockRow(9 - tGFCurrentX) := tBlockrow(9 - tGFCurrentX) OR iBlockreg(5);
elsif tGFCurrentX = tTempX + 3 then
tBlockRow(9 - tGFCurrentX) := tBlockrow(9 - tGFCurrentX) OR iBlockreg(4);
end if;
end if;
if tGFCurrentY = tTempY + 3 then
if tGFCurrentX = tTempX then
tBlockRow(9 - tGFCurrentX) := tBlockrow(9 - tGFCurrentX) OR iBlockreg(3);
elsif tGFCurrentX = tTempX + 1 then
tBlockRow(9 - tGFCurrentX) := tBlockrow(9 - tGFCurrentX) OR iBlockreg(2);
elsif tGFCurrentX = tTempX + 2 then
tBlockRow(9 - tGFCurrentX) := tBlockrow(9 - tGFCurrentX) OR iBlockreg(1);
elsif tGFCurrentX = tTempX + 3 then
tBlockRow(9 - tGFCurrentX) := tBlockrow(9 - tGFCurrentX) OR iBlockreg(0);
end if;
end if;
if tBlockRow(9 - tGFCurrentX) = '1' then
tRGB <= BLOCKCOLOR;
else
tRGB <= "000";
end if;
end if;
end if; --clk event
end process;
RGBOut: process(iClk, iClr)
begin
if iClr = '1' then
oRGB <= "000";
elsif (iClk'event and iClk = '1') then
--We're on the screen. Draw things.
oRGB <= tRGB;
end if;
end process;
end Behavioral;
| mit | 74326b297a098c989caa5fb15951dd5c | 0.630711 | 2.988958 | false | false | false | false |
DreamIP/GPStudio | support/toolchain/caph/hdl/caph_lib/split.vhd | 1 | 6,453 | -----------------------------------------------------------------------------------------
-- --
-- This file is part of the CAPH Compiler distribution --
-- http://caph.univ-bpclermont.fr --
-- --
-- Jocelyn SEROT --
-- [email protected] --
-- --
-- Copyright 2011-2015 Jocelyn SEROT. All rights reserved. --
-- This file is distributed under the terms of the GNU Library General Public License --
-- with the special exception on linking described in file ../LICENSE. --
-- --
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
-- +-----------+
-- | | d1_f
-- | |<--------
-- | | d1
-- d_f | |-------->
-- <--------| | d1_wr
-- d | |-------->
-- -------->| SPLIT |
-- d_wr | | d2_f
-- -------->| |<--------
-- | | d2
-- | |-------->
-- | | d2_wr
-- | |-------->
-- +-----------+
entity split2 is
generic ( size: integer := 10);
port (
d_f: out std_logic;
d : in std_logic_vector (size-1 downto 0);
d_wr : in std_logic;
d1_f : in std_logic;
d1 : out std_logic_vector(size-1 downto 0);
d1_wr : out std_logic;
d2_f : in std_logic;
d2 : out std_logic_vector(size-1 downto 0);
d2_wr : out std_logic
);
end split2;
architecture arch of split2 is
begin
d1 <= d;
d2 <= d;
d1_wr <= d_wr;
d2_wr <= d_wr;
d_f <= d1_f or d2_f;
end arch;
library ieee;
use ieee.std_logic_1164.ALL;
entity split3 is
generic ( size: integer := 10);
port (
d_f: out std_logic;
d : in std_logic_vector (size-1 downto 0);
d_wr : in std_logic;
d1_f : in std_logic;
d1 : out std_logic_vector(size-1 downto 0);
d1_wr : out std_logic;
d2_f : in std_logic;
d2 : out std_logic_vector(size-1 downto 0);
d2_wr : out std_logic;
d3_f : in std_logic;
d3 : out std_logic_vector(size-1 downto 0);
d3_wr : out std_logic
);
end split3;
architecture arch of split3 is
begin
d1 <= d;
d2 <= d;
d3 <= d;
d1_wr <= d_wr;
d2_wr <= d_wr;
d3_wr <= d_wr;
d_f <= d1_f or d2_f or d3_f;
end arch;
library ieee;
use ieee.std_logic_1164.ALL;
entity split4 is
generic ( size: integer := 10);
port (
d_f: out std_logic;
d : in std_logic_vector (size-1 downto 0);
d_wr : in std_logic;
d1_f : in std_logic;
d1 : out std_logic_vector(size-1 downto 0);
d1_wr : out std_logic;
d2_f : in std_logic;
d2 : out std_logic_vector(size-1 downto 0);
d2_wr : out std_logic;
d3_f : in std_logic;
d3 : out std_logic_vector(size-1 downto 0);
d3_wr : out std_logic;
d4_f : in std_logic;
d4 : out std_logic_vector(size-1 downto 0);
d4_wr : out std_logic
);
end split4;
architecture arch of split4 is
begin
d1 <= d;
d2 <= d;
d3 <= d;
d4 <= d;
d1_wr <= d_wr;
d2_wr <= d_wr;
d3_wr <= d_wr;
d4_wr <= d_wr;
d_f <= d1_f or d2_f or d3_f or d4_f;
end arch;
library ieee;
use ieee.std_logic_1164.ALL;
entity split5 is
generic ( size: integer := 10);
port (
d_f: out std_logic;
d : in std_logic_vector (size-1 downto 0);
d_wr : in std_logic;
d1_f : in std_logic;
d1 : out std_logic_vector(size-1 downto 0);
d1_wr : out std_logic;
d2_f : in std_logic;
d2 : out std_logic_vector(size-1 downto 0);
d2_wr : out std_logic;
d3_f : in std_logic;
d3 : out std_logic_vector(size-1 downto 0);
d3_wr : out std_logic;
d4_f : in std_logic;
d4 : out std_logic_vector(size-1 downto 0);
d4_wr : out std_logic;
d5_f : in std_logic;
d5 : out std_logic_vector(size-1 downto 0);
d5_wr : out std_logic
);
end split5;
architecture arch of split5 is
begin
d1 <= d;
d2 <= d;
d3 <= d;
d4 <= d;
d5 <= d;
d1_wr <= d_wr;
d2_wr <= d_wr;
d3_wr <= d_wr;
d4_wr <= d_wr;
d5_wr <= d_wr;
d_f <= d1_f or d2_f or d3_f or d4_f or d5_f;
end arch;
library ieee;
use ieee.std_logic_1164.ALL;
entity split6 is
generic ( size: integer := 10);
port (
d_f: out std_logic;
d : in std_logic_vector (size-1 downto 0);
d_wr : in std_logic;
d1_f : in std_logic;
d1 : out std_logic_vector(size-1 downto 0);
d1_wr : out std_logic;
d2_f : in std_logic;
d2 : out std_logic_vector(size-1 downto 0);
d2_wr : out std_logic;
d3_f : in std_logic;
d3 : out std_logic_vector(size-1 downto 0);
d3_wr : out std_logic;
d4_f : in std_logic;
d4 : out std_logic_vector(size-1 downto 0);
d4_wr : out std_logic;
d5_f : in std_logic;
d5 : out std_logic_vector(size-1 downto 0);
d5_wr : out std_logic;
d6_f : in std_logic;
d6 : out std_logic_vector(size-1 downto 0);
d6_wr : out std_logic
);
end split6;
architecture arch of split6 is
begin
d1 <= d;
d2 <= d;
d3 <= d;
d4 <= d;
d5 <= d;
d6 <= d;
d1_wr <= d_wr;
d2_wr <= d_wr;
d3_wr <= d_wr;
d4_wr <= d_wr;
d5_wr <= d_wr;
d6_wr <= d_wr;
d_f <= d1_f or d2_f or d3_f or d4_f or d5_f or d6_f;
end arch;
| gpl-3.0 | f5fad0bb7f93667025deca23a2f9fc3b | 0.410662 | 3.202481 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/mems/SinglePortRAM.vhdl | 1 | 2,919 | --
-- Single Port RAM
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library FPGALIB;
use FPGALIB.MEMS.all;
entity SinglePortRAM is
generic (
AWIDTH : positive:=8; -- Address width
DWIDTH : positive:=8; -- Data width
DEPTH : natural:=0; -- Memory depth
SYNCMODE : syncmode_t:=WRITE_FIRST; -- Synchronization Mode
OUTREG : boolean :=FALSE -- Optional Output Register
);
port (
clk_i : in std_logic;
wen_i : in std_logic;
addr_i : in std_logic_vector(AWIDTH-1 downto 0);
data_i : in std_logic_vector(DWIDTH-1 downto 0);
data_o : out std_logic_vector(DWIDTH-1 downto 0)
);
end entity SinglePortRAM;
architecture RTL of SinglePortRAM is
constant SIZE : positive:=getMemorySize(DEPTH,AWIDTH);
type ram_type is array(SIZE-1 downto 0) of std_logic_vector (DWIDTH-1 downto 0);
signal ram : ram_type;
signal data : std_logic_vector(DWIDTH-1 downto 0);
begin
ram_p:
process (clk_i)
begin
if rising_edge(clk_i) then
case SYNCMODE is
when READ_FIRST =>
if OUTREG then
data <= ram(to_integer(unsigned(addr_i)));
data_o <= data;
else
data_o <= ram(to_integer(unsigned(addr_i)));
end if;
if wen_i='1' then
ram(to_integer(unsigned(addr_i))) <= data_i;
end if;
when WRITE_FIRST =>
if wen_i='1' then
ram(to_integer(unsigned(addr_i))) <= data_i;
if OUTREG then
data <= data_i;
data_o <= data;
else
data_o <= data_i;
end if;
else
if OUTREG then
data <= ram(to_integer(unsigned(addr_i)));
data_o <= data;
else
data_o <= ram(to_integer(unsigned(addr_i)));
end if;
end if;
when NO_CHANGE =>
if wen_i='1' then
ram(to_integer(unsigned(addr_i))) <= data_i;
else
if OUTREG then
data <= ram(to_integer(unsigned(addr_i)));
data_o <= data;
else
data_o <= ram(to_integer(unsigned(addr_i)));
end if;
end if;
end case;
end if;
end process ram_p;
end architecture RTL;
| bsd-3-clause | 970d0edbe6a93a88757fbd9bfe9d22ae | 0.453237 | 4.267544 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_sdram_0_s1_translator.vhd | 1 | 12,747 | -- tracking_camera_system_sdram_0_s1_translator.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.13.13:59:38
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tracking_camera_system_sdram_0_s1_translator is
generic (
AV_ADDRESS_W : integer := 22;
AV_DATA_W : integer := 16;
UAV_DATA_W : integer := 16;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 2;
UAV_BYTEENABLE_W : integer := 2;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 2;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 2;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- .readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(21 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(15 downto 0); -- .writedata
av_byteenable : out std_logic_vector(1 downto 0); -- .byteenable
av_readdatavalid : in std_logic := '0'; -- .readdatavalid
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_chipselect : out std_logic; -- .chipselect
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_writebyteenable : out std_logic_vector(1 downto 0);
uav_clken : in std_logic := '0'
);
end entity tracking_camera_system_sdram_0_s1_translator;
architecture rtl of tracking_camera_system_sdram_0_s1_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(21 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_byteenable : out std_logic_vector(1 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_writebyteenable : out std_logic_vector(1 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component altera_merlin_slave_translator;
begin
sdram_0_s1_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_readdatavalid => av_readdatavalid, -- .readdatavalid
av_waitrequest => av_waitrequest, -- .waitrequest
av_chipselect => av_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
end architecture rtl; -- of tracking_camera_system_sdram_0_s1_translator
| gpl-2.0 | a955aa524506e899157d93b3b0e93a2b | 0.431631 | 4.310788 | false | false | false | false |
DreamIP/GPStudio | support/process/lbp/hdl/lbp_slave.vhd | 1 | 1,692 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity lbp_slave is
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0);
-- connections to lbp module
enable_o : out std_logic;
widthimg_o : out std_logic_vector(15 downto 0);
theshold_o : out std_logic_vector(7 downto 0)
);
end lbp_slave;
architecture rtl of lbp_slave is
constant ENABLE_REG_ADDR : natural := 0;
constant WIDTHIMG_REG_ADDR : natural := 1;
constant THRESHOLD_REG_ADDR : natural := 2;
signal enable_reg : std_logic;
signal widthimg_reg : std_logic_vector(15 downto 0);
signal theshold_reg : std_logic_vector(7 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
enable_reg <= '0';
widthimg_reg <= std_logic_vector(to_unsigned(320, 16));
theshold_reg <= std_logic_vector(to_unsigned(0, 8));
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(ENABLE_REG_ADDR, 2))=>
enable_reg <= datawr_i(0);
when std_logic_vector(to_unsigned(WIDTHIMG_REG_ADDR, 2))=>
widthimg_reg <= datawr_i(15 downto 0);
when std_logic_vector(to_unsigned(THRESHOLD_REG_ADDR, 2))=>
theshold_reg <= datawr_i(7 downto 0);
when others=>
end case;
end if;
end if;
end process;
enable_o <= enable_reg;
widthimg_o <= widthimg_reg;
theshold_o <= theshold_reg;
end rtl;
| gpl-3.0 | 68a352154aa695276ac306d47fb2b2f1 | 0.634161 | 2.694268 | false | false | false | false |
marzoul/PoC | src/arith/arith_counter_gray.vhdl | 2 | 4,565 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Module: Gray-Code counter.
--
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Steffen Koehler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity arith_counter_gray is
generic (
BITS : positive; -- Bit width of the counter
INIT : natural := 0 -- Initial/reset counter value
);
port (
clk : in std_logic;
rst : in std_logic; -- Reset to INIT value
inc : in std_logic; -- Increment
dec : in std_logic := '0'; -- Decrement
val : out std_logic_vector(BITS-1 downto 0); -- Value output
cry : out std_logic -- Carry output
);
end arith_counter_gray;
architecture rtl of arith_counter_gray is
-- purpose: gray constant encoder
function gray_encode (val : natural; len : positive) return unsigned is
variable bin : unsigned(len-1 downto 0) := to_unsigned(val, len);
begin
if len = 1 then
return bin;
end if;
return bin xor '0' & bin(len-1 downto 1);
end gray_encode;
-- purpose: parity generation
function parity (val : unsigned) return std_logic is
variable res : std_logic := '0';
begin -- parity
for i in val'range loop
res := res xor val(i);
end loop;
return res;
end parity;
-- Counter Register
constant INIT_GRAY : unsigned(BITS-1 downto 0) := gray_encode(INIT, BITS);
signal gray_cnt_r : unsigned(BITS-1 downto 0) := INIT_GRAY;
signal gray_cnt_nxt : unsigned(BITS-1 downto 0);
signal en : std_logic; -- enable: inc xor dec
begin
-----------------------------------------------------------------------------
-- Actual Counter Register
en <= inc xor dec;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
gray_cnt_r <= INIT_GRAY;
elsif en = '1' then
gray_cnt_r <= gray_cnt_nxt;
end if;
end if;
end process;
val <= std_logic_vector(gray_cnt_r);
-----------------------------------------------------------------------------
-- Computation of Increment/Decrement
-- Trivial one-bit Counter
g1: if BITS = 1 generate
gray_cnt_nxt <= not gray_cnt_r;
cry <= gray_cnt_r(0) xor dec;
end generate g1;
-- Multi-Bit Counter
g2: if BITS > 1 generate
constant INIT_PAR : std_logic := parity(INIT_GRAY);
-- search for first one in gray_cnt_r(MSB-1 downto LSB)
-- first_one_n(i) = '1' denotes position i
-- parity of gray_cnt_r
signal par_r : std_logic := INIT_PAR;
signal par_nxt : std_logic;
begin
-- Parity Register
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
par_r <= INIT_PAR;
elsif en = '1' then
par_r <= par_nxt;
end if;
end if;
end process;
-- Computation of next Value
process(gray_cnt_r, par_r, dec)
variable x : unsigned(BITS-1 downto 0);
variable s : unsigned(BITS-1 downto 0);
begin
-- Prefer inc over dec to keep combinational path short in standard use.
x := gray_cnt_r(BITS-2 downto 0) & (par_r xnor dec);
x(x'left) := not gray_cnt_r(BITS-1); -- catch final carry to invert last bit
s := not x + 1; -- locate first intermediate '1'
gray_cnt_nxt <= s(BITS-1) & (gray_cnt_r(BITS-2 downto 0) xor
(s(BITS-2 downto 0) and x(BITS-2 downto 0)));
par_nxt <= s(0) xor dec;
end process;
cry <= ((gray_cnt_r(BITS-1) xor dec) and (gray_cnt_nxt(BITS-1) xnor dec));
end generate g2;
end rtl;
| apache-2.0 | 47b9cd00ea3dd7940753b72467e34c4e | 0.57897 | 3.351689 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/fifo/src/fifoRead-rtl-ea.vhd | 3 | 5,843 | -------------------------------------------------------------------------------
--! @file fifoRead-rtl-ea.vhd
--
--! @brief FIFO read controller
--
--! @details This is a FIFO read controller.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity fifoRead is
generic (
gAddrWidth : natural := 4
);
port (
iClk : in std_logic;
iRst : in std_logic;
iRead : in std_logic;
iWrPointer : in std_logic_vector(gAddrWidth downto 0);
oEmpty : out std_logic;
oFull : out std_logic;
oPointer : out std_logic_vector(gAddrWidth downto 0);
oAddress : out std_logic_vector(gAddrWidth-1 downto 0);
oUsedWord : out std_logic_vector(gAddrWidth-1 downto 0)
);
end fifoRead;
architecture rtl of fifoRead is
signal r_ptr_reg : std_logic_vector(gAddrWidth downto 0);
signal r_ptr_next : std_logic_vector(gAddrWidth downto 0);
signal gray1 : std_logic_vector(gAddrWidth downto 0);
signal bin : std_logic_vector(gAddrWidth downto 0);
signal bin1 : std_logic_vector(gAddrWidth downto 0);
signal raddr_all : std_logic_vector(gAddrWidth-1 downto 0);
signal raddr_msb : std_logic;
signal waddr_msb : std_logic;
signal empty_flag : std_logic;
signal full_flag : std_logic;
signal r_elements_wr : std_logic_vector(gAddrWidth downto 0);
signal r_elements_rd : std_logic_vector(gAddrWidth downto 0);
signal r_elements_diff : std_logic_vector(gAddrWidth downto 0);
signal r_elements_reg : std_logic_vector(gAddrWidth-1 downto 0);
signal r_elements_next : std_logic_vector(gAddrWidth-1 downto 0);
begin
--! Clock process for registers.
regProc : process(iRst, iClk)
begin
if iRst = cActivated then
r_ptr_reg <= (others => cInactivated);
r_elements_reg <= (others => cInactivated);
elsif rising_edge(iClk) then
r_ptr_reg <= r_ptr_next;
r_elements_reg <= r_elements_next;
end if;
end process;
-- (gAddrWidth+1)-bit Gray counter
bin <= r_ptr_reg xor (cInactivated & bin(gAddrWidth downto 1));
bin1 <= std_logic_vector(unsigned(bin) + 1);
gray1 <= bin1 xor (cInactivated & bin1(gAddrWidth downto 1));
-- update read pointer
r_ptr_next <= gray1 when iRead = cActivated and empty_flag = cInactivated else
r_ptr_reg;
-- gAddrWidth-bit Gray counter
raddr_msb <= r_ptr_reg(gAddrWidth) xor r_ptr_reg(gAddrWidth-1);
raddr_all <= raddr_msb & r_ptr_reg(gAddrWidth-2 downto 0);
waddr_msb <= iWrPointer(gAddrWidth) xor iWrPointer(gAddrWidth-1);
-- check for FIFO read empty
empty_flag <= cActivated when iWrPointer(gAddrWidth) = r_ptr_reg(gAddrWidth) and
iWrPointer(gAddrWidth-2 downto 0) = r_ptr_reg(gAddrWidth-2 downto 0) and
raddr_msb = waddr_msb else
cInactivated;
-- check for FIFO read full
full_flag <= cActivated when iWrPointer(gAddrWidth) /= r_ptr_reg(gAddrWidth) and
iWrPointer(gAddrWidth-2 downto 0) = r_ptr_reg(gAddrWidth-2 downto 0) and
raddr_msb = waddr_msb else
cInactivated;
-- convert gray value to bin and obtain difference
r_elements_wr <= bin;
r_elements_rd <= iWrPointer xor (cInactivated & r_elements_rd(gAddrWidth downto 1));
r_elements_diff <= std_logic_vector(unsigned(r_elements_rd) - unsigned(r_elements_wr));
r_elements_next <= r_elements_diff(r_elements_next'range);
-- output
oAddress <= raddr_all;
oPointer <= r_ptr_reg;
oUsedWord <= r_elements_reg;
oEmpty <= empty_flag;
oFull <= full_flag;
end rtl;
| gpl-2.0 | ba31091bfb5056b41b5c959c62306a9a | 0.620572 | 4.152807 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/xilinx/openmac/src/axi_openmac-vivado-rtl-ea.vhd | 3 | 74,430 | -------------------------------------------------------------------------------
--! @file axi_openmac-vivado-rtl-ea.vhd
--
--! @brief OpenMAC toplevel for Xilinx
--
--! @details This is the openMAC toplevel for Xilinx Vivado.
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2016
-- (c) Weidmueller Interface GmbH & Co. KG, 2016
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of the copyright holders nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use openmac package
use work.openmacPkg.all;
--! AXI Lite IPIF library
library axi_lite_ipif_v3_0_4;
--! Use AXI lite ipif
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
--! AXI Master Burst library
library axi_master_burst_v2_0_7;
--! Use AXI master burst
use axi_master_burst_v2_0_7.axi_master_burst;
--! Unisim library
library unisim;
--! Use ODDR2 instance primitive
use unisim.vcomponents.oddr2;
entity axi_openmac is
generic (
-----------------------------------------------------------------------
-- General parameters
-----------------------------------------------------------------------
--! Xilinx FPGA familiy
C_FAMILY : string := "spartan6";
-----------------------------------------------------------------------
-- AXI DMA
-----------------------------------------------------------------------
--! AXI master DMA address width
C_M_AXI_MAC_DMA_ADDR_WIDTH : integer := 32;
--! AXI master DMA data width
C_M_AXI_MAC_DMA_DATA_WIDTH : integer := 32;
--! AXI master DMA native data width
C_M_AXI_MAC_DMA_NATIVE_DWIDTH : integer := 32;
--! AXI master DMA burst length width
C_M_AXI_MAC_DMA_LENGTH_WIDTH : integer := 12;
--! AXI master DMA burst length
C_M_AXI_MAC_DMA_MAX_BURST_LEN : integer := 16;
-----------------------------------------------------------------------
-- AXI REG
-----------------------------------------------------------------------
--! AXI slave REG address ranges
C_S_AXI_MAC_REG_NUM_ADDR_RANGES : integer := 2;
--! AXI slave REG range 0 base
C_S_AXI_MAC_REG_RNG0_BASEADDR : std_logic_vector := x"ffffffff";
--! AXI slave REG range 0 high
C_S_AXI_MAC_REG_RNG0_HIGHADDR : std_logic_vector := x"00000000";
--! AXI slave REG range 1 base
C_S_AXI_MAC_REG_RNG1_BASEADDR : std_logic_vector := x"ffffffff";
--! AXI slave REG range 1 high
C_S_AXI_MAC_REG_RNG1_HIGHADDR : std_logic_vector := x"00000000";
--! AXI slave REG minimum size
C_S_AXI_MAC_REG_MIN_SIZE : std_logic_vector := x"00001fff";
--! AXI slave REG data width
C_S_AXI_MAC_REG_DATA_WIDTH : integer := 32;
--! AXI slave REG address width
C_S_AXI_MAC_REG_ADDR_WIDTH : integer := 32;
--! AXI slave REG clock frequency
C_S_AXI_MAC_REG_ACLK_FREQ_HZ : integer := 50000000;
--! AXI slave REG use write strobes
C_S_AXI_MAC_REG_USE_WSTRB : integer := 1;
--! AXI slave REG enable data phase timeout timer
C_S_AXI_MAC_REG_DPHASE_TIMEOUT : integer := 0;
--! Enable clock crossing circuit
C_S_AXI_MAC_REG_CLK_XING : natural := 1;
-----------------------------------------------------------------------
-- AXI REG
-----------------------------------------------------------------------
--! AXI slave PKT base
C_S_AXI_MAC_PKT_BASEADDR : std_logic_vector := x"ffffffff";
--! AXI slave PKT high
C_S_AXI_MAC_PKT_HIGHADDR : std_logic_vector := x"00000000";
--! AXI slave REG minimum size
C_S_AXI_MAC_PKT_MIN_SIZE : std_logic_vector := x"0000ffff";
--! AXI slave PKT data width
C_S_AXI_MAC_PKT_DATA_WIDTH : integer := 32;
--! AXI slave PKT address width
C_S_AXI_MAC_PKT_ADDR_WIDTH : integer := 32;
--! AXI slave PKT use write strobes
C_S_AXI_MAC_PKT_USE_WSTRB : integer := 1;
--! AXI slave PKT enable data phase timeout timer
C_S_AXI_MAC_PKT_DPHASE_TIMEOUT : integer := 0;
-----------------------------------------------------------------------
-- Phy configuration
-----------------------------------------------------------------------
--! Number of Phy ports
gPhyPortCount : natural := 2;
--! Phy port interface type (Rmii or Mii)
gPhyPortType : natural := 1;
--! Number of SMI phy ports
gSmiPortCount : natural := 1;
-----------------------------------------------------------------------
-- General configuration
-----------------------------------------------------------------------
--! Endianness ("little" or "big")
gEndianness : string := "little";
--! Enable packet activity generator (e.g. connect to LED)
gEnableActivity : natural := 0;
--! Enable DMA observer circuit
gEnableDmaObserver : natural := 0;
-----------------------------------------------------------------------
-- DMA configuration
-----------------------------------------------------------------------
--! DMA address width (byte-addressing)
gDmaAddrWidth : natural := 32;
--! DMA data width
gDmaDataWidth : natural := 16;
--! DMA burst count width
gDmaBurstCountWidth : natural := 4;
--! DMA write burst length (Rx packets) [words]
gDmaWriteBurstLength : natural := 16;
--! DMA read burst length (Tx packets) [words]
gDmaReadBurstLength : natural := 16;
--! DMA write FIFO length (Rx packets) [words]
gDmaWriteFifoLength : natural := 16;
--! DMA read FIFO length (Tx packets) [words]
gDmaReadFifoLength : natural := 16;
-----------------------------------------------------------------------
-- Packet buffer configuration
-----------------------------------------------------------------------
--! Packet buffer location for Tx packets
gPacketBufferLocTx : natural := 1;
--! Packet buffer location for Rx packets
gPacketBufferLocRx : natural := 1;
--! Packet buffer log2(size) [log2(bytes)]
gPacketBufferLog2Size : natural := 10;
-----------------------------------------------------------------------
-- MAC timer configuration
-----------------------------------------------------------------------
--! Enable pulse timer
gTimerEnablePulse : natural := 0;
--! Enable timer pulse width control
gTimerEnablePulseWidth : natural := 0;
--! Timer pulse width register width
gTimerPulseRegWidth : natural := 10
);
port (
-----------------------------------------------------------------------
-- Clock and reset signal pairs
-----------------------------------------------------------------------
--! Main clock used for openMAC, openHUB and openFILTER (freq = 50 MHz)
iClk50 : in std_logic;
--! Twice main clock used for Rmii Tx path
iClk100 : in std_logic;
-----------------------------------------------------------------------
-- MAC REG memory mapped slave
-----------------------------------------------------------------------
--! AXI slave REG clock
S_AXI_MAC_REG_ACLK : in std_logic;
--! AXI slave REG reset (low-active)
S_AXI_MAC_REG_ARESETN : in std_logic;
--! AXI slave REG address read valid
S_AXI_MAC_REG_ARVALID : in std_logic;
--! AXI slave REG address write valid
S_AXI_MAC_REG_AWVALID : in std_logic;
--! AXI slave REG response ready
S_AXI_MAC_REG_BREADY : in std_logic;
--! AXI slave REG read ready
S_AXI_MAC_REG_RREADY : in std_logic;
--! AXI slave REG write valid
S_AXI_MAC_REG_WVALID : in std_logic;
--! AXI slave REG read address
S_AXI_MAC_REG_ARADDR : in std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
--! AXI slave REG write address
S_AXI_MAC_REG_AWADDR : in std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
--! AXI slave REG write data
S_AXI_MAC_REG_WDATA : in std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
--! AXI slave REG write strobe
S_AXI_MAC_REG_WSTRB : in std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH/8-1 downto 0);
--! AXI slave REG read address ready
S_AXI_MAC_REG_ARREADY : out std_logic;
--! AXI slave REG write address ready
S_AXI_MAC_REG_AWREADY : out std_logic;
--! AXI slave REG write response valid
S_AXI_MAC_REG_BVALID : out std_logic;
--! AXI slave REG read valid
S_AXI_MAC_REG_RVALID : out std_logic;
--! AXI slave REG write ready
S_AXI_MAC_REG_WREADY : out std_logic;
--! AXI slave REG write response
S_AXI_MAC_REG_BRESP : out std_logic_vector(1 downto 0);
--! AXI slave REG read data
S_AXI_MAC_REG_RDATA : out std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
--! AXI slave REG read response
S_AXI_MAC_REG_RRESP : out std_logic_vector(1 downto 0);
-----------------------------------------------------------------------
-- MAC PACKET BUFFER memory mapped slave
-----------------------------------------------------------------------
--! AXI slave PKT clock
S_AXI_MAC_PKT_ACLK : in std_logic;
--! AXI slave PKT reset (low-active)
S_AXI_MAC_PKT_ARESETN : in std_logic;
--! AXI slave PKT address read valid
S_AXI_MAC_PKT_ARVALID : in std_logic;
--! AXI slave PKT address write valid
S_AXI_MAC_PKT_AWVALID : in std_logic;
--! AXI slave PKT response ready
S_AXI_MAC_PKT_BREADY : in std_logic;
--! AXI slave PKT read ready
S_AXI_MAC_PKT_RREADY : in std_logic;
--! AXI slave PKT write valid
S_AXI_MAC_PKT_WVALID : in std_logic;
--! AXI slave PKT read address
S_AXI_MAC_PKT_ARADDR : in std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
--! AXI slave PKT write address
S_AXI_MAC_PKT_AWADDR : in std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
--! AXI slave PKT write data
S_AXI_MAC_PKT_WDATA : in std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
--! AXI slave PKT write strobe
S_AXI_MAC_PKT_WSTRB : in std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH/8-1 downto 0);
--! AXI slave PKT read address ready
S_AXI_MAC_PKT_ARREADY : out std_logic;
--! AXI slave PKT write address ready
S_AXI_MAC_PKT_AWREADY : out std_logic;
--! AXI slave PKT write response valid
S_AXI_MAC_PKT_BVALID : out std_logic;
--! AXI slave PKT read valid
S_AXI_MAC_PKT_RVALID : out std_logic;
--! AXI slave PKT write ready
S_AXI_MAC_PKT_WREADY : out std_logic;
--! AXI slave PKT write response
S_AXI_MAC_PKT_BRESP : out std_logic_vector(1 downto 0);
--! AXI slave PKT read data
S_AXI_MAC_PKT_RDATA : out std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
--! AXI slave PKT read response
S_AXI_MAC_PKT_RRESP : out std_logic_vector(1 downto 0);
-----------------------------------------------------------------------
-- MAC DMA memory mapped master
-----------------------------------------------------------------------
--! DMA master clock
M_AXI_MAC_DMA_ACLK : in std_logic;
--! DMA master reset (low-active)
M_AXI_MAC_DMA_ARESETN : in std_logic;
--! AXI master DMA error
M_AXI_MAC_DMA_MD_ERROR : out std_logic;
--! AXI master DMA read address ready
M_AXI_MAC_DMA_ARREADY : in std_logic;
--! AXI master DMA write address ready
M_AXI_MAC_DMA_AWREADY : in std_logic;
--! AXI master DMA write response ready
M_AXI_MAC_DMA_BVALID : in std_logic;
--! AXI master DMA read last
M_AXI_MAC_DMA_RLAST : in std_logic;
--! AXI master DMA read valid
M_AXI_MAC_DMA_RVALID : in std_logic;
--! AXI master DMA write ready
M_AXI_MAC_DMA_WREADY : in std_logic;
--! AXI master DMA write response
M_AXI_MAC_DMA_BRESP : in std_logic_vector(1 downto 0);
--! AXI master DMA read data
M_AXI_MAC_DMA_RDATA : in std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
--! AXI master DMA read response
M_AXI_MAC_DMA_RRESP : in std_logic_vector(1 downto 0);
--! AXI master DMA read address valid
M_AXI_MAC_DMA_ARVALID : out std_logic;
--! AXI master DMA write address valid
M_AXI_MAC_DMA_AWVALID : out std_logic;
--! AXI master DMA response ready
M_AXI_MAC_DMA_BREADY : out std_logic;
--! AXI master DMA read ready
M_AXI_MAC_DMA_RREADY : out std_logic;
--! AXI master DMA write last
M_AXI_MAC_DMA_WLAST : out std_logic;
--! AXI master DMA write valid
M_AXI_MAC_DMA_WVALID : out std_logic;
--! AXI master DMA read address
M_AXI_MAC_DMA_ARADDR : out std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
--! AXI master DMA burst type
M_AXI_MAC_DMA_ARBURST : out std_logic_vector(1 downto 0);
--! AXI master DMA memory type
M_AXI_MAC_DMA_ARCACHE : out std_logic_vector(3 downto 0);
--! AXI master DMA burst length
M_AXI_MAC_DMA_ARLEN : out std_logic_vector(7 downto 0);
--! AXI master DMA protection type
M_AXI_MAC_DMA_ARPROT : out std_logic_vector(2 downto 0);
--! AXI master DMA burst size
M_AXI_MAC_DMA_ARSIZE : out std_logic_vector(2 downto 0);
--! AXI master DMA write address
M_AXI_MAC_DMA_AWADDR : out std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
--! AXI master DMA burst type
M_AXI_MAC_DMA_AWBURST : out std_logic_vector(1 downto 0);
--! AXI master DMA memory type
M_AXI_MAC_DMA_AWCACHE : out std_logic_vector(3 downto 0);
--! AXI master DMA burst length
M_AXI_MAC_DMA_AWLEN : out std_logic_vector(7 downto 0);
--! AXI master DMA protection type
M_AXI_MAC_DMA_AWPROT : out std_logic_vector(2 downto 0);
--! AXI master DMA burst size
M_AXI_MAC_DMA_AWSIZE : out std_logic_vector(2 downto 0);
--! AXI master DMA write data
M_AXI_MAC_DMA_WDATA : out std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
--! AXI master DMA write strobe
M_AXI_MAC_DMA_WSTRB : out std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH/8-1 downto 0);
-----------------------------------------------------------------------
-- Interrupts
-----------------------------------------------------------------------
--! MAC TIMER interrupt
TIMER_IRQ : out std_logic;
--! MAC interrupt
MAC_IRQ : out std_logic;
--! MAC TIMER pulse interrupt
TIMER_PULSE_IRQ : out std_logic;
-----------------------------------------------------------------------
-- Rmii Phy ports
-----------------------------------------------------------------------
--! Rmii Clock ports (optional)
oRmii_clk : out std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Rx Crs data valid ports
iRmii_rxCrsDataValid : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Rx data ports
iRmii_rxData : in std_logic_vector(gPhyPortCount*2-1 downto 0);
--! Rmii Rx error ports
iRmii_rxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Tx enable ports
oRmii_txEnable : out std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Tx data ports
oRmii_txData : out std_logic_vector(gPhyPortCount*2-1 downto 0);
-----------------------------------------------------------------------
-- Mii Phy ports
-----------------------------------------------------------------------
--! Mii Rx data valid ports
iMii_rxDataValid : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Rx data ports
iMii_rxData : in std_logic_vector(gPhyPortCount*4-1 downto 0);
--! Mii Rx error ports
iMii_rxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Rx Clocks
iMii_rxClk : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Tx enable ports
oMii_txEnable : out std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Tx data ports
oMii_txData : out std_logic_vector(gPhyPortCount*4-1 downto 0);
--! Mii Tx Clocks
iMii_txClk : in std_logic_vector(gPhyPortCount-1 downto 0);
-----------------------------------------------------------------------
-- Phy management interface
-----------------------------------------------------------------------
--! Phy reset (low-active)
oSmi_nPhyRst : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI clock
oSmi_clk : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data I/O input
iSmi_dio : in std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data I/O output
oSmi_dio : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data I/O tristate
oSmi_dio_tri : out std_logic;
-----------------------------------------------------------------------
-- Other ports
-----------------------------------------------------------------------
--! Packet activity (enabled with gEnableActivity)
oPktActivity : out std_logic
);
end axi_openmac;
architecture rtl of axi_openmac is
--! Address zero padding vector
constant cZeroPadAddress : std_logic_vector(31 downto 0) := (others => cInactivated);
--! Address array for MAC REG IPIF
constant cMacReg_addressArray : SLV64_ARRAY_TYPE := (
(cZeroPadAddress & C_S_AXI_MAC_REG_RNG0_BASEADDR),
(cZeroPadAddress & C_S_AXI_MAC_REG_RNG0_HIGHADDR),
(cZeroPadAddress & C_S_AXI_MAC_REG_RNG1_BASEADDR),
(cZeroPadAddress & C_S_AXI_MAC_REG_RNG1_HIGHADDR)
);
--! Address array for PKT BUF IPIF
constant cPktBuf_addressArray : SLV64_ARRAY_TYPE := (
(cZeroPadAddress & C_S_AXI_MAC_PKT_BASEADDR),
(cZeroPadAddress & C_S_AXI_MAC_PKT_HIGHADDR)
);
--! Chipselect for MAC REG --> MAC REG
constant cMacReg_csMacReg : natural := 1;
--! Chipselect for MAC REG --> MAC TIMER
constant cMacReg_csMacTimer : natural := 0;
--! Chipselect for PKT BUF
constant cPktBuf_cs : natural := 0;
--! Clock Reset type
type tClkRst is record
clk : std_logic;
rst : std_logic;
regClk : std_logic;
regRst : std_logic;
dmaClk : std_logic;
dmaRst : std_logic;
pktClk : std_logic;
pktRst : std_logic;
clk2x : std_logic;
end record;
--! Mac Reg type
type tMacReg is record
chipselect : std_logic;
write : std_logic;
read : std_logic;
waitrequest : std_logic;
byteenable : std_logic_vector(cMacRegDataWidth/cByteLength-1 downto 0);
address : std_logic_vector(cMacRegAddrWidth-1 downto 0);
writedata : std_logic_vector(cMacRegDataWidth-1 downto 0);
readdata : std_logic_vector(cMacRegDataWidth-1 downto 0);
end record;
--! Mac Timer type
type tMacTimer is record
chipselect : std_logic;
write : std_logic;
read : std_logic;
waitrequest : std_logic;
address : std_logic_vector(cMacTimerAddrWidth-1 downto 0);
byteenable : std_logic_vector(cPktBufDataWidth/cByteLength-1 downto 0);
writedata : std_logic_vector(cMacTimerDataWidth-1 downto 0);
readdata : std_logic_vector(cMacTimerDataWidth-1 downto 0);
end record;
--! Pkt Buf type
type tPktBuf is record
chipselect : std_logic;
write : std_logic;
read : std_logic;
waitrequest : std_logic;
byteenable : std_logic_vector(cPktBufDataWidth/cByteLength-1 downto 0);
address : std_logic_vector(gPacketBufferLog2Size-1 downto 0);
writedata : std_logic_vector(cPktBufDataWidth-1 downto 0);
readdata : std_logic_vector(cPktBufDataWidth-1 downto 0);
end record;
--! Dma type
type tDma is record
write : std_logic;
read : std_logic;
waitrequest : std_logic;
readdatavalid : std_logic;
byteenable : std_logic_vector(gDmaDataWidth/cByteLength-1 downto 0);
address : std_logic_vector(gDmaAddrWidth-1 downto 0);
burstcount : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
burstcounter : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
writedata : std_logic_vector(gDmaDataWidth-1 downto 0);
readdata : std_logic_vector(gDmaDataWidth-1 downto 0);
end record;
--! AXI lite slave for MAC REG
type tAxiSlaveMacReg is record
axi_aclk : std_logic;
axi_aresetn : std_logic;
axi_awaddr : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
axi_awvalid : std_logic;
axi_awready : std_logic;
axi_wdata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
axi_wstrb : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH/8-1 downto 0);
axi_wvalid : std_logic;
axi_wready : std_logic;
axi_bresp : std_logic_vector(1 downto 0);
axi_bvalid : std_logic;
axi_bready : std_logic;
axi_araddr : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
axi_arvalid : std_logic;
axi_arready : std_logic;
axi_rdata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
axi_rresp : std_logic_vector(1 downto 0);
axi_rvalid : std_logic;
axi_rready : std_logic;
ipif_clk : std_logic;
ipif_resetn : std_logic;
ipif_addr : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
ipif_rnw : std_logic;
ipif_be : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH/8-1 downto 0);
ipif_cs : std_logic_vector(((cMacReg_addressArray'length)/2-1) downto 0);
ipif_wrdata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
ipif_rddata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
ipif_wrack : std_logic;
ipif_rdack : std_logic;
ipif_error : std_logic;
end record;
--! AXI lite slave for PKT BUF
type tAxiSlavePktBuf is record
axi_aclk : std_logic;
axi_aresetn : std_logic;
axi_awaddr : std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
axi_awvalid : std_logic;
axi_awready : std_logic;
axi_wdata : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
axi_wstrb : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH/8-1 downto 0);
axi_wvalid : std_logic;
axi_wready : std_logic;
axi_bresp : std_logic_vector(1 downto 0);
axi_bvalid : std_logic;
axi_bready : std_logic;
axi_araddr : std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
axi_arvalid : std_logic;
axi_arready : std_logic;
axi_rdata : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
axi_rresp : std_logic_vector(1 downto 0);
axi_rvalid : std_logic;
axi_rready : std_logic;
ipif_clk : std_logic;
ipif_resetn : std_logic;
ipif_addr : std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
ipif_rnw : std_logic;
ipif_be : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH/8-1 downto 0);
ipif_cs : std_logic_vector(((cPktBuf_addressArray'length)/2-1) downto 0);
ipif_wrdata : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
ipif_rddata : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
ipif_wrack : std_logic;
ipif_rdack : std_logic;
ipif_error : std_logic;
end record;
--! AXI master for DMA
type tAxiMasterDma is record
axi_aclk : std_logic;
axi_aresetn : std_logic;
md_error : std_logic;
axi_arready : std_logic;
axi_arvalid : std_logic;
axi_araddr : std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
axi_arlen : std_logic_vector(7 downto 0);
axi_arsize : std_logic_vector(2 downto 0);
axi_arburst : std_logic_vector(1 downto 0);
axi_arprot : std_logic_vector(2 downto 0);
axi_arcache : std_logic_vector(3 downto 0);
axi_rready : std_logic;
axi_rvalid : std_logic;
axi_rdata : std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
axi_rresp : std_logic_vector(1 downto 0);
axi_rlast : std_logic;
axi_awready : std_logic;
axi_awvalid : std_logic;
axi_awaddr : std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
axi_awlen : std_logic_vector(7 downto 0);
axi_awsize : std_logic_vector(2 downto 0);
axi_awburst : std_logic_vector(1 downto 0);
axi_awprot : std_logic_vector(2 downto 0);
axi_awcache : std_logic_vector(3 downto 0);
axi_wready : std_logic;
axi_wvalid : std_logic;
axi_wdata : std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
axi_wstrb : std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH/8-1 downto 0);
axi_wlast : std_logic;
axi_bready : std_logic;
axi_bvalid : std_logic;
axi_bresp : std_logic_vector(1 downto 0);
ipif_mstrd_req : std_logic;
ipif_mstwr_req : std_logic;
ipif_mst_addr : std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
ipif_mst_length : std_logic_vector(C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0);
ipif_mst_be : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8-1 downto 0);
ipif_mst_type : std_logic;
ipif_mst_lock : std_logic;
ipif_mst_reset : std_logic;
ipif_mst_cmdack : std_logic;
ipif_mst_cmplt : std_logic;
ipif_mst_error : std_logic;
ipif_mst_rearbitrate : std_logic;
ipif_mst_cmd_timeout : std_logic;
ipif_mstrd_d : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 );
ipif_mstrd_rem : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8-1 downto 0);
ipif_mstrd_sof_n : std_logic;
ipif_mstrd_eof_n : std_logic;
ipif_mstrd_src_rdy_n : std_logic;
ipif_mstrd_src_dsc_n : std_logic;
ipif_mstrd_dst_rdy_n : std_logic;
ipif_mstrd_dst_dsc_n : std_logic;
ipif_mstwr_d : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0);
ipif_mstwr_rem : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8-1 downto 0);
ipif_mstwr_sof_n : std_logic;
ipif_mstwr_eof_n : std_logic;
ipif_mstwr_src_rdy_n : std_logic;
ipif_mstwr_src_dsc_n : std_logic;
ipif_mstwr_dst_rdy_n : std_logic;
ipif_mstwr_dst_dsc_n : std_logic;
end record;
--! Clock xing for MAC REG port
type tClkXingMacRegPort is record
clk : std_logic;
cs : std_logic_vector(((cMacReg_addressArray'length)/2-1) downto 0);
rnw : std_logic;
readdata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
wrAck : std_logic;
rdAck : std_logic;
end record;
--! Clock xing for MAC REG
type tClkXingMacReg is record
rst : std_logic;
fast : tClkXingMacRegPort;
slow : tClkXingMacRegPort;
end record;
--! Data width converter for MAC REG
type tConvMacReg is record
rst : std_logic;
clk : std_logic;
master_select : std_logic;
master_write : std_logic;
master_read : std_logic;
master_byteenable : std_logic_vector(3 downto 0);
master_writedata : std_logic_vector(31 downto 0);
master_readdata : std_logic_vector(31 downto 0);
master_address : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
master_WriteAck : std_logic;
master_ReadAck : std_logic;
slave_select : std_logic;
slave_write : std_logic;
slave_read : std_logic;
slave_address : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
slave_byteenable : std_logic_vector(1 downto 0);
slave_readdata : std_logic_vector(15 downto 0);
slave_writedata : std_logic_vector(15 downto 0);
slave_ack : std_logic;
end record;
--! IPIF handler for MAC DMA
type tIpifMasterHandler is record
rst : std_logic;
clk : std_logic;
ipif_cmdAck : std_logic;
ipif_cmplt : std_logic;
ipif_error : std_logic;
ipif_rearbitrate : std_logic;
ipif_cmdTimeout : std_logic;
ipif_type : std_logic;
ipif_addr : std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
ipif_length : std_logic_vector(C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0);
ipif_be : std_logic_vector(3 downto 0);
ipif_lock : std_logic;
ipif_reset : std_logic;
ipif_rdData : std_logic_vector(31 downto 0);
ipif_rdRem : std_logic_vector(3 downto 0);
ipif_rdReq : std_logic;
nIpif_rdSof : std_logic;
nIpif_rdEof : std_logic;
nIpif_rdSrcRdy : std_logic;
nIpif_rdSrcDsc : std_logic;
nIpif_rdDstRdy : std_logic;
nIpif_rdDstDsc : std_logic;
ipif_wrData : std_logic_vector(31 downto 0);
ipif_wrRem : std_logic_vector(3 downto 0);
ipif_wrReq : std_logic;
nIpif_wrSof : std_logic;
nIpif_wrEof : std_logic;
nIpif_wrSrcRdy : std_logic;
nIpif_wrSrcDsc : std_logic;
nIpif_wrDstRdy : std_logic;
nIpif_wrDstDsc : std_logic;
masterRead : std_logic;
masterWrite : std_logic;
masterAddress : std_logic_vector(gDmaAddrWidth-1 downto 0);
masterWritedata : std_logic_vector(31 downto 0);
masterBurstcount : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
masterBurstcounter : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
masterReaddata : std_logic_vector(31 downto 0);
masterWaitrequest : std_logic;
masterReaddatavalid : std_logic;
end record;
--! Clock and resets
signal intf_clkRst : tClkRst;
--! Mac Reg
signal intf_macReg : tMacReg;
--! Mac Timer
signal intf_macTimer : tMacTimer;
--! Packet buffer
signal intf_pktBuf : tPktBuf;
--! Dma
signal intf_dma : tDma;
--! Mac Reg IPIF
signal ipif_macReg : tAxiSlaveMacReg;
--! Packet buffer IPIF
signal ipif_pktBuf : tAxiSlavePktBuf;
--! Dma IPIF
signal ipif_dma : tAxiMasterDma;
--! Clock Xing for MAC REG IPIF
signal xing_macReg : tClkXingMacReg;
--! Dara width converter for MAC REG IPIF
signal conv_macReg : tConvMacReg;
--! Dma IPIF master handler
signal ipif_dmaMasterHdler : tIpifMasterHandler;
--! Mac Tx interrupt
signal macTx_interrupt : std_logic;
--! Mac Rx interrupt
signal macRx_interrupt : std_logic;
--! Rmii Tx path
signal rmiiTx : tRmiiPathArray(gPhyPortCount-1 downto 0);
--! Rmii Rx path
signal rmiiRx : tRmiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Tx path
signal miiTx : tMiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Rx path
signal miiRx : tMiiPathArray(gPhyPortCount-1 downto 0);
--! Smi tri-state-buffer input
signal smi_data_in : std_logic_vector(gSmiPortCount-1 downto 0);
--! Smi tri-state-buffer output
signal smi_data_out : std_logic_vector(gSmiPortCount-1 downto 0);
--! Smi tri-state-buffer output enable
signal smi_data_outEnable : std_logic;
begin
---------------------------------------------------------------------------
-- Map outputs
---------------------------------------------------------------------------
-- Mac interrupts are or'd to single line.
MAC_IRQ <= macTx_interrupt or macRx_interrupt;
-- Phy Tx path
rmiiPathArrayToStdLogicVector(
iVector => rmiiTx,
oEnable => oRmii_txEnable,
oData => oRmii_txData
);
miiPathArrayToStdLogicVector(
iVector => miiTx,
oEnable => oMii_txEnable,
oData => oMii_txData
);
---------------------------------------------------------------------------
-- Map inputs
---------------------------------------------------------------------------
-- Clock and resets
intf_clkRst.clk <= iClk50;
intf_clkRst.clk2x <= iClk100;
intf_clkRst.regClk <= S_AXI_MAC_REG_ACLK;
intf_clkRst.pktClk <= S_AXI_MAC_PKT_ACLK;
intf_clkRst.dmaClk <= M_AXI_MAC_DMA_ACLK;
intf_clkRst.rst <= not S_AXI_MAC_REG_ARESETN;
intf_clkRst.regRst <= not S_AXI_MAC_REG_ARESETN;
intf_clkRst.pktRst <= not S_AXI_MAC_PKT_ARESETN;
intf_clkRst.dmaRst <= not M_AXI_MAC_DMA_ARESETN;
-- Phy Rx path
stdLogicVectorToRmiiPathArray(
iEnable => iRmii_rxCrsDataValid,
iData => iRmii_rxData,
oVector => rmiiRx
);
stdLogicVectorToMiiPathArray(
iEnable => iMii_rxDataValid,
iData => iMii_rxData,
oVector => miiRx
);
---------------------------------------------------------------------------
-- Map IOs
---------------------------------------------------------------------------
-- Assign SMI IO (the tristate buffer shall be assigned by toplevel)
oSmi_dio <= smi_data_out;
oSmi_dio_tri <= not smi_data_outEnable;
smi_data_in <= iSmi_dio;
---------------------------------------------------------------------------
-- Map Instances
---------------------------------------------------------------------------
-- MAC REG --> ipif_macReg
ipif_macReg.axi_aclk <= intf_clkRst.regClk;
ipif_macReg.axi_aresetn <= not intf_clkRst.regRst;
ipif_macReg.axi_awaddr <= S_AXI_MAC_REG_AWADDR;
ipif_macReg.axi_awvalid <= S_AXI_MAC_REG_AWVALID;
S_AXI_MAC_REG_AWREADY <= ipif_macReg.axi_awready;
ipif_macReg.axi_wdata <= S_AXI_MAC_REG_WDATA;
ipif_macReg.axi_wstrb <= S_AXI_MAC_REG_WSTRB;
ipif_macReg.axi_wvalid <= S_AXI_MAC_REG_WVALID;
S_AXI_MAC_REG_WREADY <= ipif_macReg.axi_wready;
S_AXI_MAC_REG_BRESP <= ipif_macReg.axi_bresp;
S_AXI_MAC_REG_BVALID <= ipif_macReg.axi_bvalid;
ipif_macReg.axi_bready <= S_AXI_MAC_REG_BREADY;
ipif_macReg.axi_araddr <= S_AXI_MAC_REG_ARADDR;
ipif_macReg.axi_arvalid <= S_AXI_MAC_REG_ARVALID;
S_AXI_MAC_REG_ARREADY <= ipif_macReg.axi_arready;
S_AXI_MAC_REG_RDATA <= ipif_macReg.axi_rdata;
S_AXI_MAC_REG_RRESP <= ipif_macReg.axi_rresp;
S_AXI_MAC_REG_RVALID <= ipif_macReg.axi_rvalid;
ipif_macReg.axi_rready <= S_AXI_MAC_REG_RREADY;
-- xing_macReg <-- conv_macReg or intf_macTimer
--! This process assigns the read and ack path from macReg and macTimer
--! to the clock crossing slow inputs, depending on the selected target.
ASSIGN_XING_MACREG : process (conv_macReg, intf_macTimer)
begin
-- default is MAC REG source
xing_macReg.slow.readdata <= conv_macReg.master_readdata;
xing_macReg.slow.wrAck <= conv_macReg.master_WriteAck;
xing_macReg.slow.rdAck <= conv_macReg.master_ReadAck;
if intf_macTimer.chipselect = cActivated then
xing_macReg.slow.readdata <= intf_macTimer.readdata;
xing_macReg.slow.wrAck <= intf_macTimer.write and not intf_macTimer.waitrequest;
xing_macReg.slow.rdAck <= intf_macTimer.read and not intf_macTimer.waitrequest;
end if;
end process ASSIGN_XING_MACREG;
-- ipif_macReg --> xing_macReg
--unused output: ipif_macReg.ipif_resetn;
xing_macReg.rst <= intf_clkRst.regRst;
xing_macReg.fast.clk <= ipif_macReg.ipif_clk;
xing_macReg.slow.clk <= intf_clkRst.clk;
xing_macReg.fast.rnw <= ipif_macReg.ipif_rnw;
xing_macReg.fast.cs <= ipif_macReg.ipif_cs;
ipif_macReg.ipif_rddata <= xing_macReg.fast.readdata;
ipif_macReg.ipif_wrack <= xing_macReg.fast.wrAck;
ipif_macReg.ipif_rdack <= xing_macReg.fast.rdAck;
ipif_macReg.ipif_error <= cInactivated; --unused
-- ipif_macReg --> conv_macReg | xing_macReg --> conv_macReg
conv_macReg.rst <= intf_clkRst.rst;
conv_macReg.clk <= intf_clkRst.clk;
conv_macReg.master_select <= xing_macReg.slow.cs(cMacReg_csMacReg);
conv_macReg.master_write <= not xing_macReg.slow.rnw;
conv_macReg.master_read <= xing_macReg.slow.rnw;
conv_macReg.master_byteenable <= ipif_macReg.ipif_be;
conv_macReg.master_writedata <= ipif_macReg.ipif_wrdata;
conv_macReg.master_address <= ipif_macReg.ipif_addr(conv_macReg.master_address'range);
-- conv_macReg --> intf_macReg
intf_macReg.chipselect <= conv_macReg.slave_select;
intf_macReg.write <= conv_macReg.slave_write;
intf_macReg.read <= conv_macReg.slave_read;
intf_macReg.address <= conv_macReg.slave_address(intf_macReg.address'range);
intf_macReg.byteenable <= conv_macReg.slave_byteenable;
conv_macReg.slave_readdata <= intf_macReg.readdata;
intf_macReg.writedata <= conv_macReg.slave_writedata;
conv_macReg.slave_ack <= not intf_macReg.waitrequest;
-- ipif_macReg --> intf_macTimer | xing_macReg --> intf_macTimer
intf_macTimer.chipselect <= xing_macReg.slow.cs(cMacReg_csMacTimer);
intf_macTimer.write <= not xing_macReg.slow.rnw;
intf_macTimer.read <= xing_macReg.slow.rnw;
intf_macTimer.address <= ipif_macReg.ipif_addr(intf_macTimer.address'range);
intf_macTimer.byteenable <= ipif_macReg.ipif_be;
intf_macTimer.writedata <= ipif_macReg.ipif_wrdata;
-- MAC PKT --> ipif_pktBuf
ipif_pktBuf.axi_aclk <= intf_clkRst.pktClk;
ipif_pktBuf.axi_aresetn <= not intf_clkRst.pktRst;
ipif_pktBuf.axi_awaddr <= S_AXI_MAC_PKT_AWADDR;
ipif_pktBuf.axi_awvalid <= S_AXI_MAC_PKT_AWVALID;
S_AXI_MAC_PKT_AWREADY <= ipif_pktBuf.axi_awready;
ipif_pktBuf.axi_wdata <= S_AXI_MAC_PKT_WDATA;
ipif_pktBuf.axi_wstrb <= S_AXI_MAC_PKT_WSTRB;
ipif_pktBuf.axi_wvalid <= S_AXI_MAC_PKT_WVALID;
S_AXI_MAC_PKT_WREADY <= ipif_pktBuf.axi_wready;
S_AXI_MAC_PKT_BRESP <= ipif_pktBuf.axi_bresp;
S_AXI_MAC_PKT_BVALID <= ipif_pktBuf.axi_bvalid;
ipif_pktBuf.axi_bready <= S_AXI_MAC_PKT_BREADY;
ipif_pktBuf.axi_araddr <= S_AXI_MAC_PKT_ARADDR;
ipif_pktBuf.axi_arvalid <= S_AXI_MAC_PKT_ARVALID;
S_AXI_MAC_PKT_ARREADY <= ipif_pktBuf.axi_arready;
S_AXI_MAC_PKT_RDATA <= ipif_pktBuf.axi_rdata;
S_AXI_MAC_PKT_RRESP <= ipif_pktBuf.axi_rresp;
S_AXI_MAC_PKT_RVALID <= ipif_pktBuf.axi_rvalid;
ipif_pktBuf.axi_rready <= S_AXI_MAC_PKT_RREADY;
-- ipif_pktBuf --> intf_pktBuf
--unused output: ipif_pktBuf.ipif_clk
--unused output: ipif_pktBuf.ipif_resetn
intf_pktBuf.address <= ipif_pktBuf.ipif_addr(intf_pktBuf.address'range);
intf_pktBuf.write <= not ipif_pktBuf.ipif_rnw;
intf_pktBuf.read <= ipif_pktBuf.ipif_rnw;
intf_pktBuf.byteenable <= ipif_pktBuf.ipif_be;
intf_pktBuf.chipselect <= ipif_pktBuf.ipif_cs(cPktBuf_cs);
intf_pktBuf.writedata <= ipif_pktBuf.ipif_wrdata;
ipif_pktBuf.ipif_rddata <= intf_pktBuf.readdata;
ipif_pktBuf.ipif_wrack <= intf_pktBuf.chipselect and intf_pktBuf.write and not intf_pktBuf.waitrequest;
ipif_pktBuf.ipif_rdack <= intf_pktBuf.chipselect and intf_pktBuf.read and not intf_pktBuf.waitrequest;
ipif_pktBuf.ipif_error <= cInactivated; --unused
-- MAC DMA --> ipif_dma
ipif_dma.axi_aclk <= intf_clkRst.dmaClk;
ipif_dma.axi_aresetn <= not intf_clkRst.dmaRst;
M_AXI_MAC_DMA_MD_ERROR <= ipif_dma.md_error;
ipif_dma.axi_arready <= M_AXI_MAC_DMA_ARREADY;
M_AXI_MAC_DMA_ARVALID <= ipif_dma.axi_arvalid;
M_AXI_MAC_DMA_ARADDR <= ipif_dma.axi_araddr;
M_AXI_MAC_DMA_ARLEN <= ipif_dma.axi_arlen;
M_AXI_MAC_DMA_ARSIZE <= ipif_dma.axi_arsize;
M_AXI_MAC_DMA_ARBURST <= ipif_dma.axi_arburst;
M_AXI_MAC_DMA_ARPROT <= ipif_dma.axi_arprot;
M_AXI_MAC_DMA_ARCACHE <= ipif_dma.axi_arcache;
M_AXI_MAC_DMA_RREADY <= ipif_dma.axi_rready;
ipif_dma.axi_rvalid <= M_AXI_MAC_DMA_RVALID;
ipif_dma.axi_rdata <= M_AXI_MAC_DMA_RDATA;
ipif_dma.axi_rresp <= M_AXI_MAC_DMA_RRESP;
ipif_dma.axi_rlast <= M_AXI_MAC_DMA_RLAST;
ipif_dma.axi_awready <= M_AXI_MAC_DMA_AWREADY;
M_AXI_MAC_DMA_AWVALID <= ipif_dma.axi_awvalid;
M_AXI_MAC_DMA_AWADDR <= ipif_dma.axi_awaddr;
M_AXI_MAC_DMA_AWLEN <= ipif_dma.axi_awlen;
M_AXI_MAC_DMA_AWSIZE <= ipif_dma.axi_awsize;
M_AXI_MAC_DMA_AWBURST <= ipif_dma.axi_awburst;
M_AXI_MAC_DMA_AWPROT <= ipif_dma.axi_awprot;
M_AXI_MAC_DMA_AWCACHE <= ipif_dma.axi_awcache;
ipif_dma.axi_wready <= M_AXI_MAC_DMA_WREADY;
M_AXI_MAC_DMA_WVALID <= ipif_dma.axi_wvalid;
M_AXI_MAC_DMA_WDATA <= ipif_dma.axi_wdata;
M_AXI_MAC_DMA_WSTRB <= ipif_dma.axi_wstrb;
M_AXI_MAC_DMA_WLAST <= ipif_dma.axi_wlast;
M_AXI_MAC_DMA_BREADY <= ipif_dma.axi_bready;
ipif_dma.axi_bvalid <= M_AXI_MAC_DMA_BVALID;
ipif_dma.axi_bresp <= M_AXI_MAC_DMA_BRESP;
-- ipif_dma --> ipif_dmaMasterHdler
ipif_dmaMasterHdler.rst <= intf_clkRst.dmaRst;
ipif_dmaMasterHdler.clk <= intf_clkRst.dmaClk;
ipif_dma.ipif_mstrd_req <= ipif_dmaMasterHdler.ipif_rdReq;
ipif_dma.ipif_mstwr_req <= ipif_dmaMasterHdler.ipif_wrReq;
ipif_dma.ipif_mst_addr <= ipif_dmaMasterHdler.ipif_addr(ipif_dma.ipif_mst_addr'range);
ipif_dma.ipif_mst_length <= ipif_dmaMasterHdler.ipif_length;
ipif_dma.ipif_mst_be <= ipif_dmaMasterHdler.ipif_be;
ipif_dma.ipif_mst_type <= ipif_dmaMasterHdler.ipif_type;
ipif_dma.ipif_mst_lock <= ipif_dmaMasterHdler.ipif_lock;
ipif_dma.ipif_mst_reset <= ipif_dmaMasterHdler.ipif_reset;
ipif_dmaMasterHdler.ipif_cmdAck <= ipif_dma.ipif_mst_cmdack;
ipif_dmaMasterHdler.ipif_cmplt <= ipif_dma.ipif_mst_cmplt;
ipif_dmaMasterHdler.ipif_error <= ipif_dma.ipif_mst_error;
ipif_dmaMasterHdler.ipif_rearbitrate <= ipif_dma.ipif_mst_rearbitrate;
ipif_dmaMasterHdler.ipif_cmdTimeout <= ipif_dma.ipif_mst_cmd_timeout;
ipif_dmaMasterHdler.ipif_rdData <= ipif_dma.ipif_mstrd_d;
ipif_dmaMasterHdler.ipif_rdRem <= ipif_dma.ipif_mstrd_rem;
ipif_dmaMasterHdler.nIpif_rdSof <= ipif_dma.ipif_mstrd_sof_n;
ipif_dmaMasterHdler.nIpif_rdEof <= ipif_dma.ipif_mstrd_eof_n;
ipif_dmaMasterHdler.nIpif_rdSrcRdy <= ipif_dma.ipif_mstrd_src_rdy_n;
ipif_dmaMasterHdler.nIpif_rdSrcDsc <= ipif_dma.ipif_mstrd_src_dsc_n;
ipif_dma.ipif_mstrd_dst_rdy_n <= ipif_dmaMasterHdler.nIpif_rdDstRdy;
ipif_dma.ipif_mstrd_dst_dsc_n <= ipif_dmaMasterHdler.nIpif_rdDstDsc;
ipif_dma.ipif_mstwr_d <= ipif_dmaMasterHdler.ipif_wrData;
ipif_dma.ipif_mstwr_rem <= ipif_dmaMasterHdler.ipif_wrRem;
ipif_dma.ipif_mstwr_sof_n <= ipif_dmaMasterHdler.nIpif_wrSof;
ipif_dma.ipif_mstwr_eof_n <= ipif_dmaMasterHdler.nIpif_wrEof;
ipif_dma.ipif_mstwr_src_rdy_n <= ipif_dmaMasterHdler.nIpif_wrSrcRdy;
ipif_dma.ipif_mstwr_src_dsc_n <= ipif_dmaMasterHdler.nIpif_wrSrcDsc;
ipif_dmaMasterHdler.nIpif_wrDstRdy <= ipif_dma.ipif_mstwr_dst_rdy_n;
ipif_dmaMasterHdler.nIpif_wrDstDsc <= ipif_dma.ipif_mstwr_dst_dsc_n;
-- ipif_dmaMasterHdler --> intf_dma
ipif_dmaMasterHdler.masterRead <= intf_dma.read;
ipif_dmaMasterHdler.masterWrite <= intf_dma.write;
ipif_dmaMasterHdler.masterAddress <= intf_dma.address;
ipif_dmaMasterHdler.masterWritedata <= intf_dma.writedata;
ipif_dmaMasterHdler.masterBurstcount <= intf_dma.burstcount;
ipif_dmaMasterHdler.masterBurstcounter <= intf_dma.burstcounter;
intf_dma.readdata <= ipif_dmaMasterHdler.masterReaddata;
intf_dma.waitrequest <= ipif_dmaMasterHdler.masterWaitrequest;
intf_dma.readdatavalid <= ipif_dmaMasterHdler.masterReaddatavalid;
---------------------------------------------------------------------------
-- Instantiations
---------------------------------------------------------------------------
--! This is the openMAC toplevel instantiation.
THEOPENMACTOP : entity work.openmacTop
generic map (
gPhyPortCount => gPhyPortCount,
gPhyPortType => gPhyPortType,
gSmiPortCount => gSmiPortCount,
gEndianness => gEndianness,
gEnableActivity => gEnableActivity,
gEnableDmaObserver => gEnableDmaObserver,
gDmaAddrWidth => gDmaAddrWidth,
gDmaDataWidth => gDmaDataWidth,
gDmaBurstCountWidth => gDmaBurstCountWidth,
gDmaWriteBurstLength => gDmaWriteBurstLength,
gDmaReadBurstLength => gDmaReadBurstLength,
gDmaWriteFifoLength => gDmaWriteFifoLength,
gDmaReadFifoLength => gDmaReadFifoLength,
gPacketBufferLocTx => gPacketBufferLocTx,
gPacketBufferLocRx => gPacketBufferLocRx,
gPacketBufferLog2Size => gPacketBufferLog2Size,
gTimerEnablePulse => gTimerEnablePulse,
gTimerEnablePulseWidth => gTimerEnablePulseWidth,
gTimerPulseRegWidth => gTimerPulseRegWidth
)
port map (
iClk => intf_clkRst.clk,
iRst => intf_clkRst.rst,
iDmaClk => intf_clkRst.dmaClk,
iDmaRst => intf_clkRst.dmaRst,
iPktBufClk => intf_clkRst.pktClk,
iPktBufRst => intf_clkRst.pktRst,
iClk2x => intf_clkRst.clk2x,
iMacReg_chipselect => intf_macReg.chipselect,
iMacReg_write => intf_macReg.write,
iMacReg_read => intf_macReg.read,
oMacReg_waitrequest => intf_macReg.waitrequest,
iMacReg_byteenable => intf_macReg.byteenable,
iMacReg_address => intf_macReg.address,
iMacReg_writedata => intf_macReg.writedata,
oMacReg_readdata => intf_macReg.readdata,
iMacTimer_chipselect => intf_macTimer.chipselect,
iMacTimer_write => intf_macTimer.write,
iMacTimer_read => intf_macTimer.read,
oMacTimer_waitrequest => intf_macTimer.waitrequest,
iMacTimer_address => intf_macTimer.address,
iMacTimer_byteenable => intf_macTimer.byteenable,
iMacTimer_writedata => intf_macTimer.writedata,
oMacTimer_readdata => intf_macTimer.readdata,
iPktBuf_chipselect => intf_pktBuf.chipselect,
iPktBuf_write => intf_pktBuf.write,
iPktBuf_read => intf_pktBuf.read,
oPktBuf_waitrequest => intf_pktBuf.waitrequest,
iPktBuf_byteenable => intf_pktBuf.byteenable,
iPktBuf_address => intf_pktBuf.address,
iPktBuf_writedata => intf_pktBuf.writedata,
oPktBuf_readdata => intf_pktBuf.readdata,
oDma_write => intf_dma.write,
oDma_read => intf_dma.read,
iDma_waitrequest => intf_dma.waitrequest,
iDma_readdatavalid => intf_dma.readdatavalid,
oDma_byteenable => intf_dma.byteenable,
oDma_address => intf_dma.address,
oDma_burstcount => intf_dma.burstcount,
oDma_burstcounter => intf_dma.burstcounter,
oDma_writedata => intf_dma.writedata,
iDma_readdata => intf_dma.readdata,
oMacTimer_interrupt => TIMER_IRQ,
oMacTimer_pulse => TIMER_PULSE_IRQ,
oMacTx_interrupt => macTx_interrupt,
oMacRx_interrupt => macRx_interrupt,
iRmii_Rx => rmiiRx,
iRmii_RxError => iRmii_rxError,
oRmii_Tx => rmiiTx,
iMii_Rx => miiRx,
iMii_RxError => iMii_rxError,
iMii_RxClk => iMii_rxClk,
oMii_Tx => miiTx,
iMii_TxClk => iMii_txClk,
onPhy_reset => oSmi_nPhyRst,
oSmi_clk => oSmi_clk,
oSmi_data_outEnable => smi_data_outEnable,
oSmi_data_out => smi_data_out,
iSmi_data_in => smi_data_in,
oActivity => oPktActivity
);
--! The MAC REG AXI lite IPIF converts the AXI interface to IPIF.
THEMACREG_AXILITE : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_MAC_REG_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_MAC_REG_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MAC_REG_MIN_SIZE,
C_USE_WSTRB => C_S_AXI_MAC_REG_USE_WSTRB,
C_DPHASE_TIMEOUT => C_S_AXI_MAC_REG_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => cMacReg_addressArray,
C_ARD_NUM_CE_ARRAY => (1, 1),
C_FAMILY => C_FAMILY
)
port map (
S_AXI_ACLK => ipif_macReg.axi_aclk,
S_AXI_ARESETN => ipif_macReg.axi_aresetn,
S_AXI_AWADDR => ipif_macReg.axi_awaddr,
S_AXI_AWVALID => ipif_macReg.axi_awvalid,
S_AXI_AWREADY => ipif_macReg.axi_awready,
S_AXI_WDATA => ipif_macReg.axi_wdata,
S_AXI_WSTRB => ipif_macReg.axi_wstrb,
S_AXI_WVALID => ipif_macReg.axi_wvalid,
S_AXI_WREADY => ipif_macReg.axi_wready,
S_AXI_BRESP => ipif_macReg.axi_bresp,
S_AXI_BVALID => ipif_macReg.axi_bvalid,
S_AXI_BREADY => ipif_macReg.axi_bready,
S_AXI_ARADDR => ipif_macReg.axi_araddr,
S_AXI_ARVALID => ipif_macReg.axi_arvalid,
S_AXI_ARREADY => ipif_macReg.axi_arready,
S_AXI_RDATA => ipif_macReg.axi_rdata,
S_AXI_RRESP => ipif_macReg.axi_rresp,
S_AXI_RVALID => ipif_macReg.axi_rvalid,
S_AXI_RREADY => ipif_macReg.axi_rready,
Bus2IP_Clk => ipif_macReg.ipif_clk,
Bus2IP_Resetn => ipif_macReg.ipif_resetn,
Bus2IP_Addr => ipif_macReg.ipif_addr,
Bus2IP_RNW => ipif_macReg.ipif_rnw,
Bus2IP_BE => ipif_macReg.ipif_be,
Bus2IP_CS => ipif_macReg.ipif_cs,
Bus2IP_RdCE => open, --don't need that feature
Bus2IP_WrCE => open, --don't need that feature
Bus2IP_Data => ipif_macReg.ipif_wrdata,
IP2Bus_Data => ipif_macReg.ipif_rddata,
IP2Bus_WrAck => ipif_macReg.ipif_wrack,
IP2Bus_RdAck => ipif_macReg.ipif_rdack,
IP2Bus_Error => ipif_macReg.ipif_error
);
GEN_THEMACREG_CLKXING : if C_S_AXI_MAC_REG_CLK_XING = cTrue generate
--! The clock Xing ipcore transfers the signals in the AXI clock domain to
--! the iClk50 domain.
THEMACREG_CLKXING : entity libcommon.clkXing
generic map (
gCsNum => xing_macReg.fast.cs'length,
gDataWidth => xing_macReg.fast.readdata'length
)
port map (
iArst => xing_macReg.rst,
iFastClk => xing_macReg.fast.clk,
iFastCs => xing_macReg.fast.cs,
iFastRNW => xing_macReg.fast.rnw,
oFastReaddata => xing_macReg.fast.readdata,
oFastWrAck => xing_macReg.fast.wrAck,
oFastRdAck => xing_macReg.fast.rdAck,
iSlowClk => xing_macReg.slow.clk,
oSlowCs => xing_macReg.slow.cs,
oSlowRNW => xing_macReg.slow.rnw,
iSlowReaddata => xing_macReg.slow.readdata,
iSlowWrAck => xing_macReg.slow.wrAck,
iSlowRdAck => xing_macReg.slow.rdAck
);
end generate GEN_THEMACREG_CLKXING;
GEN_NO_MACREG_CLKXING : if C_S_AXI_MAC_REG_CLK_XING = cFalse generate
xing_macReg.slow.cs <= xing_macReg.fast.cs;
xing_macReg.slow.rnw <= xing_macReg.fast.rnw;
xing_macReg.fast.readdata <= xing_macReg.slow.readdata;
xing_macReg.fast.wrAck <= xing_macReg.slow.wrAck;
xing_macReg.fast.rdAck <= xing_macReg.slow.rdAck;
end generate GEN_NO_MACREG_CLKXING;
--! The memory mapped slave converter changes from AXI's data width to 16 bit.
THEMACREG_MMCONV : entity work.mmSlaveConv
generic map (
gEndian => gEndianness,
gMasterAddrWidth => conv_macReg.master_address'length
)
port map (
iRst => conv_macReg.rst,
iClk => conv_macReg.clk,
iMaster_select => conv_macReg.master_select,
iMaster_write => conv_macReg.master_write,
iMaster_read => conv_macReg.master_read,
iMaster_byteenable => conv_macReg.master_byteenable,
iMaster_writedata => conv_macReg.master_writedata,
oMaster_readdata => conv_macReg.master_readdata,
iMaster_address => conv_macReg.master_address,
oMaster_WriteAck => conv_macReg.master_WriteAck,
oMaster_ReadAck => conv_macReg.master_ReadAck,
oSlave_select => conv_macReg.slave_select,
oSlave_write => conv_macReg.slave_write,
oSlave_read => conv_macReg.slave_read,
oSlave_address => conv_macReg.slave_address,
oSlave_byteenable => conv_macReg.slave_byteenable,
iSlave_readdata => conv_macReg.slave_readdata,
oSlave_writedata => conv_macReg.slave_writedata,
iSlave_ack => conv_macReg.slave_ack
);
--! Generate the packet buffer IPIF if any location is set to local.
GEN_THEMACPKT : if gPacketBufferLocRx = cPktBufLocal or gPacketBufferLocTx = cPktBufLocal generate
--! The MAC PKT BUF AXI lite IPIF converts the AXI interface to IPIF.
THEMACREG_AXILITE : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_MAC_PKT_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_MAC_PKT_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MAC_PKT_MIN_SIZE,
C_USE_WSTRB => C_S_AXI_MAC_PKT_USE_WSTRB,
C_DPHASE_TIMEOUT => C_S_AXI_MAC_PKT_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => cPktBuf_addressArray,
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_FAMILY => C_FAMILY
)
port map (
S_AXI_ACLK => ipif_pktBuf.axi_aclk,
S_AXI_ARESETN => ipif_pktBuf.axi_aresetn,
S_AXI_AWADDR => ipif_pktBuf.axi_awaddr,
S_AXI_AWVALID => ipif_pktBuf.axi_awvalid,
S_AXI_AWREADY => ipif_pktBuf.axi_awready,
S_AXI_WDATA => ipif_pktBuf.axi_wdata,
S_AXI_WSTRB => ipif_pktBuf.axi_wstrb,
S_AXI_WVALID => ipif_pktBuf.axi_wvalid,
S_AXI_WREADY => ipif_pktBuf.axi_wready,
S_AXI_BRESP => ipif_pktBuf.axi_bresp,
S_AXI_BVALID => ipif_pktBuf.axi_bvalid,
S_AXI_BREADY => ipif_pktBuf.axi_bready,
S_AXI_ARADDR => ipif_pktBuf.axi_araddr,
S_AXI_ARVALID => ipif_pktBuf.axi_arvalid,
S_AXI_ARREADY => ipif_pktBuf.axi_arready,
S_AXI_RDATA => ipif_pktBuf.axi_rdata,
S_AXI_RRESP => ipif_pktBuf.axi_rresp,
S_AXI_RVALID => ipif_pktBuf.axi_rvalid,
S_AXI_RREADY => ipif_pktBuf.axi_rready,
Bus2IP_Clk => ipif_pktBuf.ipif_clk,
Bus2IP_Resetn => ipif_pktBuf.ipif_resetn,
Bus2IP_Addr => ipif_pktBuf.ipif_addr,
Bus2IP_RNW => ipif_pktBuf.ipif_rnw,
Bus2IP_BE => ipif_pktBuf.ipif_be,
Bus2IP_CS => ipif_pktBuf.ipif_cs,
Bus2IP_RdCE => open, --don't need that feature
Bus2IP_WrCE => open, --don't need that feature
Bus2IP_Data => ipif_pktBuf.ipif_wrdata,
IP2Bus_Data => ipif_pktBuf.ipif_rddata,
IP2Bus_WrAck => ipif_pktBuf.ipif_wrack,
IP2Bus_RdAck => ipif_pktBuf.ipif_rdack,
IP2Bus_Error => ipif_pktBuf.ipif_error
);
end generate GEN_THEMACPKT;
GEN_THEMACDMA : if gPacketBufferLocRx = cPktBufExtern or gPacketBufferLocTx = cPktBufExtern generate
--! The MAC DMA AXI master IPIF converts the AXI interface to IPIF.
THEMACDMA_AXI : entity axi_master_burst_v2_0_7.axi_master_burst
generic map (
C_M_AXI_ADDR_WIDTH => C_M_AXI_MAC_DMA_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_MAC_DMA_DATA_WIDTH,
C_MAX_BURST_LEN => C_M_AXI_MAC_DMA_MAX_BURST_LEN,
C_ADDR_PIPE_DEPTH => 1,
C_NATIVE_DATA_WIDTH => C_M_AXI_MAC_DMA_NATIVE_DWIDTH,
C_LENGTH_WIDTH => C_M_AXI_MAC_DMA_LENGTH_WIDTH,
C_FAMILY => C_FAMILY
)
port map (
m_axi_aclk => ipif_dma.axi_aclk,
m_axi_aresetn => ipif_dma.axi_aresetn,
md_error => ipif_dma.md_error,
m_axi_arready => ipif_dma.axi_arready,
m_axi_arvalid => ipif_dma.axi_arvalid,
m_axi_araddr => ipif_dma.axi_araddr,
m_axi_arlen => ipif_dma.axi_arlen,
m_axi_arsize => ipif_dma.axi_arsize,
m_axi_arburst => ipif_dma.axi_arburst,
m_axi_arprot => ipif_dma.axi_arprot,
m_axi_arcache => ipif_dma.axi_arcache,
m_axi_rready => ipif_dma.axi_rready,
m_axi_rvalid => ipif_dma.axi_rvalid,
m_axi_rdata => ipif_dma.axi_rdata,
m_axi_rresp => ipif_dma.axi_rresp,
m_axi_rlast => ipif_dma.axi_rlast,
m_axi_awready => ipif_dma.axi_awready,
m_axi_awvalid => ipif_dma.axi_awvalid,
m_axi_awaddr => ipif_dma.axi_awaddr,
m_axi_awlen => ipif_dma.axi_awlen,
m_axi_awsize => ipif_dma.axi_awsize,
m_axi_awburst => ipif_dma.axi_awburst,
m_axi_awprot => ipif_dma.axi_awprot,
m_axi_awcache => ipif_dma.axi_awcache,
m_axi_wready => ipif_dma.axi_wready,
m_axi_wvalid => ipif_dma.axi_wvalid,
m_axi_wdata => ipif_dma.axi_wdata,
m_axi_wstrb => ipif_dma.axi_wstrb,
m_axi_wlast => ipif_dma.axi_wlast,
m_axi_bready => ipif_dma.axi_bready,
m_axi_bvalid => ipif_dma.axi_bvalid,
m_axi_bresp => ipif_dma.axi_bresp,
ip2bus_mstrd_req => ipif_dma.ipif_mstrd_req,
ip2bus_mstwr_req => ipif_dma.ipif_mstwr_req,
ip2bus_mst_addr => ipif_dma.ipif_mst_addr,
ip2bus_mst_length => ipif_dma.ipif_mst_length,
ip2bus_mst_be => ipif_dma.ipif_mst_be,
ip2bus_mst_type => ipif_dma.ipif_mst_type,
ip2bus_mst_lock => ipif_dma.ipif_mst_lock,
ip2bus_mst_reset => ipif_dma.ipif_mst_reset,
bus2ip_mst_cmdack => ipif_dma.ipif_mst_cmdack,
bus2ip_mst_cmplt => ipif_dma.ipif_mst_cmplt,
bus2ip_mst_error => ipif_dma.ipif_mst_error,
bus2ip_mst_rearbitrate => ipif_dma.ipif_mst_rearbitrate,
bus2ip_mst_cmd_timeout => ipif_dma.ipif_mst_cmd_timeout,
bus2ip_mstrd_d => ipif_dma.ipif_mstrd_d,
bus2ip_mstrd_rem => ipif_dma.ipif_mstrd_rem,
bus2ip_mstrd_sof_n => ipif_dma.ipif_mstrd_sof_n,
bus2ip_mstrd_eof_n => ipif_dma.ipif_mstrd_eof_n,
bus2ip_mstrd_src_rdy_n => ipif_dma.ipif_mstrd_src_rdy_n,
bus2ip_mstrd_src_dsc_n => ipif_dma.ipif_mstrd_src_dsc_n,
ip2bus_mstrd_dst_rdy_n => ipif_dma.ipif_mstrd_dst_rdy_n,
ip2bus_mstrd_dst_dsc_n => ipif_dma.ipif_mstrd_dst_dsc_n,
ip2bus_mstwr_d => ipif_dma.ipif_mstwr_d,
ip2bus_mstwr_rem => ipif_dma.ipif_mstwr_rem,
ip2bus_mstwr_sof_n => ipif_dma.ipif_mstwr_sof_n,
ip2bus_mstwr_eof_n => ipif_dma.ipif_mstwr_eof_n,
ip2bus_mstwr_src_rdy_n => ipif_dma.ipif_mstwr_src_rdy_n,
ip2bus_mstwr_src_dsc_n => ipif_dma.ipif_mstwr_src_dsc_n,
bus2ip_mstwr_dst_rdy_n => ipif_dma.ipif_mstwr_dst_rdy_n,
bus2ip_mstwr_dst_dsc_n => ipif_dma.ipif_mstwr_dst_dsc_n
);
--! The IPIF master handler converts the IPIF master signals to the
--! openMAC's DMA interface.
THEMACDMA_IPIF_HANDLER : entity work.ipifMasterHandler
generic map (
gMasterAddrWidth => ipif_dmaMasterHdler.masterAddress'length,
gMasterBurstCountWidth => ipif_dmaMasterHdler.masterBurstcount'length,
gIpifAddrWidth => ipif_dmaMasterHdler.ipif_addr'length,
gIpifLength => ipif_dmaMasterHdler.ipif_length'length
)
port map (
iRst => ipif_dmaMasterHdler.rst,
iClk => ipif_dmaMasterHdler.clk,
iIpif_cmdAck => ipif_dmaMasterHdler.ipif_cmdAck,
iIpif_cmplt => ipif_dmaMasterHdler.ipif_cmplt,
iIpif_error => ipif_dmaMasterHdler.ipif_error,
iIpif_rearbitrate => ipif_dmaMasterHdler.ipif_rearbitrate,
iIpif_cmdTimeout => ipif_dmaMasterHdler.ipif_cmdTimeout,
oIpif_type => ipif_dmaMasterHdler.ipif_type,
oIpif_addr => ipif_dmaMasterHdler.ipif_addr,
oIpif_length => ipif_dmaMasterHdler.ipif_length,
oIpif_be => ipif_dmaMasterHdler.ipif_be,
oIpif_lock => ipif_dmaMasterHdler.ipif_lock,
oIpif_reset => ipif_dmaMasterHdler.ipif_reset,
iIpif_rdData => ipif_dmaMasterHdler.ipif_rdData,
iIpif_rdRem => ipif_dmaMasterHdler.ipif_rdRem,
oIpif_rdReq => ipif_dmaMasterHdler.ipif_rdReq,
inIpif_rdSof => ipif_dmaMasterHdler.nIpif_rdSof,
inIpif_rdEof => ipif_dmaMasterHdler.nIpif_rdEof,
inIpif_rdSrcRdy => ipif_dmaMasterHdler.nIpif_rdSrcRdy,
inIpif_rdSrcDsc => ipif_dmaMasterHdler.nIpif_rdSrcDsc,
onIpif_rdDstRdy => ipif_dmaMasterHdler.nIpif_rdDstRdy,
onIpif_rdDstDsc => ipif_dmaMasterHdler.nIpif_rdDstDsc,
oIpif_wrData => ipif_dmaMasterHdler.ipif_wrData,
oIpif_wrRem => ipif_dmaMasterHdler.ipif_wrRem,
oIpif_wrReq => ipif_dmaMasterHdler.ipif_wrReq,
onIpif_wrSof => ipif_dmaMasterHdler.nIpif_wrSof,
onIpif_wrEof => ipif_dmaMasterHdler.nIpif_wrEof,
onIpif_wrSrcRdy => ipif_dmaMasterHdler.nIpif_wrSrcRdy,
onIpif_wrSrcDsc => ipif_dmaMasterHdler.nIpif_wrSrcDsc,
inIpif_wrDstRdy => ipif_dmaMasterHdler.nIpif_wrDstRdy,
inIpif_wrDstDsc => ipif_dmaMasterHdler.nIpif_wrDstDsc,
iMasterRead => ipif_dmaMasterHdler.masterRead,
iMasterWrite => ipif_dmaMasterHdler.masterWrite,
iMasterAddress => ipif_dmaMasterHdler.masterAddress,
iMasterWritedata => ipif_dmaMasterHdler.masterWritedata,
iMasterBurstcount => ipif_dmaMasterHdler.masterBurstcount,
iMasterBurstcounter => ipif_dmaMasterHdler.masterBurstcounter,
oMasterReaddata => ipif_dmaMasterHdler.masterReaddata,
oMasterWaitrequest => ipif_dmaMasterHdler.masterWaitrequest,
oMasterReaddatavalid => ipif_dmaMasterHdler.masterReaddatavalid
);
end generate GEN_THEMACDMA;
GEN_NO_MACDMA : if not (gPacketBufferLocRx = cPktBufExtern or gPacketBufferLocTx = cPktBufExtern) generate
ipif_dma.md_error <= '0';
ipif_dma.axi_arvalid <= '0';
ipif_dma.axi_araddr <= (others => '0');
ipif_dma.axi_arlen <= (others => '0');
ipif_dma.axi_arsize <= (others => '0');
ipif_dma.axi_arburst <= (others => '0');
ipif_dma.axi_arprot <= (others => '0');
ipif_dma.axi_arcache <= (others => '0');
ipif_dma.axi_rready <= '0';
ipif_dma.axi_awvalid <= '0';
ipif_dma.axi_awaddr <= (others => '0');
ipif_dma.axi_awlen <= (others => '0');
ipif_dma.axi_awsize <= (others => '0');
ipif_dma.axi_awburst <= (others => '0');
ipif_dma.axi_awprot <= (others => '0');
ipif_dma.axi_awcache <= (others => '0');
ipif_dma.axi_wvalid <= '0';
ipif_dma.axi_wdata <= (others => '0');
ipif_dma.axi_wstrb <= (others => '0');
ipif_dma.axi_wlast <= '0';
ipif_dma.axi_bready <= '0';
ipif_dmaMasterHdler.masterReaddata <= (others => '0');
ipif_dmaMasterHdler.masterWaitrequest <= '0';
ipif_dmaMasterHdler.masterReaddatavalid <= '0';
end generate GEN_NO_MACDMA;
GEN_RMII_CLK : if gPhyPortType = cPhyPortRmii generate
GEN_ODDR2 : for i in oRmii_clk'range generate
signal rmiiClk : std_logic;
signal nRmiiClk : std_logic;
begin
-- Assign rmii clock (used by openMAC) and the inverted to ODDR2.
rmiiClk <= intf_clkRst.clk;
nRmiiClk <= not rmiiClk;
--! This is a dual data rate output FF used to output the internal
--! RMII clock.
THEODDR2 : oddr2
generic map (
DDR_ALIGNMENT => "NONE", -- align D0 with C0 and D1 with C1 edge
INIT => '0', -- initialize Q with '0'
SRTYPE => "SYNC" -- take default, since RS are unused
)
port map (
D0 => cActivated,
D1 => cInactivated,
C0 => rmiiClk,
C1 => nRmiiClk,
CE => cActivated,
R => cInactivated, --unused
S => cInactivated, --unused
Q => oRmii_clk(i)
);
end generate GEN_ODDR2;
end generate GEN_RMII_CLK;
GEN_NO_RMII_CLK : if not (gPhyPortType = cPhyPortRmii) generate
oRmii_clk <= (others => '0');
end generate GEN_NO_RMII_CLK;
end rtl;
| gpl-2.0 | 5b8d8ca9fd10c3116e5c7bc41694e462 | 0.52503 | 4.027162 | false | false | false | false |
DreamIP/GPStudio | support/process/maxPool/hdl/maxPool.vhd | 1 | 2,057 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity maxPool is
generic (
IMAGE_WIDTH : integer := 320;
IN_SIZE : integer := 8;
OUT_SIZE : integer := 8;
CLK_PROC_FREQ : integer := 50000000
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_data : out std_logic_vector(OUT_SIZE - 1 downto 0);
out_dv : out std_logic;
out_fv : out std_logic;
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of maxPool is
component maxPool_process is
generic(
PIXEL_SIZE : integer;
IMAGE_WIDTH : integer;
KERNEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE - 1 downto 0);
in_dv : in std_logic;
in_fv : in std_logic;
out_data : out std_logic_vector (PIXEL_SIZE - 1 downto 0);
out_dv : out std_logic;
out_fv : out std_logic
);
end component;
begin
inst : maxPool_process
generic map (
PIXEL_SIZE => IN_SIZE,
KERNEL_SIZE => 2,
IMAGE_WIDTH => IMAGE_WIDTH
)
port map (
clk => clk_proc,
reset_n => reset_n,
enable => '1',
in_data => in_data,
in_dv => in_dv,
in_fv => in_fv,
out_data => out_data,
out_dv => out_dv,
out_fv => out_fv
);
end architecture;
| gpl-3.0 | 15b8bee7504bcfcaf2e9c508d5fc6468 | 0.473019 | 3.179289 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | synthesis/mems-vhdl/top.vhdl | 1 | 4,710 | --
-- Mems top level
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.MEMS.all;
entity Top is
port (
clk1_i : in std_logic;
clk2_i : in std_logic;
wen1_i : in std_logic;
wen2_i : in std_logic;
addr1_i : in std_logic_vector(7 downto 0);
addr2_i : in std_logic_vector(7 downto 0);
data1_i : in std_logic_vector(7 downto 0);
data2_i : in std_logic_vector(7 downto 0);
data1_o : out std_logic_vector(7 downto 0);
data2_o : out std_logic_vector(7 downto 0);
--
sel_i : in std_logic_vector(2 downto 0)
);
end entity Top;
architecture Structural of Top is
signal sp_nc_data1, sp_wf_data1, sp_rf_data1 : std_logic_vector(7 downto 0);
signal sdp_latch_data2, sdp_reg_data2 : std_logic_vector(7 downto 0);
signal tdp_nc_data1, tdp_wf_data1, tdp_rf_data1 : std_logic_vector(7 downto 0);
signal tdp_nc_data2, tdp_wf_data2, tdp_rf_data2 : std_logic_vector(7 downto 0);
constant isQuartus : std_logic := '1'
-- altera translate_off
and '0'
-- altera translate_on
;
begin
i_sp_nc : SinglePortRAM
generic map (AWIDTH => 8, DWIDTH => 8, DEPTH => 0, OUTREG => FALSE, SYNCMODE => NO_CHANGE)
port map (
clk_i => clk1_i,
wen_i => wen1_i,
addr_i => addr1_i,
data_i => data1_i,
data_o => sp_nc_data1
);
i_sp_wf : SinglePortRAM
generic map (AWIDTH => 8, DWIDTH => 8, DEPTH => 0, OUTREG => FALSE, SYNCMODE => WRITE_FIRST)
port map (
clk_i => clk1_i,
wen_i => wen1_i,
addr_i => addr1_i,
data_i => data1_i,
data_o => sp_wf_data1
);
i_sp_rf : SinglePortRAM
generic map (AWIDTH => 8, DWIDTH => 8, DEPTH => 0, OUTREG => FALSE, SYNCMODE => READ_FIRST)
port map (
clk_i => clk1_i,
wen_i => wen1_i,
addr_i => addr1_i,
data_i => data1_i,
data_o => sp_rf_data1
);
i_sdp_latch: SimpleDualPortRAM
generic map (AWIDTH => 8, DWIDTH => 8, DEPTH => 0, OUTREG => FALSE)
port map (
clk1_i => clk1_i,
clk2_i => clk2_i,
wen1_i => wen1_i,
addr1_i => addr1_i,
addr2_i => addr2_i,
data1_i => data1_i,
data2_o => sdp_latch_data2
);
i_sdp_reg: SimpleDualPortRAM
generic map (AWIDTH => 8, DWIDTH => 8, DEPTH => 0, OUTREG => TRUE)
port map (
clk1_i => clk1_i,
clk2_i => clk2_i,
wen1_i => wen1_i,
addr1_i => addr1_i,
addr2_i => addr2_i,
data1_i => data1_i,
data2_o => sdp_reg_data2
);
i_tdp_nc : TrueDualPortRAM
generic map (AWIDTH => 8, DWIDTH => 8, DEPTH => 0, OUTREG => FALSE, SYNCMODE => NO_CHANGE)
port map (
clk1_i => clk1_i,
clk2_i => clk2_i,
wen1_i => wen1_i,
wen2_i => wen2_i,
addr1_i => addr1_i,
addr2_i => addr2_i,
data1_i => data1_i,
data2_i => data2_i,
data1_o => tdp_nc_data1,
data2_o => tdp_nc_data2
);
i_tdp_wf : TrueDualPortRAM
generic map (AWIDTH => 8, DWIDTH => 8, DEPTH => 0, OUTREG => FALSE, SYNCMODE => WRITE_FIRST)
port map (
clk1_i => clk1_i,
clk2_i => clk2_i,
wen1_i => wen1_i,
wen2_i => wen2_i,
addr1_i => addr1_i,
addr2_i => addr2_i,
data1_i => data1_i,
data2_i => data2_i,
data1_o => tdp_wf_data1,
data2_o => tdp_wf_data2
);
g_tdp_rf: if isQuartus/='1' generate
i_tdp_rf : TrueDualPortRAM
generic map (AWIDTH => 8, DWIDTH => 8, DEPTH => 0, OUTREG => FALSE, SYNCMODE => READ_FIRST)
port map (
clk1_i => clk1_i,
clk2_i => clk2_i,
wen1_i => wen1_i,
wen2_i => wen2_i,
addr1_i => addr1_i,
addr2_i => addr2_i,
data1_i => data1_i,
data2_i => data2_i,
data1_o => tdp_rf_data1,
data2_o => tdp_rf_data2
);
end generate g_tdp_rf;
data1_o <= sp_nc_data1 when sel_i="000" else
sp_wf_data1 when sel_i="001" else
sp_rf_data1 when sel_i="010" else
tdp_nc_data1 when sel_i="011" else
tdp_wf_data1 when sel_i="100" else
tdp_rf_data1;
data2_o <= sdp_latch_data2 when sel_i="000" else
sdp_reg_data2 when sel_i="001" else
tdp_nc_data2 when sel_i="010" else
tdp_wf_data2 when sel_i="011" else
tdp_rf_data2;
end architecture Structural;
| bsd-3-clause | 7d6ab7805aa984b9025d871cdf24d69b | 0.519321 | 2.791938 | false | false | false | false |
hoglet67/ElectronFpga | src/common/mode7/saa5050.vhd | 1 | 25,425 | -- BBC Micro for Altera DE1
--
-- Copyright (c) 2011 Mike Stirling
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- * Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- * Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written agreement from the author.
--
-- * License is granted for non-commercial use only. A fee may not be charged
-- for redistributions as source code or in synthesized/hardware form without
-- specific prior written agreement from the author.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- SAA5050 teletext generator
--
-- Synchronous implementation for FPGA. Certain TV-specific functions are
-- not implemented. e.g.
--
-- No /SI pin - 'TEXT' mode is permanently enabled
-- No remote control features (/DATA, DLIM)
-- No large character support
-- No support for box overlay (BLAN, PO, DE)
--
--
--
-- (C) 2011 Mike Stirling
--
-- Updated to run at 12MHz rather than 6MHz
-- Character rounding added
-- Implemented Graphics Hold
-- Lots of fixes to correctly implement Set-At and Set-After control codes
--
-- (C) 2015 David Banks
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity saa5050 is
generic (
IncludeTTxtROM : boolean -- false if the SAA5050 character ROM needs loading
);
port (
CLOCK : in std_logic;
-- 6 MHz dot clock enable
CLKEN : in std_logic;
-- Async reset
nRESET : in std_logic;
-- Character data input (in the bus clock domain)
DI_CLOCK : in std_logic;
DI_CLKEN : in std_logic;
DI : in std_logic_vector(6 downto 0);
-- Timing inputs
-- General line reset (not used)
GLR : in std_logic; -- /HSYNC
-- Data entry window - high during VSYNC.
-- Resets ROM row counter and drives 'flash' signal
DEW : in std_logic; -- VSYNC
-- Character rounding select - high during even field
CRS : in std_logic; -- FIELD
-- Load output shift register enable - high during active video
LOSE : in std_logic; -- DE
-- Video out
R : out std_logic;
G : out std_logic;
B : out std_logic;
Y : out std_logic;
-- SAA5050 character ROM loading
char_rom_we : in std_logic := '0';
char_rom_addr : in std_logic_vector(11 downto 0) := (others => '0');
char_rom_data : in std_logic_vector(7 downto 0) := (others => '0')
);
end entity;
architecture rtl of saa5050 is
-- Register inputs in the bus clock domain
signal di_r : std_logic_vector(6 downto 0);
signal dew_r : std_logic;
signal lose_r : std_logic;
-- Data input registered in the pixel clock domain
signal code : std_logic_vector(6 downto 0);
signal line_addr : unsigned(3 downto 0);
signal rom_address1 : std_logic_vector(11 downto 0);
signal rom_address2 : std_logic_vector(11 downto 0);
signal rom_data1 : std_logic_vector(7 downto 0);
signal rom_data2 : std_logic_vector(7 downto 0);
-- Delayed display enable derived from LOSE by delaying for one and two characters
signal disp_enable : std_logic;
-- Latched timing signals for detection of falling edges
signal dew_latch : std_logic;
signal lose_latch : std_logic;
signal disp_enable_latch : std_logic;
-- Row and column addressing is handled externally. We just need to
-- keep track of which of the 10 lines we are on within the character...
signal line_counter : unsigned(3 downto 0);
-- ... and which of the 12 pixels we are on within each line
signal pixel_counter : unsigned(3 downto 0);
-- We also need to count frames to implement the flash feature.
-- The datasheet says this is 0.75 Hz with a 3:1 on/off ratio, so it
-- is probably a /64 counter, which gives us 0.78 Hz
signal flash_counter : unsigned(5 downto 0);
-- Output shift register
signal shift_reg : std_logic_vector(11 downto 0);
-- Flash mask
signal flash : std_logic;
-- Current display state
-- Foreground colour (B2, G1, R0)
signal fg : std_logic_vector(2 downto 0);
-- Background colour (B2, G1, R0)
signal bg : std_logic_vector(2 downto 0);
signal conceal : std_logic;
signal gfx : std_logic;
signal gfx_sep : std_logic;
signal gfx_hold : std_logic;
signal is_flash : std_logic;
signal double_high : std_logic;
-- One-shot versions of certain control signals to support "Set-After" semantics
signal fg_next : std_logic_vector(2 downto 0);
signal alpha_next : std_logic;
signal gfx_next : std_logic;
signal gfx_release_next : std_logic;
signal is_flash_next : std_logic;
signal double_high_next : std_logic;
signal unconceal_next : std_logic;
-- Once char delayed versions of all of the signals seen by the ROM/Shift Register/Output Stage
-- This is to compensate for the one char delay through the control state machine
signal code_r : std_logic_vector(6 downto 0);
signal disp_enable_r: std_logic;
signal fg_r : std_logic_vector(2 downto 0);
signal bg_r : std_logic_vector(2 downto 0);
signal conceal_r : std_logic;
signal is_flash_r : std_logic;
-- Last graphics character, for use by graphics hold
signal last_gfx_sep : std_logic;
signal last_gfx : std_logic_vector(6 downto 0);
signal hold_active : std_logic;
-- Set in first row of double height
signal double_high1 : std_logic;
-- Set in second row of double height
signal double_high2 : std_logic;
begin
-- Generate flash signal for 3:1 ratio
flash <= flash_counter(5) and flash_counter(4);
-- Sync inputs
process(DI_CLOCK,nRESET)
begin
if nRESET = '0' then
di_r <= (others => '0');
dew_r <= '0';
lose_r <= '0';
elsif rising_edge(DI_CLOCK) then
if DI_CLKEN = '1' then
di_r <= DI;
dew_r <= DEW;
lose_r <= LOSE;
end if;
end if;
end process;
-- Register data into pixel clock domain
process(CLOCK,nRESET)
begin
if nRESET = '0' then
code <= (others => '0');
code_r <= (others => '0');
disp_enable_r <= '0';
fg_r <= (others => '0');
bg_r <= (others => '0');
conceal_r <= '0';
is_flash_r <= '0';
elsif rising_edge(CLOCK) then
if CLKEN = '1' then
code <= di_r;
if pixel_counter = 0 then
code_r <= code;
disp_enable_r <= disp_enable;
fg_r <= fg;
bg_r <= bg;
conceal_r <= conceal;
is_flash_r <= is_flash;
end if;
end if;
end if;
end process;
-- Character row and pixel counters
process(CLOCK,nRESET)
begin
if nRESET = '0' then
dew_latch <= '0';
lose_latch <= '0';
disp_enable <= '0';
disp_enable_latch <= '0';
double_high1 <= '0';
double_high2 <= '0';
line_counter <= (others => '0');
pixel_counter <= (others => '0');
flash_counter <= (others => '0');
elsif rising_edge(CLOCK) then
if CLKEN = '1' then
-- Register syncs for edge detection
dew_latch <= dew_r;
lose_latch <= lose_r;
disp_enable_latch <= disp_enable;
-- When first entering double-height mode start on top row
if double_high = '1' and double_high1 = '0' and double_high2 = '0' then
double_high1 <= '1';
end if;
-- Count pixels between 0 and 11
if pixel_counter = 11 then
-- Start of next character and delayed display enable
pixel_counter <= (others => '0');
disp_enable <= lose_latch;
else
pixel_counter <= pixel_counter + 1;
end if;
-- Rising edge of LOSE is the start of the active line
if lose_r = '1' and lose_latch = '0' then
-- Reset pixel counter - small offset to make the output
-- line up with the cursor from the video ULA
pixel_counter <= "0010";
end if;
-- Count frames on end of VSYNC (falling edge of DEW)
if dew_r = '0' and dew_latch = '1' then
flash_counter <= flash_counter + 1;
end if;
if dew_r = '1' then
-- Reset line counter and double height state during VSYNC
line_counter <= (others => '0');
double_high1 <= '0';
double_high2 <= '0';
else
-- Count lines on end of active video (falling edge of disp_enable)
if disp_enable = '0' and disp_enable_latch = '1' then
if line_counter = 9 then
line_counter <= (others => '0');
-- Keep track of which row we are on for double-height
-- The double_high flag can be cleared before the end of a row, but if
-- double height characters are used anywhere on a row then the double_high1
-- flag will be set and remain set until the next row. This is used
-- to determine that the bottom half of the characters should be shown if
-- double_high is set once again on the row below.
double_high1 <= '0';
double_high2 <= double_high1;
else
line_counter <= line_counter + 1;
end if;
end if;
end if;
end if;
end if;
end process;
-- Control character handling
process(CLOCK,nRESET)
begin
if nRESET = '0' then
-- Current Attributes
fg <= (others => '1');
bg <= (others => '0');
conceal <= '0';
gfx <= '0';
gfx_sep <= '0';
gfx_hold <= '0';
is_flash <= '0';
double_high <= '0';
-- One-shot versions to support "Set-After" semantics
fg_next <= (others => '0');
gfx_next <= '0';
alpha_next <= '0';
gfx_release_next <= '0';
is_flash_next <= '0';
double_high_next <= '0';
unconceal_next <= '0';
-- Last graphics character
last_gfx <= (others => '0');
last_gfx_sep <= '0';
elsif rising_edge(CLOCK) then
if CLKEN = '1' then
-- Reset to start of line defaults
if disp_enable = '0' then
-- Current Attributes
fg <= (others => '1');
bg <= (others => '0');
conceal <= '0';
gfx <= '0';
gfx_sep <= '0';
gfx_hold <= '0';
is_flash <= '0';
double_high <= '0';
-- One-shot versions to support "Set-After" semantics
fg_next <= (others => '0');
gfx_next <= '0';
alpha_next <= '0';
gfx_release_next <= '0';
is_flash_next <= '0';
double_high_next <= '0';
unconceal_next <= '0';
-- Last graphics character
last_gfx <= (others => '0');
last_gfx_sep <= '0';
elsif pixel_counter = 0 then
-- One-shot versions to support "Set-After" semantics
fg_next <= (others => '0');
gfx_next <= '0';
alpha_next <= '0';
gfx_release_next <= '0';
is_flash_next <= '0';
double_high_next <= '0';
unconceal_next <= '0';
-- Latch the last graphic character (inc seperation), to support graphics hold
if code(5) = '1' then
last_gfx <= code;
last_gfx_sep <= gfx_sep;
end if;
-- Latch new control codes at the start of each character
if code(6 downto 5) = "00" then
if code(3) = '0' then
-- 0 would be black but is not allowed so has no effect
if code(2 downto 0) /= "000" then
-- Colour and graphics setting clears conceal mode - Set After
unconceal_next <= '1';
-- Select the foreground colout - Set After
fg_next <= code(2 downto 0);
-- Select graphics or alpha mode - Set After
if code(4) = '1' then
gfx_next <= '1';
else
alpha_next <= '1';
gfx_release_next <= '1';
end if;
end if;
else
case code(4 downto 0) is
-- FLASH - Set After
when "01000" =>
is_flash_next <= '1';
-- STEADY - Set At
when "01001" =>
is_flash <= '0';
-- NORMAL HEIGHT - Set At
when "01100" =>
double_high <= '0';
-- Graphics hold character is cleared by a *change* of height
if (double_high = '0') then
last_gfx <= (others => '0');
end if;
-- DOUBLE HEIGHT - Set After
when "01101" =>
double_high_next <= '1';
-- Graphics hold character is cleared by a *change* of height
if (double_high = '0') then
last_gfx <= (others => '0');
end if;
-- CONCEAL - Set At
when "11000" =>
conceal <= '1';
-- CONTIGUOUS GFX - Set At
when "11001" =>
gfx_sep <= '0';
-- SEPARATED GFX - Set At
when "11010" =>
gfx_sep <= '1';
-- BLACK BACKGROUND - Set At
when "11100" =>
bg <= (others => '0');
-- NEW BACKGROUND - Set At
when "11101" =>
-- if there is a pending foreground change, then use it
if fg_next /= "000" then
bg <= fg_next;
else
bg <= fg;
end if;
-- HOLD GFX - Set At
when "11110" =>
gfx_hold <= '1';
-- RELEASE GFX - Set After
when "11111" =>
gfx_release_next <= '1';
when others => null;
end case;
end if;
end if;
-- Delay the "Set After" control code effect until the next character
if fg_next /= "000" then
fg <= fg_next;
end if;
if gfx_next = '1' then
gfx <= '1';
end if;
if alpha_next = '1' then
gfx <= '0';
end if;
if is_flash_next = '1' then
is_flash <= '1';
end if;
if double_high_next = '1' then
double_high <= '1';
end if;
if gfx_release_next = '1' then
gfx_hold <= '0';
end if;
-- Note, conflicts can arise as setting/clearing happen in different cycles
-- e.g. 03 (Alpha Yellow) 18 (Conceal) should leave us in a conceal state
if conceal = '1' and unconceal_next = '1' then
conceal <= '0';
end if;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------
-- Character ROM
--------------------------------------------------------------------
-- Generate character rom address in pixel clock domain
-- This is done combinatorially since all the inputs are already
-- registered and the address is re-registered by the ROM
line_addr <= line_counter when double_high = '0' else
("0" & line_counter(3 downto 1)) when double_high2 = '0' else
("0" & line_counter(3 downto 1)) + 5;
hold_active <= '1' when gfx_hold = '1' and code_r(6 downto 5) = "00" else '0';
rom_address1 <= char_rom_addr when char_rom_we = '1' and not IncludeTTxtROM else
(others => '0') when (double_high = '0' and double_high2 = '1') else
gfx & last_gfx & std_logic_vector(line_addr) when hold_active = '1' else
gfx & code_r & std_logic_vector(line_addr);
-- reference row for character rounding
rom_address2 <= rom_address1 + 1 when ((double_high = '0' and CRS = '1') or (double_high = '1' and line_counter(0) = '1')) else
rom_address1 - 1;
-- If IncludeTTxtROM is true then we include the "ROM" version that is
-- initialized with the mode 7 character set data
-- (this is generally used for Xilinx builds)
char_rom_block: if IncludeTTxtROM generate
char_rom : entity work.saa5050_rom_dual_port port map (
clock => CLOCK,
addressA => rom_address1,
QA => rom_data1,
addressB => rom_address2,
QB => rom_data2
);
end generate;
-- If IncludeTTxtROM is false then we include the "RAM" version that is
-- uninitialized, and needs loading during the core boostrap phase
-- (this is generally used for Altera builds)
char_ram_block: if not IncludeTTxtROM generate
char_ram : entity work.saa5050_rom_dual_port_uninitialized port map (
clock => CLOCK,
wea => char_rom_we,
addressA => rom_address1,
dina => char_rom_data,
QA => rom_data1,
addressB => rom_address2,
QB => rom_data2
);
end generate;
--------------------------------------------------------------------
-- Shift register
--------------------------------------------------------------------
process(CLOCK,nRESET)
variable a : std_logic_vector(11 downto 0);
variable b : std_logic_vector(11 downto 0);
begin
if nRESET = '0' then
shift_reg <= (others => '0');
elsif rising_edge(CLOCK) then
if CLKEN = '1' then
if disp_enable_r = '1' and pixel_counter = 0 then
-- Character rounding
-- a is the current row of pixels, doubled up
a := rom_data1(5) & rom_data1(5) &
rom_data1(4) & rom_data1(4) &
rom_data1(3) & rom_data1(3) &
rom_data1(2) & rom_data1(2) &
rom_data1(1) & rom_data1(1) &
rom_data1(0) & rom_data1(0);
-- b is the adjacent row of pixels, doubled up
b := rom_data2(5) & rom_data2(5) &
rom_data2(4) & rom_data2(4) &
rom_data2(3) & rom_data2(3) &
rom_data2(2) & rom_data2(2) &
rom_data2(1) & rom_data2(1) &
rom_data2(0) & rom_data2(0);
-- If bit 7 of the ROM data is set then this is a graphics
-- character and separated/hold graphics modes apply.
-- We don't just assume this to be the case if gfx=1 because
-- these modes don't apply to caps even in graphics mode
if rom_data1(7) = '1' then
-- Apply a mask for separated graphics mode
if (hold_active = '0' and gfx_sep = '1') or (hold_active = '1' and last_gfx_sep = '1') then
a(10) := '0';
a(11) := '0';
a(4) := '0';
a(5) := '0';
if line_counter = 2 or line_counter = 6 or line_counter = 9 then
a := (others => '0');
end if;
end if;
else
-- Perform character rounding on alpha-numeric characters
a := a or
(('0' & a(11 downto 1)) and b and not('0' & b(11 downto 1))) or
((a(10 downto 0) & '0') and b and not(b(10 downto 0) & '0'));
end if;
-- Load the shift register with the ROM bit pattern
-- at the start of each character while disp_enable is asserted.
shift_reg <= a;
else
-- Pump the shift register
shift_reg <= shift_reg(10 downto 0) & "0";
end if;
end if;
end if;
end process;
--------------------------------------------------------------------
-- Output Pixel Colouring
--------------------------------------------------------------------
process(CLOCK,nRESET)
variable pixel : std_logic;
begin
if nRESET = '0' then
R <= '0';
G <= '0';
B <= '0';
elsif rising_edge(CLOCK) then
if CLKEN = '1' then
pixel := shift_reg(11) and not ((flash and is_flash_r) or conceal_r);
-- Generate mono output
Y <= pixel;
-- Generate colour output
if pixel = '1' then
R <= fg_r(0);
G <= fg_r(1);
B <= fg_r(2);
else
R <= bg_r(0);
G <= bg_r(1);
B <= bg_r(2);
end if;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | cf0af14576ce8ff1301395cf1d096e39 | 0.4588 | 4.479387 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_sram_0_avalon_sram_slave_translator.vhd | 1 | 12,680 | -- tracking_camera_system_sram_0_avalon_sram_slave_translator.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.13.13:59:38
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tracking_camera_system_sram_0_avalon_sram_slave_translator is
generic (
AV_ADDRESS_W : integer := 18;
AV_DATA_W : integer := 16;
UAV_DATA_W : integer := 16;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 2;
UAV_BYTEENABLE_W : integer := 2;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 2;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 2;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- .readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(17 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(15 downto 0); -- .writedata
av_byteenable : out std_logic_vector(1 downto 0); -- .byteenable
av_readdatavalid : in std_logic := '0'; -- .readdatavalid
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(1 downto 0);
uav_clken : in std_logic := '0'
);
end entity tracking_camera_system_sram_0_avalon_sram_slave_translator;
architecture rtl of tracking_camera_system_sram_0_avalon_sram_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(17 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_byteenable : out std_logic_vector(1 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(1 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component altera_merlin_slave_translator;
begin
sram_0_avalon_sram_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_readdatavalid => av_readdatavalid, -- .readdatavalid
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
end architecture rtl; -- of tracking_camera_system_sram_0_avalon_sram_slave_translator
| gpl-2.0 | e6fba5fd21fbabb4955300c88a6168e0 | 0.436278 | 4.278003 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_timer_0_s1_translator.vhd | 1 | 12,471 | -- tracking_camera_system_timer_0_s1_translator.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.13.13:59:38
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tracking_camera_system_timer_0_s1_translator is
generic (
AV_ADDRESS_W : integer := 3;
AV_DATA_W : integer := 16;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 1;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(2 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(15 downto 0); -- .writedata
av_chipselect : out std_logic; -- .chipselect
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_byteenable : out std_logic_vector(0 downto 0);
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_read : out std_logic;
av_readdatavalid : in std_logic := '0';
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(0 downto 0);
uav_clken : in std_logic := '0'
);
end entity tracking_camera_system_timer_0_s1_translator;
architecture rtl of tracking_camera_system_timer_0_s1_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(2 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_chipselect : out std_logic; -- chipselect
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component altera_merlin_slave_translator;
begin
timer_0_s1_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_chipselect => av_chipselect, -- .chipselect
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
end architecture rtl; -- of tracking_camera_system_timer_0_s1_translator
| gpl-2.0 | 13547b8f83a4617750c99eb9004613f6 | 0.43517 | 4.249063 | false | false | false | false |
SonicFrog/ArchOrd | doorlock.vhdl | 1 | 1,527 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity doorlock is
port (
keyon : in std_logic;
keycode : in std_logic(2 downto 0);
reset : in std_logic;
clk : in std_logic;
opendoor : out std_logic
);
end entity; --doorlock
architecture synth of doorlock is
type state is (s0, s1, s2);
signal current_state, future_state : state;
signal code : std_logic_vector(11 downto 0);
begin
shift : process(clk, shift_left, shift_right)
begin
if rising_edge(clk) then
if shift_left = '1' then
code <= code(11 downto 3) & keycode;
elsif shift_right = '1' then
code <= "000" & code(8 downto 0);
end if;
end if;
end process;
sync : process(clk)
begin
if reset = '1' then
current_state <= s0;
elsif rising_edge(clk) then
current_state <= future_state;
end if;
end process;
handle_state : process(current_state, keyon, keycode)
begin
future_state <= current_state;
opendoor <= '0';
case current_state is
when s0 =>
if keyon = '1' then
future_state <= s1;
if keycode = "111" then
shift_right <= '1';
else
shift_left <= '1';
end if;
end if;
when s1 =>
if code = "011110010101" then -- code is 3625
future_state <= s2;
else -- code is fake
future_state <= s0;
end if;
when s2 =>
opendoor <= '1';
future_state <= s0;
when others =>
future_state <= s0;
end case;
end process;
end architecture ; -- synth | gpl-2.0 | e2811aa80c93b3127fb4a212e2e4b963 | 0.612967 | 2.717082 | false | false | false | false |
DreamIP/GPStudio | support/io/com/hdl/hal/eth_marvell_88e1111/hdl/eth_slave.vhd | 1 | 4,054 | -- This entity has been generated via GPStudio.
-- The values at reset has been modified.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.ethernet_package.all;
entity eth_slave is
generic (pi_size_addr : integer:=3);
Port(
CLK : in STD_LOGIC;
RESET_n : in STD_LOGIC;
addr_rel_i : in std_logic_vector(pi_size_addr downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0);
--- parameters com
enable_eth_o : out std_logic;
enable_in0_o : out std_logic;
enable_in1_o : out std_logic;
enable_in2_o : out std_logic;
enable_in3_o : out std_logic;
--- parameters ethernet
mac_addr_hal_msb : out std_logic_vector(23 downto 0);
mac_addr_hal_lsb : out std_logic_vector(23 downto 0);
mac_addr_dest_msb : out std_logic_vector(23 downto 0);
mac_addr_dest_lsb : out std_logic_vector(23 downto 0);
ip_hal : out std_logic_vector(31 downto 0);
ip_dest : out std_logic_vector(31 downto 0);
port_dest : out std_logic_vector(15 downto 0)
);
end eth_slave;
architecture RTL of eth_slave is
constant MAC_ADDR_HAL_MSB_ADDR : integer := 0;
constant MAC_ADDR_HAL_LSB_ADDR : integer := 1;
constant MAC_ADDR_DEST_MSB_ADDR : integer := 2;
constant MAC_ADDR_DEST_LSB_ADDR : integer := 3;
constant IP_HAL_ADDR : integer := 4;
constant IP_DEST_ADDR : integer := 5;
constant PORT_DEST_ADDR : integer := 6;
constant ENABLE_ETH_ADDR : integer := 7;
constant ENABLE_IN0_ADDR : integer := 8;
constant ENABLE_IN1_ADDR : integer := 9;
constant ENABLE_IN2_ADDR : integer := 10;
constant ENABLE_IN3_ADDR : integer := 11;
begin
REG:process (clk, RESET_n)
begin
if (RESET_n = '0') then
enable_eth_o <= '1';
enable_in0_o <= '1';
enable_in1_o <= '1';
enable_in2_o <= '1';
enable_in3_o <= '1';
mac_addr_hal_msb <= x"005043";
mac_addr_hal_lsb <= x"430001";
mac_addr_dest_msb <= x"7845C4";
mac_addr_dest_lsb <= x"192509";
ip_hal <= x"C0A8010A";--192.168.1.10
ip_dest <= x"C0A80101";--192.168.1.1
port_dest <= x"079B";--1947
elsif rising_edge(clk) then
if(wr_i = '1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(ENABLE_ETH_ADDR,pi_size_addr+1)) =>
enable_eth_o <= datawr_i(0);
when std_logic_vector(to_unsigned(ENABLE_IN0_ADDR,pi_size_addr+1)) =>
enable_in0_o <= datawr_i(0);
when std_logic_vector(to_unsigned(ENABLE_IN1_ADDR,pi_size_addr+1)) =>
enable_in1_o <= datawr_i(0);
when std_logic_vector(to_unsigned(ENABLE_IN2_ADDR,pi_size_addr+1)) =>
enable_in2_o <= datawr_i(0);
when std_logic_vector(to_unsigned(ENABLE_IN3_ADDR,pi_size_addr+1)) =>
enable_in3_o <= datawr_i(0);
when std_logic_vector(to_unsigned(MAC_ADDR_HAL_MSB_ADDR,pi_size_addr+1)) =>
mac_addr_hal_msb <= datawr_i(23 downto 0);
when std_logic_vector(to_unsigned(MAC_ADDR_HAL_LSB_ADDR,pi_size_addr+1)) =>
mac_addr_hal_lsb <= datawr_i(23 downto 0);
when std_logic_vector(to_unsigned(MAC_ADDR_DEST_MSB_ADDR,pi_size_addr+1)) =>
mac_addr_dest_msb <= datawr_i(23 downto 0);
when std_logic_vector(to_unsigned(MAC_ADDR_DEST_LSB_ADDR,pi_size_addr+1)) =>
mac_addr_dest_lsb <= datawr_i(23 downto 0);
when std_logic_vector(to_unsigned(IP_HAL_ADDR,pi_size_addr+1)) =>
ip_hal <= datawr_i;
when std_logic_vector(to_unsigned(IP_DEST_ADDR,pi_size_addr+1)) =>
ip_dest <= datawr_i;
when std_logic_vector(to_unsigned(PORT_DEST_ADDR,pi_size_addr+1)) =>
port_dest <= datawr_i(15 downto 0);
when others =>
end case;
end if;
end if;
end process;
end RTL;
| gpl-3.0 | 861e97c815eff447ada61857a3c1f20f | 0.582881 | 2.883357 | false | false | false | false |
marzoul/PoC | src/mem/ocram/ocram_sdp.vhdl | 1 | 6,867 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Thomas B. Preusser
-- Patrick Lehmann
--
-- Module: Simple dual-port memory.
--
-- Description:
-- ------------------------------------
-- Inferring / instantiating simple dual-port memory, with:
-- * dual clock, clock enable,
-- * 1 read port plus 1 write port.
--
-- The generalized behavior across Altera and Xilinx FPGAs since
-- Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:
--
-- The Altera M512/M4K TriMatrix memory (as found e.g. in Stratix and
-- Stratix II FPGAs) defines the minimum time after which the written data at
-- the write port can be read-out at read port again. As stated in the Stratix
-- Handbook, Volume 2, page 2-13, data is actually written with the falling
-- (instead of the rising) edge of the clock into the memory array. The write
-- itself takes the write-cycle time which is less or equal to the minimum
-- clock-period time. After this, the data can be read-out at the other port.
-- Consequently, data "d" written at the rising-edge of "wclk" at address
-- "wa" can be read-out at the read port from the same address with the
-- 2nd rising-edge of "rclk" following the falling-edge of "wclk".
-- If the rising-edge of "rclk" coincides with the falling-edge of "wclk"
-- (e.g. same clock signal), then it is counted as the 1st rising-edge of
-- "rclk" in this timing.
--
-- WARNING: The simulated behavior on RT-level is not correct.
--
-- TODO: add timing diagram
-- TODO: implement correct behavior for RT-level simulation
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library STD;
use STD.TextIO.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
entity ocram_sdp is
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
rclk : in std_logic; -- read clock
rce : in std_logic; -- read clock-enable
wclk : in std_logic; -- write clock
wce : in std_logic; -- write clock-enable
we : in std_logic; -- write enable
ra : in unsigned(A_BITS-1 downto 0); -- read address
wa : in unsigned(A_BITS-1 downto 0); -- write address
d : in std_logic_vector(D_BITS-1 downto 0); -- data in
q : out std_logic_vector(D_BITS-1 downto 0)); -- data out
end entity;
architecture rtl of ocram_sdp is
attribute ramstyle : string;
constant DEPTH : positive := 2**A_BITS;
begin
gInfer: if VENDOR = VENDOR_XILINX or VENDOR = VENDOR_ALTERA generate
-- RAM can be inferred correctly
-- Xilinx notes:
-- WRITE_MODE is set to WRITE_FIRST, but this also means that read data
-- is unknown on the opposite port. (As expected.)
-- Altera notes:
-- Setting attribute "ramstyle" to "no_rw_check" suppresses generation of
-- bypass logic, when 'clk1'='clk2' and 'ra' is feed from a register.
-- This is the expected behaviour.
-- With two different clocks, synthesis complains about an undefined
-- read-write behaviour, that can be ignored.
subtype word_t is std_logic_vector(D_BITS - 1 downto 0);
type ram_t is array(0 to DEPTH - 1) of word_t;
begin
genLoadFile : if (str_length(FileName) /= 0) generate
-- Read a *.mem or *.hex file
impure function ocram_ReadMemFile(FileName : STRING) return ram_t is
file FileHandle : TEXT open READ_MODE is FileName;
variable CurrentLine : LINE;
variable TempWord : STD_LOGIC_VECTOR((div_ceil(word_t'length, 4) * 4) - 1 downto 0);
variable Result : ram_t := (others => (others => '0'));
begin
-- discard the first line of a mem file
if (str_toLower(FileName(FileName'length - 3 to FileName'length)) = ".mem") then
readline(FileHandle, CurrentLine);
end if;
for i in 0 to DEPTH - 1 loop
exit when endfile(FileHandle);
readline(FileHandle, CurrentLine);
hread(CurrentLine, TempWord);
Result(i) := resize(TempWord, word_t'length);
end loop;
return Result;
end function;
signal ram : ram_t := ocram_ReadMemFile(FILENAME);
attribute ramstyle of ram : signal is "no_rw_check";
begin
process (wclk)
begin
if rising_edge(wclk) then
if (wce and we) = '1' then
ram(to_integer(wa)) <= d;
end if;
end if;
end process;
process (rclk)
begin
if rising_edge(rclk) then
-- read data doesn't care, when reading at write address
if rce = '1' then
--synthesis translate_off
if Is_X(std_logic_vector(ra)) then
q <= (others => 'X');
else
--synthesis translate_on
q <= ram(to_integer(ra));
--synthesis translate_off
end if;
--synthesis translate_on
end if;
end if;
end process;
end generate;
genNoLoadFile : if (str_length(FileName) = 0) generate
signal ram : ram_t;
attribute ramstyle of ram : signal is "no_rw_check";
begin
process (wclk)
begin
if rising_edge(wclk) then
if (wce and we) = '1' then
ram(to_integer(wa)) <= d;
end if;
end if;
end process;
process (rclk)
begin
if rising_edge(rclk) then
-- read data doesn't care, when reading at write address
if rce = '1' then
--synthesis translate_off
if Is_X(std_logic_vector(ra)) then
q <= (others => 'X');
else
--synthesis translate_on
q <= ram(to_integer(ra));
--synthesis translate_off
end if;
--synthesis translate_on
end if;
end if;
end process;
end generate;
end generate gInfer;
assert VENDOR = VENDOR_XILINX or VENDOR = VENDOR_ALTERA
report "Device not yet supported."
severity failure;
end rtl;
| apache-2.0 | f446dd1224d518c483aaec57b6da7947 | 0.627348 | 3.476962 | false | false | false | false |
DreamIP/GPStudio | support/component/neighExtractor/neighExtractor.vhd | 1 | 10,317 | ---------------------------------------------------------------------------------
-- Design Name : neighExtractor
-- File Name : neighExtractor.vhd
-- Function : Extracts a generic neighborhood from serial in_data
-- Coder : Kamel ABDELOUAHAB
-- Institution : Institut Pascal
---------------------------------------------------------------------------------
-- ------------------
-- reset_n --->| |
-- clk --->| |
-- enable --->| |
-- | |---> out_data (pixel_array of size KERNEL_SIZE²)
-- | NE |---> out_dv
-- | |---> out_fv
-- in_data --->| |---> out_valid
-- in_dv --->| |
-- in_fv --->| |
-- | |
-- ------------------
-- out_data(0) out_data(1) out_data(2)
-- ^ ^ ^
-- | | |
-- ------- | ------- | ------- | ---------------------------
-- | | | | | | | | | | |
-- in_data --->| |---|--> | |---|--> | |---|-->| BUFFER |---> to_P1
-- | | | | | | | |
-- ------- ------- ------- ---------------------------
-- out_data(3) out_data(4) out_data(5)
-- ^ ^ ^
-- | | |
-- ------- | ------- | ------- | ---------------------------
-- | | | | | | | | | | |
-- P1 --->| |---|--> | |---|--> | |---|-->| BUFFER |---> to_P2
-- | | | | | | | |
-- ------- ------- ------- ---------------------------
-- out_data(6) out_data(7) out_data(8)
-- ^ ^ ^
-- | | |
-- ------- | ------- | ------- |
-- | | | | | | | | |
-- P2 --->| |---|--> | |---|--> | |---|
-- | | | | | |
-- ------- ------- -------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cnn_types.all;
entity neighExtractor is
generic(
PIXEL_SIZE : integer;
IMAGE_WIDTH : integer;
KERNEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector((PIXEL_SIZE-1) downto 0);
in_dv : in std_logic;
in_fv : in std_logic;
out_data : out pixel_array (0 to (KERNEL_SIZE * KERNEL_SIZE)- 1);
out_dv : out std_logic;
out_fv : out std_logic
);
end neighExtractor;
architecture rtl of neighExtractor is
-- signals
signal pixel_out : pixel_array(0 to KERNEL_SIZE-1);
-- components
component taps
generic (
PIXEL_SIZE : integer;
TAPS_WIDTH : integer;
KERNEL_SIZE : integer
);
port (
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE-1 downto 0);
taps_data : out pixel_array (0 to KERNEL_SIZE -1 );
out_data : out std_logic_vector (PIXEL_SIZE-1 downto 0)
);
end component;
component bit_taps
generic (
TAPS_WIDTH : integer
);
port (
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic;
out_data : out std_logic
);
end component;
signal all_valid : std_logic;
signal s_valid : std_logic;
signal tmp_dv : std_logic;
signal tmp_fv : std_logic;
begin
-- All valid : Logic and
all_valid <= in_dv and in_fv;
s_valid <= all_valid and enable;
----------------------------------------------------
-- SUPER FOR GENERATE : GO
----------------------------------------------------
taps_inst : for i in 0 to KERNEL_SIZE-1 generate
-- First line
gen_1 : if i=0 generate
gen1_inst : taps
generic map(
PIXEL_SIZE => PIXEL_SIZE,
TAPS_WIDTH => IMAGE_WIDTH ,
KERNEL_SIZE => KERNEL_SIZE
)
port map(
clk => clk,
reset_n => reset_n,
enable => s_valid,
in_data => in_data,
taps_data => out_data(0 to KERNEL_SIZE-1),
out_data => pixel_out(0)
);
end generate gen_1;
-- line i
gen_i : if i>0 and i<KERNEL_SIZE-1 generate
geni_inst : taps
generic map(
PIXEL_SIZE => PIXEL_SIZE,
TAPS_WIDTH => IMAGE_WIDTH,
KERNEL_SIZE => KERNEL_SIZE
)
port map(
clk => clk,
reset_n => reset_n,
enable => s_valid,
in_data => pixel_out(i-1),
taps_data => out_data(i * KERNEL_SIZE to KERNEL_SIZE*(i+1)-1),
out_data => pixel_out(i)
);
end generate gen_i;
-- Last line
gen_last : if i= (KERNEL_SIZE-1) generate
gen_last_inst : taps
generic map(
PIXEL_SIZE => PIXEL_SIZE,
TAPS_WIDTH => KERNEL_SIZE,
KERNEL_SIZE => KERNEL_SIZE
)
port map(
clk => clk,
reset_n => reset_n,
enable => s_valid,
in_data => pixel_out(i-1),
taps_data => out_data((KERNEL_SIZE-1) * KERNEL_SIZE to KERNEL_SIZE*KERNEL_SIZE - 1),
out_data => OPEN
);
end generate gen_last;
end generate taps_inst;
--------------------------------------------------------------------------
-- Manage out_dv and out_fv
--------------------------------------------------------------------------
dv_proc : process(clk)
-- 12 bits is enought to count until 4096
constant NBITS_DELAY : integer := 20;
variable delay_cmp : unsigned (NBITS_DELAY-1 downto 0) :=(others => '0');
variable edge_cmp : unsigned (NBITS_DELAY-1 downto 0) :=(others => '0');
begin
if (reset_n = '0') then
delay_cmp := (others => '0');
edge_cmp := (others => '0');
tmp_dv <='0';
tmp_fv <='0';
elsif (rising_edge(clk)) then
if(enable = '1') then
if (in_fv = '1') then
if(in_dv = '1') then
-- Initial delay : Wait until there is data in all the taps
if (delay_cmp >= to_unsigned((KERNEL_SIZE-1)*IMAGE_WIDTH + KERNEL_SIZE - 1 , NBITS_DELAY)) then
-- Taps are full : Frame can start
tmp_fv <= '1';
if ( edge_cmp > to_unsigned (IMAGE_WIDTH - KERNEL_SIZE, NBITS_DELAY)) then
-- If at edge : data is NOT valid
if ( edge_cmp = to_unsigned (IMAGE_WIDTH - 1, NBITS_DELAY)) then
edge_cmp := (others => '0');
tmp_dv <= '0';
else
edge_cmp := edge_cmp + to_unsigned(1,NBITS_DELAY);
tmp_dv <= '0';
end if;
-- Else : Data is valid
else
edge_cmp := edge_cmp + to_unsigned(1,NBITS_DELAY);
tmp_dv <= '1';
end if;
-- When taps are nor full : Frame is not valid , neither is data
else
delay_cmp := delay_cmp + to_unsigned(1,NBITS_DELAY);
tmp_dv <= '0';
tmp_fv <= '0';
end if;
else
tmp_dv <= '0';
end if;
-- When Fv = 0 (New frame comming): reset counters
else
delay_cmp := (others => '0');
edge_cmp := (others => '0');
tmp_dv <= '0';
tmp_fv <= '0';
end if;
-- When enable = 0
else
delay_cmp := (others => '0');
edge_cmp := (others => '0');
tmp_dv <= '0';
tmp_fv <= '0';
end if;
end if;
end process;
out_dv <= tmp_dv;
out_fv <= tmp_fv;
end architecture;
| gpl-3.0 | 128b1cf77654a6b0bdfa8b30b949437d | 0.301764 | 4.619794 | false | false | false | false |
hoglet67/ElectronFpga | src/altera/ElectronFpga_de1.vhd | 1 | 14,305 | -- Acorn Electron for the Altera/Terasic DE1
--
-- Copright (c) 2015 David Banks
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- Generic top-level entity for Altera DE1 board
entity ElectronFpga_de1 is
port (
-- Clocks
CLOCK_24_0 : in std_logic;
CLOCK_24_1 : in std_logic;
CLOCK_27_0 : in std_logic;
CLOCK_27_1 : in std_logic;
CLOCK_50 : in std_logic;
EXT_CLOCK : in std_logic;
-- Switches
SW : in std_logic_vector(9 downto 0);
-- Buttons
KEY : in std_logic_vector(3 downto 0);
-- 7 segment displays
HEX0 : out std_logic_vector(6 downto 0);
HEX1 : out std_logic_vector(6 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
-- Red LEDs
LEDR : out std_logic_vector(9 downto 0);
-- Green LEDs
LEDG : out std_logic_vector(7 downto 0);
-- VGA
VGA_R : out std_logic_vector(3 downto 0);
VGA_G : out std_logic_vector(3 downto 0);
VGA_B : out std_logic_vector(3 downto 0);
VGA_HS : out std_logic;
VGA_VS : out std_logic;
-- Serial
UART_RXD : in std_logic;
UART_TXD : out std_logic;
-- PS/2 Keyboard
PS2_CLK : in std_logic;
PS2_DAT : in std_logic;
-- I2C
I2C_SCLK : inout std_logic;
I2C_SDAT : inout std_logic;
-- Audio
AUD_XCK : out std_logic;
AUD_BCLK : out std_logic;
AUD_ADCLRCK : out std_logic;
AUD_ADCDAT : in std_logic;
AUD_DACLRCK : out std_logic;
AUD_DACDAT : out std_logic;
-- SRAM
SRAM_ADDR : out std_logic_vector(17 downto 0);
SRAM_DQ : inout std_logic_vector(15 downto 0);
SRAM_CE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_WE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
-- SDRAM
DRAM_ADDR : out std_logic_vector(11 downto 0);
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_BA_0 : in std_logic;
DRAM_BA_1 : in std_logic;
DRAM_CAS_N : in std_logic;
DRAM_CKE : in std_logic;
DRAM_CLK : in std_logic;
DRAM_CS_N : in std_logic;
DRAM_LDQM : in std_logic;
DRAM_RAS_N : in std_logic;
DRAM_UDQM : in std_logic;
DRAM_WE_N : in std_logic;
-- Flash
FL_ADDR : out std_logic_vector(21 downto 0);
FL_DQ : in std_logic_vector(7 downto 0);
FL_RST_N : out std_logic;
FL_OE_N : out std_logic;
FL_WE_N : out std_logic;
FL_CE_N : out std_logic;
-- SD card (SPI mode)
SD_nCS : out std_logic;
SD_MOSI : out std_logic;
SD_SCLK : out std_logic;
SD_MISO : in std_logic;
-- GPIO
GPIO_0 : inout std_logic_vector(35 downto 0);
GPIO_1 : inout std_logic_vector(35 downto 0)
);
end entity;
architecture rtl of ElectronFpga_de1 is
-------------
-- Signals
-------------
signal clock_16 : std_logic;
signal clock_24 : std_logic;
signal clock_32 : std_logic;
signal clock_33 : std_logic;
signal clock_40 : std_logic;
signal i2s_lrclk : std_logic;
signal audio_l : std_logic;
signal audio_r : std_logic;
signal hard_reset_n : std_logic;
signal pll_reset : std_logic;
signal pll1_locked : std_logic;
signal pll2_locked : std_logic;
signal motor_led : std_logic;
signal caps_led : std_logic;
signal pcm_inl : std_logic_vector(15 downto 0);
signal pcm_inr : std_logic_vector(15 downto 0);
signal pcm_outl : std_logic_vector(15 downto 0);
signal pcm_outr : std_logic_vector(15 downto 0);
signal pcm_mono : std_logic_vector(8 downto 0);
signal pcm_sign : std_logic;
signal pcm_mag : std_logic_vector(7 downto 0);
signal ext_A : std_logic_vector (18 downto 0);
signal ext_Din : std_logic_vector (7 downto 0);
signal ext_Dout : std_logic_vector (7 downto 0);
signal ext_nCS : std_logic;
signal ext_nWE : std_logic;
signal ext_nOE : std_logic;
signal is_done : std_logic;
signal is_error : std_logic;
signal cpu_addr : std_logic_vector (15 downto 0);
signal cas_monitor : std_logic;
signal cas_in : std_logic;
signal cas_out : std_logic; -- currently not used
function hex_to_seven_seg(hex: std_logic_vector(3 downto 0))
return std_logic_vector
is begin
case hex is
-- abcdefg
when x"0" => return "0111111";
when x"1" => return "0000110";
when x"2" => return "1011011";
when x"3" => return "1001111";
when x"4" => return "1100110";
when x"5" => return "1101101";
when x"6" => return "1111101";
when x"7" => return "0000111";
when x"8" => return "1111111";
when x"9" => return "1101111";
when x"a" => return "1110111";
when x"b" => return "1111100";
when x"c" => return "0111001";
when x"d" => return "1011110";
when x"e" => return "1111001";
when x"f" => return "1110001";
when others => return "0000000";
end case;
end;
begin
--------------------------------------------------------
-- Clock Generation
--------------------------------------------------------
pll1: entity work.pll1
port map (
areset => pll_reset,
inclk0 => CLOCK_24_0,
c0 => clock_16,
c1 => clock_32,
c2 => clock_40,
locked => pll1_locked
);
pll2: entity work.pll2
port map (
areset => pll_reset,
inclk0 => CLOCK_50,
c0 => clock_33,
locked => pll2_locked
);
clock_24 <= CLOCK_24_0;
--------------------------------------------------------
-- Electron Core
--------------------------------------------------------
electron_core : entity work.ElectronFpga_core
generic map (
IncludeICEDebugger => false,
IncludeABRRegs => true,
IncludeJafaMode7 => true
)
port map (
clk_16M00 => clock_16,
clk_24M00 => clock_24,
clk_32M00 => clock_32,
clk_33M33 => clock_33,
clk_40M00 => clock_40,
hard_reset_n => hard_reset_n,
ps2_clk => PS2_CLK,
ps2_data => PS2_DAT,
video_red => VGA_R,
video_green => VGA_G,
video_blue => VGA_B,
video_vsync => VGA_VS,
video_hsync => VGA_HS,
audio_l => audio_l,
audio_r => audio_r,
ext_nOE => ext_nOE,
ext_nWE => ext_nWE,
ext_nCS => ext_nCS,
ext_A => ext_A,
ext_Dout => ext_Dout,
ext_Din => ext_Din,
SDMISO => SD_MISO,
SDSS => SD_nCS,
SDCLK => SD_SCLK,
SDMOSI => SD_MOSI,
caps_led => caps_led,
motor_led => motor_led,
cassette_in => cas_in,
cassette_out => cas_out,
vid_mode => SW(8 downto 7),
test => open,
avr_RxD => UART_RXD,
avr_TxD => UART_TXD,
cpu_addr => cpu_addr
);
--------------------------------------------------------
-- Power Up Reset Generation
--------------------------------------------------------
-- Asynchronous reset
-- PLL is reset by external reset switch
pll_reset <= not KEY(0);
hard_reset_n <= not (pll_reset or not pll1_locked or not pll2_locked);
--------------------------------------------------------
-- Audio DACs
--------------------------------------------------------
-- implement tape monitoring controlled by the motor and SW1
cas_monitor <= motor_led and SW(0);
pcm_outl <= "0" & audio_l & "00000000000000" when cas_monitor <= '0' else pcm_inl;
pcm_outr <= "0" & audio_r & "00000000000000" when cas_monitor <= '0' else pcm_inr;
i2s : entity work.i2s_intf
port map (
CLK => clock_32,
nRESET => hard_reset_n,
PCM_INL => pcm_inl,
PCM_INR => pcm_inr,
PCM_OUTL => pcm_outl,
PCM_OUTR => pcm_outr,
I2S_MCLK => AUD_XCK,
I2S_LRCLK => i2s_lrclk,
I2S_BCLK => AUD_BCLK,
I2S_DOUT => AUD_DACDAT,
I2S_DIN => AUD_ADCDAT
);
AUD_DACLRCK <= i2s_lrclk;
AUD_ADCLRCK <= i2s_lrclk;
i2c : entity work.i2c_loader
generic map (
log2_divider => 7
)
port map (
CLK => clock_32,
nRESET => hard_reset_n,
I2C_SCL => I2C_SCLK,
I2C_SDA => I2C_SDAT,
IS_DONE => is_done,
IS_ERROR => is_error
);
--------------------------------------------------------
-- Casette Input (from Line In)
--------------------------------------------------------
-- generate an 9 bit mono audio signal
pcm_mono <= (pcm_INL(15) & pcm_INL(15 downto 8)) + (pcm_INR(15) & pcm_INR(15 downto 8));
-- convert to sign and 8-bit magnitude
pcm_sign <= pcm_mono(8);
pcm_mag <= pcm_mono(7 downto 0) when pcm_mono(8) = '0' else (x"00" - pcm_mono(7 downto 0));
-- the casette input is driven from the sign of the mono signal
cas_in <= pcm_sign;
--------------------------------------------------------
-- LEDs
--------------------------------------------------------
-- Red LEDs
LEDR(0) <= caps_led;
LEDR(1) <= motor_led;
LEDR(3 downto 2) <= (others => '0');
LEDR(4) <= is_error;
LEDR(5) <= not is_done;
LEDR(9 downto 6) <= (others => '0');
-- Green LEDs used as a simple VU meter for the tape input level
-- driven from the magnitude of the mono line-in signal. Reversing
-- the bits gives a more natural left-to-right appearance.
LEDG(0) <= pcm_mag(7) when motor_led = '1' else '0';
LEDG(1) <= pcm_mag(6) when motor_led = '1' else '0';
LEDG(2) <= pcm_mag(5) when motor_led = '1' else '0';
LEDG(3) <= pcm_mag(4) when motor_led = '1' else '0';
LEDG(4) <= pcm_mag(3) when motor_led = '1' else '0';
LEDG(5) <= pcm_mag(2) when motor_led = '1' else '0';
LEDG(6) <= pcm_mag(1) when motor_led = '1' else '0';
LEDG(7) <= pcm_mag(0) when motor_led = '1' else '0';
-- HEX Displays (active low) show current processor address
HEX3 <= hex_to_seven_seg(cpu_addr(15 downto 12)) xor "1111111";
HEX2 <= hex_to_seven_seg(cpu_addr(11 downto 8)) xor "1111111";
HEX1 <= hex_to_seven_seg(cpu_addr( 7 downto 4)) xor "1111111";
HEX0 <= hex_to_seven_seg(cpu_addr( 3 downto 0)) xor "1111111";
--------------------------------------------------------
-- Map external memory bus to SRAM/FLASH
--------------------------------------------------------
-- 4MB FLASH Layout
-- 0x000000-0x05FFFF = BBC ROMs
-- 0x060000-0x07FFFF = Unused
-- 0x080000-0x0BFFFF = Electron ROMs
-- 0x0C0000-0x3FFFFF - Unused
-- ext_a(18) selects between FLASH and SRAM
-- 0x00000-0x3FFFF -> FLASH 0x080000-0x0BFFFF
-- 0x40000-0x7FFFF -> SRAM
ext_Dout <= SRAM_DQ(7 downto 0) when ext_a(18) = '1' else FL_DQ;
-- FLASH control signals
FL_RST_N <= hard_reset_n;
FL_CE_N <= ext_nCS;
FL_OE_N <= ext_nOE;
FL_WE_N <= '1';
-- Flash address change every at most every 16 cycles (2MHz)
-- 001 maps to FLASH address 0x080000
FL_ADDR <= "001" & ext_a;
-- SRAM control signals
SRAM_UB_N <= '1';
SRAM_LB_N <= '0';
SRAM_CE_N <= ext_nCS;
SRAM_OE_N <= ext_nOE;
-- Gate the WE with clock to provide more address/data hold time
SRAM_WE_N <= ext_nWE or not clock_16;
SRAM_ADDR <= ext_a(17 downto 0);
SRAM_DQ(15 downto 8) <= (others => 'Z');
SRAM_DQ(7 downto 0) <= ext_Din when ext_nWE = '0' else (others => 'Z');
-- Unused outputs
DRAM_ADDR <= (others => 'Z');
DRAM_DQ <= (others => 'Z');
end architecture;
| gpl-3.0 | e43c42398c36c8f83c78206cfdad538c | 0.512548 | 3.508707 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_onchip_memory2_0_s1_translator.vhd | 1 | 12,673 | -- tracking_camera_system_onchip_memory2_0_s1_translator.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.13.13:59:38
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tracking_camera_system_onchip_memory2_0_s1_translator is
generic (
AV_ADDRESS_W : integer := 12;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 1;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(11 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_chipselect : out std_logic; -- .chipselect
av_clken : out std_logic; -- .clken
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_read : out std_logic;
av_readdatavalid : in std_logic := '0';
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(3 downto 0);
uav_clken : in std_logic := '0'
);
end entity tracking_camera_system_onchip_memory2_0_s1_translator;
architecture rtl of tracking_camera_system_onchip_memory2_0_s1_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(11 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component altera_merlin_slave_translator;
begin
onchip_memory2_0_s1_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_chipselect => av_chipselect, -- .chipselect
av_clken => av_clken, -- .clken
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
end architecture rtl; -- of tracking_camera_system_onchip_memory2_0_s1_translator
| gpl-2.0 | 88986e824a133fab96a9549972c51d0a | 0.433915 | 4.274199 | false | false | false | false |
ou-cse-378/vhdl-tetris | plus1a.vhd | 1 | 732 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: plus1a.vhd
-- // Date: 12/9/2004
-- // Description: Adds 1 to the input
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity plus1a is
Port ( input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(15 downto 0));
end plus1a;
architecture plus1a_arch of plus1a is
begin
process(input)
begin
output <= (input + '1');
end process;
end plus1a_arch;
| mit | 03ed1402b0db741e9fa86d6ea2dbf2d7 | 0.491803 | 3.641791 | false | false | false | false |
DreamIP/GPStudio | support/process/sconv/hdl/sconv_slave.vhd | 1 | 4,336 | -- Author : K. Abdelouahab
-- Company : DREAM - Institut Pascal - Unviersite Clermont Auvergne
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity conv_slave is
port (
clk_proc : in std_logic;
reset_n : in std_logic;
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0);
enable_o : out std_logic;
widthimg_o : out std_logic_vector(15 downto 0);
w11_o : out std_logic_vector (7 downto 0);
w12_o : out std_logic_vector (7 downto 0);
w13_o : out std_logic_vector (7 downto 0);
w21_o : out std_logic_vector (7 downto 0);
w22_o : out std_logic_vector (7 downto 0);
w23_o : out std_logic_vector (7 downto 0);
w31_o : out std_logic_vector (7 downto 0);
w32_o : out std_logic_vector (7 downto 0);
w33_o : out std_logic_vector (7 downto 0);
norm_o : out std_logic_vector (7 downto 0)
);
end conv_slave;
architecture rtl of conv_slave is
constant ENABLE_REG_ADDR : natural := 0;
constant WIDTHIMG_REG_ADDR : natural := 1;
constant W11_ADDR : natural := 2;
constant W12_ADDR : natural := 3;
constant W13_ADDR : natural := 4;
constant W21_ADDR : natural := 5;
constant W22_ADDR : natural := 6;
constant W23_ADDR : natural := 7;
constant W31_ADDR : natural := 8;
constant W32_ADDR : natural := 9;
constant W33_ADDR : natural := 10;
constant NORM_ADDR : natural := 11;
signal enable_reg : std_logic;
signal widthimg_reg : std_logic_vector(15 downto 0);
signal w11_reg : std_logic_vector(7 downto 0);
signal w12_reg : std_logic_vector(7 downto 0);
signal w13_reg : std_logic_vector(7 downto 0);
signal w21_reg : std_logic_vector(7 downto 0);
signal w22_reg : std_logic_vector(7 downto 0);
signal w23_reg : std_logic_vector(7 downto 0);
signal w31_reg : std_logic_vector(7 downto 0);
signal w32_reg : std_logic_vector(7 downto 0);
signal w33_reg : std_logic_vector(7 downto 0);
signal norm_reg : std_logic_vector(7 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
enable_reg <= '0';
widthimg_reg <= std_logic_vector(to_unsigned(320, 16));
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(ENABLE_REG_ADDR, 4)) => enable_reg <= datawr_i(0);
when std_logic_vector(to_unsigned(WIDTHIMG_REG_ADDR, 4)) => widthimg_reg <= datawr_i(15 downto 0);
when std_logic_vector(to_unsigned(W11_ADDR, 4)) => w11_reg <= datawr_i (7 downto 0);
when std_logic_vector(to_unsigned(W12_ADDR, 4)) => w12_reg <= datawr_i (7 downto 0);
when std_logic_vector(to_unsigned(W13_ADDR, 4)) => w13_reg <= datawr_i (7 downto 0);
when std_logic_vector(to_unsigned(W21_ADDR, 4)) => w21_reg <= datawr_i (7 downto 0);
when std_logic_vector(to_unsigned(W22_ADDR, 4)) => w22_reg <= datawr_i (7 downto 0);
when std_logic_vector(to_unsigned(W23_ADDR, 4)) => w23_reg <= datawr_i (7 downto 0);
when std_logic_vector(to_unsigned(W31_ADDR, 4)) => w31_reg <= datawr_i (7 downto 0);
when std_logic_vector(to_unsigned(W32_ADDR, 4)) => w32_reg <= datawr_i (7 downto 0);
when std_logic_vector(to_unsigned(W33_ADDR, 4)) => w33_reg <= datawr_i (7 downto 0);
when std_logic_vector(to_unsigned(NORM_ADDR, 4)) => norm_reg <= datawr_i (7 downto 0);
when others=>
end case;
end if;
end if;
end process;
enable_o <= enable_reg;
widthimg_o <= widthimg_reg;
w11_o <= w11_reg;
w12_o <= w12_reg;
w13_o <= w13_reg;
w21_o <= w21_reg;
w22_o <= w22_reg;
w23_o <= w23_reg;
w31_o <= w31_reg;
w32_o <= w32_reg;
w33_o <= w33_reg;
norm_o <= norm_reg;
end rtl;
| gpl-3.0 | f7f2dafc963934b2474e5df1ee20d647 | 0.556965 | 3.009022 | false | false | false | false |
ou-cse-378/vhdl-tetris | ctr2bit.vhd | 1 | 860 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: ctr2bit.vhd
-- // Date: 12/9/2004
-- // Description: Display component
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ctr2bit is
port (
clr : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (1 downto 0)
);
end ctr2bit;
architecture ctr2bit_arch of ctr2bit is
begin
process (clk, clr)
variable COUNT: STD_LOGIC_VECTOR (1 downto 0);
begin
if clr = '1' then
COUNT := "00";
elsif clk'event and clk='1' then
COUNT := COUNT + 1;
end if;
q <= COUNT;
end process;
end ctr2bit_arch;
| mit | 2bc7c43b505b15ecd1fa84ab60714f16 | 0.489535 | 3.659574 | false | false | false | false |
DreamIP/GPStudio | support/process/fast/hdl/components/taps.vhd | 1 | 1,112 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fast_types.all;
entity taps is
generic (
PIXEL_SIZE : integer;
TAPS_WIDTH : integer;
KERNEL_SIZE : integer
);
port (
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE-1 downto 0);
taps_data : out pixel_array (0 to KERNEL_SIZE -1 );
out_data : out std_logic_vector (PIXEL_SIZE-1 downto 0)
);
end taps;
architecture bhv of taps is
signal cell : pixel_array (0 to TAPS_WIDTH-1);
begin
process(clk)
variable i : integer := 0;
begin
if ( reset_n = '0' ) then
cell <= (others =>(others => '0'));
out_data <= (others => '0');
taps_data <= (others =>(others => '0'));
elsif (rising_edge(clk)) then
if (enable='1') then
cell(0) <= in_data;
for i in 1 to (TAPS_WIDTH-1) loop
cell(i) <= cell(i-1);
end loop;
taps_data <= cell(0 to KERNEL_SIZE-1);
out_data <= cell(TAPS_WIDTH-1);
end if;
end if;
end process;
end bhv;
| gpl-3.0 | 5861536899fbcc933c9619f441004d3c | 0.57554 | 2.544622 | false | false | false | false |
hoglet67/ElectronFpga | src/common/RAM/RAM_32K_DualPort.vhd | 2 | 1,236 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RAM_32K_DualPort is
port (
clka : in std_logic;
wea : in std_logic;
addra : in std_logic_vector(14 downto 0);
dina : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0);
clkb : in std_logic;
web : in std_logic;
addrb : in std_logic_vector(14 downto 0);
dinb : in std_logic_vector(7 downto 0);
doutb : out std_logic_vector(7 downto 0)
);
end;
architecture behavioral of RAM_32K_DualPort is
type ram_type is array (32767 downto 0) of std_logic_vector (7 downto 0);
shared variable RAM : ram_type;
begin
process (clka)
begin
if rising_edge(clka) then
if (wea = '1') then
RAM(conv_integer(addra)) := dina;
end if;
douta <= RAM(conv_integer(addra));
end if;
end process;
process (clkb)
begin
if rising_edge(clkb) then
if (web = '1') then
RAM(conv_integer(addrb)) := dinb;
end if;
doutb <= RAM(conv_integer(addrb));
end if;
end process;
end behavioral;
| gpl-3.0 | 16a50e72e10332d3fa82602256322745 | 0.550162 | 3.551724 | false | false | false | false |
marzoul/PoC | src/io/io_FanControl.vhdl | 1 | 10,106 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Generic Fan Controller
--
-- Description:
-- ------------------------------------
-- This module generates a PWM signal for a 3-pin (transistor controlled) or
-- 4-pin fan header. The FPGAs temperature is read from device specific system
-- monitors (normal, user temperature, over temperature).
--
-- For example the Xilinx System Monitors are configured as follows:
--
-- | /-----\
-- Temp_ov on=80 | - - - - - - /-------/ \
-- | / | \
-- Temp_ov off=60 | - - - - - / - - - - | - - - - \----\
-- | / | \
-- | / | | \
-- Temp_us on=35 | - /---/ | | \
-- Temp_us off=30 | - / - -|- - - - - - | - - - - - - -|- \------\
-- | / | | | \
-- ----------------|--------|------------|--------------|----------|---------
-- pwm = | min | medium | max | medium | min
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.xil.all;
entity io_FanControl is
generic (
CLOCK_FREQ : FREQ;
ADD_INPUT_SYNCHRONIZERS : BOOLEAN := TRUE;
ENABLE_TACHO : BOOLEAN := FALSE
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Fan_PWM : out STD_LOGIC;
Fan_Tacho : in STD_LOGIC;
TachoFrequency : out STD_LOGIC_VECTOR(ite(ENABLE_TACHO, 16, 1) - 1 downto 0)
);
end;
architecture rtl of io_FanControl is
constant TIME_STARTUP : TIME := 500 ms; -- StartUp time
constant PWM_RESOLUTION : POSITIVE := 4; -- 4 Bit resolution => 0 to 15 steps
constant PWM_FREQ : FREQ := 10 Hz; --
constant TACHO_RESOLUTION : POSITIVE := 8;
signal PWM_PWMIn : STD_LOGIC_VECTOR(PWM_RESOLUTION - 1 downto 0);
signal PWM_PWMOut : STD_LOGIC := '0';
begin
-- System Monitor and temperature to PWM ratio calculation for Virtex6
-- ==========================================================================================================================================================
genXilinx : if (VENDOR = VENDOR_XILINX) generate
signal OverTemperature_async : STD_LOGIC;
signal OverTemperature_sync : STD_LOGIC;
signal UserTemperature_async : STD_LOGIC;
signal UserTemperature_sync : STD_LOGIC;
signal TC_Timeout : STD_LOGIC;
signal StartUp : STD_LOGIC;
begin
genML605 : if (BOARD = BOARD_ML605) generate
SystemMonitor : xil_SystemMonitor_Virtex6
port map (
Reset => Reset, -- Reset signal for the System Monitor control logic
Alarm_UserTemp => UserTemperature_async, -- Temperature-sensor alarm output
Alarm_OverTemp => OverTemperature_async, -- Over-Temperature alarm output
Alarm => open, -- OR'ed output of all the Alarms
VP => '0', -- Dedicated Analog Input Pair
VN => '0'
);
end generate;
genSeries7Board : if ((BOARD = BOARD_KC705) or (BOARD = BOARD_VC707)) generate
SystemMonitor : xil_SystemMonitor_Series7
port map (
Reset => Reset, -- Reset signal for the System Monitor control logic
Alarm_UserTemp => UserTemperature_async, -- Temperature-sensor alarm output
Alarm_OverTemp => OverTemperature_async, -- Over-Temperature alarm output
Alarm => open, -- OR'ed output of all the Alarms
VP => '0', -- Dedicated Analog Input Pair
VN => '0'
);
end generate;
sync : entity PoC.sync_Bits
generic map (
BITS => 2
)
port map (
Clock => Clock,
Input(0) => OverTemperature_async,
Input(1) => UserTemperature_async,
Output(0) => OverTemperature_sync,
Output(1) => UserTemperature_sync
);
-- timer for warm-up control
-- ==========================================================================================================================================================
TC : entity PoC.io_TimingCounter
generic map (
TIMING_TABLE => (0 => TimingToCycles(TIME_STARTUP, CLOCK_FREQ)) -- timing table
)
port map (
Clock => Clock, -- clock
Enable => StartUp, -- enable counter
Load => '0', -- load Timing Value from TIMING_TABLE selected by slot
Slot => 0, --
Timeout => TC_Timeout -- timing reached
);
StartUp <= not TC_Timeout;
process(StartUp, UserTemperature_sync, OverTemperature_sync)
begin
if (StartUp = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100%; start up
elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100%
elsif (UserTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION - 1), PWM_RESOLUTION); -- 50%
else PWM_PWMIn <= to_slv(4, PWM_RESOLUTION); -- 13%
end if;
end process;
end generate;
genAltera : if (VENDOR = VENDOR_ALTERA) generate
-- signal OverTemperature_async : STD_LOGIC;
signal OverTemperature_sync : STD_LOGIC;
-- signal UserTemperature_async : STD_LOGIC;
signal UserTemperature_sync : STD_LOGIC;
signal TC_Timeout : STD_LOGIC;
signal StartUp : STD_LOGIC;
begin
genDE4 : if (BOARD = BOARD_DE4) generate
OverTemperature_sync <= '0';
UserTemperature_sync <= '1';
end generate;
-- timer for warm-up control
-- ==========================================================================================================================================================
TC : entity PoC.io_TimingCounter
generic map (
TIMING_TABLE => (0 => TimingToCycles(TIME_STARTUP, CLOCK_FREQ)) -- timing table
)
port map (
Clock => Clock, -- clock
Enable => StartUp, -- enable counter
Load => '0', -- load Timing Value from TIMING_TABLE selected by slot
Slot => 0, --
Timeout => TC_Timeout -- timing reached
);
StartUp <= not TC_Timeout;
process(StartUp, UserTemperature_sync, OverTemperature_sync)
begin
if (StartUp = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100%; start up
elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100%
elsif (UserTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION - 1), PWM_RESOLUTION); -- 50%
else PWM_PWMIn <= to_slv(4, PWM_RESOLUTION); -- 13%
end if;
end process;
end generate;
-- PWM signal modulator
-- ==========================================================================================================================================================
PWM : entity PoC.io_PulseWidthModulation
generic map (
CLOCK_FREQ => CLOCK_FREQ, --
PWM_FREQ => PWM_FREQ, --
PWM_RESOLUTION => PWM_RESOLUTION --
)
port map (
Clock => Clock,
Reset => Reset,
PWMIn => PWM_PWMIn,
PWMOut => PWM_PWMOut
);
-- registered output
Fan_PWM <= PWM_PWMOut when rising_edge(Clock);
-- tacho signal interpretation -> convert to RPM
-- ==========================================================================================================================================================
genNoTacho : if (ENABLE_TACHO = FALSE) generate
TachoFrequency <= (TachoFrequency'range => '0');
end generate;
genTacho : if (ENABLE_TACHO = TRUE) generate
signal Tacho_sync : STD_LOGIC;
signal Tacho_Freq : STD_LOGIC_VECTOR(TACHO_RESOLUTION - 1 downto 0);
begin
-- Input Synchronization
genNoSync : if (ADD_INPUT_SYNCHRONIZERS = FALSE) generate
Tacho_sync <= Fan_Tacho;
end generate;
genSync : if (ADD_INPUT_SYNCHRONIZERS = TRUE) generate
sync_i : entity PoC.sync_Bits
port map (
Clock => Clock, -- Clock to be synchronized to
Input(0) => Fan_Tacho, -- Data to be synchronized
Output(0) => Tacho_sync -- synchronised data
);
end generate;
Tacho : entity PoC.io_FrequencyCounter
generic map (
CLOCK_FREQ => CLOCK_FREQ, --
TIMEBASE => (60 sec / 64), -- ca. 1 second
RESOLUTION => 8 -- max. ca. 256 RPS -> max. ca. 16k RPM
)
port map (
Clock => Clock,
Reset => Reset,
FreqIn => Tacho_sync,
FreqOut => Tacho_Freq
);
-- multiply by 64; divide by 2 for RPMs (2 impulses per revolution) => append 5x '0'
TachoFrequency <= resize(Tacho_Freq & "00000", TachoFrequency'length); -- resizing to 16 bit
end generate;
end;
| apache-2.0 | df68fb80c5e06616170943cced6f2ddb | 0.516426 | 3.626121 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/video_system_pixel_buffer_avalon_sram_slave_translator.vhd | 1 | 12,666 | -- video_system_pixel_buffer_avalon_sram_slave_translator.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.09.14:34:21
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity video_system_pixel_buffer_avalon_sram_slave_translator is
generic (
AV_ADDRESS_W : integer := 18;
AV_DATA_W : integer := 16;
UAV_DATA_W : integer := 16;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 2;
UAV_BYTEENABLE_W : integer := 2;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 2;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 2;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(31 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- .readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(17 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(15 downto 0); -- .writedata
av_byteenable : out std_logic_vector(1 downto 0); -- .byteenable
av_readdatavalid : in std_logic := '0'; -- .readdatavalid
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(1 downto 0);
uav_clken : in std_logic := '0'
);
end entity video_system_pixel_buffer_avalon_sram_slave_translator;
architecture rtl of video_system_pixel_buffer_avalon_sram_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(17 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_byteenable : out std_logic_vector(1 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(1 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component altera_merlin_slave_translator;
begin
pixel_buffer_avalon_sram_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_readdatavalid => av_readdatavalid, -- .readdatavalid
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
end architecture rtl; -- of video_system_pixel_buffer_avalon_sram_slave_translator
| gpl-2.0 | f3e5aad122c1121f03aa2390d1684961 | 0.436049 | 4.287745 | false | false | false | false |
DreamIP/GPStudio | support/io/vga_out/hdl/vga_controller.vhd | 1 | 10,063 | -------------------------------------------------------------------------------
-- Copyright Institut Pascal Equipe Dream (19-10-2016)
-- Francois Berry, El Mehdi Abdali, Maxime Pelcat
-- This software is a computer program whose purpose is to manage dynamic
-- partial reconfiguration.
-- This software is governed by the CeCILL-C license under French law and
-- abiding by the rules of distribution of free software. You can use,
-- modify and/ or redistribute the software under the terms of the CeCILL-C
-- license as circulated by CEA, CNRS and INRIA at the following URL
-- "http://www.cecill.info".
-- As a counterpart to the access to the source code and rights to copy,
-- modify and redistribute granted by the license, users are provided only
-- with a limited warranty and the software's author, the holder of the
-- economic rights, and the successive licensors have only limited
-- liability.
-- In this respect, the user's attention is drawn to the risks associated
-- with loading, using, modifying and/or developing or reproducing the
-- software by the user in light of its specific status of free software,
-- that may mean that it is complicated to manipulate, and that also
-- therefore means that it is reserved for developers and experienced
-- professionals having in-depth computer knowledge. Users are therefore
-- encouraged to load and test the software's suitability as regards their
-- requirements in conditions enabling the security of their systems and/or
-- data to be ensured and, more generally, to use and operate it in the
-- same conditions as regards security.
-- The fact that you are presently reading this means that you have had
-- knowledge of the CeCILL-C license and that you accept its terms.
-------------------------------------------------------------------------------
-- Doxygen Comments -----------------------------------------------------------
--! @file vga_controller.vhd
--
--! @brief Displaying image on VGA from internal memory
--! @author Francois Berry, El Mehdi Abdali, Maxime Pelcat
--! @board DE1-SoC from Terasic
--! @version 1.0
--! @date 03/02/2017
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity vga_controller is
port(
-----
-- Board I/Os
OSC_50 : in std_logic;
RESET_N : in std_logic;
VGA_HS, VGA_VS : out std_logic;
VGA_SYNC, VGA_BLANK : out std_logic;
VGA_RED, VGA_GREEN, VGA_BLUE : out std_logic_vector(7 downto 0);
CLOCK108 : out std_logic;
x_offset : in integer range 0 to 1280; -- offset of the upper left pixel
y_offset : in integer range 0 to 1024;
-----
-- GPStudio i/os
data : in std_logic_vector(7 downto 0);
fv : in std_logic; -- frame valid
dv : in std_logic -- data valid
);
end vga_controller;
architecture hdl of vga_controller is
component PLL108
port (
refclk : in std_logic := '0'; -- refclk.clk
rst : in std_logic := '0'; -- reset.reset
outclk_0 : out std_logic -- outclk0.clk
);
end component PLL108;
component vga_generate
port(
CLOCK : in std_logic;
PIX_IN : in std_logic_vector(7 downto 0);
RESET : in std_logic;
HSYNC, VSYNC : out std_logic;
SYNC, BLANK : out std_logic;
RED, GREEN, BLUE : out std_logic_vector(7 downto 0);
DISPLAY : out std_logic;
X : out integer range 0 to 1280 := 0;
Y : out integer range 0 to 1024 := 0
);
end component vga_generate;
component FrameBuffer
port
(
data : in std_logic_vector (7 downto 0);
rdaddress : in std_logic_vector (14 downto 0);
rdclock : in std_logic;
wraddress : in std_logic_vector (14 downto 0);
wrclock : in std_logic := '1';
wren : in std_logic := '0';
q : out std_logic_vector (7 downto 0)
);
end component FrameBuffer;
signal rdaddress : std_logic_vector (14 downto 0);
signal PIX_IN_fb1 : std_logic_vector(7 downto 0); -- VGA input signal when using frame buffer 1
signal PIX_IN_fb2 : std_logic_vector(7 downto 0); -- VGA input signal when using frame buffer 2
signal PIX_IN : std_logic_vector(7 downto 0); -- VGA input signal
signal X : integer range 0 to 1280 := 0;
signal Y : integer range 0 to 1024 := 0;
signal wrdata : std_logic_vector (7 downto 0); -- data to write in the frame buffer
signal wraddress : std_logic_vector (14 downto 0); -- address to write to in the frame buffer
signal wren : std_logic; -- enabling writing to memory
signal fb_index : std_logic; -- 0 to write on fb1, read on fb2; 1 to write on fb2, readon fb1
signal OSC_108_own : std_logic;
begin
-- Bug fix:ignoring GPStudio clock andd generating own 108MHz
PLL108_inst : PLL108
port map
(
refclk => OSC_50,
rst => not RESET_N,
outclk_0 => OSC_108_own
);
VGA_inst : vga_generate
port map
(
CLOCK => OSC_108_own,
PIX_IN => PIX_IN,
RESET => not RESET_N,
HSYNC => VGA_HS,
VSYNC => VGA_VS,
SYNC => VGA_SYNC,
BLANK => VGA_BLANK,
RED => VGA_RED,
GREEN => VGA_GREEN,
BLUE => VGA_BLUE,
X => X,
Y => Y
);
-- Frame buffer with 2 different clock domain
-- 2 frame buffers are instanciated and flipped
FrameBuffer_inst1 : FrameBuffer
port map
(
data => wrdata, -- input data
wraddress => wraddress,
wrclock => OSC_50,
wren => wren and (not fb_index),
rdaddress => rdaddress,
rdclock => OSC_108_own,
q => PIX_IN_fb1 -- output data
);
FrameBuffer_inst2 : FrameBuffer
port map
(
data => wrdata, -- input data
wraddress => wraddress,
wrclock => OSC_50,
wren => wren and fb_index,
rdaddress => rdaddress,
rdclock => OSC_108_own,
q => PIX_IN_fb2 -- output data
);
PIX_IN <= PIX_IN_fb2 when (fb_index = '0') else PIX_IN_fb1;
-- Generating address for reading the image from the frame buffer
process(OSC_108_own, RESET_N)
variable line_offset : integer range 0 to 176*144 := 0; -- pixel offset due to previous lines
variable pixel_offset : integer range 0 to 176 := 0; -- pixel offset due to previous pixels in the line
begin
if(RESET_N = '0') then
rdaddress <= (others => '0');
else
if (OSC_108_own' event and OSC_108_own = '1') then
if(X < 176*2 and Y < 144*2) then
line_offset := Y/2; -- Doubling the apparent size of the image
line_offset := line_offset * 176;
pixel_offset := X/2; -- Doubling the apparent size of the image
rdaddress <= std_logic_vector(to_unsigned(pixel_offset, 15) + to_unsigned(line_offset, 15));
else
rdaddress <= std_logic_vector(to_unsigned(176*144, 15));
end if;
end if;
end if;
end process;
-- Generating address for writing the image in the frame buffer
process(OSC_50, RESET_N)
variable line_nr : integer range 0 to 144 := 0; -- current line number
variable pixel_nr : integer range 0 to 177 := 0; -- current pixel number in the row
variable line_offset : integer range 0 to 176*144 := 0; -- pixel offset due to previous lines
variable pixel_offset : integer range 0 to 176 := 0; -- pixel offset due to previous pixels in the line
begin
if(RESET_N = '0') then
wraddress <= (others => '0');
wrdata <= (others => '0');
wren <= '0';
line_nr := 0;
line_offset := 0;
pixel_nr := 0;
fb_index <= '0'; -- starting by writing on fb1, reading on fb2
else
if (OSC_50' event and OSC_50 = '1') then
if(fv = '0') then
wraddress <= (others => '0');
wrdata <= (others => '0');
wren <= '0';
line_nr := 0;
line_offset := 0;
pixel_nr := 0;
elsif(dv = '0') then -- the frame is valid
pixel_nr := 0;
else
if(line_nr = 144) then -- end of frame, incrementing line number and flipping frame buffer
wraddress <= (others => '0');
wrdata <= (others => '0');
wren <= '0';
fb_index <= not fb_index; -- flipping the frame buffer
line_nr := line_nr + 1;
line_offset := line_offset + 176;
elsif(line_nr = 145) then -- end of frame
wraddress <= (others => '0');
wrdata <= (others => '0');
wren <= '0';
elsif(pixel_nr = 176) then -- end of line, incrementing line number
wraddress <= (others => '0');
wrdata <= (others => '0');
wren <= '0';
line_nr := line_nr + 1;
line_offset := line_offset + 176;
pixel_nr := pixel_nr + 1;
elsif(pixel_nr = 177) then -- end of line
wraddress <= (others => '0');
wrdata <= (others => '0');
wren <= '0';
else
pixel_offset := pixel_nr;
wraddress <= std_logic_vector(to_unsigned(pixel_offset, 15) + to_unsigned(line_offset, 15));
wrdata <= data;
--wrdata <= (7 => data(7), 6 => data(6), 5 => data(5), 4 => data(4), 3 => data(3), 2 => data(2), 1 => data(1), 0 => data(0), others => '0');
wren <= '1';
pixel_nr := pixel_nr + 1;
end if;
end if;
end if;
end if;
end process;
CLOCK108 <= OSC_108_own;
end hdl;
| gpl-3.0 | 4a6d64092e58c7413db8adc6c34d1879 | 0.548345 | 3.813187 | false | false | false | false |
DreamIP/GPStudio | support/io/mpu/hdl/mpu_pkg.vhd | 1 | 1,866 | --------------------------------------------------------------------
-- Package containing several constant data
--------------------------------------------------------------------
library ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mpu_pkg is
constant ADDR_I2C_MPU : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1101000";
constant ADDR_I2C_COMPASS : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011110";
constant PWR_MGMT_1 : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"6B";
constant USER_CTRL : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"6A";
constant ACCEL_CONFIG_REG : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"1C";
constant SMPLRT_DIV : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"19";
constant FIFO_EN : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"23";
constant GYRO_CONFIG_REG : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"1B";
constant BYPASS_MPU : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"37";
constant COMPASS_CONF_A : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"00";
constant COMPASS_CONF_B : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"01";
constant COMPASS_MODE : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"02";
constant I2C_MST_CTRL : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"24";
constant I2C_SLV0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"25";
constant I2C_SLV0_REG : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"26";
constant I2C_SLV0_CTRL : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"27";
constant FIFO_READ : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"74";
constant COUNT_FIFO_BYTES_T : INTEGER RANGE 0 to 8100 := 8_000;
constant TRIGGER_OR_RST_FIFO_T: INTEGER RANGE 0 to 20100 := 20_000;
constant AD0_value : std_logic := '0';
constant clk_50M : unsigned(27 downto 0) := x"2FAF080";
type param is array (integer range 0 to 3) of std_logic_vector(31 downto 0);
type flow is record
data : std_logic_vector(7 downto 0);
fv : std_logic;
dv : std_logic;
end record;
end mpu_pkg;
| gpl-3.0 | 39f50bde1e7fe6996bb0b6293ee6cd2d | 0.614148 | 2.827273 | false | false | false | false |
DreamIP/GPStudio | support/process/dynroiBinMask/hdl/dynroiBinMask.vhd | 1 | 4,352 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity dynroiBinMask is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end dynroiBinMask;
architecture rtl of dynroiBinMask is
component dynroiBinMask_process
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
status_reg_bypass_bit : in std_logic;
in_size_reg_in_w_reg : in std_logic_vector(11 downto 0);
in_size_reg_in_h_reg : in std_logic_vector(11 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component dynroiBinMask_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
status_reg_bypass_bit : out std_logic;
in_size_reg_in_w_reg : out std_logic_vector(11 downto 0);
in_size_reg_in_h_reg : out std_logic_vector(11 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal status_reg_bypass_bit : std_logic;
signal in_size_reg_in_w_reg : std_logic_vector (11 downto 0);
signal in_size_reg_in_h_reg : std_logic_vector (11 downto 0);
begin
dynroiBinMask_process_inst : dynroiBinMask_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
status_reg_bypass_bit => status_reg_bypass_bit,
in_size_reg_in_w_reg => in_size_reg_in_w_reg,
in_size_reg_in_h_reg => in_size_reg_in_h_reg,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
dynroiBinMask_slave_inst : dynroiBinMask_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
status_reg_bypass_bit => status_reg_bypass_bit,
in_size_reg_in_w_reg => in_size_reg_in_w_reg,
in_size_reg_in_h_reg => in_size_reg_in_h_reg,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
| gpl-3.0 | 143e634bdbd047cf992cbecaf36db660 | 0.487362 | 3.15591 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/RGMII_MAC/eth_crc32.vhd | 1 | 5,890 | -------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : eth_crc32.vhd
-- Author : liyi <[email protected]>
-- Company : OE@HUST
-- Created : 2012-11-04
-- Last update: 2012-11-06
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-11-04 1.0 root Created
-- 经过测试没有问题！计算后输出到外面的crc值需要按照以太网的大小端模式发送才是正确的！
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-------------------------------------------------------------------------------
ENTITY eth_crc32 IS
PORT (
iClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
iInit : IN STD_LOGIC;
iCalcEn : IN STD_LOGIC;
iData : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
oCRC : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
oCRCErr : OUT STD_LOGIC);
END ENTITY eth_crc32;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF eth_crc32 IS
SIGNAL crc, nxtCrc : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN -- ARCHITECTURE rtl
nxtCrc(0) <= crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(1) <= crc(25) XOR crc(31) XOR iData(0) XOR iData(6) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(2) <= crc(26) XOR iData(5) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(3) <= crc(27) XOR iData(4) XOR crc(26) XOR iData(5) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6);
nxtCrc(4) <= crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(5) <= crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(6) <= crc(30) XOR iData(1) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(26) XOR iData(5) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6);
nxtCrc(7) <= crc(31) XOR iData(0) XOR crc(29) XOR iData(2) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5) XOR crc(24) XOR iData(7);
nxtCrc(8) <= crc(0) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(25) XOR iData(6) XOR crc(24) XOR iData(7);
nxtCrc(9) <= crc(1) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(26) XOR iData(5) XOR crc(25) XOR iData(6);
nxtCrc(10) <= crc(2) XOR crc(29) XOR iData(2) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5) XOR crc(24) XOR iData(7);
nxtCrc(11) <= crc(3) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(25) XOR iData(6) XOR crc(24) XOR iData(7);
nxtCrc(12) <= crc(4) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(26) XOR iData(5) XOR crc(25) XOR iData(6) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(13) <= crc(5) XOR crc(30) XOR iData(1) XOR crc(29) XOR iData(2) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6);
nxtCrc(14) <= crc(6) XOR crc(31) XOR iData(0) XOR crc(30) XOR iData(1) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5);
nxtCrc(15) <= crc(7) XOR crc(31) XOR iData(0) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4);
nxtCrc(16) <= crc(8) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(24) XOR iData(7);
nxtCrc(17) <= crc(9) XOR crc(30) XOR iData(1) XOR crc(29) XOR iData(2) XOR crc(25) XOR iData(6);
nxtCrc(18) <= crc(10) XOR crc(31) XOR iData(0) XOR crc(30) XOR iData(1) XOR crc(26) XOR iData(5);
nxtCrc(19) <= crc(11) XOR crc(31) XOR iData(0) XOR crc(27) XOR iData(4);
nxtCrc(20) <= crc(12) XOR crc(28) XOR iData(3);
nxtCrc(21) <= crc(13) XOR crc(29) XOR iData(2);
nxtCrc(22) <= crc(14) XOR crc(24) XOR iData(7);
nxtCrc(23) <= crc(15) XOR crc(25) XOR iData(6) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(24) <= crc(16) XOR crc(26) XOR iData(5) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6);
nxtCrc(25) <= crc(17) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5);
nxtCrc(26) <= crc(18) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(27) <= crc(19) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6);
nxtCrc(28) <= crc(20) XOR crc(30) XOR iData(1) XOR crc(29) XOR iData(2) XOR crc(26) XOR iData(5);
nxtCrc(29) <= crc(21) XOR crc(31) XOR iData(0) XOR crc(30) XOR iData(1) XOR crc(27) XOR iData(4);
nxtCrc(30) <= crc(22) XOR crc(31) XOR iData(0) XOR crc(28) XOR iData(3);
nxtCrc(31) <= crc(23) XOR crc(29) XOR iData(2);
PROCESS (iClk,iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
crc <= (OTHERS => '0');
ELSIF rising_edge(iClk) THEN
IF iInit = '1' THEN
crc <= (OTHERS => '1');
ELSIF iCalcEn = '1' THEN
crc <= nxtCrc;
END IF;
END IF;
END PROCESS;
oCRC(31 DOWNTO 24) <= NOT (crc(24)&crc(25)&crc(26)&crc(27)&crc(28)&crc(29)&crc(30)&crc(31));
oCRC(23 DOWNTO 16) <= NOT (crc(16)&crc(17)&crc(18)&crc(19)&crc(20)&crc(21)&crc(22)&crc(23));
oCRC(15 DOWNTO 8) <= NOT (crc(8)&crc(9)&crc(10)&crc(11)&crc(12)&crc(13)&crc(14)&crc(15));
oCRC(7 DOWNTO 0) <= NOT (crc(0)&crc(1)&crc(2)&crc(3)&crc(4)&crc(5)&crc(6)&crc(7));
oCRCErr <= '1' WHEN crc /= X"c704dd7b" ELSE '0'; -- CRC not equal to magic number
END ARCHITECTURE rtl;
| gpl-3.0 | 4b6a321c3e4a48f4acabd1c51c7f09c2 | 0.557831 | 2.730263 | false | false | false | false |
DreamIP/GPStudio | support/process/debayer33/debayer33_process.vhd | 1 | 13,299 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity debayer33_process is
generic( CLK_PROC_FREQ : integer;
IM_WIDTH : integer := 1280;
IM_HEIGHT : integer := 960;
COLOR_CHANNELS : integer := 3;
DATA_SIZE : integer := 8
);
port(
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- from slave -------------------------
bayer_code_slave : in std_logic_vector(1 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(DATA_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_fv : out std_logic;
out_dv : out std_logic;
out_data : out std_logic_vector((COLOR_CHANNELS*DATA_SIZE)-1 downto 0);
------------------------- for sim -------------------------
sim_en : in std_logic;
bayer_code_sim : in std_logic_vector(1 downto 0);
test_count_x_out : out std_logic_vector(integer(ceil(log2(real(IM_WIDTH))))-1 downto 0);
test_count_y_out : out std_logic_vector(integer(ceil(log2(real(IM_HEIGHT))))-1 downto 0)
);
end entity;
architecture rtl of debayer33_process is
component div_5 is
port
(
denom : in std_logic_vector (2 downto 0);
numer : in std_logic_vector (10 downto 0);
quotient : out std_logic_vector (10 downto 0);
remain : out std_logic_vector (2 downto 0)
);
end component;
----------
signal test_count_x_out_int : unsigned(integer(ceil(log2(real(IM_WIDTH))))-1 downto 0);
signal test_count_y_out_int : unsigned(integer(ceil(log2(real(IM_HEIGHT))))-1 downto 0);
type state_count_line_out_enum is(s0,s1);
signal state_count_line_out : state_count_line_out_enum;
----------
type state_demosaic_enum is(s0,s1,s2);
signal state_demosaic : state_demosaic_enum;
type ramshift_array is array(IM_WIDTH-1 downto 0) of std_logic_vector(DATA_SIZE-1 downto 0);
signal ramshift_0, ramshift_1, ramshift_2 : ramshift_array;
--type ramshift_2_array is array(2 downto 0) of std_logic_vector(DATA_SIZE-1 downto 0);
--signal ramshift_2 : ramshift_2_array;
signal bayer_code_int, code_demosaic_int : std_logic_vector(1 downto 0);
signal line_dv_int, enable_debayer_int : std_logic;
signal pixel_count_int, line_count_int : unsigned(31 downto 0);
signal red_tmp, blue_tmp : unsigned(DATA_SIZE+1 downto 0);
signal green_tmp : unsigned(DATA_SIZE+2 downto 0);
signal enable_debayer_latched_1_int, enable_debayer_latched_2_int, line_dv_tmp : std_logic;
signal path_1_int, path_2_int : std_logic_vector(1 downto 0);
signal denom_int, rem_int, threshold_int : std_logic_vector(2 downto 0);
signal red_tmp_1_latched_int, blue_tmp_1_latched_int : unsigned(DATA_SIZE+1 downto 0);
signal red_tmp_2_latched_int, blue_tmp_2_latched_int : unsigned(DATA_SIZE-1 downto 0);
signal green_tmp_1_latched_int, green_out_tmp : unsigned(DATA_SIZE+2 downto 0);
signal green_tmp_2_latched_int : std_logic_vector(DATA_SIZE+2 downto 0);
begin
bayer_code_int <= bayer_code_slave when sim_en = '0' else bayer_code_sim;
--test count pour x et y du demosaic
test_count_x_out <= std_logic_vector(test_count_x_out_int);
test_count_y_out <= std_logic_vector(test_count_y_out_int);
process(clk_proc, reset_n)
begin
if reset_n = '0' then
test_count_x_out_int <= (others => '0');
test_count_y_out_int <= (others => '0');
state_count_line_out <= s0;
elsif rising_edge(clk_proc) then
if line_dv_tmp = '1' then
test_count_x_out_int <= test_count_x_out_int + 1;
else
test_count_x_out_int <= (others => '0');
end if;
case state_count_line_out is
when s0 =>
if in_fv = '1' then
if line_dv_tmp = '1' then
test_count_y_out_int <= test_count_y_out_int;
state_count_line_out <= s1;
end if;
else
test_count_y_out_int <= (others => '0');
state_count_line_out <= s0;
end if;
when s1 =>
if in_fv = '1' then
if line_dv_tmp = '0' then
test_count_y_out_int <= test_count_y_out_int + 1;
state_count_line_out <= s0;
end if;
else
test_count_y_out_int <= (others => '0');
state_count_line_out <= s0;
end if;
when others => NULL;
end case;
end if;
end process;
--on compte les lignes
process(clk_proc,reset_n)
begin
if reset_n = '0' then
line_count_int <= (others => '0');
state_demosaic <= s0;
elsif rising_edge(clk_proc) then
case state_demosaic is
when s0 =>--attente
if in_fv = '1' then
line_count_int <= line_count_int;
if in_dv = '1' then
state_demosaic <= s1;
else
state_demosaic <= s0;
end if;
else
line_count_int <= (others => '0');
state_demosaic <= s0;
end if;
when s1 =>--attente fin d'image et/ou ligne
if in_fv = '1' then
if in_dv = '0' then --la ligne vient de se terminer
if line_count_int < IM_HEIGHT-1 then--on continue
line_count_int <= line_count_int + 1;
state_demosaic <= s0;
else--image
line_count_int <= line_count_int;
state_demosaic <= s2;
end if;
else
line_count_int <= line_count_int;
state_demosaic <= s1;
end if;
end if;
when s2 => --fin de l'image, on attend que frame valid retombe
if in_fv = '0' then
line_count_int <= (others => '0');
state_demosaic <= s0;
else
line_count_int <= line_count_int;
state_demosaic <= s2;
end if;
when others => NULL;
end case;
end if;
end process;
--pixel pipeline for 3 lines
--evaluate when debayer should be activated
process(clk_proc,reset_n)
begin
if reset_n = '0' then
pixel_count_int <= (others => '0');
enable_debayer_int <= '0';
code_demosaic_int <= (others => '0');
ramshift_0 <= (others => (others => '0'));
ramshift_1 <= (others => (others => '0'));
ramshift_2 <= (others => (others => '0'));
elsif rising_edge(clk_proc) then
if in_fv = '1' then
if in_dv = '1' then
ramshift_0 <= ramshift_1(0) & ramshift_0(IM_WIDTH-1 downto 1);-- a changer si la taille du kernel change
ramshift_1 <= ramshift_2(0) & ramshift_1(IM_WIDTH-1 downto 1);
ramshift_2 <= in_data & ramshift_2(IM_WIDTH-1 downto 1);--ramshift_2(2 downto 1);
end if;
end if;
if in_fv = '1' then
if in_dv = '1' then
pixel_count_int <= pixel_count_int + 1;
else
pixel_count_int <= (others => '0');
end if;
else
pixel_count_int <= (others => '0');
end if;
if line_count_int > 1 and line_count_int <= IM_HEIGHT-1 then
if pixel_count_int > 1 and pixel_count_int <= IM_WIDTH-1 then
enable_debayer_int <= '1';
code_demosaic_int <= line_count_int(0) & pixel_count_int(0);
else
enable_debayer_int <= '0';
code_demosaic_int <= (others => '0');
end if;
else
enable_debayer_int <= '0';
code_demosaic_int <= (others => '0');
end if;
end if;
end process;
--debayering
process(clk_proc, reset_n)
begin
if reset_n = '0' then
enable_debayer_latched_1_int <= '0';
path_1_int <= (others => '0');
red_tmp <= (others => '0');
green_tmp <= (others => '0');
blue_tmp <= (others => '0');
elsif rising_edge(clk_proc) then
if enable_debayer_int = '1' then
enable_debayer_latched_1_int <= '1';
path_1_int <= code_demosaic_int;
if code_demosaic_int = bayer_code_int(1)&bayer_code_int(0) then --"00"
red_tmp <= ("00"&unsigned(ramshift_0(IM_WIDTH-2))) + ("00"&unsigned(ramshift_2(IM_WIDTH-2)));
green_tmp <= ("000"&unsigned(ramshift_0(IM_WIDTH-1))) + ("000"&unsigned(ramshift_0(IM_WIDTH-3))) + ("000"&unsigned(ramshift_1(IM_WIDTH-2))) + ("000"&unsigned(ramshift_2(IM_WIDTH-1))) + ("000"&unsigned(ramshift_2(IM_WIDTH-3)));
blue_tmp <= ("00"&unsigned(ramshift_1(IM_WIDTH-1))) + ("00"&unsigned(ramshift_1(IM_WIDTH-3)));
elsif code_demosaic_int = bayer_code_int(1)¬(bayer_code_int(0)) then --"01"
red_tmp <= ("00"&unsigned(ramshift_0(IM_WIDTH-1))) + ("00"&unsigned(ramshift_0(IM_WIDTH-3))) + ("00"&unsigned(ramshift_2(IM_WIDTH-1))) + ("00"&unsigned(ramshift_2(IM_WIDTH-3)));
green_tmp <= ("000"&unsigned(ramshift_0(IM_WIDTH-2))) + ("000"&unsigned(ramshift_1(IM_WIDTH-1))) + ("000"&unsigned(ramshift_1(IM_WIDTH-3))) + ("000"&unsigned(ramshift_2(IM_WIDTH-2)));
blue_tmp <= ("00"&unsigned(ramshift_1(IM_WIDTH-2)));
elsif code_demosaic_int = not(bayer_code_int(1))& bayer_code_int(0) then --"01" then
red_tmp <= ("00"&unsigned(ramshift_1(IM_WIDTH-2)));
green_tmp <= ("000"&unsigned(ramshift_0(IM_WIDTH-2))) + ("000"&unsigned(ramshift_1(IM_WIDTH-1))) + ("000"&unsigned(ramshift_1(IM_WIDTH-3))) + ("000"&unsigned(ramshift_2(IM_WIDTH-2)));
blue_tmp <= ("00"&unsigned(ramshift_0(IM_WIDTH-2))) + ("00"&unsigned(ramshift_1(IM_WIDTH-1))) + ("00"&unsigned(ramshift_1(IM_WIDTH-3))) + ("00"&unsigned(ramshift_2(IM_WIDTH-2)));
else
red_tmp <= ("00"&unsigned(ramshift_1(IM_WIDTH-1))) + ("00"&unsigned(ramshift_1(IM_WIDTH-3)));
green_tmp <= ("000"&unsigned(ramshift_0(IM_WIDTH-1))) + ("000"&unsigned(ramshift_0(IM_WIDTH-3))) + ("000"&unsigned(ramshift_1(IM_WIDTH-2))) + ("000"&unsigned(ramshift_2(IM_WIDTH-1))) + ("000"&unsigned(ramshift_2(IM_WIDTH-3)));
blue_tmp <= ("00"&unsigned(ramshift_0(IM_WIDTH-2))) + ("00"&unsigned(ramshift_2(IM_WIDTH-2)));
end if;
else
enable_debayer_latched_1_int <= '0';
path_1_int <= (others => '0');
red_tmp <= (others => '0');
green_tmp <= (others => '0');
blue_tmp <= (others => '0');
end if;
end if;
end process;
--process feed divider
process(clk_proc, reset_n)
begin
if reset_n = '0' then
enable_debayer_latched_2_int <= '0';
path_2_int <= (others => '0');
red_tmp_1_latched_int <= (others => '0');
green_tmp_1_latched_int <= (others => '0');
denom_int <= "001";
blue_tmp_1_latched_int <= (others => '0');
elsif rising_edge(clk_proc) then
if enable_debayer_latched_1_int = '1' then
enable_debayer_latched_2_int <= '1';
path_2_int <= path_1_int;
red_tmp_1_latched_int <= red_tmp;
green_tmp_1_latched_int <= green_tmp;
blue_tmp_1_latched_int <= blue_tmp;
if path_1_int = "00" or path_1_int = "11" then
denom_int <= "101";
else
denom_int <= "100";
end if;
else
enable_debayer_latched_2_int <= '0';
path_2_int <= (others => '0');
red_tmp_1_latched_int <= (others => '0');
green_tmp_1_latched_int <= (others => '0');
denom_int <= (others => '0');
blue_tmp_1_latched_int <= (others => '0');
end if;
end if;
end process;
-- compute pixels
div_5_inst : div_5 PORT MAP (
denom => denom_int,-- a changer si la taille du kernel change
numer => std_logic_vector(green_tmp_1_latched_int),
quotient => green_tmp_2_latched_int,
remain => rem_int
);
threshold_int <= "011";
--cut process
process(clk_proc, reset_n)
begin
if reset_n = '0' then
red_tmp_2_latched_int <= (others => '0');
green_out_tmp <= (others => '0');
blue_tmp_2_latched_int <= (others => '0');
line_dv_tmp <= '0';
elsif rising_edge(clk_proc) then
if enable_debayer_latched_2_int = '1' then
line_dv_tmp <= '1';
if path_2_int = "00" then
red_tmp_2_latched_int <= red_tmp_1_latched_int(DATA_SIZE downto 1);
blue_tmp_2_latched_int <= blue_tmp_1_latched_int(DATA_SIZE downto 1);
if rem_int > threshold_int then
green_out_tmp <= unsigned(green_tmp_2_latched_int) + "00000000001";
else
green_out_tmp <= unsigned(green_tmp_2_latched_int);
end if;
elsif path_2_int = "01" then
red_tmp_2_latched_int <= red_tmp_1_latched_int(DATA_SIZE+1 downto 2);
blue_tmp_2_latched_int <= blue_tmp_1_latched_int(DATA_SIZE downto 1);
green_out_tmp <= unsigned(green_tmp_2_latched_int);
elsif path_2_int = "10" then
red_tmp_2_latched_int <= red_tmp_1_latched_int(DATA_SIZE-1 downto 0);
blue_tmp_2_latched_int <= blue_tmp_1_latched_int(DATA_SIZE+1 downto 2);
green_out_tmp <= unsigned(green_tmp_2_latched_int);
else--"11"
red_tmp_2_latched_int <= red_tmp_1_latched_int(DATA_SIZE downto 1);
blue_tmp_2_latched_int <= blue_tmp_1_latched_int(DATA_SIZE downto 1);
if rem_int > threshold_int then
green_out_tmp <= unsigned(green_tmp_2_latched_int) + "00000000001";
else
green_out_tmp <= unsigned(green_tmp_2_latched_int);
end if;
end if;
else
red_tmp_2_latched_int <= (others => '0');
green_out_tmp <= (others => '0');
blue_tmp_2_latched_int <= (others => '0');
line_dv_tmp <= '0';
end if;
end if;
end process;
--final process
process(clk_proc, reset_n)
begin
if reset_n = '0' then
out_dv <= '0';
out_data <= (others => '0');
elsif rising_edge(clk_proc) then
if line_dv_tmp = '1' then
out_dv <= '1';
out_data((COLOR_CHANNELS*DATA_SIZE)-1 downto ((COLOR_CHANNELS-1)*DATA_SIZE)) <= std_logic_vector(red_tmp_2_latched_int);
out_data(((COLOR_CHANNELS-1)*DATA_SIZE)-1 downto ((COLOR_CHANNELS-2)*DATA_SIZE)) <= std_logic_vector(green_out_tmp(DATA_SIZE-1 downto 0));
out_data(((COLOR_CHANNELS-2)*DATA_SIZE)-1 downto ((COLOR_CHANNELS-3)*DATA_SIZE)) <= std_logic_vector(blue_tmp_2_latched_int);
-- red_plane <= std_logic_vector(red_tmp_2_latched_int);
-- green_plane <= std_logic_vector(green_out_tmp(DATA_SIZE-1 downto 0));
-- blue_plane <= std_logic_vector(blue_tmp_2_latched_int);
else
out_dv <= '0';
out_data <= (others => '0');
-- red_plane <= (others => '0');
-- green_plane <= (others => '0');
-- blue_plane <= (others => '0');
end if;
end if;
end process;
out_fv <= in_fv;
end architecture;
| gpl-3.0 | 63740216287a4c9cc95a70f78d9f695f | 0.618392 | 2.536041 | false | false | false | false |
DreamIP/GPStudio | support/process/dynthreshold/hdl/dynthreshold.vhd | 1 | 4,251 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity dynthreshold is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end dynthreshold;
architecture rtl of dynthreshold is
component dynthreshold_process
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
desired_ratio_reg : in std_logic_vector(31 downto 0);
border_research_type_reg : in std_logic_vector(31 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component dynthreshold_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
desired_ratio_reg : out std_logic_vector(31 downto 0);
border_research_type_reg : out std_logic_vector(31 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal desired_ratio_reg : std_logic_vector (31 downto 0);
signal border_research_type_reg : std_logic_vector (31 downto 0);
begin
dynthreshold_process_inst : dynthreshold_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
desired_ratio_reg => desired_ratio_reg,
border_research_type_reg => border_research_type_reg,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
dynthreshold_slave_inst : dynthreshold_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
desired_ratio_reg => desired_ratio_reg,
border_research_type_reg => border_research_type_reg,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
| gpl-3.0 | ee75e0bcd933a850e9a1502832a707db | 0.468831 | 3.493016 | false | false | false | false |
DreamIP/GPStudio | support/process/threshold/hdl/threshold.vhd | 1 | 3,276 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity threshold is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end threshold;
architecture rtl of threshold is
component threshold_process
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
threshold_reg : in std_logic_vector(31 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component threshold_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
threshold_reg : out std_logic_vector(31 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal threshold_reg : std_logic_vector (31 downto 0);
begin
threshold_process_inst : threshold_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
threshold_reg => threshold_reg,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
threshold_slave_inst : threshold_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
threshold_reg => threshold_reg,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
| gpl-3.0 | 34640d9b997561ddc1ed035b153c0bc2 | 0.475275 | 3.285858 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | testbench/FIFO/fifo_top.vhdl | 1 | 2,782 | library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.MEMs.all;
entity FIFO_top is
port (
async_i : in std_logic; -- Test the ASYNC version
-- write side
wclk_i : in std_logic; -- Write Clock
wrst_i : in std_logic; -- Write Reset
wen_i : in std_logic; -- Write Enable
data_i : in std_logic_vector(7 downto 0); -- Data Input
full_o : out std_logic; -- Full Flag
afull_o : out std_logic; -- Almost Full Flag
overflow_o : out std_logic; -- Overflow Flag
-- read side
rclk_i : in std_logic; -- Read Clock
rrst_i : in std_logic; -- Read Reset
ren_i : in std_logic; -- Read enable
data_o : out std_logic_vector(7 downto 0); -- Data Output
empty_o : out std_logic; -- Empty flag
aempty_o : out std_logic; -- Almost Empty flag
underflow_o : out std_logic; -- Underflow Flag
valid_o : out std_logic -- Read Valid
);
end entity FIFO_top;
architecture Structural of FIFO_top is
signal full_s, afull_s, over_s : std_logic;
signal empty_s, aempty_s, under_s, valid_s : std_logic;
signal data_s, data_a : std_logic_vector(7 downto 0);
signal full_a, afull_a, over_a : std_logic;
signal empty_a, aempty_a, under_a, valid_a : std_logic;
begin
full_o <= full_a when async_i='1' else full_s;
afull_o <= afull_a when async_i='1' else afull_s;
overflow_o <= over_a when async_i='1' else over_s;
data_o <= data_a when async_i='1' else data_s;
empty_o <= empty_a when async_i='1' else empty_s;
aempty_o <= aempty_a when async_i='1' else aempty_s;
underflow_o <= under_a when async_i='1' else under_s;
valid_o <= valid_a when async_i='1' else valid_s;
fifo_sync_inst: fifo
generic map (DEPTH => 4, ASYNC => FALSE)
port map (
-- write side
wclk_i => wclk_i, wrst_i => wrst_i, wen_i => wen_i, data_i => data_i,
full_o => full_s, afull_o => afull_s, overflow_o => over_s,
-- read side
rclk_i => wclk_i, rrst_i => wrst_i, ren_i => ren_i, data_o => data_s,
empty_o => empty_s, aempty_o => aempty_s, underflow_o => under_s, valid_o => valid_s
);
fifo_async_inst: fifo
generic map (DEPTH => 4, ASYNC => TRUE)
port map (
-- write side
wclk_i => wclk_i, wrst_i => wrst_i, wen_i => wen_i, data_i => data_i,
full_o => full_a, afull_o => afull_a, overflow_o => over_a,
-- read side
rclk_i => rclk_i, rrst_i => rrst_i, ren_i => ren_i, data_o => data_a,
empty_o => empty_a, aempty_o => aempty_a, underflow_o => under_a, valid_o => valid_a
);
end architecture Structural;
| bsd-3-clause | 02505b7c3cc8c7aa586e2875f6b8fc40 | 0.557513 | 3.014085 | false | false | false | false |
DreamIP/GPStudio | support/io/gps/hdl/gps_transmitter.vhd | 1 | 3,432 | -----------------------------------------------------------------------
-- UART transmitter block. It sends the data to the GPS at the baud rate
-- defined. The data are sent following the Skytraq binary protocol.
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gps_pkg.all;
entity gps_transmitter is
port(
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
start_flag : in std_logic;
done : out std_logic;
done_send : out std_logic;
count_bd : in unsigned(15 downto 0);
count_max : in unsigned(15 downto 0);
rst_count_bd : out std_logic;
TXD : out std_logic;
bytes : in unsigned(7 downto 0);
data_in : in std_logic_vector(7 downto 0)
);
end GPS_transmitter;
architecture RTL of gps_transmitter is
signal number_of_bits : unsigned(3 downto 0);
signal data_out_s : std_logic_vector(7 downto 0);
signal gngga : std_logic_vector(55 downto 0);
signal g_flag : std_logic;
signal data_to_send : std_logic_vector(7 downto 0);
signal count_bytes : unsigned(7 downto 0);
signal count_wait : unsigned(15 downto 0);
signal TXD_r : std_logic;
type type_state is (idle, start, data, wait_st, stop);
signal state : type_state;
begin
process(clk,reset,enable)
begin
if reset='0' then
rst_count_bd <='0';
number_of_bits <= x"0";
TXD_r <= '1';
state <= idle;
elsif clk'event and clk='1'then
if enable='1' then
case(state) is
----- Starting a communication
when(idle) =>
done <= '0';
done_send <= '0';
TXD_r <= '1';
if start_flag='1' then
state <= start;
data_to_send <= data_in;
rst_count_bd <= '1';
end if;
----- Writing start bit
when(start) =>
rst_count_bd <= '0';
data_to_send <= data_in;
done <= '0';
TXD_r <= '0';
if count_bd=count_max then
state <= data;
number_of_bits <= x"0";
end if;
----- Writing the 8 bits of data (LSB first)
when(data) =>
TXD_r <= data_to_send(0);
if count_bd=count_max then
data_to_send <= '0' & data_to_send(7 downto 1);
if number_of_bits= x"7" then
state <= stop;
else
number_of_bits <= number_of_bits +1;
end if;
end if;
----- Write stop bit
when(stop) =>
TXD_r <= '1';
if count_bd=count_max then
done <= '1';
number_of_bits <= x"0";
count_bytes <= count_bytes +1;
if count_bytes=bytes-1 then
if count_max=COUNT_BD_RATE_MAX then
count_wait <= x"0000";
else
count_wait <= x"7000";
end if;
state <= wait_st;
else
state <= start;
end if;
end if;
----- Full sequence sended, waiting before sending a new one
when wait_st =>
TXD_r <= '1';
if count_bd=count_max then
count_wait <= count_wait +1;
elsif count_wait=x"FFFF" then
state <= idle;
count_bytes <= x"00";
done_send <= '1';
end if;
when others =>
TXD_r <= '1';
state <= idle;
end case;
else
rst_count_bd <='0';
number_of_bits <= x"0";
TXD_r <= '1';
state <= idle;
end if;
end if;
end process;
TXD <= TXD_r;
end RTL;
| gpl-3.0 | 81c5048954269d9c34ba1e2300e13d6c | 0.519814 | 2.930828 | false | false | false | false |
DreamIP/GPStudio | support/io/com/hdl/hal/eth_marvell_88e1111/hdl/eth_mdio.vhd | 1 | 5,715 | -- This code is used to configure the Marvell 88e1111 and handle the MDIO pins (PHY_RESET, PHY_MDC and PHY_MDIO).
-- It can write and read the internals registers of the marvell.
-- Right now, the configuration used is the configuration by default and this entity only outputs an hardware reset when power up.
-- You can add a configuration only by uncommenting the request signal (just set your address register and the data you want to write).
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity eth_mdio is
Port(
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
E_RST_L : out STD_LOGIC;
E_MDC : out STD_LOGIC;
E_MDIO : inout STD_LOGIC);
end eth_mdio;
architecture Behavioral of eth_mdio is
signal count : unsigned(27 downto 0) ;
signal request : unsigned(0 to 31);--write
signal request_r : unsigned(0 to 13);--read
signal stop_count_s : std_logic:='0';
type state_mdio is (idle, set_conf, reset_st,read_st,wait_st,config);
signal state : state_mdio;
signal count_conf : unsigned(3 downto 0):=x"0";
signal reset_done : std_logic:='0';
signal tempo : std_logic:='1';
begin
process(CLK,RESET)
begin
if RESET = '0' then
E_RST_L <= '0';--hold reset condition for 1 second
E_MDC <= '1';
E_MDIO <= 'Z';
stop_count_s <= '0';
count <= x"0000000";
elsif CLK'event and CLK = '1' then
if (count(11) = '1' or count(4) = '1') then
E_MDC <= '1';
else--maximum frequency of E_MDC is 8.3 MHz
E_MDC <= '0';--3.9 MHz
end if;
case state is
when idle =>
if count = x"F000000" and stop_count_s='0' then
state <= wait_st;
count <= x"0000000";
elsif count > x"0140000" and count < x"0280000" and stop_count_s='0' then
E_RST_L <= '0';
count <= count +1;
elsif count = x"F000000" and stop_count_s='1' then
state <= read_st;
count <= x"8000000";
else
E_RST_L <= '1';
count <= count +1;
end if;
when wait_st =>
if count = x"FFFFFFF" then
count <= x"8000000";
if reset_done='0' then
state <= set_conf;
elsif reset_done='1' and tempo='1' then
state <= wait_st;
tempo <= '0';
else
state <= config;
end if;
else
count <= count +1;
end if;
when set_conf =>
--request <= "0101" & "10010" & "10100" & "100000110011100000"; -- set delay for RX and TX in rgmii mode
if count=x"8000FFF" then
state <= reset_st;
count <= x"8000000";
else
count <= count +1;
end if;
when reset_st =>
--request <= "0101" & "10010" & "00000" & "101001000101000000"; -- reset PHY
if count=x"8000FFF" then
--stop_count_s <= '1';
count <= x"0000000";
state <= wait_st;
reset_done<='1' ;
else
count <= count +1;
end if;
when config =>
if count_conf=x"0" then
--request <= "0101" & "10010" & "10100" & "100000110011100001"; -- set reg 20 for rgmii
--request <= "0101" & "10010" & "00000" & "100101000101000000"; -- stop loopback = 100101000101000000 --reg 0
else
--request <= "0101" & "10010" & "11110" & "101000100100100000"; -- packet generator activated
end if;
if count=x"8000FFF" then
if count_conf=x"0" then
state <= config;
count <= x"8000000";
count_conf <= count_conf +1;
else
stop_count_s <= '1';
state <= idle;
end if;
else
count <= count +1;
end if;
when read_st =>
request_r <= "0110" & "10010" & "10100";
if count=x"8000FFF" then
state <= idle;
count <= x"8000000";
else
count <= count +1;
end if;
when others =>
state <= idle;
end case;
end if;
end process;
E_MDIO <= '1' when count(11 downto 5) < "0100000" and (state=set_conf or state=reset_st or state=read_st or state=config) --32 1's preamble
else request(to_integer(count(9 downto 5))) when (state=set_conf or state=reset_st or state=config) and count(11 downto 5) <= "0111111" --write data
else request_r(to_integer(count(9 downto 5))) when state=read_st and count(11 downto 5) <= "0101101" -- read data
else 'Z';
end Behavioral;
| gpl-3.0 | a765f13c2bc93650beabd43b9e65f7c3 | 0.433071 | 4.399538 | false | true | false | false |
hoglet67/ElectronFpga | src/altera/pll1.vhd | 1 | 18,368 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll1.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll1 IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll1;
ARCHITECTURE SYN OF pll1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
gate_lock_signal : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
invalid_lock_multiplier : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
valid_lock_multiplier : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 3,
clk0_duty_cycle => 50,
clk0_multiply_by => 2,
clk0_phase_shift => "0",
clk1_divide_by => 3,
clk1_duty_cycle => 50,
clk1_multiply_by => 4,
clk1_phase_shift => "0",
clk2_divide_by => 3,
clk2_duty_cycle => 50,
clk2_multiply_by => 5,
clk2_phase_shift => "0",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 41666,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_hint => "CBX_MODULE_PREFIX=pll1",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
areset => areset,
inclk => sub_wire6,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "16.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "32.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "40.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "16.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "32.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "40.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll32.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-3.0 | 9f5f051d132da480a2ce548842d29f1b | 0.699695 | 3.28528 | false | false | false | false |
DreamIP/GPStudio | support/io/com/hdl/hal/eth_marvell_88e1111/com_ethernet_example.vhd | 1 | 8,083 | -- This code is an example of the connection between com block and ethernet_udp block.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.com_package.all;
use work.ethernet_package.all;
entity com_ethernet is
generic (
MASTER_ADDR_WIDTH : integer := 2;
MASTER_PORT : std_logic_vector(15 downto 0) := x"8000";
FIFO_IN_N : integer := 4;--up to 16 fifos
FIFO_IN_ID : fifo_ID := ("000001","000010","000011",x"000100",others=>"000000");
FIFO_IN_SIZE : fifo_size := (2048,1024,2048,512,others=>0);
ONE_PACKET_SIZE : integer := 1450;
FIFO_OUT_N : integer := 3;--up to 16 fifos
FIFO_OUT_ID : fifo_ID := ("110000","100001","100010",others=>x"100000");
FIFO_OUT_SIZE : fifo_size := (512,512,others=>0)
);
port(
CLK125 : in STD_LOGIC;
clk_proc : in std_logic;
reset_n : in std_logic;
--- ETHERNET
PHY_RESET_L : out STD_LOGIC;
PHY_MDC : out STD_LOGIC;
PHY_MDIO : inout STD_LOGIC;
TX_data : out std_logic_vector(3 downto 0);
TX_dv : out std_logic;
RX_data : in std_logic_vector(3 downto 0);
RX_dv : in std_logic;
GE_TXCLK : out std_logic;
--- Clocks from PLL
clk250_marvell : in std_logic;
clk250_fpga : in std_logic;
------------à generer
flow_in0_data : in std_logic_vector(7 downto 0);
flow_in0_dv : in std_logic;
flow_in0_fv : in std_logic;
flow_in1_data : in std_logic_vector(7 downto 0);
flow_in1_dv : in std_logic;
flow_in1_fv : in std_logic;
flow_in2_data : in std_logic_vector(7 downto 0);
flow_in2_dv : in std_logic;
flow_in2_fv : in std_logic;
flow_in3_data : in std_logic_vector(7 downto 0);
flow_in3_dv : in std_logic;
flow_in3_fv : in std_logic;
flow_out0_data : out std_logic_vector(7 downto 0);
flow_out0_dv : out std_logic;
flow_out0_fv : out std_logic;
flow_out1_data : out std_logic_vector(7 downto 0);
flow_out1_dv : out std_logic;
flow_out1_fv : out std_logic;
--- PI_master
master_addr_o : out std_logic_vector(MASTER_ADDR_WIDTH downto 0);
master_wr_o : out std_logic;
master_rd_o : out std_logic;
master_datawr_o : out std_logic_vector(31 downto 0);
master_datard_i : in std_logic_vector(31 downto 0);
--- PI_slave
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end com_ethernet;
architecture RTL of com_ethernet is
signal TX_s : rgmii_t;
signal param : param_t;
signal flow_tx_out : flow_t;
signal flow_master : flow_t;
signal ID_port_in : std_logic_vector(15 downto 0);
signal ID_port_out : std_logic_vector(15 downto 0);
signal size_flow : std_logic_vector(15 downto 0);
signal TX : rgmii_t;
signal RX : rgmii_t;
signal enable_eth : std_logic;
signal enable_in0 : std_logic;
signal enable_in1 : std_logic;
signal enable_in2 : std_logic;
signal enable_in3 : std_logic;
signal mac_addr_hal_msb : std_logic_vector(23 downto 0);
signal mac_addr_hal_lsb : std_logic_vector(23 downto 0);
signal mac_addr_dest_msb: std_logic_vector(23 downto 0);
signal mac_addr_dest_lsb: std_logic_vector(23 downto 0);
signal ip_hal : std_logic_vector(31 downto 0);
signal ip_dest : std_logic_vector(31 downto 0);
signal port_dest : std_logic_vector(15 downto 0);
signal data_to_hal : std_logic_vector(7 downto 0);
signal data_to_com : std_logic_vector(7 downto 0);
signal size : std_logic_vector(15 downto 0);
signal read_data,ready : std_logic;
signal hal_ready : std_logic;
signal write_i : std_logic;
signal test : flow_t;
begin
TX_data <= TX.data;
TX_dv <= TX.dv;
RX.data <= RX_data;
RX.dv <= RX_dv;
com_inst : entity work.com
generic map(
fifo_in_N => FIFO_IN_N,
fifo_in_ID => FIFO_IN_ID,
fifo_in_size => FIFO_IN_SIZE,
one_packet => ONE_PACKET_SIZE,
fifo_out_N => FIFO_OUT_N,
fifo_out_ID => FIFO_OUT_ID,
fifo_out_size => FIFO_OUT_SIZE
)
port map (
clk_hal => clk125,
clk_proc => clk_proc,
reset_n => reset_n,
--- From flows in to HAL
hal_ready => hal_ready,
data_o => data_to_hal,
data_size_o => size,
read_data_i => read_data,
ready_o => ready,
--- From HAL to flows out
data_i => data_to_com,
write_i => write_i,
--- flow to master
flow_master => flow_master,
------------à generer
flow_in0.data => flow_in0_data,
flow_in0.dv => flow_in0_dv,
flow_in0.fv => flow_in0_fv,
flow_in1.data => flow_in1_data,
flow_in1.dv => flow_in1_dv,
flow_in1.fv => flow_in1_fv,
flow_in2.data => flow_in2_data,
flow_in2.dv => flow_in2_dv,
flow_in2.fv => flow_in2_fv,
flow_in3.data => flow_in3_data,
flow_in3.dv => flow_in3_dv,
flow_in3.fv => flow_in3_fv,
flow_out0.data => flow_out0_data,
flow_out0.dv => flow_out0_dv,
flow_out0.fv => flow_out0_fv,
flow_out1.data => flow_out1_data,
flow_out1.dv => flow_out1_dv,
flow_out1.fv => flow_out1_fv,
--- parameters from slave
------------à generer
enable_eth => enable_eth,
enable_in0 => enable_in0,
enable_in1 => enable_in1,
enable_in2 => enable_in2,
enable_in3 => enable_in3
);
ethernet_inst : entity work.ethernet_udp
port map (
--- External ports
CLK125 => clk125,
reset_n => reset_n,
PHY_RESET_L => PHY_RESET_L,
PHY_MDC => PHY_MDC,
PHY_MDIO => PHY_MDIO,
TX => TX_s,
RX => RX,
GE_TXCLK => GE_TXCLK,
--- Clocks from Clocks Interconnect
clk250_marvell => clk250_marvell,
clk250_fpga => clk250_fpga,
--- Parameters from slave
mac_addr_hal_msb => mac_addr_hal_msb,
mac_addr_hal_lsb => mac_addr_hal_lsb,
mac_addr_dest_msb => mac_addr_dest_msb,
mac_addr_dest_lsb => mac_addr_dest_lsb,
ip_hal => ip_hal,
ip_dest => ip_dest,
port_dest => port_dest,
--- Receiving data to send on link
hal_ready => hal_ready,
data_i => data_to_hal,
data_size_i => size,
read_data_o => read_data,
ready_i => ready,
--- Transmitting flows received by link
data_o => data_to_com,
write_o => write_i
--ID_port_out => ID_port_out
);
TX <= TX_s;
master : entity work.com_master
generic map (pi_size_addr => MASTER_ADDR_WIDTH)
Port map(
CLK => clk_proc,
RESET_n => reset_n,
flow_in => flow_master,
master_addr_o => master_addr_o,
master_wr_o => master_wr_o,
master_rd_o => master_rd_o,
master_datawr_o => master_datawr_o,
master_datard_i => master_datard_i
);
slave : entity work.eth_slave
generic map (pi_size_addr => 3)
Port map(
CLK => clk_proc,
RESET_n => reset_n,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o,
--- parameters com
enable_eth_o => enable_eth,
enable_in0_o => enable_in0,
enable_in1_o => enable_in1,
enable_in2_o => enable_in2,
enable_in3_o => enable_in3,
--- parameters ethernet
mac_addr_hal_msb => mac_addr_hal_msb,
mac_addr_hal_lsb => mac_addr_hal_lsb,
mac_addr_dest_msb => mac_addr_dest_msb,
mac_addr_dest_lsb => mac_addr_dest_lsb,
ip_hal => ip_hal,
ip_dest => ip_dest,
port_dest => port_dest
);
end RTL;
| gpl-3.0 | c172614ccac2c898bb2ad14d2c59411b | 0.551856 | 2.692436 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_sdram_0.vhd | 1 | 35,443 | --Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tracking_camera_system_sdram_0_input_efifo_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal rd : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal wr : IN STD_LOGIC;
signal wr_data : IN STD_LOGIC_VECTOR (40 DOWNTO 0);
-- outputs:
signal almost_empty : OUT STD_LOGIC;
signal almost_full : OUT STD_LOGIC;
signal empty : OUT STD_LOGIC;
signal full : OUT STD_LOGIC;
signal rd_data : OUT STD_LOGIC_VECTOR (40 DOWNTO 0)
);
end entity tracking_camera_system_sdram_0_input_efifo_module;
architecture europa of tracking_camera_system_sdram_0_input_efifo_module is
signal entries : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal entry_0 : STD_LOGIC_VECTOR (40 DOWNTO 0);
signal entry_1 : STD_LOGIC_VECTOR (40 DOWNTO 0);
signal internal_empty : STD_LOGIC;
signal internal_full : STD_LOGIC;
signal rd_address : STD_LOGIC;
signal rdwr : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal wr_address : STD_LOGIC;
begin
rdwr <= Std_Logic_Vector'(A_ToStdLogicVector(rd) & A_ToStdLogicVector(wr));
internal_full <= to_std_logic(((std_logic_vector'("000000000000000000000000000000") & (entries)) = std_logic_vector'("00000000000000000000000000000010")));
almost_full <= to_std_logic(((std_logic_vector'("000000000000000000000000000000") & (entries))>=std_logic_vector'("00000000000000000000000000000001")));
internal_empty <= to_std_logic(((std_logic_vector'("000000000000000000000000000000") & (entries)) = std_logic_vector'("00000000000000000000000000000000")));
almost_empty <= to_std_logic(((std_logic_vector'("000000000000000000000000000000") & (entries))<=std_logic_vector'("00000000000000000000000000000001")));
process (entry_0, entry_1, rd_address)
begin
case rd_address is -- synthesis parallel_case full_case
when std_logic'('0') =>
rd_data <= entry_0;
-- when std_logic'('0')
when std_logic'('1') =>
rd_data <= entry_1;
-- when std_logic'('1')
when others =>
-- when others
end case; -- rd_address
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
wr_address <= std_logic'('0');
rd_address <= std_logic'('0');
entries <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
case rdwr is -- synthesis parallel_case full_case
when std_logic_vector'("01") =>
-- Write data
if std_logic'(NOT(internal_full)) = '1' then
entries <= A_EXT (((std_logic_vector'("0000000000000000000000000000000") & (entries)) + std_logic_vector'("000000000000000000000000000000001")), 2);
wr_address <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(wr_address))) = std_logic_vector'("00000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(wr_address))) + std_logic_vector'("000000000000000000000000000000001")))));
end if;
-- when std_logic_vector'("01")
when std_logic_vector'("10") =>
-- Read data
if std_logic'(NOT(internal_empty)) = '1' then
entries <= A_EXT (((std_logic_vector'("0000000000000000000000000000000") & (entries)) - std_logic_vector'("000000000000000000000000000000001")), 2);
rd_address <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(rd_address))) = std_logic_vector'("00000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(rd_address))) + std_logic_vector'("000000000000000000000000000000001")))));
end if;
-- when std_logic_vector'("10")
when std_logic_vector'("11") =>
wr_address <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(wr_address))) = std_logic_vector'("00000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(wr_address))) + std_logic_vector'("000000000000000000000000000000001")))));
rd_address <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(rd_address))) = std_logic_vector'("00000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(rd_address))) + std_logic_vector'("000000000000000000000000000000001")))));
-- when std_logic_vector'("11")
when others =>
-- when others
end case; -- rdwr
end if;
end process;
process (clk)
begin
if clk'event and clk = '1' then
--Write data
if std_logic'((wr AND NOT(internal_full))) = '1' then
case wr_address is -- synthesis parallel_case full_case
when std_logic'('0') =>
entry_0 <= wr_data;
-- when std_logic'('0')
when std_logic'('1') =>
entry_1 <= wr_data;
-- when std_logic'('1')
when others =>
-- when others
end case; -- wr_address
end if;
end if;
end process;
--vhdl renameroo for output signals
empty <= internal_empty;
--vhdl renameroo for output signals
full <= internal_full;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity tracking_camera_system_sdram_0 is
port (
-- inputs:
signal az_addr : IN STD_LOGIC_VECTOR (21 DOWNTO 0);
signal az_be_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal az_cs : IN STD_LOGIC;
signal az_data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal az_rd_n : IN STD_LOGIC;
signal az_wr_n : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal za_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal za_valid : OUT STD_LOGIC;
signal za_waitrequest : OUT STD_LOGIC;
signal zs_addr : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal zs_ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal zs_cas_n : OUT STD_LOGIC;
signal zs_cke : OUT STD_LOGIC;
signal zs_cs_n : OUT STD_LOGIC;
signal zs_dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal zs_dqm : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal zs_ras_n : OUT STD_LOGIC;
signal zs_we_n : OUT STD_LOGIC
);
end entity tracking_camera_system_sdram_0;
architecture europa of tracking_camera_system_sdram_0 is
component tracking_camera_system_sdram_0_input_efifo_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal rd : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal wr : IN STD_LOGIC;
signal wr_data : IN STD_LOGIC_VECTOR (40 DOWNTO 0);
-- outputs:
signal almost_empty : OUT STD_LOGIC;
signal almost_full : OUT STD_LOGIC;
signal empty : OUT STD_LOGIC;
signal full : OUT STD_LOGIC;
signal rd_data : OUT STD_LOGIC_VECTOR (40 DOWNTO 0)
);
end component tracking_camera_system_sdram_0_input_efifo_module;
signal CODE : STD_LOGIC_VECTOR (23 DOWNTO 0);
signal ack_refresh_request : STD_LOGIC;
signal active_addr : STD_LOGIC_VECTOR (21 DOWNTO 0);
signal active_bank : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal active_cs_n : STD_LOGIC;
signal active_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal active_dqm : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal active_rnw : STD_LOGIC;
signal almost_empty : STD_LOGIC;
signal almost_full : STD_LOGIC;
signal bank_match : STD_LOGIC;
signal cas_addr : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal clk_en : STD_LOGIC;
signal cmd_all : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal cmd_code : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal cs_n : STD_LOGIC;
signal csn_decode : STD_LOGIC;
signal csn_match : STD_LOGIC;
signal f_addr : STD_LOGIC_VECTOR (21 DOWNTO 0);
signal f_bank : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal f_cs_n : STD_LOGIC;
signal f_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal f_dqm : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal f_empty : STD_LOGIC;
signal f_pop : STD_LOGIC;
signal f_rnw : STD_LOGIC;
signal f_select : STD_LOGIC;
signal fifo_read_data : STD_LOGIC_VECTOR (40 DOWNTO 0);
signal i_addr : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal i_cmd : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal i_count : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal i_next : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal i_refs : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal i_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal init_done : STD_LOGIC;
signal internal_za_waitrequest : STD_LOGIC;
signal m_addr : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal m_bank : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal m_cmd : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal m_count : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal m_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal m_dqm : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal m_next : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal m_state : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal module_input : STD_LOGIC;
signal module_input1 : STD_LOGIC_VECTOR (40 DOWNTO 0);
signal oe : STD_LOGIC;
signal pending : STD_LOGIC;
signal rd_strobe : STD_LOGIC;
signal rd_valid : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal refresh_counter : STD_LOGIC_VECTOR (13 DOWNTO 0);
signal refresh_request : STD_LOGIC;
signal rnw_match : STD_LOGIC;
signal row_match : STD_LOGIC;
signal txt_code : STD_LOGIC_VECTOR (23 DOWNTO 0);
signal za_cannotrefresh : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of m_addr : signal is "FAST_OUTPUT_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of m_bank : signal is "FAST_OUTPUT_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of m_cmd : signal is "FAST_OUTPUT_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of m_data : signal is "FAST_OUTPUT_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of m_dqm : signal is "FAST_OUTPUT_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of za_data : signal is "FAST_INPUT_REGISTER=ON";
begin
clk_en <= std_logic'('1');
--s1, which is an e_avalon_slave
(zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n) <= m_cmd;
zs_addr <= m_addr;
zs_cke <= clk_en;
zs_dq <= A_WE_StdLogicVector((std_logic'(oe) = '1'), m_data, A_REP(std_logic'('Z'), 16));
zs_dqm <= m_dqm;
zs_ba <= m_bank;
f_select <= f_pop AND pending;
f_cs_n <= std_logic'('0');
cs_n <= A_WE_StdLogic((std_logic'(f_select) = '1'), f_cs_n, active_cs_n);
csn_decode <= cs_n;
(f_rnw, f_addr(21), f_addr(20), f_addr(19), f_addr(18), f_addr(17), f_addr(16), f_addr(15), f_addr(14), f_addr(13), f_addr(12), f_addr(11), f_addr(10), f_addr(9), f_addr(8), f_addr(7), f_addr(6), f_addr(5), f_addr(4), f_addr(3), f_addr(2), f_addr(1), f_addr(0), f_dqm(1), f_dqm(0), f_data(15), f_data(14), f_data(13), f_data(12), f_data(11), f_data(10), f_data(9), f_data(8), f_data(7), f_data(6), f_data(5), f_data(4), f_data(3), f_data(2), f_data(1), f_data(0)) <= fifo_read_data;
--the_tracking_camera_system_sdram_0_input_efifo_module, which is an e_instance
the_tracking_camera_system_sdram_0_input_efifo_module : tracking_camera_system_sdram_0_input_efifo_module
port map(
almost_empty => almost_empty,
almost_full => almost_full,
empty => f_empty,
full => internal_za_waitrequest,
rd_data => fifo_read_data,
clk => clk,
rd => f_select,
reset_n => reset_n,
wr => module_input,
wr_data => module_input1
);
module_input <= ((NOT az_wr_n OR NOT az_rd_n)) AND NOT(internal_za_waitrequest);
module_input1 <= Std_Logic_Vector'(A_ToStdLogicVector(az_wr_n) & az_addr & A_WE_StdLogicVector((std_logic'(az_wr_n) = '1'), std_logic_vector'("00"), az_be_n) & az_data);
f_bank <= Std_Logic_Vector'(A_ToStdLogicVector(f_addr(21)) & A_ToStdLogicVector(f_addr(8)));
-- Refresh/init counter.
process (clk, reset_n)
begin
if reset_n = '0' then
refresh_counter <= std_logic_vector'("10011100010000");
elsif clk'event and clk = '1' then
if (std_logic_vector'("000000000000000000") & (refresh_counter)) = std_logic_vector'("00000000000000000000000000000000") then
refresh_counter <= std_logic_vector'("00011000011010");
else
refresh_counter <= A_EXT (((std_logic_vector'("0") & (refresh_counter)) - (std_logic_vector'("00000000000000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 14);
end if;
end if;
end process;
-- Refresh request signal.
process (clk, reset_n)
begin
if reset_n = '0' then
refresh_request <= std_logic'('0');
elsif clk'event and clk = '1' then
if true then
refresh_request <= (((to_std_logic((((std_logic_vector'("000000000000000000") & (refresh_counter)) = std_logic_vector'("00000000000000000000000000000000")))) OR refresh_request)) AND NOT ack_refresh_request) AND init_done;
end if;
end if;
end process;
-- Generate an Interrupt if two ref_reqs occur before one ack_refresh_request
process (clk, reset_n)
begin
if reset_n = '0' then
za_cannotrefresh <= std_logic'('0');
elsif clk'event and clk = '1' then
if true then
za_cannotrefresh <= to_std_logic((((std_logic_vector'("000000000000000000") & (refresh_counter)) = std_logic_vector'("00000000000000000000000000000000")))) AND refresh_request;
end if;
end if;
end process;
-- Initialization-done flag.
process (clk, reset_n)
begin
if reset_n = '0' then
init_done <= std_logic'('0');
elsif clk'event and clk = '1' then
if true then
init_done <= init_done OR to_std_logic(((i_state = std_logic_vector'("101"))));
end if;
end if;
end process;
-- **** Init FSM ****
process (clk, reset_n)
begin
if reset_n = '0' then
i_state <= std_logic_vector'("000");
i_next <= std_logic_vector'("000");
i_cmd <= std_logic_vector'("1111");
i_addr <= A_REP(std_logic'('1'), 12);
i_count <= A_REP(std_logic'('0'), 3);
elsif clk'event and clk = '1' then
i_addr <= A_REP(std_logic'('1'), 12);
case i_state is -- synthesis parallel_case full_case
when std_logic_vector'("000") =>
i_cmd <= std_logic_vector'("1111");
i_refs <= std_logic_vector'("000");
--Wait for refresh count-down after reset
if (std_logic_vector'("000000000000000000") & (refresh_counter)) = std_logic_vector'("00000000000000000000000000000000") then
i_state <= std_logic_vector'("001");
end if;
-- when std_logic_vector'("000")
when std_logic_vector'("001") =>
i_state <= std_logic_vector'("011");
i_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & std_logic_vector'("010"));
i_count <= std_logic_vector'("001");
i_next <= std_logic_vector'("010");
-- when std_logic_vector'("001")
when std_logic_vector'("010") =>
i_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & std_logic_vector'("001"));
i_refs <= A_EXT (((std_logic_vector'("0") & (i_refs)) + (std_logic_vector'("000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 3);
i_state <= std_logic_vector'("011");
i_count <= std_logic_vector'("111");
-- Count up init_refresh_commands
if i_refs = std_logic_vector'("001") then
i_next <= std_logic_vector'("111");
else
i_next <= std_logic_vector'("010");
end if;
-- when std_logic_vector'("010")
when std_logic_vector'("011") =>
i_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & std_logic_vector'("111"));
--WAIT til safe to Proceed...
if (std_logic_vector'("00000000000000000000000000000") & (i_count))>std_logic_vector'("00000000000000000000000000000001") then
i_count <= A_EXT (((std_logic_vector'("0") & (i_count)) - (std_logic_vector'("000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 3);
else
i_state <= i_next;
end if;
-- when std_logic_vector'("011")
when std_logic_vector'("101") =>
i_state <= std_logic_vector'("101");
-- when std_logic_vector'("101")
when std_logic_vector'("111") =>
i_state <= std_logic_vector'("011");
i_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & std_logic_vector'("000"));
i_addr <= A_REP(std_logic'('0'), 2) & A_ToStdLogicVector(std_logic'('0')) & std_logic_vector'("00") & std_logic_vector'("011") & std_logic_vector'("0000");
i_count <= std_logic_vector'("100");
i_next <= std_logic_vector'("101");
-- when std_logic_vector'("111")
when others =>
i_state <= std_logic_vector'("000");
-- when others
end case; -- i_state
end if;
end process;
active_bank <= Std_Logic_Vector'(A_ToStdLogicVector(active_addr(21)) & A_ToStdLogicVector(active_addr(8)));
csn_match <= to_std_logic((std_logic'(active_cs_n) = std_logic'(f_cs_n)));
rnw_match <= to_std_logic((std_logic'(active_rnw) = std_logic'(f_rnw)));
bank_match <= to_std_logic((active_bank = f_bank));
row_match <= to_std_logic((active_addr(20 DOWNTO 9) = f_addr(20 DOWNTO 9)));
pending <= (((csn_match AND rnw_match) AND bank_match) AND row_match) AND NOT(f_empty);
cas_addr <= A_EXT (A_WE_StdLogicVector((std_logic'(f_select) = '1'), (A_REP(std_logic'('0'), 4) & f_addr(7 DOWNTO 0)), (A_REP(std_logic'('0'), 4) & active_addr(7 DOWNTO 0))), 8);
-- **** Main FSM ****
process (clk, reset_n)
begin
if reset_n = '0' then
m_state <= std_logic_vector'("000000001");
m_next <= std_logic_vector'("000000001");
m_cmd <= std_logic_vector'("1111");
m_bank <= std_logic_vector'("00");
m_addr <= std_logic_vector'("000000000000");
m_data <= std_logic_vector'("0000000000000000");
m_dqm <= std_logic_vector'("00");
m_count <= std_logic_vector'("000");
ack_refresh_request <= std_logic'('0');
f_pop <= std_logic'('0');
oe <= std_logic'('0');
elsif clk'event and clk = '1' then
f_pop <= std_logic'('0');
oe <= std_logic'('0');
case m_state is -- synthesis parallel_case full_case
when std_logic_vector'("000000001") =>
--Wait for init-fsm to be done...
if std_logic'(init_done) = '1' then
--Hold bus if another cycle ended to arf.
if std_logic'(refresh_request) = '1' then
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & std_logic_vector'("111"));
else
m_cmd <= std_logic_vector'("1111");
end if;
ack_refresh_request <= std_logic'('0');
--Wait for a read/write request.
if std_logic'(refresh_request) = '1' then
m_state <= std_logic_vector'("001000000");
m_next <= std_logic_vector'("010000000");
m_count <= std_logic_vector'("001");
active_cs_n <= std_logic'('1');
elsif std_logic'(NOT(f_empty)) = '1' then
f_pop <= std_logic'('1');
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
m_state <= std_logic_vector'("000000010");
end if;
else
m_addr <= i_addr;
m_state <= std_logic_vector'("000000001");
m_next <= std_logic_vector'("000000001");
m_cmd <= i_cmd;
end if;
-- when std_logic_vector'("000000001")
when std_logic_vector'("000000010") =>
m_state <= std_logic_vector'("000000100");
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(csn_decode) & std_logic_vector'("011"));
m_bank <= active_bank;
m_addr <= active_addr(20 DOWNTO 9);
m_data <= active_data;
m_dqm <= active_dqm;
m_count <= std_logic_vector'("010");
m_next <= A_WE_StdLogicVector((std_logic'(active_rnw) = '1'), std_logic_vector'("000001000"), std_logic_vector'("000010000"));
-- when std_logic_vector'("000000010")
when std_logic_vector'("000000100") =>
-- precharge all if arf, else precharge csn_decode
if m_next = std_logic_vector'("010000000") then
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & std_logic_vector'("111"));
else
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(csn_decode) & std_logic_vector'("111"));
end if;
--Count down til safe to Proceed...
if (std_logic_vector'("00000000000000000000000000000") & (m_count))>std_logic_vector'("00000000000000000000000000000001") then
m_count <= A_EXT (((std_logic_vector'("0") & (m_count)) - (std_logic_vector'("000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 3);
else
m_state <= m_next;
end if;
-- when std_logic_vector'("000000100")
when std_logic_vector'("000001000") =>
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(csn_decode) & std_logic_vector'("101"));
m_bank <= A_WE_StdLogicVector((std_logic'(f_select) = '1'), f_bank, active_bank);
m_dqm <= A_WE_StdLogicVector((std_logic'(f_select) = '1'), f_dqm, active_dqm);
m_addr <= std_logic_vector'("0000") & (cas_addr);
--Do we have a transaction pending?
if std_logic'(pending) = '1' then
--if we need to ARF, bail, else spin
if std_logic'(refresh_request) = '1' then
m_state <= std_logic_vector'("000000100");
m_next <= std_logic_vector'("000000001");
m_count <= std_logic_vector'("010");
else
f_pop <= std_logic'('1');
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end if;
else
--correctly end RD spin cycle if fifo mt
if std_logic'((NOT pending AND f_pop)) = '1' then
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(csn_decode) & std_logic_vector'("111"));
end if;
m_state <= std_logic_vector'("100000000");
end if;
-- when std_logic_vector'("000001000")
when std_logic_vector'("000010000") =>
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(csn_decode) & std_logic_vector'("100"));
oe <= std_logic'('1');
m_data <= A_WE_StdLogicVector((std_logic'(f_select) = '1'), f_data, active_data);
m_dqm <= A_WE_StdLogicVector((std_logic'(f_select) = '1'), f_dqm, active_dqm);
m_bank <= A_WE_StdLogicVector((std_logic'(f_select) = '1'), f_bank, active_bank);
m_addr <= std_logic_vector'("0000") & (cas_addr);
--Do we have a transaction pending?
if std_logic'(pending) = '1' then
--if we need to ARF, bail, else spin
if std_logic'(refresh_request) = '1' then
m_state <= std_logic_vector'("000000100");
m_next <= std_logic_vector'("000000001");
m_count <= std_logic_vector'("010");
else
f_pop <= std_logic'('1');
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end if;
else
--correctly end WR spin cycle if fifo empty
if std_logic'((NOT pending AND f_pop)) = '1' then
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(csn_decode) & std_logic_vector'("111"));
oe <= std_logic'('0');
end if;
m_state <= std_logic_vector'("100000000");
end if;
-- when std_logic_vector'("000010000")
when std_logic_vector'("000100000") =>
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(csn_decode) & std_logic_vector'("111"));
--Count down til safe to Proceed...
if (std_logic_vector'("00000000000000000000000000000") & (m_count))>std_logic_vector'("00000000000000000000000000000001") then
m_count <= A_EXT (((std_logic_vector'("0") & (m_count)) - (std_logic_vector'("000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 3);
else
m_state <= std_logic_vector'("001000000");
m_count <= std_logic_vector'("001");
end if;
-- when std_logic_vector'("000100000")
when std_logic_vector'("001000000") =>
m_state <= std_logic_vector'("000000100");
m_addr <= A_REP(std_logic'('1'), 12);
-- precharge all if arf, else precharge csn_decode
if std_logic'(refresh_request) = '1' then
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & std_logic_vector'("010"));
else
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(csn_decode) & std_logic_vector'("010"));
end if;
-- when std_logic_vector'("001000000")
when std_logic_vector'("010000000") =>
ack_refresh_request <= std_logic'('1');
m_state <= std_logic_vector'("000000100");
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & std_logic_vector'("001"));
m_count <= std_logic_vector'("111");
m_next <= std_logic_vector'("000000001");
-- when std_logic_vector'("010000000")
when std_logic_vector'("100000000") =>
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(csn_decode) & std_logic_vector'("111"));
--if we need to ARF, bail, else spin
if std_logic'(refresh_request) = '1' then
m_state <= std_logic_vector'("000000100");
m_next <= std_logic_vector'("000000001");
m_count <= std_logic_vector'("001");
--wait for fifo to have contents
elsif std_logic'(NOT(f_empty)) = '1' then
--Are we 'pending' yet?
if std_logic'((((csn_match AND rnw_match) AND bank_match) AND row_match)) = '1' then
m_state <= A_WE_StdLogicVector((std_logic'(f_rnw) = '1'), std_logic_vector'("000001000"), std_logic_vector'("000010000"));
f_pop <= std_logic'('1');
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
else
m_state <= std_logic_vector'("000100000");
m_next <= std_logic_vector'("000000001");
m_count <= std_logic_vector'("001");
end if;
end if;
-- when std_logic_vector'("100000000")
when others =>
m_state <= m_state;
m_cmd <= std_logic_vector'("1111");
f_pop <= std_logic'('0');
oe <= std_logic'('0');
-- when others
end case; -- m_state
end if;
end process;
rd_strobe <= to_std_logic((m_cmd(2 DOWNTO 0) = std_logic_vector'("101")));
--Track RD Req's based on cas_latency w/shift reg
process (clk, reset_n)
begin
if reset_n = '0' then
rd_valid <= A_REP(std_logic'('0'), 3);
elsif clk'event and clk = '1' then
rd_valid <= (A_SLL(rd_valid,std_logic_vector'("00000000000000000000000000000001"))) OR (A_REP(std_logic'('0'), 2) & A_ToStdLogicVector(rd_strobe));
end if;
end process;
-- Register dq data.
process (clk, reset_n)
begin
if reset_n = '0' then
za_data <= std_logic_vector'("0000000000000000");
elsif clk'event and clk = '1' then
za_data <= zs_dq;
end if;
end process;
-- Delay za_valid to match registered data.
process (clk, reset_n)
begin
if reset_n = '0' then
za_valid <= std_logic'('0');
elsif clk'event and clk = '1' then
if true then
za_valid <= rd_valid(2);
end if;
end if;
end process;
cmd_code <= m_cmd(2 DOWNTO 0);
cmd_all <= m_cmd;
--vhdl renameroo for output signals
za_waitrequest <= internal_za_waitrequest;
--synthesis translate_off
process
VARIABLE write_line : line;
VARIABLE write_line1 : line;
VARIABLE write_line2 : line;
VARIABLE write_line3 : line;
VARIABLE write_line4 : line;
VARIABLE write_line5 : line;
VARIABLE write_line6 : line;
VARIABLE write_line7 : line;
begin
write(write_line, string'("This reference design requires a vendor simulation model."));
write(output, write_line.all & CR);
deallocate (write_line);
write(write_line1, string'("To simulate accesses to SDRAM, you must:"));
write(output, write_line1.all & CR);
deallocate (write_line1);
write(write_line2, string'(" - Download the vendor model"));
write(output, write_line2.all & CR);
deallocate (write_line2);
write(write_line3, string'(" - Install the model in the system_sim directory"));
write(output, write_line3.all & CR);
deallocate (write_line3);
write(write_line4, string'(" - Add the vendor file to the list of files passed to 'vcom' in setup_sim.do"));
write(output, write_line4.all & CR);
deallocate (write_line4);
write(write_line5, string'(" - Instantiate sdram simulation models and wire them to testbench signals"));
write(output, write_line5.all & CR);
deallocate (write_line5);
write(write_line6, string'(" - Be aware that you may have to disable some timing checks in the vendor model"));
write(output, write_line6.all & CR);
deallocate (write_line6);
write(write_line7, string'(" (because this simulation is zero-delay based)"));
write(output, write_line7.all & CR);
deallocate (write_line7);
wait;
end process;
txt_code <= A_WE_StdLogicVector(((cmd_code = std_logic_vector'("000"))), std_logic_vector'("010011000100110101010010"), A_WE_StdLogicVector(((cmd_code = std_logic_vector'("001"))), std_logic_vector'("010000010101001001000110"), A_WE_StdLogicVector(((cmd_code = std_logic_vector'("010"))), std_logic_vector'("010100000101001001000101"), A_WE_StdLogicVector(((cmd_code = std_logic_vector'("011"))), std_logic_vector'("010000010100001101010100"), A_WE_StdLogicVector(((cmd_code = std_logic_vector'("100"))), std_logic_vector'("001000000101011101010010"), A_WE_StdLogicVector(((cmd_code = std_logic_vector'("101"))), std_logic_vector'("001000000101001001000100"), A_WE_StdLogicVector(((cmd_code = std_logic_vector'("110"))), std_logic_vector'("010000100101001101010100"), A_WE_StdLogicVector(((cmd_code = std_logic_vector'("111"))), std_logic_vector'("010011100100111101010000"), std_logic_vector'("010000100100000101000100")))))))));
CODE <= A_WE_StdLogicVector((std_logic'(and_reduce(((cmd_all OR std_logic_vector'("0111"))))) = '1'), std_logic_vector'("010010010100111001001000"), txt_code);
--synthesis translate_on
end europa;
| gpl-2.0 | 1aa88c24004fc5f32e5608e2d3409d33 | 0.56076 | 3.890133 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/altera/memory/src/dpRam-rtl-a.vhd | 3 | 3,672 | --! @file dpRam-bhv-a.vhd
--
--! @brief Dual Port Ram Register Transfer Level Architecture
--
--! @details This is the DPRAM intended for synthesis on Altera platforms only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
-- Architecture : rtl
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use altera_mf library
library altera_mf;
use altera_mf.altera_mf_components.all;
architecture rtl of dpRam is
begin
altsyncram_component : altsyncram
generic map (
operation_mode => "BIDIR_DUAL_PORT",
intended_device_family => "Cyclone IV",
init_file => gInitFile,
numwords_a => gNumberOfWords,
numwords_b => gNumberOfWords,
widthad_a => logDualis(gNumberOfWords),
widthad_b => logDualis(gNumberOfWords),
width_a => gWordWidth,
width_b => gWordWidth,
width_byteena_a => gWordWidth/8,
width_byteena_b => gWordWidth/8
)
port map (
clock0 => iClk_A,
clocken0 => iEnable_A,
wren_a => iWriteEnable_A,
address_a => iAddress_A,
byteena_a => iByteenable_A,
data_a => iWritedata_A,
q_a => oReaddata_A,
clock1 => iClk_B,
clocken1 => iEnable_B,
wren_b => iWriteEnable_B,
address_b => iAddress_B,
byteena_b => iByteenable_B,
data_b => iWritedata_B,
q_b => oReaddata_B
);
end architecture rtl;
| gpl-2.0 | 9c1deec96316aaafa0f4bfc510087cc4 | 0.571895 | 4.756477 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/other/tx_arbitrator_over_ip.vhd | 1 | 2,120 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:03:30 06/04/2011
-- Design Name:
-- Module Name: tx_arbitrator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: arbitrate between two sources that want to transmit onto a bus
-- handles arbitration and multiplexing
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Made sticky on port M1 to optimise access on this port and allow immediate grant
-- Revision 0.03 - Added first
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipv4_types.all;
entity tx_arbitrator_over_ip is
port (
clk : in std_logic;
reset : in std_logic;
req_1 : in std_logic;
grant_1 : out std_logic;
data_1 : in ipv4_tx_type; -- data byte to tx
req_2 : in std_logic;
grant_2 : out std_logic;
data_2 : in ipv4_tx_type; -- data byte to tx
data : out ipv4_tx_type -- data byte to tx
);
end tx_arbitrator_over_ip;
architecture Behavioral of tx_arbitrator_over_ip is
type grant_type is (M1,M2);
signal grant : grant_type;
begin
combinatorial : process (
grant,
data_1,
data_2
)
begin
-- grant outputs
case grant is
when M1 =>
grant_1 <= '1';
grant_2 <= '0';
when M2 =>
grant_1 <= '0';
grant_2 <= '1';
end case;
-- multiplexer
if grant = M1 then
data <= data_1;
else
data <= data_2;
end if;
end process;
sequential : process (clk, reset, req_1, req_2, grant)
begin
if rising_edge(clk) then
if reset = '1' then
grant <= M1;
else
case grant is
when M1 =>
if req_1 = '1' then
grant <= M1;
elsif req_2 = '1' then
grant <= M2;
end if;
when M2 =>
if req_2 = '1' then
grant <= M2;
else
grant <= M1;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 8139a6b3c68394353a9e50ecf3e733d3 | 0.535849 | 3.081395 | false | false | false | false |
DreamIP/GPStudio | support/toolchain/caph/hdl/caph_toplevel/src/caph_toplevel.vhd | 1 | 7,261 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-- use caph_proc_comp package which list all component declaratio of caph processing
library work;
use work.caph_external_component.all;
use work.caph_processing_component.all;
use work.caph_flow_pkg.all;
entity caph_toplevel is
generic (
IN_SIZE :positive;
OUT_SIZE :positive;
INPUT_FREQ : positive;
IMAGE_WIDTH : positive;
IMAGE_HEIGHT: positive;
USE_PORTS : string :="NO";
NB_PORTS: positive;
MEM_ADDR_BUS_SIZE : POSITIVE := 4;
CLK_PROC_FREQ : positive;
CLK_CAPH_FREQ : positive
);
port (
clk_proc : in std_logic;
clk_caph : in std_logic;
reset : in std_logic;
in_data: in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_data : out std_logic_vector(OUT_SIZE-1 downto 0) ;
out_fv : out std_logic;
out_dv : out std_logic;
-- add param interface
-- param_addr_o: out std_logic_vector(MEM_ADDR_BUS_SIZE-1 DOWNTO 0);
-- param_data_i : in std_logic_vector(15 downto 0);
-- update_port_i : in std_logic
------ bus_sl ------
addr_rel_i : in std_logic_vector(MEM_ADDR_BUS_SIZE-1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end caph_toplevel;
architecture rtl of caph_toplevel is
constant TOKEN_SIZE : positive := 10;
--~ signal clk_caph : std_logic;
--TODO:change name of w3/w6
signal w3_f: std_logic;
signal w3_wr: std_logic;
signal token : std_logic_vector(TOKEN_SIZE-1 downto 0);
signal w6_rd: std_logic;
signal w6_e: std_logic;
signal w6: std_logic_vector(TOKEN_SIZE-1 downto 0);
signal frame_valid_s : std_logic := '0';
signal data_valid_s : std_logic := '0';
signal data_s : std_logic_vector(7 downto 0);
signal caph_ports_s : caph_ports_t;
signal param_wraddr_s : std_logic_vector(3 downto 0):=(others=>'0');
signal param_rdaddr_s : std_logic_vector(3 downto 0):=(others=>'0');
signal param_data_s : std_logic_vector(31 downto 0):=(others=>'0');
signal enable_s : std_logic := '0';
signal enable_s_sync : std_logic := '0';
-- signal port_s : std_logic_vector(31 downto 0):=(others=>'0');
signal imwidth_s :std_logic_vector(31 downto 0):=(others=>'0');
signal imheight_s :std_logic_vector(31 downto 0):=(others=>'0');
signal param_wr_s : std_logic:='0';
--component stroed in USB io in GPSTUDIO
component fv_synchro_signal is
port(
fv_i: in std_logic;
signal_i : in std_logic;
signal_o: out std_logic;
clk_i :in std_logic;
rst_n_i :in std_logic
);
end component;
begin
-- add pll pix_clk x 2 for caph fifo
--~ caph_pll_inst :caph_pll
--~ generic map( INPUT_FREQ => INPUT_FREQ)
--~ port map (
--~ inclk0 => clk_proc,
--~ c0 => clk_caph);
--~ TODO Synch ENABLE FV
--
ENABLE_IN0_INST: component fv_synchro_signal
port map(
fv_i => in_fv,
signal_i => enable_s,
signal_o => enable_s_sync,
clk_i => clk_proc,
rst_n_i => reset
);
tokenize_inst: component tokenize_flow
generic map(
DATA_INPUT_SIZE => IN_SIZE,
TOKEN_HEADER_SIZE => 2,
TOKEN_SIZE => TOKEN_SIZE,
IMAGE_WIDTH => 320, -- todo: remove generic
IMAGE_HEIGHT => 240
)
port map(
clk_i => clk_proc,
rst_n_i => reset,
dv_i => in_dv,
enable_i => enable_s_sync,
imwidth_i => imwidth_s,
imheight_i => imheight_s,
data_i => in_data,
clk_caph_i => clk_caph,
fifo_full_i => w3_f,
token_o => token,
wr_fifo_o => w3_wr
);
-- component params_to_ports
-- prend une connection wishbone et genere une liste de port en sortie
-- use array of record
-- TODO: use clk_caph with dual clock ram block
BI2CAPH_INST: component bus2caph
generic map(NB_PORTS=>NB_PORTS)
port map (
clk_i => clk_proc,
rst_n_i => reset,
addr_i => addr_rel_i,
wr_i => wr_i,
datawr_i => datawr_i,
enable_o => enable_s,
ports => caph_ports_s,
imwidth_o => imwidth_s,
imheight_o => imheight_s
);
--~ caph_proc : component dx_net
--~ port map(
--~ w3_f=> w3_f,
--~ w3 => token,
--~ w3_wr => w3_wr,
--~
--~ w6_e=> w6_e,
--~ w6 => w6,
--~ w6_rd=> w6_rd,
--~ clock=> clk_caph,
--~ reset => reset
--~ );
caph_proc : component conv33_port_net
port map
(
i_f=> w3_f,
i => token,
i_wr => w3_wr,
k0_f=> caph_ports_s(0).full,
k0 => caph_ports_s(0).data(15 downto 0),
k0_wr => caph_ports_s(0).wr,
k1_f=> caph_ports_s(1).full,
k1 => caph_ports_s(1).data(15 downto 0),
k1_wr => caph_ports_s(1).wr,
k2_f=> caph_ports_s(2).full,
k2 => caph_ports_s(2).data(15 downto 0),
k2_wr => caph_ports_s(2).wr,
k3_f=> caph_ports_s(3).full,
k3 => caph_ports_s(3).data(15 downto 0),
k3_wr => caph_ports_s(3).wr,
k4_f=> caph_ports_s(4).full,
k4 => caph_ports_s(4).data(15 downto 0),
k4_wr => caph_ports_s(4).wr,
k5_f=> caph_ports_s(5).full,
k5 => caph_ports_s(5).data(15 downto 0),
k5_wr => caph_ports_s(5).wr,
k6_f=> caph_ports_s(6).full,
k6 => caph_ports_s(6).data(15 downto 0),
k6_wr => caph_ports_s(6).wr,
k7_f=> caph_ports_s(7).full,
k7 => caph_ports_s(7).data(15 downto 0),
k7_wr => caph_ports_s(7).wr,
k8_f=> caph_ports_s(8).full,
k8 => caph_ports_s(8).data(15 downto 0),
k8_wr => caph_ports_s(8).wr,
n_f=> caph_ports_s(9).full,
n => caph_ports_s(9).data(7 downto 0),
n_wr => caph_ports_s(9).wr,
o_e=> w6_e,
o => w6,
o_rd=> w6_rd,
clock=> clk_caph,
reset => reset
);
--~ caph_proc : component dy_net
--~ port map(
--~ i_f=> w3_f,
--~ i => token,
--~ i_wr => w3_wr,
--~
--~ o_e=> w6_e,
--~ o => w6,
--~ o_rd=> w6_rd,
--~ clock=> clk_caph,
--~ reset => reset
--~ );
-- caph_proc : component port_test_net
-- port map(
-- w4_f=> w3_f,
-- w4 => token,
-- w4_wr => w3_wr,
--
-- w6_f=> caph_ports_s(0).full,
-- w6 => caph_ports_s(0).data(7 downto 0),
-- w6_wr => caph_ports_s(0).wr,
--
-- w9_e=> w6_e,
-- w9 => w6,
-- w9_rd=> w6_rd,
-- clock=> clk_caph,
-- reset => reset
-- );
--
--~ caph_proc : component inv_net
--~ port map(
--~ w3_f=> w3_f,
--~ w3 => token,
--~ w3_wr => w3_wr,
--~
--~ w6_e=> w6_e,
--~ w6 => w6,
--~ w6_rd=> w6_rd,
--~ clock=> clk_caph,
--~ reset => reset
--~ );
untokenize_inst: component untokenize_flow
GENERIC map(
IMAGE_WIDTH => 320,
IMAGE_HEIGHT => 240,
TOKEN_SIZE => TOKEN_SIZE,
SIZE => OUT_SIZE
)
PORT MAP(
clk_caph=> clk_caph,
clk_proc=> clk_proc,
rst_n_i => reset,
fifo_empty=> w6_e,
data_i => w6,
imwidth_i => imwidth_s,
imheight_i => imheight_s,
fifo_unpile=> w6_rd,
frame_valid_o => out_fv,
data_valid_o => out_dv,
data_o => out_data
);
-- Change 8bits to 16 for USB
--USB_packet_generator_inst:component packet_generator
-- port map(
-- rst_n_i => rst_n_i,
-- clk_i => clk_i,
-- frame_valid_i => frame_valid_s,
-- data_valid_i => data_valid_s,
-- data_i => data_s,
-- frame_valid_o => frame_valid_o,
-- data_valid_o => data_valid_o,
-- data_o => data_o
-- );
--
end rtl;
| gpl-3.0 | fdf98149fb46ac6498322a9b6f4e26e0 | 0.572098 | 2.359766 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/RGMII_MAC/eth_ddr_in.vhd | 1 | 4,001 | -- megafunction wizard: %ALTDDIO_IN%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTDDIO_IN
-- ============================================================
-- File Name: eth_ddr_in.vhd
-- Megafunction Name(s):
-- ALTDDIO_IN
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.0 Build 178 05/31/2012 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY eth_ddr_in IS
PORT
(
datain : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
inclock : IN STD_LOGIC ;
dataout_h : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
dataout_l : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END eth_ddr_in;
ARCHITECTURE SYN OF eth_ddr_in IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0);
BEGIN
dataout_h <= sub_wire0(4 DOWNTO 0);
dataout_l <= sub_wire1(4 DOWNTO 0);
ALTDDIO_IN_component : ALTDDIO_IN
GENERIC MAP (
intended_device_family => "Cyclone IV E",
invert_input_clocks => "OFF",
lpm_hint => "UNUSED",
lpm_type => "altddio_in",
power_up_high => "OFF",
width => 5
)
PORT MAP (
datain => datain,
inclock => inclock,
dataout_h => sub_wire0,
dataout_l => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH NUMERIC "5"
-- Retrieval info: USED_PORT: datain 0 0 5 0 INPUT NODEFVAL "datain[4..0]"
-- Retrieval info: CONNECT: @datain 0 0 5 0 datain 0 0 5 0
-- Retrieval info: USED_PORT: dataout_h 0 0 5 0 OUTPUT NODEFVAL "dataout_h[4..0]"
-- Retrieval info: CONNECT: dataout_h 0 0 5 0 @dataout_h 0 0 5 0
-- Retrieval info: USED_PORT: dataout_l 0 0 5 0 OUTPUT NODEFVAL "dataout_l[4..0]"
-- Retrieval info: CONNECT: dataout_l 0 0 5 0 @dataout_l 0 0 5 0
-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock"
-- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_in.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_in.qip TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_in.bsf FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_in_inst.vhd FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_in.inc FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_in.cmp FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_in.ppf TRUE FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | 639fb9bdc4d070c71099505cb2de15bc | 0.648588 | 3.607755 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/UDP/UDP_TX.vhd | 1 | 11,852 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 5 June 2011
-- Design Name:
-- Module Name: UDP_TX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple UDP TX
-- doesnt generate the checksum(supposedly optional)
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Added abort of tx when receive last from upstream
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
entity UDP_TX is
Port (
-- UDP Layer signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
-- IP layer TX signals
ip_tx_start : out std_logic;
ip_tx : out ipv4_tx_type; -- IP tx cxns
ip_tx_result : in std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : in std_logic; -- indicates IP TX is ready to take data
req_ip_layer : out std_logic;
granted_ip_layer : in std_logic
);
end UDP_TX;
architecture Behavioral of UDP_TX is
type tx_state_type is (IDLE, PAUSE, SEND_UDP_HDR, SEND_USER_DATA);
type count_mode_type is (RST, INCR, HOLD);
type settable_cnt_type is (RST, SET, INCR, HOLD);
type set_clr_type is (SET, CLR, HOLD);
-- TX state variables
signal udp_tx_state : tx_state_type;
signal tx_count : unsigned (15 downto 0);
signal tx_result_reg : std_logic_vector (1 downto 0);
signal ip_tx_start_reg : std_logic;
signal data_out_ready_reg : std_logic;
-- tx control signals
signal next_tx_state : tx_state_type;
signal set_tx_state : std_logic;
signal next_tx_result : std_logic_vector (1 downto 0);
signal set_tx_result : std_logic;
signal tx_count_val : unsigned (15 downto 0);
signal tx_count_mode : settable_cnt_type;
signal tx_data : std_logic_vector (7 downto 0);
signal set_last : std_logic;
signal set_ip_tx_start : set_clr_type;
signal tx_data_valid : std_logic; -- indicates whether data is valid to tx or not
signal tx_ip_chn_reqd : std_logic;--AJOUT JOHN
signal set_chn_reqd : set_clr_type;--AJOUT JOHN
-- tx temp signals
signal total_length : std_logic_vector (15 downto 0); -- computed combinatorially from header size
-- IP datagram header format
--
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | source port number | dest port number |
-- | | |
-- --------------------------------------------------------------------------------------------
-- | length (bytes) | checksum |
-- | (header and data combined) | |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
begin
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
tx_combinatorial : process(
-- input signals
udp_tx_start, udp_txi, clk, ip_tx_result, ip_tx_data_out_ready,
-- state variables
udp_tx_state, tx_count, tx_result_reg, ip_tx_start_reg, data_out_ready_reg, tx_ip_chn_reqd,--ajout john
-- control signals
next_tx_state, set_tx_state, next_tx_result, set_tx_result, tx_count_mode, tx_count_val,
tx_data, set_last, total_length, set_ip_tx_start, tx_data_valid, set_chn_reqd --ajout john
)
begin
-- set output followers
ip_tx_start <= ip_tx_start_reg;
ip_tx.hdr.protocol <= x"11"; -- UDP protocol
ip_tx.hdr.data_length <= total_length;
ip_tx.hdr.dst_ip_addr <= udp_txi.hdr.dst_ip_addr;
req_ip_layer <= tx_ip_chn_reqd;--AJOUT JOHN
if udp_tx_start = '1' and ip_tx_start_reg = '0' then
udp_tx_result <= UDPTX_RESULT_NONE; -- kill the result until have started the IP layer
else
udp_tx_result <= tx_result_reg;
end if;
case udp_tx_state is
when SEND_USER_DATA =>
ip_tx.data.data_out <= udp_txi.data.data_out;
tx_data_valid <= udp_txi.data.data_out_valid;
ip_tx.data.data_out_last <= udp_txi.data.data_out_last;
when SEND_UDP_HDR =>
ip_tx.data.data_out <= tx_data;
tx_data_valid <= ip_tx_data_out_ready;
ip_tx.data.data_out_last <= set_last;
when others =>
ip_tx.data.data_out <= (others => '0');
tx_data_valid <= '0';
ip_tx.data.data_out_last <= set_last;
end case;
ip_tx.data.data_out_valid <= tx_data_valid and ip_tx_data_out_ready;
-- set signal defaults
next_tx_state <= IDLE;
set_tx_state <= '0';
tx_count_mode <= HOLD;
tx_data <= x"00";
set_last <= '0';
next_tx_result <= UDPTX_RESULT_NONE;
set_tx_result <= '0';
set_ip_tx_start <= HOLD;
tx_count_val <= (others => '0');
udp_tx_data_out_ready <= '0';
set_chn_reqd <= HOLD;--ajout john
-- set temp signals
total_length <= std_logic_vector(unsigned(udp_txi.hdr.data_length) + 8); -- total length = user data length + header length (bytes)
-- TX FSM
case udp_tx_state is
when IDLE =>
udp_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
tx_count_mode <= RST;
if udp_tx_start = '1' then
-- check header count for error if too high
if unsigned(udp_txi.hdr.data_length) > 1472 then
next_tx_result <= UDPTX_RESULT_ERR;
set_tx_result <= '1';
set_chn_reqd <= CLR;--ajout john
else
-- start to send UDP header
tx_count_mode <= RST;
next_tx_result <= UDPTX_RESULT_SENDING;
set_ip_tx_start <= SET;
set_tx_result <= '1';
next_tx_state <= PAUSE;
set_tx_state <= '1';
set_chn_reqd <= SET;--ajout john
end if;
else
set_chn_reqd <= CLR;--ajout john
end if;
when PAUSE =>
if granted_ip_layer = '1' then
-- delay one clock for IP layer to respond to ip_tx_start and remove any tx error result
next_tx_state <= SEND_UDP_HDR;
set_tx_state <= '1';
end if;
when SEND_UDP_HDR =>
udp_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if ip_tx_result = IPTX_RESULT_ERR then
set_ip_tx_start <= CLR;
next_tx_result <= UDPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
elsif ip_tx_data_out_ready = '1' then
if tx_count = x"0007" then
tx_count_val <= x"0001";
tx_count_mode <= SET;
next_tx_state <= SEND_USER_DATA;
set_tx_state <= '1';
else
tx_count_mode <= INCR;
end if;
case tx_count is
when x"0000" => tx_data <= udp_txi.hdr.src_port (15 downto 8); -- src port
when x"0001" => tx_data <= udp_txi.hdr.src_port (7 downto 0);
when x"0002" => tx_data <= udp_txi.hdr.dst_port (15 downto 8); -- dst port
when x"0003" => tx_data <= udp_txi.hdr.dst_port (7 downto 0);
when x"0004" => tx_data <= total_length (15 downto 8); -- length
when x"0005" => tx_data <= total_length (7 downto 0);
when x"0006" => tx_data <= udp_txi.hdr.checksum (15 downto 8); -- checksum (set by upstream)
when x"0007" => tx_data <= udp_txi.hdr.checksum (7 downto 0);
when others =>
-- shouldnt get here - handle as error
next_tx_result <= UDPTX_RESULT_ERR;
set_tx_result <= '1';
end case;
end if;
when SEND_USER_DATA =>
udp_tx_data_out_ready <= ip_tx_data_out_ready; -- in this state, we can accept user data if IP TX rdy
if ip_tx_data_out_ready = '1' then
if udp_txi.data.data_out_valid = '1' or tx_count = x"000" then
-- only increment if ready and valid has been subsequently established, otherwise data count moves on too fast
if unsigned(tx_count) = unsigned(udp_txi.hdr.data_length) then
-- TX terminated due to count - end normally
set_last <= '1';
tx_data <= udp_txi.data.data_out;
next_tx_result <= UDPTX_RESULT_SENT;
set_ip_tx_start <= CLR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
set_chn_reqd <= CLR;--ajout john
elsif udp_txi.data.data_out_last = '1' then
-- terminate tx with error as got last from upstream before exhausting count
set_last <= '1';
tx_data <= udp_txi.data.data_out;
next_tx_result <= UDPTX_RESULT_ERR;
set_ip_tx_start <= CLR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
set_chn_reqd <= CLR;--ajout john
else
-- TX continues
tx_count_mode <= INCR;
tx_data <= udp_txi.data.data_out;
end if;
end if;
end if;
end case;
end process;
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
tx_sequential : process (clk,reset,data_out_ready_reg)
begin
if rising_edge(clk) then
data_out_ready_reg <= ip_tx_data_out_ready;
else
data_out_ready_reg <= data_out_ready_reg;
end if;
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
udp_tx_state <= IDLE;
tx_count <= x"0000";
tx_result_reg <= IPTX_RESULT_NONE;
ip_tx_start_reg <= '0';
tx_ip_chn_reqd <= '0';
else
-- Next udp_tx_state processing
if set_tx_state = '1' then
udp_tx_state <= next_tx_state;
else
udp_tx_state <= udp_tx_state;
end if;
-- ip_tx_start_reg processing
case set_ip_tx_start is
when SET => ip_tx_start_reg <= '1';
when CLR => ip_tx_start_reg <= '0';
when HOLD => ip_tx_start_reg <= ip_tx_start_reg;
end case;
-- tx result processing
if set_tx_result = '1' then
tx_result_reg <= next_tx_result;
else
tx_result_reg <= tx_result_reg;
end if;
-- tx_count processing
case tx_count_mode is
when RST => tx_count <= x"0000";
when SET => tx_count <= tx_count_val;
when INCR => tx_count <= tx_count + 1;
when HOLD => tx_count <= tx_count;
end case;
-- control access request to ip tx chn
case set_chn_reqd is
when SET => tx_ip_chn_reqd <= '1';
when CLR => tx_ip_chn_reqd <= '0';
when HOLD => tx_ip_chn_reqd <= tx_ip_chn_reqd;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 24afdab309c5d2dc5942209e4bcde61c | 0.522781 | 3.239136 | false | false | false | false |
freecores/wrimm | Example/WrimmExample_Top.vhd | 1 | 5,303 | --Latest version of all project files available at http://opencores.org/project,wrimm
--See License.txt for license details
--See WrimmManual.pdf for the Wishbone Datasheet and implementation details.
--See wrimm subversion project for version history
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.WrimmPackage.all;
entity Wrimm_Top is
port (
WishboneClock : in std_logic;
WishboneReset : out std_logic;
MasterPStrobe : in std_logic;
MasterPWrEn : in std_logic;
MasterPCyc : in std_logic;
MasterPAddr : in WbAddrType;
MasterPDataToSlave : in WbDataType;
MasterPAck : out std_logic;
MasterPErr : out std_logic;
MasterPRty : out std_logic;
MasterPDataFrSlave : out WbDataType;
MasterQStrobe : in std_logic;
MasterQWrEn : in std_logic;
MasterQCyc : in std_logic;
MasterQAddr : in WbAddrType;
MasterQDataToSlave : in WbDataType;
MasterQAck : out std_logic;
MasterQErr : out std_logic;
MasterQRty : out std_logic;
MasterQDataFrSlave : out WbDataType;
StatusRegA : in std_logic_vector(0 to 7);
StatusRegB : in std_logic_vector(0 to 7);
StatusRegC : in std_logic_vector(0 to 7);
SettingRegX : out std_logic_vector(0 to 7);
SettingRstX : in std_logic;
SettingRegY : out std_logic_vector(0 to 7);
SettingRstY : in std_logic;
SettingRegZ : out std_logic_vector(0 to 7);
SettingRstZ : in std_logic;
TriggerRegR : out std_logic;
TriggerClrR : in std_logic;
TriggerRegS : out std_logic;
TriggerClrS : in std_logic;
TriggerRegT : out std_logic;
TriggerClrT : in std_logic;
rstZ : in std_logic); --Global asyncronous reset for initialization
end entity Wrimm_Top;
architecture structure of Wrimm_Top is
component Wrimm is
--generic (
-- MasterParams : WbMasterDefType;
-- SlaveParams : WbSlaveDefType;
-- StatusParams : StatusFieldDefType;
-- SettingParams : SettingFieldDefType;
-- TriggerParams : TriggerFieldDefType);
port (
WbClk : in std_logic;
WbRst : out std_logic;
WbMasterIn : in WbMasterOutArray; --Signals from Masters
WbMasterOut : out WbSlaveOutArray; --Signals to Masters
-- WbSlaveIn : out WbMasterOutArray;
-- WbSlaveOut : in WbSlaveOutArray;
StatusRegs : in StatusArrayType;
SettingRegs : out SettingArrayType;
SettingRsts : in SettingArrayBitType;
Triggers : out TriggerArrayType;
TriggerClr : in TriggerArrayType;
rstZ : in std_logic); --Asynchronous reset
end component Wrimm;
signal masterQOut : WbSlaveOutType;
signal masterQIn : WbMasterOutType;
begin
MasterQAck <= masterQOut.ack;
MasterQErr <= masterQOut.err;
MasterQRty <= masterQOut.rty;
MasterQDataFrSlave <= masterQOut.data;
masterQIn.strobe <= MasterQStrobe;
masterQIn.wren <= MasterQWrEn;
masterQIn.cyc <= MasterQCyc;
masterQIn.addr <= MasterQAddr;
masterQIn.data <= MasterQDataToSlave;
instWrimm: Wrimm
--generic map(
-- MasterParams => ,
-- SlaveParams => ,
-- StatusParams => StatusParams,
-- SettingParams => SettingParams,
-- TriggerParams => TriggerParams)
port map(
WbClk => WishboneClock,
WbRst => WishboneReset,
WbMasterIn(P).strobe => MasterPStrobe,
WbMasterIn(P).wren => MasterPWrEn,
WbMasterIn(P).cyc => MasterPCyc,
WbMasterIn(P).addr => MasterPAddr,
WbMasterIn(P).data => MasterPDataToSlave,
WbMasterIn(Q) => masterQIn,
WbMasterOut(P).ack => MasterPAck,
WbMasterOut(P).err => MasterPErr,
WbMasterOut(P).rty => MasterPRty,
WbMasterOut(P).data => MasterPDataFrSlave,
WbMasterOut(Q) => masterQOut,
--WbSlaveIn => ,
--WbSlaveOut => ,
StatusRegs(StatusA) => StatusRegA,
StatusRegs(StatusB) => StatusRegB,
StatusRegs(StatusC) => StatusRegC,
SettingRegs(SettingX) => SettingRegX,
SettingRegs(SettingY) => SettingRegY,
SettingRegs(SettingZ) => SettingRegZ,
SettingRsts(SettingX) => SettingRstX,
SettingRsts(SettingY) => SettingRstY,
SettingRsts(SettingZ) => SettingRstZ,
Triggers(TriggerR) => TriggerRegR,
Triggers(TriggerS) => TriggerRegS,
Triggers(TriggerT) => TriggerRegT,
TriggerClr(TriggerR) => TriggerClrR,
TriggerClr(TriggerS) => TriggerClrS,
TriggerClr(TriggerT) => TriggerClrT,
rstZ => rstZ); --Asynchronous reset
end architecture structure; | bsd-3-clause | 3d85a1b397e34426a59000787108012b | 0.57326 | 3.848331 | false | false | false | false |
Reiuiji/ECE368-Lab | Lab 3/Keyboard/misc/ps2_ascii_gen.vhd | 1 | 7,948 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: PS/2 Ascii Generator
-- Project Name: Keyboard Controller
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Generate ASCII from PS/2 input
-- Maintain Keyboard(reset,set num,caps lock)
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PS2_ASCII_GEN is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
PS2_RX : in STD_LOGIC_VECTOR (7 downto 0);
PS2_RD : in STD_LOGIC;
PS2_BS : in STD_LOGIC;
PS2_ER : in STD_LOGIC;
PS2_TX : out STD_LOGIC_VECTOR (7 downto 0);
PS2_WR : out STD_LOGIC;
ASCII : out STD_LOGIC_VECTOR (7 downto 0);
ASCII_RD : out STD_LOGIC;
ASCII_SP : out STD_LOGIC); -- Special Key Flag
end PS2_ASCII_GEN;
architecture Behavioral of PS2_ASCII_GEN is
type statetype is (idle, shift, read_b, read_e, read_eb, caps_toggle, busy_wait,reset);
signal state : statetype := idle;
signal wstate : statetype := idle;
signal ascii_lower : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ascii_upper : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
shared variable shift_key : boolean := false;
shared variable caps : boolean := false;
begin
with PS2_RX select
ascii_lower <=
-- Alphabet
x"61" when x"1C",-- a
x"62" when x"32",-- b
x"63" when x"21",-- c
x"64" when x"23",-- d
x"65" when x"24",-- e
x"66" when x"2B",-- f
x"67" when x"34",-- g
x"68" when x"33",-- h
x"69" when x"43",-- i
x"6A" when x"3B",-- j
x"6B" when x"42",-- k
x"6C" when x"4B",-- l
x"6D" when x"3A",-- m
x"6E" when x"31",-- n
x"6F" when x"44",-- o
x"70" when x"4D",-- p
x"71" when x"15",-- q
x"72" when x"2D",-- r
x"73" when x"1B",-- s
x"74" when x"2C",-- t
x"75" when x"3C",-- u
x"76" when x"2A",-- v
x"77" when x"1D",-- w
x"78" when x"22",-- x
x"79" when x"35",-- y
x"7A" when x"1A",-- z
--Top Row
x"60" when x"0E",-- `
x"31" when x"16",-- 1
x"32" when x"1E",-- 2
x"33" when x"26",-- 3
x"34" when x"25",-- 4
x"35" when x"2E",-- 5
x"36" when x"36",-- 6
x"37" when x"3D",-- 7
x"38" when x"3E",-- 8
x"39" when x"46",-- 9
x"30" when x"45",-- 0
x"2D" when x"4E",-- -
x"3D" when x"55",-- =
--Enter Corner
x"5B" when x"54",-- [
x"5D" when x"5B",-- ]
x"5C" when x"5D",-- \
x"3B" when x"4C",-- ;
x"27" when x"52",-- '
x"2C" when x"41",-- ,
x"2E" when x"49",-- .
x"2F" when x"4A",-- /
--Function Keys -- Based on the IBM PC Codes
x"1B" when x"76",-- Esc (Escape)
x"3B" when x"05",-- F1
x"3C" when x"06",-- F2
x"3D" when x"04",-- F3
x"3E" when x"0C",-- F4
x"3F" when x"03",-- F5
x"40" when x"0B",-- F6
x"41" when x"83",-- F7
x"42" when x"0A",-- F8
x"43" when x"01",-- F9
x"44" when x"09",-- F10
x"85" when x"78",-- F11
x"86" when x"07",-- F12
x"09" when x"0D",-- Tab (Horizontal Tab)
x"0D" when x"5A",-- Enter (Carriage Return)
--need no value *(special characters)
x"00" when x"58",-- Caps Lock
x"00" when x"14",-- Ctrl
x"00" when x"11",-- Alt
x"00" when x"66",-- Back Space
--Direction Keys
x"48" when x"75",-- Up
x"50" when x"72",-- Down
x"4B" when x"6B",-- Left
x"4D" when x"74",-- Right
--Unknown input
x"00" when OTHERS; -- Null
with PS2_RX select
ascii_upper <=
-- Alphabet
x"41" when x"1C",-- A
x"42" when x"32",-- B
x"43" when x"21",-- C
x"44" when x"23",-- D
x"45" when x"24",-- E
x"46" when x"2B",-- F
x"47" when x"34",-- G
x"48" when x"33",-- H
x"49" when x"43",-- I
x"4A" when x"3B",-- J
x"4B" when x"42",-- K
x"4C" when x"4B",-- L
x"4D" when x"3A",-- M
x"4E" when x"31",-- N
x"4F" when x"44",-- O
x"50" when x"4D",-- P
x"51" when x"15",-- Q
x"52" when x"2D",-- R
x"53" when x"1B",-- S
x"54" when x"2C",-- T
x"55" when x"3C",-- U
x"56" when x"2A",-- V
x"57" when x"1D",-- W
x"58" when x"22",-- X
x"59" when x"35",-- Y
x"5A" when x"1A",-- Z
-- Special Upper case Characters (top left to bottom right)
-- Top Row
x"7E" when x"0E",-- ~
x"21" when x"16",-- !
x"40" when x"1E",-- @
x"23" when x"26",-- #
x"24" when x"25",-- $
x"25" when x"2E",-- %
x"5E" when x"36",-- ^
x"26" when x"3D",-- &
x"2A" when x"3E",-- *
x"28" when x"46",-- (
x"29" when x"45",-- )
x"5F" when x"4E",-- _
x"2B" when x"55",-- +
-- Enter Corner
x"7B" when x"54",-- {
x"7D" when x"5B",-- }
x"7C" when x"5D",-- |
x"3A" when x"4C",-- :
x"22" when x"52",-- "
x"3C" when x"41",-- <
x"3E" when x"49",-- >
x"3F" when x"4A",-- ?
-- Unknown Key
x"00" when OTHERS; -- Null
process (CLK,RST,PS2_RX,PS2_RD,PS2_ER)
begin
if (RST = '1' and PS2_ER = '1') then
state <= reset;
elsif (PS2_RD'event and PS2_RD = '1') then--(CLK'event and CLK = '1') then
case state is
when idle =>
--if (PS2_RD'event and PS2_RD = '1') then
ASCII_SP <= '0';
ASCII_RD <= '0';
if PS2_RX = x"F0" then
state <= read_b;
elsif PS2_RX = x"E0" then
state <= read_e;
elsif(PS2_RX = x"12" or PS2_RX = x"54") then
state <= shift;
end if;
--end if;
when read_b =>
--if (PS2_RD'event and PS2_RD = '1') then
if caps = true then
ASCII <= ascii_upper;
else
ASCII <= ascii_lower;
end if;
ASCII_RD <= '1';
--end if;
when read_e =>
--if (PS2_RD'event and PS2_RD = '1') then
if PS2_RX = x"F0" then
state <= read_eb;
ASCII_SP <= '1'; -- Enable Special Mode
else
state <= idle;
end if;
--end if;
when read_eb =>
--if (PS2_RD'event and PS2_RD = '1') then
ASCII <= ascii_lower;
ASCII_RD <= '1';
--end if;
when shift =>
--ASCII <= ascii_upper;
--ASCII_RD <= '1';
state <= idle;
when caps_toggle =>
PS2_TX <= x"ED";
PS2_WR <= '1';
when reset =>
PS2_TX <= x"FF"; --send keyboard reset cmd
PS2_WR <= '1';
state <= idle;
when busy_wait =>
if PS2_BS = '0' then
state <= wstate;
end if;
when others =>
state <= idle;
end case;
end if;
end process;
end Behavioral;
| mit | 63c13dfdbbfaf4d1e71552305e672ba0 | 0.417212 | 3.19839 | false | false | false | false |
hoglet67/ElectronFpga | AtomBusMon/src/MOS6502CpuMonCore.vhd | 1 | 14,367 | ------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : MOS6502CpuMonCore.vhd
-- /___/ /\ Timestamp : 3/11/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: MOS6502CpuMonCore
--Device: multiple
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MOS6502CpuMonCore is
generic (
UseT65Core : boolean;
UseAlanDCore : boolean;
-- default sizing is used by Electron/Beeb Fpga
num_comparators : integer := 8;
avr_prog_mem_size : integer := 1024 * 8
);
port (
clock_avr : in std_logic;
busmon_clk : in std_logic;
busmon_clken : in std_logic;
cpu_clk : in std_logic;
cpu_clken : in std_logic;
-- 6502 Signals
IRQ_n : in std_logic;
NMI_n : in std_logic;
Sync : out std_logic;
Addr : out std_logic_vector(15 downto 0);
R_W_n : out std_logic;
Din : in std_logic_vector(7 downto 0);
Dout : out std_logic_vector(7 downto 0);
SO_n : in std_logic;
Res_n : in std_logic;
Rdy : in std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- Switches
sw_reset_cpu : in std_logic;
sw_reset_avr : in std_logic;
-- LEDs
led_bkpt : out std_logic;
led_trig0 : out std_logic;
led_trig1 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic
);
end MOS6502CpuMonCore;
architecture behavioral of MOS6502CpuMonCore is
type state_type is (idle, nop0, nop1, rd, wr, exec1, exec2);
signal state : state_type;
signal cpu_clken_ss : std_logic;
signal Data : std_logic_vector(7 downto 0);
signal Din_int : std_logic_vector(7 downto 0);
signal Dout_int : std_logic_vector(7 downto 0);
signal R_W_n_int : std_logic;
signal Rd_n_mon : std_logic;
signal Wr_n_mon : std_logic;
signal Sync_mon : std_logic;
signal Done_mon : std_logic;
signal Sync_int : std_logic;
signal Addr_int : std_logic_vector(23 downto 0);
signal cpu_addr_us : unsigned (15 downto 0);
signal cpu_dout_us : unsigned (7 downto 0);
signal cpu_reset_n : std_logic;
signal Regs : std_logic_vector(63 downto 0);
signal Regs1 : std_logic_vector(255 downto 0);
signal last_PC : std_logic_vector(15 downto 0);
signal SS_Single : std_logic;
signal SS_Step : std_logic;
signal SS_Step_held : std_logic;
signal CountCycle : std_logic;
signal special : std_logic_vector(2 downto 0);
signal memory_rd : std_logic;
signal memory_rd1 : std_logic;
signal memory_wr : std_logic;
signal memory_wr1 : std_logic;
signal memory_addr : std_logic_vector(15 downto 0);
signal memory_dout : std_logic_vector(7 downto 0);
signal memory_din : std_logic_vector(7 downto 0);
signal memory_done : std_logic;
signal NMI_n_masked : std_logic;
signal IRQ_n_masked : std_logic;
signal exec : std_logic;
signal exec_held : std_logic;
signal op3 : std_logic;
begin
mon : entity work.BusMonCore
generic map (
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
clock_avr => clock_avr,
busmon_clk => busmon_clk,
busmon_clken => busmon_clken,
cpu_clk => cpu_clk,
cpu_clken => cpu_clken,
Addr => Addr_int(15 downto 0),
Data => Data,
Rd_n => Rd_n_mon,
Wr_n => Wr_n_mon,
RdIO_n => '1',
WrIO_n => '1',
Sync => Sync_mon,
Rdy => open,
nRSTin => Res_n,
nRSTout => cpu_reset_n,
CountCycle => CountCycle,
trig => trig,
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk,
Regs => Regs1,
RdMemOut => memory_rd,
WrMemOut => memory_wr,
RdIOOut => open,
WrIOOut => open,
ExecOut => exec,
AddrOut => memory_addr,
DataOut => memory_dout,
DataIn => memory_din,
Done => Done_mon,
Special => special,
SS_Step => SS_Step,
SS_Single => SS_Single
);
Wr_n_mon <= Rdy and R_W_n_int;
Rd_n_mon <= Rdy and not R_W_n_int;
Sync_mon <= Rdy and Sync_int;
Done_mon <= Rdy and memory_done;
Data <= Din when R_W_n_int = '1' else Dout_int;
NMI_n_masked <= NMI_n or special(1);
IRQ_n_masked <= IRQ_n or special(0);
-- The CPU is slightly pipelined and the register update of the last
-- instruction overlaps with the opcode fetch of the next instruction.
--
-- If the single stepping stopped on the opcode fetch cycle, then the registers
-- valued would not accurately reflect the previous instruction.
--
-- To work around this, when single stepping, we stop on the cycle after
-- the opcode fetch, which means the program counter has advanced.
--
-- To hide this from the user single stepping, all we need to do is to
-- also pipeline the value of the program counter by one stage to compensate.
last_pc_gen : process(cpu_clk)
begin
if rising_edge(cpu_clk) then
if cpu_clken = '1' then
if state = idle then
last_PC <= Regs(63 downto 48);
end if;
end if;
end if;
end process;
Regs1( 47 downto 0) <= Regs( 47 downto 0);
Regs1( 63 downto 48) <= last_PC;
Regs1(255 downto 64) <= (others => '0');
cpu_clken_ss <= '1' when Rdy = '1' and (state = idle or state = exec1 or state = exec2) and cpu_clken = '1' else '0';
GenT65Core: if UseT65Core generate
inst_t65: entity work.T65 port map (
mode => "00",
Abort_n => '1',
SO_n => SO_n,
Res_n => cpu_reset_n,
Enable => cpu_clken_ss,
Clk => cpu_clk,
Rdy => '1',
IRQ_n => IRQ_n_masked,
NMI_n => NMI_n_masked,
R_W_n => R_W_n_int,
Sync => Sync_int,
A => Addr_int,
DI => Din_int,
DO => Dout_int,
Regs => Regs
);
end generate;
GenAlanDCore: if UseAlanDCore generate
inst_r65c02: entity work.r65c02 port map (
reset => cpu_reset_n,
clk => cpu_clk,
enable => cpu_clken_ss,
nmi_n => NMI_n_masked,
irq_n => IRQ_n_masked,
di => unsigned(Din_int),
do => cpu_dout_us,
addr => cpu_addr_us,
nwe => R_W_n_int,
sync => Sync_int,
sync_irq => open,
Regs => Regs
);
Dout_int <= std_logic_vector(cpu_dout_us);
Addr_int(15 downto 0) <= std_logic_vector(cpu_addr_us);
end generate;
-- 00 IMP, INDX, IMP, IMP, ZP, ZP, ZP, IMP, IMP, IMM, IMPA, IMP, ABS, ABS, ABS, IMP,
-- 10 BRA, INDY, IND, IMP, ZP, ZPX, ZPX, IMP, IMP, ABSY, IMPA, IMP, ABS, ABSX, ABSX, IMP,
-- 20 ABS, INDX, IMP, IMP, ZP, ZP, ZP, IMP, IMP, IMM, IMPA, IMP, ABS, ABS, ABS, IMP,
-- 30 BRA, INDY, IND, IMP, ZPX, ZPX, ZPX, IMP, IMP, ABSY, IMPA, IMP, ABSX, ABSX, ABSX, IMP,
-- 40 IMP, INDX, IMP, IMP, ZP, ZP, ZP, IMP, IMP, IMM, IMPA, IMP, ABS, ABS, ABS, IMP,
-- 50 BRA, INDY, IND, IMP, ZP, ZPX, ZPX, IMP, IMP, ABSY, IMP, IMP, ABS, ABSX, ABSX, IMP,
-- 60 IMP, INDX, IMP, IMP, ZP, ZP, ZP, IMP, IMP, IMM, IMPA, IMP, IND16, ABS, ABS, IMP,
-- 70 BRA, INDY, IND, IMP, ZPX, ZPX, ZPX, IMP, IMP, ABSY, IMP, IMP, IND1X, ABSX, ABSX, IMP,
-- 80 BRA, INDX, IMP, IMP, ZP, ZP, ZP, IMP, IMP, IMM, IMP, IMP, ABS, ABS, ABS, IMP,
-- 90 BRA, INDY, IND, IMP, ZPX, ZPX, ZPY, IMP, IMP, ABSY, IMP, IMP, ABS, ABSX, ABSX, IMP,
-- A0 IMM, INDX, IMM, IMP, ZP, ZP, ZP, IMP, IMP, IMM, IMP, IMP, ABS, ABS, ABS, IMP,
-- B0 BRA, INDY, IND, IMP, ZPX, ZPX, ZPY, IMP, IMP, ABSY, IMP, IMP, ABSX, ABSX, ABSY, IMP,
-- C0 IMM, INDX, IMP, IMP, ZP, ZP, ZP, IMP, IMP, IMM, IMP, IMP, ABS, ABS, ABS, IMP,
-- D0 BRA, INDY, IND, IMP, ZP, ZPX, ZPX, IMP, IMP, ABSY, IMP, IMP, ABS, ABSX, ABSX, IMP,
-- E0 IMM, INDX, IMP, IMP, ZP, ZP, ZP, IMP, IMP, IMM, IMP, IMP, ABS, ABS, ABS, IMP,
-- F0 BRA, INDY, IND, IMP, ZP, ZPX, ZPX, IMP, IMP, ABSY, IMP, IMP, ABS, ABSX, ABSX, IMP
-- Detect forced opcodes that are 3 bytes long
op3 <= '1' when memory_dout(7 downto 0) = "00100000" else
'1' when memory_dout(4 downto 0) = "11011" else
'1' when memory_dout(3 downto 0) = "1100" else
'1' when memory_dout(3 downto 0) = "1101" else
'1' when memory_dout(3 downto 0) = "1110" else
'0';
Din_int <= memory_dout( 7 downto 0) when state = idle and Sync_int = '1' and exec_held = '1' else
memory_addr( 7 downto 0) when state = exec1 else
memory_addr(15 downto 8) when state = exec2 else
Din;
men_access_machine : process(cpu_clk, cpu_reset_n)
begin
if cpu_reset_n = '0' then
state <= idle;
elsif rising_edge(cpu_clk) then
-- Extend the control signals from BusMonitorCore which
-- only last one cycle.
if SS_Step = '1' then
SS_Step_held <= '1';
elsif state = idle then
SS_Step_held <= '0';
end if;
if memory_rd = '1' then
memory_rd1 <= '1';
elsif state = rd then
memory_rd1 <= '0';
end if;
if memory_wr = '1' then
memory_wr1 <= '1';
elsif state = wr then
memory_wr1 <= '0';
end if;
if exec = '1' then
exec_held <= '1';
elsif state = exec1 then
exec_held <= '0';
end if;
if cpu_clken = '1' and Rdy = '1' then
case state is
-- idle is when the CPU is running normally
when idle =>
if Sync_int = '1' then
if exec_held = '1' then
state <= exec1;
elsif SS_Single = '1' then
state <= nop0;
end if;
end if;
-- nop0 is the first state entered when the CPU is paused
when nop0 =>
if memory_rd1 = '1' then
state <= rd;
elsif memory_wr1 = '1' then
state <= wr;
elsif SS_Step_held = '1' or exec_held = '1' then
state <= idle;
else
state <= nop1;
end if;
-- nop1 simulates a sync cycle
when nop1 =>
state <= nop0;
-- rd is a monitor initiated read cycle
when rd =>
state <= nop0;
-- wr is a monitor initiated write cycle
when wr =>
state <= nop0;
-- exec1 is the LSB of a forced JMP
when exec1 =>
if op3 = '1' then
state <= exec2;
else
state <= idle;
end if;
-- exec2 is the MSB of a forced JMP
when exec2 =>
state <= idle;
end case;
end if;
end if;
end process;
-- Only count cycles when the 6502 is actually running
-- TODO: Should this be qualified with cpu_clken and rdy?
CountCycle <= '1' when state = idle or state = exec1 or state = exec2 else '0';
R_W_n <= R_W_n_int when state = idle else
'0' when state = wr else
'1';
Addr <= Addr_int(15 downto 0) when state = idle else
memory_addr when state = rd or state = wr else
(others => '0');
Sync <= Sync_int when state = idle else
'1' when state = nop1 else
'0';
Dout <= Dout_int when state = idle else
memory_dout;
-- Data is captured by the bus monitor on the rising edge of cpu_clk
-- that sees done = 1.
memory_done <= '1' when state = rd or state = wr or (op3 = '0' and state = exec1) or state = exec2 else '0';
memory_din <= Din;
end behavioral;
| gpl-3.0 | c1bf394aaeec0f5c90b98f0c345bd338 | 0.459177 | 3.625284 | false | false | false | false |
DreamIP/GPStudio | support/io/com/hdl/hal/eth_marvell_88e1111/hdl/encapsulation/crc32_8.vhd | 1 | 6,610 | ----------------------------------------------------------------------------------
-- Company: Laboratoire Leprince-Ringuet
-- Engineer:
--
-- Create Date: 12:09:35 10/14/2011
-- Design Name:
-- Module Name: crc32_8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- CRC Calculation
-- This VHDL code was generated using CRCGEN.PL version 1.7
-- Last Modified: 01/02/2002
-- Options Used:
-- Module Name = crc32
-- CRC Width = 32
-- Data Width = 8
-- CRC Init = F
-- Polynomial = [0 -> 32]
-- 1 1 1 0 1 1 0 1 1 0 1 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
-- Copyright (c) 2001,2002 Xilinx, Inc. All rights reserved.
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity crc32_8 is Port(
CRC_REG : out STD_LOGIC_VECTOR(31 downto 0);
CRC : out STD_LOGIC_VECTOR(7 downto 0);
D : in STD_LOGIC_VECTOR(7 downto 0);
CALC : in STD_LOGIC;
INIT : in STD_LOGIC;--synchronous reset
D_VALID : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC);--asynchronous reset
end crc32_8;
architecture Behavioral of crc32_8 is
signal next_crc : STD_LOGIC_VECTOR(31 downto 0);
signal crcreg : STD_LOGIC_VECTOR(31 downto 0);
begin
CRC_REG <= crcreg;
--CRC XOR equations
next_crc(0) <= crcreg(30) xor D(1) xor crcreg(24) xor D(7);
next_crc(1) <= D(6) xor D(7) xor D(0) xor crcreg(30) xor crcreg(31) xor D(1) xor crcreg(24) xor crcreg(25);
next_crc(2) <= crcreg(26) xor D(5) xor D(6) xor D(7) xor crcreg(30) xor D(0) xor D(1) xor crcreg(31) xor crcreg(24) xor crcreg(25);
next_crc(3) <= D(4) xor crcreg(26) xor D(5) xor crcreg(27) xor D(6) xor D(0) xor crcreg(31) xor crcreg(25);
next_crc(4) <= D(4) xor crcreg(26) xor D(5) xor crcreg(27) xor crcreg(28) xor D(7) xor crcreg(30) xor D(1) xor crcreg(24) xor D(3);
next_crc(5) <= D(4) xor crcreg(27) xor D(6) xor crcreg(28) xor D(7) xor crcreg(29) xor crcreg(30) xor D(0) xor D(1) xor crcreg(31) xor D(2) xor crcreg(24) xor D(3) xor crcreg(25);
next_crc(6) <= crcreg(26) xor D(5) xor D(6) xor crcreg(28) xor crcreg(29) xor D(0) xor crcreg(30) xor crcreg(31) xor D(1) xor D(2) xor D(3) xor crcreg(25);
next_crc(7) <= D(4) xor crcreg(26) xor D(5) xor crcreg(27) xor D(7) xor crcreg(29) xor D(0) xor crcreg(31) xor D(2) xor crcreg(24);
next_crc(8) <= D(4) xor crcreg(27) xor D(6) xor crcreg(28) xor D(7) xor crcreg(24) xor crcreg(0) xor D(3) xor crcreg(25);
next_crc(9) <= crcreg(26) xor D(5) xor D(6) xor crcreg(28) xor crcreg(29) xor D(2) xor D(3) xor crcreg(25) xor crcreg(1);
next_crc(10) <= D(4) xor crcreg(26) xor crcreg(2) xor D(5) xor crcreg(27) xor D(7) xor crcreg(29) xor D(2) xor crcreg(24);
next_crc(11) <= D(4) xor crcreg(27) xor D(6) xor crcreg(3) xor crcreg(28) xor D(7) xor crcreg(24) xor D(3) xor crcreg(25);
next_crc(12) <= crcreg(26) xor D(5) xor D(6) xor crcreg(28) xor D(7) xor crcreg(4) xor crcreg(29) xor crcreg(30) xor D(1) xor D(2) xor crcreg(24) xor D(3) xor crcreg(25);
next_crc(13) <= D(4) xor crcreg(26) xor D(5) xor crcreg(27) xor D(6) xor crcreg(29) xor D(0) xor crcreg(30) xor crcreg(5) xor crcreg(31) xor D(1) xor D(2) xor crcreg(25);
next_crc(14) <= D(4) xor crcreg(26) xor D(5) xor crcreg(27) xor crcreg(28) xor crcreg(30) xor D(0) xor D(1) xor crcreg(31) xor crcreg(6) xor D(3);
next_crc(15) <= D(4) xor crcreg(27) xor crcreg(28) xor crcreg(29) xor D(0) xor crcreg(31) xor D(2) xor crcreg(7) xor D(3);
next_crc(16) <= crcreg(28) xor D(7) xor crcreg(29) xor D(2) xor crcreg(24) xor D(3) xor crcreg(8);
next_crc(17) <= crcreg(9) xor D(6) xor crcreg(29) xor crcreg(30) xor D(1) xor D(2) xor crcreg(25);
next_crc(18) <= crcreg(26) xor D(5) xor crcreg(10) xor crcreg(30) xor D(0) xor D(1) xor crcreg(31);
next_crc(19) <= D(4) xor crcreg(27) xor crcreg(11) xor D(0) xor crcreg(31);
next_crc(20) <= crcreg(28) xor crcreg(12) xor D(3);
next_crc(21) <= crcreg(29) xor crcreg(13) xor D(2);
next_crc(22) <= D(7) xor crcreg(14) xor crcreg(24);
next_crc(23) <= D(6) xor D(7) xor crcreg(30) xor D(1) xor crcreg(15) xor crcreg(24) xor crcreg(25);
next_crc(24) <= crcreg(26) xor D(5) xor D(6) xor D(0) xor crcreg(31) xor crcreg(16) xor crcreg(25);
next_crc(25) <= D(4) xor crcreg(17) xor crcreg(26) xor D(5) xor crcreg(27);
next_crc(26) <= D(4) xor crcreg(18) xor crcreg(27) xor crcreg(28) xor D(7) xor crcreg(30) xor D(1) xor crcreg(24) xor D(3);
next_crc(27) <= D(6) xor crcreg(19) xor crcreg(28) xor crcreg(29) xor D(0) xor crcreg(31) xor D(2) xor D(3) xor crcreg(25);
next_crc(28) <= crcreg(26) xor D(5) xor crcreg(20) xor crcreg(29) xor crcreg(30) xor D(1) xor D(2);
next_crc(29) <= D(4) xor crcreg(27) xor crcreg(21) xor crcreg(30) xor D(0) xor D(1) xor crcreg(31);
next_crc(30) <= crcreg(28) xor D(0) xor crcreg(22) xor crcreg(31) xor D(3);
next_crc(31) <= crcreg(29) xor crcreg(23) xor D(2);
-- Infer CRC-32 registers
-- The crcreg register stores the CRC-32 value.
-- CRC is the most significant 8 bits of the CRC-32 value.
--
-- Truth Table:
-- -----+---------+----------+----------------------------------------------
-- CALC | D_VALID | crcreg | CRC
-- -----+---------+----------+----------------------------------------------
-- 0 | 0 | crcreg | CRC
-- 0 | 1 | shift | bit-swapped, complimented msbyte of crcreg
-- 1 | 0 | crcreg | CRC
-- 1 | 1 | next_crc | bit-swapped, complimented msbyte of next_crc
process(CLK, RESET)
begin
if RESET = '0' then
crcreg <= x"FFFFFFFF";
CRC <= x"FF";
elsif CLK'event and CLK = '1' then
if INIT = '1' then
crcreg <= x"FFFFFFFF";
CRC <= x"FF";
elsif CALC = '1' and D_VALID = '1' then
crcreg <= next_crc;
CRC <= not(next_crc(24) & next_crc(25) & next_crc(26) & next_crc(27) &
next_crc(28) & next_crc(29) & next_crc(30) & next_crc(31));
elsif CALC = '0' and D_VALID = '1' then
crcreg <= crcreg(23 downto 0) & x"FF";
CRC <= not(crcreg(16) & crcreg(17) & crcreg(18) & crcreg(19) &
crcreg(20) & crcreg(21) & crcreg(22) & crcreg(23));
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | e528b9c02c47033d77e2a0c3bee1d454 | 0.585023 | 2.538402 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_Video_RGB_Resampler.vhd | 1 | 8,495 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module converts video streams between RGB color formats. *
-- * *
-- ******************************************************************************
ENTITY Video_System_Video_RGB_Resampler IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
GENERIC (
IDW :INTEGER := 23;
ODW :INTEGER := 15;
IEW :INTEGER := 1;
OEW :INTEGER := 0;
ALPHA :STD_LOGIC_VECTOR( 9 DOWNTO 0) := B"1111111111"
);
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
stream_in_data :IN STD_LOGIC_VECTOR(IDW DOWNTO 0);
stream_in_startofpacket :IN STD_LOGIC;
stream_in_endofpacket :IN STD_LOGIC;
stream_in_empty :IN STD_LOGIC_VECTOR(IEW DOWNTO 0);
stream_in_valid :IN STD_LOGIC;
stream_out_ready :IN STD_LOGIC;
-- Bidirectional
-- Outputs
stream_in_ready :BUFFER STD_LOGIC;
stream_out_data :BUFFER STD_LOGIC_VECTOR(ODW DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_empty :BUFFER STD_LOGIC_VECTOR(OEW DOWNTO 0);
stream_out_valid :BUFFER STD_LOGIC
);
END Video_System_Video_RGB_Resampler;
ARCHITECTURE Behaviour OF Video_System_Video_RGB_Resampler IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
SIGNAL r :STD_LOGIC_VECTOR( 9 DOWNTO 0);
SIGNAL g :STD_LOGIC_VECTOR( 9 DOWNTO 0);
SIGNAL b :STD_LOGIC_VECTOR( 9 DOWNTO 0);
SIGNAL a :STD_LOGIC_VECTOR( 9 DOWNTO 0);
SIGNAL converted_data :STD_LOGIC_VECTOR(ODW DOWNTO 0);
-- Internal Registers
-- State Machine Registers
-- Integers
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
-- Output Registers
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
stream_out_data <= (OTHERS => '0');
stream_out_startofpacket <= '0';
stream_out_endofpacket <= '0';
stream_out_empty <= (OTHERS => '0');
stream_out_valid <= '0';
ELSIF ((stream_out_ready = '1') OR (stream_out_valid = '0')) THEN
stream_out_data <= converted_data;
stream_out_startofpacket <= stream_in_startofpacket;
stream_out_endofpacket <= stream_in_endofpacket;
-- stream_out_empty <= stream_in_empty;
stream_out_empty <= (OTHERS => '0');
stream_out_valid <= stream_in_valid;
END IF;
END IF;
END PROCESS;
-- Internal Registers
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
-- Output Assignments
stream_in_ready <= stream_out_ready OR NOT stream_out_valid;
-- Internal Assignments
r <= (stream_in_data(23 DOWNTO 16) & stream_in_data(23 DOWNTO 22));
g <= (stream_in_data(15 DOWNTO 8) & stream_in_data(15 DOWNTO 14));
b <= (stream_in_data( 7 DOWNTO 0) & stream_in_data( 7 DOWNTO 6));
a <= ALPHA;
converted_data(15 DOWNTO 11) <= r( 9 DOWNTO 5);
converted_data(10 DOWNTO 5) <= g( 9 DOWNTO 4);
converted_data( 4 DOWNTO 0) <= b( 9 DOWNTO 5);
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
END Behaviour;
| gpl-2.0 | 1f210e279a40725c6d9b003cdc27a18b | 0.430724 | 4.873781 | false | false | false | false |
DreamIP/GPStudio | support/process/dynroi/hdl/dynroi_process.vhd | 1 | 12,657 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity dynroi_process is
generic (
CLK_PROC_FREQ : integer;
BINIMG_SIZE : integer;
IMG_SIZE : integer;
ROI_SIZE : integer;
COORD_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
status_reg_bypass_bit : in std_logic;
status_reg_static_res_bit : in std_logic;
inImg_size_reg_in_w_reg : in std_logic_vector(11 downto 0);
inImg_size_reg_in_h_reg : in std_logic_vector(11 downto 0);
BinImg_size_reg_in_w_reg : in std_logic_vector(11 downto 0);
BinImg_size_reg_in_h_reg : in std_logic_vector(11 downto 0);
out_size_reg_out_w_reg : in std_logic_vector(11 downto 0);
out_size_reg_out_h_reg : in std_logic_vector(11 downto 0);
----------------------- BinImg flow ---------------------
BinImg_data : in std_logic_vector(BINIMG_SIZE-1 downto 0);
BinImg_fv : in std_logic;
BinImg_dv : in std_logic;
------------------------ Img flow -----------------------
Img_data : in std_logic_vector(IMG_SIZE-1 downto 0);
Img_fv : in std_logic;
Img_dv : in std_logic;
------------------------ roi flow -----------------------
roi_data : out std_logic_vector(ROI_SIZE-1 downto 0);
roi_fv : out std_logic;
roi_dv : out std_logic;
----------------------- coord flow ----------------------
coord_data : out std_logic_vector(COORD_SIZE-1 downto 0);
coord_fv : out std_logic;
coord_dv : out std_logic
);
end dynroi_process;
architecture rtl of dynroi_process is
constant X_COUNTER_SIZE : integer := 12;
constant Y_COUNTER_SIZE : integer := 12;
--process data_process vars
--bin image reference coordinates
signal xBin_pos : unsigned(X_COUNTER_SIZE-1 downto 0);
signal yBin_pos : unsigned(Y_COUNTER_SIZE-1 downto 0);
signal x_min : unsigned(X_COUNTER_SIZE-1 downto 0);
signal x_max : unsigned(X_COUNTER_SIZE-1 downto 0);
signal y_min : unsigned(Y_COUNTER_SIZE-1 downto 0);
signal y_max : unsigned(Y_COUNTER_SIZE-1 downto 0);
signal enabled : std_logic;
--conversion offset from binImg to img
signal conv_offset_x : unsigned(X_COUNTER_SIZE-1 downto 0);
signal conv_offset_y : unsigned(Y_COUNTER_SIZE-1 downto 0);
--Coord over serial line related vars
signal frame_buffer : std_logic_vector(63 downto 0);
signal frame_buffer_has_been_filled : std_logic;
signal frame_buffer_has_been_sent : std_logic;
signal frame_buffer_position : unsigned(6 downto 0);
--Apply_roi signals
signal x_temp : unsigned(X_COUNTER_SIZE-1 downto 0);
signal y_temp : unsigned(Y_COUNTER_SIZE-1 downto 0);
signal w_temp : unsigned(X_COUNTER_SIZE-1 downto 0);
signal h_temp : unsigned(Y_COUNTER_SIZE-1 downto 0);
begin
------------------------------------------------------------------------
apply_roi : process(clk_proc, reset_n)
--img reference coordinates
variable x : unsigned(X_COUNTER_SIZE-1 downto 0);
variable y : unsigned(Y_COUNTER_SIZE-1 downto 0);
variable w : unsigned(X_COUNTER_SIZE-1 downto 0);
variable h : unsigned(Y_COUNTER_SIZE-1 downto 0);
variable xImg_pos : unsigned(X_COUNTER_SIZE-1 downto 0);
variable yImg_pos : unsigned(Y_COUNTER_SIZE-1 downto 0);
begin
if(reset_n='0') then
-- reset pixel counters
xImg_pos := to_unsigned(0, X_COUNTER_SIZE);
yImg_pos := to_unsigned(0, Y_COUNTER_SIZE);
-- reset ROI coord : default is central frame with param.w/h values
x := (others => '0');
y := (others => '0');
w := (others => '0');
h := (others => '0');
x_temp <= (others => '0');
y_temp <= (others => '0');
w_temp <= (others => '0');
h_temp <= (others => '0');
roi_data <= (others => '0');
roi_dv <= '0';
roi_fv <= '0';
elsif(rising_edge(clk_proc)) then
if Img_fv = '1' and enabled = '1' then
roi_fv <= '1';
else
roi_fv <= '0';
end if;
roi_dv <= '0';
roi_data <= (others => '1');
--Updating last frame coordinates
if frame_buffer_has_been_filled = '1' and enabled = '1' then
x_temp <= unsigned(frame_buffer(X_COUNTER_SIZE-1 downto 0));
y_temp <= unsigned(frame_buffer(Y_COUNTER_SIZE+15 downto 16));
w_temp <= unsigned(frame_buffer(X_COUNTER_SIZE+31 downto 32));
h_temp <= unsigned(frame_buffer(Y_COUNTER_SIZE+47 downto 48));
end if;
-- ROI action
if Img_fv = '0' then
--Update ROI coords
x := x_temp;
y := y_temp;
w := w_temp;
h := h_temp;
--Reset pixel counters
xImg_pos := to_unsigned(0, X_COUNTER_SIZE);
yImg_pos := to_unsigned(0, Y_COUNTER_SIZE);
else
if Img_dv = '1' and enabled = '1' then
--ROI
if(yBin_pos >= y
and yBin_pos < y + h
and xBin_pos >= x
and xBin_pos < x + w )then
roi_dv <= '1';
roi_data <= Img_data;
end if;
--Pixel counter in img
xImg_pos := xImg_pos + 1;
if(xImg_pos=unsigned(inImg_size_reg_in_w_reg)) then
yImg_pos := yImg_pos + 1;
xImg_pos := to_unsigned(0, X_COUNTER_SIZE);
end if;
end if;
end if;
end if;
end process;
------------------------------------------------------------------------
------------------------------------------------------------------------
data_process : process (clk_proc, reset_n)
-- Vars used to fill frame_buffer
variable x_to_send : unsigned(X_COUNTER_SIZE-1 downto 0);
variable y_to_send : unsigned(Y_COUNTER_SIZE-1 downto 0);
variable w_to_send : unsigned(X_COUNTER_SIZE-1 downto 0);
variable h_to_send : unsigned(Y_COUNTER_SIZE-1 downto 0);
begin
if(reset_n='0') then
xBin_pos <= to_unsigned(0, X_COUNTER_SIZE);
yBin_pos <= to_unsigned(0, Y_COUNTER_SIZE);
--Cleaning frame coordinates
x_max <= (others=>'0');
y_max <= (others=>'0');
x_min <= (others => '0');
y_min <= (others => '0');
--Cleaning frame buffer
frame_buffer <= (others=>'0');
--Cleaning signals used to fill buffer
frame_buffer_has_been_filled <= '0';
frame_buffer_has_been_sent <= '0';
coord_fv <= '0';
coord_dv <= '0';
coord_data <= (others=>'0');
--Cleaning flags
enabled <= '0';
--Cleaning conv offset
conv_offset_x <= (others => '0');
conv_offset_y <= (others => '0');
elsif(rising_edge(clk_proc)) then
coord_fv <= '0';
coord_dv <= '0';
coord_data <= (others=>'0');
--offset calculation
conv_offset_x <= (unsigned(inImg_size_reg_in_w_reg)-unsigned(BinImg_size_reg_in_w_reg))/2;
conv_offset_y <= (unsigned(inImg_size_reg_in_h_reg)-unsigned(BinImg_size_reg_in_h_reg))/2;
if(BinImg_fv = '0') then
xBin_pos <= to_unsigned(0, X_COUNTER_SIZE);
yBin_pos <= to_unsigned(0, Y_COUNTER_SIZE);
--
if frame_buffer_has_been_filled = '0' then
--We send frame coordinates only if there is something to send
if enabled = '1' and frame_buffer_has_been_sent = '0' then
if status_reg_bypass_bit = '1' then
x_to_send := (others=>'0');
y_to_send := (others=>'0');
w_to_send := unsigned(inImg_size_reg_in_w_reg);
h_to_send := unsigned(inImg_size_reg_in_h_reg);
else
----roi resolution fixed by user
if status_reg_static_res_bit = '1' then
--something was detected
if x_max > 0 then
--checking top left corner position to ensure frame width is matching static_res
if x_min + conv_offset_x > (unsigned(inImg_size_reg_in_w_reg)-unsigned(out_size_reg_out_w_reg)) then
x_to_send := unsigned(inImg_size_reg_in_w_reg) - unsigned(out_size_reg_out_w_reg);
else
x_to_send := x_min + conv_offset_x;
end if;
if y_min + conv_offset_y > (unsigned(inImg_size_reg_in_h_reg)-unsigned(out_size_reg_out_h_reg)) then
y_to_send := (unsigned(inImg_size_reg_in_h_reg)-unsigned(out_size_reg_out_h_reg));
else
y_to_send := y_min + conv_offset_y;
end if;
w_to_send := unsigned(out_size_reg_out_w_reg) ;
h_to_send := unsigned(out_size_reg_out_h_reg);
else
--nothing found
x_to_send := (unsigned(inImg_size_reg_in_w_reg)-unsigned(out_size_reg_out_w_reg))/2 ;
y_to_send := (unsigned(inImg_size_reg_in_h_reg)-unsigned(out_size_reg_out_h_reg))/2;
w_to_send := unsigned(out_size_reg_out_w_reg);
h_to_send := unsigned(out_size_reg_out_h_reg);
end if;
----dynamic resolution for roi
else
--something was detected
if x_max > 0 then
x_to_send := x_min + conv_offset_x;
y_to_send := y_min + conv_offset_y;
w_to_send := x_max-x_min;
h_to_send := y_max-y_min;
else
--nothing found -> empty rectangle at image center
x_to_send := unsigned(inImg_size_reg_in_w_reg)/2;
y_to_send := unsigned(inImg_size_reg_in_h_reg)/2;
w_to_send := (others=>'0');
h_to_send := (others=>'0');
end if;
end if;
end if;
--filling buffer with matching coordinates
frame_buffer(X_COUNTER_SIZE-1 downto 0) <= std_logic_vector(x_to_send);
frame_buffer(Y_COUNTER_SIZE+15 downto 16) <= std_logic_vector(y_to_send);
frame_buffer(X_COUNTER_SIZE+31 downto 32) <= std_logic_vector(w_to_send);
frame_buffer(Y_COUNTER_SIZE+47 downto 48) <= std_logic_vector(h_to_send);
--zero padding, each value has 16 bits but only uses XY_COUNTER_SIZE bits
frame_buffer(15 downto X_COUNTER_SIZE) <= (others=>'0');
frame_buffer(31 downto X_COUNTER_SIZE+16) <= (others=>'0');
frame_buffer(47 downto X_COUNTER_SIZE+32) <= (others=>'0');
frame_buffer(63 downto X_COUNTER_SIZE+48) <= (others=>'0');
-- Get buffer ready to send
frame_buffer_has_been_filled <= '1';
frame_buffer_position <= (others=>'0') ;
end if;
--Cleaning frame coordinates
x_max <= (others=>'0');
y_max <= (others=>'0');
x_min <= unsigned(BinImg_size_reg_in_w_reg);
y_min <= unsigned(BinImg_size_reg_in_h_reg);
--To prevent sending coord after reset of x/y_min/max
frame_buffer_has_been_sent <= '1';
else
--send roi coord
coord_fv <= '1';
coord_dv <= '1';
coord_data <= frame_buffer(to_integer(frame_buffer_position)+7 downto to_integer(frame_buffer_position));
if frame_buffer_position >= 56 then
frame_buffer_has_been_filled <= '0';
frame_buffer_has_been_sent <= '1';
else
frame_buffer_position <= frame_buffer_position + to_unsigned(8, 7);
end if;
end if;
enabled <= status_reg_enable_bit;
else
coord_fv <= '0';
coord_dv <= '0';
coord_data <= (others=>'0');
frame_buffer_has_been_sent <= '0';
if status_reg_enable_bit = '1' and enabled = '1' then
if(BinImg_dv = '1' ) then
--bin img pixel counter
xBin_pos <= xBin_pos + 1;
if(xBin_pos=unsigned(BinImg_size_reg_in_w_reg)-1) then
yBin_pos <= yBin_pos + 1;
xBin_pos <= to_unsigned(0, X_COUNTER_SIZE);
end if;
-- This will give the smallest area including all non-black points
if BinImg_data /= (BinImg_data'range => '0') then
if xBin_pos < x_min then
x_min <= xBin_pos;
end if;
if xBin_pos > x_max then
x_max <= xBin_pos;
end if;
--
if yBin_pos < y_min then
y_min <= yBin_pos;
end if;
if yBin_pos > y_max then
y_max <= yBin_pos;
end if;
end if;
end if;
else
enabled <= '0';
end if;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | 6ea75f2c404ab90ebf1603ae21ce2d2d | 0.530299 | 3.110592 | false | false | false | false |
DreamIP/GPStudio | support/process/dynthreshold/hdl/dynthreshold_process.vhd | 1 | 4,448 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity dynthreshold_process is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
desired_ratio_reg : in std_logic_vector(31 downto 0);
border_research_type_reg : in std_logic_vector(31 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end dynthreshold_process;
architecture rtl of dynthreshold_process is
signal enabled : std_logic;
-- Desired ratio of white pixels in percent
signal current_desired_ratio : unsigned(31 downto 0);
-- Ratio triggering the switch between a dichotomic research and an iterative one
signal current_border_research_type : unsigned(31 downto 0);
--Threshold borders
signal lower_border_threshold : unsigned(IN_SIZE-1 downto 0):=(others=>'0');
signal upper_border_threshold : unsigned(IN_SIZE-1 downto 0):=(others=>'1');
begin
data_process : process (clk_proc, reset_n)
variable white_px_counter : integer; --unsigned(31 downto 0);
variable img_px_counter : integer; --unsigned(31 downto 0);
variable current_ratio : unsigned(31 downto 0);
variable old_ratio : unsigned(31 downto 0);
variable current_threshold : unsigned(IN_SIZE-1 downto 0);
variable old_threshold : unsigned(IN_SIZE-1 downto 0);
begin
if(reset_n='0') then
enabled <= '0';
out_data <= (others => '0');
out_dv <= '0';
out_fv <= '0';
current_threshold := (others => '0');
elsif(rising_edge(clk_proc)) then
-- Waiting for an image flow
if(in_fv = '0') then
-- Update params here, between two images processing
-- Updating threshold
if(img_px_counter /= 0 and enabled = '1') then
current_ratio :=to_unsigned(white_px_counter*100/img_px_counter,32);
-- Updating threshold with dichotomic search
if(unsigned(abs(signed(current_desired_ratio)-signed(current_ratio))) > current_border_research_type)then
if(current_ratio > current_desired_ratio) then
current_threshold := current_threshold+(upper_border_threshold-current_threshold)/2;
elsif current_ratio < current_desired_ratio then
current_threshold := lower_border_threshold + current_threshold/2;
end if;
else
-- To avoid a bouncing effect near the target, final updates are iteratives
if(current_ratio > current_desired_ratio) then
-- Too many white pixels spotted, increasing threshold value
if(current_threshold < upper_border_threshold) then
current_threshold := current_threshold + 1;
end if;
elsif current_ratio < current_desired_ratio then
-- Not enough white pixels, lowering threshold value
if(current_threshold > lower_border_threshold) then
current_threshold := current_threshold - 1;
end if;
end if;
end if;
old_ratio := current_ratio;
old_threshold := current_threshold;
end if;
-- Updating commanded ratio
current_desired_ratio <= unsigned(desired_ratio_reg);
-- Updating research type border
current_border_research_type <= unsigned(border_research_type_reg);
-- Reset pixel counter
img_px_counter := 0;
white_px_counter := 0;
enabled <= status_reg_enable_bit;
end if;
if(enabled = '1') then
if(in_dv='1' and in_fv='1') then
-- Binarisation process
if(unsigned(in_data) <= current_threshold) then
out_data <= (others => '0');
else
out_data <= (others => '1');
white_px_counter := white_px_counter + 1;
end if;
img_px_counter := img_px_counter + 1;
end if;
else
out_data <= in_data;
end if;
out_dv <= in_dv;
out_fv <= in_fv;
end if;
end process;
end rtl;
| gpl-3.0 | db95845307b97ea778248fc5383246ff | 0.599146 | 3.544223 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/master_handler.vhd | 3 | 16,749 | -------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity master_handler is
generic(
dma_highadr_g : integer := 31;
gen_tx_fifo_g : boolean := true;
tx_fifo_word_size_log2_g : natural := 5;
gen_rx_fifo_g : boolean := true;
rx_fifo_word_size_log2_g : natural := 5;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_burst_wr_const_g : boolean := true;
fifo_data_width_g : integer := 16
);
port(
m_clk : in std_logic;
rst : in std_logic;
mac_tx_off : in std_logic;
mac_rx_off : in std_logic;
tx_wr_clk : in std_logic;
tx_wr_empty : in std_logic;
tx_wr_full : in std_logic;
rx_rd_clk : in std_logic;
rx_rd_empty : in std_logic;
rx_rd_full : in std_logic;
tx_wr_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
rx_rd_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_aclr : out std_logic;
tx_wr_req : out std_logic;
rx_rd_req : out std_logic;
m_waitrequest : in std_logic;
m_readdatavalid : in std_logic;
m_write : out std_logic;
m_read : out std_logic;
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
dma_addr_in : in std_logic_vector(dma_highadr_g downto 1);
dma_len_rd : in std_logic_vector(11 downto 0);
dma_new_addr_wr : in std_logic;
dma_new_addr_rd : in std_logic;
dma_new_len_rd : in std_logic
);
end master_handler;
architecture master_handler of master_handler is
--clock signal
signal clk : std_logic;
--constants
constant tx_burst_size_c : integer := m_tx_burst_size_g; --(2**(m_burstcount_width_g-1));
constant rx_burst_size_c : integer := m_rx_burst_size_g; --(2**(m_burstcount_width_g-1));
---used to trigger rx/tx data transfers depending on fill level and burst size
constant tx_fifo_limit_c : integer := 2**tx_fifo_word_size_log2_g - tx_burst_size_c - 1; --fifo_size - burst size - 1
constant rx_fifo_limit_c : integer := rx_burst_size_c + 1; --burst size
--fsm
type transfer_t is (idle, run, finish);
signal tx_fsm, tx_fsm_next, rx_fsm, rx_fsm_next : transfer_t := idle;
--transfer signals
signal m_burstcount_s, m_burstcount_latch : std_logic_vector(m_burstcount'range);
signal m_address_latch : std_logic_vector(m_address'range);
signal m_write_s, m_read_s : std_logic;
signal rx_first_read_done, rx_rd_done : std_logic;
--fifo signals
signal arst : std_logic;
signal tx_fifo_limit, rx_fifo_limit : std_logic;
signal tx_wr_req_s, rx_rd_req_s, rx_first_rd_req : std_logic;
--generate addresses
signal tx_cnt, tx_cnt_next : std_logic_vector(m_address'range);
signal rx_cnt, rx_cnt_next : std_logic_vector(m_address'range);
--handle tx read transfer
signal tx_rd_cnt, tx_rd_cnt_next : std_logic_vector(dma_len_rd'range);
signal dma_len_rd_s : std_logic_vector(dma_len_rd'range);
begin
--m_clk, rx_rd_clk and tx_wr_clk are the same!
clk <= m_clk; --to ease typing
tx_aclr <= rst or arst;
--fifo limit is set to '1' if the fill level is equal/above the limit
tx_fifo_limit <= '1' when tx_wr_usedw >= conv_std_logic_vector(tx_fifo_limit_c, tx_wr_usedw'length) else '0';
rx_fifo_limit <= '1' when rx_rd_usedw >= conv_std_logic_vector(rx_fifo_limit_c, rx_rd_usedw'length) else '0';
process(clk, rst)
begin
if rst = '1' then
if gen_rx_fifo_g then
rx_fsm <= idle;
end if;
if gen_tx_fifo_g then
tx_fsm <= idle;
end if;
elsif clk = '1' and clk'event then
if gen_rx_fifo_g then
rx_fsm <= rx_fsm_next;
end if;
if gen_tx_fifo_g then
tx_fsm <= tx_fsm_next;
end if;
end if;
end process;
tx_fsm_next <= run when tx_fsm = idle and dma_new_addr_rd = '1' else
finish when tx_fsm = run and mac_tx_off = '1' else
idle when tx_fsm = finish and tx_wr_empty = '1' else --stay finish as long as tx fifo is filled
tx_fsm;
rx_fsm_next <= run when rx_fsm = idle and dma_new_addr_wr = '1' else
finish when rx_fsm = run and mac_rx_off = '1' else
idle when rx_fsm = finish and rx_rd_done = '1' else --stay finish as long the transfer process is not done
rx_fsm;
m_burstcount <= m_burstcount_latch when m_write_s = '1' and m_burst_wr_const_g else m_burstcount_s;
m_burstcounter <= m_burstcount_s; --output current burst counter value
m_write <= m_write_s;
m_read <= m_read_s;
--generate address
m_address <= m_address_latch when m_write_s = '1' and m_burst_wr_const_g else
rx_cnt when m_write_s = '1' and not m_burst_wr_const_g else
tx_cnt;
process(clk, rst)
begin
if rst = '1' then
if gen_tx_fifo_g then
tx_cnt <= (others => '0');
tx_rd_cnt <= (others => '0');
end if;
if gen_rx_fifo_g then
rx_cnt <= (others => '0');
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
tx_cnt <= tx_cnt_next;
tx_rd_cnt <= tx_rd_cnt_next;
end if;
if gen_rx_fifo_g then
rx_cnt <= rx_cnt_next;
end if;
end if;
end process;
dma_len_rd_s <= dma_len_rd + 1 when fifo_data_width_g = 16 else
dma_len_rd + 3 when fifo_data_width_g = 32 else
dma_len_rd;
tx_rd_cnt_next <= (others => '0') when gen_tx_fifo_g = false else
'0' & dma_len_rd_s(dma_len_rd_s'left downto 1) when dma_new_len_rd = '1' and fifo_data_width_g = 16 else
"00" & dma_len_rd_s(dma_len_rd_s'left downto 2) when dma_new_len_rd = '1' and fifo_data_width_g = 32 else
tx_rd_cnt - 1 when tx_wr_req_s = '1' and tx_rd_cnt /= 0 else
tx_rd_cnt;
tx_cnt_next <= (others => '0') when gen_tx_fifo_g = false else
tx_cnt + fifo_data_width_g/8 when tx_wr_req_s = '1' else
dma_addr_in & '0' when dma_new_addr_rd = '1' else
tx_cnt;
rx_cnt_next <= (others => '0') when gen_rx_fifo_g = false else
rx_cnt + fifo_data_width_g/8 when rx_rd_req_s = '1' else
dma_addr_in & '0' when dma_new_addr_wr = '1' else
rx_cnt;
m_byteenable <= (others => '1');
tx_wr_req_s <= m_readdatavalid;
tx_wr_req <= tx_wr_req_s;
rx_rd_req_s <= m_write_s and not m_waitrequest;
rx_rd_req <= rx_rd_req_s or rx_first_rd_req;
process(clk, rst)
--arbitration of rx and tx requests is done by process variable (tx overrules rx)
variable tx_is_the_owner_v : std_logic;
begin
if rst = '1' then
tx_is_the_owner_v := '0';
if gen_tx_fifo_g then
arst <= '0';
m_read_s <= '0';
end if;
if gen_rx_fifo_g then
rx_first_rd_req <= '0';
m_write_s <= '0';
rx_first_read_done <= '0';
rx_rd_done <= '0';
end if;
m_burstcount_s <= (others => '0');
if m_burst_wr_const_g then
m_burstcount_latch <= (others => '0');
m_address_latch <= (others => '0');
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
arst <= '0';
if m_readdatavalid = '1' then
--read was successful -> write to tx fifo
m_burstcount_s <= m_burstcount_s - 1;
end if;
case tx_fsm is
when idle =>
--no transfer in progress
when run =>
--read transfer base address is ready
if tx_fifo_limit = '0' and m_read_s = '0' and m_write_s = '0' and m_burstcount_s = 0 and tx_rd_cnt /= 0 then
--tx fifo is below defined limit -> there is place for at least one burst!
m_read_s <= '1';
if tx_rd_cnt > conv_std_logic_vector(tx_burst_size_c, tx_rd_cnt'length) then
m_burstcount_s <= conv_std_logic_vector(tx_burst_size_c, m_burstcount_s'length);
else
m_burstcount_s <= EXT(tx_rd_cnt, m_burstcount_s'length);
end if;
--a tx transfer is necessary and overrules necessary rx transfers...
tx_is_the_owner_v := '1';
elsif m_read_s = '1' and m_waitrequest = '0' then
--request is confirmed -> deassert request
m_read_s <= '0';
--so, we are done with tx requesting
tx_is_the_owner_v := '0';
end if;
when finish =>
--transfer done, MAC has its data...
---is there still a request?
if m_read_s = '1' and m_waitrequest = '0' then
--last request confirmed -> deassert request
m_read_s <= '0'; tx_is_the_owner_v := '0';
---is the burst transfer done?
elsif m_read_s = '0' and m_burstcount_s = 0 then
--burst transfer done, clear fifo
arst <= '1';
end if;
end case;
end if;
if gen_rx_fifo_g then
rx_first_rd_req <= '0';
rx_rd_done <= '0';
if m_write_s = '1' and m_waitrequest = '0' then
--write was successful
m_burstcount_s <= m_burstcount_s - 1;
end if;
case rx_fsm is
when idle =>
--no transfer in progress
rx_first_read_done <= '0';
when run =>
--a not empty fifo has to be read once, to get the very first pattern
if rx_first_read_done = '0' and rx_rd_empty = '0' then
rx_first_read_done <= '1';
rx_first_rd_req <= '1';
end if;
--write transfer base address is ready
if rx_fifo_limit = '1' and m_read_s = '0' and m_write_s = '0' and tx_is_the_owner_v = '0' and m_burstcount_s = 0 and rx_first_read_done = '1' then
--rx fifo is filled with enough data -> build burst transfer
m_write_s <= '1';
m_burstcount_s <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
elsif m_write_s = '1' and m_waitrequest = '0' and m_burstcount_s = 1 then
--last transfer is done -> deassert write qualifiers
m_write_s <= '0';
end if;
when finish =>
--MAC is finished with RX, transfer rest of fifo
---note: The last word (part of crc32) is not transferred!
if rx_rd_empty = '0' and m_read_s = '0' and m_write_s = '0' and tx_is_the_owner_v = '0' and m_burstcount_s = 0 then
--rx fifo has some data left
m_write_s <= '1';
--verify how many patterns are left in the fifo
if rx_rd_usedw < conv_std_logic_vector(rx_burst_size_c, rx_rd_usedw'length) then
--start the smaller burst write transfer
m_burstcount_s <= EXT(rx_rd_usedw, m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= EXT(rx_rd_usedw, m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
--workaround: fifo is not empty but word level is zero => set to one
if rx_rd_usedw = 0 then
m_burstcount_s <= conv_std_logic_vector(1, m_burstcount_s'length);
m_burstcount_latch <= conv_std_logic_vector(1, m_burstcount_latch'length);
end if;
else
--start the maximum burst write transfer
m_burstcount_s <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
end if;
elsif m_write_s = '1' and m_waitrequest = '0' and m_burstcount_s = 1 then
--transfer is done -> deassert write qualifiers
m_write_s <= '0';
--completely done?!
if rx_rd_empty = '1' then
--yes!
rx_rd_done <= '1';
end if;
elsif rx_rd_empty = '1' and m_write_s = '0' then
--nothing left in the fifo and we don't try to do anything -> done!
rx_rd_done <= '1';
end if;
end case;
end if;
end if;
end process;
end master_handler;
| gpl-2.0 | eac2ba83b8355dc9eb9cc2c24098fbcb | 0.499851 | 3.809188 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/altera/latch/src/dataLatch-syn-a.vhd | 3 | 3,112 | --! @file dataLatch-syn-a.vhd
--! @brief Data latch generated architecture
-------------------------------------------------------------------------------
-- Architecture : syn
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--! Use standard ieee library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Use libcommon library
library libcommon;
--! Use global package
use libcommon.global.all;
--! Use altera library
library altera;
--! Use primitive components
use altera.altera_primitives_components.dlatch;
--! @brief Altera data latch architecture
--! @details This architecture uses an Altera primitive component for the data
--! latch implementation.
architecture syn of dataLatch is
--! Low active clear
signal nClear : std_logic;
--! Low active preset
signal nPreset : std_logic;
begin
-- Generate low active signals
nClear <= not iClear;
nPreset <= cnInactivated; --unused preset
GEN_LATCH : for i in gDataWidth-1 downto 0 generate
INST_LATCH : dlatch
port map (
d => iData(i),
ena => iEnable,
clrn => nClear,
prn => nPreset,
q => oData(i)
);
end generate GEN_LATCH;
end architecture syn;
| gpl-2.0 | cc8d4b642b7d9452e7a16da063a2948e | 0.632391 | 4.817337 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/numeric/counter.vhdl | 1 | 1,369 | --
-- Counter
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library FPGALIB;
use FPGALIB.numeric.all;
entity Counter is
generic (
DEPTH : positive:=8
);
port (
clk_i : in std_logic; -- Clock
rst_i : in std_logic; -- Reset
ena_i : in std_logic; -- Input Enable
count_o : out std_logic_vector(clog2(DEPTH)-1 downto 0); -- Counter value
last_o : out std_logic -- Last value
);
end entity Counter;
architecture RTL of Counter is
constant AWIDTH : positive:=clog2(DEPTH);
signal count : unsigned(AWIDTH-1 downto 0):=(others => '0');
begin
count_p:
process (clk_i)
begin
if rising_edge(clk_i) then
last_o <= '0';
if rst_i='1' then
count <= (others => '0');
else
if ena_i='1' then
if count < DEPTH-1 then
count <= count + 1;
if count = DEPTH-2 then
last_o <= '1';
end if;
else
count <= (others => '0');
end if;
end if;
end if;
end if;
end process count_p;
count_o <= std_logic_vector(count);
end architecture RTL;
| bsd-3-clause | 8f882d12cd3130677158ab24bddb1205 | 0.521549 | 3.612137 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/verif/loopcheck.vhdl | 1 | 2,636 | --
-- LoopCheck
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016-2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity LoopCheck is
generic (
DWIDTH : positive:=8 -- Data width
);
port (
-- TX side
tx_clk_i : in std_logic;
tx_rst_i : in std_logic;
tx_stb_i : in std_logic;
tx_data_i : in std_logic_vector(DWIDTH-1 downto 0);
tx_data_o : out std_logic_vector(DWIDTH-1 downto 0);
-- RX side
rx_clk_i : in std_logic;
rx_rst_i : in std_logic;
rx_stb_i : in std_logic;
rx_data_i : in std_logic_vector(DWIDTH-1 downto 0);
rx_errors_o : out std_logic_vector(4 downto 0)
);
end entity LoopCheck;
architecture RTL of LoopCheck is
constant NOT_RECEIVED : natural:=0;
constant VAL_MISSMATCH : natural:=1;
constant QTY_MISSMATCH : natural:=2;
constant QTY_LESS : natural:=3;
constant QTY_MORE : natural:=4;
signal tx_qty, rx_qty : unsigned(DWIDTH downto 0);
signal errors : std_logic_vector(4 downto 0);
begin
tx_side: process(tx_clk_i)
begin
if rising_edge(tx_clk_i) then
if tx_rst_i='1' then
tx_data_o <= tx_data_i;
tx_qty <= '0' & unsigned(tx_data_i);
elsif tx_stb_i='1' then
tx_data_o <= std_logic_vector(tx_qty(DWIDTH-1 downto 0) + 1);
tx_qty <= tx_qty + 1;
end if;
end if;
end process;
rx_side: process(rx_clk_i)
begin
if rising_edge(rx_clk_i) then
if rx_rst_i='1' then
rx_qty <= '0' & unsigned(tx_data_i);
errors <= "00001";
elsif rx_stb_i='1' then
errors(NOT_RECEIVED) <= '0';
if rx_data_i /= std_logic_vector(rx_qty(DWIDTH-1 downto 0)) then
errors(VAL_MISSMATCH) <= '1';
end if;
if tx_qty=rx_qty+1 then
errors(QTY_MISSMATCH) <= '0';
errors(QTY_LESS) <= '0';
errors(QTY_MORE) <= '0';
elsif tx_qty>rx_qty+1 then
errors(QTY_MISSMATCH) <= '1';
errors(QTY_LESS) <= '1';
errors(QTY_MORE) <= '0';
else -- tx_qty<rx_qty+1
errors(QTY_MISSMATCH) <= '1';
errors(QTY_LESS) <= '0';
errors(QTY_MORE) <= '1';
end if;
rx_qty <= rx_qty + 1;
end if;
end if;
end process;
rx_errors_o <= errors;
end architecture RTL;
| bsd-3-clause | 29b85ed03522cecd8cc0e693d969b82e | 0.510243 | 3.175904 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/altera_avalon_reset_source.vhd | 1 | 1,708 | -- (C) 2001-2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
entity altera_avalon_reset_source is
generic ( ASSERT_HIGH_RESET : integer := 1;
INITIAL_RESET_CYCLES : integer := 0
);
port ( clk : in std_logic;
reset : out std_logic
);
end altera_avalon_reset_source;
architecture behavioral of altera_avalon_reset_source is
signal reset_active : std_logic := '1';
signal clk_counter : integer := INITIAL_RESET_CYCLES;
begin
reset <= reset_active when (ASSERT_HIGH_RESET = 1) else not reset_active;
initial_reset: process (clk, clk_counter) -- initial reset process
begin
if (clk_counter = 0) then
reset_active <= '0';
end if;
if rising_edge (clk) then
clk_counter <= clk_counter - 1;
end if;
end process initial_reset;
end behavioral;
| gpl-2.0 | 1af411d81dadf558d20bbc35f9179839 | 0.671546 | 4.335025 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/simul/clock.vhdl | 1 | 1,253 | --
-- Clock
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2015-2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
entity Clock is
generic(
FREQUENCY : positive:=25e6; -- Hz
PERIOD : time:=0 sec; -- Used insted of FREQUENCY when greater than 0 sec
RESET_CLKS : real:=1.5 -- Reset duration expresed in clocks
);
port(
clk_o : out std_logic;
rst_o : out std_logic;
stop_i : in boolean:=FALSE -- Stop clock generation
);
end entity Clock;
architecture Simulator of Clock is
function get_clock_time(per: time; freq: positive) return time is
begin
if per > 0 sec then
return per;
end if;
return 1 sec/(real(FREQUENCY));
end function get_clock_time;
signal clk : std_logic:='1';
constant CLOCK_TIME: time:=get_clock_time(PERIOD,FREQUENCY);
constant RESET_TIME: time:=CLOCK_TIME*RESET_CLKS;
begin
do_clock: process
begin
while not stop_i loop
wait for CLOCK_time/2;
clk <= not clk;
end loop;
wait;
end process do_clock;
clk_o <= clk;
rst_o <= '1', '0' after RESET_TIME;
end architecture Simulator; -- Entity: Clock
| bsd-3-clause | d00be38544900d09f641b5c0814969bf | 0.616919 | 3.509804 | false | false | false | false |
rtucker/nios_codebreaker | vhdl/codebreaker_top.vhd | 1 | 4,246 | --*****************************************************************************
--*************************** VHDL Source Code ******************************
--*****************************************************************************
-- vim: set ts=2 sw=2 tw=78 et :
--
-- DESIGNER NAME: Ryan Tucker <[email protected]>
--
-- LAB NAME: Lab 7: Game System
--
-- FILE NAME: codebreaker_top.vhd
--
-------------------------------------------------------------------------------
-- Description:
-- This module is the top level module for the CodeBreaker game system
--
--*****************************************************************************
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
-------------------------------------------------------------------------------
-- Port Declarations --
-------------------------------------------------------------------------------
entity codebreaker_top is
port (
-- Inputs
CLOCK_50 : in std_logic;
KEY : in std_logic_vector (3 downto 0);
-- Outputs
LEDG : out std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(17 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX1 : out std_logic_vector(6 downto 0);
HEX0 : out std_logic_vector(6 downto 0)
);
end codebreaker_top;
architecture structure of codebreaker_top is
component nios_system
port (
clk_clk : in std_logic;
reset_reset_n : in std_logic;
pio_keys_export : in std_logic_vector(1 downto 0);
--
led_toggle_pulse_export : out std_logic;
pio_countdown_export : out std_logic_vector(7 downto 0);
pio_leds_export : out std_logic_vector(1 downto 0)
);
end component nios_system;
signal led_toggle_pulse : std_logic;
signal led_gate : std_logic := '0';
signal leds : std_logic_vector(1 downto 0);
signal countdown : std_logic_vector(7 downto 0);
begin
NiosII : nios_system
port map(
clk_clk => clock_50,
reset_reset_n => key(0),
pio_keys_export => key(2 downto 1),
--
led_toggle_pulse_export => led_toggle_pulse,
pio_countdown_export => countdown,
pio_leds_export => leds
);
-- process: led_gate_p
-- updates the LED toggle gate signal on led toggle timers
led_gate_p : process (clock_50, key(0)) is
begin
if (key(0) = '0') then
led_gate <= '0';
elsif (rising_edge(clock_50)) then
if (led_toggle_pulse = '1') then
led_gate <= not led_gate;
end if;
end if;
end process led_gate_p;
-- combinational logic for controlling the LEDs
ledr <= (others => '1') when (leds(0) = '1' and led_gate = '1') -- LOSER
else (others => '0');
ledg <= (others => '1') when (leds(1) = '1' and led_gate = '1') -- WINNER
else (others => '0');
-- force unused 7-seg displays off
hex7 <= (others => '1');
hex6 <= (others => '1');
hex5 <= (others => '1');
hex4 <= (others => '1');
hex3 <= (others => '1');
hex2 <= (others => '1');
ssd_tens: entity work.seven_segment port map (
digit => "0" & countdown(6 downto 4),
enable => countdown(7),
bank => '0',
sevenseg => hex1
);
ssd_ones: entity work.seven_segment port map (
digit => countdown(3 downto 0),
enable => countdown(7),
bank => '0',
sevenseg => hex0
);
end structure;
| mit | a52cc13cf69693d33f566df1c1636e78 | 0.431465 | 4.110358 | false | false | false | false |
hoglet67/ElectronFpga | src/common/T6502/T65.vhd | 3 | 24,501 | -- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 313 WoS January 2015
-- Fixed issue that NMI has to be first if issued the same time as a BRK instruction is latched in
-- Now all Lorenz CPU tests on FPGAARCADE C64 core (sources used: SVN version 1021) are OK! :D :D :D
-- This is just a starting point to go for optimizations and detailed fixes (the Lorenz test can't find)
--
-- Ver 312 WoS January 2015
-- Undoc opcode timing fixes for $B3 (LAX iy) and $BB (LAS ay)
-- Added comments in MCode section to find handling of individual opcodes more easily
-- All "basic" Lorenz instruction test (individual functional checks, CPUTIMING check) work now with
-- actual FPGAARCADE C64 core (sources used: SVN version 1021).
--
-- Ver 305, 306, 307, 308, 309, 310, 311 WoS January 2015
-- Undoc opcode fixes (now all Lorenz test on instruction functionality working, except timing issues on $B3 and $BB):
-- SAX opcode
-- SHA opcode
-- SHX opcode
-- SHY opcode
-- SHS opcode
-- LAS opcode
-- alternate SBC opcode
-- fixed NOP with immediate param (caused Lorenz trap test to fail)
-- IRQ and NMI timing fixes (in conjuction with branches)
--
-- Ver 304 WoS December 2014
-- Undoc opcode fixes:
-- ARR opcode
-- ANE/XAA opcode
-- Corrected issue with NMI/IRQ prio (when asserted the same time)
--
-- Ver 303 ost(ML) July 2014
-- (Sorry for some scratchpad comments that may make little sense)
-- Mods and some 6502 undocumented instructions.
-- Not correct opcodes acc. to Lorenz tests (incomplete list):
-- NOPN (nop)
-- NOPZX (nop + byte 172)
-- NOPAX (nop + word da ... da: byte 0)
-- ASOZ (byte $07 + byte 172)
--
-- Ver 303,302 WoS April 2014
-- Bugfixes for NMI from foft
-- Bugfix for BRK command (and its special flag)
--
-- Ver 300,301 WoS January 2014
-- More merging
-- Bugfixes by ehenciak added, started tidyup *bust*
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
-- ****
--
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65.vhd 1347 2015-05-27 20:07:34Z wolfgang.scherr $
--
-- Copyright (c) 2002...2015
-- Daniel Wallner (jesus <at> opencores <dot> org)
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
-- Morten Leikvoll ()
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author(s), but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- ----- IMPORTANT NOTES -----
--
-- Limitations:
-- 65C02 and 65C816 modes are incomplete (and definitely untested after all 6502 undoc fixes)
-- 65C02 supported : inc, dec, phx, plx, phy, ply
-- 65D02 missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8
-- Some interface signals behave incorrect
-- NMI interrupt handling not nice, needs further rework (to cycle-based encoding).
--
-- Usage:
-- The enable signal allows clock gating / throttling without using the ready signal.
-- Set it to constant '1' when using the Clk input as the CPU clock directly.
--
-- TAKE CARE you route the DO signal back to the DI signal while R_W_n='0',
-- otherwise some undocumented opcodes won't work correctly.
-- EXAMPLE:
-- CPU : entity work.T65
-- port map (
-- R_W_n => cpu_rwn_s,
-- [....all other ports....]
-- DI => cpu_din_s,
-- DO => cpu_dout_s
-- );
-- cpu_din_s <= cpu_dout_s when cpu_rwn_s='0' else
-- [....other sources from peripherals and memories...]
--
-- ----- IMPORTANT NOTES -----
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
entity T65 is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Res_n : in std_logic;
Enable : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
MF : out std_logic;
XF : out std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
VDA : out std_logic;
VPA : out std_logic;
A : out std_logic_vector(23 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
-- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB)
Regs : out std_logic_vector(63 downto 0);
DEBUG : out T_t65_dbg
);
end T65;
architecture rtl of T65 is
-- Registers
signal ABC, X, Y : std_logic_vector(15 downto 0);
signal P, AD, DL : std_logic_vector(7 downto 0) := x"00";
signal PwithB : std_logic_vector(7 downto 0);--ML:New way to push P with correct B state to stack
signal BAH : std_logic_vector(7 downto 0);
signal BAL : std_logic_vector(8 downto 0);
signal PBR : std_logic_vector(7 downto 0);
signal DBR : std_logic_vector(7 downto 0);
signal PC : unsigned(15 downto 0);
signal S : unsigned(15 downto 0);
signal EF_i : std_logic;
signal MF_i : std_logic;
signal XF_i : std_logic;
signal IR : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal Mode_r : std_logic_vector(1 downto 0);
signal ALU_Op_r : T_ALU_Op;
signal Write_Data_r : T_Write_Data;
signal Set_Addr_To_r : T_Set_Addr_To;
signal PCAdder : unsigned(8 downto 0);
signal RstCycle : std_logic;
signal IRQCycle : std_logic;
signal NMICycle : std_logic;
signal SO_n_o : std_logic;
signal IRQ_n_o : std_logic;
signal NMI_n_o : std_logic;
signal NMIAct : std_logic;
signal Break : std_logic;
-- ALU signals
signal BusA : std_logic_vector(7 downto 0);
signal BusA_r : std_logic_vector(7 downto 0);
signal BusB : std_logic_vector(7 downto 0);
signal BusB_r : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal P_Out : std_logic_vector(7 downto 0);
-- Micro code outputs
signal LCycle : std_logic_vector(2 downto 0);
signal ALU_Op : T_ALU_Op;
signal Set_BusA_To : T_Set_BusA_To;
signal Set_Addr_To : T_Set_Addr_To;
signal Write_Data : T_Write_Data;
signal Jump : std_logic_vector(1 downto 0);
signal BAAdd : std_logic_vector(1 downto 0);
signal BreakAtNA : std_logic;
signal ADAdd : std_logic;
signal AddY : std_logic;
signal PCAdd : std_logic;
signal Inc_S : std_logic;
signal Dec_S : std_logic;
signal LDA : std_logic;
signal LDP : std_logic;
signal LDX : std_logic;
signal LDY : std_logic;
signal LDS : std_logic;
signal LDDI : std_logic;
signal LDALU : std_logic;
signal LDAD : std_logic;
signal LDBAL : std_logic;
signal LDBAH : std_logic;
signal SaveP : std_logic;
signal Write : std_logic;
signal Res_n_i : std_logic;
signal Res_n_d : std_logic;
signal really_rdy : std_logic;
signal WRn_i : std_logic;
signal NMI_entered : std_logic;
begin
-- gate Rdy with read/write to make an "OK, it's really OK to stop the processor
really_rdy <= Rdy or not(WRn_i);
Sync <= '1' when MCycle = "000" else '0';
EF <= EF_i;
MF <= MF_i;
XF <= XF_i;
R_W_n <= WRn_i;
ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
VDA <= '1' when Set_Addr_To_r /= Set_Addr_To_PBR else '0';
VPA <= '1' when Jump(1) = '0' else '0';
-- debugging signals
DEBUG.I <= IR;
DEBUG.A <= ABC(7 downto 0);
DEBUG.X <= X(7 downto 0);
DEBUG.Y <= Y(7 downto 0);
DEBUG.S <= std_logic_vector(S(7 downto 0));
DEBUG.P <= P;
Regs <= std_logic_vector(PC) & std_logic_vector(S)& P & Y(7 downto 0) & X(7 downto 0) & ABC(7 downto 0);
mcode : entity work.T65_MCode
port map(
--inputs
Mode => Mode_r,
IR => IR,
MCycle => MCycle,
P => P,
--outputs
LCycle => LCycle,
ALU_Op => ALU_Op,
Set_BusA_To => Set_BusA_To,
Set_Addr_To => Set_Addr_To,
Write_Data => Write_Data,
Jump => Jump,
BAAdd => BAAdd,
BreakAtNA => BreakAtNA,
ADAdd => ADAdd,
AddY => AddY,
PCAdd => PCAdd,
Inc_S => Inc_S,
Dec_S => Dec_S,
LDA => LDA,
LDP => LDP,
LDX => LDX,
LDY => LDY,
LDS => LDS,
LDDI => LDDI,
LDALU => LDALU,
LDAD => LDAD,
LDBAL => LDBAL,
LDBAH => LDBAH,
SaveP => SaveP,
Write => Write
);
alu : entity work.T65_ALU
port map(
Mode => Mode_r,
Op => ALU_Op_r,
BusA => BusA_r,
BusB => BusB,
P_In => P,
P_Out => P_Out,
Q => ALU_Q
);
-- the 65xx design requires at least two clock cycles before
-- starting its reset sequence (according to datasheet)
process (Res_n, Clk)
begin
if Res_n = '0' then
Res_n_i <= '0';
Res_n_d <= '0';
elsif Clk'event and Clk = '1' then
Res_n_i <= Res_n_d;
Res_n_d <= '1';
end if;
end process;
process (Res_n_i, Clk)
begin
if Res_n_i = '0' then
PC <= (others => '0'); -- Program Counter
IR <= "00000000";
S <= (others => '0'); -- Dummy
PBR <= (others => '0');
DBR <= (others => '0');
Mode_r <= (others => '0');
ALU_Op_r <= ALU_OP_BIT;
Write_Data_r <= Write_Data_DL;
Set_Addr_To_r <= Set_Addr_To_PBR;
WRn_i <= '1';
EF_i <= '1';
MF_i <= '1';
XF_i <= '1';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
WRn_i <= not Write or RstCycle;
PBR <= (others => '1'); -- Dummy
DBR <= (others => '1'); -- Dummy
EF_i <= '0'; -- Dummy
MF_i <= '0'; -- Dummy
XF_i <= '0'; -- Dummy
if MCycle = "000" then
Mode_r <= Mode;
if IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
if IRQCycle = '1' or NMICycle = '1' then
IR <= "00000000";
else
IR <= DI;
end if;
if LDS = '1' then -- LAS won't work properly if not limited to machine cycle 0
S(7 downto 0) <= unsigned(ALU_Q);
end if;
end if;
ALU_Op_r <= ALU_Op;
Write_Data_r <= Write_Data;
if Break = '1' then
Set_Addr_To_r <= Set_Addr_To_PBR;
else
Set_Addr_To_r <= Set_Addr_To;
end if;
if Inc_S = '1' then
S <= S + 1;
end if;
if Dec_S = '1' and RstCycle = '0' then
S <= S - 1;
end if;
if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
--
-- jump control logic
--
case Jump is
when "01" =>
PC <= PC + 1;
when "10" =>
PC <= unsigned(DI & DL);
when "11" =>
if PCAdder(8) = '1' then
if DL(7) = '0' then
PC(15 downto 8) <= PC(15 downto 8) + 1;
else
PC(15 downto 8) <= PC(15 downto 8) - 1;
end if;
end if;
PC(7 downto 0) <= PCAdder(7 downto 0);
when others => null;
end case;
end if;
end if;
end if;
end process;
PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
else "0" & PC(7 downto 0);
process (Res_n_i, Clk)
variable tmpP:std_logic_vector(7 downto 0);--Lets try to handle loading P at mcycle=0 and set/clk flags at same cycle
begin
if Res_n_i = '0' then
P <= x"00"; -- ensure we have nothing set on reset
elsif Clk'event and Clk = '1' then
tmpP:=P;
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = "000" then
if LDA = '1' then
ABC(7 downto 0) <= ALU_Q;
end if;
if LDX = '1' then
X(7 downto 0) <= ALU_Q;
end if;
if LDY = '1' then
Y(7 downto 0) <= ALU_Q;
end if;
if (LDA or LDX or LDY) = '1' then
tmpP:=P_Out;
end if;
end if;
if SaveP = '1' then
tmpP:=P_Out;
end if;
if LDP = '1' then
tmpP:=ALU_Q;
end if;
if IR(4 downto 0) = "11000" then
case IR(7 downto 5) is
when "000" =>--0x18(clc)
tmpP(Flag_C) := '0';
when "001" =>--0x38(sec)
tmpP(Flag_C) := '1';
when "010" =>--0x58(cli)
tmpP(Flag_I) := '0';
when "011" =>--0x78(sei)
tmpP(Flag_I) := '1';
when "101" =>--0xb8(clv)
tmpP(Flag_V) := '0';
when "110" =>--0xd8(cld)
tmpP(Flag_D) := '0';
when "111" =>--0xf8(sed)
tmpP(Flag_D) := '1';
when others =>
end case;
end if;
tmpP(Flag_B) := '1';
if IR = "00000000" and MCycle = "100" and RstCycle = '0' then
--This should happen after P has been pushed to stack
tmpP(Flag_I) := '1';
end if;
if SO_n_o = '1' and SO_n = '0' then
tmpP(Flag_V) := '1';
end if;
if RstCycle = '1' then
tmpP(Flag_I) := '1';
tmpP(Flag_D) := '0';
end if;
tmpP(Flag_1) := '1';
P<=tmpP;--new way
SO_n_o <= SO_n;
if IR(4 downto 0)/="10000" or Jump/="01" then -- delay interrupts during branches (checked with Lorenz test and real 6510), not best way yet, though - but works...
IRQ_n_o <= IRQ_n;
end if;
end if;
-- detect nmi even if not rdy
if IR(4 downto 0)/="10000" or Jump/="01" then -- delay interrupts during branches (checked with Lorenz test and real 6510) not best way yet, though - but works...
NMI_n_o <= NMI_n;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (Res_n_i, Clk)
begin
if Res_n_i = '0' then
BusA_r <= (others => '0');
BusB <= (others => '0');
BusB_r <= (others => '0');
AD <= (others => '0');
BAL <= (others => '0');
BAH <= (others => '0');
DL <= (others => '0');
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
NMI_entered <= '0';
if (really_rdy = '1') then
BusA_r <= BusA;
BusB <= DI;
-- not really nice, but no better way found yet !
if Set_Addr_To_r = Set_Addr_To_PBR or Set_Addr_To_r = Set_Addr_To_ZPG then
BusB_r <= std_logic_vector(unsigned(DI(7 downto 0)) + 1); -- required for SHA
end if;
case BAAdd is
when "01" =>
-- BA Inc
AD <= std_logic_vector(unsigned(AD) + 1);
BAL <= std_logic_vector(unsigned(BAL) + 1);
when "10" =>
-- BA Add
BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9));
when "11" =>
-- BA Adj
if BAL(8) = '1' then
BAH <= std_logic_vector(unsigned(BAH) + 1);
end if;
when others =>
end case;
-- modified to use Y register as well
if ADAdd = '1' then
if (AddY = '1') then
AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
else
AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
end if;
end if;
if IR = "00000000" then
BAL <= (others => '1');
BAH <= (others => '1');
if RstCycle = '1' then
BAL(2 downto 0) <= "100";
elsif NMICycle = '1' or (NMIAct = '1' and MCycle="100") or NMI_entered='1' then
BAL(2 downto 0) <= "010";
if MCycle="100" then
NMI_entered <= '1';
end if;
else
BAL(2 downto 0) <= "110";
end if;
if Set_addr_To_r = Set_Addr_To_BA then
BAL(0) <= '1';
end if;
end if;
if LDDI = '1' then
DL <= DI;
end if;
if LDALU = '1' then
DL <= ALU_Q;
end if;
if LDAD = '1' then
AD <= DI;
end if;
if LDBAL = '1' then
BAL(7 downto 0) <= DI;
end if;
if LDBAH = '1' then
BAH <= DI;
end if;
end if;
end if;
end if;
end process;
Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
with Set_BusA_To select
BusA <=
DI when Set_BusA_To_DI,
ABC(7 downto 0) when Set_BusA_To_ABC,
X(7 downto 0) when Set_BusA_To_X,
Y(7 downto 0) when Set_BusA_To_Y,
std_logic_vector(S(7 downto 0)) when Set_BusA_To_S,
P when Set_BusA_To_P,
ABC(7 downto 0) and DI when Set_BusA_To_DA,
(ABC(7 downto 0) or x"ee") and DI when Set_BusA_To_DAO,--ee for OAL instruction. constant may be different on other platforms.TODO:Move to generics
(ABC(7 downto 0) or x"ee") and DI and X(7 downto 0) when Set_BusA_To_DAX,--XAA, ee for OAL instruction. constant may be different on other platforms.TODO:Move to generics
ABC(7 downto 0) and X(7 downto 0) when Set_BusA_To_AAX,--SAX, SHA
(others => '-') when Set_BusA_To_DONTCARE;--Can probably remove this
with Set_Addr_To_r select
A <=
"0000000000000001" & std_logic_vector(S(7 downto 0)) when Set_Addr_To_SP,
DBR & "00000000" & AD when Set_Addr_To_ZPG,
"00000000" & BAH & BAL(7 downto 0) when Set_Addr_To_BA,
PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when Set_Addr_To_PBR;
-- This is the P that gets pushed on stack with correct B flag. I'm not sure if NMI also clears B, but I guess it does.
PwithB<=(P and x"ef") when (IRQCycle='1' or NMICycle='1') else P;
with Write_Data_r select
DO <=
DL when Write_Data_DL,
ABC(7 downto 0) when Write_Data_ABC,
X(7 downto 0) when Write_Data_X,
Y(7 downto 0) when Write_Data_Y,
std_logic_vector(S(7 downto 0)) when Write_Data_S,
PwithB when Write_Data_P,
std_logic_vector(PC(7 downto 0)) when Write_Data_PCL,
std_logic_vector(PC(15 downto 8)) when Write_Data_PCH,
ABC(7 downto 0) and X(7 downto 0) when Write_Data_AX,
ABC(7 downto 0) and X(7 downto 0) and BusB_r(7 downto 0) when Write_Data_AXB, -- no better way found yet...
X(7 downto 0) and BusB_r(7 downto 0) when Write_Data_XB, -- no better way found yet...
Y(7 downto 0) and BusB_r(7 downto 0) when Write_Data_YB, -- no better way found yet...
(others=>'-') when Write_Data_DONTCARE;--Can probably remove this
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (Res_n_i, Clk)
begin
if Res_n_i = '0' then
MCycle <= "001";
RstCycle <= '1';
IRQCycle <= '0';
NMICycle <= '0';
NMIAct <= '0';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = LCycle or Break = '1' then
MCycle <= "000";
RstCycle <= '0';
IRQCycle <= '0';
NMICycle <= '0';
if NMIAct = '1' and IR/=x"00" then -- delay NMI further if we just executed a BRK
NMICycle <= '1';
NMIAct <= '0'; -- reset NMI edge detector if we start processing the NMI
elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
IRQCycle <= '1';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
end if;
--detect NMI even if not rdy
if NMI_n_o = '1' and (NMI_n = '0' and (IR(4 downto 0)/="10000" or Jump/="01")) then -- branches have influence on NMI start (not best way yet, though - but works...)
NMIAct <= '1';
end if;
-- we entered NMI during BRK instruction
if NMI_entered='1' then
NMIAct <= '0';
end if;
end if;
end if;
end process;
end;
| gpl-3.0 | 1f0ec9d60314a90bb4a5736262ba429e | 0.492837 | 3.601499 | false | false | false | false |
DreamIP/GPStudio | support/process/median/hdl/median_process.vhd | 1 | 4,744 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity median_process is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer;
WEIGHT_SIZE : integer := 8
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_width : in std_logic_vector(15 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end median_process;
architecture rtl of median_process is
component matrix_extractor
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer;
OUTVALUE_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
------------------------ matrix out ---------------------
p00, p01, p02 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p10, p11, p12 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p20, p21, p22 : out std_logic_vector((PIX_WIDTH-1) downto 0);
matrix_dv : out std_logic;
---------------------- computed value -------------------
value_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
value_dv : in std_logic;
------------------------- params ------------------------
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0)
);
end component;
-- neighbors extraction
signal p00, p01, p02 : std_logic_vector((IN_SIZE-1) downto 0);
signal p10, p11, p12 : std_logic_vector((IN_SIZE-1) downto 0);
signal p20, p21, p22 : std_logic_vector((IN_SIZE-1) downto 0);
signal matrix_dv : std_logic;
signal value_data : std_logic_vector((IN_SIZE-1) downto 0);
signal value_dv : std_logic;
signal out_fv_s : std_logic;
signal enable_s : std_logic;
signal prod_dv : std_logic;
begin
matrix_extractor_inst : matrix_extractor
generic map (
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
PIX_WIDTH => IN_SIZE,
OUTVALUE_WIDTH => IN_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
p00 => p00, p01 => p01, p02 => p02,
p10 => p10, p11 => p11, p12 => p12,
p20 => p20, p21 => p21, p22 => p22,
matrix_dv => matrix_dv,
value_data => value_data,
value_dv => value_dv,
out_data => out_data,
out_fv => out_fv_s,
out_dv => out_dv,
enable_i => status_reg_enable_bit,
widthimg_i => widthimg_reg_width
);
process (clk_proc, reset_n, matrix_dv)
-- Variables declaration
variable tmp : std_logic_vector((IN_SIZE-1) downto 0);
type data is array (0 to 8) of std_logic_vector((IN_SIZE-1) downto 0);
variable b : data;
begin
if(reset_n='0') then
enable_s <= '0';
value_dv <= '0';
prod_dv <= '0';
elsif(rising_edge(clk_proc)) then
if(in_fv = '0') then
enable_s <= status_reg_enable_bit;
value_dv <= '0';
prod_dv <= '0';
end if;
prod_dv <= '0';
if(matrix_dv = '1' and enable_s = '1') then
b(0) := p00;
b(1) := p01;
b(2) := p02;
b(3) := p10;
b(4) := p11;
b(5) := p12;
b(6) := p20;
b(7) := p21;
b(8) := p22;
prod_dv <= '1';
end if;
value_dv <= '0';
if(prod_dv = '1' and enable_s = '1') then
for i in 0 to 8 loop
for j in (i+1) to 8 loop
if(unsigned(b(i)) > unsigned(b(j)))then
tmp := b(i);
b(i) := b(j);
b(j) := tmp;
end if;
end loop;
end loop;
value_data <= std_logic_vector(b(4))(OUT_SIZE -1 downto 0);
value_dv <= '1';
end if;
end if;
end process;
out_fv <= enable_s and out_fv_s;
end rtl;
| gpl-3.0 | dd6ec625eb55c1f70008d635236fa6ae | 0.482715 | 2.944755 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/verif/transloop.vhdl | 1 | 5,990 | --
-- Transceiver Loop
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016-2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library FPGALIB;
use FPGALIB.verif.all;
entity TransLoop is
generic (
DBYTES : positive:=4; -- Data bytes
TSIZE : positive:=1e4; -- Total size
FSIZE : positive:=2048 -- Frame size
);
port (
-- TX side
tx_clk_i : in std_logic;
tx_rst_i : in std_logic;
tx_data_i : in std_logic_vector(DBYTES*8-1 downto 0);
tx_data_o : out std_logic_vector(DBYTES*8-1 downto 0);
tx_isk_o : out std_logic_vector(DBYTES-1 downto 0);
tx_ready_i : in std_logic;
-- RX side
rx_clk_i : in std_logic;
rx_rst_i : in std_logic;
rx_data_i : in std_logic_vector(DBYTES*8-1 downto 0);
rx_isk_i : in std_logic_vector(DBYTES-1 downto 0);
rx_errors_o : out std_logic_vector(4 downto 0);
rx_finish_o : out std_logic;
rx_cycles_o : out std_logic_vector(31 downto 0)
);
end entity TransLoop;
architecture RTL of TransLoop is
constant K28_5 : std_logic_vector(7 downto 0):=x"BC";
constant K28_1 : std_logic_vector(7 downto 0):=x"3C";
constant DWIDTH : positive:=DBYTES*8;
signal rx_data, tx_data : std_logic_vector(DWIDTH-1 downto 0);
signal rx_stb, tx_stb : std_logic;
signal rx_cnt, tx_cnt : unsigned(DWIDTH-1 downto 0);
signal rx_cycles : unsigned(31 downto 0);
type state_t is (IDLE, STROBE, ACK, TRANSFER, GAP, FINISH);
signal tx_state, rx_state : state_t:=IDLE;
function repeat (value: std_logic_vector; num: positive) return std_logic_vector is
variable retval : std_logic_vector(num*8-1 downto 0);
begin
for i in 1 to num loop
retval(i*8-1 downto (i-1)*8):=value;
end loop;
return retval;
end repeat;
constant tied_to_vcc : std_logic_vector(DWIDTH-1 downto 0):=(others => '1');
constant tied_to_gnd : std_logic_vector(DWIDTH-1 downto 0):=(others => '0');
begin
loop_i: LoopCheck
generic map (DWIDTH => DWIDTH)
port map(
-- TX side
tx_clk_i => tx_clk_i,
tx_rst_i => tx_rst_i,
tx_stb_i => tx_stb,
tx_data_i => tx_data_i,
tx_data_o => tx_data,
-- RX side
rx_clk_i => rx_clk_i,
rx_rst_i => rx_rst_i,
rx_stb_i => rx_stb,
rx_data_i => rx_data,
rx_errors_o => rx_errors_o
);
tx_fsm: process(tx_clk_i) is
begin
if rising_edge(tx_clk_i) then
if tx_rst_i='1' then
tx_state <= IDLE;
tx_isk_o <= (others => '0');
tx_data_o <= (others => '0');
tx_cnt <= (others => '0');
tx_stb <= '0';
else
case tx_state is
when IDLE =>
if tx_ready_i='1' then
tx_state <= STROBE;
end if;
when STROBE =>
tx_isk_o <= (others => '1');
tx_data_o <= repeat(K28_5,DBYTES);
tx_state <= ACK;
when ACK =>
if rx_data_i=repeat(K28_5,DBYTES) and rx_isk_i=tied_to_vcc(DBYTES-1 downto 0) then
tx_state <= TRANSFER;
tx_stb <= '1';
end if;
when TRANSFER =>
tx_isk_o <= (others => '0');
tx_data_o <= tx_data;
tx_cnt <= tx_cnt+1;
if tx_cnt=TSIZE-1 then
tx_stb <= '0';
tx_state <= FINISH;
elsif (tx_cnt mod FSIZE = FSIZE-1) then
tx_state <= GAP;
tx_stb <= '0';
end if;
when GAP =>
tx_isk_o <= (others => '1');
tx_data_o <= repeat(K28_1,DBYTES);
tx_state <= TRANSFER;
tx_stb <= '1';
when FINISH =>
tx_isk_o <= (others => '1');
tx_data_o <= repeat(K28_5,DBYTES);
when others =>
tx_state <= IDLE;
end case;
end if;
end if;
end process tx_fsm;
rx_fsm: process(rx_clk_i) is
begin
if rising_edge(rx_clk_i) then
rx_finish_o <= '0';
if rx_rst_i='1' then
rx_state <= IDLE;
rx_cnt <= (others => '0');
else
case rx_state is
when IDLE =>
if rx_data_i=repeat(K28_5,DBYTES) and rx_isk_i=tied_to_vcc(DBYTES-1 downto 0) then
rx_state <= ACK;
end if;
when ACK =>
rx_state <= TRANSFER;
rx_cycles <= (others => '0');
when TRANSFER =>
rx_cycles <= rx_cycles + 1;
if rx_isk_i=tied_to_gnd(DBYTES-1 downto 0) then
rx_data <= rx_data_i;
rx_stb <= '1';
rx_cnt <= rx_cnt + 1;
else
rx_stb <= '0';
if rx_cnt>0 and rx_data_i=repeat(K28_5,DBYTES) then
rx_state <= FINISH;
rx_finish_o <= '1';
end if;
end if;
when FINISH =>
rx_finish_o <= '1';
when others =>
rx_state <= IDLE;
end case;
end if;
end if;
end process rx_fsm;
rx_cycles_o <= std_logic_vector(rx_cycles);
end architecture RTL;
| bsd-3-clause | f006c2db3f2a0a588eb0d44bbc023663 | 0.440735 | 3.597598 | false | false | false | false |
bpervan/simple-soc | pcores/uart_cntrl_v1_00_a/hdl/vhdl/UARTController.vhd | 1 | 2,289 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:39:42 03/11/2014
-- Design Name:
-- Module Name: UARTController - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity UARTController is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
rx : in STD_LOGIC;
w_data : in STD_LOGIC_VECTOR (7 downto 0);
w_start : in STD_LOGIC;
tx : out STD_LOGIC;
w_done : out STD_LOGIC;
r_data : out STD_LOGIC_VECTOR (7 downto 0);
r_done : out STD_LOGIC);
end UARTController;
architecture Behavioral of UARTController is
component BaudRateGenerator port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
tick : out STD_LOGIC
);
end component;
component UARTReciever port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
tick : in STD_LOGIC;
rx : in STD_LOGIC;
d_out : out STD_LOGIC_VECTOR (7 downto 0);
rx_done : out STD_LOGIC);
end component;
component UARTTransmitter port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
tick : in STD_LOGIC;
d_in : in STD_LOGIC_VECTOR (7 downto 0);
tx_start : in STD_LOGIC;
tx_done : out STD_LOGIC;
tx : out STD_LOGIC);
end component;
signal tick : std_logic;
begin
BRG: entity work.BaudRateGenerator port map (clk => clk,rst => rst,tick => tick);
URx: entity work.UARTReciever port map (clk => clk, rst => rst, tick => tick, rx => rx, d_out => r_data, rx_done => r_done);
UTx: entity work.UARTTransmitter port map (clk => clk, rst => rst, tick => tick, d_in => w_data, tx_start => w_start, tx_done => w_done, tx => tx);
end Behavioral;
| mit | ef5ef450ebc2190a5acd12a8597f3e6d | 0.579292 | 3.5 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/numeric/testbench/counter_tb.vhdl | 1 | 2,816 | --
-- Counter testbench
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.Numeric.all;
use FPGALIB.Simul.all;
entity Counter_tb is
end entity Counter_tb;
architecture TestBench of Counter_tb is
constant DEPTH : positive:=5;
signal stop : boolean;
signal clk, rst : std_logic;
signal ena, last : std_logic;
signal count : std_logic_vector(clog2(DEPTH)-1 downto 0);
begin
clock_i : Clock
generic map(FREQUENCY => 2)
port map(clk_o => clk, rst_o => rst, stop_i => stop);
counter_i: counter
generic map (
DEPTH => DEPTH
)
port map (
clk_i => clk,
rst_i => rst,
ena_i => ena,
count_o => count,
last_o => last
);
test_p : process
begin
ena <= '0';
print("* Start of Test (DEPTH=5)");
wait until rising_edge(clk) and rst = '0';
assert count="000" report "Counter value is not 0" severity failure;
assert last='0' report "Wrong last value indication" severity failure;
print("Ena 1");
ena <= '1';
wait until rising_edge(clk);
print("Ena 2");
ena <= '1';
assert count="000" report "Counter value is not 0" severity failure;
assert last='0' report "Wrong last value indication" severity failure;
wait until rising_edge(clk);
assert count="001" report "Counter value is not 1" severity failure;
assert last='0' report "Wrong last value indication" severity failure;
ena <= '0';
wait until rising_edge(clk);
print("Ena 3");
ena <= '1';
wait until rising_edge(clk);
assert count="010" report "Counter value is not 2" severity failure;
assert last='0' report "Wrong last value indication" severity failure;
ena <= '0';
wait until rising_edge(clk);
print("Ena 4");
ena <= '1';
wait until rising_edge(clk);
assert count="011" report "Counter value is not 3" severity failure;
assert last='0' report "Wrong last value indication" severity failure;
print("Ena 5");
ena <= '1';
wait until rising_edge(clk);
assert count="100" report "Counter value is not 4" severity failure;
assert last='1' report "Wrong last value indication" severity failure;
print("Ena 6");
ena <= '1';
wait until rising_edge(clk);
assert count="000" report "Counter value is not 0" severity failure;
assert last='0' report "Wrong last value indication" severity failure;
ena <= '0';
wait until rising_edge(clk);
print("* End of Test");
stop <= TRUE;
wait;
end process test_p;
end architecture TestBench;
| bsd-3-clause | b218f51c57d0d5df4f3716784ea99e02 | 0.60831 | 3.80027 | false | true | false | false |
DreamIP/GPStudio | support/process/detectroi/hdl/detectroi_process.vhd | 1 | 6,337 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity detectroi_process is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
COORD_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
in_size_reg_in_w_reg : in std_logic_vector(11 downto 0);
in_size_reg_in_h_reg : in std_logic_vector(11 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
----------------------- coord flow ----------------------
coord_data : out std_logic_vector(COORD_SIZE-1 downto 0);
coord_fv : out std_logic;
coord_dv : out std_logic
);
end detectroi_process;
architecture rtl of detectroi_process is
constant X_COUNTER_SIZE : integer := 12;
constant Y_COUNTER_SIZE : integer := 12;
--process data_process vars
--bin image reference coordinates
signal xBin_pos : unsigned(X_COUNTER_SIZE-1 downto 0);
signal yBin_pos : unsigned(Y_COUNTER_SIZE-1 downto 0);
signal x_min : unsigned(X_COUNTER_SIZE-1 downto 0);
signal x_max : unsigned(X_COUNTER_SIZE-1 downto 0);
signal y_min : unsigned(Y_COUNTER_SIZE-1 downto 0);
signal y_max : unsigned(Y_COUNTER_SIZE-1 downto 0);
signal enabled : std_logic;
signal frame_buffer : std_logic_vector(63 downto 0);
signal frame_buffer_has_been_filled : std_logic;
signal frame_buffer_has_been_sent : std_logic;
signal frame_buffer_position : unsigned(6 downto 0);
begin
send_roi : process (clk_proc, reset_n)
-- Vars used to fill frame_buffer
variable x_to_send : unsigned(X_COUNTER_SIZE-1 downto 0);
variable y_to_send : unsigned(Y_COUNTER_SIZE-1 downto 0);
variable w_to_send : unsigned(X_COUNTER_SIZE-1 downto 0);
variable h_to_send : unsigned(Y_COUNTER_SIZE-1 downto 0);
begin
if(reset_n='0') then
xBin_pos <= to_unsigned(0, X_COUNTER_SIZE);
yBin_pos <= to_unsigned(0, Y_COUNTER_SIZE);
--Cleaning frame coordinates
x_max <= (others=>'0');
y_max <= (others=>'0');
x_min <= (others=>'0');
y_min <= (others=>'0');
--Cleaning frame buffer
frame_buffer <= (others=>'0');
--Cleaning signals used to fill buffer
frame_buffer_has_been_filled <= '0';
frame_buffer_has_been_sent <= '0';
coord_fv <= '0';
coord_dv <= '0';
coord_data <= (others=>'0');
enabled <= '0';
elsif(rising_edge(clk_proc)) then
coord_fv <= '0';
coord_dv <= '0';
coord_data <= (others=>'0');
if(in_fv = '0') then
xBin_pos <= to_unsigned(0, X_COUNTER_SIZE);
yBin_pos <= to_unsigned(0, Y_COUNTER_SIZE);
--
if frame_buffer_has_been_filled = '0' then
--We send frame coordinates only if there is something to send
if enabled = '1' and frame_buffer_has_been_sent = '0' then
--something was detected
if x_max > 0 then
x_to_send := x_min;
y_to_send := y_min;
w_to_send := x_max-x_min;
h_to_send := y_max-y_min;
else
--nothing found -> empty rectangle at image center
x_to_send := unsigned(in_size_reg_in_w_reg)/2;
y_to_send := unsigned(in_size_reg_in_h_reg)/2;
w_to_send := (others=>'0');
h_to_send := (others=>'0');
end if;
--filling buffer with matching coordinates
frame_buffer(X_COUNTER_SIZE-1 downto 0) <= std_logic_vector(x_to_send);
frame_buffer(Y_COUNTER_SIZE+15 downto 16) <= std_logic_vector(y_to_send);
frame_buffer(X_COUNTER_SIZE+31 downto 32) <= std_logic_vector(w_to_send);
frame_buffer(Y_COUNTER_SIZE+47 downto 48) <= std_logic_vector(h_to_send);
--zero padding, each value has 16 bits but only uses XY_COUNTER_SIZE bits
frame_buffer(15 downto X_COUNTER_SIZE) <= (others=>'0');
frame_buffer(31 downto X_COUNTER_SIZE+16) <= (others=>'0');
frame_buffer(47 downto X_COUNTER_SIZE+32) <= (others=>'0');
frame_buffer(63 downto X_COUNTER_SIZE+48) <= (others=>'0');
-- Get buffer ready to send
frame_buffer_has_been_filled <= '1';
frame_buffer_position <= (others=>'0') ;
end if;
--Cleaning frame coordinates
x_max <= (others=>'0');
y_max <= (others=>'0');
x_min <= unsigned(in_size_reg_in_w_reg);
y_min <= unsigned(in_size_reg_in_h_reg);
else
--send roi coord
coord_fv <= '1';
coord_dv <= '1';
coord_data <= frame_buffer(to_integer(frame_buffer_position)+7 downto to_integer(frame_buffer_position));
if frame_buffer_position >= 56 then
frame_buffer_has_been_filled <= '0';
frame_buffer_has_been_sent <= '1';
else
frame_buffer_position <= frame_buffer_position + to_unsigned(8, 7);
end if;
end if;
enabled <= status_reg_enable_bit;
else
coord_fv <= '0';
coord_dv <= '0';
coord_data <= (others=>'0');
frame_buffer_has_been_sent <= '0';
if status_reg_enable_bit = '1' and enabled = '1' then
if(in_dv = '1' ) then
--bin img pixel counter
xBin_pos <= xBin_pos + 1;
if(xBin_pos=unsigned(in_size_reg_in_w_reg)-1) then
yBin_pos <= yBin_pos + 1;
xBin_pos <= to_unsigned(0, X_COUNTER_SIZE);
end if;
-- This will give the smallest area including all non-black points
if in_data /= (in_data'range => '0') then
if xBin_pos < x_min then
x_min <= xBin_pos;
end if;
if xBin_pos > x_max then
x_max <= xBin_pos;
end if;
--
if yBin_pos < y_min then
y_min <= yBin_pos;
end if;
if yBin_pos > y_max then
y_max <= yBin_pos;
end if;
end if;
end if;
else
enabled <= '0';
end if;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | 332cf2b178d4cb5cfe935fa3a1a5fef7 | 0.544106 | 3.059874 | false | false | false | false |
DreamIP/GPStudio | support/toolchain/caph/hdl/caph_lib/stream_out.vhd | 1 | 2,268 | -----------------------------------------------------------------------------------------
-- --
-- This file is part of the CAPH Compiler distribution --
-- http://caph.univ-bpclermont.fr --
-- --
-- Jocelyn SEROT --
-- [email protected] --
-- --
-- Copyright 2011-2015 Jocelyn SEROT. All rights reserved. --
-- This file is distributed under the terms of the GNU Library General Public License --
-- with the special exception on linking described in file ../LICENSE. --
-- --
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
entity stream_out is
generic ( filename: string := "vhdl_result.dat"; size: integer := 10; period: integer := 1 );
port ( empty : in std_logic;
din : in std_logic_vector(size-1 downto 0);
rd : out std_logic;
clk : in std_logic;
rst : in std_logic
);
end stream_out;
architecture beh of stream_out is
begin
process
file output_file: text;
variable file_line: line;
variable token: integer;
variable eof: boolean;
begin
if ( period < 1 ) then
report "stream_out(" & filename & ") : period < 1 !"
severity error;
end if;
eof := false;
file_open(output_file,filename,WRITE_MODE);
while not eof loop
wait until rising_edge(clk);
if ( empty = '0' ) then
write (file_line,to_bitvector(din));
writeline (output_file,file_line);
end if;
end loop; -- TODO: set eof when run is completed ?
file_close(output_file);
wait;
end process;
rd <= not(empty);
end;
| gpl-3.0 | d3aaeba94ea9bc7e9ff568bb1dcfa64a | 0.413139 | 4.930435 | false | false | false | false |
bpervan/simple-soc | pcores/uart_cntrl_v1_00_a/hdl/vhdl/UARTReciever.vhd | 1 | 3,006 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:05:12 03/11/2014
-- Design Name:
-- Module Name: UARTReciever - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity UARTReciever is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
tick : in STD_LOGIC;
rx : in STD_LOGIC;
d_out : out STD_LOGIC_VECTOR (7 downto 0);
rx_done : out STD_LOGIC);
end UARTReciever;
architecture Behavioral of UARTReciever is
type state_type is (idle, start, data, stop);
signal next_state, current_state : state_type;
signal tick_counter, tick_counter_next : unsigned (3 downto 0);
signal bit_counter, bit_counter_next : unsigned (2 downto 0);
signal reg, reg_next : std_logic_vector (7 downto 0);
begin
process (clk, rst)
begin
if (rst = '0') then
current_state <= idle;
tick_counter <= "0000";
bit_counter <= "000";
reg <= (others => '0');
else
if (clk'event and clk = '1') then
current_state <= next_state;
tick_counter <= tick_counter_next;
bit_counter <= bit_counter_next;
reg <= reg_next;
end if;
end if;
end process;
process(current_state, tick_counter, bit_counter, reg, tick, rx)
begin
next_state <= current_state;
tick_counter_next <= tick_counter;
bit_counter_next <= bit_counter;
reg_next <= reg;
rx_done <= '0';
case current_state is
when idle =>
if(rx = '0') then
next_state <= start;
tick_counter_next <= "0000";
reg_next <= "00000000";
end if;
when start =>
if(tick = '1') then
if(tick_counter < 7) then
tick_counter_next <= tick_counter + 1;
else
tick_counter_next <= "0000";
bit_counter_next <= "000";
next_state <= data;
end if;
end if;
when data =>
if(tick = '1') then
if(tick_counter < 15) then
tick_counter_next <= tick_counter + 1;
else
tick_counter_next <= "0000";
reg_next <= rx & reg (7 downto 1);
if (bit_counter = 7) then
next_state <= stop;
else
bit_counter_next <= bit_counter + 1;
end if;
end if;
end if;
when stop =>
if(tick = '1') then
if(tick_counter < 15) then
tick_counter_next <= tick_counter + 1;
else
next_state <= idle;
rx_done <= '1';
end if;
end if;
end case;
end process;
d_out <= reg;
end Behavioral;
| mit | 0535ba3a6201b6cd7b208e3e68ca4660 | 0.570526 | 3.270947 | false | false | false | false |
hoglet67/ElectronFpga | src/altera/sdram_simple.vhd | 1 | 15,994 | -- The MIT License (MIT)
--
-- Copyright (c) 2014 Matthew Hagerty
-- Copyright 2019 Google LLC
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
-- Simple SDRAM Controller for Winbond W9812G6JH-75
-- http://codehackcreate.com/archives/444
--
-- Matthew Hagerty, copyright 2014
--
-- Create Date: 18:22:00 March 18, 2014
-- Module Name: sdram_simple - RTL
--
-- Change Log:
--
-- Jul 2019 (Phillip Pearson)
-- Added clk_en to allow running at half rate, for easy timing
--
-- Jan 28, 2016
-- Changed to use positive clock edge.
-- Buffered output (read) data, sampled during RAS2.
-- Removed unused signals for features that were not implemented.
-- Changed tabs to space.
--
-- March 19, 2014
-- Initial implementation.
library IEEE, UNISIM;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity sdram_simple is
port(
-- Host side
clk_100m0_i : in std_logic; -- Master clock
clk_en : in std_logic; -- Master clock enable
reset_i : in std_logic := '0'; -- Reset, active high
refresh_i : in std_logic := '0'; -- Initiate a refresh cycle, active high
rw_i : in std_logic := '0'; -- Initiate a read or write operation, active high
we_i : in std_logic := '0'; -- Write enable, active low
addr_i : in std_logic_vector(23 downto 0) := (others => '0'); -- Address from host to SDRAM
data_i : in std_logic_vector(15 downto 0) := (others => '0'); -- Data from host to SDRAM
ub_i : in std_logic; -- Data upper byte enable, active low
lb_i : in std_logic; -- Data lower byte enable, active low
ready_o : out std_logic := '0'; -- Set to '1' when the memory is ready
done_o : out std_logic := '0'; -- Read, write, or refresh, operation is done
data_o : out std_logic_vector(15 downto 0); -- Data from SDRAM to host
-- SDRAM side
sdCke_o : out std_logic; -- Clock-enable to SDRAM
sdCe_bo : out std_logic; -- Chip-select to SDRAM
sdRas_bo : out std_logic; -- SDRAM row address strobe
sdCas_bo : out std_logic; -- SDRAM column address strobe
sdWe_bo : out std_logic; -- SDRAM write enable
sdBs_o : out std_logic_vector(1 downto 0); -- SDRAM bank address
sdAddr_o : out std_logic_vector(12 downto 0); -- SDRAM row/column address
sdData_io : inout std_logic_vector(15 downto 0); -- Data to/from SDRAM
sdDqmh_o : out std_logic; -- Enable upper-byte of SDRAM databus if true
sdDqml_o : out std_logic -- Enable lower-byte of SDRAM databus if true
);
end entity;
architecture rtl of sdram_simple is
-- SDRAM controller states.
type fsm_state_type is (
ST_INIT_WAIT, ST_INIT_PRECHARGE, ST_INIT_REFRESH1, ST_INIT_MODE, ST_INIT_REFRESH2,
ST_IDLE, ST_REFRESH, ST_ACTIVATE, ST_RCD, ST_RW, ST_RAS1, ST_RAS2, ST_PRECHARGE);
signal state_r, state_x : fsm_state_type := ST_INIT_WAIT;
-- SDRAM mode register data sent on the address bus.
--
-- | A12-A10 | A9 | A8 A7 | A6 A5 A4 | A3 | A2 A1 A0 |
-- | reserved| wr burst |reserved| CAS Ltncy|addr mode| burst len|
-- 0 0 0 0 0 0 0 1 0 0 0 0 0
constant MODE_REG : std_logic_vector(12 downto 0) := "000" & "0" & "00" & "010" & "0" & "000";
-- SDRAM commands combine SDRAM inputs: cs, ras, cas, we.
subtype cmd_type is unsigned(3 downto 0);
constant CMD_ACTIVATE : cmd_type := "0011";
constant CMD_PRECHARGE : cmd_type := "0010";
constant CMD_WRITE : cmd_type := "0100";
constant CMD_READ : cmd_type := "0101";
constant CMD_MODE : cmd_type := "0000";
constant CMD_NOP : cmd_type := "0111";
constant CMD_REFRESH : cmd_type := "0001";
signal cmd_r : cmd_type;
signal cmd_x : cmd_type;
signal bank_s : std_logic_vector(1 downto 0);
signal row_s : std_logic_vector(12 downto 0);
signal col_s : std_logic_vector(8 downto 0);
signal addr_r : std_logic_vector(12 downto 0);
signal addr_x : std_logic_vector(12 downto 0); -- SDRAM row/column address.
signal sd_dout_r : std_logic_vector(15 downto 0);
signal sd_dout_x : std_logic_vector(15 downto 0);
signal sd_busdir_r : std_logic;
signal sd_busdir_x : std_logic;
signal timer_r, timer_x : natural range 0 to 20000 := 0;
signal refcnt_r, refcnt_x : natural range 0 to 8 := 0;
signal bank_r, bank_x : std_logic_vector(1 downto 0);
signal cke_r, cke_x : std_logic;
signal sd_dqmu_r, sd_dqmu_x : std_logic;
signal sd_dqml_r, sd_dqml_x : std_logic;
signal ready_r, ready_x : std_logic;
-- Data buffer for SDRAM to Host.
signal buf_dout_r, buf_dout_x : std_logic_vector(15 downto 0);
begin
-- All signals to SDRAM buffered.
(sdCe_bo, sdRas_bo, sdCas_bo, sdWe_bo) <= cmd_r; -- SDRAM operation control bits
sdCke_o <= cke_r; -- SDRAM clock enable
sdBs_o <= bank_r; -- SDRAM bank address
sdAddr_o <= addr_r; -- SDRAM address
sdData_io <= sd_dout_r when sd_busdir_r = '1' else (others => 'Z'); -- SDRAM data bus.
sdDqmh_o <= sd_dqmu_r; -- SDRAM high data byte enable, active low
sdDqml_o <= sd_dqml_r; -- SDRAM low date byte enable, active low
-- Signals back to host.
ready_o <= ready_r;
data_o <= buf_dout_r;
-- 23 22 | 21 20 19 18 17 16 15 14 13 12 11 10 09 | 08 07 06 05 04 03 02 01 00 |
-- BS0 BS1 | ROW (A12-A0) 8192 rows | COL (A8-A0) 512 cols |
bank_s <= addr_i(23 downto 22);
row_s <= addr_i(21 downto 9);
col_s <= addr_i(8 downto 0);
process (
state_r, timer_r, refcnt_r, cke_r, addr_r, sd_dout_r, sd_busdir_r, sd_dqmu_r, sd_dqml_r, ready_r,
bank_s, row_s, col_s,
rw_i, refresh_i, addr_i, data_i, we_i, ub_i, lb_i,
buf_dout_r, sdData_io)
begin
state_x <= state_r; -- Stay in the same state unless changed.
timer_x <= timer_r; -- Hold the cycle timer by default.
refcnt_x <= refcnt_r; -- Hold the refresh timer by default.
cke_x <= cke_r; -- Stay in the same clock mode unless changed.
cmd_x <= CMD_NOP; -- Default to NOP unless changed.
bank_x <= bank_r; -- Register the SDRAM bank.
addr_x <= addr_r; -- Register the SDRAM address.
sd_dout_x <= sd_dout_r; -- Register the SDRAM write data.
sd_busdir_x <= sd_busdir_r; -- Register the SDRAM bus tristate control.
sd_dqmu_x <= sd_dqmu_r;
sd_dqml_x <= sd_dqml_r;
buf_dout_x <= buf_dout_r; -- SDRAM to host data buffer.
ready_x <= ready_r; -- Always ready unless performing initialization.
done_o <= '0'; -- Done tick, single cycle.
if timer_r /= 0 then
timer_x <= timer_r - 1;
else
cke_x <= '1';
bank_x <= bank_s;
addr_x <= "0000" & col_s; -- A10 low for rd/wr commands to suppress auto-precharge.
sd_dqmu_x <= '0';
sd_dqml_x <= '0';
case state_r is
when ST_INIT_WAIT =>
-- 1. Wait 200us with DQM signals high, cmd NOP.
-- 2. Precharge all banks.
-- 3. Eight refresh cycles.
-- 4. Set mode register.
-- 5. Eight refresh cycles.
state_x <= ST_INIT_PRECHARGE;
timer_x <= 20000; -- Wait 200us (20,000 cycles).
-- timer_x <= 2; -- for simulation
sd_dqmu_x <= '1';
sd_dqml_x <= '1';
when ST_INIT_PRECHARGE =>
state_x <= ST_INIT_REFRESH1;
refcnt_x <= 8; -- Do 8 refresh cycles in the next state.
-- refcnt_x <= 2; -- for simulation
cmd_x <= CMD_PRECHARGE;
timer_x <= 2; -- Wait 2 cycles plus state overhead for 20ns Trp.
bank_x <= "00";
addr_x(10) <= '1'; -- Precharge all banks.
when ST_INIT_REFRESH1 =>
if refcnt_r = 0 then
state_x <= ST_INIT_MODE;
else
refcnt_x <= refcnt_r - 1;
cmd_x <= CMD_REFRESH;
timer_x <= 7; -- Wait 7 cycles plus state overhead for 70ns refresh.
end if;
when ST_INIT_MODE =>
state_x <= ST_INIT_REFRESH2;
refcnt_x <= 8; -- Do 8 refresh cycles in the next state.
-- refcnt_x <= 2; -- for simulation
bank_x <= "00";
addr_x <= MODE_REG;
cmd_x <= CMD_MODE;
timer_x <= 2; -- Trsc == 2 cycles after issuing MODE command.
when ST_INIT_REFRESH2 =>
if refcnt_r = 0 then
state_x <= ST_IDLE;
ready_x <= '1';
else
refcnt_x <= refcnt_r - 1;
cmd_x <= CMD_REFRESH;
timer_x <= 7; -- Wait 7 cycles plus state overhead for 70ns refresh.
end if;
--
-- Normal Operation
--
-- Trc - 70ns - Attive to active command.
-- Trcd - 20ns - Active to read/write command.
-- Tras - 50ns - Active to precharge command.
-- Trp - 20ns - Precharge to active command.
-- TCas - 2clk - Read/write to data out.
--
-- |<----------- Trc ------------>|
-- |<----------- Tras ---------->|
-- |<- Trcd ->|<- TCas ->| |<- Trp ->|
-- T0__ T1__ T2__ T3__ T4__ T5__ T6__ T7__ T8__ T9__ T10__
-- __| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__
-- IDLE ACTVT NOP RD/WR NOP NOP PRECG IDLE ACTVT
-- --<Row>-------<Col>------------<Bank>-------<Row>--
-- ---------------<A10>-------------<A10>-------------------
-- ------------------<Din>------------<Dout>--------
-- ---------------<DQM>---------------
-- --<Refsh>-------------
--
-- A10 during rd/wr : 0 = disable auto-precharge, 1 = enable auto-precharge.
-- A10 during precharge: 0 = single bank, 1 = all banks.
-- T0__ T1__ T2__ T3__ T4__ T5__ T6__ T7__ T8__ T9__ T10__
-- __| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__
-- IDLE ACTVT NOP RD/WR NOP NOP PRECG IDLE ACTVT
-- T0__ T1__ T2__ T3__ T4__ T5__ T6__ T7__ T8__ T9__ T10__
-- __| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__
-- IDLE ACTVT NOP RD/WR NOP NOP PRECG IDLE ACTVT
when ST_IDLE =>
-- 60ns since activate when coming from PRECHARGE state.
-- 10ns since PRECHARGE. Trp == 20ns min.
if rw_i = '1' then
state_x <= ST_ACTIVATE;
cmd_x <= CMD_ACTIVATE;
addr_x <= row_s; -- Set bank select and row on activate command.
elsif refresh_i = '1' then
state_x <= ST_REFRESH;
cmd_x <= CMD_REFRESH;
timer_x <= 7; -- Wait 7 cycles plus state overhead for 70ns refresh.
end if;
when ST_REFRESH =>
state_x <= ST_IDLE;
done_o <= '1';
when ST_ACTIVATE =>
-- Trc (Active to Active Command Period) is 65ns min.
-- 70ns since activate when coming from PRECHARGE -> IDLE states.
-- 20ns since PRECHARGE.
-- ACTIVATE command is presented to the SDRAM. The command out of this
-- state will be NOP for one cycle.
state_x <= ST_RCD;
sd_dout_x <= data_i; -- Register any write data, even if not used.
when ST_RCD =>
-- 10ns since activate.
-- Trcd == 20ns min. The clock is 10ns, so the requirement is satisfied by this state.
-- READ or WRITE command will be active in the next cycle.
state_x <= ST_RW;
if we_i = '0' then
cmd_x <= CMD_WRITE;
sd_busdir_x <= '1'; -- The SDRAM latches the input data with the command.
sd_dqmu_x <= ub_i;
sd_dqml_x <= lb_i;
else
cmd_x <= CMD_READ;
end if;
when ST_RW =>
-- 20ns since activate.
-- READ or WRITE command presented to SDRAM.
state_x <= ST_RAS1;
sd_busdir_x <= '0';
when ST_RAS1 =>
-- 30ns since activate.
state_x <= ST_RAS2;
when ST_RAS2 =>
-- 40ns since activate.
-- Tras (Active to precharge Command Period) 45ns min.
-- PRECHARGE command will be active in the next cycle.
state_x <= ST_PRECHARGE;
cmd_x <= CMD_PRECHARGE;
addr_x(10) <= '1'; -- Precharge all banks.
buf_dout_x <= sdData_io;
when ST_PRECHARGE =>
-- 50ns since activate.
-- PRECHARGE presented to SDRAM.
state_x <= ST_IDLE;
done_o <= '1'; -- Read data is ready and should be latched by the host.
timer_x <= 1; -- Buffer to make sure host takes down memory request before going IDLE.
end case;
end if;
end process;
process (clk_100m0_i)
begin
if rising_edge(clk_100m0_i) then
if clk_en = '1' then
if reset_i = '1' then
state_r <= ST_INIT_WAIT;
timer_r <= 0;
cmd_r <= CMD_NOP;
cke_r <= '0';
ready_r <= '0';
else
state_r <= state_x;
timer_r <= timer_x;
refcnt_r <= refcnt_x;
cke_r <= cke_x; -- CKE to SDRAM.
cmd_r <= cmd_x; -- Command to SDRAM.
bank_r <= bank_x; -- Bank to SDRAM.
addr_r <= addr_x; -- Address to SDRAM.
sd_dout_r <= sd_dout_x; -- Data to SDRAM.
sd_busdir_r <= sd_busdir_x; -- SDRAM bus direction.
sd_dqmu_r <= sd_dqmu_x; -- Upper byte enable to SDRAM.
sd_dqml_r <= sd_dqml_x; -- Lower byte enable to SDRAM.
ready_r <= ready_x;
buf_dout_r <= buf_dout_x;
end if;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | da5777e3422468bac31aaa3122d0ee25 | 0.506252 | 3.597391 | false | false | false | false |
DreamIP/GPStudio | support/process/harris/hdl/pipliner_filter.vhd | 1 | 8,710 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
library std;
library altera_mf;
use altera_mf.altera_mf_components.all;
use work.harris_package_components.all;
--use work.harris_package_variables.all;
entity pipliner_filter is
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer;
HALF_WINDOW_WIDTH: integer -- The total window's width is :(HALF_WINDOW_WIDTH*2+1) : Should be an odd number
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0);
pixel_table_7_7 : out filter_matrix
);
end pipliner_filter;
architecture rtl of pipliner_filter is
--type pixel_mask is array (0 to 2,0 to 2) of signed((PIX_WIDTH) downto 0);
type pix_out_signal is array (0 to 5) of std_logic_vector((PIX_WIDTH-1) downto 0);
--type pixel_matrix is array (0 to 6,0 to 6) of std_logic_vector((PIX_WIDTH-1) downto 0);
--type filter_matrix is array (0 to 6,0 to 6) of std_logic_vector(RESULT_LENGTH downto 0);
constant RESULT_LENGHT : integer := 16;
constant FIFO_LENGHT : integer := LINE_WIDTH_MAX-7;
constant FIFO_LENGHT_WIDTH : integer := integer(ceil(log2(real(FIFO_LENGHT))));
--constant Ix_sobel_mask:pixel_mask:=((to_signed(-1,9),to_signed(0,9),to_signed(1,9)),(to_signed(-1,9),to_signed(0,9),to_signed(1,9)),(to_signed(-1,9),to_signed(0,9),to_signed(1,9)));
--constant Iy_sobel_mask:pixel_mask:=((to_signed(-1,9),to_signed(-1,9),to_signed(-1,9)),(to_signed(0,9),to_signed(0,9),to_signed(0,9)),(to_signed(1,9),to_signed(1,9),to_signed(1,9)));
signal fv_signal,out_clk_dv:std_logic;
signal widthimg_temp : std_logic_vector(15 downto 0):=widthimg_i;
signal sig_wrreq:std_logic:='1';
signal sig_rdreq:std_logic:='0';
signal line_pix_out:pix_out_signal;
shared variable R:std_logic_vector((RESULT_LENGHT-1) downto 0);
shared variable Prev_R_max:std_logic_vector((RESULT_LENGHT-1) downto 0);--:=x"0001DCD65000";
shared variable R_max:std_logic_vector((RESULT_LENGHT-1) downto 0);--:=x"0001DCD65000";
shared variable conv_value_x,conv_value_y:signed(17 downto 0):=to_signed(0,18);
shared variable conv_value:integer:=0;
shared variable param_changing_reset:std_logic:='0';
shared variable Ixx,Ixy,Iyy:signed(31 downto 0):=to_signed(0,32);
shared variable cast_36_bits:std_logic_vector(35 downto 0);
shared variable aclr:std_logic:='0';
shared variable Ixx_vec,Iyy_vec:std_logic_vector(31 downto 0);
shared variable mult_a,mult_b,mult_2_a,mult_2_b,mult_3_a,mult_3_b:std_logic_vector(31 downto 0);
shared variable mult_s,mult_2_s,mult_3_s,comp_a,comp_a_2,comp_b,comp_b_2,add_a_1,add_b_1,add_b_2,add_s_inter,add_s :std_logic_vector(63 downto 0);
shared variable comp_s,comp_s_2:std_logic:='1';
shared variable pixel_matrix_kernel:filter_matrix;--pixel_matrix;
component scfifo
generic
( LPM_WIDTH: POSITIVE;
LPM_WIDTHU: POSITIVE;
LPM_NUMWORDS: POSITIVE;
LPM_SHOWAHEAD: STRING := "OFF";
ALLOW_RWCYCLE_WHEN_FULL: STRING := "OFF";
OVERFLOW_CHECKING: STRING:= "ON";
UNDERFLOW_CHECKING: STRING:= "ON"
);
port
(
data: in std_logic_vector(LPM_WIDTH-1 downto 0);
clock, wrreq, rdreq, aclr: in std_logic;
full, empty, almost_full, almost_empty: out std_logic;
q: out std_logic_vector(LPM_WIDTH-1 downto 0);
usedw: out std_logic_vector(LPM_WIDTHU-1 downto 0)
);
end component;
begin
sig_wrreq<='1';
G_1 : for i in 0 to 5 generate
line_fifo : scfifo
generic map (
LPM_WIDTH =>PIX_WIDTH,
LPM_WIDTHU =>FIFO_LENGHT_WIDTH,
LPM_NUMWORDS =>FIFO_LENGHT
)
port map(
data => pixel_matrix_kernel(i+1,0),
clock => clk_proc,
wrreq => in_dv,
q => line_pix_out(i),
rdreq => sig_rdreq and in_dv,
aclr =>param_changing_reset or(not(reset_n))
);
end generate;
process (clk_proc, reset_n)
variable x_pos,y_pos : unsigned(15 downto 0);
variable counter:integer:=0;
begin
fv_signal<=in_fv;
if(reset_n='0') then
x_pos := to_unsigned(0, 16);
y_pos := to_unsigned(0, 16);
out_clk_dv<='0';
elsif(rising_edge(clk_proc)) then
fv_signal<=in_fv;
out_clk_dv<='0';
if(in_fv='0') then
x_pos := to_unsigned(0, 16);y_pos := to_unsigned(0, 16);
out_clk_dv<='0';
------------------------------------------------------------------------------------------------------
elsif(in_dv='1') then
counter:=counter+1;
if(counter=(unsigned(widthimg_i)-8)) then
sig_rdreq<='1';
end if;
out_clk_dv<='1';
for o in 0 to 6 loop
for p in 0 to 5 loop
pixel_matrix_kernel(o,p):=pixel_matrix_kernel(o,p+1);
end loop;
if (o<6) then
pixel_matrix_kernel(o,6):=line_pix_out(o);
end if;
end loop;
pixel_matrix_kernel(6,6):=in_data;
----------- end of line ----------------
if(x_pos=unsigned(widthimg_i)) then
y_pos := y_pos+1;
x_pos := to_unsigned (1, 16);
else
x_pos := x_pos+1;
end if;
-----------------------------------------
----------------------- bloquage et débloquage de l'horloge -----------------------------------------------------
if (y_pos<=to_unsigned (HALF_WINDOW_WIDTH-1, 16)) then
out_clk_dv<='0';
end if;
----------------------- blocage de bords spéciale pour les deux premiers élements de bords ----------------------
if (x_pos<=to_unsigned (HALF_WINDOW_WIDTH, 16)) then
if (y_pos=to_unsigned (3, 16)) then
out_clk_dv<='0';
end if;
end if;
-----------------------------------------------------------------------------------------------------------------
else
end if;
-------------- changing widthimg_i parameter---------------------------------------------------------------------
if (unsigned(widthimg_i)=unsigned(widthimg_temp)) then
param_changing_reset:='0';
else
param_changing_reset:='1';
counter:=0;
sig_rdreq<='0';
end if;
widthimg_temp<=widthimg_i;
-----------------------------------------------------------------------------
else
end if;
end process;
--out_data<= std_logic_vector(to_unsigned(conv_value, 8));
out_dv <= out_clk_dv;
out_fv <= fv_signal;
pixel_table_7_7<=pixel_matrix_kernel;
end rtl;
| gpl-3.0 | 247eb33c65c6091646eeed85fe89e211 | 0.438842 | 3.955929 | false | false | false | false |
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