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DreamIP/GPStudio | support/process/scharr/hdl/scharr.vhd | 1 | 3,872 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity scharr is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end scharr;
architecture rtl of scharr is
component scharr_process
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_width : in std_logic_vector(15 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component scharr_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal widthimg_reg_width : std_logic_vector (15 downto 0);
begin
scharr_process_inst : scharr_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_width => widthimg_reg_width,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
scharr_slave_inst : scharr_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_width => widthimg_reg_width,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
| gpl-3.0 | c4e70af810e4544d410cdae66a56f434 | 0.459969 | 3.340811 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/clkXingRtl.vhd | 3 | 8,481 | -------------------------------------------------------------------------------
--! @file clkXingRtl.vhd
--
--! @brief Clock Crossing Bus converter
--
--! @details Used to transfer a faster slave interface to a slower one.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! need reduce or operation
use ieee.std_logic_misc.OR_REDUCE;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity clkXing is
generic (
gCsNum : natural := 2;
gDataWidth : natural := 32
);
port (
iArst : in std_logic;
--fast
iFastClk : in std_logic;
iFastCs : in std_logic_vector(gCsNum-1 downto 0);
iFastRNW : in std_logic;
oFastReaddata : out std_logic_vector(gDataWidth-1 downto 0);
oFastWrAck : out std_logic;
oFastRdAck : out std_logic;
--slow
iSlowClk : in std_logic;
oSlowCs : out std_logic_vector(gCsNum-1 downto 0);
oSlowRNW : out std_logic;
iSlowReaddata : in std_logic_vector(gDataWidth-1 downto 0);
iSlowWrAck : in std_logic;
iSlowRdAck : in std_logic
);
end entity;
architecture rtl of clkXing is
--! Fsm type
type tFsm is (sIdle, sTransfer);
--! Clock domain registers
type tRegClkDomain is record
chipselect : std_logic_vector(gCsNum-1 downto 0);
rnw : std_logic;
sync : std_logic;
ack : std_logic;
fsm : tFsm;
end record;
--! Register init
constant cRegClkDomainInit : tRegClkDomain := (
chipselect => (others => cInactivated),
rnw => cInactivated,
sync => cInactivated,
ack => cInactivated,
fsm => sIdle
);
--! Slow clock domain register
signal slowClkReg : tRegClkDomain;
signal slowClkReg_next : tRegClkDomain;
--! Fast clock domain register
signal fastClkReg : tRegClkDomain;
signal fastClkReg_next : tRegClkDomain;
--! Readdata register
signal readdataReg : std_logic_vector(iSlowReaddata'range);
signal readdataReg_next : std_logic_vector(readdataReg'range);
--! Transferred sync signal (fast ---> slow)
signal tranSync_sync : std_logic;
--! Transferred ack signal (slow ---> fast)
signal tranAck_sync : std_logic;
begin
-- Map registers to outputs
-- FAST
oFastWrAck <= fastClkReg.ack and not iFastRNW;
oFastRdAck <= fastClkReg.ack and iFastRNW;
oFastReaddata <= readdataReg;
-- SLOW
oSlowCs <= slowClkReg.chipselect;
oSlowRNW <= iFastRNW;
--! Fast clock domain logic
fastComb : process (
fastClkReg,
tranAck_sync,
iFastCs, iFastRNW
)
begin
-- General defaults to avoid latches
fastClkReg_next <= fastClkReg;
-- Inactivate pulsing registers
fastClkReg_next.sync <= cInactivated;
-- Assign transferred signals
fastClkReg_next.ack <= tranAck_sync;
case fastClkReg.fsm is
when sIdle =>
if OR_REDUCE(iFastCs) = cActivated then
fastClkReg_next.fsm <= sTransfer;
fastClkReg_next.sync <= cActivated;
fastClkReg_next.chipselect <= iFastCs;
fastClkReg_next.rnw <= iFastRNW;
end if;
when sTransfer =>
if fastClkReg.ack = cActivated then
fastClkReg_next.fsm <= sIdle;
end if;
end case;
end process fastComb;
--! Slow clock domain logic
slowComb : process (
slowClkReg, fastClkReg, readdataReg,
tranSync_sync,
iSlowWrAck, iSlowRdAck, iSlowReaddata
)
begin
-- Default
slowClkReg_next <= slowClkReg;
readdataReg_next <= readdataReg;
-- Inactivate pulsing registers
slowClkReg_next.ack <= cInactivated;
-- Assign transferred signals
slowClkReg_next.sync <= tranSync_sync;
case slowClkReg.fsm is
when sIdle =>
if slowClkReg.sync = cActivated then
slowClkReg_next.fsm <= sTransfer;
end if;
when sTransfer =>
slowClkReg_next.chipselect <= fastClkReg.chipselect;
slowClkReg_next.rnw <= fastClkReg.rnw;
if iSlowRdAck = cActivated or iSlowWrAck = cActivated then
slowClkReg_next.fsm <= sIdle;
slowClkReg_next.chipselect <= (others => cInactivated);
slowClkReg_next.ack <= cActivated;
if iSlowRdAck = cActivated then
readdataReg_next <= iSlowReaddata;
end if;
end if;
end case;
end process slowComb;
--! Fast clock registers
fastClockReg : process(iArst, iFastClk)
begin
if iArst = cActivated then
fastClkReg <= cRegClkDomainInit;
elsif rising_edge(iFastClk) then
fastClkReg <= fastClkReg_next;
end if;
end process fastClockReg;
--! Slow clock registers
slowClockReg : process(iArst, iSlowClk)
begin
if iArst = cActivated then
slowClkReg <= cRegClkDomainInit;
readdataReg <= (others => cInactivated);
elsif rising_edge(iSlowClk) then
slowClkReg <= slowClkReg_next;
readdataReg <= readdataReg_next;
end if;
end process slowClockReg;
--! Transfer sync pulse to slow clock domain
tranSyncToSlow : entity libcommon.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iSrc_rst => iArst,
iSrc_clk => iFastClk,
iSrc_data => fastClkReg.sync,
iDst_rst => iArst,
iDst_clk => iSlowClk,
oDst_data => tranSync_sync
);
--! Transfer ack pulse to fast clock domain
tranAckToFast : entity libcommon.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iSrc_rst => iArst,
iSrc_clk => iSlowClk,
iSrc_data => slowClkReg.ack,
iDst_rst => iArst,
iDst_clk => iFastClk,
oDst_data => tranAck_sync
);
end architecture;
| gpl-2.0 | 667f5981e7aa005bd20f20cbfb7e3d50 | 0.572102 | 4.896651 | false | false | false | false |
DreamIP/GPStudio | support/process/fast/hdl/fast_slave.vhd | 1 | 895 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fast_slave is
port(
clk_proc : in std_logic;
reset_n : in std_logic;
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0);
enable_o : out std_logic
);
end fast_slave;
architecture rtl of fast_slave is
constant ENABLE_REG_ADDR : natural := 0;
signal enable_reg : std_logic;
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
enable_reg <= '0';
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(ENABLE_REG_ADDR, 2)) => enable_reg <= datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
enable_o <= enable_reg;
end rtl;
| gpl-3.0 | 8411c7c26b0dc3adee296badec5a7467 | 0.635754 | 2.452055 | false | false | false | false |
ou-cse-378/vhdl-tetris | VGA.vhd | 1 | 3,109 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: RGB_Controller.vhd
-- // Date: 12/9/2004
-- // Description: This module handles the outputting a RGB stream to the
-- // VGA ports and handles the VSync and HSync pulses.
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity VGA is
Port ( oRGB : out std_logic_vector(2 downto 0);
oVSync : out std_logic;
oHSync : out std_logic;
iClk : in std_logic;
iClr : in std_logic;
iRGB : in std_logic_vector(2 downto 0);
iDiag : in std_logic);
end VGA;
architecture VGA_Core of VGA is
Signal tHCounter, tVCounter: std_logic_vector(10 downto 0) := "00000000000";
Signal tHSync : std_logic := '1';
Constant HFRONTPORCHSTART : integer := 640; --640
constant HPULSESTART : integer := HFRONTPORCHSTART + 17; --17
constant HBACKPORCHSTART : integer := HPULSESTART + 96; --96
constant HENDOFLINE : integer := HBACKPORCHSTART + 46; --47
Constant VFRONTPORCHSTART : integer := 480; --480
constant VPULSESTART : integer := VFRONTPORCHSTART + 10; --10
constant VBACKPORCHSTART : integer := VPULSESTART + 2; --2
constant VENDOFFRAME : integer := VBACKPORCHSTART + 29; --29
begin
PixelCounter: process(iClk, iClr)
begin
if iClr = '1' then
tHCounter <= "00000000000";
elsif (iClk'event and iClk = '1') then
if tHCounter < HENDOFLINE then
tHCounter <= tHCounter + 1;
else
tHCounter <= "00000000000";
end if;
end if;
end process;
LineCounter: process(tHSync, iClr)
begin
if iClr = '1' then
tVCounter <= "00000000000";
elsif (tHSync'event and tHSync = '1') then
if tVCounter < VENDOFFRAME then
tVCounter <= tVCounter + 1;
else
tVCounter <= "00000000000";
end if;
end if;
end process;
HSync: process(iClk, tHCounter, iClr)
begin
if iClr = '1' then
oHSync <= '1';
tHSync <= '1';
elsif (iClk'event and iClk = '1') then
if tHCounter >= HPULSESTART and tHCounter < HBACKPORCHSTART then
tHSync <= '0';
oHSync <= '0';
else
oHSync <= '1';
tHSync <= '1';
end if;
end if;
end process;
VSync: process(tVCounter, iClr)
begin
if iClr = '1' then
oVSync <= '1';
elsif tVCounter >= VPULSESTART and tVCounter < VBACKPORCHSTART then
oVSync <= '0';
else
oVSync <= '1';
end if;
end process;
RGBOut: process(iClk, iClr)
begin
if iClr = '1' then
oRGB <= "000";
elsif (iClk'event and iClk = '1') then
oRGB <= "000";
if iDiag = '1' then
if tHCounter <= 213 then
oRGB <= "100";
elsif tHCounter > 213 and tHCounter <= 426 then
oRGB <= "010";
elsif tHCounter > 426 and tHCounter < HFRONTPORCHSTART then
oRGB <= "001";
end if;
else
oRGB <= iRGB;
end if;
end if;
end process;
end VGA_Core; | mit | 0ec8b1958fe70606e98551084ed1a27f | 0.583467 | 3.221762 | false | false | false | false |
hoglet67/ElectronFpga | src/common/ps2kybrd/keyboard.vhd | 1 | 7,846 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity keyboard is
port (
clk : in std_logic;
rst_n : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
col : out std_logic_vector(3 downto 0);
row : in std_logic_vector(13 downto 0);
break : out std_logic;
turbo : out std_logic_vector(1 downto 0)
);
end entity;
architecture rtl of keyboard is
type key_matrix is array(0 to 13) of std_logic_vector(3 downto 0);
signal keys : key_matrix;
signal release : std_logic;
signal extended : std_logic;
signal keyb_data : std_logic_vector(7 downto 0);
signal keyb_valid : std_logic;
signal keyb_error : std_logic;
begin
ps2 : entity work.ps2_intf port map (
CLK => clk,
nRESET => rst_n,
PS2_CLK => ps2_clk,
PS2_DATA => ps2_data,
DATA => keyb_data,
VALID => keyb_valid,
error => keyb_error
);
process(keys, row)
variable i : integer;
variable tmp : std_logic_vector(3 downto 0);
begin
tmp := "1111";
for i in 0 to 13 loop
if (row(i) = '0') then
tmp := tmp and keys(i);
end if;
end loop;
col <= tmp;
end process;
process(clk, rst_n)
begin
if rst_n = '0' then
release <= '0';
extended <= '0';
turbo <= "01"; -- 2MHz
break <= '1';
keys( 0) <= (others => '1');
keys( 1) <= (others => '1');
keys( 2) <= (others => '1');
keys( 3) <= (others => '1');
keys( 4) <= (others => '1');
keys( 5) <= (others => '1');
keys( 6) <= (others => '1');
keys( 7) <= (others => '1');
keys( 8) <= (others => '1');
keys( 9) <= (others => '1');
keys(10) <= (others => '1');
keys(11) <= (others => '1');
keys(12) <= (others => '1');
keys(13) <= (others => '1');
elsif rising_edge(clk) then
if keyb_valid = '1' then
if keyb_data = X"e0" then
extended <= '1';
elsif keyb_data = X"f0" then
release <= '1';
else
release <= '0';
extended <= '0';
case keyb_data is
-- Special keys
when X"05" => turbo <= "00"; -- F1 (1MHz)
when X"06" => turbo <= "01"; -- F2 (2MMz)
when X"04" => turbo <= "10"; -- F3 (4MHz)
when X"0C" => turbo <= "11"; -- F4 (8MHz)
when X"09" => break <= release; -- F10 (BREAK)
-- Key Matrix
when X"74" => keys( 0)(0) <= release; -- RIGHT
when X"69" => keys( 0)(1) <= release; -- END (COPY)
-- keys( 0)(2) -- NC
when X"29" => keys( 0)(3) <= release; -- SPACE
when X"6B" => keys( 1)(0) <= release; -- LEFT
when X"72" => keys( 1)(1) <= release; -- DOWN
when X"5B" => keys( 1)(1) <= release; -- ]
when X"5A" => keys( 1)(2) <= release; -- RETURN
when X"66" => keys( 1)(3) <= release; -- BACKSPACE (DELETE)
when X"4E" => keys( 2)(0) <= release; -- -
when X"75" => keys( 2)(1) <= release; -- UP
when X"54" => keys( 2)(1) <= release; -- [
when X"52" => keys( 2)(2) <= release; -- ' full colon substitute
-- keys( 2)(3) -- NC
when X"45" => keys( 3)(0) <= release; -- 0
when X"4D" => keys( 3)(1) <= release; -- P
when X"4C" => keys( 3)(2) <= release; -- ;
when X"4A" => keys( 3)(3) <= release; -- /
when X"46" => keys( 4)(0) <= release; -- 9
when X"44" => keys( 4)(1) <= release; -- O
when X"4B" => keys( 4)(2) <= release; -- L
when X"49" => keys( 4)(3) <= release; -- .
when X"3E" => keys( 5)(0) <= release; -- 8
when X"43" => keys( 5)(1) <= release; -- I
when X"42" => keys( 5)(2) <= release; -- K
when X"41" => keys( 5)(3) <= release; -- ,
when X"3D" => keys( 6)(0) <= release; -- 7
when X"3C" => keys( 6)(1) <= release; -- U
when X"3B" => keys( 6)(2) <= release; -- J
when X"3A" => keys( 6)(3) <= release; -- M
when X"36" => keys( 7)(0) <= release; -- 6
when X"35" => keys( 7)(1) <= release; -- Y
when X"33" => keys( 7)(2) <= release; -- H
when X"31" => keys( 7)(3) <= release; -- N
when X"2E" => keys( 8)(0) <= release; -- 5
when X"2C" => keys( 8)(1) <= release; -- T
when X"34" => keys( 8)(2) <= release; -- G
when X"32" => keys( 8)(3) <= release; -- B
when X"25" => keys( 9)(0) <= release; -- 4
when X"2D" => keys( 9)(1) <= release; -- R
when X"2B" => keys( 9)(2) <= release; -- F
when X"2A" => keys( 9)(3) <= release; -- V
when X"26" => keys(10)(0) <= release; -- 3
when X"24" => keys(10)(1) <= release; -- E
when X"23" => keys(10)(2) <= release; -- D
when X"21" => keys(10)(3) <= release; -- C
when X"1E" => keys(11)(0) <= release; -- 2
when X"1D" => keys(11)(1) <= release; -- W
when X"1B" => keys(11)(2) <= release; -- S
when X"22" => keys(11)(3) <= release; -- X
when X"16" => keys(12)(0) <= release; -- 1
when X"15" => keys(12)(1) <= release; -- Q
when X"1C" => keys(12)(2) <= release; -- A
when X"1A" => keys(12)(3) <= release; -- Z
when X"76" => keys(13)(0) <= release; -- ESCAPE
when X"58" => keys(13)(1) <= release; -- CAPS LOCK
when X"14" => keys(13)(2) <= release; -- LEFT/RIGHT CTRL (CTRL)
when X"12" | X"59" =>
if (extended = '0') then -- Ignore fake shifts
keys(13)(3) <= release; -- Left SHIFT -- Right SHIFT
end if;
when others => null;
end case;
end if;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 976a2a792008aae8285d817e06512fd8 | 0.336732 | 3.889936 | false | false | false | false |
marzoul/PoC | src/common/config.vhdl | 1 | 39,065 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Global configuration settings.
--
-- Description:
-- ------------------------------------
-- This file evaluates the settings declared in the project specific package my_config.
-- See also template file my_config.vhdl.template.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.my_config.all;
use PoC.my_project.all;
use PoC.utils.all;
package config is
constant PROJECT_DIR : string := MY_PROJECT_DIR;
constant OPERATING_SYSTEM : string := MY_OPERATING_SYSTEM;
-- TODO:
-- ===========================================================================
subtype T_BOARD_STRING is STRING(1 to 8);
subtype T_BOARD_CONFIG_STRING8 is STRING(1 to 8);
subtype T_BOARD_CONFIG_STRING16 is STRING(1 to 16);
subtype T_BOARD_CONFIG_STRING32 is STRING(1 to 32);
-- subtype T_BOARD_CONFIG_STRING64 is STRING(1 to 64);
subtype T_DEVICE_STRING is STRING(1 to 32);
constant C_BOARD_STRING_EMPTY : T_BOARD_STRING;
constant C_BOARD_CONFIG_STRING8_EMPTY : T_BOARD_CONFIG_STRING8;
constant C_BOARD_CONFIG_STRING16_EMPTY : T_BOARD_CONFIG_STRING16;
constant C_BOARD_CONFIG_STRING32_EMPTY : T_BOARD_CONFIG_STRING32;
-- constant C_BOARD_CONFIG_STRING64_EMPTY : T_BOARD_CONFIG_STRING64;
constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING;
-- List of known boards
-- ---------------------------------------------------------------------------
type T_BOARD is (
BOARD_CUSTOM,
-- Spartan-3 boards
BOARD_S3SK200, BOARD_S3SK1000,
BOARD_S3ESK500, BOARD_S3ESK1600,
-- Spartan-6 boards
BOARD_ATLYS,
-- Kintex-7 boards
BOARD_KC705,
-- Virtex-5 boards
BOARD_ML505,
-- Virtex-6 boards
BOARD_ML605,
-- Virtex-7 boards
BOARD_VC707,
-- Zynq-7000 boards
BOARD_ZEDBOARD,
-- Cyclon III boards
BOARD_DE0,
-- Stratix II boards
BOARD_S2GXAV,
-- Stratix IV boards
BOARD_DE4,
-- Stratix V boards
BOARD_DE5
);
-- List of known FPGA / Chip vendors
-- ---------------------------------------------------------------------------
type T_VENDOR is (
VENDOR_ALTERA,
VENDOR_LATTICE,
VENDOR_XILINX
);
subtype vendor_t is T_VENDOR;
-- List of known synthesis tool chains
-- ---------------------------------------------------------------------------
type T_SYNTHESIS_TOOL is (
SYNTHESIS_TOOL_ALTERA_QUARTUS2,
SYNTHESIS_TOOL_SYNOPSIS,
SYNTHESIS_TOOL_XILINX_XST,
SYNTHESIS_TOOL_XILINX_VIVADO
);
-- List of known devices
-- ---------------------------------------------------------------------------
type T_DEVICE is (
DEVICE_SPARTAN3, DEVICE_SPARTAN6, -- Xilinx.Spartan
DEVICE_ZYNQ7, -- Xilinx.Zynq
DEVICE_ARTIX7, -- Xilinx.Artix
DEVICE_KINTEX7, -- Xilinx.Kintex
DEVICE_VIRTEX5, DEVICE_VIRTEX6, DEVICE_VIRTEX7, -- Xilinx.Virtex
DEVICE_CYCLONE1, DEVICE_CYCLONE2, DEVICE_CYCLONE3, -- Altera.Cyclone
DEVICE_STRATIX1, DEVICE_STRATIX2, DEVICE_STRATIX4, DEVICE_STRATIX5 -- Altera.Stratix
);
subtype device_t is T_DEVICE;
-- List of known device families
-- ---------------------------------------------------------------------------
type T_DEVICE_FAMILY is (
-- Xilinx
DEVICE_FAMILY_SPARTAN,
DEVICE_FAMILY_ZYNQ,
DEVICE_FAMILY_ARTIX,
DEVICE_FAMILY_KINTEX,
DEVICE_FAMILY_VIRTEX,
DEVICE_FAMILY_CYCLONE,
DEVICE_FAMILY_STRATIX
);
-- List of known device subtypes
-- ---------------------------------------------------------------------------
type T_DEVICE_SUBTYPE is (
DEVICE_SUBTYPE_NONE,
-- Xilinx
DEVICE_SUBTYPE_X,
DEVICE_SUBTYPE_T,
DEVICE_SUBTYPE_XT,
DEVICE_SUBTYPE_HT,
DEVICE_SUBTYPE_LX,
DEVICE_SUBTYPE_SXT,
DEVICE_SUBTYPE_LXT,
DEVICE_SUBTYPE_TXT,
DEVICE_SUBTYPE_FXT,
DEVICE_SUBTYPE_CXT,
DEVICE_SUBTYPE_HXT,
-- Altera
DEVICE_SUBTYPE_E,
DEVICE_SUBTYPE_GS,
DEVICE_SUBTYPE_GX,
DEVICE_SUBTYPE_GT
);
-- List of known transceiver (sub-)types
-- ---------------------------------------------------------------------------
type T_TRANSCEIVER is (
TRANSCEIVER_GTP_DUAL, TRANSCEIVER_GTPE1, TRANSCEIVER_GTPE2, -- Xilinx GTP transceivers
TRANSCEIVER_GTX, TRANSCEIVER_GTXE1, TRANSCEIVER_GTXE2, -- Xilinx GTX transceivers
TRANSCEIVER_GTH, TRANSCEIVER_GTHE1, TRANSCEIVER_GTHE2, -- Xilinx GTH transceivers
TRANSCEIVER_GTZ, -- Xilinx GTZ transceivers
-- TODO: add Altera transceivers
TRANSCEIVER_GXB, -- Altera GXB transceiver
TRANSCEIVER_NONE
);
-- Properties of an FPGA architecture
-- ===========================================================================
type T_DEVICE_INFO is record
Vendor : T_VENDOR;
Device : T_DEVICE;
DevFamily : T_DEVICE_FAMILY;
DevNumber : natural;
DevSubType : T_DEVICE_SUBTYPE;
DevSeries : natural;
TransceiverType : T_TRANSCEIVER;
LUT_FanIn : positive;
end record;
-- Data structures to describe UART / RS232
type T_BOARD_UART_DESC is record
IsDTE : BOOLEAN; -- Data terminal Equipment (e.g. PC, Printer)
FlowControl : T_BOARD_CONFIG_STRING16; -- (NONE, SW, HW_CTS_RTS, HW_RTR_RTS)
BaudRate : T_BOARD_CONFIG_STRING16; -- e.g. "115.2 kBd"
BaudRate_Max : T_BOARD_CONFIG_STRING16;
end record;
-- Data structures to describe Ethernet
type T_BOARD_ETHERNET_DESC is record
IPStyle : T_BOARD_CONFIG_STRING8;
RS_DataInterface : T_BOARD_CONFIG_STRING8;
PHY_Device : T_BOARD_CONFIG_STRING16;
PHY_DeviceAddress : STD_LOGIC_VECTOR(7 downto 0);
PHY_DataInterface : T_BOARD_CONFIG_STRING8;
PHY_ManagementInterface : T_BOARD_CONFIG_STRING16;
end record;
subtype T_BOARD_ETHERNET_DESC_INDEX is NATURAL range 0 to 7;
type T_BOARD_ETHERNET_DESC_VECTOR is array(NATURAL range <>) of T_BOARD_ETHERNET_DESC;
-- Data structures to describe a board layout
type T_BOARD_INFO is record
FPGADevice : T_DEVICE_STRING;
UART : T_BOARD_UART_DESC;
Ethernet : T_BOARD_ETHERNET_DESC_VECTOR(T_BOARD_ETHERNET_DESC_INDEX);
EthernetCount : T_BOARD_ETHERNET_DESC_INDEX;
end record;
type T_BOARD_INFO_VECTOR is array (T_BOARD) of T_BOARD_INFO;
-- QUESTION: replace archprops with DEVICE_INFO ?
type archprops_t is record
LUT_K : positive; -- LUT Fanin
end record;
-- Functions extracting board and PCB properties from "MY_BOARD"
-- which is declared in package "my_config".
-- ===========================================================================
function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return T_BOARD;
function BOARD_INFO(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return T_BOARD_INFO;
function BOARD_DEVICE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING;
function BOARD_UART_BAUDRATE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING;
-- Functions extracting device and architecture properties from "MY_DEVICE"
-- which is declared in package "my_config".
-- ===========================================================================
function VENDOR(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_VENDOR;
function SYNTHESIS_TOOL(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_SYNTHESIS_TOOL;
function DEVICE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE;
function DEVICE_FAMILY(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_FAMILY;
function DEVICE_NUMBER(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural;
function DEVICE_SUBTYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SUBTYPE;
function DEVICE_SERIES(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural;
function TRANSCEIVER_TYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_TRANSCEIVER;
function LUT_FANIN(DeviceString : string := C_DEVICE_STRING_EMPTY) return positive;
function DEVICE_INFO(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_INFO;
function ARCH_PROPS return archprops_t;
-- force FSM to predefined encoding in debug mode
function getFSMEncoding_gray(debug : BOOLEAN) return STRING;
end package;
package body config is
-- default fill and string termination character for fixed size strings
-- ===========================================================================
constant C_POC_NUL : CHARACTER := '`';
-- deferred constant
-- ===========================================================================
constant C_BOARD_STRING_EMPTY : T_BOARD_STRING := (others => C_POC_NUL);
constant C_BOARD_CONFIG_STRING8_EMPTY : T_BOARD_CONFIG_STRING8 := (others => C_POC_NUL);
constant C_BOARD_CONFIG_STRING16_EMPTY : T_BOARD_CONFIG_STRING16 := (others => C_POC_NUL);
constant C_BOARD_CONFIG_STRING32_EMPTY : T_BOARD_CONFIG_STRING32 := (others => C_POC_NUL);
constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING := (others => C_POC_NUL);
-- private functions required by board description
-- ModelSim requires that this functions is defined before it is used below.
-- ===========================================================================
-- chr_is* function
function chr_isDigit(chr : CHARACTER) return boolean is
begin
return ((CHARACTER'pos('0') <= CHARACTER'pos(chr)) and (CHARACTER'pos(chr) <= CHARACTER'pos('9')));
end function;
function chr_isAlpha(chr : character) return boolean is
begin
return (((CHARACTER'pos('a') <= CHARACTER'pos(chr)) and (CHARACTER'pos(chr) <= CHARACTER'pos('z'))) or
((CHARACTER'pos('A') <= CHARACTER'pos(chr)) and (CHARACTER'pos(chr) <= CHARACTER'pos('Z'))));
end function;
function str_length(str : STRING) return NATURAL is
begin
for i in str'range loop
if (str(i) = C_POC_NUL) then
return i - str'low;
end if;
end loop;
return str'length;
end function;
function str_trim(str : STRING) return STRING is
begin
return str(str'low to str'low + str_length(str) - 1);
end function;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN is
constant len : NATURAL := imin(str1'length, str2'length);
variable chr1 : CHARACTER;
variable chr2 : CHARACTER;
begin
-- if both strings are empty
if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if;
-- compare char by char
for i in str1'low to str1'low + len - 1 loop
chr1 := str1(i);
chr2 := str2(str2'low + (i - str1'low ));
if (CHARACTER'pos('A') <= CHARACTER'pos(chr1)) and (CHARACTER'pos(chr1) <= CHARACTER'pos('Z')) then
chr1 := CHARACTER'val(CHARACTER'pos(chr1) - CHARACTER'pos('A') + CHARACTER'pos('a'));
end if;
if (CHARACTER'pos('A') <= CHARACTER'pos(chr2)) and (CHARACTER'pos(chr2) <= CHARACTER'pos('Z')) then
chr2 := CHARACTER'val(CHARACTER'pos(chr2) - CHARACTER'pos('A') + CHARACTER'pos('a'));
end if;
if (chr1 /= chr2) then
return FALSE;
elsif ((chr1 = C_POC_NUL) xor (chr2 = C_POC_NUL)) then
return FALSE;
elsif ((chr1 = C_POC_NUL) and (chr2 = C_POC_NUL)) then
return TRUE;
end if;
end loop;
-- check special cases,
return (((str1'length = len) and (str2'length = len)) or -- both strings are fully consumed and equal
((str1'length > len) and (str1(str1'low + len) = C_POC_NUL)) or -- str1 is longer, but str_length equals len
((str2'length > len) and (str2(str2'low + len) = C_POC_NUL))); -- str2 is longer, but str_length equals len
end function;
function str_find(str : STRING; pattern : STRING; start : NATURAL := 0) return BOOLEAN is
begin
for i in imax(str'low, start) to (str'high - pattern'length + 1) loop
exit when (str(i) = C_POC_NUL);
if (str(i to i + pattern'length - 1) = pattern) then
return TRUE;
end if;
end loop;
return FALSE;
end function;
-- helper function to create configuration strings
-- ===========================================================================
function getLocalDeviceString(DeviceString : STRING) return STRING is
function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is begin
if cond then return value1; else return value2; end if;
end function;
constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
constant MY_DEVICE_STR : STRING := BOARD_DEVICE;
variable Result : STRING(1 to T_DEVICE_STRING'length);
begin
Result := (others => C_POC_NUL);
-- report DeviceString for debugging
if (POC_VERBOSE = TRUE) then
report "getLocalDeviceString: DeviceString='" & str_trim(DeviceString) & "' MY_DEVICE='" & str_trim(MY_DEVICE) & "' MY_DEVICE_STR='" & str_trim(MY_DEVICE_STR) & "'" severity NOTE;
end if;
-- if DeviceString is populated
if ((str_length(DeviceString) /= 0) and (str_imatch(DeviceString, "None") = FALSE)) then
Result(1 to imin(T_DEVICE_STRING'length, imax(1, DeviceString'length))) := ite((DeviceString'length > 0), DeviceString(1 to imin(T_DEVICE_STRING'length, DeviceString'length)), ConstNUL);
-- if MY_DEVICE is set, prefer it
elsif ((str_length(MY_DEVICE) /= 0) and (str_imatch(MY_DEVICE, "None") = FALSE)) then
Result(1 to imin(T_DEVICE_STRING'length, imax(1, MY_DEVICE'length))) := ite((MY_DEVICE'length > 0), MY_DEVICE(1 to imin(T_DEVICE_STRING'length, MY_DEVICE'length)), ConstNUL);
-- otherwise use MY_BOARD
else
Result(1 to imin(T_DEVICE_STRING'length, imax(1, MY_DEVICE_STR'length))) := ite((MY_DEVICE_STR'length > 0), MY_DEVICE_STR(1 to imin(T_DEVICE_STRING'length, MY_DEVICE_STR'length)), ConstNUL);
end if;
return Result;
end function;
-- helper function to create configuration strings
-- ===========================================================================
function conf(str : string; Size : POSITIVE) return STRING is
constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
variable Result : STRING(1 to Size);
-- inlined function from PoC.utils, to break dependency
function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is begin
if cond then return value1; else return value2; end if;
end function;
function imin(arg1 : integer; arg2 : integer) return integer is begin
if arg1 < arg2 then return arg1; else return arg2; end if;
end function;
function imax(arg1 : integer; arg2 : integer) return integer is begin
if arg1 > arg2 then return arg1; else return arg2; end if;
end function;
begin
Result := (others => C_POC_NUL);
if (str'length > 0) then
Result(1 to imin(Size, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(Size, str'length)), ConstNUL);
end if;
return Result;
end function;
function conf8(str : string) return T_BOARD_CONFIG_STRING8 is
begin
return conf(str, 8);
end function;
function conf16(str : string) return T_BOARD_CONFIG_STRING16 is
begin
return conf(str, 16);
end function;
function conf32(str : string) return T_BOARD_CONFIG_STRING32 is
begin
return conf(str, 32);
end function;
-- function conf64(str : string) return T_BOARD_CONFIG_STRING64 is
-- begin
-- return conf(str, 64);
-- end function;
function extractFirstNumber(str : STRING) return NATURAL is
variable low : integer;
variable high : integer;
variable Result : NATURAL;
variable Digit : INTEGER;
begin
low := -1;
high := -1;
for i in str'low to str'high loop
if chr_isDigit(str(i)) then
low := i;
exit;
end if;
end loop;
-- abort if no digit can be found
if (low = -1) then return 0; end if;
for i in (low + 1) to str'high loop
if chr_isAlpha(str(i)) then
high := i - 1;
exit;
end if;
end loop;
if (high = -1) then return 0; end if;
-- return INTEGER'value(str(low to high)); -- 'value(...) is not supported by Vivado Synth 2014.1
-- convert substring to a number
for i in low to high loop
if (chr_isDigit(str(i)) = FALSE) then
return -1;
end if;
Result := (Result * 10) + (character'pos(str(i)) - character'pos('0'));
end loop;
return Result;
end function;
-- predefined UART descriptions
function brd_CreateUART(IsDTE : BOOLEAN; FlowControl : STRING; BaudRate : STRING; BaudRate_Max : STRING := "") return T_BOARD_UART_DESC is
variable Result : T_BOARD_UART_DESC;
begin
Result.IsDTE := IsDTE;
Result.FlowControl := conf16(FlowControl);
Result.BaudRate := conf16(BaudRate);
Result.BaudRate_Max := conf16(BaudRate_Max);
return Result;
end function;
constant C_BOARD_UART_EMPTY : T_BOARD_UART_DESC := brd_CreateUART(TRUE, "NONE", "0 Bd");
constant C_BOARD_UART_DTE_115200_NONE : T_BOARD_UART_DESC := brd_CreateUART(TRUE, "NONE", "115.2 kBd");
constant C_BOARD_UART_DCE_115200_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "115.2 kBd");
constant C_BOARD_UART_DCE_115200_HWCTS : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "HW_CTS_RTS", "115.2 kBd");
constant C_BOARD_UART_DTE_460800_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "460.8 kBd");
constant C_BOARD_UART_DTE_921600_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "921.6 kBd");
function brd_CreateEthernet(IPStyle : STRING; RS_DataInt : STRING; PHY_Device : STRING; PHY_DevAddress : STD_LOGIC_VECTOR(7 downto 0); PHY_DataInt : STRING; PHY_MgntInt : STRING) return T_BOARD_ETHERNET_DESC is
variable Result : T_BOARD_ETHERNET_DESC;
begin
Result.IPStyle := conf8(IPStyle);
Result.RS_DataInterface := conf8(RS_DataInt);
Result.PHY_Device := conf16(PHY_Device);
Result.PHY_DeviceAddress := PHY_DevAddress;
Result.PHY_DataInterface := conf8(PHY_DataInt);
Result.PHY_ManagementInterface := conf16(PHY_MgntInt);
return Result;
end function;
constant C_BOARD_ETH_EMPTY : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("", "", "", x"00", "", "");
constant C_BOARD_ETH_SOFT_GMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"07", "GMII", "MDIO");
constant C_BOARD_ETH_HARD_GMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("HARD", "GMII", "MARVEL_88E1111", x"07", "GMII", "MDIO");
constant C_BOARD_ETH_SOFT_SGMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"07", "SGMII", "MDIO_OVER_IIC");
constant C_BOARD_ETH_NONE : T_BOARD_ETHERNET_DESC_VECTOR(T_BOARD_ETHERNET_DESC_INDEX) := (others => C_BOARD_ETH_EMPTY);
-- board description
-- ===========================================================================
CONSTANT C_BOARD_INFO_LIST : T_BOARD_INFO_VECTOR := (
-- Xilinx boards
-- =========================================================================
BOARD_S3SK200 => (
FPGADevice => conf32("XC3S200FT256"), -- XC2S200FT256
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
BOARD_S3SK1000 => (
FPGADevice => conf32("XC3S1000FT256"), -- XC2S200FT256
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
BOARD_S3ESK500 => (
FPGADevice => conf32("XC3S500EFT256"), -- XC2S200FT256
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
BOARD_S3ESK1600 => (
FPGADevice => conf32("XC3S1600EFT256"), -- XC2S200FT256
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
BOARD_ATLYS => (
FPGADevice => conf32("XC6SLX45-3CSG324"), -- XC6SLX45-3CSG324
UART => C_BOARD_UART_DTE_460800_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),
BOARD_KC705 => (
FPGADevice => conf32("XC7K325T-2FFG900C"), -- XC7K325T-2FFG900C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => (
0 => C_BOARD_ETH_SOFT_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),
BOARD_ML505 => (
FPGADevice => conf32("XC5VLX50T-1FF1136"), -- XC5VLX50T-1FF1136
UART => C_BOARD_UART_DCE_115200_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),
BOARD_ML605 => (
FPGADevice => conf32("XC6VLX240T-1FF1156"), -- XC6VLX240T-1FF1156
UART => C_BOARD_UART_EMPTY,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),
BOARD_VC707 => (
FPGADevice => conf32("XC7VX485T-2FFG1761C"), -- XC7VX485T-2FFG1761C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => (
0 => C_BOARD_ETH_SOFT_SGMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),
BOARD_ZEDBOARD => (
FPGADevice => conf32("XC7Z020-1CLG484"), -- XC7Z020-1CLG484
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
-- Altera boards
-- =========================================================================
BOARD_DE0 => (
FPGADevice => conf32("EP3C16F484"), -- EP3C16F484
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
BOARD_S2GXAV => (
FPGADevice => conf32("EP2SGX90FF1508C3"), -- EP2SGX90FF1508C3
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
BOARD_DE4 => (
FPGADevice => conf32("EP4SGX230KF40C2"), -- EP4SGX230KF40C2
UART => C_BOARD_UART_DTE_460800_NONE,
Ethernet => (
0 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"00", "RGMII", "MDIO"),
1 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"01", "RGMII", "MDIO"),
2 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"02", "RGMII", "MDIO"),
3 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"03", "RGMII", "MDIO"),
others => C_BOARD_ETH_EMPTY
),
EthernetCount => 4
),
BOARD_DE5 => (
FPGADevice => conf32("EP5SGXEA7N2F45C2"), -- EP5SGXEA7N2F45C2
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
-- custom board / dummy entry
BOARD_CUSTOM => (
FPGADevice => conf32("Device is unknown for a custom board"),
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
)
);
-- Public functions
-- ===========================================================================
-- TODO: comment
function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return T_BOARD is
-- inlined function from PoC.utils, to break dependency
function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is begin
if cond then return value1; else return value2; end if;
end function;
constant MY_BRD : T_BOARD_STRING := ite((BoardConfig /= C_BOARD_STRING_EMPTY), conf(BoardConfig, T_BOARD_STRING'length), conf(MY_BOARD, T_BOARD_STRING'length));
begin
if (POC_VERBOSE = TRUE) then
report "PoC configuration: Used board is '" & str_trim(MY_BRD) & "'" severity NOTE;
end if;
for i in T_BOARD loop
if str_imatch(T_BOARD'image(i), "BOARD_" & str_trim(MY_BRD)) then
return i;
end if;
end loop;
report "Unknown board name in MY_BOARD = " & MY_BRD & "." severity failure;
return BOARD_CUSTOM;
end function;
function BOARD_INFO(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return T_BOARD_INFO is
constant BRD : T_BOARD := BOARD(BoardConfig);
begin
return C_BOARD_INFO_LIST(BRD);
end function;
-- TODO: comment
function BOARD_DEVICE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING is
constant BRD : T_BOARD := BOARD(BoardConfig);
begin
return str_trim(C_BOARD_INFO_LIST(BRD).FPGADevice);
end function;
function BOARD_UART_BAUDRATE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING is
constant BRD : T_BOARD := BOARD(BoardConfig);
begin
return str_trim(C_BOARD_INFO_LIST(BRD).UART.BaudRate);
end function;
-- purpose: extract vendor from MY_DEVICE
function VENDOR(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_VENDOR is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN_STR : string(1 to 2) := MY_DEV(1 to 2);
begin
case VEN_STR is
when "XC" => return VENDOR_XILINX;
when "EP" => return VENDOR_ALTERA;
when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function SYNTHESIS_TOOL(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_SYNTHESIS_TOOL is
constant VEN : T_VENDOR := VENDOR(DeviceString);
begin
case VEN is
when VENDOR_ALTERA =>
return SYNTHESIS_TOOL_ALTERA_QUARTUS2;
when VENDOR_LATTICE =>
return SYNTHESIS_TOOL_SYNOPSIS;
when VENDOR_XILINX =>
if (1 fs /= 1 us) then
return SYNTHESIS_TOOL_XILINX_XST;
else
return SYNTHESIS_TOOL_XILINX_VIVADO;
end if;
end case;
end function;
-- purpose: extract device from MY_DEVICE
function DEVICE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN : T_VENDOR := VENDOR(DeviceString);
constant DEV_STR : string(3 to 4) := MY_DEV(3 to 4);
begin
case VEN is
when VENDOR_ALTERA =>
case DEV_STR is
when "1C" => return DEVICE_CYCLONE1;
when "2C" => return DEVICE_CYCLONE2;
when "3C" => return DEVICE_CYCLONE3;
when "1S" => return DEVICE_STRATIX1;
when "2S" => return DEVICE_STRATIX2;
when "4S" => return DEVICE_STRATIX4;
when "5S" => return DEVICE_STRATIX5;
when others => report "Unknown Altera device in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when VENDOR_XILINX =>
case DEV_STR is
when "7A" => return DEVICE_ARTIX7;
when "7K" => return DEVICE_KINTEX7;
when "3S" => return DEVICE_SPARTAN3;
when "6S" => return DEVICE_SPARTAN6;
when "5V" => return DEVICE_VIRTEX5;
when "6V" => return DEVICE_VIRTEX6;
when "7V" => return DEVICE_VIRTEX7;
when "7Z" => return DEVICE_ZYNQ7;
when others => report "Unknown Xilinx device in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when others => report "Unknown vendor in MY_DEVICE = " & MY_DEV & "." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
-- purpose: extract device from MY_DEVICE
function DEVICE_FAMILY(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_FAMILY is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN : T_VENDOR := VENDOR(DeviceString);
constant FAM_CHAR : character := MY_DEV(4);
begin
case VEN is
when VENDOR_ALTERA =>
case FAM_CHAR is
when 'C' => return DEVICE_FAMILY_CYCLONE;
when 'S' => return DEVICE_FAMILY_STRATIX;
when others => report "Unknown Altera device family in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when VENDOR_XILINX =>
case FAM_CHAR is
when 'A' => return DEVICE_FAMILY_ARTIX;
when 'K' => return DEVICE_FAMILY_KINTEX;
when 'S' => return DEVICE_FAMILY_SPARTAN;
when 'V' => return DEVICE_FAMILY_VIRTEX;
when 'Z' => return DEVICE_FAMILY_ZYNQ;
when others => report "Unknown Xilinx device family in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function DEVICE_SERIES(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(DeviceString);
begin
case DEV is
when DEVICE_ARTIX7 | DEVICE_KINTEX7 | DEVICE_VIRTEX7 | DEVICE_ZYNQ7 => return 7; -- all Xilinx ****7 devices share some common features: e.g. XADC
when others => return 0;
end case;
end function;
function DEVICE_NUMBER(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN : T_VENDOR := VENDOR(DeviceString);
begin
case VEN is
when VENDOR_ALTERA => return extractFirstNumber(MY_DEV(5 to MY_DEV'high));
when VENDOR_XILINX => return extractFirstNumber(MY_DEV(5 to MY_DEV'high));
when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function DEVICE_SUBTYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return t_device_subtype is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(MY_DEV);
constant DEV_SUB_STR : string(1 to 2) := MY_DEV(5 to 6); -- work around for GHDL
begin
case DEV is
when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 => return DEVICE_SUBTYPE_NONE; -- Altera Cyclon I, II, III devices have no subtype
when DEVICE_STRATIX2 =>
if chr_isDigit(DEV_SUB_STR(1)) then return DEVICE_SUBTYPE_NONE;
elsif (DEV_SUB_STR = "GX") then return DEVICE_SUBTYPE_GX;
else report "Unknown Stratix II subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_STRATIX4 =>
if (DEV_SUB_STR(1) = 'E') then return DEVICE_SUBTYPE_E;
elsif (DEV_SUB_STR = "GX") then return DEVICE_SUBTYPE_GX;
-- elsif (DEV_SUB_STR = "GT") then return DEVICE_SUBTYPE_GT;
else report "Unknown Stratix II subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_SPARTAN3 => report "TODO: parse Spartan3 / Spartan3E / Spartan3AN device subtype." severity failure;
when DEVICE_SPARTAN6 =>
if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX;
elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT;
else report "Unknown Virtex-5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_VIRTEX5 =>
if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX;
elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT;
elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT;
elsif ((DEV_SUB_STR = "TX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_TXT;
elsif ((DEV_SUB_STR = "FX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_FXT;
else report "Unknown Virtex-5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_VIRTEX6 =>
if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX;
elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT;
elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT;
elsif ((DEV_SUB_STR = "CX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_CXT;
elsif ((DEV_SUB_STR = "HX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HXT;
else report "Unknown Virtex-6 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_ARTIX7 =>
if ( ( str_find(MY_DEV(5 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T;
else report "Unknown Artix-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_KINTEX7 =>
if ( ( str_find(MY_DEV(5 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T;
else report "Unknown Kintex-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_VIRTEX7 =>
if ( ( str_find(MY_DEV(5 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T;
elsif ((DEV_SUB_STR(1) = 'X') and ( str_find(MY_DEV(6 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_XT;
elsif ((DEV_SUB_STR(1) = 'H') and ( str_find(MY_DEV(6 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HT;
else report "Unknown Virtex-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when others => report "Transceiver type is unknown for the given device." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function LUT_FANIN(DeviceString : string := C_DEVICE_STRING_EMPTY) return positive is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(DeviceString);
begin
case DEV is
when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 => return 4;
when DEVICE_STRATIX1 | DEVICE_STRATIX2 => return 4;
when DEVICE_STRATIX4 | DEVICE_STRATIX5 => return 6;
when DEVICE_SPARTAN3 => return 4;
when DEVICE_SPARTAN6 => return 6;
when DEVICE_ARTIX7 => return 6;
when DEVICE_KINTEX7 => return 6;
when DEVICE_VIRTEX5 | DEVICE_VIRTEX6 | DEVICE_VIRTEX7 => return 6;
when DEVICE_ZYNQ7 => return 6;
when others => report "LUT fan-in is unknown for the given device." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function TRANSCEIVER_TYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_TRANSCEIVER is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(DeviceString);
constant DEV_NUM : natural := DEVICE_NUMBER(DeviceString);
constant DEV_SUB : t_device_subtype := DEVICE_SUBTYPE(DeviceString);
begin
case DEV is
when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 => return TRANSCEIVER_NONE; -- Altera Cyclon I, II, III devices have no transceivers
when DEVICE_SPARTAN3 => return TRANSCEIVER_NONE; -- Xilinx Spartan3 devices have no transceivers
when DEVICE_SPARTAN6 =>
case DEV_SUB is
when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE;
when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTPE1;
when others => report "Unknown Spartan-6 subtype: " & t_device_subtype'image(DEV_SUB) severity failure;
end case;
when DEVICE_VIRTEX5 =>
case DEV_SUB is
when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE;
when DEVICE_SUBTYPE_SXT => return TRANSCEIVER_GTP_DUAL;
when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTP_DUAL;
when DEVICE_SUBTYPE_TXT => return TRANSCEIVER_GTX;
when DEVICE_SUBTYPE_FXT => return TRANSCEIVER_GTX;
when others => report "Unknown Virtex-5 subtype: " & t_device_subtype'image(DEV_SUB) severity failure;
end case;
when DEVICE_VIRTEX6 =>
case DEV_SUB is
when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE;
when DEVICE_SUBTYPE_SXT => return TRANSCEIVER_GTXE1;
when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTXE1;
when DEVICE_SUBTYPE_HXT => return TRANSCEIVER_GTXE1;
when others => report "Unknown Virtex-6 subtype: " & t_device_subtype'image(DEV_SUB) severity failure;
end case;
when DEVICE_ARTIX7 => return TRANSCEIVER_GTPE2;
when DEVICE_KINTEX7 => return TRANSCEIVER_GTXE2;
when DEVICE_VIRTEX7 =>
case DEV_SUB is
when DEVICE_SUBTYPE_T => return TRANSCEIVER_GTXE2;
when DEVICE_SUBTYPE_XT =>
if (DEV_NUM = 485) then return TRANSCEIVER_GTXE2;
else return TRANSCEIVER_GTHE2;
end if;
when DEVICE_SUBTYPE_HT => return TRANSCEIVER_GTHE2;
when others => report "Unknown Virtex-7 subtype: " & t_device_subtype'image(DEV_SUB) severity failure;
end case;
when DEVICE_STRATIX2 => return TRANSCEIVER_GXB;
when DEVICE_STRATIX4 => return TRANSCEIVER_GXB;
when others => report "Unknown device." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
-- purpose: extract architecture properties from DEVICE
function DEVICE_INFO(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_INFO is
variable Result : T_DEVICE_INFO;
begin
Result.Vendor := VENDOR(DeviceString);
Result.Device := DEVICE(DeviceString);
Result.DevFamily := DEVICE_FAMILY(DeviceString);
Result.DevNumber := DEVICE_NUMBER(DeviceString);
Result.DevSubType := DEVICE_SUBTYPE(DeviceString);
Result.DevSeries := DEVICE_SERIES(DeviceString);
Result.TransceiverType := TRANSCEIVER_TYPE(DeviceString);
Result.LUT_FanIn := LUT_FANIN(DeviceString);
return Result;
end function;
function ARCH_PROPS return archprops_t is
variable result : archprops_t;
begin
result.LUT_K := LUT_FANIN;
return result;
end function;
-- force FSM to predefined encoding in debug mode
function getFSMEncoding_gray(debug : BOOLEAN) return STRING is
begin
if (debug = true) then
return "gray";
else
case VENDOR is
when VENDOR_XILINX => return "auto";
when VENDOR_ALTERA => return "default";
when others => report "Unknown vendor." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end if;
end function;
end package body;
| apache-2.0 | e8072b3b46758d8683c983d7699a8fcc | 0.630411 | 3.276166 | false | true | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_green_leds.vhd | 1 | 2,868 | --Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tracking_camera_system_green_leds is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal chipselect : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal write_n : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal out_port : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity tracking_camera_system_green_leds;
architecture europa of tracking_camera_system_green_leds is
signal clk_en : STD_LOGIC;
signal data_out : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal read_mux_out : STD_LOGIC_VECTOR (7 DOWNTO 0);
begin
clk_en <= std_logic'('1');
--s1, which is an e_avalon_slave
read_mux_out <= A_REP(to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000")))), 8) AND data_out;
process (clk, reset_n)
begin
if reset_n = '0' then
data_out <= std_logic_vector'("00000000");
elsif clk'event and clk = '1' then
if std_logic'(((chipselect AND NOT write_n) AND to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000")))))) = '1' then
data_out <= writedata(7 DOWNTO 0);
end if;
end if;
end process;
readdata <= std_logic_vector'("00000000000000000000000000000000") OR (std_logic_vector'("000000000000000000000000") & (read_mux_out));
out_port <= data_out;
end europa;
| gpl-2.0 | 0d0884bfb81d666412a1ed5f0be149e5 | 0.67643 | 4.156522 | false | false | false | false |
hoglet67/ElectronFpga | src/common/ElectronULA.vhd | 1 | 68,622 | --------------------------------------------------------------------------------
-- Copyright (c) 2020 David Banks
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : ElectronULA.vhd
-- /___/ /\ Timestamp : 27/06/2020
-- \ \ / \
-- \___\/\___\
--
--Design Name: ElectronULA
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ElectronULA is
generic (
IncludeMMC : boolean := true;
Include32KRAM : boolean := true;
IncludeVGA : boolean := true;
IncludeJafaMode7 : boolean := false;
LimitROMSpeed : boolean := true; -- true to limit ROM speed to 2MHz
LimitIOSpeed : boolean := true; -- true to limit IO speed to 1MHz
UseClockMux : boolean := false; -- false for Xilinx, true for Altera
UseTTxtClock : boolean := false; -- true to use clk_ttxt/clken_ttxt_12M, false to use clk_24M00
IncludeTTxtROM : boolean := true -- false if the SAA5050 character ROM needs loading
);
port (
clk_16M00 : in std_logic;
clk_24M00 : in std_logic := '0';
clk_ttxt : in std_logic := '0';
clk_32M00 : in std_logic;
clk_33M33 : in std_logic;
clk_40M00 : in std_logic;
clken_ttxt_12M : in std_logic := '0';
-- CPU Interface
addr : in std_logic_vector(15 downto 0);
data_in : in std_logic_vector(7 downto 0); -- Async, but stable on rising edge of cpu_clken
data_out : out std_logic_vector(7 downto 0);
data_en : out std_logic;
R_W_n : in std_logic;
RST_n : in std_logic;
IRQ_n : out std_logic;
NMI_n : in std_logic;
-- Rom Enable
ROM_n : out std_logic;
-- Video
red : out std_logic_vector(3 downto 0);
green : out std_logic_vector(3 downto 0);
blue : out std_logic_vector(3 downto 0);
vsync : out std_logic;
hsync : out std_logic;
-- Audio
sound : out std_logic;
-- Keyboard
kbd : in std_logic_vector(3 downto 0); -- Async
-- SD Card
SDMISO : in std_logic;
SDSS : out std_logic;
SDCLK : out std_logic;
SDMOSI : out std_logic;
-- Casette
casIn : in std_logic;
casOut : out std_logic;
-- MISC
caps : out std_logic;
motor : out std_logic;
rom_latch : out std_logic_vector(3 downto 0);
mode_init : in std_logic_vector(1 downto 0);
-- Clock Generation
cpu_clken_out : out std_logic;
cpu_clk_out : out std_logic;
turbo : in std_logic_vector(1 downto 0);
turbo_out : out std_logic_vector(1 downto 0) := "01";
-- SAA5050 character ROM loading
char_rom_we : in std_logic := '0';
char_rom_addr : in std_logic_vector(11 downto 0) := (others => '0');
char_rom_data : in std_logic_vector(7 downto 0) := (others => '0')
);
end;
architecture behavioral of ElectronULA is
signal hsync_int : std_logic;
signal hsync_int_last : std_logic;
signal vsync_int : std_logic;
signal ram_we : std_logic;
signal ram_data : std_logic_vector(7 downto 0);
signal master_irq : std_logic;
signal power_on_reset : std_logic := '1';
signal delayed_clear_reset : std_logic := '0';
signal rtc_counter : std_logic_vector(18 downto 0);
signal general_counter: std_logic_vector(15 downto 0);
signal sound_bit : std_logic;
signal isr_data : std_logic_vector(7 downto 0);
-- ULA Registers
signal isr : std_logic_vector(6 downto 2);
signal ier : std_logic_vector(6 downto 2);
signal screen_base : std_logic_vector(14 downto 6);
signal data_shift : std_logic_vector(7 downto 0);
signal page_enable : std_logic;
signal page : std_logic_vector(2 downto 0);
signal counter : std_logic_vector(7 downto 0);
signal display_mode : std_logic_vector(2 downto 0);
signal comms_mode : std_logic_vector(1 downto 0);
type palette_type is array (0 to 7) of std_logic_vector (7 downto 0);
signal palette : palette_type;
signal hsync_start : std_logic_vector(10 downto 0);
signal hsync_end : std_logic_vector(10 downto 0);
signal h_active : std_logic_vector(10 downto 0);
signal h_total : std_logic_vector(10 downto 0);
signal h_count : std_logic_vector(10 downto 0);
signal h_count1 : std_logic_vector(10 downto 0);
signal vsync_start : std_logic_vector(9 downto 0);
signal vsync_end : std_logic_vector(9 downto 0);
signal v_active_gph : std_logic_vector(9 downto 0);
signal v_active_txt : std_logic_vector(9 downto 0);
signal v_total : std_logic_vector(9 downto 0);
signal v_count : std_logic_vector(9 downto 0);
signal v_rtc : std_logic_vector(9 downto 0);
signal v_disp_gph : std_logic_vector(9 downto 0);
signal v_disp_txt : std_logic_vector(9 downto 0);
signal char_row : std_logic_vector(3 downto 0);
signal col_offset : std_logic_vector(9 downto 0);
signal screen_addr : std_logic_vector(14 downto 0);
signal screen_data : std_logic_vector(7 downto 0);
-- Screen Mode Registers
signal mode : std_logic_vector(1 downto 0);
-- bits 6..3 the of the 256 byte page that the mode starts at
signal mode_base : std_logic_vector(6 downto 3);
-- the number of bits per pixel (0 = 1BPP, 1 = 2BPP, 2=4BPP)
signal mode_bpp : std_logic_vector(1 downto 0);
-- a '1' indicates a text mode (modes 3 and 6)
signal mode_text : std_logic;
-- a '1' indicates a 40-col mode (modes 4, 5 and 6)
signal mode_40 : std_logic;
signal last_line : std_logic;
signal display_intr : std_logic;
signal display_intr1 : std_logic;
signal display_intr2 : std_logic;
signal rtc_intr : std_logic;
signal rtc_intr1 : std_logic;
signal rtc_intr2 : std_logic;
signal clk_video : std_logic;
signal ctrl_caps : std_logic;
signal field : std_logic;
signal caps_int : std_logic;
signal motor_int : std_logic;
-- Supports changing the jumpers
signal mode_init_copy : std_logic_vector(1 downto 0);
-- Tape Interface
signal cintone : std_logic;
signal cindat : std_logic;
signal cinbits : std_logic_vector(3 downto 0);
signal coutbits : std_logic_vector(3 downto 0);
signal casIn1 : std_logic;
signal casIn2 : std_logic;
signal casIn3 : std_logic;
signal ignore_next : std_logic;
-- internal RGB signals before final mux
signal red_int : std_logic_vector(3 downto 0);
signal green_int : std_logic_vector(3 downto 0);
signal blue_int : std_logic_vector(3 downto 0);
-- CRTC signals (only used when Jafa Mode 7 is enabled)
signal crtc_enable : std_logic;
signal crtc_clken : std_logic;
signal crtc_do : std_logic_vector(7 downto 0);
signal crtc_vsync : std_logic;
signal crtc_vsync_n : std_logic;
signal crtc_hsync : std_logic;
signal crtc_hsync_n : std_logic;
signal crtc_de : std_logic;
signal crtc_cursor : std_logic;
signal crtc_cursor1 : std_logic;
signal crtc_cursor2 : std_logic;
signal crtc_ma : std_logic_vector(13 downto 0);
signal crtc_ra : std_logic_vector(4 downto 0);
signal status_enable : std_logic;
signal status_do : std_logic_vector(7 downto 0);
-- SAA5050 signals (only used when Jafa Mode 7 is enabled)
signal ttxt_clock : std_logic;
signal ttxt_clken : std_logic;
signal ttxt_glr : std_logic;
signal ttxt_dew : std_logic;
signal ttxt_crs : std_logic;
signal ttxt_lose : std_logic;
signal ttxt_r_int : std_logic;
signal ttxt_g_int : std_logic;
signal ttxt_b_int : std_logic;
signal ttxt_r : std_logic;
signal ttxt_g : std_logic;
signal ttxt_b : std_logic;
signal ttxt_r_out : std_logic;
signal ttxt_g_out : std_logic;
signal ttxt_b_out : std_logic;
signal ttxt_hs_out : std_logic;
signal ttxt_vs_out : std_logic;
signal mist_r : std_logic_vector(1 downto 0);
signal mist_g : std_logic_vector(1 downto 0);
signal mist_b : std_logic_vector(1 downto 0);
signal mist_hs : std_logic;
signal mist_vs : std_logic;
signal mode7_enable : std_logic;
-- internal signals to generate the video clock
signal clk_16M00_a : std_logic;
signal clk_16M00_b : std_logic;
signal clk_16M00_c : std_logic;
signal clk_33M33_a : std_logic;
signal clk_33M33_b : std_logic;
signal clk_33M33_c : std_logic;
signal clk_40M00_a : std_logic;
signal clk_40M00_b : std_logic;
signal clk_40M00_c : std_logic;
signal ROM_n_int : std_logic;
-- clock enable generation
signal clken_counter : std_logic_vector (3 downto 0) := (others => '0');
signal turbo_sync : std_logic_vector (1 downto 0);
signal contention : std_logic;
signal contention1 : std_logic;
signal contention2 : std_logic;
signal io_access : std_logic; -- always at 1MHz, no contention
signal rom_access : std_logic; -- always at 2MHz, no contention
signal ram_access : std_logic; -- 1MHz/2MHz/Stopped
signal kbd_access : std_logic;
signal clk_stopped : std_logic_vector(1 downto 0) := "00";
signal cpu_clken : std_logic;
signal via1_clken : std_logic;
signal via4_clken : std_logic;
signal cpu_clk : std_logic := '1';
signal clk_counter : std_logic_vector(2 downto 0) := (others => '0');
signal mc6522_enable : std_logic;
signal mc6522_data : std_logic_vector(7 downto 0);
signal mc6522_data_r : std_logic_vector(7 downto 0);
signal mc6522_irq_n : std_logic;
-- Port A is not really used, so signals directly loop back out to in
signal mc6522_ca2 : std_logic;
signal mc6522_porta : std_logic_vector(7 downto 0);
-- Port B is used for the MMBEEB style SDCard Interface
signal mc6522_cb1_in : std_logic;
signal mc6522_cb1_out : std_logic;
signal mc6522_cb1_oe_l : std_logic;
signal mc6522_cb2_in : std_logic;
signal mc6522_portb_in : std_logic_vector(7 downto 0);
signal mc6522_portb_out : std_logic_vector(7 downto 0);
signal mc6522_portb_oe_l : std_logic_vector(7 downto 0);
signal sdclk_int : std_logic;
signal ula_irq_n : std_logic;
-- Helper function to cast an std_logic value to an integer
function sl2int (x: std_logic) return integer is
begin
if x = '1' then
return 1;
else
return 0;
end if;
end;
-- Helper function to cast an std_logic_vector value to an integer
function slv2int (x: std_logic_vector) return integer is
begin
return to_integer(unsigned(x));
end;
begin
-- video timing constants
-- mode 00 - RGB/s @ 50Hz non-interlaced
-- mode 01 - RGB/s @ 50Hz interlaced
-- mode 10 - SVGA @ 50Hz
-- mode 11 - SVGA @ 60Hz
gen_clk_mux : if UseClockMux generate
-- A simple clock mux causes lots of warnings from the Xilinx tool,
-- but is OK with Quartus.
clk_video <= clk_40M00 when mode = "11" else
clk_33M33 when mode = "10" else
clk_16M00;
end generate;
gen_clk_with_flops : if not UseClockMux generate
-- Regenerate the clock using edge triggered flip flops on Xilinx.
process(clk_16M00)
begin
if rising_edge(clk_16M00) then
clk_16M00_a <= not clk_16M00_a;
end if;
end process;
process(clk_16M00)
begin
if falling_edge(clk_16M00) then
clk_16M00_b <= not clk_16M00_b;
end if;
end process;
clk_16M00_c <= clk_16M00_a xor clk_16M00_b;
process(clk_33M33)
begin
if rising_edge(clk_33M33) then
clk_33M33_a <= not clk_33M33_a;
end if;
end process;
process(clk_33M33)
begin
if falling_edge(clk_33M33) then
clk_33M33_b <= not clk_33M33_b;
end if;
end process;
clk_33M33_c <= clk_33M33_a xor clk_33M33_b;
process(clk_40M00)
begin
if rising_edge(clk_40M00) then
clk_40M00_a <= not clk_40M00_a;
end if;
end process;
process(clk_40M00)
begin
if falling_edge(clk_40M00) then
clk_40M00_b <= not clk_40M00_b;
end if;
end process;
clk_40M00_c <= clk_40M00_a xor clk_40M00_b;
clk_video <= clk_40M00_c when mode = "11" and IncludeVGA else
clk_33M33_c when mode = "10" and IncludeVGA else
clk_16M00_c;
end generate;
hsync_start <= std_logic_vector(to_unsigned(759, 11)) when mode = "11" and IncludeVGA else
std_logic_vector(to_unsigned(759, 11)) when mode = "10" and IncludeVGA else
std_logic_vector(to_unsigned(768, 11));
hsync_end <= std_logic_vector(to_unsigned(887, 11)) when mode = "11" and IncludeVGA else
std_logic_vector(to_unsigned(887, 11)) when mode = "10" and IncludeVGA else
std_logic_vector(to_unsigned(832, 11));
h_total <= std_logic_vector(to_unsigned(1055, 11)) when mode = "11" and IncludeVGA else
std_logic_vector(to_unsigned(1055, 11)) when mode = "10" and IncludeVGA else
std_logic_vector(to_unsigned(1023, 11));
h_active <= std_logic_vector(to_unsigned(640, 11));
-- Note: The real ULA uses line 281->283/4 for VSYNC, but on both
-- my TVs this loses part of the top line. So here we move the
-- screen down by 7 rows. This should be transparent to software,
-- as it doesn't affect the timing of the display or RTC
-- interrupts. I'm happy to rever this is anyone complains!
vsync_start <= std_logic_vector(to_unsigned(556, 10)) when mode = "11" and IncludeVGA else
std_logic_vector(to_unsigned(556, 10)) when mode = "10" and IncludeVGA else
std_logic_vector(to_unsigned(274, 10));
vsync_end <= std_logic_vector(to_unsigned(560, 10)) when mode = "11" and IncludeVGA else
std_logic_vector(to_unsigned(560, 10)) when mode = "10" and IncludeVGA else
std_logic_vector(to_unsigned(276, 10)) when field = '0' else
std_logic_vector(to_unsigned(277, 10));
v_total <= std_logic_vector(to_unsigned(627, 10)) when mode = "11" and IncludeVGA else
std_logic_vector(to_unsigned(627, 10)) when mode = "10" and IncludeVGA else
std_logic_vector(to_unsigned(311, 10)) when field = '0' else
std_logic_vector(to_unsigned(312, 10));
v_active_gph <= std_logic_vector(to_unsigned(512, 10)) when mode = "11" and IncludeVGA else
std_logic_vector(to_unsigned(512, 10)) when mode = "10" and IncludeVGA else
std_logic_vector(to_unsigned(256, 10));
v_active_txt <= std_logic_vector(to_unsigned(500, 10)) when mode = "11" and IncludeVGA else
std_logic_vector(to_unsigned(500, 10)) when mode = "10" and IncludeVGA else
std_logic_vector(to_unsigned(250, 10));
v_disp_gph <= std_logic_vector(to_unsigned(513, 10)) when mode = "11" and IncludeVGA else
std_logic_vector(to_unsigned(513, 10)) when mode = "10" and IncludeVGA else
std_logic_vector(to_unsigned(255, 10));
v_disp_txt <= std_logic_vector(to_unsigned(501, 10)) when mode = "11" and IncludeVGA else
std_logic_vector(to_unsigned(501, 10)) when mode = "10" and IncludeVGA else
std_logic_vector(to_unsigned(249, 10));
v_rtc <= std_logic_vector(to_unsigned(201, 10)) when mode = "11" and IncludeVGA else
std_logic_vector(to_unsigned(201, 10)) when mode = "10" and IncludeVGA else
std_logic_vector(to_unsigned( 99, 10));
-- All of main memory (0x0000-0x7fff) is dual port RAM in the ULA
ram_32k_gen: if Include32KRAM generate
ram_32k : entity work.RAM_32K_DualPort port map(
-- Port A is the 6502 port
clka => clk_16M00,
wea => ram_we,
addra => addr(14 downto 0),
dina => data_in,
douta => ram_data,
-- Port B is the VGA Port
clkb => clk_video,
web => '0',
addrb => screen_addr,
dinb => x"00",
doutb => screen_data
);
ram_we <= '1' when addr(15) = '0' and R_W_n = '0' and cpu_clken = '1' else '0';
end generate;
-- Just screen memory (0x3000-0x7fff) is dual port RAM in the ULA
ram_20k_gen: if not Include32KRAM generate
-- xor'ing with 7000 maps 3000-7fff into range 0000-4fff
ram_20k : entity work.RAM_20K_DualPort port map(
-- Port A is the 6502 port
clka => clk_16M00,
wea => ram_we,
addra => addr(14 downto 0) xor "111000000000000",
dina => data_in,
douta => ram_data,
-- Port B is the VGA Port
clkb => clk_video,
web => '0',
addrb => screen_addr xor "111000000000000",
dinb => x"00",
doutb => screen_data
);
ram_we <= '1' when (addr(15 downto 12) = "0011" or addr(15 downto 14) = "01") and R_W_n = '0' and cpu_clken = '1' else '0';
end generate;
sound <= sound_bit;
-- The external ROM is enabled:
-- - When the address is C000-FBFF and FF00-FFFF (i.e. OS Rom)
-- - When the address is 8000-BFFF and the ROM 10 or 11 is paged in (101x)
ROM_n_int <= '0' when addr(15 downto 14) = "11" and io_access = '0' else
'0' when addr(15 downto 14) = "10" and page_enable = '1' and page(2 downto 1) = "01" else
'1';
ROM_n <= ROM_n_int;
-- ULA Reads + RAM Reads + KBD Reads
data_out <= ram_data when addr(15) = '0' else
"0000" & (kbd xor "1111") when kbd_access = '1' else
isr_data when addr(15 downto 8) = x"FE" and addr(3 downto 0) = x"0" else
data_shift when addr(15 downto 8) = x"FE" and addr(3 downto 0) = x"4" else
crtc_do when crtc_enable = '1' and IncludeJafaMode7 else
status_do when status_enable = '1' and IncludeJafaMode7 else
mc6522_data_r when mc6522_enable = '1' and IncludeMMC else
x"F1"; -- todo FIXEME
data_en <= '1' when addr(15) = '0' else
'1' when kbd_access = '1' else
'1' when addr(15 downto 8) = x"FE" else
'1' when crtc_enable = '1' and IncludeJafaMode7 else
'1' when status_enable = '1' and IncludeJafaMode7 else
'1' when mc6522_enable = '1' and IncludeMMC else
'0';
-- Register FEx0 is the Interrupt Status Register (Read Only)
-- Bit 7 always reads as 1
-- Bits 6..2 refect in interrups status regs
-- Bit 1 is the power up reset bit, cleared by the first read after power up
-- Bit 0 is the OR of bits 6..2
master_irq <= (isr(6) and ier(6)) or
(isr(5) and ier(5)) or
(isr(4) and ier(4)) or
(isr(3) and ier(3)) or
(isr(2) and ier(2));
ula_irq_n <= not master_irq;
isr_data <= '1' & isr(6 downto 2) & power_on_reset & master_irq;
rom_latch <= page_enable & page;
process (clk_16M00, RST_n)
begin
if rising_edge(clk_16M00) then
if (RST_n = '0') then
isr <= (others => '0');
ier <= (others => '0');
screen_base <= (others => '0');
data_shift <= (others => '0');
page_enable <= '0';
page <= (others => '0');
counter <= (others => '0');
comms_mode <= "01";
motor_int <= '0';
caps_int <= '0';
rtc_counter <= (others => '0');
general_counter <= (others => '0');
sound_bit <= '0';
mode <= mode_init;
mode_init_copy <= mode_init;
ctrl_caps <= '0';
cindat <= '0';
cintone <= '0';
else
-- Detect Jumpers being changed
if (mode_init_copy /= mode_init) then
mode <= mode_init;
mode_init_copy <= mode_init;
end if;
-- Synchronize the display interrupt signal from the VGA clock domain
display_intr1 <= display_intr;
display_intr2 <= display_intr1;
-- Generate the display end interrupt on the rising edge (line 256 of the screen)
if (display_intr2 = '0' and display_intr1 = '1') then
isr(2) <= '1';
end if;
-- Synchronize the rtc interrupt signal from the VGA clock domain
rtc_intr1 <= rtc_intr;
rtc_intr2 <= rtc_intr1;
if mode = "11" and IncludeVGA then
-- For 60Hz frame rates we must synthesise a the 50Hz real time clock interrupt
-- In theory the counter limit should be 319999, but there are additional
-- rtc ticks if not rtc interrupt is received between two display interrupts
-- hence the correction factor of 6/5. This comes from the probability
-- of the there not being a 50Hz rtc interrupts between any two successive
-- 60Hz display interrupts.
if (rtc_counter = 383999) then
rtc_counter <= (others => '0');
isr(3) <= '1';
else
rtc_counter <= rtc_counter + 1;
end if;
else
-- Generate the rtc interrupt on the rising edge (line 100 of the screen)
if (rtc_intr2 = '0' and rtc_intr1 = '1') then
isr(3) <= '1';
end if;
end if;
if (comms_mode = "00") then
-- Cassette In Mode
if (casIn2 = '0') then
general_counter <= (others => '0');
else
general_counter <= general_counter + 1;
end if;
elsif (comms_mode = "01") then
-- Sound Mode - Frequency = 1MHz / [16 * (S + 1)]
if (general_counter = 0) then
general_counter <= counter & "00000000";
sound_bit <= not sound_bit;
else
general_counter <= general_counter - 1;
end if;
elsif (comms_mode = "10") then
-- Cassette Out Mode
-- Bit 12 is at 2404Hz
-- Bit 13 is at 1202Hz
if (general_counter(11 downto 0) = 0) then
general_counter <= general_counter - x"301";
else
general_counter <= general_counter - x"001";
end if;
end if;
-- Tape Interface Receive
casIn1 <= casIn;
casIn2 <= casIn1;
casIn3 <= casIn2;
if (comms_mode = "00" and motor_int = '1') then
-- Only take actions on the falling edge of casIn
-- On the falling edge, general_counter will contain length of
-- the previous high pulse in 16MHz cycles.
-- A 1200Hz pulse is 6666 cycles
-- A 2400Hz pulse is 3333 cycles
-- A threshold in between would be 5000 cycles.
-- Ignore pulses shorter then say 500 cycles as these are
-- probably just noise.
if (casIn3 = '1' and casIn2 = '0' and general_counter > 500) then
-- a Pulse of length > 500 cycles has been detected
if (cindat = '0' and cintone = '0' and general_counter <= 5000) then
-- High Tone detected
cindat <= '0';
cintone <= '1';
cinbits <= (others => '0');
-- Generate the high tone detect interrupt
isr(6) <= '1';
elsif (cindat = '0' and cintone = '1' and general_counter > 5000) then
-- Start bit detected
cindat <= '1';
cintone <= '0';
cinbits <= (others => '0');
elsif (cindat = '1' and ignore_next = '1') then
-- Ignoring the second pulse in a bit at 2400Hz
ignore_next <= '0';
elsif (cindat = '1' and cinbits < 9) then
if (cinbits < 8) then
if (general_counter > 5000) then
-- shift in a zero
data_shift <= '0' & data_shift(7 downto 1);
else
-- shift in a one
data_shift <= '1' & data_shift(7 downto 1);
end if;
-- Generate the receive data int as soon as the
-- last bit has been shifted in.
if (cinbits = 7) then
isr(4) <= '1';
end if;
end if;
-- Ignore the second pulse in a bit at 2400Hz
if (general_counter > 5000) then
ignore_next <= '0';
else
ignore_next <= '1';
end if;
-- Move on to the next data bit
cinbits <= cinbits + 1;
elsif (cindat = '1' and cinbits = 9) then
if (general_counter > 5000) then
-- Found next start bit...
cindat <= '1';
cintone <= '0';
cinbits <= (others => '0');
else
-- Back in tone again
cindat <= '0';
cintone <= '1';
cinbits <= (others => '0');
-- Generate the high tone detect interrupt
isr(6) <= '1';
end if;
end if;
end if;
else
cindat <= '0';
cintone <= '0';
cinbits <= (others => '0');
ignore_next <= '0';
end if;
-- regardless of the comms mode, update coutbits state (at 1200Hz)
if general_counter(13 downto 0) = 0 then
-- wait to TDEmpty interrupt to be cleared before starting
if coutbits = 0 then
if isr(5) = '0' then
coutbits <= x"9";
end if;
else
-- set the TDEmpty interrpt after the last data bit is sent
if coutbits = 1 then
isr(5) <= '1';
end if;
-- shift the data shift register if not the start bit
-- shifting a 1 at the top end gives us the correct stop bit
if comms_mode = "10" and coutbits /= 9 then
data_shift <= '1' & data_shift(7 downto 1);
end if;
-- move to the next state
coutbits <= coutbits - 1;
end if;
end if;
-- Generate the cassette out tone based on the current state
if coutbits = 9 or (coutbits > 0 and data_shift(0) = '0') then
-- start bit or data bit "0" = 1200Hz
casOut <= general_counter(13);
else
-- stop bit or data bit "1" or any other time= 2400Hz
casOut <= general_counter(12);
end if;
-- ULA Writes
if (cpu_clken = '1') then
if delayed_clear_reset = '1' then
power_on_reset <= '0';
end if;
---- Detect control+caps 1...4 and change video format
if (addr = x"9fff" and page_enable = '1' and page(2 downto 1) = "00") then
if (kbd(2 downto 1) = "00") then
ctrl_caps <= '1';
else
ctrl_caps <= '0';
end if;
end if;
-- Detect "1" being pressed: RGB non-interlaced (default)
if (addr = x"afff" and page_enable = '1' and page(2 downto 1) = "00" and ctrl_caps = '1' and kbd(0) = '0') then
mode <= "00";
end if;
-- Detect "2" being pressed: RGB interlaced
if (addr = x"b7ff" and page_enable = '1' and page(2 downto 1) = "00" and ctrl_caps = '1' and kbd(0) = '0') then
mode <= "01";
end if;
-- Detect "3" being pressed: SVGA @ 50 Hz (33 MHz clock)
if (addr = x"bbff" and page_enable = '1' and page(2 downto 1) = "00" and ctrl_caps = '1' and kbd(0) = '0' and IncludeVGA) then
mode <= "10";
end if;
-- Detect "4" being pressed: SVGA @ 60 Hz (40 MHz clock)
if (addr = x"bdff" and page_enable = '1' and page(2 downto 1) = "00" and ctrl_caps = '1' and kbd(0) = '0' and IncludeVGA) then
mode <= "11";
end if;
-- Detect "5" being pressed: 1MHz
if (addr = x"beff" and page_enable = '1' and page(2 downto 1) = "00" and ctrl_caps = '1' and kbd(0) = '0') then
turbo_out <= "00";
end if;
-- Detect "6" being pressed: 2MHz with contention (default)
if (addr = x"bf7f" and page_enable = '1' and page(2 downto 1) = "00" and ctrl_caps = '1' and kbd(0) = '0') then
turbo_out <= "01";
end if;
-- Detect "7" being pressed: 2MHz no contention
if (addr = x"bfbf" and page_enable = '1' and page(2 downto 1) = "00" and ctrl_caps = '1' and kbd(0) = '0') then
turbo_out <= "10";
end if;
-- Detect "8" being pressed: 4MHz
if (addr = x"bfdf" and page_enable = '1' and page(2 downto 1) = "00" and ctrl_caps = '1' and kbd(0) = '0') then
turbo_out <= "11";
end if;
if (addr(15 downto 8) = x"FE") then
if (R_W_n = '1') then
-- Clear the power on reset flag on the first read of the ISR (FEx0)
if (addr(3 downto 0) = x"0") then
delayed_clear_reset <= '1';
end if;
-- Clear the RDFull interrupts on reading the data_shift register
if (addr(3 downto 0) = x"4") then
isr(4) <= '0';
end if;
else
case addr(3 downto 0) is
when x"0" =>
ier(6 downto 2) <= data_in(6 downto 2);
when x"1" =>
when x"2" =>
screen_base(8 downto 6) <= data_in(7 downto 5);
when x"3" =>
screen_base(14 downto 9) <= data_in(5 downto 0);
when x"4" =>
data_shift <= data_in;
-- Clear the TDEmpty interrupt on writing the
-- data_shift register
isr(5) <= '0';
when x"5" =>
if (data_in(6) = '1') then
-- Clear High Tone Detect IRQ
isr(6) <= '0';
end if;
if (data_in(5) = '1') then
-- Clear Real Time Clock IRQ
isr(3) <= '0';
end if;
if (data_in(4) = '1') then
-- Clear Display End IRQ
isr(2) <= '0';
end if;
if (page_enable = '1' and page(2) = '0') then
-- Roms 8-11 currently selected, so only selecting 8-15 will be honoured
if (data_in(3) = '1') then
page_enable <= data_in(3);
page <= data_in(2 downto 0);
end if;
else
-- Roms 0-7 or 12-15 currently selected, so anything goes
page_enable <= data_in(3);
page <= data_in(2 downto 0);
end if;
when x"6" =>
counter <= data_in;
when x"7" =>
caps_int <= data_in(7);
motor_int <= data_in(6);
case (data_in(5 downto 3)) is
when "000" =>
mode_base <= "0110"; -- 0x3000
mode_bpp <= "00";
mode_40 <= '0';
mode_text <= '0';
when "001" =>
mode_base <= "0110"; -- 0x3000
mode_bpp <= "01";
mode_40 <= '0';
mode_text <= '0';
when "010" =>
mode_base <= "0110"; -- 0x3000
mode_bpp <= "10";
mode_40 <= '0';
mode_text <= '0';
when "011" =>
mode_base <= "1000"; -- 0x4000
mode_bpp <= "00";
mode_40 <= '0';
mode_text <= '1';
when "100" =>
mode_base <= "1011"; -- 0x5800
mode_bpp <= "00";
mode_40 <= '1';
mode_text <= '0';
when "101" =>
mode_base <= "1011"; -- 0x5800
mode_bpp <= "01";
mode_40 <= '1';
mode_text <= '0';
when "110" =>
mode_base <= "1100"; -- 0x6000
mode_bpp <= "00";
mode_40 <= '1';
mode_text <= '1';
when "111" =>
-- mode 7 seems to default to mode 4
mode_base <= "1011"; -- 0x5800
mode_bpp <= "00";
mode_40 <= '1';
mode_text <= '0';
when others =>
end case;
comms_mode <= data_in(2 downto 1);
-- A quirk of the Electron ULA is that RxFull
-- interrupt fires when tape output mode is
-- entered. Games like Southen Belle rely on
-- this quirk.
if data_in(2 downto 1) = "10" then
isr(4) <= '1';
end if;
when others =>
-- A '1' in the palatte data means disable the colour
-- Invert the stored palette, to make the palette logic simpler
palette(slv2int(addr(2 downto 0))) <= data_in xor "11111111";
end case;
end if;
end if;
end if;
end if;
end if;
end process;
-- SGVA timing at 60Hz with a 40.000MHz Pixel Clock
-- Horizontal 800 + 40 + 128 + 88 = total 1056
-- Vertical 600 + 1 + 4 + 23 = total 628
-- Within the the 640x512 is centred so starts at 80,44
-- Horizontal 640 + (80 + 40) + 128 + (88 + 80) = total 1056
-- Vertical 512 + (44 + 1) + 4 + (23 + 44) = total 628
-- RGBs timing at 50Hz with a 16.000MHz Pixel Clock
-- Horizontal 640 + (96 + 26) + 75 + (91 + 96) = total 1024
-- Vertical 256 + (16 + 2) + 3 + (19 + 16) = total 312
process (clk_video)
variable pixel : std_logic_vector(3 downto 0);
-- start address of current row block (8-10 lines)
variable row_addr : std_logic_vector(14 downto 6);
-- address within current line
variable byte_addr : std_logic_vector(14 downto 3);
begin
if rising_edge(clk_video) then
-- Horizontal counter, clocked at the pixel clock rate
if h_count = h_total then
h_count <= (others => '0');
else
h_count <= h_count + 1;
end if;
-- Pipelined version of h_count by to compensate the register in the RAM
h_count1 <= h_count;
-- Vertical counter, incremented at the end of each line
if h_count = h_total then
if v_count = v_total then
v_count <= (others => '0');
else
v_count <= v_count + 1;
end if;
end if;
-- Field; field=0 is the (first) odd field, field=1 is the even field
if h_count = h_total and v_count = v_total then
if mode = "01" then
-- Interlaced, so alternate odd and even fields
field <= not field;
else
-- Non-interlaced, so odd fields only
field <= '0';
end if;
end if;
-- Char_row counts 0..7 or 0..9 depending on the mode.
-- It incremented on the trailing edge of hsync
hsync_int_last <= hsync_int;
if hsync_int = '1' and hsync_int_last = '0' then
if v_count = v_total then
char_row <= (others => '0');
elsif v_count(0) = '1' or mode(1) = '0' then
if last_line = '1' then
char_row <= (others => '0');
else
char_row <= char_row + 1;
end if;
end if;
elsif mode_text = '0' then
-- From the ULA schematics sheet 7, VA3 is a T-type Latch
-- with an additional reset input connected to GMODE, so it's
-- immediately forced to zero in a graphics mode. This is
-- needed for 0xC0DE's Vertical Rupture demo to work.
char_row(3) <= '0';
end if;
-- Determine last line of a row
if ((mode_text = '0' and char_row = 7) or (mode_text = '1' and char_row = 9)) and (v_count(0) = '1' or mode(1) = '0') then
last_line <= '1';
else
last_line <= '0';
end if;
-- RAM Address, constructed from the local row_addr and byte_addr registers
-- Some of this is taken from Hick's efforts to understand the schematics:
-- https://www.mups.co.uk/project/hardware/acorn_electron/
-- At start of the field, update row_addr and byte_addr from the ULA registers 2,3
if h_count = h_total and v_count = v_total then
row_addr := screen_base;
byte_addr := screen_base & "000";
end if;
-- At the start of hsync, update the row_addr from byte_addr which
-- gets to the start of the next block
if hsync_int = '0' and hsync_int_last = '1' and last_line = '1' then
row_addr := byte_addr(14 downto 6);
end if;
-- During hsync, reset byte reset back to start of line, unless
-- it's the last line
if hsync_int = '0' and last_line = '0' then
byte_addr := row_addr & "000";
end if;
-- Every 8 or 16 pixels depending on mode/repeats
if h_count < h_active then
if (mode_40 = '0' and h_count(2 downto 0) = "111") or
(mode_40 = '1' and h_count(3 downto 0) = "1111") then
byte_addr := byte_addr + 1;
end if;
end if;
-- Handle wrap-around back to mode_base
if byte_addr(14 downto 11) = "0000" then
byte_addr := mode_base & byte_addr(10 downto 3);
end if;
-- Screen_addr is the final 15-bit Video RAM address
if mode7_enable = '1' then
screen_addr <= "11111" & crtc_ma(9 downto 0);
else
screen_addr <= byte_addr & char_row(2 downto 0);
end if;
-- RGB Data
if (h_count1 >= h_active or (mode_text = '0' and v_count >= v_active_gph) or (mode_text = '1' and v_count >= v_active_txt) or char_row >= 8) then
-- blanking and border are always black
red_int <= (others => '0');
green_int <= (others => '0');
blue_int <= (others => '0');
contention <= '0';
else
-- Indicate possible memory contention on active scan lines
contention <= not mode_40;
-- rendering an actual pixel
if (mode_bpp = 0) then
-- 1 bit per pixel, map to colours 0 and 8 for the palette lookup
if (mode_40 = '1') then
pixel := screen_data(7 - slv2int(h_count1(3 downto 1))) & "000";
else
pixel := screen_data(7 - slv2int(h_count1(2 downto 0))) & "000";
end if;
elsif (mode_bpp = 1) then
-- 2 bits per pixel, map to colours 0, 2, 8, 10 for the palette lookup
if (mode_40 = '1') then
pixel := screen_data(7 - slv2int(h_count1(3 downto 2))) & "0" &
screen_data(3 - slv2int(h_count1(3 downto 2))) & "0";
else
pixel := screen_data(7 - slv2int(h_count1(2 downto 1))) & "0" &
screen_data(3 - slv2int(h_count1(2 downto 1))) & "0";
end if;
else
-- 4 bits per pixel, map directly for the palette lookup
if (mode_40 = '1') then
pixel := screen_data(7 - sl2int(h_count1(3))) &
screen_data(5 - sl2int(h_count1(3))) &
screen_data(3 - sl2int(h_count1(3))) &
screen_data(1 - sl2int(h_count1(3)));
else
pixel := screen_data(7 - sl2int(h_count1(2))) &
screen_data(5 - sl2int(h_count1(2))) &
screen_data(3 - sl2int(h_count1(2))) &
screen_data(1 - sl2int(h_count1(2)));
end if;
end if;
-- Implement Color Palette
case (pixel) is
when "0000" =>
red_int <= (others => palette(1)(0));
green_int <= (others => palette(1)(4));
blue_int <= (others => palette(0)(4));
when "0001" =>
red_int <= (others => palette(7)(0));
green_int <= (others => palette(7)(4));
blue_int <= (others => palette(6)(4));
when "0010" =>
red_int <= (others => palette(1)(1));
green_int <= (others => palette(1)(5));
blue_int <= (others => palette(0)(5));
when "0011" =>
red_int <= (others => palette(7)(1));
green_int <= (others => palette(7)(5));
blue_int <= (others => palette(6)(5));
when "0100" =>
red_int <= (others => palette(3)(0));
green_int <= (others => palette(3)(4));
blue_int <= (others => palette(2)(4));
when "0101" =>
red_int <= (others => palette(5)(0));
green_int <= (others => palette(5)(4));
blue_int <= (others => palette(4)(4));
when "0110" =>
red_int <= (others => palette(3)(1));
green_int <= (others => palette(3)(5));
blue_int <= (others => palette(2)(5));
when "0111" =>
red_int <= (others => palette(5)(1));
green_int <= (others => palette(5)(5));
blue_int <= (others => palette(4)(5));
when "1000" =>
red_int <= (others => palette(1)(2));
green_int <= (others => palette(0)(2));
blue_int <= (others => palette(0)(6));
when "1001" =>
red_int <= (others => palette(7)(2));
green_int <= (others => palette(6)(2));
blue_int <= (others => palette(6)(6));
when "1010" =>
red_int <= (others => palette(1)(3));
green_int <= (others => palette(0)(3));
blue_int <= (others => palette(0)(7));
when "1011" =>
red_int <= (others => palette(7)(3));
green_int <= (others => palette(6)(3));
blue_int <= (others => palette(6)(7));
when "1100" =>
red_int <= (others => palette(3)(2));
green_int <= (others => palette(2)(2));
blue_int <= (others => palette(2)(6));
when "1101" =>
red_int <= (others => palette(5)(2));
green_int <= (others => palette(4)(2));
blue_int <= (others => palette(4)(6));
when "1110" =>
red_int <= (others => palette(3)(3));
green_int <= (others => palette(2)(3));
blue_int <= (others => palette(2)(7));
when "1111" =>
red_int <= (others => palette(5)(3));
green_int <= (others => palette(4)(3));
blue_int <= (others => palette(4)(7));
when others =>
end case;
--green_int <= (not ctrl_caps) & "111"; -- DEBUG make screen green
end if;
-- Vertical Sync, lasts 2.5 lines (160us)
if (field = '0') then
-- first field (odd) of interlaced scanning (or non interlaced)
-- vsync starts at the beginning of the line
if (h_count1 = 0 and v_count = vsync_start) then
vsync_int <= '0';
elsif (h_count1 = ('0' & h_total(10 downto 1)) and v_count = vsync_end) then
vsync_int <= '1';
end if;
else
-- second field (even) of intelaced scanning
-- vsync starts half way through the line
if (h_count1 = ('0' & h_total(10 downto 1)) and v_count = vsync_start) then
vsync_int <= '0';
elsif (h_count1 = 0 and v_count = vsync_end) then
vsync_int <= '1';
end if;
end if;
-- Horizontal Sync
if (h_count1 = hsync_start) then
hsync_int <= '0';
elsif (h_count1 = hsync_end) then
hsync_int <= '1';
end if;
-- Display Interrupt, this is co-incident with the leading edge
-- of hsync at the end the last active line of display
-- (line 249 in text mode or line 255 in graphics mode)
if (h_count1 = hsync_start) and ((v_count = v_disp_gph and mode_text = '0') or (v_count = v_disp_txt and mode_text = '1')) then
display_intr <= '1';
elsif (h_count1 = hsync_end) then
display_intr <= '0';
end if;
-- RTC Interrupt, this occurs 8192us (200 lines) after the end of
-- the vsync, and is not co-incident with hsync
if (v_count = v_rtc) and ((field = '0' and h_count1 = 0) or (field = '1' and h_count1 = ('0' & h_total(10 downto 1)))) then
rtc_intr <= '1';
elsif (v_count = 0) then
rtc_intr <= '0';
end if;
end if;
end process;
red <= (others => ttxt_r_out) when mode7_enable = '1' else
red_int;
green <= (others => ttxt_g_out) when mode7_enable = '1' else
green_int;
blue <= (others => ttxt_b_out) when mode7_enable = '1' else
blue_int;
vsync <= ttxt_vs_out when mode7_enable = '1' else
'1' when mode(1) = '0' else
vsync_int;
hsync <= ttxt_hs_out when mode7_enable = '1' else
hsync_int and vsync_int when mode(1) = '0' else
hsync_int;
caps <= caps_int;
motor <= motor_int;
--------------------------------------------------------
-- clock enable generator
--------------------------------------------------------
-- Keyboard accesses always need to happen at 1MHz
kbd_access <= '1' when addr(15 downto 14) = "10" and page_enable = '1' and page(2 downto 1) = "00" else '0';
-- IO accesses always happen at 1MHz (no contention)
-- This includes keyboard reads in paged ROM slots 8/9
io_access <= '1' when addr(15 downto 8) = x"FC" or addr(15 downto 8) = x"FD" or addr(15 downto 8) = x"FE" or kbd_access = '1' else '0';
-- ROM accesses always happen at 2MHz (no contention)
rom_access <= addr(15) and not io_access;
-- RAM accesses always happen at 1MHz (with contention)
ram_access <= not addr(15);
clk_gen1 : process(clk_16M00)
begin
if rising_edge(clk_16M00) then
-- Synchronize changes in the current speed with a 1MHz clock boundary
if clken_counter = "1111" then
turbo_sync <= turbo;
end if;
-- Synchronize contention signal
contention1 <= contention;
contention2 <= contention1;
-- clken counter
clken_counter <= clken_counter + 1;
-- Logic to supress cpu cycles
case (turbo_sync) is
when "00" =>
-- 1MHz No Contention
-- RAM accesses 1MHz
-- ROM accesses 1MHz
-- IO accesses 1MHz
-- cpu_clken active on cycle 0
-- address/data changes on cycle 1
if clken_counter(3 downto 0) = "1111" then
cpu_clken <= '1';
else
cpu_clken <= '0';
end if;
-- No stopping of the clock in this mode
clk_stopped <= "00";
when "01" =>
-- 2MHz/1MHz with Contention (match original Electron)
-- RAM accesses 1MHz + contention
-- ROM accesses 2MHz
-- IO accesses 1MHz
-- cpu_clken active on cycle 0, 8
-- address/data changes on cycle 1, 9
if clken_counter(2 downto 0) = "111" and clk_stopped = 0 then
cpu_clken <= '1';
else
cpu_clken <= '0';
end if;
-- Stop the clock on RAM or IO accesses, in the same way the ULA does
if clk_stopped = 0 and clken_counter(2 downto 0) = "110" and (ram_access = '1' or io_access = '1') then
clk_stopped <= "01";
elsif clken_counter(3 downto 0) = "1110" and not (ram_access = '1' and contention2 = '1') then
clk_stopped <= "00";
end if;
when "10" =>
-- 2MHz No Contention
-- RAM accesses 2MHz
-- ROM accesses 2MHz
-- IO accesses 2MHz (or 1MHz if LimitIOSpeed true)
-- cpu_clken active on cycle 0, 8
-- address/data changes on cycle 1, 9
if clken_counter(2 downto 0) = "111" and clk_stopped = 0 then
cpu_clken <= '1';
else
cpu_clken <= '0';
end if;
-- Stop the clock on IO accesses as required
if LimitIOSpeed and clk_stopped = 0 and clken_counter(2 downto 0) = "110" and io_access = '1' then
clk_stopped <= "01";
elsif clken_counter(3 downto 0) = "1110" then
clk_stopped <= "00";
end if;
when "11" =>
-- 4MHz No contention
-- RAM accesses 4MHz
-- ROM accesses 4MHz (or 2MHz if LimitROMSpeed true)
-- IO accesses 4MHz (or 1MHz if LimitIOSpeed true)
-- cpu_clken active on cycle 0, 4, 8, 12
-- address/data changes on cycle 1, 5, 9, 13
if clken_counter(1 downto 0) = "11" and clk_stopped = 0 then
cpu_clken <= '1';
else
cpu_clken <= '0';
end if;
-- Stop the clock on ROM or IO accesses as required
if clk_stopped = 0 then
if LimitROMSpeed and rom_access = '1' and clken_counter(1 downto 0) = "10" then
clk_stopped <= "01";
elsif LimitIOSpeed and io_access = '1' and clken_counter(1 downto 0) = "10" then
if clken_counter(3 downto 2) = "00" or clken_counter(3 downto 2) = "11" then
clk_stopped <= "01";
else
clk_stopped <= "10";
end if;
end if;
else
if rom_access = '1' then
if clken_counter(2 downto 0) = "110" then
clk_stopped <= "00";
end if;
else
if clken_counter(3 downto 0) = "1110" then
if clk_stopped(1) = '1' then
clk_stopped <= "01";
else
clk_stopped <= "00";
end if;
end if;
end if;
end if;
when others =>
end case;
-- Generate clock enables for VIA one cycle before cpu_clken
if turbo_sync(1) = '0' or LimitIOSpeed then
-- 1MHz
via1_clken <= clken_counter(3) and clken_counter(2) and clken_counter(1) and not clken_counter(0);
via4_clken <= clken_counter(1) and not clken_counter(0);
elsif turbo_sync(0) = '0' then
-- 2MHz
via1_clken <= clken_counter(2) and clken_counter(1) and not clken_counter(0);
via4_clken <= not clken_counter(0);
else
-- 4MHz
via1_clken <= clken_counter(1) and not clken_counter(0);
via4_clken <= '1';
end if;
-- Generate cpu_clk
if cpu_clken = '1' then
if turbo_sync = "11" then
-- 4MHz clock; produce a 125 ns low pulse
clk_counter <= "011";
else
-- 1MHz or 2MHz clock; produce a 250 ns low pulse
clk_counter <= "001";
end if;
cpu_clk <= '0';
elsif clk_counter(2) = '0' then
clk_counter <= clk_counter + 1;
else
cpu_clk <= '1';
end if;
end if;
end process;
cpu_clken_out <= cpu_clken;
cpu_clk_out <= cpu_clk;
--------------------------------------------------------
-- Optional MMC Filing System
--------------------------------------------------------
MMCIncluded: if IncludeMMC generate
mc6522_enable <= '1' when addr(15 downto 4) = x"fcb" else '0';
via : entity work.M6522 port map(
I_RS => addr(3 downto 0),
I_DATA => data_in(7 downto 0),
O_DATA => mc6522_data(7 downto 0),
I_RW_L => R_W_n,
I_CS1 => mc6522_enable,
I_CS2_L => '0',
O_IRQ_L => mc6522_irq_n,
I_CA1 => '0',
I_CA2 => mc6522_ca2,
O_CA2 => mc6522_ca2,
O_CA2_OE_L => open,
I_PA => mc6522_porta,
O_PA => mc6522_porta,
O_PA_OE_L => open,
I_CB1 => mc6522_cb1_in,
O_CB1 => mc6522_cb1_out,
O_CB1_OE_L => mc6522_cb1_oe_l,
I_CB2 => mc6522_cb2_in,
O_CB2 => open,
O_CB2_OE_L => open,
I_PB => mc6522_portb_in,
O_PB => mc6522_portb_out,
O_PB_OE_L => mc6522_portb_oe_l,
RESET_L => RST_n,
I_P2_H => via1_clken,
ENA_4 => via4_clken,
CLK => clk_16M00);
-- This is needed as in v003 of the 6522 data out is only valid while I_P2_H is asserted
-- I_P2_H is driven from via1_clken
data_latch: process(clk_16M00)
begin
if rising_edge(clk_16M00) then
if via1_clken = '1' then
mc6522_data_r <= mc6522_data;
end if;
end if;
end process;
-- loop back data port
mc6522_portb_in <= mc6522_portb_out;
-- SDCLK is driven from either PB1 or CB1 depending on the SR Mode
sdclk_int <= mc6522_portb_out(1) when mc6522_portb_oe_l(1) = '0' else
mc6522_cb1_out when mc6522_cb1_oe_l = '0' else
'1';
SDCLK <= sdclk_int;
mc6522_cb1_in <= sdclk_int;
-- SDMOSI is always driven from PB0
SDMOSI <= mc6522_portb_out(0) when mc6522_portb_oe_l(0) = '0' else
'1';
-- SDMISO is always read from CB2
mc6522_cb2_in <= SDMISO;
-- SDSS is hardwired to 0 (always selected) as there is only one slave attached
SDSS <= '0';
IRQ_n <= ula_irq_n and mc6522_irq_n;
end generate;
MMCNotIncluded: if not IncludeMMC generate
IRQ_n <= ula_irq_n;
end generate;
--------------------------------------------------------
-- Optional Jafa Mk1 Compatible Mode 7 Implementation
--------------------------------------------------------
JafaIncluded: if IncludeJafaMode7 generate
-- FC1C - Write address register
-- FC1D - Write data register
-- FC1E - Read status register - only bit 5 (vsync) is implemented
-- FC1F - Read data register
process (clk_16M00)
variable counter : std_logic_vector(3 downto 0);
begin
if rising_edge(clk_16M00) then
if counter = "1111" then
crtc_clken <= '1';
else
crtc_clken <= '0';
end if;
counter := counter + 1;
-- Generate a cursor signal that is delayed by 2 characters
if crtc_clken = '1' then
crtc_cursor1 <= crtc_cursor;
crtc_cursor2 <= crtc_cursor1;
end if;
end if;
end process;
using_ext_ttxt_clock : if UseTTxtClock generate
-- Use external 96 MHz clock / 12 MHz enable
ttxt_clock <= clk_ttxt;
ttxt_clken <= clken_ttxt_12M;
end generate;
using_24mhz_ttxt_clock : if not UseTTxtClock generate
-- Use 24 MHz clock and generate 12 MHz enable
ttxt_clock <= clk_24M00;
process (clk_24M00)
begin
if rising_edge(clk_24M00) then
ttxt_clken <= not ttxt_clken;
end if;
end process;
end generate;
crtc_enable <= '1' when addr(15 downto 0) = x"fc1c" or
addr(15 downto 0) = x"fc1d" or
addr(15 downto 0) = x"fc1f"
else '0';
status_enable <= '1' when addr(15 downto 0) = x"fc1e" else '0';
status_do <= "00" & crtc_vsync & "00000";
crtc : entity work.mc6845 port map (
-- inputs
CLOCK => clk_16M00,
CLKEN => crtc_clken,
nRESET => RST_n,
ENABLE => crtc_enable,
R_nW => R_W_n,
RS => addr(0),
DI => data_in,
LPSTB => '0',
-- outputs
DO => crtc_do,
VSYNC => crtc_vsync,
HSYNC => crtc_hsync,
DE => crtc_de,
CURSOR => crtc_cursor,
MA => crtc_ma,
RA => crtc_ra
);
crtc_hsync_n <= not crtc_hsync;
crtc_vsync_n <= not crtc_vsync;
ttxt_glr <= crtc_hsync_n;
ttxt_dew <= crtc_vsync;
ttxt_crs <= not crtc_ra(0);
ttxt_lose <= crtc_de;
teletext : entity work.saa5050
generic map (
IncludeTTxtROM => IncludeTTxtROM
)
port map (
-- inputs
CLOCK => ttxt_clock,
CLKEN => ttxt_clken,
nRESET => RST_n,
DI_CLOCK => clk_16M00,
DI_CLKEN => '1',
DI => screen_data(6 downto 0),
GLR => ttxt_glr,
DEW => ttxt_dew,
CRS => ttxt_crs,
LOSE => ttxt_lose,
-- outputs
R => ttxt_r_int,
G => ttxt_g_int,
B => ttxt_b_int,
-- SAA5050 character ROM loading
char_rom_we => char_rom_we,
char_rom_addr => char_rom_addr,
char_rom_data => char_rom_data
);
-- make the cursor visible
ttxt_r <= ttxt_r_int xor crtc_cursor2;
ttxt_g <= ttxt_g_int xor crtc_cursor2;
ttxt_b <= ttxt_b_int xor crtc_cursor2;
-- enable mode 7
mode7_enable <= crtc_ma(13);
end generate;
JafaAndVGAIncluded: if IncludeJafaMode7 and IncludeVGA generate
-- Scan Doubler from the MIST project
inst_mist_scandoubler: entity work.mist_scandoubler port map (
clk => clk_32M00,
clk_16 => clk_16M00,
clk_16_en => '1',
scanlines => '0',
hs_in => crtc_hsync_n,
vs_in => crtc_vsync_n,
r_in => ttxt_r,
g_in => ttxt_g,
b_in => ttxt_b,
hs_out => mist_hs,
vs_out => mist_vs,
r_out => mist_r,
g_out => mist_g,
b_out => mist_b,
is15k => open
);
-- MUX to select sRGB/VGA based on vid_mode(1)
ttxt_r_out <= mist_r(1) when mode(1) = '1' else ttxt_r;
ttxt_g_out <= mist_g(1) when mode(1) = '1' else ttxt_g;
ttxt_b_out <= mist_b(1) when mode(1) = '1' else ttxt_b;
ttxt_vs_out <= mist_vs when mode(1) = '1' else '1';
ttxt_hs_out <= mist_hs when mode(1) = '1' else crtc_hsync_n and crtc_vsync_n;
end generate;
JafaAndNotVGAIncluded: if IncludeJafaMode7 and not IncludeVGA generate
ttxt_r_out <= ttxt_r;
ttxt_g_out <= ttxt_g;
ttxt_b_out <= ttxt_b;
ttxt_vs_out <= '1';
ttxt_hs_out <= crtc_hsync_n and crtc_vsync_n;
end generate;
JafaNotIncluded: if not IncludeJafaMode7 generate
-- disable mode 7
mode7_enable <= '0';
end generate;
end behavioral;
| gpl-3.0 | cef294542e4839ea883d3dbbc048a3aa | 0.444712 | 4.089755 | false | false | false | false |
DreamIP/GPStudio | support/toolchain/caph/hdl/caph_toplevel/src/caph_flow_pkg.vhd | 1 | 1,066 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package caph_flow_pkg is
constant MAX_IMAGE_WIDTH : integer := 1920;
constant MAX_IMAGE_HEIGHT : integer := 1024;
-- start of Frame & start of Line has same vhdl header
-- End of Frame/Line too ...
constant SoF:integer := 0;
constant EoF:integer := 1;
constant SoL : integer := 0;
constant EoL : integer := 1;
constant Data:integer:= 2;
constant TOKEN_HEADER_SIZE:integer :=2;
-- codage des headers caph
type my_caph_header_t is array (0 to 2) of std_logic_vector(1 downto 0);
constant CaphHeader : my_caph_header_t := ("01","10","11");
-- Must match caph_toplevel instanciation parameter ...
constant MEM_ADDR_BUS_SIZE: integer := 4;
type caph_port_t is
record
data : std_logic_vector(31 downto 0);
wr : std_logic;
full : std_logic;
end record;
constant NB_PORTS : integer := 10;
type caph_ports_t is array (0 to NB_PORTS-1) of caph_port_t;
end package caph_flow_pkg;
| gpl-3.0 | d69ac83f4c77baf20d58e1f2139e17d1 | 0.629456 | 3.1261 | false | false | false | false |
DreamIP/GPStudio | support/io/gps/hdl/gps_receiver.vhd | 1 | 2,730 | --------------------------------------------------------
-- UART receiver block. It detects the falling edge of
-- the signal from RXD pin and start acquiring data.
-- If the NMEA $GNGGA sequence is detected, the data are
-- written in the FIFO.
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity GPS_receiver is
port(
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
RXD : in std_logic;
data_ready : out std_logic;
data_out : out std_logic_vector(7 downto 0);
count_bd : in unsigned(15 downto 0);
count_max : in unsigned(15 downto 0);
rst_count_bd : out std_logic;
gngga_flag : out std_logic
);
end GPS_receiver;
architecture RTL of GPS_receiver is
signal number_of_bits : unsigned(3 downto 0);
signal data_out_s : std_logic_vector(7 downto 0);
signal gngga : std_logic_vector(55 downto 0);
signal RXD_s : std_logic;
type type_state is (idle, start, data, stop);
signal state_rec : type_state;
begin
process(clk,reset)
begin
if reset='0' then
state_rec <= idle;
gngga_flag <= '0';
data_ready <= '0';
rst_count_bd <= '0';
elsif clk'event and clk='1' then
if enable='1' then
RXD_s <= RXD;
case(state_rec) is
----- Detecting the beginning of a communication
when(idle) =>
gngga_flag <= '0';
data_ready <= '0';
if RXD = '0' or RXD_s='0' then
state_rec <= start;
rst_count_bd <= '1';
end if;
----- Start bit is read
when(start) =>
rst_count_bd <='0';
if count_bd>=count_max/2 then
state_rec <= data;
rst_count_bd <= '1';
end if;
----- 8 bits of data are read (LSB first)
when(data) =>
rst_count_bd <='0';
if count_bd=count_max then
data_out_s <= RXD & data_out_s(7 downto 1);
number_of_bits <= number_of_bits +1;
if number_of_bits = x"7" then
state_rec <= stop;
number_of_bits <= x"0";
end if;
end if;
----- Stop bit, the detection of the NMEA $GNGGA sequence is check
when(stop) =>
data_out <= data_out_s;
if count_bd+1>=count_max then
state_rec <= idle;
if gngga=x"24474E4747412C" or gngga(15 downto 0)=x"A0A1" then --or gngga=x"24474E4753412C"then
gngga_flag <= '1';
data_ready <= '0';
else
data_ready <= '1';
end if;
elsif count_bd=count_max-5 then
gngga <= gngga(47 downto 0) & data_out_s;
end if;
end case;
end if;
end if;
end process;
end RTL;
| gpl-3.0 | e023ed4ddbb5e0d43f4c3c48a6fdb4dd | 0.532601 | 2.938644 | false | false | false | false |
DreamIP/GPStudio | support/process/dynroiBinMask/hdl/dynroiBinMask_slave.vhd | 1 | 3,885 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity dynroiBinMask_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
status_reg_bypass_bit : out std_logic;
in_size_reg_in_w_reg : out std_logic_vector(11 downto 0);
in_size_reg_in_h_reg : out std_logic_vector(11 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end dynroiBinMask_slave;
architecture rtl of dynroiBinMask_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant IN_SIZE_REG_REG_ADDR : natural := 1;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal status_reg_bypass_bit_reg : std_logic;
signal in_size_reg_in_w_reg_reg : std_logic_vector (11 downto 0);
signal in_size_reg_in_h_reg_reg : std_logic_vector (11 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
status_reg_bypass_bit_reg <= '0';
in_size_reg_in_w_reg_reg <= "000000000000";
in_size_reg_in_h_reg_reg <= "000000000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case to_integer(unsigned(addr_rel_i)) is
when STATUS_REG_REG_ADDR =>
status_reg_enable_bit_reg <= datawr_i(0);
status_reg_bypass_bit_reg <= datawr_i(1);
when IN_SIZE_REG_REG_ADDR =>
in_size_reg_in_w_reg_reg <= datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
in_size_reg_in_h_reg_reg <= datawr_i(27) & datawr_i(26) & datawr_i(25) & datawr_i(24) & datawr_i(23) & datawr_i(22) & datawr_i(21) & datawr_i(20) & datawr_i(19) & datawr_i(18) & datawr_i(17) & datawr_i(16);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case to_integer(unsigned(addr_rel_i)) is
when STATUS_REG_REG_ADDR =>
datard_o <= "000000000000000000000000000000" & status_reg_bypass_bit_reg & status_reg_enable_bit_reg;
when IN_SIZE_REG_REG_ADDR =>
datard_o <= "0000" & in_size_reg_in_h_reg_reg(11) & in_size_reg_in_h_reg_reg(10) & in_size_reg_in_h_reg_reg(9) & in_size_reg_in_h_reg_reg(8) & in_size_reg_in_h_reg_reg(7) & in_size_reg_in_h_reg_reg(6) & in_size_reg_in_h_reg_reg(5) & in_size_reg_in_h_reg_reg(4) & in_size_reg_in_h_reg_reg(3) & in_size_reg_in_h_reg_reg(2) & in_size_reg_in_h_reg_reg(1) & in_size_reg_in_h_reg_reg(0) & "0000" & in_size_reg_in_w_reg_reg(11) & in_size_reg_in_w_reg_reg(10) & in_size_reg_in_w_reg_reg(9) & in_size_reg_in_w_reg_reg(8) & in_size_reg_in_w_reg_reg(7) & in_size_reg_in_w_reg_reg(6) & in_size_reg_in_w_reg_reg(5) & in_size_reg_in_w_reg_reg(4) & in_size_reg_in_w_reg_reg(3) & in_size_reg_in_w_reg_reg(2) & in_size_reg_in_w_reg_reg(1) & in_size_reg_in_w_reg_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
status_reg_bypass_bit <= status_reg_bypass_bit_reg;
in_size_reg_in_w_reg <= in_size_reg_in_w_reg_reg;
in_size_reg_in_h_reg <= in_size_reg_in_h_reg_reg;
end rtl;
| gpl-3.0 | 9d0de94ae6228043584852e6314acefb | 0.588417 | 2.512937 | false | false | false | false |
DreamIP/GPStudio | support/process/roberts/hdl/roberts.vhd | 1 | 3,881 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity roberts is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end roberts;
architecture rtl of roberts is
component roberts_process
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_width : in std_logic_vector(15 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component roberts_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal widthimg_reg_width : std_logic_vector (15 downto 0);
begin
roberts_process_inst : roberts_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_width => widthimg_reg_width,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
roberts_slave_inst : roberts_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_width => widthimg_reg_width,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
| gpl-3.0 | ed7a536c16f5295cc151ead0499408ec | 0.461221 | 3.348576 | false | false | false | false |
zatslogic/UDI_example | core_project/core_project.srcs/sources_1/ip/mult_16_x_16_res_32/mult_gen_v11_2/simulation/mult_gen_v11_2_xst_comp.vhd | 1 | 4,229 | -- $RCSfile: mult_gen_v11_2_xst_comp.vhd,v $ $Revision: 1.4 $ $Date: 2010/03/19 10:56:59 $
--------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package mult_gen_v11_2_xst_comp is
component mult_gen_v11_2_xst is
generic (
C_VERBOSITY : integer := 0;
C_MODEL_TYPE : integer := 0;
C_XDEVICEFAMILY : string := "virtex4";
C_A_WIDTH : integer := 18;
C_A_TYPE : integer := 0;
C_B_WIDTH : integer := 18;
C_B_TYPE : integer := 0;
C_OUT_HIGH : integer := 35;
C_OUT_LOW : integer := 0;
C_MULT_TYPE : integer := 1;
C_OPTIMIZE_GOAL : integer := 1;
C_HAS_CE : integer := 0;
C_HAS_SCLR : integer := 0;
C_CE_OVERRIDES_SCLR : integer := 1;
C_LATENCY : integer := -1;
C_CCM_IMP : integer := 0;
C_B_VALUE : string := "111111111111111111";
C_HAS_ZERO_DETECT : integer := 0;
C_ROUND_OUTPUT : integer := 0;
C_ROUND_PT : integer := 0);
port (
CLK : in std_logic := '1';
A : in std_logic_vector(C_A_WIDTH-1 downto 0) := (others => '0');
B : in std_logic_vector(C_B_WIDTH-1 downto 0) := (others => '0');
CE : in std_logic := '1';
SCLR : in std_logic := '0';
ZERO_DETECT : out std_logic_vector(1 downto 0) := (others => '0');
P : out std_logic_vector(C_OUT_HIGH-C_OUT_LOW downto 0) := (others => '0');
PCASC : out std_logic_vector(47 downto 0) := (others => '0'));
end component;
end mult_gen_v11_2_xst_comp;
| gpl-3.0 | a6d24e9be90c4fe138c70758ee77c517 | 0.589265 | 4.137965 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/RGMII_MAC/rgmii_rx.vhd | 1 | 23,770 | -------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : rgmii_rx.vhd
-- Author : liyi <[email protected]>
-- Company : OE@HUST
-- Created : 2012-11-14
-- Last update: 2013-05-21
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-11-14 1.0 root Created
-- 2013-05-13 1.0 liyi change dataen signal ,now the dest&sourcr mac
-- addr and type_len info are counted as valid data
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE work.eth_pkg.ALL;
-------------------------------------------------------------------------------
ENTITY rgmii_rx IS
PORT (
iClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
iRxData : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
iRxDV : IN STD_LOGIC;
iRxEr : IN STD_LOGIC;
-- these signals come from wishbone clock domian, NOT synchronized
iCheckSumIPCheck : IN STD_LOGIC;
iCheckSumTCPCheck : IN STD_LOGIC;
iCheckSumUDPCheck : IN STD_LOGIC;
iCheckSumICMPCheck : IN STD_LOGIC;
oEOF : OUT STD_LOGIC;
oSOF : OUT STD_LOGIC;
oCRCErr : OUT STD_LOGIC;
oRxErr : OUT STD_LOGIC;
oRxErr_Count : OUT STD_LOGIC_VECTOR(15 downto 0);
oLenErr : OUT STD_LOGIC;
oCheckSumErr : OUT STD_LOGIC;
iMyMAC : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
oGetARP : OUT STD_LOGIC;
oGetIPv4 : BUFFER STD_LOGIC;
oGetCtrl : OUT STD_LOGIC;
oGetRaw : BUFFER STD_LOGIC;
oTaged : OUT STD_LOGIC;
oTagInfo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
oStackTaged : BUFFER STD_LOGIC;
oTagInfo2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
oLink : OUT STD_LOGIC;
oSpeed : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
oDuplex : OUT STD_LOGIC;
oPayloadLen : BUFFER UNSIGNED(15 DOWNTO 0);
oRxData : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
oRxDV : OUT STD_LOGIC
);
END ENTITY rgmii_rx;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF rgmii_rx IS
SIGNAL sof, eof : STD_LOGIC;
SIGNAL crcEn, crcEn2 : STD_LOGIC;
SIGNAL crcErr : STD_LOGIC;
SIGNAL dvDly : STD_LOGIC_VECTOR(3 DOWNTO 0);
TYPE dataAyy_t IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL dataDly : dataAyy_t;
TYPE state_t IS (IDLE, SFD, DEST_MAC, SOURCE_MAC, FRAME_TYPE, TAG_INFO1, TAG_INFO2, PAYLOAD);
SIGNAL state : state_t;
SIGNAL byteCnt : UNSIGNED(15 DOWNTO 0);
SIGNAL destMACAddr : STD_LOGIC_VECTOR(47 DOWNTO 8);
SIGNAL frm4Me : STD_LOGIC;
SIGNAL rxDV, dataEn : STD_LOGIC;
SIGNAL rCheckSumOk : BOOLEAN;
--AJOUT FIFO RX
SIGNAL ff_reset_int, ff_rd_req_int, ff_wr_req_int, ff_empty_int, ff_full_int : STD_LOGIC;
--AJOUT JOHN DELAY
TYPE T_dly is array(2 downto 0) of std_logic_vector(7 downto 0);
signal oRxData_dly : T_dly;
signal oRxData_int : std_logic_vector(7 downto 0);
signal oRxDV_dly_2_int, oRxDV_dly_1_int, oRxDV_dly_0_int, oRxDV_int,
oSoF_int : std_logic;
signal oSoF_dly_int : std_logic_vector(6 downto 0);
--TEST
signal oLenErr_int, en_count_int : std_logic;
signal oRxErr_Count_int : UNSIGNED(15 DOWNTO 0);
BEGIN -- ARCHITECTURE rtl
-- check sum calc
blkCS : BLOCK IS
TYPE state_t IS (IDLE, IP4_HEAD, TCP, UDP, ICMP, UNKNOWN, DONE);
SIGNAL rState : state_t;
SIGNAL cRxDataD1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rCheckSum : UNSIGNED(31 DOWNTO 0);
SIGNAL cCheckSum : UNSIGNED(15 DOWNTO 0);
SIGNAL rIPCSOK : BOOLEAN; -- ip checksum ok
SIGNAL rByteCnt : UNSIGNED(15 DOWNTO 0);
SIGNAL cByteValid : STD_LOGIC;
SIGNAL rPesudoCS : UNSIGNED(18 DOWNTO 0);
SIGNAL rIPHeadLen : UNSIGNED(5 DOWNTO 0); -- 20~60 bytes
SIGNAL rTotalLen : UNSIGNED(15 DOWNTO 0);
SIGNAL cIPPayloadLen : UNSIGNED(15 DOWNTO 0);
SIGNAL rProtocol : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL cIPCSCheckEn : BOOLEAN;
SIGNAL cTCPCSCheckEn : BOOLEAN;
SIGNAL cICMPCSCheckEn : BOOLEAN;
SIGNAL cUDPCSCheckEn : BOOLEAN;
SIGNAL rGetCheckSum : BOOLEAN;
SIGNAL rCsCheckSync : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN -- BLOCK blkCS
cRxDataD1 <= dataDly(0);
cByteValid <= dvDly(0);
cCheckSum <= rCheckSum(31 DOWNTO 16) + rCheckSum(15 DOWNTO 0);
--cCheckSumOk <= cCheckSum = X"FFFF";
cIPPayloadLen <= rTotalLen - rIPHeadLen;
cIPCSCheckEn <= rCsCheckSync(1) = '1';
cTCPCSCheckEn <= rCsCheckSync(3) = '1';
cUDPCSCheckEn <= rCsCheckSync(5) = '1';
cICMPCSCheckEn <= rCsCheckSync(7) = '1';
PROCESS (iClk) IS
BEGIN
IF rising_edge(iClk) THEN
rCsCheckSync(1 DOWNTO 0) <= rCsCheckSync(0)&iCheckSumIPCheck;
rCsCheckSync(3 DOWNTO 2) <= rCsCheckSync(2)&iCheckSumTCPCheck;
rCsCheckSync(5 DOWNTO 4) <= rCsCheckSync(4)&iCheckSumUDPCheck;
rCsCheckSync(7 DOWNTO 6) <= rCsCheckSync(6)&iCheckSumICMPCheck;
END IF;
END PROCESS;
PROCESS (iClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
rState <= IDLE;
rCheckSum <= (OTHERS => '0');
rByteCnt <= (OTHERS => '0');
rPesudoCS <= (OTHERS => '0');
rIPHeadLen <= (OTHERS => '0');
rTotalLen <= (OTHERS => '0');
rProtocol <= (OTHERS => '0');
rCheckSumOk <= FALSE;
rGetCheckSum <= FALSE;
rIPCSOK <= FALSE;
en_count_int <= '0';
oRxErr_Count_int <= (othERS => '0');
ELSIF rising_edge(iClk) THEN
rGetCheckSum <= FALSE;
IF eof = '1' THEN
rState <= IDLE;
END IF;
if en_count_int = '1' then
oRxErr_Count_int <= oRxErr_Count_int + 1;
end if;
en_count_int <= '0';
CASE rState IS
WHEN IDLE =>
rPesudoCS <= (OTHERS => '0');
rCheckSum <= (OTHERS => '0');
rByteCnt <= X"0001";
rCheckSumOk <= TRUE;
rIPCSOK <= FALSE;
IF oGetIPv4 = '1' THEN
rState <= IP4_HEAD;
rCheckSumOk <= FALSE;
END IF;
---------------------------------------------------------------------
WHEN IP4_HEAD =>
IF cByteValid = '1' THEN
rByteCnt <= rByteCnt + 1;
IF rByteCnt(0) = '1' THEN -- higher byte
rCheckSum <= rCheckSum + to_integer(UNSIGNED(cRxDataD1)&X"00");
ELSE -- lower byte
rCheckSum <= rCheckSum + UNSIGNED(cRxDataD1);
END IF;
CASE rByteCnt(5 DOWNTO 0) IS
WHEN B"000001" =>
rIPHeadLen <= UNSIGNED(cRxDataD1(3 DOWNTO 0))&B"00";
WHEN B"000011" => rTotalLen(15 DOWNTO 8) <= UNSIGNED(cRxDataD1);
WHEN B"000100" => rTotalLen(7 DOWNTO 0) <= UNSIGNED(cRxDataD1);
WHEN B"001010" => -- Protocol
rPesudoCS <= rPesudoCS + UNSIGNED(cRxDataD1);
rProtocol <= cRxDataD1;
WHEN B"001011" =>
rPesudoCS <= rPesudoCS + cIPPayloadLen;
-- source &Destination ip addr
WHEN B"001101" | B"001111" | B"010001" | B"010011" =>
rPesudoCS <= rPesudoCS + to_integer(UNSIGNED(cRxDataD1)&X"00");
WHEN B"001110" | B"010000" | B"010010" | B"010100"=>
rPesudoCS <= rPesudoCS + UNSIGNED(cRxDataD1);
WHEN OTHERS => NULL;
END CASE;
IF rIPHeadLen = rByteCnt(5 DOWNTO 0) THEN
rGetCheckSum <= TRUE;
rState <= UNKNOWN;
CASE rProtocol IS
WHEN X"01" => -- ICMP
rState <= ICMP;
en_count_int <= '1';
WHEN X"06" => -- TCP
rState <= TCP;
WHEN X"11" => -- UDP
rState <= UDP;
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
---------------------------------------------------------------------
-- tcp & udp are the same,both contain a pesudo header
WHEN TCP | UDP =>
IF rGetCheckSum THEN
rIPCSOK <= NOT cIPCSCheckEn OR (cIPCSCheckEn AND cCheckSum = X"FFFF");
rCheckSum <= X"000"&B"0"&rPesudoCS;
END IF;
IF cByteValid = '1' THEN
rByteCnt <= rByteCnt + 1;
IF rByteCnt(0) = '1' THEN -- higher byte
IF rGetCheckSum THEN
rCheckSum <= X"000"&'0'&rPesudoCS + to_integer(UNSIGNED(cRxDataD1)&X"00");
ELSE
rCheckSum <= rCheckSum + to_integer(UNSIGNED(cRxDataD1)&X"00");
END IF;
ELSE -- lower byte
rCheckSum <= rCheckSum + UNSIGNED(cRxDataD1);
END IF;
IF rByteCnt = rTotalLen THEN
rState <= DONE;
rGetCheckSum <= TRUE;
END IF;
END IF;
---------------------------------------------------------------------
WHEN ICMP =>
IF rGetCheckSum THEN
rIPCSOK <= NOT cIPCSCheckEn OR (cIPCSCheckEn AND cCheckSum = X"FFFF");
rCheckSum <= (OTHERS => '0');
END IF;
IF cByteValid = '1' THEN
rByteCnt <= rByteCnt + 1;
IF rByteCnt(0) = '1' THEN -- higher byte
IF rGetCheckSum THEN
rCheckSum <= X"0000"&UNSIGNED(cRxDataD1)&X"00";
ELSE
rCheckSum <= rCheckSum + to_integer(UNSIGNED(cRxDataD1)&X"00");
END IF;
ELSE -- lower byte
rCheckSum <= rCheckSum + UNSIGNED(cRxDataD1);
END IF;
IF rByteCnt = rTotalLen THEN
rState <= DONE;
rGetCheckSum <= TRUE;
END IF;
END IF;
---------------------------------------------------------------------
WHEN UNKNOWN =>
IF rGetCheckSum THEN
rCheckSumOk <= NOT cIPCSCheckEn OR (cIPCSCheckEn AND cCheckSum = X"FFFF");
END IF;
---------------------------------------------------------------------
WHEN DONE =>
IF rGetCheckSum THEN
CASE rProtocol IS
WHEN X"01" =>
rCheckSumOk <= rIPCSOK AND
(NOT cICMPCSCheckEn OR
(cICMPCSCheckEn AND cCheckSum = X"FFFF"));
WHEN X"06" =>
rCheckSumOk <= rIPCSOK AND
(NOT cTCPCSCheckEn OR
(cTCPCSCheckEn AND cCheckSum = X"FFFF"));
WHEN X"11" =>
rCheckSumOk <= rIPCSOK AND
(NOT cUDPCSCheckEn OR
(cUDPCSCheckEn AND cCheckSum = X"FFFF"));
WHEN OTHERS => NULL;
END CASE;
END IF;
---------------------------------------------------------------------
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
END BLOCK blkCS;
-- USE normal inter-frame TO get link information
PROCESS (iClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
oLink <= '0';
oSpeed <= B"00";
oDuplex <= '0';
ELSIF rising_edge(iClk) THEN
IF iRxEr = '0' AND iRxDV = '0' THEN
oLink <= iRxData(0); -- 0=down,1=up
oSpeed <= iRxData(2 DOWNTO 1); -- 00=10Mbps,01=100Mbps,10=1000Mbps,11=reserved
oDuplex <= iRxData(3); -- 0=half-duplex,1=full-duplex
END IF;
END IF;
END PROCESS;
--CRC
crcEn2 <= crcEn AND iRxDV AND NOT iRxEr;
crcCheck : ENTITY work.eth_crc32
PORT MAP (
iClk => iClk,
iRst_n => iRst_n,
iInit => sof,
iCalcEn => crcEn2,
iData => iRxData,
oCRC => OPEN,
oCRCErr => crcErr);
--oEOF <= eof;
oCRCErr <= crcErr;
-- delay! IN order TO get OUT OF the CRC part
rxDV <= iRxDV AND dataEn AND NOT iRxEr;
oRxData_int <= dataDly(3);
oRxDV_int <= dvDly(3) AND rxDV;
--oRxDV <= dvDly(3) AND dataEn; -- changed @ 2013-05-20
PROCESS (iClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
dvDly <= (OTHERS => '0');
dataDly(0) <= (OTHERS => '0');
dataDly(1) <= (OTHERS => '0');
dataDly(2) <= (OTHERS => '0');
dataDly(3) <= (OTHERS => '0');
ELSIF rising_edge(iClk) THEN
dvDly <= dvDly(2 DOWNTO 0) & rxDV;
dataDly(0) <= iRxData;
dataDly(1) <= dataDly(0);
dataDly(2) <= dataDly(1);
dataDly(3) <= dataDly(2);
END IF;
END PROCESS;
--AJOUT JOHN DELAI SUR DV ET DATA OUT
--oRxData <= oRxData_dly(2);
oRxDV <= oRxDV_dly_2_int;
oSoF <= oSoF_dly_int(6);
PROCESS (iClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
oRxDV_dly_0_int <= '0';
oRxDV_dly_1_int <= '0';
oRxDV_dly_2_int <= '0';
oEOF <= '0';
oSoF_dly_int <= (others => '0');
oRxData_dly(0) <= (OTHERS => '0');
oRxData_dly(1) <= (OTHERS => '0');
oRxData_dly(2) <= (OTHERS => '0');
ELSIF rising_edge(iClk) THEN
oRxDV_dly_0_int <= oRxDV_int;
oRxDV_dly_1_int <= oRxDV_dly_0_int;
oRxDV_dly_2_int <= oRxDV_dly_1_int;
oEOF <= eof;
oSoF_dly_int <= oSoF_dly_int(5 downto 0) & oSoF_int;
oRxData_dly(0) <= oRxData_int;
oRxData_dly(1) <= oRxData_dly(0);
oRxData <= oRxData_dly(1);
END IF;
END PROCESS;
--TEST
oRxErr_Count <= std_logic_vector(oRxErr_Count_int);
oLenErr <= oLenErr_int;
--
PROCESS (iClk, iRst_n) IS
VARIABLE ethType : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
IF iRst_n = '0' THEN
state <= IDLE;
eof <= '0';
byteCnt <= (OTHERS => '0');
oPayloadLen <= (OTHERS => '0');
oGetCtrl <= '0';
oGetARP <= '0';
oGetIPv4 <= '0';
oGetRaw <= '0';
--oDrop <= '0';
frm4Me <= '0';
crcEn <= '0';
sof <= '0';
dataEn <= '0';
destMACAddr <= (OTHERS => '0');
oTagInfo2 <= (OTHERS => '0');
oTaged <= '0';
oStackTaged <= '0';
oTagInfo <= (OTHERS => '0');
oLenErr_int <= '0';
oCheckSumErr <= '0';
oSOF_int <= '0';
ELSIF rising_edge(iClk) THEN
--oGetCtrl <= '0';
--oGetARP <= '0';
--oGetIPv4 <= '0';
--oGetRaw <= '0';
eof <= '0';
--oDrop <= '0';
sof <= '0';
oSOF_int <= '0';
IF iRxDV = '1' AND iRxEr = '1' THEN
oRxErr <= '1';
END IF;
-- IF oLenErr_int = '1' then
-- oRxErr_Count_int <= oRxErr_Count_int + 1;
-- end if;
CASE state IS
WHEN IDLE =>
crcEn <= '0';
dataEn <= '0';
frm4Me <= '0';
oGetCtrl <= '0';
oGetARP <= '0';
oGetIPv4 <= '0';
oGetRaw <= '0';
oRxErr <= '0';
oTaged <= '0';
oStackTaged <= '0';
oLenErr_int <= '0';
oCheckSumErr <= '0';
IF iRxData = X"55" THEN
state <= SFD;
byteCnt <= (OTHERS => '0');
sof <= '1';
END IF;
-----------------------------------------------------------------------
WHEN SFD =>
IF iRxData = X"55" THEN
byteCnt <= byteCnt + 1;
ELSIF iRxData = X"D5" THEN
IF byteCnt(2 DOWNTO 0) = B"110" THEN
state <= DEST_MAC;
crcEn <= '1';
dataEn <= '1'; -- 2013-05-13
oSOF_int <= '1';
byteCnt <= (OTHERS => '0');
ELSE
state <= IDLE;
END IF;
ELSE
state <= IDLE;
END IF;
IF iRxDV = '0' THEN
state <= IDLE;
eof <= '1';
oLenErr_int <= '1';
END IF;
-----------------------------------------------------------------------
WHEN DEST_MAC =>
IF iRxDV = '1' AND iRxEr = '0' THEN
byteCnt <= byteCnt + 1;
CASE byteCnt(2 DOWNTO 0) IS
WHEN B"000" => destMACAddr(47 DOWNTO 40) <= iRxData;
WHEN B"001" => destMACAddr(39 DOWNTO 32) <= iRxData;
WHEN B"010" => destMACAddr(31 DOWNTO 24) <= iRxData;
WHEN B"011" => destMACAddr(23 DOWNTO 16) <= iRxData;
WHEN B"100" => destMACAddr(15 DOWNTO 8) <= iRxData;
WHEN B"101" =>
byteCnt(2 DOWNTO 0) <= (OTHERS => '0');
state <= SOURCE_MAC;
IF destMACAddr(47 DOWNTO 8)&iRxData = iMyMAC -- unicast
OR destMACAddr(47 DOWNTO 8)&iRxData = MAC_ADDR_CTRL -- multicast for flow control
OR destMACAddr(47 DOWNTO 8)&iRxData = X"FFFFFFFFFFFF" THEN -- broadcast
--oDrop <= '1';
frm4Me <= '1';
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
IF iRxDV = '0' THEN
state <= IDLE;
eof <= '1';
oLenErr_int <= '1';
END IF;
-----------------------------------------------------------------------
WHEN SOURCE_MAC =>
IF iRxDV = '1' AND iRxEr = '0' THEN
byteCnt <= byteCnt + 1;
IF byteCnt(2 DOWNTO 0) = B"101" THEN
state <= FRAME_TYPE;
byteCnt(2 DOWNTO 0) <= (OTHERS => '0');
END IF;
END IF;
IF iRxDV = '0' THEN
state <= IDLE;
eof <= '1';
oLenErr_int <= '1';
END IF;
-----------------------------------------------------------------------
WHEN FRAME_TYPE =>
IF iRxDV = '1' AND iRxEr = '0' THEN
byteCnt <= byteCnt + 1;
IF byteCnt(0) = '0' THEN
destMACAddr(15 DOWNTO 8) <= iRxData;
ELSE
byteCnt(1 DOWNTO 0) <= (OTHERS => '0');
ethType := destMACAddr(15 DOWNTO 8) & iRxData;
IF ethType < X"0600" AND ethType > X"0000" THEN
oGetRaw <= frm4Me;
state <= PAYLOAD;
dataEn <= '1';
END IF;
oPayloadLen <= UNSIGNED(ethType);
-- check the ethnert frame TYPE ,only ARP AND IP PACKAGE are wanted
CASE ethType IS
WHEN ETH_TYPE_IPv4 =>
oGetIPv4 <= frm4Me;
state <= PAYLOAD;
dataEn <= '1';
WHEN ETH_TYPE_ARP =>
oGetARP <= frm4Me;
state <= PAYLOAD;
dataEn <= '1';
WHEN ETH_TYPE_CTRL =>
oGetCtrl <= frm4Me;
state <= PAYLOAD;
dataEn <= '1';
WHEN x"8100" =>
oTaged <= '1';
state <= TAG_INFO1;
dataEn <= '0';
WHEN x"88A8" | x"9100" =>
oStackTaged <= '1';
state <= TAG_INFO1;
dataEn <= '0';
WHEN OTHERS => --oDrop <= '1';
state <= PAYLOAD;
dataEn <= '0';
frm4Me <= '0'; -- add @ 2013-05-13
END CASE;
END IF;
END IF;
IF iRxDV = '0' THEN
state <= IDLE;
eof <= '1';
oLenErr_int <= '1';
END IF;
-----------------------------------------------------------------------
WHEN TAG_INFO1 =>
IF iRxDV = '1' AND iRxEr = '0' THEN
byteCnt <= byteCnt + 1;
IF byteCnt(0) = '0' THEN
oTagInfo(15 DOWNTO 8) <= iRxData;
ELSE
byteCnt(1 DOWNTO 0) <= (OTHERS => '0');
oTagInfo(7 DOWNTO 0) <= iRxData;
IF oStackTaged = '1' THEN
state <= TAG_INFO2;
ELSE
state <= FRAME_TYPE;
END IF;
END IF;
END IF;
IF iRxDV = '0' THEN
state <= IDLE;
eof <= '1';
oLenErr_int <= '1';
END IF;
-----------------------------------------------------------------------
WHEN TAG_INFO2 =>
IF iRxDV = '1' AND iRxEr = '0' THEN
byteCnt <= byteCnt + 1;
CASE byteCnt(1 DOWNTO 0) IS
-- we do NOT check,but 0x8100 is expected!
WHEN B"00" => NULL;
WHEN B"01" => NULL;
WHEN B"10" =>
oTagInfo2(15 DOWNTO 8) <= iRxData;
WHEN B"11" =>
oTagInfo2(7 DOWNTO 0) <= iRxData;
byteCnt(2 DOWNTO 0) <= (OTHERS => '0');
state <= FRAME_TYPE;
WHEN OTHERS => NULL;
END CASE;
END IF;
IF iRxDV = '0' THEN
state <= IDLE;
eof <= '1';
oLenErr_int <= '1';
END IF;
-----------------------------------------------------------------------
WHEN PAYLOAD =>
IF oGetRaw = '1' THEN
IF byteCnt + 1 = oPayloadLen THEN -- PAD truncation
dataEn <= '0';
END IF;
END IF;
IF iRxDV = '1' THEN
IF iRxEr = '0' THEN
byteCnt <= byteCnt + 1;
END IF;
ELSE
state <= IDLE;
eof <= '1';
IF rCheckSumOk THEN
oCheckSumErr <= '0';
ELSE
oCheckSumErr <= '1';
END IF;
IF frm4Me = '0' THEN -- add @ 2013-05-13
oLenErr_int <= '1';
END IF;
IF oGetRaw = '0' THEN
-- oPayloadLen <= byteCnt - 4; change @ 2013-05-13
oPayloadLen <= 14 + byteCnt - 4;
ELSIF oPayloadLen > byteCnt - 4 THEN
oLenErr_int <= '1';
END IF;
-- add @ 2013-05-13
IF oGetRaw = '1' THEN
oPayloadLen <= oPayloadLen + 14;
END IF;
IF byteCnt > X"0600" OR byteCnt < X"0020" THEN
oLenErr_int <= '1';
END IF;
END IF;
WHEN OTHERS => state <= IDLE;
END CASE;
END IF;
END PROCESS;
END ARCHITECTURE rtl;
| gpl-3.0 | eca52528c6d0976d906d7022637d8764 | 0.42865 | 3.870705 | false | false | false | false |
DreamIP/GPStudio | support/io/gps/hdl/gps.vhd | 1 | 2,892 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity gps is
generic (
CLK_PROC_FREQ : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
--------------------- external ports --------------------
RXD : in std_logic;
TXD : out std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end gps;
architecture rtl of gps is
component top_GPS
port (
clk : in std_logic;
reset : in std_logic;
RXD : in std_logic;
TXD : out std_logic;
parameters : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(7 downto 0);
flow_valid : out std_logic;
data_valid : out std_logic
);
end component;
component gps_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
enable_reg : out std_logic_vector(31 downto 0);
sat_reg : out std_logic_vector(31 downto 0);
update_reg : out std_logic_vector(31 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal enable_reg : std_logic_vector (31 downto 0);
signal sat_reg : std_logic_vector (31 downto 0);
signal update_reg : std_logic_vector (31 downto 0);
signal parameters : std_logic_vector(31 downto 0);
begin
gps_slave_inst : gps_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
enable_reg => enable_reg,
sat_reg => sat_reg,
update_reg => update_reg,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
top_GPS_inst : top_GPS
port map(
clk => clk_proc,
reset => reset_n,
RXD => RXD,
TXD => TXD,
parameters => parameters,
data_out => out_data ,
flow_valid => out_fv ,
data_valid => out_dv
);
parameters(31 downto 22) <= enable_reg(0) & sat_reg(0) & update_reg(7 downto 0);
end rtl;
| gpl-3.0 | c404607955eaeefe6ee6957b99941e24 | 0.516598 | 3.076596 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_Video_DMA.vhd | 1 | 12,213 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module store and retrieves video frames to and from memory. *
-- * *
-- ******************************************************************************
`undef USE_TO_MEMORY
`define USE_32BIT_MASTER
ENTITY Video_System_Video_DMA IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
GENERIC (
DW :INTEGER := 15; -- Frame's datawidth
EW :INTEGER := 0; -- Frame's empty width
WIDTH :INTEGER := 320; -- Frame's width in pixels
HEIGHT :INTEGER := 240; -- Frame's height in lines
AW :INTEGER := 16; -- Frame's address width
WW :INTEGER := 8; -- Frame width's address width
HW :INTEGER := 7; -- Frame height's address width
MDW :INTEGER := 15; -- Avalon master's datawidth
DEFAULT_BUFFER_ADDRESS :STD_LOGIC_VECTOR(31 DOWNTO 0) := B"00000000000000000000000000000000";
DEFAULT_BACK_BUF_ADDRESS :STD_LOGIC_VECTOR(31 DOWNTO 0) := B"00000000000000000000000000000000";
ADDRESSING_BITS :STD_LOGIC_VECTOR(15 DOWNTO 0) := B"0000100000001001";
COLOR_BITS :STD_LOGIC_VECTOR( 3 DOWNTO 0) := B"1111";
COLOR_PLANES :STD_LOGIC_VECTOR( 1 DOWNTO 0) := B"00"
);
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
stream_data :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_startofpacket :IN STD_LOGIC;
stream_endofpacket :IN STD_LOGIC;
stream_empty :IN STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_valid :IN STD_LOGIC;
master_waitrequest :IN STD_LOGIC;
slave_address :IN STD_LOGIC_VECTOR( 1 DOWNTO 0);
slave_byteenable :IN STD_LOGIC_VECTOR( 3 DOWNTO 0);
slave_read :IN STD_LOGIC;
slave_write :IN STD_LOGIC;
slave_writedata :IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Bidirectional
-- Outputs
stream_ready :BUFFER STD_LOGIC;
master_address :BUFFER STD_LOGIC_VECTOR(31 DOWNTO 0);
master_write :BUFFER STD_LOGIC;
master_writedata :BUFFER STD_LOGIC_VECTOR(MDW DOWNTO 0);
slave_readdata :BUFFER STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END Video_System_Video_DMA;
ARCHITECTURE Behaviour OF Video_System_Video_DMA IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
SIGNAL inc_address :STD_LOGIC;
SIGNAL reset_address :STD_LOGIC;
SIGNAL buffer_start_address :STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL reading_last_pixel_in_frame : STD_LOGIC;
-- Internal Registers
SIGNAL w_address :STD_LOGIC_VECTOR(WW DOWNTO 0); -- Frame's width address
SIGNAL h_address :STD_LOGIC_VECTOR(HW DOWNTO 0); -- Frame's height address
-- State Machine Registers
-- Integers
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
COMPONENT altera_up_video_dma_control_slave
GENERIC (
DEFAULT_BUFFER_ADDRESS :STD_LOGIC_VECTOR(31 DOWNTO 0);
DEFAULT_BACK_BUF_ADDRESS :STD_LOGIC_VECTOR(31 DOWNTO 0);
WIDTH :INTEGER;
HEIGHT :INTEGER;
ADDRESSING_BITS :STD_LOGIC_VECTOR(15 DOWNTO 0);
COLOR_BITS :STD_LOGIC_VECTOR( 3 DOWNTO 0);
COLOR_PLANES :STD_LOGIC_VECTOR( 1 DOWNTO 0);
ADDRESSING_MODE :STD_LOGIC
);
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
address :IN STD_LOGIC_VECTOR( 1 DOWNTO 0);
byteenable :IN STD_LOGIC_VECTOR( 3 DOWNTO 0);
read :IN STD_LOGIC;
write :IN STD_LOGIC;
writedata :IN STD_LOGIC_VECTOR(31 DOWNTO 0);
swap_addresses_enable :IN STD_LOGIC;
-- Bi-Directional
-- Outputs
readdata :BUFFER STD_LOGIC_VECTOR(31 DOWNTO 0);
current_start_address :BUFFER STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT altera_up_video_dma_to_memory
GENERIC (
DW :INTEGER;
EW :INTEGER;
MDW :INTEGER
);
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
stream_data :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_startofpacket :IN STD_LOGIC;
stream_endofpacket :IN STD_LOGIC;
stream_empty :IN STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_valid :IN STD_LOGIC;
master_waitrequest :IN STD_LOGIC;
-- Bidirectional
-- Outputs
stream_ready :BUFFER STD_LOGIC;
master_write :BUFFER STD_LOGIC;
master_writedata :BUFFER STD_LOGIC_VECTOR(MDW DOWNTO 0);
inc_address :BUFFER STD_LOGIC;
reset_address :BUFFER STD_LOGIC
);
END COMPONENT;
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
-- Output Registers
-- Internal Registers
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
w_address <= (OTHERS => '0');
h_address <= (OTHERS => '0');
ELSIF (reset_address = '1') THEN
w_address <= (OTHERS => '0');
h_address <= (OTHERS => '0');
ELSIF (inc_address = '1') THEN
IF (w_address = (WIDTH - 1)) THEN
w_address <= (OTHERS => '0');
h_address <= h_address + 1;
ELSE
w_address <= w_address + 1;
END IF;
END IF;
END IF;
END PROCESS;
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
-- Output Assignments
master_address <= buffer_start_address +
h_address & w_address & '0';
-- Internal Assignments
reading_last_pixel_in_frame <= '1' WHEN (w_address = (WIDTH - 1))
AND (h_address = (HEIGHT - 1)) ELSE
'0';
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
DMA_Control_Slave : altera_up_video_dma_control_slave
GENERIC MAP (
DEFAULT_BUFFER_ADDRESS => DEFAULT_BUFFER_ADDRESS,
DEFAULT_BACK_BUF_ADDRESS => DEFAULT_BACK_BUF_ADDRESS,
WIDTH => WIDTH,
HEIGHT => HEIGHT,
ADDRESSING_BITS => ADDRESSING_BITS,
COLOR_BITS => COLOR_BITS,
COLOR_PLANES => COLOR_PLANES,
ADDRESSING_MODE => '0'
)
PORT MAP (
-- Inputs
clk => clk,
reset => reset,
address => slave_address,
byteenable => slave_byteenable,
read => slave_read,
write => slave_write,
writedata => slave_writedata,
swap_addresses_enable => reset_address,
-- Bi-Directional
-- Outputs
readdata => slave_readdata,
current_start_address => buffer_start_address
);
From_Stream_to_Memory : altera_up_video_dma_to_memory
GENERIC MAP (
DW => DW,
EW => EW,
MDW => MDW
)
PORT MAP (
-- Inputs
clk => clk,
reset => reset,
stream_data => stream_data,
stream_startofpacket => stream_startofpacket,
stream_endofpacket => stream_endofpacket,
stream_empty => stream_empty,
stream_valid => stream_valid,
master_waitrequest => master_waitrequest,
-- Bidirectional
-- Outputs
stream_ready => stream_ready,
master_write => master_write,
master_writedata => master_writedata,
inc_address => inc_address,
reset_address => reset_address
);
END Behaviour;
| gpl-2.0 | 8a1e552c402aa02b2a06090d287378e5 | 0.48563 | 4.049403 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/openfilter-rtl-ea.vhd | 3 | 12,596 | -------------------------------------------------------------------------------
--! @file openfilter-rtl-ea.vhd
--
--! @brief OpenFILTER
--
--! @details This is the openFILTER used for blocking failures on the RMII lines.
--! Note: RxDv and RxDat have to be synchron to iClk
--! The following Conditions are checked:
--! * RxDV >163.64µsec HIGH -> invalid
--! * RxDV <0.64µsec LOW -> invalid
--! * RxDV 4x <5.12µsec HIGH -> invalid
--! * RxDV >5.12µsec HIGH -> valid
--! * iRxError HIGH -> invalid
--! If invalid deactivation of port, until RxDv and iRxError > 10.24µsec low
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use openmac package
use work.openmacPkg.all;
entity openfilter is
port (
--! Reset
iRst : in std_logic;
--! RMII Clock
iClk : in std_logic;
--! RMII receive path in
iRx : in tRmiiPath;
--! RMII receive path out
oRx : out tRmiiPath;
--! RMII transmit path in
iTx : in tRmiiPath;
--! RMII transmit path out
oTx : out tRmiiPath;
--! RMII receive error
iRxError : in std_logic
);
end entity openfilter;
architecture rtl of openfilter is
--! Filter FSM type
type tFiltState is (
fs_init,
fs_GAP2short, fs_GAPext, fs_GAPok,
fs_FRMnopre, fs_FRMpre2short, fs_FRMpreOk,
fs_FRM2short, fs_FRMok, fs_FRM2long, fs_BlockAll
);
signal FiltState : tFiltState;
signal RxDel : tRmiiPathArray(3 downto 0);
signal FrameShift : std_logic;
signal LastFrameNOK : std_logic;
signal StCnt : std_logic_vector(13 downto 0);
signal BlockRxPort : std_logic;
begin
---------------------------------------------------------------------------
-- INPUT
---------------------------------------------------------------------------
RxDel(0) <= iRx;
BlockRxPort <= cActivated when (FiltState = fs_FRMnopre or
FiltState = fs_BlockAll or
LastFrameNOK = cActivated) else
cInactivated;
---------------------------------------------------------------------------
-- OUTPUT MUX
---------------------------------------------------------------------------
oRx <= cRmiiPathInit when BlockRxPort = cActivated else
RxDel(3) when FrameShift = cActivated else
RxDel(1);
oTx <= iTx;
doFsm : process(iRst, iClk)
variable RstStCnt : std_logic;
begin
if iRst = cActivated then
StCnt <= (others => cInactivated);
FiltState <= fs_init;
FrameShift <= cInactivated;
RxDel(3 downto 1) <= (others => cRmiiPathInit);
LastFrameNOK <= cInactivated;
elsif rising_edge(iClk) then
RxDel(3 downto 1) <= RxDel(2 downto 0);
-- DEFAULT --
RstStCnt := cInactivated;
case FiltState is
---------------------------------------------------------------
-- INIT
---------------------------------------------------------------
when fs_init =>
FiltState <= fs_GAP2short;
RstStCnt := cActivated;
---------------------------------------------------------------
-- GAP 2 SHORT
---------------------------------------------------------------
when fs_GAP2short =>
FrameShift <= cInactivated;
if StCnt(4) = cActivated then
-- 360ns
FiltState <= fs_GAPext;
end if;
if RxDel(0).enable = cActivated then
-- Gap < 360 ns -> too short -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
end if;
---------------------------------------------------------------
-- GAP EXTend
---------------------------------------------------------------
when fs_GAPext =>
if StCnt(5 downto 0) = "101110" then
FiltState <= fs_GAPok;
end if;
if RxDel(0).enable = cActivated then
-- GAP [360ns .. 960ns] -> short, but ok -> Start Frame
RstStCnt := cActivated;
FrameShift <= cActivated;
if RxDel(0).data = "01" then
-- GAP > 960ns -> OK -> Start Frame (preamble already beginning)
FiltState <= fs_FRMpre2short;
else
-- GAP > 960ns -> OK -> Start Frame and wait of preamble
FiltState <= fs_FRMnopre;
end if;
end if;
---------------------------------------------------------------
-- GAP OK
---------------------------------------------------------------
when fs_GAPok =>
if RxDel(0).enable = cActivated then
RstStCnt := cActivated;
if RxDel(0).data = "01" then
-- GAP > 960ns -> OK -> Start Frame (preamble already beginning)
FiltState <= fs_FRMpre2short;
else
-- GAP > 960ns -> OK -> Start Frame and wait of preamble
FiltState <= fs_FRMnopre;
end if;
end if;
---------------------------------------------------------------
-- FRAME, BUT STILL NO PREAMBLE
---------------------------------------------------------------
when fs_FRMnopre =>
if (StCnt(5) = cActivated or
RxDel(0).data = "11" or RxDel(0).data = "10" or
(RxDel(0).enable = cInactivated and RxDel(1).enable = cInactivated)) then
-- no preamble for >=660 ns or preamble wrong -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
elsif RxDel(0).data = "01" then
-- preamble starts -> Check Preamble
FiltState <= fs_FRMpre2short;
RstStCnt := cActivated;
end if;
---------------------------------------------------------------
-- FRAME CHECK PREAMBLE TOO SHORT
---------------------------------------------------------------
when fs_FRMpre2short =>
if (RxDel(0).data /= "01" or (RxDel(0).enable = cInactivated and
RxDel(1).enable = cInactivated)) then
-- preamble wrong -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
elsif StCnt(3) = cActivated then
-- preamble ok for 180 ns -> Preamble OK
FiltState <= fs_FRMpreOk;
end if;
---------------------------------------------------------------
-- FRAME CHECK PREAMBLE OK
---------------------------------------------------------------
when fs_FRMpreOk =>
if RxDel(0).data /= "01" then
-- preamble done -> Start Frame
FiltState <= fs_FRMok;
end if;
if ((StCnt(5) = cActivated and StCnt(2) = cActivated) or
(RxDel(0).enable = cInactivated and RxDel(1).enable = cInactivated)) then
-- preamble to long for 740 ns -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
end if;
-- preamble is OK
LastFrameNOK <= cInactivated;
---------------------------------------------------------------
-- FRAME OK
---------------------------------------------------------------
when fs_FRMok =>
if StCnt(13) = cActivated then
-- FRAME > 163,842 us -> too long -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
end if;
if RxDel(0).enable = cInactivated and RxDel(1).enable = cInactivated then
-- FRAME [163,842 us] -> OK -> Start GAP
FiltState <= fs_GAP2short;
RstStCnt := cActivated;
end if;
---------------------------------------------------------------
-- BLOCK FILTER
---------------------------------------------------------------
when fs_BlockAll =>
if StCnt(2) = cActivated then
-- Block for 100 nsec
FiltState <= fs_GAP2short;
RstStCnt := cActivated;
end if;
if RxDel(0).enable = cActivated then
-- Rxdv != cInactivated -> Reset Wait Period
RstStCnt := cActivated;
end if;
-- block next rx frame (until receive a valid preamble)
LastFrameNOK <= cActivated;
when others =>
FiltState <= fs_init;
end case;
if iRxError = cActivated then
-- iRxError -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
end if;
-- State Counter --
StCnt <= std_logic_vector(unsigned(StCnt) + 1);
if RstStCnt = cActivated then
StCnt <= (others => cInactivated);
end if;
end if;
end process;
end rtl;
| gpl-2.0 | c1976b813a4a8eb02e6625f3da69d2fc | 0.413465 | 6.067437 | false | false | false | false |
hoglet67/ElectronFpga | src/xilinx/DCM/dcm2.vhd | 1 | 2,015 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm2 is
port (CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic);
end dcm2;
architecture BEHAVIORAL of dcm2 is
signal CLK0_BUF : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLKFX_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 4.0, -- 33.33 = 16 * 25 / 12
CLKFX_MULTIPLY => 25,
CLKFX_DIVIDE => 12,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 62.50,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => CLK0_BUF,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => CLK0_BUF,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| gpl-3.0 | a8ba7f6ff6c47f4b442c2ea444848e20 | 0.402978 | 4.314775 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_CPU_jtag_debug_module_sysclk.vhd | 1 | 6,915 | --Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_jtag_debug_module_sysclk is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal ir_in : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal sr : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal vs_udr : IN STD_LOGIC;
signal vs_uir : IN STD_LOGIC;
-- outputs:
signal jdo : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
signal take_action_break_a : OUT STD_LOGIC;
signal take_action_break_b : OUT STD_LOGIC;
signal take_action_break_c : OUT STD_LOGIC;
signal take_action_ocimem_a : OUT STD_LOGIC;
signal take_action_ocimem_b : OUT STD_LOGIC;
signal take_action_tracectrl : OUT STD_LOGIC;
signal take_action_tracemem_a : OUT STD_LOGIC;
signal take_action_tracemem_b : OUT STD_LOGIC;
signal take_no_action_break_a : OUT STD_LOGIC;
signal take_no_action_break_b : OUT STD_LOGIC;
signal take_no_action_break_c : OUT STD_LOGIC;
signal take_no_action_ocimem_a : OUT STD_LOGIC;
signal take_no_action_tracemem_a : OUT STD_LOGIC
);
end entity Video_System_CPU_jtag_debug_module_sysclk;
architecture europa of Video_System_CPU_jtag_debug_module_sysclk is
component altera_std_synchronizer is
GENERIC (
depth : NATURAL
);
PORT (
signal dout : OUT STD_LOGIC;
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal din : IN STD_LOGIC
);
end component altera_std_synchronizer;
signal enable_action_strobe : STD_LOGIC;
signal internal_jdo1 : STD_LOGIC_VECTOR (37 DOWNTO 0);
signal ir : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal jxuir : STD_LOGIC;
signal sync2_udr : STD_LOGIC;
signal sync2_uir : STD_LOGIC;
signal sync_udr : STD_LOGIC;
signal sync_uir : STD_LOGIC;
signal unxunused_resetxx2 : STD_LOGIC;
signal unxunused_resetxx3 : STD_LOGIC;
signal update_jdo_strobe : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of jdo : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
attribute ALTERA_ATTRIBUTE of sync2_udr : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103""";
attribute ALTERA_ATTRIBUTE of sync2_uir : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103""";
begin
unxunused_resetxx2 <= std_logic'('1');
the_altera_std_synchronizer2 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => clk,
din => vs_udr,
dout => sync_udr,
reset_n => unxunused_resetxx2
);
unxunused_resetxx3 <= std_logic'('1');
the_altera_std_synchronizer3 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => clk,
din => vs_uir,
dout => sync_uir,
reset_n => unxunused_resetxx3
);
process (clk)
begin
if clk'event and clk = '1' then
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr AND NOT sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir AND NOT sync2_uir;
end if;
end process;
take_action_ocimem_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("00"))))) AND NOT internal_jdo1(35)) AND internal_jdo1(34);
take_no_action_ocimem_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("00"))))) AND NOT internal_jdo1(35)) AND NOT internal_jdo1(34);
take_action_ocimem_b <= (enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("00"))))) AND internal_jdo1(35);
take_action_tracemem_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("01"))))) AND NOT internal_jdo1(37)) AND internal_jdo1(36);
take_no_action_tracemem_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("01"))))) AND NOT internal_jdo1(37)) AND NOT internal_jdo1(36);
take_action_tracemem_b <= (enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("01"))))) AND internal_jdo1(37);
take_action_break_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND NOT internal_jdo1(36)) AND internal_jdo1(37);
take_no_action_break_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND NOT internal_jdo1(36)) AND NOT internal_jdo1(37);
take_action_break_b <= (((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND internal_jdo1(36)) AND NOT internal_jdo1(35)) AND internal_jdo1(37);
take_no_action_break_b <= (((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND internal_jdo1(36)) AND NOT internal_jdo1(35)) AND NOT internal_jdo1(37);
take_action_break_c <= (((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND internal_jdo1(36)) AND internal_jdo1(35)) AND internal_jdo1(37);
take_no_action_break_c <= (((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND internal_jdo1(36)) AND internal_jdo1(35)) AND NOT internal_jdo1(37);
take_action_tracectrl <= (enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("11"))))) AND internal_jdo1(15);
process (clk)
begin
if clk'event and clk = '1' then
if std_logic'(jxuir) = '1' then
ir <= ir_in;
end if;
if std_logic'(update_jdo_strobe) = '1' then
internal_jdo1 <= sr;
end if;
end if;
end process;
--vhdl renameroo for output signals
jdo <= internal_jdo1;
end europa;
| gpl-2.0 | c35be8ddca912e098587c1fe3f0d2302 | 0.634563 | 3.645229 | false | false | false | false |
DreamIP/GPStudio | support/component/gp_com/com_to_flow/com_to_flow.vhd | 1 | 4,907 | -- **************************************************************************
-- FLOW IN
-- **************************************************************************
-- This component is connected to USB Driver and generate FV/DV/data as outputs
-- 26/11/2014 - creation - C.Bourrasset
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ComFlow_pkg.all;
entity com_to_flow is
generic (
FIFO_DEPTH : POSITIVE := 1024;
FLOW_ID : INTEGER := 1;
FLAGS_CODES : my_array_t := InitFlagCodes;
FLOW_SIZE : INTEGER := 16;
DATA_HAL_SIZE : INTEGER := 16
);
port (
clk_proc : in std_logic;
clk_hal : in std_logic;
rst_n : in std_logic;
data_wr_i : in std_logic;
data_i : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
pktend_i : in std_logic;
enable_i : in std_logic;
data_o : out std_logic_vector(FLOW_SIZE-1 downto 0);
fv_o : out std_logic;
dv_o : out std_logic;
flow_full_o : out std_logic
);
end com_to_flow;
architecture rtl of com_to_flow is
---------------------------------------------------------
-- COMPONENT DECLARATION
---------------------------------------------------------
component com_flow_fifo_rx
generic (
FIFO_DEPTH : POSITIVE := 1024;
FLOW_ID : INTEGER := 1;
IN_SIZE : POSITIVE;
OUT_SIZE : POSITIVE
);
port (
clk_proc : in std_logic;
clk_hal : in std_logic;
rst_n : in std_logic;
data_wr_i : in std_logic;
data_i : in std_logic_vector(IN_SIZE-1 downto 0);
rdreq_i : in std_logic;
pktend_i : in std_logic;
enable_i : in std_logic;
data_o : out std_logic_vector(OUT_SIZE-1 downto 0);
flow_rdy_o : out std_logic;
f_empty_o : out std_logic;
fifos_f_o : out std_logic;
flag_o : out std_logic_vector(7 downto 0)
);
end component;
component read_flow_nbits is
generic (
FLAGS_CODES : my_array_t := InitFlagCodes;
DATA_SZ : INTEGER;
IN_SIZE : POSITIVE;
OUT_SIZE : POSITIVE
);
port (
clk : in std_logic;
rst_n : in std_logic;
data_i : in std_logic_vector(IN_SIZE-1 downto 0);
flow_rdy_i : in std_logic;
f_empty_i : in std_logic;
enable_i : in std_logic;
flag_i : in std_logic_vector(OUT_SIZE-1 downto 0);
read_data_o : out std_logic;
data_o : out std_logic_vector(DATA_SZ-1 downto 0);
fv_o : out std_logic;
dv_o : out std_logic
);
end component;
---------------------------------------------------------
-- SIGNALS FOR INTERCONNECT
---------------------------------------------------------
signal flow_rdy_s : std_logic := '0';
signal read_data_s : std_logic := '0';
signal empty_s : std_logic := '0';
signal data_o_s : std_logic_vector(DATA_HAL_SIZE-1 downto 0) := (others=>'0');
signal fifo_rx_end_s : std_logic := '0';
signal flag_s : std_logic_vector(7 downto 0) := (others=>'0');
begin
-- port map
ComFlowFifoRx_inst : component com_flow_fifo_rx
generic map (
FIFO_DEPTH => FIFO_DEPTH,
FLOW_ID => FLOW_ID,
IN_SIZE => DATA_HAL_SIZE,
OUT_SIZE => DATA_HAL_SIZE
)
port map (
clk_proc => clk_proc,
clk_hal => clk_hal,
rst_n => rst_n,
data_wr_i => data_wr_i,
data_i => data_i,
rdreq_i => read_data_s,
pktend_i => pktend_i,
enable_i => enable_i,
data_o => data_o_s,
flow_rdy_o => flow_rdy_s,
flag_o => flag_s,
f_empty_o => empty_s,
fifos_f_o => flow_full_o
);
RD_process : component read_flow_nbits
generic map (
FLAGS_CODES => FLAGS_CODES,
DATA_SZ => FLOW_SIZE,
IN_SIZE => DATA_HAL_SIZE,
OUT_SIZE => FLOW_SIZE
)
port map (
clk => clk_proc,
rst_n => rst_n,
data_i => data_o_s,
flow_rdy_i => flow_rdy_s,
f_empty_i => empty_s,
enable_i => enable_i,
flag_i => flag_s,
read_data_o => read_data_s,
data_o => data_o,
fv_o => fv_o,
dv_o => dv_o
);
end rtl;
| gpl-3.0 | cbb356755083a92131a0edb55e4db0f1 | 0.421235 | 3.608088 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/altera/memory/src/dpRamOpenmac-rtl-a.vhd | 3 | 4,025 | --! @file dpRam-bhv-a.vhd
--
--! @brief Dual Port Ram for openMAC Register Transfer Level Architecture
--
--! @details This is the DPRAM intended for synthesis on Altera platforms only.
--! It is specific for the openMAC descriptor DPRAM which require
--! simultaneous write/read from the same address.
--!
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
-- Architecture : rtl
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2015
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use altera_mf library
library altera_mf;
use altera_mf.altera_mf_components.all;
architecture rtl of dpRamOpenmac is
begin
altsyncram_component : altsyncram
generic map (
operation_mode => "BIDIR_DUAL_PORT",
intended_device_family => "Cyclone IV",
init_file => gInitFile,
numwords_a => gNumberOfWords,
numwords_b => gNumberOfWords,
widthad_a => logDualis(gNumberOfWords),
widthad_b => logDualis(gNumberOfWords),
width_a => gWordWidth,
width_b => gWordWidth,
width_byteena_a => gWordWidth/8,
width_byteena_b => gWordWidth/8,
read_during_write_mode_mixed_ports => "OLD_DATA"
)
port map (
clock0 => iClk_A,
clocken0 => iEnable_A,
wren_a => iWriteEnable_A,
address_a => iAddress_A,
byteena_a => iByteenable_A,
data_a => iWritedata_A,
q_a => oReaddata_A,
clock1 => iClk_B,
clocken1 => iEnable_B,
wren_b => iWriteEnable_B,
address_b => iAddress_B,
byteena_b => iByteenable_B,
data_b => iWritedata_B,
q_b => oReaddata_B
);
end architecture rtl;
| gpl-2.0 | 03bb4ab5fb960ae7c1d7e106284fd12c | 0.557516 | 4.896594 | false | false | false | false |
hoglet67/ElectronFpga | src/xilinx/DCM/pll2.vhd | 1 | 3,231 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity pll2 is
port
(-- Clock in ports
CLKIN_IN : in std_logic;
-- Clock out ports
CLK0_OUT : out std_logic;
CLK1_OUT : out std_logic;
CLK2_OUT : out std_logic;
CLK3_OUT : out std_logic
);
end pll2;
architecture xilinx of pll2 is
signal GND_BIT : std_logic;
signal CLKFBOUT : std_logic;
signal CLKFB : std_logic;
signal CLKFBIN : std_logic;
signal CLKIN : std_logic;
signal CLK0 : std_logic;
signal CLK0_BUF : std_logic;
signal CLK1 : std_logic;
signal CLK1_BUF : std_logic;
signal CLK2 : std_logic;
signal CLK2_BUF : std_logic;
signal CLK3 : std_logic;
signal CLK3_BUF : std_logic;
begin
GND_BIT <= '0';
-- Clock feedback output buffer
CLKFB_BUFG_INST : BUFG
port map (I => CLKFBOUT, O => CLKFB);
-- Clock feedback io2 buffer
CLKFB_BUFIO2FB_INST : BUFIO2FB
port map (I => CLKFB, O => CLKFBIN);
-- CLK0 output buffer
CLK0_BUFG_INST : BUFG
port map (I => CLK0, O => CLK0_BUF);
CLK0_OUT <= CLK0_BUF;
-- CLK1 output buffer
CLK1_BUFG_INST : BUFG
port map (I => CLK1, O => CLK1_BUF);
CLK1_OUT <= CLK1_BUF;
-- CLK2 output buffer
CLK2_BUFG_INST : BUFG
port map (I => CLK2, O => CLK2_BUF);
CLK2_OUT <= CLK2_BUF;
-- CLK3 output buffer
CLK3_BUFG_INST : BUFG
port map (I => CLK3, O => CLK3_BUF);
CLK3_OUT <= CLK3_BUF;
INST_PLL : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS", -- not sure this is correct
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 15, -- 32 x 15 = 480MHz
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 30, -- 480 / 30 = 16MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 20, -- 480 / 20 = 24 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 15, -- 480 / 15 = 32 MHz
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DIVIDE => 12, -- 480 / 12 = 40 MHZ
CLKOUT3_PHASE => 0.000,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map (
-- Input clock control
CLKIN => CLKIN_IN,
CLKFBIN => CLKFBIN,
-- Output clocks
CLKFBOUT => CLKFBOUT,
CLKOUT0 => CLK0,
CLKOUT1 => CLK1,
CLKOUT2 => CLK2,
CLKOUT3 => CLK3,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => GND_BIT
);
end xilinx;
| gpl-3.0 | 0754c76d3944d0648645aa6ebe8b33d1 | 0.487775 | 3.630337 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_onchip_memory2_0.vhd | 1 | 5,849 | --Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.all;
entity tracking_camera_system_onchip_memory2_0 is
generic (
INIT_FILE : STRING := "../tracking_camera_system_onchip_memory2_0.hex"
);
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal chipselect : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal clken : IN STD_LOGIC;
signal reset : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity tracking_camera_system_onchip_memory2_0;
architecture europa of tracking_camera_system_onchip_memory2_0 is
--synthesis translate_off
component altsyncram is
GENERIC (
byte_size : NATURAL;
init_file : STRING;
lpm_type : STRING;
maximum_depth : NATURAL;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_reg_a : STRING;
ram_block_type : STRING;
read_during_write_mode_mixed_ports : STRING;
width_a : NATURAL;
width_byteena_a : NATURAL;
widthad_a : NATURAL
);
PORT (
signal q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal wren_a : IN STD_LOGIC;
signal byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal clock0 : IN STD_LOGIC;
signal address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal clocken0 : IN STD_LOGIC;
signal data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component altsyncram;
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- component altsyncram is
--GENERIC (
-- byte_size : NATURAL;
-- init_file : STRING;
-- lpm_type : STRING;
-- maximum_depth : NATURAL;
-- numwords_a : NATURAL;
-- operation_mode : STRING;
-- outdata_reg_a : STRING;
-- ram_block_type : STRING;
-- read_during_write_mode_mixed_ports : STRING;
-- width_a : NATURAL;
-- width_byteena_a : NATURAL;
-- widthad_a : NATURAL
-- );
-- PORT (
-- signal q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
-- signal wren_a : IN STD_LOGIC;
-- signal byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
-- signal clock0 : IN STD_LOGIC;
-- signal address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- signal clocken0 : IN STD_LOGIC;
-- signal data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
-- );
-- end component altsyncram;
--synthesis read_comments_as_HDL off
signal internal_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal wren : STD_LOGIC;
begin
wren <= chipselect AND write;
--s1, which is an e_avalon_slave
--s2, which is an e_avalon_slave
--vhdl renameroo for output signals
readdata <= internal_readdata;
--synthesis translate_off
the_altsyncram : altsyncram
generic map(
byte_size => 8,
init_file => INIT_FILE,
lpm_type => "altsyncram",
maximum_depth => 4096,
numwords_a => 4096,
operation_mode => "SINGLE_PORT",
outdata_reg_a => "UNREGISTERED",
ram_block_type => "AUTO",
read_during_write_mode_mixed_ports => "DONT_CARE",
width_a => 32,
width_byteena_a => 4,
widthad_a => 12
)
port map(
address_a => address,
byteena_a => byteenable,
clock0 => clk,
clocken0 => clken,
data_a => writedata,
q_a => internal_readdata,
wren_a => wren
);
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- the_altsyncram : altsyncram
-- generic map(
-- byte_size => 8,
-- init_file => "tracking_camera_system_onchip_memory2_0.hex",
-- lpm_type => "altsyncram",
-- maximum_depth => 4096,
-- numwords_a => 4096,
-- operation_mode => "SINGLE_PORT",
-- outdata_reg_a => "UNREGISTERED",
-- ram_block_type => "AUTO",
-- read_during_write_mode_mixed_ports => "DONT_CARE",
-- width_a => 32,
-- width_byteena_a => 4,
-- widthad_a => 12
-- )
-- port map(
-- address_a => address,
-- byteena_a => byteenable,
-- clock0 => clk,
-- clocken0 => clken,
-- data_a => writedata,
-- q_a => internal_readdata,
-- wren_a => wren
-- );
--
--synthesis read_comments_as_HDL off
end europa;
| gpl-2.0 | fc04b5cacf0ddf7da69d81c64ea12f05 | 0.586083 | 3.907148 | false | false | false | false |
emusan/wifidar_fpga | src/wifidar_fpga.vhdl | 1 | 6,930 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity wifidar_fpga is
generic(
num_samples: integer range 0 to 20000 := 395;
sample_length_bits: integer range 0 to 32 := 14
);
port(
-- rot_a: in std_logic;
-- rot_b: in std_logic;
-- button_in: in std_logic_vector(3 downto 0);
switches: in std_logic_vector(3 downto 0);
change_amp: in std_logic;
SPI_SS_B: out std_logic;
AMP_CS: out std_logic;
AD_CONV: out std_logic;
SF_CE0: out std_logic;
FPGA_INIT_B: out std_logic;
AMP_SHDN: out std_logic;
SPI_MOSI: out std_logic;
SPI_MISO: in std_logic;
SPI_SCK: out std_logic;
-- DAC_SCK: out std_logic;
-- DAC_CS: out std_logic;
-- DAC_MOSI: out std_logic;
-- current_mode_out: out std_logic_vector(1 downto 0);
initial_sample: in std_logic;
uart_tx: out std_logic;
debug: out std_logic;
debug2: out std_logic;
rst: in std_logic;
clk: in std_logic
);
end wifidar_fpga;
architecture structural of wifidar_fpga is
component uart
generic(
clk_freq: integer := 50000000;
baud_rate: integer := 38400
);
port(
uart_tx: out std_logic;
data_in: in std_logic_vector(7 downto 0);
ready: out std_logic;
send_data: in std_logic;
rst: in std_logic;
clk: in std_logic
);
end component;
component sample_buffer
generic(
num_samples: integer range 0 to 20000 := 20;
sample_length_bits: integer range 0 to 32 := 14
);
port(
sample_in: in std_logic_vector(sample_length_bits - 1 downto 0);
sample_out: out std_logic_vector(sample_length_bits - 1 downto 0);
sample_in_ready: in std_logic;
initial_sample: in std_logic;
sample_out_index: in std_logic_vector(integer(ceil(log(real(num_samples))/log(real(2)))) downto 0);
buffer_full: out std_logic;
rst: in std_logic;
clk: in std_logic
);
end component;
component adc_controller
generic(
sample_div: integer := 2500
);
port(
spi_to_amp: out std_logic_vector(3 downto 0);
req_adc: out std_logic;
req_amp: out std_logic;
rst: in std_logic;
clk: in std_logic
);
end component;
component uart_minibuf
generic(
num_samples: integer range 0 to 20000 := 20;
sample_length_bits: integer range 0 to 32 := 14
);
port(
data_in: in std_logic_vector (sample_length_bits -1 downto 0);
data_out: out std_logic_vector(7 downto 0);
index_data_in: out std_logic_vector(integer(ceil(log(real(num_samples))/log(real(2)))) downto 0);
sample_buffer_full: in std_logic;
uart_send_data: out std_logic;
uart_ready: in std_logic;
rst: in std_logic;
clk: in std_logic
);
end component;
component spi_arbitrator
port(
----- other devices on SPI BUS ---
SPI_SS_B: out std_logic; -- set to 1
SF_CE0: out std_logic; -- set to 1
FPGA_INIT_B: out std_logic; -- set to 1
----- chip selects ---
AMP_CS: out std_logic; -- active low pre-amp chip select
--AD_CONV: out std_logic; -- active high ADC chip select
--DAC_CS: out std_logic; -- active low DAC chip select
----- resets ---
AMP_SHDN: out std_logic; -- ADC pre-amp shutdown signal (active high)
-- control signals
spi_controller_busy: in std_logic;
dac_ready: in std_logic;
adc_send_data: out std_logic;
amp_send_data: out std_logic;
dac_send_data: out std_logic;
req_adc: in std_logic;
req_amp: in std_logic;
rst: in std_logic;
clk: in std_logic
);
end component;
component adc_receiver
port(
send_data: in std_logic;
busy: out std_logic;
spi_sck: out std_logic;
spi_miso: in std_logic;
ad_conv: out std_logic;
outputA: out std_logic_vector (13 downto 0);
outputB: out std_logic_vector (13 downto 0);
new_reading: out std_logic;
clk: in std_logic
);
end component;
component preamp_config
port(
preamp_done: out std_logic;
send_data: in std_logic;
busy: out std_logic;
gain_in: in std_logic_vector(3 downto 0);
spi_mosi: out std_logic;
spi_sck: out std_logic;
clk: in std_logic
);
end component;
component dac_serial
port(
SPI_SCK: out std_logic; -- spi clock
DAC_CS: out std_logic; -- chip select
SPI_MOSI_1: out std_logic; -- Master output, slave (DAC) input
--SPI_MISO: in std_logic; -- Master input, slave (DAC) output
--- control ---
data_in_1: in std_logic_vector(11 downto 0);
ready_flag: out std_logic; -- sending data flag
send_data: in std_logic; -- send sine data over SPI
clk: in std_logic -- master clock
);
end component;
signal uart_data: std_logic_vector(7 downto 0);
signal uart_send_data: std_logic;
signal uart_ready: std_logic;
signal adc_sample_data: std_logic_vector(13 downto 0);
signal sample_buffer_out: std_logic_vector(13 downto 0);
signal load_adc: std_logic;
signal sample_out_index: std_logic_vector(integer(ceil(log(real(num_samples))/log(real(2)))) downto 0);
signal sample_buffer_full: std_logic;
--signal spi_to_amp: std_logic_vector(3 downto 0);
signal req_adc: std_logic;
signal req_amp: std_logic;
signal spi_controller_busy: std_logic;
signal spi_mosi_sig2: std_logic;
signal spi_sck_sig2: std_logic;
signal spi_sck_sig3: std_logic;
signal adc_busy: std_logic;
signal adc_send: std_logic;
signal amp_send: std_logic;
signal amp_busy: std_logic;
signal req_amp_controller: std_logic;
begin
uarter: uart port map (uart_tx,uart_data,uart_ready,uart_send_data,rst,clk);
sample_buefferer: sample_buffer generic map (num_samples,sample_length_bits) port map (adc_sample_data,sample_buffer_out,load_adc,initial_sample,sample_out_index,sample_buffer_full,rst,clk);
adc_controllerer: adc_controller port map (open,req_adc,req_amp_controller,rst,clk);
uart_minibuffer: uart_minibuf generic map (num_samples,sample_length_bits) port map (sample_buffer_out,uart_data,sample_out_index,sample_buffer_full,uart_send_data,uart_ready,rst,clk);
spi_arbitratorer: spi_arbitrator port map (SPI_SS_B,SF_CE0,FPGA_INIT_B,AMP_CS,AMP_SHDN,
spi_controller_busy,'0',adc_send,amp_send,open,
req_adc,req_amp,rst,clk);
--dac_controller: dac_serial port map (DAC_SCK,DAC_CS,DAC_MOSI,ramp_data_sig,dac_ready,dac_send,clk);
adc_spi_control: adc_receiver port map (adc_send,adc_busy,spi_sck_sig2,SPI_MISO,AD_CONV,adc_sample_data,open,load_adc,clk);
amp_controller: preamp_config port map (open,amp_send,amp_busy,switches,spi_mosi_sig2,spi_sck_sig3,clk);
SPI_MOSI <= spi_mosi_sig2;
SPI_SCK <= spi_sck_sig2 or spi_sck_sig3;
req_amp <= req_amp_controller or change_amp;
spi_controller_busy <= adc_busy or amp_busy;
debug <= sample_buffer_full;
debug2 <= initial_sample;
end structural;
| mit | 1c97c10e608653194e3169dbc8b699e5 | 0.650072 | 2.863636 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_switch.vhd | 1 | 2,456 | --Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tracking_camera_system_switch is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal in_port : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity tracking_camera_system_switch;
architecture europa of tracking_camera_system_switch is
signal clk_en : STD_LOGIC;
signal data_in : STD_LOGIC;
signal read_mux_out : STD_LOGIC;
begin
clk_en <= std_logic'('1');
--s1, which is an e_avalon_slave
read_mux_out <= to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000")))) AND data_in;
process (clk, reset_n)
begin
if reset_n = '0' then
readdata <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
readdata <= std_logic_vector'("00000000000000000000000000000000") OR (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(read_mux_out)));
end if;
end if;
end process;
data_in <= in_port;
end europa;
| gpl-2.0 | 279d285e99b7ccd3cf3949ca4dc30280 | 0.687296 | 4.198291 | false | false | false | false |
DreamIP/GPStudio | support/process/dynroi/hdl/dynroi.vhd | 1 | 7,305 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity dynroi is
generic (
CLK_PROC_FREQ : integer;
BINIMG_SIZE : integer;
IMG_SIZE : integer;
ROI_SIZE : integer;
COORD_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
----------------------- BinImg flow ---------------------
BinImg_data : in std_logic_vector(BINIMG_SIZE-1 downto 0);
BinImg_fv : in std_logic;
BinImg_dv : in std_logic;
------------------------ Img flow -----------------------
Img_data : in std_logic_vector(IMG_SIZE-1 downto 0);
Img_fv : in std_logic;
Img_dv : in std_logic;
------------------------ roi flow -----------------------
roi_data : out std_logic_vector(ROI_SIZE-1 downto 0);
roi_fv : out std_logic;
roi_dv : out std_logic;
----------------------- coord flow ----------------------
coord_data : out std_logic_vector(COORD_SIZE-1 downto 0);
coord_fv : out std_logic;
coord_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end dynroi;
architecture rtl of dynroi is
component dynroi_process
generic (
CLK_PROC_FREQ : integer;
BINIMG_SIZE : integer;
IMG_SIZE : integer;
ROI_SIZE : integer;
COORD_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
status_reg_bypass_bit : in std_logic;
status_reg_static_res_bit : in std_logic;
inImg_size_reg_in_w_reg : in std_logic_vector(11 downto 0);
inImg_size_reg_in_h_reg : in std_logic_vector(11 downto 0);
BinImg_size_reg_in_w_reg : in std_logic_vector(11 downto 0);
BinImg_size_reg_in_h_reg : in std_logic_vector(11 downto 0);
out_size_reg_out_w_reg : in std_logic_vector(11 downto 0);
out_size_reg_out_h_reg : in std_logic_vector(11 downto 0);
----------------------- BinImg flow ---------------------
BinImg_data : in std_logic_vector(BINIMG_SIZE-1 downto 0);
BinImg_fv : in std_logic;
BinImg_dv : in std_logic;
------------------------ Img flow -----------------------
Img_data : in std_logic_vector(IMG_SIZE-1 downto 0);
Img_fv : in std_logic;
Img_dv : in std_logic;
------------------------ roi flow -----------------------
roi_data : out std_logic_vector(ROI_SIZE-1 downto 0);
roi_fv : out std_logic;
roi_dv : out std_logic;
----------------------- coord flow ----------------------
coord_data : out std_logic_vector(COORD_SIZE-1 downto 0);
coord_fv : out std_logic;
coord_dv : out std_logic
);
end component;
component dynroi_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
status_reg_bypass_bit : out std_logic;
status_reg_static_res_bit : out std_logic;
inImg_size_reg_in_w_reg : out std_logic_vector(11 downto 0);
inImg_size_reg_in_h_reg : out std_logic_vector(11 downto 0);
BinImg_size_reg_in_w_reg : out std_logic_vector(11 downto 0);
BinImg_size_reg_in_h_reg : out std_logic_vector(11 downto 0);
out_size_reg_out_w_reg : out std_logic_vector(11 downto 0);
out_size_reg_out_h_reg : out std_logic_vector(11 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal status_reg_bypass_bit : std_logic;
signal status_reg_static_res_bit : std_logic;
signal inImg_size_reg_in_w_reg : std_logic_vector (11 downto 0);
signal inImg_size_reg_in_h_reg : std_logic_vector (11 downto 0);
signal BinImg_size_reg_in_w_reg : std_logic_vector (11 downto 0);
signal BinImg_size_reg_in_h_reg : std_logic_vector (11 downto 0);
signal out_size_reg_out_w_reg : std_logic_vector (11 downto 0);
signal out_size_reg_out_h_reg : std_logic_vector (11 downto 0);
begin
dynroi_process_inst : dynroi_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
BINIMG_SIZE => BINIMG_SIZE,
IMG_SIZE => IMG_SIZE,
ROI_SIZE => ROI_SIZE,
COORD_SIZE => COORD_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
status_reg_bypass_bit => status_reg_bypass_bit,
status_reg_static_res_bit => status_reg_static_res_bit,
inImg_size_reg_in_w_reg => inImg_size_reg_in_w_reg,
inImg_size_reg_in_h_reg => inImg_size_reg_in_h_reg,
BinImg_size_reg_in_w_reg => BinImg_size_reg_in_w_reg,
BinImg_size_reg_in_h_reg => BinImg_size_reg_in_h_reg,
out_size_reg_out_w_reg => out_size_reg_out_w_reg,
out_size_reg_out_h_reg => out_size_reg_out_h_reg,
BinImg_data => BinImg_data,
BinImg_fv => BinImg_fv,
BinImg_dv => BinImg_dv,
Img_data => Img_data,
Img_fv => Img_fv,
Img_dv => Img_dv,
roi_data => roi_data,
roi_fv => roi_fv,
roi_dv => roi_dv,
coord_data => coord_data,
coord_fv => coord_fv,
coord_dv => coord_dv
);
dynroi_slave_inst : dynroi_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
status_reg_bypass_bit => status_reg_bypass_bit,
status_reg_static_res_bit => status_reg_static_res_bit,
inImg_size_reg_in_w_reg => inImg_size_reg_in_w_reg,
inImg_size_reg_in_h_reg => inImg_size_reg_in_h_reg,
BinImg_size_reg_in_w_reg => BinImg_size_reg_in_w_reg,
BinImg_size_reg_in_h_reg => BinImg_size_reg_in_h_reg,
out_size_reg_out_w_reg => out_size_reg_out_w_reg,
out_size_reg_out_h_reg => out_size_reg_out_h_reg,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
| gpl-3.0 | 6b667e108fb88e75511fb6902636ead0 | 0.504312 | 3.069328 | false | false | false | false |
DreamIP/GPStudio | support/component/gp_com/flow_to_com/fv_signal_synchroniser.vhd | 1 | 1,771 | -- **************************************************************************
-- SYNCHRO enable avec fin de ligne
-- **************************************************************************
--
-- 16/10/2014 - creation
--------------------------------------------------------------------
-- TODO: Supprmier machine d'états => possibilité de mettre à jour le reg seulement sur le front descendant de fv
-- : A verifier !
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fv_signal_synchroniser is
port (
clk : in std_logic;
rst_n : in std_logic;
fv_i : in std_logic;
signal_i : in std_logic;
signal_o : out std_logic
);
end fv_signal_synchroniser;
architecture rtl of fv_signal_synchroniser is
type en_state_t is (WaitforSignal, WaitNextFrame, Run, WaitForEndFrame);
signal en_state : en_state_t := WaitforSignal;
signal enable_s : std_logic :='0';
signal fv_r : std_logic := '0';
begin
-- This process synchronize signal with flow valid
ENABLE_inst: process (clk, rst_n)
begin
if (rst_n = '0') then
en_state <= WaitforSignal;
signal_o <='0';
elsif rising_edge(clk) then
fv_r <= fv_i;
case en_state is
when WaitforSignal =>
if (signal_i = '1') then
-- wait for the next frame
en_state <= WaitNextFrame;
end if;
when WaitNextFrame =>
if (fv_i='0') then
signal_o <= '1';
en_state <= Run;
end if;
when Run =>
if (signal_i ='0') then
en_state <= WaitForEndFrame;
end if;
when WaitForEndFrame =>
if (fv_r ='1' and fv_i='0') then
signal_o <= '0';
en_state <= WaitforSignal;
end if;
end case;
end if;
end process;
end architecture;
| gpl-3.0 | ef217c3da894009c360f8ef0796a817d | 0.524887 | 3.310861 | false | false | false | false |
DreamIP/GPStudio | support/process/maxPool/hdl/poolH.vhd | 1 | 8,474 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity poolH is
generic(
PIXEL_SIZE : integer;
IMAGE_WIDTH : integer;
KERNEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE - 1 downto 0);
in_dv : in std_logic;
in_fv : in std_logic;
out_data : out std_logic_vector (PIXEL_SIZE - 1 downto 0);
out_dv : out std_logic;
out_fv : out std_logic
);
end entity;
architecture rtl of poolH is
--------------------------------------------------------------------------
-- Signals
--------------------------------------------------------------------------
type buffer_data_type is array ( integer range <> ) of signed (PIXEL_SIZE-1 downto 0);
signal max_value_signal : signed(PIXEL_SIZE-1 downto 0);
signal buffer_data : buffer_data_type (KERNEL_SIZE - 1 downto 0);
signal buff : signed(PIXEL_SIZE-1 downto 0);
signal buffer_fv : std_logic_vector(KERNEL_SIZE downto 0);
signal delay_fv : std_logic := '0';
signal tmp_dv : std_logic := '0';
begin
even_frame : if (IMAGE_WIDTH mod 2=0) generate
process (clk)
variable x_cmp : unsigned (15 downto 0) := (others=>'0');
begin
if (reset_n = '0') then
tmp_dv <='0';
buffer_data <= (others=>(others=>'0'));
max_value_signal <= (others=>'0');
x_cmp := (others=>'0');
elsif (rising_edge(clk)) then
if (enable = '1') then
if (in_fv = '1') then
if (in_dv = '1') then
-- Bufferize data --------------------------------------------------------
buffer_data(KERNEL_SIZE - 1) <= signed(in_data);
BUFFER_LOOP : for i in (KERNEL_SIZE - 1) downto 1 loop
buffer_data(i-1) <= buffer_data(i);
end loop;
-- Compute max -----------------------------------------------------------
if (buffer_data(0) > buffer_data(1)) then
max_value_signal <= buffer_data(0);
else
max_value_signal <= buffer_data(1);
end if;
-- H Subsample -------------------------------------------------------------
if (x_cmp = to_unsigned(KERNEL_SIZE, 16)) then
tmp_dv <= '1';
x_cmp := to_unsigned(1, 16);
else
tmp_dv <= '0';
x_cmp := x_cmp + to_unsigned(1, 16);
end if;
--------------------------------------------------------------------------
else
-- Data is not valid
tmp_dv <= '0';
end if;
else
-- Frame is not valid
tmp_dv <= '0';
buffer_data <= (others=>(others=>'0'));
max_value_signal <= (others=>'0');
x_cmp := (others=>'0');
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------
delay : process(clk)
begin
if (reset_n = '0') then
delay_fv <= '0';
buffer_fv <= (others=>'0');
elsif (rising_edge(clk)) then
if (enable = '1') then
buffer_fv <= buffer_fv(buffer_fv'HIGH -1 downto 0) & in_fv;
delay_fv <= buffer_fv(buffer_fv'HIGH);
end if;
end if;
end process;
out_data <= std_logic_vector(max_value_signal);
out_fv <= delay_fv;
out_dv <= tmp_dv;
end generate;
----------------------------------------------------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------------------------------------------
odd_frame : if (IMAGE_WIDTH mod 2 = 1) generate
begin
process (clk)
variable x_cmp : unsigned (15 downto 0) := (others=>'0');
variable line_cmp : unsigned (15 downto 0) := (others=>'0');
begin
if (reset_n = '0') then
tmp_dv <='0';
buffer_data <= (others=>(others=>'0'));
max_value_signal <= (others=>'0');
x_cmp := (others=>'0');
elsif (rising_edge(clk)) then
if (enable = '1') then
if (in_fv = '1') then
if (in_dv = '1') then
if (line_cmp = to_unsigned((IMAGE_WIDTH)/2 - 1, 16)) then
x_cmp := to_unsigned(KERNEL_SIZE-1, 16);
line_cmp := to_unsigned(0, 16);
max_value_signal <= signed(in_data);
buff <= (others=>'0');
tmp_dv <= '1';
else
-- Bufferize data --------------------------------------------------------
-- buffer_data(KERNEL_SIZE - 1) <= signed(in_data);
buff <= signed(in_data);
-- BUFFER_LOOP : for i in (KERNEL_SIZE - 1) downto 1 loop
-- end loop;
-- Compute max -----------------------------------------------------------
-- if (buffer_data(0) > buffer_data(1)) then
if (buff >signed(in_data)) then
max_value_signal <= buff;
else
max_value_signal <= signed(in_data);
end if;
-- H Subsample -------------------------------------------------------------
if (x_cmp = to_unsigned(KERNEL_SIZE-1, 16)) then
tmp_dv <= '1';
x_cmp := to_unsigned(0, 16);
else
line_cmp := line_cmp + to_unsigned(1, 16);
tmp_dv <= '0';
x_cmp := x_cmp + to_unsigned(1, 16);
end if;
end if;
--------------------------------------------------------------------------
else
-- Data is not valid
tmp_dv <= '0';
end if;
else
-- Frame is not valid
tmp_dv <= '0';
buffer_data <= (others=>(others=>'0'));
max_value_signal <= (others=>'0');
x_cmp := (others=>'0');
buff <= (others=>'0');
end if;
end if;
end if;
out_fv <= in_fv;
out_dv <= tmp_dv;
end process;
--------------------------------------------------------------------------
out_data <= std_logic_vector(max_value_signal);
end generate;
end architecture;
| gpl-3.0 | d18c75158844d9bb75056ae9d7e5db71 | 0.29797 | 5.446015 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/verif/testbench/transloop_tb.vhdl | 1 | 1,810 | --
-- Transceiver Loop Testbench
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016-2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.Verif.all;
use FPGALIB.Simul.all;
entity TransLoop_Tb is
end entity TransLoop_Tb;
architecture Test of TransLoop_Tb is
constant FREQUENCY : positive:=150e6;
signal clk, rst : std_logic;
signal stop : boolean;
-- dut
signal ready : std_logic;
signal data : std_logic_vector(31 downto 0);
signal isk : std_logic_vector(3 downto 0);
signal errors : std_logic_vector(4 downto 0);
signal finish : std_logic;
begin
do_clk: Clock
generic map(FREQUENCY => FREQUENCY)
port map(clk_o => clk, rst_o => rst, stop_i => stop);
dut: TransLoop
port map(
-- TX side
tx_clk_i => clk,
tx_rst_i => rst,
tx_data_i => (others => '0'),
tx_data_o => data,
tx_isk_o => isk,
tx_ready_i => ready,
-- RX side
rx_clk_i => clk,
rx_rst_i => rst,
rx_data_i => data,
rx_isk_i => isk,
rx_errors_o => errors,
rx_finish_o => finish,
rx_cycles_o => open
);
do_run: process
begin
ready <= '0';
wait until rising_edge(clk) and rst='0';
ready <= '1';
wait until rising_edge(clk);
ready <= '0';
wait until rising_edge(clk) and finish='1';
assert errors="00000"
report "ERROR: there were errors ("&to_str(errors)&")." severity failure;
stop <= TRUE;
wait;
end process do_run;
end architecture Test;
| bsd-3-clause | 5582f4f77db521b00ed61ac607c46090 | 0.527072 | 3.577075 | false | false | false | false |
DreamIP/GPStudio | support/io/com/hdl/hal/eth_marvell_88e1111/hdl/encapsulation/eth_tx_header.vhd | 1 | 6,703 | -- This entity add the Ethernet/IP/UDP header for each packet depending on the values set in eth_slave.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_unsigned.ALL;
use work.ethernet_package.all;
entity eth_tx_header is
Port(
CLK125 : in STD_LOGIC;
reset_n : in STD_LOGIC;
data_i : in std_logic_vector(7 downto 0);
data_size_i : in std_logic_vector(15 downto 0);
TX_i : in gmii_t;
TX_o : out gmii_t;
--- parameters from slave
mac_addr_hal_msb : in std_logic_vector(23 downto 0);
mac_addr_hal_lsb : in std_logic_vector(23 downto 0);
mac_addr_dest_msb : in std_logic_vector(23 downto 0);
mac_addr_dest_lsb : in std_logic_vector(23 downto 0);
ip_hal : in std_logic_vector(31 downto 0);
ip_dest : in std_logic_vector(31 downto 0);
port_dest : in std_logic_vector(15 downto 0)
);
end eth_tx_header;
architecture RTL of eth_tx_header is
signal fifo_udp_out : std_logic_vector(7 downto 0);
signal empty_fifo_udp : std_logic;
signal CS_sum : std_logic_vector(31 downto 0);
signal rd_fifo_udp : std_logic;
type encapsulation_fsm is (ethernet,ip,udp,data,idle);
signal state_encap : encapsulation_fsm;
signal eth_hdr : std_logic_vector(111 downto 0);
signal ip_hdr : std_logic_vector(159 downto 0);
signal udp_hdr : std_logic_vector(63 downto 0);
signal mac_addr_hal : std_logic_vector(47 downto 0);
signal mac_addr_dest : std_logic_vector(47 downto 0);
signal len_udp,len_ip : std_logic_vector(15 downto 0);
signal port_src : std_logic_vector(15 downto 0);
signal CS_udp,CS_ip : std_logic_vector(15 downto 0);
signal count_udp : std_logic_vector(7 downto 0);
signal id : std_logic_vector(5 downto 0);
signal start_encap : std_logic;
signal dv_uncap_dl : std_logic;
signal dv_uncap_dl2 : std_logic;
signal queue_dv_dl : std_logic;
signal set_length : std_logic;
signal start_encap_dl : std_logic;
signal TX : gmii_t;
signal reset : std_logic;
begin
reset <= not reset_n;
fifo_udp_inst : entity work.gp_fifo
generic map(
DATA_WIDTH => 8,
FIFO_DEPTH => 64
)
port map(
clk => CLK125,
reset_n => reset,
data_in => TX_i.data,
data_rd => rd_fifo_udp,
data_wr => TX_i.dv,
empty => empty_fifo_udp,
data_out => fifo_udp_out
);
-- Not tested
checksum_udp : process(clk125,reset_n)
begin
if reset_n ='0' then
dv_uncap_dl <= '0';
start_encap <= '0';
queue_dv_dl <= '0';
elsif CLK125'event and CLK125='1' then
dv_uncap_dl <= TX_i.dv;
dv_uncap_dl2 <= dv_uncap_dl;
queue_dv_dl <= TX.dv;
start_encap_dl <= start_encap;
--start the encapsulation when a flow is received
if TX_i.dv='1' and dv_uncap_dl='0' then
start_encap <= '1';
elsif start_encap='0' and start_encap_dl='1' then
len_udp <= data_size_i + x"8"; -- Data + udp header
len_ip <= data_size_i + x"1C";-- Data + udp header + ip header
id <= fifo_udp_out(5 downto 0);
else
start_encap <= '0';
end if;
if TX_i.dv='1' then
CS_sum <= CS_sum + TX_i.data;
elsif dv_uncap_dl='1' and TX_i.dv='0' then
CS_sum <= CS_sum + port_dest + port_src + len_udp;
elsif dv_uncap_dl='0' and dv_uncap_dl2='1' then
CS_udp <= not (CS_sum(15 downto 0) + CS_sum(31 downto 16));
CS_ip <= x"AAAA";
elsif TX.dv='0' and queue_dv_dl='1' then
CS_sum <= x"00000000";
CS_ip <= x"0000";
end if;
end if;
end process;
encapsule_ip_udp : process(clk125,reset_n)
begin
if reset_n='0' then
state_encap <= idle;
TX.dv <= '0';
TX.data <= (others =>'0');
rd_fifo_udp <= '0';
count_udp <=x"00";
elsif CLK125'event and CLK125='1' then
case(state_encap) is
-- Prepare registers that contains every information about the header to add
when idle =>
if TX_i.dv='1' and dv_uncap_dl='0' then
rd_fifo_udp <= '1';
elsif start_encap='0' and start_encap_dl='1' then
set_length <= '1';
count_udp <=x"00";
elsif set_length='1' then
set_length <= '0';
state_encap <= ethernet;
eth_hdr <= mac_addr_dest & mac_addr_hal & x"0800";
ip_hdr <= x"4500" & len_ip & x"00004000" & x"8011" & CS_ip & ip_hal & ip_dest;
udp_hdr <= port_src & port_dest & len_udp & CS_udp;
else
TX.dv <= '0';
rd_fifo_udp <= '0';
end if;
-- Add Ethernet header
when ethernet =>
TX.dv <= '1';
eth_hdr <= eth_hdr(103 downto 0) & eth_hdr(111 downto 104);
TX.data <= eth_hdr(111 downto 104);
if count_udp=x"0D" then
state_encap <= ip;
count_udp <=x"00";
else
count_udp <= count_udp +1;
end if;
-- Add IP header
when ip =>
ip_hdr <= ip_hdr(151 downto 0) & ip_hdr(159 downto 152);
TX.data <= ip_hdr(159 downto 152);
if count_udp=x"13" then
state_encap <= udp;
count_udp <=x"00";
else
count_udp <= count_udp +1;
end if;
-- Add UDP header
when udp =>
udp_hdr <= udp_hdr(55 downto 0) & udp_hdr(63 downto 56);
TX.data <= udp_hdr(63 downto 56);
count_udp <= count_udp +1;
if count_udp=x"07" then
state_encap <= data;
count_udp <=x"00";
rd_fifo_udp <= '1';
end if;
-- Read data from fifo
when data =>
TX.data <= fifo_udp_out;
if empty_fifo_udp='1' and rd_fifo_udp='1' then
rd_fifo_udp <= '0';
elsif rd_fifo_udp = '0' then
TX.dv <= '0';
state_encap <= idle;
end if;
when others =>
state_encap <= idle;
end case;
end if;
end process;
TX_o <= TX;
port_src <= "00"& id & x"00";
mac_addr_hal <= mac_addr_hal_msb & mac_addr_hal_lsb;
mac_addr_dest <= mac_addr_dest_msb & mac_addr_dest_lsb;
end RTL;
| gpl-3.0 | c7c0059ae81c31266c1f82c3c5961921 | 0.509324 | 3.003136 | false | false | false | false |
DreamIP/GPStudio | support/component/gp_com/com_to_flow/read_flow_nbits.vhd | 1 | 3,662 |
-- **************************************************************************
-- READ FLOW
-- **************************************************************************
-- Ce composant est connecte a un com_flow_fifo en entree et a un processing (FV/LV/Data) en sortie
--
-- 16/10/2014 - creation
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ComFlow_pkg.all;
entity read_flow_nbits is
generic (
FLAGS_CODES : my_array_t := InitFlagCodes;
DATA_SZ : INTEGER;
IN_SIZE : POSITIVE;
OUT_SIZE : POSITIVE
);
port(
clk : in std_logic;
rst_n : in std_logic;
data_i : in std_logic_vector(IN_SIZE-1 downto 0);
flow_rdy_i : in std_logic;
f_empty_i : in std_logic;
enable_i : in std_logic;
flag_i : in std_logic_vector(OUT_SIZE-1 downto 0);
read_data_o : out std_logic;
data_o : out std_logic_vector(DATA_SZ-1 downto 0);
fv_o : out std_logic;
dv_o : out std_logic
);
end read_flow_nbits;
architecture rtl of read_flow_nbits is
---------------------------------------------------------
-- SIGNALS
---------------------------------------------------------
constant CPT_MAX : integer := 16/DATA_SZ;
-------------
-- FSM Signal
-------------
type fsm_state_t is (Idle, DecodeFlag, ReadFlow, StartRead,ClkCycle , EndFlow);
signal fsm_state : fsm_state_t := Idle;
signal f_empty_r : std_logic:='0';
signal flow_rdy_r : std_logic:='0';
signal tmp : unsigned(IN_SIZE-1 downto 0);
signal cpt_s : integer range 0 to CPT_MAX := 1;
begin
FSM : process (clk, rst_n)
variable last_packet: std_logic := '0';
--variable cpt : integer range 0 to CPT_MAX :=0;
begin
if (rst_n = '0') then
fsm_state <= Idle;
read_data_o <='0';
fv_o <='0';
dv_o <='0';
last_packet :='0';
flow_rdy_r <='0';
cpt_s <= CPT_MAX;
elsif (rising_edge(clk)) then
f_empty_r <= f_empty_i; -- reg pour detecter rising/falling edge du signal
flow_rdy_r <= flow_rdy_i;
case fsm_state is
when Idle =>
dv_o <='0';
read_data_o <= '0';
last_packet :='0';
if (enable_i ='1' and flow_rdy_r='0' and flow_rdy_i='1') then -- si le flow est rdy
fsm_state <= DecodeFlag;
end if;
when DecodeFlag =>
if (flag_i = FLAGS_CODES(SoF) or flag_i = FLAGS_CODES(Data)) then
fv_o <= '1';
end if; -- si debut d'image on monte le fv
if (flag_i = FLAGS_CODES(EoF) or flag_i = FLAGS_CODES(Data)) then
last_packet :='1' ;
end if;
read_data_o <= '1';
fsm_state <= ClkCycle;
-- one cycle delay between read_data request and data presence as input
when StartRead =>
read_data_o <= '1';
cpt_s <= CPT_MAX;
fsm_state <= ClkCycle;
when ClkCycle =>
read_data_o <= '0';
cpt_s <= CPT_MAX;
fsm_state <= ReadFlow;
when ReadFlow =>
dv_o <='1';
for i in 0 to DATA_SZ-1 loop
data_o(i) <= data_i(i+DATA_SZ*(cpt_s-1));
end loop;
cpt_s <= cpt_s - 1;
if(cpt_s = 0) then
dv_o <='0';
if(f_empty_i='1') then
fsm_state <= EndFlow;
else
fsm_state <= StartRead;
end if;
end if;
when EndFlow =>
dv_o <= '0'; -- release Data valid
if (last_packet = '1') then
fv_o <= '0';
end if;
fsm_state <= Idle;
end case;
end if;
end process;
end rtl;
| gpl-3.0 | 618787d6ba7e0da0951a5dbb7671c704 | 0.478427 | 3.209465 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/sync/syncClockDomains.vhdl | 1 | 14,097 | --
-- Synchronizes Clock Domains
-- This core solves the communication between components working at different frequencies.
--
-- Author(s):
-- * Rodrigo A. Melo
-- * Based in a Gaisler's mechanism used in the GRLib IP library http://www.gaisler.com/
--
-- Copyright (c) 2009-2015 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
---------------------------------------------------------------------------------------------------
--
-- SyncClockDomains sirve para sincronizar 2 dispositivos que trabajan a diferentes clocks.
--
---------------------------------------------------------------------------------------------------
-- Solución de Gaisler
---------------------------------------------------------------------------------------------------
--
-- La siguiente solución es la utilizada por Gaisler en el core Ethernet de la GRLib (GReth). Está
-- incrustado en el código por todos lados y no utiliza los nombres aquí dados a las señales.
--
-- Se tiene un coreA, que trabaja a una frecuencia clkA, que habilita al coreB, que trabaja a clkB,
-- mediante una señal x. Esta señal, trabaja por cambio de estado y no generando simplemente un
-- pulso, ya que en varias oportunidades o no se llegaría a detectar, si clkA > clkB, o se
-- detectaría varias veces, si clkA < clkB. En el coreB, en cada flanco ascendente de clkB, una
-- señal x' copia el estado de x. A su vez, una señal de ack (acknowledge) del coreB al coreA, se
-- asigna en cada clkB con el valor x'.
--
-- Supongamos inicialmente que tanto x, como x' y ack, arrancan en '0'. Ahora el coreA coloca x a
-- '1'. El coreB, en el siguiente flanco de subida de clkB, asignará x' a '1', y en el que le
-- sigue, asignará ack a '1'. En coreB, de hacer un XOR entre x' y ack, se obtienen los pulsos de
-- habilitación enaB que el core precise. En coreA, una vez que se observa el ack, se pasa a '1'
-- una señal ack' y en el siguiente clkA se pasa a '1' un ack''. Con estas 2 se logran los pulsos
-- de habilitación enaA que el coreA precise. Para este punto, todas las señales que se manejan por
-- cambio de nivel quedaron a '1' y el coreA esta listo para reiniciar el ciclo colocando x a '0'.
--
-- Un diagrama de señales para verlo mas claro:
-- ____ ____ ____ ____
-- clkA __I I__I I__I I__I I__I } El coreA, a su frecuencia clkA,
-- _________________________ } pasa x a '1'.
-- x __I }
--
-- _____ _____ _____
-- clkB ____I I____I I____I I } El coreB, a su frecuencia clkB,
-- _______________________ } una vez que detecta x='1', coloca
-- x' ____I } x' a '1'.
-- ______________ }
-- ack _____________I } En el siguiente clkB, ack pasa a '1'.
-- __________ }
-- enaB ____I I_____________ } Del XOR entre x' y ack se obtiene enaB.
--
-- ____ ____ ____ ____
-- clkA __I I__I I__I I__I I__I } El coreA, a su frecuencia clkA,
-- _____________ } una vez que detecta ack='1', coloca
-- ack' ______________I } ack' a '1'.
-- _______ }
-- ack'' ____________________I } En el siguiente clkA, ack'' pasa a '1'.
-- _______ }
-- enaA ______________I I______ } Del XOR entre ack' y ack'' se obtiene enaA.
--
--
-- Del método descripto usado por Gaisler, se observa que no se utiliza directamente el cambio de
-- estado en x para generar la habilitación en coreB en el primer clkB, sino que primero se usa un
-- flip flop para obtener x' y luego esta señal se utiliza para la habilitación. Esto es así para
-- reducir problemas de metaestabilidad. Además, el core de Gaisler, mediante un generic, permite
-- seleccionar si se utiliza un solo flip flop de sincronismo o 2, dado más flip flops en cascadas,
-- más probable es recuperarse de una situación de metaestabilidad.
--
---------------------------------------------------------------------------------------------------
-- Metaestabilidad. Según Wikipedia
---------------------------------------------------------------------------------------------------
--
-- Los circuitos electrónicos digitales basan su funcionamiento en la manipulación mediante álgebra
-- binaria de los niveles lógicos 0 y 1, que físicamente se corresponden con niveles de tensión,
-- típicamente tierra y tensión de alimentación.
-- Uno de los componentes básicos empleados en los circuitos digitales son los biestables. Estos
-- componentes tienen la facultad de retardar señales binarias, permitiendo al circuito memorizar
-- estados.
-- Los biestables requieren para su funcionamiento que se les alimente con una señal periódica de
-- reloj, que les indica cuándo han de muestrear la señal a su entrada. Si esta señal de entrada
-- conmuta (cambia de valor) justo en el instante de muestreo, el biestable capturará un valor
-- intermedio entre las tensiones correspondientes a los niveles lógicos 0 y 1. Este estado en el
-- cual un biestable almacena un nivel lógico no válido se denomina estado metaestable, y puede
-- provocar que el circuito digital opere de forma inesperada o errónea.
-- El estado metaestable, aunque teóricamente puede mantenerse indefinidamente, siempre acabará
-- resolviéndose en un valor lógico válido 0 o 1, aunque no es posible saber cuánto tiempo tardará.
-- Un diseño cuidadoso del componente biestable asegurará que el tiempo medio de resolución sea lo
-- suficientemente bajo como para evitar que pueda poner en peligro el funcionamiento correcto del
-- circuito. Técnicas de diseño de más alto nivel, como el uso de circuitos sincronizadores
-- consistentes en varios biestables en cascada, o de circuitos de handshake, dan mayor robustez al
-- diseño frente al problema de la metaestabilidad, minimizando la probabilidad de que suceda hasta
-- un nivel despreciable. Pese a todo, en circuitos digitales complejos de varios cientos de miles
-- de puertas lógicas y varias señales de reloj asíncronas entre sí, como los presentes en todos
-- los chips digitales que se fabrican en la actualidad, evitar los estados metaestables es un
-- desafío que requiere gran cuidado por parte del diseñador.
--
---------------------------------------------------------------------------------------------------
-- El Core implementado
---------------------------------------------------------------------------------------------------
--
-- La idea fue reflejar el comportamiento usado por Gaisler en un componente, teniendo como
-- objetivo la reutilización y versatilidad del mismo, y esclarecer código donde sea utilizado.
--
-- La caja negra (entity) del mismo y su descripción
-- _________
-- I I
-- clkA_i ------>I I<------ clkB_i
-- I I
-- a_i ------>I I------> b_o
-- I I
-- ack_o <------I I
-- I_______I
-- rst_i -----------^
--
-- * La interfaz A, es la del componente que indica algo al otro y recibe el ack.
-- * La interfaz B, es la del componente que recibe la indicación.
-- * clkA_i y clkB_i son las señales de clock de las interfases A y B.
-- * a_i es la llamada x en la descripción del método de Gaisler, mientras que b_o y ack_o son las
-- llamadas enaB y enaA en dicha descripción.
-- * rst_i es la señal de reset, que deberá ser manejada por el componente que haya instanciado al
-- core (no es exclusivo del lado A o B).
--
-- Nota: la idea del core es que sea instanciado solo en uno de los 2 cores involucrados en la
-- comunicación, o en su defecto, en ninguno de los 2 sino en una descripción que los incluya.
--
-- Generics:
--
-- - INBYLEVEL (INput BY LEVEL, boolean):
-- Indica el tipo de señalización de a_i.
-- FALSE: a_i funciona como pulso de habilitación (valor por defecto).
-- TRUE : a_i funciona por cambio de nivel.
-- - FFSTAGES (Flip Flop STAGES, natural):
-- Indica la cantidad de flip flops a utilizar para la generación de b_o y
-- ack_o, ante un suceso en a_i.
-- Su valor mínimo es 0 y no tiene límite superior. 2 es su valor por defecto.
-- Nota: no utilizar flip flops no es recomendable por la alta probabilidad de
-- problemas de metaestabilidad, pero es agregado para poder realizar pruebas
-- de laboratorio.
-- - CHANNELS (positive):
-- Las señales a_i, b_o y ack_o, son del tipo std_logic_vector. Este GENERIC especifica su tamaño
-- y representa la cantidad de canales a utilizar. Se utiliza para resolver varias comunicaciones
-- con una sola instanciación del componente. 1 es su valor por defecto y el mínimo posible.
--
-- Modo de uso:
--
-- 1 - Incluir la librería
-- library FPGALIB;
-- use FPGALIB.sync.all;
--
-- 2 - Instanciación
-- Para el caso de un solo canal, se puede utilizar el componente SyncClockDomainsBase. El mismo
-- no cuenta con el Generic CHANNELS.
--
-- SCDB: SyncClockDomainsBase
-- generic map(INBYLEVEL => INBYLEVEL, FFSTAGES => FFSTAGES)
-- port map(
-- rst_i => rst_i, clkA_i => clkA , clkB_i => clkB,
-- a_i => entrada, b_o => salida, ack_o => acknowledge
-- );
--
-- Para el caso de más de un canal. Se utiliza el Generic CHANNEL para especificar la cantidad de
-- los mismos a utilizar.
--
-- Los puertos a_i, b_o y ack_o, pasan a ser del tipo std_logic_vector(CHANNELS downto 0)
--
-- * Ejemplo 1:
--
-- Ejemplo1: SyncClockDomains
-- generic map(CHANNELS => 2)
-- port map(
-- rst_i => rst, clkA_i => clkA, clkB_i => clkB,
-- a_i(0) => ch1_a, a_i(1) => ch2_a,
-- b_o(0) => ch1_b, b_o(1) => ch2_b,
-- ack_o(0) => ch1_ack, ack_o(1) => ch2_ack
-- );
--
-- En este caso, directamente en la instanciación asocio los puertos a las señales que quiero
-- utilizar.
--
-- * Ejemplo 2:
--
-- Ejemplo2: SyncClockDomains
-- generic map(CHANNELS => 2)
-- port map(
-- rst_i => rst, clkA_i => clkA, clkB_i => clkB,
-- a_i => entradas, b_o => salidas, ack_o => acknowledges
-- );
--
-- En este caso, los puertos se asocian a señales del mismo tipo que los puertos y se pueden
-- utilizar directamente manejando un subíndice o asignar a las señales que se precisen.
--
-- 3 - Algoritmo de utilización.
-- a) El coreA señaliza determinado suceso mediante el puerto a_i.
-- b) El coreB recibirá un pulso de habilitación mediante b_o.
-- c) El coreA recibirá el reconocimiento de que el coreB procesó la información mediante el puerto
-- ack_o y queda listo para la siguiente operación.
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity SyncClockDomainsBase is
generic(
INBYLEVEL : boolean:=FALSE; -- Input By Level
FFSTAGES : natural:= 2 -- Flip Flop Stages
);
port(
rst_i : in std_logic;
clka_i : in std_logic;
clkb_i : in std_logic;
a_i : in std_logic;
b_o : out std_logic;
ack_o : out std_logic
);
end entity SyncClockDomainsBase;
architecture RTL of SyncClockDomainsBase is
signal a : std_logic:='0';
signal acka, ackb : std_logic_vector(FFSTAGES downto 0):=(others => '0');
begin
in_by_level:
if INBYLEVEL generate
a <= a_i;
end generate in_by_level;
in_no_level:
if not INBYLEVEL generate
sideA_in:
process (clka_i)
begin
if rising_edge(clka_i) then
if rst_i = '1' then
a <= '0';
else
if a_i = '1' then
a <= not(a);
end if;
end if;
end if;
end process sideA_in;
end generate in_no_level;
sideB:
process (clkb_i)
begin
if rising_edge(clkb_i) then
if rst_i = '1' then
ackb <= (others => '0');
else
ackb(0) <= a;
if FFSTAGES > 0 then
for i in 0 to FFSTAGES-1 loop
ackb(i+1) <= ackb(i);
end loop;
end if;
end if;
end if;
end process sideB;
sideA:
process (clka_i)
begin
if rising_edge(clka_i) then
if rst_i = '1' then
acka <= (others => '0');
else
acka(0) <= ackb(FFSTAGES);
if FFSTAGES > 0 then
for i in 0 to FFSTAGES-1 loop
acka(i+1) <= acka(i);
end loop;
end if;
end if;
end if;
end process sideA;
WITHOUT_FF:
if FFSTAGES = 0 generate
b_o <= a xor ackb(0);
ack_o <= ackb(0) xor acka(0);
end generate WITHOUT_FF;
WITH_FF:
if FFSTAGES /= 0 generate
b_o <= ackb(FFSTAGES-1) xor ackb(FFSTAGES);
ack_o <= acka(FFSTAGES-1) xor acka(FFSTAGES);
end generate WITH_FF;
end architecture RTL;
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.Sync.all;
entity SyncClockDomains is
generic(
INBYLEVEL : boolean:=FALSE; -- Input By Level
FFSTAGES : natural:= 2; -- Flip Flop Stages
CHANNELS : positive:= 1 -- Channels
);
port(
rst_i : in std_logic;
clkA_i : in std_logic;
clkB_i : in std_logic;
a_i : in std_logic_vector(CHANNELS-1 downto 0);
b_o : out std_logic_vector(CHANNELS-1 downto 0);
ack_o : out std_logic_vector(CHANNELS-1 downto 0));
end entity SyncClockDomains;
architecture Structural of SyncClockDomains is
begin
make_channels:
for i in 0 to CHANNELS-1 generate
SCDB: SyncClockDomainsBase
generic map(INBYLEVEL => INBYLEVEL, FFSTAGES => FFSTAGES)
port map(rst_i => rst_i, clkA_i => clkA_i , clkB_i => clkB_i,
a_i => a_i(i), b_o => b_o(i), ack_o => ack_o(i));
end generate make_channels;
end architecture Structural;
| bsd-3-clause | 2cf89e4f7a39e04eb4bfd0e0a2852b26 | 0.584459 | 3.513059 | false | false | false | false |
DreamIP/GPStudio | support/io/mt9/hdl/mt9.vhd | 1 | 9,435 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity mt9 is
generic (
OUT_SIZE : integer := 8;
CLK_PROC_FREQ : integer := 48000000;
CLK_IMG_FREQ : integer := 9000000;
CLK_50K_FREQ : integer := 50000;
CLK_100K_FREQ : integer := 100000
);
port (
clk_proc : in std_logic;
clk_img : in std_logic;
clk_50k : in std_logic;
clk_100k : in std_logic;
reset_n : in std_logic;
--------------------- external ports --------------------
data_i : in std_logic_vector(11 downto 0);
fval_i : in std_logic;
lval_i : in std_logic;
pixclk_i : in std_logic;
extclk_o : out std_logic;
reset_n_o : out std_logic;
standby_o : out std_logic;
oe_n_o : out std_logic;
trigger_o : out std_logic;
saddr_o : out std_logic;
sdata_io : inout std_logic;
sclk_o : out std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(4 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end mt9;
architecture rtl of mt9 is
component mt9_config_slave
port(
clk_proc : in std_logic;
reset_n : in std_logic;
-- bus_sl
addr_rel_i : in std_logic_vector(4 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0);
-- connections to video sampler
enable_o : out std_logic;
flowlength_o : out std_logic_vector(31 downto 0);
-- connections to mt9_config_i2c
xstart_o : out std_logic_vector(15 downto 0);
ystart_o : out std_logic_vector(15 downto 0);
xend_o : out std_logic_vector(15 downto 0);
yend_o : out std_logic_vector(15 downto 0);
autoexp_o : out std_logic;
autoexptarget_o : out std_logic_vector(15 downto 0);
autoexpvmin_o : out std_logic_vector(15 downto 0);
autoexpvmax_o : out std_logic_vector(15 downto 0);
autoexpstepmin_o : out std_logic_vector(15 downto 0);
autoexpstepmax_o : out std_logic_vector(15 downto 0);
autoexpdampofset_o : out std_logic_vector(15 downto 0);
autoexpdampgain_o : out std_logic_vector(15 downto 0);
autoexpdampmax_o : out std_logic_vector(15 downto 0);
flipvert_o : out std_logic;
mirrorx_o : out std_logic;
binning_o : out std_logic;
integtime_o : out std_logic_vector(15 downto 0);
linelenght_o : out std_logic_vector(15 downto 0);
need_to_reconf_o : out std_logic
);
end component;
component mt9_config_i2c
port(
reset_n : in std_logic;
mt9_extclk : in std_logic;
mt9_sclk : in std_logic;
mt9_sclkdouble : in std_logic;
mt9_extclk_o : out std_logic;
mt9_reset_n_o : out std_logic;
mt9_standby_o : out std_logic;
mt9_oe_n_o : out std_logic;
mt9_trigger_o : out std_logic;
mt9_saddr_o : out std_logic;
mt9_sdata_io : inout std_logic;
mt9_sclk_o : out std_logic;
-- connections from mt9_config_i2c
xstart_i : in std_logic_vector(15 downto 0);
ystart_i : in std_logic_vector(15 downto 0);
xend_i : in std_logic_vector(15 downto 0);
yend_i : in std_logic_vector(15 downto 0);
autoexp_i : in std_logic;
autoexptarget_i : in std_logic_vector(15 downto 0);
autoexpvmin_i : in std_logic_vector(15 downto 0);
autoexpvmax_i : in std_logic_vector(15 downto 0);
autoexpstepmin_i : in std_logic_vector(15 downto 0);
autoexpstepmax_i : in std_logic_vector(15 downto 0);
autoexpdampofset_i : in std_logic_vector(15 downto 0);
autoexpdampgain_i : in std_logic_vector(15 downto 0);
autoexpdampmax_i : in std_logic_vector(15 downto 0);
flipvert_i : in std_logic;
mirrorx_i : in std_logic;
binning_i : in std_logic;
integtime_i : in std_logic_vector(15 downto 0);
linelenght_i : in std_logic_vector(15 downto 0);
send_reconf_i : in std_logic;
mt9_conf_done_o : out std_logic
);
end component;
component VideoSampler
generic(
DATA_WIDTH : integer;
PIXEL_WIDTH : integer;
FIFO_DEPTH : integer;
DEFAULT_SCR : integer;
DEFAULT_FLOWLENGHT : integer;
HREF_POLARITY : string;
VSYNC_POLARITY : string
);
port(
-- input from CLOCK50 domain
clk_i : in std_logic;
reset_n_i : in std_logic;
-- inputs from camera
pclk_i : in std_logic;
href_i : in std_logic;
vsync_i : in std_logic;
pixel_i : in std_logic_vector(OUT_SIZE-1 downto 0);
-- params from slave
enable_i : in std_logic;
flowlength_i : in std_logic_vector(31 downto 0);
-- Stream interface
data_o : out std_logic_vector(OUT_SIZE-1 downto 0);
dv_o : out std_logic;
fv_o : out std_logic
);
end component;
-- signals part
signal ext_clk_9M_s : std_logic;
signal sclk_100k_s : std_logic;
signal sclk_50k_s : std_logic;
signal enable_s : std_logic;
signal flowlength_s : std_logic_vector(31 downto 0);
signal xstart_s : std_logic_vector(15 downto 0);
signal ystart_s : std_logic_vector(15 downto 0);
signal xend_s : std_logic_vector(15 downto 0);
signal yend_s : std_logic_vector(15 downto 0);
signal autoexp_s : std_logic;
signal autoexptarget_s : std_logic_vector(15 downto 0);
signal autoexpvmin_s : std_logic_vector(15 downto 0);
signal autoexpvmax_s : std_logic_vector(15 downto 0);
signal autoexpstepmin_s : std_logic_vector(15 downto 0);
signal autoexpstepmax_s : std_logic_vector(15 downto 0);
signal autoexpdampofset_s : std_logic_vector(15 downto 0);
signal autoexpdampgain_s : std_logic_vector(15 downto 0);
signal autoexpdampmax_s : std_logic_vector(15 downto 0);
signal flipvert_s : std_logic;
signal mirrorx_s : std_logic;
signal binning_s : std_logic;
signal integtime_s : std_logic_vector(15 downto 0);
signal linelenght_s : std_logic_vector(15 downto 0);
signal need_to_reconf_s : std_logic;
signal send_reconf_s : std_logic;
signal mt9_conf_done_s : std_logic;
signal mt9_conf_done_prev_s : std_logic;
begin
mt9_config_slave_inst : mt9_config_slave
port map (
clk_proc => clk_proc,
reset_n => reset_n,
-- bus_sl
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o,
-- connections to video sampler
enable_o => enable_s,
flowlength_o => flowlength_s,
-- connections to slave i2c
xstart_o => xstart_s,
ystart_o => ystart_s,
xend_o => xend_s,
yend_o => yend_s,
autoexp_o => autoexp_s,
autoexptarget_o => autoexptarget_s,
autoexpvmin_o => autoexpvmin_s,
autoexpvmax_o => autoexpvmax_s,
autoexpstepmin_o => autoexpstepmin_s,
autoexpstepmax_o => autoexpstepmax_s,
autoexpdampofset_o => autoexpdampofset_s,
autoexpdampgain_o => autoexpdampgain_s,
autoexpdampmax_o => autoexpdampmax_s,
flipvert_o => flipvert_s,
mirrorx_o => mirrorx_s,
binning_o => binning_s,
integtime_o => integtime_s,
linelenght_o => linelenght_s,
need_to_reconf_o => need_to_reconf_s
);
mt9_config_i2c_inst : mt9_config_i2c
port map (
reset_n => reset_n,
mt9_extclk => ext_clk_9M_s,
mt9_sclk => sclk_50k_s,
mt9_sclkdouble => sclk_100k_s,
mt9_extclk_o => extclk_o,
mt9_reset_n_o => reset_n_o,
mt9_standby_o => standby_o,
mt9_oe_n_o => oe_n_o,
mt9_trigger_o => trigger_o,
mt9_saddr_o => saddr_o,
mt9_sdata_io => sdata_io,
mt9_sclk_o => sclk_o,
-- connections from mt9_config_slave
xstart_i => xstart_s,
ystart_i => ystart_s,
xend_i => xend_s,
yend_i => yend_s,
autoexp_i => autoexp_s,
autoexptarget_i => autoexptarget_s,
autoexpvmin_i => autoexpvmin_s,
autoexpvmax_i => autoexpvmax_s,
autoexpstepmin_i => autoexpstepmin_s,
autoexpstepmax_i => autoexpstepmax_s,
autoexpdampofset_i => autoexpdampofset_s,
autoexpdampgain_i => autoexpdampgain_s,
autoexpdampmax_i => autoexpdampmax_s,
flipvert_i => flipvert_s,
mirrorx_i => mirrorx_s,
binning_i => binning_s,
integtime_i => integtime_s,
linelenght_i => linelenght_s,
send_reconf_i => send_reconf_s,
mt9_conf_done_o => mt9_conf_done_s
);
VideoSampler_inst : VideoSampler
generic map (
PIXEL_WIDTH => OUT_SIZE,
DATA_WIDTH => 32,
FIFO_DEPTH => 4096*4,
DEFAULT_SCR => 0,
DEFAULT_FLOWLENGHT => 254*254,
HREF_POLARITY => "high",
VSYNC_POLARITY => "high"
)
port map (
reset_n_i => reset_n,
clk_i => clk_proc,
pclk_i => pixclk_i,
href_i => lval_i,
vsync_i => fval_i,
pixel_i => data_i(11 downto 12-OUT_SIZE), -- only take msb
enable_i => enable_s,
flowlength_i => flowlength_s,
data_o => out_data,
dv_o => out_dv,
fv_o => out_fv
);
ext_clk_9M_s <= clk_img;
sclk_100k_s <= clk_100k;
sclk_50k_s <= clk_50k;
process(clk_proc, need_to_reconf_s, mt9_conf_done_s, mt9_conf_done_prev_s)
begin
if(rising_edge(clk_proc)) then
if(need_to_reconf_s = '1') then
send_reconf_s <= '1';
elsif(mt9_conf_done_prev_s='0' and mt9_conf_done_s = '1') then
send_reconf_s <= '0';
end if;
mt9_conf_done_prev_s <= mt9_conf_done_s;
end if;
end process;
end rtl;
| gpl-3.0 | 229b0908e20a0f36b836c0fa1040dbfd | 0.624377 | 2.446202 | false | false | false | false |
DreamIP/GPStudio | support/process/sconv/hdl/pipliner_3x3.vhd | 1 | 4,189 | -- Author : K. Abdelouahab
-- Company : DREAM - Institut Pascal - Unviersite Clermont Auvergne
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity pipliner_3x3 is
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0);
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_fv : out std_logic;
out_dv : out std_logic;
p00, p01, p02 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p10, p11, p12 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p20, p21, p22 : out std_logic_vector((PIX_WIDTH-1) downto 0)
);
end pipliner_3x3;
architecture structural of pipliner_3x3 is
signal line0_pix_out : std_logic_vector((PIX_WIDTH-1) downto 0);
signal line1_pix_out : std_logic_vector((PIX_WIDTH-1) downto 0);
signal p00_s, p01_s, p02_s : std_logic_vector((PIX_WIDTH-1) downto 0);
signal p10_s, p11_s, p12_s : std_logic_vector((PIX_WIDTH-1) downto 0);
signal p20_s, p21_s, p22_s : std_logic_vector((PIX_WIDTH-1) downto 0);
signal all_valid,fvs,dvs : std_logic;
signal enable_reg : std_logic;
signal reset_st,reset_s : std_logic;
component pipline_gen
generic (
PIPLINE_LENGHT : integer;
WORD_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
e : in std_logic;
in_data : in std_logic_vector (WORD_SIZE-1 downto 0);
i0,i1,i2 : out std_logic_vector (WORD_SIZE-1 downto 0);
out_data : out std_logic_vector (WORD_SIZE-1 downto 0)
);
end component;
begin
enable_proc : process(enable_i,in_fv)
begin
if (enable_i = '0') then
reset_st <= '0';
elsif(rising_edge(in_fv)) then
reset_st <= '1';
end if;
end process;
all_valid <= in_dv and in_fv;
reset_s <= reset_st and reset_n;
data_pipline0 : pipline_gen
generic map (
PIPLINE_LENGHT => LINE_WIDTH_MAX-1,
WORD_SIZE => PIX_WIDTH
)
port map (
clk_proc => clk_proc,
reset_n => reset_s,
e => all_valid,
in_data => in_data,
i0 => p22,
i1 => p21,
i2 => p20,
out_data => line0_pix_out
);
data_pipline1 : pipline_gen
generic map (
PIPLINE_LENGHT => LINE_WIDTH_MAX-1,
WORD_SIZE => PIX_WIDTH
)
port map (
clk_proc => clk_proc,
reset_n => reset_s,
e => all_valid,
in_data => line0_pix_out,
i0 => p12,
i1 => p11,
i2 => p10,
out_data => line1_pix_out
);
data_pipline2 : pipline_gen
generic map (
PIPLINE_LENGHT => 3,
WORD_SIZE => PIX_WIDTH
)
port map (
clk_proc => clk_proc,
reset_n => reset_s,
e => all_valid,
in_data => line1_pix_out,
i0 => p02,
i1 => p01,
i2 => p00
);
fv_pipline : pipline_gen
generic map (
PIPLINE_LENGHT => LINE_WIDTH_MAX + LINE_WIDTH_MAX + 4 ,
WORD_SIZE => 1
)
port map (
clk_proc => clk_proc,
reset_n => reset_s,
e => all_valid,
in_data(0) => in_fv,
out_data(0) => fvs
);
dv_pipline : pipline_gen
generic map (
PIPLINE_LENGHT => LINE_WIDTH_MAX + LINE_WIDTH_MAX +4 ,
WORD_SIZE => 1
)
port map (
clk_proc => clk_proc,
reset_n => reset_s,
e => all_valid,
in_data(0) => in_dv,
out_data(0) => dvs
);
out_dv <= dvs and in_dv;
out_fv <= fvs and in_fv;
end structural;
| gpl-3.0 | 2a9b3a5704ef41c2f6532eaeb1d4068b | 0.485319 | 3.102963 | false | false | false | false |
ou-cse-378/vhdl-tetris | stack_ctrl.vhd | 1 | 2,342 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: stack_ctrl.vhd
-- // Date: 12/9/2004
-- // Description: Stack Controller
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity stack_ctrl is
port (
clr: in STD_LOGIC;
clk: in STD_LOGIC;
push: in STD_LOGIC;
pop: in STD_LOGIC;
we: out STD_LOGIC;
amsel: out STD_LOGIC;
wr_addr: out STD_LOGIC_VECTOR(4 downto 0);
rd_addr: out STD_LOGIC_VECTOR(4 downto 0);
full: out STD_LOGIC;
empty: out STD_LOGIC
);
end stack_ctrl;
architecture stack_ctrl_arch of stack_ctrl is
signal full_flag, empty_flag: STD_LOGIC;
begin
stk: process(clr, clk, push, pop, full_flag, empty_flag)
variable push_addr, pop_addr: STD_LOGIC_VECTOR(4 downto 0);
begin
if clr = '1' then
push_addr := "11111";
pop_addr := "00000";
empty_flag <= '1';
full_flag <= '0';
wr_addr <= "11111";
rd_addr <= "00000";
full <= full_flag;
empty <= empty_flag;
elsif clk'event and clk = '1' then
if push = '1' then
if pop = '0' then
if full_flag = '0' then
push_addr := push_addr - 1;
pop_addr := push_addr + 1;
empty_flag <= '0';
if push_addr = "11111" then
full_flag <= '1';
push_addr := "00000";
end if;
end if;
end if;
elsif pop = '1' then
if empty_flag = '0' then
pop_addr := pop_addr + 1;
if full_flag = '0' then
push_addr := push_addr + 1;
end if;
full_flag <= '0';
if pop_addr = "00000" then
empty_flag <= '1';
end if;
end if;
end if;
wr_addr <= push_addr;
rd_addr <= pop_addr;
end if;
full <= full_flag;
empty <= empty_flag;
if push = '1' and full_flag = '0' then
we <= '1';
else
we <= '0';
end if;
if push = '1' and pop = '1' then
amsel <= '1';
else
amsel <= '0';
end if;
end process stk;
end stack_ctrl_arch;
| mit | 2c22272dad318065a16249cae518c138 | 0.466268 | 3.495522 | false | false | false | false |
ou-cse-378/vhdl-tetris | dig7seg.vhd | 1 | 3,090 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: dig7seg.vhd
-- // Date: 12/9/2004
-- // Description: Main display module
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dig7seg is
Port ( T: in std_logic_vector(15 downto 0);
digload: in std_logic;
clr : in std_logic;
clk : in std_logic; --25 Mhz
cclk : in std_logic; --190 Hz
AtoG : out std_logic_vector(6 downto 0);
A : out std_logic_vector(1 to 4));
end dig7seg;
architecture Behavioral of dig7seg is
constant bus_width: positive := 16;
constant bus_width2: positive := 4;
signal y1: STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal q1: std_logic_vector(1 downto 0) :="00";
signal Tout: std_logic_vector(15 downto 0) := "0000000000000000";
signal dig1: std_logic_vector(3 downto 0) := "0000";
signal dig2: std_logic_vector(3 downto 0) := "0000";
signal dig3: std_logic_vector(3 downto 0) := "0000";
signal dig4: std_logic_vector(3 downto 0) := "0000";
component mux4g is
generic(width:positive);
port (
a: in STD_LOGIC_VECTOR (3 downto 0);
b: in STD_LOGIC_VECTOR (3 downto 0);
c: in STD_LOGIC_VECTOR (3 downto 0);
d: in STD_LOGIC_VECTOR (3 downto 0);
sel: in STD_LOGIC_VECTOR(1 downto 0);
y: out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
component seg7dec is
port (
q : in STD_LOGIC_VECTOR(3 downto 0);
AtoG : out STD_LOGIC_VECTOR(6 downto 0));
end component;
component Acode is
port (
Aen: in STD_LOGIC_VECTOR (4 downto 1);
Asel: in STD_LOGIC_VECTOR (1 downto 0);
A: out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
component ctr2bit is
port (
clr: in STD_LOGIC;
clk: in STD_LOGIC;
q: out STD_LOGIC_VECTOR (1 downto 0));
end component;
component reg is
generic(width: positive);
port (
d: in STD_LOGIC_VECTOR (width-1 downto 0);
load: in STD_LOGIC;
clr: in STD_LOGIC;
clk: in STD_LOGIC;
q: out STD_LOGIC_VECTOR (width-1 downto 0)
);
end component;
begin
dig1 <= Tout(15 downto 12);
dig2 <= Tout(11 downto 8);
dig3 <= Tout(7 downto 4);
dig4 <= Tout(3 downto 0);
DispReg: reg generic map(width => bus_width) port map(d => T, load => digload, clr => clr, clk => clk, q => Tout);
SEG7: seg7dec port map (q => y1, AtoG => AtoG);
ACODE00: Acode port map (Asel => q1, Aen => "1111", A => A);
CTR2BIT00: ctr2bit port map (clr => clr, clk => cclk, q => q1);
MUX4G00: mux4g generic map(width => bus_width2) port map(a => dig1, b => dig2, c => dig3, d => dig4, y => y1, sel => q1);
end Behavioral;
| mit | 9daf735c20d62ae03356e3179aeb769f | 0.586084 | 3.205394 | false | false | false | false |
DreamIP/GPStudio | support/process/gaussian/hdl/gaussian_slave.vhd | 1 | 3,049 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity gaussian_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end gaussian_slave;
architecture rtl of gaussian_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant WIDTHIMG_REG_REG_ADDR : natural := 1;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal widthimg_reg_width_reg : std_logic_vector (15 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
widthimg_reg_width_reg <= "0000000000000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
status_reg_enable_bit_reg <= datawr_i(0);
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
widthimg_reg_width_reg <= datawr_i(15) & datawr_i(14) & datawr_i(13) & datawr_i(12) & datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000000000000000000" & status_reg_enable_bit_reg;
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000" & widthimg_reg_width_reg(15) & widthimg_reg_width_reg(14) & widthimg_reg_width_reg(13) & widthimg_reg_width_reg(12) & widthimg_reg_width_reg(11) & widthimg_reg_width_reg(10) & widthimg_reg_width_reg(9) & widthimg_reg_width_reg(8) & widthimg_reg_width_reg(7) & widthimg_reg_width_reg(6) & widthimg_reg_width_reg(5) & widthimg_reg_width_reg(4) & widthimg_reg_width_reg(3) & widthimg_reg_width_reg(2) & widthimg_reg_width_reg(1) & widthimg_reg_width_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
widthimg_reg_width <= widthimg_reg_width_reg;
end rtl;
| gpl-3.0 | 3b7aae4835830e203267ad57d6cb2414 | 0.594293 | 2.873704 | false | false | false | false |
DreamIP/GPStudio | support/process/harris/hdl/generic_window_extractor.vhd | 1 | 6,694 | -------------------------------------------------------------------------------
-- Copyright Institut Pascal Equipe Dream (19-10-2016)
-- Francois Berry, El Mehdi Abdali, Maxime Pelcat
-- This software is a computer program whose purpose is to manage dynamic
-- partial reconfiguration.
-- This software is governed by the CeCILL-C license under French law and
-- abiding by the rules of distribution of free software. You can use,
-- modify and/ or redistribute the software under the terms of the CeCILL-C
-- license as circulated by CEA, CNRS and INRIA at the following URL
-- "http://www.cecill.info".
-- As a counterpart to the access to the source code and rights to copy,
-- modify and redistribute granted by the license, users are provided only
-- with a limited warranty and the software's author, the holder of the
-- economic rights, and the successive licensors have only limited
-- liability.
-- In this respect, the user's attention is drawn to the risks associated
-- with loading, using, modifying and/or developing or reproducing the
-- software by the user in light of its specific status of free software,
-- that may mean that it is complicated to manipulate, and that also
-- therefore means that it is reserved for developers and experienced
-- professionals having in-depth computer knowledge. Users are therefore
-- encouraged to load and test the software's suitability as regards their
-- requirements in conditions enabling the security of their systems and/or
-- data to be ensured and, more generally, to use and operate it in the
-- same conditions as regards security.
-- The fact that you are presently reading this means that you have had
-- knowledge of the CeCILL-C license and that you accept its terms.
-------------------------------------------------------------------------------
-- Doxygen Comments -----------------------------------------------------------
--! @file generic_window_extractor.vhd
--
--! @brief generic window extractor
--! @author Francois Berry, El Mehdi Abdali, Maxime Pelcat
--! @board SoCKit from Arrow and Terasic
--! @version 1.0
--! @date 11/01/2017
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
library altera_mf;
use work.window_extractor_pkg.all;
entity generic_window_extractor is
generic
(
line_width_max : integer;
pix_width : integer;
matrix_width : integer
);
port
(
clk : in std_logic;
reset_n : in std_logic;
--/* input flow */
in_data : in std_logic_vector((pix_width-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_fv : out std_logic;
out_dv : out std_logic;
widthimg_i : in std_logic_vector(15 downto 0);
pixel_window : out generic_pixel_window(0 to matrix_width-1, 0 to matrix_width-1)(pix_width-1 downto 0)
);
end generic_window_extractor;
architecture arch of generic_window_extractor is
type pix_out_signal is array (0 to matrix_width-2) of std_logic_vector((pix_width-1) downto 0);
constant FIFO_LENGHT : integer := line_width_max;
constant FIFO_LENGHT_WIDTH : integer := integer(ceil(log2(real(FIFO_LENGHT))));
signal widthimg_temp : std_logic_vector(15 downto 0):=widthimg_i;
signal sig_rdreq : std_logic := '0';
signal line_pix_out : generic_pixel_line(0 to matrix_width-1)(pix_width-1 downto 0);
shared variable param_changing_reset : std_logic := '0';
shared variable aclr : std_logic := '0';
shared variable pixel_matrix_kernel : generic_pixel_window(0 to matrix_width-1, 0 to matrix_width-1)(pix_width-1 downto 0);
component scfifo
generic
(
LPM_WIDTH : positive;
LPM_WIDTHU : positive;
LPM_NUMWORDS : positive;
LPM_SHOWAHEAD : string := "OFF";
ALLOW_RWCYCLE_WHEN_FULL : string := "OFF";
OVERFLOW_CHECKING : string := "ON";
UNDERFLOW_CHECKING : string := "ON"
);
port
(
data : in std_logic_vector(LPM_WIDTH-1 downto 0);
clock,
wrreq,
rdreq,
aclr : in std_logic;
full,
empty,
almost_full,
almost_empty : out std_logic;
q : out std_logic_vector(LPM_WIDTH-1 downto 0);
usedw : out std_logic_vector(LPM_WIDTHU-1 downto 0)
);
end component;
begin
--/* generating the matrix_width-1 line buffers */
G_1 : for i in 0 to matrix_width-2 generate
line_fifo_inst : scfifo
generic map
(
LPM_WIDTH => pix_width,
LPM_WIDTHU => FIFO_LENGHT_WIDTH,
LPM_NUMWORDS => FIFO_LENGHT
)
port map
(
data => pixel_matrix_kernel(i+1,0),
clock => clk,
wrreq => in_dv,
q => line_pix_out(i),
rdreq => sig_rdreq and in_dv,
aclr => param_changing_reset or(not(reset_n))
);
end generate;
process (clk, reset_n)
variable counter :integer:=0;
begin
if(reset_n='0') then
elsif(rising_edge(clk)) then
out_fv <= in_fv;
out_dv <= in_dv;
if(in_fv='0') then
elsif(in_dv='1') then
counter:=counter+1;
if(counter=(unsigned(widthimg_i)-matrix_width-1)) then
sig_rdreq <= '1';
end if;
--/* updating the matrix */
for o in 0 to matrix_width-1 loop
for p in 0 to matrix_width-2 loop
pixel_matrix_kernel(o,p):=pixel_matrix_kernel(o,p+1);
end loop;
if (o<matrix_width-1) then
pixel_matrix_kernel(o,matrix_width-1):=line_pix_out(o);
end if;
end loop;
pixel_matrix_kernel(matrix_width-1,matrix_width-1):=in_data;
else
end if;
--/* fifo reset when widthimg_i changes */
if (unsigned(widthimg_i)=unsigned(widthimg_temp)) then
param_changing_reset := '0';
else
param_changing_reset := '1';
counter := 0;
sig_rdreq <= '0';
end if;
widthimg_temp<=widthimg_i;
else
end if;
end process;
pixel_window <= pixel_matrix_kernel;
end arch;
| gpl-3.0 | cc7685f7d2afe3f0a0c6b49b77a730f0 | 0.560203 | 3.853771 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/altera/fifo/src/asyncFifo-syn-a.vhd | 3 | 3,739 | -------------------------------------------------------------------------------
--! @file asyncFifo-syn-a.vhd
--
--! @brief The asynchronous Fifo architecture for Altera
--
--! @details This is a dual clock fifo generated in Megawizard!
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use altera_mf library
library altera_mf;
use altera_mf.altera_mf_components.all;
architecture syn of asyncFifo is
begin
theAlteraDcFifo : dcfifo
generic map (
intended_device_family => "Cyclone IV E",
lpm_width => gDataWidth,
lpm_widthu => logDualis(gWordSize),
lpm_numwords => gWordSize,
lpm_showahead => "OFF",
lpm_type => "DCFIFO",
overflow_checking => "ON",
underflow_checking => "ON",
delay_rdusedw => 1,
delay_wrusedw => 1,
add_usedw_msb_bit => "OFF",
rdsync_delaypipe => gSyncStages+2,
wrsync_delaypipe => gSyncStages+2,
use_eab => gMemRes,
write_aclr_synch => "ON",
read_aclr_synch => "ON",
clocks_are_synchronized => "FALSE",
add_ram_output_register => "ON"
)
port map (
aclr => iAclr,
data => iWrData,
q => oRdData,
rdclk => iRdClk,
rdempty => oRdEmpty,
rdfull => oRdFull,
rdreq => iRdReq,
rdusedw => oRdUsedw,
wrclk => iWrClk,
wrempty => oWrEmpty,
wrfull => oWrFull,
wrreq => iWrReq,
wrusedw => oWrUsedw
);
end architecture syn;
| gpl-2.0 | e97643dff01855a9b76d1ef72e52fde8 | 0.550682 | 4.906824 | false | false | false | false |
DreamIP/GPStudio | support/io/gps/hdl/gps_fifo.vhd | 1 | 6,965 | -- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
-- ============================================================
-- File Name: fifo_gps.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY fifo_gps IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END fifo_gps;
ARCHITECTURE SYN OF fifo_gps IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC ;
usedw : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wrreq : IN STD_LOGIC
);
END COMPONENT;
BEGIN
usedw <= sub_wire0(7 DOWNTO 0);
empty <= sub_wire1;
full <= sub_wire2;
q <= sub_wire3(7 DOWNTO 0);
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
intended_device_family => "Cyclone III",
lpm_numwords => 256,
lpm_showahead => "OFF",
lpm_type => "scfifo",
lpm_width => 8,
lpm_widthu => 8,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
clock => clock,
data => data,
rdreq => rdreq,
wrreq => wrreq,
usedw => sub_wire0,
empty => sub_wire1,
full => sub_wire2,
q => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "256"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "8"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "8"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_gps.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_gps.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_gps.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_gps.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_gps_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | 7e21e2e0fea6ccd98d8a0d50ffcc5f5d | 0.66346 | 3.510585 | false | false | false | false |
DreamIP/GPStudio | support/io/com/hdl/hal/eth_marvell_88e1111/hdl/ethernet_udp.vhd | 1 | 5,799 | -- This is the top level of the ethernet block.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ethernet_package.all;
entity ethernet_udp is
port (
--- External ports
CLK125 : in STD_LOGIC;
reset_n : in std_logic;
PHY_RESET_L : out STD_LOGIC;
PHY_MDC : out STD_LOGIC;
PHY_MDIO : inout STD_LOGIC;
TX : out rgmii_t;
RX : in rgmii_t;
GE_TXCLK : out std_logic;
--- Clock from PLL to synchronize received data
clk250_marvell : in STD_LOGIC;
clk250_fpga : in STD_LOGIC;
--- parameters from slave
mac_addr_hal_msb : in std_logic_vector(23 downto 0);
mac_addr_hal_lsb : in std_logic_vector(23 downto 0);
mac_addr_dest_msb : in std_logic_vector(23 downto 0);
mac_addr_dest_lsb : in std_logic_vector(23 downto 0);
ip_hal : in std_logic_vector(31 downto 0);
ip_dest : in std_logic_vector(31 downto 0);
port_dest : in std_logic_vector(15 downto 0);
--- Receiving flows to send on link
hal_ready : out std_logic;
data_i : in std_logic_vector(7 downto 0);
data_size_i : in std_logic_vector(15 downto 0);
ready_i : in std_logic;
read_data_o : out std_logic;
--- Transmitting flows received by link
data_o : out std_logic_vector(7 downto 0);
write_o : out std_logic
);
end ethernet_udp;
architecture RTL of ethernet_udp is
signal eth_tx_stream : std_logic_vector(8 downto 0);
signal TX_s : rgmii_t;
signal TX_udp : gmii_t;
signal RX_gmii : gmii_t;
signal RX_sync : gmii_t;
signal RX_gmii_dl : gmii_t;
signal RX_filtered : gmii_t;
signal port_detected : std_logic_vector(15 downto 0);
signal TX_encapsulated : gmii_t;
signal TEST_rx_sync : std_logic;
signal data_valid_i : std_logic;
signal count : std_logic_vector(15 downto 0);
signal read_data_s,hal_ready_s : std_logic;
signal data_valid_dl1,data_valid_dl2 : std_logic;
signal read_data_dl : std_logic;
signal TX_s_dl : std_logic;
begin
data_o <= RX_filtered.data;
write_o <= RX_filtered.dv;
eth_tx_stream <= TX_encapsulated.dv & TX_encapsulated.data;
TX <= TX_s;
read_data_o <= read_data_s;
hal_ready <= hal_ready_s;
GE_TXCLK <= CLK125;
----- Read data from com, read data when the flow_to_com is ready
process(CLK125,reset_n)
begin
if reset_n='0' then
read_data_s <= '0';
hal_ready_s <= '1';
elsif CLK125'event and CLK125='1' then
data_valid_dl1 <= read_data_s;
data_valid_dl2 <= data_valid_dl1;
TX_s_dl <= TX_s.dv;
--- Read data from com, read data when the flow_to_com is ready
if ready_i='1' and read_data_s='0' and hal_ready_s='1' then
read_data_s <= '1';
elsif ready_i='0' then
read_data_s <= '0';
end if;
--- Set hal_ready : high when it starts reading data and low when the packet has been fully sent
if read_data_s='1' and data_valid_dl1='0' then
hal_ready_s <= '0';
elsif TX_s.dv='0' and TX_s_dl='1' then
hal_ready_s <= '1';
end if;
end if;
end process;
data_valid_i <= read_data_s and data_valid_dl2;
--- RGMII to GMII and GMII to RGMII
interface_managemet_inst : entity work.interface_management
port map (
clk125 => clk125,
clk250_marvell => clk250_marvell,
clk250_fpga => clk250_fpga,
reset_n => reset_n,
RX_i => RX,
RX_o => RX_gmii,
TX_i => TX_udp,
TX_o => TX_s
);
----- Filter mac/ip address and detect destination port
filter_mac_ip_port : entity work.eth_udp_filter
port map (
RXCLK => clk125,
reset_n => reset_n,
RX_i => RX_gmii,
RX_o => RX_filtered,
mac_addr_hal_msb => mac_addr_hal_msb,
mac_addr_hal_lsb => mac_addr_hal_lsb,
ip_hal => ip_hal,
port_detected => port_detected
);
----- Adding ip/udp header and gps header to data to send
eth_tx_hdr_inst : entity work.eth_tx_header
Port map(
CLK125 => CLK125,
reset_n => reset_n,
data_i => data_i,
data_size_i => data_size_i,
TX_i.dv => data_valid_i,
TX_i.data => data_i,
TX_o => TX_encapsulated,
--- Parameters from slave
mac_addr_hal_msb => mac_addr_hal_msb,
mac_addr_hal_lsb => mac_addr_hal_lsb,
mac_addr_dest_msb => mac_addr_dest_msb,
mac_addr_dest_lsb => mac_addr_dest_lsb,
ip_hal => ip_hal,
ip_dest => ip_dest,
port_dest => port_dest
);
----- Data to send : padding if needed, adding CRC and preamble
GMStream_inst : entity work.eth_tx_encap(Behavioral)
port map(
GE_TXEN => TX_udp.dv,
GE_TXD => TX_udp.data,
CLK125 => CLK125,
reset_n => reset_n,
ETH_TX_STREAM => eth_tx_stream
);
----- Control the configuration of the marvell and the hardware reset
eth_ctrl : entity work.eth_mdio
port map(
CLK => CLK125,
RESET => reset_n,
E_RST_L => PHY_RESET_L,
E_MDC => PHY_MDC,
E_MDIO => PHY_MDIO
);
end RTL;
| gpl-3.0 | 0c097aa8263bc0d392386d90a78ab8ce | 0.523366 | 3.168852 | false | false | false | false |
DreamIP/GPStudio | support/toolchain/caph/hdl/caph_toplevel/src/tokenize_flow.vhd | 1 | 6,193 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.caph_flow_pkg.all;
-- Bloc de creation de jetons a parti d'un signal d'entree de control dv_i et de deux registres (imwidth_i imheight_i)
-- TODO: actuellement, le bloc ecrit dans la FIFO de sortie meme si celle-ci est pleine => utiliser le signal fifo_full_i
entity tokenize_flow is
generic (
DATA_INPUT_SIZE: integer := 8;
TOKEN_HEADER_SIZE: integer := 2;
TOKEN_SIZE: integer := 10;
IMAGE_WIDTH : integer := 500;
IMAGE_HEIGHT : integer := 2
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
dv_i : in std_logic;
enable_i : in std_logic;
data_i: in std_logic_vector(DATA_INPUT_SIZE-1 downto 0);
imwidth_i : in std_LOGIC_VECTOR(31 downto 0);
imheight_i : in std_LOGIC_VECTOR(31 downto 0);
clk_caph_i:in std_logic; -- clk fifo = clk_pixelx2
fifo_full_i:in std_logic; --fifo_full input
token_o : out std_logic_vector(TOKEN_SIZE-1 downto 0);
wr_fifo_o:out std_logic -- write fifo
);
end entity tokenize_flow;
architecture rtl of tokenize_flow is
constant zero : std_logic_vector(TOKEN_SIZE-TOKEN_HEADER_SIZE-DATA_INPUT_SIZE-1 downto 0):=(others=>'0');
constant zzero : std_logic_vector(DATA_INPUT_SIZE-1 downto 0):=(others=>'0');
signal i_wrf:std_logic;
type t_state is (WaitFirstData,WaitSoL,DataValid,DumpEoL,DumpEoF);
signal state : t_state:=WaitFirstData;
signal endframe: std_logic;
signal dv_r : std_logic;
signal fifo_rdempty_r : std_logic;
signal pixel_r : std_logic_vector(7 downto 0);
signal i_token_o:std_logic_vector(TOKEN_SIZE-1 downto 0);
-- Calcul de la largeur de bus en fonction de la profondeur de la Fifo
-- 2 CLK de retard par LINE
constant FIFO_DEPTH : integer := 4*IMAGE_HEIGHT;
constant WIDTHU : integer := integer(ceil(log2(real(FIFO_DEPTH))));
-------------
-- FIFO 1 SIGNALS
-------------
signal fifo_data_s : std_logic_vector(DATA_INPUT_SIZE-1 downto 0):=(others=>'0');
signal fifo_wrclk_s : std_logic:= '0';
signal fifo_wrreq_s : std_logic:= '0';
signal fifo_wrfull_s : std_logic:= '0';
signal fifo_q_s: std_logic_vector(DATA_INPUT_SIZE-1 downto 0):=(others=>'0');
signal fifo_rdclk_s: std_logic:= '0';
signal fifo_rdreq_s: std_logic:= '0';
signal fifo_rdempty_s : std_logic:= '0';
signal fifo_rdusedw_s : std_logic_vector(integer(ceil(log2(real(FIFO_DEPTH))))-1 DOWNTO 0):=(others=>'0');
signal fifo_wrusedw_s : std_logic_vector(integer(ceil(log2(real(FIFO_DEPTH))))-1 DOWNTO 0):=(others=>'0');
signal fifo_aclr_s : std_logic :='0';
signal data_cpt: integer range 0 to MAX_IMAGE_WIDTH := 0;
signal line_cpt: integer range 0 to MAX_IMAGE_HEIGHT := 0;
---------------------------------------------------------
-- COMPONENT DECLARATION
---------------------------------------------------------
component fifo_route_matrix
GENERIC
(
DEPTH : POSITIVE := 10;
DATA_SIZE : POSITIVE := 8
);
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (DATA_INPUT_SIZE-1 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (DATA_INPUT_SIZE-1 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (WIDTHU-1 DOWNTO 0);
wrfull : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (WIDTHU-1 DOWNTO 0)
);
END component;
begin
FIFO_1 : component fifo_route_matrix
GENERIC MAP(
DEPTH => FIFO_DEPTH,
DATA_SIZE => 8
)
PORT map
(
data => fifo_data_s,
rdclk => clk_i,
rdreq => fifo_rdreq_s,
wrclk => clk_i,
wrreq => fifo_wrreq_s,
aclr => fifo_aclr_s,
q => fifo_q_s,
rdempty => fifo_rdempty_s,
rdusedw => fifo_rdusedw_s,
wrusedw => fifo_wrusedw_s,
wrfull => fifo_wrfull_s
);
fifo_data_s <= data_i;
fifo_wrreq_s <= dv_i and enable_i;
fifo_aclr_s <= not(rst_n_i and enable_i);
-- Conditions de commande de la FIFO Altera
fifo_read_label: fifo_rdreq_s <=
not(fifo_rdempty_s) when (state=WaitFirstData) else
not(fifo_rdempty_s) when (state=WaitSoL) else
not(fifo_rdempty_s) when (state=DataValid) and (data_cpt< to_integer(unsigned(imwidth_i))) else
'0' when (state=DataValid) and data_cpt=to_integer(unsigned(imwidth_i)) else
'0' when (state=DumpEoL) else
'0' when (state=DumpEoF) else
'0';
process(clk_i,rst_n_i)
begin
if (rst_n_i = '0') then
state <= WaitFirstData;
i_token_o <=(others=>'0');
pixel_r <= (others=>'0');
data_cpt <= 0;
line_cpt <=0;
dv_r <= '0';
elsif rising_edge(clk_i) then
dv_r <= dv_i;
i_token_o <=(others=>'0');
i_wrf <= '0';
fifo_rdempty_r <= fifo_rdempty_s;
case state is
-- wait for First data
when WaitFirstData =>
if dv_i='1' then
i_token_o <= CaphHeader(SoF) & zzero;
i_wrf <='1'; -- write to caph fifo
state <= WaitSoL;
end if;
-- generated start of line
when WaitSoL =>
-- write SoL token
i_token_o <= CaphHeader(SoL) & zzero;
i_wrf <='1'; -- write to caph fifo
--fifo_rdreq_s <= '1'; -- rd 1 clk avant data sur bus
state <= DataValid;
when DataValid =>
-- fifo_rdempty_r fifo_rdempty_s delayed from 1 clk
if (fifo_rdempty_r='0') then
i_token_o <= CaphHeader(Data) & zero & fifo_q_s;
i_wrf<='1';
data_cpt <= data_cpt + 1 ;
end if;
if (data_cpt = to_integer(unsigned(imwidth_i))) then
data_cpt <= 0;
line_cpt <= line_cpt + 1 ;
state <= DumpEoL;
end if;
when DumpEoL =>
i_token_o <= CaphHeader(EoF) & zzero;
i_wrf<='1';
if (line_cpt = to_integer(unsigned(imheight_i))) then
state<=DumpEoF;
line_cpt <= 0;
else
state<=WaitSoL;
end if;
when DumpEoF =>
i_token_o <= CaphHeader(EoF) & zzero;
i_wrf<='1';
state<=WaitFirstData;
end case;
end if;
end process;
token_o <= i_token_o;
wr_fifo_o <= i_wrf;
--with clk_i select
-- wr_fifo_o <= '0' when '0',
-- i_wrf when '1',
-- '0' when others;
--
end architecture;
| gpl-3.0 | e22c626324e55af9bff436153837f977 | 0.599063 | 2.798464 | false | false | false | false |
DreamIP/GPStudio | support/process/dilate/hdl/dilate.vhd | 1 | 6,293 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity dilate is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end dilate;
architecture rtl of dilate is
component dilate_process
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_value : in std_logic_vector(15 downto 0);
di00_reg_m00 : in std_logic_vector(7 downto 0);
di01_reg_m01 : in std_logic_vector(7 downto 0);
di02_reg_m02 : in std_logic_vector(7 downto 0);
di10_reg_m10 : in std_logic_vector(7 downto 0);
di11_reg_m11 : in std_logic_vector(7 downto 0);
di12_reg_m12 : in std_logic_vector(7 downto 0);
di20_reg_m20 : in std_logic_vector(7 downto 0);
di21_reg_m21 : in std_logic_vector(7 downto 0);
di22_reg_m22 : in std_logic_vector(7 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component dilate_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_value : out std_logic_vector(15 downto 0);
di00_reg_m00 : out std_logic_vector(7 downto 0);
di01_reg_m01 : out std_logic_vector(7 downto 0);
di02_reg_m02 : out std_logic_vector(7 downto 0);
di10_reg_m10 : out std_logic_vector(7 downto 0);
di11_reg_m11 : out std_logic_vector(7 downto 0);
di12_reg_m12 : out std_logic_vector(7 downto 0);
di20_reg_m20 : out std_logic_vector(7 downto 0);
di21_reg_m21 : out std_logic_vector(7 downto 0);
di22_reg_m22 : out std_logic_vector(7 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal widthimg_reg_value : std_logic_vector (15 downto 0);
signal di00_reg_m00 : std_logic_vector (7 downto 0);
signal di01_reg_m01 : std_logic_vector (7 downto 0);
signal di02_reg_m02 : std_logic_vector (7 downto 0);
signal di10_reg_m10 : std_logic_vector (7 downto 0);
signal di11_reg_m11 : std_logic_vector (7 downto 0);
signal di12_reg_m12 : std_logic_vector (7 downto 0);
signal di20_reg_m20 : std_logic_vector (7 downto 0);
signal di21_reg_m21 : std_logic_vector (7 downto 0);
signal di22_reg_m22 : std_logic_vector (7 downto 0);
begin
dilate_process_inst : dilate_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_value => widthimg_reg_value,
di00_reg_m00 => di00_reg_m00,
di01_reg_m01 => di01_reg_m01,
di02_reg_m02 => di02_reg_m02,
di10_reg_m10 => di10_reg_m10,
di11_reg_m11 => di11_reg_m11,
di12_reg_m12 => di12_reg_m12,
di20_reg_m20 => di20_reg_m20,
di21_reg_m21 => di21_reg_m21,
di22_reg_m22 => di22_reg_m22,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
dilate_slave_inst : dilate_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_value => widthimg_reg_value,
di00_reg_m00 => di00_reg_m00,
di01_reg_m01 => di01_reg_m01,
di02_reg_m02 => di02_reg_m02,
di10_reg_m10 => di10_reg_m10,
di11_reg_m11 => di11_reg_m11,
di12_reg_m12 => di12_reg_m12,
di20_reg_m20 => di20_reg_m20,
di21_reg_m21 => di21_reg_m21,
di22_reg_m22 => di22_reg_m22,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
| gpl-3.0 | 3a75ef671a224af487747cd1c580fd76 | 0.493246 | 3.016779 | false | false | false | false |
DreamIP/GPStudio | support/process/erode/hdl/erode.vhd | 1 | 6,568 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity erode is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end erode;
architecture rtl of erode is
component erode_process
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_value : in std_logic_vector(15 downto 0);
heigtimg_reg_value : in std_logic_vector(15 downto 0);
er00_reg_m00 : in std_logic_vector(7 downto 0);
er01_reg_m01 : in std_logic_vector(7 downto 0);
er02_reg_m02 : in std_logic_vector(7 downto 0);
er10_reg_m10 : in std_logic_vector(7 downto 0);
er11_reg_m11 : in std_logic_vector(7 downto 0);
er12_reg_m12 : in std_logic_vector(7 downto 0);
er20_reg_m20 : in std_logic_vector(7 downto 0);
er21_reg_m21 : in std_logic_vector(7 downto 0);
er22_reg_m22 : in std_logic_vector(7 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component erode_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_value : out std_logic_vector(15 downto 0);
heigtimg_reg_value : out std_logic_vector(15 downto 0);
er00_reg_m00 : out std_logic_vector(7 downto 0);
er01_reg_m01 : out std_logic_vector(7 downto 0);
er02_reg_m02 : out std_logic_vector(7 downto 0);
er10_reg_m10 : out std_logic_vector(7 downto 0);
er11_reg_m11 : out std_logic_vector(7 downto 0);
er12_reg_m12 : out std_logic_vector(7 downto 0);
er20_reg_m20 : out std_logic_vector(7 downto 0);
er21_reg_m21 : out std_logic_vector(7 downto 0);
er22_reg_m22 : out std_logic_vector(7 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal widthimg_reg_value : std_logic_vector (15 downto 0);
signal heigtimg_reg_value : std_logic_vector (15 downto 0);
signal er00_reg_m00 : std_logic_vector (7 downto 0);
signal er01_reg_m01 : std_logic_vector (7 downto 0);
signal er02_reg_m02 : std_logic_vector (7 downto 0);
signal er10_reg_m10 : std_logic_vector (7 downto 0);
signal er11_reg_m11 : std_logic_vector (7 downto 0);
signal er12_reg_m12 : std_logic_vector (7 downto 0);
signal er20_reg_m20 : std_logic_vector (7 downto 0);
signal er21_reg_m21 : std_logic_vector (7 downto 0);
signal er22_reg_m22 : std_logic_vector (7 downto 0);
begin
erode_process_inst : erode_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_value => widthimg_reg_value,
heigtimg_reg_value => heigtimg_reg_value,
er00_reg_m00 => er00_reg_m00,
er01_reg_m01 => er01_reg_m01,
er02_reg_m02 => er02_reg_m02,
er10_reg_m10 => er10_reg_m10,
er11_reg_m11 => er11_reg_m11,
er12_reg_m12 => er12_reg_m12,
er20_reg_m20 => er20_reg_m20,
er21_reg_m21 => er21_reg_m21,
er22_reg_m22 => er22_reg_m22,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
erode_slave_inst : erode_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_value => widthimg_reg_value,
heigtimg_reg_value => heigtimg_reg_value,
er00_reg_m00 => er00_reg_m00,
er01_reg_m01 => er01_reg_m01,
er02_reg_m02 => er02_reg_m02,
er10_reg_m10 => er10_reg_m10,
er11_reg_m11 => er11_reg_m11,
er12_reg_m12 => er12_reg_m12,
er20_reg_m20 => er20_reg_m20,
er21_reg_m21 => er21_reg_m21,
er22_reg_m22 => er22_reg_m22,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
| gpl-3.0 | 7c5f43eee79b6d5c3515d01d679f6f75 | 0.500457 | 2.989531 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/UDP_MAC_GE.vhd | 1 | 7,887 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity UDP_MAC_GE is
port (
--iRst_n : IN STD_LOGIC;
---------------------------------------------------------------------------
-- RGMII Interface
---------------------------------------------------------------------------
gtx_clk : out std_logic;
tx_en : out std_logic;
tx_data : out std_logic_vector(3 downto 0);
rx_clk : in std_logic;
rx_dv : in std_logic;
rx_data : in std_logic_vector(3 downto 0);
--phy
phy_reset_l : out std_logic;
phy_mdc : out std_logic;
phy_mdio : inout std_logic;
---------------------------------------------------------------------------
-- user Interface
---------------------------------------------------------------------------
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
udp_tx_data_out_ready : out std_logic; -- indicates udp_tx is ready to take data
-- UDP RX signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
CLK_OUT : OUT STD_LOGIC
);
end entity;
architecture rtl of UDP_MAC_GE is
COMPONENT UDP_Complete_nomac
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- UDP TX signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready : out std_logic; -- indicates udp_tx is ready to take data
-- UDP RX signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- IP RX signals
ip_rx_hdr : out ipv4_rx_header_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in udp_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tfirst : in std_logic;
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
END COMPONENT;
COMPONENT gbe_mac
port(
iRst_n : IN STD_LOGIC;
---------------------------------------------------------------------------
-- RGMII Interface
---------------------------------------------------------------------------
ENET1_GTX_CLK : OUT STD_LOGIC;
ENET1_TX_EN : OUT STD_LOGIC;
ENET1_TX_DATA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ENET1_RX_CLK : IN STD_LOGIC;
ENET1_RX_DV : IN STD_LOGIC;
ENET1_RX_DATA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
--PHY
ENET1_PHY_RESET_L : OUT std_logic;
ENET1_PHY_MDC : OUT std_logic;
ENET1_PHY_MDIO : INOUT std_logic;
--TO UDP
iMAC_HAL : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
iUDP_rx_rdy : IN STD_LOGIC;
DATA_VALID_RX_OUT : OUT STD_LOGIC;
DATA_RX_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
SOF_RX_OUT : OUT STD_LOGIC;
EOF_RX_OUT : OUT STD_LOGIC;
DATA_VALID_TX_IN : IN STD_LOGIC;
DATA_TX_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SOF_TX_IN : IN STD_LOGIC;
EOF_TX_IN : IN STD_LOGIC;
MAC_RDY_IN : OUT STD_LOGIC;
CLK_OUT : OUT STD_LOGIC
);
END COMPONENT;
constant MAC_FPGA : std_logic_vector(47 downto 0) := x"11223344AABB";
constant IP_FPGA : std_logic_vector(31 downto 0) := x"AC1B0A05";--172.27.10.5
signal clk_int : std_logic;
signal control_int : udp_control_type;
signal mac_rx_valid_int, mac_sof_rx_int, mac_eof_rx_int, mac_rx_rdy_int : std_logic;
signal mac_rx_data_int : std_logic_vector(7 downto 0);
signal mac_tx_dv_int, mac_tx_ready_int, mac_tx_sof_int, mac_tx_eof_int : std_logic;
signal mac_tx_data_int : std_logic_vector(7 downto 0);
signal count : unsigned(31 downto 0);
signal iRst_n_debounced_int : std_logic;
type state is (idle, s0, s1, s2, s3, s4);
signal state_tx : state;
begin
process(clk_int)
begin
if clk_int'event and clk_int='1' then
if count < x"3D090" then
iRst_n_debounced_int <= '0';
count <= count +1;
else
iRst_n_debounced_int <= '1';
end if;
end if;
end process;
control_int.ip_controls.arp_controls.clear_cache <= '0';
UDP_INST : UDP_Complete_nomac
generic map (
CLOCK_FREQ => 125000000, -- artificially low count to enable pragmatic testing
ARP_TIMEOUT => 20,
ARP_MAX_PKT_TMO => 10, -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES => 255 -- max entries in the ARP store
)
PORT MAP (
udp_tx_start => udp_tx_start,
udp_txi => udp_txi,
udp_tx_result => udp_tx_result,
udp_tx_data_out_ready => udp_tx_data_out_ready,
udp_rx_start => udp_rx_start,
udp_rxo => udp_rxo,
ip_rx_hdr => open,--ip_rx_hdr,
rx_clk => clk_int,
tx_clk => clk_int,
reset => not iRst_n_debounced_int,
our_ip_address => IP_FPGA,
our_mac_address => MAC_FPGA,
control => control_int,
arp_pkt_count => open,--arp_pkt_count,
ip_pkt_count => open,--ip_pkt_count,
mac_tx_tdata => mac_tx_data_int,
mac_tx_tvalid => mac_tx_dv_int,
mac_tx_tready => mac_tx_ready_int,
mac_tx_tfirst => mac_tx_sof_int,
mac_tx_tlast => mac_tx_eof_int,
mac_rx_tdata => mac_rx_data_int,
mac_rx_tvalid => mac_rx_valid_int,
mac_rx_tready => mac_rx_rdy_int,--mac_rx_tready, --TEST
mac_rx_tfirst => mac_sof_rx_int,
mac_rx_tlast => mac_eof_rx_int
);
GBE_MAC_INST : gbe_mac
PORT MAP (
iRst_n => iRst_n_debounced_int,
---------------------------------------------------------------------------
-- RGMII Interface
---------------------------------------------------------------------------
ENET1_GTX_CLK => gtx_clk,
ENET1_TX_EN => tx_en,
ENET1_TX_DATA => tx_data,
ENET1_RX_CLK => rx_clk,
ENET1_RX_DV => rx_dv,
ENET1_RX_DATA => rx_data,
--PHY
ENET1_PHY_RESET_L => phy_reset_l,
ENET1_PHY_MDC => phy_mdc,
ENET1_PHY_MDIO => phy_mdio,
--TO UDP
iMAC_HAL => MAC_FPGA,
iUDP_rx_rdy => mac_rx_rdy_int,
DATA_VALID_RX_OUT => mac_rx_valid_int,
DATA_RX_OUT => mac_rx_data_int,
SOF_RX_OUT => mac_sof_rx_int,
EOF_RX_OUT => mac_eof_rx_int,
DATA_VALID_TX_IN => mac_tx_dv_int,
DATA_TX_IN => mac_tx_data_int,
SOF_TX_IN => mac_tx_sof_int,
EOF_TX_IN => mac_tx_eof_int,
MAC_RDY_IN => mac_tx_ready_int,
CLK_OUT => clk_int
);
CLK_OUT <= clk_int;
end architecture;
| gpl-3.0 | b8e4cfba2872d8ed187831d1184d4c67 | 0.555851 | 2.92003 | false | false | false | false |
hoglet67/ElectronFpga | AtomBusMon/src/MOS6502CpuMon.vhd | 1 | 5,730 | -------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : MOS6502CpuMon.vhd
-- /___/ /\ Timestamp : 03/11/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: MOS6502CpuMon
--Device: multiple
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MOS6502CpuMon is
generic (
UseT65Core : boolean;
UseAlanDCore : boolean;
ClkMult : integer;
ClkDiv : integer;
ClkPer : real;
num_comparators : integer;
avr_prog_mem_size : integer
);
port (
clock : in std_logic;
-- 6502 Signals
Phi0 : in std_logic;
Phi1 : out std_logic;
Phi2 : out std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
Sync : out std_logic;
Addr : out std_logic_vector(15 downto 0);
R_W_n : out std_logic;
Data : inout std_logic_vector(7 downto 0);
SO_n : in std_logic;
Res_n : in std_logic;
Rdy : in std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- Jumpers
fakeTube_n : in std_logic;
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- Switches
sw_reset_cpu : in std_logic;
sw_reset_avr : in std_logic;
-- LEDs
led_bkpt : out std_logic;
led_trig0 : out std_logic;
led_trig1 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic
);
end MOS6502CpuMon;
architecture behavioral of MOS6502CpuMon is
signal clock_avr : std_logic;
signal Din : std_logic_vector(7 downto 0);
signal Dout : std_logic_vector(7 downto 0);
signal Rdy_latched : std_logic;
signal IRQ_n_sync : std_logic;
signal NMI_n_sync : std_logic;
signal Addr_int : std_logic_vector(15 downto 0);
signal R_W_n_int : std_logic;
signal Phi0_a : std_logic;
signal Phi0_b : std_logic;
signal Phi0_c : std_logic;
signal Phi0_d : std_logic;
signal cpu_clk : std_logic;
signal busmon_clk : std_logic;
begin
inst_dcm0 : entity work.DCM0
generic map (
ClkMult => ClkMult,
ClkDiv => ClkDiv,
ClkPer => ClkPer
)
port map(
CLKIN_IN => clock,
CLKFX_OUT => clock_avr
);
core : entity work.MOS6502CpuMonCore
generic map (
UseT65Core => UseT65Core,
UseAlanDCore => UseAlanDCore,
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
clock_avr => clock_avr,
busmon_clk => busmon_clk,
busmon_clken => '1',
cpu_clk => cpu_clk,
cpu_clken => '1',
IRQ_n => IRQ_n_sync,
NMI_n => NMI_n_sync,
Sync => Sync,
Addr => Addr_int,
R_W_n => R_W_n_int,
Din => Din,
Dout => Dout,
SO_n => SO_n,
Res_n => Res_n,
Rdy => Rdy_latched,
trig => trig,
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk
);
sync_gen : process(cpu_clk)
begin
if rising_edge(cpu_clk) then
NMI_n_sync <= NMI_n;
IRQ_n_sync <= IRQ_n;
end if;
end process;
-- 6502: Sample Rdy on the rising edge of Phi0
rdy_6502: if UseT65Core generate
process(Phi0)
begin
if rising_edge(Phi0) then
Rdy_latched <= Rdy;
end if;
end process;
end generate;
-- 65C02: Sample Rdy on the falling edge of Phi0
rdy_65c02: if UseAlanDCore generate
process(Phi0)
begin
if falling_edge(Phi0) then
Rdy_latched <= Rdy;
end if;
end process;
end generate;
-- Sample Data on the falling edge of Phi0_a
data_latch : process(Phi0_a)
begin
if falling_edge(Phi0_a) then
if (fakeTube_n = '0' and Addr_int = x"FEE0") then
Din <= x"FE";
else
Din <= Data;
end if;
end if;
end process;
Data <= Dout when Phi0_c = '1' and R_W_n_int = '0' else (others => 'Z');
R_W_n <= R_W_n_int;
Addr <= Addr_int;
clk_gen : process(clock)
begin
if rising_edge(clock) then
Phi0_a <= Phi0;
Phi0_b <= Phi0_a;
Phi0_c <= Phi0_b;
Phi0_d <= Phi0_c;
end if;
end process;
Phi1 <= not Phi0_b;
Phi2 <= Phi0_b;
cpu_clk <= not Phi0_d;
busmon_clk <= Phi0_d;
end behavioral;
| gpl-3.0 | 5208ae63d5070cece0fd2281dee3ad50 | 0.443455 | 3.696774 | false | false | false | false |
DreamIP/GPStudio | support/io/gps/hdl/gps_clkgen.vhd | 1 | 1,241 | --------------------------------------------------------
-- This bloc generates the baud counter which is used by
-- the receiver and the transmitter to synchronize data
-- with the GPS baud rate.
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clk_gen is
port (
clk_50M : in std_logic;
reset : in std_logic;
enable : in std_logic;
count_max : in unsigned(15 downto 0);
count_bd : out unsigned(15 downto 0);
rst_count_bd : in std_logic
);
end clk_gen;
architecture RTL of clk_gen is
signal count_bd_s : unsigned(15 downto 0);
signal rst_count_bd_dl : std_logic;
begin
process(clk_50M,reset)
begin
if reset='0' then
count_bd_s <= x"0000";
elsif clk_50M'event and clk_50M='1'then
if enable='1' then
rst_count_bd_dl <= rst_count_bd;
if (rst_count_bd='1' and rst_count_bd_dl='0') or count_bd_s=count_max then ----- Reset the counter only when it reaches the max count defined by baud rate
count_bd_s <= x"0000"; ----- or when a reset is asked by UART blocks
else
count_bd_s <= count_bd_s +1;
end if;
end if;
end if;
end process;
count_bd<= count_bd_s;
end RTL;
| gpl-3.0 | e34b557ec98e5cd7a9a1c0e3e7d98ee2 | 0.588235 | 3.004843 | false | false | false | false |
DreamIP/GPStudio | support/process/scharr/hdl/scharr_slave.vhd | 1 | 3,043 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity scharr_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end scharr_slave;
architecture rtl of scharr_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant WIDTHIMG_REG_REG_ADDR : natural := 1;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal widthimg_reg_width_reg : std_logic_vector (15 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
widthimg_reg_width_reg <= "0000000000000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
status_reg_enable_bit_reg <= datawr_i(0);
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
widthimg_reg_width_reg <= datawr_i(15) & datawr_i(14) & datawr_i(13) & datawr_i(12) & datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000000000000000000" & status_reg_enable_bit_reg;
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000" & widthimg_reg_width_reg(15) & widthimg_reg_width_reg(14) & widthimg_reg_width_reg(13) & widthimg_reg_width_reg(12) & widthimg_reg_width_reg(11) & widthimg_reg_width_reg(10) & widthimg_reg_width_reg(9) & widthimg_reg_width_reg(8) & widthimg_reg_width_reg(7) & widthimg_reg_width_reg(6) & widthimg_reg_width_reg(5) & widthimg_reg_width_reg(4) & widthimg_reg_width_reg(3) & widthimg_reg_width_reg(2) & widthimg_reg_width_reg(1) & widthimg_reg_width_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
widthimg_reg_width <= widthimg_reg_width_reg;
end rtl;
| gpl-3.0 | 22334a3f4b08bc3daedaf8f9a0aba2e3 | 0.593493 | 2.868049 | false | false | false | false |
DreamIP/GPStudio | support/process/prewitt/hdl/prewitt_process.vhd | 1 | 5,148 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity prewitt_process is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer;
WEIGHT_SIZE : integer := 8
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_width : in std_logic_vector(15 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end prewitt_process;
architecture rtl of prewitt_process is
component matrix_extractor
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer;
OUTVALUE_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
------------------------ matrix out ---------------------
p00, p01, p02 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p10, p11, p12 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p20, p21, p22 : out std_logic_vector((PIX_WIDTH-1) downto 0);
matrix_dv : out std_logic;
---------------------- computed value -------------------
value_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
value_dv : in std_logic;
------------------------- params ------------------------
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0)
);
end component;
-- neighbors extraction
signal p00, p01, p02 : std_logic_vector((IN_SIZE-1) downto 0);
signal p10, p11, p12 : std_logic_vector((IN_SIZE-1) downto 0);
signal p20, p21, p22 : std_logic_vector((IN_SIZE-1) downto 0);
signal matrix_dv : std_logic;
-- products calculation
signal prod00, prod01, prod02 : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
signal prod10, prod11, prod12 : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
signal prod20, prod21, prod22 : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
signal prod_dv : std_logic;
signal value_data : std_logic_vector((IN_SIZE-1) downto 0);
signal value_dv : std_logic;
signal out_fv_s : std_logic;
signal enable_s : std_logic;
begin
matrix_extractor_inst : matrix_extractor
generic map (
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
PIX_WIDTH => IN_SIZE,
OUTVALUE_WIDTH => IN_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
p00 => p00, p01 => p01, p02 => p02,
p10 => p10, p11 => p11, p12 => p12,
p20 => p20, p21 => p21, p22 => p22,
matrix_dv => matrix_dv,
value_data => value_data,
value_dv => value_dv,
out_data => out_data,
out_fv => out_fv_s,
out_dv => out_dv,
enable_i => status_reg_enable_bit,
widthimg_i => widthimg_reg_width
);
process (clk_proc, reset_n, matrix_dv)
variable sum : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
begin
if(reset_n='0') then
enable_s <= '0';
prod_dv <= '0';
value_dv <= '0';
elsif(rising_edge(clk_proc)) then
if(in_fv = '0') then
enable_s <= status_reg_enable_bit;
prod_dv <= '0';
value_dv <= '0';
end if;
prod_dv <= '0';
if(matrix_dv = '1' and enable_s = '1') then
prod00 <= "11111110" * signed('0' & p00);
prod01 <= "11111111" * signed('0' & p01);
prod02 <= "00000000" * signed('0' & p02);
prod10 <= "11111111" * signed('0' & p10);
prod11 <= "00000000" * signed('0' & p11);
prod12 <= "00000001" * signed('0' & p12);
prod20 <= "00000000" * signed('0' & p20);
prod21 <= "00000001" * signed('0' & p21);
prod22 <= "00000010" * signed('0' & p22);
prod_dv <= '1';
end if;
value_dv <= '0';
if(prod_dv='1' and enable_s = '1') then
sum := prod00 + prod01 + prod02 +
prod10 + prod11 + prod12 +
prod20 + prod21 + prod22;
if (sum(sum'left) = '1') then
sum := (others => '0');
end if;
value_data <= std_logic_vector(sum)(OUT_SIZE -1 downto 0);
value_dv <= '1';
end if;
end if;
end process;
out_fv <= enable_s and out_fv_s;
end rtl;
| gpl-3.0 | 6507a3072f6e329e07a41ce3e8539583 | 0.497863 | 3.173859 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/xilinx/hostinterface/src/axi_hostinterface-rtl-ea.vhd | 3 | 35,174 | -------------------------------------------------------------------------------
--! @file axi_hostinterface.vhd
--
--! @brief toplevel of host interface for Xilinx FPGA
--
--! @details This toplevel interfaces to Xilinx specific implementation.
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014, B&R Industrial Automation GmbH
-- Copyright (c) 2014, Kalycito Infotech Private Limited
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--! Use standard ieee library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Use work library
library work;
--! Common library
library libcommon;
--! Use global library
use libcommon.global.all;
entity axi_hostinterface is
generic (
--! PCP AXI Slave Data Width
C_S_AXI_PCP_DATA_WIDTH : integer := 32;
--! PCP AXI Slave Address width
C_S_AXI_PCP_ADDR_WIDTH : integer := 32;
--! PCP AXI Min Address range size (64Kb limited by scripts)
C_S_AXI_PCP_MIN_SIZE : std_logic_vector := X"0001FFFF";
--! PCP AXI Slave Base Address
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
--! PCP AXI Slave High Address
C_HIGHADDR : std_logic_vector := X"00000000";
--! PCP AXI IP Family
C_FAMILY : string := "virtex6";
--! Host AXI Slave Data Width
C_S_AXI_HOST_DATA_WIDTH : integer := 32;
--! Host AXI Address Width
C_S_AXI_HOST_ADDR_WIDTH : integer := 32;
--! HOST AXI Min Address range size
C_S_AXI_HOST_MIN_SIZE : std_logic_vector := X"0001FFFF";
--! HOST AXI Slave Base Address
C_HOST_BASEADDR : std_logic_vector := X"FFFFFFFF";
--! HOST AXI Slave High Address
C_HOST_HIGHADDR : std_logic_vector := X"00000000";
--! HOST AXI IP Family
C_HOST_FAMILY : string := "virtex6";
--! Master Bridge Address Width
C_M_AXI_ADDR_WIDTH : integer := 32;
--! Master Bridge Data Width
C_M_AXI_DATA_WIDTH : integer := 32;
--! Host Interface Version major
gVersionMajor : natural := 16#FF#;
--! Host Interface Version minor
gVersionMinor : natural := 16#FF#;
--! Host Interface Version revision
gVersionRevision : natural := 16#FF#;
--! Host Interface Version count
gVersionCount : natural := 0;
--! Host Interface Base address Dynamic Buffer 0
gBaseDynBuf0 : natural := 16#00800#;
--! Host Interface Base address Dynamic Buffer 1
gBaseDynBuf1 : natural := 16#01000#;
--! Host Interface Base address Error Counter
gBaseErrCntr : natural := 16#01800#;
--! Host Interface Base address TX NMT Queue
gBaseTxNmtQ : natural := 16#02800#;
--! Host Interface Base address TX Generic Queue
gBaseTxGenQ : natural := 16#03800#;
--! Host Interface Base address TX SyncRequest Queue
gBaseTxSynQ : natural := 16#04800#;
--! Host Interface Base address TX Virtual Ethernet Queue
gBaseTxVetQ : natural := 16#05800#;
--! Host Interface Base address RX Virtual Ethernet Queue
gBaseRxVetQ : natural := 16#06800#;
--! Host Interface Base address Kernel-to-User Queue
gBaseK2UQ : natural := 16#07000#;
--! Host Interface Base address User-to-Kernel Queue
gBaseU2KQ : natural := 16#09000#;
--! Host Interface Base address Pdo
gBasePdo : natural := 16#0B000#;
--! Base address Timesync
gBaseTimeSync : natural := 16#0E000#;
--! Host Interface Base address Reserved (-1 = high address of Timesync)
gBaseRes : natural := 16#0E400#;
--! Select Host Interface Type (0 = Avalon, 1 = Parallel)
gHostIfType : natural := 0;
--! Data width of parallel interface (16/32)
gParallelDataWidth : natural := 16;
--! Address and Data bus are multiplexed (0 = FALSE, otherwise = TRUE)
gParallelMultiplex : natural := 0
);
port (
--! AXI PCP slave PCP clock
S_AXI_PCP_ACLK : in std_logic;
--! AXI PCP slave PCP Reset Active low
S_AXI_PCP_ARESETN : in std_logic;
--! AXI PCP slave PCP Address
S_AXI_PCP_AWADDR : in std_logic_vector(C_S_AXI_PCP_ADDR_WIDTH-1 downto 0);
--! AXI PCP slave PCP Address Valid
S_AXI_PCP_AWVALID : in std_logic;
--! AXI PCP slave Write Data
S_AXI_PCP_WDATA : in std_logic_vector(C_S_AXI_PCP_DATA_WIDTH-1 downto 0);
--! AXI PCP slave Write Strobe
S_AXI_PCP_WSTRB : in std_logic_vector((C_S_AXI_PCP_DATA_WIDTH/8)-1 downto 0);
--! AXI PCP slave Write Valid
S_AXI_PCP_WVALID : in std_logic;
--! AXI PCP slave Write Response Ready
S_AXI_PCP_BREADY : in std_logic;
--! AXI PCP slave Write Response Valid
S_AXI_PCP_BVALID : out std_logic;
--! AXI PCP slave Write Response
S_AXI_PCP_BRESP : out std_logic_vector(1 downto 0);
--! AXI PCP slave Read Address
S_AXI_PCP_ARADDR : in std_logic_vector(C_S_AXI_PCP_ADDR_WIDTH-1 downto 0);
--! AXI PCP slave Address Valid
S_AXI_PCP_ARVALID : in std_logic;
--! AXI PCP slave Read Ready
S_AXI_PCP_RREADY : in std_logic;
--! AXI PCP slave Read Address Ready
S_AXI_PCP_ARREADY : out std_logic;
--! AXI PCP slave Read Data
S_AXI_PCP_RDATA : out std_logic_vector(C_S_AXI_PCP_DATA_WIDTH-1 downto 0);
--! AXI PCP slave Read Response
S_AXI_PCP_RRESP : out std_logic_vector(1 downto 0);
--! AXI PCP slave Read Valid
S_AXI_PCP_RVALID : out std_logic;
--! AXI PCP slave Write ready
S_AXI_PCP_WREADY : out std_logic;
--! AXI PCP slave Write Address Ready
S_AXI_PCP_AWREADY : out std_logic;
-- Host Interface AXI
--! AXI Host Slave Clock
S_AXI_HOST_ACLK : in std_logic;
--! AXI Host Slave Reset active low
S_AXI_HOST_ARESETN : in std_logic;
--! AXI Host Slave Write Address
S_AXI_HOST_AWADDR : in std_logic_vector(C_S_AXI_HOST_ADDR_WIDTH-1 downto 0);
--! AXI Host Slave Write Address valid
S_AXI_HOST_AWVALID : in std_logic;
--! AXI Host Slave Write Data
S_AXI_HOST_WDATA : in std_logic_vector(C_S_AXI_HOST_DATA_WIDTH-1 downto 0);
--! AXI Host Slave Write strobe
S_AXI_HOST_WSTRB : in std_logic_vector((C_S_AXI_HOST_DATA_WIDTH/8)-1 downto 0);
--! AXI Host Slave write Valid
S_AXI_HOST_WVALID : in std_logic;
--! AXI Host Slave Response Ready
S_AXI_HOST_BREADY : in std_logic;
--! AXI Host Slave Read Address
S_AXI_HOST_ARADDR : in std_logic_vector(C_S_AXI_HOST_ADDR_WIDTH-1 downto 0);
--! AXI Host Slave Read Address Valid
S_AXI_HOST_ARVALID : in std_logic;
--! AXI Host Slave Read Ready
S_AXI_HOST_RREADY : in std_logic;
--! AXI Host Slave Read Address Ready
S_AXI_HOST_ARREADY : out std_logic;
--! AXI Host SlaveRead Data
S_AXI_HOST_RDATA : out std_logic_vector(C_S_AXI_HOST_DATA_WIDTH-1 downto 0);
--! AXI Host Slave Read Response
S_AXI_HOST_RRESP : out std_logic_vector(1 downto 0);
--! AXI Host Slave Read Valid
S_AXI_HOST_RVALID : out std_logic;
--! AXI Host Slave Write Ready
S_AXI_HOST_WREADY : out std_logic;
--! AXI Host Slave Write Response
S_AXI_HOST_BRESP : out std_logic_vector(1 downto 0);
--! AXI Host Slave Write Response Valid
S_AXI_HOST_BVALID : out std_logic;
--! AXI Host Slave Write Address Ready
S_AXI_HOST_AWREADY : out std_logic;
-- Master Bridge Ports
--! AXI Bridge Master Clock
M_AXI_ACLK : in std_logic;
--! AXI Bridge Master Reset Active low
M_AXI_ARESETN : in std_logic;
--! AXI Bridge Master Write Address
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
--! AXI Bridge Master Write Address Write protection
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
--! AXI Bridge Master Write Address Valid
M_AXI_AWVALID : out std_logic;
--! AXI Bridge Master Write Ready
M_AXI_AWREADY : in std_logic;
--! AXI Bridge Master Write Data
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
--! AXI Bridge Master Write Strobe
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
--! AXI Bridge Master Write Valid
M_AXI_WVALID : out std_logic;
--! AXI Bridge Master Write Last to support AXI4 feature
M_AXI_WLAST : out std_logic;
--! AXI Bridge Master Write Ready
M_AXI_WREADY : in std_logic;
--! AXI Bridge Master Response
M_AXI_BRESP : in std_logic_vector(1 downto 0);
--! AXI Bridge Master Response Valid
M_AXI_BVALID : in std_logic;
--! AXI Bridge Master Response Ready
M_AXI_BREADY : out std_logic;
--! AXI Bridge Master Read Address
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
--! AXI Bridge Master Read Protection
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
--! AXI Bridge Master Read Address Valid
M_AXI_ARVALID : out std_logic;
--! AXI Bridge Master Read Address Ready
M_AXI_ARREADY : in std_logic;
--! AXI Bridge Master Read Data
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
--! AXI Bridge Master Read Response
M_AXI_RRESP : in std_logic_vector(1 downto 0);
--! AXI Bridge Master Read Valid
M_AXI_RVALID : in std_logic;
--! AXI Bridge Master Read Ready
M_AXI_RREADY : out std_logic;
-- Misc ports
--! HostInterface Interrupt receiver
irqSync_irq : in std_logic;
--! HostInterface Interrupt sender
irqOut_irq : out std_logic;
--! External Sync Source
iExtSync_exsync : in std_logic;
-- Parallel Host Interface
--! Parallel Interface Chip select
iParHost_chipselect : in std_logic;
--! Parallel Interface Read Signal
iParHost_read : in std_logic;
--! Parallel Interface Write Signal
iParHost_write : in std_logic;
--! Parallel Interface Address Latch enable (Multiplexed only)
iParHost_addressLatchEnable : in std_logic;
--! Parallel Interface High active Acknowledge
oParHost_acknowledge : out std_logic;
--! Parallel Interface Byte enables
iParHost_byteenable : in std_logic_vector(gParallelDataWidth/8-1 downto 0);
--! Parallel Interface Address bus (De-multiplexed, word-address)
iParHost_address : in std_logic_vector(15 downto 0);
-- Data bus IO
--! Parallel Interface Data bus input (De-multiplexed)
iParHost_data_io : in std_logic_vector(gParallelDataWidth-1 downto 0);
--! Parallel Interface Data bus output (De-multiplexed)
oParHost_data_io : out std_logic_vector(gParallelDataWidth-1 downto 0);
--! Parallel Interface Data bus tri-state enable (De-multiplexed)
oParHost_data_io_tri : out std_logic;
-- Address/data bus IO
--! Parallel Interface Address/Data bus input (Multiplexed, word-address))
iParHost_addressData_io : in std_logic_vector(gParallelDataWidth-1 downto 0);
--! Parallel Interface Address/Data bus output (Multiplexed, word-address))
oParHost_addressData_io : out std_logic_vector(gParallelDataWidth-1 downto 0);
--! Parallel Interface Address/Data bus tri-state Enable(Multiplexed, word-address))
oParHost_addressData_tri : out std_logic
);
--! Declaration for Maximum Fan out attribute
attribute MAX_FANOUT : string;
--! Declaration for Class of special signals
attribute SIGIS : string;
--! Maximum fan out for PCP clock
attribute MAX_FANOUT of S_AXI_PCP_ACLK : signal is "10000";
--! Maximum fan out for PCP Reset
attribute MAX_FANOUT of S_AXI_PCP_ARESETN : signal is "10000";
--! PCP clock is declared under clock group
attribute SIGIS of S_AXI_PCP_ACLK : signal is "Clk";
--! PCP Reset is declared under Reset group
attribute SIGIS of S_AXI_PCP_ARESETN : signal is "Rst";
--! Maximum fan out for Host clock
attribute MAX_FANOUT of S_AXI_HOST_ACLK : signal is "10000";
--! Maximum fan out for Host Reset
attribute MAX_FANOUT of S_AXI_HOST_ARESETN : signal is "10000";
--! Host clock is declared under clock group
attribute SIGIS of S_AXI_HOST_ACLK : signal is "Clk";
--! Host Reset is declared under Reset group
attribute SIGIS of S_AXI_HOST_ARESETN : signal is "Rst";
--! Maximum fan out for Bridge clock
attribute MAX_FANOUT of M_AXI_ACLK : signal is "10000";
--! Maximum fan out for Bridge Reset
attribute MAX_FANOUT of M_AXI_ARESETN : signal is "10000";
--! Bridge clock is declared under clock group
attribute SIGIS of M_AXI_ACLK : signal is "Clk";
--! Bridge Reset is declared under Reset group
attribute SIGIS of M_AXI_ARESETN : signal is "Rst";
end entity axi_hostinterface;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture rtl of axi_hostinterface is
--! Use memory blocks or registers for translation address storage (registers = 0, memory blocks /= 0)
constant cBridgeUseMemBlock : natural := cTrue;
--TODO: Export Non-secure transitions signals to top level
--! Non-secure Write signal for PCP Slave interface
signal S_AXI_PCP_AWPROT : std_logic_vector(2 downto 0);
--! Non-secure Read signal for PCP Slave interface
signal S_AXI_PCP_ARPROT : std_logic_vector(2 downto 0);
--! Non-secure Write signal for Host Slave Interface
signal S_AXI_HOST_AWPROT : std_logic_vector(2 downto 0);
--! Non-Secure Read signal for Host Slave interface
signal S_AXI_HOST_ARPROT : std_logic_vector(2 downto 0);
--Signals for wrapper to PCP Host Interface
--! Avalon slave Address for PCP
signal AvsPcpAddress : std_logic_vector(31 downto 0);
--! Avalon slave byte enable for PCP
signal AvsPcpByteenable : std_logic_vector(3 downto 0);
--! Avalon slave Read signal for PCP
signal AvsPcpRead : std_logic;
--! Avalon slave Write signal for PCP
signal AvsPcpWrite : std_logic;
--! Avalon slave Write Data for PCP
signal AvsPcpWritedata : std_logic_vector(31 downto 0);
--! Avalon slave Read Data for PCP
signal AvsPcpReaddata : std_logic_vector(31 downto 0);
--! Avalon slave wait request for PCP
signal AvsPcpWaitrequest : std_logic;
-- Avalon Master Bridge signals to AXI master
--! Avalon master Address for Bridge Interface
signal avm_hostBridge_address : std_logic_vector(29 downto 0);
--! Avalon master Byte Enable for Bridge Interface
signal avm_hostBridge_byteenable : std_logic_vector(3 downto 0);
--! Avalon master Read signal for Bridge Interface
signal avm_hostBridge_read : std_logic;
--! Avalon master Read Data signal for Bridge Interface
signal avm_hostBridge_readdata : std_logic_vector(31 downto 0);
--! Avalon master write signal for Bridge Interface
signal avm_hostBridge_write : std_logic;
--! Avalon master write data for Bridge Interface
signal avm_hostBridge_writedata : std_logic_vector(31 downto 0);
--! Avalon master wait request for Bridge Interface
signal avm_hostBridge_waitrequest : std_logic;
-- Host Interface Internal Bus (For Internal Host Processor)
--! Avalon slave Address for Host processor
signal AvsHostAddress : std_logic_vector(31 downto 0);
--! Avalon slave Byte enable for Host processor
signal AvsHostByteenable : std_logic_vector(3 downto 0);
--! Avalon slave Read signal for Host processor
signal AvsHostRead : std_logic;
--! Avalon slave Write signal for Host processor
signal AvsHostWrite : std_logic;
--! Avalon slave write data for Host processor
signal AvsHostWritedata : std_logic_vector(31 downto 0);
--! Avalon slave Read data for Host processor
signal AvsHostReaddata : std_logic_vector(31 downto 0);
--! Avalon Slave wait request for Host Processor
signal AvsHostWaitrequest : std_logic;
-- Common signals used for different host source (internal/External)
--! Host Processor (External/Internal) Address
signal host_address : std_logic_vector(16 downto 2);
--! Host Processor (External/Internal) Byte enable
signal host_byteenable : std_logic_vector(3 downto 0);
--! Host Processor (External/Internal) Read signal
signal host_Read : std_logic;
--! Host Processor (External/Internal) Read Data
signal host_readdata : std_logic_vector(31 downto 0);
--! Host Processor (External/Internal) write signal
signal host_write : std_logic;
--! Host Processor (External/Internal) write data
signal host_writedata : std_logic_vector(31 downto 0);
--! Host Processor (External/Internal) wait request
signal host_waitrequest : std_logic;
--! Clock signal for host interface and axi-wrappers
signal hostif_clock : std_logic;
--! Active high Reset for host interface
signal hostif_reset : std_logic;
--! Word aligned address for Bridge signal
signal AxiLiteBridgeAddress : std_logic_vector(31 downto 0);
begin
-- clock signal host interface IP core
hostif_clock <= S_AXI_PCP_ACLK;
-- Active high for rest for Host interface IP core
hostif_reset <= not S_AXI_PCP_ARESETN;
---------------------------------------------------------------------------
-- Host Interface IP
---------------------------------------------------------------------------
--! The Host Interface IP core
theHostInterface: entity work.hostInterface
generic map (
gVersionMajor => gVersionMajor,
gVersionMinor => gVersionMinor,
gVersionRevision => gVersionRevision,
gVersionCount => gVersionCount,
gBridgeUseMemBlock => cBridgeUseMemBlock,
gBaseDynBuf0 => gBaseDynBuf0,
gBaseDynBuf1 => gBaseDynBuf1,
gBaseErrCntr => gBaseErrCntr,
gBaseTxNmtQ => gBaseTxNmtQ,
gBaseTxGenQ => gBaseTxGenQ,
gBaseTxSynQ => gBaseTxSynQ,
gBaseTxVetQ => gBaseTxVetQ,
gBaseRxVetQ => gBaseRxVetQ,
gBaseK2UQ => gBaseK2UQ,
gBaseU2KQ => gBaseU2KQ,
gBasePdo => gBasePdo,
gBaseTimeSync => gBaseTimeSync,
gBaseRes => gBaseRes,
--FIXME: Assign address width depending on memory span!
gHostAddrWidth => host_address'left+1
)
port map (
iClk => hostif_clock,
iRst => hostif_reset,
iHostAddress => host_address,
iHostByteenable => host_byteenable,
iHostRead => host_Read,
oHostReaddata => host_readdata,
iHostWrite => host_write,
iHostWritedata => host_writedata,
oHostWaitrequest => host_waitrequest,
iPcpAddress => AvsPcpAddress(10 downto 2),
iPcpByteenable => AvsPcpByteenable,
iPcpRead => AvsPcpRead,
oPcpReaddata => AvsPcpReaddata,
iPcpWrite => AvsPcpWrite,
iPcpWritedata => AvsPcpWritedata,
oPcpWaitrequest => AvsPcpWaitrequest,
oHostBridgeAddress => avm_hostBridge_address,
oHostBridgeByteenable => avm_hostBridge_byteenable,
oHostBridgeRead => avm_hostBridge_read,
iHostBridgeReaddata => avm_hostBridge_readdata,
oHostBridgeWrite => avm_hostBridge_write,
oHostBridgeWritedata => avm_hostBridge_writedata,
iHostBridgeWaitrequest => avm_hostBridge_waitrequest,
iIrqIntSync => irqSync_irq,
iIrqExtSync => iExtSync_exsync,
oIrq => irqOut_irq
);
---------------------------------------------------------------------------
-- PCP AXI-lite Slave Interface Wrapper
---------------------------------------------------------------------------
--! AXI-lite slave wrapper for PCP interface of HostinterfaceIP core
AXI_LITE_SLAVE_PCP: entity work.axiLiteSlaveWrapper
generic map (
gBaseAddr => C_BASEADDR,
gHighAddr => C_HIGHADDR,
gAddrWidth => 32,
gDataWidth => 32
)
port map (
-- System Signals
iAclk => S_AXI_PCP_ACLK,
inAReset => S_AXI_PCP_ARESETN,
-- Slave Interface Write Address Ports
iAwaddr => S_AXI_PCP_AWADDR,
iAwprot => S_AXI_PCP_AWPROT,
iAwvalid => S_AXI_PCP_AWVALID,
oAwready => S_AXI_PCP_AWREADY,
-- Slave Interface Write Data Ports
iWdata => S_AXI_PCP_WDATA,
iWstrb => S_AXI_PCP_WSTRB,
iWvalid => S_AXI_PCP_WVALID,
oWready => S_AXI_PCP_WREADY,
-- Slave Interface Write Response Ports
oBresp => S_AXI_PCP_BRESP,
oBvalid => S_AXI_PCP_BVALID,
iBready => S_AXI_PCP_BREADY,
-- Slave Interface Read Address Ports
iAraddr => S_AXI_PCP_ARADDR,
iArprot => S_AXI_PCP_ARPROT,
iArvalid => S_AXI_PCP_ARVALID,
oArready => S_AXI_PCP_ARREADY,
-- Slave Interface Read Data Ports
oRdata => S_AXI_PCP_RDATA,
oRresp => S_AXI_PCP_RRESP,
oRvalid => S_AXI_PCP_RVALID,
iRready => S_AXI_PCP_RREADY,
--Avalon Interface
oAvsAddress => AvsPcpAddress,
oAvsByteenable => AvsPcpByteenable,
oAvsRead => AvsPcpRead,
oAvsWrite => AvsPcpWrite,
oAvsWritedata => AvsPcpWritedata,
iAvsReaddata => AvsPcpReaddata,
iAvsWaitrequest => AvsPcpWaitrequest
);
---------------------------------------------------------------------------
-- Bridge AXI-lite Master Interface Wrapper
---------------------------------------------------------------------------
--! AXI-Lite Master Wrapper for Memory Interface of HostinterfaceIP Core
AXI_LITE_MASTER_BRIDGE: entity work.axiLiteMasterWrapper
generic map (
gAddrWidth => C_M_AXI_ADDR_WIDTH,
gDataWidth => C_M_AXI_DATA_WIDTH
)
port map (
-- System Signals
iAclk => M_AXI_ACLK,
inAReset => M_AXI_ARESETN,
-- Master Interface Write Address
oAwaddr => M_AXI_AWADDR,
oAwprot => M_AXI_AWPROT,
oAwvalid => M_AXI_AWVALID,
iAwready => M_AXI_AWREADY,
-- Master Interface Write Data
oWdata => M_AXI_WDATA,
oWstrb => M_AXI_WSTRB,
oWvalid => M_AXI_WVALID,
iWready => M_AXI_WREADY,
oWlast => M_AXI_WLAST,
-- Master Interface Write Response
iBresp => M_AXI_BRESP,
iBvalid => M_AXI_BVALID,
oBready => M_AXI_BREADY,
-- Master Interface Read Address
oAraddr => M_AXI_ARADDR,
oArprot => M_AXI_ARPROT,
oArvalid => M_AXI_ARVALID,
iArready => M_AXI_ARREADY,
-- Master Interface Read Data
iRdata => M_AXI_RDATA,
iRresp => M_AXI_RRESP,
iRvalid => M_AXI_RVALID,
oRready => M_AXI_RREADY,
-- Avalon master
iAvalonClk => hostif_clock,
iAvalonReset => hostif_reset,
iAvalonRead => avm_hostBridge_read,
iAvalonWrite => avm_hostBridge_write,
iAvalonAddr => AxiLiteBridgeAddress,
iAvalonBE => avm_hostBridge_byteenable,
oAvalonWaitReq => avm_hostBridge_waitrequest,
oAvalonReadValid => open,
oAvalonReadData => avm_hostBridge_readdata,
iAvalonWriteData => avm_hostBridge_writedata
);
--TODO: Try to use full memory range, now its allowed only up to 0x3FFFFFFF
--Convert 30bit address from Avalon master to 32 bit for AXI
AxiLiteBridgeAddress <= "00" & avm_hostBridge_address;
---------------------------------------------------------------------------
-- HOST AXI-lite Slave Interface Wrapper
---------------------------------------------------------------------------
-- Generate AXI-lite slave Interface for Internal Processor Interface
genAxiHost : if gHostIfType = 0 generate
begin
--! AXI-lite slave wrapper for internal processor
AXI_LITE_SLAVE_HOST: entity work.axiLiteSlaveWrapper
generic map (
gBaseAddr => C_HOST_BASEADDR,
gHighAddr => C_HOST_HIGHADDR,
gAddrWidth => 32,
gDataWidth => 32
)
port map (
-- System Signals
iAclk => S_AXI_HOST_ACLK,
inAReset => S_AXI_HOST_ARESETN,
-- Slave Interface Write Address Ports
iAwaddr => S_AXI_HOST_AWADDR,
iAwprot => S_AXI_HOST_AWPROT,
iAwvalid => S_AXI_HOST_AWVALID,
oAwready => S_AXI_HOST_AWREADY,
-- Slave Interface Write Data Ports
iWdata => S_AXI_HOST_WDATA,
iWstrb => S_AXI_HOST_WSTRB,
iWvalid => S_AXI_HOST_WVALID,
oWready => S_AXI_HOST_WREADY,
-- Slave Interface Write Response Ports
oBresp => S_AXI_HOST_BRESP,
oBvalid => S_AXI_HOST_BVALID,
iBready => S_AXI_HOST_BREADY,
-- Slave Interface Read Address Ports
iAraddr => S_AXI_HOST_ARADDR,
iArprot => S_AXI_HOST_ARPROT,
iArvalid => S_AXI_HOST_ARVALID,
oArready => S_AXI_HOST_ARREADY,
-- Slave Interface Read Data Ports
oRdata => S_AXI_HOST_RDATA,
oRresp => S_AXI_HOST_RRESP,
oRvalid => S_AXI_HOST_RVALID,
iRready => S_AXI_HOST_RREADY,
--Avalon Interface
oAvsAddress => AvsHostAddress,
oAvsByteenable => AvsHostByteenable,
oAvsRead => AvsHostRead,
oAvsWrite => AvsHostWrite,
oAvsWritedata => AvsHostWritedata,
iAvsReaddata => AvsHostReaddata,
iAvsWaitrequest => AvsHostWaitrequest
);
-- Interface signals are hand over to common signals used for
-- both external and internal processor
host_address <= AvsHostAddress(16 downto 2);
host_byteenable <= AvsHostByteenable;
host_Read <= AvsHostRead;
host_write <= AvsHostWrite;
host_writedata <= AvsHostWritedata;
AvsHostWaitrequest <= host_waitrequest;
AvsHostReaddata <= host_readdata;
end generate genAxiHost;
---------------------------------------------------------------------------
-- Parallel Interface External Host Processor
---------------------------------------------------------------------------
-- Generate Parallel Interface for External Processor Interface
genParallel : if gHostIfType = 1 generate
--! Host Data input signal for parallel Interface
signal hostData_i : std_logic_vector(gParallelDataWidth-1 downto 0);
--! Host Data output signal for Parallel Interface
signal hostData_o : std_logic_vector(gParallelDataWidth-1 downto 0);
--! Host Data Enable for switch between input and out for a tri-state buffer
signal hostData_en : std_logic;
--! AddressData input signal for Multiplexed address/data
signal hostAddressData_i : std_logic_vector(gParallelDataWidth-1 downto 0);
--! AddressData output signal for Multiplexed address/data
signal hostAddressData_o : std_logic_vector(gParallelDataWidth-1 downto 0);
--! AddressData Enable for switch between address and data for a tri-state buffer
signal hostAddressData_en: std_logic;
begin
--! Parallel interface For communicating with external Processor
theParallelInterface : entity work.parallelInterface
generic map (
gDataWidth => gParallelDataWidth,
gMultiplex => gParallelMultiplex
)
port map (
iParHostChipselect => iParHost_chipselect,
iParHostRead => iParHost_read,
iParHostWrite => iParHost_write,
iParHostAddressLatchEnable => iParHost_addressLatchEnable,
oParHostAcknowledge => oParHost_acknowledge,
iParHostByteenable => iParHost_byteenable,
iParHostAddress => iParHost_address,
oParHostData => hostData_o,
iParHostData => hostData_i,
oParHostDataEnable => hostData_en,
oParHostAddressData => hostAddressData_o,
iParHostAddressData => hostAddressData_i,
oParHostAddressDataEnable => hostAddressData_en,
iClk => hostif_clock,
iRst => hostif_reset,
oHostAddress => host_address,
oHostByteenable => host_byteenable,
oHostRead => host_Read,
iHostReaddata => host_readdata,
oHostWrite => host_write,
oHostWritedata => host_writedata,
iHostWaitrequest => host_waitrequest
);
-- Added for Xilinx Design for enabling tri-state IO Buffers
-- '1' for In '0' for Out
hostData_i <= iParHost_data_io;
oParHost_data_io <= hostData_o;
oParHost_data_io_tri <= not hostData_en;
-- Added for Xilinx Design for enabling tri-state IO Buffers
hostAddressData_i <= iParHost_addressData_io;
oParHost_addressData_io <= hostAddressData_o;
oParHost_addressData_tri <= not hostAddressData_en;
end generate genParallel;
end rtl;
| gpl-2.0 | e5540b9e26d11ddec57de5812fae403f | 0.543669 | 4.730868 | false | false | false | false |
DreamIP/GPStudio | support/process/erode/hdl/erode_slave.vhd | 1 | 10,882 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity erode_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_value : out std_logic_vector(15 downto 0);
heigtimg_reg_value : out std_logic_vector(15 downto 0);
er00_reg_m00 : out std_logic_vector(7 downto 0);
er01_reg_m01 : out std_logic_vector(7 downto 0);
er02_reg_m02 : out std_logic_vector(7 downto 0);
er10_reg_m10 : out std_logic_vector(7 downto 0);
er11_reg_m11 : out std_logic_vector(7 downto 0);
er12_reg_m12 : out std_logic_vector(7 downto 0);
er20_reg_m20 : out std_logic_vector(7 downto 0);
er21_reg_m21 : out std_logic_vector(7 downto 0);
er22_reg_m22 : out std_logic_vector(7 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end erode_slave;
architecture rtl of erode_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant WIDTHIMG_REG_REG_ADDR : natural := 1;
constant HEIGTIMG_REG_REG_ADDR : natural := 2;
constant ER00_REG_REG_ADDR : natural := 3;
constant ER01_REG_REG_ADDR : natural := 4;
constant ER02_REG_REG_ADDR : natural := 5;
constant ER10_REG_REG_ADDR : natural := 6;
constant ER11_REG_REG_ADDR : natural := 7;
constant ER12_REG_REG_ADDR : natural := 8;
constant ER20_REG_REG_ADDR : natural := 9;
constant ER21_REG_REG_ADDR : natural := 10;
constant ER22_REG_REG_ADDR : natural := 11;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal widthimg_reg_value_reg : std_logic_vector (15 downto 0);
signal heigtimg_reg_value_reg : std_logic_vector (15 downto 0);
signal er00_reg_m00_reg : std_logic_vector (7 downto 0);
signal er01_reg_m01_reg : std_logic_vector (7 downto 0);
signal er02_reg_m02_reg : std_logic_vector (7 downto 0);
signal er10_reg_m10_reg : std_logic_vector (7 downto 0);
signal er11_reg_m11_reg : std_logic_vector (7 downto 0);
signal er12_reg_m12_reg : std_logic_vector (7 downto 0);
signal er20_reg_m20_reg : std_logic_vector (7 downto 0);
signal er21_reg_m21_reg : std_logic_vector (7 downto 0);
signal er22_reg_m22_reg : std_logic_vector (7 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
widthimg_reg_value_reg <= "0000000000000000";
heigtimg_reg_value_reg <= "0000000000000000";
er00_reg_m00_reg <= "00000000";
er01_reg_m01_reg <= "00000000";
er02_reg_m02_reg <= "00000000";
er10_reg_m10_reg <= "00000000";
er11_reg_m11_reg <= "00000000";
er12_reg_m12_reg <= "00000000";
er20_reg_m20_reg <= "00000000";
er21_reg_m21_reg <= "00000000";
er22_reg_m22_reg <= "00000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
status_reg_enable_bit_reg <= datawr_i(0);
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
widthimg_reg_value_reg <= datawr_i(15) & datawr_i(14) & datawr_i(13) & datawr_i(12) & datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(HEIGTIMG_REG_REG_ADDR, 4))=>
heigtimg_reg_value_reg <= datawr_i(15) & datawr_i(14) & datawr_i(13) & datawr_i(12) & datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(ER00_REG_REG_ADDR, 4))=>
er00_reg_m00_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(ER01_REG_REG_ADDR, 4))=>
er01_reg_m01_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(ER02_REG_REG_ADDR, 4))=>
er02_reg_m02_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(ER10_REG_REG_ADDR, 4))=>
er10_reg_m10_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(ER11_REG_REG_ADDR, 4))=>
er11_reg_m11_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(ER12_REG_REG_ADDR, 4))=>
er12_reg_m12_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(ER20_REG_REG_ADDR, 4))=>
er20_reg_m20_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(ER21_REG_REG_ADDR, 4))=>
er21_reg_m21_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(ER22_REG_REG_ADDR, 4))=>
er22_reg_m22_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000000000000000000" & status_reg_enable_bit_reg;
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000" & widthimg_reg_value_reg(15) & widthimg_reg_value_reg(14) & widthimg_reg_value_reg(13) & widthimg_reg_value_reg(12) & widthimg_reg_value_reg(11) & widthimg_reg_value_reg(10) & widthimg_reg_value_reg(9) & widthimg_reg_value_reg(8) & widthimg_reg_value_reg(7) & widthimg_reg_value_reg(6) & widthimg_reg_value_reg(5) & widthimg_reg_value_reg(4) & widthimg_reg_value_reg(3) & widthimg_reg_value_reg(2) & widthimg_reg_value_reg(1) & widthimg_reg_value_reg(0);
when std_logic_vector(to_unsigned(HEIGTIMG_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000" & heigtimg_reg_value_reg(15) & heigtimg_reg_value_reg(14) & heigtimg_reg_value_reg(13) & heigtimg_reg_value_reg(12) & heigtimg_reg_value_reg(11) & heigtimg_reg_value_reg(10) & heigtimg_reg_value_reg(9) & heigtimg_reg_value_reg(8) & heigtimg_reg_value_reg(7) & heigtimg_reg_value_reg(6) & heigtimg_reg_value_reg(5) & heigtimg_reg_value_reg(4) & heigtimg_reg_value_reg(3) & heigtimg_reg_value_reg(2) & heigtimg_reg_value_reg(1) & heigtimg_reg_value_reg(0);
when std_logic_vector(to_unsigned(ER00_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & er00_reg_m00_reg(7) & er00_reg_m00_reg(6) & er00_reg_m00_reg(5) & er00_reg_m00_reg(4) & er00_reg_m00_reg(3) & er00_reg_m00_reg(2) & er00_reg_m00_reg(1) & er00_reg_m00_reg(0);
when std_logic_vector(to_unsigned(ER01_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & er01_reg_m01_reg(7) & er01_reg_m01_reg(6) & er01_reg_m01_reg(5) & er01_reg_m01_reg(4) & er01_reg_m01_reg(3) & er01_reg_m01_reg(2) & er01_reg_m01_reg(1) & er01_reg_m01_reg(0);
when std_logic_vector(to_unsigned(ER02_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & er02_reg_m02_reg(7) & er02_reg_m02_reg(6) & er02_reg_m02_reg(5) & er02_reg_m02_reg(4) & er02_reg_m02_reg(3) & er02_reg_m02_reg(2) & er02_reg_m02_reg(1) & er02_reg_m02_reg(0);
when std_logic_vector(to_unsigned(ER10_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & er10_reg_m10_reg(7) & er10_reg_m10_reg(6) & er10_reg_m10_reg(5) & er10_reg_m10_reg(4) & er10_reg_m10_reg(3) & er10_reg_m10_reg(2) & er10_reg_m10_reg(1) & er10_reg_m10_reg(0);
when std_logic_vector(to_unsigned(ER11_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & er11_reg_m11_reg(7) & er11_reg_m11_reg(6) & er11_reg_m11_reg(5) & er11_reg_m11_reg(4) & er11_reg_m11_reg(3) & er11_reg_m11_reg(2) & er11_reg_m11_reg(1) & er11_reg_m11_reg(0);
when std_logic_vector(to_unsigned(ER12_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & er12_reg_m12_reg(7) & er12_reg_m12_reg(6) & er12_reg_m12_reg(5) & er12_reg_m12_reg(4) & er12_reg_m12_reg(3) & er12_reg_m12_reg(2) & er12_reg_m12_reg(1) & er12_reg_m12_reg(0);
when std_logic_vector(to_unsigned(ER20_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & er20_reg_m20_reg(7) & er20_reg_m20_reg(6) & er20_reg_m20_reg(5) & er20_reg_m20_reg(4) & er20_reg_m20_reg(3) & er20_reg_m20_reg(2) & er20_reg_m20_reg(1) & er20_reg_m20_reg(0);
when std_logic_vector(to_unsigned(ER21_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & er21_reg_m21_reg(7) & er21_reg_m21_reg(6) & er21_reg_m21_reg(5) & er21_reg_m21_reg(4) & er21_reg_m21_reg(3) & er21_reg_m21_reg(2) & er21_reg_m21_reg(1) & er21_reg_m21_reg(0);
when std_logic_vector(to_unsigned(ER22_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & er22_reg_m22_reg(7) & er22_reg_m22_reg(6) & er22_reg_m22_reg(5) & er22_reg_m22_reg(4) & er22_reg_m22_reg(3) & er22_reg_m22_reg(2) & er22_reg_m22_reg(1) & er22_reg_m22_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
widthimg_reg_value <= widthimg_reg_value_reg;
heigtimg_reg_value <= heigtimg_reg_value_reg;
er00_reg_m00 <= er00_reg_m00_reg;
er01_reg_m01 <= er01_reg_m01_reg;
er02_reg_m02 <= er02_reg_m02_reg;
er10_reg_m10 <= er10_reg_m10_reg;
er11_reg_m11 <= er11_reg_m11_reg;
er12_reg_m12 <= er12_reg_m12_reg;
er20_reg_m20 <= er20_reg_m20_reg;
er21_reg_m21 <= er21_reg_m21_reg;
er22_reg_m22 <= er22_reg_m22_reg;
end rtl;
| gpl-3.0 | 875f96fa65aa0caf23bba7b48eddbc9b | 0.615604 | 2.404862 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/xilinx/openmac/src/ipifMasterHandler-rtl-ea.vhd | 3 | 12,619 | -------------------------------------------------------------------------------
--! @file ipifMasterHandler-rtl-ea.vhd
--
--! @brief IPIF Master handler
--
--! @details This is the IPIF master handler converting generic master interface
--! to IPIF.
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity ipifMasterHandler is
generic (
--! Master address width
gMasterAddrWidth : natural := 31;
--! Master burst count width
gMasterBurstCountWidth : natural := 4;
--! IPIF address width
gIpifAddrWidth : natural := 32;
--! IPIF length width
gIpifLength : natural := 12
);
port (
--TODO: Add doxygen comments!
-- Common clock and reset
iRst : in std_logic;
iClk : in std_logic;
-- IPIF Master
iIpif_cmdAck : in std_logic;
iIpif_cmplt : in std_logic;
iIpif_error : in std_logic; --FIXME: Unused input
iIpif_rearbitrate : in std_logic; --FIXME: Unused input
iIpif_cmdTimeout : in std_logic; --FIXME: Unused input
oIpif_type : out std_logic;
oIpif_addr : out std_logic_vector(gIpifAddrWidth-1 downto 0);
oIpif_length : out std_logic_vector(gIpifLength-1 downto 0);
oIpif_be : out std_logic_vector(3 downto 0);
oIpif_lock : out std_logic;
oIpif_reset : out std_logic;
iIpif_rdData : in std_logic_vector(31 downto 0);
iIpif_rdRem : in std_logic_vector(3 downto 0); --FIXME: Unused input
oIpif_rdReq : out std_logic;
inIpif_rdSof : in std_logic;
inIpif_rdEof : in std_logic;
inIpif_rdSrcRdy : in std_logic;
inIpif_rdSrcDsc : in std_logic; --FIXME: Unused input
onIpif_rdDstRdy : out std_logic;
onIpif_rdDstDsc : out std_logic;
oIpif_wrData : out std_logic_vector(31 downto 0);
oIpif_wrRem : out std_logic_vector(3 downto 0);
oIpif_wrReq : out std_logic;
onIpif_wrSof : out std_logic;
onIpif_wrEof : out std_logic;
onIpif_wrSrcRdy : out std_logic;
onIpif_wrSrcDsc : out std_logic;
inIpif_wrDstRdy : in std_logic;
inIpif_wrDstDsc : in std_logic; --FIXME: Unused input
-- Generic master interface
iMasterRead : in std_logic;
iMasterWrite : in std_logic;
iMasterAddress : in std_logic_vector(gMasterAddrWidth-1 downto 0);
iMasterWritedata : in std_logic_vector(31 downto 0);
iMasterBurstcount : in std_logic_vector(gMasterBurstCountWidth-1 downto 0);
iMasterBurstcounter : in std_logic_vector(gMasterBurstCountWidth-1 downto 0);
oMasterReaddata : out std_logic_vector(31 downto 0);
oMasterWaitrequest : out std_logic;
oMasterReaddatavalid : out std_logic
);
end ipifMasterHandler;
architecture rtl of ipifMasterHandler is
--signals for requesting transfers
signal masterWrite : std_logic;
signal masterRead : std_logic;
signal nMasterEnable : std_logic;
signal masterWrite_l : std_logic;
signal masterRead_l : std_logic;
signal masterWrite_rise : std_logic;
signal masterRead_rise : std_logic;
signal masterWrite_fall : std_logic;
signal masterRead_fall : std_logic;
signal ipifWriteReq_reg : std_logic;
signal ipifWriteReq_next : std_logic;
signal ipifReadReq_reg : std_logic;
signal ipifReadReq_next : std_logic;
signal ipif_rdDstRdy : std_logic;
--signals for the transfer
type tTfState is (
sIdle,
sSof, sTf, sEof,
sSEof, --start/end of frame (single beat)
sWaitForCmplt
);
signal writeTf_reg : tTfState;
signal writeTf_next : tTfState;
signal readTf : tTfState;
begin
masterWrite <= iMasterWrite and not nMasterEnable;
masterRead <= iMasterRead and not nMasterEnable;
--reserved
oIpif_lock <= cInactivated;
oIpif_reset <= cInactivated;
--delay some signals..
del_proc : process(iClk, iRst)
begin
if iRst = cActivated then
masterWrite_l <= cInactivated;
masterRead_l <= cInactivated;
nMasterEnable <= cnActivated;
elsif rising_edge(iClk) then
masterWrite_l <= masterWrite;
masterRead_l <= masterRead;
if iIpif_cmplt = cActivated then
nMasterEnable <= cnActivated;
elsif masterWrite_fall = cActivated or masterRead_fall = cActivated then
nMasterEnable <= cnInactivated; --write/read done, wait for Mst_Cmplt
end if;
end if;
end process;
--generate pulse if write/read is asserted
masterWrite_rise <= cActivated when masterWrite_l = cInactivated and masterWrite = cActivated else
cInactivated;
masterRead_rise <= cActivated when masterRead_l = cInactivated and masterRead = cActivated else
cInactivated;
masterWrite_fall <= cActivated when masterWrite_l = cActivated and masterWrite = cInactivated else
cInactivated;
masterRead_fall <= cActivated when masterRead_l = cActivated and masterRead = cInactivated else
cInactivated;
--generate req qualifiers
req_proc : process(iClk, iRst)
begin
if iRst = cActivated then
ipifWriteReq_reg <= cInactivated;
ipifReadReq_reg <= cInactivated;
ipif_rdDstRdy <= cInactivated;
elsif rising_edge(iClk) then
ipifWriteReq_reg <= ipifWriteReq_next;
ipifReadReq_reg <= ipifReadReq_next;
if masterRead = cActivated then
ipif_rdDstRdy <= cActivated;
elsif readTf = sEof and inIpif_rdSrcRdy = cnActivated then
ipif_rdDstRdy <= cInactivated;
end if;
end if;
end process;
onIpif_rdDstRdy <= not ipif_rdDstRdy;
oIpif_rdReq <= ipifReadReq_reg;
oIpif_wrReq <= ipifWriteReq_reg;
oIpif_type <= cInactivated when iMasterBurstcount < 2 else --single beat
ipifReadReq_reg or ipifWriteReq_reg; --we are talking about bursts..
ipifWriteReq_next <= cInactivated when ipifWriteReq_reg = cActivated and iIpif_cmdAck = cActivated else
cActivated when ipifWriteReq_reg = cInactivated and masterWrite_rise = cActivated else
ipifWriteReq_reg;
ipifReadReq_next <= cInactivated when ipifReadReq_reg = cActivated and iIpif_cmdAck = cActivated else
cActivated when ipifReadReq_reg = cInactivated and masterRead_rise = cActivated else
ipifReadReq_reg;
--assign address, byteenable and burst size
comb_addrZeroPad : process(iMasterAddress)
begin
for i in oIpif_addr'range loop
if i <= iMasterAddress'high then
oIpif_addr(i) <= iMasterAddress(i);
else
oIpif_addr(i) <= cInactivated; --zero padding
end if;
end loop;
end process;
oIpif_be <= "1111";
oIpif_length <= conv_std_logic_vector(conv_integer(iMasterBurstcount),
oIpif_length'length - 2) & "00"; -- dword x 4 = byte
--write/read link
wrd_proc : process(iClk, iRst)
begin
if iRst = cActivated then
writeTf_reg <= sIdle;
elsif rising_edge(iClk) then
writeTf_reg <= writeTf_next;
end if;
end process;
--generate fsm for write and read transfers
writeTf_next <= sSEof when writeTf_reg = sIdle and ipifWriteReq_next = cActivated and (iMasterBurstcount <= 1 or iMasterBurstcount'length = 1) else
sSof when writeTf_reg = sIdle and ipifWriteReq_next = cActivated and iMasterBurstcount'length > 1 else
sEof when writeTf_reg = sSof and inIpif_wrDstRdy = cnActivated and iMasterBurstcount = 2 and iMasterBurstcount'length > 1 else
sTf when writeTf_reg = sSof and inIpif_wrDstRdy = cnActivated and iMasterBurstcount'length > 1 else
sEof when writeTf_reg = sTf and iMasterBurstcounter <= 2 and inIpif_wrDstRdy = cnActivated and iMasterBurstcount'length > 1 else
sWaitForCmplt when (writeTf_reg = sEof or writeTf_reg = sSEof) and inIpif_wrDstRdy = cnActivated else
sIdle when writeTf_reg = sWaitForCmplt and iIpif_cmplt = cActivated else
writeTf_reg;
readTf <= sSEof when inIpif_rdSof = cnActivated and inIpif_rdEof = cnActivated else
sSof when inIpif_rdSof = cnActivated else
sEof when inIpif_rdEof = cnActivated else
sTf when inIpif_rdSrcRdy = cnActivated else
sIdle;
--set write qualifiers
onIpif_wrSof <= cnActivated when writeTf_reg = sSof or writeTf_reg = sSEof else
cnInactivated;
onIpif_wrEof <= cnActivated when writeTf_reg = sEof or writeTf_reg = sSEof else
cnInactivated;
onIpif_wrSrcRdy <= cnActivated when writeTf_reg /= sIdle and writeTf_reg /= sWaitForCmplt else
cnInactivated;
onIpif_wrSrcDsc <= cnInactivated; --no support
oIpif_wrRem <= (others => cInactivated); --no support
--set read qualifiers
onIpif_rdDstDsc <= cnInactivated; --no support
--connect ipif with generic master
oMasterWaitrequest <= not iMasterWrite when inIpif_wrDstRdy = cnActivated else
not iMasterRead when ipifReadReq_reg = cActivated and iIpif_cmdAck = cActivated else cActivated;
oMasterReaddatavalid <= not inIpif_rdSrcRdy;
oIpif_wrData <= iMasterWritedata;
oMasterReaddata <= iIpif_rdData;
end rtl;
| gpl-2.0 | d1e7e445f8f069f95e25c5139151e29d | 0.589032 | 4.781736 | false | false | false | false |
zatslogic/UDI_example | core_project/core_project.srcs/sources_1/ip/mult_16_x_16_res_32/mult_gen_v11_2/simulation/mult_gen_v11_2_xst.vhd | 1 | 5,418 | -- $RCSfile: mult_gen_v11_2_xst.vhd,v $ $Revision: 1.4 $ $Date: 2010/03/19 10:56:59 $
--------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library xilinxcorelib;
use xilinxcorelib.mult_gen_v11_2_comp.all;
entity mult_gen_v11_2_xst is
generic (
C_VERBOSITY : integer := 0;
C_MODEL_TYPE : integer := 0;
C_XDEVICEFAMILY : string := "virtex4";
C_A_WIDTH : integer := 18;
C_A_TYPE : integer := 0;
C_B_WIDTH : integer := 18;
C_B_TYPE : integer := 0;
C_OUT_HIGH : integer := 35;
C_OUT_LOW : integer := 0;
C_MULT_TYPE : integer := 1;
C_OPTIMIZE_GOAL : integer := 1;
C_HAS_CE : integer := 0;
C_HAS_SCLR : integer := 0;
C_CE_OVERRIDES_SCLR : integer := 1;
C_LATENCY : integer := -1;
C_CCM_IMP : integer := 0;
C_B_VALUE : string := "111111111111111111";
C_HAS_ZERO_DETECT : integer := 0;
C_ROUND_OUTPUT : integer := 0;
C_ROUND_PT : integer := 0);
port (
CLK : in std_logic := '1';
A : in std_logic_vector(C_A_WIDTH-1 downto 0) := (others => '0');
B : in std_logic_vector(C_B_WIDTH-1 downto 0) := (others => '0');
CE : in std_logic := '1';
SCLR : in std_logic := '0';
ZERO_DETECT : out std_logic_vector(1 downto 0) := (others => '0');
P : out std_logic_vector(C_OUT_HIGH-C_OUT_LOW downto 0) := (others => '0');
PCASC : out std_logic_vector(47 downto 0) := (others => '0'));
end entity mult_gen_v11_2_xst;
--
-- behavior describing a parameterized multiplier
--
architecture behavioral of mult_gen_v11_2_xst is
begin
i_behv : mult_gen_v11_2
generic map(
C_VERBOSITY => C_VERBOSITY,
C_MODEL_TYPE => C_MODEL_TYPE,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_A_WIDTH => C_A_WIDTH,
C_A_TYPE => C_A_TYPE,
C_B_WIDTH => C_B_WIDTH,
C_B_TYPE => C_B_TYPE,
C_OUT_HIGH => C_OUT_HIGH,
C_OUT_LOW => C_OUT_LOW,
C_MULT_TYPE => C_MULT_TYPE,
C_OPTIMIZE_GOAL => C_OPTIMIZE_GOAL,
C_HAS_CE => C_HAS_CE,
C_HAS_SCLR => C_HAS_SCLR,
C_CE_OVERRIDES_SCLR => C_CE_OVERRIDES_SCLR,
C_LATENCY => C_LATENCY,
C_CCM_IMP => C_CCM_IMP,
C_B_VALUE => C_B_VALUE,
C_HAS_ZERO_DETECT => C_HAS_ZERO_DETECT,
C_ROUND_OUTPUT => C_ROUND_OUTPUT,
C_ROUND_PT => C_ROUND_PT)
port map(
CLK => CLK,
A => A,
B => B,
CE => CE,
SCLR => SCLR,
ZERO_DETECT => ZERO_DETECT,
P => P,
PCASC => PCASC);
end behavioral;
| gpl-3.0 | 191812d1f0d437bd5cf39605beb22731 | 0.563861 | 3.850746 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_Pixel_RGB_Resampler.vhd | 1 | 8,495 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module converts video streams between RGB color formats. *
-- * *
-- ******************************************************************************
ENTITY Video_System_Pixel_RGB_Resampler IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
GENERIC (
IDW :INTEGER := 15;
ODW :INTEGER := 29;
IEW :INTEGER := 0;
OEW :INTEGER := 1;
ALPHA :STD_LOGIC_VECTOR( 9 DOWNTO 0) := B"1111111111"
);
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
stream_in_data :IN STD_LOGIC_VECTOR(IDW DOWNTO 0);
stream_in_startofpacket :IN STD_LOGIC;
stream_in_endofpacket :IN STD_LOGIC;
stream_in_empty :IN STD_LOGIC_VECTOR(IEW DOWNTO 0);
stream_in_valid :IN STD_LOGIC;
stream_out_ready :IN STD_LOGIC;
-- Bidirectional
-- Outputs
stream_in_ready :BUFFER STD_LOGIC;
stream_out_data :BUFFER STD_LOGIC_VECTOR(ODW DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_empty :BUFFER STD_LOGIC_VECTOR(OEW DOWNTO 0);
stream_out_valid :BUFFER STD_LOGIC
);
END Video_System_Pixel_RGB_Resampler;
ARCHITECTURE Behaviour OF Video_System_Pixel_RGB_Resampler IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
SIGNAL r :STD_LOGIC_VECTOR( 9 DOWNTO 0);
SIGNAL g :STD_LOGIC_VECTOR( 9 DOWNTO 0);
SIGNAL b :STD_LOGIC_VECTOR( 9 DOWNTO 0);
SIGNAL a :STD_LOGIC_VECTOR( 9 DOWNTO 0);
SIGNAL converted_data :STD_LOGIC_VECTOR(ODW DOWNTO 0);
-- Internal Registers
-- State Machine Registers
-- Integers
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
-- Output Registers
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
stream_out_data <= (OTHERS => '0');
stream_out_startofpacket <= '0';
stream_out_endofpacket <= '0';
stream_out_empty <= (OTHERS => '0');
stream_out_valid <= '0';
ELSIF ((stream_out_ready = '1') OR (stream_out_valid = '0')) THEN
stream_out_data <= converted_data;
stream_out_startofpacket <= stream_in_startofpacket;
stream_out_endofpacket <= stream_in_endofpacket;
-- stream_out_empty <= stream_in_empty;
stream_out_empty <= (OTHERS => '0');
stream_out_valid <= stream_in_valid;
END IF;
END IF;
END PROCESS;
-- Internal Registers
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
-- Output Assignments
stream_in_ready <= stream_out_ready OR NOT stream_out_valid;
-- Internal Assignments
r <= (stream_in_data(15 DOWNTO 11) & stream_in_data(15 DOWNTO 11));
g <= (stream_in_data(10 DOWNTO 5) & stream_in_data(10 DOWNTO 7));
b <= (stream_in_data( 4 DOWNTO 0) & stream_in_data( 4 DOWNTO 0));
a <= ALPHA;
converted_data(29 DOWNTO 20) <= r( 9 DOWNTO 0);
converted_data(19 DOWNTO 10) <= g( 9 DOWNTO 0);
converted_data( 9 DOWNTO 0) <= b( 9 DOWNTO 0);
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
END Behaviour;
| gpl-2.0 | 17d68d8d821c34d54cb060623c03d114 | 0.430724 | 4.873781 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/boards/altera-c5soc/mn-soc-shmem-gpio/quartus/toplevel.vhd | 5 | 31,832 |
------------------------------------------------------------------------------
--Copyright (c) 2014, Kalycito Infotech Pvt Ltd
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- * Neither the name of the copyright holders nor the
-- names of its contributors may be used to endorse or promote products
-- derived from this software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
--ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
--WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS BE LIABLE FOR ANY
--DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
--LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
--ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
--(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
--SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library libcommon;
use libcommon.global.all;
entity toplevel is
generic (
gBoardRev : string := "D"
);
port (
-- FPGA peripherals ports
fpga_dipsw_pio : in std_logic_vector (3 downto 0);
fpga_button_pio : in std_logic_vector (1 downto 0);
-- HPS memory controller ports
hps_memory_mem_a : out std_logic_vector (14 downto 0);
hps_memory_mem_ba : out std_logic_vector (2 downto 0);
hps_memory_mem_ck : out std_logic;
hps_memory_mem_ck_n : out std_logic;
hps_memory_mem_cke : out std_logic;
hps_memory_mem_cs_n : out std_logic;
hps_memory_mem_ras_n : out std_logic;
hps_memory_mem_cas_n : out std_logic;
hps_memory_mem_we_n : out std_logic;
hps_memory_mem_reset_n : out std_logic;
hps_memory_mem_dq : inout std_logic_vector (39 downto 0);
hps_memory_mem_dqs : inout std_logic_vector (4 downto 0);
hps_memory_mem_dqs_n : inout std_logic_vector (4 downto 0);
hps_memory_mem_odt : out std_logic;
hps_memory_mem_dm : out std_logic_vector (4 downto 0);
hps_memory_oct_rzqin : in std_logic;
-- HPS peripherals
hps_emac1_TX_CLK : out std_logic;
hps_emac1_TXD0 : out std_logic;
hps_emac1_TXD1 : out std_logic;
hps_emac1_TXD2 : out std_logic;
hps_emac1_TXD3 : out std_logic;
hps_emac1_RXD0 : in std_logic;
hps_emac1_MDIO : inout std_logic;
hps_emac1_MDC : out std_logic;
hps_emac1_RX_CTL : in std_logic;
hps_emac1_TX_CTL : out std_logic;
hps_emac1_RX_CLK : in std_logic;
hps_emac1_RXD1 : in std_logic;
hps_emac1_RXD2 : in std_logic;
hps_emac1_RXD3 : in std_logic;
hps_qspi_IO0 : inout std_logic;
hps_qspi_IO1 : inout std_logic;
hps_qspi_IO2 : inout std_logic;
hps_qspi_IO3 : inout std_logic;
hps_qspi_SS0 : out std_logic;
hps_qspi_CLK : out std_logic;
hps_sdio_CMD : inout std_logic;
hps_sdio_D0 : inout std_logic;
hps_sdio_D1 : inout std_logic;
hps_sdio_CLK : out std_logic;
hps_sdio_D2 : inout std_logic;
hps_sdio_D3 : inout std_logic;
hps_usb1_D0 : inout std_logic;
hps_usb1_D1 : inout std_logic;
hps_usb1_D2 : inout std_logic;
hps_usb1_D3 : inout std_logic;
hps_usb1_D4 : inout std_logic;
hps_usb1_D5 : inout std_logic;
hps_usb1_D6 : inout std_logic;
hps_usb1_D7 : inout std_logic;
hps_usb1_CLK : in std_logic;
hps_usb1_STP : out std_logic;
hps_usb1_DIR : in std_logic;
hps_usb1_NXT : in std_logic;
hps_spim0_CLK : out std_logic;
hps_spim0_MOSI : out std_logic;
hps_spim0_MISO : in std_logic;
hps_spim0_SS0 : out std_logic;
hps_uart0_RX : in std_logic;
hps_uart0_TX : out std_logic;
hps_i2c0_SDA : inout std_logic;
hps_i2c0_SCL : inout std_logic;
hps_can0_RX : in std_logic;
hps_can0_TX : out std_logic;
hps_trace_CLK : out std_logic;
hps_trace_D0 : out std_logic;
hps_trace_D1 : out std_logic;
hps_trace_D2 : out std_logic;
hps_trace_D3 : out std_logic;
hps_trace_D4 : out std_logic;
hps_trace_D5 : out std_logic;
hps_trace_D6 : out std_logic;
hps_trace_D7 : out std_logic;
hps_gpio_GPIO09 : inout std_logic;
hps_gpio_GPIO35 : inout std_logic;
hps_gpio_GPIO41 : inout std_logic;
hps_gpio_GPIO42 : inout std_logic;
hps_gpio_GPIO43 : inout std_logic;
hps_gpio_GPIO44 : inout std_logic;
-- FPGA SDRAM
fpga_memory_mem_a : out std_logic_vector (14 downto 0);
fpga_memory_mem_ba : out std_logic_vector (2 downto 0);
fpga_memory_mem_ck : out std_logic_vector (0 downto 0);
fpga_memory_mem_ck_n : out std_logic_vector (0 downto 0);
fpga_memory_mem_cke : out std_logic_vector (0 downto 0);
fpga_memory_mem_cs_n : out std_logic_vector (0 downto 0);
fpga_memory_mem_dm : out std_logic_vector (3 downto 0);
fpga_memory_mem_ras_n : out std_logic_vector (0 downto 0);
fpga_memory_mem_cas_n : out std_logic_vector (0 downto 0);
fpga_memory_mem_we_n : out std_logic_vector (0 downto 0);
fpga_memory_mem_reset_n : out std_logic;
fpga_memory_mem_dq : inout std_logic_vector (31 downto 0);
fpga_memory_mem_dqs : inout std_logic_vector (3 downto 0);
fpga_memory_mem_dqs_n : inout std_logic_vector (3 downto 0);
fpga_memory_mem_odt : out std_logic_vector (0 downto 0);
fpga_oct_rzqin : in std_logic;
-- FPGA clock and reset
fpga_clk_50 : in std_logic;
PLNK_MII_TXEN : out std_logic_vector(1 downto 0);-- txEnable
PLNK_MII_TXD : out std_logic_vector(7 downto 0);-- txData
PLNK_PHY_CLK : in std_logic;
PLNK_MII_TXCLK : in std_logic_vector(1 downto 0) := (others => 'X'); -- txClk
PLNK_MII_RXERR : in std_logic_vector(1 downto 0) := (others => 'X'); -- rxError
PLNK_MII_RXDV : in std_logic_vector(1 downto 0) := (others => 'X'); -- rxDataValid
PLNK_MII_RXD : in std_logic_vector(7 downto 0) := (others => 'X'); -- rxData
PLNK_MII_RXCLK : in std_logic_vector(1 downto 0) := (others => 'X'); -- rxClk
PLNK_SMI_PHYRSTN : out std_logic_vector(0 downto 0);-- nPhyRst
PLNK_SMI_CLK : out std_logic_vector(0 downto 0);-- clk
PLNK_SMI_DIO : inout std_logic_vector(0 downto 0) := (others => 'X');-- dio
-- POWERLINK LED module
pcp_led : out std_logic_vector (1 downto 0)
);
end toplevel;
architecture rtl of toplevel is
signal hps_fpga_reset_n : std_logic;
signal ddr3_afi_resetn : std_logic;
signal fpga_memory_mem_addr : std_logic_vector (12 downto 0);
signal clk50 : std_logic;
signal clk100 : std_logic;
signal pllLocked : std_logic;
signal h2f_cold_reset_n : std_logic;
signal h2f_gp_in : std_logic_vector(31 downto 0);
signal h2f_gp_out : std_logic_vector(31 downto 0);
signal miiTxClk : std_logic_vector(1 downto 0);
component mnSocShmemGpio is
port (
memory_mem_a : out std_logic_vector(14 downto 0);
memory_mem_ba : out std_logic_vector(2 downto 0);
memory_mem_ck : out std_logic;
memory_mem_ck_n : out std_logic;
memory_mem_cke : out std_logic;
memory_mem_cs_n : out std_logic;
memory_mem_ras_n : out std_logic;
memory_mem_cas_n : out std_logic;
memory_mem_we_n : out std_logic;
memory_mem_reset_n : out std_logic;
memory_mem_dq : inout std_logic_vector(39 downto 0) := (others => 'X');
memory_mem_dqs : inout std_logic_vector(4 downto 0) := (others => 'X');
memory_mem_dqs_n : inout std_logic_vector(4 downto 0) := (others => 'X');
memory_mem_odt : out std_logic;
memory_mem_dm : out std_logic_vector(4 downto 0);
memory_oct_rzqin : in std_logic := 'X';
memory_fpga_mem_a : out std_logic_vector(12 downto 0);
memory_fpga_mem_ba : out std_logic_vector(2 downto 0);
memory_fpga_mem_ck : out std_logic_vector(0 downto 0);
memory_fpga_mem_ck_n : out std_logic_vector(0 downto 0);
memory_fpga_mem_cke : out std_logic_vector(0 downto 0);
memory_fpga_mem_cs_n : out std_logic_vector(0 downto 0);
memory_fpga_mem_dm : out std_logic_vector(3 downto 0);
memory_fpga_mem_ras_n : out std_logic_vector(0 downto 0);
memory_fpga_mem_cas_n : out std_logic_vector(0 downto 0);
memory_fpga_mem_we_n : out std_logic_vector(0 downto 0);
memory_fpga_mem_reset_n : out std_logic;
memory_fpga_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X');
memory_fpga_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X');
memory_fpga_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X');
memory_fpga_mem_odt : out std_logic_vector(0 downto 0);
oct_rzqin : in std_logic := 'X';
clk_50_clk : in std_logic := 'X';
clk_100_clk : in std_logic := 'X';
reset_reset_n : in std_logic := 'X';
hps_io_hps_io_emac1_inst_TX_CLK : out std_logic;
hps_io_hps_io_emac1_inst_TXD0 : out std_logic;
hps_io_hps_io_emac1_inst_TXD1 : out std_logic;
hps_io_hps_io_emac1_inst_TXD2 : out std_logic;
hps_io_hps_io_emac1_inst_TXD3 : out std_logic;
hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X';
hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X';
hps_io_hps_io_emac1_inst_MDC : out std_logic;
hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X';
hps_io_hps_io_emac1_inst_TX_CTL : out std_logic;
hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X';
hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X';
hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X';
hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X';
hps_io_hps_io_qspi_inst_IO0 : inout std_logic := 'X';
hps_io_hps_io_qspi_inst_IO1 : inout std_logic := 'X';
hps_io_hps_io_qspi_inst_IO2 : inout std_logic := 'X';
hps_io_hps_io_qspi_inst_IO3 : inout std_logic := 'X';
hps_io_hps_io_qspi_inst_SS0 : out std_logic;
hps_io_hps_io_qspi_inst_CLK : out std_logic;
hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X';
hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X';
hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X';
hps_io_hps_io_sdio_inst_CLK : out std_logic;
hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X';
hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X';
hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X';
hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X';
hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X';
hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X';
hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X';
hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X';
hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X';
hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X';
hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X';
hps_io_hps_io_usb1_inst_STP : out std_logic;
hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X';
hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X';
hps_io_hps_io_spim0_inst_CLK : out std_logic;
hps_io_hps_io_spim0_inst_MOSI : out std_logic;
hps_io_hps_io_spim0_inst_MISO : in std_logic := 'X';
hps_io_hps_io_spim0_inst_SS0 : out std_logic;
hps_io_hps_io_uart0_inst_RX : in std_logic := 'X';
hps_io_hps_io_uart0_inst_TX : out std_logic;
hps_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X';
hps_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X';
hps_io_hps_io_can0_inst_RX : in std_logic := 'X';
hps_io_hps_io_can0_inst_TX : out std_logic;
hps_io_hps_io_trace_inst_CLK : out std_logic;
hps_io_hps_io_trace_inst_D0 : out std_logic;
hps_io_hps_io_trace_inst_D1 : out std_logic;
hps_io_hps_io_trace_inst_D2 : out std_logic;
hps_io_hps_io_trace_inst_D3 : out std_logic;
hps_io_hps_io_trace_inst_D4 : out std_logic;
hps_io_hps_io_trace_inst_D5 : out std_logic;
hps_io_hps_io_trace_inst_D6 : out std_logic;
hps_io_hps_io_trace_inst_D7 : out std_logic;
hps_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X';
hps_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X';
hps_io_hps_io_gpio_inst_GPIO41 : inout std_logic := 'X';
hps_io_hps_io_gpio_inst_GPIO42 : inout std_logic := 'X';
hps_io_hps_io_gpio_inst_GPIO43 : inout std_logic := 'X';
hps_io_hps_io_gpio_inst_GPIO44 : inout std_logic := 'X';
hps_0_f2h_cold_reset_req_reset_n : in std_logic := 'X';
hps_0_f2h_debug_reset_req_reset_n : in std_logic := 'X';
hps_0_f2h_warm_reset_req_reset_n : in std_logic := 'X';
dipsw_pio_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X');
button_pio_external_connection_export : in std_logic_vector(1 downto 0) := (others => 'X');
ddr3_emif_0_status_local_init_done : out std_logic;
ddr3_emif_0_status_local_cal_success : out std_logic;
ddr3_emif_0_status_local_cal_fail : out std_logic;
ddr3_emif_0_pll_sharing_pll_mem_clk : out std_logic;
ddr3_emif_0_pll_sharing_pll_write_clk : out std_logic;
ddr3_emif_0_pll_sharing_pll_locked : out std_logic;
ddr3_emif_0_pll_sharing_pll_write_clk_pre_phy_clk : out std_logic;
ddr3_emif_0_pll_sharing_pll_addr_cmd_clk : out std_logic;
ddr3_emif_0_pll_sharing_pll_avl_clk : out std_logic;
ddr3_emif_0_pll_sharing_pll_config_clk : out std_logic;
ddr3_emif_0_pll_sharing_pll_dr_clk : out std_logic;
ddr3_emif_0_pll_sharing_pll_dr_clk_pre_phy_clk : out std_logic;
ddr3_emif_0_pll_sharing_pll_mem_phy_clk : out std_logic;
ddr3_emif_0_pll_sharing_afi_phy_clk : out std_logic;
ddr3_emif_0_pll_sharing_pll_avl_phy_clk : out std_logic;
ddr3_emif_0_global_reset_reset_n : in std_logic := 'X';
ddr3_emif_0_afi_reset_export_reset_n : out std_logic;
ddr3_emif_0_pll_ref_clk_clk : in std_logic := 'X';
ddr3_emif_0_soft_reset_reset_n : in std_logic := 'X';
openmac_0_mii_txEnable : out std_logic_vector(1 downto 0);
openmac_0_mii_txData : out std_logic_vector(7 downto 0);
openmac_0_mii_txClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxError : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxDataValid : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxData : in std_logic_vector(7 downto 0) := (others => 'X');
openmac_0_mii_rxClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_smi_nPhyRst : out std_logic_vector(0 downto 0);
openmac_0_smi_clk : out std_logic_vector(0 downto 0);
openmac_0_smi_dio : inout std_logic_vector(0 downto 0) := (others => 'X');
host_0_hps_0_h2f_gp_gp_in : in std_logic_vector(31 downto 0) := (others => 'X');
host_0_hps_0_h2f_gp_gp_out : out std_logic_vector(31 downto 0);
host_0_hps_0_h2f_cold_reset_reset_n : out std_logic;
pcp_0_cpu_resetrequest_resetrequest : in std_logic := 'X';
pcp_0_cpu_resetrequest_resettaken : out std_logic;
pcp_0_benchmark_pio_export : out std_logic_vector(7 downto 0);
powerlink_led_export : out std_logic_vector(1 downto 0)
);
end component mnSocShmemGpio;
-- PLL
component pll
PORT
(
refclk : in std_logic := '0';
rst : in std_logic := '0';
outclk_0 : out std_logic;
outclk_1 : out std_logic;
locked : out std_logic
);
end component pll;
begin
-- Append 0 for MSB bits of DDR Memory
fpga_memory_mem_a <= "00" & fpga_memory_mem_addr;
soc_inst: component mnSocShmemGpio
port map (
--HPS External Memory
memory_mem_a => hps_memory_mem_a,
memory_mem_ba => hps_memory_mem_ba,
memory_mem_ck => hps_memory_mem_ck,
memory_mem_ck_n => hps_memory_mem_ck_n,
memory_mem_cke => hps_memory_mem_cke,
memory_mem_cs_n => hps_memory_mem_cs_n,
memory_mem_ras_n => hps_memory_mem_ras_n,
memory_mem_cas_n => hps_memory_mem_cas_n,
memory_mem_we_n => hps_memory_mem_we_n,
memory_mem_reset_n => hps_memory_mem_reset_n,
memory_mem_dq => hps_memory_mem_dq,
memory_mem_dqs => hps_memory_mem_dqs,
memory_mem_dqs_n => hps_memory_mem_dqs_n,
memory_mem_odt => hps_memory_mem_odt,
memory_mem_dm => hps_memory_mem_dm,
memory_oct_rzqin => hps_memory_oct_rzqin,
--DIP Switch FPGA
dipsw_pio_external_connection_export => fpga_dipsw_pio,
button_pio_external_connection_export => fpga_button_pio,
hps_io_hps_io_emac1_inst_TX_CLK => hps_emac1_TX_CLK,
hps_io_hps_io_emac1_inst_TXD0 => hps_emac1_TXD0,
hps_io_hps_io_emac1_inst_TXD1 => hps_emac1_TXD1,
hps_io_hps_io_emac1_inst_TXD2 => hps_emac1_TXD2,
hps_io_hps_io_emac1_inst_TXD3 => hps_emac1_TXD3,
hps_io_hps_io_emac1_inst_RXD0 => hps_emac1_RXD0,
hps_io_hps_io_emac1_inst_MDIO => hps_emac1_MDIO,
hps_io_hps_io_emac1_inst_MDC => hps_emac1_MDC,
hps_io_hps_io_emac1_inst_RX_CTL => hps_emac1_RX_CTL,
hps_io_hps_io_emac1_inst_TX_CTL => hps_emac1_TX_CTL,
hps_io_hps_io_emac1_inst_RX_CLK => hps_emac1_RX_CLK,
hps_io_hps_io_emac1_inst_RXD1 => hps_emac1_RXD1,
hps_io_hps_io_emac1_inst_RXD2 => hps_emac1_RXD2,
hps_io_hps_io_emac1_inst_RXD3 => hps_emac1_RXD3,
hps_io_hps_io_qspi_inst_IO0 => hps_qspi_IO0,
hps_io_hps_io_qspi_inst_IO1 => hps_qspi_IO1,
hps_io_hps_io_qspi_inst_IO2 => hps_qspi_IO2,
hps_io_hps_io_qspi_inst_IO3 => hps_qspi_IO3,
hps_io_hps_io_qspi_inst_SS0 => hps_qspi_SS0,
hps_io_hps_io_qspi_inst_CLK => hps_qspi_CLK,
hps_io_hps_io_sdio_inst_CMD => hps_sdio_CMD,
hps_io_hps_io_sdio_inst_D0 => hps_sdio_D0,
hps_io_hps_io_sdio_inst_D1 => hps_sdio_D1,
hps_io_hps_io_sdio_inst_CLK => hps_sdio_CLK,
hps_io_hps_io_sdio_inst_D2 => hps_sdio_D2,
hps_io_hps_io_sdio_inst_D3 => hps_sdio_D3,
hps_io_hps_io_usb1_inst_D0 => hps_usb1_D0,
hps_io_hps_io_usb1_inst_D1 => hps_usb1_D1,
hps_io_hps_io_usb1_inst_D2 => hps_usb1_D2,
hps_io_hps_io_usb1_inst_D3 => hps_usb1_D3,
hps_io_hps_io_usb1_inst_D4 => hps_usb1_D4,
hps_io_hps_io_usb1_inst_D5 => hps_usb1_D5,
hps_io_hps_io_usb1_inst_D6 => hps_usb1_D6,
hps_io_hps_io_usb1_inst_D7 => hps_usb1_D7,
hps_io_hps_io_usb1_inst_CLK => hps_usb1_CLK,
hps_io_hps_io_usb1_inst_STP => hps_usb1_STP,
hps_io_hps_io_usb1_inst_DIR => hps_usb1_DIR,
hps_io_hps_io_usb1_inst_NXT => hps_usb1_NXT,
hps_io_hps_io_spim0_inst_CLK => hps_spim0_CLK,
hps_io_hps_io_spim0_inst_MOSI => hps_spim0_MOSI,
hps_io_hps_io_spim0_inst_MISO => hps_spim0_MISO,
hps_io_hps_io_spim0_inst_SS0 => hps_spim0_SS0,
hps_io_hps_io_uart0_inst_RX => hps_uart0_RX,
hps_io_hps_io_uart0_inst_TX => hps_uart0_TX,
hps_io_hps_io_i2c0_inst_SDA => hps_i2c0_SDA,
hps_io_hps_io_i2c0_inst_SCL => hps_i2c0_SCL,
hps_io_hps_io_can0_inst_RX => hps_can0_RX,
hps_io_hps_io_can0_inst_TX => hps_can0_TX,
hps_io_hps_io_trace_inst_CLK => hps_trace_CLK,
hps_io_hps_io_trace_inst_D0 => hps_trace_D0,
hps_io_hps_io_trace_inst_D1 => hps_trace_D1,
hps_io_hps_io_trace_inst_D2 => hps_trace_D2,
hps_io_hps_io_trace_inst_D3 => hps_trace_D3,
hps_io_hps_io_trace_inst_D4 => hps_trace_D4,
hps_io_hps_io_trace_inst_D5 => hps_trace_D5,
hps_io_hps_io_trace_inst_D6 => hps_trace_D6,
hps_io_hps_io_trace_inst_D7 => hps_trace_D7,
hps_io_hps_io_gpio_inst_GPIO09 => hps_gpio_GPIO09,
hps_io_hps_io_gpio_inst_GPIO35 => hps_gpio_GPIO35,
hps_io_hps_io_gpio_inst_GPIO41 => hps_gpio_GPIO41,
hps_io_hps_io_gpio_inst_GPIO42 => hps_gpio_GPIO42,
hps_io_hps_io_gpio_inst_GPIO43 => hps_gpio_GPIO43,
hps_io_hps_io_gpio_inst_GPIO44 => hps_gpio_GPIO44,
clk_50_clk => clk50,
clk_100_clk => clk100,
reset_reset_n => hps_fpga_reset_n,
hps_0_f2h_cold_reset_req_reset_n => cnInactivated,
hps_0_f2h_debug_reset_req_reset_n => cnInactivated,
hps_0_f2h_warm_reset_req_reset_n => cnInactivated,
memory_fpga_mem_a => fpga_memory_mem_addr,
memory_fpga_mem_ba => fpga_memory_mem_ba,
memory_fpga_mem_ck => fpga_memory_mem_ck,
memory_fpga_mem_ck_n => fpga_memory_mem_ck_n,
memory_fpga_mem_cke => fpga_memory_mem_cke,
memory_fpga_mem_cs_n => fpga_memory_mem_cs_n,
memory_fpga_mem_dm => fpga_memory_mem_dm,
memory_fpga_mem_ras_n => fpga_memory_mem_ras_n,
memory_fpga_mem_cas_n => fpga_memory_mem_cas_n,
memory_fpga_mem_we_n => fpga_memory_mem_we_n,
memory_fpga_mem_reset_n => fpga_memory_mem_reset_n,
memory_fpga_mem_dq => fpga_memory_mem_dq,
memory_fpga_mem_dqs => fpga_memory_mem_dqs,
memory_fpga_mem_dqs_n => fpga_memory_mem_dqs_n,
memory_fpga_mem_odt => fpga_memory_mem_odt,
ddr3_emif_0_global_reset_reset_n => cnInactivated,
ddr3_emif_0_soft_reset_reset_n => cnInactivated,
ddr3_emif_0_afi_reset_export_reset_n => ddr3_afi_resetn,
ddr3_emif_0_pll_ref_clk_clk => fpga_clk_50,
oct_rzqin => fpga_oct_rzqin,
openmac_0_mii_txEnable => PLNK_MII_TXEN,
openmac_0_mii_txData => PLNK_MII_TXD,
openmac_0_mii_txClk => miiTxClk,
openmac_0_mii_rxError => PLNK_MII_RXERR,
openmac_0_mii_rxDataValid => PLNK_MII_RXDV,
openmac_0_mii_rxData => PLNK_MII_RXD,
openmac_0_mii_rxClk => PLNK_MII_RXCLK,
openmac_0_smi_nPhyRst => PLNK_SMI_PHYRSTN,
openmac_0_smi_clk => PLNK_SMI_CLK,
openmac_0_smi_dio => PLNK_SMI_DIO,
host_0_hps_0_h2f_gp_gp_in => h2f_gp_in,
host_0_hps_0_h2f_gp_gp_out => h2f_gp_out,
host_0_hps_0_h2f_cold_reset_reset_n => h2f_cold_reset_n,
pcp_0_cpu_resetrequest_resetrequest => not(hps_fpga_reset_n and h2f_gp_out(0)),
pcp_0_cpu_resetrequest_resettaken => h2f_gp_in(0),
pcp_0_benchmark_pio_export => open,
powerlink_led_export => pcp_led
);
-- Remove NIOS out of reset after DDR3 and PLL ready to operate
hps_fpga_reset_n <= pllLocked and ddr3_afi_resetn and h2f_cold_reset_n;
-- Select Phy Tx clock source
process(PLNK_PHY_CLK, PLNK_MII_TXCLK)
begin
case gBoardRev is
when "C" =>
miiTxClk <= PLNK_MII_TXCLK;
when "D" =>
miiTxClk <= PLNK_PHY_CLK & PLNK_PHY_CLK;
when others =>
assert (false) report "The board revision is unknown!" severity failure;
end case;
end process;
-- PLL for Qsys
pllInst : pll
port map
(
refclk => fpga_clk_50,
rst => cInactivated,
outclk_0 => clk50,
outclk_1 => clk100,
locked => pllLocked
);
end rtl;
| gpl-2.0 | aa9f3647500e54476ba57c907e4dfcb6 | 0.459349 | 3.493415 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/boards/terasic-de2i-150/common/ipcore/gxReconfig/gxReconfig.vhd | 5 | 73,627 | -- megafunction wizard: %ALTGX_RECONFIG%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: alt_c3gxb_reconfig
-- ============================================================
-- File Name: gxReconfig.vhd
-- Megafunction Name(s):
-- alt_c3gxb_reconfig
--
-- Simulation Library Files(s):
-- altera_mf;lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--alt_c3gxb_reconfig CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone IV GX" ENABLE_BUF_CAL="TRUE" NUMBER_OF_CHANNELS=4 NUMBER_OF_RECONFIG_PORTS=1 RECONFIG_FROMGXB_WIDTH=5 RECONFIG_TOGXB_WIDTH=4 busy reconfig_clk reconfig_fromgxb reconfig_togxb
--VERSION_BEGIN 13.0 cbx_alt_c3gxb_reconfig 2013:06:12:18:03:43:SJ cbx_alt_cal 2013:06:12:18:03:43:SJ cbx_alt_dprio 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_lpm_shiftreg 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END
--alt_dprio address_width=16 CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" quad_address_width=9 address busy datain dataout dpclk dpriodisable dprioin dprioload dprioout quad_address rden reset wren wren_data
--VERSION_BEGIN 13.0 cbx_alt_dprio 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_shiftreg 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 102
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY gxReconfig_alt_dprio_v5k IS
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
busy : OUT STD_LOGIC;
datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => '0');
dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
dpclk : IN STD_LOGIC;
dpriodisable : OUT STD_LOGIC;
dprioin : OUT STD_LOGIC;
dprioload : OUT STD_LOGIC;
dprioout : IN STD_LOGIC;
quad_address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
rden : IN STD_LOGIC := '0';
reset : IN STD_LOGIC := '0';
wren : IN STD_LOGIC := '0';
wren_data : IN STD_LOGIC := '0'
);
END gxReconfig_alt_dprio_v5k;
ARCHITECTURE RTL OF gxReconfig_alt_dprio_v5k IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
ATTRIBUTE ALTERA_ATTRIBUTE : string;
ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "{-to addr_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to wr_out_data_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to rd_out_data_shift_reg[13]} DPRIO_INTERFACE_REG=ON;{-to in_data_shift_reg[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[1]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[2]} DPRIO_INTERFACE_REG=ON";
SIGNAL wire_addr_shift_reg_d : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_addr_shift_reg_asdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL addr_shift_reg : STD_LOGIC_VECTOR(31 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF addr_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
SIGNAL wire_addr_shift_reg_w_q_range209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL in_data_shift_reg : STD_LOGIC_VECTOR(15 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF in_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
SIGNAL wire_rd_out_data_shift_reg_d : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_rd_out_data_shift_reg_asdata : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL rd_out_data_shift_reg : STD_LOGIC_VECTOR(15 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF rd_out_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
SIGNAL wire_rd_out_data_shift_reg_w_q_range387w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_d : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL startup_cntr : STD_LOGIC_VECTOR(2 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF startup_cntr : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
SIGNAL wire_startup_cntr_ena : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL wire_startup_cntr_w_lg_w_q_range453w458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_lg_w_q_range456w463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_lg_w_q_range456w466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_lg_w_q_range449w451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_lg_w_q_range449w465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_lg_w_q_range449w455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_lg_w_q_range456w459w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_q_range449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_q_range453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_q_range456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL state_mc_reg : STD_LOGIC_VECTOR(2 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF state_mc_reg : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_state_mc_reg_w_q_range47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_mc_reg_w_q_range66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_mc_reg_w_q_range82w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_wr_out_data_shift_reg_d : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_wr_out_data_shift_reg_asdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wr_out_data_shift_reg : STD_LOGIC_VECTOR(31 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF wr_out_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
SIGNAL wire_wr_out_data_shift_reg_w_q_range322w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pre_amble_cmpr_w_lg_w_lg_agb211w388w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pre_amble_cmpr_w_lg_w_lg_agb211w323w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pre_amble_cmpr_w_lg_agb211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pre_amble_cmpr_aeb : STD_LOGIC;
SIGNAL wire_pre_amble_cmpr_agb : STD_LOGIC;
SIGNAL wire_pre_amble_cmpr_datab : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_rd_data_output_cmpr_ageb : STD_LOGIC;
SIGNAL wire_rd_data_output_cmpr_alb : STD_LOGIC;
SIGNAL wire_rd_data_output_cmpr_datab : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_state_mc_cmpr_aeb : STD_LOGIC;
SIGNAL wire_state_mc_cmpr_datab : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_state_mc_counter_cnt_en : STD_LOGIC;
SIGNAL wire_dprio_w_lg_write_state32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_mc_counter_q : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_state_mc_decode_eq : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_dprioin_mux_dataout : STD_LOGIC;
SIGNAL wire_dprio_w_lg_w_lg_w_lg_s0_to_050w51w52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_w_lg_s1_to_069w70w71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_w_lg_s2_to_085w86w87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_w_lg_wren38w61w74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_w_lg_wren38w61w62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_w_lg_wr_addr_state210w213w214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_rd_data_output_state389w390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_wr_data_state324w325w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_s0_to_050w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_s1_to_069w70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_s2_to_085w86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_wren38w61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_wren38w39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_wren38w56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_w_lg_w_lg_rden445w446w447w448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_wr_addr_state210w213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_idle_state75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_idle_state57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_idle_state64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_idle_state41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_idle_state78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_rd_data_output_state389w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_wr_data_state324w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s0_to_050w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s0_to_149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s1_to_069w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s1_to_168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s2_to_085w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s2_to_184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_startup_done443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_startup_idle444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_wren38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_wren_data60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_w_lg_rden445w446w447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_rden36w37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_rden445w446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_rden36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_rden445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_rdinc73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_rdinc55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s0_to_153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s1_to_172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s2_to_188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_wr_addr_state210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_wren63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_wren40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_wren77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL busy_state : STD_LOGIC;
SIGNAL idle_state : STD_LOGIC;
SIGNAL rd_addr_done : STD_LOGIC;
SIGNAL rd_addr_state : STD_LOGIC;
SIGNAL rd_data_done : STD_LOGIC;
SIGNAL rd_data_input_state : STD_LOGIC;
SIGNAL rd_data_output_state : STD_LOGIC;
SIGNAL rd_data_state : STD_LOGIC;
SIGNAL rdinc : STD_LOGIC;
SIGNAL read_state : STD_LOGIC;
SIGNAL s0_to_0 : STD_LOGIC;
SIGNAL s0_to_1 : STD_LOGIC;
SIGNAL s1_to_0 : STD_LOGIC;
SIGNAL s1_to_1 : STD_LOGIC;
SIGNAL s2_to_0 : STD_LOGIC;
SIGNAL s2_to_1 : STD_LOGIC;
SIGNAL startup_done : STD_LOGIC;
SIGNAL startup_idle : STD_LOGIC;
SIGNAL wr_addr_done : STD_LOGIC;
SIGNAL wr_addr_state : STD_LOGIC;
SIGNAL wr_data_done : STD_LOGIC;
SIGNAL wr_data_state : STD_LOGIC;
SIGNAL write_state : STD_LOGIC;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT lpm_counter
GENERIC
(
lpm_avalue : STRING := "0";
lpm_direction : STRING := "DEFAULT";
lpm_modulus : NATURAL := 0;
lpm_port_updown : STRING := "PORT_CONNECTIVITY";
lpm_pvalue : STRING := "0";
lpm_svalue : STRING := "0";
lpm_width : NATURAL;
lpm_type : STRING := "lpm_counter"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aload : IN STD_LOGIC := '0';
aset : IN STD_LOGIC := '0';
cin : IN STD_LOGIC := '1';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
cnt_en : IN STD_LOGIC := '1';
cout : OUT STD_LOGIC;
data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
eq : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
sclr : IN STD_LOGIC := '0';
sload : IN STD_LOGIC := '0';
sset : IN STD_LOGIC := '0';
updown : IN STD_LOGIC := '1'
);
END COMPONENT;
COMPONENT lpm_decode
GENERIC
(
LPM_DECODES : NATURAL;
LPM_PIPELINE : NATURAL := 0;
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_decode"
);
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
enable : IN STD_LOGIC := '1';
eq : OUT STD_LOGIC_VECTOR(LPM_DECODES-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
wire_dprio_w_lg_w_lg_w_lg_s0_to_050w51w52w(0) <= wire_dprio_w_lg_w_lg_s0_to_050w51w(0) AND wire_state_mc_reg_w_q_range47w(0);
wire_dprio_w_lg_w_lg_w_lg_s1_to_069w70w71w(0) <= wire_dprio_w_lg_w_lg_s1_to_069w70w(0) AND wire_state_mc_reg_w_q_range66w(0);
wire_dprio_w_lg_w_lg_w_lg_s2_to_085w86w87w(0) <= wire_dprio_w_lg_w_lg_s2_to_085w86w(0) AND wire_state_mc_reg_w_q_range82w(0);
wire_dprio_w_lg_w_lg_w_lg_wren38w61w74w(0) <= wire_dprio_w_lg_w_lg_wren38w61w(0) AND wire_dprio_w_lg_rdinc73w(0);
wire_dprio_w_lg_w_lg_w_lg_wren38w61w62w(0) <= wire_dprio_w_lg_w_lg_wren38w61w(0) AND rden;
wire_dprio_w_lg_w_lg_w_lg_wr_addr_state210w213w214w(0) <= wire_dprio_w_lg_w_lg_wr_addr_state210w213w(0) AND wire_pre_amble_cmpr_agb;
wire_dprio_w_lg_w_lg_rd_data_output_state389w390w(0) <= wire_dprio_w_lg_rd_data_output_state389w(0) AND wire_pre_amble_cmpr_agb;
wire_dprio_w_lg_w_lg_wr_data_state324w325w(0) <= wire_dprio_w_lg_wr_data_state324w(0) AND wire_pre_amble_cmpr_agb;
wire_dprio_w_lg_w_lg_s0_to_050w51w(0) <= wire_dprio_w_lg_s0_to_050w(0) AND wire_dprio_w_lg_s0_to_149w(0);
wire_dprio_w_lg_w_lg_s1_to_069w70w(0) <= wire_dprio_w_lg_s1_to_069w(0) AND wire_dprio_w_lg_s1_to_168w(0);
wire_dprio_w_lg_w_lg_s2_to_085w86w(0) <= wire_dprio_w_lg_s2_to_085w(0) AND wire_dprio_w_lg_s2_to_184w(0);
wire_dprio_w_lg_w_lg_wren38w61w(0) <= wire_dprio_w_lg_wren38w(0) AND wire_dprio_w_lg_wren_data60w(0);
wire_dprio_w_lg_w_lg_wren38w39w(0) <= wire_dprio_w_lg_wren38w(0) AND wire_dprio_w_lg_w_lg_rden36w37w(0);
wire_dprio_w_lg_w_lg_wren38w56w(0) <= wire_dprio_w_lg_wren38w(0) AND wire_dprio_w_lg_rdinc55w(0);
wire_dprio_w_lg_w_lg_w_lg_w_lg_rden445w446w447w448w(0) <= wire_dprio_w_lg_w_lg_w_lg_rden445w446w447w(0) AND wire_dprio_w_lg_startup_done443w(0);
wire_dprio_w_lg_w_lg_wr_addr_state210w213w(0) <= wire_dprio_w_lg_wr_addr_state210w(0) AND wire_addr_shift_reg_w_q_range209w(0);
wire_dprio_w_lg_idle_state75w(0) <= idle_state AND wire_dprio_w_lg_w_lg_w_lg_wren38w61w74w(0);
wire_dprio_w_lg_idle_state57w(0) <= idle_state AND wire_dprio_w_lg_w_lg_wren38w56w(0);
wire_dprio_w_lg_idle_state64w(0) <= idle_state AND wire_dprio_w_lg_wren63w(0);
wire_dprio_w_lg_idle_state41w(0) <= idle_state AND wire_dprio_w_lg_wren40w(0);
wire_dprio_w_lg_idle_state78w(0) <= idle_state AND wire_dprio_w_lg_wren77w(0);
wire_dprio_w_lg_rd_data_output_state389w(0) <= rd_data_output_state AND wire_rd_out_data_shift_reg_w_q_range387w(0);
wire_dprio_w_lg_wr_data_state324w(0) <= wr_data_state AND wire_wr_out_data_shift_reg_w_q_range322w(0);
wire_dprio_w_lg_s0_to_050w(0) <= NOT s0_to_0;
wire_dprio_w_lg_s0_to_149w(0) <= NOT s0_to_1;
wire_dprio_w_lg_s1_to_069w(0) <= NOT s1_to_0;
wire_dprio_w_lg_s1_to_168w(0) <= NOT s1_to_1;
wire_dprio_w_lg_s2_to_085w(0) <= NOT s2_to_0;
wire_dprio_w_lg_s2_to_184w(0) <= NOT s2_to_1;
wire_dprio_w_lg_startup_done443w(0) <= NOT startup_done;
wire_dprio_w_lg_startup_idle444w(0) <= NOT startup_idle;
wire_dprio_w_lg_wren38w(0) <= NOT wren;
wire_dprio_w_lg_wren_data60w(0) <= NOT wren_data;
wire_dprio_w_lg_w_lg_w_lg_rden445w446w447w(0) <= wire_dprio_w_lg_w_lg_rden445w446w(0) OR wire_dprio_w_lg_startup_idle444w(0);
wire_dprio_w_lg_w_lg_rden36w37w(0) <= wire_dprio_w_lg_rden36w(0) OR wren_data;
wire_dprio_w_lg_w_lg_rden445w446w(0) <= wire_dprio_w_lg_rden445w(0) OR rdinc;
wire_dprio_w_lg_rden36w(0) <= rden OR rdinc;
wire_dprio_w_lg_rden445w(0) <= rden OR wren;
wire_dprio_w_lg_rdinc73w(0) <= rdinc OR rden;
wire_dprio_w_lg_rdinc55w(0) <= rdinc OR wren_data;
wire_dprio_w_lg_s0_to_153w(0) <= s0_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s0_to_050w51w52w(0);
wire_dprio_w_lg_s1_to_172w(0) <= s1_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s1_to_069w70w71w(0);
wire_dprio_w_lg_s2_to_188w(0) <= s2_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s2_to_085w86w87w(0);
wire_dprio_w_lg_wr_addr_state210w(0) <= wr_addr_state OR rd_addr_state;
wire_dprio_w_lg_wren63w(0) <= wren OR wire_dprio_w_lg_w_lg_w_lg_wren38w61w62w(0);
wire_dprio_w_lg_wren40w(0) <= wren OR wire_dprio_w_lg_w_lg_wren38w39w(0);
wire_dprio_w_lg_wren77w(0) <= wren OR wren_data;
busy <= busy_state;
busy_state <= (write_state OR read_state);
dataout <= in_data_shift_reg;
dpriodisable <= (NOT wire_startup_cntr_w_lg_w_q_range456w466w(0));
dprioin <= wire_dprioin_mux_dataout;
dprioload <= (NOT (wire_startup_cntr_w_lg_w_q_range449w455w(0) AND (NOT startup_cntr(2))));
idle_state <= wire_state_mc_decode_eq(0);
rd_addr_done <= (rd_addr_state AND wire_state_mc_cmpr_aeb);
rd_addr_state <= (wire_state_mc_decode_eq(5) AND startup_done);
rd_data_done <= (rd_data_state AND wire_state_mc_cmpr_aeb);
rd_data_input_state <= (wire_rd_data_output_cmpr_ageb AND rd_data_state);
rd_data_output_state <= (wire_rd_data_output_cmpr_alb AND rd_data_state);
rd_data_state <= (wire_state_mc_decode_eq(7) AND startup_done);
rdinc <= '0';
read_state <= (rd_addr_state OR rd_data_state);
s0_to_0 <= ((wr_data_state AND wr_data_done) OR (rd_data_state AND rd_data_done));
s0_to_1 <= ((wire_dprio_w_lg_idle_state41w(0) OR (wr_addr_state AND wr_addr_done)) OR (rd_addr_state AND rd_addr_done));
s1_to_0 <= (((wr_data_state AND wr_data_done) OR (rd_data_state AND rd_data_done)) OR wire_dprio_w_lg_idle_state64w(0));
s1_to_1 <= ((wire_dprio_w_lg_idle_state57w(0) OR (wr_addr_state AND wr_addr_done)) OR (rd_addr_state AND rd_addr_done));
s2_to_0 <= ((((wr_addr_state AND wr_addr_done) OR (wr_data_state AND wr_data_done)) OR (rd_data_state AND rd_data_done)) OR wire_dprio_w_lg_idle_state78w(0));
s2_to_1 <= (wire_dprio_w_lg_idle_state75w(0) OR (rd_addr_state AND rd_addr_done));
startup_done <= (wire_startup_cntr_w_lg_w_q_range456w463w(0) AND startup_cntr(1));
startup_idle <= (wire_startup_cntr_w_lg_w_q_range449w451w(0) AND (NOT (startup_cntr(2) XOR startup_cntr(1))));
wr_addr_done <= (wr_addr_state AND wire_state_mc_cmpr_aeb);
wr_addr_state <= (wire_state_mc_decode_eq(1) AND startup_done);
wr_data_done <= (wr_data_state AND wire_state_mc_cmpr_aeb);
wr_data_state <= (wire_state_mc_decode_eq(3) AND startup_done);
write_state <= (wr_addr_state OR wr_data_state);
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(0) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(0) <= wire_addr_shift_reg_asdata(0);
ELSE addr_shift_reg(0) <= wire_addr_shift_reg_d(0);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(1) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(1) <= wire_addr_shift_reg_asdata(1);
ELSE addr_shift_reg(1) <= wire_addr_shift_reg_d(1);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(2) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(2) <= wire_addr_shift_reg_asdata(2);
ELSE addr_shift_reg(2) <= wire_addr_shift_reg_d(2);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(3) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(3) <= wire_addr_shift_reg_asdata(3);
ELSE addr_shift_reg(3) <= wire_addr_shift_reg_d(3);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(4) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(4) <= wire_addr_shift_reg_asdata(4);
ELSE addr_shift_reg(4) <= wire_addr_shift_reg_d(4);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(5) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(5) <= wire_addr_shift_reg_asdata(5);
ELSE addr_shift_reg(5) <= wire_addr_shift_reg_d(5);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(6) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(6) <= wire_addr_shift_reg_asdata(6);
ELSE addr_shift_reg(6) <= wire_addr_shift_reg_d(6);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(7) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(7) <= wire_addr_shift_reg_asdata(7);
ELSE addr_shift_reg(7) <= wire_addr_shift_reg_d(7);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(8) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(8) <= wire_addr_shift_reg_asdata(8);
ELSE addr_shift_reg(8) <= wire_addr_shift_reg_d(8);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(9) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(9) <= wire_addr_shift_reg_asdata(9);
ELSE addr_shift_reg(9) <= wire_addr_shift_reg_d(9);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(10) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(10) <= wire_addr_shift_reg_asdata(10);
ELSE addr_shift_reg(10) <= wire_addr_shift_reg_d(10);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(11) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(11) <= wire_addr_shift_reg_asdata(11);
ELSE addr_shift_reg(11) <= wire_addr_shift_reg_d(11);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(12) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(12) <= wire_addr_shift_reg_asdata(12);
ELSE addr_shift_reg(12) <= wire_addr_shift_reg_d(12);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(13) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(13) <= wire_addr_shift_reg_asdata(13);
ELSE addr_shift_reg(13) <= wire_addr_shift_reg_d(13);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(14) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(14) <= wire_addr_shift_reg_asdata(14);
ELSE addr_shift_reg(14) <= wire_addr_shift_reg_d(14);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(15) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(15) <= wire_addr_shift_reg_asdata(15);
ELSE addr_shift_reg(15) <= wire_addr_shift_reg_d(15);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(16) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(16) <= wire_addr_shift_reg_asdata(16);
ELSE addr_shift_reg(16) <= wire_addr_shift_reg_d(16);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(17) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(17) <= wire_addr_shift_reg_asdata(17);
ELSE addr_shift_reg(17) <= wire_addr_shift_reg_d(17);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(18) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(18) <= wire_addr_shift_reg_asdata(18);
ELSE addr_shift_reg(18) <= wire_addr_shift_reg_d(18);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(19) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(19) <= wire_addr_shift_reg_asdata(19);
ELSE addr_shift_reg(19) <= wire_addr_shift_reg_d(19);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(20) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(20) <= wire_addr_shift_reg_asdata(20);
ELSE addr_shift_reg(20) <= wire_addr_shift_reg_d(20);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(21) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(21) <= wire_addr_shift_reg_asdata(21);
ELSE addr_shift_reg(21) <= wire_addr_shift_reg_d(21);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(22) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(22) <= wire_addr_shift_reg_asdata(22);
ELSE addr_shift_reg(22) <= wire_addr_shift_reg_d(22);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(23) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(23) <= wire_addr_shift_reg_asdata(23);
ELSE addr_shift_reg(23) <= wire_addr_shift_reg_d(23);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(24) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(24) <= wire_addr_shift_reg_asdata(24);
ELSE addr_shift_reg(24) <= wire_addr_shift_reg_d(24);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(25) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(25) <= wire_addr_shift_reg_asdata(25);
ELSE addr_shift_reg(25) <= wire_addr_shift_reg_d(25);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(26) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(26) <= wire_addr_shift_reg_asdata(26);
ELSE addr_shift_reg(26) <= wire_addr_shift_reg_d(26);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(27) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(27) <= wire_addr_shift_reg_asdata(27);
ELSE addr_shift_reg(27) <= wire_addr_shift_reg_d(27);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(28) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(28) <= wire_addr_shift_reg_asdata(28);
ELSE addr_shift_reg(28) <= wire_addr_shift_reg_d(28);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(29) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(29) <= wire_addr_shift_reg_asdata(29);
ELSE addr_shift_reg(29) <= wire_addr_shift_reg_d(29);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(30) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(30) <= wire_addr_shift_reg_asdata(30);
ELSE addr_shift_reg(30) <= wire_addr_shift_reg_d(30);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(31) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(31) <= wire_addr_shift_reg_asdata(31);
ELSE addr_shift_reg(31) <= wire_addr_shift_reg_d(31);
END IF;
END IF;
END PROCESS;
wire_addr_shift_reg_asdata <= ( "00" & "00" & "0" & quad_address(8 DOWNTO 0) & "10" & address);
wire_addr_shift_reg_d <= ( addr_shift_reg(30 DOWNTO 0) & "0");
wire_addr_shift_reg_w_q_range209w(0) <= addr_shift_reg(31);
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN in_data_shift_reg <= (OTHERS => '0');
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (rd_data_input_state = '1') THEN in_data_shift_reg <= ( in_data_shift_reg(14 DOWNTO 0) & dprioout);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(0) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(0) <= wire_rd_out_data_shift_reg_asdata(0);
ELSE rd_out_data_shift_reg(0) <= wire_rd_out_data_shift_reg_d(0);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(1) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(1) <= wire_rd_out_data_shift_reg_asdata(1);
ELSE rd_out_data_shift_reg(1) <= wire_rd_out_data_shift_reg_d(1);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(2) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(2) <= wire_rd_out_data_shift_reg_asdata(2);
ELSE rd_out_data_shift_reg(2) <= wire_rd_out_data_shift_reg_d(2);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(3) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(3) <= wire_rd_out_data_shift_reg_asdata(3);
ELSE rd_out_data_shift_reg(3) <= wire_rd_out_data_shift_reg_d(3);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(4) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(4) <= wire_rd_out_data_shift_reg_asdata(4);
ELSE rd_out_data_shift_reg(4) <= wire_rd_out_data_shift_reg_d(4);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(5) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(5) <= wire_rd_out_data_shift_reg_asdata(5);
ELSE rd_out_data_shift_reg(5) <= wire_rd_out_data_shift_reg_d(5);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(6) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(6) <= wire_rd_out_data_shift_reg_asdata(6);
ELSE rd_out_data_shift_reg(6) <= wire_rd_out_data_shift_reg_d(6);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(7) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(7) <= wire_rd_out_data_shift_reg_asdata(7);
ELSE rd_out_data_shift_reg(7) <= wire_rd_out_data_shift_reg_d(7);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(8) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(8) <= wire_rd_out_data_shift_reg_asdata(8);
ELSE rd_out_data_shift_reg(8) <= wire_rd_out_data_shift_reg_d(8);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(9) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(9) <= wire_rd_out_data_shift_reg_asdata(9);
ELSE rd_out_data_shift_reg(9) <= wire_rd_out_data_shift_reg_d(9);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(10) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(10) <= wire_rd_out_data_shift_reg_asdata(10);
ELSE rd_out_data_shift_reg(10) <= wire_rd_out_data_shift_reg_d(10);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(11) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(11) <= wire_rd_out_data_shift_reg_asdata(11);
ELSE rd_out_data_shift_reg(11) <= wire_rd_out_data_shift_reg_d(11);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(12) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(12) <= wire_rd_out_data_shift_reg_asdata(12);
ELSE rd_out_data_shift_reg(12) <= wire_rd_out_data_shift_reg_d(12);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(13) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(13) <= wire_rd_out_data_shift_reg_asdata(13);
ELSE rd_out_data_shift_reg(13) <= wire_rd_out_data_shift_reg_d(13);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(14) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(14) <= wire_rd_out_data_shift_reg_asdata(14);
ELSE rd_out_data_shift_reg(14) <= wire_rd_out_data_shift_reg_d(14);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(15) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(15) <= wire_rd_out_data_shift_reg_asdata(15);
ELSE rd_out_data_shift_reg(15) <= wire_rd_out_data_shift_reg_d(15);
END IF;
END IF;
END PROCESS;
wire_rd_out_data_shift_reg_asdata <= ( "00" & "1" & "1" & "0" & quad_address & "10");
wire_rd_out_data_shift_reg_d <= ( rd_out_data_shift_reg(14 DOWNTO 0) & "0");
wire_rd_out_data_shift_reg_w_q_range387w(0) <= rd_out_data_shift_reg(15);
PROCESS (dpclk)
BEGIN
IF (dpclk = '1' AND dpclk'event) THEN
IF (wire_startup_cntr_ena(0) = '1') THEN
IF (reset = '1') THEN startup_cntr(0) <= '0';
ELSE startup_cntr(0) <= wire_startup_cntr_d(0);
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (dpclk)
BEGIN
IF (dpclk = '1' AND dpclk'event) THEN
IF (wire_startup_cntr_ena(1) = '1') THEN
IF (reset = '1') THEN startup_cntr(1) <= '0';
ELSE startup_cntr(1) <= wire_startup_cntr_d(1);
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (dpclk)
BEGIN
IF (dpclk = '1' AND dpclk'event) THEN
IF (wire_startup_cntr_ena(2) = '1') THEN
IF (reset = '1') THEN startup_cntr(2) <= '0';
ELSE startup_cntr(2) <= wire_startup_cntr_d(2);
END IF;
END IF;
END IF;
END PROCESS;
wire_startup_cntr_d <= ( wire_startup_cntr_w_lg_w_q_range456w459w & wire_startup_cntr_w_lg_w_q_range449w455w & wire_startup_cntr_w_lg_w_q_range449w451w);
loop0 : FOR i IN 0 TO 2 GENERATE
wire_startup_cntr_ena(i) <= wire_dprio_w_lg_w_lg_w_lg_w_lg_rden445w446w447w448w(0);
END GENERATE loop0;
wire_startup_cntr_w_lg_w_q_range453w458w(0) <= wire_startup_cntr_w_q_range453w(0) AND wire_startup_cntr_w_q_range449w(0);
wire_startup_cntr_w_lg_w_q_range456w463w(0) <= wire_startup_cntr_w_q_range456w(0) AND wire_startup_cntr_w_lg_w_q_range449w451w(0);
wire_startup_cntr_w_lg_w_q_range456w466w(0) <= wire_startup_cntr_w_q_range456w(0) AND wire_startup_cntr_w_lg_w_q_range449w465w(0);
wire_startup_cntr_w_lg_w_q_range449w451w(0) <= NOT wire_startup_cntr_w_q_range449w(0);
wire_startup_cntr_w_lg_w_q_range449w465w(0) <= wire_startup_cntr_w_q_range449w(0) OR wire_startup_cntr_w_q_range453w(0);
wire_startup_cntr_w_lg_w_q_range449w455w(0) <= wire_startup_cntr_w_q_range449w(0) XOR wire_startup_cntr_w_q_range453w(0);
wire_startup_cntr_w_lg_w_q_range456w459w(0) <= wire_startup_cntr_w_q_range456w(0) XOR wire_startup_cntr_w_lg_w_q_range453w458w(0);
wire_startup_cntr_w_q_range449w(0) <= startup_cntr(0);
wire_startup_cntr_w_q_range453w(0) <= startup_cntr(1);
wire_startup_cntr_w_q_range456w(0) <= startup_cntr(2);
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN state_mc_reg <= (OTHERS => '0');
ELSIF (dpclk = '1' AND dpclk'event) THEN state_mc_reg <= ( wire_dprio_w_lg_s2_to_188w & wire_dprio_w_lg_s1_to_172w & wire_dprio_w_lg_s0_to_153w);
END IF;
END PROCESS;
wire_state_mc_reg_w_q_range47w(0) <= state_mc_reg(0);
wire_state_mc_reg_w_q_range66w(0) <= state_mc_reg(1);
wire_state_mc_reg_w_q_range82w(0) <= state_mc_reg(2);
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(0) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(0) <= wire_wr_out_data_shift_reg_asdata(0);
ELSE wr_out_data_shift_reg(0) <= wire_wr_out_data_shift_reg_d(0);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(1) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(1) <= wire_wr_out_data_shift_reg_asdata(1);
ELSE wr_out_data_shift_reg(1) <= wire_wr_out_data_shift_reg_d(1);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(2) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(2) <= wire_wr_out_data_shift_reg_asdata(2);
ELSE wr_out_data_shift_reg(2) <= wire_wr_out_data_shift_reg_d(2);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(3) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(3) <= wire_wr_out_data_shift_reg_asdata(3);
ELSE wr_out_data_shift_reg(3) <= wire_wr_out_data_shift_reg_d(3);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(4) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(4) <= wire_wr_out_data_shift_reg_asdata(4);
ELSE wr_out_data_shift_reg(4) <= wire_wr_out_data_shift_reg_d(4);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(5) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(5) <= wire_wr_out_data_shift_reg_asdata(5);
ELSE wr_out_data_shift_reg(5) <= wire_wr_out_data_shift_reg_d(5);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(6) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(6) <= wire_wr_out_data_shift_reg_asdata(6);
ELSE wr_out_data_shift_reg(6) <= wire_wr_out_data_shift_reg_d(6);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(7) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(7) <= wire_wr_out_data_shift_reg_asdata(7);
ELSE wr_out_data_shift_reg(7) <= wire_wr_out_data_shift_reg_d(7);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(8) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(8) <= wire_wr_out_data_shift_reg_asdata(8);
ELSE wr_out_data_shift_reg(8) <= wire_wr_out_data_shift_reg_d(8);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(9) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(9) <= wire_wr_out_data_shift_reg_asdata(9);
ELSE wr_out_data_shift_reg(9) <= wire_wr_out_data_shift_reg_d(9);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(10) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(10) <= wire_wr_out_data_shift_reg_asdata(10);
ELSE wr_out_data_shift_reg(10) <= wire_wr_out_data_shift_reg_d(10);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(11) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(11) <= wire_wr_out_data_shift_reg_asdata(11);
ELSE wr_out_data_shift_reg(11) <= wire_wr_out_data_shift_reg_d(11);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(12) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(12) <= wire_wr_out_data_shift_reg_asdata(12);
ELSE wr_out_data_shift_reg(12) <= wire_wr_out_data_shift_reg_d(12);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(13) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(13) <= wire_wr_out_data_shift_reg_asdata(13);
ELSE wr_out_data_shift_reg(13) <= wire_wr_out_data_shift_reg_d(13);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(14) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(14) <= wire_wr_out_data_shift_reg_asdata(14);
ELSE wr_out_data_shift_reg(14) <= wire_wr_out_data_shift_reg_d(14);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(15) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(15) <= wire_wr_out_data_shift_reg_asdata(15);
ELSE wr_out_data_shift_reg(15) <= wire_wr_out_data_shift_reg_d(15);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(16) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(16) <= wire_wr_out_data_shift_reg_asdata(16);
ELSE wr_out_data_shift_reg(16) <= wire_wr_out_data_shift_reg_d(16);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(17) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(17) <= wire_wr_out_data_shift_reg_asdata(17);
ELSE wr_out_data_shift_reg(17) <= wire_wr_out_data_shift_reg_d(17);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(18) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(18) <= wire_wr_out_data_shift_reg_asdata(18);
ELSE wr_out_data_shift_reg(18) <= wire_wr_out_data_shift_reg_d(18);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(19) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(19) <= wire_wr_out_data_shift_reg_asdata(19);
ELSE wr_out_data_shift_reg(19) <= wire_wr_out_data_shift_reg_d(19);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(20) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(20) <= wire_wr_out_data_shift_reg_asdata(20);
ELSE wr_out_data_shift_reg(20) <= wire_wr_out_data_shift_reg_d(20);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(21) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(21) <= wire_wr_out_data_shift_reg_asdata(21);
ELSE wr_out_data_shift_reg(21) <= wire_wr_out_data_shift_reg_d(21);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(22) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(22) <= wire_wr_out_data_shift_reg_asdata(22);
ELSE wr_out_data_shift_reg(22) <= wire_wr_out_data_shift_reg_d(22);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(23) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(23) <= wire_wr_out_data_shift_reg_asdata(23);
ELSE wr_out_data_shift_reg(23) <= wire_wr_out_data_shift_reg_d(23);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(24) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(24) <= wire_wr_out_data_shift_reg_asdata(24);
ELSE wr_out_data_shift_reg(24) <= wire_wr_out_data_shift_reg_d(24);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(25) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(25) <= wire_wr_out_data_shift_reg_asdata(25);
ELSE wr_out_data_shift_reg(25) <= wire_wr_out_data_shift_reg_d(25);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(26) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(26) <= wire_wr_out_data_shift_reg_asdata(26);
ELSE wr_out_data_shift_reg(26) <= wire_wr_out_data_shift_reg_d(26);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(27) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(27) <= wire_wr_out_data_shift_reg_asdata(27);
ELSE wr_out_data_shift_reg(27) <= wire_wr_out_data_shift_reg_d(27);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(28) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(28) <= wire_wr_out_data_shift_reg_asdata(28);
ELSE wr_out_data_shift_reg(28) <= wire_wr_out_data_shift_reg_d(28);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(29) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(29) <= wire_wr_out_data_shift_reg_asdata(29);
ELSE wr_out_data_shift_reg(29) <= wire_wr_out_data_shift_reg_d(29);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(30) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(30) <= wire_wr_out_data_shift_reg_asdata(30);
ELSE wr_out_data_shift_reg(30) <= wire_wr_out_data_shift_reg_d(30);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(31) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(31) <= wire_wr_out_data_shift_reg_asdata(31);
ELSE wr_out_data_shift_reg(31) <= wire_wr_out_data_shift_reg_d(31);
END IF;
END IF;
END PROCESS;
wire_wr_out_data_shift_reg_asdata <= ( "00" & "01" & "0" & quad_address(8 DOWNTO 0) & "10" & datain);
wire_wr_out_data_shift_reg_d <= ( wr_out_data_shift_reg(30 DOWNTO 0) & "0");
wire_wr_out_data_shift_reg_w_q_range322w(0) <= wr_out_data_shift_reg(31);
wire_pre_amble_cmpr_w_lg_w_lg_agb211w388w(0) <= wire_pre_amble_cmpr_w_lg_agb211w(0) AND rd_data_output_state;
wire_pre_amble_cmpr_w_lg_w_lg_agb211w323w(0) <= wire_pre_amble_cmpr_w_lg_agb211w(0) AND wr_data_state;
wire_pre_amble_cmpr_w_lg_agb211w(0) <= NOT wire_pre_amble_cmpr_agb;
wire_pre_amble_cmpr_datab <= "011111";
pre_amble_cmpr : lpm_compare
GENERIC MAP (
LPM_WIDTH => 6
)
PORT MAP (
aeb => wire_pre_amble_cmpr_aeb,
agb => wire_pre_amble_cmpr_agb,
dataa => wire_state_mc_counter_q,
datab => wire_pre_amble_cmpr_datab
);
wire_rd_data_output_cmpr_datab <= "110000";
rd_data_output_cmpr : lpm_compare
GENERIC MAP (
LPM_WIDTH => 6
)
PORT MAP (
ageb => wire_rd_data_output_cmpr_ageb,
alb => wire_rd_data_output_cmpr_alb,
dataa => wire_state_mc_counter_q,
datab => wire_rd_data_output_cmpr_datab
);
wire_state_mc_cmpr_datab <= (OTHERS => '1');
state_mc_cmpr : lpm_compare
GENERIC MAP (
LPM_WIDTH => 6
)
PORT MAP (
aeb => wire_state_mc_cmpr_aeb,
dataa => wire_state_mc_counter_q,
datab => wire_state_mc_cmpr_datab
);
wire_state_mc_counter_cnt_en <= wire_dprio_w_lg_write_state32w(0);
wire_dprio_w_lg_write_state32w(0) <= write_state OR read_state;
state_mc_counter : lpm_counter
GENERIC MAP (
lpm_port_updown => "PORT_UNUSED",
lpm_width => 6
)
PORT MAP (
clock => dpclk,
cnt_en => wire_state_mc_counter_cnt_en,
q => wire_state_mc_counter_q,
sclr => reset
);
state_mc_decode : lpm_decode
GENERIC MAP (
LPM_DECODES => 8,
LPM_WIDTH => 3
)
PORT MAP (
data => state_mc_reg,
eq => wire_state_mc_decode_eq
);
wire_dprioin_mux_dataout <= (((wire_dprio_w_lg_w_lg_w_lg_wr_addr_state210w213w214w(0) OR (wire_pre_amble_cmpr_w_lg_agb211w(0) AND wire_dprio_w_lg_wr_addr_state210w(0))) OR (wire_dprio_w_lg_w_lg_wr_data_state324w325w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb211w323w(0))) OR (wire_dprio_w_lg_w_lg_rd_data_output_state389w390w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb211w388w(0))) OR NOT(((write_state OR rd_addr_state) OR rd_data_output_state));
END RTL; --gxReconfig_alt_dprio_v5k
LIBRARY altera_mf;
USE altera_mf.all;
--synthesis_resources = alt_cal_c3gxb 1 lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 114
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY gxReconfig_alt_c3gxb_reconfig_qrm IS
PORT
(
busy : OUT STD_LOGIC;
reconfig_clk : IN STD_LOGIC;
reconfig_fromgxb : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END gxReconfig_alt_c3gxb_reconfig_qrm;
ARCHITECTURE RTL OF gxReconfig_alt_c3gxb_reconfig_qrm IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
ATTRIBUTE ALTERA_ATTRIBUTE : string;
ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "{-to address_pres_reg[11]} DPRIO_CHANNEL_NUM=11;{-to address_pres_reg[10]} DPRIO_CHANNEL_NUM=10;{-to address_pres_reg[9]} DPRIO_CHANNEL_NUM=9;{-to address_pres_reg[8]} DPRIO_CHANNEL_NUM=8;{-to address_pres_reg[7]} DPRIO_CHANNEL_NUM=7;{-to address_pres_reg[6]} DPRIO_CHANNEL_NUM=6;{-to address_pres_reg[5]} DPRIO_CHANNEL_NUM=5;{-to address_pres_reg[4]} DPRIO_CHANNEL_NUM=4;{-to address_pres_reg[3]} DPRIO_CHANNEL_NUM=3;{-to address_pres_reg[2]} DPRIO_CHANNEL_NUM=2;{-to address_pres_reg[1]} DPRIO_CHANNEL_NUM=1;{-to address_pres_reg[0]} DPRIO_CHANNEL_NUM=0";
SIGNAL wire_calibration_c3gxb_w_lg_busy8w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_calibration_c3gxb_w_lg_busy7w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_calibration_c3gxb_busy : STD_LOGIC;
SIGNAL wire_calibration_c3gxb_dprio_addr : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_calibration_c3gxb_dprio_dataout : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_calibration_c3gxb_dprio_rden : STD_LOGIC;
SIGNAL wire_calibration_c3gxb_dprio_wren : STD_LOGIC;
SIGNAL wire_calibration_c3gxb_quad_addr : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_calibration_c3gxb_reset : STD_LOGIC;
SIGNAL wire_w_lg_offset_cancellation_reset5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_calibration_c3gxb_retain_addr : STD_LOGIC;
SIGNAL wire_dprio_address : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_dprio_busy : STD_LOGIC;
SIGNAL wire_dprio_datain : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_dprio_dataout : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_dprio_dpriodisable : STD_LOGIC;
SIGNAL wire_dprio_dprioin : STD_LOGIC;
SIGNAL wire_dprio_dprioload : STD_LOGIC;
SIGNAL wire_dprio_rden : STD_LOGIC;
SIGNAL wire_calibration_c3gxb_w_lg_busy9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_wren : STD_LOGIC;
SIGNAL wire_calibration_c3gxb_w_lg_busy10w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL address_pres_reg : STD_LOGIC_VECTOR(11 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF address_pres_reg : SIGNAL IS "PRESERVE_REGISTER=ON";
SIGNAL cal_busy : STD_LOGIC;
SIGNAL cal_dprioout_wire : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL cal_testbuses : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL channel_address : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL dprio_address : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL offset_cancellation_reset : STD_LOGIC;
SIGNAL quad_address : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL reconfig_reset_all : STD_LOGIC;
COMPONENT alt_cal_c3gxb
GENERIC
(
CHANNEL_ADDRESS_WIDTH : NATURAL := 1;
NUMBER_OF_CHANNELS : NATURAL;
SIM_MODEL_MODE : STRING := "FALSE";
lpm_type : STRING := "alt_cal_c3gxb"
);
PORT
(
busy : OUT STD_LOGIC;
cal_error : OUT STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS-1 DOWNTO 0);
clock : IN STD_LOGIC;
dprio_addr : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
dprio_busy : IN STD_LOGIC;
dprio_datain : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dprio_dataout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
dprio_rden : OUT STD_LOGIC;
dprio_wren : OUT STD_LOGIC;
quad_addr : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
remap_addr : IN STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
reset : IN STD_LOGIC := '0';
retain_addr : OUT STD_LOGIC;
start : IN STD_LOGIC := '0';
testbuses : IN STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT gxReconfig_alt_dprio_v5k
PORT
(
address : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
busy : OUT STD_LOGIC;
datain : IN STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
dataout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
dpclk : IN STD_LOGIC;
dpriodisable : OUT STD_LOGIC;
dprioin : OUT STD_LOGIC;
dprioload : OUT STD_LOGIC;
dprioout : IN STD_LOGIC;
quad_address : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
rden : IN STD_LOGIC := '0';
reset : IN STD_LOGIC := '0';
wren : IN STD_LOGIC := '0';
wren_data : IN STD_LOGIC := '0'
);
END COMPONENT;
BEGIN
busy <= cal_busy;
cal_busy <= wire_calibration_c3gxb_busy;
cal_dprioout_wire(0) <= ( reconfig_fromgxb(0));
cal_testbuses <= ( reconfig_fromgxb(4 DOWNTO 1));
channel_address <= wire_calibration_c3gxb_dprio_addr(14 DOWNTO 12);
dprio_address <= ( wire_calibration_c3gxb_dprio_addr(15) & address_pres_reg(2 DOWNTO 0) & wire_calibration_c3gxb_dprio_addr(11 DOWNTO 0));
offset_cancellation_reset <= '0';
quad_address <= wire_calibration_c3gxb_quad_addr;
reconfig_reset_all <= '0';
reconfig_togxb <= ( wire_calibration_c3gxb_busy & wire_dprio_dprioload & wire_dprio_dpriodisable & wire_dprio_dprioin);
loop1 : FOR i IN 0 TO 15 GENERATE
wire_calibration_c3gxb_w_lg_busy8w(i) <= wire_calibration_c3gxb_busy AND dprio_address(i);
END GENERATE loop1;
loop2 : FOR i IN 0 TO 15 GENERATE
wire_calibration_c3gxb_w_lg_busy7w(i) <= wire_calibration_c3gxb_busy AND wire_calibration_c3gxb_dprio_dataout(i);
END GENERATE loop2;
wire_calibration_c3gxb_reset <= wire_w_lg_offset_cancellation_reset5w(0);
wire_w_lg_offset_cancellation_reset5w(0) <= offset_cancellation_reset OR reconfig_reset_all;
calibration_c3gxb : alt_cal_c3gxb
GENERIC MAP (
CHANNEL_ADDRESS_WIDTH => 2,
NUMBER_OF_CHANNELS => 4,
SIM_MODEL_MODE => "FALSE"
)
PORT MAP (
busy => wire_calibration_c3gxb_busy,
clock => reconfig_clk,
dprio_addr => wire_calibration_c3gxb_dprio_addr,
dprio_busy => wire_dprio_busy,
dprio_datain => wire_dprio_dataout,
dprio_dataout => wire_calibration_c3gxb_dprio_dataout,
dprio_rden => wire_calibration_c3gxb_dprio_rden,
dprio_wren => wire_calibration_c3gxb_dprio_wren,
quad_addr => wire_calibration_c3gxb_quad_addr,
remap_addr => address_pres_reg,
reset => wire_calibration_c3gxb_reset,
retain_addr => wire_calibration_c3gxb_retain_addr,
testbuses => cal_testbuses
);
wire_dprio_address <= wire_calibration_c3gxb_w_lg_busy8w;
wire_dprio_datain <= wire_calibration_c3gxb_w_lg_busy7w;
wire_dprio_rden <= wire_calibration_c3gxb_w_lg_busy9w(0);
wire_calibration_c3gxb_w_lg_busy9w(0) <= wire_calibration_c3gxb_busy AND wire_calibration_c3gxb_dprio_rden;
wire_dprio_wren <= wire_calibration_c3gxb_w_lg_busy10w(0);
wire_calibration_c3gxb_w_lg_busy10w(0) <= wire_calibration_c3gxb_busy AND wire_calibration_c3gxb_dprio_wren;
dprio : gxReconfig_alt_dprio_v5k
PORT MAP (
address => wire_dprio_address,
busy => wire_dprio_busy,
datain => wire_dprio_datain,
dataout => wire_dprio_dataout,
dpclk => reconfig_clk,
dpriodisable => wire_dprio_dpriodisable,
dprioin => wire_dprio_dprioin,
dprioload => wire_dprio_dprioload,
dprioout => cal_dprioout_wire(0),
quad_address => address_pres_reg(11 DOWNTO 3),
rden => wire_dprio_rden,
reset => reconfig_reset_all,
wren => wire_dprio_wren,
wren_data => wire_calibration_c3gxb_retain_addr
);
PROCESS (reconfig_clk, reconfig_reset_all)
BEGIN
IF (reconfig_reset_all = '1') THEN address_pres_reg <= (OTHERS => '0');
ELSIF (reconfig_clk = '1' AND reconfig_clk'event) THEN address_pres_reg <= ( quad_address & channel_address);
END IF;
END PROCESS;
END RTL; --gxReconfig_alt_c3gxb_reconfig_qrm
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY gxReconfig IS
PORT
(
reconfig_clk : IN STD_LOGIC ;
reconfig_fromgxb : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
busy : OUT STD_LOGIC ;
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END gxReconfig;
ARCHITECTURE RTL OF gxreconfig IS
ATTRIBUTE synthesis_clearbox: natural;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
ATTRIBUTE clearbox_macroname: string;
ATTRIBUTE clearbox_macroname OF RTL: ARCHITECTURE IS "alt_c3gxb_reconfig";
ATTRIBUTE clearbox_defparam: string;
ATTRIBUTE clearbox_defparam OF RTL: ARCHITECTURE IS "cbx_blackbox_list=-lpm_mux;intended_device_family=Cyclone IV GX;number_of_channels=4;number_of_reconfig_ports=1;enable_buf_cal=true;reconfig_fromgxb_width=5;reconfig_togxb_width=4;";
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT gxReconfig_alt_c3gxb_reconfig_qrm
PORT (
busy : OUT STD_LOGIC ;
reconfig_clk : IN STD_LOGIC ;
reconfig_fromgxb : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
busy <= sub_wire0;
reconfig_togxb <= sub_wire1(3 DOWNTO 0);
gxReconfig_alt_c3gxb_reconfig_qrm_component : gxReconfig_alt_c3gxb_reconfig_qrm
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
busy => sub_wire0,
reconfig_togxb => sub_wire1
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADCE NUMERIC "0"
-- Retrieval info: PRIVATE: CMU_PLL NUMERIC "0"
-- Retrieval info: PRIVATE: DATA_RATE NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: PRIVATE: PMA NUMERIC "0"
-- Retrieval info: PRIVATE: PROTO_SWITCH NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: CONSTANT: CBX_BLACKBOX_LIST STRING "-lpm_mux"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "4"
-- Retrieval info: CONSTANT: NUMBER_OF_RECONFIG_PORTS NUMERIC "1"
-- Retrieval info: CONSTANT: enable_buf_cal STRING "true"
-- Retrieval info: CONSTANT: reconfig_fromgxb_width NUMERIC "5"
-- Retrieval info: CONSTANT: reconfig_togxb_width NUMERIC "4"
-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
-- Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
-- Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 INPUT NODEFVAL "reconfig_fromgxb[4..0]"
-- Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 OUTPUT NODEFVAL "reconfig_togxb[3..0]"
-- Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 5 0 reconfig_fromgxb 0 0 5 0
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL gxReconfig.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gxReconfig.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gxReconfig.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gxReconfig.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL GXReconfig_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gxReconfig_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: LIB_FILE: lpm
| gpl-2.0 | d975f088ed3463f7526705c051947c9b | 0.583536 | 2.932062 | false | true | false | false |
ou-cse-378/vhdl-tetris | NES.vhd | 1 | 2,404 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: NES.vhd
-- // Date: 12/9/2004
-- // Description: This module handles the input from the NES Controller.
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity NES is
Port ( DataI : in std_logic;
clkO : out std_logic;
clkI : in std_logic; --25 mhz
waitCLKI : std_logic; --48 Khz Khz
clr : in std_logic;
latchO : out std_logic;
Buttons : out std_logic_vector(7 downto 0)
);
end NES;
architecture Behavioral of NES is
type state_type is ( startup, readA, readB, readSel, readStart, readUp, readDown, readLeft, readRight);
signal current_state, next_state : state_type;
signal LatchBind : std_logic := '0';
begin
synch: process(clkI, clr)
begin
if clr = '1' then
current_state <= startup;
elsif(clkI'event and clkI = '1') then
current_state <= next_state;
end if;
end process synch;
ReadButtons: process(current_state, waitclkI, clr)
variable A, B, Sel, Start, Up, Left, Right, Down : std_logic := '1';
begin
if clr = '1' then
A :='1';
B := '1';
Sel := '1';
Start := '1';
Up := '1';
Left := '1';
Right := '1';
Down := '1';
elsif (waitclkI'event and waitclkI = '1') then
Latchbind <= '0';
case current_state is
when startup =>
next_state <= ReadA;
Latchbind <= '1';
when ReadA =>
A := DataI;
next_state <= ReadB;
when ReadB =>
B := DataI;
next_state <= ReadSel;
when readSel =>
Sel := DataI;
next_state <= readStart;
when readStart =>
Start := DataI;
next_state <= readUp;
when readUp =>
Up := DataI;
next_state <= readDown;
when readDown =>
Down := DataI;
next_state <= readLeft;
when readLeft =>
Left := DataI;
next_state <= readRight;
when readRight =>
Right := DataI;
next_state <= Startup;
end case;
Buttons(7 downto 0) <= Not(A & B & Sel & Start & Up & Down & Left & Right);
end if;
end process;
clkO <= waitCLKI;
LatchO <= waitclkI and LatchBind;
end Behavioral; | mit | a9009d48e807642cb1d69e6087591a1e | 0.524542 | 3.288646 | false | false | false | false |
DreamIP/GPStudio | support/process/dilate/hdl/dilate_slave.vhd | 1 | 9,714 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity dilate_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_value : out std_logic_vector(15 downto 0);
di00_reg_m00 : out std_logic_vector(7 downto 0);
di01_reg_m01 : out std_logic_vector(7 downto 0);
di02_reg_m02 : out std_logic_vector(7 downto 0);
di10_reg_m10 : out std_logic_vector(7 downto 0);
di11_reg_m11 : out std_logic_vector(7 downto 0);
di12_reg_m12 : out std_logic_vector(7 downto 0);
di20_reg_m20 : out std_logic_vector(7 downto 0);
di21_reg_m21 : out std_logic_vector(7 downto 0);
di22_reg_m22 : out std_logic_vector(7 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end dilate_slave;
architecture rtl of dilate_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant WIDTHIMG_REG_REG_ADDR : natural := 1;
constant DI00_REG_REG_ADDR : natural := 3;
constant DI01_REG_REG_ADDR : natural := 4;
constant DI02_REG_REG_ADDR : natural := 5;
constant DI10_REG_REG_ADDR : natural := 6;
constant DI11_REG_REG_ADDR : natural := 7;
constant DI12_REG_REG_ADDR : natural := 8;
constant DI20_REG_REG_ADDR : natural := 9;
constant DI21_REG_REG_ADDR : natural := 10;
constant DI22_REG_REG_ADDR : natural := 11;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal widthimg_reg_value_reg : std_logic_vector (15 downto 0);
signal di00_reg_m00_reg : std_logic_vector (7 downto 0);
signal di01_reg_m01_reg : std_logic_vector (7 downto 0);
signal di02_reg_m02_reg : std_logic_vector (7 downto 0);
signal di10_reg_m10_reg : std_logic_vector (7 downto 0);
signal di11_reg_m11_reg : std_logic_vector (7 downto 0);
signal di12_reg_m12_reg : std_logic_vector (7 downto 0);
signal di20_reg_m20_reg : std_logic_vector (7 downto 0);
signal di21_reg_m21_reg : std_logic_vector (7 downto 0);
signal di22_reg_m22_reg : std_logic_vector (7 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
widthimg_reg_value_reg <= "0000000000000000";
di00_reg_m00_reg <= "00000000";
di01_reg_m01_reg <= "00000000";
di02_reg_m02_reg <= "00000000";
di10_reg_m10_reg <= "00000000";
di11_reg_m11_reg <= "00000000";
di12_reg_m12_reg <= "00000000";
di20_reg_m20_reg <= "00000000";
di21_reg_m21_reg <= "00000000";
di22_reg_m22_reg <= "00000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
status_reg_enable_bit_reg <= datawr_i(0);
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
widthimg_reg_value_reg <= datawr_i(15) & datawr_i(14) & datawr_i(13) & datawr_i(12) & datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI00_REG_REG_ADDR, 4))=>
di00_reg_m00_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI01_REG_REG_ADDR, 4))=>
di01_reg_m01_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI02_REG_REG_ADDR, 4))=>
di02_reg_m02_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI10_REG_REG_ADDR, 4))=>
di10_reg_m10_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI11_REG_REG_ADDR, 4))=>
di11_reg_m11_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI12_REG_REG_ADDR, 4))=>
di12_reg_m12_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI20_REG_REG_ADDR, 4))=>
di20_reg_m20_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI21_REG_REG_ADDR, 4))=>
di21_reg_m21_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI22_REG_REG_ADDR, 4))=>
di22_reg_m22_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000000000000000000" & status_reg_enable_bit_reg;
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000" & widthimg_reg_value_reg(15) & widthimg_reg_value_reg(14) & widthimg_reg_value_reg(13) & widthimg_reg_value_reg(12) & widthimg_reg_value_reg(11) & widthimg_reg_value_reg(10) & widthimg_reg_value_reg(9) & widthimg_reg_value_reg(8) & widthimg_reg_value_reg(7) & widthimg_reg_value_reg(6) & widthimg_reg_value_reg(5) & widthimg_reg_value_reg(4) & widthimg_reg_value_reg(3) & widthimg_reg_value_reg(2) & widthimg_reg_value_reg(1) & widthimg_reg_value_reg(0);
when std_logic_vector(to_unsigned(DI00_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di00_reg_m00_reg(7) & di00_reg_m00_reg(6) & di00_reg_m00_reg(5) & di00_reg_m00_reg(4) & di00_reg_m00_reg(3) & di00_reg_m00_reg(2) & di00_reg_m00_reg(1) & di00_reg_m00_reg(0);
when std_logic_vector(to_unsigned(DI01_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di01_reg_m01_reg(7) & di01_reg_m01_reg(6) & di01_reg_m01_reg(5) & di01_reg_m01_reg(4) & di01_reg_m01_reg(3) & di01_reg_m01_reg(2) & di01_reg_m01_reg(1) & di01_reg_m01_reg(0);
when std_logic_vector(to_unsigned(DI02_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di02_reg_m02_reg(7) & di02_reg_m02_reg(6) & di02_reg_m02_reg(5) & di02_reg_m02_reg(4) & di02_reg_m02_reg(3) & di02_reg_m02_reg(2) & di02_reg_m02_reg(1) & di02_reg_m02_reg(0);
when std_logic_vector(to_unsigned(DI10_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di10_reg_m10_reg(7) & di10_reg_m10_reg(6) & di10_reg_m10_reg(5) & di10_reg_m10_reg(4) & di10_reg_m10_reg(3) & di10_reg_m10_reg(2) & di10_reg_m10_reg(1) & di10_reg_m10_reg(0);
when std_logic_vector(to_unsigned(DI11_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di11_reg_m11_reg(7) & di11_reg_m11_reg(6) & di11_reg_m11_reg(5) & di11_reg_m11_reg(4) & di11_reg_m11_reg(3) & di11_reg_m11_reg(2) & di11_reg_m11_reg(1) & di11_reg_m11_reg(0);
when std_logic_vector(to_unsigned(DI12_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di12_reg_m12_reg(7) & di12_reg_m12_reg(6) & di12_reg_m12_reg(5) & di12_reg_m12_reg(4) & di12_reg_m12_reg(3) & di12_reg_m12_reg(2) & di12_reg_m12_reg(1) & di12_reg_m12_reg(0);
when std_logic_vector(to_unsigned(DI20_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di20_reg_m20_reg(7) & di20_reg_m20_reg(6) & di20_reg_m20_reg(5) & di20_reg_m20_reg(4) & di20_reg_m20_reg(3) & di20_reg_m20_reg(2) & di20_reg_m20_reg(1) & di20_reg_m20_reg(0);
when std_logic_vector(to_unsigned(DI21_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di21_reg_m21_reg(7) & di21_reg_m21_reg(6) & di21_reg_m21_reg(5) & di21_reg_m21_reg(4) & di21_reg_m21_reg(3) & di21_reg_m21_reg(2) & di21_reg_m21_reg(1) & di21_reg_m21_reg(0);
when std_logic_vector(to_unsigned(DI22_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di22_reg_m22_reg(7) & di22_reg_m22_reg(6) & di22_reg_m22_reg(5) & di22_reg_m22_reg(4) & di22_reg_m22_reg(3) & di22_reg_m22_reg(2) & di22_reg_m22_reg(1) & di22_reg_m22_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
widthimg_reg_value <= widthimg_reg_value_reg;
di00_reg_m00 <= di00_reg_m00_reg;
di01_reg_m01 <= di01_reg_m01_reg;
di02_reg_m02 <= di02_reg_m02_reg;
di10_reg_m10 <= di10_reg_m10_reg;
di11_reg_m11 <= di11_reg_m11_reg;
di12_reg_m12 <= di12_reg_m12_reg;
di20_reg_m20 <= di20_reg_m20_reg;
di21_reg_m21 <= di21_reg_m21_reg;
di22_reg_m22 <= di22_reg_m22_reg;
end rtl;
| gpl-3.0 | 6e0555cac7ddbd99e5d4e8b46d861165 | 0.608606 | 2.422444 | false | false | false | false |
DreamIP/GPStudio | support/process/dynroi/hdl/dynroi_slave.vhd | 1 | 8,086 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity dynroi_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
status_reg_bypass_bit : out std_logic;
status_reg_static_res_bit : out std_logic;
inImg_size_reg_in_w_reg : out std_logic_vector(11 downto 0);
inImg_size_reg_in_h_reg : out std_logic_vector(11 downto 0);
BinImg_size_reg_in_w_reg : out std_logic_vector(11 downto 0);
BinImg_size_reg_in_h_reg : out std_logic_vector(11 downto 0);
out_size_reg_out_w_reg : out std_logic_vector(11 downto 0);
out_size_reg_out_h_reg : out std_logic_vector(11 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end dynroi_slave;
architecture rtl of dynroi_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant INIMG_SIZE_REG_REG_ADDR : natural := 1;
constant BINIMG_SIZE_REG_REG_ADDR : natural := 2;
constant OUT_SIZE_REG_REG_ADDR : natural := 3;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal status_reg_bypass_bit_reg : std_logic;
signal status_reg_static_res_bit_reg : std_logic;
signal inImg_size_reg_in_w_reg_reg : std_logic_vector (11 downto 0);
signal inImg_size_reg_in_h_reg_reg : std_logic_vector (11 downto 0);
signal BinImg_size_reg_in_w_reg_reg : std_logic_vector (11 downto 0);
signal BinImg_size_reg_in_h_reg_reg : std_logic_vector (11 downto 0);
signal out_size_reg_out_w_reg_reg : std_logic_vector (11 downto 0);
signal out_size_reg_out_h_reg_reg : std_logic_vector (11 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
status_reg_bypass_bit_reg <= '0';
status_reg_static_res_bit_reg <= '0';
inImg_size_reg_in_w_reg_reg <= "000000000000";
inImg_size_reg_in_h_reg_reg <= "000000000000";
BinImg_size_reg_in_w_reg_reg <= "000000000000";
BinImg_size_reg_in_h_reg_reg <= "000000000000";
out_size_reg_out_w_reg_reg <= "000000000000";
out_size_reg_out_h_reg_reg <= "000000000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case to_integer(unsigned(addr_rel_i)) is
when STATUS_REG_REG_ADDR =>
status_reg_enable_bit_reg <= datawr_i(0);
status_reg_bypass_bit_reg <= datawr_i(1);
status_reg_static_res_bit_reg <= datawr_i(2);
when INIMG_SIZE_REG_REG_ADDR =>
inImg_size_reg_in_w_reg_reg <= datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
inImg_size_reg_in_h_reg_reg <= datawr_i(27) & datawr_i(26) & datawr_i(25) & datawr_i(24) & datawr_i(23) & datawr_i(22) & datawr_i(21) & datawr_i(20) & datawr_i(19) & datawr_i(18) & datawr_i(17) & datawr_i(16);
when BINIMG_SIZE_REG_REG_ADDR =>
BinImg_size_reg_in_w_reg_reg <= datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
BinImg_size_reg_in_h_reg_reg <= datawr_i(27) & datawr_i(26) & datawr_i(25) & datawr_i(24) & datawr_i(23) & datawr_i(22) & datawr_i(21) & datawr_i(20) & datawr_i(19) & datawr_i(18) & datawr_i(17) & datawr_i(16);
when OUT_SIZE_REG_REG_ADDR =>
out_size_reg_out_w_reg_reg <= datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
out_size_reg_out_h_reg_reg <= datawr_i(27) & datawr_i(26) & datawr_i(25) & datawr_i(24) & datawr_i(23) & datawr_i(22) & datawr_i(21) & datawr_i(20) & datawr_i(19) & datawr_i(18) & datawr_i(17) & datawr_i(16);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case to_integer(unsigned(addr_rel_i)) is
when STATUS_REG_REG_ADDR =>
datard_o <= "00000000000000000000000000000" & status_reg_static_res_bit_reg & status_reg_bypass_bit_reg & status_reg_enable_bit_reg;
when INIMG_SIZE_REG_REG_ADDR =>
datard_o <= "0000" & inImg_size_reg_in_h_reg_reg(11) & inImg_size_reg_in_h_reg_reg(10) & inImg_size_reg_in_h_reg_reg(9) & inImg_size_reg_in_h_reg_reg(8) & inImg_size_reg_in_h_reg_reg(7) & inImg_size_reg_in_h_reg_reg(6) & inImg_size_reg_in_h_reg_reg(5) & inImg_size_reg_in_h_reg_reg(4) & inImg_size_reg_in_h_reg_reg(3) & inImg_size_reg_in_h_reg_reg(2) & inImg_size_reg_in_h_reg_reg(1) & inImg_size_reg_in_h_reg_reg(0) & "0000" & inImg_size_reg_in_w_reg_reg(11) & inImg_size_reg_in_w_reg_reg(10) & inImg_size_reg_in_w_reg_reg(9) & inImg_size_reg_in_w_reg_reg(8) & inImg_size_reg_in_w_reg_reg(7) & inImg_size_reg_in_w_reg_reg(6) & inImg_size_reg_in_w_reg_reg(5) & inImg_size_reg_in_w_reg_reg(4) & inImg_size_reg_in_w_reg_reg(3) & inImg_size_reg_in_w_reg_reg(2) & inImg_size_reg_in_w_reg_reg(1) & inImg_size_reg_in_w_reg_reg(0);
when BINIMG_SIZE_REG_REG_ADDR =>
datard_o <= "0000" & BinImg_size_reg_in_h_reg_reg(11) & BinImg_size_reg_in_h_reg_reg(10) & BinImg_size_reg_in_h_reg_reg(9) & BinImg_size_reg_in_h_reg_reg(8) & BinImg_size_reg_in_h_reg_reg(7) & BinImg_size_reg_in_h_reg_reg(6) & BinImg_size_reg_in_h_reg_reg(5) & BinImg_size_reg_in_h_reg_reg(4) & BinImg_size_reg_in_h_reg_reg(3) & BinImg_size_reg_in_h_reg_reg(2) & BinImg_size_reg_in_h_reg_reg(1) & BinImg_size_reg_in_h_reg_reg(0) & "0000" & BinImg_size_reg_in_w_reg_reg(11) & BinImg_size_reg_in_w_reg_reg(10) & BinImg_size_reg_in_w_reg_reg(9) & BinImg_size_reg_in_w_reg_reg(8) & BinImg_size_reg_in_w_reg_reg(7) & BinImg_size_reg_in_w_reg_reg(6) & BinImg_size_reg_in_w_reg_reg(5) & BinImg_size_reg_in_w_reg_reg(4) & BinImg_size_reg_in_w_reg_reg(3) & BinImg_size_reg_in_w_reg_reg(2) & BinImg_size_reg_in_w_reg_reg(1) & BinImg_size_reg_in_w_reg_reg(0);
when OUT_SIZE_REG_REG_ADDR =>
datard_o <= "0000" & out_size_reg_out_h_reg_reg(11) & out_size_reg_out_h_reg_reg(10) & out_size_reg_out_h_reg_reg(9) & out_size_reg_out_h_reg_reg(8) & out_size_reg_out_h_reg_reg(7) & out_size_reg_out_h_reg_reg(6) & out_size_reg_out_h_reg_reg(5) & out_size_reg_out_h_reg_reg(4) & out_size_reg_out_h_reg_reg(3) & out_size_reg_out_h_reg_reg(2) & out_size_reg_out_h_reg_reg(1) & out_size_reg_out_h_reg_reg(0) & "0000" & out_size_reg_out_w_reg_reg(11) & out_size_reg_out_w_reg_reg(10) & out_size_reg_out_w_reg_reg(9) & out_size_reg_out_w_reg_reg(8) & out_size_reg_out_w_reg_reg(7) & out_size_reg_out_w_reg_reg(6) & out_size_reg_out_w_reg_reg(5) & out_size_reg_out_w_reg_reg(4) & out_size_reg_out_w_reg_reg(3) & out_size_reg_out_w_reg_reg(2) & out_size_reg_out_w_reg_reg(1) & out_size_reg_out_w_reg_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
status_reg_bypass_bit <= status_reg_bypass_bit_reg;
status_reg_static_res_bit <= status_reg_static_res_bit_reg;
inImg_size_reg_in_w_reg <= inImg_size_reg_in_w_reg_reg;
inImg_size_reg_in_h_reg <= inImg_size_reg_in_h_reg_reg;
BinImg_size_reg_in_w_reg <= BinImg_size_reg_in_w_reg_reg;
BinImg_size_reg_in_h_reg <= BinImg_size_reg_in_h_reg_reg;
out_size_reg_out_w_reg <= out_size_reg_out_w_reg_reg;
out_size_reg_out_h_reg <= out_size_reg_out_h_reg_reg;
end rtl;
| gpl-3.0 | 46fe2010129fea044300a1dfac00b32e | 0.617116 | 2.335644 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/boards/terasic-de2-115/cn-single-hostif-drv/quartus/toplevel.vhd | 3 | 13,941 | -------------------------------------------------------------------------------
--! @file toplevel.vhd
--
--! @brief Toplevel of hostif Nios CN driver design
--
--! @details This is the toplevel of the hostif Nios CN driver design for the
--! INK DE2-115 Evaluation Board.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2015
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library libcommon;
use libcommon.global.all;
entity toplevel is
port (
-- 50 MHZ CLK IN
EXT_CLK : in std_logic;
-- PHY Interfaces
PHY_GXCLK : out std_logic_vector(1 downto 0);
PHY_LINK_n : in std_logic_vector(1 downto 0);
PHY_RXCLK : in std_logic_vector(1 downto 0);
PHY_RXER : in std_logic_vector(1 downto 0);
PHY_RXDV : in std_logic_vector(1 downto 0);
PHY_RXD : in std_logic_vector(7 downto 0);
PHY_TXCLK : in std_logic_vector(1 downto 0);
PHY_TXER : out std_logic_vector(1 downto 0);
PHY_TXEN : out std_logic_vector(1 downto 0);
PHY_TXD : out std_logic_vector(7 downto 0);
PHY_MDIO : inout std_logic_vector(1 downto 0);
PHY_MDC : out std_logic_vector(1 downto 0);
PHY_RESET_n : out std_logic_vector(1 downto 0);
-- EPCS
EPCS_DCLK : out std_logic;
EPCS_SCE : out std_logic;
EPCS_SDO : out std_logic;
EPCS_DATA0 : in std_logic;
-- LED
LEDG : out std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(15 downto 0);
-- 2 MB SRAM
SRAM_CE_n : out std_logic;
SRAM_OE_n : out std_logic;
SRAM_WE_n : out std_logic;
SRAM_ADDR : out std_logic_vector(20 downto 1);
SRAM_BE_n : out std_logic_vector(1 downto 0);
SRAM_DQ : inout std_logic_vector(15 downto 0);
-- HOST Interface
HOSTIF_AD : inout std_logic_vector(16 downto 0);
HOSTIF_BE : in std_logic_vector(1 downto 0);
HOSTIF_CS_n : in std_logic;
HOSTIF_WR_n : in std_logic;
HOSTIF_RD_n : in std_logic;
HOSTIF_ALE_n : in std_logic;
HOSTIF_ACK_n : out std_logic;
HOSTIF_IRQ_n : out std_logic
);
end toplevel;
architecture rtl of toplevel is
component cnSingleHostifDrv is
port (
clk25_clk : in std_logic;
clk50_clk : in std_logic := 'X';
clk100_clk : in std_logic;
reset_reset_n : in std_logic := 'X';
tri_state_sram_0_tcm_address_out : out std_logic_vector(20 downto 0);
tri_state_sram_0_tcm_byteenable_n_out : out std_logic_vector(1 downto 0);
tri_state_sram_0_tcm_read_n_out : out std_logic;
tri_state_sram_0_tcm_write_n_out : out std_logic;
tri_state_sram_0_tcm_data_out : inout std_logic_vector(15 downto 0) := (others => 'X');
tri_state_sram_0_tcm_chipselect_n_out : out std_logic;
pcp_0_benchmark_pio_export : out std_logic_vector(7 downto 0);
-- OPENMAC
openmac_0_mii_txEnable : out std_logic_vector(1 downto 0);
openmac_0_mii_txData : out std_logic_vector(7 downto 0);
openmac_0_mii_txClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxError : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxDataValid : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxData : in std_logic_vector(7 downto 0) := (others => 'X');
openmac_0_mii_rxClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_smi_nPhyRst : out std_logic_vector(1 downto 0);
openmac_0_smi_clk : out std_logic_vector(1 downto 0);
openmac_0_smi_dio : inout std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_pktactivity_export : out std_logic;
powerlink_led_export : out std_logic_vector(1 downto 0);
epcs_flash_dclk : out std_logic;
epcs_flash_sce : out std_logic;
epcs_flash_sdo : out std_logic;
epcs_flash_data0 : in std_logic := 'X';
hostinterface_0_irqout_irq : out std_logic;
prl0_iPrlSlv_cs : in std_logic := 'X';
prl0_iPrlSlv_rd : in std_logic := 'X';
prl0_iPrlSlv_wr : in std_logic := 'X';
prl0_iPrlSlv_ale : in std_logic := 'X';
prl0_oPrlSlv_ack : out std_logic;
prl0_iPrlSlv_be : in std_logic_vector(1 downto 0) := (others => 'X');
prl0_oPrlSlv_ad_o : out std_logic_vector(16 downto 0);
prl0_iPrlSlv_ad_i : in std_logic_vector(16 downto 0) := (others => 'X');
prl0_oPrlSlv_ad_oen : out std_logic;
-- CPU RESET REQUEST
pcp_0_cpu_resetrequest_resetrequest : in std_logic := 'X';
pcp_0_cpu_resetrequest_resettaken : out std_logic
);
end component cnSingleHostifDrv;
-- PLL component
component pll
port (
inclk0 : in std_logic;
c0 : out std_logic;
c1 : out std_logic;
c2 : out std_logic;
c3 : out std_logic;
locked : out std_logic
);
end component;
signal clk25 : std_logic;
signal clk50 : std_logic;
signal clk100 : std_logic;
signal pllLocked : std_logic;
signal sramAddr : std_logic_vector(SRAM_ADDR'high downto 0);
signal plk_status_error : std_logic_vector(1 downto 0);
signal openmac_activity : std_logic;
signal parHost_chipselect : std_logic;
signal parHost_read : std_logic;
signal parHost_write : std_logic;
signal parHost_addressLatchEnable : std_logic;
signal parHost_acknowledge : std_logic;
signal parHost_ad_o : std_logic_vector(HOSTIF_AD'range);
signal parHost_ad_i : std_logic_vector(HOSTIF_AD'range);
signal parHost_ad_oen : std_logic;
signal host_irq : std_logic;
begin
SRAM_ADDR <= sramAddr(SRAM_ADDR'range);
PHY_GXCLK <= (others => '0');
PHY_TXER <= (others => '0');
HOSTIF_ACK_n <= not parHost_acknowledge;
HOSTIF_IRQ_n <= not host_irq;
parHost_chipselect <= not HOSTIF_CS_n;
parHost_write <= not HOSTIF_WR_n;
parHost_read <= not HOSTIF_RD_n;
parHost_addressLatchEnable <= not HOSTIF_ALE_n;
-- TRISTATE Buffer for AD bus
HOSTIF_AD <= parHost_ad_o when parHost_ad_oen = '1' else (others => 'Z');
parHost_ad_i <= HOSTIF_AD;
---------------------------------------------------------------------------
-- Green LED assignments
LEDG <= plk_status_error(0) & -- POWERLINK Status LED
"000" & -- Reserved
(openmac_activity and not PHY_LINK_n(0)) & -- Gated activity
not PHY_LINK_n(0) & -- Link
(openmac_activity and not PHY_LINK_n(1)) & -- Gated activity
not PHY_LINK_n(1); -- Link
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Red LED assignments
LEDR <= x"000" & -- Reserved
"000" & -- Reserved
plk_status_error(1); -- POWERLINK Error LED
---------------------------------------------------------------------------
inst : component cnSingleHostifDrv
port map (
clk25_clk => clk25,
clk50_clk => clk50,
clk100_clk => clk100,
reset_reset_n => pllLocked,
pcp_0_cpu_resetrequest_resetrequest => '0',
pcp_0_cpu_resetrequest_resettaken => open,
openmac_0_mii_txEnable => PHY_TXEN,
openmac_0_mii_txData => PHY_TXD,
openmac_0_mii_txClk => PHY_TXCLK,
openmac_0_mii_rxError => PHY_RXER,
openmac_0_mii_rxDataValid => PHY_RXDV,
openmac_0_mii_rxData => PHY_RXD,
openmac_0_mii_rxClk => PHY_RXCLK,
openmac_0_smi_nPhyRst => PHY_RESET_n,
openmac_0_smi_clk => PHY_MDC,
openmac_0_smi_dio => PHY_MDIO,
openmac_0_pktactivity_export => openmac_activity,
tri_state_sram_0_tcm_address_out => sramAddr,
tri_state_sram_0_tcm_read_n_out => SRAM_OE_n,
tri_state_sram_0_tcm_byteenable_n_out => SRAM_BE_n,
tri_state_sram_0_tcm_write_n_out => SRAM_WE_n,
tri_state_sram_0_tcm_data_out => SRAM_DQ,
tri_state_sram_0_tcm_chipselect_n_out => SRAM_CE_n,
pcp_0_benchmark_pio_export => open,
epcs_flash_dclk => EPCS_DCLK,
epcs_flash_sce => EPCS_SCE,
epcs_flash_sdo => EPCS_SDO,
epcs_flash_data0 => EPCS_DATA0,
hostinterface_0_irqout_irq => host_irq,
prl0_iPrlSlv_cs => parHost_chipselect,
prl0_iPrlSlv_rd => parHost_read,
prl0_iPrlSlv_wr => parHost_write,
prl0_iPrlSlv_ale => parHost_addressLatchEnable,
prl0_oPrlSlv_ack => parHost_acknowledge,
prl0_iPrlSlv_be => HOSTIF_BE,
prl0_oPrlSlv_ad_o => parHost_ad_o,
prl0_iPrlSlv_ad_i => parHost_ad_i,
prl0_oPrlSlv_ad_oen => parHost_ad_oen,
powerlink_led_export => plk_status_error
);
-- Pll Instance
pllInst : pll
port map (
inclk0 => EXT_CLK,
c0 => clk50,
c1 => clk100,
c2 => clk25,
c3 => open,
locked => pllLocked
);
end rtl;
| gpl-2.0 | 2dca4688f021eb513c74e8d808ff228e | 0.452048 | 4.347053 | false | false | false | false |
DreamIP/GPStudio | support/process/conv/hdl/conv.vhd | 1 | 6,528 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity conv is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end conv;
architecture rtl of conv is
component conv_process
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_width : in std_logic_vector(15 downto 0);
w00_reg_m00 : in std_logic_vector(7 downto 0);
w01_reg_m01 : in std_logic_vector(7 downto 0);
w02_reg_m02 : in std_logic_vector(7 downto 0);
w10_reg_m10 : in std_logic_vector(7 downto 0);
w11_reg_m11 : in std_logic_vector(7 downto 0);
w12_reg_m12 : in std_logic_vector(7 downto 0);
w20_reg_m20 : in std_logic_vector(7 downto 0);
w21_reg_m21 : in std_logic_vector(7 downto 0);
w22_reg_m22 : in std_logic_vector(7 downto 0);
norm_reg_norm : in std_logic_vector(3 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component conv_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
w00_reg_m00 : out std_logic_vector(7 downto 0);
w01_reg_m01 : out std_logic_vector(7 downto 0);
w02_reg_m02 : out std_logic_vector(7 downto 0);
w10_reg_m10 : out std_logic_vector(7 downto 0);
w11_reg_m11 : out std_logic_vector(7 downto 0);
w12_reg_m12 : out std_logic_vector(7 downto 0);
w20_reg_m20 : out std_logic_vector(7 downto 0);
w21_reg_m21 : out std_logic_vector(7 downto 0);
w22_reg_m22 : out std_logic_vector(7 downto 0);
norm_reg_norm : out std_logic_vector(3 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal widthimg_reg_width : std_logic_vector (15 downto 0);
signal w00_reg_m00 : std_logic_vector (7 downto 0);
signal w01_reg_m01 : std_logic_vector (7 downto 0);
signal w02_reg_m02 : std_logic_vector (7 downto 0);
signal w10_reg_m10 : std_logic_vector (7 downto 0);
signal w11_reg_m11 : std_logic_vector (7 downto 0);
signal w12_reg_m12 : std_logic_vector (7 downto 0);
signal w20_reg_m20 : std_logic_vector (7 downto 0);
signal w21_reg_m21 : std_logic_vector (7 downto 0);
signal w22_reg_m22 : std_logic_vector (7 downto 0);
signal norm_reg_norm : std_logic_vector (3 downto 0);
begin
conv_process_inst : conv_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_width => widthimg_reg_width,
w00_reg_m00 => w00_reg_m00,
w01_reg_m01 => w01_reg_m01,
w02_reg_m02 => w02_reg_m02,
w10_reg_m10 => w10_reg_m10,
w11_reg_m11 => w11_reg_m11,
w12_reg_m12 => w12_reg_m12,
w20_reg_m20 => w20_reg_m20,
w21_reg_m21 => w21_reg_m21,
w22_reg_m22 => w22_reg_m22,
norm_reg_norm => norm_reg_norm,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
conv_slave_inst : conv_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_width => widthimg_reg_width,
w00_reg_m00 => w00_reg_m00,
w01_reg_m01 => w01_reg_m01,
w02_reg_m02 => w02_reg_m02,
w10_reg_m10 => w10_reg_m10,
w11_reg_m11 => w11_reg_m11,
w12_reg_m12 => w12_reg_m12,
w20_reg_m20 => w20_reg_m20,
w21_reg_m21 => w21_reg_m21,
w22_reg_m22 => w22_reg_m22,
norm_reg_norm => norm_reg_norm,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
| gpl-3.0 | 48e64b73d8fdb42ce999dcb23c5eacab | 0.486673 | 3.01246 | false | false | false | false |
DreamIP/GPStudio | support/process/fast/hdl/fast.vhd | 1 | 2,943 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fast is
generic (
IMAGE_WIDTH : integer := 320;
IN_SIZE : integer := 8;
OUT1_SIZE : integer := 8;
CLK_PROC_FREQ : integer := 50000000
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------------ IN FLOW ---------------------------------
in_data : in std_logic_vector((IN_SIZE-1) downto 0);
in_dv : in std_logic;
in_fv : in std_logic;
----------------------------- OUT FLOW ---------------------------------
out1_data : out std_logic_vector((OUT1_SIZE-1) downto 0);
out1_dv : out std_logic;
out1_fv : out std_logic;
------------------------------ Slaves ---------------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end fast;
architecture structural of fast is
component fast_slave
port(
clk_proc : in std_logic;
reset_n : in std_logic;
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0);
enable_o : out std_logic
);
end component;
component fast_process
generic(
PIXEL_SIZE : integer;
IMAGE_WIDTH : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector ((PIXEL_SIZE-1) downto 0);
in_dv : in std_logic;
in_fv : in std_logic;
out1_data : out std_logic_vector ((PIXEL_SIZE-1) downto 0);
out1_dv : out std_logic;
out1_fv : out std_logic
);
end component;
signal enable_s : std_logic;
begin
slave_inst : fast_slave
port map
(
clk_proc => clk_proc,
reset_n => reset_n,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o,
enable_o => enable_s
);
proce_inst : fast_process
generic map(
PIXEL_SIZE => IN_SIZE,
IMAGE_WIDTH => IMAGE_WIDTH
)
port map(
clk => clk_proc,
reset_n => reset_n,
enable => enable_s,
in_data => in_data,
in_dv => in_dv,
in_fv => in_fv,
out1_data => out1_data,
out1_dv => out1_dv,
out1_fv => out1_fv
);
end structural;
| gpl-3.0 | 2cf71fce5ec0a06d4e36c73a44e01d8f | 0.445124 | 3.251934 | false | false | false | false |
hoglet67/ElectronFpga | AtomBusMon/src/T80/T80_Pack.vhd | 1 | 9,569 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
NMICycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic;
REG : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
DIRSet : in std_logic := '0';
DIR : in std_logic_vector(211 downto 0) := (others => '0') -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0);
DOR : out std_logic_vector(127 downto 0);
DIRSet : in std_logic;
DIR : in std_logic_vector(127 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
LDHLSP : out std_logic;
ADDSPdd : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;
| gpl-3.0 | 4411df8a7c7d2d9fc8f2e6258fc03e3e | 0.536315 | 3.39206 | false | false | false | false |
DreamIP/GPStudio | support/io/vga_out/hdl/FrameBuffer.vhd | 1 | 9,055 | -- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: FrameBuffer.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 15.1.0 Build 185 10/21/2015 SJ Standard Edition
-- ************************************************************
--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity FrameBuffer is
port
(
data : in std_logic_vector (7 downto 0);
rdaddress : in std_logic_vector (14 downto 0);
rdclock : in std_logic;
wraddress : in std_logic_vector (14 downto 0);
wrclock : in std_logic := '1';
wren : in std_logic := '0';
q : out std_logic_vector (7 downto 0)
);
end FrameBuffer;
architecture SYN of framebuffer is
signal sub_wire0 : std_logic_vector (7 downto 0);
begin
q <= sub_wire0(7 downto 0);
altsyncram_component : altsyncram
generic map (
address_aclr_b => "NONE",
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
init_file => "./frame_buffer/frame-buffer.mif",
intended_device_family => "Cyclone V",
lpm_type => "altsyncram",
numwords_a => 32768,
numwords_b => 32768,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
widthad_a => 15,
widthad_b => 15,
width_a => 8,
width_b => 8,
width_byteena_a => 1
)
port map (
address_a => wraddress,
address_b => rdaddress,
clock0 => wrclock,
clock1 => rdclock,
data_a => data,
wren_a => wren,
q_b => sub_wire0
);
end SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "1"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "262144"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
-- Retrieval info: PRIVATE: MIFfilename STRING "./frame_buffer/frame-buffer.mif"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "./frame_buffer/frame-buffer.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32768"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "15"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 15 0 INPUT NODEFVAL "rdaddress[14..0]"
-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
-- Retrieval info: USED_PORT: wraddress 0 0 15 0 INPUT NODEFVAL "wraddress[14..0]"
-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 15 0 wraddress 0 0 15 0
-- Retrieval info: CONNECT: @address_b 0 0 15 0 rdaddress 0 0 15 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL FrameBuffer.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FrameBuffer.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FrameBuffer.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FrameBuffer.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FrameBuffer_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | 6bac3d44d8b4c6a0b47b551d8021ecb2 | 0.6582 | 3.831993 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Servo code/servo_pwm_tb.vhd | 2 | 1,727 | LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.VITAL_Primitives.all;
entity servo_pwm_tb is
end servo_pwm_tb;
architecture behavior of servo_pwm_tb is
component servo_pwm
port(
clk : in std_logic;
reset_n : in std_logic;
coe_servo : out std_logic;
avs_s0_write_n : in std_logic;
avs_s0_writedata : in std_logic_vector (15 downto 0)
);
end component;
signal clk : std_logic:= '1';
signal reset_n : std_logic;
signal coe_servo : std_logic;
signal avs_s0_write_n: std_logic;
signal avs_s0_writedata: std_logic_vector (15 downto 0);
constant clk_period : time := 10 ns;
begin
uut: servo_pwm port map (
clk => clk,
reset_n => reset_n,
coe_servo => coe_servo,
avs_s0_write_n => avs_s0_write_n,
avs_s0_writedata => avs_s0_writedata
);
clk_process :process begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stimuli: process
begin
reset_n <= '1';
wait for 6 ms;
reset_n <= '0';
avs_s0_write_n <= '0';
wait for 6 ms;
reset_n <= '1';
avs_s0_writedata <= "0000000010101010";
avs_s0_write_n <= '0';
wait for 1 ms;
avs_s0_write_n <= '1';
wait for 6 ms;
avs_s0_writedata <= "0000000000000000";
avs_s0_write_n <= '0';
wait for 1 ms;
avs_s0_write_n <= '1';
wait for 6 ms;
avs_s0_writedata <= "0000000010000010";
avs_s0_write_n <= '0';
wait for 1 ms;
avs_s0_write_n <= '1';
wait for 6 ms;
avs_s0_writedata <= "0000000000000000";
avs_s0_write_n <= '0';
wait for 1 ms;
avs_s0_write_n <= '1';
wait for 6 ms;
avs_s0_writedata <= "0000000010101010";
avs_s0_write_n <= '0';
wait for 1 ms;
avs_s0_write_n <= '1';
wait;
end process;
end; | gpl-2.0 | c6a4612e825ff57cbc38a87b049a2e2b | 0.617834 | 2.418768 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/synchronizerRtl.vhd | 3 | 3,460 | -------------------------------------------------------------------------------
--! @file synchronizerRtl.vhd
--
--! @brief Synchronizer
--
--! @details This is a synchronizer with configurable stage size.
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity synchronizer is
generic (
--! Stages
gStages : natural := 2;
--! Initialization level
gInit : std_logic := cInactivated
);
port (
--! Asynchronous reset
iArst : in std_logic;
--! Clock
iClk : in std_logic;
--! Asynchronous input
iAsync : in std_logic;
--! Synchronous output
oSync : out std_logic
);
end synchronizer;
architecture rtl of synchronizer is
--! Meta registers used to synchronize input signal
signal metaReg : std_logic_vector(gStages-1 downto 0);
--! Meta registers next
signal metaReg_next : std_logic_vector(metaReg'range);
begin
-- handle wrong stage generic
assert (gStages > 0)
report "gStages must be set higher 0!" severity failure;
-- output last synchronizer stage
oSync <= metaReg(metaReg'left);
-- assign asynchronous signal to metaRegisters
metaReg_next <= metaReg(metaReg'left-1 downto 0) & iAsync;
reg : process(iArst, iClk)
begin
if iArst = cActivated then
metaReg <= (others => gInit);
elsif rising_edge(iClk) then
metaReg <= metaReg_next;
end if;
end process;
end rtl;
| gpl-2.0 | aad38f233700f005a0c434a60e89be76 | 0.635549 | 4.713896 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_Color_Space_Converter.vhd | 1 | 10,796 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module converts video in stream between color spaces on the DE *
-- * boards. *
-- * *
-- ******************************************************************************
ENTITY Video_System_Color_Space_Converter IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
GENERIC (
IW :INTEGER := 23;
OW :INTEGER := 23;
EIW :INTEGER := 1;
EOW :INTEGER := 1
);
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
stream_in_data :IN STD_LOGIC_VECTOR(IW DOWNTO 0);
stream_in_startofpacket :IN STD_LOGIC;
stream_in_endofpacket :IN STD_LOGIC;
stream_in_empty :IN STD_LOGIC_VECTOR(EIW DOWNTO 0);
stream_in_valid :IN STD_LOGIC;
stream_out_ready :IN STD_LOGIC;
-- Bidirectional
-- Outputs
stream_in_ready :BUFFER STD_LOGIC;
stream_out_data :BUFFER STD_LOGIC_VECTOR(OW DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_empty :BUFFER STD_LOGIC_VECTOR(EOW DOWNTO 0);
stream_out_valid :BUFFER STD_LOGIC
);
END Video_System_Color_Space_Converter;
ARCHITECTURE Behaviour OF Video_System_Color_Space_Converter IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
SIGNAL transfer_data :STD_LOGIC;
SIGNAL converted_data :STD_LOGIC_VECTOR(OW DOWNTO 0);
SIGNAL converted_startofpacket :STD_LOGIC;
SIGNAL converted_endofpacket :STD_LOGIC;
SIGNAL converted_empty :STD_LOGIC_VECTOR(EOW DOWNTO 0);
SIGNAL converted_valid :STD_LOGIC;
-- Internal Registers
SIGNAL data :STD_LOGIC_VECTOR(IW DOWNTO 0);
SIGNAL startofpacket :STD_LOGIC;
SIGNAL endofpacket :STD_LOGIC;
SIGNAL empty :STD_LOGIC_VECTOR(EIW DOWNTO 0);
SIGNAL valid :STD_LOGIC;
-- State Machine Registers
-- Integers
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
COMPONENT altera_up_YCrCb_to_RGB_converter
PORT (
-- Inputs
clk :IN STD_LOGIC;
clk_en :IN STD_LOGIC;
reset :IN STD_LOGIC;
Y :IN STD_LOGIC_VECTOR( 7 DOWNTO 0);
Cr :IN STD_LOGIC_VECTOR( 7 DOWNTO 0);
Cb :IN STD_LOGIC_VECTOR( 7 DOWNTO 0);
stream_in_startofpacket :IN STD_LOGIC;
stream_in_endofpacket :IN STD_LOGIC;
stream_in_empty :IN STD_LOGIC_VECTOR(EIW DOWNTO 0);
stream_in_valid :IN STD_LOGIC;
-- Bidirectionals
-- Outputs
R :BUFFER STD_LOGIC_VECTOR( 7 DOWNTO 0);
G :BUFFER STD_LOGIC_VECTOR( 7 DOWNTO 0);
B :BUFFER STD_LOGIC_VECTOR( 7 DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_empty :BUFFER STD_LOGIC_VECTOR(EOW DOWNTO 0);
stream_out_valid :BUFFER STD_LOGIC
);
END COMPONENT;
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
-- Output Registers
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
stream_out_data <= (OTHERS => '0');
stream_out_startofpacket <= '0';
stream_out_endofpacket <= '0';
stream_out_empty <= B"00";
stream_out_valid <= '0';
ELSIF (transfer_data = '1') THEN
stream_out_data <= converted_data;
stream_out_startofpacket <= converted_startofpacket;
stream_out_endofpacket <= converted_endofpacket;
stream_out_empty <= converted_empty;
stream_out_valid <= converted_valid;
END IF;
END IF;
END PROCESS;
-- Internal Registers
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
data <= (OTHERS => '0');
startofpacket <= '0';
endofpacket <= '0';
empty <= (OTHERS => '0');
valid <= '0';
ELSIF (stream_in_ready = '1') THEN
data <= stream_in_data;
startofpacket <= stream_in_startofpacket;
endofpacket <= stream_in_endofpacket;
empty <= stream_in_empty;
valid <= stream_in_valid;
ELSIF (transfer_data = '1') THEN
data <= (OTHERS => '0');
startofpacket <= '0';
endofpacket <= '0';
empty <= (OTHERS => '0');
valid <= '0';
END IF;
END IF;
END PROCESS;
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
-- Output Assignments
stream_in_ready <= stream_in_valid AND ( NOT valid OR transfer_data);
-- Internal Assignments
transfer_data <= NOT stream_out_valid OR
(stream_out_ready AND stream_out_valid);
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
YCrCb_to_RGB : altera_up_YCrCb_to_RGB_converter
PORT MAP (
-- Inputs
clk => clk,
clk_en => transfer_data,
reset => reset,
Y => data( 7 DOWNTO 0),
Cr => data(23 DOWNTO 16),
Cb => data(15 DOWNTO 8),
stream_in_startofpacket => startofpacket,
stream_in_endofpacket => endofpacket,
stream_in_empty => empty,
stream_in_valid => valid,
-- Bidirectionals
-- Outputs
R => converted_data(23 DOWNTO 16),
G => converted_data(15 DOWNTO 8),
B => converted_data( 7 DOWNTO 0),
stream_out_startofpacket => converted_startofpacket,
stream_out_endofpacket => converted_endofpacket,
stream_out_empty => converted_empty,
stream_out_valid => converted_valid
);
END Behaviour;
| gpl-2.0 | 8cc1588783f415250606863f166a40c3 | 0.460078 | 4.344467 | false | false | false | false |
bpervan/simple-soc | pcores/uart_cntrl_v1_00_a/hdl/vhdl/UARTTransmitter.vhd | 1 | 3,291 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:27:32 03/11/2014
-- Design Name:
-- Module Name: UARTTransmitter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity UARTTransmitter is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
tick : in STD_LOGIC;
d_in : in STD_LOGIC_VECTOR (7 downto 0);
tx_start : in STD_LOGIC;
tx_done : out STD_LOGIC;
tx : out STD_LOGIC);
end UARTTransmitter;
architecture Behavioral of UARTTransmitter is
type state_type is (idle, start, data, stop);
signal next_state, current_state : state_type;
signal tick_counter, tick_counter_next : unsigned (3 downto 0);
signal bit_counter, bit_counter_next : unsigned (2 downto 0);
signal reg, reg_next : std_logic_vector (7 downto 0);
signal tx_reg, tx_reg_next : std_logic;
begin
process (clk, rst)
begin
if (rst = '0') then
current_state <= idle;
tick_counter <= (others => '0');
bit_counter <= (others => '0');
reg <= (others => '0');
tx_reg <= '1';
else
if (rising_edge(clk)) then
current_state <= next_state;
tick_counter <= tick_counter_next;
bit_counter <= bit_counter_next;
reg <= reg_next;
tx_reg <= tx_reg_next;
end if;
end if;
end process;
process(current_state, tick_counter, bit_counter, reg, tick, tx_reg, tx_start, d_in)
begin
next_state <= current_state;
tick_counter_next <= tick_counter;
bit_counter_next <= bit_counter;
reg_next <= reg;
tx_reg_next <= tx_reg;
tx_done <= '0';
case current_state is
when idle =>
tx_reg_next <= '1';
if(tx_start = '1') then
next_state <= start;
tick_counter_next <= "0000";
reg_next <= d_in;
end if;
when start =>
tx_reg_next <= '0';
if(tick = '1') then
if(tick_counter < 15) then
tick_counter_next <= tick_counter + 1;
else
tick_counter_next <= "0000";
bit_counter_next <= "000";
next_state <= data;
end if;
end if;
when data =>
tx_reg_next <= reg(0);
if(tick = '1') then
if(tick_counter < 15) then
tick_counter_next <= tick_counter + 1;
else
tick_counter_next <= "0000";
reg_next <= '0' & reg(7 downto 1);
if (bit_counter = 7) then
next_state <= stop;
else
bit_counter_next <= bit_counter + 1;
end if;
end if;
end if;
when stop =>
tx_reg_next <= '1';
if(tick = '1') then
if(tick_counter < 15) then
tick_counter_next <= tick_counter + 1;
else
next_state <= idle;
tx_done <= '1';
end if;
end if;
end case;
end process;
tx <= tx_reg;
end Behavioral;
| mit | 9716b4d927be5e9791000e203b570520 | 0.567001 | 3.182785 | false | false | false | false |
ou-cse-378/vhdl-tetris | ClockDiv.vhd | 1 | 1,109 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: clockdiv.vhd
-- // Date: 12/9/2004
-- // Description: A clock divider. Divides mclk into 25 Mhz, 48 Khz, and 190 Hz
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ClockDiv is
Port ( iMclk : in std_logic;
oclk190Hz : out std_logic;
oclk48Khz : out std_logic;
oclk25Mhz : out std_logic);
end ClockDiv;
architecture Behavioral of ClockDiv is
signal tClkdiv: std_logic_vector(31 downto 0) := X"00000000";
begin
process (iMclk)
begin
if iMclk = '1' and iMclk'event then
tClkdiv <= tClkdiv + 1;
end if;
end process;
oClk190Hz <= tClkdiv(17); --190.7 Hz Seven Segment Display
oClk48Khz <= tClkdiv(9); --48.8 Khz Nintenido Controller Clock
oClk25Mhz <= tClkdiv(0); --25 Mhz VGA Clock
end Behavioral;
| mit | 840242866caf05e8ada6ead00f4c5df9 | 0.550045 | 3.412308 | false | false | false | false |
DreamIP/GPStudio | support/toolchain/caph/hdl/caph_lib/port_buffer.vhd | 1 | 2,317 | -----------------------------------------------------------------------------------------
-- --
-- This file is part of the CAPH Compiler distribution --
-- http://caph.univ-bpclermont.fr --
-- --
-- Jocelyn SEROT --
-- [email protected] --
-- --
-- Copyright 2011-2015 Jocelyn SEROT. All rights reserved. --
-- This file is distributed under the terms of the GNU Library General Public License --
-- with the special exception on linking described in file ../LICENSE. --
-- --
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
-- +--------------+
-- w_f | | w_e
-- <--------| |-------->
-- wi | | wo
-- -------->| PORT_BUFFER |-------->
-- w_wr | | w_rd
-- -------->| |<--------
-- | |
-- +--------------+
entity port_buffer is
generic ( size: integer := 10);
port ( w_f: out std_logic;
wi : in std_logic_vector (size-1 downto 0);
w_wr : in std_logic;
w_e : out std_logic;
wo : out std_logic_vector(size-1 downto 0);
w_rd : in std_logic;
clk: in std_logic;
rst: in std_logic
);
end port_buffer;
architecture rtl of port_buffer is
signal buf : std_logic_vector(size-1 downto 0);
begin
process (clk) is
begin
if ( rst='0' ) then
buf <= (others => '0');
elsif ( rising_edge(clk) ) then
if ( w_wr='1' ) then -- write
buf <= wi;
end if;
end if;
end process;
w_f <= '0';
w_e <= '0';
wo <= buf;
end rtl;
| gpl-3.0 | 19be53f13879dd284ac7d3091a8e8373 | 0.307294 | 4.817048 | false | false | false | false |
ou-cse-378/vhdl-tetris | opcodes.vhd | 1 | 3,275 | --Name:Brad McMahon
--File:Opcodes.vhd
--Date:
--Description:Opcode constants
--CSE 378
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package opcodes is
subtype opcode is std_logic_vector(15 downto 0);
-- Register instructions --WHYP WORDS
constant nop: opcode := X"0000"; -- NOP
constant dup: opcode := X"0001"; -- DUP
constant swap: opcode := X"0002"; -- SWAP
constant drop: opcode := X"0003"; -- DROP
constant over: opcode := X"0004"; -- OVER
constant rot: opcode := X"0005"; -- ROT
constant mrot: opcode := X"0006"; -- -ROT
constant nip: opcode := X"0007"; -- NIP
constant tuck: opcode := X"0008"; -- TUCK
constant rot_drop: opcode := X"0009"; -- ROT_DROP
constant rot_drop_swap: opcode := X"000A"; -- ROT_DROP_SWAP
-- Function unit instructions
constant plus: opcode := X"0010"; -- +
constant minus: opcode := X"0011"; -- -
constant plus1: opcode := X"0012"; -- 1+
constant minus1: opcode := X"0013"; -- 1-
constant invert: opcode := X"0014"; -- INVERT
constant andd: opcode := X"0015"; -- AND
constant orr: opcode := X"0016"; -- OR
constant xorr: opcode := X"0017"; -- XOR
constant twotimes: opcode := X"0018"; -- 2*
constant u2slash: opcode := X"0019"; -- U2/
constant twoslash: opcode := X"001A"; -- 2/
constant rshift: opcode := X"001B"; -- RSHIFT
constant lshift: opcode := X"001C"; -- LSHIFT
constant ones: opcode := X"0020"; -- TRUE
constant zeros: opcode := X"0021"; -- FALSE
constant zeroequal: opcode := X"0022"; -- 0=
constant zeroless: opcode := X"0023"; -- 0<
constant zerogreat: opcode := X"0f23"; -- 0>
constant ugt: opcode := X"0024"; -- U>
constant ult: opcode := X"0025"; -- U<
constant eq: opcode := X"0026"; -- =
constant ugte: opcode := X"0027"; -- U>=
constant ulte: opcode := X"0028"; -- U<=
constant neq: opcode := X"0029"; -- <>
constant gt: opcode := X"002A"; -- >
constant lt: opcode := X"002B"; -- <
constant gte: opcode := X"002C"; -- >=
constant lte: opcode := X"002D"; -- <=
-- I/O instructions
constant sfetch: opcode := X"0037"; -- S@
constant digstore: opcode := X"0038"; -- DIG!
constant scorefetch: opcode := X"0040"; -- score@
constant destrofetch: opcode := X"0041"; -- destrofetch
constant ClearLines: opcode := X"0042"; -- ClearLines
-- Transfer instructions
constant lit: opcode := X"0100"; -- LIT
constant jmp: opcode := X"0101"; -- AGAIN, ELSE
constant jz: opcode := X"0102"; -- IF, UNTIL
constant jb4HI: opcode := X"010D"; -- waitB4
constant jb4LO: opcode := X"0109";
-- Return Stack and I/O instructions
constant tor: opcode := X"0030";
constant rfrom: opcode := X"0031";
constant rfetch: opcode := X"0032";
constant rfromdrop: opcode := X"0033";
constant ldstore: opcode := X"0039";
-- Transfer Instructions
constant drjne: opcode :=X"0103";
constant call: opcode :=X"0104";
constant ret: opcode :=X"0105";
end opcodes;
| mit | 0bd79646985d58716da7de6e5c90832e | 0.571603 | 3.040854 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/openmacTop-rtl-ea.vhd | 3 | 69,050 | -------------------------------------------------------------------------------
--! @file openmacTop-rtl-ea.vhd
--
--! @brief OpenMAC toplevel file including openMAC, openHUB and openFILTER
--
--! @details This is the openMAC toplevel file including the MAC layer IP-Cores.
--! Additional components are provided for packet buffer storage.
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use openmac package
use work.openmacPkg.all;
entity openmacTop is
generic (
-----------------------------------------------------------------------
-- Phy configuration
-----------------------------------------------------------------------
--! Number of Phy ports
gPhyPortCount : natural := 2;
--! Phy port interface type (Rmii or Mii)
gPhyPortType : natural := cPhyPortRmii;
--! Number of SMI phy ports
gSmiPortCount : natural := 1;
-----------------------------------------------------------------------
-- General configuration
-----------------------------------------------------------------------
--! Endianness ("little" or "big")
gEndianness : string := "little";
--! Enable packet activity generator (e.g. connect to LED)
gEnableActivity : natural := cFalse;
--! Enable DMA observer circuit
gEnableDmaObserver : natural := cFalse;
-----------------------------------------------------------------------
-- DMA configuration
-----------------------------------------------------------------------
--! DMA address width (byte-addressing)
gDmaAddrWidth : natural := 32;
--! DMA data width
gDmaDataWidth : natural := 16;
--! DMA burst count width
gDmaBurstCountWidth : natural := 4;
--! DMA write burst length (Rx packets) [words]
gDmaWriteBurstLength : natural := 16;
--! DMA read burst length (Tx packets) [words]
gDmaReadBurstLength : natural := 16;
--! DMA write FIFO length (Rx packets) [words]
gDmaWriteFifoLength : natural := 16;
--! DMA read FIFO length (Tx packets) [words]
gDmaReadFifoLength : natural := 16;
-----------------------------------------------------------------------
-- Packet buffer configuration
-----------------------------------------------------------------------
--! Packet buffer location for Tx packets
gPacketBufferLocTx : natural := cPktBufLocal;
--! Packet buffer location for Rx packets
gPacketBufferLocRx : natural := cPktBufLocal;
--! Packet buffer log2(size) [log2(bytes)]
gPacketBufferLog2Size : natural := 10;
-----------------------------------------------------------------------
-- MAC timer configuration
-----------------------------------------------------------------------
--! Enable pulse timer
gTimerEnablePulse : natural := cFalse;
--! Enable timer pulse width control
gTimerEnablePulseWidth : natural := cFalse;
--! Timer pulse width register width
gTimerPulseRegWidth : natural := 10
);
port (
-----------------------------------------------------------------------
-- Clock and reset signal pairs
-----------------------------------------------------------------------
--! Main clock used for openMAC, openHUB and openFILTER (freq = 50 MHz)
iClk : in std_logic;
--! Main reset used for openMAC, openHUB and openFILTER
iRst : in std_logic;
--! DMA master clock
iDmaClk : in std_logic;
--! DMA master reset
iDmaRst : in std_logic;
--! Packet buffer clock
iPktBufClk : in std_logic;
--! Packet buffer reset
iPktBufRst : in std_logic;
--! Twice main clock used for Rmii Tx path
iClk2x : in std_logic;
-----------------------------------------------------------------------
-- MAC REG memory mapped slave
-----------------------------------------------------------------------
--! MM slave MAC REGISTER chipselect
iMacReg_chipselect : in std_logic;
--! MM slave MAC REGISTER write
iMacReg_write : in std_logic;
--! MM slave MAC REGISTER read
iMacReg_read : in std_logic;
--! MM slave MAC REGISTER waitrequest
oMacReg_waitrequest : out std_logic;
--! MM slave MAC REGISTER byteenable
iMacReg_byteenable : in std_logic_vector(cMacRegDataWidth/cByteLength-1 downto 0);
--! MM slave MAC REGISTER address
iMacReg_address : in std_logic_vector(cMacRegAddrWidth-1 downto 0);
--! MM slave MAC REGISTER writedata
iMacReg_writedata : in std_logic_vector(cMacRegDataWidth-1 downto 0);
--! MM slave MAC REGISTER readdata
oMacReg_readdata : out std_logic_vector(cMacRegDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- MAC TIMER memory mapped slave
-----------------------------------------------------------------------
--! MM slave MAC TIMER chipselect
iMacTimer_chipselect : in std_logic;
--! MM slave MAC TIMER write
iMacTimer_write : in std_logic;
--! MM slave MAC TIMER read
iMacTimer_read : in std_logic;
--! MM slave MAC TIMER waitrequest
oMacTimer_waitrequest : out std_logic;
--! MM slave MAC TIMER address
iMacTimer_address : in std_logic_vector(cMacTimerAddrWidth-1 downto 0);
--! MM slave MAC TIMER byteenable
iMacTimer_byteenable : in std_logic_vector(cMacTimerDataWidth/cByteLength-1 downto 0);
--! MM slave MAC TIMER writedata
iMacTimer_writedata : in std_logic_vector(cMacTimerDataWidth-1 downto 0);
--! MM slave MAC TIMER readdata
oMacTimer_readdata : out std_logic_vector(cMacTimerDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- MAC PACKET BUFFER memory mapped slave
-----------------------------------------------------------------------
--! MM slave MAC PACKET BUFFER chipselect
iPktBuf_chipselect : in std_logic;
--! MM slave MAC PACKET BUFFER write
iPktBuf_write : in std_logic;
--! MM slave MAC PACKET BUFFER read
iPktBuf_read : in std_logic;
--! MM slave MAC PACKET BUFFER waitrequest
oPktBuf_waitrequest : out std_logic;
--! MM slave MAC PACKET BUFFER byteenable
iPktBuf_byteenable : in std_logic_vector(cPktBufDataWidth/cByteLength-1 downto 0);
--! MM slave MAC PACKET BUFFER address (width given by gPacketBufferLog2Size)
iPktBuf_address : in std_logic_vector(gPacketBufferLog2Size-1 downto 0);
--! MM slave MAC PACKET BUFFER writedata
iPktBuf_writedata : in std_logic_vector(cPktBufDataWidth-1 downto 0);
--! MM slave MAC PACKET BUFFER readdata
oPktBuf_readdata : out std_logic_vector(cPktBufDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- MAC DMA memory mapped master
-----------------------------------------------------------------------
--! MM master MAC DMA write
oDma_write : out std_logic;
--! MM master MAC DMA read
oDma_read : out std_logic;
--! MM master MAC DMA waitrequest
iDma_waitrequest : in std_logic;
--! MM master MAC DMA readdatavalid
iDma_readdatavalid : in std_logic;
--! MM master MAC DMA byteenable
oDma_byteenable : out std_logic_vector(gDmaDataWidth/cByteLength-1 downto 0);
--! MM master MAC DMA address
oDma_address : out std_logic_vector(gDmaAddrWidth-1 downto 0);
--! MM master MAC DMA burstcount
oDma_burstcount : out std_logic_vector(gDmaBurstCountWidth-1 downto 0);
--! MM master MAC DMA burstcounter (holds current burst count value)
oDma_burstcounter : out std_logic_vector(gDmaBurstCountWidth-1 downto 0);
--! MM master MAC DMA writedata
oDma_writedata : out std_logic_vector(gDmaDataWidth-1 downto 0);
--! MM master MAC DMA readdata
iDma_readdata : in std_logic_vector(gDmaDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- Interrupts
-----------------------------------------------------------------------
--! MAC TIMER interrupt
oMacTimer_interrupt : out std_logic;
--! MAC TIMER pulse
oMacTimer_pulse : out std_logic;
--! MAC Tx interrupt
oMacTx_interrupt : out std_logic;
--! MAC Rx interrupt
oMacRx_interrupt : out std_logic;
-----------------------------------------------------------------------
-- Rmii Phy ports
-----------------------------------------------------------------------
--! Rmii Rx ports
iRmii_Rx : in tRmiiPathArray(gPhyPortCount-1 downto 0);
--! Rmii Rx error ports
iRmii_RxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Tx ports
oRmii_Tx : out tRmiiPathArray(gPhyPortCount-1 downto 0);
-----------------------------------------------------------------------
-- Mii Phy ports
-----------------------------------------------------------------------
--! Mii Rx ports
iMii_Rx : in tMiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Rx error ports
iMii_RxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Rx Clocks
iMii_RxClk : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Tx ports
oMii_Tx : out tMiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Tx Clocks
iMii_TxClk : in std_logic_vector(gPhyPortCount-1 downto 0);
-----------------------------------------------------------------------
-- Phy management interface
-----------------------------------------------------------------------
--! Phy reset (low-active)
onPhy_reset : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI clock
oSmi_clk : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data output enable (tri-state buffer)
oSmi_data_outEnable : out std_logic;
--! SMI data output (tri-state buffer)
oSmi_data_out : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data input (tri-state buffer)
iSmi_data_in : in std_logic_vector(gSmiPortCount-1 downto 0);
-----------------------------------------------------------------------
-- Other ports
-----------------------------------------------------------------------
--! Packet activity (enabled with gEnableActivity)
oActivity : out std_logic
);
end openmacTop;
architecture rtl of openmacTop is
---------------------------------------------------------------------------
-- Constants
---------------------------------------------------------------------------
--! Lowest index of Phy port
constant cPhyPortLow : natural := cHubIntPort+1;
--! Highest index of Phy port
constant cPhyPortHigh : natural := gPhyPortCount+1;
--! Enable packet buffer interface
constant cEnablePacketBuffer : boolean := (
gPacketBufferLocRx = cPktBufLocal or gPacketBufferLocTx = cPktBufLocal
);
--! Enable dma interface
constant cEnableDma : boolean := (
gPacketBufferLocRx = cPktBufExtern or gPacketBufferLocTx = cPktBufExtern
);
--! Fixed openMAC DMA address width
constant cDmaAddrWidth : natural := 32;
---------------------------------------------------------------------------
-- Component types
---------------------------------------------------------------------------
--! openMAC port type
type tOpenMacPort is record
rst : std_logic;
clk : std_logic;
nReg_write : std_logic;
reg_selectRam : std_logic;
reg_selectCont : std_logic;
nReg_byteenable : std_logic_vector(1 downto 0);
reg_address : std_logic_vector(10 downto 1);
reg_writedata : std_logic_vector(15 downto 0);
reg_readdata : std_logic_vector(15 downto 0);
nTxInterrupt : std_logic;
nRxInterrupt : std_logic;
dma_readDone : std_logic;
dma_writeDone : std_logic;
dma_request : std_logic;
nDma_write : std_logic;
dma_acknowledge : std_logic;
dma_requestOverflow : std_logic;
dma_readLength : std_logic_vector(11 downto 0);
dma_address : std_logic_vector(cDmaAddrWidth-1 downto 1);
dma_writedata : std_logic_vector(15 downto 0);
dma_readdata : std_logic_vector(15 downto 0);
rmii : tRmii;
hubRxPort : std_logic_vector(1 downto 0);
macTime : std_logic_vector(cMacTimeWidth-1 downto 0);
end record;
--! Phy management port type
type tPhyMgmtPort is record
rst : std_logic;
clk : std_logic;
address : std_logic_vector(3 downto 1);
chipselect : std_logic;
nByteenable : std_logic_vector(1 downto 0);
nWrite : std_logic;
writedata : std_logic_vector(15 downto 0);
readdata : std_logic_vector(15 downto 0);
smiClk : std_logic;
smiDataIn : std_logic;
smiDataOut : std_logic;
smiDataOutEnable : std_logic;
nPhyReset : std_logic;
end record;
--! openMAC TIMER port type
type tOpenMacTimerPort is record
rst : std_logic;
clk : std_logic;
write : std_logic;
address : std_logic_vector(cMacTimerAddrWidth-1 downto 2);
byteenable : std_logic_vector(3 downto 0);
writedata : std_logic_vector(31 downto 0);
readdata : std_logic_vector(31 downto 0);
macTime : std_logic_vector(cMacTimeWidth-1 downto 0);
interrupt : std_logic;
pulse : std_logic;
end record;
--! openHUB port type
type tOpenHubPort is record
rst : std_logic;
clk : std_logic;
rx : tRmiiPathArray(cPhyPortHigh downto cHubIntPort);
tx : tRmiiPathArray(cPhyPortHigh downto cHubIntPort);
internPort : integer range cHubIntPort to cPhyPortHigh;
transmitMask : std_logic_vector(cPhyPortHigh downto cHubIntPort);
receivePort : integer range 0 to cPhyPortHigh;
end record;
--! openFILTER port type
type tOpenFilterPort is record
rst : std_logic;
clk : std_logic;
rxIn : tRmiiPathArray(cPhyPortHigh downto cPhyPortLow);
rxOut : tRmiiPathArray(cPhyPortHigh downto cPhyPortLow);
txIn : tRmiiPathArray(cPhyPortHigh downto cPhyPortLow);
txOut : tRmiiPathArray(cPhyPortHigh downto cPhyPortLow);
rxError : std_logic_vector(cPhyPortHigh downto cPhyPortLow);
end record;
--! RMII-to-MII converter port type
type tConvRmiiToMiiPort is record
rst : std_logic;
clk : std_logic;
rmiiTx : tRmiiPathArray(cPhyPortHigh downto cPhyPortLow);
rmiiRx : tRmiiPathArray(cPhyPortHigh downto cPhyPortLow);
miiTx : tMiiPathArray(cPhyPortHigh downto cPhyPortLow);
miiTxClk : std_logic_vector(cPhyPortHigh downto cPhyPortLow);
miiRx : tMiiPathArray(cPhyPortHigh downto cPhyPortLow);
miiRxError : std_logic_vector(cPhyPortHigh downto cPhyPortLow);
miiRxClk : std_logic_vector(cPhyPortHigh downto cPhyPortLow);
end record;
--! Packet Buffer single port type
type tPacketBufferSinglePort is record
clk : std_logic;
rst : std_logic;
enable : std_logic;
write : std_logic;
address : std_logic_vector(gPacketBufferLog2Size-1 downto logDualis(cPktBufDataWidth/cByteLength));
byteenable : std_logic_vector(cPktBufDataWidth/cByteLength-1 downto 0);
writedata : std_logic_vector(cPktBufDataWidth-1 downto 0);
readdata : std_logic_vector(cPktBufDataWidth-1 downto 0);
end record;
--! Packet Buffer dual port type (port to DMA and host)
type tPacketBufferPort is record
dma : tPacketBufferSinglePort;
dma_ack : std_logic;
dma_highWordSel : std_logic;
host : tPacketBufferSinglePort;
end record;
--! DMA port type
type tDmaMaster_dmaPort is record
clk : std_logic;
rst : std_logic; --FIXME: Rename in openMAC_DMAmaster
reqWrite : std_logic;
reqRead : std_logic;
reqOverflow : std_logic;
ackWrite : std_logic;
ackRead : std_logic;
readError : std_logic;
readLength : std_logic_vector(11 downto 0);
writeError : std_logic;
address : std_logic_vector(gDmaAddrWidth-1 downto 1);
writedata : std_logic_vector(15 downto 0);
readdata : std_logic_vector(15 downto 0);
end record;
--! Master port type
type tDmaMaster_masterPort is record
clk : std_logic;
rst : std_logic; --FIXME: Add to openMAC_DMAmaster
write : std_logic;
read : std_logic;
readdatavalid : std_logic;
waitrequest : std_logic;
address : std_logic_vector(gDmaAddrWidth-1 downto 0);
byteenable : std_logic_vector(gDmaDataWidth/cByteLength-1 downto 0);
burstcount : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
burstcounter : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
writedata : std_logic_vector(gDmaDataWidth-1 downto 0);
readdata : std_logic_vector(gDmaDataWidth-1 downto 0);
end record;
--! DMA Master port type
type tDmaMasterPort is record
dma : tDmaMaster_dmaPort;
master : tDmaMaster_masterPort;
mac_rxOff : std_logic;
mac_txOff : std_logic;
end record;
--! Activity port type
type tActivityPort is record
clk : std_logic;
rst : std_logic;
txEnable : std_logic;
rxDataValid : std_logic;
activity : std_logic;
end record;
---------------------------------------------------------------------------
-- Configuration
---------------------------------------------------------------------------
-- MAC TIMER
--! Function to convert number of timers into generate boolean for
--! second timer.
function macTimer_gen2ndTimer (timerCnt : natural) return boolean is
variable vRet_tmp : boolean;
begin
--default
vRet_tmp := FALSE;
case timerCnt is
when 1 =>
vRet_tmp := FALSE;
when 2 =>
vRet_tmp := TRUE;
when others =>
assert (FALSE)
report "The MAC TIMER only supports 1 and 2 timers!"
severity failure;
end case;
return vRet_tmp;
end function macTimer_gen2ndTimer;
--! MAC Timer generate second compare timer
constant cMacTimer_2ndTimer : boolean := (gTimerEnablePulse = cTrue);
---------------------------------------------------------------------------
-- Memory map
---------------------------------------------------------------------------
--! Select vector for MacReg
signal selVector_macReg : std_logic_vector(cMemMapCount-1 downto 0);
--! Alias for select DMA Error
alias sel_dmaError : std_logic is selVector_macReg(cMemMapIndex_dmaError);
--! Alias for select IRQ Table
alias sel_irqTable : std_logic is selVector_macReg(cMemMapIndex_irqTable);
--! Alias for select SMI
alias sel_smi : std_logic is selVector_macReg(cMemMapIndex_smi);
--! Alias for select MAC RAM
alias sel_macRam : std_logic is selVector_macReg(cMemMapIndex_macRam);
--! Alias for select MAC Filter
alias sel_macFilter : std_logic is selVector_macReg(cMemMapIndex_macFilter);
--! Alias for select MAC Content
alias sel_macCont : std_logic is selVector_macReg(cMemMapIndex_macCont);
--! Acknowledge vector for MacReg
signal ackVector : tMemAccessAckArray(cMemAccessDelayCount-1 downto 0);
--! Alias for acknowledge PKT BUF
alias ack_pktBuf : tMemAccessAck is ackVector(cMemAccessDelayIndex_pktBuf);
--! Alias for acknowledge MAC TIMER
alias ack_macTimer : tMemAccessAck is ackVector(cMemAccessDelayIndex_macTimer);
--! Alias for acknowledge MAC REG
alias ack_macReg : tMemAccessAck is ackVector(cMemAccessDelayIndex_macReg);
---------------------------------------------------------------------------
-- Interrupt signals
---------------------------------------------------------------------------
--! Interrupt table vector
signal irqTable : tMacRegIrqTable;
---------------------------------------------------------------------------
-- DMA error signals
---------------------------------------------------------------------------
--! DMA error table
signal dmaErrorTable : tMacDmaErrorTable;
---------------------------------------------------------------------------
-- RMII registers for latching input and output path (improves timing)
---------------------------------------------------------------------------
--! Rmii Rx paths
signal rmiiRxPath_reg : tRmiiPathArray(gPhyPortCount-1 downto 0)
:= (others => cRmiiPathInit); -- avoid warnings
--! Rmii Rx error paths
signal rmiiRxPathError_reg : std_logic_vector(gPhyPortCount-1 downto 0)
:= (others => cInactivated); -- avoid warnings
--! Rmii Tx paths
signal rmiiTxPath_reg : tRmiiPathArray(gPhyPortCount-1 downto 0)
:= (others => cRmiiPathInit); -- avoid warnings
---------------------------------------------------------------------------
-- MII signals
---------------------------------------------------------------------------
--! Mii Tx paths
signal miiTxPath : tMiiPathArray(gPhyPortCount-1 downto 0);
---------------------------------------------------------------------------
-- Instances
---------------------------------------------------------------------------
--! Instance openMAC port
signal inst_openmac : tOpenMacPort;
--! Instance phy management port
signal inst_phyMgmt : tPhyMgmtPort;
--! Instance openMAC TIMER port
signal inst_openmacTimer : tOpenMacTimerPort;
--! Instance openHUB port
signal inst_openhub : tOpenHubPort;
--! Instances openFILTER port
signal inst_openfilter : tOpenFilterPort;
--! Instances RMII-to-MII converter port
signal inst_convRmiiToMii : tConvRmiiToMiiPort;
--! Instance Packet buffer port
signal inst_pktBuffer : tPacketBufferPort;
--! Instance DMA master port
signal inst_dmaMaster : tDmaMasterPort;
--! Instance activity port
signal inst_activity : tActivityPort;
begin
---------------------------------------------------------------------------
-- Assign toplevel
---------------------------------------------------------------------------
--! In this block the entity's output ports are assigned to internals.
TOPLEVELMAP : block
begin
--! This process assigns the oMacReg_readdata port to the selected
--! memory.
ASSIGN_MACREG_RDDATA : process (
selVector_macReg,
irqTable,
dmaErrorTable,
iMacReg_byteenable,
inst_openmac.reg_readdata,
inst_phyMgmt.readdata
)
begin
--default assignment
oMacReg_readdata <= (others => cInactivated);
if sel_macRam = cActivated or sel_macCont = cActivated then
oMacReg_readdata <= inst_openmac.reg_readdata;
-- swap bytes if big endian and selected word
if gEndianness = "big" and iMacReg_byteenable = "11" then
oMacReg_readdata <= byteSwap(inst_openmac.reg_readdata);
end if;
elsif sel_smi = cActivated then
oMacReg_readdata <= inst_phyMgmt.readdata;
-- swap bytes if big endian and selected word
if gEndianness = "big" and iMacReg_byteenable = "11" then
oMacReg_readdata <= byteSwap(inst_phyMgmt.readdata);
end if;
elsif sel_irqTable = cActivated then
oMacReg_readdata <= irqTable;
-- swap bytes if big endian
if gEndianness = "big" then
oMacReg_readdata <= byteSwap(irqTable);
end if;
elsif sel_dmaError = cActivated then
oMacReg_readdata <= dmaErrorTable;
-- swap byte if big endian
if gEndianness = "big" then
oMacReg_readdata <= byteSwap(dmaErrorTable);
end if;
end if;
end process ASSIGN_MACREG_RDDATA;
oMacReg_waitrequest <= not(ack_macReg.write or ack_macReg.read);
oMacTimer_readdata <= inst_openmacTimer.readdata;
oMacTimer_waitrequest <= not(ack_macTimer.write or ack_macTimer.read);
oPktBuf_readdata <= inst_pktBuffer.host.readdata when cEnablePacketBuffer else
(others => cInactivated);
oPktBuf_waitrequest <= not(ack_pktBuf.write or ack_pktBuf.read) when cEnablePacketBuffer else
cActivated;
oDma_address <= inst_dmaMaster.master.address when cEnableDma else
(others => cInactivated);
oDma_burstcount <= inst_dmaMaster.master.burstcount when cEnableDma else
(others => cInactivated);
oDma_burstcounter <= inst_dmaMaster.master.burstcounter when cEnableDma else
(others => cInactivated);
oDma_byteenable <= inst_dmaMaster.master.byteenable when cEnableDma else
(others => cInactivated);
oDma_read <= inst_dmaMaster.master.read when cEnableDma else
cInactivated;
oDma_write <= inst_dmaMaster.master.write when cEnableDma else
cInactivated;
oDma_writedata <= inst_dmaMaster.master.writedata when cEnableDma else
(others => cInactivated);
oMacTimer_interrupt <= inst_openmacTimer.interrupt;
oMacTimer_pulse <= inst_openmacTimer.pulse;
oMacTx_interrupt <= not inst_openmac.nTxInterrupt;
oMacRx_interrupt <= not inst_openmac.nRxInterrupt;
oRmii_Tx <= rmiiTxPath_reg when gPhyPortType = cPhyPortRmii else
(others => cRmiiPathInit);
oMii_Tx <= miiTxPath when gPhyPortType = cPhyPortMii else
(others => cMiiPathInit);
oSmi_clk <= (others => inst_phyMgmt.smiClk);
oSmi_data_out <= (others => inst_phyMgmt.smiDataOut);
oSmi_data_outEnable <= inst_phyMgmt.smiDataOutEnable;
onPhy_reset <= (others => inst_phyMgmt.nPhyReset);
oActivity <= inst_activity.activity when gEnableActivity = cTrue else
cInactivated;
end block TOPLEVELMAP;
---------------------------------------------------------------------------
-- Assign instances
---------------------------------------------------------------------------
--! In this block the instances are assigned.
INSTANCEMAP : block
begin
-----------------------------------------------------------------------
-- The openMAC
-----------------------------------------------------------------------
inst_openmac.rst <= iRst;
inst_openmac.clk <= iClk;
inst_openmac.nReg_write <= not iMacReg_write;
inst_openmac.reg_selectRam <= sel_macRam;
inst_openmac.reg_selectCont <= sel_macCont;
inst_openmac.nReg_byteenable <= not iMacReg_byteenable;
inst_openmac.reg_address <= iMacReg_address(inst_openmac.reg_address'range);
--! This process assignes the register writedata. Additionally the DMA
--! read path and the request acknowlegde signals are assigned from the
--! configured sources (packet buffer vs. DMA).
ASSIGN_MAC : process (
iMacReg_writedata,
iMacReg_byteenable,
inst_pktBuffer,
inst_dmaMaster
)
--! DMA ack variable for or'ing all those acks.
variable vAck_tmp : std_logic;
--! Alias for packet buffer high word
alias pktBufRead_high : std_logic_vector(15 downto 0) is
inst_pktBuffer.dma.readdata(cPktBufDataWidth-1 downto cPktBufDataWidth/2);
--! Alias for packet buffer low word
alias pktBufRead_low : std_logic_vector(15 downto 0) is
inst_pktBuffer.dma.readdata(cPktBufDataWidth/2-1 downto 0);
begin
-- no defaults, so take care!
-------------------------------------------------------------------
-- writedata is directly assigned, or byte-swapped
inst_openmac.reg_writedata <= iMacReg_writedata;
-- swap bytes if big endian and selected word
if gEndianness = "big" and iMacReg_byteenable = "11" then
inst_openmac.reg_writedata <= byteSwap(iMacReg_writedata);
end if;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Initialize the ack variable to zero, then or it with all sources.
vAck_tmp := cInactivated;
-- Assign read acknowledge.
case gPacketBufferLocTx is
when cPktBufExtern =>
-- Tx packets come from DMA master
vAck_tmp := vAck_tmp or inst_dmaMaster.dma.ackRead;
when cPktBufLocal =>
-- Tx packets come from packet buffer
vAck_tmp := vAck_tmp or inst_pktBuffer.dma_ack;
when others =>
assert (FALSE)
report "The Tx packet buffer location is unknown! Don't know how to ack!"
severity failure;
end case;
-- Assign write acknowledge.
case gPacketBufferLocRx is
when cPktBufExtern =>
-- Rx packets go to DMA master
vAck_tmp := vAck_tmp or inst_dmaMaster.dma.ackWrite;
when cPktBufLocal =>
-- Rx packets go to packet buffer
vAck_tmp := vAck_tmp or inst_pktBuffer.dma_ack;
when others =>
assert (FALSE)
report "The Rx packet buffer location is unknown! Don't know how to ack!"
severity failure;
end case;
-- Assign the variable state to the signal.
inst_openmac.dma_acknowledge <= vAck_tmp;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Decide on the readdata source for the DMA.
case gPacketBufferLocTx is
when cPktBufExtern =>
-- Tx packet come from DMA master
inst_openmac.dma_readdata <= inst_dmaMaster.dma.readdata;
when cPktBufLocal =>
-- Tx packets come from packet buffer, but select the right word
if inst_pktBuffer.dma_highWordSel = cActivated then
inst_openmac.dma_readdata <= pktBufRead_high;
else
inst_openmac.dma_readdata <= pktBufRead_low;
end if;
when others =>
assert (FALSE)
report "The Tx packet buffer location is unknown! Don't know the source!"
severity failure;
end case;
end process ASSIGN_MAC;
-- Note that internal port is crossed!
inst_openmac.rmii.rx <= inst_openhub.tx(cHubIntPort);
-- Clip the hub receive port to two bits
inst_openmac.hubRxPort <= std_logic_vector(
resize(
to_unsigned(inst_openhub.receivePort, logDualis(cPhyPortHigh)),
inst_openmac.hubRxPort'length)
);
-- Assign interrupts to irq Table
irqTable <= (
cMacRegIrqTable_macRx => not inst_openmac.nRxInterrupt,
cMacRegIrqTable_macTx => not inst_openmac.nTxInterrupt,
others => cInactivated
);
-----------------------------------------------------------------------
-- The phy management
-----------------------------------------------------------------------
inst_phyMgmt.clk <= iClk;
inst_phyMgmt.rst <= iRst;
inst_phyMgmt.address <= iMacReg_address(inst_phyMgmt.address'range);
inst_phyMgmt.chipselect <= sel_smi;
inst_phyMgmt.nByteenable <= not iMacReg_byteenable;
inst_phyMgmt.nWrite <= not iMacReg_write;
inst_phyMgmt.writedata <= iMacReg_writedata when gEndianness = "little" else
iMacReg_writedata when gEndianness = "big" and iMacReg_byteenable /= "11" else
byteSwap(iMacReg_writedata);
inst_phyMgmt.smiDataIn <= reduceAnd(iSmi_data_in);
-----------------------------------------------------------------------
-- The openMAC timer
-----------------------------------------------------------------------
inst_openmacTimer.clk <= iClk;
inst_openmacTimer.rst <= iRst;
inst_openmacTimer.write <= iMacTimer_write and iMacTimer_chipselect;
inst_openmacTimer.address <= iMacTimer_address(inst_openmacTimer.address'range);
inst_openmacTimer.byteenable <= iMacTimer_byteenable;
inst_openmacTimer.writedata <= iMacTimer_writedata;
-- this is the mac time
inst_openmacTimer.macTime <= inst_openmac.macTime;
-----------------------------------------------------------------------
-- The openHUB
-----------------------------------------------------------------------
inst_openhub.rst <= iRst;
inst_openhub.clk <= iClk;
inst_openhub.internPort <= cHubIntPort;
-- Enable all ports
inst_openhub.transmitMask <= (others => cActivated);
--! This process simply assigns the hub ports.
ASSIGN_HUB : process (
inst_openmac.rmii.tx,
inst_openfilter
)
begin
-- no defaults, so take care!
-- Loop through phy ports and internal hub port (MAC).
for i in cPhyPortHigh downto cHubIntPort loop
-- Assign internal port to mac, others to filter.
if i = cHubIntPort then
-- Note that internal port is crossed!
inst_openhub.rx(i) <= inst_openmac.rmii.tx;
else
inst_openhub.rx(i) <= inst_openfilter.rxOut(i);
end if;
end loop;
end process ASSIGN_HUB;
-----------------------------------------------------------------------
-- The openFILTER(s)
-----------------------------------------------------------------------
inst_openfilter.rst <= iRst;
inst_openfilter.clk <= iClk;
--! This process assigns the phy ports to the generated filters.
ASSIGN_FILTERS : process (
inst_convRmiiToMii,
inst_openhub,
rmiiRxPath_reg,
rmiiRxPathError_reg
)
begin
-- no defaults, so take care!
-- Loop through phy ports only (internal hub port is skipped).
for i in cPhyPortHigh downto cPhyPortLow loop
-- assign from phy or RMII-to-MII converter
case gPhyPortType is
when cPhyPortRmii =>
inst_openfilter.rxIn(i) <= rmiiRxPath_reg(i-(cPhyPortLow));
inst_openfilter.rxError(i) <= rmiiRxPathError_reg(i-(cPhyPortLow));
when cPhyPortMii =>
inst_openfilter.rxIn(i) <= inst_convRmiiToMii.rmiiRx(i);
-- Filter Rx error is always zero, since converter already dumps packets!
inst_openfilter.rxError(i) <= cInactivated;
when others =>
assert (FALSE)
report "Wrong phy port type in ASSIGN_FILTERS!"
severity failure;
end case;
-- assign from hub
inst_openfilter.txIn(i) <= inst_openhub.tx(i);
end loop;
end process ASSIGN_FILTERS;
-----------------------------------------------------------------------
-- The RMII-to-MII converter(s)
-----------------------------------------------------------------------
inst_convRmiiToMii.clk <= iClk;
inst_convRmiiToMii.rst <= iRst;
inst_convRmiiToMii.rmiiTx <= inst_openfilter.txOut;
inst_convRmiiToMii.miiRx <= iMii_Rx;
inst_convRmiiToMii.miiRxError <= iMii_RxError;
inst_convRmiiToMii.miiRxClk <= iMii_RxClk;
inst_convRmiiToMii.miiTxClk <= iMii_TxClk;
-----------------------------------------------------------------------
-- The PACKET BUFFER
-----------------------------------------------------------------------
-- Assign DMA port side
inst_pktBuffer.dma.clk <= inst_openmac.clk;
inst_pktBuffer.dma.rst <= inst_openmac.rst;
inst_pktBuffer.dma.enable <= cActivated;
-- Note: DMA has data width of 16 bit and Packet Buffer DPRAM hsa 32 bit.
-- => Conversion necessary!
assert ((cPktBufDataWidth = 32) and (inst_openmac.dma_writedata'length = 16))
report "Revise DMA to packet store path. Implementation is fixed to 32/16!"
severity failure;
--! This process assigns the openMAC DMA ports to the packet buffer.
ASSIGN_DMAPORT : process (
inst_openmac
)
--! This variable is assigned to the DMA's word address
variable vDmaAddrWord_tmp : std_logic_vector(inst_openmac.dma_address'range);
--! This variable is assigned to the DMA's dword address
variable vDmaAddrDword_tmp : std_logic_vector(vDmaAddrWord_tmp'left downto 2);
begin
-- no defaults, so take care!
-- Assign DMA address to variables
vDmaAddrWord_tmp := inst_openmac.dma_address;
vDmaAddrDword_tmp := vDmaAddrWord_tmp(vDmaAddrDword_tmp'range); -- only assigned LEFT downto 2
-- Packet buffer address is for 32 bit (dwords)
inst_pktBuffer.dma.address <= std_logic_vector(resize(
unsigned(vDmaAddrDword_tmp),
inst_pktBuffer.dma.address'length)
);
-- DMA writes words, so duplicate words to packet buffer
inst_pktBuffer.dma.writedata <= inst_openmac.dma_writedata & inst_openmac.dma_writedata;
-- Packet buffer write strobe is logically and'd of request and write
-- Also the packet location is considered!
if (inst_openmac.dma_request = cActivated and
inst_openmac.nDma_write = cnActivated and
gPacketBufferLocRx = cPktBufLocal) then
inst_pktBuffer.dma.write <= cActivated;
else
inst_pktBuffer.dma.write <= cInactivated;
end if;
-- Duplicated words are present at writeport, select DMA's word addr bit
if vDmaAddrWord_tmp(vDmaAddrWord_tmp'right) = cActivated then
-- select high word
inst_pktBuffer.dma.byteenable <= "1100";
else
-- select low word
inst_pktBuffer.dma.byteenable <= "0011";
end if;
end process ASSIGN_DMAPORT;
-- Assign Host port side
inst_pktBuffer.host.clk <= iPktBufClk;
inst_pktBuffer.host.rst <= iPktBufRst;
inst_pktBuffer.host.enable <= cActivated;
inst_pktBuffer.host.write <= iPktBuf_chipselect and iPktBuf_write;
inst_pktBuffer.host.byteenable <= iPktBuf_byteenable;
inst_pktBuffer.host.address <= iPktBuf_address(inst_pktBuffer.host.address'range);
inst_pktBuffer.host.writedata <= iPktBuf_writedata;
-----------------------------------------------------------------------
-- The DMA master
-----------------------------------------------------------------------
inst_dmaMaster.dma.clk <= inst_openmac.clk;
inst_dmaMaster.dma.rst <= inst_openmac.rst;
inst_dmaMaster.dma.reqWrite <= inst_openmac.dma_request and not inst_openmac.nDma_write;
inst_dmaMaster.dma.reqRead <= inst_openmac.dma_request and inst_openmac.nDma_write;
inst_dmaMaster.dma.reqOverflow <= inst_openmac.dma_requestOverflow;
inst_dmaMaster.dma.readLength <= inst_openmac.dma_readLength;
inst_dmaMaster.dma.address <= std_logic_vector(resize(
unsigned(inst_openmac.dma_address),
inst_dmaMaster.dma.address'length)
);
inst_dmaMaster.dma.writedata <= inst_openmac.dma_writedata;
inst_dmaMaster.master.clk <= iDmaClk;
inst_dmaMaster.master.rst <= iDmaRst;
inst_dmaMaster.master.readdatavalid <= iDma_readdatavalid;
inst_dmaMaster.master.waitrequest <= iDma_waitrequest;
inst_dmaMaster.master.readdata <= iDma_readdata;
inst_dmaMaster.mac_rxOff <= inst_openmac.dma_writeDone;
inst_dmaMaster.mac_txOff <= inst_openmac.dma_readDone;
-- Assign DMA error table
dmaErrorTable <= (
cMacDmaErrorTable_read => inst_dmaMaster.dma.readError,
cMacDmaErrorTable_write => inst_dmaMaster.dma.writeError,
others => cInactivated
);
-----------------------------------------------------------------------
-- The activity generator
-----------------------------------------------------------------------
inst_activity.clk <= inst_openmac.clk;
inst_activity.rst <= inst_openmac.rst;
inst_activity.rxDataValid <= inst_openmac.rmii.rx.enable;
inst_activity.txEnable <= inst_openmac.rmii.tx.enable;
end block INSTANCEMAP;
---------------------------------------------------------------------------
-- Component instatiations
---------------------------------------------------------------------------
--! The openMAC core instance implements the MAC-layer.
--! All features are enabled to provide time-triggered packet Tx and
--! dynamic response delay.
THEOPENMAC : entity work.openmac
generic map (
gDmaHighAddr => cDmaAddrWidth-1,
gTimerEnable => TRUE,
gTimerTrigTx => TRUE,
gAutoTxDel => TRUE
)
port map (
iRst => inst_openmac.rst,
iClk => inst_openmac.clk,
inWrite => inst_openmac.nReg_write,
iSelectRam => inst_openmac.reg_selectRam,
iSelectCont => inst_openmac.reg_selectCont,
inByteenable => inst_openmac.nReg_byteenable,
iAddress => inst_openmac.reg_address,
iWritedata => inst_openmac.reg_writedata,
oReaddata => inst_openmac.reg_readdata,
onTxIrq => inst_openmac.nTxInterrupt,
onRxIrq => inst_openmac.nRxInterrupt,
onTxBegIrq => open, --unused interrupt
oDmaReadDone => inst_openmac.dma_readDone,
oDmaWriteDone => inst_openmac.dma_writeDone,
oDmaReq => inst_openmac.dma_request,
onDmaWrite => inst_openmac.nDma_write,
iDmaAck => inst_openmac.dma_acknowledge,
oDmaReqOverflow => inst_openmac.dma_requestOverflow,
oDmaReadLength => inst_openmac.dma_readLength,
oDmaAddress => inst_openmac.dma_address,
oDmaWritedata => inst_openmac.dma_writedata,
iDmaReaddata => inst_openmac.dma_readdata,
iRxData => inst_openmac.rmii.rx.data,
iRxDv => inst_openmac.rmii.rx.enable,
oTxData => inst_openmac.rmii.tx.data,
oTxEn => inst_openmac.rmii.tx.enable,
iHubRxPort => inst_openmac.hubRxPort,
oMacTime => inst_openmac.macTime
);
--! The phy management core is an SMI master to communication with the
--! phys.
THEPHYMGMT : entity work.phyMgmt
port map (
iRst => inst_phyMgmt.rst,
iClk => inst_phyMgmt.clk,
iAddress => inst_phyMgmt.address,
iSelect => inst_phyMgmt.chipselect,
inByteenable => inst_phyMgmt.nByteenable,
inWrite => inst_phyMgmt.nWrite,
iWritedata => inst_phyMgmt.writedata,
oReaddata => inst_phyMgmt.readdata,
oSmiClk => inst_phyMgmt.smiClk,
iSmiDataIn => inst_phyMgmt.smiDataIn,
oSmiDataOut => inst_phyMgmt.smiDataOut,
oSmiDataOutEnable => inst_phyMgmt.smiDataOutEnable,
onPhyReset => inst_phyMgmt.nPhyReset
);
--! The openMAC timer instance provides hardware timers referencing to the
--! openMAC's MAC Time (Mac_Zeit).
THEOPENMACTIMER : entity work.openmacTimer
generic map (
gMacTimeWidth => cMacTimeWidth,
gMacTimer_2ndTimer => cMacTimer_2ndTimer,
gTimerPulseRegWidth => gTimerPulseRegWidth,
gTimerEnablePulseWidth => (gTimerEnablePulseWidth /= cFalse)
)
port map (
iRst => inst_openmacTimer.rst,
iClk => inst_openmacTimer.clk,
iWrite => inst_openmacTimer.write,
iAddress => inst_openmacTimer.address,
iByteenable => inst_openmacTimer.byteenable,
iWritedata => inst_openmacTimer.writedata,
oReaddata => inst_openmacTimer.readdata,
iMacTime => inst_openmacTimer.macTime,
oIrq => inst_openmacTimer.interrupt,
oPulse => inst_openmacTimer.pulse
);
---------------------------------------------------------------------------
-- Conditional component instatiations
---------------------------------------------------------------------------
--! Generate address decoders for MAC REG memory map.
GENMACREG_ADDRDEC : for i in cMemMapTable'range generate
THEADDRDEC : entity libcommon.addrDecode
generic map (
gAddrWidth => iMacReg_address'length,
gBaseAddr => cMemMapTable(i).base,
gHighAddr => cMemMapTable(i).high
)
port map (
iEnable => iMacReg_chipselect,
iAddress => iMacReg_address,
oSelect => selVector_macReg(i)
);
end generate GENMACREG_ADDRDEC;
--! Generate write/read acknowlegde for MAC REG, MAC TIMER and PKT BUFFER.
GENMACREG_ACK : for i in cMemAccessDelayTable'range generate
signal selAndWrite : std_logic;
signal selAndRead : std_logic;
signal ackRst : std_logic;
signal ackClk : std_logic;
begin
--! Assign the corresponding clock and reset signals.
ASSIGN_CLKRST : process (
iClk,
iPktBufClk,
iRst,
iPktBufRst
)
begin
-- no defaults, so take care!
case i is
when cMemAccessDelayIndex_pktBuf =>
ackClk <= iPktBufClk;
ackRst <= iPktBufRst;
when cMemAccessDelayIndex_macTimer =>
ackClk <= iClk;
ackRst <= iRst;
when cMemAccessDelayIndex_macReg =>
ackClk <= iClk;
ackRst <= iRst;
when others =>
assert (FALSE)
report "Unknown access delay index. Don't know which ackClk/ackRst to use!"
severity failure;
end case;
end process ASSIGN_CLKRST;
--! This process assigns the selAndWrite and selAndRead signals used
--! to enable the acknowledge generators.
ASSIGN_SELANDRW : process (
iPktBuf_chipselect,
iPktBuf_write,
iPktBuf_read,
iMacTimer_chipselect,
iMacTimer_write,
iMacTimer_read,
iMacReg_chipselect,
iMacReg_write,
iMacReg_read
)
begin
--default
selAndWrite <= cInactivated;
selAndRead <= cInactivated;
case i is
when cMemAccessDelayIndex_pktBuf =>
selAndWrite <= iPktBuf_chipselect and iPktBuf_write;
selAndRead <= iPktBuf_chipselect and iPktBuf_read;
when cMemAccessDelayIndex_macTimer =>
selAndWrite <= iMacTimer_chipselect and iMacTimer_write;
selAndRead <= iMacTimer_chipselect and iMacTimer_read;
when cMemAccessDelayIndex_macReg =>
selAndWrite <= iMacReg_chipselect and iMacReg_write;
selAndRead <= iMacReg_chipselect and iMacReg_read;
when others =>
assert (FALSE)
report "For generate overrun! Check cMemAccessDelayTable!"
severity failure;
end case;
end process ASSIGN_SELANDRW;
--! Generate ack delay for writes.
GENWR_ACKDELAY : if cMemAccessDelayTable(i).write > 0 generate
THE_CNT : entity libcommon.cnt
generic map (
gCntWidth => logDualis(cMemAccessDelayTable(i).write + 1),
gTcntVal => cMemAccessDelayTable(i).write
)
port map (
iArst => ackRst,
iClk => ackClk,
iEnable => selAndWrite,
iSrst => cInactivated,
oCnt => open,
oTcnt => ackVector(i).write
);
end generate GENWR_ACKDELAY;
--! Generate no ack delay for writes.
GENWR_NOACKDELAY : if cMemAccessDelayTable(i).write = 0 generate
ackVector(i).write <= selAndWrite;
end generate GENWR_NOACKDELAY;
--! Generate ack delay for reads.
GENRD_ACKDELAY : if cMemAccessDelayTable(i).read > 0 generate
THE_CNT : entity libcommon.cnt
generic map (
gCntWidth => logDualis(cMemAccessDelayTable(i).read + 1),
gTcntVal => cMemAccessDelayTable(i).read
)
port map (
iArst => ackRst,
iClk => ackClk,
iEnable => selAndRead,
iSrst => cInactivated,
oCnt => open,
oTcnt => ackVector(i).read
);
end generate GENRD_ACKDELAY;
--! generate no ack delay for reads.
GENRD_NOACKDELAY : if cMemAccessDelayTable(i).read = 0 generate
ackVector(i).read <= selAndRead;
end generate GENRD_NOACKDELAY;
end generate GENMACREG_ACK;
--! The openHUB instance is only needed if more than one phy port is
--! configured.
GEN_HUB : if gPhyPortCount > 1 generate
THEOPENHUB : entity work.openhub
generic map (
gPortCount => gPhyPortCount+1 -- plus MAC port
)
port map (
iRst => inst_openhub.rst,
iClk => inst_openhub.clk,
iRx => inst_openhub.rx,
oTx => inst_openhub.tx,
iIntPort => inst_openhub.internPort,
iTxMask => inst_openhub.transmitMask,
oRxPort => inst_openhub.receivePort
);
end generate GEN_HUB;
--! In case of HUB bypass assign inst_openhub although!
GEN_HUBBYPASS : if gPhyPortCount = 1 generate
--! Port number for external phy port
constant cExtPort : natural := cPhyPortLow;
--! Port number for internal MAC port
constant cIntPort : natural := cHubIntPort;
begin
inst_openhub.tx(cExtPort) <= inst_openhub.rx(cIntPort);
inst_openhub.tx(cIntPort) <= inst_openhub.rx(cExtPort);
inst_openhub.receivePort <= cExtPort;
end generate GEN_HUBBYPASS;
--! Generate openFILTER instances for every phy port.
GEN_FILTER : for i in cPhyPortHigh downto cPhyPortLow generate
THEOPENFILTER : entity work.openfilter
port map (
iRst => inst_openfilter.rst,
iClk => inst_openfilter.clk,
iRx => inst_openfilter.rxIn(i),
oRx => inst_openfilter.rxOut(i),
iTx => inst_openfilter.txIn(i),
oTx => inst_openfilter.txOut(i),
iRxError => inst_openfilter.rxError(i)
);
end generate GEN_FILTER;
--! Generate MII signals for every phy port. Note that this includes
--! the RMII-to-MII converter.
GEN_MII : if gPhyPortType = cPhyPortMii generate
GEN_CONVERTER : for i in cPhyPortHigh downto cPhyPortLow generate
-- convert phy port to filter index range
miiTxPath(i-cHubIntPort-1) <= inst_convRmiiToMii.miiTx(i);
THERMII2MIICONVERTER : entity work.convRmiiToMii
port map (
iRst => inst_convRmiiToMii.rst,
iClk => inst_convRmiiToMii.clk,
iRmiiTx => inst_convRmiiToMii.rmiiTx(i),
oRmiiRx => inst_convRmiiToMii.rmiiRx(i),
iMiiRxClk => inst_convRmiiToMii.miiRxClk(i),
iMiiRx => inst_convRmiiToMii.miiRx(i),
iMiiRxError => inst_convRmiiToMii.miiRxError(i),
iMiiTxClk => inst_convRmiiToMii.miiTxClk(i),
oMiiTx => inst_convRmiiToMii.miiTx(i)
);
end generate GEN_CONVERTER;
end generate GEN_MII;
--! Generate RMII signals for every phy port. The Rx path is latched with
--! iClk and the Tx path is lactehd with iClk2x.
GEN_RMII : if gPhyPortType = cPhyPortRmii generate
--! Latch Rx signals before they come to internals.
LATCHRXPATH : process(iRst, iClk)
begin
if iRst = cActivated then
rmiiRxPathError_reg <= (others => cInactivated);
rmiiRxPath_reg <= (others => cRmiiPathInit);
elsif rising_edge(iClk) then
rmiiRxPathError_reg <= iRmii_RxError;
rmiiRxPath_reg <= iRmii_Rx;
end if;
end process LATCHRXPATH;
--! Latch Tx signals with falling edge before they leave.
LATCHTXPATH : process(iRst, iClk2x)
begin
if iRst = cActivated then
rmiiTxPath_reg <= (others => cRmiiPathInit);
elsif falling_edge(iClk2x) then
-- convert phy port to filter index range
for i in gPhyPortCount-1 downto 0 loop
rmiiTxPath_reg(i) <= inst_openfilter.txOut(i+cPhyPortLow);
end loop;
end if;
end process LATCHTXPATH;
end generate GEN_RMII;
--! Generate PACKET BUFFER DPRAM if Rx or Tx packets are stored localy.
GEN_PKTBUFFER : if (gPacketBufferLocTx = cPktBufLocal or
gPacketBufferLocRx = cPktBufLocal) generate
--! Packet buffer number of words (e.g. 1024 byte => 256 dword)
constant cNumberOfWords : natural := 2**(gPacketBufferLog2Size - logDualis(cPktBufDataWidth/cByteLength));
--! DMA path reset
signal dmaRst : std_logic;
--! DMA path clock
signal dmaClk : std_logic;
begin
--! This is the packet buffer DPRAM storing Tx and/or Rx packets.
--! Port A is connected to the openMAC DMA and port B is connected to
--! the memory mapped slave port (host).
THEPKTBUF : entity work.dpRam
generic map (
gWordWidth => cPktBufDataWidth,
gNumberOfWords => cNumberOfWords,
gInitFile => "UNUSED"
)
port map (
iClk_A => inst_pktBuffer.dma.clk,
iEnable_A => inst_pktBuffer.dma.enable,
iWriteEnable_A => inst_pktBuffer.dma.write,
iAddress_A => inst_pktBuffer.dma.address,
iByteenable_A => inst_pktBuffer.dma.byteenable,
iWritedata_A => inst_pktBuffer.dma.writedata,
oReaddata_A => inst_pktBuffer.dma.readdata,
iClk_B => inst_pktBuffer.host.clk,
iEnable_B => inst_pktBuffer.host.enable,
iWriteEnable_B => inst_pktBuffer.host.write,
iByteenable_B => inst_pktBuffer.host.byteenable,
iAddress_B => inst_pktBuffer.host.address,
iWritedata_B => inst_pktBuffer.host.writedata,
oReaddata_B => inst_pktBuffer.host.readdata
);
dmaRst <= inst_pktBuffer.dma.rst;
dmaClk <= inst_pktBuffer.dma.clk;
--! This process generates the DMA acknowlegde pulse. It is generated
--! for read and/or write requests with same delay.
DMAACKPULSE : process(dmaRst, dmaClk)
begin
if dmaRst = cActivated then
inst_pktBuffer.dma_ack <= cInactivated;
elsif rising_edge(dmaClk) then
-- generate pulse => default
inst_pktBuffer.dma_ack <= cInactivated;
if (inst_openmac.dma_request = cActivated and
inst_pktBuffer.dma_ack = cInactivated) then
-- Check if it is a write or read
if inst_openmac.nDma_write = cnActivated then
-- It is a write (Rx packet), check generic...
if gPacketBufferLocRx = cPktBufLocal then
inst_pktBuffer.dma_ack <= cActivated;
end if;
else
-- It is a read (Tx packet), check generic...
if gPacketBufferLocTx = cPktBufLocal then
inst_pktBuffer.dma_ack <= cActivated;
end if;
end if;
end if;
end if;
end process DMAACKPULSE;
--! This process stores the DMA high word select for DMA read path.
--! Note: This workaround is needed since data is latched after dma ack.
DMAHIGHWORDSEL : process(dmaRst, dmaClk)
begin
if dmaRst = cActivated then
inst_pktBuffer.dma_highWordSel <= cInactivated;
elsif rising_edge(dmaClk) then
if inst_openmac.dma_request = cActivated and inst_openmac.nDma_write = cnInactivated then
inst_pktBuffer.dma_highWordSel <= inst_openmac.dma_address(1);
end if;
end if;
end process DMAHIGHWORDSEL;
end generate GEN_PKTBUFFER;
--! Generate DMA Master instances if Rx or Tx packets are stored externally.
GEN_DMAMASTER : if (gPacketBufferLocTx = cPktBufExtern or
gPacketBufferLocRx = cPktBufExtern) generate
--! This is the DMA master handling the Tx and/or Rx packet transfers
--! to/from the interconnect.
THEDMAMASTER: entity work.openMAC_DMAmaster
generic map (
dma_highadr_g => gDmaAddrWidth-1,
fifo_data_width_g => gDmaDataWidth,
gen_dma_observer_g => (gEnableDmaObserver /= cFalse),
gen_rx_fifo_g => (gPacketBufferLocRx = cPktBufExtern),
gen_tx_fifo_g => (gPacketBufferLocTx = cPktBufExtern),
m_burstcount_const_g => TRUE, --TODO: check if okay
m_burstcount_width_g => gDmaBurstCountWidth,
m_rx_burst_size_g => gDmaWriteBurstLength,
rx_fifo_word_size_g => gDmaWriteFifoLength,
m_tx_burst_size_g => gDmaReadBurstLength,
tx_fifo_word_size_g => gDmaReadFifoLength,
simulate => FALSE
)
port map (
dma_clk => inst_dmaMaster.dma.clk,
rst => inst_dmaMaster.dma.rst,
dma_req_wr => inst_dmaMaster.dma.reqWrite,
dma_req_rd => inst_dmaMaster.dma.reqRead,
dma_req_overflow => inst_dmaMaster.dma.reqOverflow,
dma_ack_wr => inst_dmaMaster.dma.ackWrite,
dma_ack_rd => inst_dmaMaster.dma.ackRead,
dma_rd_err => inst_dmaMaster.dma.readError,
dma_rd_len => inst_dmaMaster.dma.readLength,
dma_wr_err => inst_dmaMaster.dma.writeError,
dma_addr => inst_dmaMaster.dma.address,
dma_dout => inst_dmaMaster.dma.writedata,
dma_din => inst_dmaMaster.dma.readdata,
m_clk => inst_dmaMaster.master.clk,
--FIXME: m_rst => inst_dmaMaster.master.rst,
m_write => inst_dmaMaster.master.write,
m_read => inst_dmaMaster.master.read,
m_readdatavalid => inst_dmaMaster.master.readdatavalid,
m_waitrequest => inst_dmaMaster.master.waitrequest,
m_address => inst_dmaMaster.master.address,
m_byteenable => inst_dmaMaster.master.byteenable,
m_burstcount => inst_dmaMaster.master.burstcount,
m_burstcounter => inst_dmaMaster.master.burstcounter,
m_writedata => inst_dmaMaster.master.writedata,
m_readdata => inst_dmaMaster.master.readdata,
mac_rx_off => inst_dmaMaster.mac_rxOff,
mac_tx_off => inst_dmaMaster.mac_txOff
);
end generate GEN_DMAMASTER;
GEN_NO_DMAMASTER : if not (gPacketBufferLocTx = cPktBufExtern or gPacketBufferLocRx = cPktBufExtern) generate
inst_dmaMaster.dma.readError <= '0';
inst_dmaMaster.dma.writeError <= '0';
end generate GEN_NO_DMAMASTER;
--! Generate MAC activity, which can be used for LED control.
GEN_ACTIVITY : if gEnableActivity = cTrue generate
--! The activity generate uses the Tx enable and Rx data valid signal
--! to detect a packet run.
THEACTIVITY : entity work.phyActGen
generic map (
gActivityFreq => cActivityFreq,
gClkFreq => cClkFreq
)
port map (
iRst => inst_activity.rst,
iClk => inst_activity.clk,
iTxEnable => inst_activity.txEnable,
iRxValid => inst_activity.rxDataValid,
oActivity => inst_activity.activity
);
end generate GEN_ACTIVITY;
end rtl;
| gpl-2.0 | 02d83343f5efce2f945ff1f3f8f69d2b | 0.508038 | 5.339881 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/boards/terasic-de2-115/cn-single-hostif-gpio/quartus/toplevel.vhd | 3 | 16,843 | -------------------------------------------------------------------------------
--! @file toplevel.vhd
--
--! @brief Toplevel of Nios CN hostif gpio design
--
--! @details This is the toplevel of the Nios CN hostif gpio design for the
--! INK DE2-115 Evaluation Board.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2017
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library libcommon;
use libcommon.global.all;
entity toplevel is
port (
-- 50 MHZ CLK IN
EXT_CLK : in std_logic;
-- EPCS
EPCS_DCLK : out std_logic;
EPCS_SCE : out std_logic;
EPCS_SDO : out std_logic;
EPCS_DATA0 : in std_logic;
-- FLASH 8Mx8
CFI_FLASH_ADDR : out std_logic_vector(22 downto 0);
CFI_FLASH_DATA : inout std_logic_vector(7 downto 0);
CFI_FLASH_WE_n : out std_logic;
CFI_FLASH_CE_n : out std_logic;
CFI_FLASH_OE_n : out std_logic;
CFI_FLASH_RESET_n : out std_logic;
CFI_FLASH_WP_n : out std_logic;
CFI_FLASH_RY : in std_logic;
-- 64 MBx2 SDRAM
SDRAM_CLK : out std_logic;
SDRAM_CAS_n : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CS_n : out std_logic;
SDRAM_RAS_n : out std_logic;
SDRAM_WE_n : out std_logic;
SDRAM_ADDR : out std_logic_vector(12 downto 0);
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_DQM : out std_logic_vector(3 downto 0);
SDRAM_DQ : inout std_logic_vector(31 downto 0);
-- NODE_SWITCH
NODE_SWITCH : in std_logic_vector(7 downto 0);
-- KEY
KEY_n : in std_logic_vector(3 downto 0);
-- LED
LEDG : out std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(15 downto 0);
-- HEX LED
HEX0 : out std_logic_vector(6 downto 0);
HEX1 : out std_logic_vector(6 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
-- LCD
LCD_ON : out std_logic;
LCD_BLON : out std_logic;
LCD_DQ : inout std_logic_vector(7 downto 0);
LCD_E : out std_logic;
LCD_RS : out std_logic;
LCD_RW : out std_logic;
-- HOST Interface
HOSTIF_AD : inout std_logic_vector(16 downto 0);
HOSTIF_BE : out std_logic_vector(1 downto 0);
HOSTIF_CS_n : out std_logic;
HOSTIF_WR_n : out std_logic;
HOSTIF_ALE_n : out std_logic;
HOSTIF_RD_n : out std_logic;
HOSTIF_ACK_n : in std_logic;
HOSTIF_IRQ_n : in std_logic
);
end toplevel;
architecture rtl of toplevel is
component cnSingleHostifGpio is
port (
clk50_clk : in std_logic := 'X'; -- clk
clk100_clk : in std_logic := 'X'; -- clk
clk25_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
host_0_benchmark_pio_export : out std_logic_vector(7 downto 0); -- export
epcs_flash_dclk : out std_logic; -- dclk
epcs_flash_sce : out std_logic; -- sce
epcs_flash_sdo : out std_logic; -- sdo
epcs_flash_data0 : in std_logic := 'X'; -- data0
lcd_RS : out std_logic; -- RS
lcd_RW : out std_logic; -- RW
lcd_data : inout std_logic_vector(7 downto 0) := (others => 'X'); -- data
lcd_E : out std_logic; -- E
sdram_0_addr : out std_logic_vector(12 downto 0); -- addr
sdram_0_ba : out std_logic_vector(1 downto 0); -- ba
sdram_0_cas_n : out std_logic; -- cas_n
sdram_0_cke : out std_logic; -- cke
sdram_0_cs_n : out std_logic; -- cs_n
sdram_0_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- dq
sdram_0_dqm : out std_logic_vector(3 downto 0); -- dqm
sdram_0_ras_n : out std_logic; -- ras_n
sdram_0_we_n : out std_logic; -- we_n
node_switch_pio_export : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
sync_irq_irq : in std_logic;
prl0_oPrlMst_cs : out std_logic; -- oPrlMst_cs
prl0_iPrlMst_ad_i : in std_logic_vector(16 downto 0) := (others => 'X'); -- iPrlMst_ad_i
prl0_oPrlMst_ad_o : out std_logic_vector(16 downto 0); -- oPrlMst_ad_o
prl0_oPrlMst_ad_oen : out std_logic; -- oPrlMst_ad_oen
prl0_oPrlMst_be : out std_logic_vector(1 downto 0); -- oPrlMst_be
prl0_oPrlMst_ale : out std_logic; -- oPrlMst_ale
prl0_oPrlMst_wr : out std_logic; -- oPrlMst_wr
prl0_oPrlMst_rd : out std_logic; -- oPrlMst_rd
prl0_iPrlMst_ack : in std_logic := 'X'; -- iPrlMst_ack
app_pio_in_port : in std_logic_vector(31 downto 0) := (others => 'X'); -- in_port
app_pio_out_port : out std_logic_vector(31 downto 0); -- out_port
tristate_cfi_flash_0_tcm_address_out : out std_logic_vector(22 downto 0); -- tcm_address_out
tristate_cfi_flash_0_tcm_read_n_out : out std_logic; -- tcm_read_n_out
tristate_cfi_flash_0_tcm_write_n_out : out std_logic; -- tcm_write_n_out
tristate_cfi_flash_0_tcm_data_out : inout std_logic_vector(7 downto 0) := (others => 'X'); -- tcm_data_out
tristate_cfi_flash_0_tcm_chipselect_n_out : out std_logic -- tcm_chipselect_n_out
);
end component cnSingleHostifGpio;
-- PLL component
component pll
port (
inclk0 : in std_logic;
c0 : out std_logic;
c1 : out std_logic;
c2 : out std_logic;
c3 : out std_logic;
locked : out std_logic
);
end component;
signal clk25 : std_logic;
signal clk50 : std_logic;
signal clk100 : std_logic;
signal clk100_p : std_logic;
signal pllLocked : std_logic;
signal hostifCs : std_logic;
signal hostifWr : std_logic;
signal hostifRd : std_logic;
signal hostifAle : std_logic;
signal hostifAck : std_logic;
signal hostifAd_i : std_logic_vector(HOSTIF_AD'range);
signal hostifAd_o : std_logic_vector(HOSTIF_AD'range);
signal hostifAd_oen : std_logic;
signal hostifIrq : std_logic;
type tSevenSegArray is array (natural range <>) of std_logic_vector(6 downto 0);
constant cNumberOfHex : natural := 8;
signal hex : std_logic_vector(cNumberOfHex*4-1 downto 0);
signal sevenSegArray : tSevenSegArray(cNumberOfHex-1 downto 0);
signal app_input : std_logic_vector(31 downto 0);
signal app_output : std_logic_vector(31 downto 0);
begin
LCD_ON <= '1';
LCD_BLON <= '1';
SDRAM_CLK <= clk100_p;
HOSTIF_CS_n <= not hostifCs;
HOSTIF_WR_n <= not hostifWr;
HOSTIF_RD_n <= not hostifRd;
HOSTIF_ALE_n <= not hostifAle;
hostifAck <= not HOSTIF_ACK_n;
-- TRISTATE Buffer for AD bus
HOSTIF_AD <= hostifAd_o when hostifAd_oen = '1' else (others => 'Z');
hostifAd_i <= HOSTIF_AD;
hostifIrq <= not HOSTIF_IRQ_n;
CFI_FLASH_RESET_n <= cnInactivated;
CFI_FLASH_WP_n <= cnInactivated;
---------------------------------------------------------------------------
-- Green LED assignments
LEDG <= (others => '0'); -- Reserved
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Red LED assignments
LEDR <= (others => '0'); -- Reserved
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Application Input and Output assignments
-- Input: Map KEY nibble to Application Input
app_input <= x"0000000" & not KEY_n;
-- Output: Map Application Output to HEX LEDs
hex <= app_output;
---------------------------------------------------------------------------
inst : component cnSingleHostifGpio
port map (
clk25_clk => clk25,
clk50_clk => clk50,
clk100_clk => clk100,
reset_reset_n => pllLocked,
node_switch_pio_export => NODE_SWITCH,
host_0_benchmark_pio_export => open,
epcs_flash_dclk => EPCS_DCLK,
epcs_flash_sce => EPCS_SCE,
epcs_flash_sdo => EPCS_SDO,
epcs_flash_data0 => EPCS_DATA0,
sdram_0_addr => SDRAM_ADDR,
sdram_0_ba => SDRAM_BA,
sdram_0_cas_n => SDRAM_CAS_n,
sdram_0_cke => SDRAM_CKE,
sdram_0_cs_n => SDRAM_CS_n,
sdram_0_dq => SDRAM_DQ,
sdram_0_dqm => SDRAM_DQM,
sdram_0_ras_n => SDRAM_RAS_n,
sdram_0_we_n => SDRAM_WE_n,
lcd_data => LCD_DQ,
lcd_E => LCD_E,
lcd_RS => LCD_RS,
lcd_RW => LCD_RW,
prl0_oPrlMst_cs => hostifCs,
prl0_iPrlMst_ad_i => hostifAd_i,
prl0_oPrlMst_ad_o => hostifAd_o,
prl0_oPrlMst_ad_oen => hostifAd_oen,
prl0_oPrlMst_be => HOSTIF_BE,
prl0_oPrlMst_ale => hostifAle,
prl0_oPrlMst_wr => hostifWr,
prl0_oPrlMst_rd => hostifRd,
prl0_iPrlMst_ack => hostifAck,
sync_irq_irq => hostifIrq,
app_pio_in_port => app_input,
app_pio_out_port => app_output,
tristate_cfi_flash_0_tcm_address_out => CFI_FLASH_ADDR,
tristate_cfi_flash_0_tcm_read_n_out => CFI_FLASH_OE_n,
tristate_cfi_flash_0_tcm_write_n_out => CFI_FLASH_WE_n,
tristate_cfi_flash_0_tcm_data_out => CFI_FLASH_DATA,
tristate_cfi_flash_0_tcm_chipselect_n_out => CFI_FLASH_CE_n
);
-- Pll Instance
pllInst : pll
port map (
inclk0 => EXT_CLK,
c0 => clk50,
c1 => clk100,
c2 => clk25,
c3 => clk100_p,
locked => pllLocked
);
-- bcd to 7 segment
genBcdTo7Seg : for i in cNumberOfHex-1 downto 0 generate
signal tmpHex : std_logic_vector(3 downto 0);
signal tmpSev : std_logic_vector(6 downto 0);
begin
tmpHex <= hex((i+1)*4-1 downto i*4);
sevenSegArray(i) <= tmpSev;
bcdTo7Seg0 : entity libcommon.bcd2led
port map (
iBcdVal => tmpHex,
oLed => open,
onLed => tmpSev
);
end generate genBcdTo7Seg;
-- assign outports to array
HEX0 <= sevenSegArray(0);
HEX1 <= sevenSegArray(1);
HEX2 <= sevenSegArray(2);
HEX3 <= sevenSegArray(3);
HEX4 <= sevenSegArray(4);
HEX5 <= sevenSegArray(5);
HEX6 <= sevenSegArray(6);
HEX7 <= sevenSegArray(7);
end rtl;
| gpl-2.0 | 1f743e5f54463f4e5f62b24fc43f99db | 0.413822 | 4.546019 | false | false | false | false |
DreamIP/GPStudio | support/io/com/hdl/hal/eth_marvell_88e1111/hdl/interface_management/interface_management.vhd | 1 | 3,941 | -- This entity is used to adapt the interface between the marvell (4 bits double data rate clocked on GE_RXCLK)
-- and the fpga (8 bits clocked on rising edge of CLK125)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_package.all;
entity interface_management is
port (
clk125 : in std_logic;
clk250_marvell : in std_logic;
clk250_fpga : in std_logic;
reset_n : in std_logic;
RX_i : in rgmii_t;
RX_o : out gmii_t;
TX_i : in gmii_t;
TX_o : out rgmii_t
);
end interface_management;
architecture RTL of interface_management is
type fsm_rcv is (idle,preamble,data);
signal state_rcv : fsm_rcv;
signal count_preamble : unsigned(3 downto 0);
signal TX_i_dl : rgmii_t;
signal half : std_logic;
signal reset : std_logic;
signal empty_rgmii2gmii : std_logic;
signal data_valid_sync : std_logic;
signal rd_en_sync : std_logic;
signal data_sync : std_logic_vector(7 downto 0);
signal RX_sync : gmii_t;
signal empty_gmii2rgmii : std_logic;
signal rd_en_tx,rd_en_tx_dl : std_logic;
signal data_valid_tx : std_logic;
signal data_tx : std_logic_vector(3 downto 0);
begin
reset <= not reset_n;
--- Data in : 4bits at 250MHz (GE_RXCLK x2) --- Data out : 8bits 125MHz
rgmii2gmii_fifo_inst : entity work.rgmii2gmii_fifo
port map (
wrclk => clk250_marvell,
wrreq => RX_i.dv,
data => RX_i.data,
rdclk => clk125,
rdreq => rd_en_sync,
q => data_sync,
rdempty => empty_rgmii2gmii
);
--- Process controling signals of rgmii2gmii fifo
process(clk125)
begin
if clk125'event and clk125='1' then
rd_en_sync <= not empty_rgmii2gmii;
data_valid_sync <= rd_en_sync and not empty_rgmii2gmii;
RX_sync.data <= data_sync;
RX_sync.dv <= data_valid_sync;
end if;
end process;
-------- Detect and remove Ethernet preamble
process(clk125,reset_n)
begin
if reset_n='0' then
state_rcv <= idle;
count_preamble <= x"0";
RX_o.dv <= '0';
RX_o.data <= x"00";
elsif (clk125'event and clk125='1') then
case (state_rcv) is
when idle =>
if RX_sync.dv='1' then
state_rcv <= preamble;
if RX_sync.data=x"55" then
count_preamble <= count_preamble +1;
end if;
else
count_preamble <= x"0";
state_rcv <= idle;
end if;
when preamble =>
if RX_sync.dv='1' and RX_sync.data=x"55" then
count_preamble <= count_preamble +1;
elsif RX_sync.data=x"D5" and count_preamble>=x"5" then
state_rcv <= data;
count_preamble <= x"0";
elsif RX_sync.dv='0' then
state_rcv <= idle;
end if;
when data =>
if RX_sync.dv='1' then
RX_o.dv <= '1';
RX_o.data <= RX_sync.data;
state_rcv <= data;
else
RX_o.dv <= '0';
RX_o.data <= x"00";
state_rcv <= idle;
end if;
when others =>
state_rcv <= idle;
end case;
end if;
end process;
------ Transmission GMII to RGMII
process(clk250_fpga,reset_n)
begin
if reset_n='0' then
TX_o.dv <= '0';
TX_o.data <= x"0";
elsif (clk250_fpga'event and clk250_fpga='1') then
TX_o.dv <= TX_i_dl.dv;
TX_o.data <= TX_i_dl.data;
TX_i_dl.dv <= TX_i.dv;
if TX_i.dv='1' and TX_i_dl.dv='0' then
TX_i_dl.data(3 downto 0) <= TX_i.data(7 downto 4);
half <= '1';
elsif TX_i_dl.dv='1' then
half <= not half;
if half='1' then
TX_i_dl.data(3 downto 0) <= TX_i.data(7 downto 4);
else
TX_i_dl.data(3 downto 0) <= TX_i.data(3 downto 0);
end if;
end if;
end if;
end process;
end RTL;
| gpl-3.0 | c03f885ab37b63d0a7edef34b44357e4 | 0.548845 | 2.837293 | false | false | false | false |
DreamIP/GPStudio | support/process/conv/hdl/conv_slave.vhd | 1 | 9,439 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity conv_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
w00_reg_m00 : out std_logic_vector(7 downto 0);
w01_reg_m01 : out std_logic_vector(7 downto 0);
w02_reg_m02 : out std_logic_vector(7 downto 0);
w10_reg_m10 : out std_logic_vector(7 downto 0);
w11_reg_m11 : out std_logic_vector(7 downto 0);
w12_reg_m12 : out std_logic_vector(7 downto 0);
w20_reg_m20 : out std_logic_vector(7 downto 0);
w21_reg_m21 : out std_logic_vector(7 downto 0);
w22_reg_m22 : out std_logic_vector(7 downto 0);
norm_reg_norm : out std_logic_vector(3 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end conv_slave;
architecture rtl of conv_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant WIDTHIMG_REG_REG_ADDR : natural := 1;
constant W00_REG_REG_ADDR : natural := 2;
constant W01_REG_REG_ADDR : natural := 3;
constant W02_REG_REG_ADDR : natural := 4;
constant W10_REG_REG_ADDR : natural := 5;
constant W11_REG_REG_ADDR : natural := 6;
constant W12_REG_REG_ADDR : natural := 7;
constant W20_REG_REG_ADDR : natural := 8;
constant W21_REG_REG_ADDR : natural := 9;
constant W22_REG_REG_ADDR : natural := 10;
constant NORM_REG_REG_ADDR : natural := 11;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal widthimg_reg_width_reg : std_logic_vector (15 downto 0);
signal w00_reg_m00_reg : std_logic_vector (7 downto 0);
signal w01_reg_m01_reg : std_logic_vector (7 downto 0);
signal w02_reg_m02_reg : std_logic_vector (7 downto 0);
signal w10_reg_m10_reg : std_logic_vector (7 downto 0);
signal w11_reg_m11_reg : std_logic_vector (7 downto 0);
signal w12_reg_m12_reg : std_logic_vector (7 downto 0);
signal w20_reg_m20_reg : std_logic_vector (7 downto 0);
signal w21_reg_m21_reg : std_logic_vector (7 downto 0);
signal w22_reg_m22_reg : std_logic_vector (7 downto 0);
signal norm_reg_norm_reg : std_logic_vector (3 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
widthimg_reg_width_reg <= "0000000000000000";
w00_reg_m00_reg <= "00000000";
w01_reg_m01_reg <= "00000000";
w02_reg_m02_reg <= "00000000";
w10_reg_m10_reg <= "00000000";
w11_reg_m11_reg <= "00000000";
w12_reg_m12_reg <= "00000000";
w20_reg_m20_reg <= "00000000";
w21_reg_m21_reg <= "00000000";
w22_reg_m22_reg <= "00000000";
norm_reg_norm_reg <= "0000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case to_integer(unsigned(addr_rel_i)) is
when STATUS_REG_REG_ADDR =>
status_reg_enable_bit_reg <= datawr_i(0);
when WIDTHIMG_REG_REG_ADDR =>
widthimg_reg_width_reg <= datawr_i(15) & datawr_i(14) & datawr_i(13) & datawr_i(12) & datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when W00_REG_REG_ADDR =>
w00_reg_m00_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when W01_REG_REG_ADDR =>
w01_reg_m01_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when W02_REG_REG_ADDR =>
w02_reg_m02_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when W10_REG_REG_ADDR =>
w10_reg_m10_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when W11_REG_REG_ADDR =>
w11_reg_m11_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when W12_REG_REG_ADDR =>
w12_reg_m12_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when W20_REG_REG_ADDR =>
w20_reg_m20_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when W21_REG_REG_ADDR =>
w21_reg_m21_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when W22_REG_REG_ADDR =>
w22_reg_m22_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when NORM_REG_REG_ADDR =>
norm_reg_norm_reg <= datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case to_integer(unsigned(addr_rel_i)) is
when STATUS_REG_REG_ADDR =>
datard_o <= "0000000000000000000000000000000" & status_reg_enable_bit_reg;
when WIDTHIMG_REG_REG_ADDR =>
datard_o <= "0000000000000000" & widthimg_reg_width_reg(15) & widthimg_reg_width_reg(14) & widthimg_reg_width_reg(13) & widthimg_reg_width_reg(12) & widthimg_reg_width_reg(11) & widthimg_reg_width_reg(10) & widthimg_reg_width_reg(9) & widthimg_reg_width_reg(8) & widthimg_reg_width_reg(7) & widthimg_reg_width_reg(6) & widthimg_reg_width_reg(5) & widthimg_reg_width_reg(4) & widthimg_reg_width_reg(3) & widthimg_reg_width_reg(2) & widthimg_reg_width_reg(1) & widthimg_reg_width_reg(0);
when W00_REG_REG_ADDR =>
datard_o <= "000000000000000000000000" & w00_reg_m00_reg(7) & w00_reg_m00_reg(6) & w00_reg_m00_reg(5) & w00_reg_m00_reg(4) & w00_reg_m00_reg(3) & w00_reg_m00_reg(2) & w00_reg_m00_reg(1) & w00_reg_m00_reg(0);
when W01_REG_REG_ADDR =>
datard_o <= "000000000000000000000000" & w01_reg_m01_reg(7) & w01_reg_m01_reg(6) & w01_reg_m01_reg(5) & w01_reg_m01_reg(4) & w01_reg_m01_reg(3) & w01_reg_m01_reg(2) & w01_reg_m01_reg(1) & w01_reg_m01_reg(0);
when W02_REG_REG_ADDR =>
datard_o <= "000000000000000000000000" & w02_reg_m02_reg(7) & w02_reg_m02_reg(6) & w02_reg_m02_reg(5) & w02_reg_m02_reg(4) & w02_reg_m02_reg(3) & w02_reg_m02_reg(2) & w02_reg_m02_reg(1) & w02_reg_m02_reg(0);
when W10_REG_REG_ADDR =>
datard_o <= "000000000000000000000000" & w10_reg_m10_reg(7) & w10_reg_m10_reg(6) & w10_reg_m10_reg(5) & w10_reg_m10_reg(4) & w10_reg_m10_reg(3) & w10_reg_m10_reg(2) & w10_reg_m10_reg(1) & w10_reg_m10_reg(0);
when W11_REG_REG_ADDR =>
datard_o <= "000000000000000000000000" & w11_reg_m11_reg(7) & w11_reg_m11_reg(6) & w11_reg_m11_reg(5) & w11_reg_m11_reg(4) & w11_reg_m11_reg(3) & w11_reg_m11_reg(2) & w11_reg_m11_reg(1) & w11_reg_m11_reg(0);
when W12_REG_REG_ADDR =>
datard_o <= "000000000000000000000000" & w12_reg_m12_reg(7) & w12_reg_m12_reg(6) & w12_reg_m12_reg(5) & w12_reg_m12_reg(4) & w12_reg_m12_reg(3) & w12_reg_m12_reg(2) & w12_reg_m12_reg(1) & w12_reg_m12_reg(0);
when W20_REG_REG_ADDR =>
datard_o <= "000000000000000000000000" & w20_reg_m20_reg(7) & w20_reg_m20_reg(6) & w20_reg_m20_reg(5) & w20_reg_m20_reg(4) & w20_reg_m20_reg(3) & w20_reg_m20_reg(2) & w20_reg_m20_reg(1) & w20_reg_m20_reg(0);
when W21_REG_REG_ADDR =>
datard_o <= "000000000000000000000000" & w21_reg_m21_reg(7) & w21_reg_m21_reg(6) & w21_reg_m21_reg(5) & w21_reg_m21_reg(4) & w21_reg_m21_reg(3) & w21_reg_m21_reg(2) & w21_reg_m21_reg(1) & w21_reg_m21_reg(0);
when W22_REG_REG_ADDR =>
datard_o <= "000000000000000000000000" & w22_reg_m22_reg(7) & w22_reg_m22_reg(6) & w22_reg_m22_reg(5) & w22_reg_m22_reg(4) & w22_reg_m22_reg(3) & w22_reg_m22_reg(2) & w22_reg_m22_reg(1) & w22_reg_m22_reg(0);
when NORM_REG_REG_ADDR =>
datard_o <= "0000000000000000000000000000" & norm_reg_norm_reg(3) & norm_reg_norm_reg(2) & norm_reg_norm_reg(1) & norm_reg_norm_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
widthimg_reg_width <= widthimg_reg_width_reg;
w00_reg_m00 <= w00_reg_m00_reg;
w01_reg_m01 <= w01_reg_m01_reg;
w02_reg_m02 <= w02_reg_m02_reg;
w10_reg_m10 <= w10_reg_m10_reg;
w11_reg_m11 <= w11_reg_m11_reg;
w12_reg_m12 <= w12_reg_m12_reg;
w20_reg_m20 <= w20_reg_m20_reg;
w21_reg_m21 <= w21_reg_m21_reg;
w22_reg_m22 <= w22_reg_m22_reg;
norm_reg_norm <= norm_reg_norm_reg;
end rtl;
| gpl-3.0 | 7b9dd7e57588a1d1708b5b3b77187404 | 0.589575 | 2.399339 | false | false | false | false |
Reiuiji/ECE368-Lab | Lab 2/SevenSegmentDisplay/SevenSeg_toplevel.vhd | 1 | 1,778 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: SevenSeg_toplevel
-- Project Name: SevenSegmentDisplay
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description: 7-segment toplevel example
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity SSeg_toplevel is
port (
CLK : in STD_LOGIC; -- 50 MHz input
SW : in STD_LOGIC_VECTOR (7 downto 0);
BTN : in STD_LOGIC;
SEG : out STD_LOGIC_VECTOR (6 downto 0);
DP : out STD_LOGIC;
AN : out STD_LOGIC_VECTOR (3 downto 0)
);
end SSeg_toplevel;
architecture Structural of SSeg_toplevel is
signal s2 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal s3 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal enl : STD_LOGIC := '1';
signal dpc : STD_LOGIC_VECTOR (3 downto 0) := "1111";
signal cen : STD_LOGIC := '0';
begin
----- Structural Components: -----
SSeg: entity work.SSegDriver
port map( CLK => CLK,
RST => BTN,
EN => enl,
SEG_0 => SW(3 downto 0),
SEG_1 => SW(7 downto 4),
SEG_2 => s2,
SEG_3 => s3,
DP_CTRL => dpc,
COL_EN => cen,
SEG_OUT => SEG,
DP_OUT => DP,
AN_OUT => AN);
----- End Structural Components -----
end Structural;
| mit | b904ce4c9233c9b4bab464a4f5df1edd | 0.497188 | 3.840173 | false | false | false | false |
marzoul/PoC | src/io/io.pkg.vhdl | 2 | 7,560 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Package: VHDL package for component declarations, types and
-- functions associated to the PoC.io namespace
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
package io is
-- not yet supported by Xilinx ISE Simulator - the subsignal I (with reverse direction) is always 'U'
-- so use this record only in pure synthesis environments
type T_IO_TRISTATE is record
I : STD_LOGIC; -- input / from device to FPGA
O : STD_LOGIC; -- output / from FPGA to device
T : STD_LOGIC; -- output disable / tristate enable
end record;
type T_IO_LVDS is record
P : STD_LOGIC;
N : STD_LOGIC;
end record;
type T_IO_TRISTATE_VECTOR is array(NATURAL range <>) of T_IO_TRISTATE;
type T_IO_LVDS_VECTOR is array(NATURAL range <>) of T_IO_LVDS;
function io_7SegmentDisplayEncoding(hex : STD_LOGIC_VECTOR(3 downto 0); dot : STD_LOGIC := '0') return STD_LOGIC_VECTOR;
function io_7SegmentDisplayEncoding(digit : T_BCD; dot : STD_LOGIC := '0') return STD_LOGIC_VECTOR;
-- IICBusController
-- ==========================================================================================================================================================
type T_IO_IIC_BUSMODE is (
IO_IIC_BUSMODE_SMBUS, -- 100 kHz; additional timing restrictions
IO_IIC_BUSMODE_STANDARDMODE, -- 100 kHz
IO_IIC_BUSMODE_FASTMODE, -- 400 kHz
IO_IIC_BUSMODE_FASTMODEPLUS, -- 1.000 kHz
IO_IIC_BUSMODE_HIGHSPEEDMODE, -- 3.400 kHz
IO_IIC_BUSMODE_ULTRAFASTMODE -- 5.000 kHz; unidirectional
);
type T_IO_IICBUS_COMMAND is (
IO_IICBUS_CMD_NONE,
IO_IICBUS_CMD_SEND_START_CONDITION,
IO_IICBUS_CMD_SEND_RESTART_CONDITION,
IO_IICBUS_CMD_SEND_STOP_CONDITION,
IO_IICBUS_CMD_SEND_LOW,
IO_IICBUS_CMD_SEND_HIGH,
IO_IICBUS_CMD_RECEIVE
);
type T_IO_IICBUS_STATUS is (
IO_IICBUS_STATUS_RESETING,
IO_IICBUS_STATUS_IDLE,
IO_IICBUS_STATUS_SENDING,
IO_IICBUS_STATUS_SEND_COMPLETE,
IO_IICBUS_STATUS_RECEIVING,
IO_IICBUS_STATUS_RECEIVED_START_CONDITION,
IO_IICBUS_STATUS_RECEIVED_STOP_CONDITION,
IO_IICBUS_STATUS_RECEIVED_LOW,
IO_IICBUS_STATUS_RECEIVED_HIGH,
IO_IICBUS_STATUS_ERROR,
IO_IICBUS_STATUS_BUS_ERROR
);
-- IICController
-- ==========================================================================================================================================================
type T_IO_IIC_COMMAND is (
IO_IIC_CMD_NONE,
IO_IIC_CMD_QUICKCOMMAND_READ, -- use this to check for an device address
IO_IIC_CMD_QUICKCOMMAND_WRITE,
IO_IIC_CMD_SEND_BYTES,
IO_IIC_CMD_RECEIVE_BYTES,
IO_IIC_CMD_PROCESS_CALL
);
type T_IO_IIC_STATUS is (
IO_IIC_STATUS_IDLE,
IO_IIC_STATUS_EXECUTING,
IO_IIC_STATUS_EXECUTE_OK,
IO_IIC_STATUS_EXECUTE_FAILED,
IO_IIC_STATUS_SENDING,
IO_IIC_STATUS_SEND_COMPLETE,
IO_IIC_STATUS_RECEIVING,
IO_IIC_STATUS_RECEIVE_COMPLETE,
IO_IIC_STATUS_CALLING,
IO_IIC_STATUS_CALL_COMPLETE,
IO_IIC_STATUS_ERROR
);
type T_IO_IIC_ERROR is (
IO_IIC_ERROR_NONE,
IO_IIC_ERROR_ADDRESS_ERROR,
IO_IIC_ERROR_ACK_ERROR,
IO_IIC_ERROR_BUS_ERROR,
IO_IIC_ERROR_FSM
);
type T_IO_IIC_COMMAND_VECTOR is array(NATURAL range <>) of T_IO_IIC_COMMAND;
type T_IO_IIC_STATUS_VECTOR is array(NATURAL range <>) of T_IO_IIC_STATUS;
type T_IO_IIC_ERROR_VECTOR is array(NATURAL range <>) of T_IO_IIC_ERROR;
-- MDIOController
-- ==========================================================================================================================================================
type T_IO_MDIO_MDIOCONTROLLER_COMMAND is (
IO_MDIO_MDIOC_CMD_NONE,
IO_MDIO_MDIOC_CMD_CHECK_ADDRESS,
IO_MDIO_MDIOC_CMD_READ,
IO_MDIO_MDIOC_CMD_WRITE,
IO_MDIO_MDIOC_CMD_ABORT
);
type T_IO_MDIO_MDIOCONTROLLER_STATUS is (
IO_MDIO_MDIOC_STATUS_IDLE,
IO_MDIO_MDIOC_STATUS_CHECKING,
IO_MDIO_MDIOC_STATUS_CHECK_OK,
IO_MDIO_MDIOC_STATUS_CHECK_FAILED,
IO_MDIO_MDIOC_STATUS_READING,
IO_MDIO_MDIOC_STATUS_READ_COMPLETE,
IO_MDIO_MDIOC_STATUS_WRITING,
IO_MDIO_MDIOC_STATUS_WRITE_COMPLETE,
IO_MDIO_MDIOC_STATUS_ERROR
);
type T_IO_MDIO_MDIOCONTROLLER_ERROR is (
IO_MDIO_MDIOC_ERROR_NONE,
IO_MDIO_MDIOC_ERROR_ADDRESS_NOT_FOUND,
IO_MDIO_MDIOC_ERROR_FSM
);
type T_IO_LCDBUS_COMMAND is (
IO_LCDBUS_CMD_NONE,
IO_LCDBUS_CMD_READ,
IO_LCDBUS_CMD_WRITE
);
type T_IO_LCDBUS_STATUS is (
IO_LCDBUS_STATUS_IDLE,
IO_LCDBUS_STATUS_READING,
IO_LCDBUS_STATUS_WRITING,
IO_LCDBUS_STATUS_ERROR
);
-- Component Declarations
-- =========================================================================
component io_FanControl
generic (
CLOCK_FREQ_MHZ : real
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Fan_PWM : out STD_LOGIC;
Fan_Tacho : in STD_LOGIC;
TachoFrequency : out STD_LOGIC_VECTOR(15 downto 0)
);
end component;
end package;
package body io is
function io_7SegmentDisplayEncoding(hex : STD_LOGIC_VECTOR(3 downto 0); dot : STD_LOGIC := '0') return STD_LOGIC_VECTOR is
variable Result : STD_LOGIC_VECTOR(7 downto 0);
begin
Result(7) := dot;
case hex is -- segments: GFEDCBA
when x"0" => Result(6 downto 0) := "0111111";
when x"1" => Result(6 downto 0) := "0000110";
when x"2" => Result(6 downto 0) := "1011011";
when x"3" => Result(6 downto 0) := "1001111";
when x"4" => Result(6 downto 0) := "1100110";
when x"5" => Result(6 downto 0) := "1101101";
when x"6" => Result(6 downto 0) := "1111101";
when x"7" => Result(6 downto 0) := "0000111";
when x"8" => Result(6 downto 0) := "1111111";
when x"9" => Result(6 downto 0) := "1101111";
when x"A" => Result(6 downto 0) := "1110111";
when x"B" => Result(6 downto 0) := "1111100";
when x"C" => Result(6 downto 0) := "0111001";
when x"D" => Result(6 downto 0) := "1011110";
when x"E" => Result(6 downto 0) := "1111001";
when x"F" => Result(6 downto 0) := "1110001";
when others => Result(6 downto 0) := "XXXXXXX";
end case;
return Result;
end function;
function io_7SegmentDisplayEncoding(digit : T_BCD; dot : STD_LOGIC := '0') return STD_LOGIC_VECTOR is
begin
return io_7SegmentDisplayEncoding(std_logic_vector(digit), dot);
end function;
end package body;
| apache-2.0 | 75b6b774f692f5a553fc98273be60a1e | 0.604233 | 3.084455 | false | false | false | false |
DreamIP/GPStudio | support/process/median/hdl/median_slave.vhd | 1 | 2,955 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity median_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end median_slave;
architecture rtl of median_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant WIDTHIMG_REG_REG_ADDR : natural := 1;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal widthimg_reg_width_reg : std_logic_vector (15 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
widthimg_reg_width_reg <= "0000000000000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case to_integer(unsigned(addr_rel_i)) is
when STATUS_REG_REG_ADDR =>
status_reg_enable_bit_reg <= datawr_i(0);
when WIDTHIMG_REG_REG_ADDR =>
widthimg_reg_width_reg <= datawr_i(15) & datawr_i(14) & datawr_i(13) & datawr_i(12) & datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case to_integer(unsigned(addr_rel_i)) is
when STATUS_REG_REG_ADDR =>
datard_o <= "0000000000000000000000000000000" & status_reg_enable_bit_reg;
when WIDTHIMG_REG_REG_ADDR =>
datard_o <= "0000000000000000" & widthimg_reg_width_reg(15) & widthimg_reg_width_reg(14) & widthimg_reg_width_reg(13) & widthimg_reg_width_reg(12) & widthimg_reg_width_reg(11) & widthimg_reg_width_reg(10) & widthimg_reg_width_reg(9) & widthimg_reg_width_reg(8) & widthimg_reg_width_reg(7) & widthimg_reg_width_reg(6) & widthimg_reg_width_reg(5) & widthimg_reg_width_reg(4) & widthimg_reg_width_reg(3) & widthimg_reg_width_reg(2) & widthimg_reg_width_reg(1) & widthimg_reg_width_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
widthimg_reg_width <= widthimg_reg_width_reg;
end rtl;
| gpl-3.0 | 6c5e8981ea22ff864adcd435b8d78460 | 0.588832 | 2.905605 | false | false | false | false |
hoglet67/ElectronFpga | AtomBusMon/src/AVR8/Memory/XPM_T65.vhd | 1 | 140,315 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- This contains 0.987 of the ICE-65C02 firmware
-- For f_log2 definition
use WORK.SynthCtrlPack.all;
entity XPM is
generic (
WIDTH : integer;
SIZE : integer
);
port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(f_log2(SIZE) - 1 downto 0);
din : in std_logic_vector(WIDTH - 1 downto 0);
dout : out std_logic_vector(WIDTH - 1 downto 0);
we : in std_logic
);
end;
architecture RTL of XPM is
type ram_type is array (0 to SIZE - 1) of std_logic_vector (WIDTH - 1 downto 0);
signal RAM : ram_type := (
x"940C",
x"059F",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"940C",
x"05C1",
x"1993",
x"1A5F",
x"1999",
x"19A7",
x"19AD",
x"19BB",
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);
begin
process (cp2)
begin
if rising_edge(cp2) then
if ce = '1' then
if (we = '1') then
RAM(conv_integer(address)) <= din;
end if;
dout <= RAM(conv_integer(address));
end if;
end if;
end process;
end RTL;
| gpl-3.0 | cdd828a61dba822ea772a40c9e54c892 | 0.295891 | 2.775272 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | synthesis/fifo-vhdl/top.vhdl | 1 | 6,021 | --
-- FIFOs Top Level
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.MEMS.all;
entity Top is
port (
wr_clk_i : in std_logic;
wr_rst_i : in std_logic;
wr_en_i : in std_logic;
data_i : in std_logic_vector(7 downto 0);
full_o : out std_logic;
afull_o : out std_logic;
overflow_o : out std_logic;
-- read side
rd_clk_i : in std_logic;
rd_rst_i : in std_logic;
rd_en_i : in std_logic;
data_o : out std_logic_vector(7 downto 0);
empty_o : out std_logic;
aempty_o : out std_logic;
underflow_o : out std_logic;
valid_o : out std_logic;
--
sel_i : in std_logic_vector(1 downto 0)
);
end entity Top;
architecture Structural of Top is
-- sp: sync_partial
-- sf: sync full
-- ap: async partial
-- af: async full
-- Write side
signal sp_full, sf_full, ap_full, af_full : std_logic;
signal sp_afull, sf_afull, ap_afull, af_afull : std_logic;
signal sp_over, sf_over, ap_over, af_over : std_logic;
-- Read side
signal sp_data, sf_data, ap_data, af_data : std_logic_vector(7 downto 0);
signal sp_empty, sf_empty, ap_empty, af_empty : std_logic;
signal sp_aempty, sf_aempty, ap_aempty, af_aempty : std_logic;
signal sp_under, sf_under, ap_under, af_under : std_logic;
signal sp_valid, sf_valid, ap_valid, af_valid : std_logic;
begin
i_sync_partial : FIFO
generic map (
DWIDTH => 8,
DEPTH => 6*1024,
OUTREG => FALSE,
AFULLOFFSET => 1,
AEMPTYOFFSET => 1,
ASYNC => FALSE
)
port map (
-- write side
wr_clk_i => wr_clk_i,
wr_rst_i => wr_rst_i,
wr_en_i => wr_en_i,
data_i => data_i,
full_o => sp_full,
afull_o => sp_afull,
overflow_o => sp_over,
-- read side
rd_clk_i => wr_clk_i,
rd_rst_i => wr_rst_i,
rd_en_i => rd_en_i,
data_o => sp_data,
empty_o => sp_empty,
aempty_o => sp_aempty,
underflow_o => sp_under,
valid_o => sp_valid
);
i_sync_full : FIFO
generic map (
DWIDTH => 8,
DEPTH => 8*1024,
OUTREG => FALSE,
AFULLOFFSET => 1,
AEMPTYOFFSET => 1,
ASYNC => FALSE
)
port map (
-- write side
wr_clk_i => wr_clk_i,
wr_rst_i => wr_rst_i,
wr_en_i => wr_en_i,
data_i => data_i,
full_o => sf_full,
afull_o => sf_afull,
overflow_o => sf_over,
-- read side
rd_clk_i => wr_clk_i,
rd_rst_i => wr_rst_i,
rd_en_i => rd_en_i,
data_o => sf_data,
empty_o => sf_empty,
aempty_o => sf_aempty,
underflow_o => sf_under,
valid_o => sf_valid
);
i_async_partial : FIFO
generic map (
DWIDTH => 8,
DEPTH => 6*1024,
OUTREG => FALSE,
AFULLOFFSET => 1,
AEMPTYOFFSET => 1,
ASYNC => TRUE
)
port map (
-- write side
wr_clk_i => wr_clk_i,
wr_rst_i => wr_rst_i,
wr_en_i => wr_en_i,
data_i => data_i,
full_o => ap_full,
afull_o => ap_afull,
overflow_o => ap_over,
-- read side
rd_clk_i => rd_clk_i,
rd_rst_i => rd_rst_i,
rd_en_i => rd_en_i,
data_o => ap_data,
empty_o => ap_empty,
aempty_o => ap_aempty,
underflow_o => ap_under,
valid_o => ap_valid
);
i_async_full : FIFO
generic map (
DWIDTH => 8,
DEPTH => 8*1024,
OUTREG => FALSE,
AFULLOFFSET => 1,
AEMPTYOFFSET => 1,
ASYNC => TRUE
)
port map (
-- write side
wr_clk_i => wr_clk_i,
wr_rst_i => wr_rst_i,
wr_en_i => wr_en_i,
data_i => data_i,
full_o => af_full,
afull_o => af_afull,
overflow_o => af_over,
-- read side
rd_clk_i => rd_clk_i,
rd_rst_i => rd_rst_i,
rd_en_i => rd_en_i,
data_o => af_data,
empty_o => af_empty,
aempty_o => af_aempty,
underflow_o => af_under,
valid_o => af_valid
);
full_o <= sp_full when sel_i="00" else
sf_full when sel_i="01" else
ap_full when sel_i="10" else
af_full;
afull_o <= sp_afull when sel_i="00" else
sf_afull when sel_i="01" else
ap_afull when sel_i="10" else
af_afull;
overflow_o <= sp_over when sel_i="00" else
sf_over when sel_i="01" else
ap_over when sel_i="10" else
af_over;
data_o <= sp_data when sel_i="00" else
sf_data when sel_i="01" else
ap_data when sel_i="10" else
af_data;
empty_o <= sp_empty when sel_i="00" else
sf_empty when sel_i="01" else
ap_empty when sel_i="10" else
af_empty;
aempty_o <= sp_aempty when sel_i="00" else
sf_aempty when sel_i="01" else
ap_aempty when sel_i="10" else
af_aempty;
underflow_o <= sp_under when sel_i="00" else
sf_under when sel_i="01" else
ap_under when sel_i="10" else
af_under;
valid_o <= sp_valid when sel_i="00" else
sf_valid when sel_i="01" else
ap_valid when sel_i="10" else
af_valid;
end architecture Structural;
| bsd-3-clause | 3e15b7ff3d0b0bb214df5dbaf4f502e8 | 0.45906 | 3.16063 | false | false | false | false |
DreamIP/GPStudio | support/io/d5m/hdl/d5m_controller.vhd | 1 | 9,341 | -------------------------------------------------------------------------------
-- Copyright Institut Pascal Equipe Dream (19-10-2016)
-- Francois Berry, El Mehdi Abdali, Maxime Pelcat
-- This software is a computer program whose purpose is to manage dynamic
-- partial reconfiguration.
-- This software is governed by the CeCILL-C license under French law and
-- abiding by the rules of distribution of free software. You can use,
-- modify and/ or redistribute the software under the terms of the CeCILL-C
-- license as circulated by CEA, CNRS and INRIA at the following URL
-- "http://www.cecill.info".
-- As a counterpart to the access to the source code and rights to copy,
-- modify and redistribute granted by the license, users are provided only
-- with a limited warranty and the software's author, the holder of the
-- economic rights, and the successive licensors have only limited
-- liability.
-- In this respect, the user's attention is drawn to the risks associated
-- with loading, using, modifying and/or developing or reproducing the
-- software by the user in light of its specific status of free software,
-- that may mean that it is complicated to manipulate, and that also
-- therefore means that it is reserved for developers and experienced
-- professionals having in-depth computer knowledge. Users are therefore
-- encouraged to load and test the software's suitability as regards their
-- requirements in conditions enabling the security of their systems and/or
-- data to be ensured and, more generally, to use and operate it in the
-- same conditions as regards security.
-- The fact that you are presently reading this means that you have had
-- knowledge of the CeCILL-C license and that you accept its terms.
-------------------------------------------------------------------------------
-- Doxygen Comments -----------------------------------------------------------
--! @file d5m_controller.vhd
--
--! @brief D5M CMOS Image sensor controller
--! @author Francois Berry, El Mehdi Abdali, Maxime Pelcat
--! @board SoCKit from Arrow and Terasic
--! @version 1.0
--! @date 16/11/2016
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity d5m_controller is
generic
(
pixel_address_width : integer
);
port
(
-----
-- Board I/Os
clk : in std_logic; -- Input clock for processing and sent to CCD_XCLKIN
reset_n : in std_logic;
ccd_trigger : out std_logic; -- Enable
ccd_reset : out std_logic; -- Reset sensor
ccd_xclkin : out std_logic;
ccd_data : in std_logic_vector(11 downto 0);
ccd_fval : in std_logic;
ccd_lval : in std_logic;
ccd_pixclk : in std_logic;
i_exposure_adj : in std_logic; -- Adjusting exposure
i2c_sclk : out std_logic;
i2c_sdata : inout std_logic;
-----
-- Unused I/Os (for future extensions)
pix_address : out std_logic_vector(pixel_address_width-1 downto 0);
oRed : out std_logic_vector(7 downto 0);
oGreen : out std_logic_vector(7 downto 0);
oBlue : out std_logic_vector(7 downto 0);
-----
-- GPStudio i/os
data : out std_logic_vector(7 downto 0); -- gray data output
dv : out std_logic; -- data valid
fv : out std_logic -- flow valid
);
end d5m_controller;
architecture arch of d5m_controller is
component CCD_Capture
port
(
oDATA : out std_logic_vector(11 downto 0);
oDVAL : out std_logic;
oX_Cont : out std_logic_vector(15 downto 0);
oY_Cont : out std_logic_vector(15 downto 0);
oFrame_Cont : out std_logic_vector(31 downto 0);
iDATA : in std_logic_vector(11 downto 0);
iFVAL : in std_logic;
iLVAL : in std_logic;
iSTART : in std_logic;
iEND : in std_logic;
iCLK : in std_logic;
iRST : in std_logic;
oADDRESS : out std_logic_vector(23 downto 0);
oLVAL : out std_logic
);
end component CCD_Capture;
component I2C_CCD_Config
port
(
iCLK : in std_logic;
iRST_N : in std_logic;
iZOOM_MODE_SW : in std_logic;
iEXPOSURE_ADJ : in std_logic;
iEXPOSURE_DEC_p : in std_logic;
I2C_SCLK : out std_logic;
I2C_SDAT : inout std_logic
);
end component I2C_CCD_Config;
component RAW2RGB
port
(
iCLK : in std_logic;
iRST : in std_logic;
iDATA : in std_logic_vector(11 downto 0);
iDVAL : in std_logic;
oRed : out std_logic_vector(11 downto 0);
oGreen : out std_logic_vector(11 downto 0);
oBlue : out std_logic_vector(11 downto 0);
oDVAL : out std_logic;
iX_Cont : in std_logic_vector(15 downto 0);
iY_Cont : in std_logic_vector(15 downto 0)
);
end component RAW2RGB;
component RGB2GRY
port
(
clk : in std_logic;
reset : in std_logic;
src_CCD_R : in std_logic_vector(11 downto 0);
src_CCD_G : in std_logic_vector(11 downto 0);
src_CCD_B : in std_logic_vector(11 downto 0);
oCCD_GRY : out std_logic_vector(7 downto 0)
);
end component RGB2GRY;
component VideoSampler
generic(
DATA_WIDTH : integer;
PIXEL_WIDTH : integer;
FIFO_DEPTH : integer;
DEFAULT_SCR : integer;
DEFAULT_FLOWLENGHT : integer;
HREF_POLARITY : string;
VSYNC_POLARITY : string
);
port(
-- input from CLOCK50 domain
clk_i : in std_logic;
reset_n_i : in std_logic;
-- inputs from camera
pclk_i : in std_logic;
href_i : in std_logic;
vsync_i : in std_logic;
pixel_i : in std_logic_vector(7 downto 0);
-- params from slave
enable_i : in std_logic;
flowlength_i : in std_logic_vector(31 downto 0);
-- Stream interface
data_o : out std_logic_vector(7 downto 0);
dv_o : out std_logic;
fv_o : out std_logic
);
end component;
signal sCCD_R, sCCD_G, sCCD_B, mCCD_DATA : std_logic_vector(11 downto 0);
signal mCCD_DVAL, sCCD_DVAL : std_logic;
signal X_Cont, Y_Cont : std_logic_vector(15 downto 0);
signal frame_count : std_logic_vector(31 downto 0);
signal temp_pix_address : std_logic_vector(23 downto 0);
signal sig_LVAL : std_logic;
signal m_DATA : std_logic_vector(7 downto 0);
constant DEFAULT_FLOWLENGTH : std_logic_vector(31 downto 0) := x"00140000"; -- 1280*1024
begin
-- Preparing debayering
CCD_Capture_inst : CCD_Capture
port map
(
iDATA => ccd_data,
iFVAL => ccd_fval,
iLVAL => ccd_lval,
iSTART => '1', -- always activating
iEND => '0',
iCLK => ccd_pixclk,
iRST => reset_n,
oDATA => mCCD_DATA,
oDVAL => mCCD_DVAL,
oX_Cont => X_Cont,
oY_Cont => Y_Cont,
oFrame_Cont => frame_count,
oADDRESS => temp_pix_address,
oLVAL => sig_LVAL
);
-- Debayering
RAW2RGB_inst : RAW2RGB
port map
(
iCLK => ccd_pixclk,
iRST => reset_n,
iDATA => mCCD_DATA,
iDVAL => mCCD_DVAL,
oRed => sCCD_R,
oGreen => sCCD_G,
oBlue => sCCD_B,
oDVAL => sCCD_DVAL,
iX_Cont => X_Cont,
iY_Cont => Y_Cont
);
-- Converting to grayscale
RGB2GRY_int : RGB2GRY
port map
(
clk => clk,
reset => not(reset_n),
src_CCD_R => sCCD_R(11 downto 0),
src_CCD_G => sCCD_G(11 downto 0),
src_CCD_B => sCCD_B(11 downto 0),
oCCD_GRY => m_DATA
);
I2C_CCD_Config_inst : I2C_CCD_Config
port map
(
iCLK => clk,
iRST_N => reset_n,
iZOOM_MODE_SW => '0',
iEXPOSURE_ADJ => i_exposure_adj,
iEXPOSURE_DEC_p => '0',
I2C_SCLK => i2c_sclk,
I2C_SDAT => i2c_sdata
);
-- Resampling
VideoSampler_inst : VideoSampler
generic map (
PIXEL_WIDTH => 8,
DATA_WIDTH => 32,
FIFO_DEPTH => 4096*4,
DEFAULT_SCR => 0,
DEFAULT_FLOWLENGHT => 1280*1024,
HREF_POLARITY => "high",
VSYNC_POLARITY => "high"
)
port map (
reset_n_i => reset_n,
clk_i => clk,
pclk_i => ccd_pixclk,
href_i => ccd_lval,
vsync_i => ccd_fval,
pixel_i => m_DATA,
enable_i => '1',
flowlength_i => DEFAULT_FLOWLENGTH,
data_o => data,
dv_o => dv,
fv_o => fv
);
oRed <= sCCD_R(11 downto 4);
oGreen <= sCCD_G(11 downto 4);
oBlue <= sCCD_B(11 downto 4);
ccd_xclkin <= clk;
ccd_trigger <= '1';
ccd_reset <= '1';
pix_address <= temp_pix_address(pixel_address_width-1 downto 0);
end arch;
| gpl-3.0 | 93f651bd5e95eb23eee0b7acff132271 | 0.54491 | 3.36734 | false | false | false | false |
SonicFrog/ArchOrd | prime.vhdl | 1 | 2,843 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity prime is
port(
-- 32-bit input signal to test.
-- Should be registered in the circuit.
number: in std_logic_vector(31 downto 0);
-- Asynchronous reset when equal to '1'.
reset: in std_logic;
-- Is '1' when the data on 'input' is valid.
start: in std_logic;
-- Clock signal for the circuit.
clock: in std_logic;
-- Is '1' when the circuit completes a test for an input.
done: out std_logic;
-- Is '1' iff number is prime and
-- the signal is valid only when done='1'.
prime: out std_logicPas de NoSQL. Après plusieurs expériences avec MongoDB et CouchDB, je n’ai pas été convaincu que les bénéfices dépassaient le coût. Il faudrait un article complet là dessus (qu’on m’a d’ailleurs demandé).
);
component divi_combiner is
port (
dividend : in std_logic_vector(31 downto 0);
divisor : in std_logic_vector(31 downto 0);
quotient : out std_logic_vector(31 downto 0);
remainder : out std_logic_vector(31 downto 0)
);
end component;
component multi_combiner is
port (
operand1 : in std_logic_vector(31 downto 0);
operand2 : in std_logic_vector(31 downto 0);
product : out std_logic_vector(63 downto 0);
);
end component;
end entity;
architecture synth of prime is
type state is (s0, s1, s2, s3);
signal future_state, current_state : state;
signal counter : std_logic_vector(31 downto 0);
multi : multi_combiner port map (
operand1 => counter,
operand2 => counter,
product => product
);
divi : divi_combiner port map (
dividend => num,
divisor => counter,
remainder => remainder,
quotient => open
);
begin
state_switcher : process(clk, future_state, reset)
begin
if reset = '1' then
future_state <= s0;
num <= (others => '0');
elsif rising_edge(clk) then
current_state <= future_state;
end if;
end process;
state_handler : process(remainder, product)
begin
future_state <= current_state;
case current_state is
when s0 => -- Waiting for start = '1'
if start = '1' then
future_state <= s1;
num <= number;
counter <= conv_std_logic_vector(2, 32);
end if;
when s1 => -- Testing if prime
counter <= counter + 1;
if product > num then -- If we exceeded the square root
if remainder = 0 then
future_state <= s2;
else
future_state <= s3;
end if;
else -- If we have not reached the square root yet
if remainder = 0 then
future_state <= s2;
end if;
end if;
when s2 => -- Not prime
done <= '1';
prime <= '0';
when s3 => -- Prime
done <= '1';
prime <= '1';
when others => -- Default case
future_state <= s0;
end case;
end process;
end architecture ; -- synth | gpl-2.0 | 56eb7167fe8602645e4240f1141a0b54 | 0.64177 | 2.958115 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/axiwrapper/src/axiLiteSlaveWrapper-rtl-ea.vhd | 3 | 14,576 | -------------------------------------------------------------------------------
--! @file axiLiteSlaveWrapper-rtl-ea.vhd
--
--! @brief AXI lite slave wrapper on avalon slave interface signals
--
--! @details AXI lite slave will convert AXI slave interface singal to Avalon
--! interface signals.
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014, B&R Industrial Automation GmbH
-- Copyright (c) 2014, Kalycito Infotech Private Limited.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--! Use standard ieee library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Use libcommon library
library libcommon;
--! Use Global Library
use libcommon.global.all;
-------------------------------------------------------------------------------
--! @brief
--! @details AXI-lite slave wrapper will receive signals from AXI bus and
--! provide proper inputs for a Avlon interface to perform the same action
--! initiated by AXI master
-------------------------------------------------------------------------------
entity axiLiteSlaveWrapper is
generic (
--! Base Lower address for the AXI-lite slave interface
gBaseAddr : std_logic_vector(31 downto 0) := x"00000000";
--! Base Higher address for the AXI-lite slave interface
gHighAddr : std_logic_vector(31 downto 0) := x"0000ffff";
--! Address width for AXI bus interface
gAddrWidth : integer := 32;
--! Data width for AXI bus interface
gDataWidth : integer := 32
);
port (
--! Global Clock for AXI
iAclk : in std_logic;
--! Global Reset for AXI
inAReset : in std_logic;
--! Address for Write Address Channel
iAwaddr : in std_logic_vector(gAddrWidth-1 downto 0);
--! Protection for Write Address Channel
iAwprot : in std_logic_vector(2 downto 0); --unused input
--! AddressValid for Write Address Channel
iAwvalid : in std_logic;
--! AddressReady for Write Address Channel
oAwready : out std_logic;
--! WriteData for Write Data Channel
iWdata : in std_logic_vector(gDataWidth-1 downto 0);
--! WriteStrobe for Write Data Channel
iWstrb : in std_logic_vector(gDataWidth/8-1 downto 0);
--! WriteValid for Write Data Channel
iWvalid : in std_logic;
--! WriteReady for Write Data Channel
oWready : out std_logic;
--! WriteResponse for Write Response Channel
oBresp : out std_logic_vector (1 downto 0);
--! ResponseValid for Write Response Channel
oBvalid : out std_logic;
--! ResponaseReady for Write Response Channel
iBready : in std_logic;
--! ReadAddress for Read Address Channel
iAraddr : in std_logic_vector(gAddrWidth-1 downto 0);
--! ReadAddressProtection for Read Address Channel
iArprot : in std_logic_vector(2 downto 0); --unused input
--! ReadAddressValid for Read Address Channel
iArvalid : in std_logic;
--! ReadAddressReady for Read Address Channel
oArready : out std_logic;
--! ReadData for Read Data Channel
oRdata : out std_logic_vector(gDataWidth-1 downto 0);
--! ReadResponse for Read Data Channel
oRresp : out std_logic_vector(1 downto 0);
--! ReadValid for Read Data Channel
oRvalid : out std_logic;
--! ReadReady for Read Data Channel
iRready : in std_logic;
--! Address to Avalon Slave Interface
oAvsAddress : out std_logic_vector(gAddrWidth-1 downto 0);
--! Byte Enable for Avalon Slave interface
oAvsByteenable : out std_logic_vector(gDataWidth/8-1 downto 0);
--! Write Data for Avalon Slave interface
oAvsWritedata : out std_logic_vector(gDataWidth-1 downto 0);
--! Read Data for Avalon Slave interface
iAvsReaddata : in std_logic_vector(gDataWidth-1 downto 0);
--! Read signal for Avalon Slave interface
oAvsRead : out std_logic;
--! Write signal for Avalon Slave interface
oAvsWrite : out std_logic;
--! WaitRequest for Avalon slave interface
iAvsWaitrequest : in std_logic
);
end axiLiteSlaveWrapper;
architecture rtl of axiLiteSlaveWrapper is
--! Control signal FSM
type tFsm is (
sIDLE,
sREAD,
sREAD_DONE,
sWRITE,
sWRITE_DONE,
sWRRES_DONE,
sDELAY
);
--Avalon Interface designs
--! address latch for Avalon Interface
signal address : std_logic_vector(gAddrWidth-1 downto 0);
--! Muxed address from AXI interface
signal mux_address : std_logic_vector(gAddrWidth-1 downto 0);
--! Chip select for address decoder
signal chip_sel : std_logic;
--! Muxed byte enable latch from AXI Interface
signal byte_enable : std_logic_vector(gDataWidth/8-1 downto 0);
--Signals for FSM
--! synchronized fsm state
signal fsm : tFsm;
--! fsm state for combinational logic
signal fsm_next : tFsm;
--Internal Signals
--! control for Avalon read signal with fsm
signal avalonRead : std_logic;
--! Read Data latch for Avalon interface
signal avalonReadDataLatch : std_logic_vector(31 downto 0);
--! control for Avalon write signal with fsm
signal avalonWrite : std_logic;
--! write data from AXI for Avalon interface
signal axiWriteData : std_logic_vector(31 downto 0);
--! valid data from AXI to Avalon
signal axiDataValid : std_logic;
--! Write start fsm operations
signal writeStart : std_logic;
--! Write select for control write operations
signal write_sel : std_logic;
--! Read Start for fsm operations
signal readStart : std_logic;
--! Read select for control read operations
signal read_sel : std_logic;
begin
--Avalon Slave Interface Signals
oAvsAddress <= address;
oAvsByteenable <= byte_enable;
oAvsRead <= avalonRead;
oAvsWrite <= avalonWrite;
oAvsWritedata <= axiWriteData;
avalonRead <= cActivated when readStart = cActivated and fsm = sIDLE else
cActivated when fsm = sREAD else
cInactivated when fsm = sREAD_DONE else
cInactivated;
avalonWrite <= cActivated when fsm = sWRITE and iWvalid = cActivated else
cActivated when fsm = sIDLE and axiDataValid = cActivated else
cActivated when fsm = sWRITE_DONE else
cInactivated;
axiWriteData <= iWdata when axiDataValid = cActivated else
axiWriteData;
-- AXI-Lite Write Data Signals
oBvalid <= cActivated when fsm = sWRITE_DONE and iAvsWaitrequest = cInactivated else
cActivated when fsm = sWRRES_DONE else
cInactivated;
oAwready <= cActivated when fsm = sIDLE and writeStart = cActivated else
cInactivated;
oWready <= cActivated when fsm = sWRITE else
cActivated when fsm = sIDLE and axiDataValid = cActivated else
cInactivated;
-- AXI-lite Read Data Signals
oArready <= cActivated when fsm = sIDLE and readStart = cActivated else
cInactivated;
oRvalid <= cActivated when iAvsWaitrequest = cInactivated and fsm = sREAD else
cActivated when fsm = sREAD_DONE else
cInactivated;
oRdata <= avalonReadDataLatch;
avalonReadDataLatch <= iAvsReaddata when iAvsWaitrequest = cInactivated else
avalonReadDataLatch;
--TODO: Check the possibility of Error Response signals
oBresp <= "00";
oRresp <= "00";
-- Address Decoder
chip_sel <= read_sel or write_sel;
-- 64Kbyte address range only supported so MSB 16 bits enough for Decoding
write_sel <= cActivated when iAwaddr(31 downto 16) = gBaseAddr(31 downto 16) else
cInactivated;
read_sel <= cActivated when iAraddr(31 downto 16) = gBaseAddr(31 downto 16) else
cInactivated;
-- TODO: Check possibilities of reduce the no of bits in MUX/latch design
-- and avoid combinational feedback on MUX
-- Mux the address first and latch it with FSM
address <= mux_address when fsm = sIDLE else
address ;
mux_address <= iAraddr when readStart = cActivated else
iAwaddr when writeStart = cActivated else
x"00000000" ;
writeStart <= chip_sel and iAwvalid;
readStart <= chip_sel and iArvalid;
axiDataValid <= iWvalid;
byte_enable <= x"F" when readStart = cActivated and fsm = sIDLE else
iWstrb when writeStart = cActivated and fsm = sIDLE else
byte_enable;
-- Main Control FSM for converting AXI-lite signals to Avalon
--! Clock Based Process for state changes
SEQ_LOGIC_FSM : process(iAclk)
begin
if rising_edge(iAclk) then
if inAReset = cnActivated then
fsm <= sIDLE;
else
fsm <= fsm_next;
end if;
end if;
end process SEQ_LOGIC_FSM;
--! Control State machine
COM_LOGIC_FSM : process (
fsm,
chip_sel,
iAwvalid,
iArvalid,
iRready,
iWvalid,
iBready,
iAvsWaitrequest
)
begin
--Default to avoid latches
fsm_next <= fsm;
case fsm is
when sIDLE =>
if chip_sel = cActivated then
--Write Operations
if iAwvalid = cActivated then
if iWvalid = cActivated then
if iAvsWaitrequest = cInactivated then
fsm_next <= sWRRES_DONE;
else
fsm_next <= sWRITE_DONE;
end if;
else
fsm_next <= sWRITE;
end if;
--Read Operations
elsif iArvalid = cActivated then
if iAvsWaitrequest = cInactivated then
fsm_next <= sREAD_DONE;
else
fsm_next <= sREAD;
end if;
else
fsm_next <= sIDLE;
end if;
else
fsm_next <= sIDLE;
end if;
when sREAD =>
-- Read Valid gets assert Here
if iAvsWaitrequest = cInactivated then
if iRready = cActivated then
fsm_next <= sIDLE;
else
fsm_next <= sREAD_DONE;
end if;
else
fsm_next <= sREAD;
end if;
when sREAD_DONE =>
if iRready = cActivated then
fsm_next <= sIDLE;
else
fsm_next <= sREAD_DONE;
end if;
when sWRITE =>
if iWvalid = cActivated then
if iAvsWaitrequest = cInactivated then
if iBready = cActivated then
fsm_next <= sIDLE;
else
fsm_next <= sWRRES_DONE;
end if;
else
fsm_next <= sWRITE_DONE;
end if;
else
fsm_next <= sWRITE;
end if;
when sWRITE_DONE =>
if iAvsWaitrequest = cInactivated then
if iBready = cActivated then
fsm_next <= sIDLE;
else
fsm_next <= sWRRES_DONE;
end if;
else
fsm_next <= sWRITE_DONE;
end if;
when sWRRES_DONE =>
if iBready = cActivated then
fsm_next <= sIDLE;
else
fsm_next <= sWRRES_DONE;
end if;
when sDELAY =>
fsm_next <= sIDLE;
when others =>
null;
end case;
end process COM_LOGIC_FSM;
end rtl;
| gpl-2.0 | d89fa6cd5bc649c8593ef85a872dce4d | 0.549259 | 5.192732 | false | false | false | false |
DreamIP/GPStudio | support/process/sobel/hdl/sobel_process.vhd | 1 | 5,345 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity sobel_process is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer;
WEIGHT_SIZE : integer := 8
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_width : in std_logic_vector(15 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end sobel_process;
architecture rtl of sobel_process is
component matrix_extractor
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer;
OUTVALUE_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
------------------------ matrix out ---------------------
p00, p01, p02 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p10, p11, p12 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p20, p21, p22 : out std_logic_vector((PIX_WIDTH-1) downto 0);
matrix_dv : out std_logic;
---------------------- computed value -------------------
value_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
value_dv : in std_logic;
------------------------- params ------------------------
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0)
);
end component;
-- neighbors extraction
signal p00, p01, p02 : std_logic_vector((IN_SIZE-1) downto 0);
signal p10, p11, p12 : std_logic_vector((IN_SIZE-1) downto 0);
signal p20, p21, p22 : std_logic_vector((IN_SIZE-1) downto 0);
signal matrix_dv : std_logic;
-- products calculation
signal prod00, prod01, prod02 : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
signal prod10, prod11, prod12 : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
signal prod20, prod21, prod22 : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
signal prod_dv : std_logic;
signal value_data : std_logic_vector((IN_SIZE-1) downto 0);
signal value_dv : std_logic;
signal out_fv_s : std_logic;
signal enable_s : std_logic;
begin
matrix_extractor_inst : matrix_extractor
generic map (
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
PIX_WIDTH => IN_SIZE,
OUTVALUE_WIDTH => IN_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
p00 => p00, p01 => p01, p02 => p02,
p10 => p10, p11 => p11, p12 => p12,
p20 => p20, p21 => p21, p22 => p22,
matrix_dv => matrix_dv,
value_data => value_data,
value_dv => value_dv,
out_data => out_data,
out_fv => out_fv_s,
out_dv => out_dv,
enable_i => status_reg_enable_bit,
widthimg_i => widthimg_reg_width
);
process (clk_proc, reset_n, matrix_dv)
variable sum : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
begin
if(reset_n='0') then
enable_s <= '0';
prod_dv <= '0';
value_dv <= '0';
elsif(rising_edge(clk_proc)) then
if(in_fv = '0') then
enable_s <= status_reg_enable_bit;
prod_dv <= '0';
value_dv <= '0';
end if;
-- product calculation pipeline stage
prod_dv <= '0';
if(matrix_dv = '1' and enable_s = '1') then
prod00 <= "11111110" * signed('0' & p00); -- w00 = -2
prod01 <= "11111110" * signed('0' & p01); -- w01 = -2
prod02 <= "00000000" * signed('0' & p02); -- w02 = 0
prod10 <= "11111110" * signed('0' & p10); -- w10 = -2
prod11 <= "00000000" * signed('0' & p11); -- w11 = 0
prod12 <= "00000010" * signed('0' & p12); -- w12 = 2
prod20 <= "00000000" * signed('0' & p20); -- w20 = 0
prod21 <= "00000010" * signed('0' & p21); -- w21 = 2
prod22 <= "00000010" * signed('0' & p22); -- w22 = 2
prod_dv <= '1';
end if;
value_dv <= '0';
if(prod_dv='1' and enable_s = '1') then
sum := prod00 + prod01 + prod02 +
prod10 + prod11 + prod12 +
prod20 + prod21 + prod22;
if (sum(sum'left) = '1') then
sum := (others => '0');
end if;
value_data <= std_logic_vector(sum)(OUT_SIZE -1 downto 0);
value_dv <= '1';
end if;
end if;
end process;
out_fv <= enable_s and out_fv_s;
end rtl;
| gpl-3.0 | a344849f9deee17c9bd537cc4bc71539 | 0.490926 | 3.084247 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/fifo/src/asyncFifo-rtl-a.vhd | 3 | 9,787 | -------------------------------------------------------------------------------
--! @file asyncFifo-rtl-a.vhd
--
--! @brief The asynchronous Fifo architecture.
--
--! @details This is a generic dual clocked FIFO using the dpRam component as
--! memory.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
architecture rtl of asyncFifo is
--! Address width
constant cAddrWidth : natural := logDualis(gWordSize);
--! Type for DPRAM port commons
type tDpramPortCommon is record
clk : std_logic;
enable : std_logic;
address : std_logic_vector(cAddrWidth-1 downto 0);
end record;
--! Type for DPRAM port assignment
type tDpramPort is record
wrPort : tDpramPortCommon;
rdPort : tDpramPortCommon;
write : std_logic;
writedata : std_logic_vector(gDataWidth-1 downto 0);
readdata : std_logic_vector(gDataWidth-1 downto 0);
end record;
--! Type for control port
type tControlPort is record
clk : std_logic;
rst : std_logic;
request : std_logic;
otherPointer : std_logic_vector(cAddrWidth downto 0);
empty : std_logic;
full : std_logic;
pointer : std_logic_vector(cAddrWidth downto 0);
address : std_logic_vector(cAddrWidth-1 downto 0);
usedWord : std_logic_vector(cAddrWidth-1 downto 0);
end record;
--! Type for pointer synchronizers
type tPointerSyncPort is record
clk : std_logic;
rst : std_logic;
din : std_logic_vector(cAddrWidth downto 0);
dout : std_logic_vector(cAddrWidth downto 0);
end record;
--! DPRAM instance
signal inst_dpram : tDpramPort;
--! Write controller instance
signal inst_writeCtrl : tControlPort;
--! Read controller instance
signal inst_readCtrl : tControlPort;
--! Write pointer synchronizer instance
signal inst_writeSync : tPointerSyncPort;
--! Read pointer synchronizer instance
signal inst_readSync : tPointerSyncPort;
begin
assert (gMemRes = "ON")
report "This FIFO implementation only supports memory resources!"
severity warning;
---------------------------------------------------------------------------
-- Assign Outputs
---------------------------------------------------------------------------
-- Write port
oWrEmpty <= inst_writeCtrl.empty;
oWrFull <= inst_writeCtrl.full;
oWrUsedw <= inst_writeCtrl.usedWord;
-- Read port
oRdEmpty <= inst_readCtrl.empty;
oRdFull <= inst_readCtrl.full;
oRdUsedw <= inst_readCtrl.usedWord;
oRdData <= inst_dpram.readdata;
---------------------------------------------------------------------------
-- Map DPRAM instance
---------------------------------------------------------------------------
-- Write port
inst_dpram.wrPort.clk <= iWrClk;
inst_dpram.wrPort.enable <= inst_writeCtrl.request;
inst_dpram.write <= inst_writeCtrl.request;
inst_dpram.wrPort.address <= inst_writeCtrl.address;
inst_dpram.writedata <= iWrData;
-- Read port
inst_dpram.rdPort.clk <= iRdClk;
inst_dpram.rdPort.enable <= iRdReq;
inst_dpram.rdPort.address <= inst_readCtrl.address;
---------------------------------------------------------------------------
-- Map Write and Read controller instance
---------------------------------------------------------------------------
inst_readCtrl.clk <= iRdClk;
inst_readCtrl.rst <= iAclr;
inst_readCtrl.request <= iRdReq;
inst_readCtrl.otherPointer <= inst_writeSync.dout;
inst_writeCtrl.clk <= iWrClk;
inst_writeCtrl.rst <= iAclr;
inst_writeCtrl.request <= iWrReq and not inst_writeCtrl.full;
inst_writeCtrl.otherPointer <= inst_readSync.dout;
---------------------------------------------------------------------------
-- Map pointer synchronizers
---------------------------------------------------------------------------
inst_readSync.rst <= iAclr;
inst_readSync.clk <= iWrClk; -- synchronize read pointer to write clock
inst_readSync.din <= inst_readCtrl.pointer;
inst_writeSync.rst <= iAclr;
inst_writeSync.clk <= iRdClk; -- synchronize write pointer to read clock
inst_writeSync.din <= inst_writeCtrl.pointer;
---------------------------------------------------------------------------
-- Instances
---------------------------------------------------------------------------
--! This is the FIFO read controller.
FIFO_READ_CONTROL : entity work.fifoRead
generic map (
gAddrWidth => cAddrWidth
)
port map (
iClk => inst_readCtrl.clk,
iRst => inst_readCtrl.rst,
iRead => inst_readCtrl.request,
iWrPointer => inst_readCtrl.otherPointer,
oEmpty => inst_readCtrl.empty,
oFull => inst_readCtrl.full,
oPointer => inst_readCtrl.pointer,
oAddress => inst_readCtrl.address,
oUsedWord => inst_readCtrl.usedWord
);
--! This is the FIFO write controller.
FIFO_WRITE_CONTROL : entity work.fifoWrite
generic map (
gAddrWidth => cAddrWidth
)
port map (
iClk => inst_writeCtrl.clk,
iRst => inst_writeCtrl.rst,
iWrite => inst_writeCtrl.request,
iRdPointer => inst_writeCtrl.otherPointer,
oEmpty => inst_writeCtrl.empty,
oFull => inst_writeCtrl.full,
oPointer => inst_writeCtrl.pointer,
oAddress => inst_writeCtrl.address,
oUsedWord => inst_writeCtrl.usedWord
);
--! This is the FIFO buffer.
FIFO_BUFFER : entity work.dpRamSplxNbe
generic map (
gWordWidth => gDataWidth,
gNumberOfWords => gWordSize,
gInitFile => "UNUSED"
)
port map (
iClk_A => inst_dpram.wrPort.clk,
iEnable_A => inst_dpram.wrPort.enable,
iWriteEnable_A => inst_dpram.write,
iAddress_A => inst_dpram.wrPort.address,
iWritedata_A => inst_dpram.writedata,
iClk_B => inst_dpram.rdPort.clk,
iEnable_B => inst_dpram.rdPort.enable,
iAddress_B => inst_dpram.rdPort.address,
oReaddata_B => inst_dpram.readdata
);
--! This generate block instantiates multiple synchrinizers to transfer
--! the write and read pointers to the opposite clock domains.
GEN_POINTERSYNC : for i in cAddrWidth downto 0 generate
WRITESYNC : entity libcommon.synchronizer
generic map (
gStages => gSyncStages,
gInit => cInactivated
)
port map (
iArst => inst_writeSync.rst,
iClk => inst_writeSync.clk,
iAsync => inst_writeSync.din(i),
oSync => inst_writeSync.dout(i)
);
READSYNC : entity libcommon.synchronizer
generic map (
gStages => gSyncStages,
gInit => cInactivated
)
port map (
iArst => inst_readSync.rst,
iClk => inst_readSync.clk,
iAsync => inst_readSync.din(i),
oSync => inst_readSync.dout(i)
);
end generate GEN_POINTERSYNC;
end rtl;
| gpl-2.0 | 977ba4471a463f4f887f940d4c530208 | 0.538061 | 4.91562 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/eth_marvell_88e1111_slave.vhd | 1 | 3,294 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity eth_marvell_88e1111_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_enable : out std_logic;
flow_in0_enable : out std_logic;
flow_in1_enable : out std_logic;
flow_in2_enable : out std_logic;
flow_in3_enable : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end eth_marvell_88e1111_slave;
architecture rtl of eth_marvell_88e1111_slave is
-- Registers address
constant STATUS_REG_ADDR : natural := 0;
constant FLOW_IN0_REG_ADDR : natural := 1;
constant FLOW_IN1_REG_ADDR : natural := 2;
constant FLOW_IN2_REG_ADDR : natural := 3;
constant FLOW_IN3_REG_ADDR : natural := 4;
-- Internal registers
signal status_enable_reg : std_logic;
signal flow_in0_enable_reg : std_logic;
signal flow_in1_enable_reg : std_logic;
signal flow_in2_enable_reg : std_logic;
signal flow_in3_enable_reg : std_logic;
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_enable_reg <= '0';
flow_in0_enable_reg <= '0';
flow_in1_enable_reg <= '0';
flow_in2_enable_reg <= '0';
flow_in3_enable_reg <= '0';
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case to_integer(unsigned(addr_rel_i)) is
when STATUS_REG_ADDR =>
status_enable_reg <= datawr_i(0);
when FLOW_IN0_REG_ADDR =>
flow_in0_enable_reg <= datawr_i(0);
when FLOW_IN1_REG_ADDR =>
flow_in1_enable_reg <= datawr_i(0);
when FLOW_IN2_REG_ADDR =>
flow_in2_enable_reg <= datawr_i(0);
when FLOW_IN3_REG_ADDR =>
flow_in3_enable_reg <= datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case to_integer(unsigned(addr_rel_i)) is
when STATUS_REG_ADDR =>
datard_o <= "0000000000000000000000000000000" & status_enable_reg;
when FLOW_IN0_REG_ADDR =>
datard_o <= "0000000000000000000000000000000" & flow_in0_enable_reg;
when FLOW_IN1_REG_ADDR =>
datard_o <= "0000000000000000000000000000000" & flow_in1_enable_reg;
when FLOW_IN2_REG_ADDR =>
datard_o <= "0000000000000000000000000000000" & flow_in2_enable_reg;
when FLOW_IN3_REG_ADDR =>
datard_o <= "0000000000000000000000000000000" & flow_in3_enable_reg;
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_enable <= status_enable_reg;
flow_in0_enable <= flow_in0_enable_reg;
flow_in1_enable <= flow_in1_enable_reg;
flow_in2_enable <= flow_in2_enable_reg;
flow_in3_enable <= flow_in3_enable_reg;
end rtl;
| gpl-3.0 | 9984a1dc7cb3fe74433ff7e989a40b7d | 0.594414 | 2.938448 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/registerFileRtl.vhd | 3 | 5,462 | -------------------------------------------------------------------------------
--! @file registerFileRtl.vhd
--
--! @brief Register table file implementation
--
--! @details This implementation is a simple dual ported memory implemented in
--! using register resources.
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity registerFile is
generic (
gRegCount : natural := 8
);
port (
iClk : in std_logic;
iRst : in std_logic;
iWriteA : in std_logic;
iWriteB : in std_logic;
iByteenableA: in std_logic_vector;
iByteenableB: in std_logic_vector;
iAddrA : in std_logic_vector(LogDualis(gRegCount)-1 downto 0);
iAddrB : in std_logic_vector(LogDualis(gRegCount)-1 downto 0);
iWritedataA : in std_logic_vector;
oReaddataA : out std_logic_vector;
iWritedataB : in std_logic_vector;
oReaddataB : out std_logic_vector
);
end registerFile;
architecture Rtl of registerFile is
constant cByte : natural := 8;
type tRegSet is
array (natural range <>) of std_logic_vector(iWritedataA'range);
signal regFile, regFile_next : tRegSet(gRegCount-1 downto 0);
begin
--register set
reg : process(iClk)
begin
if rising_edge(iClk) then
if iRst = cActivated then
--clear register file
regFile <= (others => (others => '0'));
else
regFile <= regFile_next;
end if;
end if;
end process;
--write data into Register File with respect to address
--note: a overrules b
regFileWrite : process(
iWriteA, iWriteB, iAddrA, iAddrB,
iByteenableA, iByteenableB,
iWritedataA, iWritedataB, regFile)
variable vWritedata : std_logic_vector(iWritedataA'range);
begin
--default
regFile_next <= regFile;
vWritedata := (others => cInactivated);
if iWriteB = cActivated then
--read out register content first
vWritedata := regFile(to_integer(unsigned(iAddrB)));
--then consider byteenable
for i in iWritedataB'range loop
if iByteenableB(i/cByte) = cActivated then
--if byte is enabled assign it
vWritedata(i) := iWritedataB(i);
end if;
end loop;
--write to address the masked writedata
regFile_next(to_integer(unsigned(iAddrB))) <= vWritedata;
end if;
if iWriteA = cActivated then
--read out register content first
vWritedata := regFile(to_integer(unsigned(iAddrA)));
--then consider byteenable
for i in iWritedataA'range loop
if iByteenableA(i/cByte) = cActivated then
--if byte is enabled assign it
vWritedata(i) := iWritedataA(i);
end if;
end loop;
--write to address the masked writedata
regFile_next(to_integer(unsigned(iAddrA))) <= vWritedata;
end if;
end process;
--read data from Register File with respect to iAddrRead
regFileRead : process(iAddrA, iAddrB, regFile)
begin
--read from address
oReaddataA <= regFile(to_integer(unsigned(iAddrA)));
oReaddataB <= regFile(to_integer(unsigned(iAddrB)));
end process;
end Rtl;
| gpl-2.0 | ed74ca001eb6c271ff9a1b2c15020689 | 0.604724 | 4.67237 | false | false | false | false |
DreamIP/GPStudio | support/io/com/hdl/hal/eth_marvell_88e1111/hdl/encapsulation/eth_tx_crc.vhd | 1 | 2,492 | ----------------------------------------------------------------------------------
-- Company: Laboratoire Leprince Ringuet
-- Engineer:
--
-- Create Date: 14:03:42 10/14/2011
-- Design Name:
-- Module Name: eth_tx_crc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity eth_tx_crc is Port(
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
IN_ETH_STREAM : in STD_LOGIC_VECTOR(9 downto 0);
OUT_ETH_STREAM : out STD_LOGIC_VECTOR(9 downto 0));
end eth_tx_crc;
architecture Behavioral of eth_tx_crc is
type multiple is array (3 downto 0) of std_logic_vector(7 downto 0);
signal dat_dly : multiple;
signal frm_dly : STD_LOGIC_VECTOR(3 downto 0);
signal checksum : STD_LOGIC_VECTOR(7 downto 0);
signal my_sig : std_logic;
component crc32_8 Port(
CRC_REG : out STD_LOGIC_VECTOR(31 downto 0);
CRC : out STD_LOGIC_VECTOR(7 downto 0);
D : in STD_LOGIC_VECTOR(7 downto 0);
CALC : in STD_LOGIC;
INIT : in STD_LOGIC;
D_VALID : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC);
end component;
begin
my_sig <= not frm_dly(3);
crc_checksum : crc32_8 port map(
CLK => CLK,
D => dat_dly(3),--data input
INIT => my_sig,--not frm_dly(3),--reset CRC
CALC => IN_ETH_STREAM(8),--use D in calculation
D_VALID => IN_ETH_STREAM(9),--strobe bit
CRC_REG => open,
CRC => checksum,
RESET => RESET);--global reset used as redundant signal
process(CLK,RESET)
begin
if RESET = '0' then
dat_dly(0) <= x"00";
dat_dly(1) <= x"00";
dat_dly(2) <= x"00";
dat_dly(3) <= x"00";
frm_dly <= x"0";
OUT_ETH_STREAM <= "00" & x"00";
elsif CLK'event and CLK = '1' then
if IN_ETH_STREAM(9) = '1' then
--delay the data by four bytes to detect the end of the frame
dat_dly <= dat_dly(2 downto 0) & IN_ETH_STREAM(7 downto 0);
frm_dly <= frm_dly(2 downto 0) & IN_ETH_STREAM(8);
--register output
OUT_ETH_STREAM(9 downto 8) <= '1' & frm_dly(3);
if IN_ETH_STREAM(8) = '1' then
OUT_ETH_STREAM(7 downto 0) <= dat_dly(3);
else
OUT_ETH_STREAM(7 downto 0) <= checksum;
end if;
else
OUT_ETH_STREAM(9) <= '0';
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 7664695daf90187b5f1e6aff9d72d877 | 0.564607 | 2.945626 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/tracking_camera_system_tb.vhd | 1 | 9,159 | -- tracking_camera_system_tb.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.13.13:59:35
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tracking_camera_system_tb is
end entity tracking_camera_system_tb;
architecture rtl of tracking_camera_system_tb is
component tracking_camera_system is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
character_lcd_0_external_interface_DATA : inout std_logic_vector(7 downto 0) := (others => 'X'); -- DATA
character_lcd_0_external_interface_ON : out std_logic; -- ON
character_lcd_0_external_interface_BLON : out std_logic; -- BLON
character_lcd_0_external_interface_EN : out std_logic; -- EN
character_lcd_0_external_interface_RS : out std_logic; -- RS
character_lcd_0_external_interface_RW : out std_logic; -- RW
green_leds_external_connection_export : out std_logic_vector(7 downto 0); -- export
switch_external_connection_export : in std_logic := 'X'; -- export
servo_pwm_0_conduit_end_0_export : out std_logic; -- export
altpll_0_c0_clk : out std_logic; -- clk
sdram_0_wire_addr : out std_logic_vector(11 downto 0); -- addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_0_wire_cas_n : out std_logic; -- cas_n
sdram_0_wire_cke : out std_logic; -- cke
sdram_0_wire_cs_n : out std_logic; -- cs_n
sdram_0_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_0_wire_ras_n : out std_logic; -- ras_n
sdram_0_wire_we_n : out std_logic; -- we_n
sram_0_external_interface_DQ : inout std_logic_vector(15 downto 0) := (others => 'X'); -- DQ
sram_0_external_interface_ADDR : out std_logic_vector(17 downto 0); -- ADDR
sram_0_external_interface_LB_N : out std_logic; -- LB_N
sram_0_external_interface_UB_N : out std_logic; -- UB_N
sram_0_external_interface_CE_N : out std_logic; -- CE_N
sram_0_external_interface_OE_N : out std_logic; -- OE_N
sram_0_external_interface_WE_N : out std_logic; -- WE_N
switch_0_external_connection_export : in std_logic := 'X' -- export
);
end component tracking_camera_system;
component altera_avalon_clock_source is
generic (
CLOCK_RATE : positive := 10;
CLOCK_UNIT : positive := 1000000
);
port (
clk : out std_logic -- clk
);
end component altera_avalon_clock_source;
component altera_avalon_reset_source is
generic (
ASSERT_HIGH_RESET : integer := 1;
INITIAL_RESET_CYCLES : integer := 0
);
port (
reset : out std_logic; -- reset_n
clk : in std_logic := 'X' -- clk
);
end component altera_avalon_reset_source;
signal tracking_camera_system_inst_clk_bfm_clk_clk : std_logic; -- tracking_camera_system_inst_clk_bfm:clk -> [tracking_camera_system_inst:clk_clk, tracking_camera_system_inst_reset_bfm:clk]
signal tracking_camera_system_inst_reset_bfm_reset_reset : std_logic; -- tracking_camera_system_inst_reset_bfm:reset -> tracking_camera_system_inst:reset_reset_n
begin
tracking_camera_system_inst : component tracking_camera_system
port map (
clk_clk => tracking_camera_system_inst_clk_bfm_clk_clk, -- clk.clk
reset_reset_n => tracking_camera_system_inst_reset_bfm_reset_reset, -- reset.reset_n
character_lcd_0_external_interface_DATA => open, -- character_lcd_0_external_interface.DATA
character_lcd_0_external_interface_ON => open, -- .ON
character_lcd_0_external_interface_BLON => open, -- .BLON
character_lcd_0_external_interface_EN => open, -- .EN
character_lcd_0_external_interface_RS => open, -- .RS
character_lcd_0_external_interface_RW => open, -- .RW
green_leds_external_connection_export => open, -- green_leds_external_connection.export
switch_external_connection_export => open, -- switch_external_connection.export
servo_pwm_0_conduit_end_0_export => open, -- servo_pwm_0_conduit_end_0.export
altpll_0_c0_clk => open, -- altpll_0_c0.clk
sdram_0_wire_addr => open, -- sdram_0_wire.addr
sdram_0_wire_ba => open, -- .ba
sdram_0_wire_cas_n => open, -- .cas_n
sdram_0_wire_cke => open, -- .cke
sdram_0_wire_cs_n => open, -- .cs_n
sdram_0_wire_dq => open, -- .dq
sdram_0_wire_dqm => open, -- .dqm
sdram_0_wire_ras_n => open, -- .ras_n
sdram_0_wire_we_n => open, -- .we_n
sram_0_external_interface_DQ => open, -- sram_0_external_interface.DQ
sram_0_external_interface_ADDR => open, -- .ADDR
sram_0_external_interface_LB_N => open, -- .LB_N
sram_0_external_interface_UB_N => open, -- .UB_N
sram_0_external_interface_CE_N => open, -- .CE_N
sram_0_external_interface_OE_N => open, -- .OE_N
sram_0_external_interface_WE_N => open, -- .WE_N
switch_0_external_connection_export => open -- switch_0_external_connection.export
);
tracking_camera_system_inst_clk_bfm : component altera_avalon_clock_source
generic map (
CLOCK_RATE => 50000000,
CLOCK_UNIT => 1
)
port map (
clk => tracking_camera_system_inst_clk_bfm_clk_clk -- clk.clk
);
tracking_camera_system_inst_reset_bfm : component altera_avalon_reset_source
generic map (
ASSERT_HIGH_RESET => 0,
INITIAL_RESET_CYCLES => 50
)
port map (
reset => tracking_camera_system_inst_reset_bfm_reset_reset, -- reset.reset_n
clk => tracking_camera_system_inst_clk_bfm_clk_clk -- clk.clk
);
end architecture rtl; -- of tracking_camera_system_tb
| gpl-2.0 | a556040d919aebbf802c0f1e38a93b37 | 0.399607 | 4.459104 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_altpll_0_pll_slave_translator.vhd | 1 | 12,507 | -- tracking_camera_system_altpll_0_pll_slave_translator.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.13.13:59:38
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tracking_camera_system_altpll_0_pll_slave_translator is
generic (
AV_ADDRESS_W : integer := 2;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(1 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_byteenable : out std_logic_vector(3 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(3 downto 0);
uav_clken : in std_logic := '0'
);
end entity tracking_camera_system_altpll_0_pll_slave_translator;
architecture rtl of tracking_camera_system_altpll_0_pll_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component altera_merlin_slave_translator;
begin
altpll_0_pll_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
end architecture rtl; -- of tracking_camera_system_altpll_0_pll_slave_translator
| gpl-2.0 | ef57e0f0273bab01c9b94a5e79db235a | 0.435836 | 4.252635 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_nios2_qsys_0_jtag_debug_module_tck.vhd | 1 | 9,643 | --Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tracking_camera_system_nios2_qsys_0_jtag_debug_module_tck is
port (
-- inputs:
signal MonDReg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal break_readreg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dbrk_hit0_latch : IN STD_LOGIC;
signal dbrk_hit1_latch : IN STD_LOGIC;
signal dbrk_hit2_latch : IN STD_LOGIC;
signal dbrk_hit3_latch : IN STD_LOGIC;
signal debugack : IN STD_LOGIC;
signal ir_in : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal jtag_state_rti : IN STD_LOGIC;
signal monitor_error : IN STD_LOGIC;
signal monitor_ready : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal resetlatch : IN STD_LOGIC;
signal tck : IN STD_LOGIC;
signal tdi : IN STD_LOGIC;
signal tracemem_on : IN STD_LOGIC;
signal tracemem_trcdata : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tracemem_tw : IN STD_LOGIC;
signal trc_im_addr : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal trc_on : IN STD_LOGIC;
signal trc_wrap : IN STD_LOGIC;
signal trigbrktype : IN STD_LOGIC;
signal trigger_state_1 : IN STD_LOGIC;
signal vs_cdr : IN STD_LOGIC;
signal vs_sdr : IN STD_LOGIC;
signal vs_uir : IN STD_LOGIC;
-- outputs:
signal ir_out : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal jrst_n : OUT STD_LOGIC;
signal sr : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
signal st_ready_test_idle : OUT STD_LOGIC;
signal tdo : OUT STD_LOGIC
);
end entity tracking_camera_system_nios2_qsys_0_jtag_debug_module_tck;
architecture europa of tracking_camera_system_nios2_qsys_0_jtag_debug_module_tck is
component altera_std_synchronizer is
GENERIC (
depth : NATURAL
);
PORT (
signal dout : OUT STD_LOGIC;
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal din : IN STD_LOGIC
);
end component altera_std_synchronizer;
signal DRsize : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal debugack_sync : STD_LOGIC;
signal internal_jrst_n1 : STD_LOGIC;
signal internal_sr : STD_LOGIC_VECTOR (37 DOWNTO 0);
signal monitor_ready_sync : STD_LOGIC;
signal unxcomplemented_resetxx0 : STD_LOGIC;
signal unxcomplemented_resetxx1 : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of DRSize : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103,R101""";
attribute ALTERA_ATTRIBUTE of sr : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103,R101""";
begin
process (tck)
begin
if tck'event and tck = '1' then
if std_logic'(vs_cdr) = '1' then
case ir_in is
when std_logic_vector'("00") =>
internal_sr(35) <= debugack_sync;
internal_sr(34) <= monitor_error;
internal_sr(33) <= resetlatch;
internal_sr(32 DOWNTO 1) <= MonDReg;
internal_sr(0) <= monitor_ready_sync;
-- when std_logic_vector'("00")
when std_logic_vector'("01") =>
internal_sr(35 DOWNTO 0) <= tracemem_trcdata;
internal_sr(37) <= tracemem_tw;
internal_sr(36) <= tracemem_on;
-- when std_logic_vector'("01")
when std_logic_vector'("10") =>
internal_sr(37) <= trigger_state_1;
internal_sr(36) <= dbrk_hit3_latch;
internal_sr(35) <= dbrk_hit2_latch;
internal_sr(34) <= dbrk_hit1_latch;
internal_sr(33) <= dbrk_hit0_latch;
internal_sr(32 DOWNTO 1) <= break_readreg;
internal_sr(0) <= trigbrktype;
-- when std_logic_vector'("10")
when std_logic_vector'("11") =>
internal_sr(15 DOWNTO 12) <= std_logic_vector'("000") & (A_TOSTDLOGICVECTOR(std_logic'('0')));
internal_sr(11 DOWNTO 2) <= std_logic_vector'("000") & (trc_im_addr);
internal_sr(1) <= trc_wrap;
internal_sr(0) <= trc_on;
-- when std_logic_vector'("11")
when others =>
-- when others
end case; -- ir_in
end if;
if std_logic'(vs_sdr) = '1' then
case DRsize is
when std_logic_vector'("000") =>
internal_sr <= Std_Logic_Vector'(A_ToStdLogicVector(tdi) & internal_sr(37 DOWNTO 2) & A_ToStdLogicVector(tdi));
-- when std_logic_vector'("000")
when std_logic_vector'("001") =>
internal_sr <= Std_Logic_Vector'(A_ToStdLogicVector(tdi) & internal_sr(37 DOWNTO 9) & A_ToStdLogicVector(tdi) & internal_sr(7 DOWNTO 1));
-- when std_logic_vector'("001")
when std_logic_vector'("010") =>
internal_sr <= Std_Logic_Vector'(A_ToStdLogicVector(tdi) & internal_sr(37 DOWNTO 17) & A_ToStdLogicVector(tdi) & internal_sr(15 DOWNTO 1));
-- when std_logic_vector'("010")
when std_logic_vector'("011") =>
internal_sr <= Std_Logic_Vector'(A_ToStdLogicVector(tdi) & internal_sr(37 DOWNTO 33) & A_ToStdLogicVector(tdi) & internal_sr(31 DOWNTO 1));
-- when std_logic_vector'("011")
when std_logic_vector'("100") =>
internal_sr <= Std_Logic_Vector'(A_ToStdLogicVector(tdi) & A_ToStdLogicVector(internal_sr(37)) & A_ToStdLogicVector(tdi) & internal_sr(35 DOWNTO 1));
-- when std_logic_vector'("100")
when std_logic_vector'("101") =>
internal_sr <= Std_Logic_Vector'(A_ToStdLogicVector(tdi) & internal_sr(37 DOWNTO 1));
-- when std_logic_vector'("101")
when others =>
internal_sr <= Std_Logic_Vector'(A_ToStdLogicVector(tdi) & internal_sr(37 DOWNTO 2) & A_ToStdLogicVector(tdi));
-- when others
end case; -- DRsize
end if;
if std_logic'(vs_uir) = '1' then
case ir_in is
when std_logic_vector'("00") =>
DRsize <= std_logic_vector'("100");
-- when std_logic_vector'("00")
when std_logic_vector'("01") =>
DRsize <= std_logic_vector'("101");
-- when std_logic_vector'("01")
when std_logic_vector'("10") =>
DRsize <= std_logic_vector'("101");
-- when std_logic_vector'("10")
when std_logic_vector'("11") =>
DRsize <= std_logic_vector'("010");
-- when std_logic_vector'("11")
when others =>
-- when others
end case; -- ir_in
end if;
end if;
end process;
tdo <= internal_sr(0);
st_ready_test_idle <= jtag_state_rti;
unxcomplemented_resetxx0 <= internal_jrst_n1;
the_altera_std_synchronizer : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => tck,
din => debugack,
dout => debugack_sync,
reset_n => unxcomplemented_resetxx0
);
unxcomplemented_resetxx1 <= internal_jrst_n1;
the_altera_std_synchronizer1 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => tck,
din => monitor_ready,
dout => monitor_ready_sync,
reset_n => unxcomplemented_resetxx1
);
process (tck, internal_jrst_n1)
begin
if internal_jrst_n1 = '0' then
ir_out <= std_logic_vector'("00");
elsif tck'event and tck = '1' then
ir_out <= Std_Logic_Vector'(A_ToStdLogicVector(debugack_sync) & A_ToStdLogicVector(monitor_ready_sync));
end if;
end process;
--vhdl renameroo for output signals
jrst_n <= internal_jrst_n1;
--vhdl renameroo for output signals
sr <= internal_sr;
--synthesis translate_off
internal_jrst_n1 <= reset_n;
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- internal_jrst_n1 <= std_logic'('1');
--synthesis read_comments_as_HDL off
end europa;
| gpl-2.0 | 2568ffdfbc10d2210f7f0e595478fb0e | 0.563103 | 4.044883 | false | false | false | false |
DreamIP/GPStudio | support/process/laplacian/hdl/laplacian_process.vhd | 1 | 6,315 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity laplacian_process is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer;
WEIGHT_SIZE : integer := 8
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_width : in std_logic_vector(15 downto 0);
w00_reg_m00 : in std_logic_vector(7 downto 0);
w01_reg_m01 : in std_logic_vector(7 downto 0);
w02_reg_m02 : in std_logic_vector(7 downto 0);
w10_reg_m10 : in std_logic_vector(7 downto 0);
w11_reg_m11 : in std_logic_vector(7 downto 0);
w12_reg_m12 : in std_logic_vector(7 downto 0);
w20_reg_m20 : in std_logic_vector(7 downto 0);
w21_reg_m21 : in std_logic_vector(7 downto 0);
w22_reg_m22 : in std_logic_vector(7 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end laplacian_process;
architecture rtl of laplacian_process is
component matrix_extractor
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer;
OUTVALUE_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
------------------------ matrix out ---------------------
p00, p01, p02 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p10, p11, p12 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p20, p21, p22 : out std_logic_vector((PIX_WIDTH-1) downto 0);
matrix_dv : out std_logic;
---------------------- computed value -------------------
value_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
value_dv : in std_logic;
------------------------- params ------------------------
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0)
);
end component;
-- buffered kernell weights
signal w00, w01, w02 : signed((IN_SIZE-1) downto 0);
signal w10, w11, w12 : signed((IN_SIZE-1) downto 0);
signal w20, w21, w22 : signed((IN_SIZE-1) downto 0);
-- neighbors extraction
signal p00, p01, p02 : std_logic_vector((IN_SIZE-1) downto 0);
signal p10, p11, p12 : std_logic_vector((IN_SIZE-1) downto 0);
signal p20, p21, p22 : std_logic_vector((IN_SIZE-1) downto 0);
signal matrix_dv : std_logic;
-- products calculation
signal prod00, prod01, prod02 : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
signal prod10, prod11, prod12 : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
signal prod20, prod21, prod22 : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
signal prod_dv : std_logic;
signal value_data : std_logic_vector((IN_SIZE-1) downto 0);
signal value_dv : std_logic;
signal out_fv_s : std_logic;
signal enable_s : std_logic;
begin
matrix_extractor_inst : matrix_extractor
generic map (
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
PIX_WIDTH => IN_SIZE,
OUTVALUE_WIDTH => IN_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
p00 => p00, p01 => p01, p02 => p02,
p10 => p10, p11 => p11, p12 => p12,
p20 => p20, p21 => p21, p22 => p22,
matrix_dv => matrix_dv,
value_data => value_data,
value_dv => value_dv,
out_data => out_data,
out_fv => out_fv_s,
out_dv => out_dv,
enable_i => status_reg_enable_bit,
widthimg_i => widthimg_reg_width
);
process (clk_proc, reset_n, matrix_dv)
variable sum : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
begin
if(reset_n='0') then
enable_s <= '0';
prod_dv <= '0';
value_dv <= '0';
elsif(rising_edge(clk_proc)) then
if(in_fv = '0') then
w00 <= signed(w00_reg_m00);
w01 <= signed(w01_reg_m01);
w02 <= signed(w02_reg_m02);
w10 <= signed(w10_reg_m10);
w11 <= signed(w11_reg_m11);
w12 <= signed(w12_reg_m12);
w20 <= signed(w20_reg_m20);
w21 <= signed(w21_reg_m21);
w22 <= signed(w22_reg_m22);
enable_s <= status_reg_enable_bit;
prod_dv <= '0';
value_dv <= '0';
end if;
-- product calculation pipeline stage
prod_dv <= '0';
if(matrix_dv = '1' and enable_s = '1') then
prod00 <= w00 * signed('0' & p00);
prod01 <= w01 * signed('0' & p01);
prod02 <= w02 * signed('0' & p02);
prod10 <= w10 * signed('0' & p10);
prod11 <= w11 * signed('0' & p11);
prod12 <= w12 * signed('0' & p12);
prod20 <= w20 * signed('0' & p20);
prod21 <= w21 * signed('0' & p21);
prod22 <= w22 * signed('0' & p22);
prod_dv <= '1';
end if;
value_dv <= '0';
if(prod_dv='1' and enable_s = '1') then
sum := prod00 + prod01 + prod02 +
prod10 + prod11 + prod12 +
prod20 + prod21 + prod22;
if (sum(sum'left) = '1') then
sum := (others => '0');
end if;
value_data <= std_logic_vector(unsigned(sum))(OUT_SIZE -1 downto 0);
value_dv <= '1';
end if;
end if;
end process;
out_fv <= enable_s and out_fv_s;
end rtl;
| gpl-3.0 | 8a02e890135f28c5f80c45455c67f180 | 0.498654 | 3.121602 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_CPU_jtag_debug_module_tck.vhd | 1 | 9,586 | --Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_jtag_debug_module_tck is
port (
-- inputs:
signal MonDReg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal break_readreg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dbrk_hit0_latch : IN STD_LOGIC;
signal dbrk_hit1_latch : IN STD_LOGIC;
signal dbrk_hit2_latch : IN STD_LOGIC;
signal dbrk_hit3_latch : IN STD_LOGIC;
signal debugack : IN STD_LOGIC;
signal ir_in : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal jtag_state_rti : IN STD_LOGIC;
signal monitor_error : IN STD_LOGIC;
signal monitor_ready : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal resetlatch : IN STD_LOGIC;
signal tck : IN STD_LOGIC;
signal tdi : IN STD_LOGIC;
signal tracemem_on : IN STD_LOGIC;
signal tracemem_trcdata : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tracemem_tw : IN STD_LOGIC;
signal trc_im_addr : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal trc_on : IN STD_LOGIC;
signal trc_wrap : IN STD_LOGIC;
signal trigbrktype : IN STD_LOGIC;
signal trigger_state_1 : IN STD_LOGIC;
signal vs_cdr : IN STD_LOGIC;
signal vs_sdr : IN STD_LOGIC;
signal vs_uir : IN STD_LOGIC;
-- outputs:
signal ir_out : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal jrst_n : OUT STD_LOGIC;
signal sr : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
signal st_ready_test_idle : OUT STD_LOGIC;
signal tdo : OUT STD_LOGIC
);
end entity Video_System_CPU_jtag_debug_module_tck;
architecture europa of Video_System_CPU_jtag_debug_module_tck is
component altera_std_synchronizer is
GENERIC (
depth : NATURAL
);
PORT (
signal dout : OUT STD_LOGIC;
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal din : IN STD_LOGIC
);
end component altera_std_synchronizer;
signal DRsize : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal debugack_sync : STD_LOGIC;
signal internal_jrst_n1 : STD_LOGIC;
signal internal_sr : STD_LOGIC_VECTOR (37 DOWNTO 0);
signal monitor_ready_sync : STD_LOGIC;
signal unxcomplemented_resetxx0 : STD_LOGIC;
signal unxcomplemented_resetxx1 : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of DRSize : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103,R101""";
attribute ALTERA_ATTRIBUTE of sr : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103,R101""";
begin
process (tck)
begin
if tck'event and tck = '1' then
if std_logic'(vs_cdr) = '1' then
case ir_in is
when std_logic_vector'("00") =>
internal_sr(35) <= debugack_sync;
internal_sr(34) <= monitor_error;
internal_sr(33) <= resetlatch;
internal_sr(32 DOWNTO 1) <= MonDReg;
internal_sr(0) <= monitor_ready_sync;
-- when std_logic_vector'("00")
when std_logic_vector'("01") =>
internal_sr(35 DOWNTO 0) <= tracemem_trcdata;
internal_sr(37) <= tracemem_tw;
internal_sr(36) <= tracemem_on;
-- when std_logic_vector'("01")
when std_logic_vector'("10") =>
internal_sr(37) <= trigger_state_1;
internal_sr(36) <= dbrk_hit3_latch;
internal_sr(35) <= dbrk_hit2_latch;
internal_sr(34) <= dbrk_hit1_latch;
internal_sr(33) <= dbrk_hit0_latch;
internal_sr(32 DOWNTO 1) <= break_readreg;
internal_sr(0) <= trigbrktype;
-- when std_logic_vector'("10")
when std_logic_vector'("11") =>
internal_sr(15 DOWNTO 12) <= std_logic_vector'("000") & (A_TOSTDLOGICVECTOR(std_logic'('0')));
internal_sr(11 DOWNTO 2) <= std_logic_vector'("000") & (trc_im_addr);
internal_sr(1) <= trc_wrap;
internal_sr(0) <= trc_on;
-- when std_logic_vector'("11")
when others =>
-- when others
end case; -- ir_in
end if;
if std_logic'(vs_sdr) = '1' then
case DRsize is
when std_logic_vector'("000") =>
internal_sr <= Std_Logic_Vector'(A_ToStdLogicVector(tdi) & internal_sr(37 DOWNTO 2) & A_ToStdLogicVector(tdi));
-- when std_logic_vector'("000")
when std_logic_vector'("001") =>
internal_sr <= Std_Logic_Vector'(A_ToStdLogicVector(tdi) & internal_sr(37 DOWNTO 9) & A_ToStdLogicVector(tdi) & internal_sr(7 DOWNTO 1));
-- when std_logic_vector'("001")
when std_logic_vector'("010") =>
internal_sr <= Std_Logic_Vector'(A_ToStdLogicVector(tdi) & internal_sr(37 DOWNTO 17) & A_ToStdLogicVector(tdi) & internal_sr(15 DOWNTO 1));
-- when std_logic_vector'("010")
when std_logic_vector'("011") =>
internal_sr <= Std_Logic_Vector'(A_ToStdLogicVector(tdi) & internal_sr(37 DOWNTO 33) & A_ToStdLogicVector(tdi) & internal_sr(31 DOWNTO 1));
-- when std_logic_vector'("011")
when std_logic_vector'("100") =>
internal_sr <= Std_Logic_Vector'(A_ToStdLogicVector(tdi) & A_ToStdLogicVector(internal_sr(37)) & A_ToStdLogicVector(tdi) & internal_sr(35 DOWNTO 1));
-- when std_logic_vector'("100")
when std_logic_vector'("101") =>
internal_sr <= Std_Logic_Vector'(A_ToStdLogicVector(tdi) & internal_sr(37 DOWNTO 1));
-- when std_logic_vector'("101")
when others =>
internal_sr <= Std_Logic_Vector'(A_ToStdLogicVector(tdi) & internal_sr(37 DOWNTO 2) & A_ToStdLogicVector(tdi));
-- when others
end case; -- DRsize
end if;
if std_logic'(vs_uir) = '1' then
case ir_in is
when std_logic_vector'("00") =>
DRsize <= std_logic_vector'("100");
-- when std_logic_vector'("00")
when std_logic_vector'("01") =>
DRsize <= std_logic_vector'("101");
-- when std_logic_vector'("01")
when std_logic_vector'("10") =>
DRsize <= std_logic_vector'("101");
-- when std_logic_vector'("10")
when std_logic_vector'("11") =>
DRsize <= std_logic_vector'("010");
-- when std_logic_vector'("11")
when others =>
-- when others
end case; -- ir_in
end if;
end if;
end process;
tdo <= internal_sr(0);
st_ready_test_idle <= jtag_state_rti;
unxcomplemented_resetxx0 <= internal_jrst_n1;
the_altera_std_synchronizer : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => tck,
din => debugack,
dout => debugack_sync,
reset_n => unxcomplemented_resetxx0
);
unxcomplemented_resetxx1 <= internal_jrst_n1;
the_altera_std_synchronizer1 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => tck,
din => monitor_ready,
dout => monitor_ready_sync,
reset_n => unxcomplemented_resetxx1
);
process (tck, internal_jrst_n1)
begin
if internal_jrst_n1 = '0' then
ir_out <= std_logic_vector'("00");
elsif tck'event and tck = '1' then
ir_out <= Std_Logic_Vector'(A_ToStdLogicVector(debugack_sync) & A_ToStdLogicVector(monitor_ready_sync));
end if;
end process;
--vhdl renameroo for output signals
jrst_n <= internal_jrst_n1;
--vhdl renameroo for output signals
sr <= internal_sr;
--synthesis translate_off
internal_jrst_n1 <= reset_n;
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- internal_jrst_n1 <= std_logic'('1');
--synthesis read_comments_as_HDL off
end europa;
| gpl-2.0 | 903002c116f51af4aa55e0950b8856ca | 0.561444 | 4.056708 | false | false | false | false |
Reiuiji/ECE368-Lab | Lab 3/Keyboard/misc/keycode_to_ascii.vhd | 1 | 6,714 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Keycode to Ascii
-- Project Name: Keyboard Controller
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Keycode to ascii
---------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity KEYCODE_TO_ASCII is
port(
RST : in STD_LOGIC;
KEYCODE : in STD_LOGIC_VECTOR(7 downto 0);
VALID_SIGNAL : in STD_LOGIC;
-- Output
COMPLETE: out STD_LOGIC; -- Hit Key sucessfully
WRITE_ENABLE : out STD_LOGIC; -- Can that character write to screen?
ASCII : out STD_LOGIC_VECTOR(7 downto 0)
);
end KEYCODE_TO_ASCII;
architecture dataflow of KEYCODE_TO_ASCII is
type StateType is (init, idle, READ_BREAKCODE, READ_EXTENDED, READ_KEYCODE);
signal STATE : StateType := init;
signal ASCII_LOWER : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ASCII_UPPER : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
shared variable Shift_Key : boolean := false;
shared variable Extended : boolean := false;
begin
with KEYCODE select
ASCII_LOWER <=
-- Alphabet
x"61" when x"1C", -- a
x"62" when x"32", -- b
x"63" when x"21", -- c
x"64" when x"23", -- d
x"65" when x"24", -- e
x"66" when x"2B", -- f
x"67" when x"34", -- g
x"68" when x"33", -- h
x"69" when x"43", -- i
x"6A" when x"3B", -- j
x"6B" when x"42", -- k
x"6C" when x"4B", -- l
x"6D" when x"3A", -- m
x"6E" when x"31", -- n
x"6F" when x"44", -- o
x"70" when x"4D", -- p
x"71" when x"15", -- q
x"72" when x"2D", -- r
x"73" when x"1B", -- s
x"74" when x"2C", -- t
x"75" when x"3C", -- u
x"76" when x"2A", -- v
x"77" when x"1D", -- w
x"78" when x"22", -- x
x"79" when x"35", -- y
x"7A" when x"1A", -- z
--Top Row
x"60" when x"0E", -- `
x"31" when x"16", -- 1
x"32" when x"1E", -- 2
x"33" when x"26", -- 3
x"34" when x"25", -- 4
x"35" when x"2E", -- 5
x"36" when x"36", -- 6
x"37" when x"3D", -- 7
x"38" when x"3E", -- 8
x"39" when x"46", -- 9
x"30" when x"45", -- 0
x"2D" when x"4E", -- -
x"3D" when x"55", -- =
--Enter Corner
x"5B" when x"54", -- [
x"5D" when x"5B", -- ]
x"5C" when x"5D", -- \
x"3B" when x"4C", -- ;
x"27" when x"52", -- '
x"2C" when x"41", -- ,
x"2E" when x"49", -- .
x"2F" when x"4A", -- /
--Function Keys -- Based on the IBM PC Codes
x"1B" when x"76", -- Esc (Escape)
x"3B" when x"05", -- F1
x"3C" when x"06", -- F2
x"3D" when x"04", -- F3
x"3E" when x"0C", -- F4
x"3F" when x"03", -- F5
x"40" when x"0B", -- F6
x"41" when x"83", -- F7
x"42" when x"0A", -- F8
x"43" when x"01", -- F9
x"44" when x"09", -- F10
x"85" when x"78", -- F11
x"86" when x"07", -- F12
x"09" when x"0D", -- Tab (Horizontal Tab)
x"0D" when x"5A", -- Enter (Carriage Return)
--need no value *(special characters)
x"00" when x"58", -- Caps Lock
x"00" when x"14", -- Ctrl
x"00" when x"11", -- Alt
x"00" when x"66", -- Back Space
--Direction Keys
x"48" when x"75", -- Up
x"50" when x"72", -- Down
x"4B" when x"6B", -- Left
x"4D" when x"74", -- Right
--Unknown input
x"00" when OTHERS; -- Null
with KEYCODE select
ASCII_UPPER <=
-- Alphabet
x"41" when x"1C", -- A
x"42" when x"32", -- B
x"43" when x"21", -- C
x"44" when x"23", -- D
x"45" when x"24", -- E
x"46" when x"2B", -- F
x"47" when x"34", -- G
x"48" when x"33", -- H
x"49" when x"43", -- I
x"4A" when x"3B", -- J
x"4B" when x"42", -- K
x"4C" when x"4B", -- L
x"4D" when x"3A", -- M
x"4E" when x"31", -- N
x"4F" when x"44", -- O
x"50" when x"4D", -- P
x"51" when x"15", -- Q
x"52" when x"2D", -- R
x"53" when x"1B", -- S
x"54" when x"2C", -- T
x"55" when x"3C", -- U
x"56" when x"2A", -- V
x"57" when x"1D", -- W
x"58" when x"22", -- X
x"59" when x"35", -- Y
x"5A" when x"1A", -- Z
-- Special Upper case Characters (top left to bottom right)
-- Top Row
x"7E" when x"0E", -- ~
x"21" when x"16", -- !
x"40" when x"1E", -- @
x"23" when x"26", -- #
x"24" when x"25", -- $
x"25" when x"2E", -- %
x"5E" when x"36", -- ^
x"26" when x"3D", -- &
x"2A" when x"3E", -- *
x"28" when x"46", -- (
x"29" when x"45", -- )
x"5F" when x"4E", -- _
x"2B" when x"55", -- +
-- Enter Corner
x"7B" when x"54", -- {
x"7D" when x"5B", -- }
x"7C" when x"5D", -- |
x"3A" when x"4C", -- :
x"22" when x"52", -- "
x"3C" when x"41", -- <
x"3E" when x"49", -- >
x"3F" when x"4A", -- ?
-- Unknown Key
x"00" when OTHERS; -- Null
PROCESS (KEYCODE,VALID_SIGNAL, RST)
BEGIN
if (RST = '1') then
STATE <= init;
elsif (VALID_SIGNAL= '0' AND VALID_SIGNAL'EVENT ) then
case STATE is
when init =>
ascii <= (OTHERS => '0');
COMPLETE <= '0';
WRITE_ENABLE <= '0';
state <= idle;
when idle =>
Extended := false;
if keycode=x"E0" then
state <= READ_EXTENDED;
-- A Key was pressed
elsif keycode=x"F0" then
state <= READ_KEYCODE;
else
-- No break code yet
state <= idle;
end if;
-- Shift Key was press (on)
if (keycode=x"12" or keycode=x"54") then
Shift_Key := true;
end if;
when READ_EXTENDED =>
Extended := true;
if keycode=x"F0" then
state <= READ_BREAKCODE;
else
state <= idle;
end if;
when READ_BREAKCODE =>
if keycode=x"F0" then
state <= READ_KEYCODE;
else
state <= idle;
end if;
when READ_KEYCODE =>
-- Shift Key was released (off)
if (keycode=x"12" or keycode=x"54") then
Shift_Key := false;
else
if (Shift_Key = true) then
ascii <= ASCII_UPPER;
else
ascii <= ASCII_LOWER;
end if;
end if;
--KEYCODE_OUTPUT <= KEYCODE;
if (keycode=x"76" or keycode=x"05" or keycode=x"06" or keycode=x"04" or keycode=x"0C" or keycode=x"03"
or keycode=x"03" or keycode=x"0B" or keycode=x"83" or keycode=x"0A" or keycode=x"01"
or keycode=x"09" or keycode=x"78" or keycode=x"07" or keycode=x"0D" or keycode=x"5A"
or keycode=x"75" or keycode=x"72" or keycode=x"6B" or keycode=x"74" ) then
WRITE_ENABLE <= '0';
else
WRITE_ENABLE <= '1';
end if;
COMPLETE <= '1';
state <= idle;
when OTHERS =>
end case;
end if;
end process;
end architecture dataflow;
| mit | 7b516675c3f958233286861dacef35ca | 0.513703 | 2.357444 | false | false | false | false |
hoglet67/ElectronFpga | src/altera/pll2.vhd | 1 | 15,462 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll2.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll2 IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll2;
ARCHITECTURE SYN OF pll2 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
gate_lock_signal : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
invalid_lock_multiplier : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
valid_lock_multiplier : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
locked <= sub_wire0;
sub_wire2 <= sub_wire1(0);
c0 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 50000000,
clk0_duty_cycle => 50,
clk0_multiply_by => 33333333,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_hint => "CBX_MODULE_PREFIX=pll2",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
areset => areset,
inclk => sub_wire4,
locked => sub_wire0,
clk => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "33.333332"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "33.33333300"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll32.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50000000"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "33333333"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-3.0 | 8759a2f35cacef1a8f981199889054bf | 0.699521 | 3.354741 | false | false | false | false |
DreamIP/GPStudio | support/process/harris/hdl/harris_slave.vhd | 1 | 1,354 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity harris_slave is
port (
clk_proc : in std_logic;
reset_n : in std_logic;
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0);
enable_o : out std_logic;
widthimg_o : out std_logic_vector(15 downto 0)
);
end harris_slave;
architecture rtl of harris_slave is
constant ENABLE_REG_ADDR : natural := 0;
constant WIDTHIMG_REG_ADDR : natural := 1;
signal enable_reg : std_logic;
signal widthimg_reg : std_logic_vector(15 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
enable_reg <= '0';
widthimg_reg <= std_logic_vector(to_unsigned(320, 16));
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(ENABLE_REG_ADDR, 4)) => enable_reg <= datawr_i(0);
when std_logic_vector(to_unsigned(WIDTHIMG_REG_ADDR, 4))=> widthimg_reg <= datawr_i(15 downto 0);
when others=>
end case;
end if;
end if;
end process;
enable_o <= enable_reg;
widthimg_o <= widthimg_reg;
end rtl;
| gpl-3.0 | af9e2fb1b3fd4305ec8ecd198c77d70e | 0.599705 | 2.708 | false | false | false | false |
DreamIP/GPStudio | support/process/prewitt/hdl/prewitt_slave.vhd | 1 | 3,050 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity prewitt_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end prewitt_slave;
architecture rtl of prewitt_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant WIDTHIMG_REG_REG_ADDR : natural := 1;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal widthimg_reg_width_reg : std_logic_vector (15 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
widthimg_reg_width_reg <= "0000000000000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
status_reg_enable_bit_reg <= datawr_i(0);
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
widthimg_reg_width_reg <= datawr_i(15) & datawr_i(14) & datawr_i(13) & datawr_i(12) & datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000000000000000000" & status_reg_enable_bit_reg;
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000" & widthimg_reg_width_reg(15) & widthimg_reg_width_reg(14) & widthimg_reg_width_reg(13) & widthimg_reg_width_reg(12) & widthimg_reg_width_reg(11) & widthimg_reg_width_reg(10) & widthimg_reg_width_reg(9) & widthimg_reg_width_reg(8) & widthimg_reg_width_reg(7) & widthimg_reg_width_reg(6) & widthimg_reg_width_reg(5) & widthimg_reg_width_reg(4) & widthimg_reg_width_reg(3) & widthimg_reg_width_reg(2) & widthimg_reg_width_reg(1) & widthimg_reg_width_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
widthimg_reg_width <= widthimg_reg_width_reg;
end rtl;
| gpl-3.0 | 512ec07202b0002d67083c9ee33a9eb3 | 0.593115 | 2.874647 | false | false | false | false |
hoglet67/ElectronFpga | src/common/mode7/saa5050_rom_dual_port_uninitialized.vhd | 1 | 1,547 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity saa5050_rom_dual_port_uninitialized is
generic (
ADDR_WIDTH : integer := 12;
DATA_WIDTH : integer := 8
);
port(
clock : in std_logic;
wea : in std_logic;
addressA : in std_logic_vector(ADDR_WIDTH-1 downto 0);
dina : in std_logic_vector(DATA_WIDTH-1 downto 0);
QA : out std_logic_vector(DATA_WIDTH-1 downto 0);
addressB : in std_logic_vector(ADDR_WIDTH-1 downto 0);
QB : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end saa5050_rom_dual_port_uninitialized;
architecture RTL of saa5050_rom_dual_port_uninitialized is
constant MEM_DEPTH : integer := 2**ADDR_WIDTH;
type mem_type is array (0 to MEM_DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
shared variable mem : mem_type;
begin
process(clock)
begin
if (rising_edge(clock)) then
if wea = '1' then
mem(to_integer(unsigned(addressA))) := dina;
end if;
QA <= mem(to_integer(unsigned(addressA)));
--QA <= addressA(7 downto 0); --DEBUG generate something until memory init works
end if;
end process;
process(clock)
begin
if (rising_edge(clock)) then
QB <= mem(to_integer(unsigned(addressB)));
--QB <= addressB(7 downto 0); --DEBUG generate something until memory init works
end if;
end process;
end RTL;
| gpl-3.0 | 0e3576c141f0b1b02c2c82e161860171 | 0.594699 | 3.606061 | false | false | false | false |
DreamIP/GPStudio | support/process/AveragingFilter/hdl/AveragingFilter_process.vhd | 1 | 4,773 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity AveragingFilter_process is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_width : in std_logic_vector(15 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end AveragingFilter_process;
architecture rtl of AveragingFilter_process is
component matrix_extractor
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer;
OUTVALUE_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
------------------------ matrix out ---------------------
p00, p01, p02 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p10, p11, p12 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p20, p21, p22 : out std_logic_vector((PIX_WIDTH-1) downto 0);
matrix_dv : out std_logic;
---------------------- computed value -------------------
value_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
value_dv : in std_logic;
------------------------- params ------------------------
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0)
);
end component;
-- neighbors extraction
signal p00, p01, p02 : std_logic_vector((IN_SIZE-1) downto 0);
signal p10, p11, p12 : std_logic_vector((IN_SIZE-1) downto 0);
signal p20, p21, p22 : std_logic_vector((IN_SIZE-1) downto 0);
signal matrix_dv : std_logic;
-- products calculation
signal prod_dv : std_logic;
signal value_data : std_logic_vector((IN_SIZE-1) downto 0);
signal value_dv : std_logic;
signal out_fv_s : std_logic;
signal enable_s : std_logic;
begin
matrix_extractor_inst : matrix_extractor
generic map (
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
PIX_WIDTH => IN_SIZE,
OUTVALUE_WIDTH => IN_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
p00 => p00, p01 => p01, p02 => p02,
p10 => p10, p11 => p11, p12 => p12,
p20 => p20, p21 => p21, p22 => p22,
matrix_dv => matrix_dv,
value_data => value_data,
value_dv => value_dv,
out_data => out_data,
out_fv => out_fv_s,
out_dv => out_dv,
enable_i => status_reg_enable_bit,
widthimg_i => widthimg_reg_width
);
process (clk_proc, reset_n, matrix_dv)
variable sum : unsigned(12 downto 0);
begin
if(reset_n='0') then
enable_s <= '0';
prod_dv <= '0';
value_dv <= '0';
elsif(rising_edge(clk_proc)) then
if(in_fv = '0') then
enable_s <= status_reg_enable_bit;
prod_dv <= '0';
value_dv <= '0';
end if;
-- product calculation pipeline stage
prod_dv <= '0';
if(matrix_dv = '1' and enable_s = '1') then
sum := unsigned('0' & '0' & '0' & '0' & '0' & p22) + unsigned('0' & '0' & '0' & '0' & '0' & p21) + unsigned('0' & '0' & '0' & '0' & '0' & p20)
+ unsigned('0' & '0' & '0' & '0' & '0' & p12) + unsigned('0' & '0' & '0' & '0' & '0' & p11) + unsigned('0' & '0' & '0' & '0' & '0' & p10)
+ unsigned('0' & '0' & '0' & '0' & '0' & p02) + unsigned('0' & '0' & '0' & '0' & '0' & p01) + unsigned('0' & '0' & '0' & '0' & '0' & p00);
prod_dv <= '1';
end if;
value_dv <= '0';
if(prod_dv='1' and enable_s = '1') then
if (unsigned(sum) >= to_unsigned(2048,13)) then
value_data <= (others => '1');
value_dv <= '1';
else
value_data <= std_logic_vector(shift_right(sum,3))(OUT_SIZE -1 downto 0);
value_dv <= '1';
end if;
end if;
end if;
end process;
out_fv <= enable_s and out_fv_s;
end rtl;
| gpl-3.0 | a40a2473467b759d18719963d6550cbc | 0.491934 | 2.846154 | false | false | false | false |
DreamIP/GPStudio | support/component/gp_com/utils/ComFlow_pkg.vhd | 1 | 9,975 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-- package declaration -- TODO: deplacer dans un fichier externe
package ComFlow_pkg is
function clog2 ( x : integer) return integer;
-- Number of flow in design
constant NBFLOW : integer := 2;
-- struct pour stocker les ID flow : used for Return Status in USB Driver
type IDFLOW_t is array (0 to NBFLOW-1) of integer range 0 to 255;
constant TX_PACKET_SIZE : integer := 256;
--- Define pour simplifier lecture des codes read/write flow
constant SoF:integer := 0;
constant EoF:integer := 1;
constant Data:integer:= 2;
constant SoL:integer := 3;
constant EoL:integer := 4;
-- Struct pour les flags s
type my_array_t is array (0 to 4) of std_logic_vector(7 downto 0);
constant InitFlagCodes : my_array_t := (
X"AA", -- Start of Frame Flag
X"BA", --End of Frame Flag
X"BC", -- Start+end Flow
X"DA", -- Start of Line
X"DB" -- End of Line
);
-- Component Declaration
component com_to_flow
generic (
FIFO_DEPTH : POSITIVE := 1024;
FLOW_ID : INTEGER := 1;
FLAGS_CODES : my_array_t := InitFlagCodes;
FLOW_SIZE : INTEGER := 16;
DATA_HAL_SIZE : INTEGER := 16
);
port(
clk_hal : in std_logic;
clk_proc : in std_logic;
rst_n : in std_logic;
data_wr_i : in std_logic;
data_i : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
pktend_i : in std_logic;
enable_i : in std_logic;
data_o : out std_logic_vector(FLOW_SIZE-1 downto 0);
fv_o : out std_logic;
dv_o : out std_logic;
flow_full_o : out std_logic
);
end component;
component flow_to_com is
generic (
FLOW_SIZE : POSITIVE := 8;
DATA_HAL_SIZE : POSITIVE := 16;
FIFO_DEPTH : POSITIVE := 1024;
FLOW_ID : INTEGER := 1;
PACKET_SIZE : INTEGER := 256;
FLAGS_CODES : my_array_t := InitFlagCodes
);
port(
clk_proc : in std_logic;
clk_hal : in std_logic;
rst_n : in std_logic;
in_data : in std_logic_vector(FLOW_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
rdreq_i : in std_logic;
enable_flow_i : in std_logic;
enable_global_i : in std_logic;
data_o : out std_logic_vector(DATA_HAL_SIZE-1 downto 0);
flow_rdy_o : out std_logic;
f_empty_o : out std_logic;
size_packet_o : out std_logic_vector(15 downto 0)
);
end component;
constant BURSTMODE :std_logic_vector(7 downto 0) := X"BC";
component com_to_master_pi
generic (
FIFO_DEPTH : POSITIVE := 64;
FLOW_ID_SET : INTEGER := 12;
--FLOW_ID_GET : INTEGER := 13
MASTER_ADDR_WIDTH : INTEGER;
DATA_HAL_SIZE : POSITIVE := 16
);
port (
clk_hal : in std_logic; -- clk_usb
clk_proc : in std_logic; -- clk_design
rst_n : in std_logic;
-- USB driver connexion
data_wr_i : in std_logic;
data_i : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
-- rdreq_i : in std_logic;
pktend_i : in std_logic;
fifo_full_o : out std_logic;
-- signaux pour wishbone
param_addr_o : out std_logic_vector(MASTER_ADDR_WIDTH-1 downto 0);
param_data_o : out std_logic_vector(31 downto 0);
param_wr_o : out std_logic;
-- may add RAM arbiter connexion
-- tmp signal to trigger caph update reg
tmp_update_port_o : out std_logic
);
end component;
component flow_to_com_arb4
generic (
DATA_HAL_SIZE : POSITIVE := 16
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- fv 0 signals
rdreq_0_o : out std_logic;
data_0_i : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
flow_rdy_0_i : in std_logic;
f_empty_0_i : in std_logic;
size_packet_0_i : in std_logic_vector(15 downto 0);
-- fv 1signals
rdreq_1_o : out std_logic;
data_1_i : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
flow_rdy_1_i : in std_logic;
f_empty_1_i : in std_logic;
size_packet_1_i : in std_logic_vector(15 downto 0);
-- fv 2 signals
rdreq_2_o : out std_logic;
data_2_i : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
flow_rdy_2_i : in std_logic;
f_empty_2_i : in std_logic;
size_packet_2_i : in std_logic_vector(15 downto 0);
-- fv 3 signals
rdreq_3_o : out std_logic;
data_3_i : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
flow_rdy_3_i : in std_logic;
f_empty_3_i : in std_logic;
size_packet_3_i : in std_logic_vector(15 downto 0);
-- fv usb signals
rdreq_usb_i : in std_logic;
data_usb_o : out std_logic_vector(DATA_HAL_SIZE-1 downto 0);
flow_rdy_usb_o : out std_logic;
f_empty_usb_o : out std_logic;
size_packet_o : out std_logic_vector(15 downto 0)
);
end component;
component gp_com
generic (
IN0_SIZE : INTEGER := 8;
IN1_SIZE : INTEGER := 8;
IN2_SIZE : INTEGER := 8;
IN3_SIZE : INTEGER := 8;
OUT0_SIZE : INTEGER := 8;
OUT1_SIZE : INTEGER := 8;
IN0_NBWORDS : INTEGER := 1280;
IN1_NBWORDS : INTEGER := 1280;
IN2_NBWORDS : INTEGER := 1280;
IN3_NBWORDS : INTEGER := 1280;
OUT0_NBWORDS : INTEGER := 1024;
OUT1_NBWORDS : INTEGER := 1024;
CLK_PROC_FREQ : INTEGER;
CLK_HAL_FREQ : INTEGER;
DATA_HAL_SIZE : INTEGER;
PACKET_HAL_SIZE : INTEGER;
MASTER_ADDR_WIDTH : INTEGER
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------ hal connections ------
clk_hal : in std_logic;
from_hal_data : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
from_hal_wr : in std_logic;
from_hal_full : out std_logic;
from_hal_pktend : in std_logic;
to_hal_data : out std_logic_vector(DATA_HAL_SIZE-1 downto 0);
to_hal_rd : in std_logic;
to_hal_empty : out std_logic;
to_hal_rdy : out std_logic;
to_hal_size_packet : out std_logic_vector(15 downto 0);
-------- slave -------
status_enable : in std_logic;
flow_in0_enable : in std_logic;
flow_in1_enable : in std_logic;
flow_in2_enable : in std_logic;
flow_in3_enable : in std_logic;
------ in0 flow ------
in0_data : in std_logic_vector(IN0_SIZE-1 downto 0);
in0_fv : in std_logic;
in0_dv : in std_logic;
------ in1 flow ------
in1_data : in std_logic_vector(IN1_SIZE-1 downto 0);
in1_fv : in std_logic;
in1_dv : in std_logic;
------ in2 flow ------
in2_data : in std_logic_vector(IN2_SIZE-1 downto 0);
in2_fv : in std_logic;
in2_dv : in std_logic;
------ in3 flow ------
in3_data : in std_logic_vector(IN3_SIZE-1 downto 0);
in3_fv : in std_logic;
in3_dv : in std_logic;
------ out0 flow ------
out0_data : out std_logic_vector(OUT0_SIZE-1 downto 0);
out0_fv : out std_logic;
out0_dv : out std_logic;
------ out1 flow ------
out1_data : out std_logic_vector(OUT1_SIZE-1 downto 0);
out1_fv : out std_logic;
out1_dv : out std_logic;
---- ===== Masters =====
------ bus_master ------
master_addr_o : out std_logic_vector(MASTER_ADDR_WIDTH-1 downto 0);
master_wr_o : out std_logic;
master_rd_o : out std_logic;
master_datawr_o : out std_logic_vector(31 downto 0);
master_datard_i : in std_logic_vector(31 downto 0)
);
end component;
end package ComFlow_pkg;
package body ComFlow_pkg is
function clog2(x : integer) return integer is
begin
return integer(ceil(log2(real(x))));
end;
end ComFlow_pkg;
| gpl-3.0 | 788ac72674fd0def477d0a3f3d4b84ce | 0.448321 | 3.821839 | false | false | false | false |
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